diff --git a/.github/workflows/main.yml b/.github/workflows/main.yml
new file mode 100644
index 0000000..5ae16aa
--- /dev/null
+++ b/.github/workflows/main.yml
@@ -0,0 +1,81 @@
+name: Verilator Test Suite
+
+on:
+  push:
+    branches: [ "**" ]
+
+jobs:
+  sim-split-mode:
+    runs-on: ubuntu-latest
+    container:
+      image: verilator/verilator:4.104
+    strategy:
+      matrix:
+        conf_name: [general, line-ring, multicast, vc_alloc, conv_route, tiny_topos, mesh_3d]
+    env:
+      ROOT: ${{ github.workspace }}/mpsoc
+      PRONOC_WORK: ${{ github.workspace }}/mpsoc_work
+      GOLDEN_REF: ${{ github.workspace }}/mpsoc/Integration_test/synthetic_sim/golden_ref
+      LOG_DIR: ${{ github.workspace }}/mpsoc/Integration_test/synthetic_sim/result_logs
+    steps:
+      - uses: actions/checkout@v4
+      - name: Run NoC simulation split mode - ${{ matrix.conf_name }}
+        run: |
+          set -ex
+          verilator --version
+          echo "Running simulation for config: ${{ matrix.conf_name }}"
+          cd $ROOT/Integration_test/synthetic_sim/src
+          perl ./verify.perl -p 15 -u 80 -l 2 -s 4 -d ${{ matrix.conf_name }}
+          perl ./check.pl -o $GOLDEN_REF/${{ matrix.conf_name }} -n $LOG_DIR/${{ matrix.conf_name }} || {
+            echo "❌ Verification check failed. Please inspect the simulation logs."
+            exit 1
+          }
+      - name: Upload failures artifact - ${{ matrix.conf_name }}
+        if: failure()
+        uses: actions/upload-artifact@v4
+        with:
+          name: simulation-failures-${{ matrix.conf_name }}
+          path: |
+            ${{ env.PRONOC_WORK }}/failures.txt
+      - name: Upload simulation reports - ${{ matrix.conf_name }}
+        uses: actions/upload-artifact@v4
+        with:
+          name: simulation-reports-${{ matrix.conf_name }}-${{ github.run_id }}
+          path: ${{ env.LOG_DIR }}
+          retention-days: 7
+
+  tiny-topos-flat-mode:
+    needs: sim-split-mode
+    runs-on: ubuntu-latest
+    container:
+      image: verilator/verilator:4.104
+    env:
+      ROOT: ${{ github.workspace }}/mpsoc
+      PRONOC_WORK: ${{ github.workspace }}/mpsoc_work
+      GOLDEN_REF: ${{ github.workspace }}/mpsoc/Integration_test/synthetic_sim/golden_ref
+      LOG_DIR: ${{ github.workspace }}/mpsoc/Integration_test/synthetic_sim/result_logs
+    steps:
+      - uses: actions/checkout@v4
+      - name: Run NoC simulation flat_mode - tiny_topos
+        run: |
+          set -ex
+          cd $ROOT/Integration_test/synthetic_sim/src
+          perl ./verify.perl -p 15 -u 80 -l 2 -s 4 -d tiny_topos -f
+          perl ./check.pl -o $GOLDEN_REF/tiny_topos -n $LOG_DIR/tiny_topos || {
+            echo "❌ flat config differs from non-flat."
+            exit 1
+          }
+      - name: Upload failures artifact - flat-tiny-tops
+        if: failure()
+        uses: actions/upload-artifact@v4
+        with:
+          name: simulation-failures-tiny_topos-flat-${{ github.run_id }}
+          path: |
+            ${{ env.PRONOC_WORK }}/failures.txt
+      - name: Upload simulation reports - flat-tiny-tops
+        uses: actions/upload-artifact@v4
+        with:
+          name: simulation-reports-flat-tiny-tops-${{ github.run_id }}
+          path: ${{ env.LOG_DIR }}
+          retention-days: 7
+
diff --git a/.gitignore b/.gitignore
index c77757b..e24c077 100644
--- a/.gitignore
+++ b/.gitignore
@@ -46,11 +46,12 @@ mpsoc/src_c/plot/plot
 
 mpsoc/perl_gui/lib/Paths
 mpsoc/src_c/**/*.o
-mpsoc/remove_cycle/__pycache__
+**/__pycache__/*
 
 mpsoc_work/
 mpsoc/rtl/src_openpiton/nocs
+mpsoc/rtl/src_ambachi/nocs
 
-
-
-
+mpsoc/Integration_test/**/work
+mpsoc/Integration_test/**/result_logs/*
+mpsoc/rtl/src_multi_mesh/build
diff --git a/ProNoC.png b/ProNoC.png
new file mode 100644
index 0000000..61295d5
Binary files /dev/null and b/ProNoC.png differ
diff --git a/mpsoc/Integration_test/Altera/configurations/line4_smart3 b/mpsoc/Integration_test/Altera/configurations/line4_smart3
new file mode 100644
index 0000000..548c123
--- /dev/null
+++ b/mpsoc/Integration_test/Altera/configurations/line4_smart3
@@ -0,0 +1,16 @@
+$model = bless( {
+    'noc_param'=> {
+        "SMART_MAX" => "3",
+        TOPOLOGY=>"\"LINE\"",
+        "T1" => "4",
+        "T2" => "4",
+        "V" => "1",
+        "ESCAP_VC_MASK" => "1'b1",
+        "B" => "4",
+        "LB" => "16",
+        "Fpay" => "64",
+        "SSA_EN" => "0",
+        "SELF_LOOP_EN" => "1",
+        "MCAST_ENDP_LIST" => "'b11",
+    }
+}, 'ProNOC' );
\ No newline at end of file
diff --git a/mpsoc/Integration_test/Altera/configurations/mesh_3x3_v2_ssa b/mpsoc/Integration_test/Altera/configurations/mesh_3x3_v2_ssa
new file mode 100644
index 0000000..fae94ef
--- /dev/null
+++ b/mpsoc/Integration_test/Altera/configurations/mesh_3x3_v2_ssa
@@ -0,0 +1,11 @@
+$model = bless( {
+    'noc_param'=> {
+        "T1" => "3",
+        "T2" => "3",
+        "SELF_LOOP_EN" => "1",
+        "SSA_EN"=> "1",
+        "LB" => 16,
+        "DEBUG_EN" => "0",
+        "MIN_PCK_SIZE"  => "1",
+    }
+}, 'ProNOC' );
diff --git a/mpsoc/Integration_test/Altera/configurations/mesh_4x4_2cycle_mcast_f b/mpsoc/Integration_test/Altera/configurations/mesh_4x4_2cycle_mcast_f
new file mode 100644
index 0000000..a90f35c
--- /dev/null
+++ b/mpsoc/Integration_test/Altera/configurations/mesh_4x4_2cycle_mcast_f
@@ -0,0 +1,8 @@
+$model = bless( {
+    'noc_param'=> {
+        "T1" => "4",
+        "T2" => "4",
+        "CAST_TYPE" => "\"MULTICAST_FULL\"",
+        "Fpay" => "64"
+    }
+}, 'ProNOC' );
\ No newline at end of file
diff --git a/mpsoc/Integration_test/Altera/configurations/mesh_4x4_2cycle_xy_v2 b/mpsoc/Integration_test/Altera/configurations/mesh_4x4_2cycle_xy_v2
new file mode 100644
index 0000000..b7eb7d1
--- /dev/null
+++ b/mpsoc/Integration_test/Altera/configurations/mesh_4x4_2cycle_xy_v2
@@ -0,0 +1,7 @@
+$model = bless( {
+        'noc_param'=> {
+        "T1" => "4",
+        "T2" => "4",
+        "DEBUG_EN" => "0",       
+    }
+}, 'ProNOC' );
diff --git a/mpsoc/Integration_test/Altera/golden_ref/report.txt b/mpsoc/Integration_test/Altera/golden_ref/report.txt
new file mode 100644
index 0000000..a9a9cab
--- /dev/null
+++ b/mpsoc/Integration_test/Altera/golden_ref/report.txt
@@ -0,0 +1,5 @@
+File| ALMs:partiallyorcompletelyused| MemoryALUTs| Warnings| Totalblockmemorybits| M9Kblocks| Dedicatedlogicregisters| CombinationalALUTs| Logicutilization| Maxfrequency
+line4_smart3| 1588,18050(9%)| 0,18050(0%)| 140| 5808,2939904(<1%)| 20,319(6%)| 1430,36100(4%)| 2009,36100(6%)| 2787,36100(8%)| 194.33,194.33MHz
+mesh_3x3_v2_ssa| 10679,18050(59%)| 0,18050(0%)| 408| 16320,2939904(<1%)| 33,319(10%)| 9864,36100(27%)| 13916,36100(39%)| 17659,36100(49%)| 133.87,133.87MHz
+mesh_4x4_2cycle_mcast_f| 13711,18050(76%)| 0,18050(0%)| 729| 33792,2939904(1%)| 128,319(40%)| 8821,36100(24%)| 19404,36100(54%)| 24517,36100(68%)| 145.33,145.33MHz
+mesh_4x4_2cycle_xy_v2| 12562,18050(70%)| 0,18050(0%)| 652| 17408,2939904(<1%)| 64,319(20%)| 9716,36100(27%)| 17106,36100(47%)| 21089,36100(58%)| 153.52,153.52MHz
diff --git a/mpsoc/Integration_test/Altera/report b/mpsoc/Integration_test/Altera/report
deleted file mode 100644
index a09699d..0000000
--- a/mpsoc/Integration_test/Altera/report
+++ /dev/null
@@ -1,47 +0,0 @@
-extract_results(/home/alireza/work/git/hca_git/mpsoc_work/verify/quartus_pronoc,pronoc);
-/home/alireza/work/git/hca_git/mpsoc_work/verify/quartus_pronoc
-***************** results *****************
- , Fr_max
-pronoc_output_files,  125.9  ,  Fmax =  125.9   Mhz
-
-
-
-
--,     Combinational ALUTs           
-pronoc_output_files, 12032 , 36100 ( 33 % )                    ;  
-
-
-
-
--,     Dedicated logic registers     
-pronoc_output_files, 9376 , 36100 ( 26 % )                     ;  
-
-
-
-
--,     Memory ALUTs                  
-pronoc_output_files, 0 , 18050 ( 0 % )                          ;  
-
-
-
-
--, ALMs:  partially or completely used                                               
-pronoc_output_files, 9309 , 18050 ( 52 % )    
-
-
-
-
--, Logic utilization                                                                 
-pronoc_output_files, 14767 , 36100 ( 41 % )   
-
-
-
-
--, M9K blocks                                                                        
-pronoc_output_files, 33 , 319 ( 10 % )            ;  
-
-
-
-
--, Total block memory bits           
-pronoc_output_files, 16320 , 2939904 ( < 1 % )                ;  
diff --git a/mpsoc/Integration_test/Altera/report_old b/mpsoc/Integration_test/Altera/report_old
deleted file mode 100644
index 6011be7..0000000
--- a/mpsoc/Integration_test/Altera/report_old
+++ /dev/null
@@ -1,46 +0,0 @@
-***************** results *****************
- , Fr_max
-pronoc_output_files,  125.5  ,  Fmax =  125.5   Mhz
-
-
-
-
--,     Combinational ALUTs           
-pronoc_output_files, 12019 , 36100 ( 33 % )                    ;  
-
-
-
-
--,     Dedicated logic registers     
-pronoc_output_files, 9370 , 36100 ( 26 % )                     ;  
-
-
-
-
--,     Memory ALUTs                  
-pronoc_output_files, 0 , 18050 ( 0 % )                          ;  
-
-
-
-
--, ALMs:  partially or completely used                                               
-pronoc_output_files, 9253 , 18050 ( 51 % )    
-
-
-
-
--, Logic utilization                                                                 
-pronoc_output_files, 15031 , 36100 ( 42 % )   
-
-
-
-
--, M9K blocks                                                                        
-pronoc_output_files, 33 , 319 ( 10 % )            ;  
-
-
-
-
--, Total block memory bits           
-pronoc_output_files, 16320 , 2939904 ( < 1 % )                ;  
-
diff --git a/mpsoc/Integration_test/Altera/run.sh b/mpsoc/Integration_test/Altera/run.sh
index 15ac250..e8b2a83 100755
--- a/mpsoc/Integration_test/Altera/run.sh
+++ b/mpsoc/Integration_test/Altera/run.sh
@@ -3,127 +3,186 @@
 SCRPT_FULL_PATH=$(realpath ${BASH_SOURCE[0]})
 SCRPT_DIR_PATH=$(dirname $SCRPT_FULL_PATH)
 
-
-
-
+# Source the environment variables
+conf_dir="${SCRPT_DIR_PATH}/configurations"
+log_dir="${SCRPT_DIR_PATH}/result_logs"
+golden_dir="${SCRPT_DIR_PATH}/golden_ref"
 work="${PRONOC_WORK}/verify/quartus_pronoc"
-top="quartus_pronoc"
-
-
-
-
-
-
-
-
+log_work="${PRONOC_WORK}/verify/logs"
+mkdir -p $log_work
+mkdir -p $log_dir
+
+report="report.txt"
+
+
+quartus_get_result () {
+    conf=$1
+    if [[ -z "$conf" ]]; then
+        echo "No configuration provided"
+        exit 1
+    fi
+    if [[ ! -f "${SCRPT_DIR_PATH}/configurations/$conf" ]]; then
+        echo "Configuration file ${SCRPT_DIR_PATH}/configurations/$conf does not exist"
+        exit 1
+    fi
+    if [[ ! -d "${SCRPT_DIR_PATH}/result_logs" ]]; then
+        mkdir -p "${SCRPT_DIR_PATH}/result_logs"
+    fi
+    conf_file="${SCRPT_DIR_PATH}/configurations/$conf"
+    top="quartus_pronoc"
+    log_file="${log_work}/$conf"
+    golden_ref="${SCRPT_DIR_PATH}/golden_ref/$conf"
+    
+
+    perl  ${SCRPT_DIR_PATH}/src/param_gen.pl  $conf_file
+    
+    compile
+    wait;
+    
+    mkdir -p $log_work
+    perl ${SCRPT_DIR_PATH}/src/extract.prl "$PRONOC_WORK/verify/quartus_pronoc" "pronoc" > $log_file
+    #meld "$golden_ref" "$log_file" &
+    rm -f ${SCRPT_DIR_PATH}/src/noc_localparam.v
+}
 
 copy_filelist () {
-	fname=$1
-	local DIR="$(dirname "${fname}")"
-
-
-	echo $DIR
-	pwd
-
-	
-	while read line; do	
-		# reading each line
-		#echo $line
+    fname=$1
+    local DIR="$(dirname "${fname}")"
+    echo $DIR
+    pwd
+    while read line; do
+        # reading each line
+        #echo $line
         cd $DIR
-       
-		if test -f "$DIR/$line"; then
-			echo "copy $DIR/$line "
-			cp "$DIR/$line"   $PITON_ROOT/build/src_verilog/  
-		fi
-		line="$(echo -e "${line}" | sed -e 's/^[[:space:]]*//')"   # remove only the leading white spaces
-		if [[ $line == -F* ]] || [[ $line == -f* ]] ; then 
-			line=${line:2}   # Remove the first three chars (leaving 4..end)
-			line="$(echo -e "${line}" | sed -e 's/^[[:space:]]*//')"   # remove only the leading white spaces
-			echo $line
-	 		echo "got another file list $line"
-			copy_filelist "$DIR/$line"
-		fi
-	done < $fname
+        if test -f "$DIR/$line"; then
+            echo "copy $DIR/$line "
+            cp "$DIR/$line"   $PITON_ROOT/build/src_verilog/
+        fi
+        line="$(echo -e "${line}" | sed -e 's/^[[:space:]]*//')"   # remove only the leading white spaces
+        if [[ $line == -F* ]] || [[ $line == -f* ]] ; then 
+            line=${line:2}   # Remove the first three chars (leaving 4..end)
+            line="$(echo -e "${line}" | sed -e 's/^[[:space:]]*//')"   # remove only the leading white spaces
+            echo $line
+            echo "got another file list $line"
+            copy_filelist "$DIR/$line"
+        fi
+    done < $fname
 }
 
 
-
-
-
-
 make_qsf () {
-	fname=$1
-	oname=$2
-	local DIR="$(dirname "${fname}")"
-
-
-	echo $oname
-	
-	pwd
-
-	
-	while read line; do	
-		# reading each line
-		#echo $line
+    fname=$1
+    oname=$2
+    local DIR="$(dirname "${fname}")"
+    echo $oname
+    pwd
+    while read line; do
+        # reading each line
+        #echo $line
         cd $DIR
-	
-       
-		if test -f "$DIR/$line"; then
-			echo "set_global_assignment -name SYSTEMVERILOG_FILE $DIR/$line">>"$oname"
-			# "$DIR/$line"   $PITON_ROOT/build/src_verilog/  
-		fi
-		line="$(echo -e "${line}" | sed -e 's/^[[:space:]]*//')"   # remove only the leading white spaces
-		if [[ $line == -F* ]] || [[ $line == -f* ]] ; then 
-			line=${line:2}   # Remove the first three chars (leaving 4..end)
-			line="$(echo -e "${line}" | sed -e 's/^[[:space:]]*//')"   # remove only the leading white spaces
-			#echo $line
-	 		echo "got another file list $line"
-			make_qsf "$DIR/$line" "$oname"
-		fi
-
-		if [[ $line == +incdir+* ]] ; then 
-			line=${line:8}   # Remove the first three chars (leaving 4..end)
-			echo "set_global_assignment -name SEARCH_PATH $DIR/$line">>"$oname"
-		fi
-
-	done < $fname
+        if test -f "$DIR/$line"; then
+            echo "set_global_assignment -name SYSTEMVERILOG_FILE $DIR/$line">>"$oname"
+            # "$DIR/$line"   $PITON_ROOT/build/src_verilog/  
+        fi
+        line="$(echo -e "${line}" | sed -e 's/^[[:space:]]*//')"   # remove only the leading white spaces
+        if [[ $line == -F* ]] || [[ $line == -f* ]] ; then 
+            line=${line:2}   # Remove the first three chars (leaving 4..end)
+            line="$(echo -e "${line}" | sed -e 's/^[[:space:]]*//')"   # remove only the leading white spaces
+            #echo $line
+            echo "got another file list $line"
+            make_qsf "$DIR/$line" "$oname"
+        fi
+        if [[ $line == +incdir+* ]] ; then 
+            line=${line:8}   # Remove the first three chars (leaving 4..end)
+            echo "set_global_assignment -name SEARCH_PATH $DIR/$line">>"$oname"
+        fi
+    done < $fname
 }
 
 
 compile () {
-
-	mkdir -p  $work
-	filename=$SCRPT_DIR_PATH/src/file_list.f
-	qsf_name="$work/pronoc.qsf"
-	cp -f $SCRPT_DIR_PATH/src/pronoc.qsf $qsf_name
-
-	echo "set_global_assignment -name TOP_LEVEL_ENTITY $top">>$qsf_name
-	make_qsf $filename "$qsf_name"
-
-
-
-
-	if [[ -z "${Quartus_bin}" ]]; then
-	  #"Some default value because Quartus_bin is undefined"
-	  Quartus_bin="/home/alireza/intelFPGA_lite/18.1/quartus/bin"
-	else
-	  Quartus_bin="${Quartus_bin}"
-	fi
-
-	cd $work
-	$Quartus_bin/quartus_map --64bit pronoc --read_settings_files=on
-	$Quartus_bin/quartus_fit --64bit pronoc --read_settings_files=on 
-	$Quartus_bin/quartus_asm --64bit pronoc --read_settings_files=on
-	$Quartus_bin/quartus_sta --64bit pronoc	
-
+    mkdir -p  $work
+    filename=$SCRPT_DIR_PATH/src/file_list.f
+    qsf_name="$work/pronoc.qsf"
+    cp -f $SCRPT_DIR_PATH/src/pronoc.qsf $qsf_name
+    echo "set_global_assignment -name TOP_LEVEL_ENTITY $top">>$qsf_name
+    make_qsf $filename "$qsf_name"
+    if [[ -z "${Quartus_bin}" ]]; then
+    #"Some default value because Quartus_bin is undefined"
+    Quartus_bin="/home/alireza/intelFPGA_lite/18.1/quartus/bin"
+    else
+    Quartus_bin="${Quartus_bin}"
+    fi
+    cd $work
+    $Quartus_bin/quartus_map --64bit pronoc --read_settings_files=on
+    $Quartus_bin/quartus_fit --64bit pronoc --read_settings_files=on 
+    $Quartus_bin/quartus_asm --64bit pronoc --read_settings_files=on
+    $Quartus_bin/quartus_sta --64bit pronoc
 }
 
+report_all_configurations () {
+    output_file="$log_dir/$report"
+    > "$output_file"  # Empty the file at start
+    # Initialize a set to track unique metric names
+    declare -A all_keys
+
+    # First pass: collect all metric names
+    for file in "$log_work"/*; do
+        while IFS= read -r line; do
+            [[ -z "$line" || "$line" =~ ^# ]] && continue
+            IFS='|' read -ra parts <<< "$line"
+            key="${parts[0]// /}"   # Trim whitespace from key
+            all_keys["$key"]=1
+        done < "$file"
+    done
+
+    # Build the header
+    {
+        printf "File"
+        for key in "${!all_keys[@]}"; do
+            printf "| %s" "$key"
+        done
+        printf "\n"
+    } >> "$output_file"
+
+    # Second pass: extract values for each file
+    for file in "$log_work"/*; do
+        declare -A data
+        data["File"]="${file##*/}"
+
+        while IFS= read -r line; do
+            [[ -z "$line" || "$line" =~ ^# ]] && continue
+            IFS='|' read -ra parts <<< "$line"
+            key="${parts[0]// /}"
+            val="${parts[1]// /}"
+            data["$key"]="$val"
+        done < "$file"
+
+        {
+            printf "%s" "${data["File"]}"
+            for key in "${!all_keys[@]}"; do
+                printf "| %s" "${data[$key]}"
+            done
+            printf "\n"
+        } >> "$output_file"
+
+        unset data
+    done
+}
 
-compile
+for f in "$conf_dir"/*; do
+    if [[ -d "$f" ]]; then
+        continue
+    fi
+    conf=$(basename "$f")
+    echo "Compile configuration $conf"
+    quartus_get_result "$conf"
+done
 
-wait;
 
-perl ${SCRPT_DIR_PATH}/src/extract.prl "$PRONOC_WORK/verify/quartus_pronoc" "pronoc" > report 
+report_all_configurations
 
+perl ${SCRPT_DIR_PATH}/src/compare.pl "$golden_dir/$report" "$log_dir/$report" 
+echo "All configurations processed. Results are in $log_dir/$report"
 
 
diff --git a/mpsoc/Integration_test/Altera/src/compare.pl b/mpsoc/Integration_test/Altera/src/compare.pl
new file mode 100644
index 0000000..632793a
--- /dev/null
+++ b/mpsoc/Integration_test/Altera/src/compare.pl
@@ -0,0 +1,85 @@
+#!/usr/bin/perl
+use strict;
+use warnings;
+use Data::Dumper;
+
+# Usage: perl compare_results.pl file1.txt file2.txt
+
+my ($file1, $file2) = @ARGV;
+die "Usage: $0 file1 file2\n" unless $file1 && $file2;
+
+
+# Parse files normally
+my %data1 = parse_file($file1);
+my %data2 = parse_file($file2);
+
+sub is_number {
+    return defined $_[0] && $_[0] =~ /^-?\d+(\.\d+)?$/;
+}
+foreach my $design (sort keys %data2) {
+    my @fields = sort keys %{$data2{$design}};
+    print "=== $design ===\n";
+    for my $i (@fields) {
+        my $v1 = $data1{$design}{$i}// 'N/A';
+        my $v2 = $data2{$design}{$i}// 'N/A';
+        my $delta = 
+        ($v1 eq '0' && $v2 eq '0') ? 0: 
+        ($v1 eq 'N/A' && $v2 eq 'N/A') ? 'N/A' :
+        ($v1 eq 'N/A' || $v1 eq '0') ? 'N/A' : 
+        ($v2 eq 'N/A' ) ? 'N/A' :
+        sprintf("%.2f", (($v2 - $v1) / $v1) * 100);
+        
+        my $color = ($delta eq 'N/A') ? '' :
+            (($delta > 0 && $i ne 'Maxfrequency') || ($delta < 0 && $i eq 'Maxfrequency'))       ? "\e[31m" :  # red for positive
+            (($delta < 0 && $i ne 'Maxfrequency') || ($delta > 0 && $i eq 'Maxfrequency'))       ? "\e[32m" :  # green for negative
+            "";         # default (0)
+        my $reset = "\e[0m";
+        #print only if both $v1 and $v2 are numbers, or one is number the other is 'N/A'
+        my $print_me = 
+        (is_number($v1) && is_number($v2)) ||
+        (is_number($v1) && $v2 eq 'N/A') ||
+        (is_number($v2) && $v1 eq 'N/A');       
+        printf "%-25s: %10s -> %10s (%s%s%%%s)\n", $i, $v1, $v2, $color, $delta, $reset if($print_me);
+    }
+    print "\n";
+}
+
+# Parse and return both field names and data hash
+sub parse_file {
+    my ($fname) = @_;
+    open my $fh, '<', $fname or die "Cannot open $fname: $!\n";
+
+    my @fields;
+    my %results;
+
+    while (<$fh>) {
+        chomp;
+        next if /^\s*$/; #skip empty line
+        next if /^---$/; #skip separtion lines
+        if (scalar @fields ==0) {
+            s/^\s+|\s+$//g;
+            @fields = split /\|/;
+            shift @fields;  # remove first column name
+            s/^\s+|\s+$//g for @fields;
+            next;
+        }
+
+        my @cols = split /\|/;
+        s/^\s+|\s+$//g for @cols;
+        my $name = $cols[0];
+
+        my @values;
+        my $num=0;
+        for my $field (@cols) {
+            next if($name eq $field);
+            my ($used) = split /,/, $field;
+            $results{$name}{$fields[$num]} = $used;
+            $num++;
+        }
+    #    print Dumper(\$results{$name});
+    }
+    close $fh;
+    return (%results);
+}
+
+
diff --git a/mpsoc/Integration_test/Altera/src/extract.prl b/mpsoc/Integration_test/Altera/src/extract.prl
index d8ac929..a401c4b 100755
--- a/mpsoc/Integration_test/Altera/src/extract.prl
+++ b/mpsoc/Integration_test/Altera/src/extract.prl
@@ -1,116 +1,125 @@
 #!/usr/bin/perl -w
-use Cwd qw(getcwd);
-use IPC::Run qw( run start pump finish timeout );
-
-
-
-my @HWs = (
-"; Logic utilization                                                                 ;",
-";     Combinational ALUTs           ;",
-";     Memory ALUTs                  ;",
-";     Dedicated logic registers     ;",
-"; Total block memory bits           ;",
-"; ALMs:  partially or completely used                                               ;",
-"; M9K blocks                                                                        ;"
+use strict;
+use warnings;
 
+use Cwd qw(getcwd);
+use IPC::Run qw(run timeout);
+
+# Regular expression to match hardware utilization results like:
+#   2,460 / 36,100 ( 7 % )
+#   5808 , 2939904 ( < 1 % )
+my $result_reg  = '[[:space:]]*[0-9,]+[[:space:]]*[,/][[:space:]]*[0-9,]+[[:space:]]*'
+                . '\([[:space:]]*(<\s*)?[0-9]+[[:space:]]*%[[:space:]]*\)[[:space:]]*;';
+
+# Hash of report labels and their corresponding regex patterns
+my %HWs = (
+    'Logic utilization'               => ';[[:space:]]*Logic utilization[[:space:]]*;' . $result_reg,
+    'Combinational ALUTs'            => ';[[:space:]]*Combinational ALUTs[[:space:]]*;' . $result_reg,
+    'Memory ALUTs'                   => ';[[:space:]]*Memory ALUTs[[:space:]]*;' . $result_reg,
+    'Dedicated logic registers'      => ';[[:space:]]*Dedicated logic registers[[:space:]]*;' . $result_reg,
+    'Total block memory bits'        => ';[[:space:]]*Total block memory bits[[:space:]]*;' . $result_reg,
+    'ALMs: partially or completely used' => ';[[:space:]]*ALMs:[[:space:]]*partially or completely used[[:space:]]*;' . $result_reg,
+    'M9K blocks'                     => ';[[:space:]]*M9K blocks[[:space:]]*;' . $result_reg,
 );
 
+my %HIST =(
+    'Warnings' => 'Warning[[:space:]]*\(',
+);
 
-
-my $csv="";
+# Result containers
 my %freq;
 my %results;
+my %histograms;
+my $csv = "";
 
 sub extract_results {
- 	my ($dir,$parent) =@_;
-	my @cat = qw( bash  ); 
-	chdir "$dir";
-	print getcwd()."\n";
-	
-	my ($in, $out, $err); 	
-	#Fmax
-	$in ='grep -R "; clk        ;      ;$" | sort';
-    run \@cat, \$in, \$out, \$err, timeout( 10 ) or die "grep: $?";
-	
-
-	my @lines = split("\n",$out);
-	foreach my $l (@lines)  {
-	
-		my @f=split ('/',$l);
-		my $name= "${parent}_$f[0]";
-		
-		@f=split (':',$l);
-		@f=split (';',$f[1]);
-		$f[1] =~ s/MHz//;
-		
-		if(!defined $freq{$name}){
-			$freq{$name}=$f[1];
-		}else{#get the minum reported max frequency
-			$freq{$name}=$f[1] if($f[1]< $freq{$name});
-		}
-	
-	}
-
-	
-
-
-	foreach my $hw (@HWs){
-		
-		
-		
-		my @cat = qw( bash  );
-		my $in ="grep -R \"$hw\" | sort";
-		$hw =~ s/[\;]//g;
-		
-		#$csv.="-,$hw\n";
-		$out=undef;		
-		run \@cat, \$in, \$out, \$err, timeout( 10 ) or die "grep: $?";
-		@lines = split("\n",$out);
-		
-		foreach my $l (@lines)  {
-			unless ( index($l,".fit.rpt") >= 0){ next;}
-			
-			my @f=split ('/',$l);	
-			 
-			my $name= "${parent}_$f[0]";
-			my @ff = split (/\; /,$l);
-			my $val=$ff[2];
-			$val =~ s/,//g;
-			my @vv = split ("/",$val);
-			my $t =join(',',@vv);
-			#$csv.= "$name, $t  \n" if (defined $val) ;
-			$results{$hw}{$name}=$t if (defined $val) ;
-		}
-	}
-
+    my ($dir, $parent) = @_;
+    chdir $dir or die "Cannot change to directory $dir: $!";
+
+    # -----------------------
+    # Extract Fmax frequency
+    # -----------------------
+    my ($in, $out, $err);
+    $in = 'grep -R "; clk        ;      ;$" | sort';
+    run ['bash'], \$in, \$out, \$err, timeout(10) or die "Error running Fmax grep: $?";
+    my $name;
+    for my $line (split "\n", $out) {
+        my ($file) = split '/', $line;
+        $name = "${parent}_$file";
+
+        my @parts = split ':', $line;
+        my @fields = split ';', $parts[1];
+        my $mhz = $fields[1];
+        $mhz =~ s/MHz//;
+
+        $freq{$name} = $mhz if !defined($freq{$name}) || $mhz < $freq{$name};
+    }
+
+    # -----------------------
+    # Extract HW usage stats
+    # -----------------------
+    for my $metric (sort keys %HWs) {
+        my $regex = $HWs{$metric};
+        my $grep_cmd = "grep -RE '$regex' | sort";
+
+        $out = undef;
+        run ['bash'], \$grep_cmd, \$out, \$err, timeout(10) or die "Error running grep for $metric: $?";
+
+        for my $line (split "\n", $out) {
+            next unless $line =~ /\.fit\.rpt/;
+
+            my ($file) = split '/', $line;
+            $name = "${parent}_$file";
+
+            my @fields = split(/\; /, $line);
+            my $value = $fields[2];
+            $value =~ s/[;,]//g;
+
+            my @numbers = split /[\/,]/, $value;
+            $results{$metric}{$name} = join(',', @numbers);
+        }
+    }
+    # --------------------------
+    #   Count number of warnings/Errors
+    #---------------------------
+    for my $metric (sort keys %HIST) {
+        my $regex = $HIST{$metric};
+        my $grep_cmd = "grep -RE '$regex'  | wc -l";
+        $out = undef;
+        run ['bash'], \$grep_cmd, \$out, \$err, timeout(10) or die "Error running grep for $metric: $?";
+        $histograms{$metric} = $out;
+    }
+    
 }
 
+# Main execution
+extract_results($ARGV[0], $ARGV[1]);
 
+# Print frequency results
+$csv .= "Max frequency |";
+for my $p (sort keys %freq) {
+    $csv .= "$freq{$p},  $freq{$p} MHz\n";
+}
 
-print "extract_results($ARGV[0],$ARGV[1]);\n";
-
-extract_results($ARGV[0],$ARGV[1]);
+# Print hardware utilization results
+for my $metric (sort keys %results) {
+    $csv .= "\n$metric |";
+    for my $design (sort keys %{ $results{$metric} }) {
+        $csv .= "  $results{$metric}{$design}\n";
+    }
+}
 
+for my $metric (sort keys %histograms) {
+    $csv .= "\n$metric |";
+    $csv .= "  $histograms{$metric}\n";
+}
 
 
 
-$csv.=" , Fr_max\n";
-foreach my $p (sort keys  %freq){		
-		$csv.= "$p, $freq{$p},  Fmax = $freq{$p} Mhz\n";
-}
 
+# Output
+print $csv;
 
-foreach my $p (sort keys  %results){
-	my $ref = $results{$p};
-	my %r = %{$results{$p}} if (defined $ref) ;
-	$csv.= "\n\n\n\n" ;	
-	$csv.="-,$p\n";
-	foreach my $p (sort keys  %r){
-		$csv.= "$p, $r{$p}  \n";
-	}
 
-}
 
-print "***************** results *****************\n";	
-	print $csv;
 
diff --git a/mpsoc/Integration_test/Altera/src/noc_localparam.v b/mpsoc/Integration_test/Altera/src/noc_localparam.v
deleted file mode 100644
index 60d1db2..0000000
--- a/mpsoc/Integration_test/Altera/src/noc_localparam.v
+++ /dev/null
@@ -1,50 +0,0 @@
-
-`ifdef NOC_LOCAL_PARAM
-
-
-
-
-//NoC parameters
-	localparam TOPOLOGY="MESH";
-	localparam T1=3;
-	localparam T2=3;
-	localparam T3=1;
-	localparam V=2;
-	localparam B=4;
-	localparam LB=16;
-	localparam Fpay=32;
-	localparam ROUTE_NAME="XY";
-	localparam PCK_TYPE =  "MULTI_FLIT";    //"SINGLE_FLIT";
-	localparam MIN_PCK_SIZE=1;
-	localparam BYTE_EN=0;
-	localparam SSA_EN="YES";
-	localparam CONGESTION_INDEX=3;
-	localparam ESCAP_VC_MASK=2'b01;
-	localparam VC_REALLOCATION_TYPE="NONATOMIC";
-	localparam COMBINATION_TYPE="COMB_NONSPEC";
-	localparam MUX_TYPE="BINARY";
-	localparam C=0;
-	localparam DEBUG_EN=1;
-	localparam ADD_PIPREG_AFTER_CROSSBAR=1'b0;
-	localparam FIRST_ARBITER_EXT_P_EN=1;
-	localparam SWA_ARBITER_TYPE="RRA";
-	localparam WEIGHTw=4;
-	localparam AVC_ATOMIC_EN=0;	
- 	localparam CVw=(C==0)? V : C * V;
-	localparam CLASS_SETTING={CVw{1'b1}};
- 	localparam SMART_MAX=0;
-    localparam SELF_LOOP_EN="YES";
-    localparam CAST_TYPE = "UNICAST";
-	localparam MCAST_ENDP_LIST = 'b11110011;	
-	//localparam MCAST_PRTLw=6;
-	
-	
-	
-	//simulation parameter	
-	//localparam MAX_RATIO = 1000;
-	localparam MAX_PCK_NUM = 1000000000;
-	localparam MAX_PCK_SIZ = 16383; 
-	localparam MAX_SIM_CLKs=  1000000000;
-	localparam TIMSTMP_FIFO_NUM = 16;	
-
-`endif
diff --git a/mpsoc/Integration_test/Altera/src/param_gen.pl b/mpsoc/Integration_test/Altera/src/param_gen.pl
new file mode 100644
index 0000000..a97679f
--- /dev/null
+++ b/mpsoc/Integration_test/Altera/src/param_gen.pl
@@ -0,0 +1,38 @@
+#!/usr/bin/perl -w
+package ProNOC;
+use strict;
+use warnings;
+use File::Basename;
+
+
+#add home dir in perl 5.6
+use FindBin;
+use lib $FindBin::Bin;
+use constant::boolean;
+
+use File::Path qw(make_path);
+
+
+use strict;
+use warnings;
+
+use base 'Class::Accessor::Fast';
+
+
+my $script_path = dirname(__FILE__);
+require "$script_path/../../synthetic_sim/src/src.pl";
+
+my $conf_file=$ARGV[0];
+
+
+sub create_noc_param_vv {
+    my ($conf_file)=@_;
+    my $o = do $conf_file;
+    die "Could not parse $conf_file: $@" if $@;
+    die "Could not read $conf_file: $!" unless defined $o;
+    my $param = $o->{'noc_param'};
+    my ($param_v,$include_h,$tops)=   gen_noc_localparam_v( $o,$param);
+    save_file("$script_path/noc_localparam.v",$param_v);
+}
+
+create_noc_param_vv ($conf_file);
diff --git a/mpsoc/Integration_test/Altera/src/quartus_pronoc.sv b/mpsoc/Integration_test/Altera/src/quartus_pronoc.sv
index ab1e546..9a15aca 100644
--- a/mpsoc/Integration_test/Altera/src/quartus_pronoc.sv
+++ b/mpsoc/Integration_test/Altera/src/quartus_pronoc.sv
@@ -1,67 +1,63 @@
 `include "pronoc_def.v"
 
 module quartus_pronoc
-#(
- 	parameter NOC_ID = 0
-)(
-	clk,
-	reset,
-	chan_in,
-	chan_out,
-	sel_in,
-	sel_out	
+(
+    clk,
+    reset,
+    chan_in,
+    chan_out,
+    sel_in,
+    sel_out
 );
 
-	`NOC_CONF				
-
-	input  [NE-1      :   0]  sel_in;
-	input  [NEw-1     :   0]  sel_out;
-	input  smartflit_chanel_t chan_in;
-	output  smartflit_chanel_t chan_out;
-	input reset,clk;
-	
-
-	smartflit_chanel_t chan_in_all  [NE-1 : 0];
-	smartflit_chanel_t chan_out_all [NE-1 : 0];
-	smartflit_chanel_t chan_out_all_reg [NE-1 : 0];
-	
-	wire noc_reset;
-
-	noc_top #(
-		.NOC_ID(NOC_ID)
-	) top (
-		.reset(noc_reset),
-		.clk(clk),    
-		.chan_in_all(chan_in_all),
-		.chan_out_all(chan_out_all),
-		.router_event( )
-	);
-	
-	
-	altera_reset_synchronizer sync(
-		.reset_in	(reset), 
-		.clk		(clk),
-		.reset_out	(noc_reset)
-	);
-
-	//NoC port assignment
-	
-	assign chan_out	= chan_out_all_reg[sel_out];  
-
-	always @(posedge clk) begin 
-		chan_out_all_reg	<= chan_out_all;   		
-	end
+    import pronoc_pkg::*;
+
+    input  [NE-1      :   0]  sel_in;
+    input  [NEw-1     :   0]  sel_out;
+    input  smartflit_chanel_t chan_in;
+    output  smartflit_chanel_t chan_out;
+    input reset,clk;
+    
+
+    smartflit_chanel_t chan_in_all  [NE-1 : 0];
+    smartflit_chanel_t chan_out_all [NE-1 : 0];
+    smartflit_chanel_t chan_out_all_reg [NE-1 : 0];
+    
+    wire noc_reset;
+
+    noc_top top (
+        .reset(noc_reset),
+        .clk(clk),    
+        .chan_in_all(chan_in_all),
+        .chan_out_all(chan_out_all),
+        .router_event( )
+    );
+    
+    
+    altera_reset_synchronizer sync(
+        .reset_in    (reset), 
+        .clk        (clk),
+        .reset_out    (noc_reset)
+    );
+
+    //NoC port assignment
+    
+    assign chan_out    = chan_out_all_reg[sel_out];  
+
+    always @(posedge clk) begin 
+        chan_out_all_reg  <= chan_out_all;
+    end
 
-	genvar IP_NUM;
-	generate 
+    genvar IP_NUM;
+    generate 
     for (IP_NUM=0;   IP_NUM<NE; IP_NUM=IP_NUM+1) begin :endp
 
-			always @(posedge clk) begin 
-				if(sel_in[IP_NUM] ) begin 
-					 chan_in_all[IP_NUM]<= chan_in;					
-				end 
-			end          
+            always @(posedge clk) begin 
+                if(sel_in[IP_NUM] ) begin 
+                    chan_in_all[IP_NUM]<= chan_in;
+                end 
+            end
     end
-	endgenerate
+    endgenerate
 
 endmodule
diff --git a/mpsoc/Integration_test/FPGA-kc07/models/mesh_4x4_2cycle_xy_v1 b/mpsoc/Integration_test/FPGA-kc07/models/mesh_4x4_2cycle_xy_v1
index 68179c9..279821c 100644
--- a/mpsoc/Integration_test/FPGA-kc07/models/mesh_4x4_2cycle_xy_v1
+++ b/mpsoc/Integration_test/FPGA-kc07/models/mesh_4x4_2cycle_xy_v1
@@ -1,6 +1,6 @@
 $model = bless( {
 		'compile' => "verilate_mesh.sh",
         'noc_param'=> {
-						"ROUTE_NAME" => "\"XY\"",    					
+						"ROUTE_NAME" => "\"DOR\"",    					
 						}
 }, 'ProNOC' );
diff --git a/mpsoc/Integration_test/FPGA-kc07/src/deafult_noc_param b/mpsoc/Integration_test/FPGA-kc07/src/deafult_noc_param
index ea24d7d..35fa420 100644
--- a/mpsoc/Integration_test/FPGA-kc07/src/deafult_noc_param
+++ b/mpsoc/Integration_test/FPGA-kc07/src/deafult_noc_param
@@ -8,11 +8,11 @@ $model = bless( {
 "B" => "4",
 "LB" => "B",
 "Fpay" => "32",
-"ROUTE_NAME" => "\"XY\"",
+"ROUTE_NAME" => "\"DOR\"",
 "PCK_TYPE" => "  \"MULTI_FLIT\"",  
 "MIN_PCK_SIZE" => "2",
 "BYTE_EN" => "0",
-"SSA_EN" => "\"NO\"",
+"SSA_EN" => "0",
 "CONGESTION_INDEX" => "3",
 "ESCAP_VC_MASK" => "2'b01",
 "VC_REALLOCATION_TYPE" => "\"NONATOMIC\"",
@@ -27,7 +27,7 @@ $model = bless( {
 "WEIGHTw" => "4",
 "AVC_ATOMIC_EN" => "0",
 "SMART_MAX" => "0",
-"SELF_LOOP_EN" => "\"NO\"",
+"SELF_LOOP_EN" => "0",
 "MAX_PCK_NUM " => " 1000000000",
 "MAX_PCK_SIZ " => " 16383" ,
 "MAX_SIM_CLKs" => "  1000000000",
diff --git a/mpsoc/Integration_test/FPGA-kc07/src/src.pl b/mpsoc/Integration_test/FPGA-kc07/src/src.pl
index 2e8ac8f..9ba2f89 100755
--- a/mpsoc/Integration_test/FPGA-kc07/src/src.pl
+++ b/mpsoc/Integration_test/FPGA-kc07/src/src.pl
@@ -18,7 +18,7 @@
 use warnings;
 
 my $pp;
-$pp= do "$src/deafult_noc_param";
+$pp= do "$src/default_noc_param";
 die "Error reading: $@" if $@;
 
 my $param = $pp->{'noc_param'};
diff --git a/mpsoc/Integration_test/Questa_lint/Questa_Starter_21.sh b/mpsoc/Integration_test/Questa_lint/Questa_Starter_21.sh
new file mode 100644
index 0000000..f61cb8a
--- /dev/null
+++ b/mpsoc/Integration_test/Questa_lint/Questa_Starter_21.sh
@@ -0,0 +1,5 @@
+export QUESTA_ST=$HOME/intelFPGA_lite/Questa_starter21
+export MGLS_LICENSE_FILE=;
+export LM_LICENSE_FILE=$QUESTA_ST/LR-173241_License.dat;
+export MODELSIM_HOME=$QUESTA_ST/questa_fse;
+export PATH=$PATH:$MODELSIM_HOME/bin;
diff --git a/mpsoc/Integration_test/synthetic_sim/configurations/default/Fattree_k3_L3_st b/mpsoc/Integration_test/Questa_lint/configurations/Fattree_k3_L3_st
similarity index 89%
rename from mpsoc/Integration_test/synthetic_sim/configurations/default/Fattree_k3_L3_st
rename to mpsoc/Integration_test/Questa_lint/configurations/Fattree_k3_L3_st
index 3f51129..e8816f6 100644
--- a/mpsoc/Integration_test/synthetic_sim/configurations/default/Fattree_k3_L3_st
+++ b/mpsoc/Integration_test/Questa_lint/configurations/Fattree_k3_L3_st
@@ -5,4 +5,5 @@ $model = bless( {
         "T2" => "3",
         "B"  => "5",
         "ROUTE_NAME" => "\"NCA_STRAIGHT_UP\"",
-}, 'ProNOC' );
\ No newline at end of file
+    }
+}, 'ProNOC' );
diff --git a/mpsoc/Integration_test/synthetic_sim/configurations/default/bintree_k3_L3_st b/mpsoc/Integration_test/Questa_lint/configurations/bintree_k3_L3_st
similarity index 81%
rename from mpsoc/Integration_test/synthetic_sim/configurations/default/bintree_k3_L3_st
rename to mpsoc/Integration_test/Questa_lint/configurations/bintree_k3_L3_st
index 9482df8..85fc4b5 100644
--- a/mpsoc/Integration_test/synthetic_sim/configurations/default/bintree_k3_L3_st
+++ b/mpsoc/Integration_test/Questa_lint/configurations/bintree_k3_L3_st
@@ -1,9 +1,9 @@
 $model = bless( {
-    noc_param'=> {
+    'noc_param'=> {
         "TOPOLOGY" => "\"TREE\"",
         "T1" => "3",
         "T2" => "3",
         "B"  => "5",
         "ROUTE_NAME" => "\"NCA\"",
     }
-}, 'ProNOC' );
\ No newline at end of file
+}, 'ProNOC' );
diff --git a/mpsoc/Integration_test/synthetic_sim/configurations/default/custom1_topology b/mpsoc/Integration_test/Questa_lint/configurations/custom1_topology
similarity index 100%
rename from mpsoc/Integration_test/synthetic_sim/configurations/default/custom1_topology
rename to mpsoc/Integration_test/Questa_lint/configurations/custom1_topology
diff --git a/mpsoc/Integration_test/synthetic_sim/configurations/default/fmesh_1x1_openpiton b/mpsoc/Integration_test/Questa_lint/configurations/fmesh_1x1_openpiton
similarity index 80%
rename from mpsoc/Integration_test/synthetic_sim/configurations/default/fmesh_1x1_openpiton
rename to mpsoc/Integration_test/Questa_lint/configurations/fmesh_1x1_openpiton
index fd30c47..f80a7c7 100644
--- a/mpsoc/Integration_test/synthetic_sim/configurations/default/fmesh_1x1_openpiton
+++ b/mpsoc/Integration_test/Questa_lint/configurations/fmesh_1x1_openpiton
@@ -8,8 +8,8 @@ $model = bless( {
         "B" => "4",
         "LB" => "16",
         "Fpay" => "64",
-        "SSA_EN" => "\"YES\"",
-        "SELF_LOOP_EN" => "\"YES\"",
+        "SSA_EN" => "1",
+        "SELF_LOOP_EN" => "1",
         "MIN_PCK_SIZE" => "1"
     }
 }, 'ProNOC' );
\ No newline at end of file
diff --git a/mpsoc/Integration_test/synthetic_sim/configurations/default/fmesh_2x2_openpiton b/mpsoc/Integration_test/Questa_lint/configurations/fmesh_2x2_openpiton
similarity index 78%
rename from mpsoc/Integration_test/synthetic_sim/configurations/default/fmesh_2x2_openpiton
rename to mpsoc/Integration_test/Questa_lint/configurations/fmesh_2x2_openpiton
index e2cfc21..449f321 100644
--- a/mpsoc/Integration_test/synthetic_sim/configurations/default/fmesh_2x2_openpiton
+++ b/mpsoc/Integration_test/Questa_lint/configurations/fmesh_2x2_openpiton
@@ -8,7 +8,7 @@ $model = bless( {
         "B" => "4",
         "LB" => "16",
         "Fpay" => "64",
-        "SSA_EN" => "\"YES\"",
-        "SELF_LOOP_EN" => "\"YES\"",
+        "SSA_EN" => "1",
+        "SELF_LOOP_EN" => "1",
     }
 }, 'ProNOC' );
\ No newline at end of file
diff --git a/mpsoc/Integration_test/synthetic_sim/configurations/default/fmesh_8x8_2cycle_xy b/mpsoc/Integration_test/Questa_lint/configurations/fmesh_8x8_2cycle_xy
similarity index 72%
rename from mpsoc/Integration_test/synthetic_sim/configurations/default/fmesh_8x8_2cycle_xy
rename to mpsoc/Integration_test/Questa_lint/configurations/fmesh_8x8_2cycle_xy
index ff79533..12a13c3 100644
--- a/mpsoc/Integration_test/synthetic_sim/configurations/default/fmesh_8x8_2cycle_xy
+++ b/mpsoc/Integration_test/Questa_lint/configurations/fmesh_8x8_2cycle_xy
@@ -1,6 +1,6 @@
 $model = bless( {
     'noc_param'=> {
         "TOPOLOGY" => "\"FMESH\"",
-        "ROUTE_NAME" => "\"XY\"",
+        "ROUTE_NAME" => "\"DOR\"",
     }
 }, 'ProNOC' );
\ No newline at end of file
diff --git a/mpsoc/Integration_test/synthetic_sim/configurations/default/fmesh_8x8_openpiton b/mpsoc/Integration_test/Questa_lint/configurations/fmesh_8x8_openpiton
similarity index 78%
rename from mpsoc/Integration_test/synthetic_sim/configurations/default/fmesh_8x8_openpiton
rename to mpsoc/Integration_test/Questa_lint/configurations/fmesh_8x8_openpiton
index e110fa6..37c19a2 100644
--- a/mpsoc/Integration_test/synthetic_sim/configurations/default/fmesh_8x8_openpiton
+++ b/mpsoc/Integration_test/Questa_lint/configurations/fmesh_8x8_openpiton
@@ -8,7 +8,7 @@ $model = bless( {
         "B" => "4",
         "LB" => "16",
         "Fpay" => "64",
-        "SSA_EN" => "\"YES\"",
-        "SELF_LOOP_EN" => "\"YES\"",
+        "SSA_EN" => "1",
+        "SELF_LOOP_EN" => "1",
     }
 }, 'ProNOC' );
\ No newline at end of file
diff --git a/mpsoc/Integration_test/Questa_lint/configurations/line4_smart3 b/mpsoc/Integration_test/Questa_lint/configurations/line4_smart3
new file mode 100644
index 0000000..548c123
--- /dev/null
+++ b/mpsoc/Integration_test/Questa_lint/configurations/line4_smart3
@@ -0,0 +1,16 @@
+$model = bless( {
+    'noc_param'=> {
+        "SMART_MAX" => "3",
+        TOPOLOGY=>"\"LINE\"",
+        "T1" => "4",
+        "T2" => "4",
+        "V" => "1",
+        "ESCAP_VC_MASK" => "1'b1",
+        "B" => "4",
+        "LB" => "16",
+        "Fpay" => "64",
+        "SSA_EN" => "0",
+        "SELF_LOOP_EN" => "1",
+        "MCAST_ENDP_LIST" => "'b11",
+    }
+}, 'ProNOC' );
\ No newline at end of file
diff --git a/mpsoc/Integration_test/Questa_lint/configurations/line_4_v1_B15 b/mpsoc/Integration_test/Questa_lint/configurations/line_4_v1_B15
new file mode 100644
index 0000000..5d00709
--- /dev/null
+++ b/mpsoc/Integration_test/Questa_lint/configurations/line_4_v1_B15
@@ -0,0 +1,14 @@
+$model = bless( {
+    'noc_param'=> {
+        TOPOLOGY=>"\"LINE\"",
+        "T1" => "4",
+        "T2" => "4",
+        "V" => "1",
+        "ESCAP_VC_MASK" => "1'b1",
+        "B" => "15",
+        "LB" => "15",
+        "Fpay" => "64",
+        "SSA_EN" => "0",
+        "SELF_LOOP_EN" => "0",
+    }
+}, 'ProNOC' );
\ No newline at end of file
diff --git a/mpsoc/Integration_test/Questa_lint/configurations/line_8_single_flit b/mpsoc/Integration_test/Questa_lint/configurations/line_8_single_flit
new file mode 100644
index 0000000..a73600b
--- /dev/null
+++ b/mpsoc/Integration_test/Questa_lint/configurations/line_8_single_flit
@@ -0,0 +1,9 @@
+$model = bless( {
+    'noc_param'=> {
+        TOPOLOGY=>"\"LINE\"",
+        "B" => "5",
+        "LB" => "5",
+        "MIN_PCK_SIZE" => "1",
+        "PCK_TYPE" => "  \"SINGLE_FLIT\"",
+    }
+}, 'ProNOC' );
\ No newline at end of file
diff --git a/mpsoc/Integration_test/synthetic_sim/configurations/default/mesh_2x2_openpiton b/mpsoc/Integration_test/Questa_lint/configurations/mesh_2x2_openpiton
similarity index 76%
rename from mpsoc/Integration_test/synthetic_sim/configurations/default/mesh_2x2_openpiton
rename to mpsoc/Integration_test/Questa_lint/configurations/mesh_2x2_openpiton
index cc8d20c..4b61b2e 100644
--- a/mpsoc/Integration_test/synthetic_sim/configurations/default/mesh_2x2_openpiton
+++ b/mpsoc/Integration_test/Questa_lint/configurations/mesh_2x2_openpiton
@@ -7,7 +7,7 @@ $model = bless( {
         "B" => "4",
         "LB" => "16",
         "Fpay" => "64",
-        "SSA_EN" => "\"YES\"",
-        "SELF_LOOP_EN" => "\"YES\"",
+        "SSA_EN" => "1",
+        "SELF_LOOP_EN" => "1",
     }
 }, 'ProNOC' );
\ No newline at end of file
diff --git a/mpsoc/Integration_test/Questa_lint/configurations/mesh_3d_4x3x2x2 b/mpsoc/Integration_test/Questa_lint/configurations/mesh_3d_4x3x2x2
new file mode 100644
index 0000000..5893919
--- /dev/null
+++ b/mpsoc/Integration_test/Questa_lint/configurations/mesh_3d_4x3x2x2
@@ -0,0 +1,10 @@
+$model = bless( {
+    'noc_param'=> {
+        "TOPOLOGY" => '"MESH_3D"',
+        "T1" => "4",
+        "T2" => "3",
+        "T3" => "2",
+        "T4" => "2",
+        "ROUTE_NAME" => '"DOR"',
+    }
+}, 'ProNOC' );
diff --git a/mpsoc/Integration_test/Questa_lint/configurations/mesh_3x3_v2_ssa b/mpsoc/Integration_test/Questa_lint/configurations/mesh_3x3_v2_ssa
new file mode 100644
index 0000000..1383775
--- /dev/null
+++ b/mpsoc/Integration_test/Questa_lint/configurations/mesh_3x3_v2_ssa
@@ -0,0 +1,12 @@
+$model = bless( {
+    'noc_param'=> {
+        "T1" => "3",
+        "T2" => "3",
+        "SELF_LOOP_EN" => "1",
+        "SSA_EN"=> "1",
+        "LB" => 16,
+        "DEBUG_EN" => "0",   
+        "MIN_PCK_SIZE"  => "1", 
+        "Fpay" => "64",   
+    }
+}, 'ProNOC' );
diff --git a/mpsoc/Integration_test/synthetic_sim/configurations/default/mesh_4x4_2cycle_mcast_f b/mpsoc/Integration_test/Questa_lint/configurations/mesh_4x4_2cycle_mcast_f
similarity index 100%
rename from mpsoc/Integration_test/synthetic_sim/configurations/default/mesh_4x4_2cycle_mcast_f
rename to mpsoc/Integration_test/Questa_lint/configurations/mesh_4x4_2cycle_mcast_f
diff --git a/mpsoc/Integration_test/Questa_lint/configurations/mesh_4x4_LB5_B4 b/mpsoc/Integration_test/Questa_lint/configurations/mesh_4x4_LB5_B4
new file mode 100644
index 0000000..50ac90c
--- /dev/null
+++ b/mpsoc/Integration_test/Questa_lint/configurations/mesh_4x4_LB5_B4
@@ -0,0 +1,12 @@
+$model = bless( {
+    'noc_param'=> {
+        "T1" => "4",
+        "T2" => "4",
+        "B"  => "4",
+        "LB" => "5",
+        "CAST_TYPE" => "\"MULTICAST_PARTIAL\"",
+        "MCAST_ENDP_LIST" => "16'b110011000111101",
+        "Fpay" => "64",
+        "SELF_LOOP_EN" => "1"
+    }
+}, 'ProNOC' );
\ No newline at end of file
diff --git a/mpsoc/Integration_test/Questa_lint/configurations/mesh_4x4_selflp_mcast_f b/mpsoc/Integration_test/Questa_lint/configurations/mesh_4x4_selflp_mcast_f
new file mode 100644
index 0000000..5c5852e
--- /dev/null
+++ b/mpsoc/Integration_test/Questa_lint/configurations/mesh_4x4_selflp_mcast_f
@@ -0,0 +1,9 @@
+$model = bless( {
+    'noc_param'=> {
+        "T1" => "4",
+        "T2" => "4",
+        "CAST_TYPE" => "\"MULTICAST_FULL\"",
+        "Fpay" => "64",
+        "SELF_LOOP_EN" => "1"
+    }
+}, 'ProNOC' );
\ No newline at end of file
diff --git a/mpsoc/Integration_test/synthetic_sim/configurations/default/mesh_4x4_smart3 b/mpsoc/Integration_test/Questa_lint/configurations/mesh_4x4_smart3
similarity index 80%
rename from mpsoc/Integration_test/synthetic_sim/configurations/default/mesh_4x4_smart3
rename to mpsoc/Integration_test/Questa_lint/configurations/mesh_4x4_smart3
index 1618a2d..ad8749e 100644
--- a/mpsoc/Integration_test/synthetic_sim/configurations/default/mesh_4x4_smart3
+++ b/mpsoc/Integration_test/Questa_lint/configurations/mesh_4x4_smart3
@@ -9,7 +9,7 @@ $model = bless( {
         "B" => "4",
         "LB" => "16",
         "Fpay" => "64",
-        "SSA_EN" => "\"NO\"",
-        "SELF_LOOP_EN" => "\"YES\"",
+        "SSA_EN" => "0",
+        "SELF_LOOP_EN" => "1",
     }
 }, 'ProNOC' );
\ No newline at end of file
diff --git a/mpsoc/Integration_test/synthetic_sim/configurations/default/mesh_4x4_v1_B15 b/mpsoc/Integration_test/Questa_lint/configurations/mesh_4x4_v1_B15
similarity index 77%
rename from mpsoc/Integration_test/synthetic_sim/configurations/default/mesh_4x4_v1_B15
rename to mpsoc/Integration_test/Questa_lint/configurations/mesh_4x4_v1_B15
index 05bb0f9..a07a491 100644
--- a/mpsoc/Integration_test/synthetic_sim/configurations/default/mesh_4x4_v1_B15
+++ b/mpsoc/Integration_test/Questa_lint/configurations/mesh_4x4_v1_B15
@@ -7,7 +7,7 @@ $model = bless( {
         "B" => "15",
         "LB" => "15",
         "Fpay" => "64",
-        "SSA_EN" => "\"NO\"",
-        "SELF_LOOP_EN" => "\"NO\"",
+        "SSA_EN" => "0",
+        "SELF_LOOP_EN" => "0",
     }
 }, 'ProNOC' );
\ No newline at end of file
diff --git a/mpsoc/Integration_test/Questa_lint/configurations/mesh_4x4x2_bcast_f b/mpsoc/Integration_test/Questa_lint/configurations/mesh_4x4x2_bcast_f
new file mode 100644
index 0000000..dc24a2f
--- /dev/null
+++ b/mpsoc/Integration_test/Questa_lint/configurations/mesh_4x4x2_bcast_f
@@ -0,0 +1,10 @@
+$model = bless( {
+    'noc_param'=> {
+        "T1" => "4",
+        "T2" => "4",
+        "T3" => "2",
+        "CAST_TYPE" => "\"BROADCAST_FULL\"",
+        "MCAST_ENDP_LIST" => "32'b1100110001111",
+        "Fpay" => "64"
+    }
+}, 'ProNOC' );
\ No newline at end of file
diff --git a/mpsoc/Integration_test/Questa_lint/configurations/mesh_4x4x2_bcast_p b/mpsoc/Integration_test/Questa_lint/configurations/mesh_4x4x2_bcast_p
new file mode 100644
index 0000000..23c4749
--- /dev/null
+++ b/mpsoc/Integration_test/Questa_lint/configurations/mesh_4x4x2_bcast_p
@@ -0,0 +1,10 @@
+$model = bless( {
+    'noc_param'=> {
+        "T1" => "4",
+        "T2" => "4",
+        "T3" => "2",
+        "CAST_TYPE" => "\"BROADCAST_PARTIAL\"",
+        "MCAST_ENDP_LIST" => "32'b1100110001111",
+        "Fpay" => "64"
+    }
+}, 'ProNOC' );
\ No newline at end of file
diff --git a/mpsoc/Integration_test/Questa_lint/configurations/mesh_4x4x2_mcast_p b/mpsoc/Integration_test/Questa_lint/configurations/mesh_4x4x2_mcast_p
new file mode 100644
index 0000000..ad2854b
--- /dev/null
+++ b/mpsoc/Integration_test/Questa_lint/configurations/mesh_4x4x2_mcast_p
@@ -0,0 +1,10 @@
+$model = bless( {
+    'noc_param'=> {
+        "T1" => "4",
+        "T2" => "4",
+        "T3" => "2",
+        "CAST_TYPE" => "\"MULTICAST_PARTIAL\"",
+        "MCAST_ENDP_LIST" => "32'b1100110001111",
+        "Fpay" => "64"
+    }
+}, 'ProNOC' );
\ No newline at end of file
diff --git a/mpsoc/Integration_test/synthetic_sim/configurations/default/mesh_4x4x3_2cycle_xy b/mpsoc/Integration_test/Questa_lint/configurations/mesh_4x4x3_2cycle_xy
similarity index 81%
rename from mpsoc/Integration_test/synthetic_sim/configurations/default/mesh_4x4x3_2cycle_xy
rename to mpsoc/Integration_test/Questa_lint/configurations/mesh_4x4x3_2cycle_xy
index f0c8499..ee47bc2 100644
--- a/mpsoc/Integration_test/synthetic_sim/configurations/default/mesh_4x4x3_2cycle_xy
+++ b/mpsoc/Integration_test/Questa_lint/configurations/mesh_4x4x3_2cycle_xy
@@ -4,6 +4,6 @@ $model = bless( {
         "T2" => "4",
         "T3" => "3",
         "TOPOLOGY" => "\"MESH\"",
-        "ROUTE_NAME" => "\"XY\"",
+        "ROUTE_NAME" => "\"DOR\"",
     }
 }, 'ProNOC' );
\ No newline at end of file
diff --git a/mpsoc/Integration_test/Questa_lint/configurations/mesh_4x4x3_vc_nonspec b/mpsoc/Integration_test/Questa_lint/configurations/mesh_4x4x3_vc_nonspec
new file mode 100644
index 0000000..6bb1a40
--- /dev/null
+++ b/mpsoc/Integration_test/Questa_lint/configurations/mesh_4x4x3_vc_nonspec
@@ -0,0 +1,10 @@
+$model = bless( {
+    'noc_param'=> {
+		"T1" => "4",
+		"T2" => "4",	
+		"T3" => "3",							
+		"TOPOLOGY" => "\"MESH\"",						
+		"ROUTE_NAME" => "\"DOR\"",
+		"COMBINATION_TYPE" => "\"COMB_NONSPEC\"",     					
+	}
+}, 'ProNOC' );
\ No newline at end of file
diff --git a/mpsoc/Integration_test/Questa_lint/configurations/mesh_4x4x3_vc_spec1 b/mpsoc/Integration_test/Questa_lint/configurations/mesh_4x4x3_vc_spec1
new file mode 100644
index 0000000..1c5388c
--- /dev/null
+++ b/mpsoc/Integration_test/Questa_lint/configurations/mesh_4x4x3_vc_spec1
@@ -0,0 +1,10 @@
+$model = bless( {
+    'noc_param'=> {
+		"T1" => "4",
+		"T2" => "4",	
+		"T3" => "3",							
+		"TOPOLOGY" => "\"MESH\"",						
+		"ROUTE_NAME" => "\"DOR\"",
+		"COMBINATION_TYPE" => "\"COMB_SPEC1\"",  						  					
+	}
+}, 'ProNOC' );
\ No newline at end of file
diff --git a/mpsoc/Integration_test/Questa_lint/configurations/mesh_4x4x3_vc_spec2 b/mpsoc/Integration_test/Questa_lint/configurations/mesh_4x4x3_vc_spec2
new file mode 100644
index 0000000..ed2a7f9
--- /dev/null
+++ b/mpsoc/Integration_test/Questa_lint/configurations/mesh_4x4x3_vc_spec2
@@ -0,0 +1,10 @@
+$model = bless( {
+    'noc_param'=> {
+		"T1" => "4",
+		"T2" => "4",	
+		"T3" => "3",							
+		"TOPOLOGY" => "\"MESH\"",						
+		"ROUTE_NAME" => "\"DOR\"",
+		"COMBINATION_TYPE" => "\"COMB_SPEC2\"",  						  					
+	}
+}, 'ProNOC' );
\ No newline at end of file
diff --git a/mpsoc/Integration_test/synthetic_sim/configurations/default/mesh_8x8_2cycle_adaptive b/mpsoc/Integration_test/Questa_lint/configurations/mesh_8x8_2cycle_adaptive
similarity index 69%
rename from mpsoc/Integration_test/synthetic_sim/configurations/default/mesh_8x8_2cycle_adaptive
rename to mpsoc/Integration_test/Questa_lint/configurations/mesh_8x8_2cycle_adaptive
index 20550e3..0aaa94e 100644
--- a/mpsoc/Integration_test/synthetic_sim/configurations/default/mesh_8x8_2cycle_adaptive
+++ b/mpsoc/Integration_test/Questa_lint/configurations/mesh_8x8_2cycle_adaptive
@@ -1,6 +1,6 @@
 $model = bless( {
     'noc_param'=> {
-        "ROUTE_NAME" => "\"DUATO\"",
+        "ROUTE_NAME" => "\"FULL_ADPT\"",
         "ESCAP_VC_MASK" => "2'b01"
     }
 }, 'ProNOC' );
\ No newline at end of file
diff --git a/mpsoc/Integration_test/synthetic_sim/configurations/default/mesh_8x8_2cycle_west_first b/mpsoc/Integration_test/Questa_lint/configurations/mesh_8x8_2cycle_west_first
similarity index 100%
rename from mpsoc/Integration_test/synthetic_sim/configurations/default/mesh_8x8_2cycle_west_first
rename to mpsoc/Integration_test/Questa_lint/configurations/mesh_8x8_2cycle_west_first
diff --git a/mpsoc/Integration_test/Questa_lint/configurations/mesh_8x8_2cycle_xy b/mpsoc/Integration_test/Questa_lint/configurations/mesh_8x8_2cycle_xy
new file mode 100644
index 0000000..7107201
--- /dev/null
+++ b/mpsoc/Integration_test/Questa_lint/configurations/mesh_8x8_2cycle_xy
@@ -0,0 +1,5 @@
+$model = bless( {
+    'noc_param'=> {
+        "ROUTE_NAME" => "\"DOR\"",
+    }
+}, 'ProNOC' );
\ No newline at end of file
diff --git a/mpsoc/Integration_test/Questa_lint/configurations/mesh_8x8_4vc b/mpsoc/Integration_test/Questa_lint/configurations/mesh_8x8_4vc
new file mode 100644
index 0000000..1914e8b
--- /dev/null
+++ b/mpsoc/Integration_test/Questa_lint/configurations/mesh_8x8_4vc
@@ -0,0 +1,7 @@
+$model = bless( {
+    'noc_param'=> {
+        "ROUTE_NAME" => "\"DOR\"",
+        "ESCAP_VC_MASK" => "4'd1",
+        "V" => 4,
+    }
+}, 'ProNOC' );
diff --git a/mpsoc/Integration_test/synthetic_sim/configurations/default/mesh_8x8_4vc_4c b/mpsoc/Integration_test/Questa_lint/configurations/mesh_8x8_4vc_4c
similarity index 83%
rename from mpsoc/Integration_test/synthetic_sim/configurations/default/mesh_8x8_4vc_4c
rename to mpsoc/Integration_test/Questa_lint/configurations/mesh_8x8_4vc_4c
index d2f38c8..26296f7 100644
--- a/mpsoc/Integration_test/synthetic_sim/configurations/default/mesh_8x8_4vc_4c
+++ b/mpsoc/Integration_test/Questa_lint/configurations/mesh_8x8_4vc_4c
@@ -1,6 +1,6 @@
 $model = bless( {
     'noc_param'=> {
-        "ROUTE_NAME" => "\"XY\"",
+        "ROUTE_NAME" => "\"DOR\"",
         "V" => 4,
         "C" => 4,
         "CLASS_SETTING" => "16'b1000010000100001",
diff --git a/mpsoc/Integration_test/Questa_lint/configurations/mesh_8x8_4vc_hetero1 b/mpsoc/Integration_test/Questa_lint/configurations/mesh_8x8_4vc_hetero1
new file mode 100644
index 0000000..89af385
--- /dev/null
+++ b/mpsoc/Integration_test/Questa_lint/configurations/mesh_8x8_4vc_hetero1
@@ -0,0 +1,77 @@
+$model = bless( {
+    'noc_param'=> {
+        "ROUTE_NAME" => "\"DOR\"",
+        "ESCAP_VC_MASK" => "4'd1",
+        "V" => 4,
+        "HETERO_VC"=> "1",
+        "MAX_ROUTER"=>"64",
+        "MAX_PORT"=>"1",
+        "int VC_CONFIG_TABLE [MAX_ROUTER][MAX_PORT]"=>"'{
+    //P0 P1 P2 P3 P4 
+    '{1}, // R0
+    '{2}, // R1
+    '{3}, // R2
+    '{4}, // R3
+    '{1}, // R4
+    '{2}, // R5
+    '{3}, // R6
+    '{4}, // R7
+    '{1}, // R8
+    '{2}, // R9
+    '{3}, // R10
+    '{4}, // R11
+    '{1}, // R12
+    '{2}, // R13
+    '{3}, // R14
+    '{1},  // R15
+    '{2}, // R16
+    '{3}, // R17
+    '{4}, // R18
+    '{1}, // R19
+    '{2}, // R20
+    '{3}, // R21
+    '{4}, // R22
+    '{1}, // R23
+    '{2}, // R24
+    '{3}, // R25
+    '{4}, // R26
+    '{1}, // R27
+    '{2}, // R28
+    '{3}, // R29
+    '{1}, // R30
+    '{2}, // R31
+    '{3}, // R32
+    '{4}, // R33
+    '{1}, // R34
+    '{2}, // R35
+    '{3}, // R36
+    '{4}, // R37
+    '{1}, // R38
+    '{2}, // R39
+    '{3}, // R40
+    '{4}, // R41
+    '{1}, // R42
+    '{2}, // R43
+    '{3}, // R44
+    '{1}, // R45
+    '{2}, // R46
+    '{3}, // R47
+    '{4}, // R48
+    '{1}, // R49
+    '{2}, // R50
+    '{3}, // R51
+    '{4}, // R52
+    '{1}, // R53
+    '{2}, // R54
+    '{3}, // R55
+    '{4}, // R56
+    '{1}, // R57
+    '{2}, // R58
+    '{3}, // R59
+    '{1}, // R60
+    '{2}, // R61
+    '{3}, // R62
+    '{4} // R63
+    }",
+    }
+}, 'ProNOC' );
diff --git a/mpsoc/Integration_test/Questa_lint/configurations/mesh_8x8_4vc_hetero2 b/mpsoc/Integration_test/Questa_lint/configurations/mesh_8x8_4vc_hetero2
new file mode 100644
index 0000000..bc13a6f
--- /dev/null
+++ b/mpsoc/Integration_test/Questa_lint/configurations/mesh_8x8_4vc_hetero2
@@ -0,0 +1,77 @@
+$model = bless( {
+    'noc_param'=> {
+        "ROUTE_NAME" => "\"DOR\"",
+        "V" => 4,
+        "ESCAP_VC_MASK" => "4'd1",
+        "HETERO_VC"=> "2",
+        "MAX_ROUTER"=>"64",
+        "MAX_PORT"=>"5",
+        "int VC_CONFIG_TABLE [MAX_ROUTER][MAX_PORT]"=>"'{
+	//P0 P1 P2 P3 P4 
+	'{1, 2, 3, 4, 1}, // R0
+	'{2, 3, 4, 1, 2}, // R1
+	'{3, 4, 1, 2, 3}, // R2
+	'{4, 1, 2, 3, 4}, // R3
+	'{1, 2, 3, 4, 1}, // R4
+	'{2, 3, 4, 1, 2}, // R5
+	'{3, 4, 1, 2, 3}, // R6
+	'{4, 1, 2, 3, 4}, // R7
+	'{1, 2, 3, 4, 1}, // R8
+	'{2, 3, 4, 1, 2}, // R9
+	'{3, 4, 1, 2, 3}, // R10
+	'{4, 1, 2, 3, 4}, // R11
+	'{1, 2, 3, 4, 1}, // R12
+	'{2, 3, 4, 1, 2}, // R13
+	'{3, 4, 1, 2, 3}, // R14
+	'{1, 2, 3, 4, 1},  // R15
+	'{2, 3, 4, 1, 2}, // R16
+	'{3, 4, 1, 2, 3}, // R17
+	'{4, 1, 2, 3, 4}, // R18
+	'{1, 2, 3, 4, 1}, // R19
+	'{2, 3, 4, 1, 2}, // R20
+	'{3, 4, 1, 2, 3}, // R21
+	'{4, 1, 2, 3, 4}, // R22
+	'{1, 2, 3, 4, 1}, // R23
+	'{2, 3, 4, 1, 2}, // R24
+	'{3, 4, 1, 2, 3}, // R25
+	'{4, 1, 2, 3, 4}, // R26
+	'{1, 2, 3, 4, 1}, // R27
+	'{2, 3, 4, 1, 2}, // R28
+	'{3, 4, 1, 2, 3}, // R29
+	'{1, 2, 3, 4, 1}, // R30
+	'{2, 3, 4, 1, 2}, // R31
+	'{3, 4, 1, 2, 3}, // R32
+	'{4, 1, 2, 3, 4}, // R33
+	'{1, 2, 3, 4, 1}, // R34
+	'{2, 3, 4, 1, 2}, // R35
+	'{3, 4, 1, 2, 3}, // R36
+	'{4, 1, 2, 3, 4}, // R37
+	'{1, 2, 3, 4, 1}, // R38
+	'{2, 3, 4, 1, 2}, // R39
+	'{3, 4, 1, 2, 3}, // R40
+	'{4, 1, 2, 3, 4}, // R41
+	'{1, 2, 3, 4, 1}, // R42
+	'{2, 3, 4, 1, 2}, // R43
+	'{3, 4, 1, 2, 3}, // R44
+	'{1, 2, 3, 4, 1}, // R45
+	'{2, 3, 4, 1, 2}, // R46
+	'{3, 4, 1, 2, 3}, // R47
+	'{4, 1, 2, 3, 4}, // R48
+	'{1, 2, 3, 4, 1}, // R49
+	'{2, 3, 4, 1, 2}, // R50
+	'{3, 4, 1, 2, 3}, // R51
+	'{4, 1, 2, 3, 4}, // R52
+	'{1, 2, 3, 4, 1}, // R53
+	'{2, 3, 4, 1, 2}, // R54
+	'{3, 4, 1, 2, 3}, // R55
+	'{4, 1, 2, 3, 4}, // R56
+	'{1, 2, 3, 4, 1}, // R57
+	'{2, 3, 4, 1, 2}, // R58
+	'{3, 4, 1, 2, 3}, // R59
+	'{1, 2, 3, 4, 1}, // R60
+	'{2, 3, 4, 1, 2}, // R61
+	'{3, 4, 1, 2, 3}, // R62
+	'{4, 1, 2, 3, 4}  // R63
+	}",
+    }
+}, 'ProNOC' );
diff --git a/mpsoc/Integration_test/synthetic_sim/configurations/default/mesh_8x8_b2 b/mpsoc/Integration_test/Questa_lint/configurations/mesh_8x8_b2
similarity index 72%
rename from mpsoc/Integration_test/synthetic_sim/configurations/default/mesh_8x8_b2
rename to mpsoc/Integration_test/Questa_lint/configurations/mesh_8x8_b2
index 8ad895e..166ee7c 100644
--- a/mpsoc/Integration_test/synthetic_sim/configurations/default/mesh_8x8_b2
+++ b/mpsoc/Integration_test/Questa_lint/configurations/mesh_8x8_b2
@@ -1,6 +1,6 @@
 $model = bless( {
     'noc_param'=> {
-        "ROUTE_NAME" => "\"XY\"",
+        "ROUTE_NAME" => "\"DOR\"",
         "B"=> "2",
         "LB"=> 2
     }
diff --git a/mpsoc/Integration_test/synthetic_sim/configurations/default/mesh_8x8_sbp6_xy b/mpsoc/Integration_test/Questa_lint/configurations/mesh_8x8_sbp6_xy
similarity index 100%
rename from mpsoc/Integration_test/synthetic_sim/configurations/default/mesh_8x8_sbp6_xy
rename to mpsoc/Integration_test/Questa_lint/configurations/mesh_8x8_sbp6_xy
diff --git a/mpsoc/Integration_test/synthetic_sim/configurations/default/mesh_8x8_single_flit b/mpsoc/Integration_test/Questa_lint/configurations/mesh_8x8_single_flit
similarity index 100%
rename from mpsoc/Integration_test/synthetic_sim/configurations/default/mesh_8x8_single_flit
rename to mpsoc/Integration_test/Questa_lint/configurations/mesh_8x8_single_flit
diff --git a/mpsoc/Integration_test/synthetic_sim/configurations/default/mesh_8x8_ssa_xy b/mpsoc/Integration_test/Questa_lint/configurations/mesh_8x8_ssa_xy
similarity index 65%
rename from mpsoc/Integration_test/synthetic_sim/configurations/default/mesh_8x8_ssa_xy
rename to mpsoc/Integration_test/Questa_lint/configurations/mesh_8x8_ssa_xy
index 7e36145..02cf843 100644
--- a/mpsoc/Integration_test/synthetic_sim/configurations/default/mesh_8x8_ssa_xy
+++ b/mpsoc/Integration_test/Questa_lint/configurations/mesh_8x8_ssa_xy
@@ -1,5 +1,5 @@
 $model = bless( {
     'noc_param'=> {
-        "SSA_EN" => "\"YES\"",
+        "SSA_EN" => "1",
     }
 }, 'ProNOC' );
\ No newline at end of file
diff --git a/mpsoc/Integration_test/Questa_lint/configurations/ring_8x8_2cycle_xy b/mpsoc/Integration_test/Questa_lint/configurations/ring_8x8_2cycle_xy
new file mode 100644
index 0000000..d47e3d9
--- /dev/null
+++ b/mpsoc/Integration_test/Questa_lint/configurations/ring_8x8_2cycle_xy
@@ -0,0 +1,8 @@
+$model = bless( {
+    'compile' => "verilate_mesh.sh",
+        'noc_param'=> {
+        TOPOLOGY=>"\"RING\"",
+        "TOPOLOGY" => "\"TORUS\"",
+        "ROUTE_NAME" => "\"TRANC_DOR\"",
+    }
+}, 'ProNOC' );
diff --git a/mpsoc/Integration_test/Questa_lint/configurations/star6_2cycle_mcast_par b/mpsoc/Integration_test/Questa_lint/configurations/star6_2cycle_mcast_par
new file mode 100644
index 0000000..3bf044e
--- /dev/null
+++ b/mpsoc/Integration_test/Questa_lint/configurations/star6_2cycle_mcast_par
@@ -0,0 +1,11 @@
+$model = bless( {
+    'noc_param'=> {
+        "TOPOLOGY"=>"\"STAR\"",
+        "ROUTE_NAME" =>"\"UNKNOWN\"",
+        "T1" => "6",
+        "CAST_TYPE" => "\"MULTICAST_PARTIAL\"",
+        "Fpay" => "32",
+        "MCAST_ENDP_LIST" => "'b001011",
+        "SELF_LOOP_EN" => "1"
+    }
+}, 'ProNOC' );
\ No newline at end of file
diff --git a/mpsoc/Integration_test/synthetic_sim/configurations/default/star_6 b/mpsoc/Integration_test/Questa_lint/configurations/star_6
similarity index 100%
rename from mpsoc/Integration_test/synthetic_sim/configurations/default/star_6
rename to mpsoc/Integration_test/Questa_lint/configurations/star_6
diff --git a/mpsoc/Integration_test/synthetic_sim/configurations/default/torus_8x8_2cycle_xy b/mpsoc/Integration_test/Questa_lint/configurations/torus_8x8_2cycle_xy
similarity index 69%
rename from mpsoc/Integration_test/synthetic_sim/configurations/default/torus_8x8_2cycle_xy
rename to mpsoc/Integration_test/Questa_lint/configurations/torus_8x8_2cycle_xy
index 5ade6a7..7d29733 100644
--- a/mpsoc/Integration_test/synthetic_sim/configurations/default/torus_8x8_2cycle_xy
+++ b/mpsoc/Integration_test/Questa_lint/configurations/torus_8x8_2cycle_xy
@@ -1,6 +1,6 @@
 $model = bless( {
     'noc_param'=> {
         "TOPOLOGY" => "\"TORUS\"",
-        "ROUTE_NAME" => "\"TRANC_XY\"",
+        "ROUTE_NAME" => "\"TRANC_DOR\"",
     }
 }, 'ProNOC' );
\ No newline at end of file
diff --git a/mpsoc/Integration_test/Questa_lint/golden_ref/report.txt b/mpsoc/Integration_test/Questa_lint/golden_ref/report.txt
new file mode 100644
index 0000000..35e9951
--- /dev/null
+++ b/mpsoc/Integration_test/Questa_lint/golden_ref/report.txt
@@ -0,0 +1,40 @@
+Configuration                  | # Warnings | # Errors   |
+bintree_k3_L3_st               | 0          | 0          |
+custom1_topology               | 0          | 0          |
+Fattree_k3_L3_st               | 0          | 0          |
+fmesh_1x1_openpiton            | 0          | 0          |
+fmesh_2x2_openpiton            | 0          | 0          |
+fmesh_8x8_2cycle_xy            | 0          | 0          |
+fmesh_8x8_openpiton            | 0          | 0          |
+line4_smart3                   | 0          | 0          |
+line_4_v1_B15                  | 0          | 0          |
+line_8_single_flit             | 1          | 0          |
+mesh_2x2_openpiton             | 0          | 0          |
+mesh_3x3_v2_ssa                | 0          | 0          |
+mesh_4x4_2cycle_mcast_f        | 0          | 0          |
+mesh_4x4_LB5_B4                | 0          | 0          |
+mesh_4x4_selflp_mcast_f        | 0          | 0          |
+mesh_4x4_smart3                | 0          | 0          |
+mesh_4x4_v1_B15                | 0          | 0          |
+mesh_4x4x2_bcast_f             | 0          | 0          |
+mesh_4x4x2_bcast_p             | 0          | 0          |
+mesh_4x4x2_mcast_p             | 0          | 0          |
+mesh_4x4x3_2cycle_xy           | 0          | 0          |
+mesh_4x4x3_vc_nonspec          | 0          | 0          |
+mesh_4x4x3_vc_spec1            | 0          | 0          |
+mesh_4x4x3_vc_spec2            | 0          | 0          |
+mesh_8x8_2cycle_adaptive       | 0          | 0          |
+mesh_8x8_2cycle_west_first     | 0          | 0          |
+mesh_8x8_2cycle_xy             | 0          | 0          |
+mesh_8x8_4vc                   | 0          | 0          |
+mesh_8x8_4vc_4c                | 0          | 0          |
+mesh_8x8_4vc_hetero1           | 0          | 0          |
+mesh_8x8_4vc_hetero2           | 0          | 0          |
+mesh_8x8_b2                    | 0          | 0          |
+mesh_8x8_sbp6_xy               | 0          | 0          |
+mesh_8x8_single_flit           | 1          | 0          |
+mesh_8x8_ssa_xy                | 0          | 0          |
+ring_8x8_2cycle_xy             | 0          | 0          |
+star_6                         | 0          | 0          |
+star6_2cycle_mcast_par         | 0          | 0          |
+torus_8x8_2cycle_xy            | 0          | 0          |
diff --git a/mpsoc/Integration_test/Questa_lint/run.sh b/mpsoc/Integration_test/Questa_lint/run.sh
new file mode 100644
index 0000000..e482435
--- /dev/null
+++ b/mpsoc/Integration_test/Questa_lint/run.sh
@@ -0,0 +1,107 @@
+#!/bin/bash
+
+set -e  # Global: exit on any failure
+
+SCRPT_FULL_PATH=$(realpath "${BASH_SOURCE[0]}")
+SCRPT_DIR_PATH=$(dirname "$SCRPT_FULL_PATH")
+
+# Paths
+conf_dir="${SCRPT_DIR_PATH}/configurations"
+log_dir="${SCRPT_DIR_PATH}/result_logs"
+work="${SCRPT_DIR_PATH}/work"
+file_list_f="${SCRPT_DIR_PATH}/src/file_list.f"
+report_file="${log_dir}/report.txt"
+
+mkdir -p "$work" "$log_dir"
+rm -f "$report_file"
+printf "%-30s | %-10s | %-10s |\n" "Configuration" "# Warnings" "# Errors" >> "$report_file"
+
+# Source the environment variables
+# conf_dir="${SCRPT_DIR_PATH}/conf_small"
+
+questa_lint () {
+    set -e  # Exit on any command failure
+    conf=$1
+    conf_file="${conf_dir}/$conf"
+    log_file="${log_dir}/${conf}.log"
+    rm -f $log_file
+    if [[ ! -f "$conf_file" ]]; then
+        echo "Configuration file $conf_file does not exist" >> $log_file
+        exit 1
+    fi
+
+    perl "${SCRPT_DIR_PATH}/src/param_gen.pl" "$conf_file" >> $log_file
+    export REPORT_FILENAME="${log_dir}/${conf}.txt"
+    export FILE_LIST=$file_list_f
+    
+    # Clean old work library
+    rm -rf work
+    vlib work
+    # Lint the design
+    vlog -sv -lint -f ${file_list_f} >> $log_file
+    vsim -suppress vopt-14408,vsim-16154 -c work.noc_top -do "quit"  >> $log_file
+}
+
+report_total_errors_warnings () {
+    conf="$1"
+    conf_file="${conf_dir}/${conf}"
+    log_file="${log_dir}/${conf}.log"
+    warnings=$(grep '\*\* Warning' "$log_file" | wc -l)
+    errors=$(grep '\*\*\ Error' "$log_file" | wc -l)
+    printf "%-30s | %-10s | %-10s |\n" "$conf" "$warnings" "$errors" >> "$report_file"
+}
+
+
+run_config () {
+    conf="$1"
+    log_file="${log_dir}/${conf}.log"
+    echo "▶️  Compiling configuration: $conf"
+    # Run and redirect stdout/stderr to log file only
+    if ! questa_lint "$conf"; then
+        echo "❌ Compilation failed for $conf (check $log_file)"
+        rm -f "${SCRPT_DIR_PATH}/src/noc_localparam.v"
+        exit 1
+    else
+        echo "✅ Compilation successful for $conf"
+        rm -f "${SCRPT_DIR_PATH}/src/noc_localparam.v"
+        report_total_errors_warnings "$conf"
+    fi
+}
+
+
+# === Main ===
+if [[ "$1" == "-h" || "$1" == "--help" ]]; then
+    echo "Usage: bash run.sh [config_name]"
+    echo
+    echo "If [config_name] is provided, only that configuration will be processed."
+    echo "If no argument is given, all configurations in the 'configurations/' directory will be processed."
+    echo
+    echo "Examples:"
+    echo "  bash run.sh         # Run all configurations"
+    echo "  bash run.sh conf1   # Run only conf1"
+    exit 0
+fi
+
+if [[ $# -eq 1 ]]; then
+    # Run only the specified configuration
+    conf_name="$1"
+    run_config "$conf_name"
+else
+    # Run all configurations
+    for f in "$conf_dir"/*; do
+        [[ -d "$f" ]] && continue
+        conf=$(basename "$f")
+        run_config "$conf"
+    done
+fi
+
+
+echo "Report saved in $report_file"
+echo "Summary:"
+echo "-------------------------------|------------|------------|"
+cat $report_file
+
+echo "Comparing with golden reference..."
+# Compare the results with the golden reference report  
+perl ${SCRPT_DIR_PATH}/../Altera/src/compare.pl   ${SCRPT_DIR_PATH}/golden_ref/report.txt $report_file
+echo "All configurations processed. Results are in $report_file
diff --git a/mpsoc/Integration_test/Questa_lint/src/file_list.f b/mpsoc/Integration_test/Questa_lint/src/file_list.f
new file mode 100644
index 0000000..1f5742d
--- /dev/null
+++ b/mpsoc/Integration_test/Questa_lint/src/file_list.f
@@ -0,0 +1,6 @@
++incdir+./src 
+
+-F ./../../rtl/src_noc/noc_filelist.f
+-F ./../../rtl/src_topology/custom_flist.f
+
+
diff --git a/mpsoc/Integration_test/Questa_lint/src/param_gen.pl b/mpsoc/Integration_test/Questa_lint/src/param_gen.pl
new file mode 100644
index 0000000..1ad4763
--- /dev/null
+++ b/mpsoc/Integration_test/Questa_lint/src/param_gen.pl
@@ -0,0 +1,46 @@
+#!/usr/bin/perl  
+package ProNOC;
+use strict;
+use warnings;
+use File::Basename;
+
+
+#add home dir in perl 5.6
+use FindBin;
+use lib $FindBin::Bin;
+use Cwd qw(realpath);
+
+
+
+
+use File::Path qw(make_path);
+
+
+use strict;
+use warnings;
+
+
+
+
+my $script_path = dirname(__FILE__);
+
+require "$script_path/../../synthetic_sim/src/src.pl";
+use lib "../synthetic_sim/src/perl_lib";
+
+use constant::boolean;
+use base 'Class::Accessor::Fast';
+
+my $conf_file=$ARGV[0];
+
+
+sub create_noc_param_vv {
+    my ($conf_file)=@_;
+    my $o = do $conf_file;
+    die "Could not parse $conf_file: $@" if $@;
+    die "Could not read $conf_file: $!" unless defined $o;
+    my $param = $o->{'noc_param'};
+    my ($param_v,$include_h,$tops)=   gen_noc_localparam_v( $o,$param);
+    save_file("$script_path/noc_localparam.v",$param_v);
+}
+
+create_noc_param_vv ($conf_file);
diff --git a/mpsoc/Integration_test/VCS/Golden_ref/line4_smart3.log b/mpsoc/Integration_test/VCS/Golden_ref/line4_smart3.log
new file mode 100644
index 0000000..a7862c8
--- /dev/null
+++ b/mpsoc/Integration_test/VCS/Golden_ref/line4_smart3.log
@@ -0,0 +1,1694 @@
+Use of uninitialized value $ENV{"PRONOC_WORK"} in concatenation (.) or string at /users/amonemi/ProNoC/mpsoc/Integration_test/VCS/src/../../synthetic_sim/src/src.pl line 24.
+Use of uninitialized value $ENV{"PRONOC_WORK"} in concatenation (.) or string at /users/amonemi/ProNoC/mpsoc/Integration_test/VCS/src/../../synthetic_sim/src/src.pl line 25.
+Use of uninitialized value $ENV{"PRONOC_WORK"} in concatenation (.) or string at /users/amonemi/ProNoC/mpsoc/Integration_test/VCS/src/../../synthetic_sim/src/src.pl line 26.
+Script Path: /users/amonemi/ProNoC/mpsoc/Integration_test/VCS/src/../../synthetic_sim/src
+confs_dir: /users/amonemi/ProNoC/mpsoc/Integration_test/synthetic_sim/configurations
+Root: /users/amonemi/ProNoC/mpsoc
+Parsing design file './../../rtl/src_noc/./pronoc_pkg.sv'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./pronoc_pkg.sv'.
+Parsing included file './src/noc_localparam.v'.
+Back to file './../../rtl/src_noc/./pronoc_pkg.sv'.
+Parsing included file './../../rtl/src_noc/./topology_localparam.v'.
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./topology_localparam.v'.
+Back to file './../../rtl/src_noc/./pronoc_pkg.sv'.
+Parsing design file './../../rtl/src_noc/./../main_comp.v'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./../main_comp.v'.
+Parsing design file './../../rtl/src_noc/./../arbiter.v'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./../arbiter.v'.
+Parsing design file './../../rtl/src_noc/./ovc_list.sv'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./ovc_list.sv'.
+Parsing design file './../../rtl/src_noc/./ss_allocator.sv'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./ss_allocator.sv'.
+Parsing design file './../../rtl/src_noc/./route_torus.v'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./route_torus.v'.
+Parsing design file './../../rtl/src_noc/./header_flit.sv'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./header_flit.sv'.
+Parsing design file './../../rtl/src_noc/./noc_top.sv'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./noc_top.sv'.
+Parsing design file './../../rtl/src_noc/./fattree_noc_top.sv'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./fattree_noc_top.sv'.
+Parsing design file './../../rtl/src_noc/./fattree_route.v'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./fattree_route.v'.
+Parsing design file './../../rtl/src_noc/./comb_nonspec.sv'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./comb_nonspec.sv'.
+Parsing design file './../../rtl/src_noc/./inout_ports.sv'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./inout_ports.sv'.
+Parsing design file './../../rtl/src_noc/./wrra.v'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./wrra.v'.
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./wrra.v'.
+Parsing design file './../../rtl/src_noc/./input_ports.sv'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./input_ports.sv'.
+Parsing design file './../../rtl/src_noc/./tree_noc_top.sv'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./tree_noc_top.sv'.
+Parsing design file './../../rtl/src_noc/./tree_route.v'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./tree_route.v'.
+Parsing design file './../../rtl/src_noc/./comb-spec1.v'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./comb-spec1.v'.
+Parsing design file './../../rtl/src_noc/./combined_vc_sw_alloc.sv'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./combined_vc_sw_alloc.sv'.
+Parsing design file './../../rtl/src_noc/./mesh_torus_routting.v'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./mesh_torus_routting.v'.
+Parsing design file './../../rtl/src_noc/./comb_spec2.v'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./comb_spec2.v'.
+Parsing design file './../../rtl/src_noc/./route_mesh.v'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./route_mesh.v'.
+Parsing design file './../../rtl/src_noc/./router_bypass.sv'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./router_bypass.sv'.
+Parsing design file './../../rtl/src_noc/./traffic_gen_top.sv'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./traffic_gen_top.sv'.
+Parsing design file './../../rtl/src_noc/./congestion_analyzer.v'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./congestion_analyzer.v'.
+Parsing design file './../../rtl/src_noc/./output_ports.sv'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./output_ports.sv'.
+Parsing design file './../../rtl/src_noc/./routing.v'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./routing.v'.
+Parsing design file './../../rtl/src_noc/./router_two_stage.sv'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./router_two_stage.sv'.
+Parsing design file './../../rtl/src_noc/./crossbar.v'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./crossbar.v'.
+Parsing design file './../../rtl/src_noc/./flit_buffer.sv'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./flit_buffer.sv'.
+Parsing design file './../../rtl/src_noc/./mesh_torus.sv'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./mesh_torus.sv'.
+Parsing design file './../../rtl/src_noc/./debug.v'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./debug.v'.
+Parsing design file './../../rtl/src_noc/./router_top.sv'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./router_top.sv'.
+Parsing design file './../../rtl/src_noc/./mesh_torus_noc_top.sv'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./mesh_torus_noc_top.sv'.
+Parsing design file './../../rtl/src_noc/./star_noc.sv'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./star_noc.sv'.
+Parsing design file './../../rtl/src_noc/./fmesh.sv'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./fmesh.sv'.
+Parsing design file './../../rtl/src_noc/./packet_injector.sv'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./packet_injector.sv'.
+Parsing design file './../../rtl/src_noc/./multicast.sv'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./multicast.sv'.
+Parsing design file './../../rtl/src_topology/./custom1/Tcustom1Rcustom_look_ahead_routing_genvar.v'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_topology/./custom1/Tcustom1Rcustom_look_ahead_routing_genvar.v'.
+Parsing design file './../../rtl/src_topology/./custom1/custom1_noc_genvar.sv'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_topology/./custom1/custom1_noc_genvar.sv'.
+Parsing design file './../../rtl/src_topology/./custom1/Tcustom1Rcustom_conventional_routing_genvar.v'
+Parsing design file './../../rtl/src_topology/./custom1/custom1_noc.sv'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_topology/./custom1/custom1_noc.sv'.
+Parsing design file './../../rtl/src_topology/./custom1/Tcustom1Rcustom_conventional_routing.v'
+Parsing design file './../../rtl/src_topology/./custom1/Tcustom1Rcustom_look_ahead_routing.v'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_topology/./custom1/Tcustom1Rcustom_look_ahead_routing.v'.
+Parsing design file './../../rtl/src_topology/./common/custom_ni_routing.v'
+Parsing design file './../../rtl/src_topology/./common/custom_noc_top.sv'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_topology/./common/custom_noc_top.sv'.
+Parsing design file './../../rtl/src_topology/./common/custom_lkh_routing.v'
+Top Level Modules:
+       noc_top
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./topology_localparam.v, 16
+pronoc_pkg, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./topology_localparam.v, 17
+pronoc_pkg, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./topology_localparam.v, 18
+pronoc_pkg, "(TOPOLOGY == "FATTREE")"
+  A left 32-bit expression is compared to a right 56-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FATTREE"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./topology_localparam.v, 21
+pronoc_pkg, "(TOPOLOGY == "MULTI_MESH")"
+  A left 32-bit expression is compared to a right 80-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"MULTI_MESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./topology_localparam.v, 27
+pronoc_pkg, "(SWA_ARBITER_TYPE == "WRRA")"
+  A left 24-bit expression is compared to a right 32-bit expression.
+  Comparing 'SWA_ARBITER_TYPE' of type string
+  with '"WRRA"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./topology_localparam.v, 28
+pronoc_pkg, "(PCK_TYPE == "SINGLE_FLIT")"
+  A left 80-bit expression is compared to a right 88-bit expression.
+  Comparing 'PCK_TYPE' of type string
+  with '"SINGLE_FLIT"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./topology_localparam.v, 143
+pronoc_pkg, "(ROUTE_NAME == "TRANC_DOR")"
+  A left 16-bit expression is compared to a right 64-bit expression.
+  Comparing 'ROUTE_NAME' of type string
+  with '"TRANC_DOR"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./topology_localparam.v, 143
+pronoc_pkg, "(ROUTE_NAME == "FULL_ADPT")"
+  A left 16-bit expression is compared to a right 40-bit expression.
+  Comparing 'ROUTE_NAME' of type string
+  with '"FULL_ADPT"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./topology_localparam.v, 143
+pronoc_pkg, "(ROUTE_NAME == "TRANC_FULL_ADPT")"
+  A left 16-bit expression is compared to a right 88-bit expression.
+  Comparing 'ROUTE_NAME' of type string
+  with '"TRANC_FULL_ADPT"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./topology_localparam.v, 296
+pronoc_pkg, "(CAST_TYPE == "MULTICAST_FULL")"
+  A left 56-bit expression is compared to a right 112-bit expression.
+  Comparing 'CAST_TYPE' of type string
+  with '"MULTICAST_FULL"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./topology_localparam.v, 296
+pronoc_pkg, "(CAST_TYPE == "MULTICAST_PARTIAL")"
+  A left 56-bit expression is compared to a right 136-bit expression.
+  Comparing 'CAST_TYPE' of type string
+  with '"MULTICAST_PARTIAL"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./topology_localparam.v, 296
+pronoc_pkg, "(CAST_TYPE == "MULTICAST_PARTIAL")"
+  A left 56-bit expression is compared to a right 136-bit expression.
+  Comparing 'CAST_TYPE' of type string
+  with '"MULTICAST_PARTIAL"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./output_ports.sv, 128
+output_ports, "(pronoc_pkg::VC_REALLOCATION_TYPE == "ATOMIC")"
+  A left 72-bit expression is compared to a right 48-bit expression.
+  Comparing 'pronoc_pkg::VC_REALLOCATION_TYPE' of type string
+  with '"ATOMIC"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./combined_vc_sw_alloc.sv, 131
+combined_vc_sw_alloc, "(pronoc_pkg::COMBINATION_TYPE == "COMB_SPEC1")"
+  A left 96-bit expression is compared to a right 80-bit expression.
+  Comparing 'pronoc_pkg::COMBINATION_TYPE' of type string
+  with '"COMB_SPEC1"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./combined_vc_sw_alloc.sv, 167
+combined_vc_sw_alloc, "(pronoc_pkg::COMBINATION_TYPE == "COMB_SPEC2")"
+  A left 96-bit expression is compared to a right 80-bit expression.
+  Comparing 'pronoc_pkg::COMBINATION_TYPE' of type string
+  with '"COMB_SPEC2"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./crossbar.v, 115
+crossbar, "(MUX_TYPE == "ONE_HOT")"
+  A left 48-bit expression is compared to a right 56-bit expression.
+  Comparing 'MUX_TYPE' of type string
+  with '"ONE_HOT"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./crossbar.v, 115
+crossbar, "(MUX_TYPE == "ONE_HOT")"
+  A left 48-bit expression is compared to a right 56-bit expression.
+  Comparing 'MUX_TYPE' of type string
+  with '"ONE_HOT"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./crossbar.v, 115
+crossbar, "(MUX_TYPE == "ONE_HOT")"
+  A left 48-bit expression is compared to a right 56-bit expression.
+  Comparing 'MUX_TYPE' of type string
+  with '"ONE_HOT"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./input_ports.sv, 241
+input_queue_per_port, "(pronoc_pkg::VC_REALLOCATION_TYPE == "ATOMIC")"
+  A left 72-bit expression is compared to a right 48-bit expression.
+  Comparing 'pronoc_pkg::VC_REALLOCATION_TYPE' of type string
+  with '"ATOMIC"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./input_ports.sv, 241
+input_queue_per_port, "(pronoc_pkg::VC_REALLOCATION_TYPE == "ATOMIC")"
+  A left 72-bit expression is compared to a right 48-bit expression.
+  Comparing 'pronoc_pkg::VC_REALLOCATION_TYPE' of type string
+  with '"ATOMIC"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./routing.v, 69
+conventional_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./routing.v, 69
+conventional_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./routing.v, 96
+conventional_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./input_ports.sv, 406
+input_queue_per_port, "(pronoc_pkg::TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'pronoc_pkg::TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./input_ports.sv, 423
+input_queue_per_port, "(pronoc_pkg::TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'pronoc_pkg::TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./input_ports.sv, 441
+input_queue_per_port, "(pronoc_pkg::TOPOLOGY == "FATTREE")"
+  A left 32-bit expression is compared to a right 56-bit expression.
+  Comparing 'pronoc_pkg::TOPOLOGY' of type string
+  with '"FATTREE"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./input_ports.sv, 441
+input_queue_per_port, "(pronoc_pkg::ROUTE_NAME == "NCA_STRAIGHT_UP")"
+  A left 16-bit expression is compared to a right 120-bit expression.
+  Comparing 'pronoc_pkg::ROUTE_NAME' of type string
+  with '"NCA_STRAIGHT_UP"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./input_ports.sv, 800
+input_queue_per_port, "(pronoc_pkg::TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'pronoc_pkg::TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./input_ports.sv, 821
+input_queue_per_port, "(pronoc_pkg::TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'pronoc_pkg::TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./input_ports.sv, 1026
+input_queue_per_port, "(pronoc_pkg::TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'pronoc_pkg::TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 638
+mesh_torus_conventional_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 727
+mesh_torus_conventional_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./input_ports.sv, 1138
+destp_generator, "(TOPOLOGY == "FATTREE")"
+  A left 32-bit expression is compared to a right 56-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FATTREE"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./input_ports.sv, 1166
+destp_generator, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./routing.v, 287
+look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./routing.v, 287
+look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./routing.v, 314
+look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./routing.v, 287
+look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./routing.v, 287
+look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./routing.v, 314
+look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./routing.v, 287
+look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./routing.v, 287
+look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./routing.v, 314
+look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./comb_nonspec.sv, 721
+swa_output_port_arbiter, "(ARBITER_TYPE == "WRRA")"
+  A left 24-bit expression is compared to a right 32-bit expression.
+  Comparing 'ARBITER_TYPE' of type string
+  with '"WRRA"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./comb_nonspec.sv, 747
+swa_output_port_arbiter, "(ARBITER_TYPE == "WRRA_CLASSIC")"
+  A left 24-bit expression is compared to a right 96-bit expression.
+  Comparing 'ARBITER_TYPE' of type string
+  with '"WRRA_CLASSIC"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 146
+mesh_torus_deterministic_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 146
+mesh_torus_deterministic_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 368
+mesh_torus_next_router_addr_predictor, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 368
+mesh_torus_next_router_addr_predictor, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+TimeScale is 1 ns / 1 ps
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./topology_localparam.v, 466
+pronoc_pkg, "(CAST_TYPE == "MULTICAST_PARTIAL")"
+  A left 56-bit expression is compared to a right 136-bit expression.
+  Comparing 'CAST_TYPE' of type string
+  with '"MULTICAST_PARTIAL"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./topology_localparam.v, 466
+pronoc_pkg, "(CAST_TYPE == "BROADCAST_PARTIAL")"
+  A left 56-bit expression is compared to a right 136-bit expression.
+  Comparing 'CAST_TYPE' of type string
+  with '"BROADCAST_PARTIAL"' of type string.
+
+
+Lint-[WMIA-L] Width mismatch in assignment
+./../../rtl/src_noc/./topology_localparam.v, 328
+  Width mismatch between LHS and RHS is found in assignment:
+  The following 32-bit wide expression is assigned to a 4-bit LHS target:
+  Source info: mcast_list = MCAST_ENDP_LIST;
+  Expression: mcast_list
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./topology_localparam.v, 332
+pronoc_pkg, "(CAST_TYPE == "MULTICAST_FULL")"
+  A left 56-bit expression is compared to a right 112-bit expression.
+  Comparing 'CAST_TYPE' of type string
+  with '"MULTICAST_FULL"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./topology_localparam.v, 352
+pronoc_pkg, "(CAST_TYPE == "MULTICAST_FULL")"
+  A left 56-bit expression is compared to a right 112-bit expression.
+  Comparing 'CAST_TYPE' of type string
+  with '"MULTICAST_FULL"' of type string.
+
+
+Lint-[WMIA-L] Width mismatch in assignment
+./../../rtl/src_noc/./topology_localparam.v, 356
+  Width mismatch between LHS and RHS is found in assignment:
+  The following 32-bit wide expression is assigned to a 4-bit LHS target:
+  Source info: mcast_list = MCAST_ENDP_LIST;
+  Expression: mcast_list
+
+
+Lint-[WMIA-L] Width mismatch in assignment
+./../../rtl/src_noc/./pronoc_pkg.sv, 300
+  Width mismatch between LHS and RHS is found in assignment:
+  The following 32-bit wide expression is assigned to a 1-bit LHS target:
+  Source info: hetero_ovc_unary = ((HETERO_VC == 0) ? {V {1'b1}} : ((HETERO_VC
+  == 1) ? ((1 << VC_CONFIG_TABLE[router_id][0]) - 1) : ((1 << 
+  VC_CONFIG_TABLE[router_id][router_ ...
+  Expression: hetero_ovc_unary
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./router_bypass.sv, 175
+  Following is an unused input.
+  Source info: reset
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./output_ports.sv, 555
+  Following is an unused input.
+  Source info: ssa_granted_ovc_num
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./router_two_stage.sv, 675
+credit_release_gen, "(counter == CREDIT_NUM)"
+  A left 5-bit expression is compared to a right 32-bit expression.
+  Comparing 'counter' of type reg [(W - 1):0]
+  with 'CREDIT_NUM' of type int.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./debug.v, 64
+check_flit_chanel_type_is_in_order, "(PCK_TYPE == "SINGLE_FLIT")"
+  A left 80-bit expression is compared to a right 88-bit expression.
+  Comparing 'PCK_TYPE' of type string
+  with '"SINGLE_FLIT"' of type string.
+
+
+Lint-[CAWM-L] Width mismatch
+./../../rtl/src_noc/./debug.v, 33
+  Continuous assignment width mismatch
+  1 bits (lhs) versus 32 bits (rhs).
+  Source info: assign vc_num_hdr_wr = ((hdr_flg_in & flit_in_wr) ? vc_num_in :
+  0);  
+
+
+Lint-[CAWM-L] Width mismatch
+./../../rtl/src_noc/./debug.v, 34
+  Continuous assignment width mismatch
+  1 bits (lhs) versus 32 bits (rhs).
+  Source info: assign vc_num_tail_wr = ((tail_flg_in & flit_in_wr) ? vc_num_in
+  : 0);  
+
+
+Lint-[CAWM-L] Width mismatch
+./../../rtl/src_noc/./debug.v, 35
+  Continuous assignment width mismatch
+  1 bits (lhs) versus 32 bits (rhs).
+  Source info: assign vc_num_bdy_wr = ((({hdr_flg_in, tail_flg_in} == 2'b0) &&
+  flit_in_wr) ? vc_num_in : 0);  
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 83
+"router_chan_out[(0 - 1)][pronoc_pkg::FORWARD]"
+  The select index is out of declared bounds : [3:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 79
+"router_chan_out[(3 + 1)][pronoc_pkg::BACKWARD]"
+  The select index is out of declared bounds : [3:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./inout_ports.sv, 116
+  Following is an unused input.
+  Source info: spec_ovc_num_all
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./inout_ports.sv, 118
+  Following is an unused input.
+  Source info: spec_first_arbiter_granted_ivc_all
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./inout_ports.sv, 120
+  Following is an unused input.
+  Source info: spec_granted_dest_port_all
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./output_ports.sv, 88
+  Following is an unused input.
+  Source info: crossbar_flit_out_wr_all
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./congestion_analyzer.v, 351
+  Following is an unused input.
+  Source info: ovc_status
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./congestion_analyzer.v, 352
+  Following is an unused input.
+  Source info: ovc_avalable_all
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./congestion_analyzer.v, 353
+  Following is an unused input.
+  Source info: credit_decreased_all
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./congestion_analyzer.v, 354
+  Following is an unused input.
+  Source info: credit_increased_all
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./congestion_analyzer.v, 355
+  Following is an unused input.
+  Source info: congestion_in_all
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./congestion_analyzer.v, 356
+  Following is an unused input.
+  Source info: reset
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./congestion_analyzer.v, 356
+  Following is an unused input.
+  Source info: clk
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./inout_ports.sv, 464
+  Following is an unused input.
+  Source info: port_pre_sel
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./inout_ports.sv, 467
+  Following is an unused input.
+  Source info: reset
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./inout_ports.sv, 468
+  Following is an unused input.
+  Source info: clk
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./inout_ports.sv, 471
+  Following is an unused input.
+  Source info: ivc_num_getting_ovc_grant
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./congestion_analyzer.v, 965
+  Following is an unused input.
+  Source info: ovc_avalable_all
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./congestion_analyzer.v, 966
+  Following is an unused input.
+  Source info: ivc_request_all
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./congestion_analyzer.v, 967
+  Following is an unused input.
+  Source info: ivc_num_getting_sw_grant
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./router_bypass.sv, 329
+  Following is an unused input.
+  Source info: reset
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./router_bypass.sv, 329
+  Following is an unused input.
+  Source info: clk
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./routing.v, 61
+  Following is an unused input.
+  Source info: reset
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./routing.v, 61
+  Following is an unused input.
+  Source info: clk
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./routing.v, 63
+  Following is an unused input.
+  Source info: src_e_addr
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./debug.v, 560
+  Following is an unused input.
+  Source info: dest_e_addr_in
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./debug.v, 574
+check_pck_size, "(vc_num_in == i)"
+  A left 1-bit expression is compared to a right 32-bit expression.
+  Comparing 'vc_num_in' of type wire [(V - 1):0]
+  with 'i' of type integer.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./debug.v, 574
+check_pck_size, "(vc_num_in == 0)"
+  A left 1-bit expression is compared to a right 32-bit expression.
+  Comparing 'vc_num_in' of type wire [(V - 1):0]
+  with '0' of type int.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./debug.v, 590
+check_pck_size, "(vc_num_in == 0)"
+  A left 1-bit expression is compared to a right 32-bit expression.
+  Comparing 'vc_num_in' of type wire [(V - 1):0]
+  with '0' of type int.
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./input_ports.sv, 273
+  Following is an unused input.
+  Source info: refresh_w_counter
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./input_ports.sv, 274
+  Following is an unused input.
+  Source info: granted_dest_port
+
+
+Lint-[WMIA-L] Width mismatch in assignment
+./../../rtl/src_noc/./input_ports.sv, 379
+  Width mismatch between LHS and RHS is found in assignment:
+  The following 32-bit wide expression is assigned to a 4-bit LHS target:
+  Source info: iport_weight_next = ((weight_in == {pronoc_pkg::WEIGHTw 
+  {1'b0}}) ? 1 : weight_in);
+  Expression: iport_weight_next
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./flit_buffer.sv, 80
+  Following is an unused input.
+  Source info: multiple_dest
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./flit_buffer.sv, 81
+  Following is an unused input.
+  Source info: sub_rd_ptr_ld
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./flit_buffer.sv, 80
+  Following is an unused input.
+  Source info: multiple_dest
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./flit_buffer.sv, 81
+  Following is an unused input.
+  Source info: sub_rd_ptr_ld
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./header_flit.sv, 222
+  Following is an unused input.
+  Source info: sel
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./header_flit.sv, 223
+  Following is an unused input.
+  Source info: any_ivc_sw_request_granted
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./header_flit.sv, 224
+  Following is an unused input.
+  Source info: lk_dest_not_registered
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./output_ports.sv, 639
+  Following is an unused input.
+  Source info: reset
+
+
+Lint-[CAWM-L] Width mismatch
+./../../rtl/src_noc/./output_ports.sv, 648
+  Continuous assignment width mismatch
+  1 bits (lhs) versus 32 bits (rhs).
+  Source info: assign assigned_ovc_num[0] = (ovc_is_assigned_all[0] ? 
+  assigned_ovc_num_all[(((0 + 1) * V) - 1):(0 * V)] : 0);  
+
+
+Lint-[CAWM-L] Width mismatch
+./../../rtl/src_noc/./output_ports.sv, 648
+  Continuous assignment width mismatch
+  1 bits (lhs) versus 32 bits (rhs).
+  Source info: assign assigned_ovc_num[1] = (ovc_is_assigned_all[1] ? 
+  assigned_ovc_num_all[(((1 + 1) * V) - 1):(1 * V)] : 0);  
+
+
+Lint-[CAWM-L] Width mismatch
+./../../rtl/src_noc/./output_ports.sv, 648
+  Continuous assignment width mismatch
+  1 bits (lhs) versus 32 bits (rhs).
+  Source info: assign assigned_ovc_num[2] = (ovc_is_assigned_all[2] ? 
+  assigned_ovc_num_all[(((2 + 1) * V) - 1):(2 * V)] : 0);  
+
+
+Lint-[WMIA-L] Width mismatch in assignment
+./../../rtl/src_noc/./../main_comp.v, 378
+  Width mismatch between LHS and RHS is found in assignment:
+  The following 32-bit wide expression is assigned to a 3-bit LHS target:
+  Source info: sum = 0;
+  Expression: sum
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./comb_nonspec.sv, 460
+  Following is an unused input.
+  Source info: pck_is_single_flit_all
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./mesh_torus_routting.v, 631
+  Following is an unused input.
+  Source info: current_y
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./mesh_torus_routting.v, 633
+  Following is an unused input.
+  Source info: dest_y
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./../main_comp.v, 259
+  Following is an unused input.
+  Source info: one_hot_code
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./flit_buffer.sv, 680
+fwft_fifo, "(IGNORE_SAME_LOC_RD_WR_WARNING == "NO")"
+  A left 24-bit expression is compared to a right 16-bit expression.
+  Comparing 'IGNORE_SAME_LOC_RD_WR_WARNING' of type string
+  with '"NO"' of type string.
+
+
+Lint-[CAWM-L] Width mismatch
+./../../rtl/src_noc/./flit_buffer.sv, 631
+  Continuous assignment width mismatch
+  4 bits (lhs) versus 32 bits (rhs).
+  Source info: assign mwb2.depth_2 = (depth - 2);  
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./routing.v, 276
+  Following is an unused input.
+  Source info: neighbors_r_addr
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./routing.v, 279
+  Following is an unused input.
+  Source info: src_e_addr
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./routing.v, 276
+  Following is an unused input.
+  Source info: neighbors_r_addr
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./routing.v, 279
+  Following is an unused input.
+  Source info: src_e_addr
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./routing.v, 276
+  Following is an unused input.
+  Source info: neighbors_r_addr
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./routing.v, 279
+  Following is an unused input.
+  Source info: src_e_addr
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./debug.v, 116
+  Following is an unused input.
+  Source info: reset
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./debug.v, 118
+  Following is an unused input.
+  Source info: vc_num_in
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./debug.v, 118
+  Following is an unused input.
+  Source info: flit_is_tail
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./debug.v, 118
+  Following is an unused input.
+  Source info: ivc_num_getting_sw_grant
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./../arbiter.v, 49
+  Following is an unused input.
+  Source info: clk
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./../arbiter.v, 50
+  Following is an unused input.
+  Source info: reset
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./comb_nonspec.sv, 634
+  Following is an unused input.
+  Source info: vc_weight_is_consumed
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./comb_nonspec.sv, 717
+  Following is an unused input.
+  Source info: weight_consumed
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./mesh_torus.sv, 1137
+  Following is an unused input.
+  Source info: swap_port_presel
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./mesh_torus.sv, 1138
+  Following is an unused input.
+  Source info: port_pre_sel
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./mesh_torus.sv, 324
+  Following is an unused input.
+  Source info: odd_column
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./../arbiter.v, 101
+  Following is an unused input.
+  Source info: clk
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./../arbiter.v, 102
+  Following is an unused input.
+  Source info: reset
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./../arbiter.v, 103
+  Following is an unused input.
+  Source info: priority_en
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./mesh_torus.sv, 1306
+  Following is an unused input.
+  Source info: endp_localp_num
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./mesh_torus_routting.v, 362
+  Following is an unused input.
+  Source info: current_y
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./input_ports.sv, 273
+  Following is an unused input.
+  Source info: refresh_w_counter
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./input_ports.sv, 274
+  Following is an unused input.
+  Source info: granted_dest_port
+
+
+Lint-[WMIA-L] Width mismatch in assignment
+./../../rtl/src_noc/./input_ports.sv, 379
+  Width mismatch between LHS and RHS is found in assignment:
+  The following 32-bit wide expression is assigned to a 4-bit LHS target:
+  Source info: iport_weight_next = ((weight_in == {pronoc_pkg::WEIGHTw 
+  {1'b0}}) ? 1 : weight_in);
+  Expression: iport_weight_next
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./input_ports.sv, 273
+  Following is an unused input.
+  Source info: refresh_w_counter
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./input_ports.sv, 274
+  Following is an unused input.
+  Source info: granted_dest_port
+
+
+Lint-[WMIA-L] Width mismatch in assignment
+./../../rtl/src_noc/./input_ports.sv, 379
+  Width mismatch between LHS and RHS is found in assignment:
+  The following 32-bit wide expression is assigned to a 4-bit LHS target:
+  Source info: iport_weight_next = ((weight_in == {pronoc_pkg::WEIGHTw 
+  {1'b0}}) ? 1 : weight_in);
+  Expression: iport_weight_next
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./mesh_torus_routting.v, 631
+  Following is an unused input.
+  Source info: current_y
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./mesh_torus_routting.v, 633
+  Following is an unused input.
+  Source info: dest_y
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./flit_buffer.sv, 680
+fwft_fifo, "(IGNORE_SAME_LOC_RD_WR_WARNING == "NO")"
+  A left 24-bit expression is compared to a right 16-bit expression.
+  Comparing 'IGNORE_SAME_LOC_RD_WR_WARNING' of type string
+  with '"NO"' of type string.
+
+
+Lint-[CAWM-L] Width mismatch
+./../../rtl/src_noc/./flit_buffer.sv, 631
+  Continuous assignment width mismatch
+  2 bits (lhs) versus 32 bits (rhs).
+  Source info: assign mwb2.depth_2 = (depth - 2);  
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./mesh_torus.sv, 1137
+  Following is an unused input.
+  Source info: swap_port_presel
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./mesh_torus.sv, 1138
+  Following is an unused input.
+  Source info: port_pre_sel
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./mesh_torus.sv, 1137
+  Following is an unused input.
+  Source info: swap_port_presel
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./mesh_torus.sv, 1138
+  Following is an unused input.
+  Source info: port_pre_sel
+
+Starting vcs inline pass...
+
+43 modules and 0 UDP read.
+Generating code for _VCSgd_reYIK
+Generating code for _VCSgd_bQrwm
+recompiling package pronoc_pkg
+Generating code for _VCSgd_UU20K
+recompiling module pronoc_register
+Generating code for _VCSgd_Afg9y
+Generating code for _VCSgd_dP5iL
+Generating code for _VCSgd_sGFGA
+recompiling module one_hot_demux
+Generating code for _VCSgd_PFE93
+recompiling module custom_or
+Generating code for _VCSgd_rxxii
+recompiling module one_hot_to_bin
+Generating code for _VCSgd_z7NBD
+recompiling module binary_mux
+Generating code for _VCSgd_VK6Ru
+recompiling module accumulator
+Generating code for _VCSgd_jLwrn
+recompiling module extract_header_flit_info
+Generating code for _VCSgd_Ly3qd
+recompiling module header_flit_update_lk_route_ovc
+Generating code for _VCSgd_ECtRV
+recompiling module noc_top
+Generating code for _VCSgd_qubHr
+recompiling module comb_nonspec_allocator
+Generating code for _VCSgd_wLDGV
+recompiling module swa_output_port_arbiter
+Generating code for _VCSgd_AW5ic
+recompiling module inout_ports
+Generating code for _VCSgd_xNBkF
+recompiling module vc_alloc_request_gen
+Generating code for _VCSgd_bzyYs
+recompiling module input_ports
+Generating code for _VCSgd_at0sD
+recompiling module input_queue_per_port
+Generating code for _VCSgd_vPvg3
+Generating code for _VCSgd_TypBP
+Generating code for _VCSgd_pnIHZ
+recompiling module combined_vc_sw_alloc
+Generating code for _VCSgd_L5RSt
+recompiling module mesh_torus_look_ahead_routing
+Generating code for _VCSgd_sa7gf
+recompiling module reduction_or
+Generating code for _VCSgd_msGQv
+recompiling module onehot_mux_2D
+Generating code for _VCSgd_wje7W
+recompiling module onehot_mux_1D
+Generating code for _VCSgd_etkVB
+Generating code for _VCSgd_ER2NJ
+Generating code for _VCSgd_UfJB9
+recompiling module header_flit_info
+Generating code for _VCSgd_Qu4wI
+recompiling module smart_chanel_check
+Generating code for _VCSgd_PggHf
+recompiling module smart_forward_ivc_info
+Generating code for _VCSgd_mJ8QU
+recompiling module smart_bypass_chanels
+Generating code for _VCSgd_SEDnz
+recompiling module smart_validity_check_per_ivc
+Generating code for _VCSgd_zs0vT
+recompiling module smart_allocator_per_iport
+Generating code for _VCSgd_g0Zy4
+Generating code for _VCSgd_D8VMz
+recompiling module smart_credit_manage
+Generating code for _VCSgd_InS4s
+recompiling module output_ports
+Generating code for _VCSgd_pAQwF
+recompiling module credit_monitor_per_ovc
+Generating code for _VCSgd_UPPPJ
+recompiling module oport_ovc_sig_gen
+Generating code for _VCSgd_iMQv0
+recompiling module full_ovc_predictor
+Generating code for _VCSgd_QrHZM
+recompiling module conventional_routing
+Generating code for _VCSgd_Nx31A
+recompiling module router_two_stage
+Generating code for _VCSgd_QCD2e
+recompiling module credit_release_gen
+Generating code for _VCSgd_yaiFc
+recompiling module flit_buffer
+Generating code for _VCSgd_bcmYE
+recompiling module fwft_fifo
+Generating code for _VCSgd_JPLQY
+Generating code for _VCSgd_uCyx2
+recompiling module mesh_tori_endp_addr_decode
+Generating code for _VCSgd_YhjUR
+recompiling module check_flit_chanel_type_is_in_order
+Generating code for _VCSgd_fH8fL
+recompiling module debug_mesh_tori_route_ckeck
+Generating code for _VCSgd_C3wbF
+recompiling module check_pck_size
+Generating code for _VCSgd_sIT4b
+recompiling module router_top
+Generating code for _VCSgd_J4kZy
+recompiling module mesh_torus_noc_top
+All of 43 modules done
+make: Warning: File 'filelist.hsopt.llvm2_0.objs' has modification time 55 s in the future
+make: warning:  Clock skew detected.  Your build may be incomplete.
+make: Warning: File 'filelist.cu' has modification time 47 s in the future
+make[1]: Warning: File 'filelist.cu' has modification time 47 s in the future
+rm -f _cuarc*.so _csrc*.so pre_vcsobj_*.so share_vcsobj_*.so
+make[1]: warning:  Clock skew detected.  Your build may be incomplete.
+make[1]: Warning: File 'filelist.cu' has modification time 47 s in the future
+make[1]: warning:  Clock skew detected.  Your build may be incomplete.
+if [ -x /users/amonemi/ProNoC/mpsoc/Integration_test/VCS/result_logs/work/simv ]; then chmod a-x /users/amonemi/ProNoC/mpsoc/Integration_test/VCS/result_logs/work/simv; fi
+g++  -o /users/amonemi/ProNoC/mpsoc/Integration_test/VCS/result_logs/work/simv   -no-pie    -rdynamic  -Wl,-rpath='$ORIGIN'/simv.daidir -Wl,-rpath=./simv.daidir -Wl,-rpath=/eda/synopsys/2022-23/RHELx86/VCS_2022.06-SP2/linux64/lib -L/eda/synopsys/2022-23/RHELx86/VCS_2022.06-SP2/linux64/lib  -Wl,-rpath-link=./ -Wl,--no-as-needed   objs/amcQw_d.o   _1494812_archive_1.so _prev_archive_1.so  SIM_l.o       rmapats_mop.o rmapats.o rmar.o rmar_nd.o  rmar_llvm_0_1.o rmar_llvm_0_0.o            -lnuma -lvirsim -lerrorinf -lsnpsmalloc -lvfs    -lvcsnew -lsimprofile -luclinative /eda/synopsys/2022-23/RHELx86/VCS_2022.06-SP2/linux64/lib/vcs_tls.o   -Wl,-whole-archive  -lvcsucli    -Wl,-no-whole-archive        _vcs_pli_stub_.o   /eda/synopsys/2022-23/RHELx86/VCS_2022.06-SP2/linux64/lib/vcs_save_restore_new.o /eda/synopsys/2022-23/RHELx86/VERDI_2022.06-SP2/share/PLI/VCS/LINUX64/pli.a -ldl  -lc -lm -lpthread -ldl 
+/users/amonemi/ProNoC/mpsoc/Integration_test/VCS/result_logs/work/simv up to date
+make: warning:  Clock skew detected.  Your build may be incomplete.
+Verdi KDB elaboration done and the database successfully generated: 0 error(s), 0 warning(s)
diff --git a/mpsoc/Integration_test/VCS/Golden_ref/mesh_3x3_v2_ssa.log b/mpsoc/Integration_test/VCS/Golden_ref/mesh_3x3_v2_ssa.log
new file mode 100644
index 0000000..2733830
--- /dev/null
+++ b/mpsoc/Integration_test/VCS/Golden_ref/mesh_3x3_v2_ssa.log
@@ -0,0 +1,2322 @@
+Use of uninitialized value $ENV{"PRONOC_WORK"} in concatenation (.) or string at /users/amonemi/ProNoC/mpsoc/Integration_test/VCS/src/../../synthetic_sim/src/src.pl line 24.
+Use of uninitialized value $ENV{"PRONOC_WORK"} in concatenation (.) or string at /users/amonemi/ProNoC/mpsoc/Integration_test/VCS/src/../../synthetic_sim/src/src.pl line 25.
+Use of uninitialized value $ENV{"PRONOC_WORK"} in concatenation (.) or string at /users/amonemi/ProNoC/mpsoc/Integration_test/VCS/src/../../synthetic_sim/src/src.pl line 26.
+Script Path: /users/amonemi/ProNoC/mpsoc/Integration_test/VCS/src/../../synthetic_sim/src
+confs_dir: /users/amonemi/ProNoC/mpsoc/Integration_test/synthetic_sim/configurations
+Root: /users/amonemi/ProNoC/mpsoc
+Parsing design file './../../rtl/src_noc/./pronoc_pkg.sv'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./pronoc_pkg.sv'.
+Parsing included file './src/noc_localparam.v'.
+Back to file './../../rtl/src_noc/./pronoc_pkg.sv'.
+Parsing included file './../../rtl/src_noc/./topology_localparam.v'.
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./topology_localparam.v'.
+Back to file './../../rtl/src_noc/./pronoc_pkg.sv'.
+Parsing design file './../../rtl/src_noc/./../main_comp.v'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./../main_comp.v'.
+Parsing design file './../../rtl/src_noc/./../arbiter.v'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./../arbiter.v'.
+Parsing design file './../../rtl/src_noc/./ovc_list.sv'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./ovc_list.sv'.
+Parsing design file './../../rtl/src_noc/./ss_allocator.sv'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./ss_allocator.sv'.
+Parsing design file './../../rtl/src_noc/./route_torus.v'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./route_torus.v'.
+Parsing design file './../../rtl/src_noc/./header_flit.sv'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./header_flit.sv'.
+Parsing design file './../../rtl/src_noc/./noc_top.sv'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./noc_top.sv'.
+Parsing design file './../../rtl/src_noc/./fattree_noc_top.sv'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./fattree_noc_top.sv'.
+Parsing design file './../../rtl/src_noc/./fattree_route.v'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./fattree_route.v'.
+Parsing design file './../../rtl/src_noc/./comb_nonspec.sv'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./comb_nonspec.sv'.
+Parsing design file './../../rtl/src_noc/./inout_ports.sv'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./inout_ports.sv'.
+Parsing design file './../../rtl/src_noc/./wrra.v'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./wrra.v'.
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./wrra.v'.
+Parsing design file './../../rtl/src_noc/./input_ports.sv'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./input_ports.sv'.
+Parsing design file './../../rtl/src_noc/./tree_noc_top.sv'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./tree_noc_top.sv'.
+Parsing design file './../../rtl/src_noc/./tree_route.v'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./tree_route.v'.
+Parsing design file './../../rtl/src_noc/./comb-spec1.v'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./comb-spec1.v'.
+Parsing design file './../../rtl/src_noc/./combined_vc_sw_alloc.sv'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./combined_vc_sw_alloc.sv'.
+Parsing design file './../../rtl/src_noc/./mesh_torus_routting.v'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./mesh_torus_routting.v'.
+Parsing design file './../../rtl/src_noc/./comb_spec2.v'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./comb_spec2.v'.
+Parsing design file './../../rtl/src_noc/./route_mesh.v'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./route_mesh.v'.
+Parsing design file './../../rtl/src_noc/./router_bypass.sv'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./router_bypass.sv'.
+Parsing design file './../../rtl/src_noc/./traffic_gen_top.sv'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./traffic_gen_top.sv'.
+Parsing design file './../../rtl/src_noc/./congestion_analyzer.v'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./congestion_analyzer.v'.
+Parsing design file './../../rtl/src_noc/./output_ports.sv'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./output_ports.sv'.
+Parsing design file './../../rtl/src_noc/./routing.v'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./routing.v'.
+Parsing design file './../../rtl/src_noc/./router_two_stage.sv'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./router_two_stage.sv'.
+Parsing design file './../../rtl/src_noc/./crossbar.v'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./crossbar.v'.
+Parsing design file './../../rtl/src_noc/./flit_buffer.sv'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./flit_buffer.sv'.
+Parsing design file './../../rtl/src_noc/./mesh_torus.sv'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./mesh_torus.sv'.
+Parsing design file './../../rtl/src_noc/./debug.v'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./debug.v'.
+Parsing design file './../../rtl/src_noc/./router_top.sv'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./router_top.sv'.
+Parsing design file './../../rtl/src_noc/./mesh_torus_noc_top.sv'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./mesh_torus_noc_top.sv'.
+Parsing design file './../../rtl/src_noc/./star_noc.sv'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./star_noc.sv'.
+Parsing design file './../../rtl/src_noc/./fmesh.sv'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./fmesh.sv'.
+Parsing design file './../../rtl/src_noc/./packet_injector.sv'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./packet_injector.sv'.
+Parsing design file './../../rtl/src_noc/./multicast.sv'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./multicast.sv'.
+Parsing design file './../../rtl/src_topology/./custom1/Tcustom1Rcustom_look_ahead_routing_genvar.v'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_topology/./custom1/Tcustom1Rcustom_look_ahead_routing_genvar.v'.
+Parsing design file './../../rtl/src_topology/./custom1/custom1_noc_genvar.sv'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_topology/./custom1/custom1_noc_genvar.sv'.
+Parsing design file './../../rtl/src_topology/./custom1/Tcustom1Rcustom_conventional_routing_genvar.v'
+Parsing design file './../../rtl/src_topology/./custom1/custom1_noc.sv'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_topology/./custom1/custom1_noc.sv'.
+Parsing design file './../../rtl/src_topology/./custom1/Tcustom1Rcustom_conventional_routing.v'
+Parsing design file './../../rtl/src_topology/./custom1/Tcustom1Rcustom_look_ahead_routing.v'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_topology/./custom1/Tcustom1Rcustom_look_ahead_routing.v'.
+Parsing design file './../../rtl/src_topology/./common/custom_ni_routing.v'
+Parsing design file './../../rtl/src_topology/./common/custom_noc_top.sv'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_topology/./common/custom_noc_top.sv'.
+Parsing design file './../../rtl/src_topology/./common/custom_lkh_routing.v'
+Top Level Modules:
+       noc_top
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./topology_localparam.v, 16
+pronoc_pkg, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./topology_localparam.v, 17
+pronoc_pkg, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./topology_localparam.v, 18
+pronoc_pkg, "(TOPOLOGY == "FATTREE")"
+  A left 32-bit expression is compared to a right 56-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FATTREE"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./topology_localparam.v, 21
+pronoc_pkg, "(TOPOLOGY == "MULTI_MESH")"
+  A left 32-bit expression is compared to a right 80-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"MULTI_MESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./topology_localparam.v, 27
+pronoc_pkg, "(SWA_ARBITER_TYPE == "WRRA")"
+  A left 24-bit expression is compared to a right 32-bit expression.
+  Comparing 'SWA_ARBITER_TYPE' of type string
+  with '"WRRA"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./topology_localparam.v, 28
+pronoc_pkg, "(PCK_TYPE == "SINGLE_FLIT")"
+  A left 80-bit expression is compared to a right 88-bit expression.
+  Comparing 'PCK_TYPE' of type string
+  with '"SINGLE_FLIT"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./topology_localparam.v, 143
+pronoc_pkg, "(ROUTE_NAME == "TRANC_DOR")"
+  A left 16-bit expression is compared to a right 64-bit expression.
+  Comparing 'ROUTE_NAME' of type string
+  with '"TRANC_DOR"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./topology_localparam.v, 143
+pronoc_pkg, "(ROUTE_NAME == "FULL_ADPT")"
+  A left 16-bit expression is compared to a right 40-bit expression.
+  Comparing 'ROUTE_NAME' of type string
+  with '"FULL_ADPT"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./topology_localparam.v, 143
+pronoc_pkg, "(ROUTE_NAME == "TRANC_FULL_ADPT")"
+  A left 16-bit expression is compared to a right 88-bit expression.
+  Comparing 'ROUTE_NAME' of type string
+  with '"TRANC_FULL_ADPT"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./topology_localparam.v, 296
+pronoc_pkg, "(CAST_TYPE == "MULTICAST_FULL")"
+  A left 56-bit expression is compared to a right 112-bit expression.
+  Comparing 'CAST_TYPE' of type string
+  with '"MULTICAST_FULL"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./topology_localparam.v, 296
+pronoc_pkg, "(CAST_TYPE == "MULTICAST_PARTIAL")"
+  A left 56-bit expression is compared to a right 136-bit expression.
+  Comparing 'CAST_TYPE' of type string
+  with '"MULTICAST_PARTIAL"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./topology_localparam.v, 296
+pronoc_pkg, "(CAST_TYPE == "MULTICAST_PARTIAL")"
+  A left 56-bit expression is compared to a right 136-bit expression.
+  Comparing 'CAST_TYPE' of type string
+  with '"MULTICAST_PARTIAL"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./output_ports.sv, 128
+output_ports, "(pronoc_pkg::VC_REALLOCATION_TYPE == "ATOMIC")"
+  A left 72-bit expression is compared to a right 48-bit expression.
+  Comparing 'pronoc_pkg::VC_REALLOCATION_TYPE' of type string
+  with '"ATOMIC"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./combined_vc_sw_alloc.sv, 131
+combined_vc_sw_alloc, "(pronoc_pkg::COMBINATION_TYPE == "COMB_SPEC1")"
+  A left 96-bit expression is compared to a right 80-bit expression.
+  Comparing 'pronoc_pkg::COMBINATION_TYPE' of type string
+  with '"COMB_SPEC1"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./combined_vc_sw_alloc.sv, 167
+combined_vc_sw_alloc, "(pronoc_pkg::COMBINATION_TYPE == "COMB_SPEC2")"
+  A left 96-bit expression is compared to a right 80-bit expression.
+  Comparing 'pronoc_pkg::COMBINATION_TYPE' of type string
+  with '"COMB_SPEC2"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./crossbar.v, 115
+crossbar, "(MUX_TYPE == "ONE_HOT")"
+  A left 48-bit expression is compared to a right 56-bit expression.
+  Comparing 'MUX_TYPE' of type string
+  with '"ONE_HOT"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./crossbar.v, 115
+crossbar, "(MUX_TYPE == "ONE_HOT")"
+  A left 48-bit expression is compared to a right 56-bit expression.
+  Comparing 'MUX_TYPE' of type string
+  with '"ONE_HOT"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./crossbar.v, 115
+crossbar, "(MUX_TYPE == "ONE_HOT")"
+  A left 48-bit expression is compared to a right 56-bit expression.
+  Comparing 'MUX_TYPE' of type string
+  with '"ONE_HOT"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./crossbar.v, 115
+crossbar, "(MUX_TYPE == "ONE_HOT")"
+  A left 48-bit expression is compared to a right 56-bit expression.
+  Comparing 'MUX_TYPE' of type string
+  with '"ONE_HOT"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./crossbar.v, 115
+crossbar, "(MUX_TYPE == "ONE_HOT")"
+  A left 48-bit expression is compared to a right 56-bit expression.
+  Comparing 'MUX_TYPE' of type string
+  with '"ONE_HOT"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./input_ports.sv, 241
+input_queue_per_port, "(pronoc_pkg::VC_REALLOCATION_TYPE == "ATOMIC")"
+  A left 72-bit expression is compared to a right 48-bit expression.
+  Comparing 'pronoc_pkg::VC_REALLOCATION_TYPE' of type string
+  with '"ATOMIC"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./input_ports.sv, 241
+input_queue_per_port, "(pronoc_pkg::VC_REALLOCATION_TYPE == "ATOMIC")"
+  A left 72-bit expression is compared to a right 48-bit expression.
+  Comparing 'pronoc_pkg::VC_REALLOCATION_TYPE' of type string
+  with '"ATOMIC"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./input_ports.sv, 406
+input_queue_per_port, "(pronoc_pkg::TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'pronoc_pkg::TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./input_ports.sv, 423
+input_queue_per_port, "(pronoc_pkg::TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'pronoc_pkg::TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./input_ports.sv, 441
+input_queue_per_port, "(pronoc_pkg::TOPOLOGY == "FATTREE")"
+  A left 32-bit expression is compared to a right 56-bit expression.
+  Comparing 'pronoc_pkg::TOPOLOGY' of type string
+  with '"FATTREE"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./input_ports.sv, 441
+input_queue_per_port, "(pronoc_pkg::ROUTE_NAME == "NCA_STRAIGHT_UP")"
+  A left 16-bit expression is compared to a right 120-bit expression.
+  Comparing 'pronoc_pkg::ROUTE_NAME' of type string
+  with '"NCA_STRAIGHT_UP"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./input_ports.sv, 800
+input_queue_per_port, "(pronoc_pkg::TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'pronoc_pkg::TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./input_ports.sv, 821
+input_queue_per_port, "(pronoc_pkg::TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'pronoc_pkg::TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./input_ports.sv, 800
+input_queue_per_port, "(pronoc_pkg::TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'pronoc_pkg::TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./input_ports.sv, 821
+input_queue_per_port, "(pronoc_pkg::TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'pronoc_pkg::TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./ss_allocator.sv, 222
+ssa_per_vc, "(((1 << V_LOCAL) & (~pronoc_pkg::ESCAP_VC_MASK)) != {pronoc_pkg::V {1'b0}})"
+  A left 32-bit expression is compared to a right 2-bit expression.
+  Comparing '((1 << V_LOCAL) & (~pronoc_pkg::ESCAP_VC_MASK))' of type bit 
+  [31:0]
+  with '{pronoc_pkg::V {1'b0}}' of type bit [1:0].
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./ss_allocator.sv, 222
+ssa_per_vc, "(((1 << V_LOCAL) & (~pronoc_pkg::ESCAP_VC_MASK)) != {pronoc_pkg::V {1'b0}})"
+  A left 32-bit expression is compared to a right 2-bit expression.
+  Comparing '((1 << V_LOCAL) & (~pronoc_pkg::ESCAP_VC_MASK))' of type bit 
+  [31:0]
+  with '{pronoc_pkg::V {1'b0}}' of type bit [1:0].
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./ss_allocator.sv, 222
+ssa_per_vc, "(((1 << V_LOCAL) & (~pronoc_pkg::ESCAP_VC_MASK)) != {pronoc_pkg::V {1'b0}})"
+  A left 32-bit expression is compared to a right 2-bit expression.
+  Comparing '((1 << V_LOCAL) & (~pronoc_pkg::ESCAP_VC_MASK))' of type bit 
+  [31:0]
+  with '{pronoc_pkg::V {1'b0}}' of type bit [1:0].
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./ss_allocator.sv, 222
+ssa_per_vc, "(((1 << V_LOCAL) & (~pronoc_pkg::ESCAP_VC_MASK)) != {pronoc_pkg::V {1'b0}})"
+  A left 32-bit expression is compared to a right 2-bit expression.
+  Comparing '((1 << V_LOCAL) & (~pronoc_pkg::ESCAP_VC_MASK))' of type bit 
+  [31:0]
+  with '{pronoc_pkg::V {1'b0}}' of type bit [1:0].
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./ss_allocator.sv, 222
+ssa_per_vc, "(((1 << V_LOCAL) & (~pronoc_pkg::ESCAP_VC_MASK)) != {pronoc_pkg::V {1'b0}})"
+  A left 32-bit expression is compared to a right 2-bit expression.
+  Comparing '((1 << V_LOCAL) & (~pronoc_pkg::ESCAP_VC_MASK))' of type bit 
+  [31:0]
+  with '{pronoc_pkg::V {1'b0}}' of type bit [1:0].
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./ss_allocator.sv, 222
+ssa_per_vc, "(((1 << V_LOCAL) & (~pronoc_pkg::ESCAP_VC_MASK)) != {pronoc_pkg::V {1'b0}})"
+  A left 32-bit expression is compared to a right 2-bit expression.
+  Comparing '((1 << V_LOCAL) & (~pronoc_pkg::ESCAP_VC_MASK))' of type bit 
+  [31:0]
+  with '{pronoc_pkg::V {1'b0}}' of type bit [1:0].
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./ss_allocator.sv, 222
+ssa_per_vc, "(((1 << V_LOCAL) & (~pronoc_pkg::ESCAP_VC_MASK)) != {pronoc_pkg::V {1'b0}})"
+  A left 32-bit expression is compared to a right 2-bit expression.
+  Comparing '((1 << V_LOCAL) & (~pronoc_pkg::ESCAP_VC_MASK))' of type bit 
+  [31:0]
+  with '{pronoc_pkg::V {1'b0}}' of type bit [1:0].
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./ss_allocator.sv, 222
+ssa_per_vc, "(((1 << V_LOCAL) & (~pronoc_pkg::ESCAP_VC_MASK)) != {pronoc_pkg::V {1'b0}})"
+  A left 32-bit expression is compared to a right 2-bit expression.
+  Comparing '((1 << V_LOCAL) & (~pronoc_pkg::ESCAP_VC_MASK))' of type bit 
+  [31:0]
+  with '{pronoc_pkg::V {1'b0}}' of type bit [1:0].
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./input_ports.sv, 1138
+destp_generator, "(TOPOLOGY == "FATTREE")"
+  A left 32-bit expression is compared to a right 56-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FATTREE"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./input_ports.sv, 1166
+destp_generator, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./routing.v, 287
+look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./routing.v, 287
+look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./routing.v, 314
+look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./routing.v, 287
+look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./routing.v, 287
+look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./routing.v, 314
+look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./routing.v, 287
+look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./routing.v, 287
+look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./routing.v, 314
+look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./routing.v, 287
+look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./routing.v, 287
+look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./routing.v, 314
+look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./routing.v, 287
+look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./routing.v, 287
+look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./routing.v, 314
+look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./comb_nonspec.sv, 721
+swa_output_port_arbiter, "(ARBITER_TYPE == "WRRA")"
+  A left 24-bit expression is compared to a right 32-bit expression.
+  Comparing 'ARBITER_TYPE' of type string
+  with '"WRRA"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./comb_nonspec.sv, 747
+swa_output_port_arbiter, "(ARBITER_TYPE == "WRRA_CLASSIC")"
+  A left 24-bit expression is compared to a right 96-bit expression.
+  Comparing 'ARBITER_TYPE' of type string
+  with '"WRRA_CLASSIC"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus.sv, 336
+mesh_torus_mask_non_assignable_destport_no_self_loop, "(ROUTE_NAME == "TRANC_DOR")"
+  A left 16-bit expression is compared to a right 64-bit expression.
+  Comparing 'ROUTE_NAME' of type string
+  with '"TRANC_DOR"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus.sv, 336
+mesh_torus_mask_non_assignable_destport_no_self_loop, "(ROUTE_NAME == "TRANC_DOR")"
+  A left 16-bit expression is compared to a right 64-bit expression.
+  Comparing 'ROUTE_NAME' of type string
+  with '"TRANC_DOR"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus.sv, 336
+mesh_torus_mask_non_assignable_destport_no_self_loop, "(ROUTE_NAME == "TRANC_DOR")"
+  A left 16-bit expression is compared to a right 64-bit expression.
+  Comparing 'ROUTE_NAME' of type string
+  with '"TRANC_DOR"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 146
+mesh_torus_deterministic_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 146
+mesh_torus_deterministic_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 368
+mesh_torus_next_router_addr_predictor, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 368
+mesh_torus_next_router_addr_predictor, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 638
+mesh_torus_conventional_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+TimeScale is 1 ns / 1 ps
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./topology_localparam.v, 466
+pronoc_pkg, "(CAST_TYPE == "MULTICAST_PARTIAL")"
+  A left 56-bit expression is compared to a right 136-bit expression.
+  Comparing 'CAST_TYPE' of type string
+  with '"MULTICAST_PARTIAL"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./topology_localparam.v, 466
+pronoc_pkg, "(CAST_TYPE == "BROADCAST_PARTIAL")"
+  A left 56-bit expression is compared to a right 136-bit expression.
+  Comparing 'CAST_TYPE' of type string
+  with '"BROADCAST_PARTIAL"' of type string.
+
+
+Lint-[WMIA-L] Width mismatch in assignment
+./../../rtl/src_noc/./topology_localparam.v, 328
+  Width mismatch between LHS and RHS is found in assignment:
+  The following 32-bit wide expression is assigned to a 9-bit LHS target:
+  Source info: mcast_list = MCAST_ENDP_LIST;
+  Expression: mcast_list
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./topology_localparam.v, 332
+pronoc_pkg, "(CAST_TYPE == "MULTICAST_FULL")"
+  A left 56-bit expression is compared to a right 112-bit expression.
+  Comparing 'CAST_TYPE' of type string
+  with '"MULTICAST_FULL"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./topology_localparam.v, 352
+pronoc_pkg, "(CAST_TYPE == "MULTICAST_FULL")"
+  A left 56-bit expression is compared to a right 112-bit expression.
+  Comparing 'CAST_TYPE' of type string
+  with '"MULTICAST_FULL"' of type string.
+
+
+Lint-[WMIA-L] Width mismatch in assignment
+./../../rtl/src_noc/./topology_localparam.v, 356
+  Width mismatch between LHS and RHS is found in assignment:
+  The following 32-bit wide expression is assigned to a 9-bit LHS target:
+  Source info: mcast_list = MCAST_ENDP_LIST;
+  Expression: mcast_list
+
+
+Lint-[WMIA-L] Width mismatch in assignment
+./../../rtl/src_noc/./pronoc_pkg.sv, 300
+  Width mismatch between LHS and RHS is found in assignment:
+  The following 32-bit wide expression is assigned to a 2-bit LHS target:
+  Source info: hetero_ovc_unary = ((HETERO_VC == 0) ? {V {1'b1}} : ((HETERO_VC
+  == 1) ? ((1 << VC_CONFIG_TABLE[router_id][0]) - 1) : ((1 << 
+  VC_CONFIG_TABLE[router_id][router_ ...
+  Expression: hetero_ovc_unary
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./output_ports.sv, 555
+  Following is an unused input.
+  Source info: ssa_granted_ovc_num
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./router_two_stage.sv, 675
+credit_release_gen, "(counter == CREDIT_NUM)"
+  A left 5-bit expression is compared to a right 32-bit expression.
+  Comparing 'counter' of type reg [(W - 1):0]
+  with 'CREDIT_NUM' of type int.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 128
+"chan_in_all[mesh_torus.Y_[0].X_[0].EAST_ID]"
+  The select index is out of declared bounds : [8:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 133
+"chan_in_all[mesh_torus.Y_[0].X_[0].NORTH_ID]"
+  The select index is out of declared bounds : [8:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 138
+"chan_in_all[mesh_torus.Y_[0].X_[0].WEST_ID]"
+  The select index is out of declared bounds : [8:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 143
+"chan_in_all[mesh_torus.Y_[0].X_[0].SOUTH_ID]"
+  The select index is out of declared bounds : [8:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 128
+"chan_in_all[mesh_torus.Y_[0].X_[1].EAST_ID]"
+  The select index is out of declared bounds : [8:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 133
+"chan_in_all[mesh_torus.Y_[0].X_[1].NORTH_ID]"
+  The select index is out of declared bounds : [8:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 138
+"chan_in_all[mesh_torus.Y_[0].X_[1].WEST_ID]"
+  The select index is out of declared bounds : [8:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 143
+"chan_in_all[mesh_torus.Y_[0].X_[1].SOUTH_ID]"
+  The select index is out of declared bounds : [8:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 128
+"chan_in_all[mesh_torus.Y_[0].X_[2].EAST_ID]"
+  The select index is out of declared bounds : [8:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 133
+"chan_in_all[mesh_torus.Y_[0].X_[2].NORTH_ID]"
+  The select index is out of declared bounds : [8:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 138
+"chan_in_all[mesh_torus.Y_[0].X_[2].WEST_ID]"
+  The select index is out of declared bounds : [8:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 143
+"chan_in_all[mesh_torus.Y_[0].X_[2].SOUTH_ID]"
+  The select index is out of declared bounds : [8:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 128
+"chan_in_all[mesh_torus.Y_[1].X_[0].EAST_ID]"
+  The select index is out of declared bounds : [8:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 133
+"chan_in_all[mesh_torus.Y_[1].X_[0].NORTH_ID]"
+  The select index is out of declared bounds : [8:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 138
+"chan_in_all[mesh_torus.Y_[1].X_[0].WEST_ID]"
+  The select index is out of declared bounds : [8:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 143
+"chan_in_all[mesh_torus.Y_[1].X_[0].SOUTH_ID]"
+  The select index is out of declared bounds : [8:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 128
+"chan_in_all[mesh_torus.Y_[1].X_[1].EAST_ID]"
+  The select index is out of declared bounds : [8:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 133
+"chan_in_all[mesh_torus.Y_[1].X_[1].NORTH_ID]"
+  The select index is out of declared bounds : [8:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 138
+"chan_in_all[mesh_torus.Y_[1].X_[1].WEST_ID]"
+  The select index is out of declared bounds : [8:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 143
+"chan_in_all[mesh_torus.Y_[1].X_[1].SOUTH_ID]"
+  The select index is out of declared bounds : [8:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 128
+"chan_in_all[mesh_torus.Y_[1].X_[2].EAST_ID]"
+  The select index is out of declared bounds : [8:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 133
+"chan_in_all[mesh_torus.Y_[1].X_[2].NORTH_ID]"
+  The select index is out of declared bounds : [8:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 138
+"chan_in_all[mesh_torus.Y_[1].X_[2].WEST_ID]"
+  The select index is out of declared bounds : [8:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 143
+"chan_in_all[mesh_torus.Y_[1].X_[2].SOUTH_ID]"
+  The select index is out of declared bounds : [8:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 128
+"chan_in_all[mesh_torus.Y_[2].X_[0].EAST_ID]"
+  The select index is out of declared bounds : [8:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 133
+"chan_in_all[mesh_torus.Y_[2].X_[0].NORTH_ID]"
+  The select index is out of declared bounds : [8:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 138
+"chan_in_all[mesh_torus.Y_[2].X_[0].WEST_ID]"
+  The select index is out of declared bounds : [8:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 143
+"chan_in_all[mesh_torus.Y_[2].X_[0].SOUTH_ID]"
+  The select index is out of declared bounds : [8:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 128
+"chan_in_all[mesh_torus.Y_[2].X_[1].EAST_ID]"
+  The select index is out of declared bounds : [8:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 133
+"chan_in_all[mesh_torus.Y_[2].X_[1].NORTH_ID]"
+  The select index is out of declared bounds : [8:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 138
+"chan_in_all[mesh_torus.Y_[2].X_[1].WEST_ID]"
+  The select index is out of declared bounds : [8:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 143
+"chan_in_all[mesh_torus.Y_[2].X_[1].SOUTH_ID]"
+  The select index is out of declared bounds : [8:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 128
+"chan_in_all[mesh_torus.Y_[2].X_[2].EAST_ID]"
+  The select index is out of declared bounds : [8:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 133
+"chan_in_all[mesh_torus.Y_[2].X_[2].NORTH_ID]"
+  The select index is out of declared bounds : [8:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 138
+"chan_in_all[mesh_torus.Y_[2].X_[2].WEST_ID]"
+  The select index is out of declared bounds : [8:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 143
+"chan_in_all[mesh_torus.Y_[2].X_[2].SOUTH_ID]"
+  The select index is out of declared bounds : [8:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./inout_ports.sv, 116
+  Following is an unused input.
+  Source info: spec_ovc_num_all
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./inout_ports.sv, 118
+  Following is an unused input.
+  Source info: spec_first_arbiter_granted_ivc_all
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./inout_ports.sv, 120
+  Following is an unused input.
+  Source info: spec_granted_dest_port_all
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./output_ports.sv, 88
+  Following is an unused input.
+  Source info: crossbar_flit_out_wr_all
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./congestion_analyzer.v, 351
+  Following is an unused input.
+  Source info: ovc_status
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./congestion_analyzer.v, 352
+  Following is an unused input.
+  Source info: ovc_avalable_all
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./congestion_analyzer.v, 353
+  Following is an unused input.
+  Source info: credit_decreased_all
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./congestion_analyzer.v, 354
+  Following is an unused input.
+  Source info: credit_increased_all
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./congestion_analyzer.v, 355
+  Following is an unused input.
+  Source info: congestion_in_all
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./congestion_analyzer.v, 356
+  Following is an unused input.
+  Source info: reset
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./congestion_analyzer.v, 356
+  Following is an unused input.
+  Source info: clk
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./inout_ports.sv, 464
+  Following is an unused input.
+  Source info: port_pre_sel
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./inout_ports.sv, 467
+  Following is an unused input.
+  Source info: reset
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./inout_ports.sv, 468
+  Following is an unused input.
+  Source info: clk
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./inout_ports.sv, 471
+  Following is an unused input.
+  Source info: ivc_num_getting_ovc_grant
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./congestion_analyzer.v, 965
+  Following is an unused input.
+  Source info: ovc_avalable_all
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./congestion_analyzer.v, 966
+  Following is an unused input.
+  Source info: ivc_request_all
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./congestion_analyzer.v, 967
+  Following is an unused input.
+  Source info: ivc_num_getting_sw_grant
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./input_ports.sv, 273
+  Following is an unused input.
+  Source info: refresh_w_counter
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./input_ports.sv, 274
+  Following is an unused input.
+  Source info: granted_dest_port
+
+
+Lint-[WMIA-L] Width mismatch in assignment
+./../../rtl/src_noc/./input_ports.sv, 379
+  Width mismatch between LHS and RHS is found in assignment:
+  The following 32-bit wide expression is assigned to a 4-bit LHS target:
+  Source info: iport_weight_next = ((weight_in == {pronoc_pkg::WEIGHTw 
+  {1'b0}}) ? 1 : weight_in);
+  Expression: iport_weight_next
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./flit_buffer.sv, 80
+  Following is an unused input.
+  Source info: multiple_dest
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./flit_buffer.sv, 81
+  Following is an unused input.
+  Source info: sub_rd_ptr_ld
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./flit_buffer.sv, 80
+  Following is an unused input.
+  Source info: multiple_dest
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./flit_buffer.sv, 81
+  Following is an unused input.
+  Source info: sub_rd_ptr_ld
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./header_flit.sv, 222
+  Following is an unused input.
+  Source info: sel
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./ss_allocator.sv, 364
+  Following is an unused input.
+  Source info: destport_one_hot
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./ss_allocator.sv, 365
+  Following is an unused input.
+  Source info: dest_e_addr_in
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./flit_buffer.sv, 680
+fwft_fifo, "(IGNORE_SAME_LOC_RD_WR_WARNING == "NO")"
+  A left 24-bit expression is compared to a right 16-bit expression.
+  Comparing 'IGNORE_SAME_LOC_RD_WR_WARNING' of type string
+  with '"NO"' of type string.
+
+
+Lint-[CAWM-L] Width mismatch
+./../../rtl/src_noc/./flit_buffer.sv, 631
+  Continuous assignment width mismatch
+  5 bits (lhs) versus 32 bits (rhs).
+  Source info: assign mwb2.depth_2 = (depth - 2);  
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./routing.v, 276
+  Following is an unused input.
+  Source info: neighbors_r_addr
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./routing.v, 279
+  Following is an unused input.
+  Source info: src_e_addr
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./routing.v, 276
+  Following is an unused input.
+  Source info: neighbors_r_addr
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./routing.v, 279
+  Following is an unused input.
+  Source info: src_e_addr
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./routing.v, 276
+  Following is an unused input.
+  Source info: neighbors_r_addr
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./routing.v, 279
+  Following is an unused input.
+  Source info: src_e_addr
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./routing.v, 276
+  Following is an unused input.
+  Source info: neighbors_r_addr
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./routing.v, 279
+  Following is an unused input.
+  Source info: src_e_addr
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./routing.v, 276
+  Following is an unused input.
+  Source info: neighbors_r_addr
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./routing.v, 279
+  Following is an unused input.
+  Source info: src_e_addr
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./comb_nonspec.sv, 634
+  Following is an unused input.
+  Source info: vc_weight_is_consumed
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./comb_nonspec.sv, 717
+  Following is an unused input.
+  Source info: weight_consumed
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./mesh_torus.sv, 794
+  Following is an unused input.
+  Source info: clk
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./mesh_torus.sv, 794
+  Following is an unused input.
+  Source info: ivc_num_getting_sw_grant
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./mesh_torus.sv, 794
+  Following is an unused input.
+  Source info: hdr_flg
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./mesh_torus.sv, 794
+  Following is an unused input.
+  Source info: clk
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./mesh_torus.sv, 794
+  Following is an unused input.
+  Source info: ivc_num_getting_sw_grant
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./mesh_torus.sv, 794
+  Following is an unused input.
+  Source info: hdr_flg
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./mesh_torus.sv, 324
+  Following is an unused input.
+  Source info: odd_column
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./mesh_torus.sv, 324
+  Following is an unused input.
+  Source info: odd_column
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./mesh_torus.sv, 324
+  Following is an unused input.
+  Source info: odd_column
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./mesh_torus.sv, 1213
+  Following is an unused input.
+  Source info: endp_localp_num
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./mesh_torus.sv, 1215
+  Following is an unused input.
+  Source info: swap_port_presel
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./mesh_torus.sv, 1216
+  Following is an unused input.
+  Source info: port_pre_sel
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./input_ports.sv, 273
+  Following is an unused input.
+  Source info: refresh_w_counter
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./input_ports.sv, 274
+  Following is an unused input.
+  Source info: granted_dest_port
+
+
+Lint-[WMIA-L] Width mismatch in assignment
+./../../rtl/src_noc/./input_ports.sv, 379
+  Width mismatch between LHS and RHS is found in assignment:
+  The following 32-bit wide expression is assigned to a 4-bit LHS target:
+  Source info: iport_weight_next = ((weight_in == {pronoc_pkg::WEIGHTw 
+  {1'b0}}) ? 1 : weight_in);
+  Expression: iport_weight_next
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./input_ports.sv, 273
+  Following is an unused input.
+  Source info: refresh_w_counter
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./input_ports.sv, 274
+  Following is an unused input.
+  Source info: granted_dest_port
+
+
+Lint-[WMIA-L] Width mismatch in assignment
+./../../rtl/src_noc/./input_ports.sv, 379
+  Width mismatch between LHS and RHS is found in assignment:
+  The following 32-bit wide expression is assigned to a 4-bit LHS target:
+  Source info: iport_weight_next = ((weight_in == {pronoc_pkg::WEIGHTw 
+  {1'b0}}) ? 1 : weight_in);
+  Expression: iport_weight_next
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./input_ports.sv, 273
+  Following is an unused input.
+  Source info: refresh_w_counter
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./input_ports.sv, 274
+  Following is an unused input.
+  Source info: granted_dest_port
+
+
+Lint-[WMIA-L] Width mismatch in assignment
+./../../rtl/src_noc/./input_ports.sv, 379
+  Width mismatch between LHS and RHS is found in assignment:
+  The following 32-bit wide expression is assigned to a 4-bit LHS target:
+  Source info: iport_weight_next = ((weight_in == {pronoc_pkg::WEIGHTw 
+  {1'b0}}) ? 1 : weight_in);
+  Expression: iport_weight_next
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./input_ports.sv, 273
+  Following is an unused input.
+  Source info: refresh_w_counter
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./input_ports.sv, 274
+  Following is an unused input.
+  Source info: granted_dest_port
+
+
+Lint-[WMIA-L] Width mismatch in assignment
+./../../rtl/src_noc/./input_ports.sv, 379
+  Width mismatch between LHS and RHS is found in assignment:
+  The following 32-bit wide expression is assigned to a 4-bit LHS target:
+  Source info: iport_weight_next = ((weight_in == {pronoc_pkg::WEIGHTw 
+  {1'b0}}) ? 1 : weight_in);
+  Expression: iport_weight_next
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./ss_allocator.sv, 364
+  Following is an unused input.
+  Source info: destport_one_hot
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./ss_allocator.sv, 365
+  Following is an unused input.
+  Source info: dest_e_addr_in
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./flit_buffer.sv, 680
+fwft_fifo, "(IGNORE_SAME_LOC_RD_WR_WARNING == "NO")"
+  A left 24-bit expression is compared to a right 16-bit expression.
+  Comparing 'IGNORE_SAME_LOC_RD_WR_WARNING' of type string
+  with '"NO"' of type string.
+
+
+Lint-[CAWM-L] Width mismatch
+./../../rtl/src_noc/./flit_buffer.sv, 631
+  Continuous assignment width mismatch
+  3 bits (lhs) versus 32 bits (rhs).
+  Source info: assign mwb2.depth_2 = (depth - 2);  
+
+Starting vcs inline pass...
+
+36 modules and 0 UDP read.
+Generating code for _VCSgd_reYIK
+Generating code for _VCSgd_bQrwm
+recompiling package pronoc_pkg
+Generating code for _VCSgd_UU20K
+recompiling module pronoc_register
+Generating code for _VCSgd_J18WU
+Generating code for _VCSgd_t2N4h
+Generating code for _VCSgd_dP5iL
+Generating code for _VCSgd_sGFGA
+recompiling module one_hot_demux
+Generating code for _VCSgd_PFE93
+recompiling module custom_or
+Generating code for _VCSgd_rxxii
+recompiling module one_hot_to_bin
+Generating code for _VCSgd_tmkfi
+Generating code for _VCSgd_z7NBD
+recompiling module binary_mux
+Generating code for _VCSgd_iuc87
+recompiling module arbiter
+Generating code for _VCSgd_Z8Hg1
+recompiling module arbiter_2_one_hot
+Generating code for _VCSgd_nMgKR
+recompiling module ss_allocator
+Generating code for _VCSgd_PnDZp
+recompiling module ssa_per_vc
+Generating code for _VCSgd_yqzS6
+Generating code for _VCSgd_jLwrn
+recompiling module extract_header_flit_info
+Generating code for _VCSgd_Ly3qd
+recompiling module header_flit_update_lk_route_ovc
+Generating code for _VCSgd_ECtRV
+recompiling module noc_top
+Generating code for _VCSgd_qubHr
+recompiling module comb_nonspec_allocator
+Generating code for _VCSgd_dmk1W
+recompiling module swa_input_port_arbiter
+Generating code for _VCSgd_wLDGV
+recompiling module swa_output_port_arbiter
+Generating code for _VCSgd_AW5ic
+recompiling module inout_ports
+Generating code for _VCSgd_xNBkF
+recompiling module vc_alloc_request_gen
+Generating code for _VCSgd_bzyYs
+recompiling module input_ports
+Generating code for _VCSgd_at0sD
+recompiling module input_queue_per_port
+Generating code for _VCSgd_vPvg3
+Generating code for _VCSgd_TypBP
+Generating code for _VCSgd_SQwq4
+Generating code for _VCSgd_hJjVQ
+Generating code for _VCSgd_sPxW2
+recompiling module destp_generator
+Generating code for _VCSgd_k7SJc
+Generating code for _VCSgd_g9A6z
+Generating code for _VCSgd_DJdxW
+Generating code for _VCSgd_r6P8n
+Generating code for _VCSgd_pnIHZ
+recompiling module combined_vc_sw_alloc
+Generating code for _VCSgd_L5RSt
+recompiling module mesh_torus_look_ahead_routing
+Generating code for _VCSgd_ihbcT
+recompiling module onehot_mux_1D
+Generating code for _VCSgd_wje7W
+Generating code for _VCSgd_ZzZJM
+Generating code for _VCSgd_Dh26b
+Generating code for _VCSgd_etkVB
+Generating code for _VCSgd_ER2NJ
+Generating code for _VCSgd_UfJB9
+recompiling module header_flit_info
+Generating code for _VCSgd_InS4s
+recompiling module output_ports
+Generating code for _VCSgd_IhnxI
+recompiling module credit_monitor_per_ovc
+Generating code for _VCSgd_pAQwF
+Generating code for _VCSgd_UPPPJ
+recompiling module oport_ovc_sig_gen
+Generating code for _VCSgd_iMQv0
+recompiling module full_ovc_predictor
+Generating code for _VCSgd_Nx31A
+recompiling module router_two_stage
+Generating code for _VCSgd_QCD2e
+recompiling module credit_release_gen
+Generating code for _VCSgd_yaiFc
+recompiling module flit_buffer
+Generating code for _VCSgd_bcmYE
+recompiling module fwft_fifo
+Generating code for _VCSgd_JPLQY
+Generating code for _VCSgd_jHVFt
+recompiling module mesh_torus_destp_decoder
+Generating code for _VCSgd_sIT4b
+recompiling module router_top
+Generating code for _VCSgd_J4kZy
+recompiling module mesh_torus_noc_top
+All of 36 modules done
+make: Warning: File 'filelist.hsopt.llvm2_0.objs' has modification time 55 s in the future
+make: warning:  Clock skew detected.  Your build may be incomplete.
+make: Warning: File 'filelist.cu' has modification time 54 s in the future
+make[1]: Warning: File 'filelist.cu' has modification time 54 s in the future
+rm -f _cuarc*.so _csrc*.so pre_vcsobj_*.so share_vcsobj_*.so
+make[1]: warning:  Clock skew detected.  Your build may be incomplete.
+make[1]: Warning: File 'filelist.cu' has modification time 54 s in the future
+make[1]: warning:  Clock skew detected.  Your build may be incomplete.
+if [ -x /users/amonemi/ProNoC/mpsoc/Integration_test/VCS/result_logs/work/simv ]; then chmod a-x /users/amonemi/ProNoC/mpsoc/Integration_test/VCS/result_logs/work/simv; fi
+g++  -o /users/amonemi/ProNoC/mpsoc/Integration_test/VCS/result_logs/work/simv   -no-pie    -rdynamic  -Wl,-rpath='$ORIGIN'/simv.daidir -Wl,-rpath=./simv.daidir -Wl,-rpath=/eda/synopsys/2022-23/RHELx86/VCS_2022.06-SP2/linux64/lib -L/eda/synopsys/2022-23/RHELx86/VCS_2022.06-SP2/linux64/lib  -Wl,-rpath-link=./ -Wl,--no-as-needed   objs/amcQw_d.o   _1507254_archive_1.so _prev_archive_1.so  SIM_l.o       rmapats_mop.o rmapats.o rmar.o rmar_nd.o  rmar_llvm_0_1.o rmar_llvm_0_0.o            -lnuma -lvirsim -lerrorinf -lsnpsmalloc -lvfs    -lvcsnew -lsimprofile -luclinative /eda/synopsys/2022-23/RHELx86/VCS_2022.06-SP2/linux64/lib/vcs_tls.o   -Wl,-whole-archive  -lvcsucli    -Wl,-no-whole-archive        _vcs_pli_stub_.o   /eda/synopsys/2022-23/RHELx86/VCS_2022.06-SP2/linux64/lib/vcs_save_restore_new.o /eda/synopsys/2022-23/RHELx86/VERDI_2022.06-SP2/share/PLI/VCS/LINUX64/pli.a -ldl  -lc -lm -lpthread -ldl 
+/users/amonemi/ProNoC/mpsoc/Integration_test/VCS/result_logs/work/simv up to date
+make: warning:  Clock skew detected.  Your build may be incomplete.
+Verdi KDB elaboration done and the database successfully generated: 0 error(s), 0 warning(s)
diff --git a/mpsoc/Integration_test/VCS/Golden_ref/mesh_4x4_2cycle_mcast_f.log b/mpsoc/Integration_test/VCS/Golden_ref/mesh_4x4_2cycle_mcast_f.log
new file mode 100644
index 0000000..0fc7864
--- /dev/null
+++ b/mpsoc/Integration_test/VCS/Golden_ref/mesh_4x4_2cycle_mcast_f.log
@@ -0,0 +1,2060 @@
+Use of uninitialized value $ENV{"PRONOC_WORK"} in concatenation (.) or string at /users/amonemi/ProNoC/mpsoc/Integration_test/VCS/src/../../synthetic_sim/src/src.pl line 24.
+Use of uninitialized value $ENV{"PRONOC_WORK"} in concatenation (.) or string at /users/amonemi/ProNoC/mpsoc/Integration_test/VCS/src/../../synthetic_sim/src/src.pl line 25.
+Use of uninitialized value $ENV{"PRONOC_WORK"} in concatenation (.) or string at /users/amonemi/ProNoC/mpsoc/Integration_test/VCS/src/../../synthetic_sim/src/src.pl line 26.
+Script Path: /users/amonemi/ProNoC/mpsoc/Integration_test/VCS/src/../../synthetic_sim/src
+confs_dir: /users/amonemi/ProNoC/mpsoc/Integration_test/synthetic_sim/configurations
+Root: /users/amonemi/ProNoC/mpsoc
+Parsing design file './../../rtl/src_noc/./pronoc_pkg.sv'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./pronoc_pkg.sv'.
+Parsing included file './src/noc_localparam.v'.
+Back to file './../../rtl/src_noc/./pronoc_pkg.sv'.
+Parsing included file './../../rtl/src_noc/./topology_localparam.v'.
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./topology_localparam.v'.
+Back to file './../../rtl/src_noc/./pronoc_pkg.sv'.
+Parsing design file './../../rtl/src_noc/./../main_comp.v'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./../main_comp.v'.
+Parsing design file './../../rtl/src_noc/./../arbiter.v'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./../arbiter.v'.
+Parsing design file './../../rtl/src_noc/./ovc_list.sv'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./ovc_list.sv'.
+Parsing design file './../../rtl/src_noc/./ss_allocator.sv'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./ss_allocator.sv'.
+Parsing design file './../../rtl/src_noc/./route_torus.v'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./route_torus.v'.
+Parsing design file './../../rtl/src_noc/./header_flit.sv'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./header_flit.sv'.
+Parsing design file './../../rtl/src_noc/./noc_top.sv'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./noc_top.sv'.
+Parsing design file './../../rtl/src_noc/./fattree_noc_top.sv'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./fattree_noc_top.sv'.
+Parsing design file './../../rtl/src_noc/./fattree_route.v'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./fattree_route.v'.
+Parsing design file './../../rtl/src_noc/./comb_nonspec.sv'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./comb_nonspec.sv'.
+Parsing design file './../../rtl/src_noc/./inout_ports.sv'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./inout_ports.sv'.
+Parsing design file './../../rtl/src_noc/./wrra.v'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./wrra.v'.
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./wrra.v'.
+Parsing design file './../../rtl/src_noc/./input_ports.sv'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./input_ports.sv'.
+Parsing design file './../../rtl/src_noc/./tree_noc_top.sv'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./tree_noc_top.sv'.
+Parsing design file './../../rtl/src_noc/./tree_route.v'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./tree_route.v'.
+Parsing design file './../../rtl/src_noc/./comb-spec1.v'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./comb-spec1.v'.
+Parsing design file './../../rtl/src_noc/./combined_vc_sw_alloc.sv'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./combined_vc_sw_alloc.sv'.
+Parsing design file './../../rtl/src_noc/./mesh_torus_routting.v'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./mesh_torus_routting.v'.
+Parsing design file './../../rtl/src_noc/./comb_spec2.v'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./comb_spec2.v'.
+Parsing design file './../../rtl/src_noc/./route_mesh.v'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./route_mesh.v'.
+Parsing design file './../../rtl/src_noc/./router_bypass.sv'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./router_bypass.sv'.
+Parsing design file './../../rtl/src_noc/./traffic_gen_top.sv'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./traffic_gen_top.sv'.
+Parsing design file './../../rtl/src_noc/./congestion_analyzer.v'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./congestion_analyzer.v'.
+Parsing design file './../../rtl/src_noc/./output_ports.sv'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./output_ports.sv'.
+Parsing design file './../../rtl/src_noc/./routing.v'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./routing.v'.
+Parsing design file './../../rtl/src_noc/./router_two_stage.sv'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./router_two_stage.sv'.
+Parsing design file './../../rtl/src_noc/./crossbar.v'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./crossbar.v'.
+Parsing design file './../../rtl/src_noc/./flit_buffer.sv'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./flit_buffer.sv'.
+Parsing design file './../../rtl/src_noc/./mesh_torus.sv'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./mesh_torus.sv'.
+Parsing design file './../../rtl/src_noc/./debug.v'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./debug.v'.
+Parsing design file './../../rtl/src_noc/./router_top.sv'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./router_top.sv'.
+Parsing design file './../../rtl/src_noc/./mesh_torus_noc_top.sv'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./mesh_torus_noc_top.sv'.
+Parsing design file './../../rtl/src_noc/./star_noc.sv'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./star_noc.sv'.
+Parsing design file './../../rtl/src_noc/./fmesh.sv'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./fmesh.sv'.
+Parsing design file './../../rtl/src_noc/./packet_injector.sv'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./packet_injector.sv'.
+Parsing design file './../../rtl/src_noc/./multicast.sv'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./multicast.sv'.
+Parsing design file './../../rtl/src_topology/./custom1/Tcustom1Rcustom_look_ahead_routing_genvar.v'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_topology/./custom1/Tcustom1Rcustom_look_ahead_routing_genvar.v'.
+Parsing design file './../../rtl/src_topology/./custom1/custom1_noc_genvar.sv'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_topology/./custom1/custom1_noc_genvar.sv'.
+Parsing design file './../../rtl/src_topology/./custom1/Tcustom1Rcustom_conventional_routing_genvar.v'
+Parsing design file './../../rtl/src_topology/./custom1/custom1_noc.sv'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_topology/./custom1/custom1_noc.sv'.
+Parsing design file './../../rtl/src_topology/./custom1/Tcustom1Rcustom_conventional_routing.v'
+Parsing design file './../../rtl/src_topology/./custom1/Tcustom1Rcustom_look_ahead_routing.v'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_topology/./custom1/Tcustom1Rcustom_look_ahead_routing.v'.
+Parsing design file './../../rtl/src_topology/./common/custom_ni_routing.v'
+Parsing design file './../../rtl/src_topology/./common/custom_noc_top.sv'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_topology/./common/custom_noc_top.sv'.
+Parsing design file './../../rtl/src_topology/./common/custom_lkh_routing.v'
+Top Level Modules:
+       noc_top
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./topology_localparam.v, 16
+pronoc_pkg, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./topology_localparam.v, 17
+pronoc_pkg, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./topology_localparam.v, 18
+pronoc_pkg, "(TOPOLOGY == "FATTREE")"
+  A left 32-bit expression is compared to a right 56-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FATTREE"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./topology_localparam.v, 21
+pronoc_pkg, "(TOPOLOGY == "MULTI_MESH")"
+  A left 32-bit expression is compared to a right 80-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"MULTI_MESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./topology_localparam.v, 27
+pronoc_pkg, "(SWA_ARBITER_TYPE == "WRRA")"
+  A left 24-bit expression is compared to a right 32-bit expression.
+  Comparing 'SWA_ARBITER_TYPE' of type string
+  with '"WRRA"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./topology_localparam.v, 28
+pronoc_pkg, "(PCK_TYPE == "SINGLE_FLIT")"
+  A left 80-bit expression is compared to a right 88-bit expression.
+  Comparing 'PCK_TYPE' of type string
+  with '"SINGLE_FLIT"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./topology_localparam.v, 143
+pronoc_pkg, "(ROUTE_NAME == "TRANC_DOR")"
+  A left 16-bit expression is compared to a right 64-bit expression.
+  Comparing 'ROUTE_NAME' of type string
+  with '"TRANC_DOR"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./topology_localparam.v, 143
+pronoc_pkg, "(ROUTE_NAME == "FULL_ADPT")"
+  A left 16-bit expression is compared to a right 40-bit expression.
+  Comparing 'ROUTE_NAME' of type string
+  with '"FULL_ADPT"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./topology_localparam.v, 143
+pronoc_pkg, "(ROUTE_NAME == "TRANC_FULL_ADPT")"
+  A left 16-bit expression is compared to a right 88-bit expression.
+  Comparing 'ROUTE_NAME' of type string
+  with '"TRANC_FULL_ADPT"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./topology_localparam.v, 205
+pronoc_pkg, "(CAST_TYPE != "UNICAST")"
+  A left 112-bit expression is compared to a right 56-bit expression.
+  Comparing 'CAST_TYPE' of type string
+  with '"UNICAST"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./topology_localparam.v, 246
+pronoc_pkg, "(CAST_TYPE != "UNICAST")"
+  A left 112-bit expression is compared to a right 56-bit expression.
+  Comparing 'CAST_TYPE' of type string
+  with '"UNICAST"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./topology_localparam.v, 296
+pronoc_pkg, "(CAST_TYPE == "MULTICAST_PARTIAL")"
+  A left 112-bit expression is compared to a right 136-bit expression.
+  Comparing 'CAST_TYPE' of type string
+  with '"MULTICAST_PARTIAL"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./topology_localparam.v, 296
+pronoc_pkg, "(CAST_TYPE == "MULTICAST_PARTIAL")"
+  A left 112-bit expression is compared to a right 136-bit expression.
+  Comparing 'CAST_TYPE' of type string
+  with '"MULTICAST_PARTIAL"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./topology_localparam.v, 301
+pronoc_pkg, "(CAST_TYPE == "UNICAST")"
+  A left 112-bit expression is compared to a right 56-bit expression.
+  Comparing 'CAST_TYPE' of type string
+  with '"UNICAST"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./router_two_stage.sv, 197
+router_two_stage, "(pronoc_pkg::CAST_TYPE == "UNICAST")"
+  A left 112-bit expression is compared to a right 56-bit expression.
+  Comparing 'pronoc_pkg::CAST_TYPE' of type string
+  with '"UNICAST"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./router_two_stage.sv, 197
+router_two_stage, "(pronoc_pkg::CAST_TYPE == "UNICAST")"
+  A left 112-bit expression is compared to a right 56-bit expression.
+  Comparing 'pronoc_pkg::CAST_TYPE' of type string
+  with '"UNICAST"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./router_two_stage.sv, 197
+router_two_stage, "(pronoc_pkg::CAST_TYPE == "UNICAST")"
+  A left 112-bit expression is compared to a right 56-bit expression.
+  Comparing 'pronoc_pkg::CAST_TYPE' of type string
+  with '"UNICAST"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./router_two_stage.sv, 197
+router_two_stage, "(pronoc_pkg::CAST_TYPE == "UNICAST")"
+  A left 112-bit expression is compared to a right 56-bit expression.
+  Comparing 'pronoc_pkg::CAST_TYPE' of type string
+  with '"UNICAST"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./router_two_stage.sv, 197
+router_two_stage, "(pronoc_pkg::CAST_TYPE == "UNICAST")"
+  A left 112-bit expression is compared to a right 56-bit expression.
+  Comparing 'pronoc_pkg::CAST_TYPE' of type string
+  with '"UNICAST"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./output_ports.sv, 128
+output_ports, "(pronoc_pkg::VC_REALLOCATION_TYPE == "ATOMIC")"
+  A left 72-bit expression is compared to a right 48-bit expression.
+  Comparing 'pronoc_pkg::VC_REALLOCATION_TYPE' of type string
+  with '"ATOMIC"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./output_ports.sv, 349
+output_ports, "(pronoc_pkg::CAST_TYPE == "UNICAST")"
+  A left 112-bit expression is compared to a right 56-bit expression.
+  Comparing 'pronoc_pkg::CAST_TYPE' of type string
+  with '"UNICAST"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./combined_vc_sw_alloc.sv, 131
+combined_vc_sw_alloc, "(pronoc_pkg::COMBINATION_TYPE == "COMB_SPEC1")"
+  A left 96-bit expression is compared to a right 80-bit expression.
+  Comparing 'pronoc_pkg::COMBINATION_TYPE' of type string
+  with '"COMB_SPEC1"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./combined_vc_sw_alloc.sv, 167
+combined_vc_sw_alloc, "(pronoc_pkg::COMBINATION_TYPE == "COMB_SPEC2")"
+  A left 96-bit expression is compared to a right 80-bit expression.
+  Comparing 'pronoc_pkg::COMBINATION_TYPE' of type string
+  with '"COMB_SPEC2"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./crossbar.v, 115
+crossbar, "(MUX_TYPE == "ONE_HOT")"
+  A left 48-bit expression is compared to a right 56-bit expression.
+  Comparing 'MUX_TYPE' of type string
+  with '"ONE_HOT"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./crossbar.v, 115
+crossbar, "(MUX_TYPE == "ONE_HOT")"
+  A left 48-bit expression is compared to a right 56-bit expression.
+  Comparing 'MUX_TYPE' of type string
+  with '"ONE_HOT"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./crossbar.v, 115
+crossbar, "(MUX_TYPE == "ONE_HOT")"
+  A left 48-bit expression is compared to a right 56-bit expression.
+  Comparing 'MUX_TYPE' of type string
+  with '"ONE_HOT"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./crossbar.v, 115
+crossbar, "(MUX_TYPE == "ONE_HOT")"
+  A left 48-bit expression is compared to a right 56-bit expression.
+  Comparing 'MUX_TYPE' of type string
+  with '"ONE_HOT"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./crossbar.v, 115
+crossbar, "(MUX_TYPE == "ONE_HOT")"
+  A left 48-bit expression is compared to a right 56-bit expression.
+  Comparing 'MUX_TYPE' of type string
+  with '"ONE_HOT"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./input_ports.sv, 241
+input_queue_per_port, "(pronoc_pkg::VC_REALLOCATION_TYPE == "ATOMIC")"
+  A left 72-bit expression is compared to a right 48-bit expression.
+  Comparing 'pronoc_pkg::VC_REALLOCATION_TYPE' of type string
+  with '"ATOMIC"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./debug.v, 601
+check_pck_size, "(CAST_TYPE != "UNICAST")"
+  A left 112-bit expression is compared to a right 56-bit expression.
+  Comparing 'CAST_TYPE' of type string
+  with '"UNICAST"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./debug.v, 601
+check_pck_size, "(CAST_TYPE != "UNICAST")"
+  A left 112-bit expression is compared to a right 56-bit expression.
+  Comparing 'CAST_TYPE' of type string
+  with '"UNICAST"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./input_ports.sv, 406
+input_queue_per_port, "(pronoc_pkg::TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'pronoc_pkg::TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./input_ports.sv, 406
+input_queue_per_port, "(pronoc_pkg::CAST_TYPE == "UNICAST")"
+  A left 112-bit expression is compared to a right 56-bit expression.
+  Comparing 'pronoc_pkg::CAST_TYPE' of type string
+  with '"UNICAST"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./input_ports.sv, 423
+input_queue_per_port, "(pronoc_pkg::TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'pronoc_pkg::TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./input_ports.sv, 423
+input_queue_per_port, "(pronoc_pkg::CAST_TYPE == "UNICAST")"
+  A left 112-bit expression is compared to a right 56-bit expression.
+  Comparing 'pronoc_pkg::CAST_TYPE' of type string
+  with '"UNICAST"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./input_ports.sv, 441
+input_queue_per_port, "(pronoc_pkg::TOPOLOGY == "FATTREE")"
+  A left 32-bit expression is compared to a right 56-bit expression.
+  Comparing 'pronoc_pkg::TOPOLOGY' of type string
+  with '"FATTREE"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./input_ports.sv, 441
+input_queue_per_port, "(pronoc_pkg::ROUTE_NAME == "NCA_STRAIGHT_UP")"
+  A left 16-bit expression is compared to a right 120-bit expression.
+  Comparing 'pronoc_pkg::ROUTE_NAME' of type string
+  with '"NCA_STRAIGHT_UP"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./input_ports.sv, 947
+input_queue_per_port, "(pronoc_pkg::CAST_TYPE == "UNICAST")"
+  A left 112-bit expression is compared to a right 56-bit expression.
+  Comparing 'pronoc_pkg::CAST_TYPE' of type string
+  with '"UNICAST"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./input_ports.sv, 667
+input_queue_per_port, "(pronoc_pkg::CAST_TYPE != "UNICAST")"
+  A left 112-bit expression is compared to a right 56-bit expression.
+  Comparing 'pronoc_pkg::CAST_TYPE' of type string
+  with '"UNICAST"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./input_ports.sv, 800
+input_queue_per_port, "(pronoc_pkg::TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'pronoc_pkg::TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./input_ports.sv, 800
+input_queue_per_port, "(pronoc_pkg::CAST_TYPE == "UNICAST")"
+  A left 112-bit expression is compared to a right 56-bit expression.
+  Comparing 'pronoc_pkg::CAST_TYPE' of type string
+  with '"UNICAST"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./input_ports.sv, 821
+input_queue_per_port, "(pronoc_pkg::TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'pronoc_pkg::TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./input_ports.sv, 821
+input_queue_per_port, "(pronoc_pkg::CAST_TYPE == "UNICAST")"
+  A left 112-bit expression is compared to a right 56-bit expression.
+  Comparing 'pronoc_pkg::CAST_TYPE' of type string
+  with '"UNICAST"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./input_ports.sv, 667
+input_queue_per_port, "(pronoc_pkg::CAST_TYPE != "UNICAST")"
+  A left 112-bit expression is compared to a right 56-bit expression.
+  Comparing 'pronoc_pkg::CAST_TYPE' of type string
+  with '"UNICAST"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./input_ports.sv, 800
+input_queue_per_port, "(pronoc_pkg::TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'pronoc_pkg::TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./input_ports.sv, 800
+input_queue_per_port, "(pronoc_pkg::CAST_TYPE == "UNICAST")"
+  A left 112-bit expression is compared to a right 56-bit expression.
+  Comparing 'pronoc_pkg::CAST_TYPE' of type string
+  with '"UNICAST"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./input_ports.sv, 821
+input_queue_per_port, "(pronoc_pkg::TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'pronoc_pkg::TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./input_ports.sv, 821
+input_queue_per_port, "(pronoc_pkg::CAST_TYPE == "UNICAST")"
+  A left 112-bit expression is compared to a right 56-bit expression.
+  Comparing 'pronoc_pkg::CAST_TYPE' of type string
+  with '"UNICAST"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./input_ports.sv, 1026
+input_queue_per_port, "(pronoc_pkg::TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'pronoc_pkg::TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./input_ports.sv, 1026
+input_queue_per_port, "(pronoc_pkg::CAST_TYPE == "UNICAST")"
+  A left 112-bit expression is compared to a right 56-bit expression.
+  Comparing 'pronoc_pkg::CAST_TYPE' of type string
+  with '"UNICAST"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./flit_buffer.sv, 116
+flit_buffer, "(pronoc_pkg::CAST_TYPE != "UNICAST")"
+  A left 112-bit expression is compared to a right 56-bit expression.
+  Comparing 'pronoc_pkg::CAST_TYPE' of type string
+  with '"UNICAST"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./flit_buffer.sv, 141
+flit_buffer, "(pronoc_pkg::CAST_TYPE != "UNICAST")"
+  A left 112-bit expression is compared to a right 56-bit expression.
+  Comparing 'pronoc_pkg::CAST_TYPE' of type string
+  with '"UNICAST"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./flit_buffer.sv, 141
+flit_buffer, "(pronoc_pkg::CAST_TYPE != "UNICAST")"
+  A left 112-bit expression is compared to a right 56-bit expression.
+  Comparing 'pronoc_pkg::CAST_TYPE' of type string
+  with '"UNICAST"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./flit_buffer.sv, 247
+flit_buffer, "(pronoc_pkg::CAST_TYPE != "UNICAST")"
+  A left 112-bit expression is compared to a right 56-bit expression.
+  Comparing 'pronoc_pkg::CAST_TYPE' of type string
+  with '"UNICAST"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./flit_buffer.sv, 247
+flit_buffer, "(pronoc_pkg::CAST_TYPE != "UNICAST")"
+  A left 112-bit expression is compared to a right 56-bit expression.
+  Comparing 'pronoc_pkg::CAST_TYPE' of type string
+  with '"UNICAST"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./flit_buffer.sv, 379
+flit_buffer, "(pronoc_pkg::CAST_TYPE != "UNICAST")"
+  A left 112-bit expression is compared to a right 56-bit expression.
+  Comparing 'pronoc_pkg::CAST_TYPE' of type string
+  with '"UNICAST"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./flit_buffer.sv, 379
+flit_buffer, "(pronoc_pkg::CAST_TYPE != "UNICAST")"
+  A left 112-bit expression is compared to a right 56-bit expression.
+  Comparing 'pronoc_pkg::CAST_TYPE' of type string
+  with '"UNICAST"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./input_ports.sv, 1123
+destp_generator, "(CAST_TYPE != "UNICAST")"
+  A left 112-bit expression is compared to a right 56-bit expression.
+  Comparing 'CAST_TYPE' of type string
+  with '"UNICAST"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./comb_nonspec.sv, 721
+swa_output_port_arbiter, "(ARBITER_TYPE == "WRRA")"
+  A left 24-bit expression is compared to a right 32-bit expression.
+  Comparing 'ARBITER_TYPE' of type string
+  with '"WRRA"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./comb_nonspec.sv, 747
+swa_output_port_arbiter, "(ARBITER_TYPE == "WRRA_CLASSIC")"
+  A left 24-bit expression is compared to a right 96-bit expression.
+  Comparing 'ARBITER_TYPE' of type string
+  with '"WRRA_CLASSIC"' of type string.
+
+TimeScale is 1 ns / 1 ps
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./topology_localparam.v, 466
+pronoc_pkg, "(CAST_TYPE == "MULTICAST_PARTIAL")"
+  A left 112-bit expression is compared to a right 136-bit expression.
+  Comparing 'CAST_TYPE' of type string
+  with '"MULTICAST_PARTIAL"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./topology_localparam.v, 466
+pronoc_pkg, "(CAST_TYPE == "BROADCAST_PARTIAL")"
+  A left 112-bit expression is compared to a right 136-bit expression.
+  Comparing 'CAST_TYPE' of type string
+  with '"BROADCAST_PARTIAL"' of type string.
+
+
+Lint-[WMIA-L] Width mismatch in assignment
+./../../rtl/src_noc/./topology_localparam.v, 328
+  Width mismatch between LHS and RHS is found in assignment:
+  The following 32-bit wide expression is assigned to a 16-bit LHS target:
+  Source info: mcast_list = MCAST_ENDP_LIST;
+  Expression: mcast_list
+
+
+Lint-[WMIA-L] Width mismatch in assignment
+./../../rtl/src_noc/./topology_localparam.v, 356
+  Width mismatch between LHS and RHS is found in assignment:
+  The following 32-bit wide expression is assigned to a 16-bit LHS target:
+  Source info: mcast_list = MCAST_ENDP_LIST;
+  Expression: mcast_list
+
+
+Lint-[WMIA-L] Width mismatch in assignment
+./../../rtl/src_noc/./pronoc_pkg.sv, 300
+  Width mismatch between LHS and RHS is found in assignment:
+  The following 32-bit wide expression is assigned to a 2-bit LHS target:
+  Source info: hetero_ovc_unary = ((HETERO_VC == 0) ? {V {1'b1}} : ((HETERO_VC
+  == 1) ? ((1 << VC_CONFIG_TABLE[router_id][0]) - 1) : ((1 << 
+  VC_CONFIG_TABLE[router_id][router_ ...
+  Expression: hetero_ovc_unary
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./output_ports.sv, 555
+  Following is an unused input.
+  Source info: ssa_granted_ovc_num
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./router_two_stage.sv, 675
+credit_release_gen, "(counter == CREDIT_NUM)"
+  A left 3-bit expression is compared to a right 32-bit expression.
+  Comparing 'counter' of type reg [(W - 1):0]
+  with 'CREDIT_NUM' of type int.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./debug.v, 64
+check_flit_chanel_type_is_in_order, "(PCK_TYPE == "SINGLE_FLIT")"
+  A left 80-bit expression is compared to a right 88-bit expression.
+  Comparing 'PCK_TYPE' of type string
+  with '"SINGLE_FLIT"' of type string.
+
+
+Lint-[CAWM-L] Width mismatch
+./../../rtl/src_noc/./debug.v, 33
+  Continuous assignment width mismatch
+  2 bits (lhs) versus 32 bits (rhs).
+  Source info: assign vc_num_hdr_wr = ((hdr_flg_in & flit_in_wr) ? vc_num_in :
+  0);  
+
+
+Lint-[CAWM-L] Width mismatch
+./../../rtl/src_noc/./debug.v, 34
+  Continuous assignment width mismatch
+  2 bits (lhs) versus 32 bits (rhs).
+  Source info: assign vc_num_tail_wr = ((tail_flg_in & flit_in_wr) ? vc_num_in
+  : 0);  
+
+
+Lint-[CAWM-L] Width mismatch
+./../../rtl/src_noc/./debug.v, 35
+  Continuous assignment width mismatch
+  2 bits (lhs) versus 32 bits (rhs).
+  Source info: assign vc_num_bdy_wr = ((({hdr_flg_in, tail_flg_in} == 2'b0) &&
+  flit_in_wr) ? vc_num_in : 0);  
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./debug.v, 309
+debug_mesh_edges, "(current_rx == (T1 - 1))"
+  A left 2-bit expression is compared to a right 32-bit expression.
+  Comparing 'current_rx' of type wire [(RXw - 1):0]
+  with '(T1 - 1)' of type int.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./debug.v, 311
+debug_mesh_edges, "(current_ry == (T2 - 1))"
+  A left 2-bit expression is compared to a right 32-bit expression.
+  Comparing 'current_ry' of type wire [(RYw - 1):0]
+  with '(T2 - 1)' of type int.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 128
+"chan_in_all[mesh_torus.Y_[0].X_[0].EAST_ID]"
+  The select index is out of declared bounds : [15:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 133
+"chan_in_all[mesh_torus.Y_[0].X_[0].NORTH_ID]"
+  The select index is out of declared bounds : [15:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 138
+"chan_in_all[mesh_torus.Y_[0].X_[0].WEST_ID]"
+  The select index is out of declared bounds : [15:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 143
+"chan_in_all[mesh_torus.Y_[0].X_[0].SOUTH_ID]"
+  The select index is out of declared bounds : [15:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 128
+"chan_in_all[mesh_torus.Y_[0].X_[1].EAST_ID]"
+  The select index is out of declared bounds : [15:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 133
+"chan_in_all[mesh_torus.Y_[0].X_[1].NORTH_ID]"
+  The select index is out of declared bounds : [15:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 138
+"chan_in_all[mesh_torus.Y_[0].X_[1].WEST_ID]"
+  The select index is out of declared bounds : [15:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 143
+"chan_in_all[mesh_torus.Y_[0].X_[1].SOUTH_ID]"
+  The select index is out of declared bounds : [15:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 128
+"chan_in_all[mesh_torus.Y_[0].X_[2].EAST_ID]"
+  The select index is out of declared bounds : [15:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 133
+"chan_in_all[mesh_torus.Y_[0].X_[2].NORTH_ID]"
+  The select index is out of declared bounds : [15:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 138
+"chan_in_all[mesh_torus.Y_[0].X_[2].WEST_ID]"
+  The select index is out of declared bounds : [15:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 143
+"chan_in_all[mesh_torus.Y_[0].X_[2].SOUTH_ID]"
+  The select index is out of declared bounds : [15:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 128
+"chan_in_all[mesh_torus.Y_[0].X_[3].EAST_ID]"
+  The select index is out of declared bounds : [15:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 133
+"chan_in_all[mesh_torus.Y_[0].X_[3].NORTH_ID]"
+  The select index is out of declared bounds : [15:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 138
+"chan_in_all[mesh_torus.Y_[0].X_[3].WEST_ID]"
+  The select index is out of declared bounds : [15:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 143
+"chan_in_all[mesh_torus.Y_[0].X_[3].SOUTH_ID]"
+  The select index is out of declared bounds : [15:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 128
+"chan_in_all[mesh_torus.Y_[1].X_[0].EAST_ID]"
+  The select index is out of declared bounds : [15:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 133
+"chan_in_all[mesh_torus.Y_[1].X_[0].NORTH_ID]"
+  The select index is out of declared bounds : [15:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 138
+"chan_in_all[mesh_torus.Y_[1].X_[0].WEST_ID]"
+  The select index is out of declared bounds : [15:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 143
+"chan_in_all[mesh_torus.Y_[1].X_[0].SOUTH_ID]"
+  The select index is out of declared bounds : [15:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 128
+"chan_in_all[mesh_torus.Y_[1].X_[1].EAST_ID]"
+  The select index is out of declared bounds : [15:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 133
+"chan_in_all[mesh_torus.Y_[1].X_[1].NORTH_ID]"
+  The select index is out of declared bounds : [15:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 138
+"chan_in_all[mesh_torus.Y_[1].X_[1].WEST_ID]"
+  The select index is out of declared bounds : [15:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 143
+"chan_in_all[mesh_torus.Y_[1].X_[1].SOUTH_ID]"
+  The select index is out of declared bounds : [15:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 128
+"chan_in_all[mesh_torus.Y_[1].X_[2].EAST_ID]"
+  The select index is out of declared bounds : [15:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 133
+"chan_in_all[mesh_torus.Y_[1].X_[2].NORTH_ID]"
+  The select index is out of declared bounds : [15:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 138
+"chan_in_all[mesh_torus.Y_[1].X_[2].WEST_ID]"
+  The select index is out of declared bounds : [15:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 143
+"chan_in_all[mesh_torus.Y_[1].X_[2].SOUTH_ID]"
+  The select index is out of declared bounds : [15:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 128
+"chan_in_all[mesh_torus.Y_[1].X_[3].EAST_ID]"
+  The select index is out of declared bounds : [15:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 133
+"chan_in_all[mesh_torus.Y_[1].X_[3].NORTH_ID]"
+  The select index is out of declared bounds : [15:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 138
+"chan_in_all[mesh_torus.Y_[1].X_[3].WEST_ID]"
+  The select index is out of declared bounds : [15:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 143
+"chan_in_all[mesh_torus.Y_[1].X_[3].SOUTH_ID]"
+  The select index is out of declared bounds : [15:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 128
+"chan_in_all[mesh_torus.Y_[2].X_[0].EAST_ID]"
+  The select index is out of declared bounds : [15:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 133
+"chan_in_all[mesh_torus.Y_[2].X_[0].NORTH_ID]"
+  The select index is out of declared bounds : [15:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 138
+"chan_in_all[mesh_torus.Y_[2].X_[0].WEST_ID]"
+  The select index is out of declared bounds : [15:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 143
+"chan_in_all[mesh_torus.Y_[2].X_[0].SOUTH_ID]"
+  The select index is out of declared bounds : [15:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 128
+"chan_in_all[mesh_torus.Y_[2].X_[1].EAST_ID]"
+  The select index is out of declared bounds : [15:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 133
+"chan_in_all[mesh_torus.Y_[2].X_[1].NORTH_ID]"
+  The select index is out of declared bounds : [15:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 138
+"chan_in_all[mesh_torus.Y_[2].X_[1].WEST_ID]"
+  The select index is out of declared bounds : [15:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 143
+"chan_in_all[mesh_torus.Y_[2].X_[1].SOUTH_ID]"
+  The select index is out of declared bounds : [15:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 128
+"chan_in_all[mesh_torus.Y_[2].X_[2].EAST_ID]"
+  The select index is out of declared bounds : [15:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 133
+"chan_in_all[mesh_torus.Y_[2].X_[2].NORTH_ID]"
+  The select index is out of declared bounds : [15:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 138
+"chan_in_all[mesh_torus.Y_[2].X_[2].WEST_ID]"
+  The select index is out of declared bounds : [15:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 143
+"chan_in_all[mesh_torus.Y_[2].X_[2].SOUTH_ID]"
+  The select index is out of declared bounds : [15:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 128
+"chan_in_all[mesh_torus.Y_[2].X_[3].EAST_ID]"
+  The select index is out of declared bounds : [15:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 133
+"chan_in_all[mesh_torus.Y_[2].X_[3].NORTH_ID]"
+  The select index is out of declared bounds : [15:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 138
+"chan_in_all[mesh_torus.Y_[2].X_[3].WEST_ID]"
+  The select index is out of declared bounds : [15:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 143
+"chan_in_all[mesh_torus.Y_[2].X_[3].SOUTH_ID]"
+  The select index is out of declared bounds : [15:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 128
+"chan_in_all[mesh_torus.Y_[3].X_[0].EAST_ID]"
+  The select index is out of declared bounds : [15:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 133
+"chan_in_all[mesh_torus.Y_[3].X_[0].NORTH_ID]"
+  The select index is out of declared bounds : [15:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 138
+"chan_in_all[mesh_torus.Y_[3].X_[0].WEST_ID]"
+  The select index is out of declared bounds : [15:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 143
+"chan_in_all[mesh_torus.Y_[3].X_[0].SOUTH_ID]"
+  The select index is out of declared bounds : [15:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 128
+"chan_in_all[mesh_torus.Y_[3].X_[1].EAST_ID]"
+  The select index is out of declared bounds : [15:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 133
+"chan_in_all[mesh_torus.Y_[3].X_[1].NORTH_ID]"
+  The select index is out of declared bounds : [15:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 138
+"chan_in_all[mesh_torus.Y_[3].X_[1].WEST_ID]"
+  The select index is out of declared bounds : [15:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 143
+"chan_in_all[mesh_torus.Y_[3].X_[1].SOUTH_ID]"
+  The select index is out of declared bounds : [15:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 128
+"chan_in_all[mesh_torus.Y_[3].X_[2].EAST_ID]"
+  The select index is out of declared bounds : [15:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 133
+"chan_in_all[mesh_torus.Y_[3].X_[2].NORTH_ID]"
+  The select index is out of declared bounds : [15:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 138
+"chan_in_all[mesh_torus.Y_[3].X_[2].WEST_ID]"
+  The select index is out of declared bounds : [15:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 143
+"chan_in_all[mesh_torus.Y_[3].X_[2].SOUTH_ID]"
+  The select index is out of declared bounds : [15:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 128
+"chan_in_all[mesh_torus.Y_[3].X_[3].EAST_ID]"
+  The select index is out of declared bounds : [15:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 133
+"chan_in_all[mesh_torus.Y_[3].X_[3].NORTH_ID]"
+  The select index is out of declared bounds : [15:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 138
+"chan_in_all[mesh_torus.Y_[3].X_[3].WEST_ID]"
+  The select index is out of declared bounds : [15:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 143
+"chan_in_all[mesh_torus.Y_[3].X_[3].SOUTH_ID]"
+  The select index is out of declared bounds : [15:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./router_top.sv, 289
+router_top, "(pronoc_pkg::CAST_TYPE != "UNICAST")"
+  A left 112-bit expression is compared to a right 56-bit expression.
+  Comparing 'pronoc_pkg::CAST_TYPE' of type string
+  with '"UNICAST"' of type string.
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./inout_ports.sv, 116
+  Following is an unused input.
+  Source info: spec_ovc_num_all
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./inout_ports.sv, 118
+  Following is an unused input.
+  Source info: spec_first_arbiter_granted_ivc_all
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./inout_ports.sv, 120
+  Following is an unused input.
+  Source info: spec_granted_dest_port_all
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./output_ports.sv, 88
+  Following is an unused input.
+  Source info: crossbar_flit_out_wr_all
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./congestion_analyzer.v, 351
+  Following is an unused input.
+  Source info: ovc_status
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./congestion_analyzer.v, 352
+  Following is an unused input.
+  Source info: ovc_avalable_all
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./congestion_analyzer.v, 353
+  Following is an unused input.
+  Source info: credit_decreased_all
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./congestion_analyzer.v, 354
+  Following is an unused input.
+  Source info: credit_increased_all
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./congestion_analyzer.v, 355
+  Following is an unused input.
+  Source info: congestion_in_all
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./congestion_analyzer.v, 356
+  Following is an unused input.
+  Source info: reset
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./congestion_analyzer.v, 356
+  Following is an unused input.
+  Source info: clk
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./inout_ports.sv, 464
+  Following is an unused input.
+  Source info: port_pre_sel
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./inout_ports.sv, 467
+  Following is an unused input.
+  Source info: reset
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./inout_ports.sv, 468
+  Following is an unused input.
+  Source info: clk
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./inout_ports.sv, 471
+  Following is an unused input.
+  Source info: ivc_num_getting_ovc_grant
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./congestion_analyzer.v, 965
+  Following is an unused input.
+  Source info: ovc_avalable_all
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./congestion_analyzer.v, 966
+  Following is an unused input.
+  Source info: ivc_request_all
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./congestion_analyzer.v, 967
+  Following is an unused input.
+  Source info: ivc_num_getting_sw_grant
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./debug.v, 574
+check_pck_size, "(vc_num_in == i)"
+  A left 2-bit expression is compared to a right 32-bit expression.
+  Comparing 'vc_num_in' of type wire [(V - 1):0]
+  with 'i' of type integer.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./debug.v, 574
+check_pck_size, "(vc_num_in == 0)"
+  A left 2-bit expression is compared to a right 32-bit expression.
+  Comparing 'vc_num_in' of type wire [(V - 1):0]
+  with '0' of type int.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./debug.v, 590
+check_pck_size, "(vc_num_in == 0)"
+  A left 2-bit expression is compared to a right 32-bit expression.
+  Comparing 'vc_num_in' of type wire [(V - 1):0]
+  with '0' of type int.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./debug.v, 629
+check_pck_size, "(vc_num_in == 0)"
+  A left 2-bit expression is compared to a right 32-bit expression.
+  Comparing 'vc_num_in' of type wire [(V - 1):0]
+  with '0' of type int.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./debug.v, 574
+check_pck_size, "(vc_num_in == 1)"
+  A left 2-bit expression is compared to a right 32-bit expression.
+  Comparing 'vc_num_in' of type wire [(V - 1):0]
+  with '1' of type int.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./debug.v, 590
+check_pck_size, "(vc_num_in == 1)"
+  A left 2-bit expression is compared to a right 32-bit expression.
+  Comparing 'vc_num_in' of type wire [(V - 1):0]
+  with '1' of type int.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./debug.v, 629
+check_pck_size, "(vc_num_in == 1)"
+  A left 2-bit expression is compared to a right 32-bit expression.
+  Comparing 'vc_num_in' of type wire [(V - 1):0]
+  with '1' of type int.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./debug.v, 604
+check_pck_size, "(vc_num_in == 0)"
+  A left 2-bit expression is compared to a right 32-bit expression.
+  Comparing 'vc_num_in' of type wire [(V - 1):0]
+  with '0' of type int.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./debug.v, 604
+check_pck_size, "(vc_num_in == 1)"
+  A left 2-bit expression is compared to a right 32-bit expression.
+  Comparing 'vc_num_in' of type wire [(V - 1):0]
+  with '1' of type int.
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./multicast.sv, 477
+  Following is an unused input.
+  Source info: endp_port
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./multicast.sv, 602
+multicast_chan_in_process, "(pronoc_pkg::CAST_TYPE == "MULTICAST_PARTIAL")"
+  A left 112-bit expression is compared to a right 136-bit expression.
+  Comparing 'pronoc_pkg::CAST_TYPE' of type string
+  with '"MULTICAST_PARTIAL"' of type string.
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./multicast.sv, 477
+  Following is an unused input.
+  Source info: endp_port
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./multicast.sv, 602
+multicast_chan_in_process, "(pronoc_pkg::CAST_TYPE == "MULTICAST_PARTIAL")"
+  A left 112-bit expression is compared to a right 136-bit expression.
+  Comparing 'pronoc_pkg::CAST_TYPE' of type string
+  with '"MULTICAST_PARTIAL"' of type string.
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./multicast.sv, 477
+  Following is an unused input.
+  Source info: endp_port
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./multicast.sv, 602
+multicast_chan_in_process, "(pronoc_pkg::CAST_TYPE == "MULTICAST_PARTIAL")"
+  A left 112-bit expression is compared to a right 136-bit expression.
+  Comparing 'pronoc_pkg::CAST_TYPE' of type string
+  with '"MULTICAST_PARTIAL"' of type string.
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./multicast.sv, 477
+  Following is an unused input.
+  Source info: endp_port
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./multicast.sv, 602
+multicast_chan_in_process, "(pronoc_pkg::CAST_TYPE == "MULTICAST_PARTIAL")"
+  A left 112-bit expression is compared to a right 136-bit expression.
+  Comparing 'pronoc_pkg::CAST_TYPE' of type string
+  with '"MULTICAST_PARTIAL"' of type string.
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./multicast.sv, 477
+  Following is an unused input.
+  Source info: endp_port
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./multicast.sv, 602
+multicast_chan_in_process, "(pronoc_pkg::CAST_TYPE == "MULTICAST_PARTIAL")"
+  A left 112-bit expression is compared to a right 136-bit expression.
+  Comparing 'pronoc_pkg::CAST_TYPE' of type string
+  with '"MULTICAST_PARTIAL"' of type string.
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./input_ports.sv, 273
+  Following is an unused input.
+  Source info: refresh_w_counter
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./input_ports.sv, 274
+  Following is an unused input.
+  Source info: granted_dest_port
+
+
+Lint-[WMIA-L] Width mismatch in assignment
+./../../rtl/src_noc/./input_ports.sv, 379
+  Width mismatch between LHS and RHS is found in assignment:
+  The following 32-bit wide expression is assigned to a 4-bit LHS target:
+  Source info: iport_weight_next = ((weight_in == {pronoc_pkg::WEIGHTw 
+  {1'b0}}) ? 1 : weight_in);
+  Expression: iport_weight_next
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./header_flit.sv, 222
+  Following is an unused input.
+  Source info: sel
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./header_flit.sv, 223
+  Following is an unused input.
+  Source info: any_ivc_sw_request_granted
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./header_flit.sv, 224
+  Following is an unused input.
+  Source info: lk_dest_not_registered
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./output_ports.sv, 639
+  Following is an unused input.
+  Source info: reset
+
+
+Lint-[CAWM-L] Width mismatch
+./../../rtl/src_noc/./output_ports.sv, 648
+  Continuous assignment width mismatch
+  2 bits (lhs) versus 32 bits (rhs).
+  Source info: assign assigned_ovc_num[0] = (ovc_is_assigned_all[0] ? 
+  assigned_ovc_num_all[(((0 + 1) * V) - 1):(0 * V)] : 0);  
+
+
+Lint-[CAWM-L] Width mismatch
+./../../rtl/src_noc/./output_ports.sv, 648
+  Continuous assignment width mismatch
+  2 bits (lhs) versus 32 bits (rhs).
+  Source info: assign assigned_ovc_num[1] = (ovc_is_assigned_all[1] ? 
+  assigned_ovc_num_all[(((1 + 1) * V) - 1):(1 * V)] : 0);  
+
+
+Lint-[CAWM-L] Width mismatch
+./../../rtl/src_noc/./output_ports.sv, 648
+  Continuous assignment width mismatch
+  2 bits (lhs) versus 32 bits (rhs).
+  Source info: assign assigned_ovc_num[2] = (ovc_is_assigned_all[2] ? 
+  assigned_ovc_num_all[(((2 + 1) * V) - 1):(2 * V)] : 0);  
+
+
+Lint-[CAWM-L] Width mismatch
+./../../rtl/src_noc/./output_ports.sv, 648
+  Continuous assignment width mismatch
+  2 bits (lhs) versus 32 bits (rhs).
+  Source info: assign assigned_ovc_num[3] = (ovc_is_assigned_all[3] ? 
+  assigned_ovc_num_all[(((3 + 1) * V) - 1):(3 * V)] : 0);  
+
+
+Lint-[CAWM-L] Width mismatch
+./../../rtl/src_noc/./output_ports.sv, 648
+  Continuous assignment width mismatch
+  2 bits (lhs) versus 32 bits (rhs).
+  Source info: assign assigned_ovc_num[4] = (ovc_is_assigned_all[4] ? 
+  assigned_ovc_num_all[(((4 + 1) * V) - 1):(4 * V)] : 0);  
+
+
+Lint-[CAWM-L] Width mismatch
+./../../rtl/src_noc/./output_ports.sv, 648
+  Continuous assignment width mismatch
+  2 bits (lhs) versus 32 bits (rhs).
+  Source info: assign assigned_ovc_num[5] = (ovc_is_assigned_all[5] ? 
+  assigned_ovc_num_all[(((5 + 1) * V) - 1):(5 * V)] : 0);  
+
+
+Lint-[CAWM-L] Width mismatch
+./../../rtl/src_noc/./output_ports.sv, 648
+  Continuous assignment width mismatch
+  2 bits (lhs) versus 32 bits (rhs).
+  Source info: assign assigned_ovc_num[6] = (ovc_is_assigned_all[6] ? 
+  assigned_ovc_num_all[(((6 + 1) * V) - 1):(6 * V)] : 0);  
+
+
+Lint-[CAWM-L] Width mismatch
+./../../rtl/src_noc/./output_ports.sv, 648
+  Continuous assignment width mismatch
+  2 bits (lhs) versus 32 bits (rhs).
+  Source info: assign assigned_ovc_num[7] = (ovc_is_assigned_all[7] ? 
+  assigned_ovc_num_all[(((7 + 1) * V) - 1):(7 * V)] : 0);  
+
+
+Lint-[CAWM-L] Width mismatch
+./../../rtl/src_noc/./output_ports.sv, 648
+  Continuous assignment width mismatch
+  2 bits (lhs) versus 32 bits (rhs).
+  Source info: assign assigned_ovc_num[8] = (ovc_is_assigned_all[8] ? 
+  assigned_ovc_num_all[(((8 + 1) * V) - 1):(8 * V)] : 0);  
+
+
+Lint-[CAWM-L] Width mismatch
+./../../rtl/src_noc/./output_ports.sv, 648
+  Continuous assignment width mismatch
+  2 bits (lhs) versus 32 bits (rhs).
+  Source info: assign assigned_ovc_num[9] = (ovc_is_assigned_all[9] ? 
+  assigned_ovc_num_all[(((9 + 1) * V) - 1):(9 * V)] : 0);  
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./comb_nonspec.sv, 460
+  Following is an unused input.
+  Source info: pck_is_single_flit_all
+
+
+Lint-[WMIA-L] Width mismatch in assignment
+./../../rtl/src_noc/./../main_comp.v, 378
+  Width mismatch between LHS and RHS is found in assignment:
+  The following 32-bit wide expression is assigned to a 5-bit LHS target:
+  Source info: sum = 0;
+  Expression: sum
+
+
+Lint-[WMIA-L] Width mismatch in assignment
+./../../rtl/src_noc/./../main_comp.v, 378
+  Width mismatch between LHS and RHS is found in assignment:
+  The following 32-bit wide expression is assigned to a 4-bit LHS target:
+  Source info: sum = 0;
+  Expression: sum
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./multicast.sv, 127
+multicast_routing_mesh, "(current_rx > 0)"
+  A left 2-bit expression is compared to a right 32-bit expression.
+  Comparing 'current_rx' of type wire [(RXw - 1):0]
+  with '0' of type int.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./multicast.sv, 129
+multicast_routing_mesh, "(current_rx < 0)"
+  A left 2-bit expression is compared to a right 32-bit expression.
+  Comparing 'current_rx' of type wire [(RXw - 1):0]
+  with '0' of type int.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./multicast.sv, 127
+multicast_routing_mesh, "(current_rx > 1)"
+  A left 2-bit expression is compared to a right 32-bit expression.
+  Comparing 'current_rx' of type wire [(RXw - 1):0]
+  with '1' of type int.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./multicast.sv, 129
+multicast_routing_mesh, "(current_rx < 1)"
+  A left 2-bit expression is compared to a right 32-bit expression.
+  Comparing 'current_rx' of type wire [(RXw - 1):0]
+  with '1' of type int.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./multicast.sv, 127
+multicast_routing_mesh, "(current_rx > 2)"
+  A left 2-bit expression is compared to a right 32-bit expression.
+  Comparing 'current_rx' of type wire [(RXw - 1):0]
+  with '2' of type int.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./multicast.sv, 129
+multicast_routing_mesh, "(current_rx < 2)"
+  A left 2-bit expression is compared to a right 32-bit expression.
+  Comparing 'current_rx' of type wire [(RXw - 1):0]
+  with '2' of type int.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./multicast.sv, 127
+multicast_routing_mesh, "(current_rx > 3)"
+  A left 2-bit expression is compared to a right 32-bit expression.
+  Comparing 'current_rx' of type wire [(RXw - 1):0]
+  with '3' of type int.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./multicast.sv, 129
+multicast_routing_mesh, "(current_rx < 3)"
+  A left 2-bit expression is compared to a right 32-bit expression.
+  Comparing 'current_rx' of type wire [(RXw - 1):0]
+  with '3' of type int.
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./input_ports.sv, 1114
+  Following is an unused input.
+  Source info: endp_localp_num
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./input_ports.sv, 1117
+  Following is an unused input.
+  Source info: swap_port_presel
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./input_ports.sv, 1118
+  Following is an unused input.
+  Source info: port_pre_sel
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./input_ports.sv, 1119
+  Following is an unused input.
+  Source info: odd_column
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./flit_buffer.sv, 855
+fwft_fifo_with_output_clear, "(IGNORE_SAME_LOC_RD_WR_WARNING == "NO")"
+  A left 24-bit expression is compared to a right 16-bit expression.
+  Comparing 'IGNORE_SAME_LOC_RD_WR_WARNING' of type bit [23:0]
+  with '"NO"' of type string.
+
+
+Lint-[CAWM-L] Width mismatch
+./../../rtl/src_noc/./flit_buffer.sv, 797
+  Continuous assignment width mismatch
+  2 bits (lhs) versus 32 bits (rhs).
+  Source info: assign mwb2.depth_2 = (depth - 'd2);  
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./comb_nonspec.sv, 634
+  Following is an unused input.
+  Source info: vc_weight_is_consumed
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./comb_nonspec.sv, 717
+  Following is an unused input.
+  Source info: weight_consumed
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./input_ports.sv, 273
+  Following is an unused input.
+  Source info: refresh_w_counter
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./input_ports.sv, 274
+  Following is an unused input.
+  Source info: granted_dest_port
+
+
+Lint-[WMIA-L] Width mismatch in assignment
+./../../rtl/src_noc/./input_ports.sv, 379
+  Width mismatch between LHS and RHS is found in assignment:
+  The following 32-bit wide expression is assigned to a 4-bit LHS target:
+  Source info: iport_weight_next = ((weight_in == {pronoc_pkg::WEIGHTw 
+  {1'b0}}) ? 1 : weight_in);
+  Expression: iport_weight_next
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./input_ports.sv, 273
+  Following is an unused input.
+  Source info: refresh_w_counter
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./input_ports.sv, 274
+  Following is an unused input.
+  Source info: granted_dest_port
+
+
+Lint-[WMIA-L] Width mismatch in assignment
+./../../rtl/src_noc/./input_ports.sv, 379
+  Width mismatch between LHS and RHS is found in assignment:
+  The following 32-bit wide expression is assigned to a 4-bit LHS target:
+  Source info: iport_weight_next = ((weight_in == {pronoc_pkg::WEIGHTw 
+  {1'b0}}) ? 1 : weight_in);
+  Expression: iport_weight_next
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./input_ports.sv, 273
+  Following is an unused input.
+  Source info: refresh_w_counter
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./input_ports.sv, 274
+  Following is an unused input.
+  Source info: granted_dest_port
+
+
+Lint-[WMIA-L] Width mismatch in assignment
+./../../rtl/src_noc/./input_ports.sv, 379
+  Width mismatch between LHS and RHS is found in assignment:
+  The following 32-bit wide expression is assigned to a 4-bit LHS target:
+  Source info: iport_weight_next = ((weight_in == {pronoc_pkg::WEIGHTw 
+  {1'b0}}) ? 1 : weight_in);
+  Expression: iport_weight_next
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./input_ports.sv, 273
+  Following is an unused input.
+  Source info: refresh_w_counter
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./input_ports.sv, 274
+  Following is an unused input.
+  Source info: granted_dest_port
+
+
+Lint-[WMIA-L] Width mismatch in assignment
+./../../rtl/src_noc/./input_ports.sv, 379
+  Width mismatch between LHS and RHS is found in assignment:
+  The following 32-bit wide expression is assigned to a 4-bit LHS target:
+  Source info: iport_weight_next = ((weight_in == {pronoc_pkg::WEIGHTw 
+  {1'b0}}) ? 1 : weight_in);
+  Expression: iport_weight_next
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./input_ports.sv, 1114
+  Following is an unused input.
+  Source info: endp_localp_num
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./input_ports.sv, 1117
+  Following is an unused input.
+  Source info: swap_port_presel
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./input_ports.sv, 1118
+  Following is an unused input.
+  Source info: port_pre_sel
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./input_ports.sv, 1119
+  Following is an unused input.
+  Source info: odd_column
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./input_ports.sv, 1114
+  Following is an unused input.
+  Source info: endp_localp_num
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./input_ports.sv, 1117
+  Following is an unused input.
+  Source info: swap_port_presel
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./input_ports.sv, 1118
+  Following is an unused input.
+  Source info: port_pre_sel
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./input_ports.sv, 1119
+  Following is an unused input.
+  Source info: odd_column
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./input_ports.sv, 1114
+  Following is an unused input.
+  Source info: endp_localp_num
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./input_ports.sv, 1117
+  Following is an unused input.
+  Source info: swap_port_presel
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./input_ports.sv, 1118
+  Following is an unused input.
+  Source info: port_pre_sel
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./input_ports.sv, 1119
+  Following is an unused input.
+  Source info: odd_column
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./input_ports.sv, 1114
+  Following is an unused input.
+  Source info: endp_localp_num
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./input_ports.sv, 1117
+  Following is an unused input.
+  Source info: swap_port_presel
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./input_ports.sv, 1118
+  Following is an unused input.
+  Source info: port_pre_sel
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./input_ports.sv, 1119
+  Following is an unused input.
+  Source info: odd_column
+
+Starting vcs inline pass...
+
+41 modules and 0 UDP read.
+Generating code for _VCSgd_reYIK
+Generating code for _VCSgd_bQrwm
+recompiling package pronoc_pkg
+Generating code for _VCSgd_UU20K
+recompiling module pronoc_register
+Generating code for _VCSgd_Z5xzz
+Generating code for _VCSgd_wJnV0
+Generating code for _VCSgd_sGFGA
+recompiling module one_hot_demux
+Generating code for _VCSgd_j3CNv
+Generating code for _VCSgd_PFE93
+recompiling module custom_or
+Generating code for _VCSgd_rxxii
+recompiling module one_hot_to_bin
+Generating code for _VCSgd_tmkfi
+Generating code for _VCSgd_z7NBD
+recompiling module binary_mux
+Generating code for _VCSgd_qQN2B
+recompiling module is_onehot0
+Generating code for _VCSgd_h0Zyk
+Generating code for _VCSgd_w7hk8
+recompiling module arbiter
+Generating code for _VCSgd_Z8Hg1
+recompiling module arbiter_2_one_hot
+Generating code for _VCSgd_jLwrn
+recompiling module extract_header_flit_info
+Generating code for _VCSgd_Ly3qd
+recompiling module header_flit_update_lk_route_ovc
+Generating code for _VCSgd_ECtRV
+recompiling module noc_top
+Generating code for _VCSgd_qubHr
+recompiling module comb_nonspec_allocator
+Generating code for _VCSgd_dmk1W
+recompiling module swa_input_port_arbiter
+Generating code for _VCSgd_wLDGV
+recompiling module swa_output_port_arbiter
+Generating code for _VCSgd_AW5ic
+recompiling module inout_ports
+Generating code for _VCSgd_xNBkF
+recompiling module vc_alloc_request_gen
+Generating code for _VCSgd_bzyYs
+recompiling module input_ports
+Generating code for _VCSgd_at0sD
+recompiling module input_queue_per_port
+Generating code for _VCSgd_vPvg3
+Generating code for _VCSgd_TypBP
+Generating code for _VCSgd_SQwq4
+Generating code for _VCSgd_hJjVQ
+Generating code for _VCSgd_sPxW2
+recompiling module destp_generator
+Generating code for _VCSgd_k7SJc
+Generating code for _VCSgd_g9A6z
+Generating code for _VCSgd_DJdxW
+Generating code for _VCSgd_r6P8n
+Generating code for _VCSgd_pnIHZ
+recompiling module combined_vc_sw_alloc
+Generating code for _VCSgd_pKUfH
+recompiling module add_sw_loc_one_hot
+Generating code for _VCSgd_ihbcT
+recompiling module onehot_mux_1D
+Generating code for _VCSgd_wje7W
+Generating code for _VCSgd_ZzZJM
+Generating code for _VCSgd_etkVB
+Generating code for _VCSgd_ER2NJ
+Generating code for _VCSgd_UfJB9
+recompiling module header_flit_info
+Generating code for _VCSgd_D067Y
+recompiling module port_pre_sel_gen
+Generating code for _VCSgd_InS4s
+recompiling module output_ports
+Generating code for _VCSgd_IhnxI
+recompiling module credit_monitor_per_ovc
+Generating code for _VCSgd_UPPPJ
+recompiling module oport_ovc_sig_gen
+Generating code for _VCSgd_iMQv0
+recompiling module full_ovc_predictor
+Generating code for _VCSgd_VEJYp
+recompiling module check_ovc
+Generating code for _VCSgd_Nx31A
+recompiling module router_two_stage
+Generating code for _VCSgd_QCD2e
+recompiling module credit_release_gen
+Generating code for _VCSgd_Mtzs7
+recompiling module flit_buffer
+Generating code for _VCSgd_EeYFQ
+recompiling module fwft_fifo_with_output_clear
+Generating code for _VCSgd_YhjUR
+recompiling module check_flit_chanel_type_is_in_order
+Generating code for _VCSgd_bcNyr
+recompiling module debug_mesh_edges
+Generating code for _VCSgd_C3wbF
+recompiling module check_pck_size
+Generating code for _VCSgd_sIT4b
+recompiling module router_top
+Generating code for _VCSgd_J4kZy
+recompiling module mesh_torus_noc_top
+Generating code for _VCSgd_hnFVh
+recompiling module multicast_routing
+Generating code for _VCSgd_zjIbJ
+recompiling module multicast_dst_sel
+All of 41 modules done
+make: Warning: File 'filelist.hsopt.llvm2_0.objs' has modification time 55 s in the future
+make: warning:  Clock skew detected.  Your build may be incomplete.
+make: Warning: File 'filelist.cu' has modification time 54 s in the future
+make[1]: Warning: File 'filelist.cu' has modification time 54 s in the future
+rm -f _cuarc*.so _csrc*.so pre_vcsobj_*.so share_vcsobj_*.so
+make[1]: warning:  Clock skew detected.  Your build may be incomplete.
+make[1]: Warning: File 'filelist.cu' has modification time 54 s in the future
+make[1]: warning:  Clock skew detected.  Your build may be incomplete.
+if [ -x /users/amonemi/ProNoC/mpsoc/Integration_test/VCS/result_logs/work/simv ]; then chmod a-x /users/amonemi/ProNoC/mpsoc/Integration_test/VCS/result_logs/work/simv; fi
+g++  -o /users/amonemi/ProNoC/mpsoc/Integration_test/VCS/result_logs/work/simv   -no-pie    -rdynamic  -Wl,-rpath='$ORIGIN'/simv.daidir -Wl,-rpath=./simv.daidir -Wl,-rpath=/eda/synopsys/2022-23/RHELx86/VCS_2022.06-SP2/linux64/lib -L/eda/synopsys/2022-23/RHELx86/VCS_2022.06-SP2/linux64/lib  -Wl,-rpath-link=./ -Wl,--no-as-needed   objs/amcQw_d.o   _1512038_archive_1.so _prev_archive_1.so  SIM_l.o       rmapats_mop.o rmapats.o rmar.o rmar_nd.o  rmar_llvm_0_1.o rmar_llvm_0_0.o            -lnuma -lvirsim -lerrorinf -lsnpsmalloc -lvfs    -lvcsnew -lsimprofile -luclinative /eda/synopsys/2022-23/RHELx86/VCS_2022.06-SP2/linux64/lib/vcs_tls.o   -Wl,-whole-archive  -lvcsucli    -Wl,-no-whole-archive        _vcs_pli_stub_.o   /eda/synopsys/2022-23/RHELx86/VCS_2022.06-SP2/linux64/lib/vcs_save_restore_new.o /eda/synopsys/2022-23/RHELx86/VERDI_2022.06-SP2/share/PLI/VCS/LINUX64/pli.a -ldl  -lc -lm -lpthread -ldl 
+/users/amonemi/ProNoC/mpsoc/Integration_test/VCS/result_logs/work/simv up to date
+make: warning:  Clock skew detected.  Your build may be incomplete.
+Verdi KDB elaboration done and the database successfully generated: 0 error(s), 0 warning(s)
diff --git a/mpsoc/Integration_test/VCS/Golden_ref/mesh_4x4_2cycle_xy_v2.log b/mpsoc/Integration_test/VCS/Golden_ref/mesh_4x4_2cycle_xy_v2.log
new file mode 100644
index 0000000..9dd7128
--- /dev/null
+++ b/mpsoc/Integration_test/VCS/Golden_ref/mesh_4x4_2cycle_xy_v2.log
@@ -0,0 +1,3020 @@
+Use of uninitialized value $ENV{"PRONOC_WORK"} in concatenation (.) or string at /users/amonemi/ProNoC/mpsoc/Integration_test/VCS/src/../../synthetic_sim/src/src.pl line 24.
+Use of uninitialized value $ENV{"PRONOC_WORK"} in concatenation (.) or string at /users/amonemi/ProNoC/mpsoc/Integration_test/VCS/src/../../synthetic_sim/src/src.pl line 25.
+Use of uninitialized value $ENV{"PRONOC_WORK"} in concatenation (.) or string at /users/amonemi/ProNoC/mpsoc/Integration_test/VCS/src/../../synthetic_sim/src/src.pl line 26.
+Script Path: /users/amonemi/ProNoC/mpsoc/Integration_test/VCS/src/../../synthetic_sim/src
+confs_dir: /users/amonemi/ProNoC/mpsoc/Integration_test/synthetic_sim/configurations
+Root: /users/amonemi/ProNoC/mpsoc
+Parsing design file './../../rtl/src_noc/./pronoc_pkg.sv'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./pronoc_pkg.sv'.
+Parsing included file './src/noc_localparam.v'.
+Back to file './../../rtl/src_noc/./pronoc_pkg.sv'.
+Parsing included file './../../rtl/src_noc/./topology_localparam.v'.
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./topology_localparam.v'.
+Back to file './../../rtl/src_noc/./pronoc_pkg.sv'.
+Parsing design file './../../rtl/src_noc/./../main_comp.v'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./../main_comp.v'.
+Parsing design file './../../rtl/src_noc/./../arbiter.v'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./../arbiter.v'.
+Parsing design file './../../rtl/src_noc/./ovc_list.sv'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./ovc_list.sv'.
+Parsing design file './../../rtl/src_noc/./ss_allocator.sv'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./ss_allocator.sv'.
+Parsing design file './../../rtl/src_noc/./route_torus.v'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./route_torus.v'.
+Parsing design file './../../rtl/src_noc/./header_flit.sv'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./header_flit.sv'.
+Parsing design file './../../rtl/src_noc/./noc_top.sv'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./noc_top.sv'.
+Parsing design file './../../rtl/src_noc/./fattree_noc_top.sv'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./fattree_noc_top.sv'.
+Parsing design file './../../rtl/src_noc/./fattree_route.v'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./fattree_route.v'.
+Parsing design file './../../rtl/src_noc/./comb_nonspec.sv'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./comb_nonspec.sv'.
+Parsing design file './../../rtl/src_noc/./inout_ports.sv'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./inout_ports.sv'.
+Parsing design file './../../rtl/src_noc/./wrra.v'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./wrra.v'.
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./wrra.v'.
+Parsing design file './../../rtl/src_noc/./input_ports.sv'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./input_ports.sv'.
+Parsing design file './../../rtl/src_noc/./tree_noc_top.sv'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./tree_noc_top.sv'.
+Parsing design file './../../rtl/src_noc/./tree_route.v'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./tree_route.v'.
+Parsing design file './../../rtl/src_noc/./comb-spec1.v'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./comb-spec1.v'.
+Parsing design file './../../rtl/src_noc/./combined_vc_sw_alloc.sv'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./combined_vc_sw_alloc.sv'.
+Parsing design file './../../rtl/src_noc/./mesh_torus_routting.v'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./mesh_torus_routting.v'.
+Parsing design file './../../rtl/src_noc/./comb_spec2.v'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./comb_spec2.v'.
+Parsing design file './../../rtl/src_noc/./route_mesh.v'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./route_mesh.v'.
+Parsing design file './../../rtl/src_noc/./router_bypass.sv'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./router_bypass.sv'.
+Parsing design file './../../rtl/src_noc/./traffic_gen_top.sv'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./traffic_gen_top.sv'.
+Parsing design file './../../rtl/src_noc/./congestion_analyzer.v'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./congestion_analyzer.v'.
+Parsing design file './../../rtl/src_noc/./output_ports.sv'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./output_ports.sv'.
+Parsing design file './../../rtl/src_noc/./routing.v'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./routing.v'.
+Parsing design file './../../rtl/src_noc/./router_two_stage.sv'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./router_two_stage.sv'.
+Parsing design file './../../rtl/src_noc/./crossbar.v'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./crossbar.v'.
+Parsing design file './../../rtl/src_noc/./flit_buffer.sv'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./flit_buffer.sv'.
+Parsing design file './../../rtl/src_noc/./mesh_torus.sv'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./mesh_torus.sv'.
+Parsing design file './../../rtl/src_noc/./debug.v'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./debug.v'.
+Parsing design file './../../rtl/src_noc/./router_top.sv'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./router_top.sv'.
+Parsing design file './../../rtl/src_noc/./mesh_torus_noc_top.sv'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./mesh_torus_noc_top.sv'.
+Parsing design file './../../rtl/src_noc/./star_noc.sv'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./star_noc.sv'.
+Parsing design file './../../rtl/src_noc/./fmesh.sv'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./fmesh.sv'.
+Parsing design file './../../rtl/src_noc/./packet_injector.sv'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./packet_injector.sv'.
+Parsing design file './../../rtl/src_noc/./multicast.sv'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_noc/./multicast.sv'.
+Parsing design file './../../rtl/src_topology/./custom1/Tcustom1Rcustom_look_ahead_routing_genvar.v'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_topology/./custom1/Tcustom1Rcustom_look_ahead_routing_genvar.v'.
+Parsing design file './../../rtl/src_topology/./custom1/custom1_noc_genvar.sv'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_topology/./custom1/custom1_noc_genvar.sv'.
+Parsing design file './../../rtl/src_topology/./custom1/Tcustom1Rcustom_conventional_routing_genvar.v'
+Parsing design file './../../rtl/src_topology/./custom1/custom1_noc.sv'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_topology/./custom1/custom1_noc.sv'.
+Parsing design file './../../rtl/src_topology/./custom1/Tcustom1Rcustom_conventional_routing.v'
+Parsing design file './../../rtl/src_topology/./custom1/Tcustom1Rcustom_look_ahead_routing.v'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_topology/./custom1/Tcustom1Rcustom_look_ahead_routing.v'.
+Parsing design file './../../rtl/src_topology/./common/custom_ni_routing.v'
+Parsing design file './../../rtl/src_topology/./common/custom_noc_top.sv'
+Parsing included file './../../rtl/src_noc/./../pronoc_def.v'.
+Back to file './../../rtl/src_topology/./common/custom_noc_top.sv'.
+Parsing design file './../../rtl/src_topology/./common/custom_lkh_routing.v'
+Top Level Modules:
+       noc_top
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./topology_localparam.v, 16
+pronoc_pkg, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./topology_localparam.v, 17
+pronoc_pkg, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./topology_localparam.v, 18
+pronoc_pkg, "(TOPOLOGY == "FATTREE")"
+  A left 32-bit expression is compared to a right 56-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FATTREE"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./topology_localparam.v, 21
+pronoc_pkg, "(TOPOLOGY == "MULTI_MESH")"
+  A left 32-bit expression is compared to a right 80-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"MULTI_MESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./topology_localparam.v, 27
+pronoc_pkg, "(SWA_ARBITER_TYPE == "WRRA")"
+  A left 24-bit expression is compared to a right 32-bit expression.
+  Comparing 'SWA_ARBITER_TYPE' of type string
+  with '"WRRA"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./topology_localparam.v, 28
+pronoc_pkg, "(PCK_TYPE == "SINGLE_FLIT")"
+  A left 80-bit expression is compared to a right 88-bit expression.
+  Comparing 'PCK_TYPE' of type string
+  with '"SINGLE_FLIT"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./topology_localparam.v, 143
+pronoc_pkg, "(ROUTE_NAME == "TRANC_DOR")"
+  A left 16-bit expression is compared to a right 64-bit expression.
+  Comparing 'ROUTE_NAME' of type string
+  with '"TRANC_DOR"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./topology_localparam.v, 143
+pronoc_pkg, "(ROUTE_NAME == "FULL_ADPT")"
+  A left 16-bit expression is compared to a right 40-bit expression.
+  Comparing 'ROUTE_NAME' of type string
+  with '"FULL_ADPT"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./topology_localparam.v, 143
+pronoc_pkg, "(ROUTE_NAME == "TRANC_FULL_ADPT")"
+  A left 16-bit expression is compared to a right 88-bit expression.
+  Comparing 'ROUTE_NAME' of type string
+  with '"TRANC_FULL_ADPT"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./topology_localparam.v, 296
+pronoc_pkg, "(CAST_TYPE == "MULTICAST_FULL")"
+  A left 56-bit expression is compared to a right 112-bit expression.
+  Comparing 'CAST_TYPE' of type string
+  with '"MULTICAST_FULL"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./topology_localparam.v, 296
+pronoc_pkg, "(CAST_TYPE == "MULTICAST_PARTIAL")"
+  A left 56-bit expression is compared to a right 136-bit expression.
+  Comparing 'CAST_TYPE' of type string
+  with '"MULTICAST_PARTIAL"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./topology_localparam.v, 296
+pronoc_pkg, "(CAST_TYPE == "MULTICAST_PARTIAL")"
+  A left 56-bit expression is compared to a right 136-bit expression.
+  Comparing 'CAST_TYPE' of type string
+  with '"MULTICAST_PARTIAL"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./output_ports.sv, 128
+output_ports, "(pronoc_pkg::VC_REALLOCATION_TYPE == "ATOMIC")"
+  A left 72-bit expression is compared to a right 48-bit expression.
+  Comparing 'pronoc_pkg::VC_REALLOCATION_TYPE' of type string
+  with '"ATOMIC"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./combined_vc_sw_alloc.sv, 131
+combined_vc_sw_alloc, "(pronoc_pkg::COMBINATION_TYPE == "COMB_SPEC1")"
+  A left 96-bit expression is compared to a right 80-bit expression.
+  Comparing 'pronoc_pkg::COMBINATION_TYPE' of type string
+  with '"COMB_SPEC1"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./combined_vc_sw_alloc.sv, 167
+combined_vc_sw_alloc, "(pronoc_pkg::COMBINATION_TYPE == "COMB_SPEC2")"
+  A left 96-bit expression is compared to a right 80-bit expression.
+  Comparing 'pronoc_pkg::COMBINATION_TYPE' of type string
+  with '"COMB_SPEC2"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./crossbar.v, 115
+crossbar, "(MUX_TYPE == "ONE_HOT")"
+  A left 48-bit expression is compared to a right 56-bit expression.
+  Comparing 'MUX_TYPE' of type string
+  with '"ONE_HOT"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./crossbar.v, 115
+crossbar, "(MUX_TYPE == "ONE_HOT")"
+  A left 48-bit expression is compared to a right 56-bit expression.
+  Comparing 'MUX_TYPE' of type string
+  with '"ONE_HOT"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./crossbar.v, 115
+crossbar, "(MUX_TYPE == "ONE_HOT")"
+  A left 48-bit expression is compared to a right 56-bit expression.
+  Comparing 'MUX_TYPE' of type string
+  with '"ONE_HOT"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./crossbar.v, 115
+crossbar, "(MUX_TYPE == "ONE_HOT")"
+  A left 48-bit expression is compared to a right 56-bit expression.
+  Comparing 'MUX_TYPE' of type string
+  with '"ONE_HOT"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./crossbar.v, 115
+crossbar, "(MUX_TYPE == "ONE_HOT")"
+  A left 48-bit expression is compared to a right 56-bit expression.
+  Comparing 'MUX_TYPE' of type string
+  with '"ONE_HOT"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./input_ports.sv, 241
+input_queue_per_port, "(pronoc_pkg::VC_REALLOCATION_TYPE == "ATOMIC")"
+  A left 72-bit expression is compared to a right 48-bit expression.
+  Comparing 'pronoc_pkg::VC_REALLOCATION_TYPE' of type string
+  with '"ATOMIC"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./input_ports.sv, 406
+input_queue_per_port, "(pronoc_pkg::TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'pronoc_pkg::TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./input_ports.sv, 423
+input_queue_per_port, "(pronoc_pkg::TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'pronoc_pkg::TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./input_ports.sv, 441
+input_queue_per_port, "(pronoc_pkg::TOPOLOGY == "FATTREE")"
+  A left 32-bit expression is compared to a right 56-bit expression.
+  Comparing 'pronoc_pkg::TOPOLOGY' of type string
+  with '"FATTREE"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./input_ports.sv, 441
+input_queue_per_port, "(pronoc_pkg::ROUTE_NAME == "NCA_STRAIGHT_UP")"
+  A left 16-bit expression is compared to a right 120-bit expression.
+  Comparing 'pronoc_pkg::ROUTE_NAME' of type string
+  with '"NCA_STRAIGHT_UP"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./input_ports.sv, 800
+input_queue_per_port, "(pronoc_pkg::TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'pronoc_pkg::TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./input_ports.sv, 821
+input_queue_per_port, "(pronoc_pkg::TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'pronoc_pkg::TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./input_ports.sv, 800
+input_queue_per_port, "(pronoc_pkg::TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'pronoc_pkg::TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./input_ports.sv, 821
+input_queue_per_port, "(pronoc_pkg::TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'pronoc_pkg::TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./input_ports.sv, 1138
+destp_generator, "(TOPOLOGY == "FATTREE")"
+  A left 32-bit expression is compared to a right 56-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FATTREE"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./input_ports.sv, 1166
+destp_generator, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./routing.v, 287
+look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./routing.v, 287
+look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./routing.v, 314
+look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./routing.v, 287
+look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./routing.v, 287
+look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./routing.v, 314
+look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./routing.v, 287
+look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./routing.v, 287
+look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./routing.v, 314
+look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./routing.v, 287
+look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./routing.v, 287
+look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./routing.v, 314
+look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./routing.v, 287
+look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./routing.v, 287
+look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./routing.v, 314
+look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./comb_nonspec.sv, 721
+swa_output_port_arbiter, "(ARBITER_TYPE == "WRRA")"
+  A left 24-bit expression is compared to a right 32-bit expression.
+  Comparing 'ARBITER_TYPE' of type string
+  with '"WRRA"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./comb_nonspec.sv, 747
+swa_output_port_arbiter, "(ARBITER_TYPE == "WRRA_CLASSIC")"
+  A left 24-bit expression is compared to a right 96-bit expression.
+  Comparing 'ARBITER_TYPE' of type string
+  with '"WRRA_CLASSIC"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 28
+mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus.sv, 336
+mesh_torus_mask_non_assignable_destport_no_self_loop, "(ROUTE_NAME == "TRANC_DOR")"
+  A left 16-bit expression is compared to a right 64-bit expression.
+  Comparing 'ROUTE_NAME' of type string
+  with '"TRANC_DOR"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus.sv, 336
+mesh_torus_mask_non_assignable_destport_no_self_loop, "(ROUTE_NAME == "TRANC_DOR")"
+  A left 16-bit expression is compared to a right 64-bit expression.
+  Comparing 'ROUTE_NAME' of type string
+  with '"TRANC_DOR"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus.sv, 336
+mesh_torus_mask_non_assignable_destport_no_self_loop, "(ROUTE_NAME == "TRANC_DOR")"
+  A left 16-bit expression is compared to a right 64-bit expression.
+  Comparing 'ROUTE_NAME' of type string
+  with '"TRANC_DOR"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 146
+mesh_torus_deterministic_look_ahead_routing, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 146
+mesh_torus_deterministic_look_ahead_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 368
+mesh_torus_next_router_addr_predictor, "(TOPOLOGY == "TORUS")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"TORUS"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 368
+mesh_torus_next_router_addr_predictor, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./mesh_torus_routting.v, 638
+mesh_torus_conventional_routing, "(TOPOLOGY == "FMESH")"
+  A left 32-bit expression is compared to a right 40-bit expression.
+  Comparing 'TOPOLOGY' of type string
+  with '"FMESH"' of type string.
+
+TimeScale is 1 ns / 1 ps
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./topology_localparam.v, 466
+pronoc_pkg, "(CAST_TYPE == "MULTICAST_PARTIAL")"
+  A left 56-bit expression is compared to a right 136-bit expression.
+  Comparing 'CAST_TYPE' of type string
+  with '"MULTICAST_PARTIAL"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./topology_localparam.v, 466
+pronoc_pkg, "(CAST_TYPE == "BROADCAST_PARTIAL")"
+  A left 56-bit expression is compared to a right 136-bit expression.
+  Comparing 'CAST_TYPE' of type string
+  with '"BROADCAST_PARTIAL"' of type string.
+
+
+Lint-[WMIA-L] Width mismatch in assignment
+./../../rtl/src_noc/./topology_localparam.v, 328
+  Width mismatch between LHS and RHS is found in assignment:
+  The following 32-bit wide expression is assigned to a 16-bit LHS target:
+  Source info: mcast_list = MCAST_ENDP_LIST;
+  Expression: mcast_list
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./topology_localparam.v, 332
+pronoc_pkg, "(CAST_TYPE == "MULTICAST_FULL")"
+  A left 56-bit expression is compared to a right 112-bit expression.
+  Comparing 'CAST_TYPE' of type string
+  with '"MULTICAST_FULL"' of type string.
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./topology_localparam.v, 352
+pronoc_pkg, "(CAST_TYPE == "MULTICAST_FULL")"
+  A left 56-bit expression is compared to a right 112-bit expression.
+  Comparing 'CAST_TYPE' of type string
+  with '"MULTICAST_FULL"' of type string.
+
+
+Lint-[WMIA-L] Width mismatch in assignment
+./../../rtl/src_noc/./topology_localparam.v, 356
+  Width mismatch between LHS and RHS is found in assignment:
+  The following 32-bit wide expression is assigned to a 16-bit LHS target:
+  Source info: mcast_list = MCAST_ENDP_LIST;
+  Expression: mcast_list
+
+
+Lint-[WMIA-L] Width mismatch in assignment
+./../../rtl/src_noc/./pronoc_pkg.sv, 300
+  Width mismatch between LHS and RHS is found in assignment:
+  The following 32-bit wide expression is assigned to a 2-bit LHS target:
+  Source info: hetero_ovc_unary = ((HETERO_VC == 0) ? {V {1'b1}} : ((HETERO_VC
+  == 1) ? ((1 << VC_CONFIG_TABLE[router_id][0]) - 1) : ((1 << 
+  VC_CONFIG_TABLE[router_id][router_ ...
+  Expression: hetero_ovc_unary
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./output_ports.sv, 555
+  Following is an unused input.
+  Source info: ssa_granted_ovc_num
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./router_two_stage.sv, 675
+credit_release_gen, "(counter == CREDIT_NUM)"
+  A left 3-bit expression is compared to a right 32-bit expression.
+  Comparing 'counter' of type reg [(W - 1):0]
+  with 'CREDIT_NUM' of type int.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 128
+"chan_in_all[mesh_torus.Y_[0].X_[0].EAST_ID]"
+  The select index is out of declared bounds : [15:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 133
+"chan_in_all[mesh_torus.Y_[0].X_[0].NORTH_ID]"
+  The select index is out of declared bounds : [15:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 138
+"chan_in_all[mesh_torus.Y_[0].X_[0].WEST_ID]"
+  The select index is out of declared bounds : [15:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 143
+"chan_in_all[mesh_torus.Y_[0].X_[0].SOUTH_ID]"
+  The select index is out of declared bounds : [15:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 128
+"chan_in_all[mesh_torus.Y_[0].X_[1].EAST_ID]"
+  The select index is out of declared bounds : [15:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 133
+"chan_in_all[mesh_torus.Y_[0].X_[1].NORTH_ID]"
+  The select index is out of declared bounds : [15:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 138
+"chan_in_all[mesh_torus.Y_[0].X_[1].WEST_ID]"
+  The select index is out of declared bounds : [15:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 143
+"chan_in_all[mesh_torus.Y_[0].X_[1].SOUTH_ID]"
+  The select index is out of declared bounds : [15:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 128
+"chan_in_all[mesh_torus.Y_[0].X_[2].EAST_ID]"
+  The select index is out of declared bounds : [15:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 133
+"chan_in_all[mesh_torus.Y_[0].X_[2].NORTH_ID]"
+  The select index is out of declared bounds : [15:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 138
+"chan_in_all[mesh_torus.Y_[0].X_[2].WEST_ID]"
+  The select index is out of declared bounds : [15:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 143
+"chan_in_all[mesh_torus.Y_[0].X_[2].SOUTH_ID]"
+  The select index is out of declared bounds : [15:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 128
+"chan_in_all[mesh_torus.Y_[0].X_[3].EAST_ID]"
+  The select index is out of declared bounds : [15:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 133
+"chan_in_all[mesh_torus.Y_[0].X_[3].NORTH_ID]"
+  The select index is out of declared bounds : [15:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 138
+"chan_in_all[mesh_torus.Y_[0].X_[3].WEST_ID]"
+  The select index is out of declared bounds : [15:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 143
+"chan_in_all[mesh_torus.Y_[0].X_[3].SOUTH_ID]"
+  The select index is out of declared bounds : [15:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 128
+"chan_in_all[mesh_torus.Y_[1].X_[0].EAST_ID]"
+  The select index is out of declared bounds : [15:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 133
+"chan_in_all[mesh_torus.Y_[1].X_[0].NORTH_ID]"
+  The select index is out of declared bounds : [15:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 138
+"chan_in_all[mesh_torus.Y_[1].X_[0].WEST_ID]"
+  The select index is out of declared bounds : [15:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 143
+"chan_in_all[mesh_torus.Y_[1].X_[0].SOUTH_ID]"
+  The select index is out of declared bounds : [15:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 128
+"chan_in_all[mesh_torus.Y_[1].X_[1].EAST_ID]"
+  The select index is out of declared bounds : [15:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 133
+"chan_in_all[mesh_torus.Y_[1].X_[1].NORTH_ID]"
+  The select index is out of declared bounds : [15:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 138
+"chan_in_all[mesh_torus.Y_[1].X_[1].WEST_ID]"
+  The select index is out of declared bounds : [15:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 143
+"chan_in_all[mesh_torus.Y_[1].X_[1].SOUTH_ID]"
+  The select index is out of declared bounds : [15:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 128
+"chan_in_all[mesh_torus.Y_[1].X_[2].EAST_ID]"
+  The select index is out of declared bounds : [15:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 133
+"chan_in_all[mesh_torus.Y_[1].X_[2].NORTH_ID]"
+  The select index is out of declared bounds : [15:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 138
+"chan_in_all[mesh_torus.Y_[1].X_[2].WEST_ID]"
+  The select index is out of declared bounds : [15:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 143
+"chan_in_all[mesh_torus.Y_[1].X_[2].SOUTH_ID]"
+  The select index is out of declared bounds : [15:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 128
+"chan_in_all[mesh_torus.Y_[1].X_[3].EAST_ID]"
+  The select index is out of declared bounds : [15:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 133
+"chan_in_all[mesh_torus.Y_[1].X_[3].NORTH_ID]"
+  The select index is out of declared bounds : [15:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 138
+"chan_in_all[mesh_torus.Y_[1].X_[3].WEST_ID]"
+  The select index is out of declared bounds : [15:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 143
+"chan_in_all[mesh_torus.Y_[1].X_[3].SOUTH_ID]"
+  The select index is out of declared bounds : [15:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 128
+"chan_in_all[mesh_torus.Y_[2].X_[0].EAST_ID]"
+  The select index is out of declared bounds : [15:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 133
+"chan_in_all[mesh_torus.Y_[2].X_[0].NORTH_ID]"
+  The select index is out of declared bounds : [15:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 138
+"chan_in_all[mesh_torus.Y_[2].X_[0].WEST_ID]"
+  The select index is out of declared bounds : [15:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 143
+"chan_in_all[mesh_torus.Y_[2].X_[0].SOUTH_ID]"
+  The select index is out of declared bounds : [15:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 128
+"chan_in_all[mesh_torus.Y_[2].X_[1].EAST_ID]"
+  The select index is out of declared bounds : [15:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 133
+"chan_in_all[mesh_torus.Y_[2].X_[1].NORTH_ID]"
+  The select index is out of declared bounds : [15:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 138
+"chan_in_all[mesh_torus.Y_[2].X_[1].WEST_ID]"
+  The select index is out of declared bounds : [15:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 143
+"chan_in_all[mesh_torus.Y_[2].X_[1].SOUTH_ID]"
+  The select index is out of declared bounds : [15:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 128
+"chan_in_all[mesh_torus.Y_[2].X_[2].EAST_ID]"
+  The select index is out of declared bounds : [15:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 133
+"chan_in_all[mesh_torus.Y_[2].X_[2].NORTH_ID]"
+  The select index is out of declared bounds : [15:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 138
+"chan_in_all[mesh_torus.Y_[2].X_[2].WEST_ID]"
+  The select index is out of declared bounds : [15:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 143
+"chan_in_all[mesh_torus.Y_[2].X_[2].SOUTH_ID]"
+  The select index is out of declared bounds : [15:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 128
+"chan_in_all[mesh_torus.Y_[2].X_[3].EAST_ID]"
+  The select index is out of declared bounds : [15:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 133
+"chan_in_all[mesh_torus.Y_[2].X_[3].NORTH_ID]"
+  The select index is out of declared bounds : [15:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 138
+"chan_in_all[mesh_torus.Y_[2].X_[3].WEST_ID]"
+  The select index is out of declared bounds : [15:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 143
+"chan_in_all[mesh_torus.Y_[2].X_[3].SOUTH_ID]"
+  The select index is out of declared bounds : [15:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 128
+"chan_in_all[mesh_torus.Y_[3].X_[0].EAST_ID]"
+  The select index is out of declared bounds : [15:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 133
+"chan_in_all[mesh_torus.Y_[3].X_[0].NORTH_ID]"
+  The select index is out of declared bounds : [15:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 138
+"chan_in_all[mesh_torus.Y_[3].X_[0].WEST_ID]"
+  The select index is out of declared bounds : [15:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 143
+"chan_in_all[mesh_torus.Y_[3].X_[0].SOUTH_ID]"
+  The select index is out of declared bounds : [15:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 128
+"chan_in_all[mesh_torus.Y_[3].X_[1].EAST_ID]"
+  The select index is out of declared bounds : [15:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 133
+"chan_in_all[mesh_torus.Y_[3].X_[1].NORTH_ID]"
+  The select index is out of declared bounds : [15:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 138
+"chan_in_all[mesh_torus.Y_[3].X_[1].WEST_ID]"
+  The select index is out of declared bounds : [15:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 143
+"chan_in_all[mesh_torus.Y_[3].X_[1].SOUTH_ID]"
+  The select index is out of declared bounds : [15:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 128
+"chan_in_all[mesh_torus.Y_[3].X_[2].EAST_ID]"
+  The select index is out of declared bounds : [15:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 133
+"chan_in_all[mesh_torus.Y_[3].X_[2].NORTH_ID]"
+  The select index is out of declared bounds : [15:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 138
+"chan_in_all[mesh_torus.Y_[3].X_[2].WEST_ID]"
+  The select index is out of declared bounds : [15:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 143
+"chan_in_all[mesh_torus.Y_[3].X_[2].SOUTH_ID]"
+  The select index is out of declared bounds : [15:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 128
+"chan_in_all[mesh_torus.Y_[3].X_[3].EAST_ID]"
+  The select index is out of declared bounds : [15:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 133
+"chan_in_all[mesh_torus.Y_[3].X_[3].NORTH_ID]"
+  The select index is out of declared bounds : [15:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 138
+"chan_in_all[mesh_torus.Y_[3].X_[3].WEST_ID]"
+  The select index is out of declared bounds : [15:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 143
+"chan_in_all[mesh_torus.Y_[3].X_[3].SOUTH_ID]"
+  The select index is out of declared bounds : [15:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./inout_ports.sv, 116
+  Following is an unused input.
+  Source info: spec_ovc_num_all
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./inout_ports.sv, 118
+  Following is an unused input.
+  Source info: spec_first_arbiter_granted_ivc_all
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./inout_ports.sv, 120
+  Following is an unused input.
+  Source info: spec_granted_dest_port_all
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./output_ports.sv, 88
+  Following is an unused input.
+  Source info: crossbar_flit_out_wr_all
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./congestion_analyzer.v, 351
+  Following is an unused input.
+  Source info: ovc_status
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./congestion_analyzer.v, 352
+  Following is an unused input.
+  Source info: ovc_avalable_all
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./congestion_analyzer.v, 353
+  Following is an unused input.
+  Source info: credit_decreased_all
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./congestion_analyzer.v, 354
+  Following is an unused input.
+  Source info: credit_increased_all
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./congestion_analyzer.v, 355
+  Following is an unused input.
+  Source info: congestion_in_all
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./congestion_analyzer.v, 356
+  Following is an unused input.
+  Source info: reset
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./congestion_analyzer.v, 356
+  Following is an unused input.
+  Source info: clk
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./inout_ports.sv, 464
+  Following is an unused input.
+  Source info: port_pre_sel
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./inout_ports.sv, 467
+  Following is an unused input.
+  Source info: reset
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./inout_ports.sv, 468
+  Following is an unused input.
+  Source info: clk
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./inout_ports.sv, 471
+  Following is an unused input.
+  Source info: ivc_num_getting_ovc_grant
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./congestion_analyzer.v, 965
+  Following is an unused input.
+  Source info: ovc_avalable_all
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./congestion_analyzer.v, 966
+  Following is an unused input.
+  Source info: ivc_request_all
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./congestion_analyzer.v, 967
+  Following is an unused input.
+  Source info: ivc_num_getting_sw_grant
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./input_ports.sv, 273
+  Following is an unused input.
+  Source info: refresh_w_counter
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./input_ports.sv, 274
+  Following is an unused input.
+  Source info: granted_dest_port
+
+
+Lint-[WMIA-L] Width mismatch in assignment
+./../../rtl/src_noc/./input_ports.sv, 379
+  Width mismatch between LHS and RHS is found in assignment:
+  The following 32-bit wide expression is assigned to a 4-bit LHS target:
+  Source info: iport_weight_next = ((weight_in == {pronoc_pkg::WEIGHTw 
+  {1'b0}}) ? 1 : weight_in);
+  Expression: iport_weight_next
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./flit_buffer.sv, 80
+  Following is an unused input.
+  Source info: multiple_dest
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./flit_buffer.sv, 81
+  Following is an unused input.
+  Source info: sub_rd_ptr_ld
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./header_flit.sv, 222
+  Following is an unused input.
+  Source info: sel
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./header_flit.sv, 223
+  Following is an unused input.
+  Source info: any_ivc_sw_request_granted
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./header_flit.sv, 224
+  Following is an unused input.
+  Source info: lk_dest_not_registered
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./comb_nonspec.sv, 460
+  Following is an unused input.
+  Source info: pck_is_single_flit_all
+
+
+Lint-[ULCO] Unequal length in comparison operator
+./../../rtl/src_noc/./flit_buffer.sv, 680
+fwft_fifo, "(IGNORE_SAME_LOC_RD_WR_WARNING == "NO")"
+  A left 24-bit expression is compared to a right 16-bit expression.
+  Comparing 'IGNORE_SAME_LOC_RD_WR_WARNING' of type bit [23:0]
+  with '"NO"' of type string.
+
+
+Lint-[CAWM-L] Width mismatch
+./../../rtl/src_noc/./flit_buffer.sv, 631
+  Continuous assignment width mismatch
+  2 bits (lhs) versus 32 bits (rhs).
+  Source info: assign mwb2.depth_2 = (depth - 2);  
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./routing.v, 276
+  Following is an unused input.
+  Source info: neighbors_r_addr
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./routing.v, 279
+  Following is an unused input.
+  Source info: src_e_addr
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./routing.v, 276
+  Following is an unused input.
+  Source info: neighbors_r_addr
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./routing.v, 279
+  Following is an unused input.
+  Source info: src_e_addr
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./routing.v, 276
+  Following is an unused input.
+  Source info: neighbors_r_addr
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./routing.v, 279
+  Following is an unused input.
+  Source info: src_e_addr
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./routing.v, 276
+  Following is an unused input.
+  Source info: neighbors_r_addr
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./routing.v, 279
+  Following is an unused input.
+  Source info: src_e_addr
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./routing.v, 276
+  Following is an unused input.
+  Source info: neighbors_r_addr
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./routing.v, 279
+  Following is an unused input.
+  Source info: src_e_addr
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./comb_nonspec.sv, 634
+  Following is an unused input.
+  Source info: vc_weight_is_consumed
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./comb_nonspec.sv, 717
+  Following is an unused input.
+  Source info: weight_consumed
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./mesh_torus.sv, 324
+  Following is an unused input.
+  Source info: odd_column
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./mesh_torus.sv, 324
+  Following is an unused input.
+  Source info: odd_column
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./mesh_torus.sv, 324
+  Following is an unused input.
+  Source info: odd_column
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./mesh_torus.sv, 1213
+  Following is an unused input.
+  Source info: endp_localp_num
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./mesh_torus.sv, 1215
+  Following is an unused input.
+  Source info: swap_port_presel
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./mesh_torus.sv, 1216
+  Following is an unused input.
+  Source info: port_pre_sel
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./input_ports.sv, 273
+  Following is an unused input.
+  Source info: refresh_w_counter
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./input_ports.sv, 274
+  Following is an unused input.
+  Source info: granted_dest_port
+
+
+Lint-[WMIA-L] Width mismatch in assignment
+./../../rtl/src_noc/./input_ports.sv, 379
+  Width mismatch between LHS and RHS is found in assignment:
+  The following 32-bit wide expression is assigned to a 4-bit LHS target:
+  Source info: iport_weight_next = ((weight_in == {pronoc_pkg::WEIGHTw 
+  {1'b0}}) ? 1 : weight_in);
+  Expression: iport_weight_next
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./input_ports.sv, 273
+  Following is an unused input.
+  Source info: refresh_w_counter
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./input_ports.sv, 274
+  Following is an unused input.
+  Source info: granted_dest_port
+
+
+Lint-[WMIA-L] Width mismatch in assignment
+./../../rtl/src_noc/./input_ports.sv, 379
+  Width mismatch between LHS and RHS is found in assignment:
+  The following 32-bit wide expression is assigned to a 4-bit LHS target:
+  Source info: iport_weight_next = ((weight_in == {pronoc_pkg::WEIGHTw 
+  {1'b0}}) ? 1 : weight_in);
+  Expression: iport_weight_next
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./input_ports.sv, 273
+  Following is an unused input.
+  Source info: refresh_w_counter
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./input_ports.sv, 274
+  Following is an unused input.
+  Source info: granted_dest_port
+
+
+Lint-[WMIA-L] Width mismatch in assignment
+./../../rtl/src_noc/./input_ports.sv, 379
+  Width mismatch between LHS and RHS is found in assignment:
+  The following 32-bit wide expression is assigned to a 4-bit LHS target:
+  Source info: iport_weight_next = ((weight_in == {pronoc_pkg::WEIGHTw 
+  {1'b0}}) ? 1 : weight_in);
+  Expression: iport_weight_next
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./input_ports.sv, 273
+  Following is an unused input.
+  Source info: refresh_w_counter
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./input_ports.sv, 274
+  Following is an unused input.
+  Source info: granted_dest_port
+
+
+Lint-[WMIA-L] Width mismatch in assignment
+./../../rtl/src_noc/./input_ports.sv, 379
+  Width mismatch between LHS and RHS is found in assignment:
+  The following 32-bit wide expression is assigned to a 4-bit LHS target:
+  Source info: iport_weight_next = ((weight_in == {pronoc_pkg::WEIGHTw 
+  {1'b0}}) ? 1 : weight_in);
+  Expression: iport_weight_next
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./mesh_torus.sv, 1213
+  Following is an unused input.
+  Source info: endp_localp_num
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./mesh_torus.sv, 1215
+  Following is an unused input.
+  Source info: swap_port_presel
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./mesh_torus.sv, 1216
+  Following is an unused input.
+  Source info: port_pre_sel
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./mesh_torus.sv, 1213
+  Following is an unused input.
+  Source info: endp_localp_num
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./mesh_torus.sv, 1215
+  Following is an unused input.
+  Source info: swap_port_presel
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./mesh_torus.sv, 1216
+  Following is an unused input.
+  Source info: port_pre_sel
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./mesh_torus.sv, 1213
+  Following is an unused input.
+  Source info: endp_localp_num
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./mesh_torus.sv, 1215
+  Following is an unused input.
+  Source info: swap_port_presel
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./mesh_torus.sv, 1216
+  Following is an unused input.
+  Source info: port_pre_sel
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./mesh_torus.sv, 1213
+  Following is an unused input.
+  Source info: endp_localp_num
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./mesh_torus.sv, 1215
+  Following is an unused input.
+  Source info: swap_port_presel
+
+
+Lint-[UI] Unused input
+./../../rtl/src_noc/./mesh_torus.sv, 1216
+  Following is an unused input.
+  Source info: port_pre_sel
+
+Starting vcs inline pass...
+
+35 modules and 0 UDP read.
+Generating code for _VCSgd_reYIK
+Generating code for _VCSgd_bQrwm
+recompiling package pronoc_pkg
+Generating code for _VCSgd_UU20K
+Generating code for _VCSgd_sGFGA
+recompiling module one_hot_demux
+Generating code for _VCSgd_PFE93
+recompiling module custom_or
+Generating code for _VCSgd_rxxii
+recompiling module one_hot_to_bin
+Generating code for _VCSgd_tmkfi
+Generating code for _VCSgd_z7NBD
+recompiling module binary_mux
+Generating code for _VCSgd_w7hk8
+recompiling module arbiter
+Generating code for _VCSgd_Z8Hg1
+recompiling module arbiter_2_one_hot
+Generating code for _VCSgd_jLwrn
+recompiling module extract_header_flit_info
+Generating code for _VCSgd_Ly3qd
+recompiling module header_flit_update_lk_route_ovc
+Generating code for _VCSgd_ECtRV
+recompiling module noc_top
+Generating code for _VCSgd_qubHr
+recompiling module comb_nonspec_allocator
+Generating code for _VCSgd_dmk1W
+recompiling module swa_input_port_arbiter
+Generating code for _VCSgd_wLDGV
+recompiling module swa_output_port_arbiter
+Generating code for _VCSgd_AW5ic
+recompiling module inout_ports
+Generating code for _VCSgd_xNBkF
+recompiling module vc_alloc_request_gen
+Generating code for _VCSgd_bzyYs
+recompiling module input_ports
+Generating code for _VCSgd_at0sD
+recompiling module input_queue_per_port
+Generating code for _VCSgd_vPvg3
+Generating code for _VCSgd_TypBP
+Generating code for _VCSgd_SQwq4
+Generating code for _VCSgd_hJjVQ
+Generating code for _VCSgd_sPxW2
+recompiling module destp_generator
+Generating code for _VCSgd_k7SJc
+Generating code for _VCSgd_g9A6z
+Generating code for _VCSgd_DJdxW
+Generating code for _VCSgd_r6P8n
+Generating code for _VCSgd_pnIHZ
+recompiling module combined_vc_sw_alloc
+Generating code for _VCSgd_L5RSt
+recompiling module mesh_torus_look_ahead_routing
+Generating code for _VCSgd_pKUfH
+recompiling module add_sw_loc_one_hot
+Generating code for _VCSgd_ihbcT
+recompiling module onehot_mux_1D
+Generating code for _VCSgd_wje7W
+Generating code for _VCSgd_ZzZJM
+Generating code for _VCSgd_Dh26b
+Generating code for _VCSgd_etkVB
+Generating code for _VCSgd_UfJB9
+recompiling module header_flit_info
+Generating code for _VCSgd_D067Y
+recompiling module port_pre_sel_gen
+Generating code for _VCSgd_InS4s
+recompiling module output_ports
+Generating code for _VCSgd_IhnxI
+recompiling module credit_monitor_per_ovc
+Generating code for _VCSgd_UPPPJ
+recompiling module oport_ovc_sig_gen
+Generating code for _VCSgd_iMQv0
+recompiling module full_ovc_predictor
+Generating code for _VCSgd_Nx31A
+recompiling module router_two_stage
+Generating code for _VCSgd_QCD2e
+recompiling module credit_release_gen
+Generating code for _VCSgd_Mtzs7
+recompiling module flit_buffer
+Generating code for _VCSgd_bcmYE
+recompiling module fwft_fifo
+Generating code for _VCSgd_sIT4b
+recompiling module router_top
+Generating code for _VCSgd_J4kZy
+recompiling module mesh_torus_noc_top
+34 of 35 modules done
+	However, due to incremental compilation, only 34 modules need to be compiled. 
+make: Warning: File 'filelist.hsopt.llvm2_0.objs' has modification time 55 s in the future
+make: warning:  Clock skew detected.  Your build may be incomplete.
+make: Warning: File 'filelist.cu' has modification time 54 s in the future
+make[1]: Warning: File 'filelist.cu' has modification time 54 s in the future
+rm -f _cuarc*.so _csrc*.so pre_vcsobj_*.so share_vcsobj_*.so
+make[1]: warning:  Clock skew detected.  Your build may be incomplete.
+make[1]: Warning: File 'filelist.cu' has modification time 54 s in the future
+make[1]: warning:  Clock skew detected.  Your build may be incomplete.
+if [ -x /users/amonemi/ProNoC/mpsoc/Integration_test/VCS/result_logs/work/simv ]; then chmod a-x /users/amonemi/ProNoC/mpsoc/Integration_test/VCS/result_logs/work/simv; fi
+g++  -o /users/amonemi/ProNoC/mpsoc/Integration_test/VCS/result_logs/work/simv   -no-pie    -rdynamic  -Wl,-rpath='$ORIGIN'/simv.daidir -Wl,-rpath=./simv.daidir -Wl,-rpath=/eda/synopsys/2022-23/RHELx86/VCS_2022.06-SP2/linux64/lib -L/eda/synopsys/2022-23/RHELx86/VCS_2022.06-SP2/linux64/lib  -Wl,-rpath-link=./ -Wl,--no-as-needed   objs/amcQw_d.o   _1513230_archive_1.so _prev_archive_1.so  SIM_l.o       rmapats_mop.o rmapats.o rmar.o rmar_nd.o  rmar_llvm_0_1.o rmar_llvm_0_0.o            -lnuma -lvirsim -lerrorinf -lsnpsmalloc -lvfs    -lvcsnew -lsimprofile -luclinative /eda/synopsys/2022-23/RHELx86/VCS_2022.06-SP2/linux64/lib/vcs_tls.o   -Wl,-whole-archive  -lvcsucli    -Wl,-no-whole-archive        _vcs_pli_stub_.o   /eda/synopsys/2022-23/RHELx86/VCS_2022.06-SP2/linux64/lib/vcs_save_restore_new.o /eda/synopsys/2022-23/RHELx86/VERDI_2022.06-SP2/share/PLI/VCS/LINUX64/pli.a -ldl  -lc -lm -lpthread -ldl 
+/users/amonemi/ProNoC/mpsoc/Integration_test/VCS/result_logs/work/simv up to date
+make: warning:  Clock skew detected.  Your build may be incomplete.
+Verdi KDB elaboration done and the database successfully generated: 0 error(s), 0 warning(s)
diff --git a/mpsoc/Integration_test/VCS/configurations/line4_smart3 b/mpsoc/Integration_test/VCS/configurations/line4_smart3
new file mode 100644
index 0000000..548c123
--- /dev/null
+++ b/mpsoc/Integration_test/VCS/configurations/line4_smart3
@@ -0,0 +1,16 @@
+$model = bless( {
+    'noc_param'=> {
+        "SMART_MAX" => "3",
+        TOPOLOGY=>"\"LINE\"",
+        "T1" => "4",
+        "T2" => "4",
+        "V" => "1",
+        "ESCAP_VC_MASK" => "1'b1",
+        "B" => "4",
+        "LB" => "16",
+        "Fpay" => "64",
+        "SSA_EN" => "0",
+        "SELF_LOOP_EN" => "1",
+        "MCAST_ENDP_LIST" => "'b11",
+    }
+}, 'ProNOC' );
\ No newline at end of file
diff --git a/mpsoc/Integration_test/VCS/configurations/mesh_3x3_v2_ssa b/mpsoc/Integration_test/VCS/configurations/mesh_3x3_v2_ssa
new file mode 100644
index 0000000..fae94ef
--- /dev/null
+++ b/mpsoc/Integration_test/VCS/configurations/mesh_3x3_v2_ssa
@@ -0,0 +1,11 @@
+$model = bless( {
+    'noc_param'=> {
+        "T1" => "3",
+        "T2" => "3",
+        "SELF_LOOP_EN" => "1",
+        "SSA_EN"=> "1",
+        "LB" => 16,
+        "DEBUG_EN" => "0",
+        "MIN_PCK_SIZE"  => "1",
+    }
+}, 'ProNOC' );
diff --git a/mpsoc/Integration_test/VCS/configurations/mesh_4x4_2cycle_mcast_f b/mpsoc/Integration_test/VCS/configurations/mesh_4x4_2cycle_mcast_f
new file mode 100644
index 0000000..a90f35c
--- /dev/null
+++ b/mpsoc/Integration_test/VCS/configurations/mesh_4x4_2cycle_mcast_f
@@ -0,0 +1,8 @@
+$model = bless( {
+    'noc_param'=> {
+        "T1" => "4",
+        "T2" => "4",
+        "CAST_TYPE" => "\"MULTICAST_FULL\"",
+        "Fpay" => "64"
+    }
+}, 'ProNOC' );
\ No newline at end of file
diff --git a/mpsoc/Integration_test/VCS/configurations/mesh_4x4_2cycle_xy_v2 b/mpsoc/Integration_test/VCS/configurations/mesh_4x4_2cycle_xy_v2
new file mode 100644
index 0000000..b7eb7d1
--- /dev/null
+++ b/mpsoc/Integration_test/VCS/configurations/mesh_4x4_2cycle_xy_v2
@@ -0,0 +1,7 @@
+$model = bless( {
+        'noc_param'=> {
+        "T1" => "4",
+        "T2" => "4",
+        "DEBUG_EN" => "0",       
+    }
+}, 'ProNOC' );
diff --git a/mpsoc/Integration_test/VCS/run.sh b/mpsoc/Integration_test/VCS/run.sh
new file mode 100644
index 0000000..97ecf5e
--- /dev/null
+++ b/mpsoc/Integration_test/VCS/run.sh
@@ -0,0 +1,55 @@
+#!/bin/bash
+
+SCRPT_FULL_PATH=$(realpath ${BASH_SOURCE[0]})
+SCRPT_DIR_PATH=$(dirname $SCRPT_FULL_PATH)
+
+# Source the environment variables
+conf_dir="${SCRPT_DIR_PATH}/configurations"
+log_dir="${SCRPT_DIR_PATH}/result_logs"
+work="${log_dir}/work"
+file_list="${SCRPT_DIR_PATH}/src/file_list.f"
+
+export VCS_ARCH_OVERRIDE=linux
+
+mkdir -p $work
+mkdir -p $log_dir
+
+VCS_WORK_LIB=work
+
+VCS_COMMON_ARGS=" -full64 -notice -nc -kdb -timescale=1ps/1ps  -sverilog  -debug_access  +vcs+lic+wait "
+VCS_ANALYZE_ARGS=" +lint=all,noVCDE,noVNGS,noPCTIO-L,noPCTIO  +systemverilogext+.sv  -work $VCS_WORK_LIB  +warn=all " 
+
+vcs_lint () {
+    conf=$1
+    conf_file="${conf_dir}/$conf"
+    log_file="${log_dir}/${conf}.log"
+
+    if [[ ! -f "$conf_file" ]]; then
+        echo "Configuration file $conf_file does not exist"
+        exit 1
+    fi
+
+    perl "${SCRPT_DIR_PATH}/src/param_gen.pl" "$conf_file"
+
+    vcs $VCS_COMMON_ARGS $VCS_ANALYZE_ARGS \
+        -f "$file_list" \
+        -top noc_top \
+        -o "$work/simv" \
+        -Mdir="$work/csrc"
+}
+
+for f in "$conf_dir"/*; do
+    [[ -d "$f" ]] && continue
+    conf=$(basename "$f")
+    echo "▶️  Compiling configuration: $conf"
+    vcs_lint "$conf" > "$log_dir/${conf}.log" 2>&1
+    if [[ $? -ne 0 ]]; then
+        echo "❌ Compilation failed for $conf (check $log_dir/${conf}.log)"
+        rm -f ${SCRPT_DIR_PATH}/src/noc_localparam.v
+        exit 1
+    else
+        echo "✅ Compilation successful for $conf"
+        rm -f ${SCRPT_DIR_PATH}/src/noc_localparam.v
+    fi
+    
+done
diff --git a/mpsoc/Integration_test/VCS/src/file_list.f b/mpsoc/Integration_test/VCS/src/file_list.f
new file mode 100644
index 0000000..1f5742d
--- /dev/null
+++ b/mpsoc/Integration_test/VCS/src/file_list.f
@@ -0,0 +1,6 @@
++incdir+./src 
+
+-F ./../../rtl/src_noc/noc_filelist.f
+-F ./../../rtl/src_topology/custom_flist.f
+
+
diff --git a/mpsoc/Integration_test/VCS/src/param_gen.pl b/mpsoc/Integration_test/VCS/src/param_gen.pl
new file mode 100644
index 0000000..1ad4763
--- /dev/null
+++ b/mpsoc/Integration_test/VCS/src/param_gen.pl
@@ -0,0 +1,46 @@
+#!/usr/bin/perl  
+package ProNOC;
+use strict;
+use warnings;
+use File::Basename;
+
+
+#add home dir in perl 5.6
+use FindBin;
+use lib $FindBin::Bin;
+use Cwd qw(realpath);
+
+
+
+
+use File::Path qw(make_path);
+
+
+use strict;
+use warnings;
+
+
+
+
+my $script_path = dirname(__FILE__);
+
+require "$script_path/../../synthetic_sim/src/src.pl";
+use lib "../synthetic_sim/src/perl_lib";
+
+use constant::boolean;
+use base 'Class::Accessor::Fast';
+
+my $conf_file=$ARGV[0];
+
+
+sub create_noc_param_vv {
+    my ($conf_file)=@_;
+    my $o = do $conf_file;
+    die "Could not parse $conf_file: $@" if $@;
+    die "Could not read $conf_file: $!" unless defined $o;
+    my $param = $o->{'noc_param'};
+    my ($param_v,$include_h,$tops)=   gen_noc_localparam_v( $o,$param);
+    save_file("$script_path/noc_localparam.v",$param_v);
+}
+
+create_noc_param_vv ($conf_file);
diff --git a/mpsoc/Integration_test/VCST/Golden_ref/line4_smart3.log b/mpsoc/Integration_test/VCST/Golden_ref/line4_smart3.log
new file mode 100644
index 0000000..d08082f
--- /dev/null
+++ b/mpsoc/Integration_test/VCST/Golden_ref/line4_smart3.log
@@ -0,0 +1,559 @@
+Use of uninitialized value $ENV{"PRONOC_WORK"} in concatenation (.) or string at /users/amonemi/ProNoC/mpsoc/Integration_test/VCST/src/../../synthetic_sim/src/src.pl line 24.
+Use of uninitialized value $ENV{"PRONOC_WORK"} in concatenation (.) or string at /users/amonemi/ProNoC/mpsoc/Integration_test/VCST/src/../../synthetic_sim/src/src.pl line 25.
+Use of uninitialized value $ENV{"PRONOC_WORK"} in concatenation (.) or string at /users/amonemi/ProNoC/mpsoc/Integration_test/VCST/src/../../synthetic_sim/src/src.pl line 26.
+Script Path: /users/amonemi/ProNoC/mpsoc/Integration_test/VCST/src/../../synthetic_sim/src
+confs_dir: /users/amonemi/ProNoC/mpsoc/Integration_test/synthetic_sim/configurations
+Root: /users/amonemi/ProNoC/mpsoc
+Note: DISPLAY is not set, GUI view commands are disabled.
+
+                                   VC Static 
+
+                Version T-2022.06-SP2 for linux64 - Nov 29, 2022
+
+                    Copyright (c) 2010 - 2022 Synopsys, Inc.
+   This software and the associated documentation are proprietary to Synopsys,
+ Inc. This software may only be used in accordance with the terms and conditions
+ of a written license agreement with Synopsys, Inc. All other use, reproduction,
+   or distribution of this software is strictly prohibited.  Licensed Products
+     communicate with Synopsys servers for the purpose of providing software
+    updates, detecting software piracy and verifying that customers are using
+    Licensed Products in conformity with the applicable License Key for such
+  Licensed Products. Synopsys will use information gathered in connection with
+    this process to deliver software updates and pursue software pirates and
+                                   infringers.
+
+ Inclusivity & Diversity - Visit SolvNetPlus to read the "Synopsys Statement on
+            Inclusivity and Diversity" (Refer to article 000036315 at
+                        https://solvnetplus.synopsys.com)
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
vc_static_shell> set script_dir [file dirname [file normalize [info script]]]
+/users/amonemi/ProNoC/mpsoc/Integration_test/VCST/src
+set DESIGN  noc_top
+noc_top
+set report_filename $::env(REPORT_FILENAME)
+/users/amonemi/ProNoC/mpsoc/Integration_test/VCST/result_logs/line4_smart3_vc_static.txt
+# Waivers:
+#sg_read_waiver -file ${script_dir}/waiver.awl
+#source ${script_dir}/waiver.tcl
+# Reading Intel linting rules 
+source $script_dir/lint_rules.tcl
+[Error] LINT_CMD042: In configure_hdl_tag_param, tag name W71 and parameter name REPORT_ONLY_FROM_ONE_HIERARCHY are not associated, ignore the command.
+[Error] LINT_CMD042: In configure_hdl_tag_param, tag name W71 and parameter name REPORT_ONLY_FROM_ONE_HIERARCHY are not associated, ignore the command.
+[Error] LINT_CMD042: In configure_hdl_tag_param, tag name W71 and parameter name REPORT_ONLY_FROM_ONE_HIERARCHY are not associated, ignore the command.
+[Error] LINT_CMD042: In configure_hdl_tag_param, tag name W71 and parameter name REPORT_ONLY_FROM_ONE_HIERARCHY are not associated, ignore the command.
+[Error] LINT_CMD042: In configure_hdl_tag_param, tag name W123 and parameter name REPORT_ONLY_FROM_ONE_HIERARCHY are not associated, ignore the command.
+[Error] LINT_CMD042: In configure_hdl_tag_param, tag name W123 and parameter name REPORT_ONLY_FROM_ONE_HIERARCHY are not associated, ignore the command.
+[Error] LINT_CMD042: In configure_hdl_tag_param, tag name W123 and parameter name REPORT_ONLY_FROM_ONE_HIERARCHY are not associated, ignore the command.
+[Error] LINT_CMD042: In configure_hdl_tag_param, tag name W123 and parameter name REPORT_ONLY_FROM_ONE_HIERARCHY are not associated, ignore the command.
+[Error] LINT_CMD042: In configure_hdl_tag_param, tag name W123 and parameter name REPORT_ONLY_FROM_ONE_HIERARCHY are not associated, ignore the command.
+[Error] LINT_CMD042: In configure_hdl_tag_param, tag name W240 and parameter name REPORT_ONLY_FROM_ONE_HIERARCHY are not associated, ignore the command.
+[Error] LINT_CMD042: In configure_hdl_tag_param, tag name W240 and parameter name REPORT_ONLY_FROM_ONE_HIERARCHY are not associated, ignore the command.
+[Error] LINT_CMD042: In configure_hdl_tag_param, tag name W240 and parameter name REPORT_ONLY_FROM_ONE_HIERARCHY are not associated, ignore the command.
+[Error] LINT_CMD042: In configure_hdl_tag_param, tag name W240 and parameter name REPORT_ONLY_FROM_ONE_HIERARCHY are not associated, ignore the command.
+[Error] LINT_CMD042: In configure_hdl_tag_param, tag name W240 and parameter name REPORT_ONLY_FROM_ONE_HIERARCHY are not associated, ignore the command.
+[Error] LINT_CMD042: In configure_hdl_tag_param, tag name W240 and parameter name REPORT_ONLY_FROM_ONE_HIERARCHY are not associated, ignore the command.
+[Error] LINT_CMD042: In configure_hdl_tag_param, tag name W240 and parameter name REPORT_ONLY_FROM_ONE_HIERARCHY are not associated, ignore the command.
+[Error] RDB_CONFIGURE_BAD_TAG: None of the tag pattern(s) 'InferLatch' (/users/amonemi/ProNoC/mpsoc/Integration_test/VCST/src/lint_rules.tcl:242) were found.
+	Revise your tag list and try again..
+[Warning] TCL_COMMAND_FAILED: 'configure_tag' command failed. [set sh_continue_on_error true] is set. Hence continuing the run.
+[Error] LINT_CMD040: In configure_hdl_tag_param, tag name 02041 does not exist.
+[Warning] TCL_COMMAND_FAILED: 'configure_lint_tag_parameter' command failed. [set sh_continue_on_error true] is set. Hence continuing the run.
+[Error] LINT_CMD042: In configure_hdl_tag_param, tag name W120 and parameter name REPORT_ONLY_FROM_ONE_HIERARCHY are not associated, ignore the command.
+[Error] LINT_CMD042: In configure_hdl_tag_param, tag name W120 and parameter name REPORT_ONLY_FROM_ONE_HIERARCHY are not associated, ignore the command.
+[Error] LINT_CMD042: In configure_hdl_tag_param, tag name W120 and parameter name REPORT_ONLY_FROM_ONE_HIERARCHY are not associated, ignore the command.
+[Error] LINT_CMD042: In configure_hdl_tag_param, tag name W120 and parameter name REPORT_ONLY_FROM_ONE_HIERARCHY are not associated, ignore the command.
+[Error] LINT_CMD042: In configure_hdl_tag_param, tag name W120 and parameter name REPORT_ONLY_FROM_ONE_HIERARCHY are not associated, ignore the command.
+[Error] LINT_CMD042: In configure_hdl_tag_param, tag name W120 and parameter name REPORT_ONLY_FROM_ONE_HIERARCHY are not associated, ignore the command.
+[Error] LINT_CMD042: In configure_hdl_tag_param, tag name W120 and parameter name REPORT_ONLY_FROM_ONE_HIERARCHY are not associated, ignore the command.
+[Error] LINT_CMD040: In configure_hdl_tag_param, tag name 60024 does not exist.
+[Warning] TCL_COMMAND_FAILED: 'configure_lint_tag_parameter' command failed. [set sh_continue_on_error true] is set. Hence continuing the run.
+[Error] LINT_CMD040: In configure_hdl_tag_param, tag name 60013 does not exist.
+[Warning] TCL_COMMAND_FAILED: 'configure_lint_tag_parameter' command failed. [set sh_continue_on_error true] is set. Hence continuing the run.
+[Error] LINT_CMD040: In configure_hdl_tag_param, tag name 60117 does not exist.
+[Warning] TCL_COMMAND_FAILED: 'configure_lint_tag_parameter' command failed. [set sh_continue_on_error true] is set. Hence continuing the run.
+[Error] LINT_CMD040: In configure_hdl_tag_param, tag name 60010 does not exist.
+[Warning] TCL_COMMAND_FAILED: 'configure_lint_tag_parameter' command failed. [set sh_continue_on_error true] is set. Hence continuing the run.
+[Error] LINT_CMD040: In configure_hdl_tag_param, tag name 60010 does not exist.
+[Warning] TCL_COMMAND_FAILED: 'configure_lint_tag_parameter' command failed. [set sh_continue_on_error true] is set. Hence continuing the run.
+[Error] LINT_CMD040: In configure_hdl_tag_param, tag name 54005 does not exist.
+[Warning] TCL_COMMAND_FAILED: 'configure_lint_tag_parameter' command failed. [set sh_continue_on_error true] is set. Hence continuing the run.
+[Error] LINT_CMD040: In configure_hdl_tag_param, tag name 54005 does not exist.
+[Warning] TCL_COMMAND_FAILED: 'configure_lint_tag_parameter' command failed. [set sh_continue_on_error true] is set. Hence continuing the run.
+[Error] LINT_CMD040: In configure_hdl_tag_param, tag name 54005 does not exist.
+[Warning] TCL_COMMAND_FAILED: 'configure_lint_tag_parameter' command failed. [set sh_continue_on_error true] is set. Hence continuing the run.
+[Error] LINT_CMD040: In configure_hdl_tag_param, tag name 54005 does not exist.
+[Warning] TCL_COMMAND_FAILED: 'configure_lint_tag_parameter' command failed. [set sh_continue_on_error true] is set. Hence continuing the run.
+[Error] LINT_CMD040: In configure_hdl_tag_param, tag name 54006 does not exist.
+[Warning] TCL_COMMAND_FAILED: 'configure_lint_tag_parameter' command failed. [set sh_continue_on_error true] is set. Hence continuing the run.
+[Error] LINT_CMD040: In configure_hdl_tag_param, tag name 54007 does not exist.
+[Warning] TCL_COMMAND_FAILED: 'configure_lint_tag_parameter' command failed. [set sh_continue_on_error true] is set. Hence continuing the run.
+[Error] LINT_CMD040: In configure_hdl_tag_param, tag name 60701 does not exist.
+[Warning] TCL_COMMAND_FAILED: 'configure_lint_tag_parameter' command failed. [set sh_continue_on_error true] is set. Hence continuing the run.
+[Error] LINT_CMD040: In configure_hdl_tag_param, tag name 60152 does not exist.
+[Warning] TCL_COMMAND_FAILED: 'configure_lint_tag_parameter' command failed. [set sh_continue_on_error true] is set. Hence continuing the run.
+[Error] LINT_CMD040: In configure_hdl_tag_param, tag name 60702 does not exist.
+[Warning] TCL_COMMAND_FAILED: 'configure_lint_tag_parameter' command failed. [set sh_continue_on_error true] is set. Hence continuing the run.
+[Error] LINT_CMD040: In configure_hdl_tag_param, tag name 60702 does not exist.
+[Warning] TCL_COMMAND_FAILED: 'configure_lint_tag_parameter' command failed. [set sh_continue_on_error true] is set. Hence continuing the run.
+[Error] LINT_CMD040: In configure_hdl_tag_param, tag name 60703 does not exist.
+[Warning] TCL_COMMAND_FAILED: 'configure_lint_tag_parameter' command failed. [set sh_continue_on_error true] is set. Hence continuing the run.
+[Error] LINT_CMD040: In configure_hdl_tag_param, tag name 60703 does not exist.
+[Warning] TCL_COMMAND_FAILED: 'configure_lint_tag_parameter' command failed. [set sh_continue_on_error true] is set. Hence continuing the run.
+[Error] LINT_CMD040: In configure_hdl_tag_param, tag name 60704 does not exist.
+[Warning] TCL_COMMAND_FAILED: 'configure_lint_tag_parameter' command failed. [set sh_continue_on_error true] is set. Hence continuing the run.
+[Error] LINT_CMD040: In configure_hdl_tag_param, tag name 60704 does not exist.
+[Warning] TCL_COMMAND_FAILED: 'configure_lint_tag_parameter' command failed. [set sh_continue_on_error true] is set. Hence continuing the run.
+[Error] LINT_CMD040: In configure_hdl_tag_param, tag name 60706 does not exist.
+[Warning] TCL_COMMAND_FAILED: 'configure_lint_tag_parameter' command failed. [set sh_continue_on_error true] is set. Hence continuing the run.
+[Error] LINT_CMD040: In configure_hdl_tag_param, tag name 60706 does not exist.
+[Warning] TCL_COMMAND_FAILED: 'configure_lint_tag_parameter' command failed. [set sh_continue_on_error true] is set. Hence continuing the run.
+[Error] LINT_CMD040: In configure_hdl_tag_param, tag name 60706 does not exist.
+[Warning] TCL_COMMAND_FAILED: 'configure_lint_tag_parameter' command failed. [set sh_continue_on_error true] is set. Hence continuing the run.
+[Error] LINT_CMD040: In configure_hdl_tag_param, tag name 60706 does not exist.
+[Warning] TCL_COMMAND_FAILED: 'configure_lint_tag_parameter' command failed. [set sh_continue_on_error true] is set. Hence continuing the run.
+[Error] LINT_CMD040: In configure_hdl_tag_param, tag name 70600 does not exist.
+[Warning] TCL_COMMAND_FAILED: 'configure_lint_tag_parameter' command failed. [set sh_continue_on_error true] is set. Hence continuing the run.
+[Error] LINT_CMD040: In configure_hdl_tag_param, tag name 70600 does not exist.
+[Warning] TCL_COMMAND_FAILED: 'configure_lint_tag_parameter' command failed. [set sh_continue_on_error true] is set. Hence continuing the run.
+[Error] LINT_CMD040: In configure_hdl_tag_param, tag name 70600 does not exist.
+[Warning] TCL_COMMAND_FAILED: 'configure_lint_tag_parameter' command failed. [set sh_continue_on_error true] is set. Hence continuing the run.
+[Error] LINT_CMD040: In configure_hdl_tag_param, tag name 70601 does not exist.
+[Warning] TCL_COMMAND_FAILED: 'configure_lint_tag_parameter' command failed. [set sh_continue_on_error true] is set. Hence continuing the run.
+[Error] LINT_CMD040: In configure_hdl_tag_param, tag name 70601 does not exist.
+[Warning] TCL_COMMAND_FAILED: 'configure_lint_tag_parameter' command failed. [set sh_continue_on_error true] is set. Hence continuing the run.
+[Error] LINT_CMD040: In configure_hdl_tag_param, tag name 70601 does not exist.
+[Warning] TCL_COMMAND_FAILED: 'configure_lint_tag_parameter' command failed. [set sh_continue_on_error true] is set. Hence continuing the run.
+[Error] LINT_CMD040: In configure_hdl_tag_param, tag name 70601 does not exist.
+[Warning] TCL_COMMAND_FAILED: 'configure_lint_tag_parameter' command failed. [set sh_continue_on_error true] is set. Hence continuing the run.
+[Error] LINT_CMD040: In configure_hdl_tag_param, tag name 70602 does not exist.
+[Warning] TCL_COMMAND_FAILED: 'configure_lint_tag_parameter' command failed. [set sh_continue_on_error true] is set. Hence continuing the run.
+[Error] LINT_CMD040: In configure_hdl_tag_param, tag name 70602 does not exist.
+[Warning] TCL_COMMAND_FAILED: 'configure_lint_tag_parameter' command failed. [set sh_continue_on_error true] is set. Hence continuing the run.
+[Error] LINT_CMD040: In configure_hdl_tag_param, tag name 70602 does not exist.
+[Warning] TCL_COMMAND_FAILED: 'configure_lint_tag_parameter' command failed. [set sh_continue_on_error true] is set. Hence continuing the run.
+[Error] LINT_CMD040: In configure_hdl_tag_param, tag name 70602 does not exist.
+[Warning] TCL_COMMAND_FAILED: 'configure_lint_tag_parameter' command failed. [set sh_continue_on_error true] is set. Hence continuing the run.
+[Error] LINT_CMD040: In configure_hdl_tag_param, tag name 70603 does not exist.
+[Warning] TCL_COMMAND_FAILED: 'configure_lint_tag_parameter' command failed. [set sh_continue_on_error true] is set. Hence continuing the run.
+[Error] LINT_CMD040: In configure_hdl_tag_param, tag name 70603 does not exist.
+[Warning] TCL_COMMAND_FAILED: 'configure_lint_tag_parameter' command failed. [set sh_continue_on_error true] is set. Hence continuing the run.
+[Error] LINT_CMD040: In configure_hdl_tag_param, tag name 70603 does not exist.
+[Warning] TCL_COMMAND_FAILED: 'configure_lint_tag_parameter' command failed. [set sh_continue_on_error true] is set. Hence continuing the run.
+[Error] LINT_CMD040: In configure_hdl_tag_param, tag name 70603 does not exist.
+[Warning] TCL_COMMAND_FAILED: 'configure_lint_tag_parameter' command failed. [set sh_continue_on_error true] is set. Hence continuing the run.
+[Error] LINT_CMD040: In configure_hdl_tag_param, tag name 70604 does not exist.
+[Warning] TCL_COMMAND_FAILED: 'configure_lint_tag_parameter' command failed. [set sh_continue_on_error true] is set. Hence continuing the run.
+[Error] LINT_CMD040: In configure_hdl_tag_param, tag name 70604 does not exist.
+[Warning] TCL_COMMAND_FAILED: 'configure_lint_tag_parameter' command failed. [set sh_continue_on_error true] is set. Hence continuing the run.
+[Error] LINT_CMD040: In configure_hdl_tag_param, tag name 70605 does not exist.
+[Warning] TCL_COMMAND_FAILED: 'configure_lint_tag_parameter' command failed. [set sh_continue_on_error true] is set. Hence continuing the run.
+[Error] LINT_CMD040: In configure_hdl_tag_param, tag name 70605 does not exist.
+[Warning] TCL_COMMAND_FAILED: 'configure_lint_tag_parameter' command failed. [set sh_continue_on_error true] is set. Hence continuing the run.
+[Error] LINT_CMD040: In configure_hdl_tag_param, tag name 70605_Info does not exist.
+[Warning] TCL_COMMAND_FAILED: 'configure_lint_tag_parameter' command failed. [set sh_continue_on_error true] is set. Hence continuing the run.
+[Error] LINT_CMD040: In configure_hdl_tag_param, tag name 70605_Info does not exist.
+[Warning] TCL_COMMAND_FAILED: 'configure_lint_tag_parameter' command failed. [set sh_continue_on_error true] is set. Hence continuing the run.
+[Error] LINT_CMD040: In configure_hdl_tag_param, tag name 70606 does not exist.
+[Warning] TCL_COMMAND_FAILED: 'configure_lint_tag_parameter' command failed. [set sh_continue_on_error true] is set. Hence continuing the run.
+[Error] LINT_CMD040: In configure_hdl_tag_param, tag name 70606 does not exist.
+[Warning] TCL_COMMAND_FAILED: 'configure_lint_tag_parameter' command failed. [set sh_continue_on_error true] is set. Hence continuing the run.
+[Error] LINT_CMD040: In configure_hdl_tag_param, tag name 70606 does not exist.
+[Warning] TCL_COMMAND_FAILED: 'configure_lint_tag_parameter' command failed. [set sh_continue_on_error true] is set. Hence continuing the run.
+[Error] LINT_CMD040: In configure_hdl_tag_param, tag name 70607 does not exist.
+[Warning] TCL_COMMAND_FAILED: 'configure_lint_tag_parameter' command failed. [set sh_continue_on_error true] is set. Hence continuing the run.
+[Error] LINT_CMD040: In configure_hdl_tag_param, tag name 70607 does not exist.
+[Warning] TCL_COMMAND_FAILED: 'configure_lint_tag_parameter' command failed. [set sh_continue_on_error true] is set. Hence continuing the run.
+[Error] LINT_CMD040: In configure_hdl_tag_param, tag name 70608 does not exist.
+[Warning] TCL_COMMAND_FAILED: 'configure_lint_tag_parameter' command failed. [set sh_continue_on_error true] is set. Hence continuing the run.
+[Error] LINT_CMD040: In configure_hdl_tag_param, tag name 70608 does not exist.
+[Warning] TCL_COMMAND_FAILED: 'configure_lint_tag_parameter' command failed. [set sh_continue_on_error true] is set. Hence continuing the run.
+[Error] LINT_CMD040: In configure_hdl_tag_param, tag name 70609 does not exist.
+[Warning] TCL_COMMAND_FAILED: 'configure_lint_tag_parameter' command failed. [set sh_continue_on_error true] is set. Hence continuing the run.
+[Error] LINT_CMD040: In configure_hdl_tag_param, tag name 70609 does not exist.
+[Warning] TCL_COMMAND_FAILED: 'configure_lint_tag_parameter' command failed. [set sh_continue_on_error true] is set. Hence continuing the run.
+[Error] LINT_CMD040: In configure_hdl_tag_param, tag name 70609 does not exist.
+[Warning] TCL_COMMAND_FAILED: 'configure_lint_tag_parameter' command failed. [set sh_continue_on_error true] is set. Hence continuing the run.
+[Error] LINT_CMD040: In configure_hdl_tag_param, tag name 70610 does not exist.
+[Warning] TCL_COMMAND_FAILED: 'configure_lint_tag_parameter' command failed. [set sh_continue_on_error true] is set. Hence continuing the run.
+[Error] LINT_CMD040: In configure_hdl_tag_param, tag name 70610 does not exist.
+[Warning] TCL_COMMAND_FAILED: 'configure_lint_tag_parameter' command failed. [set sh_continue_on_error true] is set. Hence continuing the run.
+[Error] LINT_CMD040: In configure_hdl_tag_param, tag name 70611 does not exist.
+[Warning] TCL_COMMAND_FAILED: 'configure_lint_tag_parameter' command failed. [set sh_continue_on_error true] is set. Hence continuing the run.
+[Error] LINT_CMD040: In configure_hdl_tag_param, tag name 70611 does not exist.
+[Warning] TCL_COMMAND_FAILED: 'configure_lint_tag_parameter' command failed. [set sh_continue_on_error true] is set. Hence continuing the run.
+[Error] LINT_CMD040: In configure_hdl_tag_param, tag name 70612 does not exist.
+[Warning] TCL_COMMAND_FAILED: 'configure_lint_tag_parameter' command failed. [set sh_continue_on_error true] is set. Hence continuing the run.
+[Error] LINT_CMD040: In configure_hdl_tag_param, tag name 70612 does not exist.
+[Warning] TCL_COMMAND_FAILED: 'configure_lint_tag_parameter' command failed. [set sh_continue_on_error true] is set. Hence continuing the run.
+[Error] LINT_CMD040: In configure_hdl_tag_param, tag name 70612 does not exist.
+[Warning] TCL_COMMAND_FAILED: 'configure_lint_tag_parameter' command failed. [set sh_continue_on_error true] is set. Hence continuing the run.
+[Error] LINT_CMD040: In configure_hdl_tag_param, tag name 70612 does not exist.
+[Warning] TCL_COMMAND_FAILED: 'configure_lint_tag_parameter' command failed. [set sh_continue_on_error true] is set. Hence continuing the run.
+[Error] LINT_CMD040: In configure_hdl_tag_param, tag name 70612 does not exist.
+[Warning] TCL_COMMAND_FAILED: 'configure_lint_tag_parameter' command failed. [set sh_continue_on_error true] is set. Hence continuing the run.
+[Error] LINT_CMD040: In configure_hdl_tag_param, tag name W164b_a does not exist.
+[Warning] TCL_COMMAND_FAILED: 'configure_lint_tag_parameter' command failed. [set sh_continue_on_error true] is set. Hence continuing the run.
+[Error] LINT_CMD040: In configure_hdl_tag_param, tag name W164b_a does not exist.
+[Warning] TCL_COMMAND_FAILED: 'configure_lint_tag_parameter' command failed. [set sh_continue_on_error true] is set. Hence continuing the run.
+[Error] LINT_CMD040: In configure_hdl_tag_param, tag name W164b_a does not exist.
+[Warning] TCL_COMMAND_FAILED: 'configure_lint_tag_parameter' command failed. [set sh_continue_on_error true] is set. Hence continuing the run.
+[Error] LINT_CMD040: In configure_hdl_tag_param, tag name W164b_a does not exist.
+[Warning] TCL_COMMAND_FAILED: 'configure_lint_tag_parameter' command failed. [set sh_continue_on_error true] is set. Hence continuing the run.
+[Error] LINT_CMD040: In configure_hdl_tag_param, tag name W164b_a does not exist.
+[Warning] TCL_COMMAND_FAILED: 'configure_lint_tag_parameter' command failed. [set sh_continue_on_error true] is set. Hence continuing the run.
+[Error] LINT_CMD040: In configure_hdl_tag_param, tag name W164b_a does not exist.
+[Warning] TCL_COMMAND_FAILED: 'configure_lint_tag_parameter' command failed. [set sh_continue_on_error true] is set. Hence continuing the run.
+[Error] LINT_CMD040: In configure_hdl_tag_param, tag name W164b_a does not exist.
+[Warning] TCL_COMMAND_FAILED: 'configure_lint_tag_parameter' command failed. [set sh_continue_on_error true] is set. Hence continuing the run.
+[Error] LINT_CMD040: In configure_hdl_tag_param, tag name W164b_a does not exist.
+[Warning] TCL_COMMAND_FAILED: 'configure_lint_tag_parameter' command failed. [set sh_continue_on_error true] is set. Hence continuing the run.
+[Error] LINT_CMD040: In configure_hdl_tag_param, tag name W164b_a does not exist.
+[Warning] TCL_COMMAND_FAILED: 'configure_lint_tag_parameter' command failed. [set sh_continue_on_error true] is set. Hence continuing the run.
+[Error] LINT_CMD040: In configure_hdl_tag_param, tag name W164b_a does not exist.
+[Warning] TCL_COMMAND_FAILED: 'configure_lint_tag_parameter' command failed. [set sh_continue_on_error true] is set. Hence continuing the run.
+[Error] LINT_CMD040: In configure_hdl_tag_param, tag name W164b_a does not exist.
+[Warning] TCL_COMMAND_FAILED: 'configure_lint_tag_parameter' command failed. [set sh_continue_on_error true] is set. Hence continuing the run.
+[Error] LINT_CMD040: In configure_hdl_tag_param, tag name W164b_a does not exist.
+[Warning] TCL_COMMAND_FAILED: 'configure_lint_tag_parameter' command failed. [set sh_continue_on_error true] is set. Hence continuing the run.
+[Error] LINT_CMD040: In configure_hdl_tag_param, tag name W164b_b does not exist.
+[Warning] TCL_COMMAND_FAILED: 'configure_lint_tag_parameter' command failed. [set sh_continue_on_error true] is set. Hence continuing the run.
+[Error] LINT_CMD040: In configure_hdl_tag_param, tag name W164b_b does not exist.
+[Warning] TCL_COMMAND_FAILED: 'configure_lint_tag_parameter' command failed. [set sh_continue_on_error true] is set. Hence continuing the run.
+[Error] LINT_CMD040: In configure_hdl_tag_param, tag name W164b_b does not exist.
+[Warning] TCL_COMMAND_FAILED: 'configure_lint_tag_parameter' command failed. [set sh_continue_on_error true] is set. Hence continuing the run.
+[Error] LINT_CMD040: In configure_hdl_tag_param, tag name W164b_b does not exist.
+[Warning] TCL_COMMAND_FAILED: 'configure_lint_tag_parameter' command failed. [set sh_continue_on_error true] is set. Hence continuing the run.
+[Error] LINT_CMD040: In configure_hdl_tag_param, tag name W164b_b does not exist.
+[Warning] TCL_COMMAND_FAILED: 'configure_lint_tag_parameter' command failed. [set sh_continue_on_error true] is set. Hence continuing the run.
+[Error] LINT_CMD040: In configure_hdl_tag_param, tag name W164b_b does not exist.
+[Warning] TCL_COMMAND_FAILED: 'configure_lint_tag_parameter' command failed. [set sh_continue_on_error true] is set. Hence continuing the run.
+[Error] LINT_CMD040: In configure_hdl_tag_param, tag name W164b_b does not exist.
+[Warning] TCL_COMMAND_FAILED: 'configure_lint_tag_parameter' command failed. [set sh_continue_on_error true] is set. Hence continuing the run.
+[Error] LINT_CMD040: In configure_hdl_tag_param, tag name W164b_b does not exist.
+[Warning] TCL_COMMAND_FAILED: 'configure_lint_tag_parameter' command failed. [set sh_continue_on_error true] is set. Hence continuing the run.
+[Error] LINT_CMD040: In configure_hdl_tag_param, tag name W164b_b does not exist.
+[Warning] TCL_COMMAND_FAILED: 'configure_lint_tag_parameter' command failed. [set sh_continue_on_error true] is set. Hence continuing the run.
+[Error] LINT_CMD040: In configure_hdl_tag_param, tag name W164b_b does not exist.
+[Warning] TCL_COMMAND_FAILED: 'configure_lint_tag_parameter' command failed. [set sh_continue_on_error true] is set. Hence continuing the run.
+[Error] LINT_CMD040: In configure_hdl_tag_param, tag name W164b_b does not exist.
+[Warning] TCL_COMMAND_FAILED: 'configure_lint_tag_parameter' command failed. [set sh_continue_on_error true] is set. Hence continuing the run.
+[Error] LINT_CMD040: In configure_hdl_tag_param, tag name W362a does not exist.
+[Warning] TCL_COMMAND_FAILED: 'configure_lint_tag_parameter' command failed. [set sh_continue_on_error true] is set. Hence continuing the run.
+[Error] LINT_CMD040: In configure_hdl_tag_param, tag name W362a does not exist.
+[Warning] TCL_COMMAND_FAILED: 'configure_lint_tag_parameter' command failed. [set sh_continue_on_error true] is set. Hence continuing the run.
+[Error] LINT_CMD040: In configure_hdl_tag_param, tag name W362a does not exist.
+[Warning] TCL_COMMAND_FAILED: 'configure_lint_tag_parameter' command failed. [set sh_continue_on_error true] is set. Hence continuing the run.
+[Error] LINT_CMD040: In configure_hdl_tag_param, tag name W362a does not exist.
+[Warning] TCL_COMMAND_FAILED: 'configure_lint_tag_parameter' command failed. [set sh_continue_on_error true] is set. Hence continuing the run.
+[Error] LINT_CMD040: In configure_hdl_tag_param, tag name W362a does not exist.
+[Warning] TCL_COMMAND_FAILED: 'configure_lint_tag_parameter' command failed. [set sh_continue_on_error true] is set. Hence continuing the run.
+[Error] LINT_CMD040: In configure_hdl_tag_param, tag name W362a does not exist.
+[Warning] TCL_COMMAND_FAILED: 'configure_lint_tag_parameter' command failed. [set sh_continue_on_error true] is set. Hence continuing the run.
+[Error] LINT_CMD040: In configure_hdl_tag_param, tag name W362b does not exist.
+[Warning] TCL_COMMAND_FAILED: 'configure_lint_tag_parameter' command failed. [set sh_continue_on_error true] is set. Hence continuing the run.
+[Error] LINT_CMD040: In configure_hdl_tag_param, tag name W362b does not exist.
+[Warning] TCL_COMMAND_FAILED: 'configure_lint_tag_parameter' command failed. [set sh_continue_on_error true] is set. Hence continuing the run.
+[Error] LINT_CMD040: In configure_hdl_tag_param, tag name W362b does not exist.
+[Warning] TCL_COMMAND_FAILED: 'configure_lint_tag_parameter' command failed. [set sh_continue_on_error true] is set. Hence continuing the run.
+[Error] LINT_CMD040: In configure_hdl_tag_param, tag name W362b does not exist.
+[Warning] TCL_COMMAND_FAILED: 'configure_lint_tag_parameter' command failed. [set sh_continue_on_error true] is set. Hence continuing the run.
+[Error] LINT_CMD040: In configure_hdl_tag_param, tag name W362b does not exist.
+[Warning] TCL_COMMAND_FAILED: 'configure_lint_tag_parameter' command failed. [set sh_continue_on_error true] is set. Hence continuing the run.
+[Error] LINT_CMD040: In configure_hdl_tag_param, tag name W362b does not exist.
+[Warning] TCL_COMMAND_FAILED: 'configure_lint_tag_parameter' command failed. [set sh_continue_on_error true] is set. Hence continuing the run.
+[Error] LINT_CMD040: In configure_hdl_tag_param, tag name W110_a does not exist.
+[Warning] TCL_COMMAND_FAILED: 'configure_lint_tag_parameter' command failed. [set sh_continue_on_error true] is set. Hence continuing the run.
+[Error] LINT_CMD040: In configure_hdl_tag_param, tag name W110_a does not exist.
+[Warning] TCL_COMMAND_FAILED: 'configure_lint_tag_parameter' command failed. [set sh_continue_on_error true] is set. Hence continuing the run.
+[Error] LINT_CMD040: In configure_hdl_tag_param, tag name W110_a does not exist.
+[Warning] TCL_COMMAND_FAILED: 'configure_lint_tag_parameter' command failed. [set sh_continue_on_error true] is set. Hence continuing the run.
+[Error] LINT_CMD040: In configure_hdl_tag_param, tag name W110_b does not exist.
+[Warning] TCL_COMMAND_FAILED: 'configure_lint_tag_parameter' command failed. [set sh_continue_on_error true] is set. Hence continuing the run.
+[Error] LINT_CMD040: In configure_hdl_tag_param, tag name W110_b does not exist.
+[Warning] TCL_COMMAND_FAILED: 'configure_lint_tag_parameter' command failed. [set sh_continue_on_error true] is set. Hence continuing the run.
+[Error] LINT_CMD040: In configure_hdl_tag_param, tag name W110_b does not exist.
+[Warning] TCL_COMMAND_FAILED: 'configure_lint_tag_parameter' command failed. [set sh_continue_on_error true] is set. Hence continuing the run.
+[Error] LINT_CMD040: In configure_hdl_tag_param, tag name 70094 does not exist.
+[Warning] TCL_COMMAND_FAILED: 'configure_lint_tag_parameter' command failed. [set sh_continue_on_error true] is set. Hence continuing the run.
+[Error] LINT_CMD040: In configure_hdl_tag_param, tag name 60000_a does not exist.
+[Warning] TCL_COMMAND_FAILED: 'configure_lint_tag_parameter' command failed. [set sh_continue_on_error true] is set. Hence continuing the run.
+[Error] LINT_CMD040: In configure_hdl_tag_param, tag name 50520 does not exist.
+[Warning] TCL_COMMAND_FAILED: 'configure_lint_tag_parameter' command failed. [set sh_continue_on_error true] is set. Hence continuing the run.
+[Error] LINT_CMD040: In configure_hdl_tag_param, tag name 50520 does not exist.
+[Warning] TCL_COMMAND_FAILED: 'configure_lint_tag_parameter' command failed. [set sh_continue_on_error true] is set. Hence continuing the run.
+[Error] LINT_CMD042: In configure_hdl_tag_param, tag name ExprParen and parameter name IGNORE_MODULE are not associated, ignore the command.
+[Error] LINT_CMD042: In configure_hdl_tag_param, tag name ExprParen and parameter name IGNORE_MODULE are not associated, ignore the command.
+[Error] LINT_CMD042: In configure_hdl_tag_param, tag name ExprParen and parameter name IGNORE_MODULE are not associated, ignore the command.
+[Error] LINT_CMD040: In configure_hdl_tag_param, tag name 2216 does not exist.
+[Warning] TCL_COMMAND_FAILED: 'configure_lint_tag_parameter' command failed. [set sh_continue_on_error true] is set. Hence continuing the run.
+[Error] LINT_CMD040: In configure_hdl_tag_param, tag name 50002 does not exist.
+[Warning] TCL_COMMAND_FAILED: 'configure_lint_tag_parameter' command failed. [set sh_continue_on_error true] is set. Hence continuing the run.
+[Error] LINT_CMD040: In configure_hdl_tag_param, tag name 50002 does not exist.
+[Warning] TCL_COMMAND_FAILED: 'configure_lint_tag_parameter' command failed. [set sh_continue_on_error true] is set. Hence continuing the run.
+[Error] LINT_CMD040: In configure_hdl_tag_param, tag name ParamReDefined does not exist.
+[Warning] TCL_COMMAND_FAILED: 'configure_lint_tag_parameter' command failed. [set sh_continue_on_error true] is set. Hence continuing the run.
+[Error] LINT_CMD040: In configure_hdl_tag_param, tag name ParamReDefined does not exist.
+[Warning] TCL_COMMAND_FAILED: 'configure_lint_tag_parameter' command failed. [set sh_continue_on_error true] is set. Hence continuing the run.
+[Error] LINT_CMD040: In configure_hdl_tag_param, tag name 60130 does not exist.
+[Warning] TCL_COMMAND_FAILED: 'configure_lint_tag_parameter' command failed. [set sh_continue_on_error true] is set. Hence continuing the run.
+[Error] RDB_CONFIGURE_BAD_TAG: None of the tag pattern(s) 'DetectUnderAndOverFlows-ML' (/users/amonemi/ProNoC/mpsoc/Integration_test/VCST/src/lint_rules.tcl:1298) were found.
+	Revise your tag list and try again..
+[Warning] TCL_COMMAND_FAILED: 'configure_tag' command failed. [set sh_continue_on_error true] is set. Hence continuing the run.
+[Error] LINT_CMD041: In configure_hdl_tag_param, parameter name DIFFERENTIATE_NESTED_CAST does not exist.
+[Warning] TCL_COMMAND_FAILED: 'configure_lint_tag_parameter' command failed. [set sh_continue_on_error true] is set. Hence continuing the run.
+[Error] LINT_CMD040: In configure_hdl_tag_param, tag name CheckGuardMacro does not exist.
+[Warning] TCL_COMMAND_FAILED: 'configure_lint_tag_parameter' command failed. [set sh_continue_on_error true] is set. Hence continuing the run.
+[Error] RDB_CONFIGURE_BAD_TAG: None of the tag pattern(s) 'AvoidMultiDimParam-ML' (/users/amonemi/ProNoC/mpsoc/Integration_test/VCST/src/lint_rules.tcl:1322) were found.
+	Revise your tag list and try again..
+[Warning] TCL_COMMAND_FAILED: 'configure_tag' command failed. [set sh_continue_on_error true] is set. Hence continuing the run.
+[Info] COM_OPT030: Accepted message severity specification
+[Info] COM_OPT030: Accepted message severity specification
+[Error] RDB_CONFIGURE_BAD_TAG: None of the tag pattern(s) 'VC_WAIVER_ONLY_TAG_GIVEN' (/users/amonemi/ProNoC/mpsoc/Integration_test/VCST/src/lint_rules.tcl:1352) were found.
+	Revise your tag list and try again..
+[Warning] TCL_COMMAND_FAILED: 'configure_tag' command failed. [set sh_continue_on_error true] is set. Hence continuing the run.
+[Info] COM_OPT030: Accepted message severity specification
+[Info] COM_OPT030: Accepted message severity specification
+[Info] COM_OPT030: Accepted message severity specification
+[Info] COM_OPT030: Accepted message severity specification
+[Info] COM_OPT030: Accepted message severity specification
+[Info] COM_OPT030: Accepted message severity specification
+[Info] COM_OPT030: Accepted message severity specification
+[Info] COM_OPT030: Accepted message severity specification
+[Info] COM_OPT030: Accepted message severity specification
+[Info] COM_OPT030: Accepted message severity specification
+[Info] COM_OPT030: Accepted message severity specification
+[Info] COM_OPT030: Accepted message severity specification
+[Info] COM_OPT030: Accepted message severity specification
+[Info] COM_OPT030: Accepted message severity specification
+[Info] COM_OPT030: Accepted message severity specification
+[Info] COM_OPT030: Accepted message severity specification
+[Info] COM_OPT030: Accepted message severity specification
+[Info] COM_OPT030: Accepted message severity specification
+[Info] COM_OPT030: Accepted message severity specification
+[Info] COM_OPT030: Accepted message severity specification
+[Info] COM_OPT030: Accepted message severity specification
+[Info] COM_OPT030: Accepted message severity specification
+[Info] COM_OPT030: Accepted message severity specification
+[Info] COM_OPT030: Accepted message severity specification
+# Replace this with the actual path to your .f file
+set filelist_path $::env(FILE_LIST)
+/users/amonemi/ProNoC/mpsoc/Integration_test/VCST/src/file_list.f
+# Loop through lines
+# File handle and storage
+set fp [open $filelist_path r]
+file29
+while {[gets $fp line] >= 0} {
+    set line [string trim $line]
+
+    # Skip empty lines and comments
+    if {$line eq "" || [string match "#*" $line]} {
+        continue
+    }
+
+    # Handle +incdir+<path>
+    #if {[string match "+incdir+*" $line]} {
+    #    set incdir [string range $line 8 end]
+    # set_option include_path $incdir
+    #    continue
+    #}
+
+    # Add source file
+    lappend names_list $line
+}
+close $fp
+analyze -format sverilog    "$names_list"
+
+Warning-[UTSFM] Unspecified `timescale for module
+./../../rtl/src_topology/./common/custom_ni_routing.v, 2
+  Module "custom_ni_routing" has `timescale but previous module(s) do not.
+  Please either remove this module's timescale or add timescale for previous 
+  module(s)to avoid unexpected simulation result.
+
+
+Warning-[UTSFM] Unspecified `timescale for module
+./../../rtl/src_topology/./common/custom_noc_top.sv, 3
+  Module "custom_noc_top" has `timescale but previous module(s) do not.
+  Please either remove this module's timescale or add timescale for previous 
+  module(s)to avoid unexpected simulation result.
+
+
+Warning-[UTSFM] Unspecified `timescale for module
+./../../rtl/src_topology/./common/custom_lkh_routing.v, 3
+  Module "custom_lkh_routing" has `timescale but previous module(s) do not.
+  Please either remove this module's timescale or add timescale for previous 
+  module(s)to avoid unexpected simulation result.
+
+1
+elaborate $DESIGN
+[Warning] COM_OPT009: 'search_path' has not been set.
+[Warning] COM_OPT010: 'link_library' has not been set.
+
+Warning-[LCA_FEATURES_ENABLED] Usage warning
+  LCA features enabled by '-lca' argument on the command line.  For more 
+  information regarding list of LCA features please refer to Chapter "LCA 
+  features" in the VCS Release Notes
+
+Doing common elaboration 
+
+Warning-[UESU] Incorrect -error switch used
+  Message ID 'SM_TUFC' is not an error ID , it is invalid to specify 
+  'noSM_TUFC' only in -error switch without 'all' argument in front of it.
+  If you meant to upgrade all messages to error except for ID 'SM_TUFC', 
+  please use '-error=all,noSM_TUFC'.
+
+
+Warning-[UESU] Incorrect -error switch used
+  Message ID 'SM_PNP' is not an error ID , it is invalid to specify 'noSM_PNP'
+  only in -error switch without 'all' argument in front of it.
+  If you meant to upgrade all messages to error except for ID 'SM_PNP', please
+  use '-error=all,noSM_PNP'.
+
+
+Warning-[UESU] Incorrect -error switch used
+  Message ID 'SM_PCNP' is not an error ID , it is invalid to specify 
+  'noSM_PCNP' only in -error switch without 'all' argument in front of it.
+  If you meant to upgrade all messages to error except for ID 'SM_PCNP', 
+  please use '-error=all,noSM_PCNP'.
+
+
+Warning-[UESU] Incorrect -error switch used
+  Message ID 'SM_FCNF' is not an error ID , it is invalid to specify 
+  'noSM_FCNF' only in -error switch without 'all' argument in front of it.
+  If you meant to upgrade all messages to error except for ID 'SM_FCNF', 
+  please use '-error=all,noSM_FCNF'.
+
+Final timescale is '1ps/1ps'
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 83
+"router_chan_out[(0 - 1)][pronoc_pkg::FORWARD]"
+  The select index is out of declared bounds : [3:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+
+Warning-[SIOB] Select index out of bounds
+./../../rtl/src_noc/./mesh_torus_noc_top.sv, 79
+"router_chan_out[(3 + 1)][pronoc_pkg::BACKWARD]"
+  The select index is out of declared bounds : [3:0].
+  In module instance : tori_noc.noc_top 
+  In module : mesh_torus_noc_top.
+
+Info: Invoking Simon...
+Info: Simon VCS Start
+=======================================================
+VCS CPU Time(s)     :0.89
+SIMON CPU Time(s)   :2.27
+SIMON Total Time(s) :0.48
+Peak Memory(MB)     :411
+=======================================================
+Info: Simon VCS Finished
+Info: Simon call complete 
+Info: Exiting after Simon Analysis 
+Verdi KDB elaboration done and the database successfully generated: 0 error(s), 0 warning(s)
+# Gate Counts 
+Number of Flat Instances = 65472
+Number of Operator = 65472
+Number of Libcells = 0
+Number of Black-Box Instances = 0
+
+1
+#read_sdc $constraints_path
+# Need to add this waiver in here, otherwise is not applicable
+#source ${script_dir}/waiver.tcl
+check_lint
+[2025-06-05.14:55:11] Queuing for License......
+Waiting to acquire VC-LINT-BASE license in 259200 seconds...
+[Info] Loading Lint Structural Checker Plugin... Success
+Inferring all potential clocks
+Inferring all potential resets
+1
+report_lint -verbose -file ${report_filename}
+1
+report_lint
+
+  -----------------------------------------------------------------------------
+  Management Summary
+  -----------------------------------------------------------------------------
+  Stage             Family      Fatals    Errors  Warnings     Infos  Compressed
+  -----             --------  --------  --------  --------  --------  ----------
+  BUILTIN_CHECK     CODING           0        81         0         0           0
+  LANGUAGE_CHECK    CODING           0      1417      1662         6           0
+  STRUCTURAL_CHECK  CODING           0         8       727         1         463
+  STRUCTURAL_CHECK  CONN             0         0      1656         0           0
+  -----             --------  --------  --------  --------  --------  ----------
+  Total                              0      1506      4045         7         463
+
+
+  -----------------------------------------------------------------------------
+  Tree Summary
+  -----------------------------------------------------------------------------
+  Severity  Stage             Tag                       Count  Compressed
+  --------  -----             ------------------------  -----  ----------
+  error     BUILTIN_CHECK     ExprParen                    81           0
+  error     LANGUAGE_CHECK    AlwaysFalseTrueCond-ML     1157           0
+  error     LANGUAGE_CHECK    NoAssignX-ML                 15           0
+  error     LANGUAGE_CHECK    OneModule-ML                 14           0
+  error     LANGUAGE_CHECK    STARC05-1.1.1.1               8           0
+  error     LANGUAGE_CHECK    STARC05-1.1.1.3             154           0
+  error     LANGUAGE_CHECK    STARC05-2.10.3.7              8           0
+  error     LANGUAGE_CHECK    SignedUnsignedExpr-ML         1           0
+  error     LANGUAGE_CHECK    UseSVAlways-ML               13           0
+  error     LANGUAGE_CHECK    W121                          6           0
+  error     LANGUAGE_CHECK    W123                         37           0
+  error     LANGUAGE_CHECK    W215                          1           0
+  error     LANGUAGE_CHECK    W416                          3           0
+  error     LANGUAGE_CHECK    W504                          1           0
+  error     STRUCTURAL_CHECK  FlopEConst                    1           0
+  error     STRUCTURAL_CHECK  UndrivenOutPort-ML            7           4
+  warning   LANGUAGE_CHECK    ConstName                    95           0
+  warning   LANGUAGE_CHECK    FileHdr                      24           0
+  warning   LANGUAGE_CHECK    ImproperRangeIndex-ML         1           0
+  warning   LANGUAGE_CHECK    ParamName                   178           0
+  warning   LANGUAGE_CHECK    PortName                    155           0
+  warning   LANGUAGE_CHECK    STARC05-1.1.1.2               4           0
+  warning   LANGUAGE_CHECK    SigName                       5           0
+  warning   LANGUAGE_CHECK    W120                        176           0
+  warning   LANGUAGE_CHECK    W175                         40           0
+  warning   LANGUAGE_CHECK    W240                        902           0
+  warning   LANGUAGE_CHECK    W241                         25           0
+  warning   LANGUAGE_CHECK    W287a                        36           0
+  warning   LANGUAGE_CHECK    W287b                        23           0
+  warning   LANGUAGE_CHECK    W468                          1           0
+  warning   STRUCTURAL_CHECK  RegInput-ML                 150         157
+  warning   STRUCTURAL_CHECK  RegOutputs                  160         300
+  warning   STRUCTURAL_CHECK  UndrivenNUnloaded-ML        369           0
+  warning   STRUCTURAL_CHECK  UnloadedInPort-ML           907           0
+  warning   STRUCTURAL_CHECK  UnloadedNet-ML               48           0
+  warning   STRUCTURAL_CHECK  UnloadedOutTerm-ML          749           0
+  info      LANGUAGE_CHECK    NoExprInPort-ML               1           0
+  info      LANGUAGE_CHECK    ReportPortInfo-ML             1           0
+  info      STRUCTURAL_CHECK  AvoidAsync                    1           2
+  --------  -----             ------------------------  -----  ----------
+  Total                                                  5558         463
+
+
+1
+exit 0
+=======================================================
+Total Time(S)  :191.15
+CPU Time(S)    :45.49
+Peak Memory(MB):1264
+=======================================================
diff --git a/mpsoc/Integration_test/VCST/Golden_ref/line4_smart3_vc_static.txt b/mpsoc/Integration_test/VCST/Golden_ref/line4_smart3_vc_static.txt
new file mode 100644
index 0000000..d48e414
--- /dev/null
+++ b/mpsoc/Integration_test/VCST/Golden_ref/line4_smart3_vc_static.txt
@@ -0,0 +1,17558 @@
+
+  -----------------------------------------------------------------------------
+  Report Summary
+  -----------------------------------------------------------------------------
+  Product Info
+    Name    : VC Static Master Shell
+    Version : T-2022.06-SP2 -- Nov 29, 2022
+
+  Report Info
+    Created : Jun 05, 2025  14:57:59
+
+    TopLevelModule: noc_top
+
+  -----------------------------------------------------------------------------
+  Management Summary
+  -----------------------------------------------------------------------------
+  Stage             Family      Fatals    Errors  Warnings     Infos  Compressed
+  -----             --------  --------  --------  --------  --------  ----------
+  BUILTIN_CHECK     CODING           0        81         0         0           0
+  LANGUAGE_CHECK    CODING           0      1417      1662         6           0
+  STRUCTURAL_CHECK  CODING           0         8       727         1         463
+  STRUCTURAL_CHECK  CONN             0         0      1656         0           0
+  -----             --------  --------  --------  --------  --------  ----------
+  Total                              0      1506      4045         7         463
+
+
+  -----------------------------------------------------------------------------
+  Tree Summary
+  -----------------------------------------------------------------------------
+  Severity  Stage             Tag                       Count  Compressed
+  --------  -----             ------------------------  -----  ----------
+  error     BUILTIN_CHECK     ExprParen                    81           0
+  error     LANGUAGE_CHECK    AlwaysFalseTrueCond-ML     1157           0 *
+  error     LANGUAGE_CHECK    NoAssignX-ML                 15           0
+  error     LANGUAGE_CHECK    OneModule-ML                 14           0
+  error     LANGUAGE_CHECK    STARC05-1.1.1.1               8           0
+  error     LANGUAGE_CHECK    STARC05-1.1.1.3             154           0 *
+  error     LANGUAGE_CHECK    STARC05-2.10.3.7              8           0
+  error     LANGUAGE_CHECK    SignedUnsignedExpr-ML         1           0
+  error     LANGUAGE_CHECK    UseSVAlways-ML               13           0
+  error     LANGUAGE_CHECK    W121                          6           0
+  error     LANGUAGE_CHECK    W123                         37           0
+  error     LANGUAGE_CHECK    W215                          1           0
+  error     LANGUAGE_CHECK    W416                          3           0
+  error     LANGUAGE_CHECK    W504                          1           0
+  error     STRUCTURAL_CHECK  FlopEConst                    1           0
+  error     STRUCTURAL_CHECK  UndrivenOutPort-ML            7           4
+  warning   LANGUAGE_CHECK    ConstName                    95           0
+  warning   LANGUAGE_CHECK    FileHdr                      24           0
+  warning   LANGUAGE_CHECK    ImproperRangeIndex-ML         1           0
+  warning   LANGUAGE_CHECK    ParamName                   178           0 *
+  warning   LANGUAGE_CHECK    PortName                    155           0 *
+  warning   LANGUAGE_CHECK    STARC05-1.1.1.2               4           0
+  warning   LANGUAGE_CHECK    SigName                       5           0
+  warning   LANGUAGE_CHECK    W120                        176           0 *
+  warning   LANGUAGE_CHECK    W175                         40           0
+  warning   LANGUAGE_CHECK    W240                        902           0 *
+  warning   LANGUAGE_CHECK    W241                         25           0
+  warning   LANGUAGE_CHECK    W287a                        36           0
+  warning   LANGUAGE_CHECK    W287b                        23           0
+  warning   LANGUAGE_CHECK    W468                          1           0
+  warning   STRUCTURAL_CHECK  RegInput-ML                 150         157 *
+  warning   STRUCTURAL_CHECK  RegOutputs                  160         300 *
+  warning   STRUCTURAL_CHECK  UndrivenNUnloaded-ML        369           0 *
+  warning   STRUCTURAL_CHECK  UnloadedInPort-ML           907           0 *
+  warning   STRUCTURAL_CHECK  UnloadedNet-ML               48           0
+  warning   STRUCTURAL_CHECK  UnloadedOutTerm-ML          749           0 *
+  info      LANGUAGE_CHECK    NoExprInPort-ML               1           0
+  info      LANGUAGE_CHECK    ReportPortInfo-ML             1           0
+  info      STRUCTURAL_CHECK  AvoidAsync                    1           2
+  --------  -----             ------------------------  -----  ----------
+  Total                                                  5558         463
+
+  * The following detailed reports have been limited to 100 per tag.
+
+
+  -----------------------------------------------------------------------------
+  AlwaysFalseTrueCond-ML  (1157 errors/0 waived)
+  -----------------------------------------------------------------------------
+  Tag            : AlwaysFalseTrueCond-ML
+  Description    : Condition '[RTL_CONDITION]' can never be '[NodeType]' [Hierarchy: '[HIERARCHY]']
+  Violation      : Lint:5097
+  Goal           : lint_rtl
+  Module         : input_queue_per_port
+  FileName       : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber     : 508
+  Statement      :         if(IS_MULTI_MESH==0) begin :ovc_
+  RTL_CONDITION  : (IS_MULTI_MESH==0)
+  NodeType       : false
+  HIERARCHY      : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[1].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[1].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag            : AlwaysFalseTrueCond-ML
+  Description    : Condition '[RTL_CONDITION]' can never be '[NodeType]' [Hierarchy: '[HIERARCHY]']
+  Violation      : Lint:4225
+  Goal           : lint_rtl
+  Module         : input_queue_per_port
+  FileName       : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber     : 234
+  Statement      :         P_1 = (SELF_LOOP_EN )?  P : P-1,
+  RTL_CONDITION  : SELF_LOOP_EN
+  NodeType       : false
+  HIERARCHY      : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[2].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag            : AlwaysFalseTrueCond-ML
+  Description    : Condition '[RTL_CONDITION]' can never be '[NodeType]' [Hierarchy: '[HIERARCHY]']
+  Violation      : Lint:5713
+  Goal           : lint_rtl
+  Module         : input_queue_per_port
+  FileName       : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber     : 947
+  Statement      :     if(CAST_TYPE== "UNICAST") begin : unicast
+  RTL_CONDITION  : (CAST_TYPE=="UNICAST")
+  NodeType       : false
+  HIERARCHY      : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[3].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[0].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag            : AlwaysFalseTrueCond-ML
+  Description    : Condition '[RTL_CONDITION]' can never be '[NodeType]' [Hierarchy: '[HIERARCHY]']
+  Violation      : Lint:5776
+  Goal           : lint_rtl
+  Module         : input_queue_per_port
+  FileName       : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber     : 406
+  Statement      :     if (( TOPOLOGY == "RING" || TOPOLOGY == "LINE" || TOPOLOGY == "MESH" || TOPOLOGY == "TORUS") && (T3>1) && CAST_TYPE== "UNICAST") begin : multi_local
+  RTL_CONDITION  : (TOPOLOGY=="MESH")
+  NodeType       : true
+  HIERARCHY      : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[3].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[1].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag            : AlwaysFalseTrueCond-ML
+  Description    : Condition '[RTL_CONDITION]' can never be '[NodeType]' [Hierarchy: '[HIERARCHY]']
+  Violation      : Lint:4126
+  Goal           : lint_rtl
+  Module         : mesh_torus_destp_generator
+  FileName       : ./../../rtl/src_noc/./mesh_torus.sv
+  LineNumber     : 1145
+  Statement      :     if (TOPOLOGY == "RING" || TOPOLOGY == "LINE" ) begin : one_D
+  RTL_CONDITION  : ((TOPOLOGY=="RING")||(TOPOLOGY=="LINE"))
+  NodeType       : false
+  HIERARCHY      : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[1].the_input_queue_per_port @input_queue_per_port:\V_[0].decoder @destp_generator:\mesh.destp_generator @mesh_torus_destp_generator
+  -----------------------------------------------------------------------------
+  Tag            : AlwaysFalseTrueCond-ML
+  Description    : Condition '[RTL_CONDITION]' can never be '[NodeType]' [Hierarchy: '[HIERARCHY]']
+  Violation      : Lint:5686
+  Goal           : lint_rtl
+  Module         : input_queue_per_port
+  FileName       : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber     : 441
+  Statement      :     if(TOPOLOGY=="FATTREE" && ROUTE_NAME == "NCA_STRAIGHT_UP") begin : fat
+  RTL_CONDITION  : (ROUTE_NAME=="NCA_STRAIGHT_UP")
+  NodeType       : true
+  HIERARCHY      : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[3].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[0].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag            : AlwaysFalseTrueCond-ML
+  Description    : Condition '[RTL_CONDITION]' can never be '[NodeType]' [Hierarchy: '[HIERARCHY]']
+  Violation      : Lint:5670
+  Goal           : lint_rtl
+  Module         : input_queue_per_port
+  FileName       : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber     : 406
+  Statement      :     if (( TOPOLOGY == "RING" || TOPOLOGY == "LINE" || TOPOLOGY == "MESH" || TOPOLOGY == "TORUS") && (T3>1) && CAST_TYPE== "UNICAST") begin : multi_local
+  RTL_CONDITION  : ((((((TOPOLOGY=="RING")||(TOPOLOGY=="LINE"))||(TOPOLOGY=="MESH"))||(TOPOLOGY=="TORUS"))&&(T3 > 1))&&(CAST_TYPE=="UNICAST"))
+  NodeType       : true
+  HIERARCHY      : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[3].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[0].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag            : AlwaysFalseTrueCond-ML
+  Description    : Condition '[RTL_CONDITION]' can never be '[NodeType]' [Hierarchy: '[HIERARCHY]']
+  Violation      : Lint:3564
+  Goal           : lint_rtl
+  Module         : noc_top
+  FileName       : ./../../rtl/src_noc/./topology_localparam.v
+  LineNumber     : 275
+  Statement      :         NE =
+  RTL_CONDITION  : ((IS_RING||IS_LINE)||IS_MESH)
+  NodeType       : false
+  HIERARCHY      : :noc_top
+  -----------------------------------------------------------------------------
+  Tag            : AlwaysFalseTrueCond-ML
+  Description    : Condition '[RTL_CONDITION]' can never be '[NodeType]' [Hierarchy: '[HIERARCHY]']
+  Violation      : Lint:5194
+  Goal           : lint_rtl
+  Module         : input_queue_per_port
+  FileName       : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber     : 480
+  Statement      :             ( MIN_PCK_SIZE == 1 )? flit_is_tail[i] & ~ovc_is_assigned[i] :  1'b0; 
+  RTL_CONDITION  : (MIN_PCK_SIZE==1)
+  NodeType       : true
+  HIERARCHY      : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[1].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[2].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag            : AlwaysFalseTrueCond-ML
+  Description    : Condition '[RTL_CONDITION]' can never be '[NodeType]' [Hierarchy: '[HIERARCHY]']
+  Violation      : Lint:5895
+  Goal           : lint_rtl
+  Module         : input_queue_per_port
+  FileName       : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber     : 667
+  Statement      :         if(CAST_TYPE!= "UNICAST") begin : muticast
+  RTL_CONDITION  : (CAST_TYPE!="UNICAST")
+  NodeType       : true
+  HIERARCHY      : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[3].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[2].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag            : AlwaysFalseTrueCond-ML
+  Description    : Condition '[RTL_CONDITION]' can never be '[NodeType]' [Hierarchy: '[HIERARCHY]']
+  Violation      : Lint:3627
+  Goal           : lint_rtl
+  Module         : mesh_torus_noc_top
+  FileName       : ./../../rtl/src_noc/./mesh_torus_noc_top.sv
+  LineNumber     : 80
+  Statement      :                 (x < NX-1) ?  router_chan_out[x+1][BACKWARD] : 
+  RTL_CONDITION  : (x < (NX - 1))
+  NodeType       : false
+  HIERARCHY      : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top
+  -----------------------------------------------------------------------------
+  Tag            : AlwaysFalseTrueCond-ML
+  Description    : Condition '[RTL_CONDITION]' can never be '[NodeType]' [Hierarchy: '[HIERARCHY]']
+  Violation      : Lint:4797
+  Goal           : lint_rtl
+  Module         : conventional_routing
+  FileName       : ./../../rtl/src_noc/./routing.v
+  LineNumber     : 69
+  Statement      :     if(TOPOLOGY == "MESH" || TOPOLOGY == "FMESH" || TOPOLOGY == "TORUS"  || TOPOLOGY ==  "RING" || TOPOLOGY ==  "LINE") begin :mesh_torus
+  RTL_CONDITION  : (((TOPOLOGY=="MESH")||(TOPOLOGY=="FMESH"))||(TOPOLOGY=="TORUS"))
+  NodeType       : true
+  HIERARCHY      : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:\smart.Port_[1].smart_en.smart_allocator @smart_allocator_per_iport:routing@conventional_routing
+  -----------------------------------------------------------------------------
+  Tag            : AlwaysFalseTrueCond-ML
+  Description    : Condition '[RTL_CONDITION]' can never be '[NodeType]' [Hierarchy: '[HIERARCHY]']
+  Violation      : Lint:5521
+  Goal           : lint_rtl
+  Module         : input_queue_per_port
+  FileName       : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber     : 332
+  Statement      :     assign smart_hdr_en  = (SMART_EN) ? smart_ctrl_in.ivc_num_getting_ovc_grant: {V{1'b0}};
+  RTL_CONDITION  : SMART_EN
+  NodeType       : false
+  HIERARCHY      : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[2].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[2].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag            : AlwaysFalseTrueCond-ML
+  Description    : Condition '[RTL_CONDITION]' can never be '[NodeType]' [Hierarchy: '[HIERARCHY]']
+  Violation      : Lint:5709
+  Goal           : lint_rtl
+  Module         : input_queue_per_port
+  FileName       : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber     : 846
+  Statement      :         if(SWA_ARBITER_TYPE != "RRA")begin  : wrra
+  RTL_CONDITION  : (SWA_ARBITER_TYPE!="RRA")
+  NodeType       : true
+  HIERARCHY      : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[3].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[0].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag            : AlwaysFalseTrueCond-ML
+  Description    : Condition '[RTL_CONDITION]' can never be '[NodeType]' [Hierarchy: '[HIERARCHY]']
+  Violation      : Lint:4071
+  Goal           : lint_rtl
+  Module         : input_queue_per_port
+  FileName       : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber     : 800
+  Statement      :         if (( TOPOLOGY == "RING" || TOPOLOGY == "LINE" || TOPOLOGY == "MESH" || TOPOLOGY == "TORUS") && (T3>1) && (CAST_TYPE== "UNICAST")) begin : multi_local
+  RTL_CONDITION  : (((((TOPOLOGY=="RING")||(TOPOLOGY=="LINE"))||(TOPOLOGY=="MESH"))||(TOPOLOGY=="TORUS"))&&(T3 > 1))
+  NodeType       : true
+  HIERARCHY      : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[1].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag            : AlwaysFalseTrueCond-ML
+  Description    : Condition '[RTL_CONDITION]' can never be '[NodeType]' [Hierarchy: '[HIERARCHY]']
+  Violation      : Lint:5668
+  Goal           : lint_rtl
+  Module         : input_queue_per_port
+  FileName       : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber     : 247
+  Statement      :         PLw = (IS_FMESH) ? Pw : ELw,
+  RTL_CONDITION  : IS_FMESH
+  NodeType       : true
+  HIERARCHY      : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[3].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[0].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag            : AlwaysFalseTrueCond-ML
+  Description    : Condition '[RTL_CONDITION]' can never be '[NodeType]' [Hierarchy: '[HIERARCHY]']
+  Violation      : Lint:5877
+  Goal           : lint_rtl
+  Module         : input_queue_per_port
+  FileName       : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber     : 406
+  Statement      :     if (( TOPOLOGY == "RING" || TOPOLOGY == "LINE" || TOPOLOGY == "MESH" || TOPOLOGY == "TORUS") && (T3>1) && CAST_TYPE== "UNICAST") begin : multi_local
+  RTL_CONDITION  : (TOPOLOGY=="RING")
+  NodeType       : true
+  HIERARCHY      : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[3].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[2].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag            : AlwaysFalseTrueCond-ML
+  Description    : Condition '[RTL_CONDITION]' can never be '[NodeType]' [Hierarchy: '[HIERARCHY]']
+  Violation      : Lint:5799
+  Goal           : lint_rtl
+  Module         : input_queue_per_port
+  FileName       : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber     : 800
+  Statement      :         if (( TOPOLOGY == "RING" || TOPOLOGY == "LINE" || TOPOLOGY == "MESH" || TOPOLOGY == "TORUS") && (T3>1) && (CAST_TYPE== "UNICAST")) begin : multi_local
+  RTL_CONDITION  : (TOPOLOGY=="RING")
+  NodeType       : true
+  HIERARCHY      : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[3].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[1].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag            : AlwaysFalseTrueCond-ML
+  Description    : Condition '[RTL_CONDITION]' can never be '[NodeType]' [Hierarchy: '[HIERARCHY]']
+  Violation      : Lint:5437
+  Goal           : lint_rtl
+  Module         : input_queue_per_port
+  FileName       : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber     : 441
+  Statement      :     if(TOPOLOGY=="FATTREE" && ROUTE_NAME == "NCA_STRAIGHT_UP") begin : fat
+  RTL_CONDITION  : ((TOPOLOGY=="FATTREE")&&(ROUTE_NAME=="NCA_STRAIGHT_UP"))
+  NodeType       : true
+  HIERARCHY      : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[2].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[1].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag            : AlwaysFalseTrueCond-ML
+  Description    : Condition '[RTL_CONDITION]' can never be '[NodeType]' [Hierarchy: '[HIERARCHY]']
+  Violation      : Lint:4109
+  Goal           : lint_rtl
+  Module         : fwft_fifo
+  FileName       : ./../../rtl/src_noc/./flit_buffer.sv
+  LineNumber     : 586
+  Statement      :     if(MAX_DEPTH>2) begin :mwb2
+  RTL_CONDITION  : (MAX_DEPTH > 2)
+  NodeType       : false
+  HIERARCHY      : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[1].the_input_queue_per_port @input_queue_per_port:\V_[0].smart_.dest_e_addr_fifo @fwft_fifo
+  -----------------------------------------------------------------------------
+  Tag            : AlwaysFalseTrueCond-ML
+  Description    : Condition '[RTL_CONDITION]' can never be '[NodeType]' [Hierarchy: '[HIERARCHY]']
+  Violation      : Lint:4087
+  Goal           : lint_rtl
+  Module         : input_queue_per_port
+  FileName       : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber     : 929
+  Statement      :     if(PORT_IVC != V) begin : hetero
+  RTL_CONDITION  : (PORT_IVC!=V)
+  NodeType       : true
+  HIERARCHY      : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[1].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag            : AlwaysFalseTrueCond-ML
+  Description    : Condition '[RTL_CONDITION]' can never be '[NodeType]' [Hierarchy: '[HIERARCHY]']
+  Violation      : Lint:4272
+  Goal           : lint_rtl
+  Module         : input_queue_per_port
+  FileName       : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber     : 821
+  Statement      :         end else if ( TOPOLOGY == "FMESH" && CAST_TYPE== "UNICAST") begin : fmesh
+  RTL_CONDITION  : (CAST_TYPE=="UNICAST")
+  NodeType       : false
+  HIERARCHY      : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[2].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag            : AlwaysFalseTrueCond-ML
+  Description    : Condition '[RTL_CONDITION]' can never be '[NodeType]' [Hierarchy: '[HIERARCHY]']
+  Violation      : Lint:3587
+  Goal           : lint_rtl
+  Module         : noc_top
+  FileName       : ./../../rtl/src_noc/./pronoc_pkg.sv
+  LineNumber     : 26
+  Statement      :         SMART_EN = (SMART_MAX !=0),
+  RTL_CONDITION  : (SMART_MAX!=0)
+  NodeType       : false
+  HIERARCHY      : :noc_top
+  -----------------------------------------------------------------------------
+  Tag            : AlwaysFalseTrueCond-ML
+  Description    : Condition '[RTL_CONDITION]' can never be '[NodeType]' [Hierarchy: '[HIERARCHY]']
+  Violation      : Lint:4111
+  Goal           : lint_rtl
+  Module         : destp_generator
+  FileName       : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber     : 1112
+  Statement      :     localparam P_1 = (SELF_LOOP_EN )?  P : P-1;
+  RTL_CONDITION  : SELF_LOOP_EN
+  NodeType       : false
+  HIERARCHY      : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[1].the_input_queue_per_port @input_queue_per_port:\V_[0].decoder @destp_generator
+  -----------------------------------------------------------------------------
+  Tag            : AlwaysFalseTrueCond-ML
+  Description    : Condition '[RTL_CONDITION]' can never be '[NodeType]' [Hierarchy: '[HIERARCHY]']
+  Violation      : Lint:5784
+  Goal           : lint_rtl
+  Module         : input_queue_per_port
+  FileName       : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber     : 441
+  Statement      :     if(TOPOLOGY=="FATTREE" && ROUTE_NAME == "NCA_STRAIGHT_UP") begin : fat
+  RTL_CONDITION  : (TOPOLOGY=="FATTREE")
+  NodeType       : true
+  HIERARCHY      : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[3].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[1].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag            : AlwaysFalseTrueCond-ML
+  Description    : Condition '[RTL_CONDITION]' can never be '[NodeType]' [Hierarchy: '[HIERARCHY]']
+  Violation      : Lint:4982
+  Goal           : lint_rtl
+  Module         : input_queue_per_port
+  FileName       : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber     : 406
+  Statement      :     if (( TOPOLOGY == "RING" || TOPOLOGY == "LINE" || TOPOLOGY == "MESH" || TOPOLOGY == "TORUS") && (T3>1) && CAST_TYPE== "UNICAST") begin : multi_local
+  RTL_CONDITION  : ((TOPOLOGY=="RING")||(TOPOLOGY=="LINE"))
+  NodeType       : false
+  HIERARCHY      : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[1].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[0].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag            : AlwaysFalseTrueCond-ML
+  Description    : Condition '[RTL_CONDITION]' can never be '[NodeType]' [Hierarchy: '[HIERARCHY]']
+  Violation      : Lint:5212
+  Goal           : lint_rtl
+  Module         : input_queue_per_port
+  FileName       : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber     : 821
+  Statement      :         end else if ( TOPOLOGY == "FMESH" && CAST_TYPE== "UNICAST") begin : fmesh
+  RTL_CONDITION  : ((TOPOLOGY=="FMESH")&&(CAST_TYPE=="UNICAST"))
+  NodeType       : true
+  HIERARCHY      : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[1].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[2].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag            : AlwaysFalseTrueCond-ML
+  Description    : Condition '[RTL_CONDITION]' can never be '[NodeType]' [Hierarchy: '[HIERARCHY]']
+  Violation      : Lint:4284
+  Goal           : lint_rtl
+  Module         : destp_generator
+  FileName       : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber     : 1166
+  Statement      :     end else if(TOPOLOGY == "RING" || TOPOLOGY == "LINE" || TOPOLOGY == "MESH"|| TOPOLOGY == "TORUS") begin : mesh
+  RTL_CONDITION  : ((TOPOLOGY=="RING")||(TOPOLOGY=="LINE"))
+  NodeType       : false
+  HIERARCHY      : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[2].the_input_queue_per_port @input_queue_per_port:\V_[0].decoder @destp_generator
+  -----------------------------------------------------------------------------
+  Tag            : AlwaysFalseTrueCond-ML
+  Description    : Condition '[RTL_CONDITION]' can never be '[NodeType]' [Hierarchy: '[HIERARCHY]']
+  Violation      : Lint:5900
+  Goal           : lint_rtl
+  Module         : input_queue_per_port
+  FileName       : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber     : 800
+  Statement      :         if (( TOPOLOGY == "RING" || TOPOLOGY == "LINE" || TOPOLOGY == "MESH" || TOPOLOGY == "TORUS") && (T3>1) && (CAST_TYPE== "UNICAST")) begin : multi_local
+  RTL_CONDITION  : (((TOPOLOGY=="RING")||(TOPOLOGY=="LINE"))||(TOPOLOGY=="MESH"))
+  NodeType       : false
+  HIERARCHY      : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[3].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[2].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag            : AlwaysFalseTrueCond-ML
+  Description    : Condition '[RTL_CONDITION]' can never be '[NodeType]' [Hierarchy: '[HIERARCHY]']
+  Violation      : Lint:5216
+  Goal           : lint_rtl
+  Module         : input_queue_per_port
+  FileName       : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber     : 868
+  Statement      :     if(SWA_ARBITER_TYPE != "RRA")begin  : wrra
+  RTL_CONDITION  : (SWA_ARBITER_TYPE!="RRA")
+  NodeType       : true
+  HIERARCHY      : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[1].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[2].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag            : AlwaysFalseTrueCond-ML
+  Description    : Condition '[RTL_CONDITION]' can never be '[NodeType]' [Hierarchy: '[HIERARCHY]']
+  Violation      : Lint:5673
+  Goal           : lint_rtl
+  Module         : input_queue_per_port
+  FileName       : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber     : 406
+  Statement      :     if (( TOPOLOGY == "RING" || TOPOLOGY == "LINE" || TOPOLOGY == "MESH" || TOPOLOGY == "TORUS") && (T3>1) && CAST_TYPE== "UNICAST") begin : multi_local
+  RTL_CONDITION  : (((TOPOLOGY=="RING")||(TOPOLOGY=="LINE"))||(TOPOLOGY=="MESH"))
+  NodeType       : false
+  HIERARCHY      : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[3].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[0].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag            : AlwaysFalseTrueCond-ML
+  Description    : Condition '[RTL_CONDITION]' can never be '[NodeType]' [Hierarchy: '[HIERARCHY]']
+  Violation      : Lint:3847
+  Goal           : lint_rtl
+  Module         : one_hot_to_bin
+  FileName       : ./../../rtl/src_noc/./../main_comp.v
+  LineNumber     : 274
+  Statement      :         if(ONE_HOT_WIDTH>1)begin :if1
+  RTL_CONDITION  : (ONE_HOT_WIDTH > 1)
+  NodeType       : true
+  HIERARCHY      : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[0].the_input_queue_per_port @input_queue_per_port:the_flit_buffer@flit_buffer:\pow2.wr_vc_start_addr @one_hot_to_bin
+  -----------------------------------------------------------------------------
+  Tag            : AlwaysFalseTrueCond-ML
+  Description    : Condition '[RTL_CONDITION]' can never be '[NodeType]' [Hierarchy: '[HIERARCHY]']
+  Violation      : Lint:5773
+  Goal           : lint_rtl
+  Module         : input_queue_per_port
+  FileName       : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber     : 406
+  Statement      :     if (( TOPOLOGY == "RING" || TOPOLOGY == "LINE" || TOPOLOGY == "MESH" || TOPOLOGY == "TORUS") && (T3>1) && CAST_TYPE== "UNICAST") begin : multi_local
+  RTL_CONDITION  : ((TOPOLOGY=="RING")||(TOPOLOGY=="LINE"))
+  NodeType       : false
+  HIERARCHY      : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[3].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[1].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag            : AlwaysFalseTrueCond-ML
+  Description    : Condition '[RTL_CONDITION]' can never be '[NodeType]' [Hierarchy: '[HIERARCHY]']
+  Violation      : Lint:3576
+  Goal           : lint_rtl
+  Module         : noc_top
+  FileName       : ./../../rtl/src_noc/./topology_localparam.v
+  LineNumber     : 296
+  Statement      :         MCASTw =
+  RTL_CONDITION  : (EAw < MCAST_PRTLw)
+  NodeType       : true
+  HIERARCHY      : :noc_top
+  -----------------------------------------------------------------------------
+  Tag            : AlwaysFalseTrueCond-ML
+  Description    : Condition '[RTL_CONDITION]' can never be '[NodeType]' [Hierarchy: '[HIERARCHY]']
+  Violation      : Lint:5070
+  Goal           : lint_rtl
+  Module         : input_queue_per_port
+  FileName       : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber     : 240
+  Statement      :         NON_ATOM_PCKS =  (PORT_B>MIN_PCK_SIZE)?  (PORT_B/MIN_PCK_SIZE)+ OFFSET : 1,
+  RTL_CONDITION  : (PORT_B > MIN_PCK_SIZE)
+  NodeType       : false
+  HIERARCHY      : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[1].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[1].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag            : AlwaysFalseTrueCond-ML
+  Description    : Condition '[RTL_CONDITION]' can never be '[NodeType]' [Hierarchy: '[HIERARCHY]']
+  Violation      : Lint:3895
+  Goal           : lint_rtl
+  Module         : remove_sw_loc_one_hot
+  FileName       : ./../../rtl/src_noc/./mesh_torus_routting.v
+  LineNumber     : 472
+  Statement      :     if(SW_LOC==0)begin :local_p
+  RTL_CONDITION  : (SW_LOC==0)
+  NodeType       : false
+  HIERARCHY      : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[0].the_input_queue_per_port @input_queue_per_port:\V_[0].decoder @destp_generator:\mesh.destp_generator @mesh_torus_destp_generator:mask_destport@mesh_torus_mask_non_assignable_destport:\slp.remove_sw_loc @remove_sw_loc_one_hot
+  -----------------------------------------------------------------------------
+  Tag            : AlwaysFalseTrueCond-ML
+  Description    : Condition '[RTL_CONDITION]' can never be '[NodeType]' [Hierarchy: '[HIERARCHY]']
+  Violation      : Lint:3679
+  Goal           : lint_rtl
+  Module         : router_two_stage
+  FileName       : ./../../rtl/src_noc/./router_two_stage.sv
+  LineNumber     : 197
+  Statement      :             if(CAST_TYPE == "UNICAST") begin : uni 
+  RTL_CONDITION  : (CAST_TYPE=="UNICAST")
+  NodeType       : false
+  HIERARCHY      : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:router_ref@router_two_stage
+  -----------------------------------------------------------------------------
+  Tag            : AlwaysFalseTrueCond-ML
+  Description    : Condition '[RTL_CONDITION]' can never be '[NodeType]' [Hierarchy: '[HIERARCHY]']
+  Violation      : Lint:5795
+  Goal           : lint_rtl
+  Module         : input_queue_per_port
+  FileName       : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber     : 800
+  Statement      :         if (( TOPOLOGY == "RING" || TOPOLOGY == "LINE" || TOPOLOGY == "MESH" || TOPOLOGY == "TORUS") && (T3>1) && (CAST_TYPE== "UNICAST")) begin : multi_local
+  RTL_CONDITION  : (((((TOPOLOGY=="RING")||(TOPOLOGY=="LINE"))||(TOPOLOGY=="MESH"))||(TOPOLOGY=="TORUS"))&&(T3 > 1))
+  NodeType       : true
+  HIERARCHY      : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[3].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[1].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag            : AlwaysFalseTrueCond-ML
+  Description    : Condition '[RTL_CONDITION]' can never be '[NodeType]' [Hierarchy: '[HIERARCHY]']
+  Violation      : Lint:4145
+  Goal           : lint_rtl
+  Module         : line_ring_destp_decoder
+  FileName       : ./../../rtl/src_noc/./mesh_torus.sv
+  LineNumber     : 1319
+  Statement      :         if(SELF_LOOP_EN == 0) begin :nslp
+  RTL_CONDITION  : (SELF_LOOP_EN==0)
+  NodeType       : true
+  HIERARCHY      : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[1].the_input_queue_per_port @input_queue_per_port:\V_[0].decoder @destp_generator:\mesh.destp_generator @mesh_torus_destp_generator:\one_D.decoder @line_ring_destp_decoder
+  -----------------------------------------------------------------------------
+  Tag            : AlwaysFalseTrueCond-ML
+  Description    : Condition '[RTL_CONDITION]' can never be '[NodeType]' [Hierarchy: '[HIERARCHY]']
+  Violation      : Lint:4783
+  Goal           : lint_rtl
+  Module         : smart_allocator_per_iport
+  FileName       : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber     : 606
+  Statement      :         (IS_RING | IS_LINE) ? (SW_LOC == 0 || SW_LOC > 2) :
+  RTL_CONDITION  : (SW_LOC==0)
+  NodeType       : true
+  HIERARCHY      : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:\smart.Port_[1].smart_en.smart_allocator @smart_allocator_per_iport
+  -----------------------------------------------------------------------------
+  Tag            : AlwaysFalseTrueCond-ML
+  Description    : Condition '[RTL_CONDITION]' can never be '[NodeType]' [Hierarchy: '[HIERARCHY]']
+  Violation      : Lint:4315
+  Goal           : lint_rtl
+  Module         : look_ahead_routing
+  FileName       : ./../../rtl/src_noc/./routing.v
+  LineNumber     : 287
+  Statement      :     if(TOPOLOGY == "MESH" || TOPOLOGY == "FMESH" || TOPOLOGY == "TORUS"  || TOPOLOGY ==  "RING" || TOPOLOGY ==  "LINE")begin :mesh_torus
+  RTL_CONDITION  : (((((TOPOLOGY=="MESH")||(TOPOLOGY=="FMESH"))||(TOPOLOGY=="TORUS"))||(TOPOLOGY=="RING"))||(TOPOLOGY=="LINE"))
+  NodeType       : false
+  HIERARCHY      : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[2].the_input_queue_per_port @input_queue_per_port:\unicast.lk_routing @look_ahead_routing
+  -----------------------------------------------------------------------------
+  Tag            : AlwaysFalseTrueCond-ML
+  Description    : Condition '[RTL_CONDITION]' can never be '[NodeType]' [Hierarchy: '[HIERARCHY]']
+  Violation      : Lint:5704
+  Goal           : lint_rtl
+  Module         : input_queue_per_port
+  FileName       : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber     : 800
+  Statement      :         if (( TOPOLOGY == "RING" || TOPOLOGY == "LINE" || TOPOLOGY == "MESH" || TOPOLOGY == "TORUS") && (T3>1) && (CAST_TYPE== "UNICAST")) begin : multi_local
+  RTL_CONDITION  : (T3 > 1)
+  NodeType       : true
+  HIERARCHY      : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[3].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[0].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag            : AlwaysFalseTrueCond-ML
+  Description    : Condition '[RTL_CONDITION]' can never be '[NodeType]' [Hierarchy: '[HIERARCHY]']
+  Violation      : Lint:5613
+  Goal           : lint_rtl
+  Module         : inout_ports
+  FileName       : ./../../rtl/src_noc/./inout_ports.sv
+  LineNumber     : 283
+  Statement      :     if( SSA_EN == 1 ) begin : ssa
+  RTL_CONDITION  : (SSA_EN==1)
+  NodeType       : true
+  HIERARCHY      : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[3].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports
+  -----------------------------------------------------------------------------
+  Tag            : AlwaysFalseTrueCond-ML
+  Description    : Condition '[RTL_CONDITION]' can never be '[NodeType]' [Hierarchy: '[HIERARCHY]']
+  Violation      : Lint:3807
+  Goal           : lint_rtl
+  Module         : input_queue_per_port
+  FileName       : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber     : 947
+  Statement      :     if(CAST_TYPE== "UNICAST") begin : unicast
+  RTL_CONDITION  : (CAST_TYPE=="UNICAST")
+  NodeType       : false
+  HIERARCHY      : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[0].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag            : AlwaysFalseTrueCond-ML
+  Description    : Condition '[RTL_CONDITION]' can never be '[NodeType]' [Hierarchy: '[HIERARCHY]']
+  Violation      : Lint:3874
+  Goal           : lint_rtl
+  Module         : destp_generator
+  FileName       : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber     : 1166
+  Statement      :     end else if(TOPOLOGY == "RING" || TOPOLOGY == "LINE" || TOPOLOGY == "MESH"|| TOPOLOGY == "TORUS") begin : mesh
+  RTL_CONDITION  : (TOPOLOGY=="RING")
+  NodeType       : true
+  HIERARCHY      : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[0].the_input_queue_per_port @input_queue_per_port:\V_[0].decoder @destp_generator
+  -----------------------------------------------------------------------------
+  Tag            : AlwaysFalseTrueCond-ML
+  Description    : Condition '[RTL_CONDITION]' can never be '[NodeType]' [Hierarchy: '[HIERARCHY]']
+  Violation      : Lint:3575
+  Goal           : lint_rtl
+  Module         : noc_top
+  FileName       : ./../../rtl/src_noc/./topology_localparam.v
+  LineNumber     : 296
+  Statement      :         MCASTw =
+  RTL_CONDITION  : ((CAST_TYPE=="MULTICAST_PARTIAL")&&(EAw < MCAST_PRTLw))
+  NodeType       : true
+  HIERARCHY      : :noc_top
+  -----------------------------------------------------------------------------
+  Tag            : AlwaysFalseTrueCond-ML
+  Description    : Condition '[RTL_CONDITION]' can never be '[NodeType]' [Hierarchy: '[HIERARCHY]']
+  Violation      : Lint:3848
+  Goal           : lint_rtl
+  Module         : fifo_ram
+  FileName       : ./../../rtl/src_noc/./flit_buffer.sv
+  LineNumber     : 459
+  Statement      :     if(SSA_EN == 1) begin :predict
+  RTL_CONDITION  : (SSA_EN==1)
+  NodeType       : true
+  HIERARCHY      : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[0].the_input_queue_per_port @input_queue_per_port:the_flit_buffer@flit_buffer:\pow2.the_queue @fifo_ram
+  -----------------------------------------------------------------------------
+  Tag            : AlwaysFalseTrueCond-ML
+  Description    : Condition '[RTL_CONDITION]' can never be '[NodeType]' [Hierarchy: '[HIERARCHY]']
+  Violation      : Lint:5000
+  Goal           : lint_rtl
+  Module         : input_queue_per_port
+  FileName       : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber     : 643
+  Statement      :         if(C>1)begin :cb1
+  RTL_CONDITION  : (C > 1)
+  NodeType       : true
+  HIERARCHY      : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[1].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[0].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag            : AlwaysFalseTrueCond-ML
+  Description    : Condition '[RTL_CONDITION]' can never be '[NodeType]' [Hierarchy: '[HIERARCHY]']
+  Violation      : Lint:5528
+  Goal           : lint_rtl
+  Module         : input_queue_per_port
+  FileName       : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber     : 406
+  Statement      :     if (( TOPOLOGY == "RING" || TOPOLOGY == "LINE" || TOPOLOGY == "MESH" || TOPOLOGY == "TORUS") && (T3>1) && CAST_TYPE== "UNICAST") begin : multi_local
+  RTL_CONDITION  : (TOPOLOGY=="LINE")
+  NodeType       : false
+  HIERARCHY      : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[2].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[2].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag            : AlwaysFalseTrueCond-ML
+  Description    : Condition '[RTL_CONDITION]' can never be '[NodeType]' [Hierarchy: '[HIERARCHY]']
+  Violation      : Lint:5218
+  Goal           : lint_rtl
+  Module         : input_queue_per_port
+  FileName       : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber     : 929
+  Statement      :     if(PORT_IVC != V) begin : hetero
+  RTL_CONDITION  : (PORT_IVC!=V)
+  NodeType       : true
+  HIERARCHY      : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[1].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[2].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag            : AlwaysFalseTrueCond-ML
+  Description    : Condition '[RTL_CONDITION]' can never be '[NodeType]' [Hierarchy: '[HIERARCHY]']
+  Violation      : Lint:5677
+  Goal           : lint_rtl
+  Module         : input_queue_per_port
+  FileName       : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber     : 406
+  Statement      :     if (( TOPOLOGY == "RING" || TOPOLOGY == "LINE" || TOPOLOGY == "MESH" || TOPOLOGY == "TORUS") && (T3>1) && CAST_TYPE== "UNICAST") begin : multi_local
+  RTL_CONDITION  : (TOPOLOGY=="MESH")
+  NodeType       : true
+  HIERARCHY      : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[3].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[0].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag            : AlwaysFalseTrueCond-ML
+  Description    : Condition '[RTL_CONDITION]' can never be '[NodeType]' [Hierarchy: '[HIERARCHY]']
+  Violation      : Lint:4799
+  Goal           : lint_rtl
+  Module         : conventional_routing
+  FileName       : ./../../rtl/src_noc/./routing.v
+  LineNumber     : 69
+  Statement      :     if(TOPOLOGY == "MESH" || TOPOLOGY == "FMESH" || TOPOLOGY == "TORUS"  || TOPOLOGY ==  "RING" || TOPOLOGY ==  "LINE") begin :mesh_torus
+  RTL_CONDITION  : (TOPOLOGY=="MESH")
+  NodeType       : true
+  HIERARCHY      : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:\smart.Port_[1].smart_en.smart_allocator @smart_allocator_per_iport:routing@conventional_routing
+  -----------------------------------------------------------------------------
+  Tag            : AlwaysFalseTrueCond-ML
+  Description    : Condition '[RTL_CONDITION]' can never be '[NodeType]' [Hierarchy: '[HIERARCHY]']
+  Violation      : Lint:5867
+  Goal           : lint_rtl
+  Module         : input_queue_per_port
+  FileName       : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber     : 242
+  Statement      :         IGNORE_SAME_LOC_RD_WR_WARNING = ((SSA_EN==1) || (SMART_EN==1))? "YES" : "NO";
+  RTL_CONDITION  : ((SSA_EN==1)||(SMART_EN==1))
+  NodeType       : false
+  HIERARCHY      : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[3].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[2].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag            : AlwaysFalseTrueCond-ML
+  Description    : Condition '[RTL_CONDITION]' can never be '[NodeType]' [Hierarchy: '[HIERARCHY]']
+  Violation      : Lint:4912
+  Goal           : lint_rtl
+  Module         : router_two_stage
+  FileName       : ./../../rtl/src_noc/./router_two_stage.sv
+  LineNumber     : 164
+  Statement      :         end else if (IS_MULTI_MESH) begin
+  RTL_CONDITION  : IS_MULTI_MESH
+  NodeType       : true
+  HIERARCHY      : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[1].the_router @router_top:router_ref@router_two_stage
+  -----------------------------------------------------------------------------
+  Tag            : AlwaysFalseTrueCond-ML
+  Description    : Condition '[RTL_CONDITION]' can never be '[NodeType]' [Hierarchy: '[HIERARCHY]']
+  Violation      : Lint:3929
+  Goal           : lint_rtl
+  Module         : mesh_tori_endp_addr_decode
+  FileName       : ./../../rtl/src_noc/./mesh_torus.sv
+  LineNumber     : 955
+  Statement      :         EYw = (TOPOLOGY=="RING" || TOPOLOGY == "LINE")? 1 : log2(NY),
+  RTL_CONDITION  : (TOPOLOGY=="RING")
+  NodeType       : true
+  HIERARCHY      : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[0].the_input_queue_per_port @input_queue_per_port:\unicast.lk_routing @look_ahead_routing:\mesh_torus.mesh.end_addr_decode @mesh_tori_endp_addr_decode
+  -----------------------------------------------------------------------------
+  Tag            : AlwaysFalseTrueCond-ML
+  Description    : Condition '[RTL_CONDITION]' can never be '[NodeType]' [Hierarchy: '[HIERARCHY]']
+  Violation      : Lint:5096
+  Goal           : lint_rtl
+  Module         : input_queue_per_port
+  FileName       : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber     : 491
+  Statement      :         if( P==MAX_P ) begin 
+  RTL_CONDITION  : (P==MAX_P)
+  NodeType       : false
+  HIERARCHY      : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[1].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[1].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag            : AlwaysFalseTrueCond-ML
+  Description    : Condition '[RTL_CONDITION]' can never be '[NodeType]' [Hierarchy: '[HIERARCHY]']
+  Violation      : Lint:5685
+  Goal           : lint_rtl
+  Module         : input_queue_per_port
+  FileName       : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber     : 441
+  Statement      :     if(TOPOLOGY=="FATTREE" && ROUTE_NAME == "NCA_STRAIGHT_UP") begin : fat
+  RTL_CONDITION  : (TOPOLOGY=="FATTREE")
+  NodeType       : true
+  HIERARCHY      : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[3].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[0].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag            : AlwaysFalseTrueCond-ML
+  Description    : Condition '[RTL_CONDITION]' can never be '[NodeType]' [Hierarchy: '[HIERARCHY]']
+  Violation      : Lint:3771
+  Goal           : lint_rtl
+  Module         : input_queue_per_port
+  FileName       : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber     : 406
+  Statement      :     if (( TOPOLOGY == "RING" || TOPOLOGY == "LINE" || TOPOLOGY == "MESH" || TOPOLOGY == "TORUS") && (T3>1) && CAST_TYPE== "UNICAST") begin : multi_local
+  RTL_CONDITION  : (TOPOLOGY=="MESH")
+  NodeType       : true
+  HIERARCHY      : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[0].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag            : AlwaysFalseTrueCond-ML
+  Description    : Condition '[RTL_CONDITION]' can never be '[NodeType]' [Hierarchy: '[HIERARCHY]']
+  Violation      : Lint:5416
+  Goal           : lint_rtl
+  Module         : input_queue_per_port
+  FileName       : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber     : 240
+  Statement      :         NON_ATOM_PCKS =  (PORT_B>MIN_PCK_SIZE)?  (PORT_B/MIN_PCK_SIZE)+ OFFSET : 1,
+  RTL_CONDITION  : (PORT_B > MIN_PCK_SIZE)
+  NodeType       : false
+  HIERARCHY      : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[2].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[1].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag            : AlwaysFalseTrueCond-ML
+  Description    : Condition '[RTL_CONDITION]' can never be '[NodeType]' [Hierarchy: '[HIERARCHY]']
+  Violation      : Lint:5805
+  Goal           : lint_rtl
+  Module         : input_queue_per_port
+  FileName       : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber     : 821
+  Statement      :         end else if ( TOPOLOGY == "FMESH" && CAST_TYPE== "UNICAST") begin : fmesh
+  RTL_CONDITION  : ((TOPOLOGY=="FMESH")&&(CAST_TYPE=="UNICAST"))
+  NodeType       : true
+  HIERARCHY      : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[3].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[1].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag            : AlwaysFalseTrueCond-ML
+  Description    : Condition '[RTL_CONDITION]' can never be '[NodeType]' [Hierarchy: '[HIERARCHY]']
+  Violation      : Lint:4976
+  Goal           : lint_rtl
+  Module         : input_queue_per_port
+  FileName       : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber     : 247
+  Statement      :         PLw = (IS_FMESH) ? Pw : ELw,
+  RTL_CONDITION  : IS_FMESH
+  NodeType       : true
+  HIERARCHY      : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[1].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[0].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag            : AlwaysFalseTrueCond-ML
+  Description    : Condition '[RTL_CONDITION]' can never be '[NodeType]' [Hierarchy: '[HIERARCHY]']
+  Violation      : Lint:5696
+  Goal           : lint_rtl
+  Module         : input_queue_per_port
+  FileName       : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber     : 800
+  Statement      :         if (( TOPOLOGY == "RING" || TOPOLOGY == "LINE" || TOPOLOGY == "MESH" || TOPOLOGY == "TORUS") && (T3>1) && (CAST_TYPE== "UNICAST")) begin : multi_local
+  RTL_CONDITION  : (((((TOPOLOGY=="RING")||(TOPOLOGY=="LINE"))||(TOPOLOGY=="MESH"))||(TOPOLOGY=="TORUS"))&&(T3 > 1))
+  NodeType       : true
+  HIERARCHY      : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[3].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[0].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag            : AlwaysFalseTrueCond-ML
+  Description    : Condition '[RTL_CONDITION]' can never be '[NodeType]' [Hierarchy: '[HIERARCHY]']
+  Violation      : Lint:3601
+  Goal           : lint_rtl
+  Module         : noc_top
+  FileName       : ./../../rtl/src_noc/./pronoc_pkg.sv
+  LineNumber     : 55
+  Statement      :         OVC_ALLOC_MODE= ((V==1 || B <= 4) ) ?   1'b1 : 1'b0;
+  RTL_CONDITION  : ((V==1)||(B<=4))
+  NodeType       : false
+  HIERARCHY      : :noc_top
+  -----------------------------------------------------------------------------
+  Tag            : AlwaysFalseTrueCond-ML
+  Description    : Condition '[RTL_CONDITION]' can never be '[NodeType]' [Hierarchy: '[HIERARCHY]']
+  Violation      : Lint:3591
+  Goal           : lint_rtl
+  Module         : noc_top
+  FileName       : ./../../rtl/src_noc/./pronoc_pkg.sv
+  LineNumber     : 32
+  Statement      :     localparam CONGw= 
+  RTL_CONDITION  : (CONGESTION_INDEX==5)
+  NodeType       : true
+  HIERARCHY      : :noc_top
+  -----------------------------------------------------------------------------
+  Tag            : AlwaysFalseTrueCond-ML
+  Description    : Condition '[RTL_CONDITION]' can never be '[NodeType]' [Hierarchy: '[HIERARCHY]']
+  Violation      : Lint:5804
+  Goal           : lint_rtl
+  Module         : input_queue_per_port
+  FileName       : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber     : 800
+  Statement      :         if (( TOPOLOGY == "RING" || TOPOLOGY == "LINE" || TOPOLOGY == "MESH" || TOPOLOGY == "TORUS") && (T3>1) && (CAST_TYPE== "UNICAST")) begin : multi_local
+  RTL_CONDITION  : (CAST_TYPE=="UNICAST")
+  NodeType       : false
+  HIERARCHY      : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[3].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[1].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag            : AlwaysFalseTrueCond-ML
+  Description    : Condition '[RTL_CONDITION]' can never be '[NodeType]' [Hierarchy: '[HIERARCHY]']
+  Violation      : Lint:3868
+  Goal           : lint_rtl
+  Module         : destp_generator
+  FileName       : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber     : 1123
+  Statement      :     if(CAST_TYPE!= "UNICAST") begin : muticast
+  RTL_CONDITION  : (CAST_TYPE!="UNICAST")
+  NodeType       : true
+  HIERARCHY      : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[0].the_input_queue_per_port @input_queue_per_port:\V_[0].decoder @destp_generator
+  -----------------------------------------------------------------------------
+  Tag            : AlwaysFalseTrueCond-ML
+  Description    : Condition '[RTL_CONDITION]' can never be '[NodeType]' [Hierarchy: '[HIERARCHY]']
+  Violation      : Lint:5363
+  Goal           : lint_rtl
+  Module         : input_queue_per_port
+  FileName       : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber     : 846
+  Statement      :         if(SWA_ARBITER_TYPE != "RRA")begin  : wrra
+  RTL_CONDITION  : (SWA_ARBITER_TYPE!="RRA")
+  NodeType       : true
+  HIERARCHY      : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[2].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[0].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag            : AlwaysFalseTrueCond-ML
+  Description    : Condition '[RTL_CONDITION]' can never be '[NodeType]' [Hierarchy: '[HIERARCHY]']
+  Violation      : Lint:5679
+  Goal           : lint_rtl
+  Module         : input_queue_per_port
+  FileName       : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber     : 406
+  Statement      :     if (( TOPOLOGY == "RING" || TOPOLOGY == "LINE" || TOPOLOGY == "MESH" || TOPOLOGY == "TORUS") && (T3>1) && CAST_TYPE== "UNICAST") begin : multi_local
+  RTL_CONDITION  : (T3 > 1)
+  NodeType       : true
+  HIERARCHY      : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[3].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[0].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag            : AlwaysFalseTrueCond-ML
+  Description    : Condition '[RTL_CONDITION]' can never be '[NodeType]' [Hierarchy: '[HIERARCHY]']
+  Violation      : Lint:3534
+  Goal           : lint_rtl
+  Module         : noc_top
+  FileName       : ./../../rtl/src_noc/./topology_localparam.v
+  LineNumber     : 121
+  Statement      :         if(IS_MESH || IS_FMESH || IS_TORUS || IS_RING || IS_LINE)begin 
+  RTL_CONDITION  : (IS_MESH||IS_FMESH)
+  NodeType       : true
+  HIERARCHY      : :noc_top
+  -----------------------------------------------------------------------------
+  Tag            : AlwaysFalseTrueCond-ML
+  Description    : Condition '[RTL_CONDITION]' can never be '[NodeType]' [Hierarchy: '[HIERARCHY]']
+  Violation      : Lint:5012
+  Goal           : lint_rtl
+  Module         : input_queue_per_port
+  FileName       : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber     : 800
+  Statement      :         if (( TOPOLOGY == "RING" || TOPOLOGY == "LINE" || TOPOLOGY == "MESH" || TOPOLOGY == "TORUS") && (T3>1) && (CAST_TYPE== "UNICAST")) begin : multi_local
+  RTL_CONDITION  : (T3 > 1)
+  NodeType       : true
+  HIERARCHY      : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[1].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[0].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag            : AlwaysFalseTrueCond-ML
+  Description    : Condition '[RTL_CONDITION]' can never be '[NodeType]' [Hierarchy: '[HIERARCHY]']
+  Violation      : Lint:5119
+  Goal           : lint_rtl
+  Module         : input_queue_per_port
+  FileName       : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber     : 929
+  Statement      :     if(PORT_IVC != V) begin : hetero
+  RTL_CONDITION  : (PORT_IVC!=V)
+  NodeType       : true
+  HIERARCHY      : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[1].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[1].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag            : AlwaysFalseTrueCond-ML
+  Description    : Condition '[RTL_CONDITION]' can never be '[NodeType]' [Hierarchy: '[HIERARCHY]']
+  Violation      : Lint:5428
+  Goal           : lint_rtl
+  Module         : input_queue_per_port
+  FileName       : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber     : 406
+  Statement      :     if (( TOPOLOGY == "RING" || TOPOLOGY == "LINE" || TOPOLOGY == "MESH" || TOPOLOGY == "TORUS") && (T3>1) && CAST_TYPE== "UNICAST") begin : multi_local
+  RTL_CONDITION  : (TOPOLOGY=="RING")
+  NodeType       : true
+  HIERARCHY      : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[2].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[1].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag            : AlwaysFalseTrueCond-ML
+  Description    : Condition '[RTL_CONDITION]' can never be '[NodeType]' [Hierarchy: '[HIERARCHY]']
+  Violation      : Lint:3565
+  Goal           : lint_rtl
+  Module         : noc_top
+  FileName       : ./../../rtl/src_noc/./topology_localparam.v
+  LineNumber     : 275
+  Statement      :         NE =
+  RTL_CONDITION  : (IS_RING||IS_LINE)
+  NodeType       : false
+  HIERARCHY      : :noc_top
+  -----------------------------------------------------------------------------
+  Tag            : AlwaysFalseTrueCond-ML
+  Description    : Condition '[RTL_CONDITION]' can never be '[NodeType]' [Hierarchy: '[HIERARCHY]']
+  Violation      : Lint:4292
+  Goal           : lint_rtl
+  Module         : mesh_torus_destp_generator
+  FileName       : ./../../rtl/src_noc/./mesh_torus.sv
+  LineNumber     : 1132
+  Statement      :     localparam P_1 = (SELF_LOOP_EN )?  P : P-1;
+  RTL_CONDITION  : SELF_LOOP_EN
+  NodeType       : false
+  HIERARCHY      : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[2].the_input_queue_per_port @input_queue_per_port:\V_[0].decoder @destp_generator:\mesh.destp_generator @mesh_torus_destp_generator
+  -----------------------------------------------------------------------------
+  Tag            : AlwaysFalseTrueCond-ML
+  Description    : Condition '[RTL_CONDITION]' can never be '[NodeType]' [Hierarchy: '[HIERARCHY]']
+  Violation      : Lint:5427
+  Goal           : lint_rtl
+  Module         : input_queue_per_port
+  FileName       : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber     : 406
+  Statement      :     if (( TOPOLOGY == "RING" || TOPOLOGY == "LINE" || TOPOLOGY == "MESH" || TOPOLOGY == "TORUS") && (T3>1) && CAST_TYPE== "UNICAST") begin : multi_local
+  RTL_CONDITION  : ((TOPOLOGY=="RING")||(TOPOLOGY=="LINE"))
+  NodeType       : false
+  HIERARCHY      : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[2].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[1].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag            : AlwaysFalseTrueCond-ML
+  Description    : Condition '[RTL_CONDITION]' can never be '[NodeType]' [Hierarchy: '[HIERARCHY]']
+  Violation      : Lint:3670
+  Goal           : lint_rtl
+  Module         : router_top
+  FileName       : ./../../rtl/src_noc/./router_top.sv
+  LineNumber     : 161
+  Statement      :             if(SS_PORT == DISABLED) begin: smart_dis
+  RTL_CONDITION  : (SS_PORT==DISABLED)
+  NodeType       : false
+  HIERARCHY      : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top
+  -----------------------------------------------------------------------------
+  Tag            : AlwaysFalseTrueCond-ML
+  Description    : Condition '[RTL_CONDITION]' can never be '[NodeType]' [Hierarchy: '[HIERARCHY]']
+  Violation      : Lint:4171
+  Goal           : lint_rtl
+  Module         : mesh_torus_deterministic_look_ahead_routing
+  FileName       : ./../../rtl/src_noc/./mesh_torus_routting.v
+  LineNumber     : 132
+  Statement      :         Yw = (TOPOLOGY=="RING" || TOPOLOGY == "LINE") ? 1 : log2(NY);    // number of node in y axis
+  RTL_CONDITION  : ((TOPOLOGY=="RING")||(TOPOLOGY=="LINE"))
+  NodeType       : false
+  HIERARCHY      : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[1].the_input_queue_per_port @input_queue_per_port:\unicast.lk_routing @look_ahead_routing:\mesh_torus.look_ahead_route @mesh_torus_look_ahead_routing:\dtrmst.deterministic_look_ahead @mesh_torus_deterministic_look_ahead_routing
+  -----------------------------------------------------------------------------
+  Tag            : AlwaysFalseTrueCond-ML
+  Description    : Condition '[RTL_CONDITION]' can never be '[NodeType]' [Hierarchy: '[HIERARCHY]']
+  Violation      : Lint:3871
+  Goal           : lint_rtl
+  Module         : destp_generator
+  FileName       : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber     : 1166
+  Statement      :     end else if(TOPOLOGY == "RING" || TOPOLOGY == "LINE" || TOPOLOGY == "MESH"|| TOPOLOGY == "TORUS") begin : mesh
+  RTL_CONDITION  : ((((TOPOLOGY=="RING")||(TOPOLOGY=="LINE"))||(TOPOLOGY=="MESH"))||(TOPOLOGY=="TORUS"))
+  NodeType       : false
+  HIERARCHY      : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[0].the_input_queue_per_port @input_queue_per_port:\V_[0].decoder @destp_generator
+  -----------------------------------------------------------------------------
+  Tag            : AlwaysFalseTrueCond-ML
+  Description    : Condition '[RTL_CONDITION]' can never be '[NodeType]' [Hierarchy: '[HIERARCHY]']
+  Violation      : Lint:3767
+  Goal           : lint_rtl
+  Module         : input_queue_per_port
+  FileName       : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber     : 406
+  Statement      :     if (( TOPOLOGY == "RING" || TOPOLOGY == "LINE" || TOPOLOGY == "MESH" || TOPOLOGY == "TORUS") && (T3>1) && CAST_TYPE== "UNICAST") begin : multi_local
+  RTL_CONDITION  : (((TOPOLOGY=="RING")||(TOPOLOGY=="LINE"))||(TOPOLOGY=="MESH"))
+  NodeType       : false
+  HIERARCHY      : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[0].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag            : AlwaysFalseTrueCond-ML
+  Description    : Condition '[RTL_CONDITION]' can never be '[NodeType]' [Hierarchy: '[HIERARCHY]']
+  Violation      : Lint:5700
+  Goal           : lint_rtl
+  Module         : input_queue_per_port
+  FileName       : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber     : 800
+  Statement      :         if (( TOPOLOGY == "RING" || TOPOLOGY == "LINE" || TOPOLOGY == "MESH" || TOPOLOGY == "TORUS") && (T3>1) && (CAST_TYPE== "UNICAST")) begin : multi_local
+  RTL_CONDITION  : (TOPOLOGY=="RING")
+  NodeType       : true
+  HIERARCHY      : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[3].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[0].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag            : AlwaysFalseTrueCond-ML
+  Description    : Condition '[RTL_CONDITION]' can never be '[NodeType]' [Hierarchy: '[HIERARCHY]']
+  Violation      : Lint:4073
+  Goal           : lint_rtl
+  Module         : input_queue_per_port
+  FileName       : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber     : 800
+  Statement      :         if (( TOPOLOGY == "RING" || TOPOLOGY == "LINE" || TOPOLOGY == "MESH" || TOPOLOGY == "TORUS") && (T3>1) && (CAST_TYPE== "UNICAST")) begin : multi_local
+  RTL_CONDITION  : (((TOPOLOGY=="RING")||(TOPOLOGY=="LINE"))||(TOPOLOGY=="MESH"))
+  NodeType       : false
+  HIERARCHY      : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[1].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag            : AlwaysFalseTrueCond-ML
+  Description    : Condition '[RTL_CONDITION]' can never be '[NodeType]' [Hierarchy: '[HIERARCHY]']
+  Violation      : Lint:3572
+  Goal           : lint_rtl
+  Module         : noc_top
+  FileName       : ./../../rtl/src_noc/./topology_localparam.v
+  LineNumber     : 296
+  Statement      :         MCASTw =
+  RTL_CONDITION  : ((CAST_TYPE=="MULTICAST_PARTIAL")&&(EAw>=MCAST_PRTLw))
+  NodeType       : true
+  HIERARCHY      : :noc_top
+  -----------------------------------------------------------------------------
+  Tag            : AlwaysFalseTrueCond-ML
+  Description    : Condition '[RTL_CONDITION]' can never be '[NodeType]' [Hierarchy: '[HIERARCHY]']
+  Violation      : Lint:4112
+  Goal           : lint_rtl
+  Module         : destp_generator
+  FileName       : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber     : 1123
+  Statement      :     if(CAST_TYPE!= "UNICAST") begin : muticast
+  RTL_CONDITION  : (CAST_TYPE!="UNICAST")
+  NodeType       : true
+  HIERARCHY      : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[1].the_input_queue_per_port @input_queue_per_port:\V_[0].decoder @destp_generator
+  -----------------------------------------------------------------------------
+  Tag            : AlwaysFalseTrueCond-ML
+  Description    : Condition '[RTL_CONDITION]' can never be '[NodeType]' [Hierarchy: '[HIERARCHY]']
+  Violation      : Lint:3593
+  Goal           : lint_rtl
+  Module         : noc_top
+  FileName       : ./../../rtl/src_noc/./pronoc_pkg.sv
+  LineNumber     : 32
+  Statement      :     localparam CONGw= 
+  RTL_CONDITION  : (CONGESTION_INDEX==9)
+  NodeType       : true
+  HIERARCHY      : :noc_top
+  -----------------------------------------------------------------------------
+  Tag            : AlwaysFalseTrueCond-ML
+  Description    : Condition '[RTL_CONDITION]' can never be '[NodeType]' [Hierarchy: '[HIERARCHY]']
+  Violation      : Lint:5466
+  Goal           : lint_rtl
+  Module         : input_queue_per_port
+  FileName       : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber     : 947
+  Statement      :     if(CAST_TYPE== "UNICAST") begin : unicast
+  RTL_CONDITION  : (CAST_TYPE=="UNICAST")
+  NodeType       : false
+  HIERARCHY      : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[2].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[1].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag            : AlwaysFalseTrueCond-ML
+  Description    : Condition '[RTL_CONDITION]' can never be '[NodeType]' [Hierarchy: '[HIERARCHY]']
+  Violation      : Lint:4998
+  Goal           : lint_rtl
+  Module         : input_queue_per_port
+  FileName       : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber     : 508
+  Statement      :         if(IS_MULTI_MESH==0) begin :ovc_
+  RTL_CONDITION  : (IS_MULTI_MESH==0)
+  NodeType       : false
+  HIERARCHY      : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[1].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[0].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag            : AlwaysFalseTrueCond-ML
+  Description    : Condition '[RTL_CONDITION]' can never be '[NodeType]' [Hierarchy: '[HIERARCHY]']
+  Violation      : Lint:5186
+  Goal           : lint_rtl
+  Module         : input_queue_per_port
+  FileName       : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber     : 406
+  Statement      :     if (( TOPOLOGY == "RING" || TOPOLOGY == "LINE" || TOPOLOGY == "MESH" || TOPOLOGY == "TORUS") && (T3>1) && CAST_TYPE== "UNICAST") begin : multi_local
+  RTL_CONDITION  : (CAST_TYPE=="UNICAST")
+  NodeType       : false
+  HIERARCHY      : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[1].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[2].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag            : AlwaysFalseTrueCond-ML
+  Description    : Condition '[RTL_CONDITION]' can never be '[NodeType]' [Hierarchy: '[HIERARCHY]']
+  Violation      : Lint:5767
+  Goal           : lint_rtl
+  Module         : input_queue_per_port
+  FileName       : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber     : 247
+  Statement      :         PLw = (IS_FMESH) ? Pw : ELw,
+  RTL_CONDITION  : IS_FMESH
+  NodeType       : true
+  HIERARCHY      : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[3].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[1].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag            : AlwaysFalseTrueCond-ML
+  Description    : Condition '[RTL_CONDITION]' can never be '[NodeType]' [Hierarchy: '[HIERARCHY]']
+  Violation      : Lint:5778
+  Goal           : lint_rtl
+  Module         : input_queue_per_port
+  FileName       : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber     : 406
+  Statement      :     if (( TOPOLOGY == "RING" || TOPOLOGY == "LINE" || TOPOLOGY == "MESH" || TOPOLOGY == "TORUS") && (T3>1) && CAST_TYPE== "UNICAST") begin : multi_local
+  RTL_CONDITION  : (T3 > 1)
+  NodeType       : true
+  HIERARCHY      : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[3].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[1].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag            : AlwaysFalseTrueCond-ML
+  Description    : Condition '[RTL_CONDITION]' can never be '[NodeType]' [Hierarchy: '[HIERARCHY]']
+  Violation      : Lint:5333
+  Goal           : lint_rtl
+  Module         : input_queue_per_port
+  FileName       : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber     : 406
+  Statement      :     if (( TOPOLOGY == "RING" || TOPOLOGY == "LINE" || TOPOLOGY == "MESH" || TOPOLOGY == "TORUS") && (T3>1) && CAST_TYPE== "UNICAST") begin : multi_local
+  RTL_CONDITION  : (T3 > 1)
+  NodeType       : true
+  HIERARCHY      : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[2].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[0].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag            : AlwaysFalseTrueCond-ML
+  Description    : Condition '[RTL_CONDITION]' can never be '[NodeType]' [Hierarchy: '[HIERARCHY]']
+  Violation      : Lint:5079
+  Goal           : lint_rtl
+  Module         : input_queue_per_port
+  FileName       : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber     : 406
+  Statement      :     if (( TOPOLOGY == "RING" || TOPOLOGY == "LINE" || TOPOLOGY == "MESH" || TOPOLOGY == "TORUS") && (T3>1) && CAST_TYPE== "UNICAST") begin : multi_local
+  RTL_CONDITION  : ((((TOPOLOGY=="RING")||(TOPOLOGY=="LINE"))||(TOPOLOGY=="MESH"))||(TOPOLOGY=="TORUS"))
+  NodeType       : false
+  HIERARCHY      : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[1].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[1].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag            : AlwaysFalseTrueCond-ML
+  Description    : Condition '[RTL_CONDITION]' can never be '[NodeType]' [Hierarchy: '[HIERARCHY]']
+  Violation      : Lint:4055
+  Goal           : lint_rtl
+  Module         : input_queue_per_port
+  FileName       : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber     : 406
+  Statement      :     if (( TOPOLOGY == "RING" || TOPOLOGY == "LINE" || TOPOLOGY == "MESH" || TOPOLOGY == "TORUS") && (T3>1) && CAST_TYPE== "UNICAST") begin : multi_local
+  RTL_CONDITION  : (CAST_TYPE=="UNICAST")
+  NodeType       : false
+  HIERARCHY      : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[1].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag            : AlwaysFalseTrueCond-ML
+  Description    : Condition '[RTL_CONDITION]' can never be '[NodeType]' [Hierarchy: '[HIERARCHY]']
+  Violation      : Lint:5451
+  Goal           : lint_rtl
+  Module         : input_queue_per_port
+  FileName       : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber     : 800
+  Statement      :         if (( TOPOLOGY == "RING" || TOPOLOGY == "LINE" || TOPOLOGY == "MESH" || TOPOLOGY == "TORUS") && (T3>1) && (CAST_TYPE== "UNICAST")) begin : multi_local
+  RTL_CONDITION  : (((TOPOLOGY=="RING")||(TOPOLOGY=="LINE"))||(TOPOLOGY=="MESH"))
+  NodeType       : false
+  HIERARCHY      : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[2].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[1].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag            : AlwaysFalseTrueCond-ML
+  Description    : Condition '[RTL_CONDITION]' can never be '[NodeType]' [Hierarchy: '[HIERARCHY]']
+  Violation      : Lint:5202
+  Goal           : lint_rtl
+  Module         : input_queue_per_port
+  FileName       : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber     : 800
+  Statement      :         if (( TOPOLOGY == "RING" || TOPOLOGY == "LINE" || TOPOLOGY == "MESH" || TOPOLOGY == "TORUS") && (T3>1) && (CAST_TYPE== "UNICAST")) begin : multi_local
+  RTL_CONDITION  : (((((TOPOLOGY=="RING")||(TOPOLOGY=="LINE"))||(TOPOLOGY=="MESH"))||(TOPOLOGY=="TORUS"))&&(T3 > 1))
+  NodeType       : true
+  HIERARCHY      : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[1].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[2].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag            : AlwaysFalseTrueCond-ML
+  Description    : Condition '[RTL_CONDITION]' can never be '[NodeType]' [Hierarchy: '[HIERARCHY]']
+  Violation      : Lint:4169
+  Goal           : lint_rtl
+  Module         : mesh_torus_look_ahead_routing
+  FileName       : ./../../rtl/src_noc/./mesh_torus_routting.v
+  LineNumber     : 43
+  Statement      :         Yw = (TOPOLOGY=="RING" || TOPOLOGY == "LINE") ? 1 : log2(NY);    // number of node in y axis
+  RTL_CONDITION  : (TOPOLOGY=="LINE")
+  NodeType       : false
+  HIERARCHY      : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[1].the_input_queue_per_port @input_queue_per_port:\unicast.lk_routing @look_ahead_routing:\mesh_torus.look_ahead_route @mesh_torus_look_ahead_routing
+  -----------------------------------------------------------------------------
+  Tag            : AlwaysFalseTrueCond-ML
+  Description    : Condition '[RTL_CONDITION]' can never be '[NodeType]' [Hierarchy: '[HIERARCHY]']
+  Violation      : Lint:3865
+  Goal           : lint_rtl
+  Module         : fwft_fifo
+  FileName       : ./../../rtl/src_noc/./flit_buffer.sv
+  LineNumber     : 586
+  Statement      :     if(MAX_DEPTH>2) begin :mwb2
+  RTL_CONDITION  : (MAX_DEPTH > 2)
+  NodeType       : false
+  HIERARCHY      : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[0].the_input_queue_per_port @input_queue_per_port:\V_[0].smart_.dest_e_addr_fifo @fwft_fifo
+  -----------------------------------------------------------------------------
+  Tag            : AlwaysFalseTrueCond-ML
+  Description    : Condition '[RTL_CONDITION]' can never be '[NodeType]' [Hierarchy: '[HIERARCHY]']
+  Violation      : Lint:5791
+  Goal           : lint_rtl
+  Module         : input_queue_per_port
+  FileName       : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber     : 643
+  Statement      :         if(C>1)begin :cb1
+  RTL_CONDITION  : (C > 1)
+  NodeType       : true
+  HIERARCHY      : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[3].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[1].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag            : AlwaysFalseTrueCond-ML
+  Description    : Condition '[RTL_CONDITION]' can never be '[NodeType]' [Hierarchy: '[HIERARCHY]']
+  Violation      : Lint:4266
+  Goal           : lint_rtl
+  Module         : input_queue_per_port
+  FileName       : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber     : 800
+  Statement      :         if (( TOPOLOGY == "RING" || TOPOLOGY == "LINE" || TOPOLOGY == "MESH" || TOPOLOGY == "TORUS") && (T3>1) && (CAST_TYPE== "UNICAST")) begin : multi_local
+  RTL_CONDITION  : (TOPOLOGY=="MESH")
+  NodeType       : true
+  HIERARCHY      : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[2].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag            : AlwaysFalseTrueCond-ML
+  Description    : Condition '[RTL_CONDITION]' can never be '[NodeType]' [Hierarchy: '[HIERARCHY]']
+  Violation      : Lint:4170
+  Goal           : lint_rtl
+  Module         : mesh_torus_look_ahead_routing
+  FileName       : ./../../rtl/src_noc/./mesh_torus_routting.v
+  LineNumber     : 59
+  Statement      :     if(ROUTE_TYPE=="DETERMINISTIC") begin :dtrmst
+  RTL_CONDITION  : (ROUTE_TYPE=="DETERMINISTIC")
+  NodeType       : false
+  HIERARCHY      : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[1].the_input_queue_per_port @input_queue_per_port:\unicast.lk_routing @look_ahead_routing:\mesh_torus.look_ahead_route @mesh_torus_look_ahead_routing
+  -----------------------------------------------------------------------------
+  Tag            : AlwaysFalseTrueCond-ML
+  Description    : Condition '[RTL_CONDITION]' can never be '[NodeType]' [Hierarchy: '[HIERARCHY]']
+  Violation      : Lint:5174
+  Goal           : lint_rtl
+  Module         : input_queue_per_port
+  FileName       : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber     : 247
+  Statement      :         PLw = (IS_FMESH) ? Pw : ELw,
+  RTL_CONDITION  : IS_FMESH
+  NodeType       : true
+  HIERARCHY      : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[1].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[2].the_input_queue_per_port @input_queue_per_port
+
+  -----------------------------------------------------------------------------
+  ExprParen  (81 errors/0 waived)
+  -----------------------------------------------------------------------------
+  Tag             : ExprParen
+  Description     : Use parenthesis in complex expression [RTL_EXPRESSION] [Node_Value]
+  Violation       : Lint:5995
+  Goal            : lint_rtl
+  Module          : look_ahead_routing
+  FileName        : ./../../rtl/src_noc/./routing.v
+  LineNumber      : 300
+  Statement       :         localparam SL_SW_LOC = ( SW_LOC > P-T3) ? 0 : SW_LOC; //single_local
+  RTL_EXPRESSION  : (Operators > and - used)
+  Node_Value      : (Expr: (SW_LOC > (P - T3)))
+  -----------------------------------------------------------------------------
+  Tag             : ExprParen
+  Description     : Use parenthesis in complex expression [RTL_EXPRESSION] [Node_Value]
+  Violation       : Lint:5958
+  Goal            : lint_rtl
+  Module          : ovc_list
+  FileName        : ./../../rtl/src_noc/./ovc_list.sv
+  LineNumber      : 36
+  Statement       :         logic [CVw-1 : 0] shiftted = CLASS_SETTING >> c*V;
+  RTL_EXPRESSION  : (Operators >> and * used)
+  Node_Value      : (Expr: (CLASS_SETTING >> (c * V)))
+  -----------------------------------------------------------------------------
+  Tag             : ExprParen
+  Description     : Use parenthesis in complex expression [RTL_EXPRESSION] [Node_Value]
+  Violation       : Lint:5945
+  Goal            : lint_rtl
+  Module          : 
+  FileName        : ./../../rtl/src_noc/./topology_localparam.v
+  LineNumber      : 122
+  Statement       :             if (router_port_num == 0 || router_port_num > 4 ) port_buffer_size = LB;
+  RTL_EXPRESSION  : (Operators == and || used)
+  Node_Value      : (Expr: ((router_port_num == 0) || (router_port_num > 4)))
+  -----------------------------------------------------------------------------
+  Tag             : ExprParen
+  Description     : Use parenthesis in complex expression [RTL_EXPRESSION] [Node_Value]
+  Violation       : Lint:5987
+  Goal            : lint_rtl
+  Module          : conventional_routing
+  FileName        : ./../../rtl/src_noc/./routing.v
+  LineNumber      : 55
+  Statement       :         while(2**log2<number) begin
+  RTL_EXPRESSION  : (Operators ** and < used)
+  Node_Value      : (Expr: ((2 ** log2) < number))
+  -----------------------------------------------------------------------------
+  Tag             : ExprParen
+  Description     : Use parenthesis in complex expression [RTL_EXPRESSION] [Node_Value]
+  Violation       : Lint:5976
+  Goal            : lint_rtl
+  Module          : mesh_torus_next_router_addr_predictor
+  FileName        : ./../../rtl/src_noc/./mesh_torus_routting.v
+  LineNumber      : 392
+  Statement       :     end else  if(TOPOLOGY=="RING" || TOPOLOGY == "LINE") begin : ring
+  RTL_EXPRESSION  : (Operators == and || used)
+  Node_Value      : (Expr: ((TOPOLOGY == "RING") || (TOPOLOGY == "LINE")))
+  -----------------------------------------------------------------------------
+  Tag             : ExprParen
+  Description     : Use parenthesis in complex expression [RTL_EXPRESSION] [Node_Value]
+  Violation       : Lint:6014
+  Goal            : lint_rtl
+  Module          : mesh_tori_endp_addr_decode
+  FileName        : ./../../rtl/src_noc/./mesh_torus.sv
+  LineNumber      : 945
+  Statement       :         while(2**log2<number) begin    
+  RTL_EXPRESSION  : (Operators ** and < used)
+  Node_Value      : (Expr: ((2 ** log2) < number))
+  -----------------------------------------------------------------------------
+  Tag             : ExprParen
+  Description     : Use parenthesis in complex expression [RTL_EXPRESSION] [Node_Value]
+  Violation       : Lint:5997
+  Goal            : lint_rtl
+  Module          : flit_buffer
+  FileName        : ./../../rtl/src_noc/./flit_buffer.sv
+  LineNumber      : 293
+  Statement       :                 if (wr[i] ) wr_ptr_next[i] =(wr_ptr[i]==(B*(i+1))-1)? (B*i) : wr_ptr [i]+ 1'h1;
+  RTL_EXPRESSION  : (Operators == and - used)
+  Node_Value      : (Expr: (wr_ptr[i] == ((B * (i + 1)) - 1)))
+  -----------------------------------------------------------------------------
+  Tag             : ExprParen
+  Description     : Use parenthesis in complex expression [RTL_EXPRESSION] [Node_Value]
+  Violation       : Lint:5986
+  Goal            : lint_rtl
+  Module          : congestion_out_gen
+  FileName        : ./../../rtl/src_noc/./congestion_analyzer.v
+  LineNumber      : 1028
+  Statement       :         end  else if  (CONGESTION_INDEX==11 || CONGESTION_INDEX==12) begin :indx11
+  RTL_EXPRESSION  : (Operators == and || used)
+  Node_Value      : (Expr: ((CONGESTION_INDEX == 11) || (CONGESTION_INDEX == 12)))
+  -----------------------------------------------------------------------------
+  Tag             : ExprParen
+  Description     : Use parenthesis in complex expression [RTL_EXPRESSION] [Node_Value]
+  Violation       : Lint:5965
+  Goal            : lint_rtl
+  Module          : input_queue_per_port
+  FileName        : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber      : 821
+  Statement       :         end else if ( TOPOLOGY == "FMESH" && CAST_TYPE== "UNICAST") begin : fmesh
+  RTL_EXPRESSION  : (Operators == and && used)
+  Node_Value      : (Expr: ((TOPOLOGY == "FMESH") && (CAST_TYPE == "UNICAST")))
+  -----------------------------------------------------------------------------
+  Tag             : ExprParen
+  Description     : Use parenthesis in complex expression [RTL_EXPRESSION] [Node_Value]
+  Violation       : Lint:6020
+  Goal            : lint_rtl
+  Module          : mesh_torus_noc_top
+  FileName        : ./../../rtl/src_noc/./mesh_torus_noc_top.sv
+  LineNumber      : 149
+  Statement       :                     if(x == NX-1)  assign chan_out_all [EAST_ID] = router_chan_out [fmesh_router_id(x,y)][EAST];
+  RTL_EXPRESSION  : (Operators == and - used)
+  Node_Value      : (Expr: (x == (NX - 1)))
+  -----------------------------------------------------------------------------
+  Tag             : ExprParen
+  Description     : Use parenthesis in complex expression [RTL_EXPRESSION] [Node_Value]
+  Violation       : Lint:5953
+  Goal            : lint_rtl
+  Module          : 
+  FileName        : ./../../rtl/src_noc/./topology_localparam.v
+  LineNumber      : 406
+  Statement       :             fmesh_addrencode = ( p<<(NXw+NYw) | (y<<NXw) | x);
+  RTL_EXPRESSION  : (Operators << and | used)
+  Node_Value      : (Expr: ((p << (NXw + NYw)) | (y << NXw)))
+  -----------------------------------------------------------------------------
+  Tag             : ExprParen
+  Description     : Use parenthesis in complex expression [RTL_EXPRESSION] [Node_Value]
+  Violation       : Lint:5968
+  Goal            : lint_rtl
+  Module          : mesh_torus_look_ahead_routing
+  FileName        : ./../../rtl/src_noc/./mesh_torus_routting.v
+  LineNumber      : 34
+  Statement       :         while(2**log2<number) begin    
+  RTL_EXPRESSION  : (Operators ** and < used)
+  Node_Value      : (Expr: ((2 ** log2) < number))
+  -----------------------------------------------------------------------------
+  Tag             : ExprParen
+  Description     : Use parenthesis in complex expression [RTL_EXPRESSION] [Node_Value]
+  Violation       : Lint:5959
+  Goal            : lint_rtl
+  Module          : ovc_list
+  FileName        : ./../../rtl/src_noc/./ovc_list.sv
+  LineNumber      : 46
+  Statement       :     assign  ovcs_out= (C == 0 || C == 1)? {V{1'b1}} : class_table[class_in];
+  RTL_EXPRESSION  : (Operators == and || used)
+  Node_Value      : (Expr: ((C == 0) || (C == 1)))
+  -----------------------------------------------------------------------------
+  Tag             : ExprParen
+  Description     : Use parenthesis in complex expression [RTL_EXPRESSION] [Node_Value]
+  Violation       : Lint:6008
+  Goal            : lint_rtl
+  Module          : mesh_torus_mask_non_assignable_destport_no_self_loop
+  FileName        : ./../../rtl/src_noc/./mesh_torus.sv
+  LineNumber      : 336
+  Statement       :         if ( ROUTE_NAME == "DOR" || ROUTE_NAME == "TRANC_DOR") begin :xy
+  RTL_EXPRESSION  : (Operators == and || used)
+  Node_Value      : (Expr: ((ROUTE_NAME == "DOR") || (ROUTE_NAME == "TRANC_DOR")))
+  -----------------------------------------------------------------------------
+  Tag             : ExprParen
+  Description     : Use parenthesis in complex expression [RTL_EXPRESSION] [Node_Value]
+  Violation       : Lint:5972
+  Goal            : lint_rtl
+  Module          : mesh_torus_deterministic_look_ahead_routing
+  FileName        : ./../../rtl/src_noc/./mesh_torus_routting.v
+  LineNumber      : 146
+  Statement       :     if (TOPOLOGY == "MESH" || TOPOLOGY == "TORUS" || TOPOLOGY == "FMESH" ) begin: twoD
+  RTL_EXPRESSION  : (Operators == and || used)
+  Node_Value      : (Expr: ((TOPOLOGY == "MESH") || (TOPOLOGY == "TORUS")))
+  -----------------------------------------------------------------------------
+  Tag             : ExprParen
+  Description     : Use parenthesis in complex expression [RTL_EXPRESSION] [Node_Value]
+  Violation       : Lint:5992
+  Goal            : lint_rtl
+  Module          : look_ahead_routing
+  FileName        : ./../../rtl/src_noc/./routing.v
+  LineNumber      : 260
+  Statement       :         while(2**log2<number) begin
+  RTL_EXPRESSION  : (Operators ** and < used)
+  Node_Value      : (Expr: ((2 ** log2) < number))
+  -----------------------------------------------------------------------------
+  Tag             : ExprParen
+  Description     : Use parenthesis in complex expression [RTL_EXPRESSION] [Node_Value]
+  Violation       : Lint:6006
+  Goal            : lint_rtl
+  Module          : mesh_torus_mask_non_assignable_destport
+  FileName        : ./../../rtl/src_noc/./mesh_torus.sv
+  LineNumber      : 255
+  Statement       :         wire sw_loc_val = (SW_LOC>0 && SW_LOC<5) ? 1'b0 : dest_port_in [SW_LOC];
+  RTL_EXPRESSION  : (Operators > and && used)
+  Node_Value      : (Expr: ((SW_LOC > 0) && (SW_LOC < 5)))
+  -----------------------------------------------------------------------------
+  Tag             : ExprParen
+  Description     : Use parenthesis in complex expression [RTL_EXPRESSION] [Node_Value]
+  Violation       : Lint:5981
+  Goal            : lint_rtl
+  Module          : xy_line_routing
+  FileName        : ./../../rtl/src_noc/./mesh_torus_routting.v
+  LineNumber      : 932
+  Statement       :         while(2**log2<number) begin    
+  RTL_EXPRESSION  : (Operators ** and < used)
+  Node_Value      : (Expr: ((2 ** log2) < number))
+  -----------------------------------------------------------------------------
+  Tag             : ExprParen
+  Description     : Use parenthesis in complex expression [RTL_EXPRESSION] [Node_Value]
+  Violation       : Lint:5955
+  Goal            : lint_rtl
+  Module          : one_hot_to_bin
+  FileName        : ./../../rtl/src_noc/./../main_comp.v
+  LineNumber      : 265
+  Statement       :         while(2**log2<number) begin    
+  RTL_EXPRESSION  : (Operators ** and < used)
+  Node_Value      : (Expr: ((2 ** log2) < number))
+  -----------------------------------------------------------------------------
+  Tag             : ExprParen
+  Description     : Use parenthesis in complex expression [RTL_EXPRESSION] [Node_Value]
+  Violation       : Lint:6002
+  Goal            : lint_rtl
+  Module          : fwft_fifo
+  FileName        : ./../../rtl/src_noc/./flit_buffer.sv
+  LineNumber      : 625
+  Statement       :         assign nearly_full = depth >= MAX_DEPTH [DEPTH_DATA_WIDTH-1 : 0] -1'b1;
+  RTL_EXPRESSION  : (Operators >= and - used)
+  Node_Value      : (Expr: (depth >= (MAX_DEPTH[(DEPTH_DATA_WIDTH - 1):0] - 1'b1)))
+  -----------------------------------------------------------------------------
+  Tag             : ExprParen
+  Description     : Use parenthesis in complex expression [RTL_EXPRESSION] [Node_Value]
+  Violation       : Lint:6004
+  Goal            : lint_rtl
+  Module          : fwft_fifo
+  FileName        : ./../../rtl/src_noc/./flit_buffer.sv
+  LineNumber      : 643
+  Statement       :         assign nearly_full = depth >= MAX_DEPTH [DEPTH_DATA_WIDTH-1 : 0] -1'b1;
+  RTL_EXPRESSION  : (Operators >= and - used)
+  Node_Value      : (Expr: (depth >= (MAX_DEPTH[(DEPTH_DATA_WIDTH - 1):0] - 1'b1)))
+  -----------------------------------------------------------------------------
+  Tag             : ExprParen
+  Description     : Use parenthesis in complex expression [RTL_EXPRESSION] [Node_Value]
+  Violation       : Lint:6015
+  Goal            : lint_rtl
+  Module          : mesh_tori_endp_addr_decode
+  FileName        : ./../../rtl/src_noc/./mesh_torus.sv
+  LineNumber      : 955
+  Statement       :         EYw = (TOPOLOGY=="RING" || TOPOLOGY == "LINE")? 1 : log2(NY),
+  RTL_EXPRESSION  : (Operators == and || used)
+  Node_Value      : (Expr: ((TOPOLOGY == "RING") || (TOPOLOGY == "LINE")))
+  -----------------------------------------------------------------------------
+  Tag             : ExprParen
+  Description     : Use parenthesis in complex expression [RTL_EXPRESSION] [Node_Value]
+  Violation       : Lint:5998
+  Goal            : lint_rtl
+  Module          : flit_buffer
+  FileName        : ./../../rtl/src_noc/./flit_buffer.sv
+  LineNumber      : 294
+  Statement       :                 if (rd[i] ) rd_ptr_next[i] =(rd_ptr[i]==(B*(i+1))-1)? (B*i) : rd_ptr [i]+ 1'h1;
+  RTL_EXPRESSION  : (Operators == and - used)
+  Node_Value      : (Expr: (rd_ptr[i] == ((B * (i + 1)) - 1)))
+  -----------------------------------------------------------------------------
+  Tag             : ExprParen
+  Description     : Use parenthesis in complex expression [RTL_EXPRESSION] [Node_Value]
+  Violation       : Lint:5957
+  Goal            : lint_rtl
+  Module          : my_one_hot_arbiter
+  FileName        : ./../../rtl/src_noc/./../arbiter.v
+  LineNumber      : 158
+  Statement       :         while(2**log2<number) begin
+  RTL_EXPRESSION  : (Operators ** and < used)
+  Node_Value      : (Expr: ((2 ** log2) < number))
+  -----------------------------------------------------------------------------
+  Tag             : ExprParen
+  Description     : Use parenthesis in complex expression [RTL_EXPRESSION] [Node_Value]
+  Violation       : Lint:5978
+  Goal            : lint_rtl
+  Module          : mesh_torus_conventional_routing
+  FileName        : ./../../rtl/src_noc/./mesh_torus_routting.v
+  LineNumber      : 623
+  Statement       :         P = (TOPOLOGY=="RING" || TOPOLOGY=="LINE" )? 3 : 5,
+  RTL_EXPRESSION  : (Operators == and || used)
+  Node_Value      : (Expr: ((TOPOLOGY == "RING") || (TOPOLOGY == "LINE")))
+  -----------------------------------------------------------------------------
+  Tag             : ExprParen
+  Description     : Use parenthesis in complex expression [RTL_EXPRESSION] [Node_Value]
+  Violation       : Lint:5985
+  Goal            : lint_rtl
+  Module          : smart_allocator_per_iport
+  FileName        : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber      : 607
+  Statement       :         (IS_MESH | IS_TORUS | IS_FMESH) ? (SW_LOC == 0 || SW_LOC > 4 ) : 0;
+  RTL_EXPRESSION  : (Operators == and || used)
+  Node_Value      : (Expr: ((SW_LOC == 0) || (SW_LOC > 4)))
+  -----------------------------------------------------------------------------
+  Tag             : ExprParen
+  Description     : Use parenthesis in complex expression [RTL_EXPRESSION] [Node_Value]
+  Violation       : Lint:5966
+  Goal            : lint_rtl
+  Module          : destp_generator
+  FileName        : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber      : 1166
+  Statement       :     end else if(TOPOLOGY == "RING" || TOPOLOGY == "LINE" || TOPOLOGY == "MESH"|| TOPOLOGY == "TORUS") begin : mesh
+  RTL_EXPRESSION  : (Operators == and || used)
+  Node_Value      : (Expr: ((TOPOLOGY == "RING") || (TOPOLOGY == "LINE")))
+  -----------------------------------------------------------------------------
+  Tag             : ExprParen
+  Description     : Use parenthesis in complex expression [RTL_EXPRESSION] [Node_Value]
+  Violation       : Lint:5974
+  Goal            : lint_rtl
+  Module          : mesh_torus_next_router_addr_predictor
+  FileName        : ./../../rtl/src_noc/./mesh_torus_routting.v
+  LineNumber      : 345
+  Statement       :         Yw = (TOPOLOGY=="RING" || TOPOLOGY == "LINE")? 1 : log2(NY);
+  RTL_EXPRESSION  : (Operators == and || used)
+  Node_Value      : (Expr: ((TOPOLOGY == "RING") || (TOPOLOGY == "LINE")))
+  -----------------------------------------------------------------------------
+  Tag             : ExprParen
+  Description     : Use parenthesis in complex expression [RTL_EXPRESSION] [Node_Value]
+  Violation       : Lint:6021
+  Goal            : lint_rtl
+  Module          : mesh_torus_noc_top
+  FileName        : ./../../rtl/src_noc/./mesh_torus_noc_top.sv
+  LineNumber      : 152
+  Statement       :                     if(y == NY-1 ) assign chan_out_all [SOUTH_ID] = router_chan_out[fmesh_router_id(x, y)][SOUTH];
+  RTL_EXPRESSION  : (Operators == and - used)
+  Node_Value      : (Expr: (y == (NY - 1)))
+  -----------------------------------------------------------------------------
+  Tag             : ExprParen
+  Description     : Use parenthesis in complex expression [RTL_EXPRESSION] [Node_Value]
+  Violation       : Lint:5948
+  Goal            : lint_rtl
+  Module          : 
+  FileName        : ./../../rtl/src_noc/./topology_localparam.v
+  LineNumber      : 298
+  Statement       :             (CAST_TYPE == "MULTICAST_PARTIAL" && EAw >= MCAST_PRTLw) ? EAw +1 : 
+  RTL_EXPRESSION  : (Operators == and && used)
+  Node_Value      : (Expr: ((CAST_TYPE == "MULTICAST_PARTIAL") && (EAw >= MCAST_PRTLw)))
+  -----------------------------------------------------------------------------
+  Tag             : ExprParen
+  Description     : Use parenthesis in complex expression [RTL_EXPRESSION] [Node_Value]
+  Violation       : Lint:5970
+  Goal            : lint_rtl
+  Module          : mesh_torus_deterministic_look_ahead_routing
+  FileName        : ./../../rtl/src_noc/./mesh_torus_routting.v
+  LineNumber      : 123
+  Statement       :         while(2**log2<number) begin    
+  RTL_EXPRESSION  : (Operators ** and < used)
+  Node_Value      : (Expr: ((2 ** log2) < number))
+  -----------------------------------------------------------------------------
+  Tag             : ExprParen
+  Description     : Use parenthesis in complex expression [RTL_EXPRESSION] [Node_Value]
+  Violation       : Lint:5954
+  Goal            : lint_rtl
+  Module          : 
+  FileName        : ./../../rtl/src_noc/./pronoc_pkg.sv
+  LineNumber      : 55
+  Statement       :         OVC_ALLOC_MODE= ((V==1 || B <= 4) ) ?   1'b1 : 1'b0;
+  RTL_EXPRESSION  : (Operators == and || used)
+  Node_Value      : (Expr: ((V == 1) || (B <= 4)))
+  -----------------------------------------------------------------------------
+  Tag             : ExprParen
+  Description     : Use parenthesis in complex expression [RTL_EXPRESSION] [Node_Value]
+  Violation       : Lint:5991
+  Goal            : lint_rtl
+  Module          : conventional_routing
+  FileName        : ./../../rtl/src_noc/./routing.v
+  LineNumber      : 140
+  Statement       :     end else if(TOPOLOGY == "FATTREE" || TOPOLOGY == "TREE" ) begin :tree_based
+  RTL_EXPRESSION  : (Operators == and || used)
+  Node_Value      : (Expr: ((TOPOLOGY == "FATTREE") || (TOPOLOGY == "TREE")))
+  -----------------------------------------------------------------------------
+  Tag             : ExprParen
+  Description     : Use parenthesis in complex expression [RTL_EXPRESSION] [Node_Value]
+  Violation       : Lint:6007
+  Goal            : lint_rtl
+  Module          : mesh_torus_mask_non_assignable_destport_no_self_loop
+  FileName        : ./../../rtl/src_noc/./mesh_torus.sv
+  LineNumber      : 328
+  Statement       :     if (TOPOLOGY == "RING" || TOPOLOGY == "LINE") begin : oneD // A port can send packets to all other ports in these topologies
+  RTL_EXPRESSION  : (Operators == and || used)
+  Node_Value      : (Expr: ((TOPOLOGY == "RING") || (TOPOLOGY == "LINE")))
+  -----------------------------------------------------------------------------
+  Tag             : ExprParen
+  Description     : Use parenthesis in complex expression [RTL_EXPRESSION] [Node_Value]
+  Violation       : Lint:5996
+  Goal            : lint_rtl
+  Module          : crossbar
+  FileName        : ./../../rtl/src_noc/./crossbar.v
+  LineNumber      : 47
+  Statement       :         while(2**log2<number) begin
+  RTL_EXPRESSION  : (Operators ** and < used)
+  Node_Value      : (Expr: ((2 ** log2) < number))
+  -----------------------------------------------------------------------------
+  Tag             : ExprParen
+  Description     : Use parenthesis in complex expression [RTL_EXPRESSION] [Node_Value]
+  Violation       : Lint:5967
+  Goal            : lint_rtl
+  Module          : mesh_torus_look_ahead_routing
+  FileName        : ./../../rtl/src_noc/./mesh_torus_routting.v
+  LineNumber      : 28
+  Statement       :     localparam  P = (TOPOLOGY == "MESH" || TOPOLOGY == "FMESH" || TOPOLOGY == "TORUS")?  5:3;
+  RTL_EXPRESSION  : (Operators == and || used)
+  Node_Value      : (Expr: ((TOPOLOGY == "MESH") || (TOPOLOGY == "FMESH")))
+  -----------------------------------------------------------------------------
+  Tag             : ExprParen
+  Description     : Use parenthesis in complex expression [RTL_EXPRESSION] [Node_Value]
+  Violation       : Lint:5979
+  Goal            : lint_rtl
+  Module          : mesh_torus_conventional_routing
+  FileName        : ./../../rtl/src_noc/./mesh_torus_routting.v
+  LineNumber      : 624
+  Statement       :         Yw = (TOPOLOGY=="RING" || TOPOLOGY=="LINE" )? 1 : log2(NY),
+  RTL_EXPRESSION  : (Operators == and || used)
+  Node_Value      : (Expr: ((TOPOLOGY == "RING") || (TOPOLOGY == "LINE")))
+  -----------------------------------------------------------------------------
+  Tag             : ExprParen
+  Description     : Use parenthesis in complex expression [RTL_EXPRESSION] [Node_Value]
+  Violation       : Lint:5962
+  Goal            : lint_rtl
+  Module          : input_queue_per_port
+  FileName        : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber      : 423
+  Statement       :     if ( TOPOLOGY == "FMESH" && CAST_TYPE== "UNICAST" ) begin : fmesh
+  RTL_EXPRESSION  : (Operators == and && used)
+  Node_Value      : (Expr: ((TOPOLOGY == "FMESH") && (CAST_TYPE == "UNICAST")))
+  -----------------------------------------------------------------------------
+  Tag             : ExprParen
+  Description     : Use parenthesis in complex expression [RTL_EXPRESSION] [Node_Value]
+  Violation       : Lint:5964
+  Goal            : lint_rtl
+  Module          : input_queue_per_port
+  FileName        : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber      : 800
+  Statement       :         if (( TOPOLOGY == "RING" || TOPOLOGY == "LINE" || TOPOLOGY == "MESH" || TOPOLOGY == "TORUS") && (T3>1) && (CAST_TYPE== "UNICAST")) begin : multi_local
+  RTL_EXPRESSION  : (Operators == and || used)
+  Node_Value      : (Expr: ((TOPOLOGY == "RING") || (TOPOLOGY == "LINE")))
+  -----------------------------------------------------------------------------
+  Tag             : ExprParen
+  Description     : Use parenthesis in complex expression [RTL_EXPRESSION] [Node_Value]
+  Violation       : Lint:5963
+  Goal            : lint_rtl
+  Module          : input_queue_per_port
+  FileName        : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber      : 441
+  Statement       :     if(TOPOLOGY=="FATTREE" && ROUTE_NAME == "NCA_STRAIGHT_UP") begin : fat
+  RTL_EXPRESSION  : (Operators == and && used)
+  Node_Value      : (Expr: ((TOPOLOGY == "FATTREE") && (ROUTE_NAME == "NCA_STRAIGHT_UP")))
+  -----------------------------------------------------------------------------
+  Tag             : ExprParen
+  Description     : Use parenthesis in complex expression [RTL_EXPRESSION] [Node_Value]
+  Violation       : Lint:5946
+  Goal            : lint_rtl
+  Module          : 
+  FileName        : ./../../rtl/src_noc/./topology_localparam.v
+  LineNumber      : 144
+  Statement       :             (ROUTE_NAME == "DOR" || ROUTE_NAME == "TRANC_DOR" )?    "DETERMINISTIC" : 
+  RTL_EXPRESSION  : (Operators == and || used)
+  Node_Value      : (Expr: ((ROUTE_NAME == "DOR") || (ROUTE_NAME == "TRANC_DOR")))
+  -----------------------------------------------------------------------------
+  Tag             : ExprParen
+  Description     : Use parenthesis in complex expression [RTL_EXPRESSION] [Node_Value]
+  Violation       : Lint:6011
+  Goal            : lint_rtl
+  Module          : mesh_torus_mask_non_assignable_destport_no_self_loop
+  FileName        : ./../../rtl/src_noc/./mesh_torus.sv
+  LineNumber      : 381
+  Statement       :         end else  if ( ROUTE_NAME == "NEGETIVE_FIRST" || ROUTE_NAME == "TRANC_NEGETIVE_FIRST") begin :negetive_first
+  RTL_EXPRESSION  : (Operators == and || used)
+  Node_Value      : (Expr: ((ROUTE_NAME == "NEGETIVE_FIRST") || (ROUTE_NAME == "TRANC_NEGETIVE_FIRST")))
+  -----------------------------------------------------------------------------
+  Tag             : ExprParen
+  Description     : Use parenthesis in complex expression [RTL_EXPRESSION] [Node_Value]
+  Violation       : Lint:5971
+  Goal            : lint_rtl
+  Module          : mesh_torus_deterministic_look_ahead_routing
+  FileName        : ./../../rtl/src_noc/./mesh_torus_routting.v
+  LineNumber      : 132
+  Statement       :         Yw = (TOPOLOGY=="RING" || TOPOLOGY == "LINE") ? 1 : log2(NY);    // number of node in y axis
+  RTL_EXPRESSION  : (Operators == and || used)
+  Node_Value      : (Expr: ((TOPOLOGY == "RING") || (TOPOLOGY == "LINE")))
+  -----------------------------------------------------------------------------
+  Tag             : ExprParen
+  Description     : Use parenthesis in complex expression [RTL_EXPRESSION] [Node_Value]
+  Violation       : Lint:6009
+  Goal            : lint_rtl
+  Module          : mesh_torus_mask_non_assignable_destport_no_self_loop
+  FileName        : ./../../rtl/src_noc/./mesh_torus.sv
+  LineNumber      : 352
+  Statement       :         end else  if ( ROUTE_NAME == "WEST_FIRST" || ROUTE_NAME == "TRANC_WEST_FIRST") begin :west_first
+  RTL_EXPRESSION  : (Operators == and || used)
+  Node_Value      : (Expr: ((ROUTE_NAME == "WEST_FIRST") || (ROUTE_NAME == "TRANC_WEST_FIRST")))
+  -----------------------------------------------------------------------------
+  Tag             : ExprParen
+  Description     : Use parenthesis in complex expression [RTL_EXPRESSION] [Node_Value]
+  Violation       : Lint:5975
+  Goal            : lint_rtl
+  Module          : mesh_torus_next_router_addr_predictor
+  FileName        : ./../../rtl/src_noc/./mesh_torus_routting.v
+  LineNumber      : 368
+  Statement       :     if(TOPOLOGY=="MESH" || TOPOLOGY == "TORUS" || TOPOLOGY == "FMESH" ) begin : mesh
+  RTL_EXPRESSION  : (Operators == and || used)
+  Node_Value      : (Expr: ((TOPOLOGY == "MESH") || (TOPOLOGY == "TORUS")))
+  -----------------------------------------------------------------------------
+  Tag             : ExprParen
+  Description     : Use parenthesis in complex expression [RTL_EXPRESSION] [Node_Value]
+  Violation       : Lint:5982
+  Goal            : lint_rtl
+  Module          : check_straight_oport
+  FileName        : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber      : 390
+  Statement       :         if (SS_PORT_LOC == 0 || SS_PORT_LOC > 4) begin : local_ports
+  RTL_EXPRESSION  : (Operators == and || used)
+  Node_Value      : (Expr: ((SS_PORT_LOC == 0) || (SS_PORT_LOC > 4)))
+  -----------------------------------------------------------------------------
+  Tag             : ExprParen
+  Description     : Use parenthesis in complex expression [RTL_EXPRESSION] [Node_Value]
+  Violation       : Lint:5944
+  Goal            : lint_rtl
+  Module          : 
+  FileName        : ./../../rtl/src_noc/./topology_localparam.v
+  LineNumber      : 107
+  Statement       :                     (current_port == (router_port_num-1)/2) ?  router_port_num: //DISABLED;
+  RTL_EXPRESSION  : (Operators == and / used)
+  Node_Value      : (Expr: (current_port == ((router_port_num - 1) / 2)))
+  -----------------------------------------------------------------------------
+  Tag             : ExprParen
+  Description     : Use parenthesis in complex expression [RTL_EXPRESSION] [Node_Value]
+  Violation       : Lint:6017
+  Goal            : lint_rtl
+  Module          : mesh_torus_noc_top
+  FileName        : ./../../rtl/src_noc/./mesh_torus_noc_top.sv
+  LineNumber      : 80
+  Statement       :                 (x < NX-1) ?  router_chan_out[x+1][BACKWARD] : 
+  RTL_EXPRESSION  : (Operators < and - used)
+  Node_Value      : (Expr: (x < (NX - 1)))
+  -----------------------------------------------------------------------------
+  Tag             : ExprParen
+  Description     : Use parenthesis in complex expression [RTL_EXPRESSION] [Node_Value]
+  Violation       : Lint:5980
+  Goal            : lint_rtl
+  Module          : mesh_torus_conventional_routing
+  FileName        : ./../../rtl/src_noc/./mesh_torus_routting.v
+  LineNumber      : 638
+  Statement       :     if (TOPOLOGY == "MESH" || TOPOLOGY == "FMESH")begin :mesh
+  RTL_EXPRESSION  : (Operators == and || used)
+  Node_Value      : (Expr: ((TOPOLOGY == "MESH") || (TOPOLOGY == "FMESH")))
+  -----------------------------------------------------------------------------
+  Tag             : ExprParen
+  Description     : Use parenthesis in complex expression [RTL_EXPRESSION] [Node_Value]
+  Violation       : Lint:5973
+  Goal            : lint_rtl
+  Module          : mesh_torus_next_router_addr_predictor
+  FileName        : ./../../rtl/src_noc/./mesh_torus_routting.v
+  LineNumber      : 337
+  Statement       :         while(2**log2<number) begin    
+  RTL_EXPRESSION  : (Operators ** and < used)
+  Node_Value      : (Expr: ((2 ** log2) < number))
+  -----------------------------------------------------------------------------
+  Tag             : ExprParen
+  Description     : Use parenthesis in complex expression [RTL_EXPRESSION] [Node_Value]
+  Violation       : Lint:5950
+  Goal            : lint_rtl
+  Module          : 
+  FileName        : ./../../rtl/src_noc/./topology_localparam.v
+  LineNumber      : 336
+  Statement       :             while( k!=mcast_id+1) begin              
+  RTL_EXPRESSION  : (Operators != and + used)
+  Node_Value      : (Expr: (k != (mcast_id + 1)))
+  -----------------------------------------------------------------------------
+  Tag             : ExprParen
+  Description     : Use parenthesis in complex expression [RTL_EXPRESSION] [Node_Value]
+  Violation       : Lint:5949
+  Goal            : lint_rtl
+  Module          : 
+  FileName        : ./../../rtl/src_noc/./topology_localparam.v
+  LineNumber      : 299
+  Statement       :             (CAST_TYPE == "MULTICAST_PARTIAL" && EAw <  MCAST_PRTLw) ? MCAST_PRTLw +1 :
+  RTL_EXPRESSION  : (Operators == and && used)
+  Node_Value      : (Expr: ((CAST_TYPE == "MULTICAST_PARTIAL") && (EAw < MCAST_PRTLw)))
+  -----------------------------------------------------------------------------
+  Tag             : ExprParen
+  Description     : Use parenthesis in complex expression [RTL_EXPRESSION] [Node_Value]
+  Violation       : Lint:6003
+  Goal            : lint_rtl
+  Module          : fwft_fifo
+  FileName        : ./../../rtl/src_noc/./flit_buffer.sv
+  LineNumber      : 628
+  Statement       :         assign recieve_more_than_1 = ~( depth == {DEPTH_DATA_WIDTH{1'b0}} ||  depth== 1 );
+  RTL_EXPRESSION  : (Operators == and || used)
+  Node_Value      : (Expr: ((depth == {DEPTH_DATA_WIDTH {1'b0}}) || (depth == 1)))
+  -----------------------------------------------------------------------------
+  Tag             : ExprParen
+  Description     : Use parenthesis in complex expression [RTL_EXPRESSION] [Node_Value]
+  Violation       : Lint:5941
+  Goal            : lint_rtl
+  Module          : 
+  FileName        : ./../../rtl/src_noc/./topology_localparam.v
+  LineNumber      : 53
+  Statement       :         while(2**log2<number) begin    
+  RTL_EXPRESSION  : (Operators ** and < used)
+  Node_Value      : (Expr: ((2 ** log2) < number))
+  -----------------------------------------------------------------------------
+  Tag             : ExprParen
+  Description     : Use parenthesis in complex expression [RTL_EXPRESSION] [Node_Value]
+  Violation       : Lint:5956
+  Goal            : lint_rtl
+  Module          : binary_mux
+  FileName        : ./../../rtl/src_noc/./../main_comp.v
+  LineNumber      : 308
+  Statement       :         while(2**log2<number) begin    
+  RTL_EXPRESSION  : (Operators ** and < used)
+  Node_Value      : (Expr: ((2 ** log2) < number))
+  -----------------------------------------------------------------------------
+  Tag             : ExprParen
+  Description     : Use parenthesis in complex expression [RTL_EXPRESSION] [Node_Value]
+  Violation       : Lint:6013
+  Goal            : lint_rtl
+  Module          : mesh_tori_router_addr_decode
+  FileName        : ./../../rtl/src_noc/./mesh_torus.sv
+  LineNumber      : 903
+  Statement       :         RYw = (TOPOLOGY=="RING" || TOPOLOGY == "LINE") ? 1 : log2(NY);    // number of node in y axis
+  RTL_EXPRESSION  : (Operators == and || used)
+  Node_Value      : (Expr: ((TOPOLOGY == "RING") || (TOPOLOGY == "LINE")))
+  -----------------------------------------------------------------------------
+  Tag             : ExprParen
+  Description     : Use parenthesis in complex expression [RTL_EXPRESSION] [Node_Value]
+  Violation       : Lint:6016
+  Goal            : lint_rtl
+  Module          : mesh_torus_destp_generator
+  FileName        : ./../../rtl/src_noc/./mesh_torus.sv
+  LineNumber      : 1145
+  Statement       :     if (TOPOLOGY == "RING" || TOPOLOGY == "LINE" ) begin : one_D
+  RTL_EXPRESSION  : (Operators == and || used)
+  Node_Value      : (Expr: ((TOPOLOGY == "RING") || (TOPOLOGY == "LINE")))
+  -----------------------------------------------------------------------------
+  Tag             : ExprParen
+  Description     : Use parenthesis in complex expression [RTL_EXPRESSION] [Node_Value]
+  Violation       : Lint:5942
+  Goal            : lint_rtl
+  Module          : 
+  FileName        : ./../../rtl/src_noc/./topology_localparam.v
+  LineNumber      : 92
+  Statement       :                 (IS_MULTI_MESH && current_port== UP)? DOWN: 
+  RTL_EXPRESSION  : (Operators && and == used)
+  Node_Value      : (Expr: (IS_MULTI_MESH && (current_port == UP)))
+  -----------------------------------------------------------------------------
+  Tag             : ExprParen
+  Description     : Use parenthesis in complex expression [RTL_EXPRESSION] [Node_Value]
+  Violation       : Lint:5960
+  Goal            : lint_rtl
+  Module          : vc_alloc_request_gen
+  FileName        : ./../../rtl/src_noc/./inout_ports.sv
+  LineNumber      : 529
+  Statement       :         if(P==5 && SELF_LOOP_EN == 0 )begin : sl_mesh // combine portsel and available VC mux as proposed in ProNoC paper
+  RTL_EXPRESSION  : (Operators == and && used)
+  Node_Value      : (Expr: ((P == 5) && (SELF_LOOP_EN == 0)))
+  -----------------------------------------------------------------------------
+  Tag             : ExprParen
+  Description     : Use parenthesis in complex expression [RTL_EXPRESSION] [Node_Value]
+  Violation       : Lint:6005
+  Goal            : lint_rtl
+  Module          : fwft_fifo
+  FileName        : ./../../rtl/src_noc/./flit_buffer.sv
+  LineNumber      : 646
+  Statement       :         assign recieve_more_than_1 = ~( depth == 0 ||  depth== 1 );
+  RTL_EXPRESSION  : (Operators == and || used)
+  Node_Value      : (Expr: ((depth == 0) || (depth == 1)))
+  -----------------------------------------------------------------------------
+  Tag             : ExprParen
+  Description     : Use parenthesis in complex expression [RTL_EXPRESSION] [Node_Value]
+  Violation       : Lint:6018
+  Goal            : lint_rtl
+  Module          : mesh_torus_noc_top
+  FileName        : ./../../rtl/src_noc/./mesh_torus_noc_top.sv
+  LineNumber      : 129
+  Statement       :                     (x < NX-1) ? router_chan_out[fmesh_router_id(x+1, y)][WEST] : //not_last_x
+  RTL_EXPRESSION  : (Operators < and - used)
+  Node_Value      : (Expr: (x < (NX - 1)))
+  -----------------------------------------------------------------------------
+  Tag             : ExprParen
+  Description     : Use parenthesis in complex expression [RTL_EXPRESSION] [Node_Value]
+  Violation       : Lint:5988
+  Goal            : lint_rtl
+  Module          : conventional_routing
+  FileName        : ./../../rtl/src_noc/./routing.v
+  LineNumber      : 69
+  Statement       :     if(TOPOLOGY == "MESH" || TOPOLOGY == "FMESH" || TOPOLOGY == "TORUS"  || TOPOLOGY ==  "RING" || TOPOLOGY ==  "LINE") begin :mesh_torus
+  RTL_EXPRESSION  : (Operators == and || used)
+  Node_Value      : (Expr: ((TOPOLOGY == "MESH") || (TOPOLOGY == "FMESH")))
+  -----------------------------------------------------------------------------
+  Tag             : ExprParen
+  Description     : Use parenthesis in complex expression [RTL_EXPRESSION] [Node_Value]
+  Violation       : Lint:5984
+  Goal            : lint_rtl
+  Module          : smart_allocator_per_iport
+  FileName        : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber      : 606
+  Statement       :         (IS_RING | IS_LINE) ? (SW_LOC == 0 || SW_LOC > 2) :
+  RTL_EXPRESSION  : (Operators == and || used)
+  Node_Value      : (Expr: ((SW_LOC == 0) || (SW_LOC > 2)))
+  -----------------------------------------------------------------------------
+  Tag             : ExprParen
+  Description     : Use parenthesis in complex expression [RTL_EXPRESSION] [Node_Value]
+  Violation       : Lint:6010
+  Goal            : lint_rtl
+  Module          : mesh_torus_mask_non_assignable_destport_no_self_loop
+  FileName        : ./../../rtl/src_noc/./mesh_torus.sv
+  LineNumber      : 369
+  Statement       :         end else  if ( ROUTE_NAME == "NORTH_LAST" || ROUTE_NAME == "TRANC_NORTH_LAST") begin :north_last
+  RTL_EXPRESSION  : (Operators == and || used)
+  Node_Value      : (Expr: ((ROUTE_NAME == "NORTH_LAST") || (ROUTE_NAME == "TRANC_NORTH_LAST")))
+  -----------------------------------------------------------------------------
+  Tag             : ExprParen
+  Description     : Use parenthesis in complex expression [RTL_EXPRESSION] [Node_Value]
+  Violation       : Lint:6012
+  Goal            : lint_rtl
+  Module          : mesh_tori_router_addr_decode
+  FileName        : ./../../rtl/src_noc/./mesh_torus.sv
+  LineNumber      : 893
+  Statement       :         while(2**log2<number) begin    
+  RTL_EXPRESSION  : (Operators ** and < used)
+  Node_Value      : (Expr: ((2 ** log2) < number))
+  -----------------------------------------------------------------------------
+  Tag             : ExprParen
+  Description     : Use parenthesis in complex expression [RTL_EXPRESSION] [Node_Value]
+  Violation       : Lint:5983
+  Goal            : lint_rtl
+  Module          : check_straight_oport
+  FileName        : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber      : 403
+  Statement       :         if (SS_PORT_LOC == 0 || SS_PORT_LOC > 2) begin : local_ports
+  RTL_EXPRESSION  : (Operators == and || used)
+  Node_Value      : (Expr: ((SS_PORT_LOC == 0) || (SS_PORT_LOC > 2)))
+  -----------------------------------------------------------------------------
+  Tag             : ExprParen
+  Description     : Use parenthesis in complex expression [RTL_EXPRESSION] [Node_Value]
+  Violation       : Lint:5961
+  Goal            : lint_rtl
+  Module          : input_queue_per_port
+  FileName        : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber      : 406
+  Statement       :     if (( TOPOLOGY == "RING" || TOPOLOGY == "LINE" || TOPOLOGY == "MESH" || TOPOLOGY == "TORUS") && (T3>1) && CAST_TYPE== "UNICAST") begin : multi_local
+  RTL_EXPRESSION  : (Operators == and || used)
+  Node_Value      : (Expr: ((TOPOLOGY == "RING") || (TOPOLOGY == "LINE")))
+  -----------------------------------------------------------------------------
+  Tag             : ExprParen
+  Description     : Use parenthesis in complex expression [RTL_EXPRESSION] [Node_Value]
+  Violation       : Lint:5951
+  Goal            : lint_rtl
+  Module          : 
+  FileName        : ./../../rtl/src_noc/./topology_localparam.v
+  LineNumber      : 392
+  Statement       :             end else if  ( diff < 2* NX) begin //bottom mesh edge 
+  RTL_EXPRESSION  : (Operators < and * used)
+  Node_Value      : (Expr: (diff < (2 * NX)))
+  -----------------------------------------------------------------------------
+  Tag             : ExprParen
+  Description     : Use parenthesis in complex expression [RTL_EXPRESSION] [Node_Value]
+  Violation       : Lint:5989
+  Goal            : lint_rtl
+  Module          : conventional_routing
+  FileName        : ./../../rtl/src_noc/./routing.v
+  LineNumber      : 75
+  Statement       :             RYw = (TOPOLOGY=="RING" || TOPOLOGY == "LINE") ? 1 :log2(NY),
+  RTL_EXPRESSION  : (Operators == and || used)
+  Node_Value      : (Expr: ((TOPOLOGY == "RING") || (TOPOLOGY == "LINE")))
+  -----------------------------------------------------------------------------
+  Tag             : ExprParen
+  Description     : Use parenthesis in complex expression [RTL_EXPRESSION] [Node_Value]
+  Violation       : Lint:5943
+  Goal            : lint_rtl
+  Module          : 
+  FileName        : ./../../rtl/src_noc/./topology_localparam.v
+  LineNumber      : 93
+  Statement       :                 (IS_MULTI_MESH && current_port== DOWN)? UP:
+  RTL_EXPRESSION  : (Operators && and == used)
+  Node_Value      : (Expr: (IS_MULTI_MESH && (current_port == DOWN)))
+  -----------------------------------------------------------------------------
+  Tag             : ExprParen
+  Description     : Use parenthesis in complex expression [RTL_EXPRESSION] [Node_Value]
+  Violation       : Lint:5977
+  Goal            : lint_rtl
+  Module          : mesh_torus_conventional_routing
+  FileName        : ./../../rtl/src_noc/./mesh_torus_routting.v
+  LineNumber      : 615
+  Statement       :         while(2**log2<number) begin    
+  RTL_EXPRESSION  : (Operators ** and < used)
+  Node_Value      : (Expr: ((2 ** log2) < number))
+  -----------------------------------------------------------------------------
+  Tag             : ExprParen
+  Description     : Use parenthesis in complex expression [RTL_EXPRESSION] [Node_Value]
+  Violation       : Lint:6000
+  Goal            : lint_rtl
+  Module          : fifo_ram
+  FileName        : ./../../rtl/src_noc/./flit_buffer.sv
+  LineNumber      : 450
+  Statement       :     reg [DATA_WIDTH-1:0] queue [2**ADDR_WIDTH-1:0] /* synthesis ramstyle = "no_rw_check , M9K" */;
+  RTL_EXPRESSION  : (Operators ** and - used)
+  Node_Value      : (Expr: ((2 ** ADDR_WIDTH) - 1))
+  -----------------------------------------------------------------------------
+  Tag             : ExprParen
+  Description     : Use parenthesis in complex expression [RTL_EXPRESSION] [Node_Value]
+  Violation       : Lint:5999
+  Goal            : lint_rtl
+  Module          : flit_buffer
+  FileName        : ./../../rtl/src_noc/./flit_buffer.sv
+  LineNumber      : 308
+  Statement       :                     else if(sub_rd[i])  sub_rd_ptr_next[i] = (sub_rd_ptr[i]==(B*(i+1))-1)? (B*i) : sub_rd_ptr [i]+ 1'h1; 
+  RTL_EXPRESSION  : (Operators == and - used)
+  Node_Value      : (Expr: (sub_rd_ptr[i] == ((B * (i + 1)) - 1)))
+  -----------------------------------------------------------------------------
+  Tag             : ExprParen
+  Description     : Use parenthesis in complex expression [RTL_EXPRESSION] [Node_Value]
+  Violation       : Lint:6019
+  Goal            : lint_rtl
+  Module          : mesh_torus_noc_top
+  FileName        : ./../../rtl/src_noc/./mesh_torus_noc_top.sv
+  LineNumber      : 144
+  Statement       :                     (y < NY-1)? router_chan_out[fmesh_router_id(x, y+1)][NORTH] : //not_last_y
+  RTL_EXPRESSION  : (Operators < and - used)
+  Node_Value      : (Expr: (y < (NY - 1)))
+  -----------------------------------------------------------------------------
+  Tag             : ExprParen
+  Description     : Use parenthesis in complex expression [RTL_EXPRESSION] [Node_Value]
+  Violation       : Lint:5947
+  Goal            : lint_rtl
+  Module          : 
+  FileName        : ./../../rtl/src_noc/./topology_localparam.v
+  LineNumber      : 145
+  Statement       :             (ROUTE_NAME == "FULL_ADPT" || ROUTE_NAME == "TRANC_FULL_ADPT" )?   "FULL_ADAPTIVE": "PAR_ADAPTIVE",
+  RTL_EXPRESSION  : (Operators == and || used)
+  Node_Value      : (Expr: ((ROUTE_NAME == "FULL_ADPT") || (ROUTE_NAME == "TRANC_FULL_ADPT")))
+  -----------------------------------------------------------------------------
+  Tag             : ExprParen
+  Description     : Use parenthesis in complex expression [RTL_EXPRESSION] [Node_Value]
+  Violation       : Lint:5993
+  Goal            : lint_rtl
+  Module          : look_ahead_routing
+  FileName        : ./../../rtl/src_noc/./routing.v
+  LineNumber      : 287
+  Statement       :     if(TOPOLOGY == "MESH" || TOPOLOGY == "FMESH" || TOPOLOGY == "TORUS"  || TOPOLOGY ==  "RING" || TOPOLOGY ==  "LINE")begin :mesh_torus
+  RTL_EXPRESSION  : (Operators == and || used)
+  Node_Value      : (Expr: ((TOPOLOGY == "MESH") || (TOPOLOGY == "FMESH")))
+  -----------------------------------------------------------------------------
+  Tag             : ExprParen
+  Description     : Use parenthesis in complex expression [RTL_EXPRESSION] [Node_Value]
+  Violation       : Lint:5990
+  Goal            : lint_rtl
+  Module          : conventional_routing
+  FileName        : ./../../rtl/src_noc/./routing.v
+  LineNumber      : 77
+  Statement       :             EYw = (TOPOLOGY=="RING" || TOPOLOGY == "LINE") ? 1 : RYw;
+  RTL_EXPRESSION  : (Operators == and || used)
+  Node_Value      : (Expr: ((TOPOLOGY == "RING") || (TOPOLOGY == "LINE")))
+  -----------------------------------------------------------------------------
+  Tag             : ExprParen
+  Description     : Use parenthesis in complex expression [RTL_EXPRESSION] [Node_Value]
+  Violation       : Lint:5994
+  Goal            : lint_rtl
+  Module          : look_ahead_routing
+  FileName        : ./../../rtl/src_noc/./routing.v
+  LineNumber      : 293
+  Statement       :             RYw = (TOPOLOGY=="RING" || TOPOLOGY == "LINE")? 1 : log2(NY),
+  RTL_EXPRESSION  : (Operators == and || used)
+  Node_Value      : (Expr: ((TOPOLOGY == "RING") || (TOPOLOGY == "LINE")))
+  -----------------------------------------------------------------------------
+  Tag             : ExprParen
+  Description     : Use parenthesis in complex expression [RTL_EXPRESSION] [Node_Value]
+  Violation       : Lint:5969
+  Goal            : lint_rtl
+  Module          : mesh_torus_look_ahead_routing
+  FileName        : ./../../rtl/src_noc/./mesh_torus_routting.v
+  LineNumber      : 43
+  Statement       :         Yw = (TOPOLOGY=="RING" || TOPOLOGY == "LINE") ? 1 : log2(NY);    // number of node in y axis
+  RTL_EXPRESSION  : (Operators == and || used)
+  Node_Value      : (Expr: ((TOPOLOGY == "RING") || (TOPOLOGY == "LINE")))
+  -----------------------------------------------------------------------------
+  Tag             : ExprParen
+  Description     : Use parenthesis in complex expression [RTL_EXPRESSION] [Node_Value]
+  Violation       : Lint:5952
+  Goal            : lint_rtl
+  Module          : 
+  FileName        : ./../../rtl/src_noc/./topology_localparam.v
+  LineNumber      : 396
+  Statement       :             end else if  ( diff < (2* NX)+NY ) begin //left mesh edge 
+  RTL_EXPRESSION  : (Operators < and + used)
+  Node_Value      : (Expr: (diff < ((2 * NX) + NY)))
+  -----------------------------------------------------------------------------
+  Tag             : ExprParen
+  Description     : Use parenthesis in complex expression [RTL_EXPRESSION] [Node_Value]
+  Violation       : Lint:6001
+  Goal            : lint_rtl
+  Module          : fwft_fifo
+  FileName        : ./../../rtl/src_noc/./flit_buffer.sv
+  LineNumber      : 568
+  Statement       :         while(2**log2<number) begin
+  RTL_EXPRESSION  : (Operators ** and < used)
+  Node_Value      : (Expr: ((2 ** log2) < number))
+
+  -----------------------------------------------------------------------------
+  FlopEConst  (1 error/0 waived)
+  -----------------------------------------------------------------------------
+  Tag              : FlopEConst
+  Description      : Enable pin [Input_Pin] on Flop [DesignObjSignal] (master [MasterName]) is [CValue](connected to [ObjSrcNet])
+  Violation        : Lint:4
+  Goal             : lint_rtl
+  Module           : fwft_fifo
+  MasterName       : RTL_FD
+  Input_Pin        : SEL
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/router_ref/the_inout_ports/the_input_port/Port_[2].the_input_queue_per_port/V_[0].smart_.dest_e_addr_fifo/mwb2.wb1.shiftreg[0][0]
+  CValue           :  always disabled (tied low)
+  ObjSrcNet        : tori_noc.noc_top/ring_line.R_[0].the_router/router_ref/the_inout_ports/the_input_port/Port_[2].the_input_queue_per_port/V_[0].smart_.dest_e_addr_fifo/wr_en
+  FileName         : ./../../rtl/src_noc/./flit_buffer.sv
+  LineNumber       : 601
+  Statement        :                     if(wr_en) shiftreg[i] <= {shiftreg[i][MAX_DEPTH-3 : 0]  ,din[i]};
+
+  -----------------------------------------------------------------------------
+  NoAssignX-ML  (15 errors/0 waived)
+  -----------------------------------------------------------------------------
+  Tag            : NoAssignX-ML
+  Description    : RHS of the assignment contains 'X'[Signal]
+  Violation      : Lint:3813
+  Goal           : lint_rtl
+  Module         : extract_header_flit_info
+  LINT_FOLLOWER  : 
+  FileName       : ./../../rtl/src_noc/./header_flit.sv
+  LineNumber     : 168
+  Statement      :         assign weight_o = {WEIGHTw{1'bX}};        
+  Signal         : 
+  -----------------------------------------------------------------------------
+  Tag            : NoAssignX-ML
+  Description    : RHS of the assignment contains 'X'[Signal]
+  Violation      : Lint:4612
+  Goal           : lint_rtl
+  Module         : nonspec_sw_alloc
+  LINT_FOLLOWER  : 
+  FileName       : ./../../rtl/src_noc/./comb_nonspec.sv
+  LineNumber     : 557
+  Statement      :             assign single_flit_granted_dst[i] = {P_1{1'bx}};
+  Signal         : 
+  -----------------------------------------------------------------------------
+  Tag            : NoAssignX-ML
+  Description    : RHS of the assignment contains 'X'[Signal]
+  Violation      : Lint:3750
+  Goal           : lint_rtl
+  Module         : input_queue_per_port
+  LINT_FOLLOWER  : 
+  FileName       : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber     : 862
+  Statement      :             assign vc_weight_is_consumed[i] = 1'bX;
+  Signal         : 
+  -----------------------------------------------------------------------------
+  Tag            : NoAssignX-ML
+  Description    : RHS of the assignment contains 'X'[Signal]
+  Violation      : Lint:3751
+  Goal           : lint_rtl
+  Module         : input_queue_per_port
+  LINT_FOLLOWER  : 
+  FileName       : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber     : 901
+  Statement      :         assign iport_weight_is_consumed=1'bX;
+  Signal         : 
+  -----------------------------------------------------------------------------
+  Tag            : NoAssignX-ML
+  Description    : RHS of the assignment contains 'X'[Signal]
+  Violation      : Lint:3831
+  Goal           : lint_rtl
+  Module         : flit_buffer
+  LINT_FOLLOWER  : 
+  FileName       : ./../../rtl/src_noc/./flit_buffer.sv
+  LineNumber     : 131
+  Statement      :         assign dout = {flgs_out,{V{1'bX}},flit_rest_out};
+  Signal         : 
+  -----------------------------------------------------------------------------
+  Tag            : NoAssignX-ML
+  Description    : RHS of the assignment contains 'X'[Signal]
+  Violation      : Lint:4569
+  Goal           : lint_rtl
+  Module         : combined_vc_sw_alloc
+  LINT_FOLLOWER  : 
+  FileName       : ./../../rtl/src_noc/./combined_vc_sw_alloc.sv
+  LineNumber     : 255
+  Statement      :         assign spec_granted_dest_port_all         = {PP_1{1'bx}};
+  Signal         : 
+  -----------------------------------------------------------------------------
+  Tag            : NoAssignX-ML
+  Description    : RHS of the assignment contains 'X'[Signal]
+  Violation      : Lint:3749
+  Goal           : lint_rtl
+  Module         : input_queue_per_port
+  LINT_FOLLOWER  : 
+  FileName       : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber     : 842
+  Statement      :             assign endp_localp_num[(i+1)*PLw-1 : i*PLw] = {PLw{1'bx}}; 
+  Signal         : 
+  -----------------------------------------------------------------------------
+  Tag            : NoAssignX-ML
+  Description    : RHS of the assignment contains 'X'[Signal]
+  Violation      : Lint:4557
+  Goal           : lint_rtl
+  Module         : vc_alloc_request_gen
+  LINT_FOLLOWER  : 
+  FileName       : ./../../rtl/src_noc/./inout_ports.sv
+  LineNumber     : 525
+  Statement      :         assign sel = {PV{1'bx}};
+  Signal         : 
+  -----------------------------------------------------------------------------
+  Tag            : NoAssignX-ML
+  Description    : RHS of the assignment contains 'X'[Signal]
+  Violation      : Lint:3814
+  Goal           : lint_rtl
+  Module         : extract_header_flit_info
+  LINT_FOLLOWER  : 
+  FileName       : ./../../rtl/src_noc/./header_flit.sv
+  LineNumber     : 173
+  Statement      :         assign be_o = {BEw{1'bX}};
+  Signal         : 
+  -----------------------------------------------------------------------------
+  Tag            : NoAssignX-ML
+  Description    : RHS of the assignment contains 'X'[Signal]
+  Violation      : Lint:4618
+  Goal           : lint_rtl
+  Module         : swa_input_port_arbiter
+  LINT_FOLLOWER  : 
+  FileName       : ./../../rtl/src_noc/./comb_nonspec.sv
+  LineNumber     : 665
+  Statement      :         assign winner_weight_consumed = 1'bx;
+  Signal         : 
+  -----------------------------------------------------------------------------
+  Tag            : NoAssignX-ML
+  Description    : RHS of the assignment contains 'X'[Signal]
+  Violation      : Lint:4556
+  Goal           : lint_rtl
+  Module         : vc_alloc_request_gen
+  LINT_FOLLOWER  : 
+  FileName       : ./../../rtl/src_noc/./inout_ports.sv
+  LineNumber     : 523
+  Statement      :         assign swap_port_presel = {PV{1'bx}};
+  Signal         : 
+  -----------------------------------------------------------------------------
+  Tag            : NoAssignX-ML
+  Description    : RHS of the assignment contains 'X'[Signal]
+  Violation      : Lint:4611
+  Goal           : lint_rtl
+  Module         : nonspec_sw_alloc
+  LINT_FOLLOWER  : 
+  FileName       : ./../../rtl/src_noc/./comb_nonspec.sv
+  LineNumber     : 556
+  Statement      :             assign single_flit_pck_local_grant[i] = 1'bx;
+  Signal         : 
+  -----------------------------------------------------------------------------
+  Tag            : NoAssignX-ML
+  Description    : RHS of the assignment contains 'X'[Signal]
+  Violation      : Lint:4570
+  Goal           : lint_rtl
+  Module         : combined_vc_sw_alloc
+  LINT_FOLLOWER  : 
+  FileName       : ./../../rtl/src_noc/./combined_vc_sw_alloc.sv
+  LineNumber     : 256
+  Statement      :         assign spec_ovc_num_all                      = {PVV{1'bx}};
+  Signal         : 
+  -----------------------------------------------------------------------------
+  Tag            : NoAssignX-ML
+  Description    : RHS of the assignment contains 'X'[Signal]
+  Violation      : Lint:3752
+  Goal           : lint_rtl
+  Module         : input_queue_per_port
+  LINT_FOLLOWER  : 
+  FileName       : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber     : 902
+  Statement      :         assign oports_weight = {WP{1'bX}};
+  Signal         : 
+  -----------------------------------------------------------------------------
+  Tag            : NoAssignX-ML
+  Description    : RHS of the assignment contains 'X'[Signal]
+  Violation      : Lint:4567
+  Goal           : lint_rtl
+  Module         : congestion_out_gen
+  LINT_FOLLOWER  : 
+  FileName       : ./../../rtl/src_noc/./congestion_analyzer.v
+  LineNumber     : 1043
+  Statement      :         assign  congestion_out_all_next = {CONG_ALw{1'bx}};   
+  Signal         : 
+
+  -----------------------------------------------------------------------------
+  OneModule-ML  (14 errors/0 waived)
+  -----------------------------------------------------------------------------
+  Tag              : OneModule-ML
+  Description      : File '[CulpritFileName]' contains more than one module
+  Violation        : Lint:2902
+  Goal             : lint_rtl
+  Module           : mesh_torus_deterministic_look_ahead_routing
+  FileName         : ./../../rtl/src_noc/./mesh_torus_routting.v
+  LineNumber       : 105
+  Statement        : module  mesh_torus_deterministic_look_ahead_routing #(
+  CulpritFileName  : ./../../rtl/src_noc/./mesh_torus_routting.v
+  -----------------------------------------------------------------------------
+  Tag              : OneModule-ML
+  Description      : File '[CulpritFileName]' contains more than one module
+  Violation        : Lint:2908
+  Goal             : lint_rtl
+  Module           : fifo_ram
+  FileName         : ./../../rtl/src_noc/./flit_buffer.sv
+  LineNumber       : 426
+  Statement        : module fifo_ram #(
+  CulpritFileName  : ./../../rtl/src_noc/./flit_buffer.sv
+  -----------------------------------------------------------------------------
+  Tag              : OneModule-ML
+  Description      : File '[CulpritFileName]' contains more than one module
+  Violation        : Lint:2899
+  Goal             : lint_rtl
+  Module           : nonspec_sw_alloc
+  FileName         : ./../../rtl/src_noc/./comb_nonspec.sv
+  LineNumber       : 425
+  Statement        : module nonspec_sw_alloc #(
+  CulpritFileName  : ./../../rtl/src_noc/./comb_nonspec.sv
+  -----------------------------------------------------------------------------
+  Tag              : OneModule-ML
+  Description      : File '[CulpritFileName]' contains more than one module
+  Violation        : Lint:2898
+  Goal             : lint_rtl
+  Module           : header_flit_update_lk_route_ovc
+  FileName         : ./../../rtl/src_noc/./header_flit.sv
+  LineNumber       : 195
+  Statement        : module header_flit_update_lk_route_ovc #(
+  CulpritFileName  : ./../../rtl/src_noc/./header_flit.sv
+  -----------------------------------------------------------------------------
+  Tag              : OneModule-ML
+  Description      : File '[CulpritFileName]' contains more than one module
+  Violation        : Lint:2906
+  Goal             : lint_rtl
+  Module           : look_ahead_routing
+  FileName         : ./../../rtl/src_noc/./routing.v
+  LineNumber       : 231
+  Statement        : module look_ahead_routing #(
+  CulpritFileName  : ./../../rtl/src_noc/./routing.v
+  -----------------------------------------------------------------------------
+  Tag              : OneModule-ML
+  Description      : File '[CulpritFileName]' contains more than one module
+  Violation        : Lint:2909
+  Goal             : lint_rtl
+  Module           : mesh_torus_mask_non_assignable_destport_no_self_loop
+  FileName         : ./../../rtl/src_noc/./mesh_torus.sv
+  LineNumber       : 280
+  Statement        : module mesh_torus_mask_non_assignable_destport_no_self_loop #(
+  CulpritFileName  : ./../../rtl/src_noc/./mesh_torus.sv
+  -----------------------------------------------------------------------------
+  Tag              : OneModule-ML
+  Description      : File '[CulpritFileName]' contains more than one module
+  Violation        : Lint:2907
+  Goal             : lint_rtl
+  Module           : credit_release_gen
+  FileName         : ./../../rtl/src_noc/./router_two_stage.sv
+  LineNumber       : 655
+  Statement        : module credit_release_gen #(
+  CulpritFileName  : ./../../rtl/src_noc/./router_two_stage.sv
+  -----------------------------------------------------------------------------
+  Tag              : OneModule-ML
+  Description      : File '[CulpritFileName]' contains more than one module
+  Violation        : Lint:2900
+  Goal             : lint_rtl
+  Module           : vc_alloc_request_gen
+  FileName         : ./../../rtl/src_noc/./inout_ports.sv
+  LineNumber       : 431
+  Statement        : module  vc_alloc_request_gen #(
+  CulpritFileName  : ./../../rtl/src_noc/./inout_ports.sv
+  -----------------------------------------------------------------------------
+  Tag              : OneModule-ML
+  Description      : File '[CulpritFileName]' contains more than one module
+  Violation        : Lint:2896
+  Goal             : lint_rtl
+  Module           : pronoc_register_reset_init
+  FileName         : ./../../rtl/src_noc/./../main_comp.v
+  LineNumber       : 52
+  Statement        : module pronoc_register_reset_init #(
+  CulpritFileName  : ./../../rtl/src_noc/./../main_comp.v
+  -----------------------------------------------------------------------------
+  Tag              : OneModule-ML
+  Description      : File '[CulpritFileName]' contains more than one module
+  Violation        : Lint:2905
+  Goal             : lint_rtl
+  Module           : credit_monitor_per_ovc
+  FileName         : ./../../rtl/src_noc/./output_ports.sv
+  LineNumber       : 397
+  Statement        : module   credit_monitor_per_ovc  #(
+  CulpritFileName  : ./../../rtl/src_noc/./output_ports.sv
+  -----------------------------------------------------------------------------
+  Tag              : OneModule-ML
+  Description      : File '[CulpritFileName]' contains more than one module
+  Violation        : Lint:2901
+  Goal             : lint_rtl
+  Module           : input_queue_per_port
+  FileName         : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber       : 181
+  Statement        : module input_queue_per_port #(
+  CulpritFileName  : ./../../rtl/src_noc/./input_ports.sv
+  -----------------------------------------------------------------------------
+  Tag              : OneModule-ML
+  Description      : File '[CulpritFileName]' contains more than one module
+  Violation        : Lint:2897
+  Goal             : lint_rtl
+  Module           : arbiter_priority_en
+  FileName         : ./../../rtl/src_noc/./../arbiter.v
+  LineNumber       : 88
+  Statement        : module arbiter_priority_en #(
+  CulpritFileName  : ./../../rtl/src_noc/./../arbiter.v
+  -----------------------------------------------------------------------------
+  Tag              : OneModule-ML
+  Description      : File '[CulpritFileName]' contains more than one module
+  Violation        : Lint:2903
+  Goal             : lint_rtl
+  Module           : onehot_mux_2D
+  FileName         : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber       : 41
+  Statement        : module onehot_mux_2D #(
+  CulpritFileName  : ./../../rtl/src_noc/./router_bypass.sv
+  -----------------------------------------------------------------------------
+  Tag              : OneModule-ML
+  Description      : File '[CulpritFileName]' contains more than one module
+  Violation        : Lint:2904
+  Goal             : lint_rtl
+  Module           : congestion_out_gen
+  FileName         : ./../../rtl/src_noc/./congestion_analyzer.v
+  LineNumber       : 946
+  Statement        : module congestion_out_gen #(
+  CulpritFileName  : ./../../rtl/src_noc/./congestion_analyzer.v
+
+  -----------------------------------------------------------------------------
+  SignedUnsignedExpr-ML  (1 error/0 waived)
+  -----------------------------------------------------------------------------
+  Tag             : SignedUnsignedExpr-ML
+  Description     : Unsigned expression '[RTL_EXPRESSION]' used with signed expression '[HdlExp]'[HDL_STATEMENT]
+  Violation       : Lint:3754
+  Goal            : lint_rtl
+  Module          : input_queue_per_port
+  FileName        : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber      : 241
+  Statement       :         MAX_PCK = (VC_REALLOCATION_TYPE== "ATOMIC")?  1 : NON_ATOM_PCKS + OVC_ALLOC_MODE,// min packet size is two hence the max packet number in buffer is (B/2)
+  RTL_EXPRESSION  : OVC_ALLOC_MODE
+  HdlExp          : NON_ATOM_PCKS
+  HDL_STATEMENT   : 
+
+  -----------------------------------------------------------------------------
+  STARC05-1.1.1.1  (8 errors/0 waived)
+  -----------------------------------------------------------------------------
+  Tag              : STARC05-1.1.1.1
+  Description      : Filename '[CulpritFileName]' does not indicate module and should be '[Module_Name]'[End_In_Name]
+  Violation        : Lint:3498
+  Goal             : lint_rtl
+  Module           : extract_header_flit_info
+  FileName         : ./../../rtl/src_noc/./header_flit.sv
+  LineNumber       : 107
+  Statement        : module extract_header_flit_info # (
+  CulpritFileName  : ./../../rtl/src_noc/./header_flit.sv
+  Module_Name      : extract_header_flit_info.sv
+  End_In_Name      : 
+  -----------------------------------------------------------------------------
+  Tag              : STARC05-1.1.1.1
+  Description      : Filename '[CulpritFileName]' does not indicate module and should be '[Module_Name]'[End_In_Name]
+  Violation        : Lint:3502
+  Goal             : lint_rtl
+  Module           : port_pre_sel_gen
+  FileName         : ./../../rtl/src_noc/./congestion_analyzer.v
+  LineNumber       : 326
+  Statement        : module port_pre_sel_gen #(
+  CulpritFileName  : ./../../rtl/src_noc/./congestion_analyzer.v
+  Module_Name      : port_pre_sel_gen.v
+  End_In_Name      : 
+  -----------------------------------------------------------------------------
+  Tag              : STARC05-1.1.1.1
+  Description      : Filename '[CulpritFileName]' does not indicate module and should be '[Module_Name]'[End_In_Name]
+  Violation        : Lint:3500
+  Goal             : lint_rtl
+  Module           : mesh_torus_look_ahead_routing
+  FileName         : ./../../rtl/src_noc/./mesh_torus_routting.v
+  LineNumber       : 8
+  Statement        : module mesh_torus_look_ahead_routing #(
+  CulpritFileName  : ./../../rtl/src_noc/./mesh_torus_routting.v
+  Module_Name      : mesh_torus_look_ahead_routing.v
+  End_In_Name      :  reason multiple modules
+  -----------------------------------------------------------------------------
+  Tag              : STARC05-1.1.1.1
+  Description      : Filename '[CulpritFileName]' does not indicate module and should be '[Module_Name]'[End_In_Name]
+  Violation        : Lint:3499
+  Goal             : lint_rtl
+  Module           : comb_nonspec_allocator
+  FileName         : ./../../rtl/src_noc/./comb_nonspec.sv
+  LineNumber       : 31
+  Statement        : module comb_nonspec_allocator # (
+  CulpritFileName  : ./../../rtl/src_noc/./comb_nonspec.sv
+  Module_Name      : comb_nonspec_allocator.sv
+  End_In_Name      : 
+  -----------------------------------------------------------------------------
+  Tag              : STARC05-1.1.1.1
+  Description      : Filename '[CulpritFileName]' does not indicate module and should be '[Module_Name]'[End_In_Name]
+  Violation        : Lint:3497
+  Goal             : lint_rtl
+  Module           : pronoc_register
+  FileName         : ./../../rtl/src_noc/./../main_comp.v
+  LineNumber       : 31
+  Statement        : module pronoc_register #(
+  CulpritFileName  : ./../../rtl/src_noc/./../main_comp.v
+  Module_Name      : pronoc_register.v
+  End_In_Name      : 
+  -----------------------------------------------------------------------------
+  Tag              : STARC05-1.1.1.1
+  Description      : Filename '[CulpritFileName]' does not indicate module and should be '[Module_Name]'[End_In_Name]
+  Violation        : Lint:3501
+  Goal             : lint_rtl
+  Module           : reduction_or
+  FileName         : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber       : 23
+  Statement        : module reduction_or #(
+  CulpritFileName  : ./../../rtl/src_noc/./router_bypass.sv
+  Module_Name      : reduction_or.sv
+  End_In_Name      : 
+  -----------------------------------------------------------------------------
+  Tag              : STARC05-1.1.1.1
+  Description      : Filename '[CulpritFileName]' does not indicate module and should be '[Module_Name]'[End_In_Name]
+  Violation        : Lint:3503
+  Goal             : lint_rtl
+  Module           : conventional_routing
+  FileName         : ./../../rtl/src_noc/./routing.v
+  LineNumber       : 30
+  Statement        : module conventional_routing #(
+  CulpritFileName  : ./../../rtl/src_noc/./routing.v
+  Module_Name      : conventional_routing.v
+  End_In_Name      : 
+  -----------------------------------------------------------------------------
+  Tag              : STARC05-1.1.1.1
+  Description      : Filename '[CulpritFileName]' does not indicate module and should be '[Module_Name]'[End_In_Name]
+  Violation        : Lint:3504
+  Goal             : lint_rtl
+  Module           : mesh_torus_mask_non_assignable_destport
+  FileName         : ./../../rtl/src_noc/./mesh_torus.sv
+  LineNumber       : 223
+  Statement        : module   mesh_torus_mask_non_assignable_destport #(
+  CulpritFileName  : ./../../rtl/src_noc/./mesh_torus.sv
+  Module_Name      : mesh_torus_mask_non_assignable_destport.sv
+  End_In_Name      : 
+
+  -----------------------------------------------------------------------------
+  STARC05-1.1.1.3  (154 errors/0 waived)
+  -----------------------------------------------------------------------------
+  Tag           : STARC05-1.1.1.3
+  Description   : Verilog/VHDL reserved keyword '[NodeName]' used
+  Violation     : Lint:3344
+  Goal          : lint_rtl
+  Module        : noc_top
+  FileName      : ./../../rtl/src_noc/./topology_localparam.v
+  LineNumber    : 377
+  Statement     :     input integer in;
+  NodeName      : in
+  -----------------------------------------------------------------------------
+  Tag           : STARC05-1.1.1.3
+  Description   : Verilog/VHDL reserved keyword '[NodeName]' used
+  Violation     : Lint:3368
+  Goal          : lint_rtl
+  Module        : noc_top
+  FileName      : ./../../rtl/src_noc/./route_torus.v
+  LineNumber    : 151
+  Statement     :     localparam LOCAL=   3'd0;  
+  NodeName      : LOCAL
+  -----------------------------------------------------------------------------
+  Tag           : STARC05-1.1.1.3
+  Description   : Verilog/VHDL reserved keyword '[NodeName]' used
+  Violation     : Lint:3464
+  Goal          : lint_rtl
+  Module        : oport_ovc_sig_gen
+  FileName      : ./../../rtl/src_noc/./output_ports.sv
+  LineNumber    : 501
+  Statement     :         .out (muxout1),
+  NodeName      : out
+  -----------------------------------------------------------------------------
+  Tag           : STARC05-1.1.1.3
+  Description   : Verilog/VHDL reserved keyword '[NodeName]' used
+  Violation     : Lint:3428
+  Goal          : lint_rtl
+  Module        : smart_validity_check_per_ivc
+  FileName      : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber    : 504
+  Statement     :     pronoc_register #(.W(1)) req1 (.in(smart_req_valid_next), .reset(reset), .clk(clk), .out(smart_req_valid));
+  NodeName      : in
+  -----------------------------------------------------------------------------
+  Tag           : STARC05-1.1.1.3
+  Description   : Verilog/VHDL reserved keyword '[NodeName]' used
+  Violation     : Lint:3426
+  Goal          : lint_rtl
+  Module        : smart_forward_ivc_info
+  FileName      : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber    : 299
+  Statement     :             ) register (
+  NodeName      : register
+  -----------------------------------------------------------------------------
+  Tag           : STARC05-1.1.1.3
+  Description   : Verilog/VHDL reserved keyword '[NodeName]' used
+  Violation     : Lint:3409
+  Goal          : lint_rtl
+  Module        : mesh_torus_look_ahead_routing
+  FileName      : ./../../rtl/src_noc/./mesh_torus_routting.v
+  LineNumber    : 95
+  Statement     :     pronoc_register #(.W(Xw) ) reg1 (.in(dest_x ), .out(destx_delayed), .reset(reset), .clk(clk));
+  NodeName      : out
+  -----------------------------------------------------------------------------
+  Tag           : STARC05-1.1.1.3
+  Description   : Verilog/VHDL reserved keyword '[NodeName]' used
+  Violation     : Lint:3423
+  Goal          : lint_rtl
+  Module        : onehot_mux_1D
+  FileName      : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber    : 66
+  Statement     :     output [W-1 : 0] out    
+  NodeName      : out
+  -----------------------------------------------------------------------------
+  Tag           : STARC05-1.1.1.3
+  Description   : Verilog/VHDL reserved keyword '[NodeName]' used
+  Violation     : Lint:3461
+  Goal          : lint_rtl
+  Module        : credit_monitor_per_ovc
+  FileName      : ./../../rtl/src_noc/./output_ports.sv
+  LineNumber    : 446
+  Statement     :         .in(credit_counter_next),
+  NodeName      : in
+  -----------------------------------------------------------------------------
+  Tag           : STARC05-1.1.1.3
+  Description   : Verilog/VHDL reserved keyword '[NodeName]' used
+  Violation     : Lint:3453
+  Goal          : lint_rtl
+  Module        : noc_top
+  FileName      : ./../../rtl/src_noc/./congestion_analyzer.v
+  LineNumber    : 865
+  Statement     :     in,
+  NodeName      : in
+  -----------------------------------------------------------------------------
+  Tag           : STARC05-1.1.1.3
+  Description   : Verilog/VHDL reserved keyword '[NodeName]' used
+  Violation     : Lint:3406
+  Goal          : lint_rtl
+  Module        : noc_top
+  FileName      : ./../../rtl/src_noc/./tree_route.v
+  LineNumber    : 252
+  Statement     :     pronoc_register #(.W(DSPw)) reg1 (.in(destport_encoded  ), .out(destport_encoded_delayed), .reset(reset), .clk(clk));
+  NodeName      : in
+  -----------------------------------------------------------------------------
+  Tag           : STARC05-1.1.1.3
+  Description   : Verilog/VHDL reserved keyword '[NodeName]' used
+  Violation     : Lint:3481
+  Goal          : lint_rtl
+  Module        : noc_top
+  FileName      : ./../../rtl/src_noc/./flit_buffer.sv
+  LineNumber    : 825
+  Statement     :     pronoc_register #(.W(DEPTH_DATA_WIDTH)) reg1 (.in(depth_next), .out(depth), .reset(reset), .clk(clk));
+  NodeName      : out
+  -----------------------------------------------------------------------------
+  Tag           : STARC05-1.1.1.3
+  Description   : Verilog/VHDL reserved keyword '[NodeName]' used
+  Violation     : Lint:3410
+  Goal          : lint_rtl
+  Module        : noc_top
+  FileName      : ./../../rtl/src_noc/./mesh_torus_routting.v
+  LineNumber    : 870
+  Statement     :         LOCAL = 3'b001,  
+  NodeName      : LOCAL
+  -----------------------------------------------------------------------------
+  Tag           : STARC05-1.1.1.3
+  Description   : Verilog/VHDL reserved keyword '[NodeName]' used
+  Violation     : Lint:3486
+  Goal          : lint_rtl
+  Module        : noc_top
+  FileName      : ./../../rtl/src_noc/./mesh_torus.sv
+  LineNumber    : 563
+  Statement     :         LOCAL = 0,  
+  NodeName      : LOCAL
+  -----------------------------------------------------------------------------
+  Tag           : STARC05-1.1.1.3
+  Description   : Verilog/VHDL reserved keyword '[NodeName]' used
+  Violation     : Lint:3412
+  Goal          : lint_rtl
+  Module        : noc_top
+  FileName      : ./../../rtl/src_noc/./route_mesh.v
+  LineNumber    : 69
+  Statement     :         LOCAL    =    (OUT_BIN==1)?    0 :  1 ,//5'b00001
+  NodeName      : LOCAL
+  -----------------------------------------------------------------------------
+  Tag           : STARC05-1.1.1.3
+  Description   : Verilog/VHDL reserved keyword '[NodeName]' used
+  Violation     : Lint:3447
+  Goal          : lint_rtl
+  Module        : noc_top
+  FileName      : ./../../rtl/src_noc/./congestion_analyzer.v
+  LineNumber    : 680
+  Statement     :             .in(ovc_not_avb[i]),
+  NodeName      : in
+  -----------------------------------------------------------------------------
+  Tag           : STARC05-1.1.1.3
+  Description   : Verilog/VHDL reserved keyword '[NodeName]' used
+  Violation     : Lint:3466
+  Goal          : lint_rtl
+  Module        : full_ovc_predictor
+  FileName      : ./../../rtl/src_noc/./output_ports.sv
+  LineNumber    : 577
+  Statement     :         .out    (full_muxout1),
+  NodeName      : out
+  -----------------------------------------------------------------------------
+  Tag           : STARC05-1.1.1.3
+  Description   : Verilog/VHDL reserved keyword '[NodeName]' used
+  Violation     : Lint:3480
+  Goal          : lint_rtl
+  Module        : noc_top
+  FileName      : ./../../rtl/src_noc/./flit_buffer.sv
+  LineNumber    : 825
+  Statement     :     pronoc_register #(.W(DEPTH_DATA_WIDTH)) reg1 (.in(depth_next), .out(depth), .reset(reset), .clk(clk));
+  NodeName      : in
+  -----------------------------------------------------------------------------
+  Tag           : STARC05-1.1.1.3
+  Description   : Verilog/VHDL reserved keyword '[NodeName]' used
+  Violation     : Lint:3399
+  Goal          : lint_rtl
+  Module        : noc_top
+  FileName      : ./../../rtl/src_noc/./wrra.v
+  LineNumber    : 230
+  Statement     :     pronoc_register #(.W(WEIGHTw)) reg2 (.in(counter_next ), .out(counter), .reset(reset), .clk(clk));
+  NodeName      : in
+  -----------------------------------------------------------------------------
+  Tag           : STARC05-1.1.1.3
+  Description   : Verilog/VHDL reserved keyword '[NodeName]' used
+  Violation     : Lint:3442
+  Goal          : lint_rtl
+  Module        : noc_top
+  FileName      : ./../../rtl/src_noc/./congestion_analyzer.v
+  LineNumber    : 494
+  Statement     :         .out(ivc_request_not_granted)
+  NodeName      : out
+  -----------------------------------------------------------------------------
+  Tag           : STARC05-1.1.1.3
+  Description   : Verilog/VHDL reserved keyword '[NodeName]' used
+  Violation     : Lint:3495
+  Goal          : lint_rtl
+  Module        : noc_top
+  FileName      : ./../../rtl/src_noc/./fmesh.sv
+  LineNumber    : 117
+  Statement     :         input integer in,nx,nxw,nl,nyw,ny;
+  NodeName      : in
+  -----------------------------------------------------------------------------
+  Tag           : STARC05-1.1.1.3
+  Description   : Verilog/VHDL reserved keyword '[NodeName]' used
+  Violation     : Lint:3492
+  Goal          : lint_rtl
+  Module        : noc_top
+  FileName      : ./../../rtl/src_noc/./mesh_torus.sv
+  LineNumber    : 1388
+  Statement     :     localparam LOCAL = 0,  
+  NodeName      : LOCAL
+  -----------------------------------------------------------------------------
+  Tag           : STARC05-1.1.1.3
+  Description   : Verilog/VHDL reserved keyword '[NodeName]' used
+  Violation     : Lint:3449
+  Goal          : lint_rtl
+  Module        : noc_top
+  FileName      : ./../../rtl/src_noc/./congestion_analyzer.v
+  LineNumber    : 741
+  Statement     :             .in(counter_in[i]),
+  NodeName      : in
+  -----------------------------------------------------------------------------
+  Tag           : STARC05-1.1.1.3
+  Description   : Verilog/VHDL reserved keyword '[NodeName]' used
+  Violation     : Lint:3385
+  Goal          : lint_rtl
+  Module        : comb_nonspec_allocator
+  FileName      : ./../../rtl/src_noc/./comb_nonspec.sv
+  LineNumber    : 186
+  Statement     :             .out(candidate_ovc_local_num[i]),
+  NodeName      : out
+  -----------------------------------------------------------------------------
+  Tag           : STARC05-1.1.1.3
+  Description   : Verilog/VHDL reserved keyword '[NodeName]' used
+  Violation     : Lint:3448
+  Goal          : lint_rtl
+  Module        : noc_top
+  FileName      : ./../../rtl/src_noc/./congestion_analyzer.v
+  LineNumber    : 681
+  Statement     :             .out(threshold[i])
+  NodeName      : out
+  -----------------------------------------------------------------------------
+  Tag           : STARC05-1.1.1.3
+  Description   : Verilog/VHDL reserved keyword '[NodeName]' used
+  Violation     : Lint:3487
+  Goal          : lint_rtl
+  Module        : noc_top
+  FileName      : ./../../rtl/src_noc/./mesh_torus.sv
+  LineNumber    : 625
+  Statement     :         .in(sel),
+  NodeName      : in
+  -----------------------------------------------------------------------------
+  Tag           : STARC05-1.1.1.3
+  Description   : Verilog/VHDL reserved keyword '[NodeName]' used
+  Violation     : Lint:3395
+  Goal          : lint_rtl
+  Module        : vc_alloc_request_gen_determinstic
+  FileName      : ./../../rtl/src_noc/./inout_ports.sv
+  LineNumber    : 666
+  Statement     :             .out    (ovc_avb_muxed      [i]),
+  NodeName      : out
+  -----------------------------------------------------------------------------
+  Tag           : STARC05-1.1.1.3
+  Description   : Verilog/VHDL reserved keyword '[NodeName]' used
+  Violation     : Lint:3450
+  Goal          : lint_rtl
+  Module        : noc_top
+  FileName      : ./../../rtl/src_noc/./congestion_analyzer.v
+  LineNumber    : 742
+  Statement     :             .out(threshold[i])
+  NodeName      : out
+  -----------------------------------------------------------------------------
+  Tag           : STARC05-1.1.1.3
+  Description   : Verilog/VHDL reserved keyword '[NodeName]' used
+  Violation     : Lint:3373
+  Goal          : lint_rtl
+  Module        : header_flit_update_lk_route_ovc
+  FileName      : ./../../rtl/src_noc/./header_flit.sv
+  LineNumber    : 232
+  Statement     :     pronoc_register #(.W(V)) reg1 (.in(vc_num_in), .out(vc_num_delayed), .reset(reset), .clk(clk));   
+  NodeName      : out
+  -----------------------------------------------------------------------------
+  Tag           : STARC05-1.1.1.3
+  Description   : Verilog/VHDL reserved keyword '[NodeName]' used
+  Violation     : Lint:3431
+  Goal          : lint_rtl
+  Module        : smart_allocator_per_iport
+  FileName      : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber    : 632
+  Statement     :     pronoc_register #(.W(DSTPw)) reg1 (.in(destport), .reset(reset), .clk(clk), .out(smart_destport_o));
+  NodeName      : out
+  -----------------------------------------------------------------------------
+  Tag           : STARC05-1.1.1.3
+  Description   : Verilog/VHDL reserved keyword '[NodeName]' used
+  Violation     : Lint:3392
+  Goal          : lint_rtl
+  Module        : swa_output_port_arbiter
+  FileName      : ./../../rtl/src_noc/./comb_nonspec.sv
+  LineNumber    : 730
+  Statement     :             .in(weight_consumed),
+  NodeName      : in
+  -----------------------------------------------------------------------------
+  Tag           : STARC05-1.1.1.3
+  Description   : Verilog/VHDL reserved keyword '[NodeName]' used
+  Violation     : Lint:3473
+  Goal          : lint_rtl
+  Module        : crossbar
+  FileName      : ./../../rtl/src_noc/./crossbar.v
+  LineNumber    : 122
+  Statement     :                 .out (flit_out_all[(i+1)*Fw-1 : i*Fw]),
+  NodeName      : out
+  -----------------------------------------------------------------------------
+  Tag           : STARC05-1.1.1.3
+  Description   : Verilog/VHDL reserved keyword '[NodeName]' used
+  Violation     : Lint:3488
+  Goal          : lint_rtl
+  Module        : noc_top
+  FileName      : ./../../rtl/src_noc/./mesh_torus.sv
+  LineNumber    : 626
+  Statement     :         .out(sel_muxed),
+  NodeName      : out
+  -----------------------------------------------------------------------------
+  Tag           : STARC05-1.1.1.3
+  Description   : Verilog/VHDL reserved keyword '[NodeName]' used
+  Violation     : Lint:3411
+  Goal          : lint_rtl
+  Module        : xy_line_routing
+  FileName      : ./../../rtl/src_noc/./mesh_torus_routting.v
+  LineNumber    : 948
+  Statement     :         LOCAL = (OUT_BIN)?  3'd0 : 3'b001,  
+  NodeName      : LOCAL
+  -----------------------------------------------------------------------------
+  Tag           : STARC05-1.1.1.3
+  Description   : Verilog/VHDL reserved keyword '[NodeName]' used
+  Violation     : Lint:3360
+  Goal          : lint_rtl
+  Module        : arbiter_3_one_hot
+  FileName      : ./../../rtl/src_noc/./../arbiter.v
+  LineNumber    : 213
+  Statement     :     output reg[2 : 0] out,
+  NodeName      : out
+  -----------------------------------------------------------------------------
+  Tag           : STARC05-1.1.1.3
+  Description   : Verilog/VHDL reserved keyword '[NodeName]' used
+  Violation     : Lint:3476
+  Goal          : lint_rtl
+  Module        : fwft_fifo
+  FileName      : ./../../rtl/src_noc/./flit_buffer.sv
+  LineNumber    : 636
+  Statement     :         reg [DATA_WIDTH-1 : 0] register;
+  NodeName      : register
+  -----------------------------------------------------------------------------
+  Tag           : STARC05-1.1.1.3
+  Description   : Verilog/VHDL reserved keyword '[NodeName]' used
+  Violation     : Lint:3359
+  Goal          : lint_rtl
+  Module        : arbiter_3_one_hot
+  FileName      : ./../../rtl/src_noc/./../arbiter.v
+  LineNumber    : 212
+  Statement     :     input [2 : 0] in,
+  NodeName      : in
+  -----------------------------------------------------------------------------
+  Tag           : STARC05-1.1.1.3
+  Description   : Verilog/VHDL reserved keyword '[NodeName]' used
+  Violation     : Lint:3427
+  Goal          : lint_rtl
+  Module        : smart_bypass_chanels
+  FileName      : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber    : 340
+  Statement     :     localparam DISABLE = P;
+  NodeName      : DISABLE
+  -----------------------------------------------------------------------------
+  Tag           : STARC05-1.1.1.3
+  Description   : Verilog/VHDL reserved keyword '[NodeName]' used
+  Violation     : Lint:3496
+  Goal          : lint_rtl
+  Module        : noc_top
+  FileName      : ./../../rtl/src_noc/./fmesh.sv
+  LineNumber    : 152
+  Statement     :         NEw = log2(NE);    
+  NodeName      : NEw
+  -----------------------------------------------------------------------------
+  Tag           : STARC05-1.1.1.3
+  Description   : Verilog/VHDL reserved keyword '[NodeName]' used
+  Violation     : Lint:3384
+  Goal          : lint_rtl
+  Module        : comb_nonspec_allocator
+  FileName      : ./../../rtl/src_noc/./comb_nonspec.sv
+  LineNumber    : 185
+  Statement     :             .in(masked_candidate_ovc_per_port[i]),
+  NodeName      : in
+  -----------------------------------------------------------------------------
+  Tag           : STARC05-1.1.1.3
+  Description   : Verilog/VHDL reserved keyword '[NodeName]' used
+  Violation     : Lint:3402
+  Goal          : lint_rtl
+  Module        : noc_top
+  FileName      : ./../../rtl/src_noc/./wrra.v
+  LineNumber    : 507
+  Statement     :             .out(weight_sum[i])         
+  NodeName      : out
+  -----------------------------------------------------------------------------
+  Tag           : STARC05-1.1.1.3
+  Description   : Verilog/VHDL reserved keyword '[NodeName]' used
+  Violation     : Lint:3459
+  Goal          : lint_rtl
+  Module        : output_ports
+  FileName      : ./../../rtl/src_noc/./output_ports.sv
+  LineNumber    : 120
+  Statement     :     pronoc_register #(.W(PV)) reg_1 ( .in(full_all_next), .reset(reset), .clk(clk), .out(full_all));
+  NodeName      : in
+  -----------------------------------------------------------------------------
+  Tag           : STARC05-1.1.1.3
+  Description   : Verilog/VHDL reserved keyword '[NodeName]' used
+  Violation     : Lint:3348
+  Goal          : lint_rtl
+  Module        : pronoc_register_reset_init
+  FileName      : ./../../rtl/src_noc/./../main_comp.v
+  LineNumber    : 55
+  Statement     :     input [W-1: 0] in,
+  NodeName      : in
+  -----------------------------------------------------------------------------
+  Tag           : STARC05-1.1.1.3
+  Description   : Verilog/VHDL reserved keyword '[NodeName]' used
+  Violation     : Lint:3463
+  Goal          : lint_rtl
+  Module        : oport_ovc_sig_gen
+  FileName      : ./../../rtl/src_noc/./output_ports.sv
+  LineNumber    : 500
+  Statement     :         .in  (assigned_ovc_num_masked),
+  NodeName      : in
+  -----------------------------------------------------------------------------
+  Tag           : STARC05-1.1.1.3
+  Description   : Verilog/VHDL reserved keyword '[NodeName]' used
+  Violation     : Lint:3437
+  Goal          : lint_rtl
+  Module        : noc_top
+  FileName      : ./../../rtl/src_noc/./congestion_analyzer.v
+  LineNumber    : 253
+  Statement     :     pronoc_register #(.W(PPSw)) reg1 (.in(conjestion_cmp ), .reset(reset), .clk(clk), .out(port_pre_sel));    
+  NodeName      : in
+  -----------------------------------------------------------------------------
+  Tag           : STARC05-1.1.1.3
+  Description   : Verilog/VHDL reserved keyword '[NodeName]' used
+  Violation     : Lint:3418
+  Goal          : lint_rtl
+  Module        : reduction_or
+  FileName      : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber    : 27
+  Statement     :     in,
+  NodeName      : in
+  -----------------------------------------------------------------------------
+  Tag           : STARC05-1.1.1.3
+  Description   : Verilog/VHDL reserved keyword '[NodeName]' used
+  Violation     : Lint:3405
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 345
+  Statement     :         .out    (ovc_is_assigned   ));
+  NodeName      : out
+  -----------------------------------------------------------------------------
+  Tag           : STARC05-1.1.1.3
+  Description   : Verilog/VHDL reserved keyword '[NodeName]' used
+  Violation     : Lint:3377
+  Goal          : lint_rtl
+  Module        : noc_top
+  FileName      : ./../../rtl/src_noc/./fattree_route.v
+  LineNumber    : 156
+  Statement     :         .in({counter[0],counter[K-1:1]}),
+  NodeName      : in
+  -----------------------------------------------------------------------------
+  Tag           : STARC05-1.1.1.3
+  Description   : Verilog/VHDL reserved keyword '[NodeName]' used
+  Violation     : Lint:3430
+  Goal          : lint_rtl
+  Module        : smart_allocator_per_iport
+  FileName      : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber    : 632
+  Statement     :     pronoc_register #(.W(DSTPw)) reg1 (.in(destport), .reset(reset), .clk(clk), .out(smart_destport_o));
+  NodeName      : in
+  -----------------------------------------------------------------------------
+  Tag           : STARC05-1.1.1.3
+  Description   : Verilog/VHDL reserved keyword '[NodeName]' used
+  Violation     : Lint:3470
+  Goal          : lint_rtl
+  Module        : router_two_stage
+  FileName      : ./../../rtl/src_noc/./router_two_stage.sv
+  LineNumber    : 345
+  Statement     :     pronoc_register #(.W(PP_1)) reg2 (.in(granted_dest_port_all ), .out(granted_dest_port_all_delayed), .reset(reset), .clk(clk));
+  NodeName      : in
+  -----------------------------------------------------------------------------
+  Tag           : STARC05-1.1.1.3
+  Description   : Verilog/VHDL reserved keyword '[NodeName]' used
+  Violation     : Lint:3379
+  Goal          : lint_rtl
+  Module        : noc_top
+  FileName      : ./../../rtl/src_noc/./fattree_route.v
+  LineNumber    : 246
+  Statement     :         .in({counter[0],counter[K-1:1]}),
+  NodeName      : in
+  -----------------------------------------------------------------------------
+  Tag           : STARC05-1.1.1.3
+  Description   : Verilog/VHDL reserved keyword '[NodeName]' used
+  Violation     : Lint:3484
+  Goal          : lint_rtl
+  Module        : noc_top
+  FileName      : ./../../rtl/src_noc/./mesh_torus.sv
+  LineNumber    : 472
+  Statement     :     pronoc_register #(.W(1)) reg2 (.in(swap_port_presel_next ), .out(swap_reg), .reset(reset), .clk(clk));
+  NodeName      : in
+  -----------------------------------------------------------------------------
+  Tag           : STARC05-1.1.1.3
+  Description   : Verilog/VHDL reserved keyword '[NodeName]' used
+  Violation     : Lint:3433
+  Goal          : lint_rtl
+  Module        : smart_credit_manage_per_vc
+  FileName      : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber    : 764
+  Statement     :     pronoc_register #(.W(Bw+1)) reg1 (.in(counter_next), .reset(reset), .clk(clk), .out(counter));
+  NodeName      : out
+  -----------------------------------------------------------------------------
+  Tag           : STARC05-1.1.1.3
+  Description   : Verilog/VHDL reserved keyword '[NodeName]' used
+  Violation     : Lint:3491
+  Goal          : lint_rtl
+  Module        : noc_top
+  FileName      : ./../../rtl/src_noc/./mesh_torus.sv
+  LineNumber    : 1096
+  Statement     :         NEw = log2(NE);    
+  NodeName      : NEw
+  -----------------------------------------------------------------------------
+  Tag           : STARC05-1.1.1.3
+  Description   : Verilog/VHDL reserved keyword '[NodeName]' used
+  Violation     : Lint:3478
+  Goal          : lint_rtl
+  Module        : fwft_fifo
+  FileName      : ./../../rtl/src_noc/./flit_buffer.sv
+  LineNumber    : 659
+  Statement     :     pronoc_register #(.W(DEPTH_DATA_WIDTH)) reg1 (.in(depth_next), .out(depth), .reset(reset), .clk(clk));
+  NodeName      : out
+  -----------------------------------------------------------------------------
+  Tag           : STARC05-1.1.1.3
+  Description   : Verilog/VHDL reserved keyword '[NodeName]' used
+  Violation     : Lint:3441
+  Goal          : lint_rtl
+  Module        : noc_top
+  FileName      : ./../../rtl/src_noc/./congestion_analyzer.v
+  LineNumber    : 491
+  Statement     :         .in(ivc_request_all & ~ivc_num_getting_sw_grant),
+  NodeName      : in
+  -----------------------------------------------------------------------------
+  Tag           : STARC05-1.1.1.3
+  Description   : Verilog/VHDL reserved keyword '[NodeName]' used
+  Violation     : Lint:3468
+  Goal          : lint_rtl
+  Module        : noc_top
+  FileName      : ./../../rtl/src_noc/./routing.v
+  LineNumber    : 465
+  Statement     :         .in(neighbors_rx),
+  NodeName      : in
+  -----------------------------------------------------------------------------
+  Tag           : STARC05-1.1.1.3
+  Description   : Verilog/VHDL reserved keyword '[NodeName]' used
+  Violation     : Lint:3460
+  Goal          : lint_rtl
+  Module        : output_ports
+  FileName      : ./../../rtl/src_noc/./output_ports.sv
+  LineNumber    : 120
+  Statement     :     pronoc_register #(.W(PV)) reg_1 ( .in(full_all_next), .reset(reset), .clk(clk), .out(full_all));
+  NodeName      : out
+  -----------------------------------------------------------------------------
+  Tag           : STARC05-1.1.1.3
+  Description   : Verilog/VHDL reserved keyword '[NodeName]' used
+  Violation     : Lint:3443
+  Goal          : lint_rtl
+  Module        : noc_top
+  FileName      : ./../../rtl/src_noc/./congestion_analyzer.v
+  LineNumber    : 574
+  Statement     :             .in(counter_in[i]),
+  NodeName      : in
+  -----------------------------------------------------------------------------
+  Tag           : STARC05-1.1.1.3
+  Description   : Verilog/VHDL reserved keyword '[NodeName]' used
+  Violation     : Lint:3440
+  Goal          : lint_rtl
+  Module        : noc_top
+  FileName      : ./../../rtl/src_noc/./congestion_analyzer.v
+  LineNumber    : 445
+  Statement     :         .out (congestion_out)
+  NodeName      : out
+  -----------------------------------------------------------------------------
+  Tag           : STARC05-1.1.1.3
+  Description   : Verilog/VHDL reserved keyword '[NodeName]' used
+  Violation     : Lint:3416
+  Goal          : lint_rtl
+  Module        : noc_top
+  FileName      : ./../../rtl/src_noc/./route_mesh.v
+  LineNumber    : 441
+  Statement     :     localparam LOCAL =  3'd0;  
+  NodeName      : LOCAL
+  -----------------------------------------------------------------------------
+  Tag           : STARC05-1.1.1.3
+  Description   : Verilog/VHDL reserved keyword '[NodeName]' used
+  Violation     : Lint:3421
+  Goal          : lint_rtl
+  Module        : onehot_mux_2D
+  FileName      : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber    : 47
+  Statement     :     out    
+  NodeName      : out
+  -----------------------------------------------------------------------------
+  Tag           : STARC05-1.1.1.3
+  Description   : Verilog/VHDL reserved keyword '[NodeName]' used
+  Violation     : Lint:3407
+  Goal          : lint_rtl
+  Module        : noc_top
+  FileName      : ./../../rtl/src_noc/./tree_route.v
+  LineNumber    : 252
+  Statement     :     pronoc_register #(.W(DSPw)) reg1 (.in(destport_encoded  ), .out(destport_encoded_delayed), .reset(reset), .clk(clk));
+  NodeName      : out
+  -----------------------------------------------------------------------------
+  Tag           : STARC05-1.1.1.3
+  Description   : Verilog/VHDL reserved keyword '[NodeName]' used
+  Violation     : Lint:3400
+  Goal          : lint_rtl
+  Module        : noc_top
+  FileName      : ./../../rtl/src_noc/./wrra.v
+  LineNumber    : 301
+  Statement     :         for (i=1;i<P;i=i+1)begin : port
+  NodeName      : port
+  -----------------------------------------------------------------------------
+  Tag           : STARC05-1.1.1.3
+  Description   : Verilog/VHDL reserved keyword '[NodeName]' used
+  Violation     : Lint:3408
+  Goal          : lint_rtl
+  Module        : mesh_torus_look_ahead_routing
+  FileName      : ./../../rtl/src_noc/./mesh_torus_routting.v
+  LineNumber    : 95
+  Statement     :     pronoc_register #(.W(Xw) ) reg1 (.in(dest_x ), .out(destx_delayed), .reset(reset), .clk(clk));
+  NodeName      : in
+  -----------------------------------------------------------------------------
+  Tag           : STARC05-1.1.1.3
+  Description   : Verilog/VHDL reserved keyword '[NodeName]' used
+  Violation     : Lint:3364
+  Goal          : lint_rtl
+  Module        : noc_top
+  FileName      : ./../../rtl/src_noc/./../arbiter.v
+  LineNumber    : 315
+  Statement     :         if(ARBITER_WIDTH    ==2) begin : w2 arbiter_2_one_hot arb( .in(request) , .out(grant), .low_pr(low_pr)); end
+  NodeName      : out
+  -----------------------------------------------------------------------------
+  Tag           : STARC05-1.1.1.3
+  Description   : Verilog/VHDL reserved keyword '[NodeName]' used
+  Violation     : Lint:3444
+  Goal          : lint_rtl
+  Module        : noc_top
+  FileName      : ./../../rtl/src_noc/./congestion_analyzer.v
+  LineNumber    : 575
+  Statement     :             .out(congestion_out[i])
+  NodeName      : out
+  -----------------------------------------------------------------------------
+  Tag           : STARC05-1.1.1.3
+  Description   : Verilog/VHDL reserved keyword '[NodeName]' used
+  Violation     : Lint:3425
+  Goal          : lint_rtl
+  Module        : smart_forward_ivc_info
+  FileName      : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber    : 264
+  Statement     :         pronoc_register #(.W(V)) reg1 (.in(ovc_locally_requested_next[i]), .reset(reset), .clk(clk), .out(ovc_locally_requested[i]));
+  NodeName      : out
+  -----------------------------------------------------------------------------
+  Tag           : STARC05-1.1.1.3
+  Description   : Verilog/VHDL reserved keyword '[NodeName]' used
+  Violation     : Lint:3375
+  Goal          : lint_rtl
+  Module        : noc_top
+  FileName      : ./../../rtl/src_noc/./fattree_route.v
+  LineNumber    : 63
+  Statement     :         .in({counter[0],counter[K-1:1]}),
+  NodeName      : in
+  -----------------------------------------------------------------------------
+  Tag           : STARC05-1.1.1.3
+  Description   : Verilog/VHDL reserved keyword '[NodeName]' used
+  Violation     : Lint:3374
+  Goal          : lint_rtl
+  Module        : noc_top
+  FileName      : ./../../rtl/src_noc/./fattree_noc_top.sv
+  LineNumber    : 96
+  Statement     :     genvar pos,level,port;
+  NodeName      : port
+  -----------------------------------------------------------------------------
+  Tag           : STARC05-1.1.1.3
+  Description   : Verilog/VHDL reserved keyword '[NodeName]' used
+  Violation     : Lint:3382
+  Goal          : lint_rtl
+  Module        : noc_top
+  FileName      : ./../../rtl/src_noc/./fattree_route.v
+  LineNumber    : 451
+  Statement     :         .out(destport_encoded_delayed)
+  NodeName      : out
+  -----------------------------------------------------------------------------
+  Tag           : STARC05-1.1.1.3
+  Description   : Verilog/VHDL reserved keyword '[NodeName]' used
+  Violation     : Lint:3355
+  Goal          : lint_rtl
+  Module        : my_one_hot_arbiter
+  FileName      : ./../../rtl/src_noc/./../arbiter.v
+  LineNumber    : 184
+  Statement     :         if(ARBITER_WIDTH    ==2) begin: w2  arbiter_2_one_hot arb( .in(request) , .out(grant), .low_pr(low_pr)); end
+  NodeName      : in
+  -----------------------------------------------------------------------------
+  Tag           : STARC05-1.1.1.3
+  Description   : Verilog/VHDL reserved keyword '[NodeName]' used
+  Violation     : Lint:3474
+  Goal          : lint_rtl
+  Module        : flit_buffer
+  FileName      : ./../../rtl/src_noc/./flit_buffer.sv
+  LineNumber    : 145
+  Statement     :         pronoc_register #(.W(PTRw),.RESET_TO(RESET_TO)) reg4 (.in(sub_rd_ptr_next[i]), .out(sub_rd_ptr[i]), .reset(reset), .clk(clk));
+  NodeName      : in
+  -----------------------------------------------------------------------------
+  Tag           : STARC05-1.1.1.3
+  Description   : Verilog/VHDL reserved keyword '[NodeName]' used
+  Violation     : Lint:3353
+  Goal          : lint_rtl
+  Module        : noc_top
+  FileName      : ./../../rtl/src_noc/./../main_comp.v
+  LineNumber    : 445
+  Statement     :     input   [IN_WIDTH-1 : 0]  in,
+  NodeName      : in
+  -----------------------------------------------------------------------------
+  Tag           : STARC05-1.1.1.3
+  Description   : Verilog/VHDL reserved keyword '[NodeName]' used
+  Violation     : Lint:3363
+  Goal          : lint_rtl
+  Module        : noc_top
+  FileName      : ./../../rtl/src_noc/./../arbiter.v
+  LineNumber    : 315
+  Statement     :         if(ARBITER_WIDTH    ==2) begin : w2 arbiter_2_one_hot arb( .in(request) , .out(grant), .low_pr(low_pr)); end
+  NodeName      : in
+  -----------------------------------------------------------------------------
+  Tag           : STARC05-1.1.1.3
+  Description   : Verilog/VHDL reserved keyword '[NodeName]' used
+  Violation     : Lint:3434
+  Goal          : lint_rtl
+  Module        : noc_top
+  FileName      : ./../../rtl/src_noc/./congestion_analyzer.v
+  LineNumber    : 77
+  Statement     :             .out(vc_counter[i])
+  NodeName      : out
+  -----------------------------------------------------------------------------
+  Tag           : STARC05-1.1.1.3
+  Description   : Verilog/VHDL reserved keyword '[NodeName]' used
+  Violation     : Lint:3393
+  Goal          : lint_rtl
+  Module        : swa_output_port_arbiter
+  FileName      : ./../../rtl/src_noc/./comb_nonspec.sv
+  LineNumber    : 731
+  Statement     :             .out(pr_en),
+  NodeName      : out
+  -----------------------------------------------------------------------------
+  Tag           : STARC05-1.1.1.3
+  Description   : Verilog/VHDL reserved keyword '[NodeName]' used
+  Violation     : Lint:3401
+  Goal          : lint_rtl
+  Module        : noc_top
+  FileName      : ./../../rtl/src_noc/./wrra.v
+  LineNumber    : 394
+  Statement     :             .out(counter_is_reset)
+  NodeName      : out
+  -----------------------------------------------------------------------------
+  Tag           : STARC05-1.1.1.3
+  Description   : Verilog/VHDL reserved keyword '[NodeName]' used
+  Violation     : Lint:3485
+  Goal          : lint_rtl
+  Module        : noc_top
+  FileName      : ./../../rtl/src_noc/./mesh_torus.sv
+  LineNumber    : 472
+  Statement     :     pronoc_register #(.W(1)) reg2 (.in(swap_port_presel_next ), .out(swap_reg), .reset(reset), .clk(clk));
+  NodeName      : out
+  -----------------------------------------------------------------------------
+  Tag           : STARC05-1.1.1.3
+  Description   : Verilog/VHDL reserved keyword '[NodeName]' used
+  Violation     : Lint:3352
+  Goal          : lint_rtl
+  Module        : noc_top
+  FileName      : ./../../rtl/src_noc/./../main_comp.v
+  LineNumber    : 358
+  Statement     :     wire [N-1 : 0] in [NUM-1 : 0];
+  NodeName      : in
+  -----------------------------------------------------------------------------
+  Tag           : STARC05-1.1.1.3
+  Description   : Verilog/VHDL reserved keyword '[NodeName]' used
+  Violation     : Lint:3417
+  Goal          : lint_rtl
+  Module        : noc_top
+  FileName      : ./../../rtl/src_noc/./route_mesh.v
+  LineNumber    : 565
+  Statement     :         LOCAL=   3'd0,  
+  NodeName      : LOCAL
+  -----------------------------------------------------------------------------
+  Tag           : STARC05-1.1.1.3
+  Description   : Verilog/VHDL reserved keyword '[NodeName]' used
+  Violation     : Lint:3354
+  Goal          : lint_rtl
+  Module        : noc_top
+  FileName      : ./../../rtl/src_noc/./../main_comp.v
+  LineNumber    : 466
+  Statement     :         .out(sum)         
+  NodeName      : out
+  -----------------------------------------------------------------------------
+  Tag           : STARC05-1.1.1.3
+  Description   : Verilog/VHDL reserved keyword '[NodeName]' used
+  Violation     : Lint:3438
+  Goal          : lint_rtl
+  Module        : noc_top
+  FileName      : ./../../rtl/src_noc/./congestion_analyzer.v
+  LineNumber    : 253
+  Statement     :     pronoc_register #(.W(PPSw)) reg1 (.in(conjestion_cmp ), .reset(reset), .clk(clk), .out(port_pre_sel));    
+  NodeName      : out
+  -----------------------------------------------------------------------------
+  Tag           : STARC05-1.1.1.3
+  Description   : Verilog/VHDL reserved keyword '[NodeName]' used
+  Violation     : Lint:3432
+  Goal          : lint_rtl
+  Module        : smart_credit_manage_per_vc
+  FileName      : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber    : 764
+  Statement     :     pronoc_register #(.W(Bw+1)) reg1 (.in(counter_next), .reset(reset), .clk(clk), .out(counter));
+  NodeName      : in
+  -----------------------------------------------------------------------------
+  Tag           : STARC05-1.1.1.3
+  Description   : Verilog/VHDL reserved keyword '[NodeName]' used
+  Violation     : Lint:3471
+  Goal          : lint_rtl
+  Module        : router_two_stage
+  FileName      : ./../../rtl/src_noc/./router_two_stage.sv
+  LineNumber    : 345
+  Statement     :     pronoc_register #(.W(PP_1)) reg2 (.in(granted_dest_port_all ), .out(granted_dest_port_all_delayed), .reset(reset), .clk(clk));
+  NodeName      : out
+  -----------------------------------------------------------------------------
+  Tag           : STARC05-1.1.1.3
+  Description   : Verilog/VHDL reserved keyword '[NodeName]' used
+  Violation     : Lint:3357
+  Goal          : lint_rtl
+  Module        : noc_top
+  FileName      : ./../../rtl/src_noc/./../arbiter.v
+  LineNumber    : 192
+  Statement     :     input [1 : 0] in,
+  NodeName      : in
+  -----------------------------------------------------------------------------
+  Tag           : STARC05-1.1.1.3
+  Description   : Verilog/VHDL reserved keyword '[NodeName]' used
+  Violation     : Lint:3376
+  Goal          : lint_rtl
+  Module        : noc_top
+  FileName      : ./../../rtl/src_noc/./fattree_route.v
+  LineNumber    : 66
+  Statement     :         .out(counter)
+  NodeName      : out
+  -----------------------------------------------------------------------------
+  Tag           : STARC05-1.1.1.3
+  Description   : Verilog/VHDL reserved keyword '[NodeName]' used
+  Violation     : Lint:3414
+  Goal          : lint_rtl
+  Module        : noc_top
+  FileName      : ./../../rtl/src_noc/./route_mesh.v
+  LineNumber    : 232
+  Statement     :         LOCAL=   3'd0,  
+  NodeName      : LOCAL
+  -----------------------------------------------------------------------------
+  Tag           : STARC05-1.1.1.3
+  Description   : Verilog/VHDL reserved keyword '[NodeName]' used
+  Violation     : Lint:3343
+  Goal          : lint_rtl
+  Module        : noc_top
+  FileName      : ./../../rtl/src_noc/./topology_localparam.v
+  LineNumber    : 34
+  Statement     :         LOCAL   =   0,
+  NodeName      : LOCAL
+  -----------------------------------------------------------------------------
+  Tag           : STARC05-1.1.1.3
+  Description   : Verilog/VHDL reserved keyword '[NodeName]' used
+  Violation     : Lint:3462
+  Goal          : lint_rtl
+  Module        : credit_monitor_per_ovc
+  FileName      : ./../../rtl/src_noc/./output_ports.sv
+  LineNumber    : 449
+  Statement     :         .out(credit_counter),
+  NodeName      : out
+  -----------------------------------------------------------------------------
+  Tag           : STARC05-1.1.1.3
+  Description   : Verilog/VHDL reserved keyword '[NodeName]' used
+  Violation     : Lint:3350
+  Goal          : lint_rtl
+  Module        : binary_mux
+  FileName      : ./../../rtl/src_noc/./../main_comp.v
+  LineNumber    : 324
+  Statement     :             for (i=0; i< IN_NUM; i=i+1) begin : loop
+  NodeName      : loop
+  -----------------------------------------------------------------------------
+  Tag           : STARC05-1.1.1.3
+  Description   : Verilog/VHDL reserved keyword '[NodeName]' used
+  Violation     : Lint:3436
+  Goal          : lint_rtl
+  Module        : noc_top
+  FileName      : ./../../rtl/src_noc/./congestion_analyzer.v
+  LineNumber    : 173
+  Statement     :             .out(credit_per_port[i])
+  NodeName      : out
+  -----------------------------------------------------------------------------
+  Tag           : STARC05-1.1.1.3
+  Description   : Verilog/VHDL reserved keyword '[NodeName]' used
+  Violation     : Lint:3356
+  Goal          : lint_rtl
+  Module        : my_one_hot_arbiter
+  FileName      : ./../../rtl/src_noc/./../arbiter.v
+  LineNumber    : 184
+  Statement     :         if(ARBITER_WIDTH    ==2) begin: w2  arbiter_2_one_hot arb( .in(request) , .out(grant), .low_pr(low_pr)); end
+  NodeName      : out
+  -----------------------------------------------------------------------------
+  Tag           : STARC05-1.1.1.3
+  Description   : Verilog/VHDL reserved keyword '[NodeName]' used
+  Violation     : Lint:3452
+  Goal          : lint_rtl
+  Module        : noc_top
+  FileName      : ./../../rtl/src_noc/./congestion_analyzer.v
+  LineNumber    : 822
+  Statement     :         .out(ivc_request_not_granted)
+  NodeName      : out
+  -----------------------------------------------------------------------------
+  Tag           : STARC05-1.1.1.3
+  Description   : Verilog/VHDL reserved keyword '[NodeName]' used
+  Violation     : Lint:3493
+  Goal          : lint_rtl
+  Module        : noc_top
+  FileName      : ./../../rtl/src_noc/./debug.v
+  LineNumber    : 482
+  Statement     :     localparam NEw= log2(NE);
+  NodeName      : NEw
+  -----------------------------------------------------------------------------
+  Tag           : STARC05-1.1.1.3
+  Description   : Verilog/VHDL reserved keyword '[NodeName]' used
+  Violation     : Lint:3349
+  Goal          : lint_rtl
+  Module        : pronoc_register_reset_init
+  FileName      : ./../../rtl/src_noc/./../main_comp.v
+  LineNumber    : 58
+  Statement     :     output reg [W-1: 0] out,
+  NodeName      : out
+  -----------------------------------------------------------------------------
+  Tag           : STARC05-1.1.1.3
+  Description   : Verilog/VHDL reserved keyword '[NodeName]' used
+  Violation     : Lint:3439
+  Goal          : lint_rtl
+  Module        : noc_top
+  FileName      : ./../../rtl/src_noc/./congestion_analyzer.v
+  LineNumber    : 444
+  Statement     :         .in (ivc_request_all),
+  NodeName      : in
+  -----------------------------------------------------------------------------
+  Tag           : STARC05-1.1.1.3
+  Description   : Verilog/VHDL reserved keyword '[NodeName]' used
+  Violation     : Lint:3351
+  Goal          : lint_rtl
+  Module        : noc_top
+  FileName      : ./../../rtl/src_noc/./../main_comp.v
+  LineNumber    : 341
+  Statement     :     out         
+  NodeName      : out
+  -----------------------------------------------------------------------------
+  Tag           : STARC05-1.1.1.3
+  Description   : Verilog/VHDL reserved keyword '[NodeName]' used
+  Violation     : Lint:3404
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 342
+  Statement     :         .in     (ovc_is_assigned_next), 
+  NodeName      : in
+  -----------------------------------------------------------------------------
+  Tag           : STARC05-1.1.1.3
+  Description   : Verilog/VHDL reserved keyword '[NodeName]' used
+  Violation     : Lint:3403
+  Goal          : lint_rtl
+  Module        : noc_top
+  FileName      : ./../../rtl/src_noc/./wrra.v
+  LineNumber    : 690
+  Statement     :             .out(iweight_sum)         
+  NodeName      : out
+  -----------------------------------------------------------------------------
+  Tag           : STARC05-1.1.1.3
+  Description   : Verilog/VHDL reserved keyword '[NodeName]' used
+  Violation     : Lint:3420
+  Goal          : lint_rtl
+  Module        : onehot_mux_2D
+  FileName      : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber    : 45
+  Statement     :     in,
+  NodeName      : in
+
+  -----------------------------------------------------------------------------
+  STARC05-2.10.3.7  (8 errors/0 waived)
+  -----------------------------------------------------------------------------
+  Tag             : STARC05-2.10.3.7
+  Description     : Bit-width '[Exp_Size]' should match the based number width '[ExprSize]' in '[RTL_EXPRESSION]'
+  Violation       : Lint:3966
+  Goal            : lint_rtl
+  Module          : mesh_torus_next_router_addr_predictor
+  FileName        : ./../../rtl/src_noc/./mesh_torus_routting.v
+  LineNumber      : 348
+  Statement       :         EAST = 3'd1, 
+  Exp_Size        : 1
+  ExprSize        : 3
+  RTL_EXPRESSION  : 3'd1
+  -----------------------------------------------------------------------------
+  Tag             : STARC05-2.10.3.7
+  Description     : Bit-width '[Exp_Size]' should match the based number width '[ExprSize]' in '[RTL_EXPRESSION]'
+  Violation       : Lint:3987
+  Goal            : lint_rtl
+  Module          : xy_line_routing
+  FileName        : ./../../rtl/src_noc/./mesh_torus_routting.v
+  LineNumber      : 950
+  Statement       :         MINUS = (OUT_BIN)?  3'd2 : 3'b100;         
+  Exp_Size        : 2
+  ExprSize        : 3
+  RTL_EXPRESSION  : 3'd2
+  -----------------------------------------------------------------------------
+  Tag             : STARC05-2.10.3.7
+  Description     : Bit-width '[Exp_Size]' should match the based number width '[ExprSize]' in '[RTL_EXPRESSION]'
+  Violation       : Lint:4635
+  Goal            : lint_rtl
+  Module          : arbiter_3_one_hot
+  FileName        : ./../../rtl/src_noc/./../arbiter.v
+  LineNumber      : 223
+  Statement       :             2'd1:
+  Exp_Size        : 1
+  ExprSize        : 2
+  RTL_EXPRESSION  : 2'd1
+  -----------------------------------------------------------------------------
+  Tag             : STARC05-2.10.3.7
+  Description     : Bit-width '[Exp_Size]' should match the based number width '[ExprSize]' in '[RTL_EXPRESSION]'
+  Violation       : Lint:3967
+  Goal            : lint_rtl
+  Module          : mesh_torus_next_router_addr_predictor
+  FileName        : ./../../rtl/src_noc/./mesh_torus_routting.v
+  LineNumber      : 349
+  Statement       :         NORTH = 3'd2,  
+  Exp_Size        : 2
+  ExprSize        : 3
+  RTL_EXPRESSION  : 3'd2
+  -----------------------------------------------------------------------------
+  Tag             : STARC05-2.10.3.7
+  Description     : Bit-width '[Exp_Size]' should match the based number width '[ExprSize]' in '[RTL_EXPRESSION]'
+  Violation       : Lint:3989
+  Goal            : lint_rtl
+  Module          : line_ring_encode_dstport
+  FileName        : ./../../rtl/src_noc/./mesh_torus_routting.v
+  LineNumber      : 977
+  Statement       :         FORWARD = 2'd1,
+  Exp_Size        : 1
+  ExprSize        : 2
+  RTL_EXPRESSION  : 2'd1
+  -----------------------------------------------------------------------------
+  Tag             : STARC05-2.10.3.7
+  Description     : Bit-width '[Exp_Size]' should match the based number width '[ExprSize]' in '[RTL_EXPRESSION]'
+  Violation       : Lint:3969
+  Goal            : lint_rtl
+  Module          : mesh_torus_next_router_addr_predictor
+  FileName        : ./../../rtl/src_noc/./mesh_torus_routting.v
+  LineNumber      : 354
+  Statement       :         FORWARD = 2'd1,
+  Exp_Size        : 1
+  ExprSize        : 2
+  RTL_EXPRESSION  : 2'd1
+  -----------------------------------------------------------------------------
+  Tag             : STARC05-2.10.3.7
+  Description     : Bit-width '[Exp_Size]' should match the based number width '[ExprSize]' in '[RTL_EXPRESSION]'
+  Violation       : Lint:3986
+  Goal            : lint_rtl
+  Module          : xy_line_routing
+  FileName        : ./../../rtl/src_noc/./mesh_torus_routting.v
+  LineNumber      : 949
+  Statement       :         PLUS = (OUT_BIN)?  3'd1 : 3'b010,   
+  Exp_Size        : 1
+  ExprSize        : 3
+  RTL_EXPRESSION  : 3'd1
+  -----------------------------------------------------------------------------
+  Tag             : STARC05-2.10.3.7
+  Description     : Bit-width '[Exp_Size]' should match the based number width '[ExprSize]' in '[RTL_EXPRESSION]'
+  Violation       : Lint:3968
+  Goal            : lint_rtl
+  Module          : mesh_torus_next_router_addr_predictor
+  FileName        : ./../../rtl/src_noc/./mesh_torus_routting.v
+  LineNumber      : 350
+  Statement       :         WEST = 3'd3,  
+  Exp_Size        : 2
+  ExprSize        : 3
+  RTL_EXPRESSION  : 3'd3
+
+  -----------------------------------------------------------------------------
+  UndrivenOutPort-ML  (7 errors/0 waived/4 compressed)
+  -----------------------------------------------------------------------------
+  Tag            : UndrivenOutPort-ML
+  Description    : Detected undriven output port [Signal]
+  Violation      : Lint:469
+  Goal           : lint_rtl
+  Module         : router_top
+  FileName       : ./../../rtl/src_noc/./router_top.sv
+  LineNumber     : 50
+  Statement      :     output smartflit_chanel_t chan_out [P-1 : 0];
+  Signal         : chan_out[0].smart_chanel.dest_e_addr
+  SignalRange    : 0-1
+  -----------------------------------------------------------------------------
+  Tag            : UndrivenOutPort-ML
+  Description    : Detected undriven output port [Signal]
+  Violation      : Lint:471
+  Goal           : lint_rtl
+  Module         : router_top
+  FileName       : ./../../rtl/src_noc/./router_top.sv
+  LineNumber     : 50
+  Statement      :     output smartflit_chanel_t chan_out [P-1 : 0];
+  Signal         : chan_out[0].smart_chanel.ovc[0]
+  -----------------------------------------------------------------------------
+  Tag            : UndrivenOutPort-ML
+  Description    : Detected undriven output port [Signal]
+  Violation      : Lint:465
+  Goal           : lint_rtl
+  Module         : router_top
+  FileName       : ./../../rtl/src_noc/./router_top.sv
+  LineNumber     : 50
+  Statement      :     output smartflit_chanel_t chan_out [P-1 : 0];
+  Signal         : chan_out[0].smart_chanel.bypassed_num
+  SignalRange    : 0-1
+  -----------------------------------------------------------------------------
+  Tag            : UndrivenOutPort-ML
+  Description    : Detected undriven output port [Signal]
+  Violation      : Lint:467
+  Goal           : lint_rtl
+  Module         : router_top
+  FileName       : ./../../rtl/src_noc/./router_top.sv
+  LineNumber     : 50
+  Statement      :     output smartflit_chanel_t chan_out [P-1 : 0];
+  Signal         : chan_out[0].smart_chanel.flit_in_bypassed
+  -----------------------------------------------------------------------------
+  Tag            : UndrivenOutPort-ML
+  Description    : Detected undriven output port [Signal]
+  Violation      : Lint:468
+  Goal           : lint_rtl
+  Module         : router_top
+  FileName       : ./../../rtl/src_noc/./router_top.sv
+  LineNumber     : 50
+  Statement      :     output smartflit_chanel_t chan_out [P-1 : 0];
+  Signal         : chan_out[0].smart_chanel.hdr_flit
+  -----------------------------------------------------------------------------
+  Tag            : UndrivenOutPort-ML
+  Description    : Detected undriven output port [Signal]
+  Violation      : Lint:475
+  Goal           : lint_rtl
+  Module         : router_top
+  FileName       : ./../../rtl/src_noc/./router_top.sv
+  LineNumber     : 52
+  Statement      :     output router_event_t router_event [P-1 : 0];
+  Signal         : router_event[0].flit_in_bypassed
+  -----------------------------------------------------------------------------
+  Tag            : UndrivenOutPort-ML
+  Description    : Detected undriven output port [Signal]
+  Violation      : Lint:472
+  Goal           : lint_rtl
+  Module         : router_top
+  FileName       : ./../../rtl/src_noc/./router_top.sv
+  LineNumber     : 50
+  Statement      :     output smartflit_chanel_t chan_out [P-1 : 0];
+  Signal         : chan_out[0].smart_chanel.requests
+  SignalRange    : 0-2
+
+  -----------------------------------------------------------------------------
+  UseSVAlways-ML  (11 errors/0 waived)
+  -----------------------------------------------------------------------------
+  Tag           : UseSVAlways-ML
+  Description   : Preferably use always_comb construct for procedural combinatorial code '[NodeName]'
+  Violation     : Lint:4834
+  Goal          : lint_rtl
+  Module        : smart_credit_manage_per_vc
+  FileName      : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber    : 757
+  Statement     :     always @(*) begin 
+  NodeName      : smart_credit_manage_per_vc.counter_next
+  -----------------------------------------------------------------------------
+  Tag           : UseSVAlways-ML
+  Description   : Preferably use always_comb construct for procedural combinatorial code '[NodeName]'
+  Violation     : Lint:3857
+  Goal          : lint_rtl
+  Module        : header_flit_update_lk_route_ovc
+  FileName      : ./../../rtl/src_noc/./header_flit.sv
+  LineNumber    : 301
+  Statement     :     always @(*)begin 
+  NodeName      : header_flit_update_lk_route_ovc.flit_out[DST_P_MSB:DST_P_LSB] 
+  -----------------------------------------------------------------------------
+  Tag           : UseSVAlways-ML
+  Description   : Preferably use always_comb construct for procedural combinatorial code '[NodeName]'
+  Violation     : Lint:3673
+  Goal          : lint_rtl
+  Module        : router_top
+  FileName      : ./../../rtl/src_noc/./router_top.sv
+  LineNumber    : 236
+  Statement     :                 always @(*) begin
+  NodeName      : router_top.chan_out[i].flit_chanel.flit_wr
+  -----------------------------------------------------------------------------
+  Tag           : UseSVAlways-ML
+  Description   : Preferably use always_comb construct for procedural combinatorial code '[NodeName]'
+  Violation     : Lint:4752
+  Goal          : lint_rtl
+  Module        : smart_bypass_chanels
+  FileName      : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber    : 361
+  Statement     :             always @(*) begin 
+  NodeName      : smart_bypass_chanels.smart_chanel_shifted[i].bypassed_num
+  -----------------------------------------------------------------------------
+  Tag           : UseSVAlways-ML
+  Description   : Preferably use always_comb construct for procedural combinatorial code '[NodeName]'
+  Violation     : Lint:3843
+  Goal          : lint_rtl
+  Module        : flit_buffer
+  FileName      : ./../../rtl/src_noc/./flit_buffer.sv
+  LineNumber    : 235
+  Statement     :             always @ (*) begin
+  NodeName      : flit_buffer.depth_next[i]
+  -----------------------------------------------------------------------------
+  Tag           : UseSVAlways-ML
+  Description   : Preferably use always_comb construct for procedural combinatorial code '[NodeName]'
+  Violation     : Lint:4448
+  Goal          : lint_rtl
+  Module        : credit_monitor_per_ovc
+  FileName      : ./../../rtl/src_noc/./output_ports.sv
+  LineNumber    : 429
+  Statement     :     always @(*) begin        
+  NodeName      : credit_monitor_per_ovc.credit_counter_o[(DEPTHw - 1):0] 
+  -----------------------------------------------------------------------------
+  Tag           : UseSVAlways-ML
+  Description   : Preferably use always_comb construct for procedural combinatorial code '[NodeName]'
+  Violation     : Lint:3808
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 545
+  Statement     :             always @ (*) begin
+  NodeName      : input_queue_per_port.ovc_is_assigned_next[i]
+  -----------------------------------------------------------------------------
+  Tag           : UseSVAlways-ML
+  Description   : Preferably use always_comb construct for procedural combinatorial code '[NodeName]'
+  Violation     : Lint:3810
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 377
+  Statement     :     always @ (*)begin 
+  NodeName      : input_queue_per_port.iport_weight_next
+  -----------------------------------------------------------------------------
+  Tag           : UseSVAlways-ML
+  Description   : Preferably use always_comb construct for procedural combinatorial code '[NodeName]'
+  Violation     : Lint:3809
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 557
+  Statement     :             always @(*) begin
+  NodeName      : input_queue_per_port.assigned_ovc_num_next[(((i + 1) * V) - 1):(i * V)] 
+  -----------------------------------------------------------------------------
+  Tag           : UseSVAlways-ML
+  Description   : Preferably use always_comb construct for procedural combinatorial code '[NodeName]'
+  Violation     : Lint:3672
+  Goal          : lint_rtl
+  Module        : router_top
+  FileName      : ./../../rtl/src_noc/./router_top.sv
+  LineNumber    : 222
+  Statement     :                 always @(*) begin
+  NodeName      : router_top.ss_flit_chanel[SS_PORT].flit[DST_P_MSB:DST_P_LSB] 
+  -----------------------------------------------------------------------------
+  Tag           : UseSVAlways-ML
+  Description   : Preferably use always_comb construct for procedural combinatorial code '[NodeName]'
+  Violation     : Lint:4833
+  Goal          : lint_rtl
+  Module        : smart_validity_check_per_ivc
+  FileName      : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber    : 494
+  Statement     :     always @(*) begin 
+  NodeName      : smart_validity_check_per_ivc.smart_ivc_granted_ovc_num_o[IVC_NUM]
+
+  -----------------------------------------------------------------------------
+  UseSVAlways-ML  (2 errors/0 waived)
+  -----------------------------------------------------------------------------
+  Tag           : UseSVAlways-ML
+  Description   : Preferably use always_ff construct for sequential logic inferring flip-flop '[NodeName]'
+  Violation     : Lint:4648
+  Goal          : lint_rtl
+  Module        : credit_release_gen
+  FileName      : ./../../rtl/src_noc/./router_two_stage.sv
+  LineNumber    : 678
+  Statement     :     always @ (`pronoc_clk_reset_edge )begin 
+  NodeName      : credit_release_gen.credit_out
+  -----------------------------------------------------------------------------
+  Tag           : UseSVAlways-ML
+  Description   : Preferably use always_ff construct for sequential logic inferring flip-flop '[NodeName]'
+  Violation     : Lint:3842
+  Goal          : lint_rtl
+  Module        : flit_buffer
+  FileName      : ./../../rtl/src_noc/./flit_buffer.sv
+  LineNumber    : 227
+  Statement     :             always @(posedge clk) begin
+  NodeName      : flit_buffer.tail_fifo[i][wr_ptr[i]]
+
+  -----------------------------------------------------------------------------
+  W121  (6 errors/0 waived)
+  -----------------------------------------------------------------------------
+  Tag                : W121
+  Description        : Name '[NodeName]' is not unique - may shadow another variable(Previously used at line no. [CulpritLineNumber] in [CulpritFileName])
+  Violation          : Lint:4639
+  Goal               : lint_rtl
+  Module             : crossbar
+  FileName           : ./../../rtl/src_noc/./crossbar.v
+  LineNumber         : 84
+  Statement          :         for(j=0;j<P;j=j+1)begin : P_ 
+  NodeName           : P_
+  CulpritLineNumber  : 82
+  CulpritFileName    : ./../../rtl/src_noc/./crossbar.v
+  MultiLine          :         for(j=0;j<P;j=j+1)begin : P_ (./../../rtl/src_noc/./crossbar.v:84)
+  MultiLine          :     for(i=0;i<P;i=i+1) begin : P_(./../../rtl/src_noc/./crossbar.v:82)
+  -----------------------------------------------------------------------------
+  Tag                : W121
+  Description        : Name '[NodeName]' is not unique - may shadow another variable(Previously used at line no. [CulpritLineNumber] in [CulpritFileName])
+  Violation          : Lint:4641
+  Goal               : lint_rtl
+  Module             : crossbar
+  FileName           : ./../../rtl/src_noc/./crossbar.v
+  LineNumber         : 95
+  Statement          :             end else begin : slp
+  NodeName           : slp
+  CulpritLineNumber  : 151
+  CulpritFileName    : ./../../rtl/src_noc/./crossbar.v
+  MultiLine          :             end else begin : slp(./../../rtl/src_noc/./crossbar.v:95)
+  MultiLine          :         end else begin :slp (./../../rtl/src_noc/./crossbar.v:151)
+  -----------------------------------------------------------------------------
+  Tag                : W121
+  Description        : Name '[NodeName]' is not unique - may shadow another variable(Previously used at line no. [CulpritLineNumber] in [CulpritFileName])
+  Violation          : Lint:4640
+  Goal               : lint_rtl
+  Module             : crossbar
+  FileName           : ./../../rtl/src_noc/./crossbar.v
+  LineNumber         : 85
+  Statement          :             if(SELF_LOOP_EN == 0) begin : nslp
+  NodeName           : nslp
+  CulpritLineNumber  : 143
+  CulpritFileName    : ./../../rtl/src_noc/./crossbar.v
+  MultiLine          :             if(SELF_LOOP_EN == 0) begin : nslp(./../../rtl/src_noc/./crossbar.v:85)
+  MultiLine          :         if(SELF_LOOP_EN == 0) begin : nslp(./../../rtl/src_noc/./crossbar.v:143)
+  -----------------------------------------------------------------------------
+  Tag                : W121
+  Description        : Name '[NodeName]' is not unique - may shadow another variable(Previously used at line no. [CulpritLineNumber] in [CulpritFileName])
+  Violation          : Lint:4607
+  Goal               : lint_rtl
+  Module             : nonspec_sw_alloc
+  FileName           : ./../../rtl/src_noc/./comb_nonspec.sv
+  LineNumber         : 561
+  Statement          :         for(j=0;j<P;    j=j+1)begin: P_
+  NodeName           : P_
+  CulpritLineNumber  : 493
+  CulpritFileName    : ./../../rtl/src_noc/./comb_nonspec.sv
+  MultiLine          :         for(j=0;j<P;    j=j+1)begin: P_(./../../rtl/src_noc/./comb_nonspec.sv:561)
+  MultiLine          :     for(i=0;i< P;i=i+1) begin : P_(./../../rtl/src_noc/./comb_nonspec.sv:493)
+  -----------------------------------------------------------------------------
+  Tag                : W121
+  Description        : Name '[NodeName]' is not unique - may shadow another variable(Previously used at line no. [CulpritLineNumber] in [CulpritFileName])
+  Violation          : Lint:4616
+  Goal               : lint_rtl
+  Module             : custom_or
+  FileName           : ./../../rtl/src_noc/./../main_comp.v
+  LineNumber         : 183
+  Statement          :         for (j=0;j<IN_NUM;j=j+1) begin: sep_loop
+  NodeName           : sep_loop
+  CulpritLineNumber  : 182
+  CulpritFileName    : ./../../rtl/src_noc/./../main_comp.v
+  MultiLine          :         for (j=0;j<IN_NUM;j=j+1) begin: sep_loop(./../../rtl/src_noc/./../main_comp.v:183)
+  MultiLine          :     for (i=0;i<OUT_WIDTH;i=i+1) begin: sep_loop(./../../rtl/src_noc/./../main_comp.v:182)
+  -----------------------------------------------------------------------------
+  Tag                : W121
+  Description        : Name '[NodeName]' is not unique - may shadow another variable(Previously used at line no. [CulpritLineNumber] in [CulpritFileName])
+  Violation          : Lint:3674
+  Goal               : lint_rtl
+  Module             : router_two_stage
+  FileName           : ./../../rtl/src_noc/./router_two_stage.sv
+  LineNumber         : 161
+  Statement          :     function automatic int get_enp_num(input int i);
+  NodeName           : i
+  CulpritLineNumber  : 190
+  CulpritFileName    : ./../../rtl/src_noc/./router_two_stage.sv
+  MultiLine          :     function automatic int get_enp_num(input int i);(./../../rtl/src_noc/./router_two_stage.sv:161)
+  MultiLine          :     genvar i,j;(./../../rtl/src_noc/./router_two_stage.sv:190)
+
+  -----------------------------------------------------------------------------
+  W123  (36 errors/0 waived)
+  -----------------------------------------------------------------------------
+  Tag           : W123
+  Description   : Variable '[VariableName]'[ExprSize] read but never set.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5569
+  Goal          : lint_rtl
+  Module        : router_top
+  FileName      : ./../../rtl/src_noc/./router_top.sv
+  LineNumber    : 149
+  Statement     :             .smart_chanel_in(smart_chanel_in),
+  VariableName  : smart_chanel_in[0].dest_e_addr[1:0]
+  ExprSize      : 
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[3].the_router @router_top
+  -----------------------------------------------------------------------------
+  Tag           : W123
+  Description   : Variable '[VariableName]'[ExprSize] read but never set.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:4877
+  Goal          : lint_rtl
+  Module        : router_top
+  FileName      : ./../../rtl/src_noc/./router_top.sv
+  LineNumber    : 149
+  Statement     :             .smart_chanel_in(smart_chanel_in),
+  VariableName  : smart_chanel_in[0].dest_e_addr[1:0]
+  ExprSize      : 
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[1].the_router @router_top
+  -----------------------------------------------------------------------------
+  Tag           : W123
+  Description   : Variable '[VariableName]'[ExprSize] read but never set.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:3638
+  Goal          : lint_rtl
+  Module        : router_top
+  FileName      : ./../../rtl/src_noc/./router_top.sv
+  LineNumber    : 149
+  Statement     :             .smart_chanel_in(smart_chanel_in),
+  VariableName  : smart_chanel_in[0].flit_in_bypassed
+  ExprSize      : 
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top
+  -----------------------------------------------------------------------------
+  Tag           : W123
+  Description   : Variable '[VariableName]'[ExprSize] read but never set.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5566
+  Goal          : lint_rtl
+  Module        : router_top
+  FileName      : ./../../rtl/src_noc/./router_top.sv
+  LineNumber    : 178
+  Statement     :                     .neighbors_r_addr_i(neighbors_r_addr),
+  VariableName  : smart.neighbors_r_addr
+  ExprSize      : (2 bits)
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[3].the_router @router_top:\smart 
+  -----------------------------------------------------------------------------
+  Tag           : W123
+  Description   : Variable '[VariableName]'[ExprSize] read but never set.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:3613
+  Goal          : lint_rtl
+  Module        : mesh_torus_noc_top
+  FileName      : ./../../rtl/src_noc/./mesh_torus_noc_top.sv
+  LineNumber    : 71
+  Statement     :                 .router_config_in(router_config_in[RID]),                
+  VariableName  : router_config_in[2].endp_addrs[1:0]
+  ExprSize      : 
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top
+  -----------------------------------------------------------------------------
+  Tag           : W123
+  Description   : Variable '[VariableName]'[ExprSize] read but never set.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:3615
+  Goal          : lint_rtl
+  Module        : mesh_torus_noc_top
+  FileName      : ./../../rtl/src_noc/./mesh_torus_noc_top.sv
+  LineNumber    : 71
+  Statement     :                 .router_config_in(router_config_in[RID]),                
+  VariableName  : router_config_in[1].endp_addrs[1:0]
+  ExprSize      : 
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top
+  -----------------------------------------------------------------------------
+  Tag           : W123
+  Description   : Variable '[VariableName]'[ExprSize] read but never set.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5572
+  Goal          : lint_rtl
+  Module        : router_top
+  FileName      : ./../../rtl/src_noc/./router_top.sv
+  LineNumber    : 149
+  Statement     :             .smart_chanel_in(smart_chanel_in),
+  VariableName  : smart_chanel_in[0].bypassed_num[1:0]
+  ExprSize      : 
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[3].the_router @router_top
+  -----------------------------------------------------------------------------
+  Tag           : W123
+  Description   : Variable '[VariableName]'[ExprSize] read but never set.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:3616
+  Goal          : lint_rtl
+  Module        : mesh_torus_noc_top
+  FileName      : ./../../rtl/src_noc/./mesh_torus_noc_top.sv
+  LineNumber    : 71
+  Statement     :                 .router_config_in(router_config_in[RID]),                
+  VariableName  : router_config_in[1].endp_ids[1:0]
+  ExprSize      : 
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top
+  -----------------------------------------------------------------------------
+  Tag           : W123
+  Description   : Variable '[VariableName]'[ExprSize] read but never set.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:3612
+  Goal          : lint_rtl
+  Module        : mesh_torus_noc_top
+  FileName      : ./../../rtl/src_noc/./mesh_torus_noc_top.sv
+  LineNumber    : 71
+  Statement     :                 .router_config_in(router_config_in[RID]),                
+  VariableName  : router_config_in[3].endp_ids[1:0]
+  ExprSize      : 
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top
+  -----------------------------------------------------------------------------
+  Tag           : W123
+  Description   : Variable '[VariableName]'[ExprSize] read but never set.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:3634
+  Goal          : lint_rtl
+  Module        : router_top
+  FileName      : ./../../rtl/src_noc/./router_top.sv
+  LineNumber    : 149
+  Statement     :             .smart_chanel_in(smart_chanel_in),
+  VariableName  : smart_chanel_in[0].requests[2:0]
+  ExprSize      : 
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top
+  -----------------------------------------------------------------------------
+  Tag           : W123
+  Description   : Variable '[VariableName]'[ExprSize] read but never set.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:3614
+  Goal          : lint_rtl
+  Module        : mesh_torus_noc_top
+  FileName      : ./../../rtl/src_noc/./mesh_torus_noc_top.sv
+  LineNumber    : 71
+  Statement     :                 .router_config_in(router_config_in[RID]),                
+  VariableName  : router_config_in[2].endp_ids[1:0]
+  ExprSize      : 
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top
+  -----------------------------------------------------------------------------
+  Tag           : W123
+  Description   : Variable '[VariableName]'[ExprSize] read but never set.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5222
+  Goal          : lint_rtl
+  Module        : router_top
+  FileName      : ./../../rtl/src_noc/./router_top.sv
+  LineNumber    : 149
+  Statement     :             .smart_chanel_in(smart_chanel_in),
+  VariableName  : smart_chanel_in[0].ovc[0]
+  ExprSize      : 
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[2].the_router @router_top
+  -----------------------------------------------------------------------------
+  Tag           : W123
+  Description   : Variable '[VariableName]'[ExprSize] read but never set.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:3637
+  Goal          : lint_rtl
+  Module        : router_top
+  FileName      : ./../../rtl/src_noc/./router_top.sv
+  LineNumber    : 149
+  Statement     :             .smart_chanel_in(smart_chanel_in),
+  VariableName  : smart_chanel_in[0].hdr_flit
+  ExprSize      : 
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top
+  -----------------------------------------------------------------------------
+  Tag           : W123
+  Description   : Variable '[VariableName]'[ExprSize] read but never set.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5224
+  Goal          : lint_rtl
+  Module        : router_top
+  FileName      : ./../../rtl/src_noc/./router_top.sv
+  LineNumber    : 149
+  Statement     :             .smart_chanel_in(smart_chanel_in),
+  VariableName  : smart_chanel_in[0].hdr_flit
+  ExprSize      : 
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[2].the_router @router_top
+  -----------------------------------------------------------------------------
+  Tag           : W123
+  Description   : Variable '[VariableName]'[ExprSize] read but never set.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5225
+  Goal          : lint_rtl
+  Module        : router_top
+  FileName      : ./../../rtl/src_noc/./router_top.sv
+  LineNumber    : 149
+  Statement     :             .smart_chanel_in(smart_chanel_in),
+  VariableName  : smart_chanel_in[0].flit_in_bypassed
+  ExprSize      : 
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[2].the_router @router_top
+  -----------------------------------------------------------------------------
+  Tag           : W123
+  Description   : Variable '[VariableName]'[ExprSize] read but never set.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:3639
+  Goal          : lint_rtl
+  Module        : router_top
+  FileName      : ./../../rtl/src_noc/./router_top.sv
+  LineNumber    : 149
+  Statement     :             .smart_chanel_in(smart_chanel_in),
+  VariableName  : smart_chanel_in[0].bypassed_num[1:0]
+  ExprSize      : 
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top
+  -----------------------------------------------------------------------------
+  Tag           : W123
+  Description   : Variable '[VariableName]'[ExprSize] read but never set.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:4876
+  Goal          : lint_rtl
+  Module        : router_top
+  FileName      : ./../../rtl/src_noc/./router_top.sv
+  LineNumber    : 149
+  Statement     :             .smart_chanel_in(smart_chanel_in),
+  VariableName  : smart_chanel_in[0].ovc[0]
+  ExprSize      : 
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[1].the_router @router_top
+  -----------------------------------------------------------------------------
+  Tag           : W123
+  Description   : Variable '[VariableName]'[ExprSize] read but never set.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:3635
+  Goal          : lint_rtl
+  Module        : router_top
+  FileName      : ./../../rtl/src_noc/./router_top.sv
+  LineNumber    : 149
+  Statement     :             .smart_chanel_in(smart_chanel_in),
+  VariableName  : smart_chanel_in[0].ovc[0]
+  ExprSize      : 
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top
+  -----------------------------------------------------------------------------
+  Tag           : W123
+  Description   : Variable '[VariableName]'[ExprSize] read but never set.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:4875
+  Goal          : lint_rtl
+  Module        : router_top
+  FileName      : ./../../rtl/src_noc/./router_top.sv
+  LineNumber    : 149
+  Statement     :             .smart_chanel_in(smart_chanel_in),
+  VariableName  : smart_chanel_in[0].requests[2:0]
+  ExprSize      : 
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[1].the_router @router_top
+  -----------------------------------------------------------------------------
+  Tag           : W123
+  Description   : Variable '[VariableName]'[ExprSize] read but never set.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:4880
+  Goal          : lint_rtl
+  Module        : router_top
+  FileName      : ./../../rtl/src_noc/./router_top.sv
+  LineNumber    : 149
+  Statement     :             .smart_chanel_in(smart_chanel_in),
+  VariableName  : smart_chanel_in[0].bypassed_num[1:0]
+  ExprSize      : 
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[1].the_router @router_top
+  -----------------------------------------------------------------------------
+  Tag           : W123
+  Description   : Variable '[VariableName]'[ExprSize] read but never set.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:3617
+  Goal          : lint_rtl
+  Module        : mesh_torus_noc_top
+  FileName      : ./../../rtl/src_noc/./mesh_torus_noc_top.sv
+  LineNumber    : 71
+  Statement     :                 .router_config_in(router_config_in[RID]),                
+  VariableName  : router_config_in[0].endp_addrs[1:0]
+  ExprSize      : 
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top
+  -----------------------------------------------------------------------------
+  Tag           : W123
+  Description   : Variable '[VariableName]'[ExprSize] read but never set.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5568
+  Goal          : lint_rtl
+  Module        : router_top
+  FileName      : ./../../rtl/src_noc/./router_top.sv
+  LineNumber    : 149
+  Statement     :             .smart_chanel_in(smart_chanel_in),
+  VariableName  : smart_chanel_in[0].ovc[0]
+  ExprSize      : 
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[3].the_router @router_top
+  -----------------------------------------------------------------------------
+  Tag           : W123
+  Description   : Variable '[VariableName]'[ExprSize] read but never set.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:3611
+  Goal          : lint_rtl
+  Module        : mesh_torus_noc_top
+  FileName      : ./../../rtl/src_noc/./mesh_torus_noc_top.sv
+  LineNumber    : 71
+  Statement     :                 .router_config_in(router_config_in[RID]),                
+  VariableName  : router_config_in[3].endp_addrs[1:0]
+  ExprSize      : 
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top
+  -----------------------------------------------------------------------------
+  Tag           : W123
+  Description   : Variable '[VariableName]'[ExprSize] read but never set.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:3618
+  Goal          : lint_rtl
+  Module        : mesh_torus_noc_top
+  FileName      : ./../../rtl/src_noc/./mesh_torus_noc_top.sv
+  LineNumber    : 71
+  Statement     :                 .router_config_in(router_config_in[RID]),                
+  VariableName  : router_config_in[0].endp_ids[1:0]
+  ExprSize      : 
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top
+  -----------------------------------------------------------------------------
+  Tag           : W123
+  Description   : Variable '[VariableName]'[ExprSize] read but never set.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5220
+  Goal          : lint_rtl
+  Module        : router_top
+  FileName      : ./../../rtl/src_noc/./router_top.sv
+  LineNumber    : 178
+  Statement     :                     .neighbors_r_addr_i(neighbors_r_addr),
+  VariableName  : smart.neighbors_r_addr
+  ExprSize      : (2 bits)
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[2].the_router @router_top:\smart 
+  -----------------------------------------------------------------------------
+  Tag           : W123
+  Description   : Variable '[VariableName]'[ExprSize] read but never set.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:4874
+  Goal          : lint_rtl
+  Module        : router_top
+  FileName      : ./../../rtl/src_noc/./router_top.sv
+  LineNumber    : 178
+  Statement     :                     .neighbors_r_addr_i(neighbors_r_addr),
+  VariableName  : smart.neighbors_r_addr
+  ExprSize      : (2 bits)
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[1].the_router @router_top:\smart 
+  -----------------------------------------------------------------------------
+  Tag           : W123
+  Description   : Variable '[VariableName]'[ExprSize] read but never set.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5223
+  Goal          : lint_rtl
+  Module        : router_top
+  FileName      : ./../../rtl/src_noc/./router_top.sv
+  LineNumber    : 149
+  Statement     :             .smart_chanel_in(smart_chanel_in),
+  VariableName  : smart_chanel_in[0].dest_e_addr[1:0]
+  ExprSize      : 
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[2].the_router @router_top
+  -----------------------------------------------------------------------------
+  Tag           : W123
+  Description   : Variable '[VariableName]'[ExprSize] read but never set.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:4878
+  Goal          : lint_rtl
+  Module        : router_top
+  FileName      : ./../../rtl/src_noc/./router_top.sv
+  LineNumber    : 149
+  Statement     :             .smart_chanel_in(smart_chanel_in),
+  VariableName  : smart_chanel_in[0].hdr_flit
+  ExprSize      : 
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[1].the_router @router_top
+  -----------------------------------------------------------------------------
+  Tag           : W123
+  Description   : Variable '[VariableName]'[ExprSize] read but never set.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5226
+  Goal          : lint_rtl
+  Module        : router_top
+  FileName      : ./../../rtl/src_noc/./router_top.sv
+  LineNumber    : 149
+  Statement     :             .smart_chanel_in(smart_chanel_in),
+  VariableName  : smart_chanel_in[0].bypassed_num[1:0]
+  ExprSize      : 
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[2].the_router @router_top
+  -----------------------------------------------------------------------------
+  Tag           : W123
+  Description   : Variable '[VariableName]'[ExprSize] read but never set.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:3636
+  Goal          : lint_rtl
+  Module        : router_top
+  FileName      : ./../../rtl/src_noc/./router_top.sv
+  LineNumber    : 149
+  Statement     :             .smart_chanel_in(smart_chanel_in),
+  VariableName  : smart_chanel_in[0].dest_e_addr[1:0]
+  ExprSize      : 
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top
+  -----------------------------------------------------------------------------
+  Tag           : W123
+  Description   : Variable '[VariableName]'[ExprSize] read but never set.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5567
+  Goal          : lint_rtl
+  Module        : router_top
+  FileName      : ./../../rtl/src_noc/./router_top.sv
+  LineNumber    : 149
+  Statement     :             .smart_chanel_in(smart_chanel_in),
+  VariableName  : smart_chanel_in[0].requests[2:0]
+  ExprSize      : 
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[3].the_router @router_top
+  -----------------------------------------------------------------------------
+  Tag           : W123
+  Description   : Variable '[VariableName]'[ExprSize] read but never set.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5570
+  Goal          : lint_rtl
+  Module        : router_top
+  FileName      : ./../../rtl/src_noc/./router_top.sv
+  LineNumber    : 149
+  Statement     :             .smart_chanel_in(smart_chanel_in),
+  VariableName  : smart_chanel_in[0].hdr_flit
+  ExprSize      : 
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[3].the_router @router_top
+  -----------------------------------------------------------------------------
+  Tag           : W123
+  Description   : Variable '[VariableName]'[ExprSize] read but never set.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5221
+  Goal          : lint_rtl
+  Module        : router_top
+  FileName      : ./../../rtl/src_noc/./router_top.sv
+  LineNumber    : 149
+  Statement     :             .smart_chanel_in(smart_chanel_in),
+  VariableName  : smart_chanel_in[0].requests[2:0]
+  ExprSize      : 
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[2].the_router @router_top
+  -----------------------------------------------------------------------------
+  Tag           : W123
+  Description   : Variable '[VariableName]'[ExprSize] read but never set.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:3633
+  Goal          : lint_rtl
+  Module        : router_top
+  FileName      : ./../../rtl/src_noc/./router_top.sv
+  LineNumber    : 178
+  Statement     :                     .neighbors_r_addr_i(neighbors_r_addr),
+  VariableName  : smart.neighbors_r_addr
+  ExprSize      : (2 bits)
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:\smart 
+  -----------------------------------------------------------------------------
+  Tag           : W123
+  Description   : Variable '[VariableName]'[ExprSize] read but never set.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:4879
+  Goal          : lint_rtl
+  Module        : router_top
+  FileName      : ./../../rtl/src_noc/./router_top.sv
+  LineNumber    : 149
+  Statement     :             .smart_chanel_in(smart_chanel_in),
+  VariableName  : smart_chanel_in[0].flit_in_bypassed
+  ExprSize      : 
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[1].the_router @router_top
+  -----------------------------------------------------------------------------
+  Tag           : W123
+  Description   : Variable '[VariableName]'[ExprSize] read but never set.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5571
+  Goal          : lint_rtl
+  Module        : router_top
+  FileName      : ./../../rtl/src_noc/./router_top.sv
+  LineNumber    : 149
+  Statement     :             .smart_chanel_in(smart_chanel_in),
+  VariableName  : smart_chanel_in[0].flit_in_bypassed
+  ExprSize      : 
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[3].the_router @router_top
+
+  -----------------------------------------------------------------------------
+  W215  (1 error/0 waived)
+  -----------------------------------------------------------------------------
+  Tag           : W215
+  Description   : Inappropriate bit select for [NodeType] variable: "[VariableName]"
+  Violation     : Lint:3509
+  Goal          : lint_rtl
+  Module        : noc_top
+  FileName      : ./../../rtl/src_noc/./topology_localparam.v
+  LineNumber    : 101
+  Statement     :              if(router_port_num[0]==1'b0) begin //even port num
+  NodeType      : int_bit_sel
+  VariableName  : router_port_num[0]
+
+  -----------------------------------------------------------------------------
+  W416  (3 errors/0 waived)
+  -----------------------------------------------------------------------------
+  Tag            : W416
+  Description    : Return type width '[LHS_Size]' is [RTL_CONDITION] than return value width '[RHS_Size]' in function '[FunctionName]' [Hierarchy: '[HIERARCHY]']
+  Violation      : Lint:5814
+  Goal           : lint_rtl
+  Module         : input_queue_per_port
+  FileName       : ./../../rtl/src_noc/./topology_localparam.v
+  LineNumber     : 76
+  Statement      :             sum_powi = sum_powi + powi( x, i );
+  LHS_Size       : 32
+  RTL_CONDITION  : less
+  RHS_Size       : 33
+  FunctionName   : sum_powi
+  HIERARCHY      : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[3].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[2].the_input_queue_per_port @input_queue_per_port:sum_powi
+  -----------------------------------------------------------------------------
+  Tag            : W416
+  Description    : Return type width '[LHS_Size]' is [RTL_CONDITION] than return value width '[RHS_Size]' in function '[FunctionName]' [Hierarchy: '[HIERARCHY]']
+  Violation      : Lint:5815
+  Goal           : lint_rtl
+  Module         : input_queue_per_port
+  FileName       : ./../../rtl/src_noc/./topology_localparam.v
+  LineNumber     : 406
+  Statement      :             fmesh_addrencode = ( p<<(NXw+NYw) | (y<<NXw) | x);
+  LHS_Size       : 32
+  RTL_CONDITION  : less
+  RHS_Size       : 36
+  FunctionName   : fmesh_addrencode
+  HIERARCHY      : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[3].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[2].the_input_queue_per_port @input_queue_per_port:fmesh_addrencode
+  -----------------------------------------------------------------------------
+  Tag            : W416
+  Description    : Return type width '[LHS_Size]' is [RTL_CONDITION] than return value width '[RHS_Size]' in function '[FunctionName]' [Hierarchy: '[HIERARCHY]']
+  Violation      : Lint:5813
+  Goal           : lint_rtl
+  Module         : input_queue_per_port
+  FileName       : ./../../rtl/src_noc/./topology_localparam.v
+  LineNumber     : 65
+  Statement      :             powi=powi * x;
+  LHS_Size       : 32
+  RTL_CONDITION  : less
+  RHS_Size       : 64
+  FunctionName   : powi
+  HIERARCHY      : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[3].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[2].the_input_queue_per_port @input_queue_per_port:powi
+
+  -----------------------------------------------------------------------------
+  W504  (1 error/0 waived)
+  -----------------------------------------------------------------------------
+  Tag            : W504
+  Description    : Integer [Value_Name] is used in port expression of port [Mod_Port_Name]
+  Violation      : Lint:3811
+  Goal           : lint_rtl
+  Module         : pronoc_register
+  FileName       : ./../../rtl/src_noc/./../main_comp.v
+  LineNumber     : 42
+  Statement      :     )reg1( 
+  Value_Name     : 1
+  Mod_Port_Name  : reset_to
+
+  -----------------------------------------------------------------------------
+  ConstName  (95 warnings/0 waived)
+  -----------------------------------------------------------------------------
+  Tag           : ConstName
+  Description   : Constant '[CValue]' does not follow recommended naming convention
+  Violation     : Lint:2929
+  Goal          : lint_rtl
+  Module        : nonspec_sw_alloc
+  FileName      : ./../../rtl/src_noc/./comb_nonspec.sv
+  LineNumber    : 431
+  Statement     :     parameter SELF_LOOP_EN=0
+  CValue        : SELF_LOOP_EN
+  -----------------------------------------------------------------------------
+  Tag           : ConstName
+  Description   : Constant '[CValue]' does not follow recommended naming convention
+  Violation     : Lint:2945
+  Goal          : lint_rtl
+  Module        : destp_generator
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 1101
+  Statement     :     parameter CAST_TYPE = "UNICAST"
+  CValue        : CAST_TYPE
+  -----------------------------------------------------------------------------
+  Tag           : ConstName
+  Description   : Constant '[CValue]' does not follow recommended naming convention
+  Violation     : Lint:2928
+  Goal          : lint_rtl
+  Module        : nonspec_sw_alloc
+  FileName      : ./../../rtl/src_noc/./comb_nonspec.sv
+  LineNumber    : 430
+  Statement     :     parameter MIN_PCK_SIZE=2, //minimum packet size in flits. The minimum value is 1.
+  CValue        : MIN_PCK_SIZE
+  -----------------------------------------------------------------------------
+  Tag           : ConstName
+  Description   : Constant '[CValue]' does not follow recommended naming convention
+  Violation     : Lint:2967
+  Goal          : lint_rtl
+  Module        : conventional_routing
+  FileName      : ./../../rtl/src_noc/./routing.v
+  LineNumber    : 34
+  Statement     :     parameter ROUTE_TYPE        = "DETERMINISTIC",
+  CValue        : ROUTE_TYPE
+  -----------------------------------------------------------------------------
+  Tag           : ConstName
+  Description   : Constant '[CValue]' does not follow recommended naming convention
+  Violation     : Lint:3001
+  Goal          : lint_rtl
+  Module        : line_ring_destp_decoder
+  FileName      : ./../../rtl/src_noc/./mesh_torus.sv
+  LineNumber    : 1295
+  Statement     :     parameter ELw=1,
+  CValue        : ELw
+  -----------------------------------------------------------------------------
+  Tag           : ConstName
+  Description   : Constant '[CValue]' does not follow recommended naming convention
+  Violation     : Lint:2935
+  Goal          : lint_rtl
+  Module        : vc_alloc_request_gen_determinstic
+  FileName      : ./../../rtl/src_noc/./inout_ports.sv
+  LineNumber    : 605
+  Statement     :     parameter SELF_LOOP_EN=0,
+  CValue        : SELF_LOOP_EN
+  -----------------------------------------------------------------------------
+  Tag           : ConstName
+  Description   : Constant '[CValue]' does not follow recommended naming convention
+  Violation     : Lint:2940
+  Goal          : lint_rtl
+  Module        : destp_generator
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 1092
+  Statement     :     parameter ROUTE_TYPE="DETERMINISTIC",
+  CValue        : ROUTE_TYPE
+  -----------------------------------------------------------------------------
+  Tag           : ConstName
+  Description   : Constant '[CValue]' does not follow recommended naming convention
+  Violation     : Lint:2992
+  Goal          : lint_rtl
+  Module        : mesh_tori_endp_addr_decode
+  FileName      : ./../../rtl/src_noc/./mesh_torus.sv
+  LineNumber    : 933
+  Statement     :     parameter EAw=9
+  CValue        : EAw
+  -----------------------------------------------------------------------------
+  Tag           : ConstName
+  Description   : Constant '[CValue]' does not follow recommended naming convention
+  Violation     : Lint:2960
+  Goal          : lint_rtl
+  Module        : congestion_out_gen
+  FileName      : ./../../rtl/src_noc/./congestion_analyzer.v
+  LineNumber    : 949
+  Statement     :     parameter ROUTE_TYPE ="ADAPTIVE", 
+  CValue        : ROUTE_TYPE
+  -----------------------------------------------------------------------------
+  Tag           : ConstName
+  Description   : Constant '[CValue]' does not follow recommended naming convention
+  Violation     : Lint:2949
+  Goal          : lint_rtl
+  Module        : mesh_torus_conventional_routing
+  FileName      : ./../../rtl/src_noc/./mesh_torus_routting.v
+  LineNumber    : 599
+  Statement     :     parameter ROUTE_NAME = "DOR",
+  CValue        : ROUTE_NAME
+  -----------------------------------------------------------------------------
+  Tag           : ConstName
+  Description   : Constant '[CValue]' does not follow recommended naming convention
+  Violation     : Lint:2915
+  Goal          : lint_rtl
+  Module        : one_hot_demux
+  FileName      : ./../../rtl/src_noc/./../main_comp.v
+  LineNumber    : 148
+  Statement     :     parameter OUT_WIDTH=IN_WIDTH*SEL_WIDTH
+  CValue        : OUT_WIDTH
+  -----------------------------------------------------------------------------
+  Tag           : ConstName
+  Description   : Constant '[CValue]' does not follow recommended naming convention
+  Violation     : Lint:2988
+  Goal          : lint_rtl
+  Module        : mesh_torus_mask_non_assignable_destport
+  FileName      : ./../../rtl/src_noc/./mesh_torus.sv
+  LineNumber    : 225
+  Statement     :     parameter ROUTE_NAME="DOR",
+  CValue        : ROUTE_NAME
+  -----------------------------------------------------------------------------
+  Tag           : ConstName
+  Description   : Constant '[CValue]' does not follow recommended naming convention
+  Violation     : Lint:2957
+  Goal          : lint_rtl
+  Module        : port_pre_sel_gen
+  FileName      : ./../../rtl/src_noc/./congestion_analyzer.v
+  LineNumber    : 332
+  Statement     :     parameter CONGw=2,
+  CValue        : CONGw
+  -----------------------------------------------------------------------------
+  Tag           : ConstName
+  Description   : Constant '[CValue]' does not follow recommended naming convention
+  Violation     : Lint:2952
+  Goal          : lint_rtl
+  Module        : check_straight_oport
+  FileName      : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber    : 379
+  Statement     :     parameter SS_PORT_LOC = 1
+  CValue        : SS_PORT_LOC
+  -----------------------------------------------------------------------------
+  Tag           : ConstName
+  Description   : Constant '[CValue]' does not follow recommended naming convention
+  Violation     : Lint:3002
+  Goal          : lint_rtl
+  Module        : line_ring_destp_decoder
+  FileName      : ./../../rtl/src_noc/./mesh_torus.sv
+  LineNumber    : 1296
+  Statement     :     parameter PPSw=4,
+  CValue        : PPSw
+  -----------------------------------------------------------------------------
+  Tag           : ConstName
+  Description   : Constant '[CValue]' does not follow recommended naming convention
+  Violation     : Lint:2920
+  Goal          : lint_rtl
+  Module        : one_hot_to_bin
+  FileName      : ./../../rtl/src_noc/./../main_comp.v
+  LineNumber    : 257
+  Statement     :     parameter BIN_WIDTH = (ONE_HOT_WIDTH>1)? log2(ONE_HOT_WIDTH):1
+  CValue        : BIN_WIDTH
+  -----------------------------------------------------------------------------
+  Tag           : ConstName
+  Description   : Constant '[CValue]' does not follow recommended naming convention
+  Violation     : Lint:2934
+  Goal          : lint_rtl
+  Module        : inout_ports
+  FileName      : ./../../rtl/src_noc/./inout_ports.sv
+  LineNumber    : 30
+  Statement     :     parameter ROUTER_ID=0,
+  CValue        : ROUTER_ID
+  -----------------------------------------------------------------------------
+  Tag           : ConstName
+  Description   : Constant '[CValue]' does not follow recommended naming convention
+  Violation     : Lint:2974
+  Goal          : lint_rtl
+  Module        : look_ahead_routing
+  FileName      : ./../../rtl/src_noc/./routing.v
+  LineNumber    : 239
+  Statement     :     parameter EAw = 3,
+  CValue        : EAw
+  -----------------------------------------------------------------------------
+  Tag           : ConstName
+  Description   : Constant '[CValue]' does not follow recommended naming convention
+  Violation     : Lint:2913
+  Goal          : lint_rtl
+  Module        : one_hot_mux
+  FileName      : ./../../rtl/src_noc/./../main_comp.v
+  LineNumber    : 115
+  Statement     :     parameter   OUT_WIDTH = IN_WIDTH/SEL_WIDTH
+  CValue        : OUT_WIDTH
+  -----------------------------------------------------------------------------
+  Tag           : ConstName
+  Description   : Constant '[CValue]' does not follow recommended naming convention
+  Violation     : Lint:2989
+  Goal          : lint_rtl
+  Module        : mesh_torus_mask_non_assignable_destport
+  FileName      : ./../../rtl/src_noc/./mesh_torus.sv
+  LineNumber    : 228
+  Statement     :     parameter SELF_LOOP_EN=0
+  CValue        : SELF_LOOP_EN
+  -----------------------------------------------------------------------------
+  Tag           : ConstName
+  Description   : Constant '[CValue]' does not follow recommended naming convention
+  Violation     : Lint:2966
+  Goal          : lint_rtl
+  Module        : conventional_routing
+  FileName      : ./../../rtl/src_noc/./routing.v
+  LineNumber    : 33
+  Statement     :     parameter ROUTE_NAME        = "DOR",
+  CValue        : ROUTE_NAME
+  -----------------------------------------------------------------------------
+  Tag           : ConstName
+  Description   : Constant '[CValue]' does not follow recommended naming convention
+  Violation     : Lint:2947
+  Goal          : lint_rtl
+  Module        : mesh_torus_look_ahead_routing
+  FileName      : ./../../rtl/src_noc/./mesh_torus_routting.v
+  LineNumber    : 14
+  Statement     :     parameter ROUTE_TYPE = "DETERMINISTIC"// "DETERMINISTIC", "FULL_ADAPTIVE", "PAR_ADAPTIVE"
+  CValue        : ROUTE_TYPE
+  -----------------------------------------------------------------------------
+  Tag           : ConstName
+  Description   : Constant '[CValue]' does not follow recommended naming convention
+  Violation     : Lint:2910
+  Goal          : lint_rtl
+  Module        : noc_top
+  FileName      : ./../../rtl/src_noc/./../main_comp.v
+  LineNumber    : 29
+  Statement     : `define PRONOC_COMMON
+  CValue        : PRONOC_COMMON
+  -----------------------------------------------------------------------------
+  Tag           : ConstName
+  Description   : Constant '[CValue]' does not follow recommended naming convention
+  Violation     : Lint:2986
+  Goal          : lint_rtl
+  Module        : fwft_fifo
+  FileName      : ./../../rtl/src_noc/./flit_buffer.sv
+  LineNumber    : 550
+  Statement     :     parameter MAX_DEPTH = 2,
+  CValue        : MAX_DEPTH
+  -----------------------------------------------------------------------------
+  Tag           : ConstName
+  Description   : Constant '[CValue]' does not follow recommended naming convention
+  Violation     : Lint:2981
+  Goal          : lint_rtl
+  Module        : crossbar
+  FileName      : ./../../rtl/src_noc/./crossbar.v
+  LineNumber    : 33
+  Statement     :     parameter Fw   = 36,
+  CValue        : Fw
+  -----------------------------------------------------------------------------
+  Tag           : ConstName
+  Description   : Constant '[CValue]' does not follow recommended naming convention
+  Violation     : Lint:2975
+  Goal          : lint_rtl
+  Module        : look_ahead_routing
+  FileName      : ./../../rtl/src_noc/./routing.v
+  LineNumber    : 240
+  Statement     :     parameter DAw = 3,
+  CValue        : DAw
+  -----------------------------------------------------------------------------
+  Tag           : ConstName
+  Description   : Constant '[CValue]' does not follow recommended naming convention
+  Violation     : Lint:2965
+  Goal          : lint_rtl
+  Module        : full_ovc_predictor
+  FileName      : ./../../rtl/src_noc/./output_ports.sv
+  LineNumber    : 535
+  Statement     :     parameter SELF_LOOP_EN = 0
+  CValue        : SELF_LOOP_EN
+  -----------------------------------------------------------------------------
+  Tag           : ConstName
+  Description   : Constant '[CValue]' does not follow recommended naming convention
+  Violation     : Lint:2916
+  Goal          : lint_rtl
+  Module        : custom_or
+  FileName      : ./../../rtl/src_noc/./../main_comp.v
+  LineNumber    : 170
+  Statement     :     parameter OUT_WIDTH = 5
+  CValue        : OUT_WIDTH
+  -----------------------------------------------------------------------------
+  Tag           : ConstName
+  Description   : Constant '[CValue]' does not follow recommended naming convention
+  Violation     : Lint:2937
+  Goal          : lint_rtl
+  Module        : input_ports
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 33
+  Statement     :     parameter ROUTER_ID=0,
+  CValue        : ROUTER_ID
+  -----------------------------------------------------------------------------
+  Tag           : ConstName
+  Description   : Constant '[CValue]' does not follow recommended naming convention
+  Violation     : Lint:2938
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 183
+  Statement     :     parameter ROUTER_ID=0,
+  CValue        : ROUTER_ID
+  -----------------------------------------------------------------------------
+  Tag           : ConstName
+  Description   : Constant '[CValue]' does not follow recommended naming convention
+  Violation     : Lint:2969
+  Goal          : lint_rtl
+  Module        : conventional_routing
+  FileName      : ./../../rtl/src_noc/./routing.v
+  LineNumber    : 39
+  Statement     :     parameter EAw               = 3,
+  CValue        : EAw
+  -----------------------------------------------------------------------------
+  Tag           : ConstName
+  Description   : Constant '[CValue]' does not follow recommended naming convention
+  Violation     : Lint:2997
+  Goal          : lint_rtl
+  Module        : mesh_torus_destp_generator
+  FileName      : ./../../rtl/src_noc/./mesh_torus.sv
+  LineNumber    : 1121
+  Statement     :     parameter PPSw=4,
+  CValue        : PPSw
+  -----------------------------------------------------------------------------
+  Tag           : ConstName
+  Description   : Constant '[CValue]' does not follow recommended naming convention
+  Violation     : Lint:2984
+  Goal          : lint_rtl
+  Module        : fifo_ram
+  FileName      : ./../../rtl/src_noc/./flit_buffer.sv
+  LineNumber    : 428
+  Statement     :     parameter ADDR_WIDTH = 8,
+  CValue        : ADDR_WIDTH
+  -----------------------------------------------------------------------------
+  Tag           : ConstName
+  Description   : Constant '[CValue]' does not follow recommended naming convention
+  Violation     : Lint:2987
+  Goal          : lint_rtl
+  Module        : fwft_fifo
+  FileName      : ./../../rtl/src_noc/./flit_buffer.sv
+  LineNumber    : 551
+  Statement     :     parameter IGNORE_SAME_LOC_RD_WR_WARNING="YES" // "YES" , "NO" 
+  CValue        : IGNORE_SAME_LOC_RD_WR_WARNING
+  -----------------------------------------------------------------------------
+  Tag           : ConstName
+  Description   : Constant '[CValue]' does not follow recommended naming convention
+  Violation     : Lint:2978
+  Goal          : lint_rtl
+  Module        : look_ahead_routing
+  FileName      : ./../../rtl/src_noc/./routing.v
+  LineNumber    : 245
+  Statement     :     parameter ROUTE_TYPE="DETERMINISTIC"// "DETERMINISTIC", "FULL_ADAPTIVE", "PAR_ADAPTIVE"
+  CValue        : ROUTE_TYPE
+  -----------------------------------------------------------------------------
+  Tag           : ConstName
+  Description   : Constant '[CValue]' does not follow recommended naming convention
+  Violation     : Lint:2922
+  Goal          : lint_rtl
+  Module        : arbiter
+  FileName      : ./../../rtl/src_noc/./../arbiter.v
+  LineNumber    : 38
+  Statement     :     parameter    ARBITER_WIDTH    =8
+  CValue        : ARBITER_WIDTH
+  -----------------------------------------------------------------------------
+  Tag           : ConstName
+  Description   : Constant '[CValue]' does not follow recommended naming convention
+  Violation     : Lint:2936
+  Goal          : lint_rtl
+  Module        : vc_alloc_request_gen_determinstic
+  FileName      : ./../../rtl/src_noc/./inout_ports.sv
+  LineNumber    : 606
+  Statement     :     parameter CAST_TYPE = "UNICAST" 
+  CValue        : CAST_TYPE
+  -----------------------------------------------------------------------------
+  Tag           : ConstName
+  Description   : Constant '[CValue]' does not follow recommended naming convention
+  Violation     : Lint:2991
+  Goal          : lint_rtl
+  Module        : mesh_tori_router_addr_decode
+  FileName      : ./../../rtl/src_noc/./mesh_torus.sv
+  LineNumber    : 882
+  Statement     :     parameter RAw=6
+  CValue        : RAw
+  -----------------------------------------------------------------------------
+  Tag           : ConstName
+  Description   : Constant '[CValue]' does not follow recommended naming convention
+  Violation     : Lint:2973
+  Goal          : lint_rtl
+  Module        : look_ahead_routing
+  FileName      : ./../../rtl/src_noc/./routing.v
+  LineNumber    : 238
+  Statement     :     parameter RAw = 3,
+  CValue        : RAw
+  -----------------------------------------------------------------------------
+  Tag           : ConstName
+  Description   : Constant '[CValue]' does not follow recommended naming convention
+  Violation     : Lint:2919
+  Goal          : lint_rtl
+  Module        : one_hot_to_bin
+  FileName      : ./../../rtl/src_noc/./../main_comp.v
+  LineNumber    : 256
+  Statement     :     parameter ONE_HOT_WIDTH = 4,
+  CValue        : ONE_HOT_WIDTH
+  -----------------------------------------------------------------------------
+  Tag           : ConstName
+  Description   : Constant '[CValue]' does not follow recommended naming convention
+  Violation     : Lint:2985
+  Goal          : lint_rtl
+  Module        : fwft_fifo
+  FileName      : ./../../rtl/src_noc/./flit_buffer.sv
+  LineNumber    : 549
+  Statement     :     parameter DATA_WIDTH = 2,
+  CValue        : DATA_WIDTH
+  -----------------------------------------------------------------------------
+  Tag           : ConstName
+  Description   : Constant '[CValue]' does not follow recommended naming convention
+  Violation     : Lint:2925
+  Goal          : lint_rtl
+  Module        : extract_header_flit_info
+  FileName      : ./../../rtl/src_noc/./header_flit.sv
+  LineNumber    : 109
+  Statement     :     parameter DATA_w = 0
+  CValue        : DATA_w
+  -----------------------------------------------------------------------------
+  Tag           : ConstName
+  Description   : Constant '[CValue]' does not follow recommended naming convention
+  Violation     : Lint:2912
+  Goal          : lint_rtl
+  Module        : one_hot_mux
+  FileName      : ./../../rtl/src_noc/./../main_comp.v
+  LineNumber    : 114
+  Statement     :     parameter   SEL_WIDTH = 5, 
+  CValue        : SEL_WIDTH
+  -----------------------------------------------------------------------------
+  Tag           : ConstName
+  Description   : Constant '[CValue]' does not follow recommended naming convention
+  Violation     : Lint:2942
+  Goal          : lint_rtl
+  Module        : destp_generator
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 1097
+  Statement     :     parameter PLw=1,
+  CValue        : PLw
+  -----------------------------------------------------------------------------
+  Tag           : ConstName
+  Description   : Constant '[CValue]' does not follow recommended naming convention
+  Violation     : Lint:2968
+  Goal          : lint_rtl
+  Module        : conventional_routing
+  FileName      : ./../../rtl/src_noc/./routing.v
+  LineNumber    : 38
+  Statement     :     parameter RAw               = 3,
+  CValue        : RAw
+  -----------------------------------------------------------------------------
+  Tag           : ConstName
+  Description   : Constant '[CValue]' does not follow recommended naming convention
+  Violation     : Lint:2924
+  Goal          : lint_rtl
+  Module        : my_one_hot_arbiter
+  FileName      : ./../../rtl/src_noc/./../arbiter.v
+  LineNumber    : 146
+  Statement     :     parameter ARBITER_WIDTH    =4
+  CValue        : ARBITER_WIDTH
+  -----------------------------------------------------------------------------
+  Tag           : ConstName
+  Description   : Constant '[CValue]' does not follow recommended naming convention
+  Violation     : Lint:2948
+  Goal          : lint_rtl
+  Module        : mesh_torus_deterministic_look_ahead_routing
+  FileName      : ./../../rtl/src_noc/./mesh_torus_routting.v
+  LineNumber    : 111
+  Statement     :     parameter ROUTE_NAME="DOR"// "DOR", "TRANC_DOR"
+  CValue        : ROUTE_NAME
+  -----------------------------------------------------------------------------
+  Tag           : ConstName
+  Description   : Constant '[CValue]' does not follow recommended naming convention
+  Violation     : Lint:3004
+  Goal          : lint_rtl
+  Module        : router_top
+  FileName      : ./../../rtl/src_noc/./router_top.sv
+  LineNumber    : 31
+  Statement     :     parameter ROUTER_ID=0,
+  CValue        : ROUTER_ID
+  -----------------------------------------------------------------------------
+  Tag           : ConstName
+  Description   : Constant '[CValue]' does not follow recommended naming convention
+  Violation     : Lint:2972
+  Goal          : lint_rtl
+  Module        : conventional_routing
+  FileName      : ./../../rtl/src_noc/./routing.v
+  LineNumber    : 42
+  Statement     :     parameter LOCATED_IN_NI     = 1 // only needed for mesh and odd-even routing
+  CValue        : LOCATED_IN_NI
+  -----------------------------------------------------------------------------
+  Tag           : ConstName
+  Description   : Constant '[CValue]' does not follow recommended naming convention
+  Violation     : Lint:2976
+  Goal          : lint_rtl
+  Module        : look_ahead_routing
+  FileName      : ./../../rtl/src_noc/./routing.v
+  LineNumber    : 241
+  Statement     :     parameter DSTPw=P-1,
+  CValue        : DSTPw
+  -----------------------------------------------------------------------------
+  Tag           : ConstName
+  Description   : Constant '[CValue]' does not follow recommended naming convention
+  Violation     : Lint:2959
+  Goal          : lint_rtl
+  Module        : port_pre_sel_gen
+  FileName      : ./../../rtl/src_noc/./congestion_analyzer.v
+  LineNumber    : 334
+  Statement     :     parameter [V-1 : 0] ESCAP_VC_MASK= 4'b0001
+  CValue        : ESCAP_VC_MASK
+  -----------------------------------------------------------------------------
+  Tag           : ConstName
+  Description   : Constant '[CValue]' does not follow recommended naming convention
+  Violation     : Lint:2931
+  Goal          : lint_rtl
+  Module        : swa_input_port_arbiter
+  FileName      : ./../../rtl/src_noc/./comb_nonspec.sv
+  LineNumber    : 617
+  Statement     :     parameter ARBITER_TYPE = "WRRA"// RRA, WRRA
+  CValue        : ARBITER_TYPE
+  -----------------------------------------------------------------------------
+  Tag           : ConstName
+  Description   : Constant '[CValue]' does not follow recommended naming convention
+  Violation     : Lint:2951
+  Goal          : lint_rtl
+  Module        : mesh_torus_conventional_routing
+  FileName      : ./../../rtl/src_noc/./mesh_torus_routting.v
+  LineNumber    : 603
+  Statement     :     parameter LOCATED_IN_NI = 0//use for add even only
+  CValue        : LOCATED_IN_NI
+  -----------------------------------------------------------------------------
+  Tag           : ConstName
+  Description   : Constant '[CValue]' does not follow recommended naming convention
+  Violation     : Lint:2983
+  Goal          : lint_rtl
+  Module        : fifo_ram
+  FileName      : ./../../rtl/src_noc/./flit_buffer.sv
+  LineNumber    : 427
+  Statement     :     parameter DATA_WIDTH = 32,
+  CValue        : DATA_WIDTH
+  -----------------------------------------------------------------------------
+  Tag           : ConstName
+  Description   : Constant '[CValue]' does not follow recommended naming convention
+  Violation     : Lint:2964
+  Goal          : lint_rtl
+  Module        : full_ovc_predictor
+  FileName      : ./../../rtl/src_noc/./output_ports.sv
+  LineNumber    : 534
+  Statement     :     parameter OVC_ALLOC_MODE=1'b0,
+  CValue        : OVC_ALLOC_MODE
+  -----------------------------------------------------------------------------
+  Tag           : ConstName
+  Description   : Constant '[CValue]' does not follow recommended naming convention
+  Violation     : Lint:2979
+  Goal          : lint_rtl
+  Module        : router_two_stage
+  FileName      : ./../../rtl/src_noc/./router_two_stage.sv
+  LineNumber    : 34
+  Statement     :     parameter ROUTER_ID=0,
+  CValue        : ROUTER_ID
+  -----------------------------------------------------------------------------
+  Tag           : ConstName
+  Description   : Constant '[CValue]' does not follow recommended naming convention
+  Violation     : Lint:2944
+  Goal          : lint_rtl
+  Module        : destp_generator
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 1100
+  Statement     :     parameter SELF_LOOP_EN=0,
+  CValue        : SELF_LOOP_EN
+  -----------------------------------------------------------------------------
+  Tag           : ConstName
+  Description   : Constant '[CValue]' does not follow recommended naming convention
+  Violation     : Lint:2970
+  Goal          : lint_rtl
+  Module        : conventional_routing
+  FileName      : ./../../rtl/src_noc/./routing.v
+  LineNumber    : 40
+  Statement     :     parameter DAw               = EAw,
+  CValue        : DAw
+  -----------------------------------------------------------------------------
+  Tag           : ConstName
+  Description   : Constant '[CValue]' does not follow recommended naming convention
+  Violation     : Lint:2998
+  Goal          : lint_rtl
+  Module        : mesh_torus_destp_generator
+  FileName      : ./../../rtl/src_noc/./mesh_torus.sv
+  LineNumber    : 1123
+  Statement     :     parameter SELF_LOOP_EN=0 
+  CValue        : SELF_LOOP_EN
+  -----------------------------------------------------------------------------
+  Tag           : ConstName
+  Description   : Constant '[CValue]' does not follow recommended naming convention
+  Violation     : Lint:2994
+  Goal          : lint_rtl
+  Module        : mesh_torus_destp_generator
+  FileName      : ./../../rtl/src_noc/./mesh_torus.sv
+  LineNumber    : 1116
+  Statement     :     parameter ROUTE_TYPE = "DETERMINISTIC",
+  CValue        : ROUTE_TYPE
+  -----------------------------------------------------------------------------
+  Tag           : ConstName
+  Description   : Constant '[CValue]' does not follow recommended naming convention
+  Violation     : Lint:2971
+  Goal          : lint_rtl
+  Module        : conventional_routing
+  FileName      : ./../../rtl/src_noc/./routing.v
+  LineNumber    : 41
+  Statement     :     parameter DSTPw             = 4,
+  CValue        : DSTPw
+  -----------------------------------------------------------------------------
+  Tag           : ConstName
+  Description   : Constant '[CValue]' does not follow recommended naming convention
+  Violation     : Lint:2932
+  Goal          : lint_rtl
+  Module        : swa_output_port_arbiter
+  FileName      : ./../../rtl/src_noc/./comb_nonspec.sv
+  LineNumber    : 701
+  Statement     :     parameter ARBITER_WIDTH =4,
+  CValue        : ARBITER_WIDTH
+  -----------------------------------------------------------------------------
+  Tag           : ConstName
+  Description   : Constant '[CValue]' does not follow recommended naming convention
+  Violation     : Lint:2958
+  Goal          : lint_rtl
+  Module        : port_pre_sel_gen
+  FileName      : ./../../rtl/src_noc/./congestion_analyzer.v
+  LineNumber    : 333
+  Statement     :     parameter ROUTE_TYPE="ADAPTIVE",
+  CValue        : ROUTE_TYPE
+  -----------------------------------------------------------------------------
+  Tag           : ConstName
+  Description   : Constant '[CValue]' does not follow recommended naming convention
+  Violation     : Lint:2999
+  Goal          : lint_rtl
+  Module        : line_ring_destp_decoder
+  FileName      : ./../../rtl/src_noc/./mesh_torus.sv
+  LineNumber    : 1291
+  Statement     :     parameter ROUTE_TYPE="DETERMINISTIC",
+  CValue        : ROUTE_TYPE
+  -----------------------------------------------------------------------------
+  Tag           : ConstName
+  Description   : Constant '[CValue]' does not follow recommended naming convention
+  Violation     : Lint:2933
+  Goal          : lint_rtl
+  Module        : swa_output_port_arbiter
+  FileName      : ./../../rtl/src_noc/./comb_nonspec.sv
+  LineNumber    : 702
+  Statement     :     parameter ARBITER_TYPE = "WRRA" // RRA, WRRA
+  CValue        : ARBITER_TYPE
+  -----------------------------------------------------------------------------
+  Tag           : ConstName
+  Description   : Constant '[CValue]' does not follow recommended naming convention
+  Violation     : Lint:3000
+  Goal          : lint_rtl
+  Module        : line_ring_destp_decoder
+  FileName      : ./../../rtl/src_noc/./mesh_torus.sv
+  LineNumber    : 1293
+  Statement     :     parameter DSTPw=2,
+  CValue        : DSTPw
+  -----------------------------------------------------------------------------
+  Tag           : ConstName
+  Description   : Constant '[CValue]' does not follow recommended naming convention
+  Violation     : Lint:2963
+  Goal          : lint_rtl
+  Module        : oport_ovc_sig_gen
+  FileName      : ./../../rtl/src_noc/./output_ports.sv
+  LineNumber    : 461
+  Statement     :     parameter SELF_LOOP_EN = 0
+  CValue        : SELF_LOOP_EN
+  -----------------------------------------------------------------------------
+  Tag           : ConstName
+  Description   : Constant '[CValue]' does not follow recommended naming convention
+  Violation     : Lint:2954
+  Goal          : lint_rtl
+  Module        : smart_credit_manage_per_vc
+  FileName      : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber    : 745
+  Statement     :     parameter Bw=2
+  CValue        : Bw
+  -----------------------------------------------------------------------------
+  Tag           : ConstName
+  Description   : Constant '[CValue]' does not follow recommended naming convention
+  Violation     : Lint:2993
+  Goal          : lint_rtl
+  Module        : mesh_torus_destp_generator
+  FileName      : ./../../rtl/src_noc/./mesh_torus.sv
+  LineNumber    : 1115
+  Statement     :     parameter ROUTE_NAME = "DOR",  
+  CValue        : ROUTE_NAME
+  -----------------------------------------------------------------------------
+  Tag           : ConstName
+  Description   : Constant '[CValue]' does not follow recommended naming convention
+  Violation     : Lint:3003
+  Goal          : lint_rtl
+  Module        : line_ring_destp_decoder
+  FileName      : ./../../rtl/src_noc/./mesh_torus.sv
+  LineNumber    : 1298
+  Statement     :     parameter SELF_LOOP_EN= 0
+  CValue        : SELF_LOOP_EN
+  -----------------------------------------------------------------------------
+  Tag           : ConstName
+  Description   : Constant '[CValue]' does not follow recommended naming convention
+  Violation     : Lint:2982
+  Goal          : lint_rtl
+  Module        : crossbar
+  FileName      : ./../../rtl/src_noc/./crossbar.v
+  LineNumber    : 36
+  Statement     :     parameter SELF_LOOP_EN= 0
+  CValue        : SELF_LOOP_EN
+  -----------------------------------------------------------------------------
+  Tag           : ConstName
+  Description   : Constant '[CValue]' does not follow recommended naming convention
+  Violation     : Lint:2995
+  Goal          : lint_rtl
+  Module        : mesh_torus_destp_generator
+  FileName      : ./../../rtl/src_noc/./mesh_torus.sv
+  LineNumber    : 1118
+  Statement     :     parameter DSTPw=4,
+  CValue        : DSTPw
+  -----------------------------------------------------------------------------
+  Tag           : ConstName
+  Description   : Constant '[CValue]' does not follow recommended naming convention
+  Violation     : Lint:2977
+  Goal          : lint_rtl
+  Module        : look_ahead_routing
+  FileName      : ./../../rtl/src_noc/./routing.v
+  LineNumber    : 244
+  Statement     :     parameter ROUTE_NAME="DOR",//
+  CValue        : ROUTE_NAME
+  -----------------------------------------------------------------------------
+  Tag           : ConstName
+  Description   : Constant '[CValue]' does not follow recommended naming convention
+  Violation     : Lint:2962
+  Goal          : lint_rtl
+  Module        : congestion_out_gen
+  FileName      : ./../../rtl/src_noc/./congestion_analyzer.v
+  LineNumber    : 951
+  Statement     :     parameter CONGw=2
+  CValue        : CONGw
+  -----------------------------------------------------------------------------
+  Tag           : ConstName
+  Description   : Constant '[CValue]' does not follow recommended naming convention
+  Violation     : Lint:2923
+  Goal          : lint_rtl
+  Module        : arbiter_priority_en
+  FileName      : ./../../rtl/src_noc/./../arbiter.v
+  LineNumber    : 89
+  Statement     :     parameter    ARBITER_WIDTH    =8
+  CValue        : ARBITER_WIDTH
+  -----------------------------------------------------------------------------
+  Tag           : ConstName
+  Description   : Constant '[CValue]' does not follow recommended naming convention
+  Violation     : Lint:2943
+  Goal          : lint_rtl
+  Module        : destp_generator
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 1098
+  Statement     :     parameter PPSw=4,
+  CValue        : PPSw
+  -----------------------------------------------------------------------------
+  Tag           : ConstName
+  Description   : Constant '[CValue]' does not follow recommended naming convention
+  Violation     : Lint:2980
+  Goal          : lint_rtl
+  Module        : credit_release_gen
+  FileName      : ./../../rtl/src_noc/./router_two_stage.sv
+  LineNumber    : 657
+  Statement     :     parameter CREDIT_NUM=4
+  CValue        : CREDIT_NUM
+  -----------------------------------------------------------------------------
+  Tag           : ConstName
+  Description   : Constant '[CValue]' does not follow recommended naming convention
+  Violation     : Lint:2953
+  Goal          : lint_rtl
+  Module        : smart_allocator_per_iport
+  FileName      : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber    : 538
+  Statement     :     parameter SS_PORT_LOC=1
+  CValue        : SS_PORT_LOC
+  -----------------------------------------------------------------------------
+  Tag           : ConstName
+  Description   : Constant '[CValue]' does not follow recommended naming convention
+  Violation     : Lint:2946
+  Goal          : lint_rtl
+  Module        : mesh_torus_look_ahead_routing
+  FileName      : ./../../rtl/src_noc/./mesh_torus_routting.v
+  LineNumber    : 13
+  Statement     :     parameter ROUTE_NAME = "DOR",// 
+  CValue        : ROUTE_NAME
+  -----------------------------------------------------------------------------
+  Tag           : ConstName
+  Description   : Constant '[CValue]' does not follow recommended naming convention
+  Violation     : Lint:2955
+  Goal          : lint_rtl
+  Module        : port_pre_sel_gen
+  FileName      : ./../../rtl/src_noc/./congestion_analyzer.v
+  LineNumber    : 327
+  Statement     :     parameter PPSw=4,
+  CValue        : PPSw
+  -----------------------------------------------------------------------------
+  Tag           : ConstName
+  Description   : Constant '[CValue]' does not follow recommended naming convention
+  Violation     : Lint:2956
+  Goal          : lint_rtl
+  Module        : port_pre_sel_gen
+  FileName      : ./../../rtl/src_noc/./congestion_analyzer.v
+  LineNumber    : 331
+  Statement     :     parameter CONGESTION_INDEX=2,
+  CValue        : CONGESTION_INDEX
+  -----------------------------------------------------------------------------
+  Tag           : ConstName
+  Description   : Constant '[CValue]' does not follow recommended naming convention
+  Violation     : Lint:2930
+  Goal          : lint_rtl
+  Module        : swa_input_port_arbiter
+  FileName      : ./../../rtl/src_noc/./comb_nonspec.sv
+  LineNumber    : 615
+  Statement     :     parameter ARBITER_WIDTH =4,
+  CValue        : ARBITER_WIDTH
+  -----------------------------------------------------------------------------
+  Tag           : ConstName
+  Description   : Constant '[CValue]' does not follow recommended naming convention
+  Violation     : Lint:2927
+  Goal          : lint_rtl
+  Module        : nonspec_sw_alloc
+  FileName      : ./../../rtl/src_noc/./comb_nonspec.sv
+  LineNumber    : 429
+  Statement     :     parameter SWA_ARBITER_TYPE = "WRRA",
+  CValue        : SWA_ARBITER_TYPE
+  -----------------------------------------------------------------------------
+  Tag           : ConstName
+  Description   : Constant '[CValue]' does not follow recommended naming convention
+  Violation     : Lint:2950
+  Goal          : lint_rtl
+  Module        : mesh_torus_conventional_routing
+  FileName      : ./../../rtl/src_noc/./mesh_torus_routting.v
+  LineNumber    : 600
+  Statement     :     parameter ROUTE_TYPE = "DETERMINISTIC",    
+  CValue        : ROUTE_TYPE
+  -----------------------------------------------------------------------------
+  Tag           : ConstName
+  Description   : Constant '[CValue]' does not follow recommended naming convention
+  Violation     : Lint:2917
+  Goal          : lint_rtl
+  Module        : bin_to_one_hot
+  FileName      : ./../../rtl/src_noc/./../main_comp.v
+  LineNumber    : 237
+  Statement     :     parameter BIN_WIDTH = 2,
+  CValue        : BIN_WIDTH
+  -----------------------------------------------------------------------------
+  Tag           : ConstName
+  Description   : Constant '[CValue]' does not follow recommended naming convention
+  Violation     : Lint:2941
+  Goal          : lint_rtl
+  Module        : destp_generator
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 1096
+  Statement     :     parameter DSTPw=4,
+  CValue        : DSTPw
+  -----------------------------------------------------------------------------
+  Tag           : ConstName
+  Description   : Constant '[CValue]' does not follow recommended naming convention
+  Violation     : Lint:2961
+  Goal          : lint_rtl
+  Module        : congestion_out_gen
+  FileName      : ./../../rtl/src_noc/./congestion_analyzer.v
+  LineNumber    : 950
+  Statement     :     parameter CONGESTION_INDEX=2,
+  CValue        : CONGESTION_INDEX
+  -----------------------------------------------------------------------------
+  Tag           : ConstName
+  Description   : Constant '[CValue]' does not follow recommended naming convention
+  Violation     : Lint:2921
+  Goal          : lint_rtl
+  Module        : binary_mux
+  FileName      : ./../../rtl/src_noc/./../main_comp.v
+  LineNumber    : 299
+  Statement     :     parameter OUT_WIDTH = 5
+  CValue        : OUT_WIDTH
+  -----------------------------------------------------------------------------
+  Tag           : ConstName
+  Description   : Constant '[CValue]' does not follow recommended naming convention
+  Violation     : Lint:2918
+  Goal          : lint_rtl
+  Module        : bin_to_one_hot
+  FileName      : ./../../rtl/src_noc/./../main_comp.v
+  LineNumber    : 238
+  Statement     :     parameter ONE_HOT_WIDTH = 2**BIN_WIDTH
+  CValue        : ONE_HOT_WIDTH
+  -----------------------------------------------------------------------------
+  Tag           : ConstName
+  Description   : Constant '[CValue]' does not follow recommended naming convention
+  Violation     : Lint:2939
+  Goal          : lint_rtl
+  Module        : destp_generator
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 1091
+  Statement     :     parameter ROUTE_NAME="DOR",
+  CValue        : ROUTE_NAME
+  -----------------------------------------------------------------------------
+  Tag           : ConstName
+  Description   : Constant '[CValue]' does not follow recommended naming convention
+  Violation     : Lint:2996
+  Goal          : lint_rtl
+  Module        : mesh_torus_destp_generator
+  FileName      : ./../../rtl/src_noc/./mesh_torus.sv
+  LineNumber    : 1120
+  Statement     :     parameter PLw=1,
+  CValue        : PLw
+  -----------------------------------------------------------------------------
+  Tag           : ConstName
+  Description   : Constant '[CValue]' does not follow recommended naming convention
+  Violation     : Lint:2914
+  Goal          : lint_rtl
+  Module        : one_hot_demux
+  FileName      : ./../../rtl/src_noc/./../main_comp.v
+  LineNumber    : 147
+  Statement     :     parameter SEL_WIDTH=4,
+  CValue        : SEL_WIDTH
+  -----------------------------------------------------------------------------
+  Tag           : ConstName
+  Description   : Constant '[CValue]' does not follow recommended naming convention
+  Violation     : Lint:2990
+  Goal          : lint_rtl
+  Module        : mesh_torus_mask_non_assignable_destport_no_self_loop
+  FileName      : ./../../rtl/src_noc/./mesh_torus.sv
+  LineNumber    : 282
+  Statement     :     parameter ROUTE_NAME="DOR",
+  CValue        : ROUTE_NAME
+  -----------------------------------------------------------------------------
+  Tag           : ConstName
+  Description   : Constant '[CValue]' does not follow recommended naming convention
+  Violation     : Lint:2911
+  Goal          : lint_rtl
+  Module        : noc_top
+  FileName      : ./../../rtl/src_noc/./../arbiter.v
+  LineNumber    : 35
+  Statement     : `define PRONOC_ARBITER
+  CValue        : PRONOC_ARBITER
+  -----------------------------------------------------------------------------
+  Tag           : ConstName
+  Description   : Constant '[CValue]' does not follow recommended naming convention
+  Violation     : Lint:2926
+  Goal          : lint_rtl
+  Module        : nonspec_sw_alloc
+  FileName      : ./../../rtl/src_noc/./comb_nonspec.sv
+  LineNumber    : 428
+  Statement     :     parameter FIRST_ARBITER_EXT_P_EN = 1, 
+  CValue        : FIRST_ARBITER_EXT_P_EN
+
+  -----------------------------------------------------------------------------
+  FileHdr  (24 warnings/0 waived)
+  -----------------------------------------------------------------------------
+  Tag           : FileHdr
+  Description   : Non-standard file header: [Reason_Name]
+  Violation     : Lint:5917
+  Goal          : lint_rtl
+  Module        : noc_top
+  FileName      : ./../../rtl/src_noc/./../main_comp.v
+  LineNumber    : 1
+  Statement     : `include "pronoc_def.v"
+  Reason_Name   : Could not find file-header start
+  -----------------------------------------------------------------------------
+  Tag           : FileHdr
+  Description   : Non-standard file header: [Reason_Name]
+  Violation     : Lint:5938
+  Goal          : lint_rtl
+  Module        : noc_top
+  FileName      : ./../../rtl/src_noc/./pronoc_pkg.sv
+  LineNumber    : 2
+  Statement     : `include "pronoc_def.v"
+  Reason_Name   : Could not find file-header start
+  -----------------------------------------------------------------------------
+  Tag           : FileHdr
+  Description   : Non-standard file header: [Reason_Name]
+  Violation     : Lint:5929
+  Goal          : lint_rtl
+  Module        : noc_top
+  FileName      : ./../../rtl/src_noc/./congestion_analyzer.v
+  LineNumber    : 1
+  Statement     : `include "pronoc_def.v"
+  Reason_Name   : Could not find file-header start
+  -----------------------------------------------------------------------------
+  Tag           : FileHdr
+  Description   : Non-standard file header: [Reason_Name]
+  Violation     : Lint:5924
+  Goal          : lint_rtl
+  Module        : noc_top
+  FileName      : ./../../rtl/src_noc/./inout_ports.sv
+  LineNumber    : 1
+  Statement     : `include "pronoc_def.v"
+  Reason_Name   : Could not find file-header start
+  -----------------------------------------------------------------------------
+  Tag           : FileHdr
+  Description   : Non-standard file header: [Reason_Name]
+  Violation     : Lint:5928
+  Goal          : lint_rtl
+  Module        : noc_top
+  FileName      : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber    : 1
+  Statement     : `include "pronoc_def.v"
+  Reason_Name   : Could not find file-header start
+  -----------------------------------------------------------------------------
+  Tag           : FileHdr
+  Description   : Non-standard file header: [Reason_Name]
+  Violation     : Lint:5932
+  Goal          : lint_rtl
+  Module        : noc_top
+  FileName      : ./../../rtl/src_noc/./router_two_stage.sv
+  LineNumber    : 1
+  Statement     : `include "pronoc_def.v"
+  Reason_Name   : Could not find file-header start
+  -----------------------------------------------------------------------------
+  Tag           : FileHdr
+  Description   : Non-standard file header: [Reason_Name]
+  Violation     : Lint:5922
+  Goal          : lint_rtl
+  Module        : noc_top
+  FileName      : ./../../rtl/src_noc/./noc_top.sv
+  LineNumber    : 1
+  Statement     : `include "pronoc_def.v"
+  Reason_Name   : Could not find file-header start
+  -----------------------------------------------------------------------------
+  Tag           : FileHdr
+  Description   : Non-standard file header: [Reason_Name]
+  Violation     : Lint:5935
+  Goal          : lint_rtl
+  Module        : noc_top
+  FileName      : ./../../rtl/src_noc/./mesh_torus.sv
+  LineNumber    : 1
+  Statement     : `include "pronoc_def.v"
+  Reason_Name   : Could not find file-header start
+  -----------------------------------------------------------------------------
+  Tag           : FileHdr
+  Description   : Non-standard file header: [Reason_Name]
+  Violation     : Lint:5925
+  Goal          : lint_rtl
+  Module        : noc_top
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 1
+  Statement     : `include "pronoc_def.v"
+  Reason_Name   : Could not find file-header start
+  -----------------------------------------------------------------------------
+  Tag           : FileHdr
+  Description   : Non-standard file header: [Reason_Name]
+  Violation     : Lint:5918
+  Goal          : lint_rtl
+  Module        : noc_top
+  FileName      : ./../../rtl/src_noc/./../arbiter.v
+  LineNumber    : 1
+  Statement     : `include "pronoc_def.v"
+  Reason_Name   : Could not find file-header start
+  -----------------------------------------------------------------------------
+  Tag           : FileHdr
+  Description   : Non-standard file header: [Reason_Name]
+  Violation     : Lint:5920
+  Goal          : lint_rtl
+  Module        : noc_top
+  FileName      : ./../../rtl/src_noc/./header_flit.sv
+  LineNumber    : 1
+  Statement     : `include "pronoc_def.v"
+  Reason_Name   : Could not find file-header start
+  -----------------------------------------------------------------------------
+  Tag           : FileHdr
+  Description   : Non-standard file header: [Reason_Name]
+  Violation     : Lint:5940
+  Goal          : lint_rtl
+  Module        : noc_top
+  FileName      : ./../../rtl/src_noc/./topology_localparam.v
+  LineNumber    : 1
+  Statement     : `include "pronoc_def.v"
+  Reason_Name   : Could not find file-header start
+  -----------------------------------------------------------------------------
+  Tag           : FileHdr
+  Description   : Non-standard file header: [Reason_Name]
+  Violation     : Lint:5936
+  Goal          : lint_rtl
+  Module        : noc_top
+  FileName      : ./../../rtl/src_noc/./router_top.sv
+  LineNumber    : 1
+  Statement     : `include "pronoc_def.v"
+  Reason_Name   : Could not find file-header start
+  -----------------------------------------------------------------------------
+  Tag           : FileHdr
+  Description   : Non-standard file header: [Reason_Name]
+  Violation     : Lint:5919
+  Goal          : lint_rtl
+  Module        : noc_top
+  FileName      : ./../../rtl/src_noc/./ovc_list.sv
+  LineNumber    : 1
+  Statement     : `include "pronoc_def.v"
+  Reason_Name   : Could not find file-header start
+  -----------------------------------------------------------------------------
+  Tag           : FileHdr
+  Description   : Non-standard file header: [Reason_Name]
+  Violation     : Lint:5916
+  Goal          : lint_rtl
+  Module        : noc_top
+  FileName      : ./../../rtl/src_noc/./../pronoc_def.v
+  LineNumber    : 1
+  Statement     : `ifndef PRONOC_DEF
+  Reason_Name   : Could not find file-header start
+  -----------------------------------------------------------------------------
+  Tag           : FileHdr
+  Description   : Non-standard file header: [Reason_Name]
+  Violation     : Lint:5923
+  Goal          : lint_rtl
+  Module        : noc_top
+  FileName      : ./../../rtl/src_noc/./comb_nonspec.sv
+  LineNumber    : 1
+  Statement     : `include "pronoc_def.v"
+  Reason_Name   : Could not find file-header start
+  -----------------------------------------------------------------------------
+  Tag           : FileHdr
+  Description   : Non-standard file header: [Reason_Name]
+  Violation     : Lint:5926
+  Goal          : lint_rtl
+  Module        : noc_top
+  FileName      : ./../../rtl/src_noc/./combined_vc_sw_alloc.sv
+  LineNumber    : 1
+  Statement     : `include "pronoc_def.v"
+  Reason_Name   : Could not find file-header start
+  -----------------------------------------------------------------------------
+  Tag           : FileHdr
+  Description   : Non-standard file header: [Reason_Name]
+  Violation     : Lint:5931
+  Goal          : lint_rtl
+  Module        : noc_top
+  FileName      : ./../../rtl/src_noc/./routing.v
+  LineNumber    : 1
+  Statement     : `include "pronoc_def.v"
+  Reason_Name   : Could not find file-header start
+  -----------------------------------------------------------------------------
+  Tag           : FileHdr
+  Description   : Non-standard file header: [Reason_Name]
+  Violation     : Lint:5933
+  Goal          : lint_rtl
+  Module        : noc_top
+  FileName      : ./../../rtl/src_noc/./crossbar.v
+  LineNumber    : 1
+  Statement     : `include "pronoc_def.v"
+  Reason_Name   : Could not find file-header start
+  -----------------------------------------------------------------------------
+  Tag           : FileHdr
+  Description   : Non-standard file header: [Reason_Name]
+  Violation     : Lint:5937
+  Goal          : lint_rtl
+  Module        : noc_top
+  FileName      : ./../../rtl/src_noc/./mesh_torus_noc_top.sv
+  LineNumber    : 1
+  Statement     : `include "pronoc_def.v"
+  Reason_Name   : Could not find file-header start
+  -----------------------------------------------------------------------------
+  Tag           : FileHdr
+  Description   : Non-standard file header: [Reason_Name]
+  Violation     : Lint:5930
+  Goal          : lint_rtl
+  Module        : noc_top
+  FileName      : ./../../rtl/src_noc/./output_ports.sv
+  LineNumber    : 1
+  Statement     : `include "pronoc_def.v"
+  Reason_Name   : Could not find file-header start
+  -----------------------------------------------------------------------------
+  Tag           : FileHdr
+  Description   : Non-standard file header: [Reason_Name]
+  Violation     : Lint:5934
+  Goal          : lint_rtl
+  Module        : noc_top
+  FileName      : ./../../rtl/src_noc/./flit_buffer.sv
+  LineNumber    : 1
+  Statement     : `include "pronoc_def.v"
+  Reason_Name   : Could not find file-header start
+  -----------------------------------------------------------------------------
+  Tag           : FileHdr
+  Description   : Non-standard file header: [Reason_Name]
+  Violation     : Lint:5927
+  Goal          : lint_rtl
+  Module        : noc_top
+  FileName      : ./../../rtl/src_noc/./mesh_torus_routting.v
+  LineNumber    : 1
+  Statement     : `include "pronoc_def.v"
+  Reason_Name   : Could not find file-header start
+  -----------------------------------------------------------------------------
+  Tag           : FileHdr
+  Description   : Non-standard file header: [Reason_Name]
+  Violation     : Lint:5939
+  Goal          : lint_rtl
+  Module        : noc_top
+  FileName      : ./src/noc_localparam.v
+  LineNumber    : 1
+  Statement     : `ifdef NOC_LOCAL_PARAM 
+  Reason_Name   : Could not find file-header start
+
+  -----------------------------------------------------------------------------
+  ImproperRangeIndex-ML  (1 warning/0 waived)
+  -----------------------------------------------------------------------------
+  Tag             : ImproperRangeIndex-ML
+  Description     : Index '[RTL_EXPRESSION]' of width '[NewExprSize]' is [Reason_Name] than the width '[ExprSize]' required for the max value '[MaxValue]' of the signal '[NodeName]'[Hierarchy: [HIERARCHY]]
+  Violation       : Lint:5862
+  Goal            : lint_rtl
+  Module          : noc_top
+  FileName        : ./../../rtl/src_noc/./topology_localparam.v
+  LineNumber      : 337
+  Statement       :                 if( mcast_list[mcast_id_to_endp_id]==1'b1) begin 
+  RTL_EXPRESSION  : mcast_id_to_endp_id
+  NewExprSize     : 32
+  Reason_Name     : larger
+  ExprSize        : 2
+  MaxValue        : 3
+  NodeName        : mcast_list
+  HIERARCHY       : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[3].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[2].the_input_queue_per_port @input_queue_per_port:mcast_id_to_endp_id
+
+  -----------------------------------------------------------------------------
+  ParamName  (178 warnings/0 waived)
+  -----------------------------------------------------------------------------
+  Tag           : ParamName
+  Description   : Parameter name [Param] does not follow naming convention
+  Violation     : Lint:3204
+  Goal          : lint_rtl
+  Module        : mesh_torus_conventional_routing
+  FileName      : ./../../rtl/src_noc/./mesh_torus_routting.v
+  LineNumber    : 603
+  Statement     :     parameter LOCATED_IN_NI = 0//use for add even only
+  Param         : LOCATED_IN_NI
+  -----------------------------------------------------------------------------
+  Tag           : ParamName
+  Description   : Parameter name [Param] does not follow naming convention
+  Violation     : Lint:3200
+  Goal          : lint_rtl
+  Module        : mesh_torus_look_ahead_routing
+  FileName      : ./../../rtl/src_noc/./mesh_torus_routting.v
+  LineNumber    : 14
+  Statement     :     parameter ROUTE_TYPE = "DETERMINISTIC"// "DETERMINISTIC", "FULL_ADAPTIVE", "PAR_ADAPTIVE"
+  Param         : ROUTE_TYPE
+  -----------------------------------------------------------------------------
+  Tag           : ParamName
+  Description   : Parameter name [Param] does not follow naming convention
+  Violation     : Lint:3340
+  Goal          : lint_rtl
+  Module        : mesh_tori_endp_addr_decode
+  FileName      : ./../../rtl/src_noc/./mesh_torus.sv
+  LineNumber    : 955
+  Statement     :         EYw = (TOPOLOGY=="RING" || TOPOLOGY == "LINE")? 1 : log2(NY),
+  Param         : EYw
+  -----------------------------------------------------------------------------
+  Tag           : ParamName
+  Description   : Parameter name [Param] does not follow naming convention
+  Violation     : Lint:3166
+  Goal          : lint_rtl
+  Module        : one_hot_mux
+  FileName      : ./../../rtl/src_noc/./../main_comp.v
+  LineNumber    : 115
+  Statement     :     parameter   OUT_WIDTH = IN_WIDTH/SEL_WIDTH
+  Param         : OUT_WIDTH
+  -----------------------------------------------------------------------------
+  Tag           : ParamName
+  Description   : Parameter name [Param] does not follow naming convention
+  Violation     : Lint:3299
+  Goal          : lint_rtl
+  Module        : credit_monitor_per_ovc
+  FileName      : ./../../rtl/src_noc/./output_ports.sv
+  LineNumber    : 415
+  Statement     :         DEPTHw = log2(PORT_B+1);
+  Param         : DEPTHw
+  -----------------------------------------------------------------------------
+  Tag           : ParamName
+  Description   : Parameter name [Param] does not follow naming convention
+  Violation     : Lint:3326
+  Goal          : lint_rtl
+  Module        : flit_buffer
+  FileName      : ./../../rtl/src_noc/./flit_buffer.sv
+  LineNumber    : 58
+  Statement     :         BVw = log2(BV),
+  Param         : BVw
+  -----------------------------------------------------------------------------
+  Tag           : ParamName
+  Description   : Parameter name [Param] does not follow naming convention
+  Violation     : Lint:3303
+  Goal          : lint_rtl
+  Module        : conventional_routing
+  FileName      : ./../../rtl/src_noc/./routing.v
+  LineNumber    : 76
+  Statement     :             EXw = RXw,
+  Param         : EXw
+  -----------------------------------------------------------------------------
+  Tag           : ParamName
+  Description   : Parameter name [Param] does not follow naming convention
+  Violation     : Lint:3233
+  Goal          : lint_rtl
+  Module        : credit_release_gen
+  FileName      : ./../../rtl/src_noc/./router_two_stage.sv
+  LineNumber    : 657
+  Statement     :     parameter CREDIT_NUM=4
+  Param         : CREDIT_NUM
+  -----------------------------------------------------------------------------
+  Tag           : ParamName
+  Description   : Parameter name [Param] does not follow naming convention
+  Violation     : Lint:3298
+  Goal          : lint_rtl
+  Module        : output_ports
+  FileName      : ./../../rtl/src_noc/./output_ports.sv
+  LineNumber    : 72
+  Statement     :     localparam  CONG_ALw= CONGw * P;   //  congestion width per router;
+  Param         : CONG_ALw
+  -----------------------------------------------------------------------------
+  Tag           : ParamName
+  Description   : Parameter name [Param] does not follow naming convention
+  Violation     : Lint:3330
+  Goal          : lint_rtl
+  Module        : flit_buffer
+  FileName      : ./../../rtl/src_noc/./flit_buffer.sv
+  LineNumber    : 62
+  Statement     :         BVwV = BVw * V,
+  Param         : BVwV
+  -----------------------------------------------------------------------------
+  Tag           : ParamName
+  Description   : Parameter name [Param] does not follow naming convention
+  Violation     : Lint:3323
+  Goal          : lint_rtl
+  Module        : crossbar
+  FileName      : ./../../rtl/src_noc/./crossbar.v
+  LineNumber    : 63
+  Statement     :         P_1Fw = P_1 * Fw,
+  Param         : P_1Fw
+  -----------------------------------------------------------------------------
+  Tag           : ParamName
+  Description   : Parameter name [Param] does not follow naming convention
+  Violation     : Lint:3306
+  Goal          : lint_rtl
+  Module        : conventional_routing
+  FileName      : ./../../rtl/src_noc/./routing.v
+  LineNumber    : 146
+  Statement     :             LKw= L*Kw,
+  Param         : LKw
+  -----------------------------------------------------------------------------
+  Tag           : ParamName
+  Description   : Parameter name [Param] does not follow naming convention
+  Violation     : Lint:3211
+  Goal          : lint_rtl
+  Module        : port_pre_sel_gen
+  FileName      : ./../../rtl/src_noc/./congestion_analyzer.v
+  LineNumber    : 333
+  Statement     :     parameter ROUTE_TYPE="ADAPTIVE",
+  Param         : ROUTE_TYPE
+  -----------------------------------------------------------------------------
+  Tag           : ParamName
+  Description   : Parameter name [Param] does not follow naming convention
+  Violation     : Lint:3230
+  Goal          : lint_rtl
+  Module        : look_ahead_routing
+  FileName      : ./../../rtl/src_noc/./routing.v
+  LineNumber    : 244
+  Statement     :     parameter ROUTE_NAME="DOR",//
+  Param         : ROUTE_NAME
+  -----------------------------------------------------------------------------
+  Tag           : ParamName
+  Description   : Parameter name [Param] does not follow naming convention
+  Violation     : Lint:3258
+  Goal          : lint_rtl
+  Module        : one_hot_to_bin
+  FileName      : ./../../rtl/src_noc/./../main_comp.v
+  LineNumber    : 270
+  Statement     :     localparam MUX_IN_WIDTH = BIN_WIDTH* ONE_HOT_WIDTH;
+  Param         : MUX_IN_WIDTH
+  -----------------------------------------------------------------------------
+  Tag           : ParamName
+  Description   : Parameter name [Param] does not follow naming convention
+  Violation     : Lint:3217
+  Goal          : lint_rtl
+  Module        : full_ovc_predictor
+  FileName      : ./../../rtl/src_noc/./output_ports.sv
+  LineNumber    : 534
+  Statement     :     parameter OVC_ALLOC_MODE=1'b0,
+  Param         : OVC_ALLOC_MODE
+  -----------------------------------------------------------------------------
+  Tag           : ParamName
+  Description   : Parameter name [Param] does not follow naming convention
+  Violation     : Lint:3267
+  Goal          : lint_rtl
+  Module        : inout_ports
+  FileName      : ./../../rtl/src_noc/./inout_ports.sv
+  LineNumber    : 104
+  Statement     :         PRAw= P * RAw;
+  Param         : PRAw
+  -----------------------------------------------------------------------------
+  Tag           : ParamName
+  Description   : Parameter name [Param] does not follow naming convention
+  Violation     : Lint:3261
+  Goal          : lint_rtl
+  Module        : extract_header_flit_info
+  FileName      : ./../../rtl/src_noc/./header_flit.sv
+  LineNumber    : 132
+  Statement     :         Dw = (DATA_w==0)? 1 : DATA_w,
+  Param         : Dw
+  -----------------------------------------------------------------------------
+  Tag           : ParamName
+  Description   : Parameter name [Param] does not follow naming convention
+  Violation     : Lint:3341
+  Goal          : lint_rtl
+  Module        : mesh_tori_endp_addr_decode
+  FileName      : ./../../rtl/src_noc/./mesh_torus.sv
+  LineNumber    : 956
+  Statement     :         ELw = log2(NL);    // number of node in y axis
+  Param         : ELw
+  -----------------------------------------------------------------------------
+  Tag           : ParamName
+  Description   : Parameter name [Param] does not follow naming convention
+  Violation     : Lint:3300
+  Goal          : lint_rtl
+  Module        : credit_monitor_per_ovc
+  FileName      : ./../../rtl/src_noc/./output_ports.sv
+  LineNumber    : 416
+  Statement     :     localparam [DEPTHw-1 : 0] Bint = PORT_B [DEPTHw-1 : 0];
+  Param         : Bint
+  -----------------------------------------------------------------------------
+  Tag           : ParamName
+  Description   : Parameter name [Param] does not follow naming convention
+  Violation     : Lint:3178
+  Goal          : lint_rtl
+  Module        : extract_header_flit_info
+  FileName      : ./../../rtl/src_noc/./header_flit.sv
+  LineNumber    : 109
+  Statement     :     parameter DATA_w = 0
+  Param         : DATA_w
+  -----------------------------------------------------------------------------
+  Tag           : ParamName
+  Description   : Parameter name [Param] does not follow naming convention
+  Violation     : Lint:3169
+  Goal          : lint_rtl
+  Module        : custom_or
+  FileName      : ./../../rtl/src_noc/./../main_comp.v
+  LineNumber    : 170
+  Statement     :     parameter OUT_WIDTH = 5
+  Param         : OUT_WIDTH
+  -----------------------------------------------------------------------------
+  Tag           : ParamName
+  Description   : Parameter name [Param] does not follow naming convention
+  Violation     : Lint:3322
+  Goal          : lint_rtl
+  Module        : crossbar
+  FileName      : ./../../rtl/src_noc/./crossbar.v
+  LineNumber    : 62
+  Statement     :         PFw = P*Fw,
+  Param         : PFw
+  -----------------------------------------------------------------------------
+  Tag           : ParamName
+  Description   : Parameter name [Param] does not follow naming convention
+  Violation     : Lint:3256
+  Goal          : lint_rtl
+  Module        : line_ring_destp_decoder
+  FileName      : ./../../rtl/src_noc/./mesh_torus.sv
+  LineNumber    : 1298
+  Statement     :     parameter SELF_LOOP_EN= 0
+  Param         : SELF_LOOP_EN
+  -----------------------------------------------------------------------------
+  Tag           : ParamName
+  Description   : Parameter name [Param] does not follow naming convention
+  Violation     : Lint:3331
+  Goal          : lint_rtl
+  Module        : flit_buffer
+  FileName      : ./../../rtl/src_noc/./flit_buffer.sv
+  LineNumber    : 63
+  Statement     :         RESTw = Fw -2-V , 
+  Param         : RESTw
+  -----------------------------------------------------------------------------
+  Tag           : ParamName
+  Description   : Parameter name [Param] does not follow naming convention
+  Violation     : Lint:3213
+  Goal          : lint_rtl
+  Module        : congestion_out_gen
+  FileName      : ./../../rtl/src_noc/./congestion_analyzer.v
+  LineNumber    : 949
+  Statement     :     parameter ROUTE_TYPE ="ADAPTIVE", 
+  Param         : ROUTE_TYPE
+  -----------------------------------------------------------------------------
+  Tag           : ParamName
+  Description   : Parameter name [Param] does not follow naming convention
+  Violation     : Lint:3329
+  Goal          : lint_rtl
+  Module        : flit_buffer
+  FileName      : ./../../rtl/src_noc/./flit_buffer.sv
+  LineNumber    : 61
+  Statement     :         BwV = Bw * V,
+  Param         : BwV
+  -----------------------------------------------------------------------------
+  Tag           : ParamName
+  Description   : Parameter name [Param] does not follow naming convention
+  Violation     : Lint:3327
+  Goal          : lint_rtl
+  Module        : flit_buffer
+  FileName      : ./../../rtl/src_noc/./flit_buffer.sv
+  LineNumber    : 59
+  Statement     :         Vw = (V==1)? 1 : log2(V),
+  Param         : Vw
+  -----------------------------------------------------------------------------
+  Tag           : ParamName
+  Description   : Parameter name [Param] does not follow naming convention
+  Violation     : Lint:3187
+  Goal          : lint_rtl
+  Module        : inout_ports
+  FileName      : ./../../rtl/src_noc/./inout_ports.sv
+  LineNumber    : 30
+  Statement     :     parameter ROUTER_ID=0,
+  Param         : ROUTER_ID
+  -----------------------------------------------------------------------------
+  Tag           : ParamName
+  Description   : Parameter name [Param] does not follow naming convention
+  Violation     : Lint:3262
+  Goal          : lint_rtl
+  Module        : extract_header_flit_info
+  FileName      : ./../../rtl/src_noc/./header_flit.sv
+  LineNumber    : 135
+  Statement     :         OFFSETw = DATA_MSB - DATA_LSB +1; 
+  Param         : OFFSETw
+  -----------------------------------------------------------------------------
+  Tag           : ParamName
+  Description   : Parameter name [Param] does not follow naming convention
+  Violation     : Lint:3310
+  Goal          : lint_rtl
+  Module        : look_ahead_routing
+  FileName      : ./../../rtl/src_noc/./routing.v
+  LineNumber    : 272
+  Statement     :         Lw = log2(T2),
+  Param         : Lw
+  -----------------------------------------------------------------------------
+  Tag           : ParamName
+  Description   : Parameter name [Param] does not follow naming convention
+  Violation     : Lint:3216
+  Goal          : lint_rtl
+  Module        : oport_ovc_sig_gen
+  FileName      : ./../../rtl/src_noc/./output_ports.sv
+  LineNumber    : 461
+  Statement     :     parameter SELF_LOOP_EN = 0
+  Param         : SELF_LOOP_EN
+  -----------------------------------------------------------------------------
+  Tag           : ParamName
+  Description   : Parameter name [Param] does not follow naming convention
+  Violation     : Lint:3192
+  Goal          : lint_rtl
+  Module        : destp_generator
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 1091
+  Statement     :     parameter ROUTE_NAME="DOR",
+  Param         : ROUTE_NAME
+  -----------------------------------------------------------------------------
+  Tag           : ParamName
+  Description   : Parameter name [Param] does not follow naming convention
+  Violation     : Lint:3288
+  Goal          : lint_rtl
+  Module        : mesh_torus_next_router_addr_predictor
+  FileName      : ./../../rtl/src_noc/./mesh_torus_routting.v
+  LineNumber    : 358
+  Statement     :     localparam [Yw-1 : 0] LAST_Y_ADDR =(NY[Yw-1 : 0]-1'b1);                
+  Param         : LAST_Y_ADDR
+  -----------------------------------------------------------------------------
+  Tag           : ParamName
+  Description   : Parameter name [Param] does not follow naming convention
+  Violation     : Lint:3281
+  Goal          : lint_rtl
+  Module        : mesh_torus_look_ahead_routing
+  FileName      : ./../../rtl/src_noc/./mesh_torus_routting.v
+  LineNumber    : 42
+  Statement     :         Xw = log2(NX),   // number of node in x axis
+  Param         : Xw
+  -----------------------------------------------------------------------------
+  Tag           : ParamName
+  Description   : Parameter name [Param] does not follow naming convention
+  Violation     : Lint:3328
+  Goal          : lint_rtl
+  Module        : flit_buffer
+  FileName      : ./../../rtl/src_noc/./flit_buffer.sv
+  LineNumber    : 60
+  Statement     :         DEPTHw = log2(B+1),
+  Param         : DEPTHw
+  -----------------------------------------------------------------------------
+  Tag           : ParamName
+  Description   : Parameter name [Param] does not follow naming convention
+  Violation     : Lint:3221
+  Goal          : lint_rtl
+  Module        : conventional_routing
+  FileName      : ./../../rtl/src_noc/./routing.v
+  LineNumber    : 38
+  Statement     :     parameter RAw               = 3,
+  Param         : RAw
+  -----------------------------------------------------------------------------
+  Tag           : ParamName
+  Description   : Parameter name [Param] does not follow naming convention
+  Violation     : Lint:3186
+  Goal          : lint_rtl
+  Module        : swa_output_port_arbiter
+  FileName      : ./../../rtl/src_noc/./comb_nonspec.sv
+  LineNumber    : 702
+  Statement     :     parameter ARBITER_TYPE = "WRRA" // RRA, WRRA
+  Param         : ARBITER_TYPE
+  -----------------------------------------------------------------------------
+  Tag           : ParamName
+  Description   : Parameter name [Param] does not follow naming convention
+  Violation     : Lint:3198
+  Goal          : lint_rtl
+  Module        : destp_generator
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 1101
+  Statement     :     parameter CAST_TYPE = "UNICAST"
+  Param         : CAST_TYPE
+  -----------------------------------------------------------------------------
+  Tag           : ParamName
+  Description   : Parameter name [Param] does not follow naming convention
+  Violation     : Lint:3222
+  Goal          : lint_rtl
+  Module        : conventional_routing
+  FileName      : ./../../rtl/src_noc/./routing.v
+  LineNumber    : 39
+  Statement     :     parameter EAw               = 3,
+  Param         : EAw
+  -----------------------------------------------------------------------------
+  Tag           : ParamName
+  Description   : Parameter name [Param] does not follow naming convention
+  Violation     : Lint:3305
+  Goal          : lint_rtl
+  Module        : conventional_routing
+  FileName      : ./../../rtl/src_noc/./routing.v
+  LineNumber    : 145
+  Statement     :             Kw = log2(K),
+  Param         : Kw
+  -----------------------------------------------------------------------------
+  Tag           : ParamName
+  Description   : Parameter name [Param] does not follow naming convention
+  Violation     : Lint:3324
+  Goal          : lint_rtl
+  Module        : crossbar
+  FileName      : ./../../rtl/src_noc/./crossbar.v
+  LineNumber    : 64
+  Statement     :         P_1w = log2(P_1);
+  Param         : P_1w
+  -----------------------------------------------------------------------------
+  Tag           : ParamName
+  Description   : Parameter name [Param] does not follow naming convention
+  Violation     : Lint:3189
+  Goal          : lint_rtl
+  Module        : vc_alloc_request_gen_determinstic
+  FileName      : ./../../rtl/src_noc/./inout_ports.sv
+  LineNumber    : 606
+  Statement     :     parameter CAST_TYPE = "UNICAST" 
+  Param         : CAST_TYPE
+  -----------------------------------------------------------------------------
+  Tag           : ParamName
+  Description   : Parameter name [Param] does not follow naming convention
+  Violation     : Lint:3206
+  Goal          : lint_rtl
+  Module        : smart_allocator_per_iport
+  FileName      : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber    : 538
+  Statement     :     parameter SS_PORT_LOC=1
+  Param         : SS_PORT_LOC
+  -----------------------------------------------------------------------------
+  Tag           : ParamName
+  Description   : Parameter name [Param] does not follow naming convention
+  Violation     : Lint:3336
+  Goal          : lint_rtl
+  Module        : fwft_fifo
+  FileName      : ./../../rtl/src_noc/./flit_buffer.sv
+  LineNumber    : 575
+  Statement     :     localparam MUX_SEL_WIDTH = log2(MAX_DEPTH-1);
+  Param         : MUX_SEL_WIDTH
+  -----------------------------------------------------------------------------
+  Tag           : ParamName
+  Description   : Parameter name [Param] does not follow naming convention
+  Violation     : Lint:3237
+  Goal          : lint_rtl
+  Module        : fifo_ram
+  FileName      : ./../../rtl/src_noc/./flit_buffer.sv
+  LineNumber    : 428
+  Statement     :     parameter ADDR_WIDTH = 8,
+  Param         : ADDR_WIDTH
+  -----------------------------------------------------------------------------
+  Tag           : ParamName
+  Description   : Parameter name [Param] does not follow naming convention
+  Violation     : Lint:3274
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 240
+  Statement     :         NON_ATOM_PCKS =  (PORT_B>MIN_PCK_SIZE)?  (PORT_B/MIN_PCK_SIZE)+ OFFSET : 1,
+  Param         : NON_ATOM_PCKS
+  -----------------------------------------------------------------------------
+  Tag           : ParamName
+  Description   : Parameter name [Param] does not follow naming convention
+  Violation     : Lint:3276
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 245
+  Statement     :         ELw = log2(T3),
+  Param         : ELw
+  -----------------------------------------------------------------------------
+  Tag           : ParamName
+  Description   : Parameter name [Param] does not follow naming convention
+  Violation     : Lint:3259
+  Goal          : lint_rtl
+  Module        : binary_mux
+  FileName      : ./../../rtl/src_noc/./../main_comp.v
+  LineNumber    : 316
+  Statement     :         SEL_WIDTH_BIN = (IN_NUM>1) ? log2(IN_NUM): 1; 
+  Param         : SEL_WIDTH_BIN
+  -----------------------------------------------------------------------------
+  Tag           : ParamName
+  Description   : Parameter name [Param] does not follow naming convention
+  Violation     : Lint:3283
+  Goal          : lint_rtl
+  Module        : mesh_torus_deterministic_look_ahead_routing
+  FileName      : ./../../rtl/src_noc/./mesh_torus_routting.v
+  LineNumber    : 131
+  Statement     :         Xw = log2(NX),   // number of node in x axis
+  Param         : Xw
+  -----------------------------------------------------------------------------
+  Tag           : ParamName
+  Description   : Parameter name [Param] does not follow naming convention
+  Violation     : Lint:3318
+  Goal          : lint_rtl
+  Module        : look_ahead_routing
+  FileName      : ./../../rtl/src_noc/./routing.v
+  LineNumber    : 300
+  Statement     :         localparam SL_SW_LOC = ( SW_LOC > P-T3) ? 0 : SW_LOC; //single_local
+  Param         : SL_SW_LOC
+  -----------------------------------------------------------------------------
+  Tag           : ParamName
+  Description   : Parameter name [Param] does not follow naming convention
+  Violation     : Lint:3301
+  Goal          : lint_rtl
+  Module        : conventional_routing
+  FileName      : ./../../rtl/src_noc/./routing.v
+  LineNumber    : 74
+  Statement     :             RXw = log2(NX),
+  Param         : RXw
+  -----------------------------------------------------------------------------
+  Tag           : ParamName
+  Description   : Parameter name [Param] does not follow naming convention
+  Violation     : Lint:3238
+  Goal          : lint_rtl
+  Module        : fwft_fifo
+  FileName      : ./../../rtl/src_noc/./flit_buffer.sv
+  LineNumber    : 549
+  Statement     :     parameter DATA_WIDTH = 2,
+  Param         : DATA_WIDTH
+  -----------------------------------------------------------------------------
+  Tag           : ParamName
+  Description   : Parameter name [Param] does not follow naming convention
+  Violation     : Lint:3332
+  Goal          : lint_rtl
+  Module        : flit_buffer
+  FileName      : ./../../rtl/src_noc/./flit_buffer.sv
+  LineNumber    : 64
+  Statement     :         PTRw = ((2**Bw)==B)? Bw : BVw, // if B is power of 2 PTRw is Bw else is BVw
+  Param         : PTRw
+  -----------------------------------------------------------------------------
+  Tag           : ParamName
+  Description   : Parameter name [Param] does not follow naming convention
+  Violation     : Lint:3214
+  Goal          : lint_rtl
+  Module        : congestion_out_gen
+  FileName      : ./../../rtl/src_noc/./congestion_analyzer.v
+  LineNumber    : 950
+  Statement     :     parameter CONGESTION_INDEX=2,
+  Param         : CONGESTION_INDEX
+  -----------------------------------------------------------------------------
+  Tag           : ParamName
+  Description   : Parameter name [Param] does not follow naming convention
+  Violation     : Lint:3339
+  Goal          : lint_rtl
+  Module        : mesh_tori_endp_addr_decode
+  FileName      : ./../../rtl/src_noc/./mesh_torus.sv
+  LineNumber    : 954
+  Statement     :         EXw = log2(NX),    // number of node in x axis
+  Param         : EXw
+  -----------------------------------------------------------------------------
+  Tag           : ParamName
+  Description   : Parameter name [Param] does not follow naming convention
+  Violation     : Lint:3296
+  Goal          : lint_rtl
+  Module        : congestion_out_gen
+  FileName      : ./../../rtl/src_noc/./congestion_analyzer.v
+  LineNumber    : 963
+  Statement     :     CONG_ALw = CONGw* P;   //  congestion width per router;;
+  Param         : CONG_ALw
+  -----------------------------------------------------------------------------
+  Tag           : ParamName
+  Description   : Parameter name [Param] does not follow naming convention
+  Violation     : Lint:3284
+  Goal          : lint_rtl
+  Module        : mesh_torus_deterministic_look_ahead_routing
+  FileName      : ./../../rtl/src_noc/./mesh_torus_routting.v
+  LineNumber    : 132
+  Statement     :         Yw = (TOPOLOGY=="RING" || TOPOLOGY == "LINE") ? 1 : log2(NY);    // number of node in y axis
+  Param         : Yw
+  -----------------------------------------------------------------------------
+  Tag           : ParamName
+  Description   : Parameter name [Param] does not follow naming convention
+  Violation     : Lint:3319
+  Goal          : lint_rtl
+  Module        : router_two_stage
+  FileName      : ./../../rtl/src_noc/./router_two_stage.sv
+  LineNumber    : 87
+  Statement     :         PFw = P*Fw,
+  Param         : PFw
+  -----------------------------------------------------------------------------
+  Tag           : ParamName
+  Description   : Parameter name [Param] does not follow naming convention
+  Violation     : Lint:3174
+  Goal          : lint_rtl
+  Module        : binary_mux
+  FileName      : ./../../rtl/src_noc/./../main_comp.v
+  LineNumber    : 299
+  Statement     :     parameter OUT_WIDTH = 5
+  Param         : OUT_WIDTH
+  -----------------------------------------------------------------------------
+  Tag           : ParamName
+  Description   : Parameter name [Param] does not follow naming convention
+  Violation     : Lint:3184
+  Goal          : lint_rtl
+  Module        : swa_input_port_arbiter
+  FileName      : ./../../rtl/src_noc/./comb_nonspec.sv
+  LineNumber    : 617
+  Statement     :     parameter ARBITER_TYPE = "WRRA"// RRA, WRRA
+  Param         : ARBITER_TYPE
+  -----------------------------------------------------------------------------
+  Tag           : ParamName
+  Description   : Parameter name [Param] does not follow naming convention
+  Violation     : Lint:3278
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 247
+  Statement     :         PLw = (IS_FMESH) ? Pw : ELw,
+  Param         : PLw
+  -----------------------------------------------------------------------------
+  Tag           : ParamName
+  Description   : Parameter name [Param] does not follow naming convention
+  Violation     : Lint:3313
+  Goal          : lint_rtl
+  Module        : look_ahead_routing
+  FileName      : ./../../rtl/src_noc/./routing.v
+  LineNumber    : 275
+  Statement     :         PLKw = P * LKw;
+  Param         : PLKw
+  -----------------------------------------------------------------------------
+  Tag           : ParamName
+  Description   : Parameter name [Param] does not follow naming convention
+  Violation     : Lint:3243
+  Goal          : lint_rtl
+  Module        : mesh_torus_mask_non_assignable_destport_no_self_loop
+  FileName      : ./../../rtl/src_noc/./mesh_torus.sv
+  LineNumber    : 282
+  Statement     :     parameter ROUTE_NAME="DOR",
+  Param         : ROUTE_NAME
+  -----------------------------------------------------------------------------
+  Tag           : ParamName
+  Description   : Parameter name [Param] does not follow naming convention
+  Violation     : Lint:3280
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 249
+  Statement     :         PRAw= P * RAw;
+  Param         : PRAw
+  -----------------------------------------------------------------------------
+  Tag           : ParamName
+  Description   : Parameter name [Param] does not follow naming convention
+  Violation     : Lint:3229
+  Goal          : lint_rtl
+  Module        : look_ahead_routing
+  FileName      : ./../../rtl/src_noc/./routing.v
+  LineNumber    : 241
+  Statement     :     parameter DSTPw=P-1,
+  Param         : DSTPw
+  -----------------------------------------------------------------------------
+  Tag           : ParamName
+  Description   : Parameter name [Param] does not follow naming convention
+  Violation     : Lint:3311
+  Goal          : lint_rtl
+  Module        : look_ahead_routing
+  FileName      : ./../../rtl/src_noc/./routing.v
+  LineNumber    : 273
+  Statement     :         LKw= T2 * Kw,
+  Param         : LKw
+  -----------------------------------------------------------------------------
+  Tag           : ParamName
+  Description   : Parameter name [Param] does not follow naming convention
+  Violation     : Lint:3337
+  Goal          : lint_rtl
+  Module        : mesh_tori_router_addr_decode
+  FileName      : ./../../rtl/src_noc/./mesh_torus.sv
+  LineNumber    : 902
+  Statement     :         RXw = log2(NX),    // number of node in x axis
+  Param         : RXw
+  -----------------------------------------------------------------------------
+  Tag           : ParamName
+  Description   : Parameter name [Param] does not follow naming convention
+  Violation     : Lint:3182
+  Goal          : lint_rtl
+  Module        : nonspec_sw_alloc
+  FileName      : ./../../rtl/src_noc/./comb_nonspec.sv
+  LineNumber    : 431
+  Statement     :     parameter SELF_LOOP_EN=0
+  Param         : SELF_LOOP_EN
+  -----------------------------------------------------------------------------
+  Tag           : ParamName
+  Description   : Parameter name [Param] does not follow naming convention
+  Violation     : Lint:3241
+  Goal          : lint_rtl
+  Module        : mesh_torus_mask_non_assignable_destport
+  FileName      : ./../../rtl/src_noc/./mesh_torus.sv
+  LineNumber    : 225
+  Statement     :     parameter ROUTE_NAME="DOR",
+  Param         : ROUTE_NAME
+  -----------------------------------------------------------------------------
+  Tag           : ParamName
+  Description   : Parameter name [Param] does not follow naming convention
+  Violation     : Lint:3165
+  Goal          : lint_rtl
+  Module        : one_hot_mux
+  FileName      : ./../../rtl/src_noc/./../main_comp.v
+  LineNumber    : 114
+  Statement     :     parameter   SEL_WIDTH = 5, 
+  Param         : SEL_WIDTH
+  -----------------------------------------------------------------------------
+  Tag           : ParamName
+  Description   : Parameter name [Param] does not follow naming convention
+  Violation     : Lint:3287
+  Goal          : lint_rtl
+  Module        : mesh_torus_next_router_addr_predictor
+  FileName      : ./../../rtl/src_noc/./mesh_torus_routting.v
+  LineNumber    : 357
+  Statement     :     localparam [Xw-1 : 0] LAST_X_ADDR =(NX[Xw-1 : 0]-1'b1);
+  Param         : LAST_X_ADDR
+  -----------------------------------------------------------------------------
+  Tag           : ParamName
+  Description   : Parameter name [Param] does not follow naming convention
+  Violation     : Lint:3203
+  Goal          : lint_rtl
+  Module        : mesh_torus_conventional_routing
+  FileName      : ./../../rtl/src_noc/./mesh_torus_routting.v
+  LineNumber    : 600
+  Statement     :     parameter ROUTE_TYPE = "DETERMINISTIC",    
+  Param         : ROUTE_TYPE
+  -----------------------------------------------------------------------------
+  Tag           : ParamName
+  Description   : Parameter name [Param] does not follow naming convention
+  Violation     : Lint:3308
+  Goal          : lint_rtl
+  Module        : look_ahead_routing
+  FileName      : ./../../rtl/src_noc/./routing.v
+  LineNumber    : 267
+  Statement     :         PRAw= P * RAw;
+  Param         : PRAw
+  -----------------------------------------------------------------------------
+  Tag           : ParamName
+  Description   : Parameter name [Param] does not follow naming convention
+  Violation     : Lint:3273
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 231
+  Statement     :         VDSTPw = V * DSTPw,
+  Param         : VDSTPw
+  -----------------------------------------------------------------------------
+  Tag           : ParamName
+  Description   : Parameter name [Param] does not follow naming convention
+  Violation     : Lint:3309
+  Goal          : lint_rtl
+  Module        : look_ahead_routing
+  FileName      : ./../../rtl/src_noc/./routing.v
+  LineNumber    : 271
+  Statement     :         Kw = log2(T1),
+  Param         : Kw
+  -----------------------------------------------------------------------------
+  Tag           : ParamName
+  Description   : Parameter name [Param] does not follow naming convention
+  Violation     : Lint:3314
+  Goal          : lint_rtl
+  Module        : look_ahead_routing
+  FileName      : ./../../rtl/src_noc/./routing.v
+  LineNumber    : 292
+  Statement     :             RXw = log2(NX),
+  Param         : RXw
+  -----------------------------------------------------------------------------
+  Tag           : ParamName
+  Description   : Parameter name [Param] does not follow naming convention
+  Violation     : Lint:3207
+  Goal          : lint_rtl
+  Module        : smart_credit_manage_per_vc
+  FileName      : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber    : 745
+  Statement     :     parameter Bw=2
+  Param         : Bw
+  -----------------------------------------------------------------------------
+  Tag           : ParamName
+  Description   : Parameter name [Param] does not follow naming convention
+  Violation     : Lint:3252
+  Goal          : lint_rtl
+  Module        : line_ring_destp_decoder
+  FileName      : ./../../rtl/src_noc/./mesh_torus.sv
+  LineNumber    : 1291
+  Statement     :     parameter ROUTE_TYPE="DETERMINISTIC",
+  Param         : ROUTE_TYPE
+  -----------------------------------------------------------------------------
+  Tag           : ParamName
+  Description   : Parameter name [Param] does not follow naming convention
+  Violation     : Lint:3171
+  Goal          : lint_rtl
+  Module        : bin_to_one_hot
+  FileName      : ./../../rtl/src_noc/./../main_comp.v
+  LineNumber    : 238
+  Statement     :     parameter ONE_HOT_WIDTH = 2**BIN_WIDTH
+  Param         : ONE_HOT_WIDTH
+  -----------------------------------------------------------------------------
+  Tag           : ParamName
+  Description   : Parameter name [Param] does not follow naming convention
+  Violation     : Lint:3249
+  Goal          : lint_rtl
+  Module        : mesh_torus_destp_generator
+  FileName      : ./../../rtl/src_noc/./mesh_torus.sv
+  LineNumber    : 1120
+  Statement     :     parameter PLw=1,
+  Param         : PLw
+  -----------------------------------------------------------------------------
+  Tag           : ParamName
+  Description   : Parameter name [Param] does not follow naming convention
+  Violation     : Lint:3193
+  Goal          : lint_rtl
+  Module        : destp_generator
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 1092
+  Statement     :     parameter ROUTE_TYPE="DETERMINISTIC",
+  Param         : ROUTE_TYPE
+  -----------------------------------------------------------------------------
+  Tag           : ParamName
+  Description   : Parameter name [Param] does not follow naming convention
+  Violation     : Lint:3172
+  Goal          : lint_rtl
+  Module        : one_hot_to_bin
+  FileName      : ./../../rtl/src_noc/./../main_comp.v
+  LineNumber    : 256
+  Statement     :     parameter ONE_HOT_WIDTH = 4,
+  Param         : ONE_HOT_WIDTH
+  -----------------------------------------------------------------------------
+  Tag           : ParamName
+  Description   : Parameter name [Param] does not follow naming convention
+  Violation     : Lint:3264
+  Goal          : lint_rtl
+  Module        : inout_ports
+  FileName      : ./../../rtl/src_noc/./inout_ports.sv
+  LineNumber    : 98
+  Statement     :         PFw = P * Fw,
+  Param         : PFw
+  -----------------------------------------------------------------------------
+  Tag           : ParamName
+  Description   : Parameter name [Param] does not follow naming convention
+  Violation     : Lint:3253
+  Goal          : lint_rtl
+  Module        : line_ring_destp_decoder
+  FileName      : ./../../rtl/src_noc/./mesh_torus.sv
+  LineNumber    : 1293
+  Statement     :     parameter DSTPw=2,
+  Param         : DSTPw
+  -----------------------------------------------------------------------------
+  Tag           : ParamName
+  Description   : Parameter name [Param] does not follow naming convention
+  Violation     : Lint:3325
+  Goal          : lint_rtl
+  Module        : flit_buffer
+  FileName      : ./../../rtl/src_noc/./flit_buffer.sv
+  LineNumber    : 56
+  Statement     :         Bw = (B==1)? 1 : log2(B),
+  Param         : Bw
+  -----------------------------------------------------------------------------
+  Tag           : ParamName
+  Description   : Parameter name [Param] does not follow naming convention
+  Violation     : Lint:3291
+  Goal          : lint_rtl
+  Module        : mesh_torus_conventional_routing
+  FileName      : ./../../rtl/src_noc/./mesh_torus_routting.v
+  LineNumber    : 628
+  Statement     :         DSTw = P_1;               
+  Param         : DSTw
+  -----------------------------------------------------------------------------
+  Tag           : ParamName
+  Description   : Parameter name [Param] does not follow naming convention
+  Violation     : Lint:3316
+  Goal          : lint_rtl
+  Module        : look_ahead_routing
+  FileName      : ./../../rtl/src_noc/./routing.v
+  LineNumber    : 294
+  Statement     :             EXw = RXw,
+  Param         : EXw
+  -----------------------------------------------------------------------------
+  Tag           : ParamName
+  Description   : Parameter name [Param] does not follow naming convention
+  Violation     : Lint:3290
+  Goal          : lint_rtl
+  Module        : mesh_torus_conventional_routing
+  FileName      : ./../../rtl/src_noc/./mesh_torus_routting.v
+  LineNumber    : 627
+  Statement     :         Xw = log2(NX),        
+  Param         : Xw
+  -----------------------------------------------------------------------------
+  Tag           : ParamName
+  Description   : Parameter name [Param] does not follow naming convention
+  Violation     : Lint:3224
+  Goal          : lint_rtl
+  Module        : conventional_routing
+  FileName      : ./../../rtl/src_noc/./routing.v
+  LineNumber    : 41
+  Statement     :     parameter DSTPw             = 4,
+  Param         : DSTPw
+  -----------------------------------------------------------------------------
+  Tag           : ParamName
+  Description   : Parameter name [Param] does not follow naming convention
+  Violation     : Lint:3202
+  Goal          : lint_rtl
+  Module        : mesh_torus_conventional_routing
+  FileName      : ./../../rtl/src_noc/./mesh_torus_routting.v
+  LineNumber    : 599
+  Statement     :     parameter ROUTE_NAME = "DOR",
+  Param         : ROUTE_NAME
+  -----------------------------------------------------------------------------
+  Tag           : ParamName
+  Description   : Parameter name [Param] does not follow naming convention
+  Violation     : Lint:3170
+  Goal          : lint_rtl
+  Module        : bin_to_one_hot
+  FileName      : ./../../rtl/src_noc/./../main_comp.v
+  LineNumber    : 237
+  Statement     :     parameter BIN_WIDTH = 2,
+  Param         : BIN_WIDTH
+  -----------------------------------------------------------------------------
+  Tag           : ParamName
+  Description   : Parameter name [Param] does not follow naming convention
+  Violation     : Lint:3195
+  Goal          : lint_rtl
+  Module        : destp_generator
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 1097
+  Statement     :     parameter PLw=1,
+  Param         : PLw
+  -----------------------------------------------------------------------------
+  Tag           : ParamName
+  Description   : Parameter name [Param] does not follow naming convention
+  Violation     : Lint:3235
+  Goal          : lint_rtl
+  Module        : crossbar
+  FileName      : ./../../rtl/src_noc/./crossbar.v
+  LineNumber    : 36
+  Statement     :     parameter SELF_LOOP_EN= 0
+  Param         : SELF_LOOP_EN
+  -----------------------------------------------------------------------------
+  Tag           : ParamName
+  Description   : Parameter name [Param] does not follow naming convention
+  Violation     : Lint:3277
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 246
+  Statement     :         Pw  = log2(P),
+  Param         : Pw
+  -----------------------------------------------------------------------------
+  Tag           : ParamName
+  Description   : Parameter name [Param] does not follow naming convention
+  Violation     : Lint:3248
+  Goal          : lint_rtl
+  Module        : mesh_torus_destp_generator
+  FileName      : ./../../rtl/src_noc/./mesh_torus.sv
+  LineNumber    : 1118
+  Statement     :     parameter DSTPw=4,
+  Param         : DSTPw
+  -----------------------------------------------------------------------------
+  Tag           : ParamName
+  Description   : Parameter name [Param] does not follow naming convention
+  Violation     : Lint:3181
+  Goal          : lint_rtl
+  Module        : nonspec_sw_alloc
+  FileName      : ./../../rtl/src_noc/./comb_nonspec.sv
+  LineNumber    : 430
+  Statement     :     parameter MIN_PCK_SIZE=2, //minimum packet size in flits. The minimum value is 1.
+  Param         : MIN_PCK_SIZE
+  -----------------------------------------------------------------------------
+  Tag           : ParamName
+  Description   : Parameter name [Param] does not follow naming convention
+  Violation     : Lint:3271
+  Goal          : lint_rtl
+  Module        : input_ports
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 87
+  Statement     :         PRAw= P * RAw;    
+  Param         : PRAw
+  -----------------------------------------------------------------------------
+  Tag           : ParamName
+  Description   : Parameter name [Param] does not follow naming convention
+  Violation     : Lint:3176
+  Goal          : lint_rtl
+  Module        : arbiter_priority_en
+  FileName      : ./../../rtl/src_noc/./../arbiter.v
+  LineNumber    : 89
+  Statement     :     parameter    ARBITER_WIDTH    =8
+  Param         : ARBITER_WIDTH
+  -----------------------------------------------------------------------------
+  Tag           : ParamName
+  Description   : Parameter name [Param] does not follow naming convention
+  Violation     : Lint:3180
+  Goal          : lint_rtl
+  Module        : nonspec_sw_alloc
+  FileName      : ./../../rtl/src_noc/./comb_nonspec.sv
+  LineNumber    : 429
+  Statement     :     parameter SWA_ARBITER_TYPE = "WRRA",
+  Param         : SWA_ARBITER_TYPE
+
+  -----------------------------------------------------------------------------
+  PortName  (155 warnings/0 waived)
+  -----------------------------------------------------------------------------
+  Tag            : PortName
+  Description    : Port [Mod_Port_Name] does not follow naming convention
+  Violation      : Lint:3042
+  Goal           : lint_rtl
+  Module         : inout_ports
+  FileName       : ./../../rtl/src_noc/./inout_ports.sv
+  LineNumber     : 57
+  Statement      :     granted_dest_port_all,
+  Mod_Port_Name  : granted_dest_port_all
+  -----------------------------------------------------------------------------
+  Tag            : PortName
+  Description    : Port [Mod_Port_Name] does not follow naming convention
+  Violation      : Lint:3073
+  Goal           : lint_rtl
+  Module         : input_queue_per_port
+  FileName       : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber     : 189
+  Statement      :     ivc_num_getting_sw_grant,// for non spec ivc_num_getting_first_sw_grant,
+  Mod_Port_Name  : ivc_num_getting_sw_grant
+  -----------------------------------------------------------------------------
+  Tag            : PortName
+  Description    : Port [Mod_Port_Name] does not follow naming convention
+  Violation      : Lint:3106
+  Goal           : lint_rtl
+  Module         : smart_validity_check_per_ivc
+  FileName       : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber     : 447
+  Statement      :     smart_single_flit_pck_o,
+  Mod_Port_Name  : smart_single_flit_pck_o
+  -----------------------------------------------------------------------------
+  Tag            : PortName
+  Description    : Port [Mod_Port_Name] does not follow naming convention
+  Violation      : Lint:3054
+  Goal           : lint_rtl
+  Module         : inout_ports
+  FileName       : ./../../rtl/src_noc/./inout_ports.sv
+  LineNumber     : 81
+  Statement      :     vsa_credit_decreased_all,
+  Mod_Port_Name  : vsa_credit_decreased_all
+  -----------------------------------------------------------------------------
+  Tag            : PortName
+  Description    : Port [Mod_Port_Name] does not follow naming convention
+  Violation      : Lint:3052
+  Goal           : lint_rtl
+  Module         : inout_ports
+  FileName       : ./../../rtl/src_noc/./inout_ports.sv
+  LineNumber     : 77
+  Statement      :     refresh_w_counter,
+  Mod_Port_Name  : refresh_w_counter
+  -----------------------------------------------------------------------------
+  Tag            : PortName
+  Description    : Port [Mod_Port_Name] does not follow naming convention
+  Violation      : Lint:3126
+  Goal           : lint_rtl
+  Module         : smart_allocator_per_iport
+  FileName       : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber     : 564
+  Statement      :     smart_mask_available_ss_ovc_o,
+  Mod_Port_Name  : smart_mask_available_ss_ovc_o
+  -----------------------------------------------------------------------------
+  Tag            : PortName
+  Description    : Port [Mod_Port_Name] does not follow naming convention
+  Violation      : Lint:3107
+  Goal           : lint_rtl
+  Module         : smart_validity_check_per_ivc
+  FileName       : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber     : 448
+  Statement      :     smart_ivc_smart_en_o,
+  Mod_Port_Name  : smart_ivc_smart_en_o
+  -----------------------------------------------------------------------------
+  Tag            : PortName
+  Description    : Port [Mod_Port_Name] does not follow naming convention
+  Violation      : Lint:3131
+  Goal           : lint_rtl
+  Module         : port_pre_sel_gen
+  FileName       : ./../../rtl/src_noc/./congestion_analyzer.v
+  LineNumber     : 339
+  Statement      :     congestion_in_all,
+  Mod_Port_Name  : congestion_in_all
+  -----------------------------------------------------------------------------
+  Tag            : PortName
+  Description    : Port [Mod_Port_Name] does not follow naming convention
+  Violation      : Lint:3058
+  Goal           : lint_rtl
+  Module         : vc_alloc_request_gen
+  FileName       : ./../../rtl/src_noc/./inout_ports.sv
+  LineNumber     : 445
+  Statement      :     ivc_num_getting_ovc_grant, 
+  Mod_Port_Name  : ivc_num_getting_ovc_grant
+  -----------------------------------------------------------------------------
+  Tag            : PortName
+  Description    : Port [Mod_Port_Name] does not follow naming convention
+  Violation      : Lint:3134
+  Goal           : lint_rtl
+  Module         : congestion_out_gen
+  FileName       : ./../../rtl/src_noc/./congestion_analyzer.v
+  LineNumber     : 954
+  Statement      :     ivc_num_getting_sw_grant,
+  Mod_Port_Name  : ivc_num_getting_sw_grant
+  -----------------------------------------------------------------------------
+  Tag            : PortName
+  Description    : Port [Mod_Port_Name] does not follow naming convention
+  Violation      : Lint:3024
+  Goal           : lint_rtl
+  Module         : nonspec_sw_alloc
+  FileName       : ./../../rtl/src_noc/./comb_nonspec.sv
+  LineNumber     : 439
+  Statement      :     first_arbiter_granted_ivc_all,
+  Mod_Port_Name  : first_arbiter_granted_ivc_all
+  -----------------------------------------------------------------------------
+  Tag            : PortName
+  Description    : Port [Mod_Port_Name] does not follow naming convention
+  Violation      : Lint:3080
+  Goal           : lint_rtl
+  Module         : input_queue_per_port
+  FileName       : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber     : 212
+  Statement      :     granted_dest_port,
+  Mod_Port_Name  : granted_dest_port
+  -----------------------------------------------------------------------------
+  Tag            : PortName
+  Description    : Port [Mod_Port_Name] does not follow naming convention
+  Violation      : Lint:3141
+  Goal           : lint_rtl
+  Module         : output_ports
+  FileName       : ./../../rtl/src_noc/./output_ports.sv
+  LineNumber     : 43
+  Statement      :     congestion_in_all,    
+  Mod_Port_Name  : congestion_in_all
+  -----------------------------------------------------------------------------
+  Tag            : PortName
+  Description    : Port [Mod_Port_Name] does not follow naming convention
+  Violation      : Lint:3035
+  Goal           : lint_rtl
+  Module         : inout_ports
+  FileName       : ./../../rtl/src_noc/./inout_ports.sv
+  LineNumber     : 49
+  Statement      :     vsa_ovc_allocated_all,
+  Mod_Port_Name  : vsa_ovc_allocated_all
+  -----------------------------------------------------------------------------
+  Tag            : PortName
+  Description    : Port [Mod_Port_Name] does not follow naming convention
+  Violation      : Lint:3153
+  Goal           : lint_rtl
+  Module         : full_ovc_predictor
+  FileName       : ./../../rtl/src_noc/./output_ports.sv
+  LineNumber     : 537
+  Statement      :     ssa_granted_ovc_num,
+  Mod_Port_Name  : ssa_granted_ovc_num
+  -----------------------------------------------------------------------------
+  Tag            : PortName
+  Description    : Port [Mod_Port_Name] does not follow naming convention
+  Violation      : Lint:3111
+  Goal           : lint_rtl
+  Module         : smart_validity_check_per_ivc
+  FileName       : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber     : 453
+  Statement      :     smart_mask_available_ss_ovc_o, 
+  Mod_Port_Name  : smart_mask_available_ss_ovc_o
+  -----------------------------------------------------------------------------
+  Tag            : PortName
+  Description    : Port [Mod_Port_Name] does not follow naming convention
+  Violation      : Lint:3045
+  Goal           : lint_rtl
+  Module         : inout_ports
+  FileName       : ./../../rtl/src_noc/./inout_ports.sv
+  LineNumber     : 60
+  Statement      :     granted_dst_is_from_a_single_flit_pck,
+  Mod_Port_Name  : granted_dst_is_from_a_single_flit_pck
+  -----------------------------------------------------------------------------
+  Tag            : PortName
+  Description    : Port [Mod_Port_Name] does not follow naming convention
+  Violation      : Lint:3105
+  Goal           : lint_rtl
+  Module         : smart_validity_check_per_ivc
+  FileName       : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber     : 445
+  Statement      :     ss_ovc_crossbar_wr,
+  Mod_Port_Name  : ss_ovc_crossbar_wr
+  -----------------------------------------------------------------------------
+  Tag            : PortName
+  Description    : Port [Mod_Port_Name] does not follow naming convention
+  Violation      : Lint:3037
+  Goal           : lint_rtl
+  Module         : inout_ports
+  FileName       : ./../../rtl/src_noc/./inout_ports.sv
+  LineNumber     : 51
+  Statement      :     ivc_num_getting_ovc_grant,
+  Mod_Port_Name  : ivc_num_getting_ovc_grant
+  -----------------------------------------------------------------------------
+  Tag            : PortName
+  Description    : Port [Mod_Port_Name] does not follow naming convention
+  Violation      : Lint:3156
+  Goal           : lint_rtl
+  Module         : look_ahead_routing
+  FileName       : ./../../rtl/src_noc/./routing.v
+  LineNumber     : 252
+  Statement      :     lkdestport_encoded, // look ahead destination port number
+  Mod_Port_Name  : lkdestport_encoded
+  -----------------------------------------------------------------------------
+  Tag            : PortName
+  Description    : Port [Mod_Port_Name] does not follow naming convention
+  Violation      : Lint:3038
+  Goal           : lint_rtl
+  Module         : inout_ports
+  FileName       : ./../../rtl/src_noc/./inout_ports.sv
+  LineNumber     : 53
+  Statement      :     nonspec_first_arbiter_granted_ivc_all,
+  Mod_Port_Name  : nonspec_first_arbiter_granted_ivc_all
+  -----------------------------------------------------------------------------
+  Tag            : PortName
+  Description    : Port [Mod_Port_Name] does not follow naming convention
+  Violation      : Lint:3009
+  Goal           : lint_rtl
+  Module         : comb_nonspec_allocator
+  FileName       : ./../../rtl/src_noc/./comb_nonspec.sv
+  LineNumber     : 42
+  Statement      :     ovc_allocated_all,//to the output port
+  Mod_Port_Name  : ovc_allocated_all
+  -----------------------------------------------------------------------------
+  Tag            : PortName
+  Description    : Port [Mod_Port_Name] does not follow naming convention
+  Violation      : Lint:3074
+  Goal           : lint_rtl
+  Module         : input_queue_per_port
+  FileName       : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber     : 190
+  Statement      :     any_ivc_sw_request_granted,
+  Mod_Port_Name  : any_ivc_sw_request_granted
+  -----------------------------------------------------------------------------
+  Tag            : PortName
+  Description    : Port [Mod_Port_Name] does not follow naming convention
+  Violation      : Lint:3133
+  Goal           : lint_rtl
+  Module         : port_pre_sel_gen
+  FileName       : ./../../rtl/src_noc/./congestion_analyzer.v
+  LineNumber     : 341
+  Statement      :     credit_increased_all,
+  Mod_Port_Name  : credit_increased_all
+  -----------------------------------------------------------------------------
+  Tag            : PortName
+  Description    : Port [Mod_Port_Name] does not follow naming convention
+  Violation      : Lint:3044
+  Goal           : lint_rtl
+  Module         : inout_ports
+  FileName       : ./../../rtl/src_noc/./inout_ports.sv
+  LineNumber     : 59
+  Statement      :     any_ovc_granted_in_outport_all,
+  Mod_Port_Name  : any_ovc_granted_in_outport_all
+  -----------------------------------------------------------------------------
+  Tag            : PortName
+  Description    : Port [Mod_Port_Name] does not follow naming convention
+  Violation      : Lint:3132
+  Goal           : lint_rtl
+  Module         : port_pre_sel_gen
+  FileName       : ./../../rtl/src_noc/./congestion_analyzer.v
+  LineNumber     : 340
+  Statement      :     credit_decreased_all,
+  Mod_Port_Name  : credit_decreased_all
+  -----------------------------------------------------------------------------
+  Tag            : PortName
+  Description    : Port [Mod_Port_Name] does not follow naming convention
+  Violation      : Lint:3149
+  Goal           : lint_rtl
+  Module         : credit_monitor_per_ovc
+  FileName       : ./../../rtl/src_noc/./output_ports.sv
+  LineNumber     : 401
+  Statement      :     credit_init_val_i,
+  Mod_Port_Name  : credit_init_val_i
+  -----------------------------------------------------------------------------
+  Tag            : PortName
+  Description    : Port [Mod_Port_Name] does not follow naming convention
+  Violation      : Lint:3053
+  Goal           : lint_rtl
+  Module         : inout_ports
+  FileName       : ./../../rtl/src_noc/./inout_ports.sv
+  LineNumber     : 78
+  Statement      :     crossbar_flit_out_wr_all,
+  Mod_Port_Name  : crossbar_flit_out_wr_all
+  -----------------------------------------------------------------------------
+  Tag            : PortName
+  Description    : Port [Mod_Port_Name] does not follow naming convention
+  Violation      : Lint:3039
+  Goal           : lint_rtl
+  Module         : inout_ports
+  FileName       : ./../../rtl/src_noc/./inout_ports.sv
+  LineNumber     : 54
+  Statement      :     spec_first_arbiter_granted_ivc_all,
+  Mod_Port_Name  : spec_first_arbiter_granted_ivc_all
+  -----------------------------------------------------------------------------
+  Tag            : PortName
+  Description    : Port [Mod_Port_Name] does not follow naming convention
+  Violation      : Lint:3092
+  Goal           : lint_rtl
+  Module         : combined_vc_sw_alloc
+  FileName       : ./../../rtl/src_noc/./combined_vc_sw_alloc.sv
+  LineNumber     : 43
+  Statement      :     spec_granted_dest_port_all,
+  Mod_Port_Name  : spec_granted_dest_port_all
+  -----------------------------------------------------------------------------
+  Tag            : PortName
+  Description    : Port [Mod_Port_Name] does not follow naming convention
+  Violation      : Lint:3028
+  Goal           : lint_rtl
+  Module         : nonspec_sw_alloc
+  FileName       : ./../../rtl/src_noc/./comb_nonspec.sv
+  LineNumber     : 444
+  Statement      :     iport_weight_is_consumed_all,
+  Mod_Port_Name  : iport_weight_is_consumed_all
+  -----------------------------------------------------------------------------
+  Tag            : PortName
+  Description    : Port [Mod_Port_Name] does not follow naming convention
+  Violation      : Lint:3136
+  Goal           : lint_rtl
+  Module         : output_ports
+  FileName       : ./../../rtl/src_noc/./output_ports.sv
+  LineNumber     : 33
+  Statement      :     vsa_ovc_allocated_all,
+  Mod_Port_Name  : vsa_ovc_allocated_all
+  -----------------------------------------------------------------------------
+  Tag            : PortName
+  Description    : Port [Mod_Port_Name] does not follow naming convention
+  Violation      : Lint:3055
+  Goal           : lint_rtl
+  Module         : inout_ports
+  FileName       : ./../../rtl/src_noc/./inout_ports.sv
+  LineNumber     : 82
+  Statement      :     vsa_ovc_released_all,
+  Mod_Port_Name  : vsa_ovc_released_all
+  -----------------------------------------------------------------------------
+  Tag            : PortName
+  Description    : Port [Mod_Port_Name] does not follow naming convention
+  Violation      : Lint:3104
+  Goal           : lint_rtl
+  Module         : smart_validity_check_per_ivc
+  FileName       : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber     : 444
+  Statement      :     ss_port_link_reg_flit_wr,
+  Mod_Port_Name  : ss_port_link_reg_flit_wr
+  -----------------------------------------------------------------------------
+  Tag            : PortName
+  Description    : Port [Mod_Port_Name] does not follow naming convention
+  Violation      : Lint:3077
+  Goal           : lint_rtl
+  Module         : input_queue_per_port
+  FileName       : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber     : 209
+  Statement      :     vc_weight_is_consumed,
+  Mod_Port_Name  : vc_weight_is_consumed
+  -----------------------------------------------------------------------------
+  Tag            : PortName
+  Description    : Port [Mod_Port_Name] does not follow naming convention
+  Violation      : Lint:3020
+  Goal           : lint_rtl
+  Module         : nonspec_sw_alloc
+  FileName       : ./../../rtl/src_noc/./comb_nonspec.sv
+  LineNumber     : 434
+  Statement      :     ivc_request_masked_all,
+  Mod_Port_Name  : ivc_request_masked_all
+  -----------------------------------------------------------------------------
+  Tag            : PortName
+  Description    : Port [Mod_Port_Name] does not follow naming convention
+  Violation      : Lint:3108
+  Goal           : lint_rtl
+  Module         : smart_validity_check_per_ivc
+  FileName       : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber     : 450
+  Statement      :     smart_buff_space_decreased_o,
+  Mod_Port_Name  : smart_buff_space_decreased_o
+  -----------------------------------------------------------------------------
+  Tag            : PortName
+  Description    : Port [Mod_Port_Name] does not follow naming convention
+  Violation      : Lint:3012
+  Goal           : lint_rtl
+  Module         : comb_nonspec_allocator
+  FileName       : ./../../rtl/src_noc/./comb_nonspec.sv
+  LineNumber     : 48
+  Statement      :     vc_weight_is_consumed_all,
+  Mod_Port_Name  : vc_weight_is_consumed_all
+  -----------------------------------------------------------------------------
+  Tag            : PortName
+  Description    : Port [Mod_Port_Name] does not follow naming convention
+  Violation      : Lint:3135
+  Goal           : lint_rtl
+  Module         : congestion_out_gen
+  FileName       : ./../../rtl/src_noc/./congestion_analyzer.v
+  LineNumber     : 956
+  Statement      :     congestion_out_all,
+  Mod_Port_Name  : congestion_out_all
+  -----------------------------------------------------------------------------
+  Tag            : PortName
+  Description    : Port [Mod_Port_Name] does not follow naming convention
+  Violation      : Lint:3006
+  Goal           : lint_rtl
+  Module         : header_flit_update_lk_route_ovc
+  FileName       : ./../../rtl/src_noc/./header_flit.sv
+  LineNumber     : 205
+  Statement      :     lk_dest_not_registered,
+  Mod_Port_Name  : lk_dest_not_registered
+  -----------------------------------------------------------------------------
+  Tag            : PortName
+  Description    : Port [Mod_Port_Name] does not follow naming convention
+  Violation      : Lint:3018
+  Goal           : lint_rtl
+  Module         : comb_nonspec_allocator
+  FileName       : ./../../rtl/src_noc/./comb_nonspec.sv
+  LineNumber     : 56
+  Statement      :     any_ovc_granted_in_outport_all,
+  Mod_Port_Name  : any_ovc_granted_in_outport_all
+  -----------------------------------------------------------------------------
+  Tag            : PortName
+  Description    : Port [Mod_Port_Name] does not follow naming convention
+  Violation      : Lint:3057
+  Goal           : lint_rtl
+  Module         : vc_alloc_request_gen
+  FileName       : ./../../rtl/src_noc/./inout_ports.sv
+  LineNumber     : 438
+  Statement      :     masked_ovc_request_all,    
+  Mod_Port_Name  : masked_ovc_request_all
+  -----------------------------------------------------------------------------
+  Tag            : PortName
+  Description    : Port [Mod_Port_Name] does not follow naming convention
+  Violation      : Lint:3010
+  Goal           : lint_rtl
+  Module         : comb_nonspec_allocator
+  FileName       : ./../../rtl/src_noc/./comb_nonspec.sv
+  LineNumber     : 43
+  Statement      :     granted_ovc_num_all, // to the input port
+  Mod_Port_Name  : granted_ovc_num_all
+  -----------------------------------------------------------------------------
+  Tag            : PortName
+  Description    : Port [Mod_Port_Name] does not follow naming convention
+  Violation      : Lint:3097
+  Goal           : lint_rtl
+  Module         : combined_vc_sw_alloc
+  FileName       : ./../../rtl/src_noc/./combined_vc_sw_alloc.sv
+  LineNumber     : 49
+  Statement      :     granted_dst_is_from_a_single_flit_pck,
+  Mod_Port_Name  : granted_dst_is_from_a_single_flit_pck
+  -----------------------------------------------------------------------------
+  Tag            : PortName
+  Description    : Port [Mod_Port_Name] does not follow naming convention
+  Violation      : Lint:3120
+  Goal           : lint_rtl
+  Module         : smart_allocator_per_iport
+  FileName       : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber     : 557
+  Statement      :     smart_ivc_smart_en_o,
+  Mod_Port_Name  : smart_ivc_smart_en_o
+  -----------------------------------------------------------------------------
+  Tag            : PortName
+  Description    : Port [Mod_Port_Name] does not follow naming convention
+  Violation      : Lint:3148
+  Goal           : lint_rtl
+  Module         : output_ports
+  FileName       : ./../../rtl/src_noc/./output_ports.sv
+  LineNumber     : 58
+  Statement      :     credit_init_val_in
+  Mod_Port_Name  : credit_init_val_in
+  -----------------------------------------------------------------------------
+  Tag            : PortName
+  Description    : Port [Mod_Port_Name] does not follow naming convention
+  Violation      : Lint:3124
+  Goal           : lint_rtl
+  Module         : smart_allocator_per_iport
+  FileName       : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber     : 562
+  Statement      :     smart_ivc_num_getting_ovc_grant_o,
+  Mod_Port_Name  : smart_ivc_num_getting_ovc_grant_o
+  -----------------------------------------------------------------------------
+  Tag            : PortName
+  Description    : Port [Mod_Port_Name] does not follow naming convention
+  Violation      : Lint:3047
+  Goal           : lint_rtl
+  Module         : inout_ports
+  FileName       : ./../../rtl/src_noc/./inout_ports.sv
+  LineNumber     : 66
+  Statement      :     assigned_ovc_not_full_all,
+  Mod_Port_Name  : assigned_ovc_not_full_all
+  -----------------------------------------------------------------------------
+  Tag            : PortName
+  Description    : Port [Mod_Port_Name] does not follow naming convention
+  Violation      : Lint:3142
+  Goal           : lint_rtl
+  Module         : output_ports
+  FileName       : ./../../rtl/src_noc/./output_ports.sv
+  LineNumber     : 44
+  Statement      :     granted_dst_is_from_a_single_flit_pck,
+  Mod_Port_Name  : granted_dst_is_from_a_single_flit_pck
+  -----------------------------------------------------------------------------
+  Tag            : PortName
+  Description    : Port [Mod_Port_Name] does not follow naming convention
+  Violation      : Lint:3026
+  Goal           : lint_rtl
+  Module         : nonspec_sw_alloc
+  FileName       : ./../../rtl/src_noc/./comb_nonspec.sv
+  LineNumber     : 442
+  Statement      :     any_ovc_granted_all,
+  Mod_Port_Name  : any_ovc_granted_all
+  -----------------------------------------------------------------------------
+  Tag            : PortName
+  Description    : Port [Mod_Port_Name] does not follow naming convention
+  Violation      : Lint:3123
+  Goal           : lint_rtl
+  Module         : smart_allocator_per_iport
+  FileName       : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber     : 561
+  Statement      :     smart_ss_ovc_is_released_o, 
+  Mod_Port_Name  : smart_ss_ovc_is_released_o
+  -----------------------------------------------------------------------------
+  Tag            : PortName
+  Description    : Port [Mod_Port_Name] does not follow naming convention
+  Violation      : Lint:3060
+  Goal           : lint_rtl
+  Module         : vc_alloc_request_gen_determinstic
+  FileName       : ./../../rtl/src_noc/./inout_ports.sv
+  LineNumber     : 611
+  Statement      :     ovc_is_assigned_all,
+  Mod_Port_Name  : ovc_is_assigned_all
+  -----------------------------------------------------------------------------
+  Tag            : PortName
+  Description    : Port [Mod_Port_Name] does not follow naming convention
+  Violation      : Lint:3113
+  Goal           : lint_rtl
+  Module         : smart_validity_check_per_ivc
+  FileName       : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber     : 455
+  Statement      :     smart_ivc_reset_o,
+  Mod_Port_Name  : smart_ivc_reset_o
+  -----------------------------------------------------------------------------
+  Tag            : PortName
+  Description    : Port [Mod_Port_Name] does not follow naming convention
+  Violation      : Lint:3025
+  Goal           : lint_rtl
+  Module         : nonspec_sw_alloc
+  FileName       : ./../../rtl/src_noc/./comb_nonspec.sv
+  LineNumber     : 441
+  Statement      :     any_ivc_granted_all,
+  Mod_Port_Name  : any_ivc_granted_all
+  -----------------------------------------------------------------------------
+  Tag            : PortName
+  Description    : Port [Mod_Port_Name] does not follow naming convention
+  Violation      : Lint:3125
+  Goal           : lint_rtl
+  Module         : smart_allocator_per_iport
+  FileName       : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber     : 563
+  Statement      :     smart_ivc_reset_o,
+  Mod_Port_Name  : smart_ivc_reset_o
+  -----------------------------------------------------------------------------
+  Tag            : PortName
+  Description    : Port [Mod_Port_Name] does not follow naming convention
+  Violation      : Lint:3019
+  Goal           : lint_rtl
+  Module         : comb_nonspec_allocator
+  FileName       : ./../../rtl/src_noc/./comb_nonspec.sv
+  LineNumber     : 57
+  Statement      :     granted_dst_is_from_a_single_flit_pck,
+  Mod_Port_Name  : granted_dst_is_from_a_single_flit_pck
+  -----------------------------------------------------------------------------
+  Tag            : PortName
+  Description    : Port [Mod_Port_Name] does not follow naming convention
+  Violation      : Lint:3121
+  Goal           : lint_rtl
+  Module         : smart_allocator_per_iport
+  FileName       : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber     : 559
+  Statement      :     smart_buff_space_decreased_o,
+  Mod_Port_Name  : smart_buff_space_decreased_o
+  -----------------------------------------------------------------------------
+  Tag            : PortName
+  Description    : Port [Mod_Port_Name] does not follow naming convention
+  Violation      : Lint:3033
+  Goal           : lint_rtl
+  Module         : inout_ports
+  FileName       : ./../../rtl/src_noc/./inout_ports.sv
+  LineNumber     : 44
+  Statement      :     credit_init_val_in,
+  Mod_Port_Name  : credit_init_val_in
+  -----------------------------------------------------------------------------
+  Tag            : PortName
+  Description    : Port [Mod_Port_Name] does not follow naming convention
+  Violation      : Lint:3023
+  Goal           : lint_rtl
+  Module         : nonspec_sw_alloc
+  FileName       : ./../../rtl/src_noc/./comb_nonspec.sv
+  LineNumber     : 438
+  Statement      :     granted_dest_port_all,
+  Mod_Port_Name  : granted_dest_port_all
+  -----------------------------------------------------------------------------
+  Tag            : PortName
+  Description    : Port [Mod_Port_Name] does not follow naming convention
+  Violation      : Lint:3008
+  Goal           : lint_rtl
+  Module         : comb_nonspec_allocator
+  FileName       : ./../../rtl/src_noc/./comb_nonspec.sv
+  LineNumber     : 39
+  Statement      :     pck_is_single_flit_all,
+  Mod_Port_Name  : pck_is_single_flit_all
+  -----------------------------------------------------------------------------
+  Tag            : PortName
+  Description    : Port [Mod_Port_Name] does not follow naming convention
+  Violation      : Lint:3146
+  Goal           : lint_rtl
+  Module         : output_ports
+  FileName       : ./../../rtl/src_noc/./output_ports.sv
+  LineNumber     : 50
+  Statement      :     vsa_ovc_released_all,
+  Mod_Port_Name  : vsa_ovc_released_all
+  -----------------------------------------------------------------------------
+  Tag            : PortName
+  Description    : Port [Mod_Port_Name] does not follow naming convention
+  Violation      : Lint:3082
+  Goal           : lint_rtl
+  Module         : destp_generator
+  FileName       : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber     : 1104
+  Statement      :     dest_port_encoded,
+  Mod_Port_Name  : dest_port_encoded
+  -----------------------------------------------------------------------------
+  Tag            : PortName
+  Description    : Port [Mod_Port_Name] does not follow naming convention
+  Violation      : Lint:3040
+  Goal           : lint_rtl
+  Module         : inout_ports
+  FileName       : ./../../rtl/src_noc/./inout_ports.sv
+  LineNumber     : 55
+  Statement      :     nonspec_granted_dest_port_all,
+  Mod_Port_Name  : nonspec_granted_dest_port_all
+  -----------------------------------------------------------------------------
+  Tag            : PortName
+  Description    : Port [Mod_Port_Name] does not follow naming convention
+  Violation      : Lint:3016
+  Goal           : lint_rtl
+  Module         : comb_nonspec_allocator
+  FileName       : ./../../rtl/src_noc/./comb_nonspec.sv
+  LineNumber     : 54
+  Statement      :     nonspec_first_arbiter_granted_ivc_all,
+  Mod_Port_Name  : nonspec_first_arbiter_granted_ivc_all
+  -----------------------------------------------------------------------------
+  Tag            : PortName
+  Description    : Port [Mod_Port_Name] does not follow naming convention
+  Violation      : Lint:3159
+  Goal           : lint_rtl
+  Module         : fwft_fifo
+  FileName       : ./../../rtl/src_noc/./flit_buffer.sv
+  LineNumber     : 560
+  Statement      :     output recieve_more_than_1,
+  Mod_Port_Name  : recieve_more_than_1
+  -----------------------------------------------------------------------------
+  Tag            : PortName
+  Description    : Port [Mod_Port_Name] does not follow naming convention
+  Violation      : Lint:3076
+  Goal           : lint_rtl
+  Module         : input_queue_per_port
+  FileName       : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber     : 205
+  Statement      :     nonspec_first_arbiter_granted_ivc,
+  Mod_Port_Name  : nonspec_first_arbiter_granted_ivc
+  -----------------------------------------------------------------------------
+  Tag            : PortName
+  Description    : Port [Mod_Port_Name] does not follow naming convention
+  Violation      : Lint:3088
+  Goal           : lint_rtl
+  Module         : combined_vc_sw_alloc
+  FileName       : ./../../rtl/src_noc/./combined_vc_sw_alloc.sv
+  LineNumber     : 39
+  Statement      :     spec_first_arbiter_granted_ivc_all,
+  Mod_Port_Name  : spec_first_arbiter_granted_ivc_all
+  -----------------------------------------------------------------------------
+  Tag            : PortName
+  Description    : Port [Mod_Port_Name] does not follow naming convention
+  Violation      : Lint:3034
+  Goal           : lint_rtl
+  Module         : inout_ports
+  FileName       : ./../../rtl/src_noc/./inout_ports.sv
+  LineNumber     : 45
+  Statement      :     credit_init_val_out,
+  Mod_Port_Name  : credit_init_val_out
+  -----------------------------------------------------------------------------
+  Tag            : PortName
+  Description    : Port [Mod_Port_Name] does not follow naming convention
+  Violation      : Lint:3116
+  Goal           : lint_rtl
+  Module         : smart_allocator_per_iport
+  FileName       : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber     : 551
+  Statement      :     ovc_locally_requested,//make sure no conflict is existed between local & SMART VC allocation
+  Mod_Port_Name  : ovc_locally_requested
+  -----------------------------------------------------------------------------
+  Tag            : PortName
+  Description    : Port [Mod_Port_Name] does not follow naming convention
+  Violation      : Lint:3151
+  Goal           : lint_rtl
+  Module         : oport_ovc_sig_gen
+  FileName       : ./../../rtl/src_noc/./output_ports.sv
+  LineNumber     : 466
+  Statement      :     granted_dest_port,
+  Mod_Port_Name  : granted_dest_port
+  -----------------------------------------------------------------------------
+  Tag            : PortName
+  Description    : Port [Mod_Port_Name] does not follow naming convention
+  Violation      : Lint:3122
+  Goal           : lint_rtl
+  Module         : smart_allocator_per_iport
+  FileName       : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber     : 560
+  Statement      :     smart_ss_ovc_is_allocated_o,
+  Mod_Port_Name  : smart_ss_ovc_is_allocated_o
+  -----------------------------------------------------------------------------
+  Tag            : PortName
+  Description    : Port [Mod_Port_Name] does not follow naming convention
+  Violation      : Lint:3144
+  Goal           : lint_rtl
+  Module         : output_ports
+  FileName       : ./../../rtl/src_noc/./output_ports.sv
+  LineNumber     : 48
+  Statement      :     any_ovc_granted_in_outport_all, 
+  Mod_Port_Name  : any_ovc_granted_in_outport_all
+  -----------------------------------------------------------------------------
+  Tag            : PortName
+  Description    : Port [Mod_Port_Name] does not follow naming convention
+  Violation      : Lint:3099
+  Goal           : lint_rtl
+  Module         : smart_forward_ivc_info
+  FileName       : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber     : 217
+  Statement      :     ovc_locally_requested,
+  Mod_Port_Name  : ovc_locally_requested
+  -----------------------------------------------------------------------------
+  Tag            : PortName
+  Description    : Port [Mod_Port_Name] does not follow naming convention
+  Violation      : Lint:3147
+  Goal           : lint_rtl
+  Module         : output_ports
+  FileName       : ./../../rtl/src_noc/./output_ports.sv
+  LineNumber     : 51
+  Statement      :     crossbar_flit_out_wr_all,
+  Mod_Port_Name  : crossbar_flit_out_wr_all
+  -----------------------------------------------------------------------------
+  Tag            : PortName
+  Description    : Port [Mod_Port_Name] does not follow naming convention
+  Violation      : Lint:3011
+  Goal           : lint_rtl
+  Module         : comb_nonspec_allocator
+  FileName       : ./../../rtl/src_noc/./comb_nonspec.sv
+  LineNumber     : 44
+  Statement      :     ivc_num_getting_ovc_grant,
+  Mod_Port_Name  : ivc_num_getting_ovc_grant
+  -----------------------------------------------------------------------------
+  Tag            : PortName
+  Description    : Port [Mod_Port_Name] does not follow naming convention
+  Violation      : Lint:3112
+  Goal           : lint_rtl
+  Module         : smart_validity_check_per_ivc
+  FileName       : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber     : 454
+  Statement      :     smart_ivc_num_getting_ovc_grant_o,
+  Mod_Port_Name  : smart_ivc_num_getting_ovc_grant_o
+  -----------------------------------------------------------------------------
+  Tag            : PortName
+  Description    : Port [Mod_Port_Name] does not follow naming convention
+  Violation      : Lint:3051
+  Goal           : lint_rtl
+  Module         : inout_ports
+  FileName       : ./../../rtl/src_noc/./inout_ports.sv
+  LineNumber     : 76
+  Statement      :     oports_weight_all,
+  Mod_Port_Name  : oports_weight_all
+  -----------------------------------------------------------------------------
+  Tag            : PortName
+  Description    : Port [Mod_Port_Name] does not follow naming convention
+  Violation      : Lint:3056
+  Goal           : lint_rtl
+  Module         : vc_alloc_request_gen
+  FileName       : ./../../rtl/src_noc/./inout_ports.sv
+  LineNumber     : 437
+  Statement      :     dest_port_decoded_all,
+  Mod_Port_Name  : dest_port_decoded_all
+  -----------------------------------------------------------------------------
+  Tag            : PortName
+  Description    : Port [Mod_Port_Name] does not follow naming convention
+  Violation      : Lint:3130
+  Goal           : lint_rtl
+  Module         : smart_allocator_per_iport
+  FileName       : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber     : 568
+  Statement      :     smart_ovc_single_flit_pck_o
+  Mod_Port_Name  : smart_ovc_single_flit_pck_o
+  -----------------------------------------------------------------------------
+  Tag            : PortName
+  Description    : Port [Mod_Port_Name] does not follow naming convention
+  Violation      : Lint:3069
+  Goal           : lint_rtl
+  Module         : input_ports
+  FileName       : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber     : 59
+  Statement      :     oports_weight_all,
+  Mod_Port_Name  : oports_weight_all
+  -----------------------------------------------------------------------------
+  Tag            : PortName
+  Description    : Port [Mod_Port_Name] does not follow naming convention
+  Violation      : Lint:3143
+  Goal           : lint_rtl
+  Module         : output_ports
+  FileName       : ./../../rtl/src_noc/./output_ports.sv
+  LineNumber     : 45
+  Statement      :     granted_ovc_num_all,
+  Mod_Port_Name  : granted_ovc_num_all
+  -----------------------------------------------------------------------------
+  Tag            : PortName
+  Description    : Port [Mod_Port_Name] does not follow naming convention
+  Violation      : Lint:3063
+  Goal           : lint_rtl
+  Module         : input_ports
+  FileName       : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber     : 38
+  Statement      :     any_ivc_sw_request_granted_all,
+  Mod_Port_Name  : any_ivc_sw_request_granted_all
+  -----------------------------------------------------------------------------
+  Tag            : PortName
+  Description    : Port [Mod_Port_Name] does not follow naming convention
+  Violation      : Lint:3079
+  Goal           : lint_rtl
+  Module         : input_queue_per_port
+  FileName       : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber     : 211
+  Statement      :     refresh_w_counter,
+  Mod_Port_Name  : refresh_w_counter
+  -----------------------------------------------------------------------------
+  Tag            : PortName
+  Description    : Port [Mod_Port_Name] does not follow naming convention
+  Violation      : Lint:3096
+  Goal           : lint_rtl
+  Module         : combined_vc_sw_alloc
+  FileName       : ./../../rtl/src_noc/./combined_vc_sw_alloc.sv
+  LineNumber     : 48
+  Statement      :     iport_weight_is_consumed_all, 
+  Mod_Port_Name  : iport_weight_is_consumed_all
+  -----------------------------------------------------------------------------
+  Tag            : PortName
+  Description    : Port [Mod_Port_Name] does not follow naming convention
+  Violation      : Lint:3154
+  Goal           : lint_rtl
+  Module         : full_ovc_predictor
+  FileName       : ./../../rtl/src_noc/./output_ports.sv
+  LineNumber     : 545
+  Statement      :     ivc_getting_sw_grant,
+  Mod_Port_Name  : ivc_getting_sw_grant
+  -----------------------------------------------------------------------------
+  Tag            : PortName
+  Description    : Port [Mod_Port_Name] does not follow naming convention
+  Violation      : Lint:3157
+  Goal           : lint_rtl
+  Module         : crossbar
+  FileName       : ./../../rtl/src_noc/./crossbar.v
+  LineNumber     : 38
+  Statement      :     granted_dest_port_all,
+  Mod_Port_Name  : granted_dest_port_all
+  -----------------------------------------------------------------------------
+  Tag            : PortName
+  Description    : Port [Mod_Port_Name] does not follow naming convention
+  Violation      : Lint:3095
+  Goal           : lint_rtl
+  Module         : combined_vc_sw_alloc
+  FileName       : ./../../rtl/src_noc/./combined_vc_sw_alloc.sv
+  LineNumber     : 47
+  Statement      :     vc_weight_is_consumed_all, 
+  Mod_Port_Name  : vc_weight_is_consumed_all
+  -----------------------------------------------------------------------------
+  Tag            : PortName
+  Description    : Port [Mod_Port_Name] does not follow naming convention
+  Violation      : Lint:3062
+  Goal           : lint_rtl
+  Module         : input_ports
+  FileName       : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber     : 37
+  Statement      :     ivc_num_getting_sw_grant,// for non spec ivc_num_getting_first_sw_grant,
+  Mod_Port_Name  : ivc_num_getting_sw_grant
+  -----------------------------------------------------------------------------
+  Tag            : PortName
+  Description    : Port [Mod_Port_Name] does not follow naming convention
+  Violation      : Lint:3007
+  Goal           : lint_rtl
+  Module         : comb_nonspec_allocator
+  FileName       : ./../../rtl/src_noc/./comb_nonspec.sv
+  LineNumber     : 38
+  Statement      :     masked_ovc_request_all,
+  Mod_Port_Name  : masked_ovc_request_all
+  -----------------------------------------------------------------------------
+  Tag            : PortName
+  Description    : Port [Mod_Port_Name] does not follow naming convention
+  Violation      : Lint:3021
+  Goal           : lint_rtl
+  Module         : nonspec_sw_alloc
+  FileName       : ./../../rtl/src_noc/./comb_nonspec.sv
+  LineNumber     : 435
+  Statement      :     pck_is_single_flit_all,
+  Mod_Port_Name  : pck_is_single_flit_all
+  -----------------------------------------------------------------------------
+  Tag            : PortName
+  Description    : Port [Mod_Port_Name] does not follow naming convention
+  Violation      : Lint:3086
+  Goal           : lint_rtl
+  Module         : combined_vc_sw_alloc
+  FileName       : ./../../rtl/src_noc/./combined_vc_sw_alloc.sv
+  LineNumber     : 37
+  Statement      :     ivc_num_getting_ovc_grant,
+  Mod_Port_Name  : ivc_num_getting_ovc_grant
+  -----------------------------------------------------------------------------
+  Tag            : PortName
+  Description    : Port [Mod_Port_Name] does not follow naming convention
+  Violation      : Lint:3115
+  Goal           : lint_rtl
+  Module         : smart_allocator_per_iport
+  FileName       : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber     : 544
+  Statement      :     neighbors_r_addr_i,
+  Mod_Port_Name  : neighbors_r_addr_i
+  -----------------------------------------------------------------------------
+  Tag            : PortName
+  Description    : Port [Mod_Port_Name] does not follow naming convention
+  Violation      : Lint:3101
+  Goal           : lint_rtl
+  Module         : smart_validity_check_per_ivc
+  FileName       : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber     : 438
+  Statement      :     assigned_to_ss_ovc,
+  Mod_Port_Name  : assigned_to_ss_ovc
+  -----------------------------------------------------------------------------
+  Tag            : PortName
+  Description    : Port [Mod_Port_Name] does not follow naming convention
+  Violation      : Lint:3158
+  Goal           : lint_rtl
+  Module         : fwft_fifo
+  FileName       : ./../../rtl/src_noc/./flit_buffer.sv
+  LineNumber     : 559
+  Statement      :     output recieve_more_than_0,
+  Mod_Port_Name  : recieve_more_than_0
+  -----------------------------------------------------------------------------
+  Tag            : PortName
+  Description    : Port [Mod_Port_Name] does not follow naming convention
+  Violation      : Lint:3081
+  Goal           : lint_rtl
+  Module         : input_queue_per_port
+  FileName       : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber     : 217
+  Statement      :     credit_init_val_out,
+  Mod_Port_Name  : credit_init_val_out
+  -----------------------------------------------------------------------------
+  Tag            : PortName
+  Description    : Port [Mod_Port_Name] does not follow naming convention
+  Violation      : Lint:3050
+  Goal           : lint_rtl
+  Module         : inout_ports
+  FileName       : ./../../rtl/src_noc/./inout_ports.sv
+  LineNumber     : 69
+  Statement      :     iport_weight_is_consumed_all, 
+  Mod_Port_Name  : iport_weight_is_consumed_all
+  -----------------------------------------------------------------------------
+  Tag            : PortName
+  Description    : Port [Mod_Port_Name] does not follow naming convention
+  Violation      : Lint:3103
+  Goal           : lint_rtl
+  Module         : smart_validity_check_per_ivc
+  FileName       : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber     : 443
+  Statement      :     ss_ovc_avalable_in_ss_port,
+  Mod_Port_Name  : ss_ovc_avalable_in_ss_port
+  -----------------------------------------------------------------------------
+  Tag            : PortName
+  Description    : Port [Mod_Port_Name] does not follow naming convention
+  Violation      : Lint:3013
+  Goal           : lint_rtl
+  Module         : comb_nonspec_allocator
+  FileName       : ./../../rtl/src_noc/./comb_nonspec.sv
+  LineNumber     : 49
+  Statement      :     iport_weight_is_consumed_all,
+  Mod_Port_Name  : iport_weight_is_consumed_all
+  -----------------------------------------------------------------------------
+  Tag            : PortName
+  Description    : Port [Mod_Port_Name] does not follow naming convention
+  Violation      : Lint:3084
+  Goal           : lint_rtl
+  Module         : combined_vc_sw_alloc
+  FileName       : ./../../rtl/src_noc/./combined_vc_sw_alloc.sv
+  LineNumber     : 35
+  Statement      :     ovc_allocated_all,
+  Mod_Port_Name  : ovc_allocated_all
+  -----------------------------------------------------------------------------
+  Tag            : PortName
+  Description    : Port [Mod_Port_Name] does not follow naming convention
+  Violation      : Lint:3027
+  Goal           : lint_rtl
+  Module         : nonspec_sw_alloc
+  FileName       : ./../../rtl/src_noc/./comb_nonspec.sv
+  LineNumber     : 443
+  Statement      :     vc_weight_is_consumed_all,
+  Mod_Port_Name  : vc_weight_is_consumed_all
+
+  -----------------------------------------------------------------------------
+  RegInput-ML  (150 warnings/0 waived/157 compressed)
+  -----------------------------------------------------------------------------
+  Tag          : RegInput-ML
+  Description  : Input port '[Signal]' is not registered [module:[MASTER]]
+  Violation    : Lint:2636
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./../main_comp.v
+  LineNumber   : 259
+  Statement    :     input   [ONE_HOT_WIDTH-1 : 0] one_hot_code,
+  Signal       : one_hot_code
+  Module       : one_hot_to_bin
+  MASTER       : one_hot_to_bin
+  -----------------------------------------------------------------------------
+  Tag          : RegInput-ML
+  Description  : Input port '[Signal]' is not registered [module:[MASTER]]
+  Violation    : Lint:2845
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber   : 472
+  Statement    :     assigned_to_ss_ovc,
+  Signal       : assigned_to_ss_ovc
+  Module       : smart_validity_check_per_ivc
+  MASTER       : smart_validity_check_per_ivc
+  -----------------------------------------------------------------------------
+  Tag          : RegInput-ML
+  Description  : Input port '[Signal]' is not registered [module:[MASTER]]
+  Violation    : Lint:2724
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./congestion_analyzer.v
+  LineNumber   : 351
+  Statement    :     input [PV-1 : 0] ovc_status;
+  Signal       : ovc_status
+  Module       : port_pre_sel_gen
+  MASTER       : port_pre_sel_gen
+  -----------------------------------------------------------------------------
+  Tag          : RegInput-ML
+  Description  : Input port '[Signal]' is not registered [module:[MASTER]]
+  Violation    : Lint:2667
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./ovc_list.sv
+  LineNumber   : 32
+  Statement    :     input [Cw-1 : 0] class_in;
+  Signal       : class_in
+  Module       : ovc_list
+  MASTER       : ovc_list
+  -----------------------------------------------------------------------------
+  Tag          : RegInput-ML
+  Description  : Input port '[Signal]' is not registered [module:[MASTER]]
+  Violation    : Lint:2849
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber   : 477
+  Statement    :     ss_ovc_avalable_in_ss_port,
+  Signal       : ss_ovc_avalable_in_ss_port
+  Module       : smart_validity_check_per_ivc
+  MASTER       : smart_validity_check_per_ivc
+  -----------------------------------------------------------------------------
+  Tag          : RegInput-ML
+  Description  : Input port '[Signal]' is not registered [module:[MASTER]]
+  Violation    : Lint:2772
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./combined_vc_sw_alloc.sv
+  LineNumber   : 78
+  Statement    :     input  [P-1 :  0] iport_weight_is_consumed_all;
+  Signal       : iport_weight_is_consumed_all
+  SignalRange  : 
+  Module       : combined_vc_sw_alloc
+  MASTER       : combined_vc_sw_alloc
+  -----------------------------------------------------------------------------
+  Tag          : RegInput-ML
+  Description  : Input port '[Signal]' is not registered [module:[MASTER]]
+  Violation    : Lint:2730
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./congestion_analyzer.v
+  LineNumber   : 356
+  Statement    :     input reset,clk;
+  Signal       : clk
+  SignalRange  : 
+  Module       : port_pre_sel_gen
+  MASTER       : port_pre_sel_gen
+  -----------------------------------------------------------------------------
+  Tag          : RegInput-ML
+  Description  : Input port '[Signal]' is not registered [module:[MASTER]]
+  Violation    : Lint:2676
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./mesh_torus_routting.v
+  LineNumber   : 45
+  Statement    :     input [Xw-1 : 0]  current_x;
+  Signal       : current_x
+  SignalRange  : 
+  Module       : mesh_torus_look_ahead_routing
+  MASTER       : mesh_torus_look_ahead_routing
+  -----------------------------------------------------------------------------
+  Tag          : RegInput-ML
+  Description  : Input port '[Signal]' is not registered [module:[MASTER]]
+  Violation    : Lint:2694
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./mesh_torus.sv
+  LineNumber   : 963
+  Statement    :     input  [EAw-1 : 0] e_addr;
+  Signal       : e_addr
+  Module       : mesh_tori_endp_addr_decode
+  MASTER       : mesh_tori_endp_addr_decode
+  -----------------------------------------------------------------------------
+  Tag          : RegInput-ML
+  Description  : Input port '[Signal]' is not registered [module:[MASTER]]
+  Violation    : Lint:2672
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./routing.v
+  LineNumber   : 276
+  Statement    :     input   [PRAw-1:  0]  neighbors_r_addr;
+  Signal       : neighbors_r_addr
+  Module       : look_ahead_routing
+  MASTER       : look_ahead_routing
+  -----------------------------------------------------------------------------
+  Tag          : RegInput-ML
+  Description  : Input port '[Signal]' is not registered [module:[MASTER]]
+  Violation    : Lint:2763
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./inout_ports.sv
+  LineNumber   : 625
+  Statement    :     input   [PV-1       :   0]  ovc_is_assigned_all;
+  Signal       : ovc_is_assigned_all
+  Module       : vc_alloc_request_gen_determinstic
+  MASTER       : vc_alloc_request_gen_determinstic
+  -----------------------------------------------------------------------------
+  Tag          : RegInput-ML
+  Description  : Input port '[Signal]' is not registered [module:[MASTER]]
+  Violation    : Lint:2733
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./output_ports.sv
+  LineNumber   : 479
+  Statement    :     input [V-1 : 0]  ovc_is_assigned;
+  Signal       : ovc_is_assigned
+  SignalRange  : 
+  Module       : oport_ovc_sig_gen
+  MASTER       : oport_ovc_sig_gen
+  -----------------------------------------------------------------------------
+  Tag          : RegInput-ML
+  Description  : Input port '[Signal]' is not registered [module:[MASTER]]
+  Violation    : Lint:2606
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber   : 256
+  Statement    :     input   any_ivc_sw_request_granted;
+  Signal       : any_ivc_sw_request_granted
+  SignalRange  : 
+  Module       : input_queue_per_port
+  MASTER       : input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag          : RegInput-ML
+  Description  : Input port '[Signal]' is not registered [module:[MASTER]]
+  Violation    : Lint:2725
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./congestion_analyzer.v
+  LineNumber   : 352
+  Statement    :     input [PV-1 : 0] ovc_avalable_all;
+  Signal       : ovc_avalable_all
+  SignalRange  : 
+  Module       : port_pre_sel_gen
+  MASTER       : port_pre_sel_gen
+  -----------------------------------------------------------------------------
+  Tag          : RegInput-ML
+  Description  : Input port '[Signal]' is not registered [module:[MASTER]]
+  Violation    : Lint:2567
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./inout_ports.sv
+  LineNumber   : 157
+  Statement    :     input   [CRDTw-1 : 0 ] credit_init_val_in  [P-1 : 0][V-1 : 0];
+  Signal       : credit_init_val_in[2][0]
+  SignalRange  : 0, 0-1, 1-2, 2-3, 3-4, 4
+  Module       : inout_ports
+  MASTER       : inout_ports
+  -----------------------------------------------------------------------------
+  Tag          : RegInput-ML
+  Description  : Input port '[Signal]' is not registered [module:[MASTER]]
+  Violation    : Lint:2741
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./output_ports.sv
+  LineNumber   : 555
+  Statement    :     input [V-1 : 0]  assigned_ovc_num,granted_ovc_num,ssa_granted_ovc_num;
+  Signal       : granted_ovc_num
+  Module       : full_ovc_predictor
+  MASTER       : full_ovc_predictor
+  -----------------------------------------------------------------------------
+  Tag          : RegInput-ML
+  Description  : Input port '[Signal]' is not registered [module:[MASTER]]
+  Violation    : Lint:2784
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./../main_comp.v
+  LineNumber   : 177
+  Statement    :     input [IN_WIDTH-1 : 0]  or_in;
+  Signal       : or_in
+  Module       : custom_or
+  MASTER       : custom_or
+  -----------------------------------------------------------------------------
+  Tag          : RegInput-ML
+  Description  : Input port '[Signal]' is not registered [module:[MASTER]]
+  Violation    : Lint:2700
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./output_ports.sv
+  LineNumber   : 76
+  Statement    :     input [PVP_1-1 : 0] dest_port_all;
+  Signal       : dest_port_all
+  SignalRange  : 
+  Module       : output_ports
+  MASTER       : output_ports
+  -----------------------------------------------------------------------------
+  Tag          : RegInput-ML
+  Description  : Input port '[Signal]' is not registered [module:[MASTER]]
+  Violation    : Lint:2551
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./router_top.sv
+  LineNumber   : 47
+  Statement    :     input router_config_t router_config_in;
+  Signal       : router_config_in
+  SignalRange  : 
+  Module       : router_top
+  MASTER       : router_top
+  -----------------------------------------------------------------------------
+  Tag          : RegInput-ML
+  Description  : Input port '[Signal]' is not registered [module:[MASTER]]
+  Violation    : Lint:2595
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber   : 106
+  Statement    :     input   [PPSw-1 : 0] port_pre_sel;
+  Signal       : port_pre_sel
+  SignalRange  : 
+  Module       : input_ports
+  MASTER       : input_ports
+  -----------------------------------------------------------------------------
+  Tag          : RegInput-ML
+  Description  : Input port '[Signal]' is not registered [module:[MASTER]]
+  Violation    : Lint:2843
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber   : 469
+  Statement    :     flit_wr_i,
+  Signal       : flit_wr_i
+  Module       : smart_validity_check_per_ivc
+  MASTER       : smart_validity_check_per_ivc
+  -----------------------------------------------------------------------------
+  Tag          : RegInput-ML
+  Description  : Input port '[Signal]' is not registered [module:[MASTER]]
+  Violation    : Lint:2576
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./inout_ports.sv
+  LineNumber   : 116
+  Statement    :     input [PVV-1 : 0] spec_ovc_num_all;
+  Signal       : spec_ovc_num_all
+  Module       : inout_ports
+  MASTER       : inout_ports
+  -----------------------------------------------------------------------------
+  Tag          : RegInput-ML
+  Description  : Input port '[Signal]' is not registered [module:[MASTER]]
+  Violation    : Lint:2651
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber   : 1119
+  Statement    :     input odd_column;
+  Signal       : odd_column
+  SignalRange  : 
+  Module       : destp_generator
+  MASTER       : destp_generator
+  -----------------------------------------------------------------------------
+  Tag          : RegInput-ML
+  Description  : Input port '[Signal]' is not registered [module:[MASTER]]
+  Violation    : Lint:2764
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./inout_ports.sv
+  LineNumber   : 626
+  Statement    :     input   [PVP_1-1    :   0]  dest_port_in_all;
+  Signal       : dest_port_in_all
+  Module       : vc_alloc_request_gen_determinstic
+  MASTER       : vc_alloc_request_gen_determinstic
+  -----------------------------------------------------------------------------
+  Tag          : RegInput-ML
+  Description  : Input port '[Signal]' is not registered [module:[MASTER]]
+  Violation    : Lint:2771
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./combined_vc_sw_alloc.sv
+  LineNumber   : 77
+  Statement    :     input  [PV-1 :  0] vc_weight_is_consumed_all;
+  Signal       : vc_weight_is_consumed_all
+  SignalRange  : 
+  Module       : combined_vc_sw_alloc
+  MASTER       : combined_vc_sw_alloc
+  -----------------------------------------------------------------------------
+  Tag          : RegInput-ML
+  Description  : Input port '[Signal]' is not registered [module:[MASTER]]
+  Violation    : Lint:2812
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber   : 226
+  Statement    :     input  oport_info_t oport_info  [P-1 : 0]; 
+  Signal       : oport_info
+  SignalRange  : 
+  Module       : smart_forward_ivc_info
+  MASTER       : smart_forward_ivc_info
+  -----------------------------------------------------------------------------
+  Tag          : RegInput-ML
+  Description  : Input port '[Signal]' is not registered [module:[MASTER]]
+  Violation    : Lint:2584
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./inout_ports.sv
+  LineNumber   : 129
+  Statement    :     input [P-1 : 0] granted_dst_is_from_a_single_flit_pck;
+  Signal       : granted_dst_is_from_a_single_flit_pck
+  SignalRange  : 
+  Module       : inout_ports
+  MASTER       : inout_ports
+  -----------------------------------------------------------------------------
+  Tag          : RegInput-ML
+  Description  : Input port '[Signal]' is not registered [module:[MASTER]]
+  Violation    : Lint:2585
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./inout_ports.sv
+  LineNumber   : 144
+  Statement    :     input refresh_w_counter;
+  Signal       : refresh_w_counter
+  SignalRange  : 
+  Module       : inout_ports
+  MASTER       : inout_ports
+  -----------------------------------------------------------------------------
+  Tag          : RegInput-ML
+  Description  : Input port '[Signal]' is not registered [module:[MASTER]]
+  Violation    : Lint:2561
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./inout_ports.sv
+  LineNumber   : 125
+  Statement    :     input [CONG_ALw-1 : 0] congestion_in_all;
+  Signal       : congestion_in_all
+  SignalRange  : 
+  Module       : inout_ports
+  MASTER       : inout_ports
+  -----------------------------------------------------------------------------
+  Tag          : RegInput-ML
+  Description  : Input port '[Signal]' is not registered [module:[MASTER]]
+  Violation    : Lint:2824
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber   : 576
+  Statement    :     input smart_chanel_t smart_chanel_i;
+  Signal       : smart_chanel_i
+  Module       : smart_allocator_per_iport
+  MASTER       : smart_allocator_per_iport
+  -----------------------------------------------------------------------------
+  Tag          : RegInput-ML
+  Description  : Input port '[Signal]' is not registered [module:[MASTER]]
+  Violation    : Lint:2555
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./router_two_stage.sv
+  LineNumber   : 67
+  Statement    :     input   ctrl_chanel_t ctrl_in  [P-1 : 0];
+  Signal       : ctrl_in
+  SignalRange  : 
+  Module       : router_two_stage
+  MASTER       : router_two_stage
+  -----------------------------------------------------------------------------
+  Tag          : RegInput-ML
+  Description  : Input port '[Signal]' is not registered [module:[MASTER]]
+  Violation    : Lint:2549
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./noc_top.sv
+  LineNumber   : 44
+  Statement    :     input   smartflit_chanel_t chan_in_all  [NE-1 : 0];
+  Signal       : chan_in_all[93:0][3:0]
+  Module       : noc_top
+  MASTER       : noc_top
+  -----------------------------------------------------------------------------
+  Tag          : RegInput-ML
+  Description  : Input port '[Signal]' is not registered [module:[MASTER]]
+  Violation    : Lint:2752
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./inout_ports.sv
+  LineNumber   : 461
+  Statement    :     input   [PVP_1-1    :   0]  dest_port_decoded_all;   
+  Signal       : dest_port_decoded_all
+  Module       : vc_alloc_request_gen
+  MASTER       : vc_alloc_request_gen
+  -----------------------------------------------------------------------------
+  Tag          : RegInput-ML
+  Description  : Input port '[Signal]' is not registered [module:[MASTER]]
+  Violation    : Lint:2621
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./../main_comp.v
+  LineNumber   : 59
+  Statement    :     input [W-1 : 0] reset_to
+  Signal       : reset_to
+  Module       : pronoc_register_reset_init
+  MASTER       : pronoc_register_reset_init
+  -----------------------------------------------------------------------------
+  Tag          : RegInput-ML
+  Description  : Input port '[Signal]' is not registered [module:[MASTER]]
+  Violation    : Lint:2827
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber   : 582
+  Statement    :     input ovc_info_t   ss_ovc_info [V-1 : 0];
+  Signal       : ss_ovc_info
+  Module       : smart_allocator_per_iport
+  MASTER       : smart_allocator_per_iport
+  -----------------------------------------------------------------------------
+  Tag          : RegInput-ML
+  Description  : Input port '[Signal]' is not registered [module:[MASTER]]
+  Violation    : Lint:2837
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber   : 462
+  Statement    :     input goes_straight,
+  Signal       : goes_straight
+  Module       : smart_validity_check_per_ivc
+  MASTER       : smart_validity_check_per_ivc
+  -----------------------------------------------------------------------------
+  Tag          : RegInput-ML
+  Description  : Input port '[Signal]' is not registered [module:[MASTER]]
+  Violation    : Lint:2593
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber   : 103
+  Statement    :     input   [PV-1  : 0] assigned_ovc_not_full_all;
+  Signal       : assigned_ovc_not_full_all
+  Module       : input_ports
+  MASTER       : input_ports
+  -----------------------------------------------------------------------------
+  Tag          : RegInput-ML
+  Description  : Input port '[Signal]' is not registered [module:[MASTER]]
+  Violation    : Lint:2729
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./congestion_analyzer.v
+  LineNumber   : 356
+  Statement    :     input reset,clk;
+  Signal       : reset
+  SignalRange  : 
+  Module       : port_pre_sel_gen
+  MASTER       : port_pre_sel_gen
+  -----------------------------------------------------------------------------
+  Tag          : RegInput-ML
+  Description  : Input port '[Signal]' is not registered [module:[MASTER]]
+  Violation    : Lint:2737
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./../main_comp.v
+  LineNumber   : 151
+  Statement    :     input   [IN_WIDTH-1 : 0] demux_in,//repeated
+  Signal       : demux_in
+  Module       : one_hot_demux
+  MASTER       : one_hot_demux
+  -----------------------------------------------------------------------------
+  Tag          : RegInput-ML
+  Description  : Input port '[Signal]' is not registered [module:[MASTER]]
+  Violation    : Lint:2559
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./inout_ports.sv
+  LineNumber   : 108
+  Statement    :     input [P-1 : 0] flit_in_wr_all;
+  Signal       : flit_in_wr_all
+  SignalRange  : 
+  Module       : inout_ports
+  MASTER       : inout_ports
+  -----------------------------------------------------------------------------
+  Tag          : RegInput-ML
+  Description  : Input port '[Signal]' is not registered [module:[MASTER]]
+  Violation    : Lint:2809
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./router_two_stage.sv
+  LineNumber   : 668
+  Statement    :     input  en;
+  Signal       : en
+  Module       : credit_release_gen
+  MASTER       : credit_release_gen
+  -----------------------------------------------------------------------------
+  Tag          : RegInput-ML
+  Description  : Input port '[Signal]' is not registered [module:[MASTER]]
+  Violation    : Lint:2578
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./inout_ports.sv
+  LineNumber   : 118
+  Statement    :     input [PV-1 : 0] spec_first_arbiter_granted_ivc_all;
+  Signal       : spec_first_arbiter_granted_ivc_all
+  Module       : inout_ports
+  MASTER       : inout_ports
+  -----------------------------------------------------------------------------
+  Tag          : RegInput-ML
+  Description  : Input port '[Signal]' is not registered [module:[MASTER]]
+  Violation    : Lint:2848
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber   : 475
+  Statement    :     ivc_request,
+  Signal       : ivc_request
+  Module       : smart_validity_check_per_ivc
+  MASTER       : smart_validity_check_per_ivc
+  -----------------------------------------------------------------------------
+  Tag          : RegInput-ML
+  Description  : Input port '[Signal]' is not registered [module:[MASTER]]
+  Violation    : Lint:2580
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./inout_ports.sv
+  LineNumber   : 120
+  Statement    :     input [PP_1-1 : 0] spec_granted_dest_port_all;    
+  Signal       : spec_granted_dest_port_all
+  Module       : inout_ports
+  MASTER       : inout_ports
+  -----------------------------------------------------------------------------
+  Tag          : RegInput-ML
+  Description  : Input port '[Signal]' is not registered [module:[MASTER]]
+  Violation    : Lint:2829
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber   : 583
+  Statement    :     input ss_port_link_reg_flit_wr;    
+  Signal       : ss_port_link_reg_flit_wr
+  SignalRange  : 
+  Module       : smart_allocator_per_iport
+  MASTER       : smart_allocator_per_iport
+  -----------------------------------------------------------------------------
+  Tag          : RegInput-ML
+  Description  : Input port '[Signal]' is not registered [module:[MASTER]]
+  Violation    : Lint:2629
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./flit_buffer.sv
+  LineNumber   : 79
+  Statement    :     input [V-1 :0]  ssa_rd;
+  Signal       : ssa_rd
+  Module       : flit_buffer
+  MASTER       : flit_buffer
+  -----------------------------------------------------------------------------
+  Tag          : RegInput-ML
+  Description  : Input port '[Signal]' is not registered [module:[MASTER]]
+  Violation    : Lint:2661
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./mesh_torus_routting.v
+  LineNumber   : 468
+  Statement    :     input [P-1 : 0] destport_in;
+  Signal       : destport_in
+  SignalRange  : 
+  Module       : remove_sw_loc_one_hot
+  MASTER       : remove_sw_loc_one_hot
+  -----------------------------------------------------------------------------
+  Tag          : RegInput-ML
+  Description  : Input port '[Signal]' is not registered [module:[MASTER]]
+  Violation    : Lint:2652
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./mesh_torus.sv
+  LineNumber   : 1134
+  Statement    :     input  [DSTPw-1 : 0] dest_port_coded;
+  Signal       : dest_port_coded
+  SignalRange  : 
+  Module       : mesh_torus_destp_generator
+  MASTER       : mesh_torus_destp_generator
+  -----------------------------------------------------------------------------
+  Tag          : RegInput-ML
+  Description  : Input port '[Signal]' is not registered [module:[MASTER]]
+  Violation    : Lint:2579
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./inout_ports.sv
+  LineNumber   : 119
+  Statement    :     input [PP_1-1 : 0] nonspec_granted_dest_port_all;
+  Signal       : nonspec_granted_dest_port_all
+  SignalRange  : 
+  Module       : inout_ports
+  MASTER       : inout_ports
+  -----------------------------------------------------------------------------
+  Tag          : RegInput-ML
+  Description  : Input port '[Signal]' is not registered [module:[MASTER]]
+  Violation    : Lint:2598
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber   : 124
+  Statement    :     input   [DSTPw-1 : 0] destport_clear [P-1 : 0][V-1 : 0];
+  Signal       : destport_clear
+  SignalRange  : 
+  Module       : input_ports
+  MASTER       : input_ports
+  -----------------------------------------------------------------------------
+  Tag          : RegInput-ML
+  Description  : Input port '[Signal]' is not registered [module:[MASTER]]
+  Violation    : Lint:2770
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./combined_vc_sw_alloc.sv
+  LineNumber   : 64
+  Statement    :     input  [PVV-1 :  0] masked_ovc_request_all;
+  Signal       : masked_ovc_request_all
+  SignalRange  : 
+  Module       : combined_vc_sw_alloc
+  MASTER       : combined_vc_sw_alloc
+  -----------------------------------------------------------------------------
+  Tag          : RegInput-ML
+  Description  : Input port '[Signal]' is not registered [module:[MASTER]]
+  Violation    : Lint:2788
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./comb_nonspec.sv
+  LineNumber   : 629
+  Statement    :     input [ARBITER_WIDTH-1 : 0] request;
+  Signal       : request
+  SignalRange  : 
+  Module       : swa_input_port_arbiter
+  MASTER       : swa_input_port_arbiter
+  -----------------------------------------------------------------------------
+  Tag          : RegInput-ML
+  Description  : Input port '[Signal]' is not registered [module:[MASTER]]
+  Violation    : Lint:2575
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./inout_ports.sv
+  LineNumber   : 115
+  Statement    :     input [PV-1 : 0] ivc_num_getting_ovc_grant;
+  Signal       : ivc_num_getting_ovc_grant
+  SignalRange  : 
+  Module       : inout_ports
+  MASTER       : inout_ports
+  -----------------------------------------------------------------------------
+  Tag          : RegInput-ML
+  Description  : Input port '[Signal]' is not registered [module:[MASTER]]
+  Violation    : Lint:2608
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber   : 258
+  Statement    :     input   flit_in_wr;
+  Signal       : flit_in_wr
+  SignalRange  : 
+  Module       : input_queue_per_port
+  MASTER       : input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag          : RegInput-ML
+  Description  : Input port '[Signal]' is not registered [module:[MASTER]]
+  Violation    : Lint:2736
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./../main_comp.v
+  LineNumber   : 150
+  Statement    :     input   [SEL_WIDTH-1 : 0] demux_sel,//selectore
+  Signal       : demux_sel
+  Module       : one_hot_demux
+  MASTER       : one_hot_demux
+  -----------------------------------------------------------------------------
+  Tag          : RegInput-ML
+  Description  : Input port '[Signal]' is not registered [module:[MASTER]]
+  Violation    : Lint:2678
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./mesh_torus_routting.v
+  LineNumber   : 48
+  Statement    :     input [Yw-1 : 0]  dest_y;
+  Signal       : dest_y
+  SignalRange  : 
+  Module       : mesh_torus_look_ahead_routing
+  MASTER       : mesh_torus_look_ahead_routing
+  -----------------------------------------------------------------------------
+  Tag          : RegInput-ML
+  Description  : Input port '[Signal]' is not registered [module:[MASTER]]
+  Violation    : Lint:2825
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber   : 577
+  Statement    :     input flit_chanel_t flit_chanel_i;
+  Signal       : flit_chanel_i
+  Module       : smart_allocator_per_iport
+  MASTER       : smart_allocator_per_iport
+  -----------------------------------------------------------------------------
+  Tag          : RegInput-ML
+  Description  : Input port '[Signal]' is not registered [module:[MASTER]]
+  Violation    : Lint:2747
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./output_ports.sv
+  LineNumber   : 559
+  Statement    :     input [VP_1-1 : 0] nearly_full;
+  Signal       : nearly_full
+  Module       : full_ovc_predictor
+  MASTER       : full_ovc_predictor
+  -----------------------------------------------------------------------------
+  Tag          : RegInput-ML
+  Description  : Input port '[Signal]' is not registered [module:[MASTER]]
+  Violation    : Lint:2739
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./output_ports.sv
+  LineNumber   : 420
+  Statement    :     input credit_decreased;    
+  Signal       : credit_decreased
+  Module       : credit_monitor_per_ovc
+  MASTER       : credit_monitor_per_ovc
+  -----------------------------------------------------------------------------
+  Tag          : RegInput-ML
+  Description  : Input port '[Signal]' is not registered [module:[MASTER]]
+  Violation    : Lint:2744
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./output_ports.sv
+  LineNumber   : 556
+  Statement    :     input [P_1-1 : 0] dest_port;
+  Signal       : dest_port
+  Module       : full_ovc_predictor
+  MASTER       : full_ovc_predictor
+  -----------------------------------------------------------------------------
+  Tag          : RegInput-ML
+  Description  : Input port '[Signal]' is not registered [module:[MASTER]]
+  Violation    : Lint:2609
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber   : 264
+  Statement    :     input   [V-1  : 0] assigned_ovc_not_full;
+  Signal       : assigned_ovc_not_full
+  SignalRange  : 
+  Module       : input_queue_per_port
+  MASTER       : input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag          : RegInput-ML
+  Description  : Input port '[Signal]' is not registered [module:[MASTER]]
+  Violation    : Lint:2642
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./header_flit.sv
+  LineNumber   : 219
+  Statement    :     input [VDSTPw-1 : 0]  lk_dest_all_in;
+  Signal       : lk_dest_all_in
+  Module       : header_flit_update_lk_route_ovc
+  MASTER       : header_flit_update_lk_route_ovc
+  -----------------------------------------------------------------------------
+  Tag          : RegInput-ML
+  Description  : Input port '[Signal]' is not registered [module:[MASTER]]
+  Violation    : Lint:2645
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./header_flit.sv
+  LineNumber   : 224
+  Statement    :     input [DSTPw-1 : 0]  lk_dest_not_registered;
+  Signal       : lk_dest_not_registered
+  Module       : header_flit_update_lk_route_ovc
+  MASTER       : header_flit_update_lk_route_ovc
+  -----------------------------------------------------------------------------
+  Tag          : RegInput-ML
+  Description  : Input port '[Signal]' is not registered [module:[MASTER]]
+  Violation    : Lint:2639
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./flit_buffer.sv
+  LineNumber   : 442
+  Statement    :     input [ADDR_WIDTH-1 :    0]  rd_addr;
+  Signal       : rd_addr
+  Module       : fifo_ram
+  MASTER       : fifo_ram
+  -----------------------------------------------------------------------------
+  Tag          : RegInput-ML
+  Description  : Input port '[Signal]' is not registered [module:[MASTER]]
+  Violation    : Lint:2801
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./../arbiter.v
+  LineNumber   : 214
+  Statement    :     input [1 : 0] low_pr
+  Signal       : low_pr
+  Module       : arbiter_3_one_hot
+  MASTER       : arbiter_3_one_hot
+  -----------------------------------------------------------------------------
+  Tag          : RegInput-ML
+  Description  : Input port '[Signal]' is not registered [module:[MASTER]]
+  Violation    : Lint:2616
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber   : 274
+  Statement    :     input   [P_1-1 : 0] granted_dest_port; 
+  Signal       : granted_dest_port
+  SignalRange  : 
+  Module       : input_queue_per_port
+  MASTER       : input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag          : RegInput-ML
+  Description  : Input port '[Signal]' is not registered [module:[MASTER]]
+  Violation    : Lint:2749
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./output_ports.sv
+  LineNumber   : 418
+  Statement    :     input [CRDTw-1 : 0] credit_init_val_i;
+  Signal       : credit_init_val_i
+  Module       : credit_monitor_per_ovc
+  MASTER       : credit_monitor_per_ovc
+  -----------------------------------------------------------------------------
+  Tag          : RegInput-ML
+  Description  : Input port '[Signal]' is not registered [module:[MASTER]]
+  Violation    : Lint:2582
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./inout_ports.sv
+  LineNumber   : 122
+  Statement    :     input [P-1 : 0] any_ivc_sw_request_granted_all;
+  Signal       : any_ivc_sw_request_granted_all
+  SignalRange  : 
+  Module       : inout_ports
+  MASTER       : inout_ports
+  -----------------------------------------------------------------------------
+  Tag          : RegInput-ML
+  Description  : Input port '[Signal]' is not registered [module:[MASTER]]
+  Violation    : Lint:2699
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./output_ports.sv
+  LineNumber   : 75
+  Statement    :     input [PV-1 : 0] flit_is_tail_all;   
+  Signal       : flit_is_tail_all
+  Module       : output_ports
+  MASTER       : output_ports
+  -----------------------------------------------------------------------------
+  Tag          : RegInput-ML
+  Description  : Input port '[Signal]' is not registered [module:[MASTER]]
+  Violation    : Lint:2626
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./flit_buffer.sv
+  LineNumber   : 72
+  Statement    :     input [V-1 :0]   vc_num_rd;//read virtual chanel
+  Signal       : vc_num_rd
+  Module       : flit_buffer
+  MASTER       : flit_buffer
+  -----------------------------------------------------------------------------
+  Tag          : RegInput-ML
+  Description  : Input port '[Signal]' is not registered [module:[MASTER]]
+  Violation    : Lint:2643
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./header_flit.sv
+  LineNumber   : 221
+  Statement    :     input [VV-1 : 0]  assigned_ovc_num;
+  Signal       : assigned_ovc_num
+  SignalRange  : 
+  Module       : header_flit_update_lk_route_ovc
+  MASTER       : header_flit_update_lk_route_ovc
+  -----------------------------------------------------------------------------
+  Tag          : RegInput-ML
+  Description  : Input port '[Signal]' is not registered [module:[MASTER]]
+  Violation    : Lint:2738
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./output_ports.sv
+  LineNumber   : 419
+  Statement    :     input credit_increased;
+  Signal       : credit_increased
+  SignalRange  : 
+  Module       : credit_monitor_per_ovc
+  MASTER       : credit_monitor_per_ovc
+  -----------------------------------------------------------------------------
+  Tag          : RegInput-ML
+  Description  : Input port '[Signal]' is not registered [module:[MASTER]]
+  Violation    : Lint:2625
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./flit_buffer.sv
+  LineNumber   : 71
+  Statement    :     input [V-1 :0]   vc_num_wr;//write virtual chanel
+  Signal       : vc_num_wr
+  Module       : flit_buffer
+  MASTER       : flit_buffer
+  -----------------------------------------------------------------------------
+  Tag          : RegInput-ML
+  Description  : Input port '[Signal]' is not registered [module:[MASTER]]
+  Violation    : Lint:2841
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber   : 467
+  Statement    :     flit_hdr_flag_i ,
+  Signal       : flit_hdr_flag_i
+  Module       : smart_validity_check_per_ivc
+  MASTER       : smart_validity_check_per_ivc
+  -----------------------------------------------------------------------------
+  Tag          : RegInput-ML
+  Description  : Input port '[Signal]' is not registered [module:[MASTER]]
+  Violation    : Lint:2556
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./router_two_stage.sv
+  LineNumber   : 76
+  Statement    :     input   smart_ctrl_t   smart_ctrl_in [P-1 : 0];
+  Signal       : smart_ctrl_in
+  SignalRange  : 
+  Module       : router_two_stage
+  MASTER       : router_two_stage
+  -----------------------------------------------------------------------------
+  Tag          : RegInput-ML
+  Description  : Input port '[Signal]' is not registered [module:[MASTER]]
+  Violation    : Lint:2853
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber   : 724
+  Statement    :     input [V-1 : 0]  credit_in, smart_credit_in;
+  Signal       : smart_credit_in
+  SignalRange  : 
+  Module       : smart_credit_manage
+  MASTER       : smart_credit_manage
+  -----------------------------------------------------------------------------
+  Tag          : RegInput-ML
+  Description  : Input port '[Signal]' is not registered [module:[MASTER]]
+  Violation    : Lint:2583
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./inout_ports.sv
+  LineNumber   : 123
+  Statement    :     input [P-1 : 0] any_ovc_granted_in_outport_all;   
+  Signal       : any_ovc_granted_in_outport_all
+  SignalRange  : 
+  Module       : inout_ports
+  MASTER       : inout_ports
+  -----------------------------------------------------------------------------
+  Tag          : RegInput-ML
+  Description  : Input port '[Signal]' is not registered [module:[MASTER]]
+  Violation    : Lint:2630
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./flit_buffer.sv
+  LineNumber   : 80
+  Statement    :     input [V-1 :0]  multiple_dest;
+  Signal       : multiple_dest
+  Module       : flit_buffer
+  MASTER       : flit_buffer
+  -----------------------------------------------------------------------------
+  Tag          : RegInput-ML
+  Description  : Input port '[Signal]' is not registered [module:[MASTER]]
+  Violation    : Lint:2731
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./output_ports.sv
+  LineNumber   : 477
+  Statement    :     input [V-1 : 0]  flit_is_tail;
+  Signal       : flit_is_tail
+  Module       : oport_ovc_sig_gen
+  MASTER       : oport_ovc_sig_gen
+  -----------------------------------------------------------------------------
+  Tag          : RegInput-ML
+  Description  : Input port '[Signal]' is not registered [module:[MASTER]]
+  Violation    : Lint:2573
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./inout_ports.sv
+  LineNumber   : 111
+  Statement    :     input [PV-1 : 0] vsa_ovc_allocated_all;
+  Signal       : vsa_ovc_allocated_all
+  SignalRange  : 
+  Module       : inout_ports
+  MASTER       : inout_ports
+  -----------------------------------------------------------------------------
+  Tag          : RegInput-ML
+  Description  : Input port '[Signal]' is not registered [module:[MASTER]]
+  Violation    : Lint:2638
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./flit_buffer.sv
+  LineNumber   : 441
+  Statement    :     input [ADDR_WIDTH-1 :    0]  wr_addr;
+  Signal       : wr_addr
+  Module       : fifo_ram
+  MASTER       : fifo_ram
+  -----------------------------------------------------------------------------
+  Tag          : RegInput-ML
+  Description  : Input port '[Signal]' is not registered [module:[MASTER]]
+  Violation    : Lint:2830
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber   : 584
+  Statement    :     input smart_chanel_t ss_smart_chanel_new;
+  Signal       : ss_smart_chanel_new
+  Module       : smart_allocator_per_iport
+  MASTER       : smart_allocator_per_iport
+  -----------------------------------------------------------------------------
+  Tag          : RegInput-ML
+  Description  : Input port '[Signal]' is not registered [module:[MASTER]]
+  Violation    : Lint:2838
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber   : 463
+  Statement    :     smart_requests_i,
+  Signal       : smart_requests_i
+  Module       : smart_validity_check_per_ivc
+  MASTER       : smart_validity_check_per_ivc
+  -----------------------------------------------------------------------------
+  Tag          : RegInput-ML
+  Description  : Input port '[Signal]' is not registered [module:[MASTER]]
+  Violation    : Lint:2631
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./flit_buffer.sv
+  LineNumber   : 81
+  Statement    :     input [V-1 :0]  sub_rd_ptr_ld;
+  Signal       : sub_rd_ptr_ld
+  Module       : flit_buffer
+  MASTER       : flit_buffer
+  -----------------------------------------------------------------------------
+  Tag          : RegInput-ML
+  Description  : Input port '[Signal]' is not registered [module:[MASTER]]
+  Violation    : Lint:2671
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./routing.v
+  LineNumber   : 277
+  Statement    :     input   [RAw-1   :   0]  current_r_addr;
+  Signal       : current_r_addr
+  SignalRange  : 
+  Module       : look_ahead_routing
+  MASTER       : look_ahead_routing
+  -----------------------------------------------------------------------------
+  Tag          : RegInput-ML
+  Description  : Input port '[Signal]' is not registered [module:[MASTER]]
+  Violation    : Lint:2560
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./inout_ports.sv
+  LineNumber   : 110
+  Statement    :     input [PV-1 : 0] credit_in_all;
+  Signal       : credit_in_all
+  SignalRange  : 
+  Module       : inout_ports
+  MASTER       : inout_ports
+  -----------------------------------------------------------------------------
+  Tag          : RegInput-ML
+  Description  : Input port '[Signal]' is not registered [module:[MASTER]]
+  Violation    : Lint:2852
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber   : 724
+  Statement    :     input [V-1 : 0]  credit_in, smart_credit_in;
+  Signal       : credit_in
+  SignalRange  : 
+  Module       : smart_credit_manage
+  MASTER       : smart_credit_manage
+  -----------------------------------------------------------------------------
+  Tag          : RegInput-ML
+  Description  : Input port '[Signal]' is not registered [module:[MASTER]]
+  Violation    : Lint:2662
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./mesh_torus_routting.v
+  LineNumber   : 579
+  Statement    :     input sw_loc_val;
+  Signal       : sw_loc_val
+  Module       : add_sw_loc_one_hot_val
+  MASTER       : add_sw_loc_one_hot_val
+  -----------------------------------------------------------------------------
+  Tag          : RegInput-ML
+  Description  : Input port '[Signal]' is not registered [module:[MASTER]]
+  Violation    : Lint:2550
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./mesh_torus_noc_top.sv
+  LineNumber   : 43
+  Statement    :     input   smartflit_chanel_t chan_in_all  [NE-1 : 0];
+  Signal       : chan_in_all
+  Module       : mesh_torus_noc_top
+  MASTER       : mesh_torus_noc_top
+  -----------------------------------------------------------------------------
+  Tag          : RegInput-ML
+  Description  : Input port '[Signal]' is not registered [module:[MASTER]]
+  Violation    : Lint:2828
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber   : 580
+  Statement    :     input [V-1 : 0] ovc_locally_requested;
+  Signal       : ovc_locally_requested
+  SignalRange  : 
+  Module       : smart_allocator_per_iport
+  MASTER       : smart_allocator_per_iport
+  -----------------------------------------------------------------------------
+  Tag          : RegInput-ML
+  Description  : Input port '[Signal]' is not registered [module:[MASTER]]
+  Violation    : Lint:2789
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./comb_nonspec.sv
+  LineNumber   : 634
+  Statement    :     input  [ARBITER_WIDTH-1 : 0] vc_weight_is_consumed;
+  Signal       : vc_weight_is_consumed
+  Module       : swa_input_port_arbiter
+  MASTER       : swa_input_port_arbiter
+  -----------------------------------------------------------------------------
+  Tag          : RegInput-ML
+  Description  : Input port '[Signal]' is not registered [module:[MASTER]]
+  Violation    : Lint:2735
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./output_ports.sv
+  LineNumber   : 481
+  Statement    :     input [V-1 : 0] first_arbiter_granted_ivc;
+  Signal       : first_arbiter_granted_ivc
+  Module       : oport_ovc_sig_gen
+  MASTER       : oport_ovc_sig_gen
+  -----------------------------------------------------------------------------
+  Tag          : RegInput-ML
+  Description  : Input port '[Signal]' is not registered [module:[MASTER]]
+  Violation    : Lint:2814
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./../main_comp.v
+  LineNumber   : 241
+  Statement    :     input   [BIN_WIDTH-1 : 0]  bin_code,
+  Signal       : bin_code
+  Module       : bin_to_one_hot
+  MASTER       : bin_to_one_hot
+  -----------------------------------------------------------------------------
+  Tag          : RegInput-ML
+  Description  : Input port '[Signal]' is not registered [module:[MASTER]]
+  Violation    : Lint:2740
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./output_ports.sv
+  LineNumber   : 555
+  Statement    :     input [V-1 : 0]  assigned_ovc_num,granted_ovc_num,ssa_granted_ovc_num;
+  Signal       : ssa_granted_ovc_num
+  Module       : full_ovc_predictor
+  MASTER       : full_ovc_predictor
+  -----------------------------------------------------------------------------
+  Tag          : RegInput-ML
+  Description  : Input port '[Signal]' is not registered [module:[MASTER]]
+  Violation    : Lint:2727
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./congestion_analyzer.v
+  LineNumber   : 353
+  Statement    :     input [PV-1 : 0] credit_decreased_all;
+  Signal       : credit_decreased_all
+  Module       : port_pre_sel_gen
+  MASTER       : port_pre_sel_gen
+  -----------------------------------------------------------------------------
+  Tag          : RegInput-ML
+  Description  : Input port '[Signal]' is not registered [module:[MASTER]]
+  Violation    : Lint:2775
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./comb_nonspec.sv
+  LineNumber   : 76
+  Statement    :     input  [PV-1 : 0] pck_is_single_flit_all;
+  Signal       : pck_is_single_flit_all
+  SignalRange  : 
+  Module       : comb_nonspec_allocator
+  MASTER       : comb_nonspec_allocator
+  -----------------------------------------------------------------------------
+  Tag          : RegInput-ML
+  Description  : Input port '[Signal]' is not registered [module:[MASTER]]
+  Violation    : Lint:2823
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber   : 574
+  Statement    :     input [RAw-1:  0]  neighbors_r_addr_i [P-1 : 0];
+  Signal       : neighbors_r_addr_i
+  Module       : smart_allocator_per_iport
+  MASTER       : smart_allocator_per_iport
+  -----------------------------------------------------------------------------
+  Tag          : RegInput-ML
+  Description  : Input port '[Signal]' is not registered [module:[MASTER]]
+  Violation    : Lint:2818
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber   : 330
+  Statement    :     input smart_chanel_t smart_chanel_new  [P-1 : 0];
+  Signal       : smart_chanel_new
+  Module       : smart_bypass_chanels
+  MASTER       : smart_bypass_chanels
+  -----------------------------------------------------------------------------
+  Tag          : RegInput-ML
+  Description  : Input port '[Signal]' is not registered [module:[MASTER]]
+  Violation    : Lint:2677
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./mesh_torus_routting.v
+  LineNumber   : 46
+  Statement    :     input [Yw-1 : 0]  current_y;                  
+  Signal       : current_y
+  SignalRange  : 
+  Module       : mesh_torus_look_ahead_routing
+  MASTER       : mesh_torus_look_ahead_routing
+  -----------------------------------------------------------------------------
+  Tag          : RegInput-ML
+  Description  : Input port '[Signal]' is not registered [module:[MASTER]]
+  Violation    : Lint:2842
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber   : 468
+  Statement    :     flit_tail_flag_i,
+  Signal       : flit_tail_flag_i
+  Module       : smart_validity_check_per_ivc
+  MASTER       : smart_validity_check_per_ivc
+
+  -----------------------------------------------------------------------------
+  RegOutputs  (160 warnings/0 waived/300 compressed)
+  -----------------------------------------------------------------------------
+  Tag          : RegOutputs
+  Description  : Port '[Signal]' is not driven by a register
+  Violation    : Lint:420
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./noc_top.sv
+  LineNumber   : 53
+  Statement    :         ) noc_top (
+  Module       : noc_top
+  Signal       : router_event[2][0].pck_wr_o
+  -----------------------------------------------------------------------------
+  Tag          : RegOutputs
+  Description  : Port '[Signal]' is not driven by a register
+  Violation    : Lint:184
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./noc_top.sv
+  LineNumber   : 53
+  Statement    :         ) noc_top (
+  Module       : noc_top
+  Signal       : chan_out_all[1].flit_chanel.flit.hdr_flag
+  -----------------------------------------------------------------------------
+  Tag          : RegOutputs
+  Description  : Port '[Signal]' is not driven by a register
+  Violation    : Lint:412
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./noc_top.sv
+  LineNumber   : 53
+  Statement    :         ) noc_top (
+  Module       : noc_top
+  Signal       : router_event[1][2].flit_wr_o
+  -----------------------------------------------------------------------------
+  Tag          : RegOutputs
+  Description  : Port '[Signal]' is not driven by a register
+  Violation    : Lint:435
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./noc_top.sv
+  LineNumber   : 53
+  Statement    :         ) noc_top (
+  Module       : noc_top
+  Signal       : router_event[2][2].pck_wr_o
+  -----------------------------------------------------------------------------
+  Tag          : RegOutputs
+  Description  : Port '[Signal]' is not driven by a register
+  Violation    : Lint:294
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./noc_top.sv
+  LineNumber   : 53
+  Statement    :         ) noc_top (
+  Module       : noc_top
+  Signal       : chan_out_all[3].smart_chanel.dest_e_addr
+  SignalRange  : 1-0
+  -----------------------------------------------------------------------------
+  Tag          : RegOutputs
+  Description  : Port '[Signal]' is not driven by a register
+  Violation    : Lint:423
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./noc_top.sv
+  LineNumber   : 53
+  Statement    :         ) noc_top (
+  Module       : noc_top
+  Signal       : router_event[2][1].empty
+  -----------------------------------------------------------------------------
+  Tag          : RegOutputs
+  Description  : Port '[Signal]' is not driven by a register
+  Violation    : Lint:375
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./noc_top.sv
+  LineNumber   : 53
+  Statement    :         ) noc_top (
+  Module       : noc_top
+  Signal       : router_event[0][1].empty
+  -----------------------------------------------------------------------------
+  Tag          : RegOutputs
+  Description  : Port '[Signal]' is not driven by a register
+  Violation    : Lint:415
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./noc_top.sv
+  LineNumber   : 53
+  Statement    :         ) noc_top (
+  Module       : noc_top
+  Signal       : router_event[1][2].bypassed_num
+  SignalRange  : 1-0
+  -----------------------------------------------------------------------------
+  Tag          : RegOutputs
+  Description  : Port '[Signal]' is not driven by a register
+  Violation    : Lint:12
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./noc_top.sv
+  LineNumber   : 53
+  Statement    :         ) noc_top (
+  Module       : noc_top
+  Signal       : chan_out_all[0].ctrl_chanel.router_addr
+  SignalRange  : 1-0
+  -----------------------------------------------------------------------------
+  Tag          : RegOutputs
+  Description  : Port '[Signal]' is not driven by a register
+  Violation    : Lint:430
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./noc_top.sv
+  LineNumber   : 53
+  Statement    :         ) noc_top (
+  Module       : noc_top
+  Signal       : router_event[2][1].bypassed_num
+  SignalRange  : 1-0
+  -----------------------------------------------------------------------------
+  Tag          : RegOutputs
+  Description  : Port '[Signal]' is not driven by a register
+  Violation    : Lint:439
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./noc_top.sv
+  LineNumber   : 53
+  Statement    :         ) noc_top (
+  Module       : noc_top
+  Signal       : router_event[2][2].bypassed_num
+  SignalRange  : 1-0
+  -----------------------------------------------------------------------------
+  Tag          : RegOutputs
+  Description  : Port '[Signal]' is not driven by a register
+  Violation    : Lint:297
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./noc_top.sv
+  LineNumber   : 53
+  Statement    :         ) noc_top (
+  Module       : noc_top
+  Signal       : chan_out_all[3].smart_chanel.requests
+  SignalRange  : 2-0
+  -----------------------------------------------------------------------------
+  Tag          : RegOutputs
+  Description  : Port '[Signal]' is not driven by a register
+  Violation    : Lint:417
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./noc_top.sv
+  LineNumber   : 53
+  Statement    :         ) noc_top (
+  Module       : noc_top
+  Signal       : router_event[2][0].empty
+  -----------------------------------------------------------------------------
+  Tag          : RegOutputs
+  Description  : Port '[Signal]' is not driven by a register
+  Violation    : Lint:454
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./noc_top.sv
+  LineNumber   : 53
+  Statement    :         ) noc_top (
+  Module       : noc_top
+  Signal       : router_event[3][1].bypassed_num
+  SignalRange  : 1-0
+  -----------------------------------------------------------------------------
+  Tag          : RegOutputs
+  Description  : Port '[Signal]' is not driven by a register
+  Violation    : Lint:20
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./noc_top.sv
+  LineNumber   : 53
+  Statement    :         ) noc_top (
+  Module       : noc_top
+  Signal       : chan_out_all[0].smart_chanel.hdr_flit
+  -----------------------------------------------------------------------------
+  Tag          : RegOutputs
+  Description  : Port '[Signal]' is not driven by a register
+  Violation    : Lint:393
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./noc_top.sv
+  LineNumber   : 53
+  Statement    :         ) noc_top (
+  Module       : noc_top
+  Signal       : router_event[1][0].empty
+  -----------------------------------------------------------------------------
+  Tag          : RegOutputs
+  Description  : Port '[Signal]' is not driven by a register
+  Violation    : Lint:17
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./noc_top.sv
+  LineNumber   : 53
+  Statement    :         ) noc_top (
+  Module       : noc_top
+  Signal       : chan_out_all[0].smart_chanel.bypassed_num
+  SignalRange  : 1-0
+  -----------------------------------------------------------------------------
+  Tag          : RegOutputs
+  Description  : Port '[Signal]' is not driven by a register
+  Violation    : Lint:27
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./noc_top.sv
+  LineNumber   : 53
+  Statement    :         ) noc_top (
+  Module       : noc_top
+  Signal       : chan_out_all[0].flit_chanel.flit.payload
+  SignalRange  : 63-0
+  -----------------------------------------------------------------------------
+  Tag          : RegOutputs
+  Description  : Port '[Signal]' is not driven by a register
+  Violation    : Lint:293
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./noc_top.sv
+  LineNumber   : 53
+  Statement    :         ) noc_top (
+  Module       : noc_top
+  Signal       : chan_out_all[3].smart_chanel.hdr_flit
+  -----------------------------------------------------------------------------
+  Tag          : RegOutputs
+  Description  : Port '[Signal]' is not driven by a register
+  Violation    : Lint:452
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./noc_top.sv
+  LineNumber   : 53
+  Statement    :         ) noc_top (
+  Module       : noc_top
+  Signal       : router_event[3][1].pck_wr_i
+  -----------------------------------------------------------------------------
+  Tag          : RegOutputs
+  Description  : Port '[Signal]' is not driven by a register
+  Violation    : Lint:290
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./noc_top.sv
+  LineNumber   : 53
+  Statement    :         ) noc_top (
+  Module       : noc_top
+  Signal       : chan_out_all[3].smart_chanel.bypassed_num
+  SignalRange  : 1-0
+  -----------------------------------------------------------------------------
+  Tag          : RegOutputs
+  Description  : Port '[Signal]' is not driven by a register
+  Violation    : Lint:437
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./noc_top.sv
+  LineNumber   : 53
+  Statement    :         ) noc_top (
+  Module       : noc_top
+  Signal       : router_event[2][2].pck_wr_i
+  -----------------------------------------------------------------------------
+  Tag          : RegOutputs
+  Description  : Port '[Signal]' is not driven by a register
+  Violation    : Lint:418
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./noc_top.sv
+  LineNumber   : 53
+  Statement    :         ) noc_top (
+  Module       : noc_top
+  Signal       : router_event[2][0].active_high_reset
+  -----------------------------------------------------------------------------
+  Tag          : RegOutputs
+  Description  : Port '[Signal]' is not driven by a register
+  Violation    : Lint:462
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./noc_top.sv
+  LineNumber   : 53
+  Statement    :         ) noc_top (
+  Module       : noc_top
+  Signal       : router_event[3][2].flit_wr_i
+  -----------------------------------------------------------------------------
+  Tag          : RegOutputs
+  Description  : Port '[Signal]' is not driven by a register
+  Violation    : Lint:434
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./noc_top.sv
+  LineNumber   : 53
+  Statement    :         ) noc_top (
+  Module       : noc_top
+  Signal       : router_event[2][2].flit_in_bypassed
+  -----------------------------------------------------------------------------
+  Tag          : RegOutputs
+  Description  : Port '[Signal]' is not driven by a register
+  Violation    : Lint:456
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./noc_top.sv
+  LineNumber   : 53
+  Statement    :         ) noc_top (
+  Module       : noc_top
+  Signal       : router_event[3][2].empty
+  -----------------------------------------------------------------------------
+  Tag          : RegOutputs
+  Description  : Port '[Signal]' is not driven by a register
+  Violation    : Lint:368
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./noc_top.sv
+  LineNumber   : 53
+  Statement    :         ) noc_top (
+  Module       : noc_top
+  Signal       : chan_out_all[3].flit_chanel.flit_wr
+  -----------------------------------------------------------------------------
+  Tag          : RegOutputs
+  Description  : Port '[Signal]' is not driven by a register
+  Violation    : Lint:436
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./noc_top.sv
+  LineNumber   : 53
+  Statement    :         ) noc_top (
+  Module       : noc_top
+  Signal       : router_event[2][2].flit_wr_o
+  -----------------------------------------------------------------------------
+  Tag          : RegOutputs
+  Description  : Port '[Signal]' is not driven by a register
+  Violation    : Lint:23
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./noc_top.sv
+  LineNumber   : 53
+  Statement    :         ) noc_top (
+  Module       : noc_top
+  Signal       : chan_out_all[0].smart_chanel.ovc[0]
+  -----------------------------------------------------------------------------
+  Tag          : RegOutputs
+  Description  : Port '[Signal]' is not driven by a register
+  Violation    : Lint:108
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./noc_top.sv
+  LineNumber   : 53
+  Statement    :         ) noc_top (
+  Module       : noc_top
+  Signal       : chan_out_all[1].smart_chanel.bypassed_num
+  SignalRange  : 1-0
+  -----------------------------------------------------------------------------
+  Tag          : RegOutputs
+  Description  : Port '[Signal]' is not driven by a register
+  Violation    : Lint:373
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./noc_top.sv
+  LineNumber   : 53
+  Statement    :         ) noc_top (
+  Module       : noc_top
+  Signal       : router_event[0][0].flit_wr_o
+  -----------------------------------------------------------------------------
+  Tag          : RegOutputs
+  Description  : Port '[Signal]' is not driven by a register
+  Violation    : Lint:107
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./noc_top.sv
+  LineNumber   : 53
+  Statement    :         ) noc_top (
+  Module       : noc_top
+  Signal       : chan_out_all[1].ctrl_chanel.endp_port
+  -----------------------------------------------------------------------------
+  Tag          : RegOutputs
+  Description  : Port '[Signal]' is not driven by a register
+  Violation    : Lint:385
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./noc_top.sv
+  LineNumber   : 53
+  Statement    :         ) noc_top (
+  Module       : noc_top
+  Signal       : router_event[0][2].active_high_reset
+  -----------------------------------------------------------------------------
+  Tag          : RegOutputs
+  Description  : Port '[Signal]' is not driven by a register
+  Violation    : Lint:388
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./noc_top.sv
+  LineNumber   : 53
+  Statement    :         ) noc_top (
+  Module       : noc_top
+  Signal       : router_event[0][2].flit_wr_o
+  -----------------------------------------------------------------------------
+  Tag          : RegOutputs
+  Description  : Port '[Signal]' is not driven by a register
+  Violation    : Lint:103
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./noc_top.sv
+  LineNumber   : 53
+  Statement    :         ) noc_top (
+  Module       : noc_top
+  Signal       : chan_out_all[1].ctrl_chanel.router_addr
+  SignalRange  : 1-0
+  -----------------------------------------------------------------------------
+  Tag          : RegOutputs
+  Description  : Port '[Signal]' is not driven by a register
+  Violation    : Lint:115
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./noc_top.sv
+  LineNumber   : 53
+  Statement    :         ) noc_top (
+  Module       : noc_top
+  Signal       : chan_out_all[1].smart_chanel.requests
+  SignalRange  : 2-0
+  -----------------------------------------------------------------------------
+  Tag          : RegOutputs
+  Description  : Port '[Signal]' is not driven by a register
+  Violation    : Lint:401
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./noc_top.sv
+  LineNumber   : 53
+  Statement    :         ) noc_top (
+  Module       : noc_top
+  Signal       : router_event[1][1].flit_in_bypassed
+  -----------------------------------------------------------------------------
+  Tag          : RegOutputs
+  Description  : Port '[Signal]' is not driven by a register
+  Violation    : Lint:386
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./noc_top.sv
+  LineNumber   : 53
+  Statement    :         ) noc_top (
+  Module       : noc_top
+  Signal       : router_event[0][2].flit_in_bypassed
+  -----------------------------------------------------------------------------
+  Tag          : RegOutputs
+  Description  : Port '[Signal]' is not driven by a register
+  Violation    : Lint:6
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./noc_top.sv
+  LineNumber   : 53
+  Statement    :         ) noc_top (
+  Module       : noc_top
+  Signal       : chan_out_all[0].ctrl_chanel.credit_release_en[0]
+  -----------------------------------------------------------------------------
+  Tag          : RegOutputs
+  Description  : Port '[Signal]' is not driven by a register
+  Violation    : Lint:112
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./noc_top.sv
+  LineNumber   : 53
+  Statement    :         ) noc_top (
+  Module       : noc_top
+  Signal       : chan_out_all[1].smart_chanel.dest_e_addr
+  SignalRange  : 1-0
+  -----------------------------------------------------------------------------
+  Tag          : RegOutputs
+  Description  : Port '[Signal]' is not driven by a register
+  Violation    : Lint:296
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./noc_top.sv
+  LineNumber   : 53
+  Statement    :         ) noc_top (
+  Module       : noc_top
+  Signal       : chan_out_all[3].smart_chanel.ovc[0]
+  -----------------------------------------------------------------------------
+  Tag          : RegOutputs
+  Description  : Port '[Signal]' is not driven by a register
+  Violation    : Lint:400
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./noc_top.sv
+  LineNumber   : 53
+  Statement    :         ) noc_top (
+  Module       : noc_top
+  Signal       : router_event[1][1].active_high_reset
+  -----------------------------------------------------------------------------
+  Tag          : RegOutputs
+  Description  : Port '[Signal]' is not driven by a register
+  Violation    : Lint:289
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./noc_top.sv
+  LineNumber   : 53
+  Statement    :         ) noc_top (
+  Module       : noc_top
+  Signal       : chan_out_all[3].ctrl_chanel.endp_port
+  -----------------------------------------------------------------------------
+  Tag          : RegOutputs
+  Description  : Port '[Signal]' is not driven by a register
+  Violation    : Lint:276
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./noc_top.sv
+  LineNumber   : 53
+  Statement    :         ) noc_top (
+  Module       : noc_top
+  Signal       : chan_out_all[2].flit_chanel.credit[0]
+  -----------------------------------------------------------------------------
+  Tag          : RegOutputs
+  Description  : Port '[Signal]' is not driven by a register
+  Violation    : Lint:279
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./noc_top.sv
+  LineNumber   : 53
+  Statement    :         ) noc_top (
+  Module       : noc_top
+  Signal       : chan_out_all[3].ctrl_chanel.credit_release_en[0]
+  -----------------------------------------------------------------------------
+  Tag          : RegOutputs
+  Description  : Port '[Signal]' is not driven by a register
+  Violation    : Lint:366
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./noc_top.sv
+  LineNumber   : 53
+  Statement    :         ) noc_top (
+  Module       : noc_top
+  Signal       : chan_out_all[3].flit_chanel.flit.hdr_flag
+  -----------------------------------------------------------------------------
+  Tag          : RegOutputs
+  Description  : Port '[Signal]' is not driven by a register
+  Violation    : Lint:406
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./noc_top.sv
+  LineNumber   : 53
+  Statement    :         ) noc_top (
+  Module       : noc_top
+  Signal       : router_event[1][1].bypassed_num
+  SignalRange  : 1-0
+  -----------------------------------------------------------------------------
+  Tag          : RegOutputs
+  Description  : Port '[Signal]' is not driven by a register
+  Violation    : Lint:14
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./noc_top.sv
+  LineNumber   : 53
+  Statement    :         ) noc_top (
+  Module       : noc_top
+  Signal       : chan_out_all[0].ctrl_chanel.endp_addr
+  SignalRange  : 1-0
+  -----------------------------------------------------------------------------
+  Tag          : RegOutputs
+  Description  : Port '[Signal]' is not driven by a register
+  Violation    : Lint:198
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./noc_top.sv
+  LineNumber   : 53
+  Statement    :         ) noc_top (
+  Module       : noc_top
+  Signal       : chan_out_all[2].ctrl_chanel.endp_port
+  -----------------------------------------------------------------------------
+  Tag          : RegOutputs
+  Description  : Port '[Signal]' is not driven by a register
+  Violation    : Lint:432
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./noc_top.sv
+  LineNumber   : 53
+  Statement    :         ) noc_top (
+  Module       : noc_top
+  Signal       : router_event[2][2].empty
+  -----------------------------------------------------------------------------
+  Tag          : RegOutputs
+  Description  : Port '[Signal]' is not driven by a register
+  Violation    : Lint:21
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./noc_top.sv
+  LineNumber   : 53
+  Statement    :         ) noc_top (
+  Module       : noc_top
+  Signal       : chan_out_all[0].smart_chanel.dest_e_addr
+  SignalRange  : 1-0
+  -----------------------------------------------------------------------------
+  Tag          : RegOutputs
+  Description  : Port '[Signal]' is not driven by a register
+  Violation    : Lint:367
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./noc_top.sv
+  LineNumber   : 53
+  Statement    :         ) noc_top (
+  Module       : noc_top
+  Signal       : chan_out_all[3].flit_chanel.credit[0]
+  -----------------------------------------------------------------------------
+  Tag          : RegOutputs
+  Description  : Port '[Signal]' is not driven by a register
+  Violation    : Lint:410
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./noc_top.sv
+  LineNumber   : 53
+  Statement    :         ) noc_top (
+  Module       : noc_top
+  Signal       : router_event[1][2].flit_in_bypassed
+  -----------------------------------------------------------------------------
+  Tag          : RegOutputs
+  Description  : Port '[Signal]' is not driven by a register
+  Violation    : Lint:7
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./noc_top.sv
+  LineNumber   : 53
+  Statement    :         ) noc_top (
+  Module       : noc_top
+  Signal       : chan_out_all[0].ctrl_chanel.credit_init_val[0]
+  SignalRange  : 4-0
+  -----------------------------------------------------------------------------
+  Tag          : RegOutputs
+  Description  : Port '[Signal]' is not driven by a register
+  Violation    : Lint:444
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./noc_top.sv
+  LineNumber   : 53
+  Statement    :         ) noc_top (
+  Module       : noc_top
+  Signal       : router_event[3][0].pck_wr_o
+  -----------------------------------------------------------------------------
+  Tag          : RegOutputs
+  Description  : Port '[Signal]' is not driven by a register
+  Violation    : Lint:387
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./noc_top.sv
+  LineNumber   : 53
+  Statement    :         ) noc_top (
+  Module       : noc_top
+  Signal       : router_event[0][2].pck_wr_o
+  -----------------------------------------------------------------------------
+  Tag          : RegOutputs
+  Description  : Port '[Signal]' is not driven by a register
+  Violation    : Lint:92
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./noc_top.sv
+  LineNumber   : 53
+  Statement    :         ) noc_top (
+  Module       : noc_top
+  Signal       : chan_out_all[0].flit_chanel.flit.tail_flag
+  -----------------------------------------------------------------------------
+  Tag          : RegOutputs
+  Description  : Port '[Signal]' is not driven by a register
+  Violation    : Lint:110
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./noc_top.sv
+  LineNumber   : 53
+  Statement    :         ) noc_top (
+  Module       : noc_top
+  Signal       : chan_out_all[1].smart_chanel.flit_in_bypassed
+  -----------------------------------------------------------------------------
+  Tag          : RegOutputs
+  Description  : Port '[Signal]' is not driven by a register
+  Violation    : Lint:371
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./noc_top.sv
+  LineNumber   : 53
+  Statement    :         ) noc_top (
+  Module       : noc_top
+  Signal       : router_event[0][0].flit_in_bypassed
+  -----------------------------------------------------------------------------
+  Tag          : RegOutputs
+  Description  : Port '[Signal]' is not driven by a register
+  Violation    : Lint:384
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./noc_top.sv
+  LineNumber   : 53
+  Statement    :         ) noc_top (
+  Module       : noc_top
+  Signal       : router_event[0][2].empty
+  -----------------------------------------------------------------------------
+  Tag          : RegOutputs
+  Description  : Port '[Signal]' is not driven by a register
+  Violation    : Lint:93
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./noc_top.sv
+  LineNumber   : 53
+  Statement    :         ) noc_top (
+  Module       : noc_top
+  Signal       : chan_out_all[0].flit_chanel.flit.hdr_flag
+  -----------------------------------------------------------------------------
+  Tag          : RegOutputs
+  Description  : Port '[Signal]' is not driven by a register
+  Violation    : Lint:448
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./noc_top.sv
+  LineNumber   : 53
+  Statement    :         ) noc_top (
+  Module       : noc_top
+  Signal       : router_event[3][1].active_high_reset
+  -----------------------------------------------------------------------------
+  Tag          : RegOutputs
+  Description  : Port '[Signal]' is not driven by a register
+  Violation    : Lint:378
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./noc_top.sv
+  LineNumber   : 53
+  Statement    :         ) noc_top (
+  Module       : noc_top
+  Signal       : router_event[0][1].pck_wr_o
+  -----------------------------------------------------------------------------
+  Tag          : RegOutputs
+  Description  : Port '[Signal]' is not driven by a register
+  Violation    : Lint:409
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./noc_top.sv
+  LineNumber   : 53
+  Statement    :         ) noc_top (
+  Module       : noc_top
+  Signal       : router_event[1][2].active_high_reset
+  -----------------------------------------------------------------------------
+  Tag          : RegOutputs
+  Description  : Port '[Signal]' is not driven by a register
+  Violation    : Lint:379
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./noc_top.sv
+  LineNumber   : 53
+  Statement    :         ) noc_top (
+  Module       : noc_top
+  Signal       : router_event[0][1].flit_wr_o
+  -----------------------------------------------------------------------------
+  Tag          : RegOutputs
+  Description  : Port '[Signal]' is not driven by a register
+  Violation    : Lint:389
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./noc_top.sv
+  LineNumber   : 53
+  Statement    :         ) noc_top (
+  Module       : noc_top
+  Signal       : router_event[0][2].pck_wr_i
+  -----------------------------------------------------------------------------
+  Tag          : RegOutputs
+  Description  : Port '[Signal]' is not driven by a register
+  Violation    : Lint:372
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./noc_top.sv
+  LineNumber   : 53
+  Statement    :         ) noc_top (
+  Module       : noc_top
+  Signal       : router_event[0][0].pck_wr_o
+  -----------------------------------------------------------------------------
+  Tag          : RegOutputs
+  Description  : Port '[Signal]' is not driven by a register
+  Violation    : Lint:428
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./noc_top.sv
+  LineNumber   : 53
+  Statement    :         ) noc_top (
+  Module       : noc_top
+  Signal       : router_event[2][1].pck_wr_i
+  -----------------------------------------------------------------------------
+  Tag          : RegOutputs
+  Description  : Port '[Signal]' is not driven by a register
+  Violation    : Lint:300
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./noc_top.sv
+  LineNumber   : 53
+  Statement    :         ) noc_top (
+  Module       : noc_top
+  Signal       : chan_out_all[3].flit_chanel.flit.payload
+  SignalRange  : 63-0
+  -----------------------------------------------------------------------------
+  Tag          : RegOutputs
+  Description  : Port '[Signal]' is not driven by a register
+  Violation    : Lint:403
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./noc_top.sv
+  LineNumber   : 53
+  Statement    :         ) noc_top (
+  Module       : noc_top
+  Signal       : router_event[1][1].flit_wr_o
+  -----------------------------------------------------------------------------
+  Tag          : RegOutputs
+  Description  : Port '[Signal]' is not driven by a register
+  Violation    : Lint:426
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./noc_top.sv
+  LineNumber   : 53
+  Statement    :         ) noc_top (
+  Module       : noc_top
+  Signal       : router_event[2][1].pck_wr_o
+  -----------------------------------------------------------------------------
+  Tag          : RegOutputs
+  Description  : Port '[Signal]' is not driven by a register
+  Violation    : Lint:453
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./noc_top.sv
+  LineNumber   : 53
+  Statement    :         ) noc_top (
+  Module       : noc_top
+  Signal       : router_event[3][1].flit_wr_i
+  -----------------------------------------------------------------------------
+  Tag          : RegOutputs
+  Description  : Port '[Signal]' is not driven by a register
+  Violation    : Lint:199
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./noc_top.sv
+  LineNumber   : 53
+  Statement    :         ) noc_top (
+  Module       : noc_top
+  Signal       : chan_out_all[2].smart_chanel.bypassed_num
+  SignalRange  : 1-0
+  -----------------------------------------------------------------------------
+  Tag          : RegOutputs
+  Description  : Port '[Signal]' is not driven by a register
+  Violation    : Lint:381
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./noc_top.sv
+  LineNumber   : 53
+  Statement    :         ) noc_top (
+  Module       : noc_top
+  Signal       : router_event[0][1].flit_wr_i
+  -----------------------------------------------------------------------------
+  Tag          : RegOutputs
+  Description  : Port '[Signal]' is not driven by a register
+  Violation    : Lint:364
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./noc_top.sv
+  LineNumber   : 53
+  Statement    :         ) noc_top (
+  Module       : noc_top
+  Signal       : chan_out_all[3].flit_chanel.flit.vc[0]
+  -----------------------------------------------------------------------------
+  Tag          : RegOutputs
+  Description  : Port '[Signal]' is not driven by a register
+  Violation    : Lint:183
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./noc_top.sv
+  LineNumber   : 53
+  Statement    :         ) noc_top (
+  Module       : noc_top
+  Signal       : chan_out_all[1].flit_chanel.flit.tail_flag
+  -----------------------------------------------------------------------------
+  Tag          : RegOutputs
+  Description  : Port '[Signal]' is not driven by a register
+  Violation    : Lint:421
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./noc_top.sv
+  LineNumber   : 53
+  Statement    :         ) noc_top (
+  Module       : noc_top
+  Signal       : router_event[2][0].flit_wr_o
+  -----------------------------------------------------------------------------
+  Tag          : RegOutputs
+  Description  : Port '[Signal]' is not driven by a register
+  Violation    : Lint:451
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./noc_top.sv
+  LineNumber   : 53
+  Statement    :         ) noc_top (
+  Module       : noc_top
+  Signal       : router_event[3][1].flit_wr_o
+  -----------------------------------------------------------------------------
+  Tag          : RegOutputs
+  Description  : Port '[Signal]' is not driven by a register
+  Violation    : Lint:111
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./noc_top.sv
+  LineNumber   : 53
+  Statement    :         ) noc_top (
+  Module       : noc_top
+  Signal       : chan_out_all[1].smart_chanel.hdr_flit
+  -----------------------------------------------------------------------------
+  Tag          : RegOutputs
+  Description  : Port '[Signal]' is not driven by a register
+  Violation    : Lint:429
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./noc_top.sv
+  LineNumber   : 53
+  Statement    :         ) noc_top (
+  Module       : noc_top
+  Signal       : router_event[2][1].flit_wr_i
+  -----------------------------------------------------------------------------
+  Tag          : RegOutputs
+  Description  : Port '[Signal]' is not driven by a register
+  Violation    : Lint:446
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./noc_top.sv
+  LineNumber   : 53
+  Statement    :         ) noc_top (
+  Module       : noc_top
+  Signal       : router_event[3][0].pck_wr_i
+  -----------------------------------------------------------------------------
+  Tag          : RegOutputs
+  Description  : Port '[Signal]' is not driven by a register
+  Violation    : Lint:463
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./noc_top.sv
+  LineNumber   : 53
+  Statement    :         ) noc_top (
+  Module       : noc_top
+  Signal       : router_event[3][2].bypassed_num
+  SignalRange  : 1-0
+  -----------------------------------------------------------------------------
+  Tag          : RegOutputs
+  Description  : Port '[Signal]' is not driven by a register
+  Violation    : Lint:203
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./noc_top.sv
+  LineNumber   : 53
+  Statement    :         ) noc_top (
+  Module       : noc_top
+  Signal       : chan_out_all[2].smart_chanel.dest_e_addr
+  SignalRange  : 1-0
+  -----------------------------------------------------------------------------
+  Tag          : RegOutputs
+  Description  : Port '[Signal]' is not driven by a register
+  Violation    : Lint:377
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./noc_top.sv
+  LineNumber   : 53
+  Statement    :         ) noc_top (
+  Module       : noc_top
+  Signal       : router_event[0][1].flit_in_bypassed
+  -----------------------------------------------------------------------------
+  Tag          : RegOutputs
+  Description  : Port '[Signal]' is not driven by a register
+  Violation    : Lint:292
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./noc_top.sv
+  LineNumber   : 53
+  Statement    :         ) noc_top (
+  Module       : noc_top
+  Signal       : chan_out_all[3].smart_chanel.flit_in_bypassed
+  -----------------------------------------------------------------------------
+  Tag          : RegOutputs
+  Description  : Port '[Signal]' is not driven by a register
+  Violation    : Lint:380
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./noc_top.sv
+  LineNumber   : 53
+  Statement    :         ) noc_top (
+  Module       : noc_top
+  Signal       : router_event[0][1].pck_wr_i
+  -----------------------------------------------------------------------------
+  Tag          : RegOutputs
+  Description  : Port '[Signal]' is not driven by a register
+  Violation    : Lint:442
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./noc_top.sv
+  LineNumber   : 53
+  Statement    :         ) noc_top (
+  Module       : noc_top
+  Signal       : router_event[3][0].active_high_reset
+  -----------------------------------------------------------------------------
+  Tag          : RegOutputs
+  Description  : Port '[Signal]' is not driven by a register
+  Violation    : Lint:16
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./noc_top.sv
+  LineNumber   : 53
+  Statement    :         ) noc_top (
+  Module       : noc_top
+  Signal       : chan_out_all[0].ctrl_chanel.endp_port
+  -----------------------------------------------------------------------------
+  Tag          : RegOutputs
+  Description  : Port '[Signal]' is not driven by a register
+  Violation    : Lint:274
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./noc_top.sv
+  LineNumber   : 53
+  Statement    :         ) noc_top (
+  Module       : noc_top
+  Signal       : chan_out_all[2].flit_chanel.flit.tail_flag
+  -----------------------------------------------------------------------------
+  Tag          : RegOutputs
+  Description  : Port '[Signal]' is not driven by a register
+  Violation    : Lint:118
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./noc_top.sv
+  LineNumber   : 53
+  Statement    :         ) noc_top (
+  Module       : noc_top
+  Signal       : chan_out_all[1].flit_chanel.flit.payload
+  SignalRange  : 63-0
+  -----------------------------------------------------------------------------
+  Tag          : RegOutputs
+  Description  : Port '[Signal]' is not driven by a register
+  Violation    : Lint:285
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./noc_top.sv
+  LineNumber   : 53
+  Statement    :         ) noc_top (
+  Module       : noc_top
+  Signal       : chan_out_all[3].ctrl_chanel.router_addr
+  SignalRange  : 1-0
+  -----------------------------------------------------------------------------
+  Tag          : RegOutputs
+  Description  : Port '[Signal]' is not driven by a register
+  Violation    : Lint:402
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./noc_top.sv
+  LineNumber   : 53
+  Statement    :         ) noc_top (
+  Module       : noc_top
+  Signal       : router_event[1][1].pck_wr_o
+  -----------------------------------------------------------------------------
+  Tag          : RegOutputs
+  Description  : Port '[Signal]' is not driven by a register
+  Violation    : Lint:395
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./noc_top.sv
+  LineNumber   : 53
+  Statement    :         ) noc_top (
+  Module       : noc_top
+  Signal       : router_event[1][0].flit_in_bypassed
+  -----------------------------------------------------------------------------
+  Tag          : RegOutputs
+  Description  : Port '[Signal]' is not driven by a register
+  Violation    : Lint:390
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./noc_top.sv
+  LineNumber   : 53
+  Statement    :         ) noc_top (
+  Module       : noc_top
+  Signal       : router_event[0][2].flit_wr_i
+  -----------------------------------------------------------------------------
+  Tag          : RegOutputs
+  Description  : Port '[Signal]' is not driven by a register
+  Violation    : Lint:422
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./noc_top.sv
+  LineNumber   : 53
+  Statement    :         ) noc_top (
+  Module       : noc_top
+  Signal       : router_event[2][0].pck_wr_i
+  -----------------------------------------------------------------------------
+  Tag          : RegOutputs
+  Description  : Port '[Signal]' is not driven by a register
+  Violation    : Lint:441
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./noc_top.sv
+  LineNumber   : 53
+  Statement    :         ) noc_top (
+  Module       : noc_top
+  Signal       : router_event[3][0].empty
+  -----------------------------------------------------------------------------
+  Tag          : RegOutputs
+  Description  : Port '[Signal]' is not driven by a register
+  Violation    : Lint:369
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./noc_top.sv
+  LineNumber   : 53
+  Statement    :         ) noc_top (
+  Module       : noc_top
+  Signal       : router_event[0][0].empty
+  -----------------------------------------------------------------------------
+  Tag          : RegOutputs
+  Description  : Port '[Signal]' is not driven by a register
+  Violation    : Lint:438
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./noc_top.sv
+  LineNumber   : 53
+  Statement    :         ) noc_top (
+  Module       : noc_top
+  Signal       : router_event[2][2].flit_wr_i
+  -----------------------------------------------------------------------------
+  Tag          : RegOutputs
+  Description  : Port '[Signal]' is not driven by a register
+  Violation    : Lint:5
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./noc_top.sv
+  LineNumber   : 53
+  Statement    :         ) noc_top (
+  Module       : noc_top
+  Signal       : chan_out_all[0].ctrl_chanel.hetero_ovc_presence[0]
+  -----------------------------------------------------------------------------
+  Tag          : RegOutputs
+  Description  : Port '[Signal]' is not driven by a register
+  Violation    : Lint:187
+  Goal         : lint_rtl
+  FileName     : ./../../rtl/src_noc/./noc_top.sv
+  LineNumber   : 53
+  Statement    :         ) noc_top (
+  Module       : noc_top
+  Signal       : chan_out_all[2].ctrl_chanel.hetero_ovc_presence[0]
+
+  -----------------------------------------------------------------------------
+  SigName  (5 warnings/0 waived)
+  -----------------------------------------------------------------------------
+  Tag           : SigName
+  Description   : Signal [Signal] does not follow naming convention
+  Violation     : Lint:3163
+  Goal          : lint_rtl
+  Module        : router_two_stage
+  FileName      : ./../../rtl/src_noc/./router_two_stage.sv
+  LineNumber    : 117
+  Statement     :     wire  [PV-1 : 0] spec_first_arbiter_granted_ivc_all;
+  Signal        : spec_first_arbiter_granted_ivc_all
+  -----------------------------------------------------------------------------
+  Tag           : SigName
+  Description   : Signal [Signal] does not follow naming convention
+  Violation     : Lint:3162
+  Goal          : lint_rtl
+  Module        : router_two_stage
+  FileName      : ./../../rtl/src_noc/./router_two_stage.sv
+  LineNumber    : 116
+  Statement     :     wire  [PV-1 : 0] nonspec_first_arbiter_granted_ivc_all;
+  Signal        : nonspec_first_arbiter_granted_ivc_all
+  -----------------------------------------------------------------------------
+  Tag           : SigName
+  Description   : Signal [Signal] does not follow naming convention
+  Violation     : Lint:3164
+  Goal          : lint_rtl
+  Module        : router_two_stage
+  FileName      : ./../../rtl/src_noc/./router_two_stage.sv
+  LineNumber    : 123
+  Statement     :     wire  [P-1 : 0] granted_dst_is_from_a_single_flit_pck;
+  Signal        : granted_dst_is_from_a_single_flit_pck
+  -----------------------------------------------------------------------------
+  Tag           : SigName
+  Description   : Signal [Signal] does not follow naming convention
+  Violation     : Lint:3161
+  Goal          : lint_rtl
+  Module        : vc_alloc_request_gen
+  FileName      : ./../../rtl/src_noc/./inout_ports.sv
+  LineNumber    : 483
+  Statement     :     wire [PV-1 : 0] non_vsa_ivc_num_getting_ovc_grant_all;   
+  Signal        : non_vsa_ivc_num_getting_ovc_grant_all
+  -----------------------------------------------------------------------------
+  Tag           : SigName
+  Description   : Signal [Signal] does not follow naming convention
+  Violation     : Lint:3160
+  Goal          : lint_rtl
+  Module        : comb_nonspec_allocator
+  FileName      : ./../../rtl/src_noc/./comb_nonspec.sv
+  LineNumber    : 129
+  Statement     :     wire   [V-1 : 0] first_arbiter_granted_ivc_per_port[P-1 : 0] ;
+  Signal        : first_arbiter_granted_ivc_per_port
+
+  -----------------------------------------------------------------------------
+  STARC05-1.1.1.2  (4 warnings/0 waived)
+  -----------------------------------------------------------------------------
+  Tag           : STARC05-1.1.1.2
+  Description   : '[NodeName]' does not follow naming convention
+  Violation     : Lint:3508
+  Goal          : lint_rtl
+  Module        : line_ring_destp_decoder
+  FileName      : ./../../rtl/src_noc/./mesh_torus.sv
+  LineNumber    : 1330
+  Statement     :     end else begin :_me
+  NodeName      : _me
+  -----------------------------------------------------------------------------
+  Tag           : STARC05-1.1.1.2
+  Description   : '[NodeName]' does not follow naming convention
+  Violation     : Lint:3505
+  Goal          : lint_rtl
+  Module        : smart_forward_ivc_info
+  FileName      : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber    : 276
+  Statement     :         ) _or (
+  NodeName      : _or
+  -----------------------------------------------------------------------------
+  Tag           : STARC05-1.1.1.2
+  Description   : '[NodeName]' does not follow naming convention
+  Violation     : Lint:3507
+  Goal          : lint_rtl
+  Module        : line_ring_destp_decoder
+  FileName      : ./../../rtl/src_noc/./mesh_torus.sv
+  LineNumber    : 1318
+  Statement     :     if(NL==1) begin :_se
+  NodeName      : _se
+  -----------------------------------------------------------------------------
+  Tag           : STARC05-1.1.1.2
+  Description   : '[NodeName]' does not follow naming convention
+  Violation     : Lint:3506
+  Goal          : lint_rtl
+  Module        : comb_nonspec_allocator
+  FileName      : ./../../rtl/src_noc/./comb_nonspec.sv
+  LineNumber    : 215
+  Statement     :     for(i=0;i< PV;i=i+1) begin :_PV
+  NodeName      : _PV
+
+  -----------------------------------------------------------------------------
+  UndrivenNUnloaded-ML  (369 warnings/0 waived)
+  -----------------------------------------------------------------------------
+  Tag              : UndrivenNUnloaded-ML
+  Description      : Detected undriven and unloaded(unconnected) [NodeType] [DesignObjSignal]
+  Violation        : Lint:2323
+  Goal             : lint_rtl
+  Module           : router_top
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 104
+  Statement        :     flit_chanel_t ss_flit_chanel [P-1 : 0]; //flit  bypass link goes to straight port
+  NodeType         : net
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[1].the_router/ss_flit_chanel[0].congestion[1]
+  -----------------------------------------------------------------------------
+  Tag              : UndrivenNUnloaded-ML
+  Description      : Detected undriven and unloaded(unconnected) [NodeType] [DesignObjSignal]
+  Violation        : Lint:2414
+  Goal             : lint_rtl
+  Module           : router_top
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 104
+  Statement        :     flit_chanel_t ss_flit_chanel [P-1 : 0]; //flit  bypass link goes to straight port
+  NodeType         : net
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[2].the_router/ss_flit_chanel[0].flit.payload[13]
+  -----------------------------------------------------------------------------
+  Tag              : UndrivenNUnloaded-ML
+  Description      : Detected undriven and unloaded(unconnected) [NodeType] [DesignObjSignal]
+  Violation        : Lint:2373
+  Goal             : lint_rtl
+  Module           : router_top
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 104
+  Statement        :     flit_chanel_t ss_flit_chanel [P-1 : 0]; //flit  bypass link goes to straight port
+  NodeType         : net
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[1].the_router/ss_flit_chanel[0].flit.payload[48]
+  -----------------------------------------------------------------------------
+  Tag              : UndrivenNUnloaded-ML
+  Description      : Detected undriven and unloaded(unconnected) [NodeType] [DesignObjSignal]
+  Violation        : Lint:2282
+  Goal             : lint_rtl
+  Module           : router_top
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 65
+  Statement        :     smart_chanel_t smart_chanel_in   [P-1 : 0];
+  NodeType         : net
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[1].the_router/smart_chanel_in[0].dest_e_addr[1]
+  -----------------------------------------------------------------------------
+  Tag              : UndrivenNUnloaded-ML
+  Description      : Detected undriven and unloaded(unconnected) [NodeType] [DesignObjSignal]
+  Violation        : Lint:2434
+  Goal             : lint_rtl
+  Module           : router_top
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 104
+  Statement        :     flit_chanel_t ss_flit_chanel [P-1 : 0]; //flit  bypass link goes to straight port
+  NodeType         : net
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[2].the_router/ss_flit_chanel[0].flit.payload[33]
+  -----------------------------------------------------------------------------
+  Tag              : UndrivenNUnloaded-ML
+  Description      : Detected undriven and unloaded(unconnected) [NodeType] [DesignObjSignal]
+  Violation        : Lint:2541
+  Goal             : lint_rtl
+  Module           : router_top
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 104
+  Statement        :     flit_chanel_t ss_flit_chanel [P-1 : 0]; //flit  bypass link goes to straight port
+  NodeType         : net
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[3].the_router/ss_flit_chanel[0].flit.payload[62]
+  -----------------------------------------------------------------------------
+  Tag              : UndrivenNUnloaded-ML
+  Description      : Detected undriven and unloaded(unconnected) [NodeType] [DesignObjSignal]
+  Violation        : Lint:2378
+  Goal             : lint_rtl
+  Module           : router_top
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 104
+  Statement        :     flit_chanel_t ss_flit_chanel [P-1 : 0]; //flit  bypass link goes to straight port
+  NodeType         : net
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[1].the_router/ss_flit_chanel[0].flit.payload[53]
+  -----------------------------------------------------------------------------
+  Tag              : UndrivenNUnloaded-ML
+  Description      : Detected undriven and unloaded(unconnected) [NodeType] [DesignObjSignal]
+  Violation        : Lint:2391
+  Goal             : lint_rtl
+  Module           : router_top
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 104
+  Statement        :     flit_chanel_t ss_flit_chanel [P-1 : 0]; //flit  bypass link goes to straight port
+  NodeType         : net
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[1].the_router/ss_flit_chanel[0].flit.hdr_flag
+  -----------------------------------------------------------------------------
+  Tag              : UndrivenNUnloaded-ML
+  Description      : Detected undriven and unloaded(unconnected) [NodeType] [DesignObjSignal]
+  Violation        : Lint:2262
+  Goal             : lint_rtl
+  Module           : router_top
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 65
+  Statement        :     smart_chanel_t smart_chanel_in   [P-1 : 0];
+  NodeType         : net
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/smart_chanel_in[0].dest_e_addr[0]
+  -----------------------------------------------------------------------------
+  Tag              : UndrivenNUnloaded-ML
+  Description      : Detected undriven and unloaded(unconnected) [NodeType] [DesignObjSignal]
+  Violation        : Lint:2379
+  Goal             : lint_rtl
+  Module           : router_top
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 104
+  Statement        :     flit_chanel_t ss_flit_chanel [P-1 : 0]; //flit  bypass link goes to straight port
+  NodeType         : net
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[1].the_router/ss_flit_chanel[0].flit.payload[54]
+  -----------------------------------------------------------------------------
+  Tag              : UndrivenNUnloaded-ML
+  Description      : Detected undriven and unloaded(unconnected) [NodeType] [DesignObjSignal]
+  Violation        : Lint:2473
+  Goal             : lint_rtl
+  Module           : mesh_torus_noc_top
+  FileName         : ./../../rtl/src_noc/./mesh_torus_noc_top.sv
+  LineNumber       : 51
+  Statement        :     smartflit_chanel_t    router_chan_out  [NR-1 :0][MAX_P-1 : 0];
+  NodeType         : net
+  DesignObjSignal  : tori_noc.noc_top/router_chan_out[3][1].ctrl_chanel.endp_addr[0]
+  -----------------------------------------------------------------------------
+  Tag              : UndrivenNUnloaded-ML
+  Description      : Detected undriven and unloaded(unconnected) [NodeType] [DesignObjSignal]
+  Violation        : Lint:2236
+  Goal             : lint_rtl
+  Module           : router_top
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 104
+  Statement        :     flit_chanel_t ss_flit_chanel [P-1 : 0]; //flit  bypass link goes to straight port
+  NodeType         : net
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/ss_flit_chanel[0].flit.payload[48]
+  -----------------------------------------------------------------------------
+  Tag              : UndrivenNUnloaded-ML
+  Description      : Detected undriven and unloaded(unconnected) [NodeType] [DesignObjSignal]
+  Violation        : Lint:2207
+  Goal             : lint_rtl
+  Module           : router_top
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 104
+  Statement        :     flit_chanel_t ss_flit_chanel [P-1 : 0]; //flit  bypass link goes to straight port
+  NodeType         : net
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/ss_flit_chanel[0].flit.payload[19]
+  -----------------------------------------------------------------------------
+  Tag              : UndrivenNUnloaded-ML
+  Description      : Detected undriven and unloaded(unconnected) [NodeType] [DesignObjSignal]
+  Violation        : Lint:2268
+  Goal             : lint_rtl
+  Module           : smart_bypass_chanels
+  FileName         : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber       : 339
+  Statement        :     smart_chanel_t smart_chanel_shifted  [P-1 : 0];
+  NodeType         : net
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/smart.smart_bypass/smart_chanel_shifted[0].bypassed_num[0]
+  -----------------------------------------------------------------------------
+  Tag              : UndrivenNUnloaded-ML
+  Description      : Detected undriven and unloaded(unconnected) [NodeType] [DesignObjSignal]
+  Violation        : Lint:2488
+  Goal             : lint_rtl
+  Module           : router_top
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 104
+  Statement        :     flit_chanel_t ss_flit_chanel [P-1 : 0]; //flit  bypass link goes to straight port
+  NodeType         : net
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[3].the_router/ss_flit_chanel[0].flit.payload[9]
+  -----------------------------------------------------------------------------
+  Tag              : UndrivenNUnloaded-ML
+  Description      : Detected undriven and unloaded(unconnected) [NodeType] [DesignObjSignal]
+  Violation        : Lint:2303
+  Goal             : lint_rtl
+  Module           : router_top
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 65
+  Statement        :     smart_chanel_t smart_chanel_in   [P-1 : 0];
+  NodeType         : net
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[3].the_router/smart_chanel_in[0].ovc[0]
+  -----------------------------------------------------------------------------
+  Tag              : UndrivenNUnloaded-ML
+  Description      : Detected undriven and unloaded(unconnected) [NodeType] [DesignObjSignal]
+  Violation        : Lint:2267
+  Goal             : lint_rtl
+  Module           : router_top
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 65
+  Statement        :     smart_chanel_t smart_chanel_in   [P-1 : 0];
+  NodeType         : net
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/smart_chanel_in[0].requests[2]
+  -----------------------------------------------------------------------------
+  Tag              : UndrivenNUnloaded-ML
+  Description      : Detected undriven and unloaded(unconnected) [NodeType] [DesignObjSignal]
+  Violation        : Lint:2496
+  Goal             : lint_rtl
+  Module           : router_top
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 104
+  Statement        :     flit_chanel_t ss_flit_chanel [P-1 : 0]; //flit  bypass link goes to straight port
+  NodeType         : net
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[3].the_router/ss_flit_chanel[0].flit.payload[17]
+  -----------------------------------------------------------------------------
+  Tag              : UndrivenNUnloaded-ML
+  Description      : Detected undriven and unloaded(unconnected) [NodeType] [DesignObjSignal]
+  Violation        : Lint:2192
+  Goal             : lint_rtl
+  Module           : router_top
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 104
+  Statement        :     flit_chanel_t ss_flit_chanel [P-1 : 0]; //flit  bypass link goes to straight port
+  NodeType         : net
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/ss_flit_chanel[0].flit.payload[4]
+  -----------------------------------------------------------------------------
+  Tag              : UndrivenNUnloaded-ML
+  Description      : Detected undriven and unloaded(unconnected) [NodeType] [DesignObjSignal]
+  Violation        : Lint:2456
+  Goal             : lint_rtl
+  Module           : router_top
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 104
+  Statement        :     flit_chanel_t ss_flit_chanel [P-1 : 0]; //flit  bypass link goes to straight port
+  NodeType         : net
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[2].the_router/ss_flit_chanel[0].flit.payload[55]
+  -----------------------------------------------------------------------------
+  Tag              : UndrivenNUnloaded-ML
+  Description      : Detected undriven and unloaded(unconnected) [NodeType] [DesignObjSignal]
+  Violation        : Lint:2405
+  Goal             : lint_rtl
+  Module           : router_top
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 104
+  Statement        :     flit_chanel_t ss_flit_chanel [P-1 : 0]; //flit  bypass link goes to straight port
+  NodeType         : net
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[2].the_router/ss_flit_chanel[0].flit.payload[4]
+  -----------------------------------------------------------------------------
+  Tag              : UndrivenNUnloaded-ML
+  Description      : Detected undriven and unloaded(unconnected) [NodeType] [DesignObjSignal]
+  Violation        : Lint:2521
+  Goal             : lint_rtl
+  Module           : router_top
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 104
+  Statement        :     flit_chanel_t ss_flit_chanel [P-1 : 0]; //flit  bypass link goes to straight port
+  NodeType         : net
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[3].the_router/ss_flit_chanel[0].flit.payload[42]
+  -----------------------------------------------------------------------------
+  Tag              : UndrivenNUnloaded-ML
+  Description      : Detected undriven and unloaded(unconnected) [NodeType] [DesignObjSignal]
+  Violation        : Lint:2483
+  Goal             : lint_rtl
+  Module           : router_top
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 104
+  Statement        :     flit_chanel_t ss_flit_chanel [P-1 : 0]; //flit  bypass link goes to straight port
+  NodeType         : net
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[3].the_router/ss_flit_chanel[0].flit.payload[4]
+  -----------------------------------------------------------------------------
+  Tag              : UndrivenNUnloaded-ML
+  Description      : Detected undriven and unloaded(unconnected) [NodeType] [DesignObjSignal]
+  Violation        : Lint:2438
+  Goal             : lint_rtl
+  Module           : router_top
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 104
+  Statement        :     flit_chanel_t ss_flit_chanel [P-1 : 0]; //flit  bypass link goes to straight port
+  NodeType         : net
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[2].the_router/ss_flit_chanel[0].flit.payload[37]
+  -----------------------------------------------------------------------------
+  Tag              : UndrivenNUnloaded-ML
+  Description      : Detected undriven and unloaded(unconnected) [NodeType] [DesignObjSignal]
+  Violation        : Lint:2514
+  Goal             : lint_rtl
+  Module           : router_top
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 104
+  Statement        :     flit_chanel_t ss_flit_chanel [P-1 : 0]; //flit  bypass link goes to straight port
+  NodeType         : net
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[3].the_router/ss_flit_chanel[0].flit.payload[35]
+  -----------------------------------------------------------------------------
+  Tag              : UndrivenNUnloaded-ML
+  Description      : Detected undriven and unloaded(unconnected) [NodeType] [DesignObjSignal]
+  Violation        : Lint:2461
+  Goal             : lint_rtl
+  Module           : router_top
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 104
+  Statement        :     flit_chanel_t ss_flit_chanel [P-1 : 0]; //flit  bypass link goes to straight port
+  NodeType         : net
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[2].the_router/ss_flit_chanel[0].flit.payload[60]
+  -----------------------------------------------------------------------------
+  Tag              : UndrivenNUnloaded-ML
+  Description      : Detected undriven and unloaded(unconnected) [NodeType] [DesignObjSignal]
+  Violation        : Lint:2224
+  Goal             : lint_rtl
+  Module           : router_top
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 104
+  Statement        :     flit_chanel_t ss_flit_chanel [P-1 : 0]; //flit  bypass link goes to straight port
+  NodeType         : net
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/ss_flit_chanel[0].flit.payload[36]
+  -----------------------------------------------------------------------------
+  Tag              : UndrivenNUnloaded-ML
+  Description      : Detected undriven and unloaded(unconnected) [NodeType] [DesignObjSignal]
+  Violation        : Lint:2493
+  Goal             : lint_rtl
+  Module           : router_top
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 104
+  Statement        :     flit_chanel_t ss_flit_chanel [P-1 : 0]; //flit  bypass link goes to straight port
+  NodeType         : net
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[3].the_router/ss_flit_chanel[0].flit.payload[14]
+  -----------------------------------------------------------------------------
+  Tag              : UndrivenNUnloaded-ML
+  Description      : Detected undriven and unloaded(unconnected) [NodeType] [DesignObjSignal]
+  Violation        : Lint:2223
+  Goal             : lint_rtl
+  Module           : router_top
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 104
+  Statement        :     flit_chanel_t ss_flit_chanel [P-1 : 0]; //flit  bypass link goes to straight port
+  NodeType         : net
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/ss_flit_chanel[0].flit.payload[35]
+  -----------------------------------------------------------------------------
+  Tag              : UndrivenNUnloaded-ML
+  Description      : Detected undriven and unloaded(unconnected) [NodeType] [DesignObjSignal]
+  Violation        : Lint:2294
+  Goal             : lint_rtl
+  Module           : router_top
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 65
+  Statement        :     smart_chanel_t smart_chanel_in   [P-1 : 0];
+  NodeType         : net
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[2].the_router/smart_chanel_in[0].requests[0]
+  -----------------------------------------------------------------------------
+  Tag              : UndrivenNUnloaded-ML
+  Description      : Detected undriven and unloaded(unconnected) [NodeType] [DesignObjSignal]
+  Violation        : Lint:2285
+  Goal             : lint_rtl
+  Module           : router_top
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 65
+  Statement        :     smart_chanel_t smart_chanel_in   [P-1 : 0];
+  NodeType         : net
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[1].the_router/smart_chanel_in[0].requests[1]
+  -----------------------------------------------------------------------------
+  Tag              : UndrivenNUnloaded-ML
+  Description      : Detected undriven and unloaded(unconnected) [NodeType] [DesignObjSignal]
+  Violation        : Lint:2404
+  Goal             : lint_rtl
+  Module           : router_top
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 104
+  Statement        :     flit_chanel_t ss_flit_chanel [P-1 : 0]; //flit  bypass link goes to straight port
+  NodeType         : net
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[2].the_router/ss_flit_chanel[0].flit.payload[3]
+  -----------------------------------------------------------------------------
+  Tag              : UndrivenNUnloaded-ML
+  Description      : Detected undriven and unloaded(unconnected) [NodeType] [DesignObjSignal]
+  Violation        : Lint:2503
+  Goal             : lint_rtl
+  Module           : router_top
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 104
+  Statement        :     flit_chanel_t ss_flit_chanel [P-1 : 0]; //flit  bypass link goes to straight port
+  NodeType         : net
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[3].the_router/ss_flit_chanel[0].flit.payload[24]
+  -----------------------------------------------------------------------------
+  Tag              : UndrivenNUnloaded-ML
+  Description      : Detected undriven and unloaded(unconnected) [NodeType] [DesignObjSignal]
+  Violation        : Lint:2384
+  Goal             : lint_rtl
+  Module           : router_top
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 104
+  Statement        :     flit_chanel_t ss_flit_chanel [P-1 : 0]; //flit  bypass link goes to straight port
+  NodeType         : net
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[1].the_router/ss_flit_chanel[0].flit.payload[59]
+  -----------------------------------------------------------------------------
+  Tag              : UndrivenNUnloaded-ML
+  Description      : Detected undriven and unloaded(unconnected) [NodeType] [DesignObjSignal]
+  Violation        : Lint:2513
+  Goal             : lint_rtl
+  Module           : router_top
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 104
+  Statement        :     flit_chanel_t ss_flit_chanel [P-1 : 0]; //flit  bypass link goes to straight port
+  NodeType         : net
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[3].the_router/ss_flit_chanel[0].flit.payload[34]
+  -----------------------------------------------------------------------------
+  Tag              : UndrivenNUnloaded-ML
+  Description      : Detected undriven and unloaded(unconnected) [NodeType] [DesignObjSignal]
+  Violation        : Lint:2447
+  Goal             : lint_rtl
+  Module           : router_top
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 104
+  Statement        :     flit_chanel_t ss_flit_chanel [P-1 : 0]; //flit  bypass link goes to straight port
+  NodeType         : net
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[2].the_router/ss_flit_chanel[0].flit.payload[46]
+  -----------------------------------------------------------------------------
+  Tag              : UndrivenNUnloaded-ML
+  Description      : Detected undriven and unloaded(unconnected) [NodeType] [DesignObjSignal]
+  Violation        : Lint:2278
+  Goal             : lint_rtl
+  Module           : router_top
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 65
+  Statement        :     smart_chanel_t smart_chanel_in   [P-1 : 0];
+  NodeType         : net
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[1].the_router/smart_chanel_in[0].bypassed_num[1]
+  -----------------------------------------------------------------------------
+  Tag              : UndrivenNUnloaded-ML
+  Description      : Detected undriven and unloaded(unconnected) [NodeType] [DesignObjSignal]
+  Violation        : Lint:2355
+  Goal             : lint_rtl
+  Module           : router_top
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 104
+  Statement        :     flit_chanel_t ss_flit_chanel [P-1 : 0]; //flit  bypass link goes to straight port
+  NodeType         : net
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[1].the_router/ss_flit_chanel[0].flit.payload[30]
+  -----------------------------------------------------------------------------
+  Tag              : UndrivenNUnloaded-ML
+  Description      : Detected undriven and unloaded(unconnected) [NodeType] [DesignObjSignal]
+  Violation        : Lint:2516
+  Goal             : lint_rtl
+  Module           : router_top
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 104
+  Statement        :     flit_chanel_t ss_flit_chanel [P-1 : 0]; //flit  bypass link goes to straight port
+  NodeType         : net
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[3].the_router/ss_flit_chanel[0].flit.payload[37]
+  -----------------------------------------------------------------------------
+  Tag              : UndrivenNUnloaded-ML
+  Description      : Detected undriven and unloaded(unconnected) [NodeType] [DesignObjSignal]
+  Violation        : Lint:2542
+  Goal             : lint_rtl
+  Module           : router_top
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 104
+  Statement        :     flit_chanel_t ss_flit_chanel [P-1 : 0]; //flit  bypass link goes to straight port
+  NodeType         : net
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[3].the_router/ss_flit_chanel[0].flit.payload[63]
+  -----------------------------------------------------------------------------
+  Tag              : UndrivenNUnloaded-ML
+  Description      : Detected undriven and unloaded(unconnected) [NodeType] [DesignObjSignal]
+  Violation        : Lint:2500
+  Goal             : lint_rtl
+  Module           : router_top
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 104
+  Statement        :     flit_chanel_t ss_flit_chanel [P-1 : 0]; //flit  bypass link goes to straight port
+  NodeType         : net
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[3].the_router/ss_flit_chanel[0].flit.payload[21]
+  -----------------------------------------------------------------------------
+  Tag              : UndrivenNUnloaded-ML
+  Description      : Detected undriven and unloaded(unconnected) [NodeType] [DesignObjSignal]
+  Violation        : Lint:2381
+  Goal             : lint_rtl
+  Module           : router_top
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 104
+  Statement        :     flit_chanel_t ss_flit_chanel [P-1 : 0]; //flit  bypass link goes to straight port
+  NodeType         : net
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[1].the_router/ss_flit_chanel[0].flit.payload[56]
+  -----------------------------------------------------------------------------
+  Tag              : UndrivenNUnloaded-ML
+  Description      : Detected undriven and unloaded(unconnected) [NodeType] [DesignObjSignal]
+  Violation        : Lint:2387
+  Goal             : lint_rtl
+  Module           : router_top
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 104
+  Statement        :     flit_chanel_t ss_flit_chanel [P-1 : 0]; //flit  bypass link goes to straight port
+  NodeType         : net
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[1].the_router/ss_flit_chanel[0].flit.payload[62]
+  -----------------------------------------------------------------------------
+  Tag              : UndrivenNUnloaded-ML
+  Description      : Detected undriven and unloaded(unconnected) [NodeType] [DesignObjSignal]
+  Violation        : Lint:2313
+  Goal             : lint_rtl
+  Module           : router_top
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 156
+  Statement        :         wire  [RAw-1:  0]  neighbors_r_addr [P-1: 0];
+  NodeType         : net
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[3].the_router/smart.neighbors_r_addr[0][0]
+  -----------------------------------------------------------------------------
+  Tag              : UndrivenNUnloaded-ML
+  Description      : Detected undriven and unloaded(unconnected) [NodeType] [DesignObjSignal]
+  Violation        : Lint:2383
+  Goal             : lint_rtl
+  Module           : router_top
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 104
+  Statement        :     flit_chanel_t ss_flit_chanel [P-1 : 0]; //flit  bypass link goes to straight port
+  NodeType         : net
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[1].the_router/ss_flit_chanel[0].flit.payload[58]
+  -----------------------------------------------------------------------------
+  Tag              : UndrivenNUnloaded-ML
+  Description      : Detected undriven and unloaded(unconnected) [NodeType] [DesignObjSignal]
+  Violation        : Lint:2288
+  Goal             : lint_rtl
+  Module           : router_top
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 65
+  Statement        :     smart_chanel_t smart_chanel_in   [P-1 : 0];
+  NodeType         : net
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[2].the_router/smart_chanel_in[0].bypassed_num[1]
+  -----------------------------------------------------------------------------
+  Tag              : UndrivenNUnloaded-ML
+  Description      : Detected undriven and unloaded(unconnected) [NodeType] [DesignObjSignal]
+  Violation        : Lint:2302
+  Goal             : lint_rtl
+  Module           : router_top
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 65
+  Statement        :     smart_chanel_t smart_chanel_in   [P-1 : 0];
+  NodeType         : net
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[3].the_router/smart_chanel_in[0].dest_e_addr[1]
+  -----------------------------------------------------------------------------
+  Tag              : UndrivenNUnloaded-ML
+  Description      : Detected undriven and unloaded(unconnected) [NodeType] [DesignObjSignal]
+  Violation        : Lint:2455
+  Goal             : lint_rtl
+  Module           : router_top
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 104
+  Statement        :     flit_chanel_t ss_flit_chanel [P-1 : 0]; //flit  bypass link goes to straight port
+  NodeType         : net
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[2].the_router/ss_flit_chanel[0].flit.payload[54]
+  -----------------------------------------------------------------------------
+  Tag              : UndrivenNUnloaded-ML
+  Description      : Detected undriven and unloaded(unconnected) [NodeType] [DesignObjSignal]
+  Violation        : Lint:2536
+  Goal             : lint_rtl
+  Module           : router_top
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 104
+  Statement        :     flit_chanel_t ss_flit_chanel [P-1 : 0]; //flit  bypass link goes to straight port
+  NodeType         : net
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[3].the_router/ss_flit_chanel[0].flit.payload[57]
+  -----------------------------------------------------------------------------
+  Tag              : UndrivenNUnloaded-ML
+  Description      : Detected undriven and unloaded(unconnected) [NodeType] [DesignObjSignal]
+  Violation        : Lint:2220
+  Goal             : lint_rtl
+  Module           : router_top
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 104
+  Statement        :     flit_chanel_t ss_flit_chanel [P-1 : 0]; //flit  bypass link goes to straight port
+  NodeType         : net
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/ss_flit_chanel[0].flit.payload[32]
+  -----------------------------------------------------------------------------
+  Tag              : UndrivenNUnloaded-ML
+  Description      : Detected undriven and unloaded(unconnected) [NodeType] [DesignObjSignal]
+  Violation        : Lint:2546
+  Goal             : lint_rtl
+  Module           : router_top
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 104
+  Statement        :     flit_chanel_t ss_flit_chanel [P-1 : 0]; //flit  bypass link goes to straight port
+  NodeType         : net
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[3].the_router/ss_flit_chanel[0].credit[0]
+  -----------------------------------------------------------------------------
+  Tag              : UndrivenNUnloaded-ML
+  Description      : Detected undriven and unloaded(unconnected) [NodeType] [DesignObjSignal]
+  Violation        : Lint:2470
+  Goal             : lint_rtl
+  Module           : router_top
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 157
+  Statement        :         wire  [V-1  :  0]  credit_out [P-1 : 0];
+  NodeType         : net
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[2].the_router/smart.credit_out[0][0]
+  -----------------------------------------------------------------------------
+  Tag              : UndrivenNUnloaded-ML
+  Description      : Detected undriven and unloaded(unconnected) [NodeType] [DesignObjSignal]
+  Violation        : Lint:2199
+  Goal             : lint_rtl
+  Module           : router_top
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 104
+  Statement        :     flit_chanel_t ss_flit_chanel [P-1 : 0]; //flit  bypass link goes to straight port
+  NodeType         : net
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/ss_flit_chanel[0].flit.payload[11]
+  -----------------------------------------------------------------------------
+  Tag              : UndrivenNUnloaded-ML
+  Description      : Detected undriven and unloaded(unconnected) [NodeType] [DesignObjSignal]
+  Violation        : Lint:2317
+  Goal             : lint_rtl
+  Module           : smart_allocator_per_iport
+  FileName         : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber       : 623
+  Statement        :     ) routing (
+  NodeType         : terminal
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/smart.Port_[2].smart_en.smart_allocator/routing/src_e_addr[1:0]
+  -----------------------------------------------------------------------------
+  Tag              : UndrivenNUnloaded-ML
+  Description      : Detected undriven and unloaded(unconnected) [NodeType] [DesignObjSignal]
+  Violation        : Lint:2476
+  Goal             : lint_rtl
+  Module           : router_top
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 104
+  Statement        :     flit_chanel_t ss_flit_chanel [P-1 : 0]; //flit  bypass link goes to straight port
+  NodeType         : net
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[3].the_router/ss_flit_chanel[0].congestion[0]
+  -----------------------------------------------------------------------------
+  Tag              : UndrivenNUnloaded-ML
+  Description      : Detected undriven and unloaded(unconnected) [NodeType] [DesignObjSignal]
+  Violation        : Lint:2429
+  Goal             : lint_rtl
+  Module           : router_top
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 104
+  Statement        :     flit_chanel_t ss_flit_chanel [P-1 : 0]; //flit  bypass link goes to straight port
+  NodeType         : net
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[2].the_router/ss_flit_chanel[0].flit.payload[28]
+  -----------------------------------------------------------------------------
+  Tag              : UndrivenNUnloaded-ML
+  Description      : Detected undriven and unloaded(unconnected) [NodeType] [DesignObjSignal]
+  Violation        : Lint:2257
+  Goal             : lint_rtl
+  Module           : router_top
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 157
+  Statement        :         wire  [V-1  :  0]  credit_out [P-1 : 0];
+  NodeType         : net
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/smart.credit_out[0][0]
+  -----------------------------------------------------------------------------
+  Tag              : UndrivenNUnloaded-ML
+  Description      : Detected undriven and unloaded(unconnected) [NodeType] [DesignObjSignal]
+  Violation        : Lint:2374
+  Goal             : lint_rtl
+  Module           : router_top
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 104
+  Statement        :     flit_chanel_t ss_flit_chanel [P-1 : 0]; //flit  bypass link goes to straight port
+  NodeType         : net
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[1].the_router/ss_flit_chanel[0].flit.payload[49]
+  -----------------------------------------------------------------------------
+  Tag              : UndrivenNUnloaded-ML
+  Description      : Detected undriven and unloaded(unconnected) [NodeType] [DesignObjSignal]
+  Violation        : Lint:2320
+  Goal             : lint_rtl
+  Module           : mesh_torus_noc_top
+  FileName         : ./../../rtl/src_noc/./mesh_torus_noc_top.sv
+  LineNumber       : 53
+  Statement        :     router_config_t router_config_in [NR-1 :0];
+  NodeType         : net
+  DesignObjSignal  : tori_noc.noc_top/router_config_in[1].endp_ids[1]
+  -----------------------------------------------------------------------------
+  Tag              : UndrivenNUnloaded-ML
+  Description      : Detected undriven and unloaded(unconnected) [NodeType] [DesignObjSignal]
+  Violation        : Lint:2409
+  Goal             : lint_rtl
+  Module           : router_top
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 104
+  Statement        :     flit_chanel_t ss_flit_chanel [P-1 : 0]; //flit  bypass link goes to straight port
+  NodeType         : net
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[2].the_router/ss_flit_chanel[0].flit.payload[8]
+  -----------------------------------------------------------------------------
+  Tag              : UndrivenNUnloaded-ML
+  Description      : Detected undriven and unloaded(unconnected) [NodeType] [DesignObjSignal]
+  Violation        : Lint:2358
+  Goal             : lint_rtl
+  Module           : router_top
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 104
+  Statement        :     flit_chanel_t ss_flit_chanel [P-1 : 0]; //flit  bypass link goes to straight port
+  NodeType         : net
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[1].the_router/ss_flit_chanel[0].flit.payload[33]
+  -----------------------------------------------------------------------------
+  Tag              : UndrivenNUnloaded-ML
+  Description      : Detected undriven and unloaded(unconnected) [NodeType] [DesignObjSignal]
+  Violation        : Lint:2453
+  Goal             : lint_rtl
+  Module           : router_top
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 104
+  Statement        :     flit_chanel_t ss_flit_chanel [P-1 : 0]; //flit  bypass link goes to straight port
+  NodeType         : net
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[2].the_router/ss_flit_chanel[0].flit.payload[52]
+  -----------------------------------------------------------------------------
+  Tag              : UndrivenNUnloaded-ML
+  Description      : Detected undriven and unloaded(unconnected) [NodeType] [DesignObjSignal]
+  Violation        : Lint:2343
+  Goal             : lint_rtl
+  Module           : router_top
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 104
+  Statement        :     flit_chanel_t ss_flit_chanel [P-1 : 0]; //flit  bypass link goes to straight port
+  NodeType         : net
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[1].the_router/ss_flit_chanel[0].flit.payload[18]
+  -----------------------------------------------------------------------------
+  Tag              : UndrivenNUnloaded-ML
+  Description      : Detected undriven and unloaded(unconnected) [NodeType] [DesignObjSignal]
+  Violation        : Lint:2471
+  Goal             : lint_rtl
+  Module           : mesh_torus_noc_top
+  FileName         : ./../../rtl/src_noc/./mesh_torus_noc_top.sv
+  LineNumber       : 53
+  Statement        :     router_config_t router_config_in [NR-1 :0];
+  NodeType         : net
+  DesignObjSignal  : tori_noc.noc_top/router_config_in[3].endp_ids[0]
+  -----------------------------------------------------------------------------
+  Tag              : UndrivenNUnloaded-ML
+  Description      : Detected undriven and unloaded(unconnected) [NodeType] [DesignObjSignal]
+  Violation        : Lint:2368
+  Goal             : lint_rtl
+  Module           : router_top
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 104
+  Statement        :     flit_chanel_t ss_flit_chanel [P-1 : 0]; //flit  bypass link goes to straight port
+  NodeType         : net
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[1].the_router/ss_flit_chanel[0].flit.payload[43]
+  -----------------------------------------------------------------------------
+  Tag              : UndrivenNUnloaded-ML
+  Description      : Detected undriven and unloaded(unconnected) [NodeType] [DesignObjSignal]
+  Violation        : Lint:2509
+  Goal             : lint_rtl
+  Module           : router_top
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 104
+  Statement        :     flit_chanel_t ss_flit_chanel [P-1 : 0]; //flit  bypass link goes to straight port
+  NodeType         : net
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[3].the_router/ss_flit_chanel[0].flit.payload[30]
+  -----------------------------------------------------------------------------
+  Tag              : UndrivenNUnloaded-ML
+  Description      : Detected undriven and unloaded(unconnected) [NodeType] [DesignObjSignal]
+  Violation        : Lint:2394
+  Goal             : lint_rtl
+  Module           : router_top
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 157
+  Statement        :         wire  [V-1  :  0]  credit_out [P-1 : 0];
+  NodeType         : net
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[1].the_router/smart.credit_out[0][0]
+  -----------------------------------------------------------------------------
+  Tag              : UndrivenNUnloaded-ML
+  Description      : Detected undriven and unloaded(unconnected) [NodeType] [DesignObjSignal]
+  Violation        : Lint:2265
+  Goal             : lint_rtl
+  Module           : router_top
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 65
+  Statement        :     smart_chanel_t smart_chanel_in   [P-1 : 0];
+  NodeType         : net
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/smart_chanel_in[0].requests[0]
+  -----------------------------------------------------------------------------
+  Tag              : UndrivenNUnloaded-ML
+  Description      : Detected undriven and unloaded(unconnected) [NodeType] [DesignObjSignal]
+  Violation        : Lint:2319
+  Goal             : lint_rtl
+  Module           : mesh_torus_noc_top
+  FileName         : ./../../rtl/src_noc/./mesh_torus_noc_top.sv
+  LineNumber       : 53
+  Statement        :     router_config_t router_config_in [NR-1 :0];
+  NodeType         : net
+  DesignObjSignal  : tori_noc.noc_top/router_config_in[1].endp_ids[0]
+  -----------------------------------------------------------------------------
+  Tag              : UndrivenNUnloaded-ML
+  Description      : Detected undriven and unloaded(unconnected) [NodeType] [DesignObjSignal]
+  Violation        : Lint:2349
+  Goal             : lint_rtl
+  Module           : router_top
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 104
+  Statement        :     flit_chanel_t ss_flit_chanel [P-1 : 0]; //flit  bypass link goes to straight port
+  NodeType         : net
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[1].the_router/ss_flit_chanel[0].flit.payload[24]
+  -----------------------------------------------------------------------------
+  Tag              : UndrivenNUnloaded-ML
+  Description      : Detected undriven and unloaded(unconnected) [NodeType] [DesignObjSignal]
+  Violation        : Lint:2221
+  Goal             : lint_rtl
+  Module           : router_top
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 104
+  Statement        :     flit_chanel_t ss_flit_chanel [P-1 : 0]; //flit  bypass link goes to straight port
+  NodeType         : net
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/ss_flit_chanel[0].flit.payload[33]
+  -----------------------------------------------------------------------------
+  Tag              : UndrivenNUnloaded-ML
+  Description      : Detected undriven and unloaded(unconnected) [NodeType] [DesignObjSignal]
+  Violation        : Lint:2253
+  Goal             : lint_rtl
+  Module           : router_top
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 104
+  Statement        :     flit_chanel_t ss_flit_chanel [P-1 : 0]; //flit  bypass link goes to straight port
+  NodeType         : net
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/ss_flit_chanel[0].flit.tail_flag
+  -----------------------------------------------------------------------------
+  Tag              : UndrivenNUnloaded-ML
+  Description      : Detected undriven and unloaded(unconnected) [NodeType] [DesignObjSignal]
+  Violation        : Lint:2213
+  Goal             : lint_rtl
+  Module           : router_top
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 104
+  Statement        :     flit_chanel_t ss_flit_chanel [P-1 : 0]; //flit  bypass link goes to straight port
+  NodeType         : net
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/ss_flit_chanel[0].flit.payload[25]
+  -----------------------------------------------------------------------------
+  Tag              : UndrivenNUnloaded-ML
+  Description      : Detected undriven and unloaded(unconnected) [NodeType] [DesignObjSignal]
+  Violation        : Lint:2217
+  Goal             : lint_rtl
+  Module           : router_top
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 104
+  Statement        :     flit_chanel_t ss_flit_chanel [P-1 : 0]; //flit  bypass link goes to straight port
+  NodeType         : net
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/ss_flit_chanel[0].flit.payload[29]
+  -----------------------------------------------------------------------------
+  Tag              : UndrivenNUnloaded-ML
+  Description      : Detected undriven and unloaded(unconnected) [NodeType] [DesignObjSignal]
+  Violation        : Lint:2459
+  Goal             : lint_rtl
+  Module           : router_top
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 104
+  Statement        :     flit_chanel_t ss_flit_chanel [P-1 : 0]; //flit  bypass link goes to straight port
+  NodeType         : net
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[2].the_router/ss_flit_chanel[0].flit.payload[58]
+  -----------------------------------------------------------------------------
+  Tag              : UndrivenNUnloaded-ML
+  Description      : Detected undriven and unloaded(unconnected) [NodeType] [DesignObjSignal]
+  Violation        : Lint:2444
+  Goal             : lint_rtl
+  Module           : router_top
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 104
+  Statement        :     flit_chanel_t ss_flit_chanel [P-1 : 0]; //flit  bypass link goes to straight port
+  NodeType         : net
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[2].the_router/ss_flit_chanel[0].flit.payload[43]
+  -----------------------------------------------------------------------------
+  Tag              : UndrivenNUnloaded-ML
+  Description      : Detected undriven and unloaded(unconnected) [NodeType] [DesignObjSignal]
+  Violation        : Lint:2279
+  Goal             : lint_rtl
+  Module           : router_top
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 65
+  Statement        :     smart_chanel_t smart_chanel_in   [P-1 : 0];
+  NodeType         : net
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[1].the_router/smart_chanel_in[0].flit_in_bypassed
+  -----------------------------------------------------------------------------
+  Tag              : UndrivenNUnloaded-ML
+  Description      : Detected undriven and unloaded(unconnected) [NodeType] [DesignObjSignal]
+  Violation        : Lint:2230
+  Goal             : lint_rtl
+  Module           : router_top
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 104
+  Statement        :     flit_chanel_t ss_flit_chanel [P-1 : 0]; //flit  bypass link goes to straight port
+  NodeType         : net
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/ss_flit_chanel[0].flit.payload[42]
+  -----------------------------------------------------------------------------
+  Tag              : UndrivenNUnloaded-ML
+  Description      : Detected undriven and unloaded(unconnected) [NodeType] [DesignObjSignal]
+  Violation        : Lint:2376
+  Goal             : lint_rtl
+  Module           : router_top
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 104
+  Statement        :     flit_chanel_t ss_flit_chanel [P-1 : 0]; //flit  bypass link goes to straight port
+  NodeType         : net
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[1].the_router/ss_flit_chanel[0].flit.payload[51]
+  -----------------------------------------------------------------------------
+  Tag              : UndrivenNUnloaded-ML
+  Description      : Detected undriven and unloaded(unconnected) [NodeType] [DesignObjSignal]
+  Violation        : Lint:2463
+  Goal             : lint_rtl
+  Module           : router_top
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 104
+  Statement        :     flit_chanel_t ss_flit_chanel [P-1 : 0]; //flit  bypass link goes to straight port
+  NodeType         : net
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[2].the_router/ss_flit_chanel[0].flit.payload[62]
+  -----------------------------------------------------------------------------
+  Tag              : UndrivenNUnloaded-ML
+  Description      : Detected undriven and unloaded(unconnected) [NodeType] [DesignObjSignal]
+  Violation        : Lint:2510
+  Goal             : lint_rtl
+  Module           : router_top
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 104
+  Statement        :     flit_chanel_t ss_flit_chanel [P-1 : 0]; //flit  bypass link goes to straight port
+  NodeType         : net
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[3].the_router/ss_flit_chanel[0].flit.payload[31]
+  -----------------------------------------------------------------------------
+  Tag              : UndrivenNUnloaded-ML
+  Description      : Detected undriven and unloaded(unconnected) [NodeType] [DesignObjSignal]
+  Violation        : Lint:2415
+  Goal             : lint_rtl
+  Module           : router_top
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 104
+  Statement        :     flit_chanel_t ss_flit_chanel [P-1 : 0]; //flit  bypass link goes to straight port
+  NodeType         : net
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[2].the_router/ss_flit_chanel[0].flit.payload[14]
+  -----------------------------------------------------------------------------
+  Tag              : UndrivenNUnloaded-ML
+  Description      : Detected undriven and unloaded(unconnected) [NodeType] [DesignObjSignal]
+  Violation        : Lint:2431
+  Goal             : lint_rtl
+  Module           : router_top
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 104
+  Statement        :     flit_chanel_t ss_flit_chanel [P-1 : 0]; //flit  bypass link goes to straight port
+  NodeType         : net
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[2].the_router/ss_flit_chanel[0].flit.payload[30]
+  -----------------------------------------------------------------------------
+  Tag              : UndrivenNUnloaded-ML
+  Description      : Detected undriven and unloaded(unconnected) [NodeType] [DesignObjSignal]
+  Violation        : Lint:2422
+  Goal             : lint_rtl
+  Module           : router_top
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 104
+  Statement        :     flit_chanel_t ss_flit_chanel [P-1 : 0]; //flit  bypass link goes to straight port
+  NodeType         : net
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[2].the_router/ss_flit_chanel[0].flit.payload[21]
+  -----------------------------------------------------------------------------
+  Tag              : UndrivenNUnloaded-ML
+  Description      : Detected undriven and unloaded(unconnected) [NodeType] [DesignObjSignal]
+  Violation        : Lint:2195
+  Goal             : lint_rtl
+  Module           : router_top
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 104
+  Statement        :     flit_chanel_t ss_flit_chanel [P-1 : 0]; //flit  bypass link goes to straight port
+  NodeType         : net
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/ss_flit_chanel[0].flit.payload[7]
+  -----------------------------------------------------------------------------
+  Tag              : UndrivenNUnloaded-ML
+  Description      : Detected undriven and unloaded(unconnected) [NodeType] [DesignObjSignal]
+  Violation        : Lint:2494
+  Goal             : lint_rtl
+  Module           : router_top
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 104
+  Statement        :     flit_chanel_t ss_flit_chanel [P-1 : 0]; //flit  bypass link goes to straight port
+  NodeType         : net
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[3].the_router/ss_flit_chanel[0].flit.payload[15]
+  -----------------------------------------------------------------------------
+  Tag              : UndrivenNUnloaded-ML
+  Description      : Detected undriven and unloaded(unconnected) [NodeType] [DesignObjSignal]
+  Violation        : Lint:2523
+  Goal             : lint_rtl
+  Module           : router_top
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 104
+  Statement        :     flit_chanel_t ss_flit_chanel [P-1 : 0]; //flit  bypass link goes to straight port
+  NodeType         : net
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[3].the_router/ss_flit_chanel[0].flit.payload[44]
+  -----------------------------------------------------------------------------
+  Tag              : UndrivenNUnloaded-ML
+  Description      : Detected undriven and unloaded(unconnected) [NodeType] [DesignObjSignal]
+  Violation        : Lint:2352
+  Goal             : lint_rtl
+  Module           : router_top
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 104
+  Statement        :     flit_chanel_t ss_flit_chanel [P-1 : 0]; //flit  bypass link goes to straight port
+  NodeType         : net
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[1].the_router/ss_flit_chanel[0].flit.payload[27]
+  -----------------------------------------------------------------------------
+  Tag              : UndrivenNUnloaded-ML
+  Description      : Detected undriven and unloaded(unconnected) [NodeType] [DesignObjSignal]
+  Violation        : Lint:2258
+  Goal             : lint_rtl
+  Module           : router_top
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 65
+  Statement        :     smart_chanel_t smart_chanel_in   [P-1 : 0];
+  NodeType         : net
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/smart_chanel_in[0].bypassed_num[0]
+  -----------------------------------------------------------------------------
+  Tag              : UndrivenNUnloaded-ML
+  Description      : Detected undriven and unloaded(unconnected) [NodeType] [DesignObjSignal]
+  Violation        : Lint:2474
+  Goal             : lint_rtl
+  Module           : mesh_torus_noc_top
+  FileName         : ./../../rtl/src_noc/./mesh_torus_noc_top.sv
+  LineNumber       : 51
+  Statement        :     smartflit_chanel_t    router_chan_out  [NR-1 :0][MAX_P-1 : 0];
+  NodeType         : net
+  DesignObjSignal  : tori_noc.noc_top/router_chan_out[3][1].ctrl_chanel.endp_addr[1]
+  -----------------------------------------------------------------------------
+  Tag              : UndrivenNUnloaded-ML
+  Description      : Detected undriven and unloaded(unconnected) [NodeType] [DesignObjSignal]
+  Violation        : Lint:2259
+  Goal             : lint_rtl
+  Module           : router_top
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 65
+  Statement        :     smart_chanel_t smart_chanel_in   [P-1 : 0];
+  NodeType         : net
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/smart_chanel_in[0].bypassed_num[1]
+  -----------------------------------------------------------------------------
+  Tag              : UndrivenNUnloaded-ML
+  Description      : Detected undriven and unloaded(unconnected) [NodeType] [DesignObjSignal]
+  Violation        : Lint:2212
+  Goal             : lint_rtl
+  Module           : router_top
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 104
+  Statement        :     flit_chanel_t ss_flit_chanel [P-1 : 0]; //flit  bypass link goes to straight port
+  NodeType         : net
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/ss_flit_chanel[0].flit.payload[24]
+  -----------------------------------------------------------------------------
+  Tag              : UndrivenNUnloaded-ML
+  Description      : Detected undriven and unloaded(unconnected) [NodeType] [DesignObjSignal]
+  Violation        : Lint:2342
+  Goal             : lint_rtl
+  Module           : router_top
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 104
+  Statement        :     flit_chanel_t ss_flit_chanel [P-1 : 0]; //flit  bypass link goes to straight port
+  NodeType         : net
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[1].the_router/ss_flit_chanel[0].flit.payload[17]
+  -----------------------------------------------------------------------------
+  Tag              : UndrivenNUnloaded-ML
+  Description      : Detected undriven and unloaded(unconnected) [NodeType] [DesignObjSignal]
+  Violation        : Lint:2356
+  Goal             : lint_rtl
+  Module           : router_top
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 104
+  Statement        :     flit_chanel_t ss_flit_chanel [P-1 : 0]; //flit  bypass link goes to straight port
+  NodeType         : net
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[1].the_router/ss_flit_chanel[0].flit.payload[31]
+  -----------------------------------------------------------------------------
+  Tag              : UndrivenNUnloaded-ML
+  Description      : Detected undriven and unloaded(unconnected) [NodeType] [DesignObjSignal]
+  Violation        : Lint:2328
+  Goal             : lint_rtl
+  Module           : router_top
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 104
+  Statement        :     flit_chanel_t ss_flit_chanel [P-1 : 0]; //flit  bypass link goes to straight port
+  NodeType         : net
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[1].the_router/ss_flit_chanel[0].flit.payload[3]
+  -----------------------------------------------------------------------------
+  Tag              : UndrivenNUnloaded-ML
+  Description      : Detected undriven and unloaded(unconnected) [NodeType] [DesignObjSignal]
+  Violation        : Lint:2539
+  Goal             : lint_rtl
+  Module           : router_top
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 104
+  Statement        :     flit_chanel_t ss_flit_chanel [P-1 : 0]; //flit  bypass link goes to straight port
+  NodeType         : net
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[3].the_router/ss_flit_chanel[0].flit.payload[60]
+  -----------------------------------------------------------------------------
+  Tag              : UndrivenNUnloaded-ML
+  Description      : Detected undriven and unloaded(unconnected) [NodeType] [DesignObjSignal]
+  Violation        : Lint:2210
+  Goal             : lint_rtl
+  Module           : router_top
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 104
+  Statement        :     flit_chanel_t ss_flit_chanel [P-1 : 0]; //flit  bypass link goes to straight port
+  NodeType         : net
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/ss_flit_chanel[0].flit.payload[22]
+  -----------------------------------------------------------------------------
+  Tag              : UndrivenNUnloaded-ML
+  Description      : Detected undriven and unloaded(unconnected) [NodeType] [DesignObjSignal]
+  Violation        : Lint:2316
+  Goal             : lint_rtl
+  Module           : smart_allocator_per_iport
+  FileName         : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber       : 655
+  Statement        :     ) lkrouting (
+  NodeType         : terminal
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/smart.Port_[1].smart_en.smart_allocator/lkrouting/src_e_addr[1:0]
+  -----------------------------------------------------------------------------
+  Tag              : UndrivenNUnloaded-ML
+  Description      : Detected undriven and unloaded(unconnected) [NodeType] [DesignObjSignal]
+  Violation        : Lint:2346
+  Goal             : lint_rtl
+  Module           : router_top
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 104
+  Statement        :     flit_chanel_t ss_flit_chanel [P-1 : 0]; //flit  bypass link goes to straight port
+  NodeType         : net
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[1].the_router/ss_flit_chanel[0].flit.payload[21]
+  -----------------------------------------------------------------------------
+  Tag              : UndrivenNUnloaded-ML
+  Description      : Detected undriven and unloaded(unconnected) [NodeType] [DesignObjSignal]
+  Violation        : Lint:2529
+  Goal             : lint_rtl
+  Module           : router_top
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 104
+  Statement        :     flit_chanel_t ss_flit_chanel [P-1 : 0]; //flit  bypass link goes to straight port
+  NodeType         : net
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[3].the_router/ss_flit_chanel[0].flit.payload[50]
+
+  -----------------------------------------------------------------------------
+  UnloadedInPort-ML  (907 warnings/0 waived)
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedInPort-ML
+  Description      : Detected unloaded(unconnected)input port [DesignObjSignal]
+  Violation        : Lint:1428
+  Goal             : lint_rtl
+  Module           : input_queue_per_port
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[3].the_router/router_ref/the_inout_ports/the_input_port/Port_[2].the_input_queue_per_port/ctrl_in[0].endp_addr[0]
+  FileName         : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber       : 284
+  Statement        :     input   ctrl_chanel_t ctrl_in  [P-1 : 0];
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedInPort-ML
+  Description      : Detected unloaded(unconnected)input port [DesignObjSignal]
+  Violation        : Lint:1162
+  Goal             : lint_rtl
+  Module           : smart_allocator_per_iport
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[1].the_router/smart.Port_[2].smart_en.smart_allocator/flit_chanel_i.flit.vc[0]
+  FileName         : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber       : 577
+  Statement        :     input flit_chanel_t flit_chanel_i;
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedInPort-ML
+  Description      : Detected unloaded(unconnected)input port [DesignObjSignal]
+  Violation        : Lint:893
+  Goal             : lint_rtl
+  Module           : smart_forward_ivc_info
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/smart.forward_ivc/ivc_info[1][0].dest_port_encoded[0]
+  FileName         : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber       : 224
+  Statement        :     input  ivc_info_t     ivc_info    [P-1 : 0][V-1 : 0];
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedInPort-ML
+  Description      : Detected unloaded(unconnected)input port [DesignObjSignal]
+  Violation        : Lint:620
+  Goal             : lint_rtl
+  Module           : look_ahead_routing
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/router_ref/the_inout_ports/the_input_port/Port_[0].the_input_queue_per_port/unicast.lk_routing/src_e_addr[1]
+  FileName         : ./../../rtl/src_noc/./routing.v
+  LineNumber       : 279
+  Statement        :     input   [EAw-1   :   0]  src_e_addr;
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedInPort-ML
+  Description      : Detected unloaded(unconnected)input port [DesignObjSignal]
+  Violation        : Lint:659
+  Goal             : lint_rtl
+  Module           : look_ahead_routing
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/router_ref/the_inout_ports/the_input_port/Port_[1].the_input_queue_per_port/unicast.lk_routing/src_e_addr[0]
+  FileName         : ./../../rtl/src_noc/./routing.v
+  LineNumber       : 279
+  Statement        :     input   [EAw-1   :   0]  src_e_addr;
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedInPort-ML
+  Description      : Detected unloaded(unconnected)input port [DesignObjSignal]
+  Violation        : Lint:1110
+  Goal             : lint_rtl
+  Module           : smart_allocator_per_iport
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[1].the_router/smart.Port_[2].smart_en.smart_allocator/flit_chanel_i.flit.payload[12]
+  FileName         : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber       : 577
+  Statement        :     input flit_chanel_t flit_chanel_i;
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedInPort-ML
+  Description      : Detected unloaded(unconnected)input port [DesignObjSignal]
+  Violation        : Lint:1087
+  Goal             : lint_rtl
+  Module           : smart_allocator_per_iport
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/smart.Port_[2].smart_en.smart_allocator/ss_smart_chanel_new.dest_e_addr[1]
+  FileName         : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber       : 584
+  Statement        :     input smart_chanel_t ss_smart_chanel_new;
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedInPort-ML
+  Description      : Detected unloaded(unconnected)input port [DesignObjSignal]
+  Violation        : Lint:1247
+  Goal             : lint_rtl
+  Module           : input_queue_per_port
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[1].the_router/router_ref/the_inout_ports/the_input_port/Port_[2].the_input_queue_per_port/ctrl_in[0].credit_init_val[0][4]
+  FileName         : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber       : 284
+  Statement        :     input   ctrl_chanel_t ctrl_in  [P-1 : 0];
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedInPort-ML
+  Description      : Detected unloaded(unconnected)input port [DesignObjSignal]
+  Violation        : Lint:1262
+  Goal             : lint_rtl
+  Module           : inout_ports
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[2].the_router/router_ref/the_inout_ports/spec_first_arbiter_granted_ivc_all[1]
+  FileName         : ./../../rtl/src_noc/./inout_ports.sv
+  LineNumber       : 118
+  Statement        :     input [PV-1 : 0] spec_first_arbiter_granted_ivc_all;
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedInPort-ML
+  Description      : Detected unloaded(unconnected)input port [DesignObjSignal]
+  Violation        : Lint:555
+  Goal             : lint_rtl
+  Module           : extract_header_flit_info
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/router_ref/the_inout_ports/the_input_port/Port_[0].the_input_queue_per_port/header_extractor/flit_in[9]
+  FileName         : ./../../rtl/src_noc/./header_flit.sv
+  LineNumber       : 137
+  Statement        :     input [Fw-1 : 0] flit_in;
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedInPort-ML
+  Description      : Detected unloaded(unconnected)input port [DesignObjSignal]
+  Violation        : Lint:1306
+  Goal             : lint_rtl
+  Module           : input_queue_per_port
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[2].the_router/router_ref/the_inout_ports/the_input_port/Port_[1].the_input_queue_per_port/ctrl_in[0].credit_init_val[0][4]
+  FileName         : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber       : 284
+  Statement        :     input   ctrl_chanel_t ctrl_in  [P-1 : 0];
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedInPort-ML
+  Description      : Detected unloaded(unconnected)input port [DesignObjSignal]
+  Violation        : Lint:1142
+  Goal             : lint_rtl
+  Module           : smart_allocator_per_iport
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[1].the_router/smart.Port_[2].smart_en.smart_allocator/flit_chanel_i.flit.payload[44]
+  FileName         : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber       : 577
+  Statement        :     input flit_chanel_t flit_chanel_i;
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedInPort-ML
+  Description      : Detected unloaded(unconnected)input port [DesignObjSignal]
+  Violation        : Lint:1368
+  Goal             : lint_rtl
+  Module           : input_queue_per_port
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[3].the_router/router_ref/the_inout_ports/the_input_port/Port_[0].the_input_queue_per_port/ctrl_in[0].endp_addr[0]
+  FileName         : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber       : 284
+  Statement        :     input   ctrl_chanel_t ctrl_in  [P-1 : 0];
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedInPort-ML
+  Description      : Detected unloaded(unconnected)input port [DesignObjSignal]
+  Violation        : Lint:935
+  Goal             : lint_rtl
+  Module           : smart_bypass_chanels
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/smart.smart_bypass/ivc_info[2][0].ivc_req
+  FileName         : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber       : 332
+  Statement        :     input ivc_info_t   ivc_info    [P-1 : 0][V-1 : 0];
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedInPort-ML
+  Description      : Detected unloaded(unconnected)input port [DesignObjSignal]
+  Violation        : Lint:991
+  Goal             : lint_rtl
+  Module           : smart_allocator_per_iport
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/smart.Port_[1].smart_en.smart_allocator/flit_chanel_i.flit.payload[8]
+  FileName         : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber       : 577
+  Statement        :     input flit_chanel_t flit_chanel_i;
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedInPort-ML
+  Description      : Detected unloaded(unconnected)input port [DesignObjSignal]
+  Violation        : Lint:966
+  Goal             : lint_rtl
+  Module           : smart_bypass_chanels
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/smart.smart_bypass/smart_chanel_new[0].hdr_flit
+  FileName         : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber       : 330
+  Statement        :     input smart_chanel_t smart_chanel_new  [P-1 : 0];
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedInPort-ML
+  Description      : Detected unloaded(unconnected)input port [DesignObjSignal]
+  Violation        : Lint:591
+  Goal             : lint_rtl
+  Module           : extract_header_flit_info
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/router_ref/the_inout_ports/the_input_port/Port_[0].the_input_queue_per_port/header_extractor/flit_in[45]
+  FileName         : ./../../rtl/src_noc/./header_flit.sv
+  LineNumber       : 137
+  Statement        :     input [Fw-1 : 0] flit_in;
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedInPort-ML
+  Description      : Detected unloaded(unconnected)input port [DesignObjSignal]
+  Violation        : Lint:1421
+  Goal             : lint_rtl
+  Module           : input_queue_per_port
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[3].the_router/router_ref/the_inout_ports/the_input_port/Port_[2].the_input_queue_per_port/ctrl_in[0].credit_init_val[0][0]
+  FileName         : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber       : 284
+  Statement        :     input   ctrl_chanel_t ctrl_in  [P-1 : 0];
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedInPort-ML
+  Description      : Detected unloaded(unconnected)input port [DesignObjSignal]
+  Violation        : Lint:579
+  Goal             : lint_rtl
+  Module           : extract_header_flit_info
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/router_ref/the_inout_ports/the_input_port/Port_[0].the_input_queue_per_port/header_extractor/flit_in[33]
+  FileName         : ./../../rtl/src_noc/./header_flit.sv
+  LineNumber       : 137
+  Statement        :     input [Fw-1 : 0] flit_in;
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedInPort-ML
+  Description      : Detected unloaded(unconnected)input port [DesignObjSignal]
+  Violation        : Lint:1353
+  Goal             : lint_rtl
+  Module           : input_queue_per_port
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[3].the_router/router_ref/the_inout_ports/the_input_port/Port_[0].the_input_queue_per_port/granted_dest_port[0]
+  FileName         : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber       : 274
+  Statement        :     input   [P_1-1 : 0] granted_dest_port; 
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedInPort-ML
+  Description      : Detected unloaded(unconnected)input port [DesignObjSignal]
+  Violation        : Lint:1059
+  Goal             : lint_rtl
+  Module           : smart_allocator_per_iport
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/smart.Port_[1].smart_en.smart_allocator/ss_ovc_info[0].credit[0]
+  FileName         : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber       : 582
+  Statement        :     input ovc_info_t   ss_ovc_info [V-1 : 0];
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedInPort-ML
+  Description      : Detected unloaded(unconnected)input port [DesignObjSignal]
+  Violation        : Lint:1302
+  Goal             : lint_rtl
+  Module           : input_queue_per_port
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[2].the_router/router_ref/the_inout_ports/the_input_port/Port_[1].the_input_queue_per_port/ctrl_in[0].credit_init_val[0][0]
+  FileName         : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber       : 284
+  Statement        :     input   ctrl_chanel_t ctrl_in  [P-1 : 0];
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedInPort-ML
+  Description      : Detected unloaded(unconnected)input port [DesignObjSignal]
+  Violation        : Lint:793
+  Goal             : lint_rtl
+  Module           : vc_alloc_request_gen
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/router_ref/the_inout_ports/vc_alloc_req_gen/ivc_info[1][0].destport_one_hot[2]
+  FileName         : ./../../rtl/src_noc/./inout_ports.sv
+  LineNumber       : 474
+  Statement        :     input   ivc_info_t   ivc_info    [P-1 : 0][V-1 : 0];
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedInPort-ML
+  Description      : Detected unloaded(unconnected)input port [DesignObjSignal]
+  Violation        : Lint:742
+  Goal             : lint_rtl
+  Module           : output_ports
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/router_ref/the_inout_ports/output_ports/smart_ctrl_in[1].ivc_num_getting_ovc_grant[0]
+  FileName         : ./../../rtl/src_noc/./output_ports.sv
+  LineNumber       : 97
+  Statement        :     input  smart_ctrl_t  smart_ctrl_in [P-1: 0];
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedInPort-ML
+  Description      : Detected unloaded(unconnected)input port [DesignObjSignal]
+  Violation        : Lint:664
+  Goal             : lint_rtl
+  Module           : input_queue_per_port
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/router_ref/the_inout_ports/the_input_port/Port_[2].the_input_queue_per_port/smart_ctrl_in.mask_available_ovc[0]
+  FileName         : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber       : 280
+  Statement        :     input   smart_ctrl_t  smart_ctrl_in;
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedInPort-ML
+  Description      : Detected unloaded(unconnected)input port [DesignObjSignal]
+  Violation        : Lint:1122
+  Goal             : lint_rtl
+  Module           : smart_allocator_per_iport
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[1].the_router/smart.Port_[2].smart_en.smart_allocator/flit_chanel_i.flit.payload[24]
+  FileName         : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber       : 577
+  Statement        :     input flit_chanel_t flit_chanel_i;
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedInPort-ML
+  Description      : Detected unloaded(unconnected)input port [DesignObjSignal]
+  Violation        : Lint:1342
+  Goal             : lint_rtl
+  Module           : router_top
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[3].the_router/chan_in[0].smart_chanel.flit_in_bypassed
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 49
+  Statement        :     input smartflit_chanel_t chan_in [P-1 : 0];
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedInPort-ML
+  Description      : Detected unloaded(unconnected)input port [DesignObjSignal]
+  Violation        : Lint:1300
+  Goal             : lint_rtl
+  Module           : input_queue_per_port
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[2].the_router/router_ref/the_inout_ports/the_input_port/Port_[1].the_input_queue_per_port/ctrl_in[0].hetero_ovc_presence[0]
+  FileName         : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber       : 284
+  Statement        :     input   ctrl_chanel_t ctrl_in  [P-1 : 0];
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedInPort-ML
+  Description      : Detected unloaded(unconnected)input port [DesignObjSignal]
+  Violation        : Lint:1068
+  Goal             : lint_rtl
+  Module           : conventional_routing
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/smart.Port_[1].smart_en.smart_allocator/routing/reset
+  FileName         : ./../../rtl/src_noc/./routing.v
+  LineNumber       : 61
+  Statement        :     input  reset,clk;
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedInPort-ML
+  Description      : Detected unloaded(unconnected)input port [DesignObjSignal]
+  Violation        : Lint:947
+  Goal             : lint_rtl
+  Module           : smart_bypass_chanels
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/smart.smart_bypass/iport_info[0].granted_oport_one_hot[2]
+  FileName         : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber       : 333
+  Statement        :     input iport_info_t iport_info  [P-1 : 0];
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedInPort-ML
+  Description      : Detected unloaded(unconnected)input port [DesignObjSignal]
+  Violation        : Lint:1323
+  Goal             : lint_rtl
+  Module           : input_queue_per_port
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[2].the_router/router_ref/the_inout_ports/the_input_port/Port_[2].the_input_queue_per_port/smart_ctrl_in.lk_destport[1]
+  FileName         : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber       : 280
+  Statement        :     input   smart_ctrl_t  smart_ctrl_in;
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedInPort-ML
+  Description      : Detected unloaded(unconnected)input port [DesignObjSignal]
+  Violation        : Lint:1133
+  Goal             : lint_rtl
+  Module           : smart_allocator_per_iport
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[1].the_router/smart.Port_[2].smart_en.smart_allocator/flit_chanel_i.flit.payload[35]
+  FileName         : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber       : 577
+  Statement        :     input flit_chanel_t flit_chanel_i;
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedInPort-ML
+  Description      : Detected unloaded(unconnected)input port [DesignObjSignal]
+  Violation        : Lint:975
+  Goal             : lint_rtl
+  Module           : smart_allocator_per_iport
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/smart.Port_[1].smart_en.smart_allocator/smart_chanel_i.bypassed_num[0]
+  FileName         : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber       : 576
+  Statement        :     input smart_chanel_t smart_chanel_i;
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedInPort-ML
+  Description      : Detected unloaded(unconnected)input port [DesignObjSignal]
+  Violation        : Lint:1250
+  Goal             : lint_rtl
+  Module           : input_queue_per_port
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[1].the_router/router_ref/the_inout_ports/the_input_port/Port_[2].the_input_queue_per_port/ctrl_in[0].endp_addr[0]
+  FileName         : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber       : 284
+  Statement        :     input   ctrl_chanel_t ctrl_in  [P-1 : 0];
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedInPort-ML
+  Description      : Detected unloaded(unconnected)input port [DesignObjSignal]
+  Violation        : Lint:529
+  Goal             : lint_rtl
+  Module           : router_top
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/chan_in[0].smart_chanel.requests[0]
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 49
+  Statement        :     input smartflit_chanel_t chan_in [P-1 : 0];
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedInPort-ML
+  Description      : Detected unloaded(unconnected)input port [DesignObjSignal]
+  Violation        : Lint:1170
+  Goal             : lint_rtl
+  Module           : router_top
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[1].the_router/chan_in[0].smart_chanel.requests[1]
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 49
+  Statement        :     input smartflit_chanel_t chan_in [P-1 : 0];
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedInPort-ML
+  Description      : Detected unloaded(unconnected)input port [DesignObjSignal]
+  Violation        : Lint:1297
+  Goal             : lint_rtl
+  Module           : input_queue_per_port
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[2].the_router/router_ref/the_inout_ports/the_input_port/Port_[1].the_input_queue_per_port/vsa_ctrl_in.buff_space_decreased[0]
+  FileName         : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber       : 281
+  Statement        :     input   vsa_ctrl_t  vsa_ctrl_in;
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedInPort-ML
+  Description      : Detected unloaded(unconnected)input port [DesignObjSignal]
+  Violation        : Lint:668
+  Goal             : lint_rtl
+  Module           : input_queue_per_port
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/router_ref/the_inout_ports/the_input_port/Port_[2].the_input_queue_per_port/smart_ctrl_in.credit_out[0]
+  FileName         : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber       : 280
+  Statement        :     input   smart_ctrl_t  smart_ctrl_in;
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedInPort-ML
+  Description      : Detected unloaded(unconnected)input port [DesignObjSignal]
+  Violation        : Lint:1260
+  Goal             : lint_rtl
+  Module           : router_top
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[2].the_router/chan_in[0].smart_chanel.requests[2]
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 49
+  Statement        :     input smartflit_chanel_t chan_in [P-1 : 0];
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedInPort-ML
+  Description      : Detected unloaded(unconnected)input port [DesignObjSignal]
+  Violation        : Lint:736
+  Goal             : lint_rtl
+  Module           : output_ports
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/router_ref/the_inout_ports/output_ports/vsa_ctrl_in[2].ivc_reset[0]
+  FileName         : ./../../rtl/src_noc/./output_ports.sv
+  LineNumber       : 95
+  Statement        :     input  vsa_ctrl_t vsa_ctrl_in [P-1: 0];
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedInPort-ML
+  Description      : Detected unloaded(unconnected)input port [DesignObjSignal]
+  Violation        : Lint:1120
+  Goal             : lint_rtl
+  Module           : smart_allocator_per_iport
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[1].the_router/smart.Port_[2].smart_en.smart_allocator/flit_chanel_i.flit.payload[22]
+  FileName         : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber       : 577
+  Statement        :     input flit_chanel_t flit_chanel_i;
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedInPort-ML
+  Description      : Detected unloaded(unconnected)input port [DesignObjSignal]
+  Violation        : Lint:737
+  Goal             : lint_rtl
+  Module           : output_ports
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/router_ref/the_inout_ports/output_ports/vsa_ctrl_in[2].ivc_num_getting_ovc_grant[0]
+  FileName         : ./../../rtl/src_noc/./output_ports.sv
+  LineNumber       : 95
+  Statement        :     input  vsa_ctrl_t vsa_ctrl_in [P-1: 0];
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedInPort-ML
+  Description      : Detected unloaded(unconnected)input port [DesignObjSignal]
+  Violation        : Lint:1393
+  Goal             : lint_rtl
+  Module           : input_queue_per_port
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[3].the_router/router_ref/the_inout_ports/the_input_port/Port_[1].the_input_queue_per_port/ctrl_in[0].credit_init_val[0][2]
+  FileName         : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber       : 284
+  Statement        :     input   ctrl_chanel_t ctrl_in  [P-1 : 0];
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedInPort-ML
+  Description      : Detected unloaded(unconnected)input port [DesignObjSignal]
+  Violation        : Lint:766
+  Goal             : lint_rtl
+  Module           : port_pre_sel_gen
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/router_ref/the_inout_ports/output_ports/port_pre_sel_top/congestion_in_all[1]
+  FileName         : ./../../rtl/src_noc/./congestion_analyzer.v
+  LineNumber       : 355
+  Statement        :     input [CONG_ALw-1 : 0] congestion_in_all;  
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedInPort-ML
+  Description      : Detected unloaded(unconnected)input port [DesignObjSignal]
+  Violation        : Lint:1404
+  Goal             : lint_rtl
+  Module           : input_queue_per_port
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[3].the_router/router_ref/the_inout_ports/the_input_port/Port_[2].the_input_queue_per_port/smart_ctrl_in.mask_available_ovc[0]
+  FileName         : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber       : 280
+  Statement        :     input   smart_ctrl_t  smart_ctrl_in;
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedInPort-ML
+  Description      : Detected unloaded(unconnected)input port [DesignObjSignal]
+  Violation        : Lint:1064
+  Goal             : lint_rtl
+  Module           : smart_allocator_per_iport
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/smart.Port_[1].smart_en.smart_allocator/ss_smart_chanel_new.dest_e_addr[0]
+  FileName         : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber       : 584
+  Statement        :     input smart_chanel_t ss_smart_chanel_new;
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedInPort-ML
+  Description      : Detected unloaded(unconnected)input port [DesignObjSignal]
+  Violation        : Lint:1223
+  Goal             : lint_rtl
+  Module           : input_queue_per_port
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[1].the_router/router_ref/the_inout_ports/the_input_port/Port_[2].the_input_queue_per_port/granted_dest_port[0]
+  FileName         : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber       : 274
+  Statement        :     input   [P_1-1 : 0] granted_dest_port; 
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedInPort-ML
+  Description      : Detected unloaded(unconnected)input port [DesignObjSignal]
+  Violation        : Lint:1047
+  Goal             : lint_rtl
+  Module           : smart_allocator_per_iport
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/smart.Port_[1].smart_en.smart_allocator/flit_chanel_i.flit.vc[0]
+  FileName         : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber       : 577
+  Statement        :     input flit_chanel_t flit_chanel_i;
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedInPort-ML
+  Description      : Detected unloaded(unconnected)input port [DesignObjSignal]
+  Violation        : Lint:950
+  Goal             : lint_rtl
+  Module           : smart_bypass_chanels
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/smart.smart_bypass/iport_info[1].any_ivc_get_swa_grant
+  FileName         : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber       : 333
+  Statement        :     input iport_info_t iport_info  [P-1 : 0];
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedInPort-ML
+  Description      : Detected unloaded(unconnected)input port [DesignObjSignal]
+  Violation        : Lint:1285
+  Goal             : lint_rtl
+  Module           : input_queue_per_port
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[2].the_router/router_ref/the_inout_ports/the_input_port/Port_[1].the_input_queue_per_port/smart_ctrl_in.mask_available_ovc[0]
+  FileName         : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber       : 280
+  Statement        :     input   smart_ctrl_t  smart_ctrl_in;
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedInPort-ML
+  Description      : Detected unloaded(unconnected)input port [DesignObjSignal]
+  Violation        : Lint:1400
+  Goal             : lint_rtl
+  Module           : input_queue_per_port
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[3].the_router/router_ref/the_inout_ports/the_input_port/Port_[1].the_input_queue_per_port/ctrl_in[0].endp_port
+  FileName         : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber       : 284
+  Statement        :     input   ctrl_chanel_t ctrl_in  [P-1 : 0];
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedInPort-ML
+  Description      : Detected unloaded(unconnected)input port [DesignObjSignal]
+  Violation        : Lint:566
+  Goal             : lint_rtl
+  Module           : extract_header_flit_info
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/router_ref/the_inout_ports/the_input_port/Port_[0].the_input_queue_per_port/header_extractor/flit_in[20]
+  FileName         : ./../../rtl/src_noc/./header_flit.sv
+  LineNumber       : 137
+  Statement        :     input [Fw-1 : 0] flit_in;
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedInPort-ML
+  Description      : Detected unloaded(unconnected)input port [DesignObjSignal]
+  Violation        : Lint:561
+  Goal             : lint_rtl
+  Module           : extract_header_flit_info
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/router_ref/the_inout_ports/the_input_port/Port_[0].the_input_queue_per_port/header_extractor/flit_in[15]
+  FileName         : ./../../rtl/src_noc/./header_flit.sv
+  LineNumber       : 137
+  Statement        :     input [Fw-1 : 0] flit_in;
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedInPort-ML
+  Description      : Detected unloaded(unconnected)input port [DesignObjSignal]
+  Violation        : Lint:752
+  Goal             : lint_rtl
+  Module           : output_ports
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/router_ref/the_inout_ports/output_ports/smart_ctrl_in[2].mask_available_ovc[0]
+  FileName         : ./../../rtl/src_noc/./output_ports.sv
+  LineNumber       : 97
+  Statement        :     input  smart_ctrl_t  smart_ctrl_in [P-1: 0];
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedInPort-ML
+  Description      : Detected unloaded(unconnected)input port [DesignObjSignal]
+  Violation        : Lint:846
+  Goal             : lint_rtl
+  Module           : vc_alloc_request_gen
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/router_ref/the_inout_ports/vc_alloc_req_gen/ctrl_in[0].endp_addr[0]
+  FileName         : ./../../rtl/src_noc/./inout_ports.sv
+  LineNumber       : 475
+  Statement        :     input   ctrl_chanel_t ctrl_in  [P-1 : 0];
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedInPort-ML
+  Description      : Detected unloaded(unconnected)input port [DesignObjSignal]
+  Violation        : Lint:655
+  Goal             : lint_rtl
+  Module           : flit_buffer
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/router_ref/the_inout_ports/the_input_port/Port_[1].the_input_queue_per_port/the_flit_buffer/sub_rd_ptr_ld[0]
+  FileName         : ./../../rtl/src_noc/./flit_buffer.sv
+  LineNumber       : 81
+  Statement        :     input [V-1 :0]  sub_rd_ptr_ld;
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedInPort-ML
+  Description      : Detected unloaded(unconnected)input port [DesignObjSignal]
+  Violation        : Lint:1236
+  Goal             : lint_rtl
+  Module           : input_queue_per_port
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[1].the_router/router_ref/the_inout_ports/the_input_port/Port_[2].the_input_queue_per_port/smart_ctrl_in.hdr_flit_req
+  FileName         : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber       : 280
+  Statement        :     input   smart_ctrl_t  smart_ctrl_in;
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedInPort-ML
+  Description      : Detected unloaded(unconnected)input port [DesignObjSignal]
+  Violation        : Lint:1279
+  Goal             : lint_rtl
+  Module           : input_queue_per_port
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[2].the_router/router_ref/the_inout_ports/the_input_port/Port_[0].the_input_queue_per_port/ctrl_in[0].endp_addr[0]
+  FileName         : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber       : 284
+  Statement        :     input   ctrl_chanel_t ctrl_in  [P-1 : 0];
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedInPort-ML
+  Description      : Detected unloaded(unconnected)input port [DesignObjSignal]
+  Violation        : Lint:592
+  Goal             : lint_rtl
+  Module           : extract_header_flit_info
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/router_ref/the_inout_ports/the_input_port/Port_[0].the_input_queue_per_port/header_extractor/flit_in[46]
+  FileName         : ./../../rtl/src_noc/./header_flit.sv
+  LineNumber       : 137
+  Statement        :     input [Fw-1 : 0] flit_in;
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedInPort-ML
+  Description      : Detected unloaded(unconnected)input port [DesignObjSignal]
+  Violation        : Lint:1149
+  Goal             : lint_rtl
+  Module           : smart_allocator_per_iport
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[1].the_router/smart.Port_[2].smart_en.smart_allocator/flit_chanel_i.flit.payload[51]
+  FileName         : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber       : 577
+  Statement        :     input flit_chanel_t flit_chanel_i;
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedInPort-ML
+  Description      : Detected unloaded(unconnected)input port [DesignObjSignal]
+  Violation        : Lint:1066
+  Goal             : lint_rtl
+  Module           : smart_allocator_per_iport
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/smart.Port_[1].smart_en.smart_allocator/ss_smart_chanel_new.requests[1]
+  FileName         : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber       : 584
+  Statement        :     input smart_chanel_t ss_smart_chanel_new;
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedInPort-ML
+  Description      : Detected unloaded(unconnected)input port [DesignObjSignal]
+  Violation        : Lint:856
+  Goal             : lint_rtl
+  Module           : comb_nonspec_allocator
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/router_ref/vsa/nonspec.cmb_v1.nonspec_comb/ivc_info[0][0].flit_is_tail
+  FileName         : ./../../rtl/src_noc/./comb_nonspec.sv
+  LineNumber       : 73
+  Statement        :     input  ivc_info_t ivc_info [P-1 : 0][V-1 : 0]; 
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedInPort-ML
+  Description      : Detected unloaded(unconnected)input port [DesignObjSignal]
+  Violation        : Lint:957
+  Goal             : lint_rtl
+  Module           : smart_bypass_chanels
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/smart.smart_bypass/iport_info[2].granted_oport_one_hot[0]
+  FileName         : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber       : 333
+  Statement        :     input iport_info_t iport_info  [P-1 : 0];
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedInPort-ML
+  Description      : Detected unloaded(unconnected)input port [DesignObjSignal]
+  Violation        : Lint:1201
+  Goal             : lint_rtl
+  Module           : input_queue_per_port
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[1].the_router/router_ref/the_inout_ports/the_input_port/Port_[1].the_input_queue_per_port/smart_ctrl_in.destport[0]
+  FileName         : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber       : 280
+  Statement        :     input   smart_ctrl_t  smart_ctrl_in;
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedInPort-ML
+  Description      : Detected unloaded(unconnected)input port [DesignObjSignal]
+  Violation        : Lint:1044
+  Goal             : lint_rtl
+  Module           : smart_allocator_per_iport
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/smart.Port_[1].smart_en.smart_allocator/flit_chanel_i.flit.payload[61]
+  FileName         : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber       : 577
+  Statement        :     input flit_chanel_t flit_chanel_i;
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedInPort-ML
+  Description      : Detected unloaded(unconnected)input port [DesignObjSignal]
+  Violation        : Lint:1367
+  Goal             : lint_rtl
+  Module           : input_queue_per_port
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[3].the_router/router_ref/the_inout_ports/the_input_port/Port_[0].the_input_queue_per_port/ctrl_in[0].router_addr[1]
+  FileName         : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber       : 284
+  Statement        :     input   ctrl_chanel_t ctrl_in  [P-1 : 0];
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedInPort-ML
+  Description      : Detected unloaded(unconnected)input port [DesignObjSignal]
+  Violation        : Lint:1255
+  Goal             : lint_rtl
+  Module           : router_top
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[2].the_router/chan_in[0].smart_chanel.dest_e_addr[0]
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 49
+  Statement        :     input smartflit_chanel_t chan_in [P-1 : 0];
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedInPort-ML
+  Description      : Detected unloaded(unconnected)input port [DesignObjSignal]
+  Violation        : Lint:662
+  Goal             : lint_rtl
+  Module           : input_queue_per_port
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/router_ref/the_inout_ports/the_input_port/Port_[2].the_input_queue_per_port/granted_dest_port[1]
+  FileName         : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber       : 274
+  Statement        :     input   [P_1-1 : 0] granted_dest_port; 
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedInPort-ML
+  Description      : Detected unloaded(unconnected)input port [DesignObjSignal]
+  Violation        : Lint:530
+  Goal             : lint_rtl
+  Module           : router_top
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/chan_in[0].smart_chanel.requests[1]
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 49
+  Statement        :     input smartflit_chanel_t chan_in [P-1 : 0];
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedInPort-ML
+  Description      : Detected unloaded(unconnected)input port [DesignObjSignal]
+  Violation        : Lint:1134
+  Goal             : lint_rtl
+  Module           : smart_allocator_per_iport
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[1].the_router/smart.Port_[2].smart_en.smart_allocator/flit_chanel_i.flit.payload[36]
+  FileName         : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber       : 577
+  Statement        :     input flit_chanel_t flit_chanel_i;
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedInPort-ML
+  Description      : Detected unloaded(unconnected)input port [DesignObjSignal]
+  Violation        : Lint:699
+  Goal             : lint_rtl
+  Module           : output_ports
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/router_ref/the_inout_ports/output_ports/ivc_info[0][0].assigned_ovc_not_full
+  FileName         : ./../../rtl/src_noc/./output_ports.sv
+  LineNumber       : 94
+  Statement        :     input  ivc_info_t ivc_info [P-1 : 0][V-1 : 0]; 
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedInPort-ML
+  Description      : Detected unloaded(unconnected)input port [DesignObjSignal]
+  Violation        : Lint:901
+  Goal             : lint_rtl
+  Module           : smart_forward_ivc_info
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/smart.forward_ivc/iport_info[0].any_ivc_get_swa_grant
+  FileName         : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber       : 225
+  Statement        :     input  iport_info_t iport_info  [P-1 : 0];
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedInPort-ML
+  Description      : Detected unloaded(unconnected)input port [DesignObjSignal]
+  Violation        : Lint:725
+  Goal             : lint_rtl
+  Module           : output_ports
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/router_ref/the_inout_ports/output_ports/ivc_info[2][0].dest_e_addr[0]
+  FileName         : ./../../rtl/src_noc/./output_ports.sv
+  LineNumber       : 94
+  Statement        :     input  ivc_info_t ivc_info [P-1 : 0][V-1 : 0]; 
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedInPort-ML
+  Description      : Detected unloaded(unconnected)input port [DesignObjSignal]
+  Violation        : Lint:672
+  Goal             : lint_rtl
+  Module           : input_queue_per_port
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/router_ref/the_inout_ports/the_input_port/Port_[2].the_input_queue_per_port/smart_ctrl_in.lk_destport[1]
+  FileName         : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber       : 280
+  Statement        :     input   smart_ctrl_t  smart_ctrl_in;
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedInPort-ML
+  Description      : Detected unloaded(unconnected)input port [DesignObjSignal]
+  Violation        : Lint:960
+  Goal             : lint_rtl
+  Module           : smart_bypass_chanels
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/smart.smart_bypass/iport_info[2].swa_grant[0]
+  FileName         : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber       : 333
+  Statement        :     input iport_info_t iport_info  [P-1 : 0];
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedInPort-ML
+  Description      : Detected unloaded(unconnected)input port [DesignObjSignal]
+  Violation        : Lint:1369
+  Goal             : lint_rtl
+  Module           : input_queue_per_port
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[3].the_router/router_ref/the_inout_ports/the_input_port/Port_[0].the_input_queue_per_port/ctrl_in[0].endp_addr[1]
+  FileName         : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber       : 284
+  Statement        :     input   ctrl_chanel_t ctrl_in  [P-1 : 0];
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedInPort-ML
+  Description      : Detected unloaded(unconnected)input port [DesignObjSignal]
+  Violation        : Lint:1132
+  Goal             : lint_rtl
+  Module           : smart_allocator_per_iport
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[1].the_router/smart.Port_[2].smart_en.smart_allocator/flit_chanel_i.flit.payload[34]
+  FileName         : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber       : 577
+  Statement        :     input flit_chanel_t flit_chanel_i;
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedInPort-ML
+  Description      : Detected unloaded(unconnected)input port [DesignObjSignal]
+  Violation        : Lint:959
+  Goal             : lint_rtl
+  Module           : smart_bypass_chanels
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/smart.smart_bypass/iport_info[2].granted_oport_one_hot[2]
+  FileName         : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber       : 333
+  Statement        :     input iport_info_t iport_info  [P-1 : 0];
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedInPort-ML
+  Description      : Detected unloaded(unconnected)input port [DesignObjSignal]
+  Violation        : Lint:1286
+  Goal             : lint_rtl
+  Module           : input_queue_per_port
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[2].the_router/router_ref/the_inout_ports/the_input_port/Port_[1].the_input_queue_per_port/smart_ctrl_in.ovc_is_released[0]
+  FileName         : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber       : 280
+  Statement        :     input   smart_ctrl_t  smart_ctrl_in;
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedInPort-ML
+  Description      : Detected unloaded(unconnected)input port [DesignObjSignal]
+  Violation        : Lint:1209
+  Goal             : lint_rtl
+  Module           : input_queue_per_port
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[1].the_router/router_ref/the_inout_ports/the_input_port/Port_[1].the_input_queue_per_port/vsa_ctrl_in.ovc_is_released[0]
+  FileName         : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber       : 281
+  Statement        :     input   vsa_ctrl_t  vsa_ctrl_in;
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedInPort-ML
+  Description      : Detected unloaded(unconnected)input port [DesignObjSignal]
+  Violation        : Lint:569
+  Goal             : lint_rtl
+  Module           : extract_header_flit_info
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/router_ref/the_inout_ports/the_input_port/Port_[0].the_input_queue_per_port/header_extractor/flit_in[23]
+  FileName         : ./../../rtl/src_noc/./header_flit.sv
+  LineNumber       : 137
+  Statement        :     input [Fw-1 : 0] flit_in;
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedInPort-ML
+  Description      : Detected unloaded(unconnected)input port [DesignObjSignal]
+  Violation        : Lint:835
+  Goal             : lint_rtl
+  Module           : vc_alloc_request_gen
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/router_ref/the_inout_ports/vc_alloc_req_gen/smart_ctrl_in[2].hdr_flit_req
+  FileName         : ./../../rtl/src_noc/./inout_ports.sv
+  LineNumber       : 473
+  Statement        :     input   smart_ctrl_t  smart_ctrl_in [P-1: 0];
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedInPort-ML
+  Description      : Detected unloaded(unconnected)input port [DesignObjSignal]
+  Violation        : Lint:1141
+  Goal             : lint_rtl
+  Module           : smart_allocator_per_iport
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[1].the_router/smart.Port_[2].smart_en.smart_allocator/flit_chanel_i.flit.payload[43]
+  FileName         : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber       : 577
+  Statement        :     input flit_chanel_t flit_chanel_i;
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedInPort-ML
+  Description      : Detected unloaded(unconnected)input port [DesignObjSignal]
+  Violation        : Lint:914
+  Goal             : lint_rtl
+  Module           : smart_bypass_chanels
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/smart.smart_bypass/ivc_info[0][0].dest_port_encoded[1]
+  FileName         : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber       : 332
+  Statement        :     input ivc_info_t   ivc_info    [P-1 : 0][V-1 : 0];
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedInPort-ML
+  Description      : Detected unloaded(unconnected)input port [DesignObjSignal]
+  Violation        : Lint:1392
+  Goal             : lint_rtl
+  Module           : input_queue_per_port
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[3].the_router/router_ref/the_inout_ports/the_input_port/Port_[1].the_input_queue_per_port/ctrl_in[0].credit_init_val[0][1]
+  FileName         : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber       : 284
+  Statement        :     input   ctrl_chanel_t ctrl_in  [P-1 : 0];
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedInPort-ML
+  Description      : Detected unloaded(unconnected)input port [DesignObjSignal]
+  Violation        : Lint:1080
+  Goal             : lint_rtl
+  Module           : smart_allocator_per_iport
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/smart.Port_[2].smart_en.smart_allocator/ss_ovc_info[0].nearly_full
+  FileName         : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber       : 582
+  Statement        :     input ovc_info_t   ss_ovc_info [V-1 : 0];
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedInPort-ML
+  Description      : Detected unloaded(unconnected)input port [DesignObjSignal]
+  Violation        : Lint:1257
+  Goal             : lint_rtl
+  Module           : router_top
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[2].the_router/chan_in[0].smart_chanel.ovc[0]
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 49
+  Statement        :     input smartflit_chanel_t chan_in [P-1 : 0];
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedInPort-ML
+  Description      : Detected unloaded(unconnected)input port [DesignObjSignal]
+  Violation        : Lint:918
+  Goal             : lint_rtl
+  Module           : smart_bypass_chanels
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/smart.smart_bypass/ivc_info[0][0].assigned_ovc_num[0]
+  FileName         : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber       : 332
+  Statement        :     input ivc_info_t   ivc_info    [P-1 : 0][V-1 : 0];
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedInPort-ML
+  Description      : Detected unloaded(unconnected)input port [DesignObjSignal]
+  Violation        : Lint:890
+  Goal             : lint_rtl
+  Module           : smart_forward_ivc_info
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/smart.forward_ivc/ivc_info[0][0].assigned_ovc_num[0]
+  FileName         : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber       : 224
+  Statement        :     input  ivc_info_t     ivc_info    [P-1 : 0][V-1 : 0];
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedInPort-ML
+  Description      : Detected unloaded(unconnected)input port [DesignObjSignal]
+  Violation        : Lint:972
+  Goal             : lint_rtl
+  Module           : smart_bypass_chanels
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/smart.smart_bypass/smart_chanel_new[0].requests[2]
+  FileName         : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber       : 330
+  Statement        :     input smart_chanel_t smart_chanel_new  [P-1 : 0];
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedInPort-ML
+  Description      : Detected unloaded(unconnected)input port [DesignObjSignal]
+  Violation        : Lint:1127
+  Goal             : lint_rtl
+  Module           : smart_allocator_per_iport
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[1].the_router/smart.Port_[2].smart_en.smart_allocator/flit_chanel_i.flit.payload[29]
+  FileName         : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber       : 577
+  Statement        :     input flit_chanel_t flit_chanel_i;
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedInPort-ML
+  Description      : Detected unloaded(unconnected)input port [DesignObjSignal]
+  Violation        : Lint:1117
+  Goal             : lint_rtl
+  Module           : smart_allocator_per_iport
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[1].the_router/smart.Port_[2].smart_en.smart_allocator/flit_chanel_i.flit.payload[19]
+  FileName         : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber       : 577
+  Statement        :     input flit_chanel_t flit_chanel_i;
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedInPort-ML
+  Description      : Detected unloaded(unconnected)input port [DesignObjSignal]
+  Violation        : Lint:541
+  Goal             : lint_rtl
+  Module           : input_queue_per_port
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/router_ref/the_inout_ports/the_input_port/Port_[0].the_input_queue_per_port/ctrl_in[0].hetero_ovc_presence[0]
+  FileName         : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber       : 284
+  Statement        :     input   ctrl_chanel_t ctrl_in  [P-1 : 0];
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedInPort-ML
+  Description      : Detected unloaded(unconnected)input port [DesignObjSignal]
+  Violation        : Lint:1013
+  Goal             : lint_rtl
+  Module           : smart_allocator_per_iport
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/smart.Port_[1].smart_en.smart_allocator/flit_chanel_i.flit.payload[30]
+  FileName         : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber       : 577
+  Statement        :     input flit_chanel_t flit_chanel_i;
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedInPort-ML
+  Description      : Detected unloaded(unconnected)input port [DesignObjSignal]
+  Violation        : Lint:1243
+  Goal             : lint_rtl
+  Module           : input_queue_per_port
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[1].the_router/router_ref/the_inout_ports/the_input_port/Port_[2].the_input_queue_per_port/ctrl_in[0].credit_init_val[0][0]
+  FileName         : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber       : 284
+  Statement        :     input   ctrl_chanel_t ctrl_in  [P-1 : 0];
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedInPort-ML
+  Description      : Detected unloaded(unconnected)input port [DesignObjSignal]
+  Violation        : Lint:1375
+  Goal             : lint_rtl
+  Module           : input_queue_per_port
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[3].the_router/router_ref/the_inout_ports/the_input_port/Port_[1].the_input_queue_per_port/smart_ctrl_in.ovc_is_released[0]
+  FileName         : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber       : 280
+  Statement        :     input   smart_ctrl_t  smart_ctrl_in;
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedInPort-ML
+  Description      : Detected unloaded(unconnected)input port [DesignObjSignal]
+  Violation        : Lint:577
+  Goal             : lint_rtl
+  Module           : extract_header_flit_info
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/router_ref/the_inout_ports/the_input_port/Port_[0].the_input_queue_per_port/header_extractor/flit_in[31]
+  FileName         : ./../../rtl/src_noc/./header_flit.sv
+  LineNumber       : 137
+  Statement        :     input [Fw-1 : 0] flit_in;
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedInPort-ML
+  Description      : Detected unloaded(unconnected)input port [DesignObjSignal]
+  Violation        : Lint:665
+  Goal             : lint_rtl
+  Module           : input_queue_per_port
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/router_ref/the_inout_ports/the_input_port/Port_[2].the_input_queue_per_port/smart_ctrl_in.ovc_is_released[0]
+  FileName         : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber       : 280
+  Statement        :     input   smart_ctrl_t  smart_ctrl_in;
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedInPort-ML
+  Description      : Detected unloaded(unconnected)input port [DesignObjSignal]
+  Violation        : Lint:939
+  Goal             : lint_rtl
+  Module           : smart_bypass_chanels
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/smart.smart_bypass/ivc_info[2][0].destport_one_hot[1]
+  FileName         : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber       : 332
+  Statement        :     input ivc_info_t   ivc_info    [P-1 : 0][V-1 : 0];
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedInPort-ML
+  Description      : Detected unloaded(unconnected)input port [DesignObjSignal]
+  Violation        : Lint:554
+  Goal             : lint_rtl
+  Module           : extract_header_flit_info
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/router_ref/the_inout_ports/the_input_port/Port_[0].the_input_queue_per_port/header_extractor/flit_in[8]
+  FileName         : ./../../rtl/src_noc/./header_flit.sv
+  LineNumber       : 137
+  Statement        :     input [Fw-1 : 0] flit_in;
+
+  -----------------------------------------------------------------------------
+  UnloadedNet-ML  (48 warnings/0 waived)
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedNet-ML
+  Description      : Detected unloaded(unconnected) net [DesignObjSignal]
+  Violation        : Lint:516
+  Goal             : lint_rtl
+  Module           : router_top
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 104
+  Statement        :     flit_chanel_t ss_flit_chanel [P-1 : 0]; //flit  bypass link goes to straight port
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[2].the_router/ss_flit_chanel[2].congestion[0]
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedNet-ML
+  Description      : Detected unloaded(unconnected) net [DesignObjSignal]
+  Violation        : Lint:505
+  Goal             : lint_rtl
+  Module           : router_top
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 104
+  Statement        :     flit_chanel_t ss_flit_chanel [P-1 : 0]; //flit  bypass link goes to straight port
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[1].the_router/ss_flit_chanel[1].congestion[1]
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedNet-ML
+  Description      : Detected unloaded(unconnected) net [DesignObjSignal]
+  Violation        : Lint:476
+  Goal             : lint_rtl
+  Module           : router_top
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 104
+  Statement        :     flit_chanel_t ss_flit_chanel [P-1 : 0]; //flit  bypass link goes to straight port
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/ss_flit_chanel[2].congestion[0]
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedNet-ML
+  Description      : Detected unloaded(unconnected) net [DesignObjSignal]
+  Violation        : Lint:479
+  Goal             : lint_rtl
+  Module           : router_top
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 104
+  Statement        :     flit_chanel_t ss_flit_chanel [P-1 : 0]; //flit  bypass link goes to straight port
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/ss_flit_chanel[2].credit[0]
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedNet-ML
+  Description      : Detected unloaded(unconnected) net [DesignObjSignal]
+  Violation        : Lint:500
+  Goal             : lint_rtl
+  Module           : combined_vc_sw_alloc
+  FileName         : ./../../rtl/src_noc/./combined_vc_sw_alloc.sv
+  LineNumber       : 93
+  Statement        :         assign ovc_is_assigned_all[i] = ivc_info[C_PORT][i%V].ovc_is_assigned;
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/router_ref/vsa/ovc_is_assigned_all[1]
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedNet-ML
+  Description      : Detected unloaded(unconnected) net [DesignObjSignal]
+  Violation        : Lint:518
+  Goal             : lint_rtl
+  Module           : router_top
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 104
+  Statement        :     flit_chanel_t ss_flit_chanel [P-1 : 0]; //flit  bypass link goes to straight port
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[2].the_router/ss_flit_chanel[2].congestion[2]
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedNet-ML
+  Description      : Detected unloaded(unconnected) net [DesignObjSignal]
+  Violation        : Lint:499
+  Goal             : lint_rtl
+  Module           : combined_vc_sw_alloc
+  FileName         : ./../../rtl/src_noc/./combined_vc_sw_alloc.sv
+  LineNumber       : 93
+  Statement        :         assign ovc_is_assigned_all[i] = ivc_info[C_PORT][i%V].ovc_is_assigned;
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/router_ref/vsa/ovc_is_assigned_all[0]
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedNet-ML
+  Description      : Detected unloaded(unconnected) net [DesignObjSignal]
+  Violation        : Lint:497
+  Goal             : lint_rtl
+  Module           : combined_vc_sw_alloc
+  FileName         : ./../../rtl/src_noc/./combined_vc_sw_alloc.sv
+  LineNumber       : 91
+  Statement        :         assign ivc_request_all[i] = ivc_info[C_PORT][i%V].ivc_req;
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/router_ref/vsa/ivc_request_all[1]
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedNet-ML
+  Description      : Detected unloaded(unconnected) net [DesignObjSignal]
+  Violation        : Lint:520
+  Goal             : lint_rtl
+  Module           : router_top
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 104
+  Statement        :     flit_chanel_t ss_flit_chanel [P-1 : 0]; //flit  bypass link goes to straight port
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[3].the_router/ss_flit_chanel[1].congestion[0]
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedNet-ML
+  Description      : Detected unloaded(unconnected) net [DesignObjSignal]
+  Violation        : Lint:494
+  Goal             : lint_rtl
+  Module           : combined_vc_sw_alloc
+  FileName         : ./../../rtl/src_noc/./combined_vc_sw_alloc.sv
+  LineNumber       : 92
+  Statement        :         assign assigned_ovc_not_full_all[i] = ivc_info[C_PORT][i%V].assigned_ovc_not_full;
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/router_ref/vsa/assigned_ovc_not_full_all[1]
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedNet-ML
+  Description      : Detected unloaded(unconnected) net [DesignObjSignal]
+  Violation        : Lint:504
+  Goal             : lint_rtl
+  Module           : router_top
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 104
+  Statement        :     flit_chanel_t ss_flit_chanel [P-1 : 0]; //flit  bypass link goes to straight port
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[1].the_router/ss_flit_chanel[1].congestion[0]
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedNet-ML
+  Description      : Detected unloaded(unconnected) net [DesignObjSignal]
+  Violation        : Lint:510
+  Goal             : lint_rtl
+  Module           : router_top
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 104
+  Statement        :     flit_chanel_t ss_flit_chanel [P-1 : 0]; //flit  bypass link goes to straight port
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[1].the_router/ss_flit_chanel[2].congestion[2]
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedNet-ML
+  Description      : Detected unloaded(unconnected) net [DesignObjSignal]
+  Violation        : Lint:493
+  Goal             : lint_rtl
+  Module           : combined_vc_sw_alloc
+  FileName         : ./../../rtl/src_noc/./combined_vc_sw_alloc.sv
+  LineNumber       : 92
+  Statement        :         assign assigned_ovc_not_full_all[i] = ivc_info[C_PORT][i%V].assigned_ovc_not_full;
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/router_ref/vsa/assigned_ovc_not_full_all[0]
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedNet-ML
+  Description      : Detected unloaded(unconnected) net [DesignObjSignal]
+  Violation        : Lint:517
+  Goal             : lint_rtl
+  Module           : router_top
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 104
+  Statement        :     flit_chanel_t ss_flit_chanel [P-1 : 0]; //flit  bypass link goes to straight port
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[2].the_router/ss_flit_chanel[2].congestion[1]
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedNet-ML
+  Description      : Detected unloaded(unconnected) net [DesignObjSignal]
+  Violation        : Lint:506
+  Goal             : lint_rtl
+  Module           : router_top
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 104
+  Statement        :     flit_chanel_t ss_flit_chanel [P-1 : 0]; //flit  bypass link goes to straight port
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[1].the_router/ss_flit_chanel[1].congestion[2]
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedNet-ML
+  Description      : Detected unloaded(unconnected) net [DesignObjSignal]
+  Violation        : Lint:485
+  Goal             : lint_rtl
+  Module           : vc_alloc_request_gen
+  FileName         : ./../../rtl/src_noc/./inout_ports.sv
+  LineNumber       : 499
+  Statement        :             assign dest_port_encoded_all [(i*V+j+1)*DSTPw-1  :  (i*V+j)*DSTPw]=ivc_info[i][j].dest_port_encoded;
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/router_ref/the_inout_ports/vc_alloc_req_gen/dest_port_encoded_all[1]
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedNet-ML
+  Description      : Detected unloaded(unconnected) net [DesignObjSignal]
+  Violation        : Lint:487
+  Goal             : lint_rtl
+  Module           : vc_alloc_request_gen
+  FileName         : ./../../rtl/src_noc/./inout_ports.sv
+  LineNumber       : 499
+  Statement        :             assign dest_port_encoded_all [(i*V+j+1)*DSTPw-1  :  (i*V+j)*DSTPw]=ivc_info[i][j].dest_port_encoded;
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/router_ref/the_inout_ports/vc_alloc_req_gen/dest_port_encoded_all[3]
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedNet-ML
+  Description      : Detected unloaded(unconnected) net [DesignObjSignal]
+  Violation        : Lint:486
+  Goal             : lint_rtl
+  Module           : vc_alloc_request_gen
+  FileName         : ./../../rtl/src_noc/./inout_ports.sv
+  LineNumber       : 499
+  Statement        :             assign dest_port_encoded_all [(i*V+j+1)*DSTPw-1  :  (i*V+j)*DSTPw]=ivc_info[i][j].dest_port_encoded;
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/router_ref/the_inout_ports/vc_alloc_req_gen/dest_port_encoded_all[2]
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedNet-ML
+  Description      : Detected unloaded(unconnected) net [DesignObjSignal]
+  Violation        : Lint:477
+  Goal             : lint_rtl
+  Module           : router_top
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 104
+  Statement        :     flit_chanel_t ss_flit_chanel [P-1 : 0]; //flit  bypass link goes to straight port
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/ss_flit_chanel[2].congestion[1]
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedNet-ML
+  Description      : Detected unloaded(unconnected) net [DesignObjSignal]
+  Violation        : Lint:478
+  Goal             : lint_rtl
+  Module           : router_top
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 104
+  Statement        :     flit_chanel_t ss_flit_chanel [P-1 : 0]; //flit  bypass link goes to straight port
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/ss_flit_chanel[2].congestion[2]
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedNet-ML
+  Description      : Detected unloaded(unconnected) net [DesignObjSignal]
+  Violation        : Lint:498
+  Goal             : lint_rtl
+  Module           : combined_vc_sw_alloc
+  FileName         : ./../../rtl/src_noc/./combined_vc_sw_alloc.sv
+  LineNumber       : 91
+  Statement        :         assign ivc_request_all[i] = ivc_info[C_PORT][i%V].ivc_req;
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/router_ref/vsa/ivc_request_all[2]
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedNet-ML
+  Description      : Detected unloaded(unconnected) net [DesignObjSignal]
+  Violation        : Lint:514
+  Goal             : lint_rtl
+  Module           : router_top
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 104
+  Statement        :     flit_chanel_t ss_flit_chanel [P-1 : 0]; //flit  bypass link goes to straight port
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[2].the_router/ss_flit_chanel[1].congestion[2]
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedNet-ML
+  Description      : Detected unloaded(unconnected) net [DesignObjSignal]
+  Violation        : Lint:489
+  Goal             : lint_rtl
+  Module           : vc_alloc_request_gen
+  FileName         : ./../../rtl/src_noc/./inout_ports.sv
+  LineNumber       : 499
+  Statement        :             assign dest_port_encoded_all [(i*V+j+1)*DSTPw-1  :  (i*V+j)*DSTPw]=ivc_info[i][j].dest_port_encoded;
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/router_ref/the_inout_ports/vc_alloc_req_gen/dest_port_encoded_all[5]
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedNet-ML
+  Description      : Detected unloaded(unconnected) net [DesignObjSignal]
+  Violation        : Lint:481
+  Goal             : lint_rtl
+  Module           : fwft_fifo
+  FileName         : ./../../rtl/src_noc/./flit_buffer.sv
+  LineNumber       : 631
+  Statement        :         assign depth_2 = depth - 2;
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/router_ref/the_inout_ports/the_input_port/Port_[0].the_input_queue_per_port/V_[0].smart_.dest_e_addr_fifo/mwb2.depth_2[3]
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedNet-ML
+  Description      : Detected unloaded(unconnected) net [DesignObjSignal]
+  Violation        : Lint:522
+  Goal             : lint_rtl
+  Module           : router_top
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 104
+  Statement        :     flit_chanel_t ss_flit_chanel [P-1 : 0]; //flit  bypass link goes to straight port
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[3].the_router/ss_flit_chanel[1].congestion[2]
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedNet-ML
+  Description      : Detected unloaded(unconnected) net [DesignObjSignal]
+  Violation        : Lint:490
+  Goal             : lint_rtl
+  Module           : vc_alloc_request_gen
+  FileName         : ./../../rtl/src_noc/./inout_ports.sv
+  LineNumber       : 495
+  Statement        :         assign non_vsa_ivc_num_getting_ovc_grant_all [(i+1)*V-1 : i*V] = ssa_ctrl_in[i].ivc_num_getting_ovc_grant | smart_ctrl_in[i].ivc_num_getting_ovc_grant;
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/router_ref/the_inout_ports/vc_alloc_req_gen/non_vsa_ivc_num_getting_ovc_grant_all[0]
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedNet-ML
+  Description      : Detected unloaded(unconnected) net [DesignObjSignal]
+  Violation        : Lint:519
+  Goal             : lint_rtl
+  Module           : router_top
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 104
+  Statement        :     flit_chanel_t ss_flit_chanel [P-1 : 0]; //flit  bypass link goes to straight port
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[2].the_router/ss_flit_chanel[2].credit[0]
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedNet-ML
+  Description      : Detected unloaded(unconnected) net [DesignObjSignal]
+  Violation        : Lint:503
+  Goal             : lint_rtl
+  Module           : smart_bypass_chanels
+  FileName         : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber       : 349
+  Statement        :         assign ivc_forwardable[i] =  (IS_SINGLE_FLIT)?  {V{1'b1}} :~iport_info[i].ivc_req;
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/smart.smart_bypass/ivc_forwardable[0][0]
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedNet-ML
+  Description      : Detected unloaded(unconnected) net [DesignObjSignal]
+  Violation        : Lint:509
+  Goal             : lint_rtl
+  Module           : router_top
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 104
+  Statement        :     flit_chanel_t ss_flit_chanel [P-1 : 0]; //flit  bypass link goes to straight port
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[1].the_router/ss_flit_chanel[2].congestion[1]
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedNet-ML
+  Description      : Detected unloaded(unconnected) net [DesignObjSignal]
+  Violation        : Lint:507
+  Goal             : lint_rtl
+  Module           : router_top
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 104
+  Statement        :     flit_chanel_t ss_flit_chanel [P-1 : 0]; //flit  bypass link goes to straight port
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[1].the_router/ss_flit_chanel[1].credit[0]
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedNet-ML
+  Description      : Detected unloaded(unconnected) net [DesignObjSignal]
+  Violation        : Lint:502
+  Goal             : lint_rtl
+  Module           : smart_bypass_chanels
+  FileName         : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber       : 355
+  Statement        :             assign outport_is_granted[i] = oport_info[i].any_ovc_granted;
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/smart.smart_bypass/outport_is_granted[0]
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedNet-ML
+  Description      : Detected unloaded(unconnected) net [DesignObjSignal]
+  Violation        : Lint:512
+  Goal             : lint_rtl
+  Module           : router_top
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 104
+  Statement        :     flit_chanel_t ss_flit_chanel [P-1 : 0]; //flit  bypass link goes to straight port
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[2].the_router/ss_flit_chanel[1].congestion[0]
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedNet-ML
+  Description      : Detected unloaded(unconnected) net [DesignObjSignal]
+  Violation        : Lint:523
+  Goal             : lint_rtl
+  Module           : router_top
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 104
+  Statement        :     flit_chanel_t ss_flit_chanel [P-1 : 0]; //flit  bypass link goes to straight port
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[3].the_router/ss_flit_chanel[1].credit[0]
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedNet-ML
+  Description      : Detected unloaded(unconnected) net [DesignObjSignal]
+  Violation        : Lint:488
+  Goal             : lint_rtl
+  Module           : vc_alloc_request_gen
+  FileName         : ./../../rtl/src_noc/./inout_ports.sv
+  LineNumber       : 499
+  Statement        :             assign dest_port_encoded_all [(i*V+j+1)*DSTPw-1  :  (i*V+j)*DSTPw]=ivc_info[i][j].dest_port_encoded;
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/router_ref/the_inout_ports/vc_alloc_req_gen/dest_port_encoded_all[4]
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedNet-ML
+  Description      : Detected unloaded(unconnected) net [DesignObjSignal]
+  Violation        : Lint:483
+  Goal             : lint_rtl
+  Module           : fwft_fifo
+  FileName         : ./../../rtl/src_noc/./flit_buffer.sv
+  LineNumber       : 631
+  Statement        :         assign depth_2 = depth - 2;
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/router_ref/the_inout_ports/the_input_port/Port_[1].the_input_queue_per_port/V_[0].smart_.dest_e_addr_fifo/mwb2.depth_2[1]
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedNet-ML
+  Description      : Detected unloaded(unconnected) net [DesignObjSignal]
+  Violation        : Lint:508
+  Goal             : lint_rtl
+  Module           : router_top
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 104
+  Statement        :     flit_chanel_t ss_flit_chanel [P-1 : 0]; //flit  bypass link goes to straight port
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[1].the_router/ss_flit_chanel[2].congestion[0]
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedNet-ML
+  Description      : Detected unloaded(unconnected) net [DesignObjSignal]
+  Violation        : Lint:495
+  Goal             : lint_rtl
+  Module           : combined_vc_sw_alloc
+  FileName         : ./../../rtl/src_noc/./combined_vc_sw_alloc.sv
+  LineNumber       : 92
+  Statement        :         assign assigned_ovc_not_full_all[i] = ivc_info[C_PORT][i%V].assigned_ovc_not_full;
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/router_ref/vsa/assigned_ovc_not_full_all[2]
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedNet-ML
+  Description      : Detected unloaded(unconnected) net [DesignObjSignal]
+  Violation        : Lint:491
+  Goal             : lint_rtl
+  Module           : vc_alloc_request_gen
+  FileName         : ./../../rtl/src_noc/./inout_ports.sv
+  LineNumber       : 495
+  Statement        :         assign non_vsa_ivc_num_getting_ovc_grant_all [(i+1)*V-1 : i*V] = ssa_ctrl_in[i].ivc_num_getting_ovc_grant | smart_ctrl_in[i].ivc_num_getting_ovc_grant;
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/router_ref/the_inout_ports/vc_alloc_req_gen/non_vsa_ivc_num_getting_ovc_grant_all[1]
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedNet-ML
+  Description      : Detected unloaded(unconnected) net [DesignObjSignal]
+  Violation        : Lint:484
+  Goal             : lint_rtl
+  Module           : vc_alloc_request_gen
+  FileName         : ./../../rtl/src_noc/./inout_ports.sv
+  LineNumber       : 499
+  Statement        :             assign dest_port_encoded_all [(i*V+j+1)*DSTPw-1  :  (i*V+j)*DSTPw]=ivc_info[i][j].dest_port_encoded;
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/router_ref/the_inout_ports/vc_alloc_req_gen/dest_port_encoded_all[0]
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedNet-ML
+  Description      : Detected unloaded(unconnected) net [DesignObjSignal]
+  Violation        : Lint:511
+  Goal             : lint_rtl
+  Module           : router_top
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 104
+  Statement        :     flit_chanel_t ss_flit_chanel [P-1 : 0]; //flit  bypass link goes to straight port
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[1].the_router/ss_flit_chanel[2].credit[0]
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedNet-ML
+  Description      : Detected unloaded(unconnected) net [DesignObjSignal]
+  Violation        : Lint:515
+  Goal             : lint_rtl
+  Module           : router_top
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 104
+  Statement        :     flit_chanel_t ss_flit_chanel [P-1 : 0]; //flit  bypass link goes to straight port
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[2].the_router/ss_flit_chanel[1].credit[0]
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedNet-ML
+  Description      : Detected unloaded(unconnected) net [DesignObjSignal]
+  Violation        : Lint:513
+  Goal             : lint_rtl
+  Module           : router_top
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 104
+  Statement        :     flit_chanel_t ss_flit_chanel [P-1 : 0]; //flit  bypass link goes to straight port
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[2].the_router/ss_flit_chanel[1].congestion[1]
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedNet-ML
+  Description      : Detected unloaded(unconnected) net [DesignObjSignal]
+  Violation        : Lint:480
+  Goal             : lint_rtl
+  Module           : flit_buffer
+  FileName         : ./../../rtl/src_noc/./flit_buffer.sv
+  LineNumber       : 128
+  Statement        :         assign {flgs_in,vc_in,flit_rest_in}=din;
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/router_ref/the_inout_ports/the_input_port/Port_[0].the_input_queue_per_port/the_flit_buffer/vc_in[0]
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedNet-ML
+  Description      : Detected unloaded(unconnected) net [DesignObjSignal]
+  Violation        : Lint:501
+  Goal             : lint_rtl
+  Module           : combined_vc_sw_alloc
+  FileName         : ./../../rtl/src_noc/./combined_vc_sw_alloc.sv
+  LineNumber       : 93
+  Statement        :         assign ovc_is_assigned_all[i] = ivc_info[C_PORT][i%V].ovc_is_assigned;
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/router_ref/vsa/ovc_is_assigned_all[2]
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedNet-ML
+  Description      : Detected unloaded(unconnected) net [DesignObjSignal]
+  Violation        : Lint:482
+  Goal             : lint_rtl
+  Module           : flit_buffer
+  FileName         : ./../../rtl/src_noc/./flit_buffer.sv
+  LineNumber       : 128
+  Statement        :         assign {flgs_in,vc_in,flit_rest_in}=din;
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/router_ref/the_inout_ports/the_input_port/Port_[1].the_input_queue_per_port/the_flit_buffer/vc_in[0]
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedNet-ML
+  Description      : Detected unloaded(unconnected) net [DesignObjSignal]
+  Violation        : Lint:496
+  Goal             : lint_rtl
+  Module           : combined_vc_sw_alloc
+  FileName         : ./../../rtl/src_noc/./combined_vc_sw_alloc.sv
+  LineNumber       : 91
+  Statement        :         assign ivc_request_all[i] = ivc_info[C_PORT][i%V].ivc_req;
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/router_ref/vsa/ivc_request_all[0]
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedNet-ML
+  Description      : Detected unloaded(unconnected) net [DesignObjSignal]
+  Violation        : Lint:492
+  Goal             : lint_rtl
+  Module           : vc_alloc_request_gen
+  FileName         : ./../../rtl/src_noc/./inout_ports.sv
+  LineNumber       : 495
+  Statement        :         assign non_vsa_ivc_num_getting_ovc_grant_all [(i+1)*V-1 : i*V] = ssa_ctrl_in[i].ivc_num_getting_ovc_grant | smart_ctrl_in[i].ivc_num_getting_ovc_grant;
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/router_ref/the_inout_ports/vc_alloc_req_gen/non_vsa_ivc_num_getting_ovc_grant_all[2]
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedNet-ML
+  Description      : Detected unloaded(unconnected) net [DesignObjSignal]
+  Violation        : Lint:521
+  Goal             : lint_rtl
+  Module           : router_top
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 104
+  Statement        :     flit_chanel_t ss_flit_chanel [P-1 : 0]; //flit  bypass link goes to straight port
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[3].the_router/ss_flit_chanel[1].congestion[1]
+
+  -----------------------------------------------------------------------------
+  UnloadedOutTerm-ML  (749 warnings/0 waived)
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedOutTerm-ML
+  Description      : Detected unloaded(unconnected) output terminal [DesignObjSignal] ([String2])
+  Violation        : Lint:2063
+  Goal             : lint_rtl
+  Module           : mesh_torus_noc_top
+  FileName         : ./../../rtl/src_noc/./mesh_torus_noc_top.sv
+  LineNumber       : 70
+  Statement        :             ) the_router (
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[3].the_router/chan_out[1].flit_chanel.flit.payload[11]
+  String1          : 
+  String2          : Connected to floating net 'router_chan_out[3][1].flit_chanel.flit.payload[11]'
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedOutTerm-ML
+  Description      : Detected unloaded(unconnected) output terminal [DesignObjSignal] ([String2])
+  Violation        : Lint:1993
+  Goal             : lint_rtl
+  Module           : router_two_stage
+  FileName         : ./../../rtl/src_noc/./router_two_stage.sv
+  LineNumber       : 269
+  Statement        :     ) the_inout_ports (
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[2].the_router/router_ref/the_inout_ports/oports_weight_all[0]
+  String1          : 
+  String2          : Connected to floating net 'oports_weight_all[0]'
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedOutTerm-ML
+  Description      : Detected unloaded(unconnected) output terminal [DesignObjSignal] ([String2])
+  Violation        : Lint:1595
+  Goal             : lint_rtl
+  Module           : input_queue_per_port
+  FileName         : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber       : 719
+  Statement        :             ) lk_dest_fifo (
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[1].the_router/router_ref/the_inout_ports/the_input_port/Port_[1].the_input_queue_per_port/V_[0].unicast.lk_dest_fifo/nearly_full
+  String1          :  
+  String2          : Left Open
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedOutTerm-ML
+  Description      : Detected unloaded(unconnected) output terminal [DesignObjSignal] ([String2])
+  Violation        : Lint:1441
+  Goal             : lint_rtl
+  Module           : router_top
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 110
+  Statement        :     )router_ref (
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/router_ref/ovc_info[0][0].avalable
+  String1          : 
+  String2          : Connected to floating net 'ovc_info[0][0].avalable'
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedOutTerm-ML
+  Description      : Detected unloaded(unconnected) output terminal [DesignObjSignal] ([String2])
+  Violation        : Lint:2150
+  Goal             : lint_rtl
+  Module           : router_two_stage
+  FileName         : ./../../rtl/src_noc/./router_two_stage.sv
+  LineNumber       : 269
+  Statement        :     ) the_inout_ports (
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[3].the_router/router_ref/the_inout_ports/oports_weight_all[9]
+  String1          : 
+  String2          : Connected to floating net 'oports_weight_all[9]'
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedOutTerm-ML
+  Description      : Detected unloaded(unconnected) output terminal [DesignObjSignal] ([String2])
+  Violation        : Lint:1520
+  Goal             : lint_rtl
+  Module           : input_queue_per_port
+  FileName         : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber       : 625
+  Statement        :             ) dest_e_addr_fifo (
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[1].the_router/router_ref/the_inout_ports/the_input_port/Port_[0].the_input_queue_per_port/V_[0].smart_.dest_e_addr_fifo/recieve_more_than_0
+  String1          :  
+  String2          : Left Open
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedOutTerm-ML
+  Description      : Detected unloaded(unconnected) output terminal [DesignObjSignal] ([String2])
+  Violation        : Lint:1937
+  Goal             : lint_rtl
+  Module           : router_two_stage
+  FileName         : ./../../rtl/src_noc/./router_two_stage.sv
+  LineNumber       : 269
+  Statement        :     ) the_inout_ports (
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[1].the_router/router_ref/the_inout_ports/oports_weight_all[6]
+  String1          : 
+  String2          : Connected to floating net 'oports_weight_all[6]'
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedOutTerm-ML
+  Description      : Detected unloaded(unconnected) output terminal [DesignObjSignal] ([String2])
+  Violation        : Lint:1524
+  Goal             : lint_rtl
+  Module           : input_queue_per_port
+  FileName         : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber       : 719
+  Statement        :             ) lk_dest_fifo (
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[1].the_router/router_ref/the_inout_ports/the_input_port/Port_[0].the_input_queue_per_port/V_[0].unicast.lk_dest_fifo/recieve_more_than_0
+  String1          :  
+  String2          : Left Open
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedOutTerm-ML
+  Description      : Detected unloaded(unconnected) output terminal [DesignObjSignal] ([String2])
+  Violation        : Lint:2030
+  Goal             : lint_rtl
+  Module           : inout_ports
+  FileName         : ./../../rtl/src_noc/./inout_ports.sv
+  LineNumber       : 175
+  Statement        :     ) the_input_port (
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[2].the_router/router_ref/the_inout_ports/the_input_port/reset_ivc_all[1]
+  String1          : 
+  String2          : Connected to floating net 'reset_ivc_all[1]'
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedOutTerm-ML
+  Description      : Detected unloaded(unconnected) output terminal [DesignObjSignal] ([String2])
+  Violation        : Lint:1745
+  Goal             : lint_rtl
+  Module           : mesh_torus_noc_top
+  FileName         : ./../../rtl/src_noc/./mesh_torus_noc_top.sv
+  LineNumber       : 70
+  Statement        :             ) the_router (
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/chan_out[2].flit_chanel.flit.payload[5]
+  String1          : 
+  String2          : Connected to floating net 'router_chan_out[0][2].flit_chanel.flit.payload[5]'
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedOutTerm-ML
+  Description      : Detected unloaded(unconnected) output terminal [DesignObjSignal] ([String2])
+  Violation        : Lint:1431
+  Goal             : lint_rtl
+  Module           : mesh_torus_noc_top
+  FileName         : ./../../rtl/src_noc/./mesh_torus_noc_top.sv
+  LineNumber       : 70
+  Statement        :             ) the_router (
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/chan_out[2].ctrl_chanel.endp_port
+  String1          : 
+  String2          : Connected to floating net 'router_chan_out[0][2].ctrl_chanel.endp_port'
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedOutTerm-ML
+  Description      : Detected unloaded(unconnected) output terminal [DesignObjSignal] ([String2])
+  Violation        : Lint:1785
+  Goal             : lint_rtl
+  Module           : mesh_torus_noc_top
+  FileName         : ./../../rtl/src_noc/./mesh_torus_noc_top.sv
+  LineNumber       : 70
+  Statement        :             ) the_router (
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/chan_out[2].flit_chanel.flit.payload[45]
+  String1          : 
+  String2          : Connected to floating net 'router_chan_out[0][2].flit_chanel.flit.payload[45]'
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedOutTerm-ML
+  Description      : Detected unloaded(unconnected) output terminal [DesignObjSignal] ([String2])
+  Violation        : Lint:1876
+  Goal             : lint_rtl
+  Module           : router_top
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 144
+  Statement        :         ) smart_bypass (
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/smart.smart_bypass/smart_chanel_out[0].bypassed_num[0]
+  String1          : 
+  String2          : Connected to floating net 'smart_chanel_out[0].bypassed_num[0]'
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedOutTerm-ML
+  Description      : Detected unloaded(unconnected) output terminal [DesignObjSignal] ([String2])
+  Violation        : Lint:1437
+  Goal             : lint_rtl
+  Module           : router_top
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 110
+  Statement        :     )router_ref (
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/router_ref/ovc_info[0][0].empty
+  String1          : 
+  String2          : Connected to floating net 'ovc_info[0][0].empty'
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedOutTerm-ML
+  Description      : Detected unloaded(unconnected) output terminal [DesignObjSignal] ([String2])
+  Violation        : Lint:2056
+  Goal             : lint_rtl
+  Module           : mesh_torus_noc_top
+  FileName         : ./../../rtl/src_noc/./mesh_torus_noc_top.sv
+  LineNumber       : 70
+  Statement        :             ) the_router (
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[3].the_router/chan_out[1].flit_chanel.flit.payload[4]
+  String1          : 
+  String2          : Connected to floating net 'router_chan_out[3][1].flit_chanel.flit.payload[4]'
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedOutTerm-ML
+  Description      : Detected unloaded(unconnected) output terminal [DesignObjSignal] ([String2])
+  Violation        : Lint:2024
+  Goal             : lint_rtl
+  Module           : router_two_stage
+  FileName         : ./../../rtl/src_noc/./router_two_stage.sv
+  LineNumber       : 269
+  Statement        :     ) the_inout_ports (
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[2].the_router/router_ref/the_inout_ports/oports_weight_all[31]
+  String1          : 
+  String2          : Connected to floating net 'oports_weight_all[31]'
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedOutTerm-ML
+  Description      : Detected unloaded(unconnected) output terminal [DesignObjSignal] ([String2])
+  Violation        : Lint:1459
+  Goal             : lint_rtl
+  Module           : input_queue_per_port
+  FileName         : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber       : 387
+  Statement        :     ) header_extractor (
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[1].the_router/router_ref/the_inout_ports/the_input_port/Port_[0].the_input_queue_per_port/header_extractor/tail_flg_o
+  String1          :  
+  String2          : Connected to floating net 'tail_flg_in'
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedOutTerm-ML
+  Description      : Detected unloaded(unconnected) output terminal [DesignObjSignal] ([String2])
+  Violation        : Lint:1908
+  Goal             : lint_rtl
+  Module           : router_top
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 110
+  Statement        :     )router_ref (
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[1].the_router/router_ref/ovc_info[0][0].credit[0]
+  String1          : 
+  String2          : Connected to floating net 'ovc_info[0][0].credit[0]'
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedOutTerm-ML
+  Description      : Detected unloaded(unconnected) output terminal [DesignObjSignal] ([String2])
+  Violation        : Lint:1787
+  Goal             : lint_rtl
+  Module           : mesh_torus_noc_top
+  FileName         : ./../../rtl/src_noc/./mesh_torus_noc_top.sv
+  LineNumber       : 70
+  Statement        :             ) the_router (
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/chan_out[2].flit_chanel.flit.payload[47]
+  String1          : 
+  String2          : Connected to floating net 'router_chan_out[0][2].flit_chanel.flit.payload[47]'
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedOutTerm-ML
+  Description      : Detected unloaded(unconnected) output terminal [DesignObjSignal] ([String2])
+  Violation        : Lint:1825
+  Goal             : lint_rtl
+  Module           : router_two_stage
+  FileName         : ./../../rtl/src_noc/./router_two_stage.sv
+  LineNumber       : 269
+  Statement        :     ) the_inout_ports (
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/router_ref/the_inout_ports/iport_weight_all[8]
+  String1          : 
+  String2          : Connected to floating net 'iport_weight_all[8]'
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedOutTerm-ML
+  Description      : Detected unloaded(unconnected) output terminal [DesignObjSignal] ([String2])
+  Violation        : Lint:1649
+  Goal             : lint_rtl
+  Module           : input_queue_per_port
+  FileName         : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber       : 740
+  Statement        :                 ) dest_fifo (
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[3].the_router/router_ref/the_inout_ports/the_input_port/Port_[1].the_input_queue_per_port/V_[0].unicast.dtrmn_dest.dest_fifo/recieve_more_than_1
+  String1          :  
+  String2          : Left Open
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedOutTerm-ML
+  Description      : Detected unloaded(unconnected) output terminal [DesignObjSignal] ([String2])
+  Violation        : Lint:2111
+  Goal             : lint_rtl
+  Module           : mesh_torus_noc_top
+  FileName         : ./../../rtl/src_noc/./mesh_torus_noc_top.sv
+  LineNumber       : 70
+  Statement        :             ) the_router (
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[3].the_router/chan_out[1].flit_chanel.flit.payload[59]
+  String1          : 
+  String2          : Connected to floating net 'router_chan_out[3][1].flit_chanel.flit.payload[59]'
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedOutTerm-ML
+  Description      : Detected unloaded(unconnected) output terminal [DesignObjSignal] ([String2])
+  Violation        : Lint:2057
+  Goal             : lint_rtl
+  Module           : mesh_torus_noc_top
+  FileName         : ./../../rtl/src_noc/./mesh_torus_noc_top.sv
+  LineNumber       : 70
+  Statement        :             ) the_router (
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[3].the_router/chan_out[1].flit_chanel.flit.payload[5]
+  String1          : 
+  String2          : Connected to floating net 'router_chan_out[3][1].flit_chanel.flit.payload[5]'
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedOutTerm-ML
+  Description      : Detected unloaded(unconnected) output terminal [DesignObjSignal] ([String2])
+  Violation        : Lint:1435
+  Goal             : lint_rtl
+  Module           : mesh_torus_noc_top
+  FileName         : ./../../rtl/src_noc/./mesh_torus_noc_top.sv
+  LineNumber       : 70
+  Statement        :             ) the_router (
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/chan_out[2].flit_chanel.flit.hdr_flag
+  String1          : 
+  String2          : Connected to floating net 'router_chan_out[0][2].flit_chanel.flit.hdr_flag'
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedOutTerm-ML
+  Description      : Detected unloaded(unconnected) output terminal [DesignObjSignal] ([String2])
+  Violation        : Lint:1494
+  Goal             : lint_rtl
+  Module           : input_queue_per_port
+  FileName         : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber       : 387
+  Statement        :     ) header_extractor (
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[3].the_router/router_ref/the_inout_ports/the_input_port/Port_[1].the_input_queue_per_port/header_extractor/tail_flg_o
+  String1          :  
+  String2          : Connected to floating net 'tail_flg_in'
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedOutTerm-ML
+  Description      : Detected unloaded(unconnected) output terminal [DesignObjSignal] ([String2])
+  Violation        : Lint:1529
+  Goal             : lint_rtl
+  Module           : input_queue_per_port
+  FileName         : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber       : 740
+  Statement        :                 ) dest_fifo (
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[1].the_router/router_ref/the_inout_ports/the_input_port/Port_[0].the_input_queue_per_port/V_[0].unicast.dtrmn_dest.dest_fifo/recieve_more_than_1
+  String1          :  
+  String2          : Left Open
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedOutTerm-ML
+  Description      : Detected unloaded(unconnected) output terminal [DesignObjSignal] ([String2])
+  Violation        : Lint:1508
+  Goal             : lint_rtl
+  Module           : input_queue_per_port
+  FileName         : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber       : 625
+  Statement        :             ) dest_e_addr_fifo (
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/router_ref/the_inout_ports/the_input_port/Port_[0].the_input_queue_per_port/V_[0].smart_.dest_e_addr_fifo/recieve_more_than_0
+  String1          :  
+  String2          : Left Open
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedOutTerm-ML
+  Description      : Detected unloaded(unconnected) output terminal [DesignObjSignal] ([String2])
+  Violation        : Lint:1730
+  Goal             : lint_rtl
+  Module           : mesh_torus_noc_top
+  FileName         : ./../../rtl/src_noc/./mesh_torus_noc_top.sv
+  LineNumber       : 70
+  Statement        :             ) the_router (
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/chan_out[2].smart_chanel.bypassed_num[1]
+  String1          : 
+  String2          : Connected to floating net 'router_chan_out[0][2].smart_chanel.bypassed_num[1]'
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedOutTerm-ML
+  Description      : Detected unloaded(unconnected) output terminal [DesignObjSignal] ([String2])
+  Violation        : Lint:1592
+  Goal             : lint_rtl
+  Module           : input_queue_per_port
+  FileName         : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber       : 625
+  Statement        :             ) dest_e_addr_fifo (
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[1].the_router/router_ref/the_inout_ports/the_input_port/Port_[1].the_input_queue_per_port/V_[0].smart_.dest_e_addr_fifo/recieve_more_than_0
+  String1          :  
+  String2          : Left Open
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedOutTerm-ML
+  Description      : Detected unloaded(unconnected) output terminal [DesignObjSignal] ([String2])
+  Violation        : Lint:2044
+  Goal             : lint_rtl
+  Module           : mesh_torus_noc_top
+  FileName         : ./../../rtl/src_noc/./mesh_torus_noc_top.sv
+  LineNumber       : 70
+  Statement        :             ) the_router (
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[3].the_router/chan_out[1].smart_chanel.dest_e_addr[1]
+  String1          : 
+  String2          : Connected to floating net 'router_chan_out[3][1].smart_chanel.dest_e_addr[1]'
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedOutTerm-ML
+  Description      : Detected unloaded(unconnected) output terminal [DesignObjSignal] ([String2])
+  Violation        : Lint:1923
+  Goal             : lint_rtl
+  Module           : router_two_stage
+  FileName         : ./../../rtl/src_noc/./router_two_stage.sv
+  LineNumber       : 269
+  Statement        :     ) the_inout_ports (
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[1].the_router/router_ref/the_inout_ports/iport_weight_all[4]
+  String1          : 
+  String2          : Connected to floating net 'iport_weight_all[4]'
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedOutTerm-ML
+  Description      : Detected unloaded(unconnected) output terminal [DesignObjSignal] ([String2])
+  Violation        : Lint:1839
+  Goal             : lint_rtl
+  Module           : router_two_stage
+  FileName         : ./../../rtl/src_noc/./router_two_stage.sv
+  LineNumber       : 269
+  Statement        :     ) the_inout_ports (
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/router_ref/the_inout_ports/oports_weight_all[10]
+  String1          : 
+  String2          : Connected to floating net 'oports_weight_all[10]'
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedOutTerm-ML
+  Description      : Detected unloaded(unconnected) output terminal [DesignObjSignal] ([String2])
+  Violation        : Lint:2119
+  Goal             : lint_rtl
+  Module           : router_top
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 110
+  Statement        :     )router_ref (
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[3].the_router/router_ref/ovc_info[0][0].credit[1]
+  String1          : 
+  String2          : Connected to floating net 'ovc_info[0][0].credit[1]'
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedOutTerm-ML
+  Description      : Detected unloaded(unconnected) output terminal [DesignObjSignal] ([String2])
+  Violation        : Lint:1735
+  Goal             : lint_rtl
+  Module           : mesh_torus_noc_top
+  FileName         : ./../../rtl/src_noc/./mesh_torus_noc_top.sv
+  LineNumber       : 70
+  Statement        :             ) the_router (
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/chan_out[2].smart_chanel.requests[1]
+  String1          : 
+  String2          : Connected to floating net 'router_chan_out[0][2].smart_chanel.requests[1]'
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedOutTerm-ML
+  Description      : Detected unloaded(unconnected) output terminal [DesignObjSignal] ([String2])
+  Violation        : Lint:1467
+  Goal             : lint_rtl
+  Module           : input_queue_per_port
+  FileName         : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber       : 387
+  Statement        :     ) header_extractor (
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[1].the_router/router_ref/the_inout_ports/the_input_port/Port_[2].the_input_queue_per_port/header_extractor/class_o[0]
+  String1          :  
+  String2          : Connected to floating net 'class_in'
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedOutTerm-ML
+  Description      : Detected unloaded(unconnected) output terminal [DesignObjSignal] ([String2])
+  Violation        : Lint:1977
+  Goal             : lint_rtl
+  Module           : router_two_stage
+  FileName         : ./../../rtl/src_noc/./router_two_stage.sv
+  LineNumber       : 269
+  Statement        :     ) the_inout_ports (
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[2].the_router/router_ref/the_inout_ports/ovc_is_assigned_all[2]
+  String1          : 
+  String2          : Connected to floating net 'ovc_is_assigned_all[2]'
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedOutTerm-ML
+  Description      : Detected unloaded(unconnected) output terminal [DesignObjSignal] ([String2])
+  Violation        : Lint:2020
+  Goal             : lint_rtl
+  Module           : router_two_stage
+  FileName         : ./../../rtl/src_noc/./router_two_stage.sv
+  LineNumber       : 269
+  Statement        :     ) the_inout_ports (
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[2].the_router/router_ref/the_inout_ports/oports_weight_all[27]
+  String1          : 
+  String2          : Connected to floating net 'oports_weight_all[27]'
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedOutTerm-ML
+  Description      : Detected unloaded(unconnected) output terminal [DesignObjSignal] ([String2])
+  Violation        : Lint:1813
+  Goal             : lint_rtl
+  Module           : router_two_stage
+  FileName         : ./../../rtl/src_noc/./router_two_stage.sv
+  LineNumber       : 269
+  Statement        :     ) the_inout_ports (
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/router_ref/the_inout_ports/ovc_is_assigned_all[2]
+  String1          : 
+  String2          : Connected to floating net 'ovc_is_assigned_all[2]'
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedOutTerm-ML
+  Description      : Detected unloaded(unconnected) output terminal [DesignObjSignal] ([String2])
+  Violation        : Lint:1493
+  Goal             : lint_rtl
+  Module           : input_queue_per_port
+  FileName         : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber       : 387
+  Statement        :     ) header_extractor (
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[3].the_router/router_ref/the_inout_ports/the_input_port/Port_[1].the_input_queue_per_port/header_extractor/data_o[0]
+  String1          :  
+  String2          : Left Open
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedOutTerm-ML
+  Description      : Detected unloaded(unconnected) output terminal [DesignObjSignal] ([String2])
+  Violation        : Lint:2108
+  Goal             : lint_rtl
+  Module           : mesh_torus_noc_top
+  FileName         : ./../../rtl/src_noc/./mesh_torus_noc_top.sv
+  LineNumber       : 70
+  Statement        :             ) the_router (
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[3].the_router/chan_out[1].flit_chanel.flit.payload[56]
+  String1          : 
+  String2          : Connected to floating net 'router_chan_out[3][1].flit_chanel.flit.payload[56]'
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedOutTerm-ML
+  Description      : Detected unloaded(unconnected) output terminal [DesignObjSignal] ([String2])
+  Violation        : Lint:2012
+  Goal             : lint_rtl
+  Module           : router_two_stage
+  FileName         : ./../../rtl/src_noc/./router_two_stage.sv
+  LineNumber       : 269
+  Statement        :     ) the_inout_ports (
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[2].the_router/router_ref/the_inout_ports/oports_weight_all[19]
+  String1          : 
+  String2          : Connected to floating net 'oports_weight_all[19]'
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedOutTerm-ML
+  Description      : Detected unloaded(unconnected) output terminal [DesignObjSignal] ([String2])
+  Violation        : Lint:1546
+  Goal             : lint_rtl
+  Module           : input_queue_per_port
+  FileName         : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber       : 719
+  Statement        :             ) lk_dest_fifo (
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[3].the_router/router_ref/the_inout_ports/the_input_port/Port_[0].the_input_queue_per_port/V_[0].unicast.lk_dest_fifo/full
+  String1          :  
+  String2          : Left Open
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedOutTerm-ML
+  Description      : Detected unloaded(unconnected) output terminal [DesignObjSignal] ([String2])
+  Violation        : Lint:1882
+  Goal             : lint_rtl
+  Module           : router_top
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 144
+  Statement        :         ) smart_bypass (
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/smart.smart_bypass/smart_chanel_out[0].requests[1]
+  String1          : 
+  String2          : Connected to floating net 'smart_chanel_out[0].requests[1]'
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedOutTerm-ML
+  Description      : Detected unloaded(unconnected) output terminal [DesignObjSignal] ([String2])
+  Violation        : Lint:2023
+  Goal             : lint_rtl
+  Module           : router_two_stage
+  FileName         : ./../../rtl/src_noc/./router_two_stage.sv
+  LineNumber       : 269
+  Statement        :     ) the_inout_ports (
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[2].the_router/router_ref/the_inout_ports/oports_weight_all[30]
+  String1          : 
+  String2          : Connected to floating net 'oports_weight_all[30]'
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedOutTerm-ML
+  Description      : Detected unloaded(unconnected) output terminal [DesignObjSignal] ([String2])
+  Violation        : Lint:2084
+  Goal             : lint_rtl
+  Module           : mesh_torus_noc_top
+  FileName         : ./../../rtl/src_noc/./mesh_torus_noc_top.sv
+  LineNumber       : 70
+  Statement        :             ) the_router (
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[3].the_router/chan_out[1].flit_chanel.flit.payload[32]
+  String1          : 
+  String2          : Connected to floating net 'router_chan_out[3][1].flit_chanel.flit.payload[32]'
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedOutTerm-ML
+  Description      : Detected unloaded(unconnected) output terminal [DesignObjSignal] ([String2])
+  Violation        : Lint:1752
+  Goal             : lint_rtl
+  Module           : mesh_torus_noc_top
+  FileName         : ./../../rtl/src_noc/./mesh_torus_noc_top.sv
+  LineNumber       : 70
+  Statement        :             ) the_router (
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/chan_out[2].flit_chanel.flit.payload[12]
+  String1          : 
+  String2          : Connected to floating net 'router_chan_out[0][2].flit_chanel.flit.payload[12]'
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedOutTerm-ML
+  Description      : Detected unloaded(unconnected) output terminal [DesignObjSignal] ([String2])
+  Violation        : Lint:1909
+  Goal             : lint_rtl
+  Module           : router_top
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 110
+  Statement        :     )router_ref (
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[1].the_router/router_ref/ovc_info[0][0].credit[1]
+  String1          : 
+  String2          : Connected to floating net 'ovc_info[0][0].credit[1]'
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedOutTerm-ML
+  Description      : Detected unloaded(unconnected) output terminal [DesignObjSignal] ([String2])
+  Violation        : Lint:1912
+  Goal             : lint_rtl
+  Module           : router_top
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 110
+  Statement        :     )router_ref (
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[1].the_router/router_ref/ovc_info[0][0].credit[4]
+  String1          : 
+  String2          : Connected to floating net 'ovc_info[0][0].credit[4]'
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedOutTerm-ML
+  Description      : Detected unloaded(unconnected) output terminal [DesignObjSignal] ([String2])
+  Violation        : Lint:2080
+  Goal             : lint_rtl
+  Module           : mesh_torus_noc_top
+  FileName         : ./../../rtl/src_noc/./mesh_torus_noc_top.sv
+  LineNumber       : 70
+  Statement        :             ) the_router (
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[3].the_router/chan_out[1].flit_chanel.flit.payload[28]
+  String1          : 
+  String2          : Connected to floating net 'router_chan_out[3][1].flit_chanel.flit.payload[28]'
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedOutTerm-ML
+  Description      : Detected unloaded(unconnected) output terminal [DesignObjSignal] ([String2])
+  Violation        : Lint:1490
+  Goal             : lint_rtl
+  Module           : input_queue_per_port
+  FileName         : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber       : 387
+  Statement        :     ) header_extractor (
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[3].the_router/router_ref/the_inout_ports/the_input_port/Port_[0].the_input_queue_per_port/header_extractor/hdr_flg_o
+  String1          :  
+  String2          : Connected to floating net 'hdr_flg_in'
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedOutTerm-ML
+  Description      : Detected unloaded(unconnected) output terminal [DesignObjSignal] ([String2])
+  Violation        : Lint:1731
+  Goal             : lint_rtl
+  Module           : mesh_torus_noc_top
+  FileName         : ./../../rtl/src_noc/./mesh_torus_noc_top.sv
+  LineNumber       : 70
+  Statement        :             ) the_router (
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/chan_out[2].smart_chanel.dest_e_addr[0]
+  String1          : 
+  String2          : Connected to floating net 'router_chan_out[0][2].smart_chanel.dest_e_addr[0]'
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedOutTerm-ML
+  Description      : Detected unloaded(unconnected) output terminal [DesignObjSignal] ([String2])
+  Violation        : Lint:1442
+  Goal             : lint_rtl
+  Module           : input_queue_per_port
+  FileName         : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber       : 387
+  Statement        :     ) header_extractor (
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/router_ref/the_inout_ports/the_input_port/Port_[0].the_input_queue_per_port/header_extractor/class_o[0]
+  String1          :  
+  String2          : Connected to floating net 'class_in'
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedOutTerm-ML
+  Description      : Detected unloaded(unconnected) output terminal [DesignObjSignal] ([String2])
+  Violation        : Lint:2086
+  Goal             : lint_rtl
+  Module           : mesh_torus_noc_top
+  FileName         : ./../../rtl/src_noc/./mesh_torus_noc_top.sv
+  LineNumber       : 70
+  Statement        :             ) the_router (
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[3].the_router/chan_out[1].flit_chanel.flit.payload[34]
+  String1          : 
+  String2          : Connected to floating net 'router_chan_out[3][1].flit_chanel.flit.payload[34]'
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedOutTerm-ML
+  Description      : Detected unloaded(unconnected) output terminal [DesignObjSignal] ([String2])
+  Violation        : Lint:1686
+  Goal             : lint_rtl
+  Module           : router_top
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 144
+  Statement        :         ) smart_bypass (
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[2].the_router/smart.smart_bypass/smart_chanel_out[0].hdr_flit
+  String1          : 
+  String2          : Connected to floating net 'smart_chanel_out[0].hdr_flit'
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedOutTerm-ML
+  Description      : Detected unloaded(unconnected) output terminal [DesignObjSignal] ([String2])
+  Violation        : Lint:1981
+  Goal             : lint_rtl
+  Module           : router_two_stage
+  FileName         : ./../../rtl/src_noc/./router_two_stage.sv
+  LineNumber       : 269
+  Statement        :     ) the_inout_ports (
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[2].the_router/router_ref/the_inout_ports/iport_weight_all[0]
+  String1          : 
+  String2          : Connected to floating net 'iport_weight_all[0]'
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedOutTerm-ML
+  Description      : Detected unloaded(unconnected) output terminal [DesignObjSignal] ([String2])
+  Violation        : Lint:2114
+  Goal             : lint_rtl
+  Module           : mesh_torus_noc_top
+  FileName         : ./../../rtl/src_noc/./mesh_torus_noc_top.sv
+  LineNumber       : 70
+  Statement        :             ) the_router (
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[3].the_router/chan_out[1].flit_chanel.flit.payload[62]
+  String1          : 
+  String2          : Connected to floating net 'router_chan_out[3][1].flit_chanel.flit.payload[62]'
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedOutTerm-ML
+  Description      : Detected unloaded(unconnected) output terminal [DesignObjSignal] ([String2])
+  Violation        : Lint:1887
+  Goal             : lint_rtl
+  Module           : router_top
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 144
+  Statement        :         ) smart_bypass (
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[1].the_router/smart.smart_bypass/smart_chanel_out[0].dest_e_addr[1]
+  String1          : 
+  String2          : Connected to floating net 'smart_chanel_out[0].dest_e_addr[1]'
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedOutTerm-ML
+  Description      : Detected unloaded(unconnected) output terminal [DesignObjSignal] ([String2])
+  Violation        : Lint:2050
+  Goal             : lint_rtl
+  Module           : mesh_torus_noc_top
+  FileName         : ./../../rtl/src_noc/./mesh_torus_noc_top.sv
+  LineNumber       : 70
+  Statement        :             ) the_router (
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[3].the_router/chan_out[1].flit_chanel.congestion[1]
+  String1          : 
+  String2          : Connected to floating net 'router_chan_out[3][1].flit_chanel.congestion[1]'
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedOutTerm-ML
+  Description      : Detected unloaded(unconnected) output terminal [DesignObjSignal] ([String2])
+  Violation        : Lint:2055
+  Goal             : lint_rtl
+  Module           : mesh_torus_noc_top
+  FileName         : ./../../rtl/src_noc/./mesh_torus_noc_top.sv
+  LineNumber       : 70
+  Statement        :             ) the_router (
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[3].the_router/chan_out[1].flit_chanel.flit.payload[3]
+  String1          : 
+  String2          : Connected to floating net 'router_chan_out[3][1].flit_chanel.flit.payload[3]'
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedOutTerm-ML
+  Description      : Detected unloaded(unconnected) output terminal [DesignObjSignal] ([String2])
+  Violation        : Lint:1651
+  Goal             : lint_rtl
+  Module           : input_queue_per_port
+  FileName         : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber       : 625
+  Statement        :             ) dest_e_addr_fifo (
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[3].the_router/router_ref/the_inout_ports/the_input_port/Port_[2].the_input_queue_per_port/V_[0].smart_.dest_e_addr_fifo/nearly_full
+  String1          :  
+  String2          : Left Open
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedOutTerm-ML
+  Description      : Detected unloaded(unconnected) output terminal [DesignObjSignal] ([String2])
+  Violation        : Lint:2157
+  Goal             : lint_rtl
+  Module           : router_two_stage
+  FileName         : ./../../rtl/src_noc/./router_two_stage.sv
+  LineNumber       : 269
+  Statement        :     ) the_inout_ports (
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[3].the_router/router_ref/the_inout_ports/oports_weight_all[16]
+  String1          : 
+  String2          : Connected to floating net 'oports_weight_all[16]'
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedOutTerm-ML
+  Description      : Detected unloaded(unconnected) output terminal [DesignObjSignal] ([String2])
+  Violation        : Lint:1742
+  Goal             : lint_rtl
+  Module           : mesh_torus_noc_top
+  FileName         : ./../../rtl/src_noc/./mesh_torus_noc_top.sv
+  LineNumber       : 70
+  Statement        :             ) the_router (
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/chan_out[2].flit_chanel.flit.payload[2]
+  String1          : 
+  String2          : Connected to floating net 'router_chan_out[0][2].flit_chanel.flit.payload[2]'
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedOutTerm-ML
+  Description      : Detected unloaded(unconnected) output terminal [DesignObjSignal] ([String2])
+  Violation        : Lint:1801
+  Goal             : lint_rtl
+  Module           : mesh_torus_noc_top
+  FileName         : ./../../rtl/src_noc/./mesh_torus_noc_top.sv
+  LineNumber       : 70
+  Statement        :             ) the_router (
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/chan_out[2].flit_chanel.flit.payload[61]
+  String1          : 
+  String2          : Connected to floating net 'router_chan_out[0][2].flit_chanel.flit.payload[61]'
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedOutTerm-ML
+  Description      : Detected unloaded(unconnected) output terminal [DesignObjSignal] ([String2])
+  Violation        : Lint:1816
+  Goal             : lint_rtl
+  Module           : router_two_stage
+  FileName         : ./../../rtl/src_noc/./router_two_stage.sv
+  LineNumber       : 269
+  Statement        :     ) the_inout_ports (
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/router_ref/the_inout_ports/assigned_ovc_not_full_all[2]
+  String1          : 
+  String2          : Connected to floating net 'assigned_ovc_not_full_all[2]'
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedOutTerm-ML
+  Description      : Detected unloaded(unconnected) output terminal [DesignObjSignal] ([String2])
+  Violation        : Lint:1987
+  Goal             : lint_rtl
+  Module           : router_two_stage
+  FileName         : ./../../rtl/src_noc/./router_two_stage.sv
+  LineNumber       : 269
+  Statement        :     ) the_inout_ports (
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[2].the_router/router_ref/the_inout_ports/iport_weight_all[6]
+  String1          : 
+  String2          : Connected to floating net 'iport_weight_all[6]'
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedOutTerm-ML
+  Description      : Detected unloaded(unconnected) output terminal [DesignObjSignal] ([String2])
+  Violation        : Lint:2060
+  Goal             : lint_rtl
+  Module           : mesh_torus_noc_top
+  FileName         : ./../../rtl/src_noc/./mesh_torus_noc_top.sv
+  LineNumber       : 70
+  Statement        :             ) the_router (
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[3].the_router/chan_out[1].flit_chanel.flit.payload[8]
+  String1          : 
+  String2          : Connected to floating net 'router_chan_out[3][1].flit_chanel.flit.payload[8]'
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedOutTerm-ML
+  Description      : Detected unloaded(unconnected) output terminal [DesignObjSignal] ([String2])
+  Violation        : Lint:1817
+  Goal             : lint_rtl
+  Module           : router_two_stage
+  FileName         : ./../../rtl/src_noc/./router_two_stage.sv
+  LineNumber       : 269
+  Statement        :     ) the_inout_ports (
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/router_ref/the_inout_ports/iport_weight_all[0]
+  String1          : 
+  String2          : Connected to floating net 'iport_weight_all[0]'
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedOutTerm-ML
+  Description      : Detected unloaded(unconnected) output terminal [DesignObjSignal] ([String2])
+  Violation        : Lint:2142
+  Goal             : lint_rtl
+  Module           : router_two_stage
+  FileName         : ./../../rtl/src_noc/./router_two_stage.sv
+  LineNumber       : 269
+  Statement        :     ) the_inout_ports (
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[3].the_router/router_ref/the_inout_ports/oports_weight_all[1]
+  String1          : 
+  String2          : Connected to floating net 'oports_weight_all[1]'
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedOutTerm-ML
+  Description      : Detected unloaded(unconnected) output terminal [DesignObjSignal] ([String2])
+  Violation        : Lint:2112
+  Goal             : lint_rtl
+  Module           : mesh_torus_noc_top
+  FileName         : ./../../rtl/src_noc/./mesh_torus_noc_top.sv
+  LineNumber       : 70
+  Statement        :             ) the_router (
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[3].the_router/chan_out[1].flit_chanel.flit.payload[60]
+  String1          : 
+  String2          : Connected to floating net 'router_chan_out[3][1].flit_chanel.flit.payload[60]'
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedOutTerm-ML
+  Description      : Detected unloaded(unconnected) output terminal [DesignObjSignal] ([String2])
+  Violation        : Lint:1899
+  Goal             : lint_rtl
+  Module           : router_top
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 144
+  Statement        :         ) smart_bypass (
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[2].the_router/smart.smart_bypass/smart_chanel_out[0].requests[2]
+  String1          : 
+  String2          : Connected to floating net 'smart_chanel_out[0].requests[2]'
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedOutTerm-ML
+  Description      : Detected unloaded(unconnected) output terminal [DesignObjSignal] ([String2])
+  Violation        : Lint:2041
+  Goal             : lint_rtl
+  Module           : mesh_torus_noc_top
+  FileName         : ./../../rtl/src_noc/./mesh_torus_noc_top.sv
+  LineNumber       : 70
+  Statement        :             ) the_router (
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[3].the_router/chan_out[1].smart_chanel.bypassed_num[0]
+  String1          : 
+  String2          : Connected to floating net 'router_chan_out[3][1].smart_chanel.bypassed_num[0]'
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedOutTerm-ML
+  Description      : Detected unloaded(unconnected) output terminal [DesignObjSignal] ([String2])
+  Violation        : Lint:1868
+  Goal             : lint_rtl
+  Module           : check_straight_oport
+  FileName         : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber       : 407
+  Statement        :             line_ring_decode_dstport decoder(
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/smart.Port_[1].smart_en.smart_allocator/check_straight/oneD.non_local.decoder/dstport_one_hot[0]
+  String1          : 
+  String2          : Connected to floating net 'oneD.non_local.destport_one_hot[0]'
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedOutTerm-ML
+  Description      : Detected unloaded(unconnected) output terminal [DesignObjSignal] ([String2])
+  Violation        : Lint:1826
+  Goal             : lint_rtl
+  Module           : router_two_stage
+  FileName         : ./../../rtl/src_noc/./router_two_stage.sv
+  LineNumber       : 269
+  Statement        :     ) the_inout_ports (
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/router_ref/the_inout_ports/iport_weight_all[9]
+  String1          : 
+  String2          : Connected to floating net 'iport_weight_all[9]'
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedOutTerm-ML
+  Description      : Detected unloaded(unconnected) output terminal [DesignObjSignal] ([String2])
+  Violation        : Lint:1871
+  Goal             : lint_rtl
+  Module           : check_straight_oport
+  FileName         : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber       : 407
+  Statement        :             line_ring_decode_dstport decoder(
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/smart.Port_[2].smart_en.smart_allocator/check_straight/oneD.non_local.decoder/dstport_one_hot[2]
+  String1          : 
+  String2          : Connected to floating net 'oneD.non_local.destport_one_hot[2]'
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedOutTerm-ML
+  Description      : Detected unloaded(unconnected) output terminal [DesignObjSignal] ([String2])
+  Violation        : Lint:1775
+  Goal             : lint_rtl
+  Module           : mesh_torus_noc_top
+  FileName         : ./../../rtl/src_noc/./mesh_torus_noc_top.sv
+  LineNumber       : 70
+  Statement        :             ) the_router (
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/chan_out[2].flit_chanel.flit.payload[35]
+  String1          : 
+  String2          : Connected to floating net 'router_chan_out[0][2].flit_chanel.flit.payload[35]'
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedOutTerm-ML
+  Description      : Detected unloaded(unconnected) output terminal [DesignObjSignal] ([String2])
+  Violation        : Lint:1500
+  Goal             : lint_rtl
+  Module           : input_queue_per_port
+  FileName         : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber       : 387
+  Statement        :     ) header_extractor (
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[3].the_router/router_ref/the_inout_ports/the_input_port/Port_[2].the_input_queue_per_port/header_extractor/hdr_flg_o
+  String1          :  
+  String2          : Connected to floating net 'hdr_flg_in'
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedOutTerm-ML
+  Description      : Detected unloaded(unconnected) output terminal [DesignObjSignal] ([String2])
+  Violation        : Lint:1704
+  Goal             : lint_rtl
+  Module           : router_top
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 110
+  Statement        :     )router_ref (
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[2].the_router/router_ref/ovc_info[0][0].empty
+  String1          : 
+  String2          : Connected to floating net 'ovc_info[0][0].empty'
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedOutTerm-ML
+  Description      : Detected unloaded(unconnected) output terminal [DesignObjSignal] ([String2])
+  Violation        : Lint:1756
+  Goal             : lint_rtl
+  Module           : mesh_torus_noc_top
+  FileName         : ./../../rtl/src_noc/./mesh_torus_noc_top.sv
+  LineNumber       : 70
+  Statement        :             ) the_router (
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/chan_out[2].flit_chanel.flit.payload[16]
+  String1          : 
+  String2          : Connected to floating net 'router_chan_out[0][2].flit_chanel.flit.payload[16]'
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedOutTerm-ML
+  Description      : Detected unloaded(unconnected) output terminal [DesignObjSignal] ([String2])
+  Violation        : Lint:2067
+  Goal             : lint_rtl
+  Module           : mesh_torus_noc_top
+  FileName         : ./../../rtl/src_noc/./mesh_torus_noc_top.sv
+  LineNumber       : 70
+  Statement        :             ) the_router (
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[3].the_router/chan_out[1].flit_chanel.flit.payload[15]
+  String1          : 
+  String2          : Connected to floating net 'router_chan_out[3][1].flit_chanel.flit.payload[15]'
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedOutTerm-ML
+  Description      : Detected unloaded(unconnected) output terminal [DesignObjSignal] ([String2])
+  Violation        : Lint:1806
+  Goal             : lint_rtl
+  Module           : router_top
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 110
+  Statement        :     )router_ref (
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/router_ref/ovc_info[0][0].credit[0]
+  String1          : 
+  String2          : Connected to floating net 'ovc_info[0][0].credit[0]'
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedOutTerm-ML
+  Description      : Detected unloaded(unconnected) output terminal [DesignObjSignal] ([String2])
+  Violation        : Lint:1782
+  Goal             : lint_rtl
+  Module           : mesh_torus_noc_top
+  FileName         : ./../../rtl/src_noc/./mesh_torus_noc_top.sv
+  LineNumber       : 70
+  Statement        :             ) the_router (
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/chan_out[2].flit_chanel.flit.payload[42]
+  String1          : 
+  String2          : Connected to floating net 'router_chan_out[0][2].flit_chanel.flit.payload[42]'
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedOutTerm-ML
+  Description      : Detected unloaded(unconnected) output terminal [DesignObjSignal] ([String2])
+  Violation        : Lint:1963
+  Goal             : lint_rtl
+  Module           : router_two_stage
+  FileName         : ./../../rtl/src_noc/./router_two_stage.sv
+  LineNumber       : 269
+  Statement        :     ) the_inout_ports (
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[1].the_router/router_ref/the_inout_ports/oports_weight_all[32]
+  String1          : 
+  String2          : Connected to floating net 'oports_weight_all[32]'
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedOutTerm-ML
+  Description      : Detected unloaded(unconnected) output terminal [DesignObjSignal] ([String2])
+  Violation        : Lint:2017
+  Goal             : lint_rtl
+  Module           : router_two_stage
+  FileName         : ./../../rtl/src_noc/./router_two_stage.sv
+  LineNumber       : 269
+  Statement        :     ) the_inout_ports (
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[2].the_router/router_ref/the_inout_ports/oports_weight_all[24]
+  String1          : 
+  String2          : Connected to floating net 'oports_weight_all[24]'
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedOutTerm-ML
+  Description      : Detected unloaded(unconnected) output terminal [DesignObjSignal] ([String2])
+  Violation        : Lint:1951
+  Goal             : lint_rtl
+  Module           : router_two_stage
+  FileName         : ./../../rtl/src_noc/./router_two_stage.sv
+  LineNumber       : 269
+  Statement        :     ) the_inout_ports (
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[1].the_router/router_ref/the_inout_ports/oports_weight_all[20]
+  String1          : 
+  String2          : Connected to floating net 'oports_weight_all[20]'
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedOutTerm-ML
+  Description      : Detected unloaded(unconnected) output terminal [DesignObjSignal] ([String2])
+  Violation        : Lint:2052
+  Goal             : lint_rtl
+  Module           : mesh_torus_noc_top
+  FileName         : ./../../rtl/src_noc/./mesh_torus_noc_top.sv
+  LineNumber       : 70
+  Statement        :             ) the_router (
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[3].the_router/chan_out[1].flit_chanel.flit.payload[0]
+  String1          : 
+  String2          : Connected to floating net 'router_chan_out[3][1].flit_chanel.flit.payload[0]'
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedOutTerm-ML
+  Description      : Detected unloaded(unconnected) output terminal [DesignObjSignal] ([String2])
+  Violation        : Lint:2146
+  Goal             : lint_rtl
+  Module           : router_two_stage
+  FileName         : ./../../rtl/src_noc/./router_two_stage.sv
+  LineNumber       : 269
+  Statement        :     ) the_inout_ports (
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[3].the_router/router_ref/the_inout_ports/oports_weight_all[5]
+  String1          : 
+  String2          : Connected to floating net 'oports_weight_all[5]'
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedOutTerm-ML
+  Description      : Detected unloaded(unconnected) output terminal [DesignObjSignal] ([String2])
+  Violation        : Lint:2048
+  Goal             : lint_rtl
+  Module           : mesh_torus_noc_top
+  FileName         : ./../../rtl/src_noc/./mesh_torus_noc_top.sv
+  LineNumber       : 70
+  Statement        :             ) the_router (
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[3].the_router/chan_out[1].smart_chanel.requests[2]
+  String1          : 
+  String2          : Connected to floating net 'router_chan_out[3][1].smart_chanel.requests[2]'
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedOutTerm-ML
+  Description      : Detected unloaded(unconnected) output terminal [DesignObjSignal] ([String2])
+  Violation        : Lint:1589
+  Goal             : lint_rtl
+  Module           : input_queue_per_port
+  FileName         : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber       : 740
+  Statement        :                 ) dest_fifo (
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/router_ref/the_inout_ports/the_input_port/Port_[2].the_input_queue_per_port/V_[0].unicast.dtrmn_dest.dest_fifo/recieve_more_than_1
+  String1          :  
+  String2          : Left Open
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedOutTerm-ML
+  Description      : Detected unloaded(unconnected) output terminal [DesignObjSignal] ([String2])
+  Violation        : Lint:1827
+  Goal             : lint_rtl
+  Module           : router_two_stage
+  FileName         : ./../../rtl/src_noc/./router_two_stage.sv
+  LineNumber       : 269
+  Statement        :     ) the_inout_ports (
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/router_ref/the_inout_ports/iport_weight_all[10]
+  String1          : 
+  String2          : Connected to floating net 'iport_weight_all[10]'
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedOutTerm-ML
+  Description      : Detected unloaded(unconnected) output terminal [DesignObjSignal] ([String2])
+  Violation        : Lint:1799
+  Goal             : lint_rtl
+  Module           : mesh_torus_noc_top
+  FileName         : ./../../rtl/src_noc/./mesh_torus_noc_top.sv
+  LineNumber       : 70
+  Statement        :             ) the_router (
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/chan_out[2].flit_chanel.flit.payload[59]
+  String1          : 
+  String2          : Connected to floating net 'router_chan_out[0][2].flit_chanel.flit.payload[59]'
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedOutTerm-ML
+  Description      : Detected unloaded(unconnected) output terminal [DesignObjSignal] ([String2])
+  Violation        : Lint:1509
+  Goal             : lint_rtl
+  Module           : input_queue_per_port
+  FileName         : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber       : 625
+  Statement        :             ) dest_e_addr_fifo (
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/router_ref/the_inout_ports/the_input_port/Port_[0].the_input_queue_per_port/V_[0].smart_.dest_e_addr_fifo/recieve_more_than_1
+  String1          :  
+  String2          : Left Open
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedOutTerm-ML
+  Description      : Detected unloaded(unconnected) output terminal [DesignObjSignal] ([String2])
+  Violation        : Lint:1712
+  Goal             : lint_rtl
+  Module           : mesh_torus_noc_top
+  FileName         : ./../../rtl/src_noc/./mesh_torus_noc_top.sv
+  LineNumber       : 70
+  Statement        :             ) the_router (
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[3].the_router/chan_out[1].flit_chanel.flit.tail_flag
+  String1          : 
+  String2          : Connected to floating net 'router_chan_out[3][1].flit_chanel.flit.tail_flag'
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedOutTerm-ML
+  Description      : Detected unloaded(unconnected) output terminal [DesignObjSignal] ([String2])
+  Violation        : Lint:1772
+  Goal             : lint_rtl
+  Module           : mesh_torus_noc_top
+  FileName         : ./../../rtl/src_noc/./mesh_torus_noc_top.sv
+  LineNumber       : 70
+  Statement        :             ) the_router (
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/chan_out[2].flit_chanel.flit.payload[32]
+  String1          : 
+  String2          : Connected to floating net 'router_chan_out[0][2].flit_chanel.flit.payload[32]'
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedOutTerm-ML
+  Description      : Detected unloaded(unconnected) output terminal [DesignObjSignal] ([String2])
+  Violation        : Lint:1763
+  Goal             : lint_rtl
+  Module           : mesh_torus_noc_top
+  FileName         : ./../../rtl/src_noc/./mesh_torus_noc_top.sv
+  LineNumber       : 70
+  Statement        :             ) the_router (
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/chan_out[2].flit_chanel.flit.payload[23]
+  String1          : 
+  String2          : Connected to floating net 'router_chan_out[0][2].flit_chanel.flit.payload[23]'
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedOutTerm-ML
+  Description      : Detected unloaded(unconnected) output terminal [DesignObjSignal] ([String2])
+  Violation        : Lint:1789
+  Goal             : lint_rtl
+  Module           : mesh_torus_noc_top
+  FileName         : ./../../rtl/src_noc/./mesh_torus_noc_top.sv
+  LineNumber       : 70
+  Statement        :             ) the_router (
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/chan_out[2].flit_chanel.flit.payload[49]
+  String1          : 
+  String2          : Connected to floating net 'router_chan_out[0][2].flit_chanel.flit.payload[49]'
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedOutTerm-ML
+  Description      : Detected unloaded(unconnected) output terminal [DesignObjSignal] ([String2])
+  Violation        : Lint:1917
+  Goal             : lint_rtl
+  Module           : router_two_stage
+  FileName         : ./../../rtl/src_noc/./router_two_stage.sv
+  LineNumber       : 269
+  Statement        :     ) the_inout_ports (
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[1].the_router/router_ref/the_inout_ports/assigned_ovc_not_full_all[1]
+  String1          : 
+  String2          : Connected to floating net 'assigned_ovc_not_full_all[1]'
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedOutTerm-ML
+  Description      : Detected unloaded(unconnected) output terminal [DesignObjSignal] ([String2])
+  Violation        : Lint:1874
+  Goal             : lint_rtl
+  Module           : router_top
+  FileName         : ./../../rtl/src_noc/./router_top.sv
+  LineNumber       : 131
+  Statement        :         ) forward_ivc (
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[2].the_router/smart.forward_ivc/ovc_locally_requested[0][0]
+  String1          : 
+  String2          : Connected to floating net 'ovc_locally_requested[0][0]'
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedOutTerm-ML
+  Description      : Detected unloaded(unconnected) output terminal [DesignObjSignal] ([String2])
+  Violation        : Lint:1811
+  Goal             : lint_rtl
+  Module           : router_two_stage
+  FileName         : ./../../rtl/src_noc/./router_two_stage.sv
+  LineNumber       : 269
+  Statement        :     ) the_inout_ports (
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[0].the_router/router_ref/the_inout_ports/ovc_is_assigned_all[0]
+  String1          : 
+  String2          : Connected to floating net 'ovc_is_assigned_all[0]'
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedOutTerm-ML
+  Description      : Detected unloaded(unconnected) output terminal [DesignObjSignal] ([String2])
+  Violation        : Lint:2004
+  Goal             : lint_rtl
+  Module           : router_two_stage
+  FileName         : ./../../rtl/src_noc/./router_two_stage.sv
+  LineNumber       : 269
+  Statement        :     ) the_inout_ports (
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[2].the_router/router_ref/the_inout_ports/oports_weight_all[11]
+  String1          : 
+  String2          : Connected to floating net 'oports_weight_all[11]'
+  -----------------------------------------------------------------------------
+  Tag              : UnloadedOutTerm-ML
+  Description      : Detected unloaded(unconnected) output terminal [DesignObjSignal] ([String2])
+  Violation        : Lint:2083
+  Goal             : lint_rtl
+  Module           : mesh_torus_noc_top
+  FileName         : ./../../rtl/src_noc/./mesh_torus_noc_top.sv
+  LineNumber       : 70
+  Statement        :             ) the_router (
+  DesignObjSignal  : tori_noc.noc_top/ring_line.R_[3].the_router/chan_out[1].flit_chanel.flit.payload[31]
+  String1          : 
+  String2          : Connected to floating net 'router_chan_out[3][1].flit_chanel.flit.payload[31]'
+
+  -----------------------------------------------------------------------------
+  W120  (175 warnings/0 waived)
+  -----------------------------------------------------------------------------
+  Tag           : W120
+  Description   : Variable '[VariableName]'[ExprSize] declared but not used.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:4222
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 291
+  Statement     :     wire  [DSTPw-1 : 0] dest_port_multi   [V-1 : 0];
+  VariableName  : dest_port_multi
+  ExprSize      : (2 bits)
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[2].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag           : W120
+  Description   : Variable '[VariableName]'[ExprSize] declared but not used.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5405
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 292
+  Statement     :     wire  [V-1 : 0] multiple_dest,dst_onhot0;
+  VariableName  : dst_onhot0
+  ExprSize      : 
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[2].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[1].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag           : W120
+  Description   : Variable '[VariableName]'[ExprSize] declared but not used.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:4142
+  Goal          : lint_rtl
+  Module        : line_ring_destp_decoder
+  FileName      : ./../../rtl/src_noc/./mesh_torus.sv
+  LineNumber    : 1308
+  Statement     :     wire [NL-1 : 0] endp_localp_onehot;
+  VariableName  : endp_localp_onehot
+  ExprSize      : 
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[1].the_input_queue_per_port @input_queue_per_port:\V_[0].decoder @destp_generator:\mesh.destp_generator @mesh_torus_destp_generator:\one_D.decoder @line_ring_destp_decoder
+  -----------------------------------------------------------------------------
+  Tag           : W120
+  Description   : Variable '[VariableName]'[ExprSize] declared but not used.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5597
+  Goal          : lint_rtl
+  Module        : router_top
+  FileName      : ./../../rtl/src_noc/./router_top.sv
+  LineNumber    : 104
+  Statement     :     flit_chanel_t ss_flit_chanel [P-1 : 0]; //flit  bypass link goes to straight port
+  VariableName  : ss_flit_chanel[0].flit.payload[63:0]
+  ExprSize      : 
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[3].the_router @router_top
+  -----------------------------------------------------------------------------
+  Tag           : W120
+  Description   : Variable '[VariableName]'[ExprSize] declared but not used.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5413
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 317
+  Statement     :     wire [Pw-1 : 0] endp_p_in;
+  VariableName  : endp_p_in[1:0]
+  ExprSize      : 
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[2].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[1].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag           : W120
+  Description   : Variable '[VariableName]'[ExprSize] declared but not used.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5752
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 328
+  Statement     :     wire [V-1 : 0] dstport_fifo_not_empty;
+  VariableName  : dstport_fifo_not_empty
+  ExprSize      : 
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[3].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[1].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag           : W120
+  Description   : Variable '[VariableName]'[ExprSize] declared but not used.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:3897
+  Goal          : lint_rtl
+  Module        : line_ring_destp_decoder
+  FileName      : ./../../rtl/src_noc/./mesh_torus.sv
+  LineNumber    : 1308
+  Statement     :     wire [NL-1 : 0] endp_localp_onehot;
+  VariableName  : endp_localp_onehot
+  ExprSize      : 
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[0].the_input_queue_per_port @input_queue_per_port:\V_[0].decoder @destp_generator:\mesh.destp_generator @mesh_torus_destp_generator:\one_D.decoder @line_ring_destp_decoder
+  -----------------------------------------------------------------------------
+  Tag           : W120
+  Description   : Variable '[VariableName]'[ExprSize] declared but not used.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5855
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 316
+  Statement     :     wire [ELw-1 : 0] endp_l_in;
+  VariableName  : endp_l_in
+  ExprSize      : 
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[3].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[2].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag           : W120
+  Description   : Variable '[VariableName]'[ExprSize] declared but not used.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5505
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 328
+  Statement     :     wire [V-1 : 0] dstport_fifo_not_empty;
+  VariableName  : dstport_fifo_not_empty
+  ExprSize      : 
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[2].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[2].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag           : W120
+  Description   : Variable '[VariableName]'[ExprSize] declared but not used.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5251
+  Goal          : lint_rtl
+  Module        : router_top
+  FileName      : ./../../rtl/src_noc/./router_top.sv
+  LineNumber    : 104
+  Statement     :     flit_chanel_t ss_flit_chanel [P-1 : 0]; //flit  bypass link goes to straight port
+  VariableName  : ss_flit_chanel[0].flit.payload[63:0]
+  ExprSize      : 
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[2].the_router @router_top
+  -----------------------------------------------------------------------------
+  Tag           : W120
+  Description   : Variable '[VariableName]'[ExprSize] declared but not used.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:4035
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 317
+  Statement     :     wire [Pw-1 : 0] endp_p_in;
+  VariableName  : endp_p_in[1:0]
+  ExprSize      : 
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[1].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag           : W120
+  Description   : Variable '[VariableName]'[ExprSize] declared but not used.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:4431
+  Goal          : lint_rtl
+  Module        : output_ports
+  FileName      : ./../../rtl/src_noc/./output_ports.sv
+  LineNumber    : 124
+  Statement     :     integer k;
+  VariableName  : k
+  ExprSize      : 
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:output_ports@output_ports
+  -----------------------------------------------------------------------------
+  Tag           : W120
+  Description   : Variable '[VariableName]'[ExprSize] declared but not used.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:3825
+  Goal          : lint_rtl
+  Module        : flit_buffer
+  FileName      : ./../../rtl/src_noc/./flit_buffer.sv
+  LineNumber    : 109
+  Statement     :     wire [V-1 : 0] sub_restore;
+  VariableName  : sub_restore
+  ExprSize      : 
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[0].the_input_queue_per_port @input_queue_per_port:the_flit_buffer@flit_buffer
+  -----------------------------------------------------------------------------
+  Tag           : W120
+  Description   : Variable '[VariableName]'[ExprSize] declared but not used.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:4746
+  Goal          : lint_rtl
+  Module        : smart_bypass_chanels
+  FileName      : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber    : 343
+  Statement     :     wire [P-1 :0] smart_forwardable;
+  VariableName  : smart_forwardable[0]
+  ExprSize      : 
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:\smart.smart_bypass @smart_bypass_chanels
+  -----------------------------------------------------------------------------
+  Tag           : W120
+  Description   : Variable '[VariableName]'[ExprSize] declared but not used.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5166
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 317
+  Statement     :     wire [Pw-1 : 0] endp_p_in;
+  VariableName  : endp_p_in[1:0]
+  ExprSize      : 
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[1].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[2].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag           : W120
+  Description   : Variable '[VariableName]'[ExprSize] declared but not used.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5063
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 457
+  Statement     :     logic [1:0] ovc_sel_ivc [V-1 : 0];
+  VariableName  : ovc_sel_ivc
+  ExprSize      : (2 bits)
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[1].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[1].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag           : W120
+  Description   : Variable '[VariableName]'[ExprSize] declared but not used.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5861
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 317
+  Statement     :     wire [Pw-1 : 0] endp_p_in;
+  VariableName  : endp_p_in[1:0]
+  ExprSize      : 
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[3].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[2].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag           : W120
+  Description   : Variable '[VariableName]'[ExprSize] declared but not used.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5853
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 292
+  Statement     :     wire  [V-1 : 0] multiple_dest,dst_onhot0;
+  VariableName  : dst_onhot0
+  ExprSize      : 
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[3].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[2].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag           : W120
+  Description   : Variable '[VariableName]'[ExprSize] declared but not used.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5160
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 316
+  Statement     :     wire [ELw-1 : 0] endp_l_in;
+  VariableName  : endp_l_in
+  ExprSize      : 
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[1].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[2].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag           : W120
+  Description   : Variable '[VariableName]'[ExprSize] declared but not used.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5592
+  Goal          : lint_rtl
+  Module        : router_top
+  FileName      : ./../../rtl/src_noc/./router_top.sv
+  LineNumber    : 104
+  Statement     :     flit_chanel_t ss_flit_chanel [P-1 : 0]; //flit  bypass link goes to straight port
+  VariableName  : ss_flit_chanel[0].flit_wr
+  ExprSize      : 
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[3].the_router @router_top
+  -----------------------------------------------------------------------------
+  Tag           : W120
+  Description   : Variable '[VariableName]'[ExprSize] declared but not used.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5591
+  Goal          : lint_rtl
+  Module        : router_top
+  FileName      : ./../../rtl/src_noc/./router_top.sv
+  LineNumber    : 158
+  Statement     :         wire  [V-1  :  0]  ivc_smart_en [P-1 : 0];
+  VariableName  : smart.ivc_smart_en
+  ExprSize      : (1 bits)
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[3].the_router @router_top:\smart 
+  -----------------------------------------------------------------------------
+  Tag           : W120
+  Description   : Variable '[VariableName]'[ExprSize] declared but not used.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:4744
+  Goal          : lint_rtl
+  Module        : smart_bypass_chanels
+  FileName      : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber    : 339
+  Statement     :     smart_chanel_t smart_chanel_shifted  [P-1 : 0];
+  VariableName  : smart_chanel_shifted[0].flit_in_bypassed
+  ExprSize      : 
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:\smart.smart_bypass @smart_bypass_chanels
+  -----------------------------------------------------------------------------
+  Tag           : W120
+  Description   : Variable '[VariableName]'[ExprSize] declared but not used.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:3746
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 291
+  Statement     :     wire  [DSTPw-1 : 0] dest_port_multi   [V-1 : 0];
+  VariableName  : dest_port_multi
+  ExprSize      : (2 bits)
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[0].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag           : W120
+  Description   : Variable '[VariableName]'[ExprSize] declared but not used.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5506
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 316
+  Statement     :     wire [ELw-1 : 0] endp_l_in;
+  VariableName  : endp_l_in
+  ExprSize      : 
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[2].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[2].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag           : W120
+  Description   : Variable '[VariableName]'[ExprSize] declared but not used.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:3741
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 328
+  Statement     :     wire [V-1 : 0] dstport_fifo_not_empty;
+  VariableName  : dstport_fifo_not_empty
+  ExprSize      : 
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[0].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag           : W120
+  Description   : Variable '[VariableName]'[ExprSize] declared but not used.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5596
+  Goal          : lint_rtl
+  Module        : router_top
+  FileName      : ./../../rtl/src_noc/./router_top.sv
+  LineNumber    : 104
+  Statement     :     flit_chanel_t ss_flit_chanel [P-1 : 0]; //flit  bypass link goes to straight port
+  VariableName  : ss_flit_chanel[0].flit.vc[0]
+  ExprSize      : 
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[3].the_router @router_top
+  -----------------------------------------------------------------------------
+  Tag           : W120
+  Description   : Variable '[VariableName]'[ExprSize] declared but not used.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5507
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 339
+  Statement     :     wire  [V-1 : 0] flit_is_tail2;
+  VariableName  : flit_is_tail2
+  ExprSize      : 
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[2].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[2].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag           : W120
+  Description   : Variable '[VariableName]'[ExprSize] declared but not used.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5164
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 291
+  Statement     :     wire  [DSTPw-1 : 0] dest_port_multi   [V-1 : 0];
+  VariableName  : dest_port_multi
+  ExprSize      : (2 bits)
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[1].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[2].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag           : W120
+  Description   : Variable '[VariableName]'[ExprSize] declared but not used.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5854
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 328
+  Statement     :     wire [V-1 : 0] dstport_fifo_not_empty;
+  VariableName  : dstport_fifo_not_empty
+  ExprSize      : 
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[3].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[2].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag           : W120
+  Description   : Variable '[VariableName]'[ExprSize] declared but not used.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:3668
+  Goal          : lint_rtl
+  Module        : router_top
+  FileName      : ./../../rtl/src_noc/./router_top.sv
+  LineNumber    : 104
+  Statement     :     flit_chanel_t ss_flit_chanel [P-1 : 0]; //flit  bypass link goes to straight port
+  VariableName  : ss_flit_chanel[0].flit.payload[63:0]
+  ExprSize      : 
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top
+  -----------------------------------------------------------------------------
+  Tag           : W120
+  Description   : Variable '[VariableName]'[ExprSize] declared but not used.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5248
+  Goal          : lint_rtl
+  Module        : router_top
+  FileName      : ./../../rtl/src_noc/./router_top.sv
+  LineNumber    : 104
+  Statement     :     flit_chanel_t ss_flit_chanel [P-1 : 0]; //flit  bypass link goes to straight port
+  VariableName  : ss_flit_chanel[0].flit.hdr_flag
+  ExprSize      : 
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[2].the_router @router_top
+  -----------------------------------------------------------------------------
+  Tag           : W120
+  Description   : Variable '[VariableName]'[ExprSize] declared but not used.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5246
+  Goal          : lint_rtl
+  Module        : router_top
+  FileName      : ./../../rtl/src_noc/./router_top.sv
+  LineNumber    : 104
+  Statement     :     flit_chanel_t ss_flit_chanel [P-1 : 0]; //flit  bypass link goes to straight port
+  VariableName  : ss_flit_chanel[0].flit_wr
+  ExprSize      : 
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[2].the_router @router_top
+  -----------------------------------------------------------------------------
+  Tag           : W120
+  Description   : Variable '[VariableName]'[ExprSize] declared but not used.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:3669
+  Goal          : lint_rtl
+  Module        : router_top
+  FileName      : ./../../rtl/src_noc/./router_top.sv
+  LineNumber    : 104
+  Statement     :     flit_chanel_t ss_flit_chanel [P-1 : 0]; //flit  bypass link goes to straight port
+  VariableName  : ss_flit_chanel[0].congestion[2:0]
+  ExprSize      : 
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top
+  -----------------------------------------------------------------------------
+  Tag           : W120
+  Description   : Variable '[VariableName]'[ExprSize] declared but not used.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5062
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 339
+  Statement     :     wire  [V-1 : 0] flit_is_tail2;
+  VariableName  : flit_is_tail2
+  ExprSize      : 
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[1].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[1].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag           : W120
+  Description   : Variable '[VariableName]'[ExprSize] declared but not used.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:4902
+  Goal          : lint_rtl
+  Module        : router_top
+  FileName      : ./../../rtl/src_noc/./router_top.sv
+  LineNumber    : 104
+  Statement     :     flit_chanel_t ss_flit_chanel [P-1 : 0]; //flit  bypass link goes to straight port
+  VariableName  : ss_flit_chanel[0].flit.hdr_flag
+  ExprSize      : 
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[1].the_router @router_top
+  -----------------------------------------------------------------------------
+  Tag           : W120
+  Description   : Variable '[VariableName]'[ExprSize] declared but not used.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5306
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 292
+  Statement     :     wire  [V-1 : 0] multiple_dest,dst_onhot0;
+  VariableName  : dst_onhot0
+  ExprSize      : 
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[2].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[0].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag           : W120
+  Description   : Variable '[VariableName]'[ExprSize] declared but not used.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:3744
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 457
+  Statement     :     logic [1:0] ovc_sel_ivc [V-1 : 0];
+  VariableName  : ovc_sel_ivc
+  ExprSize      : (2 bits)
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[0].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag           : W120
+  Description   : Variable '[VariableName]'[ExprSize] declared but not used.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:3747
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 456
+  Statement     :     logic [1:0] ovc_sel_i;
+  VariableName  : ovc_sel_i[1:0]
+  ExprSize      : 
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[0].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag           : W120
+  Description   : Variable '[VariableName]'[ExprSize] declared but not used.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:4610
+  Goal          : lint_rtl
+  Module        : nonspec_sw_alloc
+  FileName      : ./../../rtl/src_noc/./comb_nonspec.sv
+  LineNumber    : 473
+  Statement     :     wire [V-1 : 0] pck_is_single_flit [P-1 : 0];  
+  VariableName  : pck_is_single_flit
+  ExprSize      : (3 bits)
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:router_ref@router_two_stage:vsa@combined_vc_sw_alloc:\nonspec.cmb_v1.nonspec_comb @comb_nonspec_allocator:nonspeculative_sw_allocator@nonspec_sw_alloc
+  -----------------------------------------------------------------------------
+  Tag           : W120
+  Description   : Variable '[VariableName]'[ExprSize] declared but not used.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5595
+  Goal          : lint_rtl
+  Module        : router_top
+  FileName      : ./../../rtl/src_noc/./router_top.sv
+  LineNumber    : 104
+  Statement     :     flit_chanel_t ss_flit_chanel [P-1 : 0]; //flit  bypass link goes to straight port
+  VariableName  : ss_flit_chanel[0].flit.tail_flag
+  ExprSize      : 
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[3].the_router @router_top
+  -----------------------------------------------------------------------------
+  Tag           : W120
+  Description   : Variable '[VariableName]'[ExprSize] declared but not used.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:4031
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 457
+  Statement     :     logic [1:0] ovc_sel_ivc [V-1 : 0];
+  VariableName  : ovc_sel_ivc
+  ExprSize      : (2 bits)
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[1].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag           : W120
+  Description   : Variable '[VariableName]'[ExprSize] declared but not used.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:4966
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 291
+  Statement     :     wire  [DSTPw-1 : 0] dest_port_multi   [V-1 : 0];
+  VariableName  : dest_port_multi
+  ExprSize      : (2 bits)
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[1].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[0].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag           : W120
+  Description   : Variable '[VariableName]'[ExprSize] declared but not used.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5509
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 293
+  Statement     :     wire   [DSTPw-1 : 0] clear_dspt_mulicast  [V-1 : 0];
+  VariableName  : clear_dspt_mulicast
+  ExprSize      : (2 bits)
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[2].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[2].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag           : W120
+  Description   : Variable '[VariableName]'[ExprSize] declared but not used.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5067
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 317
+  Statement     :     wire [Pw-1 : 0] endp_p_in;
+  VariableName  : endp_p_in[1:0]
+  ExprSize      : 
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[1].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[1].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag           : W120
+  Description   : Variable '[VariableName]'[ExprSize] declared but not used.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5412
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 456
+  Statement     :     logic [1:0] ovc_sel_i;
+  VariableName  : ovc_sel_i[1:0]
+  ExprSize      : 
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[2].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[1].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag           : W120
+  Description   : Variable '[VariableName]'[ExprSize] declared but not used.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:4742
+  Goal          : lint_rtl
+  Module        : smart_bypass_chanels
+  FileName      : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber    : 339
+  Statement     :     smart_chanel_t smart_chanel_shifted  [P-1 : 0];
+  VariableName  : smart_chanel_shifted[0].dest_e_addr[1:0]
+  ExprSize      : 
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:\smart.smart_bypass @smart_bypass_chanels
+  -----------------------------------------------------------------------------
+  Tag           : W120
+  Description   : Variable '[VariableName]'[ExprSize] declared but not used.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:3829
+  Goal          : lint_rtl
+  Module        : flit_buffer
+  FileName      : ./../../rtl/src_noc/./flit_buffer.sv
+  LineNumber    : 90
+  Statement     :     wire [PTRw- 1 : 0] sub_rd_ptr [V-1 :0];
+  VariableName  : sub_rd_ptr
+  ExprSize      : (4 bits)
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[0].the_input_queue_per_port @input_queue_per_port:the_flit_buffer@flit_buffer
+  -----------------------------------------------------------------------------
+  Tag           : W120
+  Description   : Variable '[VariableName]'[ExprSize] declared but not used.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5593
+  Goal          : lint_rtl
+  Module        : router_top
+  FileName      : ./../../rtl/src_noc/./router_top.sv
+  LineNumber    : 104
+  Statement     :     flit_chanel_t ss_flit_chanel [P-1 : 0]; //flit  bypass link goes to straight port
+  VariableName  : ss_flit_chanel[0].credit[0]
+  ExprSize      : 
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[3].the_router @router_top
+  -----------------------------------------------------------------------------
+  Tag           : W120
+  Description   : Variable '[VariableName]'[ExprSize] declared but not used.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5252
+  Goal          : lint_rtl
+  Module        : router_top
+  FileName      : ./../../rtl/src_noc/./router_top.sv
+  LineNumber    : 104
+  Statement     :     flit_chanel_t ss_flit_chanel [P-1 : 0]; //flit  bypass link goes to straight port
+  VariableName  : ss_flit_chanel[0].congestion[2:0]
+  ExprSize      : 
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[2].the_router @router_top
+  -----------------------------------------------------------------------------
+  Tag           : W120
+  Description   : Variable '[VariableName]'[ExprSize] declared but not used.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:3845
+  Goal          : lint_rtl
+  Module        : one_hot_to_bin
+  FileName      : ./../../rtl/src_noc/./../main_comp.v
+  LineNumber    : 271
+  Statement     :     wire [MUX_IN_WIDTH-1 : 0]  bin_temp ;
+  VariableName  : bin_temp
+  ExprSize      : 
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[0].the_input_queue_per_port @input_queue_per_port:the_flit_buffer@flit_buffer:\pow2.wr_vc_start_addr @one_hot_to_bin
+  -----------------------------------------------------------------------------
+  Tag           : W120
+  Description   : Variable '[VariableName]'[ExprSize] declared but not used.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5511
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 456
+  Statement     :     logic [1:0] ovc_sel_i;
+  VariableName  : ovc_sel_i[1:0]
+  ExprSize      : 
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[2].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[2].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag           : W120
+  Description   : Variable '[VariableName]'[ExprSize] declared but not used.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5756
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 293
+  Statement     :     wire   [DSTPw-1 : 0] clear_dspt_mulicast  [V-1 : 0];
+  VariableName  : clear_dspt_mulicast
+  ExprSize      : (2 bits)
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[3].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[1].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag           : W120
+  Description   : Variable '[VariableName]'[ExprSize] declared but not used.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5598
+  Goal          : lint_rtl
+  Module        : router_top
+  FileName      : ./../../rtl/src_noc/./router_top.sv
+  LineNumber    : 104
+  Statement     :     flit_chanel_t ss_flit_chanel [P-1 : 0]; //flit  bypass link goes to straight port
+  VariableName  : ss_flit_chanel[0].congestion[2:0]
+  ExprSize      : 
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[3].the_router @router_top
+  -----------------------------------------------------------------------------
+  Tag           : W120
+  Description   : Variable '[VariableName]'[ExprSize] declared but not used.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5660
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 317
+  Statement     :     wire [Pw-1 : 0] endp_p_in;
+  VariableName  : endp_p_in[1:0]
+  ExprSize      : 
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[3].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[0].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag           : W120
+  Description   : Variable '[VariableName]'[ExprSize] declared but not used.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:3743
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 339
+  Statement     :     wire  [V-1 : 0] flit_is_tail2;
+  VariableName  : flit_is_tail2
+  ExprSize      : 
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[0].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag           : W120
+  Description   : Variable '[VariableName]'[ExprSize] declared but not used.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5755
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 457
+  Statement     :     logic [1:0] ovc_sel_ivc [V-1 : 0];
+  VariableName  : ovc_sel_ivc
+  ExprSize      : (2 bits)
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[3].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[1].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag           : W120
+  Description   : Variable '[VariableName]'[ExprSize] declared but not used.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5860
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 456
+  Statement     :     logic [1:0] ovc_sel_i;
+  VariableName  : ovc_sel_i[1:0]
+  ExprSize      : 
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[3].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[2].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag           : W120
+  Description   : Variable '[VariableName]'[ExprSize] declared but not used.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:4741
+  Goal          : lint_rtl
+  Module        : smart_bypass_chanels
+  FileName      : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber    : 339
+  Statement     :     smart_chanel_t smart_chanel_shifted  [P-1 : 0];
+  VariableName  : smart_chanel_shifted[0].ovc[0]
+  ExprSize      : 
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:\smart.smart_bypass @smart_bypass_chanels
+  -----------------------------------------------------------------------------
+  Tag           : W120
+  Description   : Variable '[VariableName]'[ExprSize] declared but not used.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5504
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 292
+  Statement     :     wire  [V-1 : 0] multiple_dest,dst_onhot0;
+  VariableName  : dst_onhot0
+  ExprSize      : 
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[2].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[2].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag           : W120
+  Description   : Variable '[VariableName]'[ExprSize] declared but not used.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5244
+  Goal          : lint_rtl
+  Module        : router_top
+  FileName      : ./../../rtl/src_noc/./router_top.sv
+  LineNumber    : 157
+  Statement     :         wire  [V-1  :  0]  credit_out [P-1 : 0];
+  VariableName  : smart.credit_out
+  ExprSize      : (1 bits)
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[2].the_router @router_top:\smart 
+  -----------------------------------------------------------------------------
+  Tag           : W120
+  Description   : Variable '[VariableName]'[ExprSize] declared but not used.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5758
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 456
+  Statement     :     logic [1:0] ovc_sel_i;
+  VariableName  : ovc_sel_i[1:0]
+  ExprSize      : 
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[3].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[1].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag           : W120
+  Description   : Variable '[VariableName]'[ExprSize] declared but not used.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:4028
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 328
+  Statement     :     wire [V-1 : 0] dstport_fifo_not_empty;
+  VariableName  : dstport_fifo_not_empty
+  ExprSize      : 
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[1].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag           : W120
+  Description   : Variable '[VariableName]'[ExprSize] declared but not used.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5161
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 339
+  Statement     :     wire  [V-1 : 0] flit_is_tail2;
+  VariableName  : flit_is_tail2
+  ExprSize      : 
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[1].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[2].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag           : W120
+  Description   : Variable '[VariableName]'[ExprSize] declared but not used.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:4091
+  Goal          : lint_rtl
+  Module        : flit_buffer
+  FileName      : ./../../rtl/src_noc/./flit_buffer.sv
+  LineNumber    : 108
+  Statement     :     wire [V-1 : 0] sub_rd;
+  VariableName  : sub_rd
+  ExprSize      : 
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[1].the_input_queue_per_port @input_queue_per_port:the_flit_buffer@flit_buffer
+  -----------------------------------------------------------------------------
+  Tag           : W120
+  Description   : Variable '[VariableName]'[ExprSize] declared but not used.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:3824
+  Goal          : lint_rtl
+  Module        : flit_buffer
+  FileName      : ./../../rtl/src_noc/./flit_buffer.sv
+  LineNumber    : 108
+  Statement     :     wire [V-1 : 0] sub_rd;
+  VariableName  : sub_rd
+  ExprSize      : 
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[0].the_input_queue_per_port @input_queue_per_port:the_flit_buffer@flit_buffer
+  -----------------------------------------------------------------------------
+  Tag           : W120
+  Description   : Variable '[VariableName]'[ExprSize] declared but not used.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:4967
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 456
+  Statement     :     logic [1:0] ovc_sel_i;
+  VariableName  : ovc_sel_i[1:0]
+  ExprSize      : 
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[1].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[0].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag           : W120
+  Description   : Variable '[VariableName]'[ExprSize] declared but not used.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:4094
+  Goal          : lint_rtl
+  Module        : flit_buffer
+  FileName      : ./../../rtl/src_noc/./flit_buffer.sv
+  LineNumber    : 101
+  Statement     :     wire [DEPTHw-1  : 0] sub_depth       [V-1 :0];
+  VariableName  : sub_depth
+  ExprSize      : (3 bits)
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[1].the_input_queue_per_port @input_queue_per_port:the_flit_buffer@flit_buffer
+  -----------------------------------------------------------------------------
+  Tag           : W120
+  Description   : Variable '[VariableName]'[ExprSize] declared but not used.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:3748
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 317
+  Statement     :     wire [Pw-1 : 0] endp_p_in;
+  VariableName  : endp_p_in[1:0]
+  ExprSize      : 
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[0].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag           : W120
+  Description   : Variable '[VariableName]'[ExprSize] declared but not used.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:3662
+  Goal          : lint_rtl
+  Module        : router_top
+  FileName      : ./../../rtl/src_noc/./router_top.sv
+  LineNumber    : 158
+  Statement     :         wire  [V-1  :  0]  ivc_smart_en [P-1 : 0];
+  VariableName  : smart.ivc_smart_en
+  ExprSize      : (1 bits)
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:\smart 
+  -----------------------------------------------------------------------------
+  Tag           : W120
+  Description   : Variable '[VariableName]'[ExprSize] declared but not used.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5411
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 291
+  Statement     :     wire  [DSTPw-1 : 0] dest_port_multi   [V-1 : 0];
+  VariableName  : dest_port_multi
+  ExprSize      : (2 bits)
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[2].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[1].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag           : W120
+  Description   : Variable '[VariableName]'[ExprSize] declared but not used.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:3663
+  Goal          : lint_rtl
+  Module        : router_top
+  FileName      : ./../../rtl/src_noc/./router_top.sv
+  LineNumber    : 104
+  Statement     :     flit_chanel_t ss_flit_chanel [P-1 : 0]; //flit  bypass link goes to straight port
+  VariableName  : ss_flit_chanel[0].flit_wr
+  ExprSize      : 
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top
+  -----------------------------------------------------------------------------
+  Tag           : W120
+  Description   : Variable '[VariableName]'[ExprSize] declared but not used.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5308
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 316
+  Statement     :     wire [ELw-1 : 0] endp_l_in;
+  VariableName  : endp_l_in
+  ExprSize      : 
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[2].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[0].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag           : W120
+  Description   : Variable '[VariableName]'[ExprSize] declared but not used.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5245
+  Goal          : lint_rtl
+  Module        : router_top
+  FileName      : ./../../rtl/src_noc/./router_top.sv
+  LineNumber    : 158
+  Statement     :         wire  [V-1  :  0]  ivc_smart_en [P-1 : 0];
+  VariableName  : smart.ivc_smart_en
+  ExprSize      : (1 bits)
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[2].the_router @router_top:\smart 
+  -----------------------------------------------------------------------------
+  Tag           : W120
+  Description   : Variable '[VariableName]'[ExprSize] declared but not used.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:3745
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 293
+  Statement     :     wire   [DSTPw-1 : 0] clear_dspt_mulicast  [V-1 : 0];
+  VariableName  : clear_dspt_mulicast
+  ExprSize      : (2 bits)
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[0].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag           : W120
+  Description   : Variable '[VariableName]'[ExprSize] declared but not used.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:4096
+  Goal          : lint_rtl
+  Module        : flit_buffer
+  FileName      : ./../../rtl/src_noc/./flit_buffer.sv
+  LineNumber    : 90
+  Statement     :     wire [PTRw- 1 : 0] sub_rd_ptr [V-1 :0];
+  VariableName  : sub_rd_ptr
+  ExprSize      : (2 bits)
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[1].the_input_queue_per_port @input_queue_per_port:the_flit_buffer@flit_buffer
+  -----------------------------------------------------------------------------
+  Tag           : W120
+  Description   : Variable '[VariableName]'[ExprSize] declared but not used.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:4906
+  Goal          : lint_rtl
+  Module        : router_top
+  FileName      : ./../../rtl/src_noc/./router_top.sv
+  LineNumber    : 104
+  Statement     :     flit_chanel_t ss_flit_chanel [P-1 : 0]; //flit  bypass link goes to straight port
+  VariableName  : ss_flit_chanel[0].congestion[2:0]
+  ExprSize      : 
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[1].the_router @router_top
+  -----------------------------------------------------------------------------
+  Tag           : W120
+  Description   : Variable '[VariableName]'[ExprSize] declared but not used.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5857
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 457
+  Statement     :     logic [1:0] ovc_sel_ivc [V-1 : 0];
+  VariableName  : ovc_sel_ivc
+  ExprSize      : (2 bits)
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[3].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[2].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag           : W120
+  Description   : Variable '[VariableName]'[ExprSize] declared but not used.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5064
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 293
+  Statement     :     wire   [DSTPw-1 : 0] clear_dspt_mulicast  [V-1 : 0];
+  VariableName  : clear_dspt_mulicast
+  ExprSize      : (2 bits)
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[1].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[1].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag           : W120
+  Description   : Variable '[VariableName]'[ExprSize] declared but not used.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5658
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 291
+  Statement     :     wire  [DSTPw-1 : 0] dest_port_multi   [V-1 : 0];
+  VariableName  : dest_port_multi
+  ExprSize      : (2 bits)
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[3].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[0].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag           : W120
+  Description   : Variable '[VariableName]'[ExprSize] declared but not used.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:4219
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 339
+  Statement     :     wire  [V-1 : 0] flit_is_tail2;
+  VariableName  : flit_is_tail2
+  ExprSize      : 
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[2].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag           : W120
+  Description   : Variable '[VariableName]'[ExprSize] declared but not used.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:4027
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 292
+  Statement     :     wire  [V-1 : 0] multiple_dest,dst_onhot0;
+  VariableName  : dst_onhot0
+  ExprSize      : 
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[1].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag           : W120
+  Description   : Variable '[VariableName]'[ExprSize] declared but not used.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5311
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 293
+  Statement     :     wire   [DSTPw-1 : 0] clear_dspt_mulicast  [V-1 : 0];
+  VariableName  : clear_dspt_mulicast
+  ExprSize      : (2 bits)
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[2].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[0].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag           : W120
+  Description   : Variable '[VariableName]'[ExprSize] declared but not used.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5061
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 316
+  Statement     :     wire [ELw-1 : 0] endp_l_in;
+  VariableName  : endp_l_in
+  ExprSize      : 
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[1].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[1].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag           : W120
+  Description   : Variable '[VariableName]'[ExprSize] declared but not used.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5407
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 316
+  Statement     :     wire [ELw-1 : 0] endp_l_in;
+  VariableName  : endp_l_in
+  ExprSize      : 
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[2].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[1].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag           : W120
+  Description   : Variable '[VariableName]'[ExprSize] declared but not used.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:4604
+  Goal          : lint_rtl
+  Module        : comb_nonspec_allocator
+  FileName      : ./../../rtl/src_noc/./comb_nonspec.sv
+  LineNumber    : 93
+  Statement     :     wire  [P-1 : 0] any_cand_ovc_exsit;    
+  VariableName  : any_cand_ovc_exsit[2:0]
+  ExprSize      : 
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:router_ref@router_two_stage:vsa@combined_vc_sw_alloc:\nonspec.cmb_v1.nonspec_comb @comb_nonspec_allocator
+  -----------------------------------------------------------------------------
+  Tag           : W120
+  Description   : Variable '[VariableName]'[ExprSize] declared but not used.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5751
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 292
+  Statement     :     wire  [V-1 : 0] multiple_dest,dst_onhot0;
+  VariableName  : dst_onhot0
+  ExprSize      : 
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[3].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[1].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag           : W120
+  Description   : Variable '[VariableName]'[ExprSize] declared but not used.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5066
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 456
+  Statement     :     logic [1:0] ovc_sel_i;
+  VariableName  : ovc_sel_i[1:0]
+  ExprSize      : 
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[1].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[1].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag           : W120
+  Description   : Variable '[VariableName]'[ExprSize] declared but not used.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:4964
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 457
+  Statement     :     logic [1:0] ovc_sel_ivc [V-1 : 0];
+  VariableName  : ovc_sel_ivc
+  ExprSize      : (2 bits)
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[1].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[0].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag           : W120
+  Description   : Variable '[VariableName]'[ExprSize] declared but not used.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:3860
+  Goal          : lint_rtl
+  Module        : ovc_list
+  FileName      : ./../../rtl/src_noc/./ovc_list.sv
+  LineNumber    : 42
+  Statement     :     logic [V-1 : 0] ovc_message_class;
+  VariableName  : ovc_message_class
+  ExprSize      : 
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[0].the_input_queue_per_port @input_queue_per_port:\V_[0].ovc_.OvcList @ovc_list
+  -----------------------------------------------------------------------------
+  Tag           : W120
+  Description   : Variable '[VariableName]'[ExprSize] declared but not used.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5594
+  Goal          : lint_rtl
+  Module        : router_top
+  FileName      : ./../../rtl/src_noc/./router_top.sv
+  LineNumber    : 104
+  Statement     :     flit_chanel_t ss_flit_chanel [P-1 : 0]; //flit  bypass link goes to straight port
+  VariableName  : ss_flit_chanel[0].flit.hdr_flag
+  ExprSize      : 
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[3].the_router @router_top
+  -----------------------------------------------------------------------------
+  Tag           : W120
+  Description   : Variable '[VariableName]'[ExprSize] declared but not used.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5590
+  Goal          : lint_rtl
+  Module        : router_top
+  FileName      : ./../../rtl/src_noc/./router_top.sv
+  LineNumber    : 157
+  Statement     :         wire  [V-1  :  0]  credit_out [P-1 : 0];
+  VariableName  : smart.credit_out
+  ExprSize      : (1 bits)
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[3].the_router @router_top:\smart 
+  -----------------------------------------------------------------------------
+  Tag           : W120
+  Description   : Variable '[VariableName]'[ExprSize] declared but not used.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5163
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 293
+  Statement     :     wire   [DSTPw-1 : 0] clear_dspt_mulicast  [V-1 : 0];
+  VariableName  : clear_dspt_mulicast
+  ExprSize      : (2 bits)
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[1].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[2].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag           : W120
+  Description   : Variable '[VariableName]'[ExprSize] declared but not used.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:4030
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 339
+  Statement     :     wire  [V-1 : 0] flit_is_tail2;
+  VariableName  : flit_is_tail2
+  ExprSize      : 
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[1].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag           : W120
+  Description   : Variable '[VariableName]'[ExprSize] declared but not used.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5654
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 316
+  Statement     :     wire [ELw-1 : 0] endp_l_in;
+  VariableName  : endp_l_in
+  ExprSize      : 
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[3].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[0].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag           : W120
+  Description   : Variable '[VariableName]'[ExprSize] declared but not used.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5656
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 457
+  Statement     :     logic [1:0] ovc_sel_ivc [V-1 : 0];
+  VariableName  : ovc_sel_ivc
+  ExprSize      : (2 bits)
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[3].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[0].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag           : W120
+  Description   : Variable '[VariableName]'[ExprSize] declared but not used.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5065
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 291
+  Statement     :     wire  [DSTPw-1 : 0] dest_port_multi   [V-1 : 0];
+  VariableName  : dest_port_multi
+  ExprSize      : (2 bits)
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[1].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[1].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag           : W120
+  Description   : Variable '[VariableName]'[ExprSize] declared but not used.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5310
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 457
+  Statement     :     logic [1:0] ovc_sel_ivc [V-1 : 0];
+  VariableName  : ovc_sel_ivc
+  ExprSize      : (2 bits)
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[2].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[0].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag           : W120
+  Description   : Variable '[VariableName]'[ExprSize] declared but not used.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:4309
+  Goal          : lint_rtl
+  Module        : line_ring_destp_decoder
+  FileName      : ./../../rtl/src_noc/./mesh_torus.sv
+  LineNumber    : 1308
+  Statement     :     wire [NL-1 : 0] endp_localp_onehot;
+  VariableName  : endp_localp_onehot
+  ExprSize      : 
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[2].the_input_queue_per_port @input_queue_per_port:\V_[0].decoder @destp_generator:\mesh.destp_generator @mesh_torus_destp_generator:\one_D.decoder @line_ring_destp_decoder
+  -----------------------------------------------------------------------------
+  Tag           : W120
+  Description   : Variable '[VariableName]'[ExprSize] declared but not used.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:3664
+  Goal          : lint_rtl
+  Module        : router_top
+  FileName      : ./../../rtl/src_noc/./router_top.sv
+  LineNumber    : 104
+  Statement     :     flit_chanel_t ss_flit_chanel [P-1 : 0]; //flit  bypass link goes to straight port
+  VariableName  : ss_flit_chanel[0].credit[0]
+  ExprSize      : 
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top
+  -----------------------------------------------------------------------------
+  Tag           : W120
+  Description   : Variable '[VariableName]'[ExprSize] declared but not used.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5655
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 339
+  Statement     :     wire  [V-1 : 0] flit_is_tail2;
+  VariableName  : flit_is_tail2
+  ExprSize      : 
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[3].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[0].the_input_queue_per_port @input_queue_per_port
+
+  -----------------------------------------------------------------------------
+  W175  (40 warnings/0 waived)
+  -----------------------------------------------------------------------------
+  Tag           : W175
+  Description   : Parameter '[Param]' declared but not used
+  Violation     : Lint:2895
+  Goal          : lint_rtl
+  Module        : line_ring_destp_decoder
+  FileName      : ./../../rtl/src_noc/./mesh_torus.sv
+  LineNumber    : 1291
+  Statement     :     parameter ROUTE_TYPE="DETERMINISTIC",
+  Param         : ROUTE_TYPE
+  -----------------------------------------------------------------------------
+  Tag           : W175
+  Description   : Parameter '[Param]' declared but not used
+  Violation     : Lint:2887
+  Goal          : lint_rtl
+  Module        : fwft_fifo
+  FileName      : ./../../rtl/src_noc/./flit_buffer.sv
+  LineNumber    : 551
+  Statement     :     parameter IGNORE_SAME_LOC_RD_WR_WARNING="YES" // "YES" , "NO" 
+  Param         : IGNORE_SAME_LOC_RD_WR_WARNING
+  -----------------------------------------------------------------------------
+  Tag           : W175
+  Description   : Parameter '[Param]' declared but not used
+  Violation     : Lint:2860
+  Goal          : lint_rtl
+  Module        : inout_ports
+  FileName      : ./../../rtl/src_noc/./inout_ports.sv
+  LineNumber    : 103
+  Statement     :         PVDSTPw= PV * DSTPw,
+  Param         : PVDSTPw
+  -----------------------------------------------------------------------------
+  Tag           : W175
+  Description   : Parameter '[Param]' declared but not used
+  Violation     : Lint:2884
+  Goal          : lint_rtl
+  Module        : crossbar
+  FileName      : ./../../rtl/src_noc/./crossbar.v
+  LineNumber    : 30
+  Statement     :     parameter TOPOLOGY = "MESH",
+  Param         : TOPOLOGY
+  -----------------------------------------------------------------------------
+  Tag           : W175
+  Description   : Parameter '[Param]' declared but not used
+  Violation     : Lint:2885
+  Goal          : lint_rtl
+  Module        : flit_buffer
+  FileName      : ./../../rtl/src_noc/./flit_buffer.sv
+  LineNumber    : 62
+  Statement     :         BVwV = BVw * V,
+  Param         : BVwV
+  -----------------------------------------------------------------------------
+  Tag           : W175
+  Description   : Parameter '[Param]' declared but not used
+  Violation     : Lint:2865
+  Goal          : lint_rtl
+  Module        : input_ports
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 80
+  Statement     :         VP_1 = V * P_1,
+  Param         : VP_1
+  -----------------------------------------------------------------------------
+  Tag           : W175
+  Description   : Parameter '[Param]' declared but not used
+  Violation     : Lint:2856
+  Goal          : lint_rtl
+  Module        : extract_header_flit_info
+  FileName      : ./../../rtl/src_noc/./header_flit.sv
+  LineNumber    : 108
+  Statement     :     parameter NOC_ID=0,
+  Param         : NOC_ID
+  -----------------------------------------------------------------------------
+  Tag           : W175
+  Description   : Parameter '[Param]' declared but not used
+  Violation     : Lint:2864
+  Goal          : lint_rtl
+  Module        : input_ports
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 86
+  Statement     :         PVDSTPw= PV * DSTPw,
+  Param         : PVDSTPw
+  -----------------------------------------------------------------------------
+  Tag           : W175
+  Description   : Parameter '[Param]' declared but not used
+  Violation     : Lint:2877
+  Goal          : lint_rtl
+  Module        : look_ahead_routing
+  FileName      : ./../../rtl/src_noc/./routing.v
+  LineNumber    : 237
+  Statement     :     parameter T4= 8,
+  Param         : T4
+  -----------------------------------------------------------------------------
+  Tag           : W175
+  Description   : Parameter '[Param]' declared but not used
+  Violation     : Lint:2872
+  Goal          : lint_rtl
+  Module        : smart_bypass_chanels
+  FileName      : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber    : 314
+  Statement     :     parameter NOC_ID=0,
+  Param         : NOC_ID
+  -----------------------------------------------------------------------------
+  Tag           : W175
+  Description   : Parameter '[Param]' declared but not used
+  Violation     : Lint:2882
+  Goal          : lint_rtl
+  Module        : crossbar
+  FileName      : ./../../rtl/src_noc/./crossbar.v
+  LineNumber    : 57
+  Statement     :         PVV = PV * V,
+  Param         : PVV
+  -----------------------------------------------------------------------------
+  Tag           : W175
+  Description   : Parameter '[Param]' declared but not used
+  Violation     : Lint:2889
+  Goal          : lint_rtl
+  Module        : mesh_torus_mask_non_assignable_destport_no_self_loop
+  FileName      : ./../../rtl/src_noc/./mesh_torus.sv
+  LineNumber    : 312
+  Statement     :         E_WEST = 2,  
+  Param         : E_WEST
+  -----------------------------------------------------------------------------
+  Tag           : W175
+  Description   : Parameter '[Param]' declared but not used
+  Violation     : Lint:2894
+  Goal          : lint_rtl
+  Module        : line_ring_destp_decoder
+  FileName      : ./../../rtl/src_noc/./mesh_torus.sv
+  LineNumber    : 1296
+  Statement     :     parameter PPSw=4,
+  Param         : PPSw
+  -----------------------------------------------------------------------------
+  Tag           : W175
+  Description   : Parameter '[Param]' declared but not used
+  Violation     : Lint:2893
+  Goal          : lint_rtl
+  Module        : mesh_tori_router_addr_decode
+  FileName      : ./../../rtl/src_noc/./mesh_torus.sv
+  LineNumber    : 881
+  Statement     :     parameter T3=4,
+  Param         : T3
+  -----------------------------------------------------------------------------
+  Tag           : W175
+  Description   : Parameter '[Param]' declared but not used
+  Violation     : Lint:2867
+  Goal          : lint_rtl
+  Module        : input_ports
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 76
+  Statement     :         VV = V * V,
+  Param         : VV
+  -----------------------------------------------------------------------------
+  Tag           : W175
+  Description   : Parameter '[Param]' declared but not used
+  Violation     : Lint:2876
+  Goal          : lint_rtl
+  Module        : credit_monitor_per_ovc
+  FileName      : ./../../rtl/src_noc/./output_ports.sv
+  LineNumber    : 398
+  Statement     :     parameter NOC_ID=0,
+  Param         : NOC_ID
+  -----------------------------------------------------------------------------
+  Tag           : W175
+  Description   : Parameter '[Param]' declared but not used
+  Violation     : Lint:2873
+  Goal          : lint_rtl
+  Module        : smart_validity_check_per_ivc
+  FileName      : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber    : 422
+  Statement     :     parameter NOC_ID=0,
+  Param         : NOC_ID
+  -----------------------------------------------------------------------------
+  Tag           : W175
+  Description   : Parameter '[Param]' declared but not used
+  Violation     : Lint:2857
+  Goal          : lint_rtl
+  Module        : header_flit_update_lk_route_ovc
+  FileName      : ./../../rtl/src_noc/./header_flit.sv
+  LineNumber    : 196
+  Statement     :     parameter NOC_ID=0,
+  Param         : NOC_ID
+  -----------------------------------------------------------------------------
+  Tag           : W175
+  Description   : Parameter '[Param]' declared but not used
+  Violation     : Lint:2878
+  Goal          : lint_rtl
+  Module        : look_ahead_routing
+  FileName      : ./../../rtl/src_noc/./routing.v
+  LineNumber    : 232
+  Statement     :     parameter NOC_ID=0,
+  Param         : NOC_ID
+  -----------------------------------------------------------------------------
+  Tag           : W175
+  Description   : Parameter '[Param]' declared but not used
+  Violation     : Lint:2863
+  Goal          : lint_rtl
+  Module        : input_ports
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 87
+  Statement     :         PRAw= P * RAw;    
+  Param         : PRAw
+  -----------------------------------------------------------------------------
+  Tag           : W175
+  Description   : Parameter '[Param]' declared but not used
+  Violation     : Lint:2866
+  Goal          : lint_rtl
+  Module        : input_ports
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 77
+  Statement     :         PVV = PV * V,    
+  Param         : PVV
+  -----------------------------------------------------------------------------
+  Tag           : W175
+  Description   : Parameter '[Param]' declared but not used
+  Violation     : Lint:2874
+  Goal          : lint_rtl
+  Module        : port_pre_sel_gen
+  FileName      : ./../../rtl/src_noc/./congestion_analyzer.v
+  LineNumber    : 347
+  Statement     :         P_1 = P-1,
+  Param         : P_1
+  -----------------------------------------------------------------------------
+  Tag           : W175
+  Description   : Parameter '[Param]' declared but not used
+  Violation     : Lint:2868
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 225
+  Statement     :         PORT_Bw= log2(PORT_B),
+  Param         : PORT_Bw
+  -----------------------------------------------------------------------------
+  Tag           : W175
+  Description   : Parameter '[Param]' declared but not used
+  Violation     : Lint:2862
+  Goal          : lint_rtl
+  Module        : vc_alloc_request_gen_determinstic
+  FileName      : ./../../rtl/src_noc/./inout_ports.sv
+  LineNumber    : 606
+  Statement     :     parameter CAST_TYPE = "UNICAST" 
+  Param         : CAST_TYPE
+  -----------------------------------------------------------------------------
+  Tag           : W175
+  Description   : Parameter '[Param]' declared but not used
+  Violation     : Lint:2892
+  Goal          : lint_rtl
+  Module        : mesh_torus_mask_non_assignable_destport_no_self_loop
+  FileName      : ./../../rtl/src_noc/./mesh_torus.sv
+  LineNumber    : 292
+  Statement     :         EAST = 1, 
+  Param         : EAST
+  -----------------------------------------------------------------------------
+  Tag           : W175
+  Description   : Parameter '[Param]' declared but not used
+  Violation     : Lint:2890
+  Goal          : lint_rtl
+  Module        : mesh_torus_mask_non_assignable_destport_no_self_loop
+  FileName      : ./../../rtl/src_noc/./mesh_torus.sv
+  LineNumber    : 311
+  Statement     :         E_NORTH = 1,  
+  Param         : E_NORTH
+  -----------------------------------------------------------------------------
+  Tag           : W175
+  Description   : Parameter '[Param]' declared but not used
+  Violation     : Lint:2858
+  Goal          : lint_rtl
+  Module        : comb_nonspec_allocator
+  FileName      : ./../../rtl/src_noc/./comb_nonspec.sv
+  LineNumber    : 32
+  Statement     :     parameter NOC_ID = 0,
+  Param         : NOC_ID
+  -----------------------------------------------------------------------------
+  Tag           : W175
+  Description   : Parameter '[Param]' declared but not used
+  Violation     : Lint:2888
+  Goal          : lint_rtl
+  Module        : mesh_torus_mask_non_assignable_destport_no_self_loop
+  FileName      : ./../../rtl/src_noc/./mesh_torus.sv
+  LineNumber    : 313
+  Statement     :         E_SOUTH = 3; 
+  Param         : E_SOUTH
+  -----------------------------------------------------------------------------
+  Tag           : W175
+  Description   : Parameter '[Param]' declared but not used
+  Violation     : Lint:2871
+  Goal          : lint_rtl
+  Module        : smart_forward_ivc_info
+  FileName      : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber    : 210
+  Statement     :     parameter NOC_ID=0,
+  Param         : NOC_ID
+  -----------------------------------------------------------------------------
+  Tag           : W175
+  Description   : Parameter '[Param]' declared but not used
+  Violation     : Lint:2875
+  Goal          : lint_rtl
+  Module        : port_pre_sel_gen
+  FileName      : ./../../rtl/src_noc/./congestion_analyzer.v
+  LineNumber    : 334
+  Statement     :     parameter [V-1 : 0] ESCAP_VC_MASK= 4'b0001
+  Param         : ESCAP_VC_MASK
+  -----------------------------------------------------------------------------
+  Tag           : W175
+  Description   : Parameter '[Param]' declared but not used
+  Violation     : Lint:2881
+  Goal          : lint_rtl
+  Module        : crossbar
+  FileName      : ./../../rtl/src_noc/./crossbar.v
+  LineNumber    : 59
+  Statement     :         VP_1 = V * P_1,
+  Param         : VP_1
+  -----------------------------------------------------------------------------
+  Tag           : W175
+  Description   : Parameter '[Param]' declared but not used
+  Violation     : Lint:2886
+  Goal          : lint_rtl
+  Module        : flit_buffer
+  FileName      : ./../../rtl/src_noc/./flit_buffer.sv
+  LineNumber    : 61
+  Statement     :         BwV = Bw * V,
+  Param         : BwV
+  -----------------------------------------------------------------------------
+  Tag           : W175
+  Description   : Parameter '[Param]' declared but not used
+  Violation     : Lint:2861
+  Goal          : lint_rtl
+  Module        : vc_alloc_request_gen
+  FileName      : ./../../rtl/src_noc/./inout_ports.sv
+  LineNumber    : 432
+  Statement     :     parameter NOC_ID=0,
+  Param         : NOC_ID
+  -----------------------------------------------------------------------------
+  Tag           : W175
+  Description   : Parameter '[Param]' declared but not used
+  Violation     : Lint:2880
+  Goal          : lint_rtl
+  Module        : crossbar
+  FileName      : ./../../rtl/src_noc/./crossbar.v
+  LineNumber    : 61
+  Statement     :         PVP_1 = PV * P_1,
+  Param         : PVP_1
+  -----------------------------------------------------------------------------
+  Tag           : W175
+  Description   : Parameter '[Param]' declared but not used
+  Violation     : Lint:2891
+  Goal          : lint_rtl
+  Module        : mesh_torus_mask_non_assignable_destport_no_self_loop
+  FileName      : ./../../rtl/src_noc/./mesh_torus.sv
+  LineNumber    : 310
+  Statement     :         E_LOCAL = 0, 
+  Param         : E_LOCAL
+  -----------------------------------------------------------------------------
+  Tag           : W175
+  Description   : Parameter '[Param]' declared but not used
+  Violation     : Lint:2859
+  Goal          : lint_rtl
+  Module        : inout_ports
+  FileName      : ./../../rtl/src_noc/./inout_ports.sv
+  LineNumber    : 104
+  Statement     :         PRAw= P * RAw;
+  Param         : PRAw
+  -----------------------------------------------------------------------------
+  Tag           : W175
+  Description   : Parameter '[Param]' declared but not used
+  Violation     : Lint:2883
+  Goal          : lint_rtl
+  Module        : crossbar
+  FileName      : ./../../rtl/src_noc/./crossbar.v
+  LineNumber    : 55
+  Statement     :         VV = V * V,
+  Param         : VV
+  -----------------------------------------------------------------------------
+  Tag           : W175
+  Description   : Parameter '[Param]' declared but not used
+  Violation     : Lint:2870
+  Goal          : lint_rtl
+  Module        : mesh_torus_conventional_routing
+  FileName      : ./../../rtl/src_noc/./mesh_torus_routting.v
+  LineNumber    : 600
+  Statement     :     parameter ROUTE_TYPE = "DETERMINISTIC",    
+  Param         : ROUTE_TYPE
+  -----------------------------------------------------------------------------
+  Tag           : W175
+  Description   : Parameter '[Param]' declared but not used
+  Violation     : Lint:2869
+  Goal          : lint_rtl
+  Module        : mesh_torus_deterministic_look_ahead_routing
+  FileName      : ./../../rtl/src_noc/./mesh_torus_routting.v
+  LineNumber    : 109
+  Statement     :     parameter SW_LOC =0,
+  Param         : SW_LOC
+  -----------------------------------------------------------------------------
+  Tag           : W175
+  Description   : Parameter '[Param]' declared but not used
+  Violation     : Lint:2879
+  Goal          : lint_rtl
+  Module        : credit_release_gen
+  FileName      : ./../../rtl/src_noc/./router_two_stage.sv
+  LineNumber    : 656
+  Statement     :     parameter NOC_ID=0,
+  Param         : NOC_ID
+
+  -----------------------------------------------------------------------------
+  W240  (901 warnings/0 waived)
+  -----------------------------------------------------------------------------
+  Tag           : W240
+  Description   : Input '[Signal]' declared but not read.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:4464
+  Goal          : lint_rtl
+  Module        : vc_alloc_request_gen
+  FileName      : ./../../rtl/src_noc/./inout_ports.sv
+  LineNumber    : 472
+  Statement     :     input   ssa_ctrl_t  ssa_ctrl_in [P-1: 0];
+  Signal        : ssa_ctrl_in[2].ivc_granted_ovc_num[0]
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:vc_alloc_req_gen@vc_alloc_request_gen
+  -----------------------------------------------------------------------------
+  Tag           : W240
+  Description   : Input '[Signal]' declared but not read.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:4939
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 280
+  Statement     :     input   smart_ctrl_t  smart_ctrl_in;
+  Signal        : smart_ctrl_in.credit_out[0]
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[1].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[0].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag           : W240
+  Description   : Input '[Signal]' declared but not read.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:3997
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 281
+  Statement     :     input   vsa_ctrl_t  vsa_ctrl_in;
+  Signal        : vsa_ctrl_in.ovc_is_released[0]
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[1].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag           : W240
+  Description   : Input '[Signal]' declared but not read.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:4486
+  Goal          : lint_rtl
+  Module        : vc_alloc_request_gen
+  FileName      : ./../../rtl/src_noc/./inout_ports.sv
+  LineNumber    : 473
+  Statement     :     input   smart_ctrl_t  smart_ctrl_in [P-1: 0];
+  Signal        : smart_ctrl_in[2].buff_space_decreased[0]
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:vc_alloc_req_gen@vc_alloc_request_gen
+  -----------------------------------------------------------------------------
+  Tag           : W240
+  Description   : Input '[Signal]' declared but not read.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:4727
+  Goal          : lint_rtl
+  Module        : smart_bypass_chanels
+  FileName      : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber    : 332
+  Statement     :     input ivc_info_t   ivc_info    [P-1 : 0][V-1 : 0];
+  Signal        : ivc_info[0][0].assigned_ovc_not_full
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:\smart.smart_bypass @smart_bypass_chanels
+  -----------------------------------------------------------------------------
+  Tag           : W240
+  Description   : Input '[Signal]' declared but not read.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:4187
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 281
+  Statement     :     input   vsa_ctrl_t  vsa_ctrl_in;
+  Signal        : vsa_ctrl_in.buff_space_decreased[0]
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[2].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag           : W240
+  Description   : Input '[Signal]' declared but not read.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:4441
+  Goal          : lint_rtl
+  Module        : port_pre_sel_gen
+  FileName      : ./../../rtl/src_noc/./congestion_analyzer.v
+  LineNumber    : 351
+  Statement     :     input [PV-1 : 0] ovc_status;
+  Signal        : ovc_status[2:0]
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:output_ports@output_ports:port_pre_sel_top@port_pre_sel_gen
+  -----------------------------------------------------------------------------
+  Tag           : W240
+  Description   : Input '[Signal]' declared but not read.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5740
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 284
+  Statement     :     input   ctrl_chanel_t ctrl_in  [P-1 : 0];
+  Signal        : ctrl_in[2].hetero_ovc_presence[0]
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[3].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[1].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag           : W240
+  Description   : Input '[Signal]' declared but not read.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5403
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 284
+  Statement     :     input   ctrl_chanel_t ctrl_in  [P-1 : 0];
+  Signal        : ctrl_in[0].hetero_ovc_presence[0]
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[2].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[1].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag           : W240
+  Description   : Input '[Signal]' declared but not read.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:4770
+  Goal          : lint_rtl
+  Module        : smart_allocator_per_iport
+  FileName      : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber    : 579
+  Statement     :     input ivc_info_t ivc_info [V-1 : 0];
+  Signal        : ivc_info[0].flit_is_tail
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:\smart.Port_[1].smart_en.smart_allocator @smart_allocator_per_iport
+  -----------------------------------------------------------------------------
+  Tag           : W240
+  Description   : Input '[Signal]' declared but not read.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5487
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 280
+  Statement     :     input   smart_ctrl_t  smart_ctrl_in;
+  Signal        : smart_ctrl_in.mask_available_ovc[0]
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[2].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[2].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag           : W240
+  Description   : Input '[Signal]' declared but not read.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:4385
+  Goal          : lint_rtl
+  Module        : output_ports
+  FileName      : ./../../rtl/src_noc/./output_ports.sv
+  LineNumber    : 97
+  Statement     :     input  smart_ctrl_t  smart_ctrl_in [P-1: 0];
+  Signal        : smart_ctrl_in[1].ivc_reset[0]
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:output_ports@output_ports
+  -----------------------------------------------------------------------------
+  Tag           : W240
+  Description   : Input '[Signal]' declared but not read.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:4201
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 253
+  Statement     :     input   router_info_t router_info;
+  Signal        : router_info.router_id[31:0]
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[2].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag           : W240
+  Description   : Input '[Signal]' declared but not read.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:4713
+  Goal          : lint_rtl
+  Module        : smart_bypass_chanels
+  FileName      : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber    : 332
+  Statement     :     input ivc_info_t   ivc_info    [P-1 : 0][V-1 : 0];
+  Signal        : ivc_info[1][0].ivc_req
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:\smart.smart_bypass @smart_bypass_chanels
+  -----------------------------------------------------------------------------
+  Tag           : W240
+  Description   : Input '[Signal]' declared but not read.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5231
+  Goal          : lint_rtl
+  Module        : router_top
+  FileName      : ./../../rtl/src_noc/./router_top.sv
+  LineNumber    : 49
+  Statement     :     input smartflit_chanel_t chan_in [P-1 : 0];
+  Signal        : chan_in[0].smart_chanel.flit_in_bypassed
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[2].the_router @router_top
+  -----------------------------------------------------------------------------
+  Tag           : W240
+  Description   : Input '[Signal]' declared but not read.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:4578
+  Goal          : lint_rtl
+  Module        : comb_nonspec_allocator
+  FileName      : ./../../rtl/src_noc/./comb_nonspec.sv
+  LineNumber    : 73
+  Statement     :     input  ivc_info_t ivc_info [P-1 : 0][V-1 : 0]; 
+  Signal        : ivc_info[2][0].destport_one_hot[2:0]
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:router_ref@router_two_stage:vsa@combined_vc_sw_alloc:\nonspec.cmb_v1.nonspec_comb @comb_nonspec_allocator
+  -----------------------------------------------------------------------------
+  Tag           : W240
+  Description   : Input '[Signal]' declared but not read.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:4540
+  Goal          : lint_rtl
+  Module        : vc_alloc_request_gen
+  FileName      : ./../../rtl/src_noc/./inout_ports.sv
+  LineNumber    : 474
+  Statement     :     input   ivc_info_t   ivc_info    [P-1 : 0][V-1 : 0];
+  Signal        : ivc_info[0][0].single_flit_pck
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:vc_alloc_req_gen@vc_alloc_request_gen
+  -----------------------------------------------------------------------------
+  Tag           : W240
+  Description   : Input '[Signal]' declared but not read.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:4710
+  Goal          : lint_rtl
+  Module        : smart_bypass_chanels
+  FileName      : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber    : 332
+  Statement     :     input ivc_info_t   ivc_info    [P-1 : 0][V-1 : 0];
+  Signal        : ivc_info[1][0].assigned_ovc_bin[0]
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:\smart.smart_bypass @smart_bypass_chanels
+  -----------------------------------------------------------------------------
+  Tag           : W240
+  Description   : Input '[Signal]' declared but not read.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:3991
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 280
+  Statement     :     input   smart_ctrl_t  smart_ctrl_in;
+  Signal        : smart_ctrl_in.hdr_flit_req
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[1].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag           : W240
+  Description   : Input '[Signal]' declared but not read.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5731
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 280
+  Statement     :     input   smart_ctrl_t  smart_ctrl_in;
+  Signal        : smart_ctrl_in.buff_space_decreased[0]
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[3].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[1].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag           : W240
+  Description   : Input '[Signal]' declared but not read.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5272
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 282
+  Statement     :     input   ssa_ctrl_t  ssa_ctrl_in;
+  Signal        : ssa_ctrl_in.ssa_flit_wr
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[2].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[0].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag           : W240
+  Description   : Input '[Signal]' declared but not read.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5300
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 284
+  Statement     :     input   ctrl_chanel_t ctrl_in  [P-1 : 0];
+  Signal        : ctrl_in[2:0].endp_port
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[2].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[0].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag           : W240
+  Description   : Input '[Signal]' declared but not read.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:4766
+  Goal          : lint_rtl
+  Module        : smart_allocator_per_iport
+  FileName      : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber    : 579
+  Statement     :     input ivc_info_t ivc_info [V-1 : 0];
+  Signal        : ivc_info[0].dest_e_addr[1:0]
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:\smart.Port_[1].smart_en.smart_allocator @smart_allocator_per_iport
+  -----------------------------------------------------------------------------
+  Tag           : W240
+  Description   : Input '[Signal]' declared but not read.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5494
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 284
+  Statement     :     input   ctrl_chanel_t ctrl_in  [P-1 : 0];
+  Signal        : ctrl_in[1].endp_addr[1:0]
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[2].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[2].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag           : W240
+  Description   : Input '[Signal]' declared but not read.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5303
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 284
+  Statement     :     input   ctrl_chanel_t ctrl_in  [P-1 : 0];
+  Signal        : ctrl_in[0].credit_release_en[0]
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[2].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[0].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag           : W240
+  Description   : Input '[Signal]' declared but not read.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5739
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 284
+  Statement     :     input   ctrl_chanel_t ctrl_in  [P-1 : 0];
+  Signal        : ctrl_in[2].credit_release_en[0]
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[3].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[1].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag           : W240
+  Description   : Input '[Signal]' declared but not read.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:4360
+  Goal          : lint_rtl
+  Module        : output_ports
+  FileName      : ./../../rtl/src_noc/./output_ports.sv
+  LineNumber    : 96
+  Statement     :     input  ssa_ctrl_t ssa_ctrl_in [P-1: 0];
+  Signal        : ssa_ctrl_in[2].ivc_reset[0]
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:output_ports@output_ports
+  -----------------------------------------------------------------------------
+  Tag           : W240
+  Description   : Input '[Signal]' declared but not read.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5476
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 282
+  Statement     :     input   ssa_ctrl_t  ssa_ctrl_in;
+  Signal        : ssa_ctrl_in.ovc_is_allocated[0]
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[2].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[2].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag           : W240
+  Description   : Input '[Signal]' declared but not read.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:4655
+  Goal          : lint_rtl
+  Module        : smart_forward_ivc_info
+  FileName      : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber    : 224
+  Statement     :     input  ivc_info_t     ivc_info    [P-1 : 0][V-1 : 0];
+  Signal        : ivc_info[2][0].single_flit_pck
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:\smart.forward_ivc @smart_forward_ivc_info
+  -----------------------------------------------------------------------------
+  Tag           : W240
+  Description   : Input '[Signal]' declared but not read.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:3996
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 281
+  Statement     :     input   vsa_ctrl_t  vsa_ctrl_in;
+  Signal        : vsa_ctrl_in.ovc_is_allocated[0]
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[1].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag           : W240
+  Description   : Input '[Signal]' declared but not read.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5124
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 282
+  Statement     :     input   ssa_ctrl_t  ssa_ctrl_in;
+  Signal        : ssa_ctrl_in.ssa_flit_wr
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[1].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[2].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag           : W240
+  Description   : Input '[Signal]' declared but not read.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:4000
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 282
+  Statement     :     input   ssa_ctrl_t  ssa_ctrl_in;
+  Signal        : ssa_ctrl_in.ovc_is_released[0]
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[1].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag           : W240
+  Description   : Input '[Signal]' declared but not read.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:4375
+  Goal          : lint_rtl
+  Module        : output_ports
+  FileName      : ./../../rtl/src_noc/./output_ports.sv
+  LineNumber    : 97
+  Statement     :     input  smart_ctrl_t  smart_ctrl_in [P-1: 0];
+  Signal        : smart_ctrl_in[2].ivc_num_getting_ovc_grant[0]
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:output_ports@output_ports
+  -----------------------------------------------------------------------------
+  Tag           : W240
+  Description   : Input '[Signal]' declared but not read.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:4514
+  Goal          : lint_rtl
+  Module        : vc_alloc_request_gen
+  FileName      : ./../../rtl/src_noc/./inout_ports.sv
+  LineNumber    : 473
+  Statement     :     input   smart_ctrl_t  smart_ctrl_in [P-1: 0];
+  Signal        : smart_ctrl_in[0].ivc_single_flit_pck[0]
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:vc_alloc_req_gen@vc_alloc_request_gen
+  -----------------------------------------------------------------------------
+  Tag           : W240
+  Description   : Input '[Signal]' declared but not read.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5725
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 282
+  Statement     :     input   ssa_ctrl_t  ssa_ctrl_in;
+  Signal        : ssa_ctrl_in.buff_space_decreased[0]
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[3].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[1].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag           : W240
+  Description   : Input '[Signal]' declared but not read.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5623
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 281
+  Statement     :     input   vsa_ctrl_t  vsa_ctrl_in;
+  Signal        : vsa_ctrl_in.buff_space_decreased[0]
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[3].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[0].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag           : W240
+  Description   : Input '[Signal]' declared but not read.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:4387
+  Goal          : lint_rtl
+  Module        : output_ports
+  FileName      : ./../../rtl/src_noc/./output_ports.sv
+  LineNumber    : 97
+  Statement     :     input  smart_ctrl_t  smart_ctrl_in [P-1: 0];
+  Signal        : smart_ctrl_in[1].ivc_single_flit_pck[0]
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:output_ports@output_ports
+  -----------------------------------------------------------------------------
+  Tag           : W240
+  Description   : Input '[Signal]' declared but not read.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:4422
+  Goal          : lint_rtl
+  Module        : output_ports
+  FileName      : ./../../rtl/src_noc/./output_ports.sv
+  LineNumber    : 94
+  Statement     :     input  ivc_info_t ivc_info [P-1 : 0][V-1 : 0]; 
+  Signal        : ivc_info[0][0].destport_one_hot[2:0]
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:output_ports@output_ports
+  -----------------------------------------------------------------------------
+  Tag           : W240
+  Description   : Input '[Signal]' declared but not read.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:4548
+  Goal          : lint_rtl
+  Module        : vc_alloc_request_gen
+  FileName      : ./../../rtl/src_noc/./inout_ports.sv
+  LineNumber    : 475
+  Statement     :     input   ctrl_chanel_t ctrl_in  [P-1 : 0];
+  Signal        : ctrl_in[1].hetero_ovc_presence[0]
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:vc_alloc_req_gen@vc_alloc_request_gen
+  -----------------------------------------------------------------------------
+  Tag           : W240
+  Description   : Input '[Signal]' declared but not read.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5048
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 284
+  Statement     :     input   ctrl_chanel_t ctrl_in  [P-1 : 0];
+  Signal        : ctrl_in[2].hetero_ovc_presence[0]
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[1].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[1].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag           : W240
+  Description   : Input '[Signal]' declared but not read.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:4407
+  Goal          : lint_rtl
+  Module        : output_ports
+  FileName      : ./../../rtl/src_noc/./output_ports.sv
+  LineNumber    : 94
+  Statement     :     input  ivc_info_t ivc_info [P-1 : 0][V-1 : 0]; 
+  Signal        : ivc_info[2][0].candidate_ovc[0]
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:output_ports@output_ports
+  -----------------------------------------------------------------------------
+  Tag           : W240
+  Description   : Input '[Signal]' declared but not read.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:4841
+  Goal          : lint_rtl
+  Module        : smart_allocator_per_iport
+  FileName      : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber    : 584
+  Statement     :     input smart_chanel_t ss_smart_chanel_new;
+  Signal        : ss_smart_chanel_new.bypassed_num[1:0]
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:\smart.Port_[2].smart_en.smart_allocator @smart_allocator_per_iport
+  -----------------------------------------------------------------------------
+  Tag           : W240
+  Description   : Input '[Signal]' declared but not read.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5388
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 280
+  Statement     :     input   smart_ctrl_t  smart_ctrl_in;
+  Signal        : smart_ctrl_in.mask_available_ovc[0]
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[2].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[1].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag           : W240
+  Description   : Input '[Signal]' declared but not read.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5046
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 284
+  Statement     :     input   ctrl_chanel_t ctrl_in  [P-1 : 0];
+  Signal        : ctrl_in[2].router_addr[1:0]
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[1].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[1].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag           : W240
+  Description   : Input '[Signal]' declared but not read.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:4146
+  Goal          : lint_rtl
+  Module        : look_ahead_routing
+  FileName      : ./../../rtl/src_noc/./routing.v
+  LineNumber    : 279
+  Statement     :     input   [EAw-1   :   0]  src_e_addr;
+  Signal        : src_e_addr[1:0]
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[1].the_input_queue_per_port @input_queue_per_port:\unicast.lk_routing @look_ahead_routing
+  -----------------------------------------------------------------------------
+  Tag           : W240
+  Description   : Input '[Signal]' declared but not read.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5644
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 284
+  Statement     :     input   ctrl_chanel_t ctrl_in  [P-1 : 0];
+  Signal        : ctrl_in[1].credit_release_en[0]
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[3].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[0].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag           : W240
+  Description   : Input '[Signal]' declared but not read.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:3723
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 284
+  Statement     :     input   ctrl_chanel_t ctrl_in  [P-1 : 0];
+  Signal        : ctrl_in[0].credit_release_en[0]
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[0].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag           : W240
+  Description   : Input '[Signal]' declared but not read.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:4591
+  Goal          : lint_rtl
+  Module        : comb_nonspec_allocator
+  FileName      : ./../../rtl/src_noc/./comb_nonspec.sv
+  LineNumber    : 73
+  Statement     :     input  ivc_info_t ivc_info [P-1 : 0][V-1 : 0]; 
+  Signal        : ivc_info[1][0].class_num[0]
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:router_ref@router_two_stage:vsa@combined_vc_sw_alloc:\nonspec.cmb_v1.nonspec_comb @comb_nonspec_allocator
+  -----------------------------------------------------------------------------
+  Tag           : W240
+  Description   : Input '[Signal]' declared but not read.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:4196
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 280
+  Statement     :     input   smart_ctrl_t  smart_ctrl_in;
+  Signal        : smart_ctrl_in.buff_space_decreased[0]
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[2].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag           : W240
+  Description   : Input '[Signal]' declared but not read.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:4515
+  Goal          : lint_rtl
+  Module        : vc_alloc_request_gen
+  FileName      : ./../../rtl/src_noc/./inout_ports.sv
+  LineNumber    : 473
+  Statement     :     input   smart_ctrl_t  smart_ctrl_in [P-1: 0];
+  Signal        : smart_ctrl_in[0].ovc_single_flit_pck[0]
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:vc_alloc_req_gen@vc_alloc_request_gen
+  -----------------------------------------------------------------------------
+  Tag           : W240
+  Description   : Input '[Signal]' declared but not read.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:4688
+  Goal          : lint_rtl
+  Module        : smart_bypass_chanels
+  FileName      : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber    : 331
+  Statement     :     input smart_chanel_t smart_chanel_in   [P-1 : 0];
+  Signal        : smart_chanel_in[0].dest_e_addr[1:0]
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:\smart.smart_bypass @smart_bypass_chanels
+  -----------------------------------------------------------------------------
+  Tag           : W240
+  Description   : Input '[Signal]' declared but not read.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:4583
+  Goal          : lint_rtl
+  Module        : comb_nonspec_allocator
+  FileName      : ./../../rtl/src_noc/./comb_nonspec.sv
+  LineNumber    : 73
+  Statement     :     input  ivc_info_t ivc_info [P-1 : 0][V-1 : 0]; 
+  Signal        : ivc_info[2][0].single_flit_pck
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:router_ref@router_two_stage:vsa@combined_vc_sw_alloc:\nonspec.cmb_v1.nonspec_comb @comb_nonspec_allocator
+  -----------------------------------------------------------------------------
+  Tag           : W240
+  Description   : Input '[Signal]' declared but not read.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:4859
+  Goal          : lint_rtl
+  Module        : smart_allocator_per_iport
+  FileName      : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber    : 577
+  Statement     :     input flit_chanel_t flit_chanel_i;
+  Signal        : flit_chanel_i.flit.payload[63:0]
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:\smart.Port_[2].smart_en.smart_allocator @smart_allocator_per_iport
+  -----------------------------------------------------------------------------
+  Tag           : W240
+  Description   : Input '[Signal]' declared but not read.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5818
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 280
+  Statement     :     input   smart_ctrl_t  smart_ctrl_in;
+  Signal        : smart_ctrl_in.smart_en
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[3].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[2].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag           : W240
+  Description   : Input '[Signal]' declared but not read.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:4147
+  Goal          : lint_rtl
+  Module        : look_ahead_routing
+  FileName      : ./../../rtl/src_noc/./routing.v
+  LineNumber    : 276
+  Statement     :     input   [PRAw-1:  0]  neighbors_r_addr;
+  Signal        : neighbors_r_addr[5:0]
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[1].the_input_queue_per_port @input_queue_per_port:\unicast.lk_routing @look_ahead_routing
+  -----------------------------------------------------------------------------
+  Tag           : W240
+  Description   : Input '[Signal]' declared but not read.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5132
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 282
+  Statement     :     input   ssa_ctrl_t  ssa_ctrl_in;
+  Signal        : ssa_ctrl_in.buff_space_decreased[0]
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[1].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[2].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag           : W240
+  Description   : Input '[Signal]' declared but not read.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:4659
+  Goal          : lint_rtl
+  Module        : smart_forward_ivc_info
+  FileName      : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber    : 224
+  Statement     :     input  ivc_info_t     ivc_info    [P-1 : 0][V-1 : 0];
+  Signal        : ivc_info[1][0].assigned_ovc_not_full
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:\smart.forward_ivc @smart_forward_ivc_info
+  -----------------------------------------------------------------------------
+  Tag           : W240
+  Description   : Input '[Signal]' declared but not read.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:4849
+  Goal          : lint_rtl
+  Module        : smart_allocator_per_iport
+  FileName      : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber    : 579
+  Statement     :     input ivc_info_t ivc_info [V-1 : 0];
+  Signal        : ivc_info[0].assigned_ovc_bin[0]
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:\smart.Port_[2].smart_en.smart_allocator @smart_allocator_per_iport
+  -----------------------------------------------------------------------------
+  Tag           : W240
+  Description   : Input '[Signal]' declared but not read.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5138
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 280
+  Statement     :     input   smart_ctrl_t  smart_ctrl_in;
+  Signal        : smart_ctrl_in.buff_space_decreased[0]
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[1].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[2].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag           : W240
+  Description   : Input '[Signal]' declared but not read.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:4190
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 282
+  Statement     :     input   ssa_ctrl_t  ssa_ctrl_in;
+  Signal        : ssa_ctrl_in.buff_space_decreased[0]
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[2].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag           : W240
+  Description   : Input '[Signal]' declared but not read.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5153
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 284
+  Statement     :     input   ctrl_chanel_t ctrl_in  [P-1 : 0];
+  Signal        : ctrl_in[0].endp_addr[1:0]
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[1].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[2].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag           : W240
+  Description   : Input '[Signal]' declared but not read.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:4412
+  Goal          : lint_rtl
+  Module        : output_ports
+  FileName      : ./../../rtl/src_noc/./output_ports.sv
+  LineNumber    : 94
+  Statement     :     input  ivc_info_t ivc_info [P-1 : 0][V-1 : 0]; 
+  Signal        : ivc_info[1][0].destport_one_hot[2:0]
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:output_ports@output_ports
+  -----------------------------------------------------------------------------
+  Tag           : W240
+  Description   : Input '[Signal]' declared but not read.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5640
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 284
+  Statement     :     input   ctrl_chanel_t ctrl_in  [P-1 : 0];
+  Signal        : ctrl_in[2].credit_release_en[0]
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[3].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[0].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag           : W240
+  Description   : Input '[Signal]' declared but not read.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:4669
+  Goal          : lint_rtl
+  Module        : smart_forward_ivc_info
+  FileName      : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber    : 224
+  Statement     :     input  ivc_info_t     ivc_info    [P-1 : 0][V-1 : 0];
+  Signal        : ivc_info[0][0].single_flit_pck
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:\smart.forward_ivc @smart_forward_ivc_info
+  -----------------------------------------------------------------------------
+  Tag           : W240
+  Description   : Input '[Signal]' declared but not read.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:3722
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 284
+  Statement     :     input   ctrl_chanel_t ctrl_in  [P-1 : 0];
+  Signal        : ctrl_in[0].router_addr[1:0]
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[0].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag           : W240
+  Description   : Input '[Signal]' declared but not read.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:3705
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 280
+  Statement     :     input   smart_ctrl_t  smart_ctrl_in;
+  Signal        : smart_ctrl_in.credit_out[0]
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[0].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag           : W240
+  Description   : Input '[Signal]' declared but not read.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:4404
+  Goal          : lint_rtl
+  Module        : output_ports
+  FileName      : ./../../rtl/src_noc/./output_ports.sv
+  LineNumber    : 94
+  Statement     :     input  ivc_info_t ivc_info [P-1 : 0][V-1 : 0]; 
+  Signal        : ivc_info[2][0].ivc_req
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:output_ports@output_ports
+  -----------------------------------------------------------------------------
+  Tag           : W240
+  Description   : Input '[Signal]' declared but not read.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:4724
+  Goal          : lint_rtl
+  Module        : smart_bypass_chanels
+  FileName      : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber    : 332
+  Statement     :     input ivc_info_t   ivc_info    [P-1 : 0][V-1 : 0];
+  Signal        : ivc_info[0][0].dest_port_encoded[1:0]
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:\smart.smart_bypass @smart_bypass_chanels
+  -----------------------------------------------------------------------------
+  Tag           : W240
+  Description   : Input '[Signal]' declared but not read.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:4141
+  Goal          : lint_rtl
+  Module        : line_ring_destp_decoder
+  FileName      : ./../../rtl/src_noc/./mesh_torus.sv
+  LineNumber    : 1306
+  Statement     :     input  [ELw-1 : 0] endp_localp_num;
+  Signal        : endp_localp_num[0]
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[1].the_input_queue_per_port @input_queue_per_port:\V_[0].decoder @destp_generator:\mesh.destp_generator @mesh_torus_destp_generator:\one_D.decoder @line_ring_destp_decoder
+  -----------------------------------------------------------------------------
+  Tag           : W240
+  Description   : Input '[Signal]' declared but not read.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:4207
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 284
+  Statement     :     input   ctrl_chanel_t ctrl_in  [P-1 : 0];
+  Signal        : ctrl_in[1].router_addr[1:0]
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[2].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag           : W240
+  Description   : Input '[Signal]' declared but not read.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5493
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 284
+  Statement     :     input   ctrl_chanel_t ctrl_in  [P-1 : 0];
+  Signal        : ctrl_in[2].hetero_ovc_presence[0]
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[2].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[2].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag           : W240
+  Description   : Input '[Signal]' declared but not read.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5501
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 284
+  Statement     :     input   ctrl_chanel_t ctrl_in  [P-1 : 0];
+  Signal        : ctrl_in[0].credit_release_en[0]
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[2].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[2].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag           : W240
+  Description   : Input '[Signal]' declared but not read.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:4512
+  Goal          : lint_rtl
+  Module        : vc_alloc_request_gen
+  FileName      : ./../../rtl/src_noc/./inout_ports.sv
+  LineNumber    : 473
+  Statement     :     input   smart_ctrl_t  smart_ctrl_in [P-1: 0];
+  Signal        : smart_ctrl_in[0].ovc_is_released[0]
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:vc_alloc_req_gen@vc_alloc_request_gen
+  -----------------------------------------------------------------------------
+  Tag           : W240
+  Description   : Input '[Signal]' declared but not read.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:3706
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 280
+  Statement     :     input   smart_ctrl_t  smart_ctrl_in;
+  Signal        : smart_ctrl_in.buff_space_decreased[0]
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[0].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag           : W240
+  Description   : Input '[Signal]' declared but not read.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:3720
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 284
+  Statement     :     input   ctrl_chanel_t ctrl_in  [P-1 : 0];
+  Signal        : ctrl_in[2:0].endp_port
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[0].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag           : W240
+  Description   : Input '[Signal]' declared but not read.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:3691
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 280
+  Statement     :     input   smart_ctrl_t  smart_ctrl_in;
+  Signal        : smart_ctrl_in.smart_en
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[0].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag           : W240
+  Description   : Input '[Signal]' declared but not read.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5626
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 282
+  Statement     :     input   ssa_ctrl_t  ssa_ctrl_in;
+  Signal        : ssa_ctrl_in.buff_space_decreased[0]
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[3].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[0].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag           : W240
+  Description   : Input '[Signal]' declared but not read.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:4463
+  Goal          : lint_rtl
+  Module        : vc_alloc_request_gen
+  FileName      : ./../../rtl/src_noc/./inout_ports.sv
+  LineNumber    : 472
+  Statement     :     input   ssa_ctrl_t  ssa_ctrl_in [P-1: 0];
+  Signal        : ssa_ctrl_in[2].ovc_single_flit_pck[0]
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:vc_alloc_req_gen@vc_alloc_request_gen
+  -----------------------------------------------------------------------------
+  Tag           : W240
+  Description   : Input '[Signal]' declared but not read.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5304
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 284
+  Statement     :     input   ctrl_chanel_t ctrl_in  [P-1 : 0];
+  Signal        : ctrl_in[0].hetero_ovc_presence[0]
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[2].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[0].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag           : W240
+  Description   : Input '[Signal]' declared but not read.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5625
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 282
+  Statement     :     input   ssa_ctrl_t  ssa_ctrl_in;
+  Signal        : ssa_ctrl_in.ovc_is_released[0]
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[3].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[0].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag           : W240
+  Description   : Input '[Signal]' declared but not read.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:4860
+  Goal          : lint_rtl
+  Module        : smart_allocator_per_iport
+  FileName      : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber    : 577
+  Statement     :     input flit_chanel_t flit_chanel_i;
+  Signal        : flit_chanel_i.congestion[2:0]
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:\smart.Port_[2].smart_en.smart_allocator @smart_allocator_per_iport
+  -----------------------------------------------------------------------------
+  Tag           : W240
+  Description   : Input '[Signal]' declared but not read.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:4927
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 269
+  Statement     :     input   [DSTPw-1 : 0] destport_clear [V-1 : 0];
+  Signal        : destport_clear
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[1].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[0].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag           : W240
+  Description   : Input '[Signal]' declared but not read.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:4181
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 280
+  Statement     :     input   smart_ctrl_t  smart_ctrl_in;
+  Signal        : smart_ctrl_in.smart_en
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[2].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag           : W240
+  Description   : Input '[Signal]' declared but not read.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5230
+  Goal          : lint_rtl
+  Module        : router_top
+  FileName      : ./../../rtl/src_noc/./router_top.sv
+  LineNumber    : 49
+  Statement     :     input smartflit_chanel_t chan_in [P-1 : 0];
+  Signal        : chan_in[0].smart_chanel.hdr_flit
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[2].the_router @router_top
+  -----------------------------------------------------------------------------
+  Tag           : W240
+  Description   : Input '[Signal]' declared but not read.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:4687
+  Goal          : lint_rtl
+  Module        : smart_bypass_chanels
+  FileName      : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber    : 331
+  Statement     :     input smart_chanel_t smart_chanel_in   [P-1 : 0];
+  Signal        : smart_chanel_in[0].ovc[0]
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:\smart.smart_bypass @smart_bypass_chanels
+  -----------------------------------------------------------------------------
+  Tag           : W240
+  Description   : Input '[Signal]' declared but not read.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:4858
+  Goal          : lint_rtl
+  Module        : smart_allocator_per_iport
+  FileName      : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber    : 577
+  Statement     :     input flit_chanel_t flit_chanel_i;
+  Signal        : flit_chanel_i.flit.vc[0]
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:\smart.Port_[2].smart_en.smart_allocator @smart_allocator_per_iport
+  -----------------------------------------------------------------------------
+  Tag           : W240
+  Description   : Input '[Signal]' declared but not read.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:4956
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 284
+  Statement     :     input   ctrl_chanel_t ctrl_in  [P-1 : 0];
+  Signal        : ctrl_in[0].router_addr[1:0]
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[1].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[0].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag           : W240
+  Description   : Input '[Signal]' declared but not read.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5838
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 253
+  Statement     :     input   router_info_t router_info;
+  Signal        : router_info.router_id[31:0]
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[3].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[2].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag           : W240
+  Description   : Input '[Signal]' declared but not read.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:4924
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 280
+  Statement     :     input   smart_ctrl_t  smart_ctrl_in;
+  Signal        : smart_ctrl_in.hdr_flit_req
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[1].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[0].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag           : W240
+  Description   : Input '[Signal]' declared but not read.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:4695
+  Goal          : lint_rtl
+  Module        : smart_bypass_chanels
+  FileName      : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber    : 332
+  Statement     :     input ivc_info_t   ivc_info    [P-1 : 0][V-1 : 0];
+  Signal        : ivc_info[2][0].dest_e_addr[1:0]
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:\smart.smart_bypass @smart_bypass_chanels
+  -----------------------------------------------------------------------------
+  Tag           : W240
+  Description   : Input '[Signal]' declared but not read.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:4656
+  Goal          : lint_rtl
+  Module        : smart_forward_ivc_info
+  FileName      : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber    : 224
+  Statement     :     input  ivc_info_t     ivc_info    [P-1 : 0][V-1 : 0];
+  Signal        : ivc_info[1][0].assigned_ovc_num[0]
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:\smart.forward_ivc @smart_forward_ivc_info
+  -----------------------------------------------------------------------------
+  Tag           : W240
+  Description   : Input '[Signal]' declared but not read.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5042
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 280
+  Statement     :     input   smart_ctrl_t  smart_ctrl_in;
+  Signal        : smart_ctrl_in.mask_available_ovc[0]
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[1].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[1].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag           : W240
+  Description   : Input '[Signal]' declared but not read.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:4349
+  Goal          : lint_rtl
+  Module        : output_ports
+  FileName      : ./../../rtl/src_noc/./output_ports.sv
+  LineNumber    : 95
+  Statement     :     input  vsa_ctrl_t vsa_ctrl_in [P-1: 0];
+  Signal        : vsa_ctrl_in[2].ivc_granted_ovc_num[0]
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:output_ports@output_ports
+  -----------------------------------------------------------------------------
+  Tag           : W240
+  Description   : Input '[Signal]' declared but not read.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5484
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 280
+  Statement     :     input   smart_ctrl_t  smart_ctrl_in;
+  Signal        : smart_ctrl_in.buff_space_decreased[0]
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[2].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[2].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag           : W240
+  Description   : Input '[Signal]' declared but not read.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5290
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 280
+  Statement     :     input   smart_ctrl_t  smart_ctrl_in;
+  Signal        : smart_ctrl_in.ovc_single_flit_pck[0]
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[2].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[0].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag           : W240
+  Description   : Input '[Signal]' declared but not read.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:4467
+  Goal          : lint_rtl
+  Module        : vc_alloc_request_gen
+  FileName      : ./../../rtl/src_noc/./inout_ports.sv
+  LineNumber    : 472
+  Statement     :     input   ssa_ctrl_t  ssa_ctrl_in [P-1: 0];
+  Signal        : ssa_ctrl_in[1].ivc_num_getting_sw_grant[0]
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:vc_alloc_req_gen@vc_alloc_request_gen
+  -----------------------------------------------------------------------------
+  Tag           : W240
+  Description   : Input '[Signal]' declared but not read.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:4012
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 253
+  Statement     :     input   router_info_t router_info;
+  Signal        : router_info.router_id[31:0]
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[1].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag           : W240
+  Description   : Input '[Signal]' declared but not read.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:4586
+  Goal          : lint_rtl
+  Module        : comb_nonspec_allocator
+  FileName      : ./../../rtl/src_noc/./comb_nonspec.sv
+  LineNumber    : 73
+  Statement     :     input  ivc_info_t ivc_info [P-1 : 0][V-1 : 0]; 
+  Signal        : ivc_info[1][0].assigned_ovc_bin[0]
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:router_ref@router_two_stage:vsa@combined_vc_sw_alloc:\nonspec.cmb_v1.nonspec_comb @comb_nonspec_allocator
+  -----------------------------------------------------------------------------
+  Tag           : W240
+  Description   : Input '[Signal]' declared but not read.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5630
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 280
+  Statement     :     input   smart_ctrl_t  smart_ctrl_in;
+  Signal        : smart_ctrl_in.destport[1:0]
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[3].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[0].the_input_queue_per_port @input_queue_per_port
+  -----------------------------------------------------------------------------
+  Tag           : W240
+  Description   : Input '[Signal]' declared but not read.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5843
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 284
+  Statement     :     input   ctrl_chanel_t ctrl_in  [P-1 : 0];
+  Signal        : ctrl_in[1].endp_addr[1:0]
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[3].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[2].the_input_queue_per_port @input_queue_per_port
+
+  -----------------------------------------------------------------------------
+  W241  (24 warnings/0 waived)
+  -----------------------------------------------------------------------------
+  Tag           : W241
+  Description   : Output '[Signal]' is never set.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:4891
+  Goal          : lint_rtl
+  Module        : router_top
+  FileName      : ./../../rtl/src_noc/./router_top.sv
+  LineNumber    : 50
+  Statement     :     output smartflit_chanel_t chan_out [P-1 : 0];
+  Signal        : chan_out[0].smart_chanel.bypassed_num[1:0]
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[1].the_router @router_top
+  -----------------------------------------------------------------------------
+  Tag           : W241
+  Description   : Output '[Signal]' is never set.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5233
+  Goal          : lint_rtl
+  Module        : router_top
+  FileName      : ./../../rtl/src_noc/./router_top.sv
+  LineNumber    : 50
+  Statement     :     output smartflit_chanel_t chan_out [P-1 : 0];
+  Signal        : chan_out[0].smart_chanel.ovc[0]
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[2].the_router @router_top
+  -----------------------------------------------------------------------------
+  Tag           : W241
+  Description   : Output '[Signal]' is never set.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:4890
+  Goal          : lint_rtl
+  Module        : router_top
+  FileName      : ./../../rtl/src_noc/./router_top.sv
+  LineNumber    : 50
+  Statement     :     output smartflit_chanel_t chan_out [P-1 : 0];
+  Signal        : chan_out[0].smart_chanel.flit_in_bypassed
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[1].the_router @router_top
+  -----------------------------------------------------------------------------
+  Tag           : W241
+  Description   : Output '[Signal]' is never set.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5583
+  Goal          : lint_rtl
+  Module        : router_top
+  FileName      : ./../../rtl/src_noc/./router_top.sv
+  LineNumber    : 50
+  Statement     :     output smartflit_chanel_t chan_out [P-1 : 0];
+  Signal        : chan_out[0].smart_chanel.bypassed_num[1:0]
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[3].the_router @router_top
+  -----------------------------------------------------------------------------
+  Tag           : W241
+  Description   : Output '[Signal]' is never set.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:3647
+  Goal          : lint_rtl
+  Module        : router_top
+  FileName      : ./../../rtl/src_noc/./router_top.sv
+  LineNumber    : 50
+  Statement     :     output smartflit_chanel_t chan_out [P-1 : 0];
+  Signal        : chan_out[0].smart_chanel.requests[2:0]
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top
+  -----------------------------------------------------------------------------
+  Tag           : W241
+  Description   : Output '[Signal]' is never set.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5582
+  Goal          : lint_rtl
+  Module        : router_top
+  FileName      : ./../../rtl/src_noc/./router_top.sv
+  LineNumber    : 50
+  Statement     :     output smartflit_chanel_t chan_out [P-1 : 0];
+  Signal        : chan_out[0].smart_chanel.flit_in_bypassed
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[3].the_router @router_top
+  -----------------------------------------------------------------------------
+  Tag           : W241
+  Description   : Output '[Signal]' is never set.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5235
+  Goal          : lint_rtl
+  Module        : router_top
+  FileName      : ./../../rtl/src_noc/./router_top.sv
+  LineNumber    : 50
+  Statement     :     output smartflit_chanel_t chan_out [P-1 : 0];
+  Signal        : chan_out[0].smart_chanel.hdr_flit
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[2].the_router @router_top
+  -----------------------------------------------------------------------------
+  Tag           : W241
+  Description   : Output '[Signal]' is never set.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5578
+  Goal          : lint_rtl
+  Module        : router_top
+  FileName      : ./../../rtl/src_noc/./router_top.sv
+  LineNumber    : 50
+  Statement     :     output smartflit_chanel_t chan_out [P-1 : 0];
+  Signal        : chan_out[0].smart_chanel.requests[2:0]
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[3].the_router @router_top
+  -----------------------------------------------------------------------------
+  Tag           : W241
+  Description   : Output '[Signal]' is never set.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5232
+  Goal          : lint_rtl
+  Module        : router_top
+  FileName      : ./../../rtl/src_noc/./router_top.sv
+  LineNumber    : 50
+  Statement     :     output smartflit_chanel_t chan_out [P-1 : 0];
+  Signal        : chan_out[0].smart_chanel.requests[2:0]
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[2].the_router @router_top
+  -----------------------------------------------------------------------------
+  Tag           : W241
+  Description   : Output '[Signal]' is never set.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:3650
+  Goal          : lint_rtl
+  Module        : router_top
+  FileName      : ./../../rtl/src_noc/./router_top.sv
+  LineNumber    : 50
+  Statement     :     output smartflit_chanel_t chan_out [P-1 : 0];
+  Signal        : chan_out[0].smart_chanel.hdr_flit
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top
+  -----------------------------------------------------------------------------
+  Tag           : W241
+  Description   : Output '[Signal]' is never set.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5581
+  Goal          : lint_rtl
+  Module        : router_top
+  FileName      : ./../../rtl/src_noc/./router_top.sv
+  LineNumber    : 50
+  Statement     :     output smartflit_chanel_t chan_out [P-1 : 0];
+  Signal        : chan_out[0].smart_chanel.hdr_flit
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[3].the_router @router_top
+  -----------------------------------------------------------------------------
+  Tag           : W241
+  Description   : Output '[Signal]' is never set.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5236
+  Goal          : lint_rtl
+  Module        : router_top
+  FileName      : ./../../rtl/src_noc/./router_top.sv
+  LineNumber    : 50
+  Statement     :     output smartflit_chanel_t chan_out [P-1 : 0];
+  Signal        : chan_out[0].smart_chanel.flit_in_bypassed
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[2].the_router @router_top
+  -----------------------------------------------------------------------------
+  Tag           : W241
+  Description   : Output '[Signal]' is never set.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:3652
+  Goal          : lint_rtl
+  Module        : router_top
+  FileName      : ./../../rtl/src_noc/./router_top.sv
+  LineNumber    : 50
+  Statement     :     output smartflit_chanel_t chan_out [P-1 : 0];
+  Signal        : chan_out[0].smart_chanel.bypassed_num[1:0]
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top
+  -----------------------------------------------------------------------------
+  Tag           : W241
+  Description   : Output '[Signal]' is never set.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:3651
+  Goal          : lint_rtl
+  Module        : router_top
+  FileName      : ./../../rtl/src_noc/./router_top.sv
+  LineNumber    : 50
+  Statement     :     output smartflit_chanel_t chan_out [P-1 : 0];
+  Signal        : chan_out[0].smart_chanel.flit_in_bypassed
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top
+  -----------------------------------------------------------------------------
+  Tag           : W241
+  Description   : Output '[Signal]' is never set.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:3649
+  Goal          : lint_rtl
+  Module        : router_top
+  FileName      : ./../../rtl/src_noc/./router_top.sv
+  LineNumber    : 50
+  Statement     :     output smartflit_chanel_t chan_out [P-1 : 0];
+  Signal        : chan_out[0].smart_chanel.dest_e_addr[1:0]
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top
+  -----------------------------------------------------------------------------
+  Tag           : W241
+  Description   : Output '[Signal]' is never set.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:4888
+  Goal          : lint_rtl
+  Module        : router_top
+  FileName      : ./../../rtl/src_noc/./router_top.sv
+  LineNumber    : 50
+  Statement     :     output smartflit_chanel_t chan_out [P-1 : 0];
+  Signal        : chan_out[0].smart_chanel.dest_e_addr[1:0]
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[1].the_router @router_top
+  -----------------------------------------------------------------------------
+  Tag           : W241
+  Description   : Output '[Signal]' is never set.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5234
+  Goal          : lint_rtl
+  Module        : router_top
+  FileName      : ./../../rtl/src_noc/./router_top.sv
+  LineNumber    : 50
+  Statement     :     output smartflit_chanel_t chan_out [P-1 : 0];
+  Signal        : chan_out[0].smart_chanel.dest_e_addr[1:0]
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[2].the_router @router_top
+  -----------------------------------------------------------------------------
+  Tag           : W241
+  Description   : Output '[Signal]' is never set.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:4886
+  Goal          : lint_rtl
+  Module        : router_top
+  FileName      : ./../../rtl/src_noc/./router_top.sv
+  LineNumber    : 50
+  Statement     :     output smartflit_chanel_t chan_out [P-1 : 0];
+  Signal        : chan_out[0].smart_chanel.requests[2:0]
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[1].the_router @router_top
+  -----------------------------------------------------------------------------
+  Tag           : W241
+  Description   : Output '[Signal]' is never set.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5237
+  Goal          : lint_rtl
+  Module        : router_top
+  FileName      : ./../../rtl/src_noc/./router_top.sv
+  LineNumber    : 50
+  Statement     :     output smartflit_chanel_t chan_out [P-1 : 0];
+  Signal        : chan_out[0].smart_chanel.bypassed_num[1:0]
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[2].the_router @router_top
+  -----------------------------------------------------------------------------
+  Tag           : W241
+  Description   : Output '[Signal]' is never set.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:4887
+  Goal          : lint_rtl
+  Module        : router_top
+  FileName      : ./../../rtl/src_noc/./router_top.sv
+  LineNumber    : 50
+  Statement     :     output smartflit_chanel_t chan_out [P-1 : 0];
+  Signal        : chan_out[0].smart_chanel.ovc[0]
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[1].the_router @router_top
+  -----------------------------------------------------------------------------
+  Tag           : W241
+  Description   : Output '[Signal]' is never set.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:3648
+  Goal          : lint_rtl
+  Module        : router_top
+  FileName      : ./../../rtl/src_noc/./router_top.sv
+  LineNumber    : 50
+  Statement     :     output smartflit_chanel_t chan_out [P-1 : 0];
+  Signal        : chan_out[0].smart_chanel.ovc[0]
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top
+  -----------------------------------------------------------------------------
+  Tag           : W241
+  Description   : Output '[Signal]' is never set.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5579
+  Goal          : lint_rtl
+  Module        : router_top
+  FileName      : ./../../rtl/src_noc/./router_top.sv
+  LineNumber    : 50
+  Statement     :     output smartflit_chanel_t chan_out [P-1 : 0];
+  Signal        : chan_out[0].smart_chanel.ovc[0]
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[3].the_router @router_top
+  -----------------------------------------------------------------------------
+  Tag           : W241
+  Description   : Output '[Signal]' is never set.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:4889
+  Goal          : lint_rtl
+  Module        : router_top
+  FileName      : ./../../rtl/src_noc/./router_top.sv
+  LineNumber    : 50
+  Statement     :     output smartflit_chanel_t chan_out [P-1 : 0];
+  Signal        : chan_out[0].smart_chanel.hdr_flit
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[1].the_router @router_top
+  -----------------------------------------------------------------------------
+  Tag           : W241
+  Description   : Output '[Signal]' is never set.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5580
+  Goal          : lint_rtl
+  Module        : router_top
+  FileName      : ./../../rtl/src_noc/./router_top.sv
+  LineNumber    : 50
+  Statement     :     output smartflit_chanel_t chan_out [P-1 : 0];
+  Signal        : chan_out[0].smart_chanel.dest_e_addr[1:0]
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[3].the_router @router_top
+
+  -----------------------------------------------------------------------------
+  W287a  (32 warnings/0 waived)
+  -----------------------------------------------------------------------------
+  Tag           : W287a
+  Description   : Input '[Signal]' of instance '[InstName]' is undriven.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:4897
+  Goal          : lint_rtl
+  Module        : router_top
+  FileName      : ./../../rtl/src_noc/./router_top.sv
+  LineNumber    : 149
+  Statement     :             .smart_chanel_in(smart_chanel_in),
+  Signal        : smart_chanel_in[0].bypassed_num[1:0]
+  InstName      : smart_bypass
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[1].the_router @router_top
+  -----------------------------------------------------------------------------
+  Tag           : W287a
+  Description   : Input '[Signal]' of instance '[InstName]' is undriven.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:3655
+  Goal          : lint_rtl
+  Module        : router_top
+  FileName      : ./../../rtl/src_noc/./router_top.sv
+  LineNumber    : 149
+  Statement     :             .smart_chanel_in(smart_chanel_in),
+  Signal        : smart_chanel_in[0].dest_e_addr[1:0]
+  InstName      : smart_bypass
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top
+  -----------------------------------------------------------------------------
+  Tag           : W287a
+  Description   : Input '[Signal]' of instance '[InstName]' is undriven.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:3621
+  Goal          : lint_rtl
+  Module        : mesh_torus_noc_top
+  FileName      : ./../../rtl/src_noc/./mesh_torus_noc_top.sv
+  LineNumber    : 71
+  Statement     :                 .router_config_in(router_config_in[RID]),                
+  Signal        : router_config_in[2].endp_addrs[1:0]
+  InstName      : the_router
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top
+  -----------------------------------------------------------------------------
+  Tag           : W287a
+  Description   : Input '[Signal]' of instance '[InstName]' is undriven.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5241
+  Goal          : lint_rtl
+  Module        : router_top
+  FileName      : ./../../rtl/src_noc/./router_top.sv
+  LineNumber    : 149
+  Statement     :             .smart_chanel_in(smart_chanel_in),
+  Signal        : smart_chanel_in[0].hdr_flit
+  InstName      : smart_bypass
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[2].the_router @router_top
+  -----------------------------------------------------------------------------
+  Tag           : W287a
+  Description   : Input '[Signal]' of instance '[InstName]' is undriven.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:3622
+  Goal          : lint_rtl
+  Module        : mesh_torus_noc_top
+  FileName      : ./../../rtl/src_noc/./mesh_torus_noc_top.sv
+  LineNumber    : 71
+  Statement     :                 .router_config_in(router_config_in[RID]),                
+  Signal        : router_config_in[2].endp_ids[1:0]
+  InstName      : the_router
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top
+  -----------------------------------------------------------------------------
+  Tag           : W287a
+  Description   : Input '[Signal]' of instance '[InstName]' is undriven.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:4895
+  Goal          : lint_rtl
+  Module        : router_top
+  FileName      : ./../../rtl/src_noc/./router_top.sv
+  LineNumber    : 149
+  Statement     :             .smart_chanel_in(smart_chanel_in),
+  Signal        : smart_chanel_in[0].hdr_flit
+  InstName      : smart_bypass
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[1].the_router @router_top
+  -----------------------------------------------------------------------------
+  Tag           : W287a
+  Description   : Input '[Signal]' of instance '[InstName]' is undriven.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5585
+  Goal          : lint_rtl
+  Module        : router_top
+  FileName      : ./../../rtl/src_noc/./router_top.sv
+  LineNumber    : 149
+  Statement     :             .smart_chanel_in(smart_chanel_in),
+  Signal        : smart_chanel_in[0].ovc[0]
+  InstName      : smart_bypass
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[3].the_router @router_top
+  -----------------------------------------------------------------------------
+  Tag           : W287a
+  Description   : Input '[Signal]' of instance '[InstName]' is undriven.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:3625
+  Goal          : lint_rtl
+  Module        : mesh_torus_noc_top
+  FileName      : ./../../rtl/src_noc/./mesh_torus_noc_top.sv
+  LineNumber    : 71
+  Statement     :                 .router_config_in(router_config_in[RID]),                
+  Signal        : router_config_in[0].endp_addrs[1:0]
+  InstName      : the_router
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top
+  -----------------------------------------------------------------------------
+  Tag           : W287a
+  Description   : Input '[Signal]' of instance '[InstName]' is undriven.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:3658
+  Goal          : lint_rtl
+  Module        : router_top
+  FileName      : ./../../rtl/src_noc/./router_top.sv
+  LineNumber    : 149
+  Statement     :             .smart_chanel_in(smart_chanel_in),
+  Signal        : smart_chanel_in[0].bypassed_num[1:0]
+  InstName      : smart_bypass
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top
+  -----------------------------------------------------------------------------
+  Tag           : W287a
+  Description   : Input '[Signal]' of instance '[InstName]' is undriven.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:3620
+  Goal          : lint_rtl
+  Module        : mesh_torus_noc_top
+  FileName      : ./../../rtl/src_noc/./mesh_torus_noc_top.sv
+  LineNumber    : 71
+  Statement     :                 .router_config_in(router_config_in[RID]),                
+  Signal        : router_config_in[3].endp_ids[1:0]
+  InstName      : the_router
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top
+  -----------------------------------------------------------------------------
+  Tag           : W287a
+  Description   : Input '[Signal]' of instance '[InstName]' is undriven.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:3624
+  Goal          : lint_rtl
+  Module        : mesh_torus_noc_top
+  FileName      : ./../../rtl/src_noc/./mesh_torus_noc_top.sv
+  LineNumber    : 71
+  Statement     :                 .router_config_in(router_config_in[RID]),                
+  Signal        : router_config_in[1].endp_ids[1:0]
+  InstName      : the_router
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top
+  -----------------------------------------------------------------------------
+  Tag           : W287a
+  Description   : Input '[Signal]' of instance '[InstName]' is undriven.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5587
+  Goal          : lint_rtl
+  Module        : router_top
+  FileName      : ./../../rtl/src_noc/./router_top.sv
+  LineNumber    : 149
+  Statement     :             .smart_chanel_in(smart_chanel_in),
+  Signal        : smart_chanel_in[0].hdr_flit
+  InstName      : smart_bypass
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[3].the_router @router_top
+  -----------------------------------------------------------------------------
+  Tag           : W287a
+  Description   : Input '[Signal]' of instance '[InstName]' is undriven.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5239
+  Goal          : lint_rtl
+  Module        : router_top
+  FileName      : ./../../rtl/src_noc/./router_top.sv
+  LineNumber    : 149
+  Statement     :             .smart_chanel_in(smart_chanel_in),
+  Signal        : smart_chanel_in[0].ovc[0]
+  InstName      : smart_bypass
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[2].the_router @router_top
+  -----------------------------------------------------------------------------
+  Tag           : W287a
+  Description   : Input '[Signal]' of instance '[InstName]' is undriven.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:3619
+  Goal          : lint_rtl
+  Module        : mesh_torus_noc_top
+  FileName      : ./../../rtl/src_noc/./mesh_torus_noc_top.sv
+  LineNumber    : 71
+  Statement     :                 .router_config_in(router_config_in[RID]),                
+  Signal        : router_config_in[3].endp_addrs[1:0]
+  InstName      : the_router
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top
+  -----------------------------------------------------------------------------
+  Tag           : W287a
+  Description   : Input '[Signal]' of instance '[InstName]' is undriven.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5584
+  Goal          : lint_rtl
+  Module        : router_top
+  FileName      : ./../../rtl/src_noc/./router_top.sv
+  LineNumber    : 149
+  Statement     :             .smart_chanel_in(smart_chanel_in),
+  Signal        : smart_chanel_in[0].requests[2:0]
+  InstName      : smart_bypass
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[3].the_router @router_top
+  -----------------------------------------------------------------------------
+  Tag           : W287a
+  Description   : Input '[Signal]' of instance '[InstName]' is undriven.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:3626
+  Goal          : lint_rtl
+  Module        : mesh_torus_noc_top
+  FileName      : ./../../rtl/src_noc/./mesh_torus_noc_top.sv
+  LineNumber    : 71
+  Statement     :                 .router_config_in(router_config_in[RID]),                
+  Signal        : router_config_in[0].endp_ids[1:0]
+  InstName      : the_router
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top
+  -----------------------------------------------------------------------------
+  Tag           : W287a
+  Description   : Input '[Signal]' of instance '[InstName]' is undriven.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:3656
+  Goal          : lint_rtl
+  Module        : router_top
+  FileName      : ./../../rtl/src_noc/./router_top.sv
+  LineNumber    : 149
+  Statement     :             .smart_chanel_in(smart_chanel_in),
+  Signal        : smart_chanel_in[0].hdr_flit
+  InstName      : smart_bypass
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top
+  -----------------------------------------------------------------------------
+  Tag           : W287a
+  Description   : Input '[Signal]' of instance '[InstName]' is undriven.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:4892
+  Goal          : lint_rtl
+  Module        : router_top
+  FileName      : ./../../rtl/src_noc/./router_top.sv
+  LineNumber    : 149
+  Statement     :             .smart_chanel_in(smart_chanel_in),
+  Signal        : smart_chanel_in[0].requests[2:0]
+  InstName      : smart_bypass
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[1].the_router @router_top
+  -----------------------------------------------------------------------------
+  Tag           : W287a
+  Description   : Input '[Signal]' of instance '[InstName]' is undriven.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5242
+  Goal          : lint_rtl
+  Module        : router_top
+  FileName      : ./../../rtl/src_noc/./router_top.sv
+  LineNumber    : 149
+  Statement     :             .smart_chanel_in(smart_chanel_in),
+  Signal        : smart_chanel_in[0].flit_in_bypassed
+  InstName      : smart_bypass
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[2].the_router @router_top
+  -----------------------------------------------------------------------------
+  Tag           : W287a
+  Description   : Input '[Signal]' of instance '[InstName]' is undriven.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:3653
+  Goal          : lint_rtl
+  Module        : router_top
+  FileName      : ./../../rtl/src_noc/./router_top.sv
+  LineNumber    : 149
+  Statement     :             .smart_chanel_in(smart_chanel_in),
+  Signal        : smart_chanel_in[0].requests[2:0]
+  InstName      : smart_bypass
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top
+  -----------------------------------------------------------------------------
+  Tag           : W287a
+  Description   : Input '[Signal]' of instance '[InstName]' is undriven.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:3657
+  Goal          : lint_rtl
+  Module        : router_top
+  FileName      : ./../../rtl/src_noc/./router_top.sv
+  LineNumber    : 149
+  Statement     :             .smart_chanel_in(smart_chanel_in),
+  Signal        : smart_chanel_in[0].flit_in_bypassed
+  InstName      : smart_bypass
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top
+  -----------------------------------------------------------------------------
+  Tag           : W287a
+  Description   : Input '[Signal]' of instance '[InstName]' is undriven.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5243
+  Goal          : lint_rtl
+  Module        : router_top
+  FileName      : ./../../rtl/src_noc/./router_top.sv
+  LineNumber    : 149
+  Statement     :             .smart_chanel_in(smart_chanel_in),
+  Signal        : smart_chanel_in[0].bypassed_num[1:0]
+  InstName      : smart_bypass
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[2].the_router @router_top
+  -----------------------------------------------------------------------------
+  Tag           : W287a
+  Description   : Input '[Signal]' of instance '[InstName]' is undriven.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5586
+  Goal          : lint_rtl
+  Module        : router_top
+  FileName      : ./../../rtl/src_noc/./router_top.sv
+  LineNumber    : 149
+  Statement     :             .smart_chanel_in(smart_chanel_in),
+  Signal        : smart_chanel_in[0].dest_e_addr[1:0]
+  InstName      : smart_bypass
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[3].the_router @router_top
+  -----------------------------------------------------------------------------
+  Tag           : W287a
+  Description   : Input '[Signal]' of instance '[InstName]' is undriven.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:3623
+  Goal          : lint_rtl
+  Module        : mesh_torus_noc_top
+  FileName      : ./../../rtl/src_noc/./mesh_torus_noc_top.sv
+  LineNumber    : 71
+  Statement     :                 .router_config_in(router_config_in[RID]),                
+  Signal        : router_config_in[1].endp_addrs[1:0]
+  InstName      : the_router
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top
+  -----------------------------------------------------------------------------
+  Tag           : W287a
+  Description   : Input '[Signal]' of instance '[InstName]' is undriven.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:4896
+  Goal          : lint_rtl
+  Module        : router_top
+  FileName      : ./../../rtl/src_noc/./router_top.sv
+  LineNumber    : 149
+  Statement     :             .smart_chanel_in(smart_chanel_in),
+  Signal        : smart_chanel_in[0].flit_in_bypassed
+  InstName      : smart_bypass
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[1].the_router @router_top
+  -----------------------------------------------------------------------------
+  Tag           : W287a
+  Description   : Input '[Signal]' of instance '[InstName]' is undriven.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5588
+  Goal          : lint_rtl
+  Module        : router_top
+  FileName      : ./../../rtl/src_noc/./router_top.sv
+  LineNumber    : 149
+  Statement     :             .smart_chanel_in(smart_chanel_in),
+  Signal        : smart_chanel_in[0].flit_in_bypassed
+  InstName      : smart_bypass
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[3].the_router @router_top
+  -----------------------------------------------------------------------------
+  Tag           : W287a
+  Description   : Input '[Signal]' of instance '[InstName]' is undriven.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5589
+  Goal          : lint_rtl
+  Module        : router_top
+  FileName      : ./../../rtl/src_noc/./router_top.sv
+  LineNumber    : 149
+  Statement     :             .smart_chanel_in(smart_chanel_in),
+  Signal        : smart_chanel_in[0].bypassed_num[1:0]
+  InstName      : smart_bypass
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[3].the_router @router_top
+  -----------------------------------------------------------------------------
+  Tag           : W287a
+  Description   : Input '[Signal]' of instance '[InstName]' is undriven.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:4894
+  Goal          : lint_rtl
+  Module        : router_top
+  FileName      : ./../../rtl/src_noc/./router_top.sv
+  LineNumber    : 149
+  Statement     :             .smart_chanel_in(smart_chanel_in),
+  Signal        : smart_chanel_in[0].dest_e_addr[1:0]
+  InstName      : smart_bypass
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[1].the_router @router_top
+  -----------------------------------------------------------------------------
+  Tag           : W287a
+  Description   : Input '[Signal]' of instance '[InstName]' is undriven.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:3654
+  Goal          : lint_rtl
+  Module        : router_top
+  FileName      : ./../../rtl/src_noc/./router_top.sv
+  LineNumber    : 149
+  Statement     :             .smart_chanel_in(smart_chanel_in),
+  Signal        : smart_chanel_in[0].ovc[0]
+  InstName      : smart_bypass
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top
+  -----------------------------------------------------------------------------
+  Tag           : W287a
+  Description   : Input '[Signal]' of instance '[InstName]' is undriven.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5238
+  Goal          : lint_rtl
+  Module        : router_top
+  FileName      : ./../../rtl/src_noc/./router_top.sv
+  LineNumber    : 149
+  Statement     :             .smart_chanel_in(smart_chanel_in),
+  Signal        : smart_chanel_in[0].requests[2:0]
+  InstName      : smart_bypass
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[2].the_router @router_top
+  -----------------------------------------------------------------------------
+  Tag           : W287a
+  Description   : Input '[Signal]' of instance '[InstName]' is undriven.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:5240
+  Goal          : lint_rtl
+  Module        : router_top
+  FileName      : ./../../rtl/src_noc/./router_top.sv
+  LineNumber    : 149
+  Statement     :             .smart_chanel_in(smart_chanel_in),
+  Signal        : smart_chanel_in[0].dest_e_addr[1:0]
+  InstName      : smart_bypass
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[2].the_router @router_top
+  -----------------------------------------------------------------------------
+  Tag           : W287a
+  Description   : Input '[Signal]' of instance '[InstName]' is undriven.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:4893
+  Goal          : lint_rtl
+  Module        : router_top
+  FileName      : ./../../rtl/src_noc/./router_top.sv
+  LineNumber    : 149
+  Statement     :             .smart_chanel_in(smart_chanel_in),
+  Signal        : smart_chanel_in[0].ovc[0]
+  InstName      : smart_bypass
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[1].the_router @router_top
+
+  -----------------------------------------------------------------------------
+  W287a  (4 warnings/0 waived)
+  -----------------------------------------------------------------------------
+  Tag           : W287a
+  Description   : Input '[Signal]' of instance '[InstName]' is unconnected.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:4862
+  Goal          : lint_rtl
+  Module        : smart_allocator_per_iport
+  FileName      : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber    : 659
+  Statement     :         .src_e_addr       (            ),// needed only for custom routing
+  Signal        : src_e_addr
+  InstName      : lkrouting
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:\smart.Port_[2].smart_en.smart_allocator @smart_allocator_per_iport
+  -----------------------------------------------------------------------------
+  Tag           : W287a
+  Description   : Input '[Signal]' of instance '[InstName]' is unconnected.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:4779
+  Goal          : lint_rtl
+  Module        : smart_allocator_per_iport
+  FileName      : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber    : 627
+  Statement     :         .src_e_addr       (            ),// needed only for custom routing
+  Signal        : src_e_addr
+  InstName      : routing
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:\smart.Port_[1].smart_en.smart_allocator @smart_allocator_per_iport
+  -----------------------------------------------------------------------------
+  Tag           : W287a
+  Description   : Input '[Signal]' of instance '[InstName]' is unconnected.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:4861
+  Goal          : lint_rtl
+  Module        : smart_allocator_per_iport
+  FileName      : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber    : 627
+  Statement     :         .src_e_addr       (            ),// needed only for custom routing
+  Signal        : src_e_addr
+  InstName      : routing
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:\smart.Port_[2].smart_en.smart_allocator @smart_allocator_per_iport
+  -----------------------------------------------------------------------------
+  Tag           : W287a
+  Description   : Input '[Signal]' of instance '[InstName]' is unconnected.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:4780
+  Goal          : lint_rtl
+  Module        : smart_allocator_per_iport
+  FileName      : ./../../rtl/src_noc/./router_bypass.sv
+  LineNumber    : 659
+  Statement     :         .src_e_addr       (            ),// needed only for custom routing
+  Signal        : src_e_addr
+  InstName      : lkrouting
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:\smart.Port_[1].smart_en.smart_allocator @smart_allocator_per_iport
+
+  -----------------------------------------------------------------------------
+  W287b  (23 warnings/0 waived)
+  -----------------------------------------------------------------------------
+  Tag           : W287b
+  Description   : Instance output port '[ModPortName]' is not connected
+  Violation     : Lint:3903
+  Goal          : lint_rtl
+  Module        : look_ahead_routing
+  FileName      : ./../../rtl/src_noc/./routing.v
+  LineNumber    : 311
+  Statement     :             .valid( )
+  ModPortName   : valid
+  -----------------------------------------------------------------------------
+  Tag           : W287b
+  Description   : Instance output port '[ModPortName]' is not connected
+  Violation     : Lint:3733
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 725
+  Statement     :                 .nearly_full (),
+  ModPortName   : nearly_full
+  -----------------------------------------------------------------------------
+  Tag           : W287b
+  Description   : Instance output port '[ModPortName]' is not connected
+  Violation     : Lint:3727
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 399
+  Statement     :         .be_o( ),
+  ModPortName   : be_o
+  -----------------------------------------------------------------------------
+  Tag           : W287b
+  Description   : Instance output port '[ModPortName]' is not connected
+  Violation     : Lint:3732
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 724
+  Statement     :                 .full (),
+  ModPortName   : full
+  -----------------------------------------------------------------------------
+  Tag           : W287b
+  Description   : Instance output port '[ModPortName]' is not connected
+  Violation     : Lint:3731
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 633
+  Statement     :                 .recieve_more_than_1 ( ),
+  ModPortName   : recieve_more_than_1
+  -----------------------------------------------------------------------------
+  Tag           : W287b
+  Description   : Instance output port '[ModPortName]' is not connected
+  Violation     : Lint:3738
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 747
+  Statement     :                     .recieve_more_than_0(),
+  ModPortName   : recieve_more_than_0
+  -----------------------------------------------------------------------------
+  Tag           : W287b
+  Description   : Instance output port '[ModPortName]' is not connected
+  Violation     : Lint:3736
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 745
+  Statement     :                     .full(),
+  ModPortName   : full
+  -----------------------------------------------------------------------------
+  Tag           : W287b
+  Description   : Instance output port '[ModPortName]' is not connected
+  Violation     : Lint:3905
+  Goal          : lint_rtl
+  Module        : look_ahead_routing
+  FileName      : ./../../rtl/src_noc/./routing.v
+  LineNumber    : 340
+  Statement     :                 .valid()
+  ModPortName   : valid
+  -----------------------------------------------------------------------------
+  Tag           : W287b
+  Description   : Instance output port '[ModPortName]' is not connected
+  Violation     : Lint:3726
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 400
+  Statement     :         .data_o( )
+  ModPortName   : data_o
+  -----------------------------------------------------------------------------
+  Tag           : W287b
+  Description   : Instance output port '[ModPortName]' is not connected
+  Violation     : Lint:3734
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 726
+  Statement     :                 .recieve_more_than_0 (),
+  ModPortName   : recieve_more_than_0
+  -----------------------------------------------------------------------------
+  Tag           : W287b
+  Description   : Instance output port '[ModPortName]' is not connected
+  Violation     : Lint:4794
+  Goal          : lint_rtl
+  Module        : conventional_routing
+  FileName      : ./../../rtl/src_noc/./routing.v
+  LineNumber    : 122
+  Statement     :                 .valid()
+  ModPortName   : valid
+  -----------------------------------------------------------------------------
+  Tag           : W287b
+  Description   : Instance output port '[ModPortName]' is not connected
+  Violation     : Lint:3659
+  Goal          : lint_rtl
+  Module        : router_top
+  FileName      : ./../../rtl/src_noc/./router_top.sv
+  LineNumber    : 151
+  Statement     :             .smart_req(),
+  ModPortName   : smart_req
+  -----------------------------------------------------------------------------
+  Tag           : W287b
+  Description   : Instance output port '[ModPortName]' is not connected
+  Violation     : Lint:4609
+  Goal          : lint_rtl
+  Module        : nonspec_sw_alloc
+  FileName      : ./../../rtl/src_noc/./comb_nonspec.sv
+  LineNumber    : 513
+  Statement     :             .any_grant( ),
+  ModPortName   : any_grant
+  -----------------------------------------------------------------------------
+  Tag           : W287b
+  Description   : Instance output port '[ModPortName]' is not connected
+  Violation     : Lint:3729
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 631
+  Statement     :                 .nearly_full ( ),
+  ModPortName   : nearly_full
+  -----------------------------------------------------------------------------
+  Tag           : W287b
+  Description   : Instance output port '[ModPortName]' is not connected
+  Violation     : Lint:3735
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 727
+  Statement     :                 .recieve_more_than_1 (),
+  ModPortName   : recieve_more_than_1
+  -----------------------------------------------------------------------------
+  Tag           : W287b
+  Description   : Instance output port '[ModPortName]' is not connected
+  Violation     : Lint:3730
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 632
+  Statement     :                 .recieve_more_than_0 ( ),
+  ModPortName   : recieve_more_than_0
+  -----------------------------------------------------------------------------
+  Tag           : W287b
+  Description   : Instance output port '[ModPortName]' is not connected
+  Violation     : Lint:3728
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 630
+  Statement     :                 .full ( ),
+  ModPortName   : full
+  -----------------------------------------------------------------------------
+  Tag           : W287b
+  Description   : Instance output port '[ModPortName]' is not connected
+  Violation     : Lint:3904
+  Goal          : lint_rtl
+  Module        : look_ahead_routing
+  FileName      : ./../../rtl/src_noc/./routing.v
+  LineNumber    : 339
+  Statement     :                 .el( ),
+  ModPortName   : el
+  -----------------------------------------------------------------------------
+  Tag           : W287b
+  Description   : Instance output port '[ModPortName]' is not connected
+  Violation     : Lint:3737
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 746
+  Statement     :                     .nearly_full(),
+  ModPortName   : nearly_full
+  -----------------------------------------------------------------------------
+  Tag           : W287b
+  Description   : Instance output port '[ModPortName]' is not connected
+  Violation     : Lint:4793
+  Goal          : lint_rtl
+  Module        : conventional_routing
+  FileName      : ./../../rtl/src_noc/./routing.v
+  LineNumber    : 121
+  Statement     :                 .el( ),
+  ModPortName   : el
+  -----------------------------------------------------------------------------
+  Tag           : W287b
+  Description   : Instance output port '[ModPortName]' is not connected
+  Violation     : Lint:4792
+  Goal          : lint_rtl
+  Module        : conventional_routing
+  FileName      : ./../../rtl/src_noc/./routing.v
+  LineNumber    : 93
+  Statement     :                 .valid( )
+  ModPortName   : valid
+  -----------------------------------------------------------------------------
+  Tag           : W287b
+  Description   : Instance output port '[ModPortName]' is not connected
+  Violation     : Lint:3739
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 748
+  Statement     :                     .recieve_more_than_1(),
+  ModPortName   : recieve_more_than_1
+  -----------------------------------------------------------------------------
+  Tag           : W287b
+  Description   : Instance output port '[ModPortName]' is not connected
+  Violation     : Lint:4602
+  Goal          : lint_rtl
+  Module        : comb_nonspec_allocator
+  FileName      : ./../../rtl/src_noc/./comb_nonspec.sv
+  LineNumber    : 161
+  Statement     :             .any_grant()
+  ModPortName   : any_grant
+
+  -----------------------------------------------------------------------------
+  W468  (1 warning/0 waived)
+  -----------------------------------------------------------------------------
+  Tag           : W468
+  Description   : Variable/Signal '[Signal_Name]' is indexed by '[Signal]' which cannot index the full range of this vector.[Hierarchy: '[HIERARCHY]']
+  Violation     : Lint:3858
+  Goal          : lint_rtl
+  Module        : ovc_list
+  FileName      : ./../../rtl/src_noc/./ovc_list.sv
+  LineNumber    : 46
+  Statement     :     assign  ovcs_out= (C == 0 || C == 1)? {V{1'b1}} : class_table[class_in];
+  Signal_Name   : class_table
+  Signal        : class_in
+  HIERARCHY     : :noc_top:\tori_noc.noc_top @mesh_torus_noc_top:\ring_line.R_[0].the_router @router_top:router_ref@router_two_stage:the_inout_ports@inout_ports:the_input_port@input_ports:\Port_[0].the_input_queue_per_port @input_queue_per_port:\V_[0].ovc_.OvcList @ovc_list
+
+  -----------------------------------------------------------------------------
+  AvoidAsync  (1 info/0 waived/2 compressed)
+  -----------------------------------------------------------------------------
+  Tag           : AvoidAsync
+  Description   : Asynchronous [NodeType] signal '[Signal]' used at flop '[FLOP]'
+  Violation     : Lint:1
+  Goal          : lint_rtl
+  NodeType      : Reset
+  Signal        : reset
+  SignalRange   : 
+  Module        : pronoc_register_reset_init
+  HIERARCHY     : pronoc_register_reset_init
+  SeqSetRstNet  : tori_noc.noc_top/ring_line.R_[0].the_router/router_ref/the_inout_ports/the_input_port/Port_[0].the_input_queue_per_port/reg1/reg1/reset
+  FileName      : ./../../rtl/src_noc/./../main_comp.v
+  LineNumber    : 56
+  Statement     :     input reset,    
+  FLOP          : out[0]
+
+  -----------------------------------------------------------------------------
+  NoExprInPort-ML  (1 info/0 waived)
+  -----------------------------------------------------------------------------
+  Tag           : NoExprInPort-ML
+  Description   : Expressions [HdlExp] used in port connection in module instantiation
+  Violation     : Lint:3753
+  Goal          : lint_rtl
+  Module        : input_queue_per_port
+  FileName      : ./../../rtl/src_noc/./input_ports.sv
+  LineNumber    : 372
+  Statement     :         .in     (ivc_num_getting_sw_grant & ~ multiple_dest),
+  HdlExp        : (ivc_num_getting_sw_grant & (~multiple_dest))
+
+  -----------------------------------------------------------------------------
+  ReportPortInfo-ML  (1 info/0 waived)
+  -----------------------------------------------------------------------------
+  Tag           : ReportPortInfo-ML
+  Description   : Port Information for top design unit has been generated. For details see report ReportPortInfo.rpt
+  Violation     : Lint:5921
+  Goal          : lint_rtl
+  FileName      : .//vc_lint0/noc_top/VC_GOAL0/spyglass_reports/morelint/ReportPortInfo
+  LineNumber    : 1
+  Statement     : #     Comment          : Report Top Level Module Port Info
+
+  -----------------------------------------------------------------------------
+  W120  (1 info/0 waived)
+  -----------------------------------------------------------------------------
+  Tag           : W120
+  Description   : Please refer to 'SignalUsageReport.rpt' for details of violating bits
+  Violation     : Lint:3660
+  Goal          : lint_rtl
+  Module        : noc_top
+  FileName      : .//vc_lint0/noc_top/VC_GOAL0/spyglass_reports/lint/SignalUsageReport.rpt
+  LineNumber    : 1
+  Statement     : #     Comment          : SignalUsageReport : It dumps details of violating bits of a signal
+
+  -----------------------------------------------------------------------------
+  W123  (1 info/0 waived)
+  -----------------------------------------------------------------------------
+  Tag           : W123
+  Description   : Please refer to 'SignalUsageReport.rpt' for details of violating bits
+  Violation     : Lint:3610
+  Goal          : lint_rtl
+  Module        : noc_top
+  FileName      : .//vc_lint0/noc_top/VC_GOAL0/spyglass_reports/lint/SignalUsageReport.rpt
+  LineNumber    : 1
+  Statement     : #     Comment          : SignalUsageReport : It dumps details of violating bits of a signal
+
+  -----------------------------------------------------------------------------
+  W240  (1 info/0 waived)
+  -----------------------------------------------------------------------------
+  Tag           : W240
+  Description   : Please refer to 'SignalUsageReport.rpt' for details of violating bits
+  Violation     : Lint:3640
+  Goal          : lint_rtl
+  Module        : noc_top
+  FileName      : .//vc_lint0/noc_top/VC_GOAL0/spyglass_reports/lint/SignalUsageReport.rpt
+  LineNumber    : 1
+  Statement     : #     Comment          : SignalUsageReport : It dumps details of violating bits of a signal
+
+  -----------------------------------------------------------------------------
+  W241  (1 info/0 waived)
+  -----------------------------------------------------------------------------
+  Tag           : W241
+  Description   : Please refer to 'SignalUsageReport.rpt' for details of violating bits
+  Violation     : Lint:3646
+  Goal          : lint_rtl
+  Module        : noc_top
+  FileName      : .//vc_lint0/noc_top/VC_GOAL0/spyglass_reports/lint/SignalUsageReport.rpt
+  LineNumber    : 1
+  Statement     : #     Comment          : SignalUsageReport : It dumps details of violating bits of a signal
diff --git a/mpsoc/Integration_test/VCST/configurations/line4_smart3 b/mpsoc/Integration_test/VCST/configurations/line4_smart3
new file mode 100644
index 0000000..548c123
--- /dev/null
+++ b/mpsoc/Integration_test/VCST/configurations/line4_smart3
@@ -0,0 +1,16 @@
+$model = bless( {
+    'noc_param'=> {
+        "SMART_MAX" => "3",
+        TOPOLOGY=>"\"LINE\"",
+        "T1" => "4",
+        "T2" => "4",
+        "V" => "1",
+        "ESCAP_VC_MASK" => "1'b1",
+        "B" => "4",
+        "LB" => "16",
+        "Fpay" => "64",
+        "SSA_EN" => "0",
+        "SELF_LOOP_EN" => "1",
+        "MCAST_ENDP_LIST" => "'b11",
+    }
+}, 'ProNOC' );
\ No newline at end of file
diff --git a/mpsoc/Integration_test/VCST/run.sh b/mpsoc/Integration_test/VCST/run.sh
new file mode 100644
index 0000000..898f19e
--- /dev/null
+++ b/mpsoc/Integration_test/VCST/run.sh
@@ -0,0 +1,56 @@
+#!/bin/bash
+
+SCRPT_FULL_PATH=$(realpath ${BASH_SOURCE[0]})
+SCRPT_DIR_PATH=$(dirname $SCRPT_FULL_PATH)
+
+# Source the environment variables
+conf_dir="${SCRPT_DIR_PATH}/configurations"
+log_dir="${SCRPT_DIR_PATH}/result_logs"
+conf_dir="${SCRPT_DIR_PATH}/configurations"
+work="${SCRPT_DIR_PATH}/work"
+file_list_f="${SCRPT_DIR_PATH}/src/file_list.f"
+lint_file="${SCRPT_DIR_PATH}/src/lint.tcl"
+
+export VCS_ARCH_OVERRIDE=linux
+
+mkdir -p $work
+mkdir -p $log_dir
+
+
+VCST_COMMON_ARGS=" -full64  "
+
+
+vcst_lint () {
+    conf=$1
+    conf_file="${conf_dir}/$conf"
+    log_file="${log_dir}/${conf}.log"
+
+    if [[ ! -f "$conf_file" ]]; then
+        echo "Configuration file $conf_file does not exist"
+        exit 1
+    fi
+
+    perl "${SCRPT_DIR_PATH}/src/param_gen.pl" "$conf_file"
+    export REPORT_FILENAME="${log_dir}/${conf}_vc_static.txt"
+    export FILE_LIST=$file_list_f
+    cd work
+    vc_static_shell ${VCST_COMMON_ARGS} -file ${lint_file} -batch -lic_wait 10
+    cd -
+}
+
+for f in "$conf_dir"/*; do
+    [[ -d "$f" ]] && continue
+    conf=$(basename "$f")
+    log_file="${log_dir}/${conf}.log"
+    echo "▶️  Compiling configuration: $conf"
+    vcst_lint "$conf"  |& tee $log_file
+    if [[ $? -ne 0 ]]; then
+        echo "❌ Compilation failed for $conf (check $log_file)"
+        rm -f ${SCRPT_DIR_PATH}/src/noc_localparam.v
+        exit 1
+    else
+        echo "✅ Compilation successful for $conf"
+        rm -f ${SCRPT_DIR_PATH}/src/noc_localparam.v
+    fi
+    
+done
diff --git a/mpsoc/Integration_test/VCST/src/file_list.f b/mpsoc/Integration_test/VCST/src/file_list.f
new file mode 100644
index 0000000..a86c752
--- /dev/null
+++ b/mpsoc/Integration_test/VCST/src/file_list.f
@@ -0,0 +1,6 @@
++incdir+../src 
+
+-F ../../../rtl/src_noc/noc_filelist.f
+-F ../../../rtl/src_topology/custom_flist.f
+
+
diff --git a/mpsoc/Integration_test/VCST/src/lint.tcl b/mpsoc/Integration_test/VCST/src/lint.tcl
new file mode 100644
index 0000000..820ad6d
--- /dev/null
+++ b/mpsoc/Integration_test/VCST/src/lint.tcl
@@ -0,0 +1,55 @@
+set script_dir [file dirname [file normalize [info script]]]
+
+set DESIGN  noc_top
+set report_filename $::env(REPORT_FILENAME)
+
+# Waivers:
+#sg_read_waiver -file ${script_dir}/waiver.awl
+#source ${script_dir}/waiver.tcl
+
+# Reading Intel linting rules 
+source $script_dir/lint_rules.tcl
+
+
+# Replace this with the actual path to your .f file
+set filelist_path $::env(FILE_LIST)
+
+# Loop through lines
+# File handle and storage
+set fp [open $filelist_path r]
+while {[gets $fp line] >= 0} {
+    set line [string trim $line]
+
+    # Skip empty lines and comments
+    if {$line eq "" || [string match "#*" $line]} {
+        continue
+    }
+
+    # Handle +incdir+<path>
+    #if {[string match "+incdir+*" $line]} {
+    #    set incdir [string range $line 8 end]
+    # set_option include_path $incdir
+    #    continue
+    #}
+
+    # Add source file
+    lappend names_list $line
+}
+close $fp
+
+
+
+analyze -format sverilog    "$names_list"
+
+elaborate $DESIGN
+
+#read_sdc $constraints_path
+
+# Need to add this waiver in here, otherwise is not applicable
+#source ${script_dir}/waiver.tcl
+
+check_lint
+
+report_lint -verbose -file ${report_filename}
+report_lint
+exit 0
\ No newline at end of file
diff --git a/mpsoc/Integration_test/VCST/src/lint_rules.tcl b/mpsoc/Integration_test/VCST/src/lint_rules.tcl
new file mode 100644
index 0000000..90fcaff
--- /dev/null
+++ b/mpsoc/Integration_test/VCST/src/lint_rules.tcl
@@ -0,0 +1,1420 @@
+ # Goal: SpyglassConvergedLintSOC
+
+set saved_sh_continue_on_error [get_app_var sh_continue_on_error]
+
+set_app_var sh_continue_on_error true
+
+
+configure_lint_tag -enable -tag "badimplicitSM1" -severity Error
+
+configure_lint_tag -enable -tag "badimplicitSM2" -severity Error
+
+configure_lint_tag -enable -tag "badimplicitSM4" -severity Error
+
+configure_lint_tag -enable -tag "BlockHeader" -severity Warning
+
+configure_lint_tag -enable -tag "bothedges" -severity Error
+
+configure_lint_tag -enable -tag "STARC05-2.1.6.5" -severity Error
+
+configure_lint_tag -enable -tag "STARC05-2.3.1.2c" -severity Error
+
+configure_lint_tag -enable -tag "W421"  -severity Error
+
+configure_lint_tag -enable -tag "W442a"  -severity Error
+
+configure_lint_tag -enable -tag "W442b"  -severity Error
+
+configure_lint_tag -enable -tag "sim_race02" -severity Error
+
+configure_lint_tag_parameter -tag "sim_race02" -parameter WAIVER_COMPAT -value {W143}
+
+configure_lint_tag -enable -tag "W110a"  -severity Error
+
+configure_lint_tag -enable -tag "W416"  -severity Error
+
+configure_lint_tag -enable -tag "W416" -type_id SG_LINT_W416_VERILOG_W416_VE_ORDER_DEADCODE -severity Warning
+
+configure_lint_tag -enable -tag "W416" -type_id SG_LINT_W416_VERILOG_W416_VE_WIDTH_DEADCODE -severity Warning
+
+configure_lint_tag_parameter -tag "W416" -parameter CHECK_STATIC_VALUE -value {yes}
+
+configure_lint_tag_parameter -tag "W416" -parameter ENABLE_RTL_DEADCODE -value {yes}
+
+configure_lint_tag_parameter -tag "W416" -parameter HANDLE_ZERO_PADDING -value {yes}
+
+configure_lint_tag_parameter -tag "W416" -parameter IGNORE_NONSTATIC_COUNTER -value {yes}
+
+configure_lint_tag_parameter -tag "W416" -parameter CHECK_COUNTER_ASSIGNMENT -value {yes}
+
+configure_lint_tag_parameter -tag "W416" -parameter NOCHECKOVERFLOW  -value {no}
+
+configure_lint_tag -enable -tag "PragmaComments-ML" -severity Warning
+
+configure_lint_tag -enable -tag "STARC05-2.10.2.3" -severity Error
+
+configure_lint_tag -enable -tag "STARC05-2.11.3.1" -severity Warning
+
+configure_lint_tag_parameter -tag "STARC05-2.11.3.1" -parameter STRICT -value {no}
+
+configure_lint_tag -enable -tag "STARC05-2.3.1.5b" -severity Error
+
+configure_lint_tag -enable -tag "W215"  -severity Error
+
+configure_lint_tag -enable -tag "W216"  -severity Error
+
+configure_lint_tag -enable -tag "W289"  -severity Error
+
+configure_lint_tag -enable -tag "W292"  -severity Error
+
+configure_lint_tag -enable -tag "W293"  -severity Error
+
+configure_lint_tag -enable -tag "W317"  -severity Error
+
+configure_lint_tag -enable -tag "W352"  -severity Error
+
+configure_lint_tag -enable -tag "W398"  -severity Error
+
+configure_lint_tag_parameter -tag "W398" -parameter STRICT -value {no}
+
+configure_lint_tag_parameter -tag "W398" -parameter WAIVER_COMPAT -value {W143}
+
+configure_lint_tag -enable -tag "W422"  -severity Error
+
+configure_lint_tag -enable -tag "W424"  -severity Error
+
+configure_lint_tag -enable -tag "W425"  -severity Error
+
+configure_lint_tag -enable -tag "W426"  -severity Error
+
+configure_lint_tag -enable -tag "W427"  -severity Error
+
+configure_lint_tag -enable -tag "W428"  -severity Error
+
+configure_lint_tag -enable -tag "STARC05-2.1.2.4" -severity Error
+
+configure_lint_tag_parameter -tag "STARC05-2.1.2.4" -parameter IGNORE_SYSTEM_TASKS -value {yes}
+
+configure_lint_tag -enable -tag "InterfaceWithoutModport-ML" -severity Error
+
+configure_lint_tag -enable -tag "W467"  -severity Error
+
+configure_lint_tag_parameter -tag "W467" -parameter IGNORE_PARAM_CASE_CONDITION -value {yes}
+
+configure_lint_tag -enable -tag "W481a"  -severity Error
+
+configure_lint_tag_parameter -tag "W481a" -parameter STRICT -value {no}
+
+configure_lint_tag -enable -tag "W481b"  -severity Error
+
+configure_lint_tag -enable -tag "W496a"  -severity Error
+
+configure_lint_tag -enable -tag "W496b"  -severity Error
+
+configure_lint_tag -enable -tag "W71"  -severity Error
+
+configure_lint_tag_parameter -tag "W71" -parameter CHECK_SEQUENTIAL -value {yes}
+
+configure_lint_tag_parameter -tag "W71" -parameter STRICT -value {no}
+
+configure_lint_tag_parameter -tag "W71" -parameter REPORT_ONLY_FROM_ONE_HIERARCHY -value {yes}
+
+configure_lint_tag -enable -tag "NoAssignX-ML" -severity Error
+
+configure_lint_tag_parameter -tag "NoAssignX-ML" -parameter ADD_SIGNATURE_EXPRESSION -value {yes}
+
+configure_lint_tag_parameter -tag "NoAssignX-ML" -parameter CHECK_ENUM_DECL -value {yes}
+
+configure_lint_tag_parameter -tag "NoAssignX-ML" -parameter CHECK_XASSIGN_CASEDEFAULT -value {yes}
+
+configure_lint_tag -enable -tag "ReportPortInfo-ML" -severity Info
+
+configure_lint_tag -enable -tag "STARC05-2.1.3.1" -severity Error
+
+configure_lint_tag_parameter -tag "STARC05-2.1.3.1" -parameter NOCHECKOVERFLOW -value {no}
+
+configure_lint_tag -enable -tag "STARC05-2.2.3.3" -severity Error
+
+configure_lint_tag_parameter -tag "STARC05-2.2.3.3" -parameter STRICT -value {no}
+
+configure_lint_tag -enable -tag "STARC05-2.3.1.6" -severity Error
+
+configure_lint_tag -enable -tag "W116"  -severity Error
+
+configure_lint_tag -enable -tag "W116" -type_id SG_LINT_W116_VERILOG_LINT_W116_DEADCODE -severity Warning
+
+configure_lint_tag_parameter -tag "W116" -parameter CHECK_COUNTER_ASSIGNMENT -value {yes}
+
+configure_lint_tag_parameter -tag "W116" -parameter CHECK_STATIC_VALUE -value {yes}
+
+configure_lint_tag_parameter -tag "W116" -parameter ENABLE_RTL_DEADCODE -value {yes}
+
+configure_lint_tag_parameter -tag "W116" -parameter IGNORE_NONSTATIC_COUNTER -value {yes}
+
+configure_lint_tag_parameter -tag "W116" -parameter NOCHECKOVERFLOW -value {no}
+
+configure_lint_tag_parameter -tag "W116" -parameter REPORTCONSTASSIGN -value {yes}
+
+configure_lint_tag_parameter -tag "W116" -parameter STRICT -value {no}
+
+configure_lint_tag_parameter -tag "W116" -parameter REPORT_ONLY_FROM_ONE_HIERARCHY -value {yes}
+
+configure_lint_tag -enable -tag "W122"  -severity Error
+
+configure_lint_tag_parameter -tag "W122" -parameter STRICT -value {no}
+
+configure_lint_tag -enable -tag "W123"  -severity Error
+
+configure_lint_tag -enable -tag "W123"  -type_id SG_LINT_W123_VHDL_SIGNALUSAGEREPORT_REFER -severity Info
+
+configure_lint_tag -enable -tag "W123"  -type_id SG_LINT_W123_VERILOG_SIGNALUSAGEREPORT_REFER -severity Info
+
+configure_lint_tag_parameter -tag "W123" -parameter CHECKFULLRECORD -value {yes}
+
+configure_lint_tag_parameter -tag "W123" -parameter HANDLE_LARGE_BUS -value {yes}
+
+configure_lint_tag_parameter -tag "W123" -parameter IGNOREMODULEINSTANCE -value {yes}
+
+configure_lint_tag_parameter -tag "W123" -parameter REPORT_STRUCT_NAME_ONLY -value {yes}
+
+configure_lint_tag_parameter -tag "W123" -parameter REPORT_ONLY_FROM_ONE_HIERARCHY -value {yes}
+
+configure_lint_tag -enable -tag "W19"  -severity Error
+
+configure_lint_tag_parameter -tag "W19" -parameter STRICT -value {no}
+
+configure_lint_tag -enable -tag "W218"  -severity Error
+
+configure_lint_tag -enable -tag "W240"  -severity Warning
+
+configure_lint_tag -enable -tag "W240" -type_id SG_LINT_W240_VERILOG_SIGNALUSAGEREPORT_REFER -severity Info
+
+configure_lint_tag -enable -tag "W240" -type_id SG_LINT_W240_VHDL_SIGNALUSAGEREPORT_REFER -severity Info
+
+configure_lint_tag_parameter -tag "W240" -parameter CHECKFULLRECORD -value {yes}
+
+configure_lint_tag_parameter -tag "W240" -parameter HANDLE_LARGE_BUS -value {yes}
+
+configure_lint_tag_parameter -tag "W240" -parameter REPORT_ONLY_FROM_ONE_HIERARCHY -value {yes}
+
+configure_lint_tag -enable -tag "W263"  -severity Error
+
+configure_lint_tag_parameter -tag "W263" -parameter NOCHECKOVERFLOW -value {no}
+
+configure_lint_tag_parameter -tag "W263" -parameter STRICT -value {no}
+
+configure_lint_tag -enable -tag "W337"  -severity Error
+
+configure_lint_tag_parameter -tag "W337" -parameter STRICT -value {no}
+
+configure_lint_tag -enable -tag "W486"  -severity Error
+
+configure_lint_tag -enable -tag "W486" -type_id SG_LINT_W486_VERILOG_W486_VE_DEADCODE -severity Warning
+
+configure_lint_tag_parameter -tag "W486" -parameter ENABLE_RTL_DEADCODE -value {yes}
+
+configure_lint_tag_parameter -tag "W486" -parameter NOCHECKOVERFLOW -value {no}
+
+configure_lint_tag_parameter -tag "W486" -parameter PROCESS_COMPLETE_CONDOP -value {yes}
+
+configure_lint_tag -enable -tag "W499"  -severity Error
+
+configure_lint_tag -enable -tag "W499" -type_id SG_LINT_W499_VERILOG_SIGNALUSAGEREPORT_REFER -severity Info
+
+configure_lint_tag_parameter -tag "W499" -parameter HANDLE_LARGE_BUS -value {yes}
+
+configure_lint_tag_parameter -tag "W499" -parameter IGNORE_AUTO_FUNCTION_RETURN -value {yes}
+
+configure_lint_tag -enable -tag "W502"  -severity Error
+
+configure_lint_tag -enable -tag "W505"  -severity Error
+
+configure_lint_tag -enable -tag "W66"  -severity Error
+
+configure_lint_tag -enable -tag "InferLatch" -severity Error
+
+configure_lint_tag -enable -tag "InferLatch" -type_id SG_OPENMORE_INFERLATCH_VERILOG_INFERLATCH -severity Error
+
+configure_lint_tag -enable -tag "InferLatch" -type_id SG_OPENMORE_INFERLATCH_MIXED_INFERLATCH -severity Error
+
+configure_lint_tag -enable -tag "InferLatch" -type_id SG_OPENMORE_INFERLATCH_MIXED_INFERLATCH_FOR_REPORTLATCHHIERARCHY -severity Warning
+
+configure_lint_tag -enable -tag "InferLatch" -type_id SG_OPENMORE_INFERLATCH_MIXED_INFERLATCH_HL -severity Warning
+
+configure_lint_tag_parameter -tag "InferLatch" -parameter IGNOREREALLATCH -value {yes}
+
+configure_lint_tag_parameter -tag "InferLatch" -parameter STRICT -value {no}
+
+#configure_lint_tag_parameter -tag "InferLatch" -parameter REPORTHANGINGLATCH -value {yes}
+
+configure_lint_tag -enable -tag "STARC05-2.5.1.7" -severity Error
+
+configure_lint_tag -enable -tag "STARC05-2.5.1.9" -severity Error
+
+configure_lint_tag -enable -tag "STARC05-2.10.3.2a" -severity Warning
+
+configure_lint_tag_parameter -tag "STARC05-2.10.3.2a" -parameter ENABLE_RTL_DEADCODE -value {yes}
+
+configure_lint_tag_parameter -tag "STARC05-2.10.3.2a" -parameter NOCHECKOVERFLOW -value {no}
+
+configure_lint_tag_parameter -tag "STARC05-2.10.3.2a" -parameter CHECK_STATIC_VALUE -value {yes}
+
+configure_lint_tag -enable -tag "W336"  -severity Error
+
+configure_lint_tag_parameter -tag "W336" -parameter CHECK_TEMPORARY_FLOP -value {yes}
+
+configure_lint_tag_parameter -tag "W336" -parameter IGNORECELLNAME -value {ctech_lib_clk_ffb,ctech_lib_clk_ffb_rstb,ctech_lib_clk_divider2,ctech_lib_clk_divider2_rstb}
+
+configure_lint_tag -enable -tag "W414"  -severity Error
+
+configure_lint_tag -enable -tag "W450L"  -severity Error
+
+configure_lint_tag -enable -tag "UndrivenInTerm-ML" -severity Error
+
+configure_lint_tag_parameter -tag "UndrivenInTerm-ML" -parameter CHECKINHIERARCHY -value {yes}
+
+configure_lint_tag_parameter -tag "UndrivenInTerm-ML" -parameter CHECKRTLCINST -value {yes}
+
+configure_lint_tag_parameter -tag "UndrivenInTerm-ML" -parameter IGNORERTLBUFFER -value {yes}
+
+configure_lint_tag_parameter -tag "UndrivenInTerm-ML" -parameter IGNORE_DELIBERATELY_UNCONNECTED -value {yes}
+
+configure_lint_tag_parameter -tag "UndrivenInTerm-ML" -parameter IGNORE_UNUSED_FLOP -value {yes}
+
+configure_lint_tag -enable -tag "CombLoop" -severity Error
+
+configure_lint_tag -enable -tag "CombLoop" -type_id SG_OPENMORE_COMBLOOP_MIXED_COMBLOOP_MORE_LATCH -severity Warning
+
+configure_lint_tag -enable -tag "CombLoop" -type_id SG_OPENMORE_COMBLOOP_MIXED_COMBLOOPRPT -severity Info
+
+configure_lint_tag_parameter -tag "CombLoop" -parameter ALLVIOL -value {yes}
+
+configure_lint_tag_parameter -tag "CombLoop" -parameter ENABLEE2Q -value {yes}
+
+configure_lint_tag_parameter -tag "CombLoop" -parameter ENABLE_LATCH_BASED_CLUSTERS -value {yes}
+
+configure_lint_tag_parameter -tag "CombLoop" -parameter IGNORE_INTERNAL_LOOPS -value {yes}
+
+configure_lint_tag_parameter -tag "CombLoop" -parameter REPORT_FLOP_RESET_LOOP -value {yes}
+
+configure_lint_tag_parameter -tag "CombLoop" -parameter STRICT -value {no}
+
+configure_lint_tag -enable -tag "FlopClockConstant" -severity Error
+
+configure_lint_tag_parameter -tag "FlopClockConstant" -parameter ALLVIOL -value {yes}
+
+configure_lint_tag_parameter -tag "FlopClockConstant" -parameter IGNORE_HANGING_FLOP -value {yes}
+
+configure_lint_tag_parameter -tag "FlopClockConstant" -parameter REPORT_CONST_CONNECT -value {yes}
+
+configure_lint_tag_parameter -tag "FlopClockConstant" -parameter REPORT_INFERRED_CELL -value {yes}
+
+#configure_lint_tag_parameter -tag "FlopClockConstant" -parameter REPORT_IMMEDIATE_SRC -value {yes}
+
+configure_lint_tag -enable -tag "FlopEConst" -severity Error
+
+configure_lint_tag_parameter -tag "FlopEConst" -parameter ALLVIOL -value {yes}
+
+configure_lint_tag_parameter -tag "FlopEConst" -parameter IGNORE_HANGING_FLOP -value {yes}
+
+configure_lint_tag_parameter -tag "FlopEConst" -parameter REPORT_CONST_CONNECT -value {yes}
+
+configure_lint_tag_parameter -tag "FlopEConst" -parameter REPORT_INFERRED_CELL -value {yes}
+
+#configure_lint_tag_parameter -tag "FlopEConst" -parameter REPORT_IMMEDIATE_SRC -value {yes}
+
+configure_lint_tag -enable -tag "FlopSRConst" -severity Error
+
+configure_lint_tag_parameter -tag "FlopSRConst" -parameter ALLVIOL -value {yes}
+
+configure_lint_tag_parameter -tag "FlopSRConst" -parameter IGNORE_HANGING_FLOP -value {yes}
+
+configure_lint_tag_parameter -tag "FlopSRConst" -parameter REPORT_INFERRED_CELL -value {yes}
+
+#configure_lint_tag_parameter -tag "FlopSRConst" -parameter REPORT_IMMEDIATE_SRC -value {yes}
+
+configure_lint_tag -enable -tag "LatchFeedback" -severity Warning
+
+configure_lint_tag -enable -tag "STARC05-1.2.1.2" -severity Error
+
+configure_lint_tag -enable -tag "STARC05-1.4.3.4" -severity Error
+
+configure_lint_tag_parameter -tag "STARC05-1.4.3.4" -parameter REPORT_ALLCLK -value {no}
+
+configure_lint_tag_parameter -tag "STARC05-1.4.3.4" -parameter REPORT_ALLCLK_OPTIMIZED -value {no}
+
+configure_lint_tag -enable -tag "STARC05-2.1.4.5" -severity Error
+
+configure_lint_tag -enable -tag "STARC05-2.4.1.5" -severity Error
+
+configure_lint_tag_parameter -tag "STARC05-2.4.1.5" -parameter IGNORE_MUX_CELL -value {yes}
+
+configure_lint_tag_parameter -tag "STARC05-2.4.1.5" -parameter COMBO_DEPTH -value {1}
+
+configure_lint_tag -enable -tag "STARC05-2.5.1.2" -severity Error
+
+configure_lint_tag_parameter -tag "STARC05-2.5.1.2" -parameter STRICT -value {no}
+
+configure_lint_tag -enable -tag "W415" -severity Error
+
+configure_lint_tag -enable -tag "W415" -type_id SG_LINT_W415_MIXED_W415RPT -severity Info
+
+configure_lint_tag_parameter -tag "W415" -parameter ASSUME_DRIVER_LOAD -value {yes}
+
+configure_lint_tag_parameter -tag "W415" -parameter CHECKCONSTASSIGN -value {yes}
+
+configure_lint_tag_parameter -tag "W415" -parameter HANDLE_EQUIVALENT_DRIVERS -value {yes}
+
+configure_lint_tag_parameter -tag "W415" -parameter STRICT -value {no}
+
+configure_lint_tag -enable -tag "STARC05-2.10.1.4a" -severity Error
+
+configure_lint_tag_parameter -tag "STARC05-2.10.1.4a" -parameter CHECK_ANY_BIT_FOR_XZ -value {yes}
+
+configure_lint_tag_parameter -tag "STARC05-2.10.1.4a" -parameter IGNORE_QMARK -value {yes}
+
+configure_lint_tag -enable -tag "STARC05-2.10.1.4b" -severity Error
+
+configure_lint_tag_parameter -tag "STARC05-2.10.1.4b" -parameter IGNORE_CASE_COMPARE_OP -value {1}
+
+configure_lint_tag -enable -tag "W156" -severity Warning
+
+configure_lint_tag_parameter -tag "W156" -parameter STRICT -value {no}
+
+configure_lint_tag -enable -tag "STARC05-2.3.3.1" -severity Error
+
+configure_lint_tag -enable -tag "W287b" -severity Warning
+
+configure_lint_tag -enable -tag "W224"  -severity Error
+
+configure_lint_tag_parameter -tag "W224" -parameter USE_NATURAL_WIDTH -value {yes}
+
+configure_lint_tag_parameter -tag "W224" -parameter REPORT_ONLY_FROM_ONE_HIERARCHY -value {yes}
+
+configure_lint_tag -enable -tag "W287a" -severity Warning
+
+configure_lint_tag_parameter -tag "W287a" -parameter STRICT -value {no}
+
+configure_lint_tag_parameter -tag "W287a" -parameter REPORT_ONLY_FROM_ONE_HIERARCHY -value {yes}
+
+configure_lint_tag -enable -tag "mixedsenselist" -severity Warning
+
+configure_lint_tag -enable -tag "W339a"  -severity Error
+
+configure_lint_tag -enable -tag "W430"  -severity Warning
+
+configure_lint_tag -enable -tag "W257"  -severity Error
+
+configure_lint_tag_parameter -tag "W257" -parameter ALLVIOL -value {yes}
+
+configure_lint_tag -enable -tag "W294"  -severity Error
+
+configure_lint_tag -enable -tag "NoStrengthInput-ML" -severity Error
+
+configure_lint_tag -enable -tag "STARC05-3.2.4.3" -severity Error
+
+configure_lint_tag -enable -tag "W182g"  -severity Error
+
+configure_lint_tag -enable -tag "W182h"  -severity Error
+
+configure_lint_tag -enable -tag "W182k"  -severity Error
+
+configure_lint_tag -enable -tag "W182n"  -severity Error
+
+configure_lint_tag -enable -tag "W213"  -severity Error
+
+configure_lint_tag_parameter -tag "W213" -parameter IGNORE_PLI_TASKS_AND_FUNCTIONS -value {display,info,warning,error,fatal}
+
+configure_lint_tag -enable -tag "1490"  -severity Error
+
+configure_lint_tag -enable -tag "1492"  -severity Error
+
+configure_lint_tag -enable -tag "2082"  -severity Error
+
+configure_lint_tag -enable -tag "02041"  -severity Error
+
+configure_lint_tag_parameter -tag "02041" -parameter CHECK_DECL_IN_FUNC -value {yes}
+
+configure_lint_tag -enable -tag "UnrecSynthDir-ML" -severity Warning
+
+configure_lint_tag_parameter -tag "UnrecSynthDir-ML" -parameter CHECK_ALL_PRAGMAS -value {yes}
+
+configure_lint_tag -enable -tag "W495"  -severity Warning
+
+configure_lint_tag_parameter -tag "W495" -parameter HANDLE_LARGE_BUS -value {yes}
+
+configure_lint_tag -enable -tag "W120"  -severity Warning
+
+configure_lint_tag -enable -tag "W120" -type_id SG_LINT_W120_VHDL_SIGNALUSAGEREPORT_REFER -severity Info
+
+configure_lint_tag -enable -tag "W120" -type_id SG_LINT_W120_VERILOG_SIGNALUSAGEREPORT_REFER -severity Info
+
+configure_lint_tag_parameter -tag "W120" -parameter CHECKFULLRECORD -value {yes}
+
+configure_lint_tag_parameter -tag "W120" -parameter HANDLE_LARGE_BUS -value {yes}
+
+configure_lint_tag_parameter -tag "W120" -parameter REPORT_ONLY_FROM_ONE_HIERARCHY -value {yes}
+
+configure_lint_tag -enable -tag "W241"  -severity Warning
+
+configure_lint_tag -enable -tag "W241" -type_id SG_LINT_W241_VERILOG_SIGNALUSAGEREPORT_REFER -severity Info
+
+configure_lint_tag -enable -tag "W241" -type_id SG_LINT_W241_VHDL_SIGNALUSAGEREPORT_REFER -severity Info
+
+configure_lint_tag_parameter -tag "W241" -parameter HANDLE_LARGE_BUS -value {yes}
+
+configure_lint_tag -enable -tag "W494"  -severity Warning
+
+configure_lint_tag_parameter -tag "W494" -parameter CHKTOPMODULE -value {yes}
+
+configure_lint_tag_parameter -tag "W494" -parameter HANDLE_LARGE_BUS -value {yes}
+
+configure_lint_tag_parameter -tag "W494" -parameter STRICT -value {no}
+
+configure_lint_tag -enable -tag "UnloadedOutTerm-ML" -severity Warning
+
+configure_lint_tag_parameter -tag "UnloadedOutTerm-ML" -parameter CHECKINHIERARCHY -value {yes}
+
+configure_lint_tag_parameter -tag "UnloadedOutTerm-ML" -parameter IGNORERTLBUFFER -value {yes}
+
+configure_lint_tag_parameter -tag "UnloadedOutTerm-ML" -parameter IGNORE_DELIBERATELY_UNCONNECTED -value {yes}
+
+configure_lint_tag -enable -tag "UnloadedInPort-ML" -severity Warning
+
+configure_lint_tag_parameter -tag "UnloadedInPort-ML" -parameter CHECKINHIERARCHY -value {yes}
+
+configure_lint_tag_parameter -tag "UnloadedInPort-ML" -parameter IGNORERTLBUFFER -value {yes}
+
+configure_lint_tag -enable -tag "UndrivenOutPort-ML" -severity Error
+
+configure_lint_tag_parameter -tag "UndrivenOutPort-ML" -parameter CHECKINHIERARCHY -value {yes}
+
+configure_lint_tag_parameter -tag "UndrivenOutPort-ML" -parameter IGNORERTLBUFFER -value {yes}
+
+configure_lint_tag -enable -tag "UndrivenNUnloaded-ML" -severity Warning
+
+configure_lint_tag_parameter -tag "UndrivenNUnloaded-ML" -parameter CHECKINHIERARCHY -value {yes}
+
+configure_lint_tag_parameter -tag "UndrivenNUnloaded-ML" -parameter IGNORERTLBUFFER -value {yes}
+
+configure_lint_tag -enable -tag "UndrivenOutTermNLoaded-ML" -severity Error
+
+configure_lint_tag_parameter -tag "UndrivenOutTermNLoaded-ML" -parameter CHECKINHIERARCHY -value {yes}
+
+configure_lint_tag -enable -tag "UnloadedNet-ML" -severity Warning
+
+configure_lint_tag_parameter -tag "UnloadedNet-ML" -parameter CHECKINHIERARCHY -value {yes}
+
+configure_lint_tag_parameter -tag "UnloadedNet-ML" -parameter IGNORERTLBUFFER -value {yes}
+
+configure_lint_tag -enable -tag "LatchEnableConstant" -severity Error
+
+#configure_lint_tag_parameter -tag "LatchEnableConstant" -parameter REPORT_IMMEDIATE_SRC -value {yes}
+
+configure_lint_tag_parameter -tag "LatchEnableConstant" -parameter ALLVIOL -value {yes}
+
+configure_lint_tag -enable -tag "LatchEnableUndriven" -severity Error
+
+configure_lint_tag_parameter -tag "LatchEnableUndriven" -parameter ALLVIOL -value {yes}
+
+configure_lint_tag_parameter -tag "W210" -parameter SET_MESSAGE_SEVERITY -value {yes}
+
+configure_lint_tag -enable -tag "W210" -type_id SG_LINT_W210_VHDL_MISSING_PORT_ERROR -severity Error
+
+configure_lint_tag -enable -tag "W210" -type_id SG_LINT_W210_VERILOG_MISSING_PORT_ERROR -severity Error
+
+configure_lint_tag -enable -tag "W210" -type_id SG_LINT_W210_VHDL_MISSING_PORT_WARNING -severity Warning
+
+configure_lint_tag -enable -tag "W210" -type_id SG_LINT_W210_VERILOG_MISSING_PORT_WARNING -severity Warning
+
+configure_lint_tag -enable -tag "60004"  -severity Error
+
+configure_lint_tag -enable -tag "60006"  -severity Error
+
+configure_lint_tag -enable -tag "UndrivenNet-ML" -severity Warning
+
+configure_lint_tag_parameter -tag "UndrivenNet-ML" -parameter CHECKINHIERARCHY -value {yes}
+
+configure_lint_tag_parameter -tag "UndrivenNet-ML" -parameter IGNORERTLBUFFER -value {yes}
+
+configure_lint_tag_parameter -tag "UndrivenNet-ML" -parameter IGNORE_UNUSED_FLOP -value {yes}
+
+configure_lint_tag -enable -tag "NoExprInPort-ML" -severity Info
+
+configure_lint_tag_parameter -tag "NoExprInPort-ML" -parameter CHECKGATEINST -value {yes}
+
+configure_lint_tag_parameter -tag "NoExprInPort-ML" -parameter IGNOREINVERSIONOPERATION -value {yes}
+
+configure_lint_tag -enable -tag "NamedAssoc" -severity Error
+
+configure_lint_tag -enable -tag "AssignPatInInst-ML" -severity Error
+
+configure_lint_tag -enable -tag "60013"  -severity Error
+
+configure_lint_tag_parameter -tag "60013" -parameter PERMIT_SIMILAR_NAMES_AMONGST_DIFFERENT_OBJECT_TYPES -value {1}
+
+configure_lint_tag -enable -tag "ParamName" -severity Warning
+
+configure_lint_tag_parameter -tag "ParamName" -parameter PARAMNAME -value {/^[A-Z][0-9A-Z]*/ and not /[a-z]/}
+
+configure_lint_tag -enable -tag "SigName"  -severity Warning
+
+configure_lint_tag_parameter -tag "SigName" -parameter PRINT_RECOMMENDED_REGEXP -value {yes}
+
+configure_lint_tag_parameter -tag "SigName" -parameter SIGNAME -value {/^[a-zA-Z]([a-zA-Z0-9_])*$/ and /^.{1,1024}$/ and not /__/}
+
+configure_lint_tag -enable -tag "PortName" -severity Warning
+
+configure_lint_tag_parameter -tag "PortName" -parameter IGNORE_FILE -value {.*\.binc\.vs|.*\.tinc\.vs|.*\.ports\.v}
+
+configure_lint_tag_parameter -tag "PortName" -parameter PORTNAME -value {/^[a-zA-Z]([a-zA-Z0-9_])*$/ and /^.{1,128}$/ and not /__/}
+
+configure_lint_tag_parameter -tag "PortName" -parameter PRINT_RECOMMENDED_REGEXP -value {yes}
+
+configure_lint_tag -enable -tag "VarName"  -severity Warning
+
+configure_lint_tag_parameter -tag "VarName" -parameter PRINT_RECOMMENDED_REGEXP -value {yes}
+
+configure_lint_tag_parameter -tag "VarName" -parameter VARNAME -value {/^[a-zA-Z]([a-zA-Z0-9_])*$/ and /^.{1,1024}$/ and not /__/}
+
+configure_lint_tag -enable -tag "ConstName" -severity Warning
+
+configure_lint_tag_parameter -tag "ConstName" -parameter CONSTNAME -value {/^[A-Z][A-Z0-9_]*$/}
+
+configure_lint_tag_parameter -tag "ConstName" -parameter PRINT_RECOMMENDED_REGEXP -value {yes}
+
+configure_lint_tag -enable -tag "W121"  -severity Error
+
+configure_lint_tag_parameter -tag "W121" -parameter IGNORE_MACRO_TO_NONMACRO -value {yes}
+
+configure_lint_tag_parameter -tag "W121" -parameter LIMIT_TASK_FUNCTION_SCOPE -value {yes}
+
+configure_lint_tag_parameter -tag "W121" -parameter WAIVER_COMPAT -value {W143}
+
+configure_lint_tag -enable -tag "STARC05-1.1.1.2" -severity Warning
+
+configure_lint_tag_parameter -tag "STARC05-1.1.1.2" -parameter IGNORE_FILE -value {.*\.binc\.vs|.*\.tinc\.vs|.*\.ports\.v}
+
+configure_lint_tag_parameter -tag "STARC05-1.1.1.2" -parameter REPORT_TYPEDEF -value {yes}
+
+configure_lint_tag -enable -tag "STARC05-1.1.1.3" -severity Error
+
+configure_lint_tag_parameter -tag "STARC05-1.1.1.3" -parameter DISABLE_VHDL_KEYWORDS -value {yes}
+
+configure_lint_tag -enable -tag "60117"  -severity Error
+
+configure_lint_tag_parameter -tag "60117" -parameter REGEXP_FORBIDDEN_MACROS -value {^((?:LS_\w*)$|ISO_(HIGH|LOW)|AND_ISO|EPG).*}
+
+configure_lint_tag -enable -tag "60010"  -severity Error
+
+configure_lint_tag_parameter -tag "60010" -parameter REPORT_OBJECT_TYPES -value {net,port,variable,struct,union,enum,typedef,userdefined}
+
+configure_lint_tag_parameter -tag "60010" -parameter KEYWORDS -value {^semaphore$ ^gnd$ ^above$ ^abs$ ^absdelay$ ^acos$ ^acosh$ ^ac_stim$ ^aliasparam$ ^analog$ ^analysis$ ^asin$ ^asinh$ ^atan$ ^atan2$ ^atanh$ ^branch$ ^ceil$ ^connectrules$ ^cos$ ^cosh$ ^ddt$ ^ddx$ ^discipline$ ^driver_update$ ^enddiscipline$ ^endconnectrules$ ^exclude$ ^exp$ ^final_step$ ^flicker_noise$ ^floor$ ^flow$ ^from$ ^ground$ ^hypot$ ^idt$ ^idtmod$ ^inf$ ^initial_step$ ^laplace_nd$ ^laplace_np$ ^laplace_zd$ ^laplace_zp$ ^last_crossing$ ^limexp$ ^ln$ ^log$ ^max$ ^min$ ^nature$ ^net_resolution$ ^noise_table$ ^paramset$ ^potential$ ^pow$ ^pulldown$ ^sin$ ^sinh$ ^slew$ ^tan$ ^tanh$ ^timer$ ^transition$ ^white_noise$ ^wreal$ ^zi_nd$ ^zi_np$ ^zi_zd$ ^VCC ^vcc ^VDD ^vdd ^VSS ^vss}
+
+configure_lint_tag -enable -tag "AlwaysEnabledCG"  -severity Error
+
+configure_lint_tag -enable -tag "AlwaysDisabledCG"  -severity Error
+
+configure_lint_tag -enable -tag "FewSeqOnCG"  -severity Warning
+
+configure_lint_tag -enable -tag "54005" -severity Error
+
+configure_lint_tag_parameter -tag "54005" -parameter BIST_CMP_REGEX -value {.*BIST_CMP.*}
+
+configure_lint_tag_parameter -tag "54005" -parameter BIST_REN_REGEX -value {.*BIST_REN.*}
+
+configure_lint_tag_parameter -tag "54005" -parameter ENABLE_SANITY_CHECK -value {1}
+
+configure_lint_tag_parameter -tag "54005" -parameter EXCLUDE_REGEX -value {.*ungated.*|.*fwls.*|.*dfx_mbist.*}
+
+configure_lint_tag -enable -tag "54006"  -severity Error
+
+configure_lint_tag_parameter -tag "54006" -parameter EXCLUDE_REGEX -value {.*ungated.*|.*fwls.*|.*dfx_mbist.*}
+
+configure_lint_tag -enable -tag "54007"  -severity Error
+
+configure_lint_tag_parameter -tag "54007" -parameter EXCLUDE_REGEX -value {.*ungated.*|.*fwls.*|.*dfx_mbist.*}
+
+configure_lint_tag -enable -tag "54009"  -severity Error
+
+configure_lint_tag -enable -tag "60701"  -severity Error
+
+configure_lint_tag_parameter -tag "60701" -parameter MODULES_REGEXP -value {^(b12.*|d04.*|b05.*|b14.*|b15.*|cc0.*|ec0.*|e05.*|yc8.*|fa0.*|f05.*)}
+
+configure_lint_tag -enable -tag "60152"  -severity Error
+
+configure_lint_tag_parameter -tag "60152" -parameter PATTERN_REGEXP -value {(.*ctech.*|.*_macro_tech_map\.vh$)}
+
+configure_lint_tag -enable -tag "60702"  -severity Error
+
+configure_lint_tag_parameter -tag "60702" -parameter CTECH_LIB_REGEXP -value {^ctech_lib.*|^Ctech_lib.*}
+
+configure_lint_tag_parameter -tag "60702" -parameter MAP_FILE_REGEXP -value {(\w+)_map\.(v|sv)$}
+
+configure_lint_tag -enable -tag "60703"  -severity Error
+
+configure_lint_tag_parameter -tag "60703" -parameter CTECH_LIB_REGEXP -value {^ctech_lib.*|^Ctech_lib.*}
+
+configure_lint_tag_parameter -tag "60703" -parameter MAP_FILE_REGEXP -value {(\w+)_map\.(v|sv)$}
+
+configure_lint_tag -enable -tag "60704"  -severity Info
+
+configure_lint_tag_parameter -tag "60704" -parameter CTECH_LIB_REGEXP -value {^ctech_lib.*|^Ctech_lib.*}
+
+configure_lint_tag_parameter -tag "60704" -parameter MAP_FILE_REGEXP -value {(\w+)_map\.(v|sv)$}
+
+configure_lint_tag -enable -tag "60706"  -severity Error
+
+configure_lint_tag_parameter -tag "60706" -parameter CTECH_LIB_REGEXP -value {^ctech_lib.*|^Ctech_lib.*}
+
+configure_lint_tag_parameter -tag "60706" -parameter EXCLUDE_FILE -value {/nfs/site/disks/hdk_.*|/nfs/site/proj/tech1/.*}
+
+configure_lint_tag_parameter -tag "60706" -parameter EXCLUDE_PATH -value {/p/hdk/cad/ctech/.*|/nfs/site/disks/crt_tools.*|/nfs/site/disks/.crt_tools.*|/nfs/site/disks/hdk.cad.*|/nfs/site/disks/hdk_stdroot.*|/p/hdk/cad/stdcells/.*|/nfs/site/disks/crt_stdcells.*}
+
+configure_lint_tag_parameter -tag "60706" -parameter MAP_FILE_REGEXP -value {(\w+)_map\.(v|sv)$}
+
+configure_lint_tag -enable -tag "70600"  -severity Error
+
+configure_lint_tag_parameter -tag "70600" -parameter DFT_ARRAYMODULES_REGEXP -value {.*dfx_wrapper|.*MSWT_WRP}
+
+configure_lint_tag_parameter -tag "70600" -parameter VISA_MODULES_REGEXP -value {visa_(iomapper|unit|partition|repeater|central)_[0-9a-z_]+}
+
+configure_lint_tag_parameter -tag "70600" -parameter VISA_MODULES_TO_IGNORE -value {visa_clk_mux,visa_mux_stage,visa_lane_mux,visa_lane_mux_slider}
+
+configure_lint_tag -enable -tag "70601"  -severity Error
+
+configure_lint_tag_parameter -tag "70601" -parameter VISA_INPUT_PORT2_CHECKREGEXP -value {lane_in}
+
+configure_lint_tag_parameter -tag "70601" -parameter VISA_MODULES_REGEXP -value {visa_(iomapper|unit|partition|repeater|central)_[0-9a-z_]+}
+
+configure_lint_tag_parameter -tag "70601" -parameter VISA_MODULES_TO_IGNORE -value {visa_clk_mux,visa_mux_stage,visa_lane_mux,visa_lane_mux_slider}
+
+configure_lint_tag_parameter -tag "70601" -parameter REPORT_OVERLAPPING_PATHS -value {yes}
+
+configure_lint_tag -enable -tag "70602"  -severity Error
+
+configure_lint_tag_parameter -tag "70602" -parameter VISA_INPUT_PORT2_CHECKREGEXP -value {lane_in}
+
+configure_lint_tag_parameter -tag "70602" -parameter VISA_MODULES_REGEXP -value {visa_(iomapper|unit|partition|repeater|central)_[0-9a-z_]+}
+
+configure_lint_tag_parameter -tag "70602" -parameter VISA_MODULES_TO_IGNORE -value {visa_clk_mux,visa_mux_stage,visa_lane_mux,visa_lane_mux_slider}
+
+configure_lint_tag_parameter -tag "70602" -parameter REPORT_OVERLAPPING_PATHS -value {no}
+
+configure_lint_tag -enable -tag "70603"  -severity Error
+
+configure_lint_tag_parameter -tag "70603" -parameter VISA_INPUT_PORT2_CHECKREGEXP -value {lane_in}
+
+configure_lint_tag_parameter -tag "70603" -parameter VISA_MODULES_REGEXP -value {visa_(iomapper|unit|partition|repeater|central)_[0-9a-z_]+}
+
+configure_lint_tag_parameter -tag "70603" -parameter VISA_MODULES_TO_IGNORE -value {visa_clk_mux,visa_mux_stage,visa_lane_mux,visa_lane_mux_slider}
+
+configure_lint_tag_parameter -tag "70603" -parameter REPORT_OVERLAPPING_PATHS -value {yes}
+
+configure_lint_tag -enable -tag "70604"  -severity Warning
+
+configure_lint_tag_parameter -tag "70604" -parameter VISA_MODULES_REGEXP -value {visa_(iomapper|unit|partition|repeater|central)_[0-9a-z_]+}
+
+configure_lint_tag_parameter -tag "70604" -parameter VISA_MODULES_TO_IGNORE -value {visa_clk_mux,visa_mux_stage,visa_lane_mux,visa_lane_mux_slider}
+
+configure_lint_tag -enable -tag "70605"  -severity Info
+
+configure_lint_tag_parameter -tag "70605" -parameter VISA_MODULES_REGEXP -value {visa_(iomapper|unit|partition|repeater|central)_[0-9a-z_]+}
+
+configure_lint_tag_parameter -tag "70605" -parameter VISA_MODULES_TO_IGNORE -value {visa_clk_mux,visa_mux_stage,visa_lane_mux,visa_lane_mux_slider}
+
+configure_lint_tag -enable -tag "70605_Info"  -severity Info
+
+configure_lint_tag_parameter -tag "70605_Info" -parameter VISA_MODULES_REGEXP -value {visa_(iomapper|unit|partition|repeater|central)_[0-9a-z_]+}
+
+configure_lint_tag_parameter -tag "70605_Info" -parameter VISA_MODULES_TO_IGNORE -value {visa_clk_mux,visa_mux_stage,visa_lane_mux,visa_lane_mux_slider}
+
+configure_lint_tag -enable -tag "70606"  -severity Error
+
+configure_lint_tag_parameter -tag "70606" -parameter VISA_MODULES_REGEXP -value {visa_(iomapper|unit|partition|repeater|central)_[0-9a-z_]+}
+
+configure_lint_tag_parameter -tag "70606" -parameter VISA_MODULES_TO_IGNORE -value {visa_clk_mux,visa_mux_stage,visa_lane_mux,visa_lane_mux_slider}
+
+configure_lint_tag_parameter -tag "70606" -parameter REPORT_OVERLAPPING_PATHS -value {yes}
+
+configure_lint_tag -enable -tag "70607"  -severity Warning
+
+configure_lint_tag_parameter -tag "70607" -parameter VISA_MODULES_REGEXP -value {visa_(iomapper|unit|partition|repeater|central)_[0-9a-z_]+}
+
+configure_lint_tag_parameter -tag "70607" -parameter VISA_MODULES_TO_IGNORE -value {visa_clk_mux,visa_mux_stage,visa_lane_mux,visa_lane_mux_slider}
+
+configure_lint_tag -enable -tag "70608"  -severity Error
+
+configure_lint_tag_parameter -tag "70608" -parameter VISA_MODULES_REGEXP -value {visa_(iomapper|unit|partition|repeater|central)_[0-9a-z_]+}
+
+configure_lint_tag_parameter -tag "70608" -parameter VISA_MODULES_TO_IGNORE -value {visa_clk_mux,visa_mux_stage,visa_lane_mux,visa_lane_mux_slider}
+
+configure_lint_tag -enable -tag "70609"  -severity Error
+
+configure_lint_tag_parameter -tag "70609" -parameter STAY_EMPTY_PORTNAME -value {.*xbar_out}
+
+configure_lint_tag_parameter -tag "70609" -parameter VISA_MODULES_REGEXP -value {visa_(iomapper|unit|partition|repeater|central)_[0-9a-z_]+}
+
+configure_lint_tag_parameter -tag "70609" -parameter VISA_MODULES_TO_IGNORE -value {visa_clk_mux,visa_mux_stage,visa_lane_mux,visa_lane_mux_slider}
+
+configure_lint_tag -enable -tag "70610"  -severity Error
+
+configure_lint_tag_parameter -tag "70610" -parameter VISA_MODULES_REGEXP -value {visa_(iomapper|unit|partition|repeater|central)_[0-9a-z_]+}
+
+configure_lint_tag_parameter -tag "70610" -parameter VISA_MODULES_TO_IGNORE -value {visa_clk_mux,visa_mux_stage,visa_lane_mux,visa_lane_mux_slider}
+
+configure_lint_tag -enable -tag "70611"  -severity Error
+
+configure_lint_tag_parameter -tag "70611" -parameter VISA_MODULES_REGEXP -value {visa_(iomapper|unit|partition|repeater|central)_[0-9a-z_]+}
+
+configure_lint_tag_parameter -tag "70611" -parameter VISA_MODULES_TO_IGNORE -value {visa_clk_mux,visa_mux_stage,visa_lane_mux,visa_lane_mux_slider}
+
+configure_lint_tag -enable -tag "70612"  -severity Error
+
+configure_lint_tag_parameter -tag "70612" -parameter VISA_CONFIG_INPUTPIN -value {serial_cfg_in.*}
+
+configure_lint_tag_parameter -tag "70612" -parameter VISA_CONFIG_OUTPUTPIN -value {serial_cfg_out.*}
+
+configure_lint_tag_parameter -tag "70612" -parameter VISA_MODULES_REGEXP -value {visa_(iomapper|unit|partition|repeater|central)_[0-9a-z_]+}
+
+configure_lint_tag_parameter -tag "70612" -parameter VISA_MODULES_TO_IGNORE -value {visa_clk_mux,visa_mux_stage,visa_lane_mux,visa_lane_mux_slider}
+
+configure_lint_tag_parameter -tag "70612" -parameter REPORT_OVERLAPPING_PATHS -value {yes}
+
+configure_lint_tag -enable -tag "68801"  -severity Error
+
+configure_lint_tag -enable -tag "InvalidAutoAssign"  -severity Error
+
+configure_lint_tag -enable -tag "68803"  -severity Error
+
+configure_lint_tag -enable -tag "68804"  -severity Error
+
+configure_lint_tag -enable -tag "68805"  -severity Error
+
+configure_lint_tag -enable -tag "00843"  -severity Error
+
+configure_lint_tag -enable -tag "STARC05-2.2.2.2b"  -severity Error
+
+configure_lint_tag -enable -tag "SensListRepeat-ML"  -severity Error
+
+configure_lint_tag -enable -tag "STARC05-2.2.2.3a" -severity Error
+
+configure_lint_tag_parameter -tag "STARC05-2.2.2.3a" -parameter STRICT -value {no}
+
+configure_lint_tag -enable -tag "W164a_a"  -severity Error
+
+configure_lint_tag -enable -tag "W164a_a" -type_id SG_LINT_W164A_A_VERILOG_ASSIGN_WIDTH_MISMATCH_DEADCODE -severity Warning
+
+configure_lint_tag -enable -tag "W164a_a" -type_id SG_LINT_W164A_A_VERILOG_ASSIGN_WIDTH_MISMATCH_NBA_DEADCODE -severity Warning
+
+configure_lint_tag -enable -tag "W164a_a" -type_id SG_LINT_W164A_A_VERILOG_CONCAT_ASSIGN_WIDTH_MISMATCH_DEADCODE -severity Warning
+
+configure_lint_tag -enable -tag "W164a_a" -type_id SG_LINT_W164A_A_VERILOG_CONCAT_ASSIGN_WIDTH_MISMATCH_NBA_DEADCODE -severity Warning
+
+configure_lint_tag -enable -tag "W164a_a" -type_id SG_LINT_W164A_A_VERILOG_PACKED_CONCAT_ASSIGN_WIDTH_MISMATCH_DEADCODE -severity Warning
+
+configure_lint_tag -enable -tag "W164a_a" -type_id SG_LINT_W164A_A_VERILOG_PACKED_CONCAT_ASSIGN_WIDTH_MISMATCH_NBA_DEADCODE -severity Warning
+
+configure_lint_tag -enable -tag "W164a_a" -type_id SG_LINT_W164A_A_VERILOG_W164_SS_DEADCODE -severity Warning
+
+configure_lint_tag_parameter -tag "W164a_a" -parameter CHECK_NATURAL_WIDTH_OF_MULTIPLICATION -value {yes}
+
+configure_lint_tag_parameter -tag "W164a_a" -parameter CHECK_STATIC_VALUE -value {yes}
+
+configure_lint_tag_parameter -tag "W164a_a" -parameter CONCAT_WIDTH_NF -value {yes}
+
+configure_lint_tag_parameter -tag "W164a_a" -parameter ENABLE_RTL_DEADCODE -value {yes}
+
+configure_lint_tag_parameter -tag "W164a_a" -parameter HANDLE_LRM_PARAM_IN_SHIFT -value {yes}
+
+configure_lint_tag_parameter -tag "W164a_a" -parameter HANDLE_SHIFT_OP -value {shift_both}
+
+configure_lint_tag_parameter -tag "W164a_a" -parameter HANDLE_ZERO_PADDING -value {yes}
+
+configure_lint_tag_parameter -tag "W164a_a" -parameter NOCHECKOVERFLOW -value {no}
+
+configure_lint_tag_parameter -tag "W164a_a" -parameter PROCESS_COMPLETE_CONDOP -value {yes}
+
+configure_lint_tag_parameter -tag "W164a_a" -parameter STRICT -value {yes}
+
+configure_lint_tag_parameter -tag "W164a_a" -parameter TREAT_CONCAT_ASSIGN_SEPARATELY -value {yes}
+
+configure_lint_tag_parameter -tag "W164a_a" -parameter REPORT_ONLY_FROM_ONE_HIERARCHY -value {yes}
+
+configure_lint_tag -enable -tag "W164a_b"  -severity Warning
+
+configure_lint_tag_parameter -tag "W164a_b" -parameter CHECK_COUNTER_ASSIGNMENT -value {yes}
+
+configure_lint_tag_parameter -tag "W164a_b" -parameter CHECK_NATURAL_WIDTH_OF_MULTIPLICATION -value {yes}
+
+configure_lint_tag_parameter -tag "W164a_b" -parameter CHECK_STATIC_VALUE -value {yes}
+
+configure_lint_tag_parameter -tag "W164a_b" -parameter CONCAT_WIDTH_NF -value {yes}
+
+configure_lint_tag_parameter -tag "W164a_b" -parameter ENABLE_RTL_DEADCODE -value {yes}
+
+configure_lint_tag_parameter -tag "W164a_b" -parameter HANDLE_LRM_PARAM_IN_SHIFT -value {yes}
+
+configure_lint_tag_parameter -tag "W164a_b" -parameter HANDLE_SHIFT_OP -value {shift_both}
+
+configure_lint_tag_parameter -tag "W164a_b" -parameter HANDLE_ZERO_PADDING -value {yes}
+
+configure_lint_tag_parameter -tag "W164a_b" -parameter NOCHECKOVERFLOW -value {no}
+
+configure_lint_tag_parameter -tag "W164a_b" -parameter PROCESS_COMPLETE_CONDOP -value {yes}
+
+configure_lint_tag_parameter -tag "W164a_b" -parameter STRICT -value {yes}
+
+configure_lint_tag_parameter -tag "W164a_b" -parameter TREAT_CONCAT_ASSIGN_SEPARATELY -value {yes}
+
+configure_lint_tag_parameter -tag "W164a_b" -parameter REPORT_ONLY_FROM_ONE_HIERARCHY -value {yes}
+
+configure_lint_tag -enable -tag "W164b_a"  -severity Error
+
+configure_lint_tag_parameter -tag "W164b_a" -parameter CHECK_NATURAL_WIDTH_OF_MULTIPLICATION -value {yes}
+
+configure_lint_tag_parameter -tag "W164b_a" -parameter CHECK_STATIC_VALUE -value {yes}
+
+configure_lint_tag_parameter -tag "W164b_a" -parameter CONCAT_WIDTH_NF -value {yes}
+
+configure_lint_tag_parameter -tag "W164b_a" -parameter ENABLE_RTL_DEADCODE -value {yes}
+
+configure_lint_tag_parameter -tag "W164b_a" -parameter HANDLE_LRM_PARAM_IN_SHIFT -value {yes}
+
+configure_lint_tag_parameter -tag "W164b_a" -parameter HANDLE_SHIFT_OP -value {shift_left}
+
+configure_lint_tag_parameter -tag "W164b_a" -parameter HANDLE_ZERO_PADDING -value {yes}
+
+configure_lint_tag_parameter -tag "W164b_a" -parameter NOCHECKOVERFLOW -value {no}
+
+configure_lint_tag_parameter -tag "W164b_a" -parameter PROCESS_COMPLETE_CONDOP -value {yes}
+
+configure_lint_tag_parameter -tag "W164b_a" -parameter STRICT -value {yes}
+
+configure_lint_tag_parameter -tag "W164b_a" -parameter TREAT_CONCAT_ASSIGN_SEPARATELY -value {yes}
+
+configure_lint_tag_parameter -tag "W164b_a" -parameter REPORT_ONLY_FROM_ONE_HIERARCHY -value {yes}
+
+configure_lint_tag -enable -tag "W164b_b"  -severity Warning
+
+configure_lint_tag_parameter -tag "W164b_b" -parameter CHECK_NATURAL_WIDTH_OF_MULTIPLICATION -value {yes}
+
+configure_lint_tag_parameter -tag "W164b_b" -parameter CHECK_STATIC_VALUE -value {yes}
+
+configure_lint_tag_parameter -tag "W164b_b" -parameter ENABLE_RTL_DEADCODE -value {yes}
+
+configure_lint_tag_parameter -tag "W164b_b" -parameter HANDLE_LRM_PARAM_IN_SHIFT -value {yes}
+
+configure_lint_tag_parameter -tag "W164b_b" -parameter HANDLE_SHIFT_OP -value {shift_left}
+
+configure_lint_tag_parameter -tag "W164b_b" -parameter HANDLE_ZERO_PADDING -value {yes}
+
+configure_lint_tag_parameter -tag "W164b_b" -parameter NOCHECKOVERFLOW -value {no}
+
+configure_lint_tag_parameter -tag "W164b_b" -parameter PROCESS_COMPLETE_CONDOP -value {yes}
+
+configure_lint_tag_parameter -tag "W164b_b" -parameter STRICT -value {yes}
+
+configure_lint_tag_parameter -tag "W164b_b" -parameter TREAT_CONCAT_ASSIGN_SEPARATELY -value {yes}
+
+configure_lint_tag_parameter -tag "W164b_b" -parameter REPORT_ONLY_FROM_ONE_HIERARCHY -value {yes}
+
+configure_lint_tag -enable -tag "W362a"  -severity Error
+
+configure_lint_tag_parameter -tag "W362a" -parameter CHECK_STATIC_VALUE -value {yes}
+
+configure_lint_tag_parameter -tag "W362a" -parameter ENABLE_RTL_DEADCODE -value {yes}
+
+configure_lint_tag_parameter -tag "W362a" -parameter HANDLE_ZERO_PADDING -value {yes}
+
+configure_lint_tag_parameter -tag "W362a" -parameter NOCHECKOVERFLOW -value {no}
+
+configure_lint_tag_parameter -tag "W362a" -parameter STRICT -value {yes}
+
+configure_lint_tag_parameter -tag "W362a" -parameter REPORT_ONLY_FROM_ONE_HIERARCHY -value {yes}
+
+configure_lint_tag -enable -tag "W362b"  -severity Error
+
+configure_lint_tag_parameter -tag "W362b" -parameter CHECK_STATIC_VALUE -value {yes}
+
+configure_lint_tag_parameter -tag "W362b" -parameter ENABLE_RTL_DEADCODE -value {yes}
+
+configure_lint_tag_parameter -tag "W362b" -parameter HANDLE_ZERO_PADDING -value {yes}
+
+configure_lint_tag_parameter -tag "W362b" -parameter NOCHECKOVERFLOW -value {no}
+
+configure_lint_tag_parameter -tag "W362b" -parameter STRICT -value {yes}
+
+configure_lint_tag_parameter -tag "W362b" -parameter REPORT_ONLY_FROM_ONE_HIERARCHY -value {yes}
+
+configure_lint_tag_parameter -tag "W110_a" -parameter HANDLE_SHIFT_OP -value {shift_both}
+
+configure_lint_tag_parameter -tag "W110_a" -parameter HANDLE_ZERO_PADDING -value {yes}
+
+configure_lint_tag_parameter -tag "W110_a" -parameter NOCHECKOVERFLOW -value {no}
+
+configure_lint_tag -enable -tag "W110_b"  -severity Error
+
+configure_lint_tag_parameter -tag "W110_b" -parameter HANDLE_SHIFT_OP -value {shift_both}
+
+configure_lint_tag_parameter -tag "W110_b" -parameter HANDLE_ZERO_PADDING -value {yes}
+
+configure_lint_tag_parameter -tag "W110_b" -parameter NOCHECKOVERFLOW -value {no}
+
+configure_lint_tag -enable -tag "W348"  -severity Error
+
+configure_lint_tag -enable -tag "STARC05-2.10.3.7" -severity Error
+
+configure_lint_tag_parameter -tag "STARC05-2.10.3.7" -parameter IGNORE_BASED_WIDTH -value {yes}
+
+configure_lint_tag_parameter -tag "STARC05-2.10.3.7" -parameter STRICT -value {no}
+
+configure_lint_tag -enable -tag "STARC05-2.10.3.6" -severity Error
+
+configure_lint_tag_parameter -tag "STARC05-2.10.3.6" -parameter BITWIDTH_BASEDCONST -value {32}
+
+configure_lint_tag_parameter -tag "STARC05-2.10.3.6" -parameter STRICT -value {no}
+
+configure_lint_tag -enable -tag "STARC05-1.4.3.1a" -severity Warning
+
+configure_lint_tag_parameter -tag "STARC05-1.4.3.1a" -parameter IGNORECELLNAME -value {ctech_lib_clk_ffb,ctech_lib_clk_ffb_rstb,ctech_lib_clk_divider2,ctech_lib_clk_divider2_rstb}
+
+configure_lint_tag_parameter -tag "STARC05-1.4.3.1a" -parameter IGNOREMODNAME -value {ctech_lib_clk.*}
+
+configure_lint_tag -enable -tag "STARC05-1.4.3.1b" -severity Warning
+
+configure_lint_tag_parameter -tag "STARC05-1.4.3.1b" -parameter IGNORECELLNAME -value {ctech_lib_clk_ffb,ctech_lib_clk_ffb_rstb,ctech_lib_clk_divider2,ctech_lib_clk_divider2_rstb}
+
+configure_lint_tag_parameter -tag "STARC05-1.4.3.1b" -parameter IGNOREMODNAME -value {ctech_lib_clk.*}
+
+configure_lint_tag -enable -tag "FlopClockUndriven" -severity Error
+
+configure_lint_tag_parameter -tag "FlopClockUndriven" -parameter ALLVIOL -value {yes}
+
+#configure_lint_tag -enable -tag "ClockEnableRace" -severity Warning
+
+#configure_lint_tag_parameter -tag "ClockEnableRace" -parameter CHECKCOMBLOGIC -value {yes}
+
+#configure_lint_tag_parameter -tag "ClockEnableRace" -parameter IGNORE_HANGING_FLOP -value {yes}
+
+#configure_lint_tag_parameter -tag "ClockEnableRace" -parameter REPORT_COMMON_SOURCE -value {yes}
+
+configure_lint_tag -enable -tag "sim_race07" -severity Error
+
+configure_lint_tag -enable -tag "sim_race04" -severity Error
+
+#configure_lint_tag -enable -tag "clock_used_as_data" -severity Warning
+
+#configure_lint_tag_parameter -tag "clock_used_as_data" -parameter ALLVIOL -value {yes}
+
+configure_lint_tag -enable -tag "70094"  -severity Error
+
+configure_lint_tag_parameter -tag "70094" -parameter CHECKSEQPHASE -value {yes}
+
+configure_lint_tag -enable -tag "W193"  -severity Error
+
+configure_lint_tag_parameter -tag "W193" -parameter REPORT_IF_BLOCKS_ONLY -value {yes}
+
+configure_lint_tag -enable -tag "IfWithoutElse-ML" -severity Error
+
+configure_lint_tag_parameter -tag "IfWithoutElse-ML" -parameter IGNOREREALLATCH -value {yes}
+
+configure_lint_tag_parameter -tag "IfWithoutElse-ML" -parameter IGNORE_LOOP_INDEX -value {yes}
+
+configure_lint_tag_parameter -tag "IfWithoutElse-ML" -parameter IGNORE_STATIC_CONDITION -value {yes}
+
+configure_lint_tag -enable -tag "AlwaysFalseTrueCond-ML" -type_id SG_MORELINT_ALWAYSFALSETRUECOND_ML_VERILOG_ALWAYSFALSETRUECOND_ML_VE -severity Error
+
+configure_lint_tag -enable -tag "AlwaysFalseTrueCond-ML" -type_id SG_MORELINT_ALWAYSFALSETRUECOND_ML_VERILOG_ALWAYSFALSETRUECOND_ML_VE_1 -severity Warning
+
+configure_lint_tag_parameter -tag "AlwaysFalseTrueCond-ML" -parameter EVALUATE_FOR_LOOP_INDEX -value {yes}
+
+configure_lint_tag_parameter -tag "AlwaysFalseTrueCond-ML" -parameter IGNORE_COND_HAVING_IDENTIFIER -value {yes}
+
+configure_lint_tag_parameter -tag "AlwaysFalseTrueCond-ML" -parameter REPORT_ALWAYS_COND -value {false}
+
+configure_lint_tag_parameter -tag "AlwaysFalseTrueCond-ML" -parameter REPORT_LESS_SEVERITY -value {yes}
+
+configure_lint_tag -enable -tag "W527"  -severity Warning
+
+configure_lint_tag -enable -tag "60000_a"  -severity Error
+
+configure_lint_tag_parameter -tag "60000_a" -parameter CHECK_OUTPUT_PORTS -value {yes}
+
+#configure_lint_tag_parameter -tag "60000_a" -parameter IGNORE_FUNCTION_INITIALIZATION -value {yes}
+
+configure_lint_tag -enable -tag "NullPort-ML" -severity Error
+
+configure_lint_tag -enable -tag "W192"  -severity Warning
+
+configure_lint_tag -enable -tag "2218"  -severity Error
+
+configure_lint_tag -enable -tag "50520"  -severity Error
+
+configure_lint_tag_parameter -tag "50520" -parameter IFDEFS -value {SVA_OFF,VCSSIM,INST_ON,DC,SYNTHESIS,VCS,FGPA,QUICKCOV_INST_ENABLE,QC_COVER_ENABLE,MANUAL_XPROP,ASSERT_OFF,ASSERT_ON,SIMULATION,XPROPAGATION,HIPS_PS_RESOLUTION,PULSE_WIDTH_OFF,no_unit_delay,VCS_BUG,LINTRA_BUG,SPYGLASS_BUG,QUESTACDC_BUG,DC_BUG,VELOCE_BUG,ZEBU_BUG,FISHTAIL_BUG,FEV_BUG,SYNPLICITY_BUG,POWERARTIST_BUG,VERDI_BUG,JASPERGOLD_BUG,EMULATION,NO_PWR_PINS,JEM_STANDALONE,JEM_USE_DPI_ENABLING,SLA_RTL_TLM_PORTS_OFF,SLA_RTL_TLM_MONITOR_INST_OFF,SLA_EXTERNAL_RTL_TLM_IMPL,JEM_TLM_PORTS_OFF,JEM_NO_CDT_DPI,JEM_NO_DPI_IN_INITIAL,JEM_INIT_CLK,JEM_INIT_CLK_EDGE,JEM_TLM_PORT_ENABLE_INIT_STATE,JEM_EMILATION_ZSE,JEM_COV_SAMPLE_CLK,QUICKCOV_JEM_COLLECTION,OVM,UVM,SNPS201412B}
+
+configure_lint_tag -enable -tag "52544"  -severity Error
+
+configure_lint_tag -enable -tag "ExprParen" -severity Error
+
+configure_lint_tag_parameter -tag "ExprParen" -parameter ALLOWEDOPPRECEDENCE -value {(a + b * c)(a - b * c)(a + b / c)(a - b / c)(a - b + c)(a * b / c)(a - b - c)(a + b + c)(a * b * c)(a / b/ c)(!a)(~a)(a & b & c)(a | b | c)}
+
+configure_lint_tag_parameter -tag "ExprParen" -parameter DISPLAYEXPRESSION -value {yes}
+
+configure_lint_tag_parameter -tag "ExprParen" -parameter IGNORE_MODULE -value {1}
+
+configure_lint_tag -enable -tag "CheckExprCast" -severity Error
+
+configure_lint_tag -enable -tag "SignedUnsignedExpr-ML" -severity Error
+
+configure_lint_tag_parameter -tag "SignedUnsignedExpr-ML" -parameter IGNORE_STATIC_EXPRS -value {yes}
+
+configure_lint_tag_parameter -tag "SignedUnsignedExpr-ML" -parameter IGNOREFORINDEX -value {yes}
+
+configure_lint_tag_parameter -tag "SignedUnsignedExpr-ML" -parameter STRICT -value {no}
+
+configure_lint_tag -enable -tag "W129"  -severity Error
+
+configure_lint_tag -enable -tag "W188"  -severity Error
+
+configure_lint_tag -enable -tag "W504"  -severity Error
+
+configure_lint_tag_parameter -tag "W504" -parameter STRICT -value {yes}
+
+configure_lint_tag -enable -tag "InvalidMacroCall-ML" -severity Error
+
+configure_lint_tag -enable -tag "60047"  -severity Error
+
+configure_lint_tag -enable -tag "check_forloop_index" -severity Info
+
+configure_lint_tag -enable -tag "60118"  -severity Error
+
+configure_lint_tag -enable -tag "0209"  -severity Error
+
+configure_lint_tag -enable -tag "STARC05-2.8.1.5" -severity Error
+
+configure_lint_tag -enable -tag "STARC05-2.8.5.1" -severity Error
+
+configure_lint_tag -enable -tag "W171"  -severity Warning
+
+configure_lint_tag_parameter -tag "W171" -parameter IGNORE_CONST_SELECTOR -value {yes}
+
+configure_lint_tag -enable -tag "DuplicateCase-ML" -severity Error
+
+configure_lint_tag_parameter -tag "DuplicateCase-ML" -parameter IGNORE_PRIORITY_CASE -value {yes}
+
+configure_lint_tag -enable -tag "STARC05-2.8.3.5" -severity Warning
+
+configure_lint_tag -enable -tag "UseSVAlways-ML" -severity Error
+
+configure_lint_tag_parameter -tag "UseSVAlways-ML" -parameter STRICT -value {yes}
+
+configure_lint_tag -enable -tag "2216"  -severity Error
+
+configure_lint_tag_parameter -tag "2216" -parameter VIOLATE_SAME_SIGNAL_ONLY -value {yes}
+
+configure_lint_tag -enable -tag "RptNegEdgeFF-ML" -severity Info
+
+configure_lint_tag -enable -tag "UnInitializedReset-ML" -severity Error
+
+configure_lint_tag_parameter -tag "UnInitializedReset-ML" -parameter IGNORE_SYNC_RESET -value {yes}
+
+configure_lint_tag -enable -tag "RegInput-ML" -severity Warning
+
+configure_lint_tag_parameter -tag "RegInput-ML" -parameter DEPTH_ML -value {1}
+
+configure_lint_tag -enable -tag "RegOutputs" -severity Warning
+
+configure_lint_tag_parameter -tag "RegOutputs" -parameter REPORTUNDRIVENOUT -value {no}
+
+configure_lint_tag -enable -tag "AvoidAsync" -severity Info
+
+configure_lint_tag -enable -tag "02084"  -severity Error
+
+configure_lint_tag -enable -tag "0536"  -severity Error
+
+configure_lint_tag -enable -tag "STARC05-2.2.3.1" -severity Error
+
+configure_lint_tag -enable -tag "0563"  -severity Error
+
+configure_lint_tag -enable -tag "60041"  -severity Error
+
+configure_lint_tag -enable -tag "60086"  -severity Error
+
+configure_lint_tag -enable -tag "60137"  -severity Error
+
+configure_lint_tag -enable -tag "W372"  -severity Error
+
+configure_lint_tag_parameter -tag "W372" -parameter REPORT_CAST -value {yes}
+
+configure_lint_tag -enable -tag "UnsetProcedureRecord" -severity Warning
+
+configure_lint_tag -enable -tag "50002"  -severity Error
+
+configure_lint_tag_parameter -tag "50002" -parameter CHECK_PARTIAL_CASE_CASEZ -value {yes}
+
+configure_lint_tag_parameter -tag "50002" -parameter IGNORE_X_INCASE_CASEZ -value {yes}
+
+configure_lint_tag -enable -tag "DisallowXInCaseZ-ML" -severity Error
+
+configure_lint_tag -enable -tag "OneModule-ML" -severity Error
+
+configure_lint_tag_parameter -tag "OneModule-ML" -parameter IGNOREFILES -value {(.*ctech.*|.*LVISION.*|.*_map\.sv$|.*mbist.*|.*\.lib$)}
+
+configure_lint_tag -enable -tag "STARC05-1.1.1.1" -severity Error
+
+configure_lint_tag_parameter -tag "STARC05-1.1.1.1" -parameter IGNORE_FILE_PATH -value {yes}
+
+configure_lint_tag_parameter -tag "STARC05-1.1.1.1" -parameter IGNORE_FILE_WITH_MULTIPLE_MODULES -value {yes}
+
+configure_lint_tag_parameter -tag "STARC05-1.1.1.1" -parameter STARC_FILE_EXT_VLOG -value {.v,.vs,.sv,.xfsm.vs}
+
+configure_lint_tag -enable -tag "FileHdr" -severity Warning
+
+configure_lint_tag_parameter -tag "FileHdr" -parameter FILE_HDR_IGNORE_PATH -value {.*src\/rtl\/tessent\/.*_(wrapper|uscg)_tessent.*\.v}
+
+configure_lint_tag_parameter -tag "FileHdr" -parameter IGNORE_FILES_WITH_STOPPED_MODULES -value {yes}
+
+configure_lint_tag -enable -tag "ModuleInIncludeFile" -severity Warning
+
+configure_lint_tag -enable -tag "ArrayIndex" -severity Error
+
+configure_lint_tag_parameter -tag "ArrayIndex" -parameter CHECKALLDIMENSION -value {yes}
+
+configure_lint_tag_parameter -tag "ArrayIndex" -parameter STRICT -value {no}
+
+configure_lint_tag -enable -tag "W468"  -severity Warning
+
+# SG rule SYNTH_5130 is mapped to ImproperRangeIndex-ML
+# SG rule SYNTH_5255 is also partially mapped to rule ImproperRangeIndex-ML,
+# therefore uprevving it to Error with the below exception for ceratin type_ids
+
+configure_lint_tag -enable -tag "ImproperRangeIndex-ML" -severity Warning
+
+configure_lint_tag -enable -tag "ImproperRangeIndex-ML" -type_id SG_MORELINT_IMPROPERRANGEINDEX_ML_VERILOG_IMPROPERRANGEINDEX_ML_STATICBITSELECT -severity Warning
+
+configure_lint_tag -enable -tag "ImproperRangeIndex-ML" -type_id SG_MORELINT_IMPROPERRANGEINDEX_ML_VERILOG_IMPROPERRANGEINDEX_ML_STATICPARTSELECT -severity Warning
+
+configure_lint_tag_parameter -tag "ImproperRangeIndex-ML" -parameter REPORT_LOOP_VAR_EXPR -value {yes}
+
+configure_lint_tag_parameter -tag "ImproperRangeIndex-ML" -parameter NOCHECKOVERFLOW -value {no}
+
+configure_lint_tag_parameter -tag "ImproperRangeIndex-ML" -parameter REPORT_STATIC_INDEXES -value {yes}
+
+configure_lint_tag_parameter -tag "ImproperRangeIndex-ML" -parameter REPORT_ONLY_FROM_ONE_HIERARCHY -value {yes}
+
+configure_lint_tag -enable -tag "W576"  -severity Error
+
+configure_lint_tag -enable -tag "ParamReDefined" -severity Warning
+
+configure_lint_tag_parameter -tag "ParamReDefined" -parameter IGNORE_MULTIPLE_PACKAGE_IMPORT -value {yes}
+
+configure_lint_tag_parameter -tag "ParamReDefined" -parameter IGNORE_PARAMS_WITH_SAME_VALUE -value {yes}
+
+configure_lint_tag -enable -tag "W154"  -severity Error
+
+configure_lint_tag_parameter -tag "W154" -parameter GROUP_BY_MODULE -value {yes}
+
+configure_lint_tag_parameter -tag "W154" -parameter IGNORE_FILES_REGEXP -value {.*collage.*|.*defacto.*}
+
+configure_lint_tag_parameter -tag "W154" -parameter REPORT_PORT_NET -value {yes}
+
+configure_lint_tag -enable -tag "2083"  -severity Warning
+
+configure_lint_tag -enable -tag "UnusedTypedef" -severity Warning
+
+configure_lint_tag -enable -tag "W175"  -severity Warning
+
+configure_lint_tag_parameter -tag "W175" -parameter REPORT_GLOBAL_PARAM -value {yes}
+
+configure_lint_tag -enable -tag "60175"  -severity Error
+
+configure_lint_tag -enable -tag "60044"  -severity Warning
+
+configure_lint_tag -enable -tag "0301"  -severity Warning
+
+configure_lint_tag -enable -tag "60130"  -severity Error
+
+
+configure_lint_tag -enable -tag "60159"  -severity Error
+
+#configure_lint_tag_parameter -tag "60159" -parameter DEFINITION_TYPES -value {functions,tasks,typedefs,parameters,local_parameters,import_statments}
+
+configure_lint_tag -enable -tag "ProhibitedDataTypes-ML" -severity Error
+
+configure_lint_tag_parameter -tag "ProhibitedDataTypes-ML" -parameter PROHIBITED_DATA_TYPES -value {logic,bit}
+
+configure_lint_tag -enable -tag "CheckExplicitImports" -severity Warning
+
+configure_lint_tag -enable -tag "UseParamInsteadDefine-ML" -severity Error
+
+configure_lint_tag -enable -tag "W259"  -severity Error
+
+configure_lint_tag -enable -tag "DetectInvalidSignedAssignment-ML" -severity Info
+
+configure_lint_tag -enable -tag "DetectUnderAndOverFlows-ML" -type_id SG_MORELINT_DETECTUNDERANDOVERFLOWS_ML_VERILOG_DETECTUNDERANDOVERFLOWS_ML_MSG_WARNING -severity Error
+
+configure_lint_tag -enable -tag "DetectUnderAndOverFlows-ML" -type_id SG_MORELINT_DETECTUNDERANDOVERFLOWS_ML_VERILOG_DETECTUNDERANDOVERFLOWS_ML_MSG_NC_TRUNCATION -severity Warning
+
+configure_lint_tag -enable -tag "DetectUnderAndOverFlows-ML" -type_id SG_MORELINT_DETECTUNDERANDOVERFLOWS_ML_VERILOG_DETECTUNDERANDOVERFLOWS_ML_MSG_INFO -severity Warning
+
+configure_lint_tag_parameter -tag "DetectUnderAndOverFlows-ML" -parameter CHECK_TYPE_CAST -value {yes}
+
+configure_lint_tag_parameter -tag "DetectUnderAndOverFlows-ML" -parameter NOCHECKOVERFLOW -value {no}
+
+configure_lint_tag_parameter -tag "DetectUnderAndOverFlows-ML" -parameter HANDLE_SHIFT_OP -value {shift_left}
+
+configure_lint_tag_parameter -tag "DetectUnderAndOverFlows-ML" -parameter DIFFERENTIATE_NESTED_CAST -value {yes}
+
+configure_lint_tag -enable -tag "UseParamInsteadDefine-ML" -severity Error
+
+configure_lint_tag -enable -tag "IfOverlap-ML" -severity Error
+
+configure_lint_tag -enable -tag "UniqueIfMissingCond-ML" -severity Error -formal
+
+configure_lint_tag -enable -tag "CheckGuardMacro" -severity Error
+
+configure_lint_tag_parameter -tag "CheckGuardMacro" -parameter CHECK_FILE_NAME -value {yes}
+
+configure_lint_tag -enable -tag "AvoidMultiDimParam-ML" -severity Error
+
+# Rules for testing purposes ONLY
+
+#configure_lint_tag -enable -tag DefaultState -severity Warning
+
+#configure_lint_tag_parameter -tag "DefaultState" -parameter CHECK_ONLY_CASE_STMT -value {yes}
+
+set_app_var sh_continue_on_error $saved_sh_continue_on_error
+
+#################### Builtin Rule Configurations ####################
+
+set saved_sh_continue_on_error [get_app_var sh_continue_on_error]
+
+set_app_var sh_continue_on_error true
+
+#Rule configuration for SG rule : INFO_1010
+
+configure_tag -tag VC_INFO_UDP_TRANSLATE -enable -severity Error
+
+#Rule configuration for SG rule : SGDCWRN_127
+
+configure_tag -tag VC_PRAGMA_INCORRECT_RULE -disable
+
+#Rule configuration for SG rule : SGDC_waive35
+
+configure_tag -tag VC_WAIVER_BLOCK_NOT_FOUND -severity Warning
+
+# blanket waivers are NOT allowed : SGDC_waive39
+
+configure_tag -tag {VC_WAIVER_ONLY_TAG_GIVEN} -severity {Error}
+
+#Rule configuration for SG rule : SYNTH_1082
+
+configure_tag -tag OOECAIAB -enable -severity Error
+
+#Rule configuration for SG rule : SYNTH_1111
+
+configure_tag -tag SM_URT -enable -severity Error
+
+#Rule configuration for SG rule : SYNTH_12605
+
+configure_tag -tag { SM_FCNF SM_PCNP SM_PNP SM_TUFC } -enable -severity Warning
+
+#Rule configuration for SG rule : SYNTH_12608
+
+configure_tag -tag { SM_MCAL SM_MLAC SM_MLAFF } -enable -severity Error
+
+#Rule configuration for SG rule : SYNTH_132
+
+configure_tag -tag VC_SYNTH_HIER_REF -enable -severity Error
+
+#Rule configuration for SG rule : SYNTH_196
+
+configure_tag -tag VC_SYNTH_TASK_EVENT -enable -severity Error
+
+#Rule configuration for SG rule : SYNTH_5064
+
+configure_tag -tag VC_SYNTH_STMT_IGNORED -disable
+
+#Rule configuration for SG rule : SYNTH_5142
+
+configure_tag -tag VC_SYNTH_SPECIFY_UNSUPP -enable -severity Error
+
+#Rule configuration for SG rule : SYNTH_5143
+
+configure_tag -tag SM_IGN_INITIAL -disable
+
+#Rule configuration for SG rule : WRN_1036
+
+configure_tag -tag VC_WRN_EVENT_VALID -enable -severity Error
+
+#Rule configuration for SG rule : WRN_1041
+
+configure_tag -tag VC_WRN_UNDERSCORE_IGNORED -severity Error
+
+#Rule configuration for SG rule : WRN_1042
+
+configure_tag -tag IIPCNDO -enable -severity Error
+
+#Rule configuration for SG rule : WRN_1453
+
+configure_tag -tag VC_WRN_PORT_INVALID -enable -severity Error
+
+#Rule configuration for SG rule : WRN_1469
+
+configure_tag -tag ENUMASSIGN -enable -severity Warning
+
+#Rule configuration for SG rule : WRN_26
+
+configure_tag -tag TMR -enable -severity Error
+
+#Rule configuration for SG rule : WRN_32
+
+configure_tag -tag IICD -severity Warning
+
+#Rule configuration for SG rule : WRN_54 and WRN_1464
+
+configure_tag -tag AOUP -enable -severity Error
+
+#Rule configuration for SG rule : WRN_70
+
+configure_tag -tag SAGB -enable -severity Error
+
+configure_tag -tag  OPD -enable -severity Info
+
+#Rule configuration for SG rule: WRN_1467
+
+configure_tag -tag DPIMI -enable -severity Error
+
+# Rule configuration for SG rule: STX_VE_361
+
+#configure_tag -tag IUAO -enable -severity Fatal
+
+configure_tag -tag IBLHS-NT -enable -severity Fatal
+
+# Rule configuration for SG rule: STX_VE_467
+
+configure_tag -tag ICTA -enable -severity Fatal
+
+# Rule configuration for SG rule: STX_VE_462
+
+configure_tag -tag SV-USAC -enable -severity Fatal
+
+# Rule configuration for SG rule: WRN_40
+
+configure_tag -tag IPDW -enable -severity Fatal
+
+# Rule configuration for SG rule: WRN_1471
+
+configure_tag -tag USL -enable -severity Error
+
+#Rule configuration for SG rule : SYNTH_89
+
+configure_tag -tag VC_SYNTH_INITIAL_IGNORED -enable -severity Error
+
+set_app_var sh_continue_on_error $saved_sh_continue_on_error
+
+#################### Builtin Rule Configurations End
+####################
+
+#configure_lint_setup  -j 4
diff --git a/mpsoc/Integration_test/VCST/src/param_gen.pl b/mpsoc/Integration_test/VCST/src/param_gen.pl
new file mode 100644
index 0000000..1ad4763
--- /dev/null
+++ b/mpsoc/Integration_test/VCST/src/param_gen.pl
@@ -0,0 +1,46 @@
+#!/usr/bin/perl  
+package ProNOC;
+use strict;
+use warnings;
+use File::Basename;
+
+
+#add home dir in perl 5.6
+use FindBin;
+use lib $FindBin::Bin;
+use Cwd qw(realpath);
+
+
+
+
+use File::Path qw(make_path);
+
+
+use strict;
+use warnings;
+
+
+
+
+my $script_path = dirname(__FILE__);
+
+require "$script_path/../../synthetic_sim/src/src.pl";
+use lib "../synthetic_sim/src/perl_lib";
+
+use constant::boolean;
+use base 'Class::Accessor::Fast';
+
+my $conf_file=$ARGV[0];
+
+
+sub create_noc_param_vv {
+    my ($conf_file)=@_;
+    my $o = do $conf_file;
+    die "Could not parse $conf_file: $@" if $@;
+    die "Could not read $conf_file: $!" unless defined $o;
+    my $param = $o->{'noc_param'};
+    my ($param_v,$include_h,$tops)=   gen_noc_localparam_v( $o,$param);
+    save_file("$script_path/noc_localparam.v",$param_v);
+}
+
+create_noc_param_vv ($conf_file);
diff --git a/mpsoc/Integration_test/default_noc_param b/mpsoc/Integration_test/default_noc_param
new file mode 100644
index 0000000..b370372
--- /dev/null
+++ b/mpsoc/Integration_test/default_noc_param
@@ -0,0 +1,94 @@
+$model = bless({
+    'noc_param' => {
+        "NOC_ID" => "0",
+        "TOPOLOGY" => "\"MESH\"",
+        "T1" => "8",
+        "T2" => "8",
+        "T3" => "1",
+        "T4" => "1",
+        "V" => "2",
+        "B" => "4",
+        "LB" => "B",
+        "Fpay" => "32",
+        "ROUTE_NAME" => "\"DOR\"",
+        "ROUTE_MODE" => "\"LOOKAHEAD\"",
+        "PCK_TYPE" => "  \"MULTI_FLIT\"",  
+        "MIN_PCK_SIZE" => "2",
+        "BYTE_EN" => "0",
+        "SSA_EN" => "0",
+        "CONGESTION_INDEX" => "3",
+        "ESCAP_VC_MASK" => "2'b01",
+        "VC_REALLOCATION_TYPE" => "\"NONATOMIC\"",
+        "COMBINATION_TYPE" => "\"COMB_NONSPEC\"",
+        "MUX_TYPE" => "\"BINARY\"",
+        "C" => "0",
+        "CLASS_SETTING"=> "{V{1'b1}}",
+        "DEBUG_EN" => "1",
+        "ADD_PIPREG_AFTER_CROSSBAR" => "1'b0",
+        "FIRST_ARBITER_EXT_P_EN" => "1",
+        "SWA_ARBITER_TYPE" => "\"RRA\"",
+        "WEIGHTw" => "4",
+        "AVC_ATOMIC_EN" => "0",
+        "CLASS_SETTING" => "{V{1'b1}}",
+        "SMART_MAX" => "0",
+        "SELF_LOOP_EN" => "0",
+        "MAX_PCK_NUM " => " 1000000000",
+        "MAX_PCK_SIZ " => " 16383" ,
+        "MAX_SIM_CLKs" => "  1000000000",
+        "TIMSTMP_FIFO_NUM " => " 16",
+        "CVw"=> "(C==0)? V : C * V",
+        "CAST_TYPE" => "\"UNICAST\"",
+        "MCAST_ENDP_LIST" => "'b1111",
+        "HETERO_VC"=> "0",
+        "MAX_ROUTER"=>"1",
+        "MAX_PORT"=>"1",
+        "int VC_CONFIG_TABLE [MAX_ROUTER][MAX_PORT]"=>"'{'{0}}",
+    },
+    
+    'parameters_order' => {
+        'noc_param' => [
+            'NOC_ID',
+            'TOPOLOGY',
+            'T1',
+            'T2',
+            'T3',
+            'T4',
+            'V',
+            'B',
+            'LB',
+            'Fpay',
+            'ROUTE_NAME',
+            'ROUTE_MODE',
+            'PCK_TYPE',
+            'MIN_PCK_SIZE',
+            'BYTE_EN',
+            'SSA_EN',
+            'SMART_MAX',
+            'CONGESTION_INDEX',
+            'ESCAP_VC_MASK',
+            'VC_REALLOCATION_TYPE',
+            'COMBINATION_TYPE',
+            'MUX_TYPE',
+            'C',
+            'CLASS_SETTING',
+            'DEBUG_EN',
+            'ADD_PIPREG_AFTER_CROSSBAR',
+            'FIRST_ARBITER_EXT_P_EN',
+            'SWA_ARBITER_TYPE',
+            'WEIGHTw',
+            'SELF_LOOP_EN',
+            'AVC_ATOMIC_EN',
+            "MAX_PCK_NUM " ,
+            "MAX_PCK_SIZ ",
+            "MAX_SIM_CLKs",
+            "TIMSTMP_FIFO_NUM ", 
+            "CVw",
+            "CAST_TYPE",
+            "MCAST_ENDP_LIST",
+            "HETERO_VC",
+            "MAX_ROUTER",
+            "MAX_PORT",
+            "int VC_CONFIG_TABLE [MAX_ROUTER][MAX_PORT]",
+        ],
+    }
+},);
diff --git a/mpsoc/Integration_test/synthetic_sim/configurations/conv_route/Fattree_k3_L3_st b/mpsoc/Integration_test/synthetic_sim/configurations/conv_route/Fattree_k3_L3_st
new file mode 100644
index 0000000..069ecc8
--- /dev/null
+++ b/mpsoc/Integration_test/synthetic_sim/configurations/conv_route/Fattree_k3_L3_st
@@ -0,0 +1,10 @@
+$model = bless( {
+    'noc_param'=> {
+        "TOPOLOGY" => "\"FATTREE\"",
+        "T1" => "3",
+        "T2" => "3",
+        "B"  => "5",
+        "ROUTE_NAME" => "\"NCA_STRAIGHT_UP\"",
+        "ROUTE_MODE" => "\"CONVENTIONAL\"",
+    }
+}, 'ProNOC' );
diff --git a/mpsoc/Integration_test/synthetic_sim/configurations/conv_route/bintree_k3_L3_st b/mpsoc/Integration_test/synthetic_sim/configurations/conv_route/bintree_k3_L3_st
new file mode 100644
index 0000000..9b5a564
--- /dev/null
+++ b/mpsoc/Integration_test/synthetic_sim/configurations/conv_route/bintree_k3_L3_st
@@ -0,0 +1,10 @@
+$model = bless( {
+    'noc_param'=> {
+        "TOPOLOGY" => "\"TREE\"",
+        "T1" => "3",
+        "T2" => "3",
+        "B"  => "5",
+        "ROUTE_NAME" => "\"NCA\"",
+        "ROUTE_MODE" => "\"CONVENTIONAL\"",
+    }
+}, 'ProNOC' );
diff --git a/mpsoc/Integration_test/synthetic_sim/configurations/conv_route/custom1_topology b/mpsoc/Integration_test/synthetic_sim/configurations/conv_route/custom1_topology
new file mode 100644
index 0000000..b2d125b
--- /dev/null
+++ b/mpsoc/Integration_test/synthetic_sim/configurations/conv_route/custom1_topology
@@ -0,0 +1,11 @@
+$model = bless( {
+    'noc_param'=> {
+    "TOPOLOGY"=>"\"custom1\"",
+        "CUSTOM_TOPOLOGY_NAME"=>"\"custom1\"",
+        "T1" => "16",
+        "T2" => "16",
+        "T3" => "5",
+        "ROUTE_NAME" =>"\"custom\"",
+        "ROUTE_MODE" => "\"CONVENTIONAL\"",
+    }
+}, 'ProNOC' );
\ No newline at end of file
diff --git a/mpsoc/Integration_test/synthetic_sim/configurations/conv_route/fmesh_2x2_openpiton b/mpsoc/Integration_test/synthetic_sim/configurations/conv_route/fmesh_2x2_openpiton
new file mode 100644
index 0000000..adab76f
--- /dev/null
+++ b/mpsoc/Integration_test/synthetic_sim/configurations/conv_route/fmesh_2x2_openpiton
@@ -0,0 +1,15 @@
+$model = bless( {
+    'noc_param'=> {
+        "TOPOLOGY"=> "\"FMESH\"",
+        "T1" => "2",
+        "T2" => "2",
+        "V" => "1",
+        "ESCAP_VC_MASK" => "1'b1",
+        "B" => "4",
+        "LB" => "16",
+        "Fpay" => "64",
+        "SSA_EN" => "1",
+        "SELF_LOOP_EN" => "1",
+        "ROUTE_MODE" => "\"CONVENTIONAL\"",
+    }
+}, 'ProNOC' );
\ No newline at end of file
diff --git a/mpsoc/Integration_test/synthetic_sim/configurations/conv_route/fmesh_4x4_smart3 b/mpsoc/Integration_test/synthetic_sim/configurations/conv_route/fmesh_4x4_smart3
new file mode 100644
index 0000000..352b170
--- /dev/null
+++ b/mpsoc/Integration_test/synthetic_sim/configurations/conv_route/fmesh_4x4_smart3
@@ -0,0 +1,16 @@
+$model = bless( {
+    'noc_param'=> {
+        "SMART_MAX" => "3",
+        "TOPOLOGY"=> "\"FMESH\"",
+        "T1" => "4",
+        "T2" => "4",
+        "V" => "1",
+        "ESCAP_VC_MASK" => "1'b1",
+        "B" => "4",
+        "LB" => "16",
+        "Fpay" => "64",
+        "SSA_EN" => "0",
+        "SELF_LOOP_EN" => "1",
+        "ROUTE_MODE" => "\"CONVENTIONAL\"",
+    }
+}, 'ProNOC' );
\ No newline at end of file
diff --git a/mpsoc/Integration_test/synthetic_sim/configurations/conv_route/mesh_3x3_v2_ssa b/mpsoc/Integration_test/synthetic_sim/configurations/conv_route/mesh_3x3_v2_ssa
new file mode 100644
index 0000000..94d2a4f
--- /dev/null
+++ b/mpsoc/Integration_test/synthetic_sim/configurations/conv_route/mesh_3x3_v2_ssa
@@ -0,0 +1,13 @@
+$model = bless( {
+    'noc_param'=> {
+        "T1" => "3",
+        "T2" => "3",
+        "SELF_LOOP_EN" => "1",
+        "SSA_EN"=> "1",
+        "LB" => 16,
+        "DEBUG_EN" => "0",   
+        "MIN_PCK_SIZE"  => "1", 
+        "Fpay" => "64",
+        "ROUTE_MODE" => "\"CONVENTIONAL\"",
+    }
+}, 'ProNOC' );
diff --git a/mpsoc/Integration_test/synthetic_sim/configurations/conv_route/mesh_4x4_2cycle_mcast_f b/mpsoc/Integration_test/synthetic_sim/configurations/conv_route/mesh_4x4_2cycle_mcast_f
new file mode 100644
index 0000000..d1d279d
--- /dev/null
+++ b/mpsoc/Integration_test/synthetic_sim/configurations/conv_route/mesh_4x4_2cycle_mcast_f
@@ -0,0 +1,9 @@
+$model = bless( {
+    'noc_param'=> {
+        "T1" => "4",
+        "T2" => "4",
+        "CAST_TYPE" => "\"MULTICAST_FULL\"",
+        "Fpay" => "64",
+        "ROUTE_MODE" => "\"CONVENTIONAL\"",
+    }
+}, 'ProNOC' );
diff --git a/mpsoc/Integration_test/synthetic_sim/configurations/conv_route/mesh_4x4_selflp_mcast_f b/mpsoc/Integration_test/synthetic_sim/configurations/conv_route/mesh_4x4_selflp_mcast_f
new file mode 100644
index 0000000..a2367b7
--- /dev/null
+++ b/mpsoc/Integration_test/synthetic_sim/configurations/conv_route/mesh_4x4_selflp_mcast_f
@@ -0,0 +1,10 @@
+$model = bless( {
+    'noc_param'=> {
+        "T1" => "4",
+        "T2" => "4",
+        "CAST_TYPE" => "\"MULTICAST_FULL\"",
+        "Fpay" => "64",
+        "SELF_LOOP_EN" => "1",
+        "ROUTE_MODE" => "\"CONVENTIONAL\"",
+    }
+}, 'ProNOC' );
\ No newline at end of file
diff --git a/mpsoc/Integration_test/synthetic_sim/configurations/conv_route/mesh_4x4x2_bcast_f b/mpsoc/Integration_test/synthetic_sim/configurations/conv_route/mesh_4x4x2_bcast_f
new file mode 100644
index 0000000..23eb21a
--- /dev/null
+++ b/mpsoc/Integration_test/synthetic_sim/configurations/conv_route/mesh_4x4x2_bcast_f
@@ -0,0 +1,11 @@
+$model = bless( {
+    'noc_param'=> {
+        "T1" => "4",
+        "T2" => "4",
+        "T3" => "2",
+        "CAST_TYPE" => "\"BROADCAST_FULL\"",
+        "MCAST_ENDP_LIST" => "32'b1100110001111",
+        "Fpay" => "64",
+        "ROUTE_MODE" => "\"CONVENTIONAL\"",
+    }
+}, 'ProNOC' );
\ No newline at end of file
diff --git a/mpsoc/Integration_test/synthetic_sim/configurations/conv_route/mesh_8x8_2cycle_adaptive b/mpsoc/Integration_test/synthetic_sim/configurations/conv_route/mesh_8x8_2cycle_adaptive
new file mode 100644
index 0000000..ad4952e
--- /dev/null
+++ b/mpsoc/Integration_test/synthetic_sim/configurations/conv_route/mesh_8x8_2cycle_adaptive
@@ -0,0 +1,7 @@
+$model = bless( {
+    'noc_param'=> {
+        "ROUTE_NAME" => "\"FULL_ADPT\"",
+        "ESCAP_VC_MASK" => "2'b01",
+        "ROUTE_MODE" => "\"CONVENTIONAL\"",
+    }
+}, 'ProNOC' );
\ No newline at end of file
diff --git a/mpsoc/Integration_test/synthetic_sim/configurations/conv_route/mesh_8x8_sbp6_xy b/mpsoc/Integration_test/synthetic_sim/configurations/conv_route/mesh_8x8_sbp6_xy
new file mode 100644
index 0000000..1c97e29
--- /dev/null
+++ b/mpsoc/Integration_test/synthetic_sim/configurations/conv_route/mesh_8x8_sbp6_xy
@@ -0,0 +1,6 @@
+$model = bless( {
+    'noc_param'=> {
+        "SMART_MAX" => "6",
+        "ROUTE_MODE" => "\"CONVENTIONAL\"",
+    }
+}, 'ProNOC' );
\ No newline at end of file
diff --git a/mpsoc/Integration_test/synthetic_sim/configurations/conv_route/mesh_8x8_single_flit b/mpsoc/Integration_test/synthetic_sim/configurations/conv_route/mesh_8x8_single_flit
new file mode 100644
index 0000000..f0579e4
--- /dev/null
+++ b/mpsoc/Integration_test/synthetic_sim/configurations/conv_route/mesh_8x8_single_flit
@@ -0,0 +1,9 @@
+$model = bless( {
+    'noc_param'=> {
+        "B" => "5",
+        "LB" => "5",
+        "MIN_PCK_SIZE" => "1",
+        "PCK_TYPE" => "  \"SINGLE_FLIT\"",
+        "ROUTE_MODE" => "\"CONVENTIONAL\"",
+    }
+}, 'ProNOC' );
\ No newline at end of file
diff --git a/mpsoc/Integration_test/synthetic_sim/configurations/conv_route/ring_8x8_2cycle_xy b/mpsoc/Integration_test/synthetic_sim/configurations/conv_route/ring_8x8_2cycle_xy
new file mode 100644
index 0000000..ae75953
--- /dev/null
+++ b/mpsoc/Integration_test/synthetic_sim/configurations/conv_route/ring_8x8_2cycle_xy
@@ -0,0 +1,9 @@
+$model = bless( {
+    'compile' => "verilate_mesh.sh",
+        'noc_param'=> {
+        TOPOLOGY=>"\"RING\"",
+        "TOPOLOGY" => "\"TORUS\"",
+        "ROUTE_NAME" => "\"TRANC_DOR\"",
+        "ROUTE_MODE" => "\"CONVENTIONAL\"",
+    }
+}, 'ProNOC' );
diff --git a/mpsoc/Integration_test/synthetic_sim/configurations/conv_route/star_6 b/mpsoc/Integration_test/synthetic_sim/configurations/conv_route/star_6
new file mode 100644
index 0000000..ab0bc8a
--- /dev/null
+++ b/mpsoc/Integration_test/synthetic_sim/configurations/conv_route/star_6
@@ -0,0 +1,9 @@
+$model = bless( {
+    'noc_param'=> {
+        "TOPOLOGY" => "\"STAR\"",
+        "T1" => "6",
+        "T2" => "1",
+        "B"  => "5",
+        "ROUTE_MODE" => "\"CONVENTIONAL\"",
+    }
+}, 'ProNOC' );
\ No newline at end of file
diff --git a/mpsoc/Integration_test/synthetic_sim/configurations/conv_route/torus_8x8_2cycle_xy b/mpsoc/Integration_test/synthetic_sim/configurations/conv_route/torus_8x8_2cycle_xy
new file mode 100644
index 0000000..bb0e659
--- /dev/null
+++ b/mpsoc/Integration_test/synthetic_sim/configurations/conv_route/torus_8x8_2cycle_xy
@@ -0,0 +1,7 @@
+$model = bless( {
+    'noc_param'=> {
+        "TOPOLOGY" => "\"TORUS\"",
+        "ROUTE_NAME" => "\"TRANC_DOR\"",
+        "ROUTE_MODE" => "\"CONVENTIONAL\"",
+    }
+}, 'ProNOC' );
\ No newline at end of file
diff --git a/mpsoc/Integration_test/synthetic_sim/configurations/failed-model/mesh_4x4_openpiton_mcast_f b/mpsoc/Integration_test/synthetic_sim/configurations/failed-model/mesh_4x4_openpiton_mcast_f
index 49d5467..3b7ab6a 100644
--- a/mpsoc/Integration_test/synthetic_sim/configurations/failed-model/mesh_4x4_openpiton_mcast_f
+++ b/mpsoc/Integration_test/synthetic_sim/configurations/failed-model/mesh_4x4_openpiton_mcast_f
@@ -1,15 +1,14 @@
 $model = bless( {
-		'compile' => "verilate_mesh.sh",
-        'noc_param'=> {
-						"T1" => "4",
-						"T2" => "4",
-						"V" => "1",	
-						"ESCAP_VC_MASK" => "1'b1",
-						"B" => "4",
-						"LB" => "16",
-						"Fpay" => "64",					
-						"SSA_EN" => "\"YES\"",	
-						"SELF_LOOP_EN" => "\"YES\"",
-						"CAST_TYPE" => "\"MULTICAST_FULL\"",			
-						}
-}, 'ProNOC' );
+    'noc_param'=> {
+        "T1" => "4",
+        "T2" => "4",
+        "V" => "1",
+        "ESCAP_VC_MASK" => "1'b1",
+        "B" => "4",
+        "LB" => "16",
+        "Fpay" => "64",
+        "SSA_EN" => "1",
+        "SELF_LOOP_EN" => "1",
+        "CAST_TYPE" => "\"MULTICAST_FULL\"",
+    }
+}, 'ProNOC' );
\ No newline at end of file
diff --git a/mpsoc/Integration_test/synthetic_sim/configurations/general/Fattree_k3_L3_st b/mpsoc/Integration_test/synthetic_sim/configurations/general/Fattree_k3_L3_st
new file mode 100644
index 0000000..e8816f6
--- /dev/null
+++ b/mpsoc/Integration_test/synthetic_sim/configurations/general/Fattree_k3_L3_st
@@ -0,0 +1,9 @@
+$model = bless( {
+    'noc_param'=> {
+        "TOPOLOGY" => "\"FATTREE\"",
+        "T1" => "3",
+        "T2" => "3",
+        "B"  => "5",
+        "ROUTE_NAME" => "\"NCA_STRAIGHT_UP\"",
+    }
+}, 'ProNOC' );
diff --git a/mpsoc/Integration_test/synthetic_sim/configurations/general/bintree_k3_L3_st b/mpsoc/Integration_test/synthetic_sim/configurations/general/bintree_k3_L3_st
new file mode 100644
index 0000000..85fc4b5
--- /dev/null
+++ b/mpsoc/Integration_test/synthetic_sim/configurations/general/bintree_k3_L3_st
@@ -0,0 +1,9 @@
+$model = bless( {
+    'noc_param'=> {
+        "TOPOLOGY" => "\"TREE\"",
+        "T1" => "3",
+        "T2" => "3",
+        "B"  => "5",
+        "ROUTE_NAME" => "\"NCA\"",
+    }
+}, 'ProNOC' );
diff --git a/mpsoc/Integration_test/synthetic_sim/configurations/general/custom1_topology b/mpsoc/Integration_test/synthetic_sim/configurations/general/custom1_topology
new file mode 100644
index 0000000..8b17d0e
--- /dev/null
+++ b/mpsoc/Integration_test/synthetic_sim/configurations/general/custom1_topology
@@ -0,0 +1,10 @@
+$model = bless( {
+    'noc_param'=> {
+    "TOPOLOGY"=>"\"custom1\"",
+        "CUSTOM_TOPOLOGY_NAME"=>"\"custom1\"",
+        "T1" => "16",
+        "T2" => "16",
+        "T3" => "5",
+        "ROUTE_NAME" =>"\"custom\""
+    }
+}, 'ProNOC' );
\ No newline at end of file
diff --git a/mpsoc/Integration_test/synthetic_sim/configurations/general/fmesh_1x1_openpiton b/mpsoc/Integration_test/synthetic_sim/configurations/general/fmesh_1x1_openpiton
new file mode 100644
index 0000000..f80a7c7
--- /dev/null
+++ b/mpsoc/Integration_test/synthetic_sim/configurations/general/fmesh_1x1_openpiton
@@ -0,0 +1,15 @@
+$model = bless( {
+    'noc_param'=> {
+        "TOPOLOGY"=> "\"FMESH\"",
+        "T1" => "1",
+        "T2" => "1",
+        "V" => "1",
+        "ESCAP_VC_MASK" => "1'b1",
+        "B" => "4",
+        "LB" => "16",
+        "Fpay" => "64",
+        "SSA_EN" => "1",
+        "SELF_LOOP_EN" => "1",
+        "MIN_PCK_SIZE" => "1"
+    }
+}, 'ProNOC' );
\ No newline at end of file
diff --git a/mpsoc/Integration_test/synthetic_sim/configurations/general/fmesh_2x2_openpiton b/mpsoc/Integration_test/synthetic_sim/configurations/general/fmesh_2x2_openpiton
new file mode 100644
index 0000000..449f321
--- /dev/null
+++ b/mpsoc/Integration_test/synthetic_sim/configurations/general/fmesh_2x2_openpiton
@@ -0,0 +1,14 @@
+$model = bless( {
+    'noc_param'=> {
+        "TOPOLOGY"=> "\"FMESH\"",
+        "T1" => "2",
+        "T2" => "2",
+        "V" => "1",
+        "ESCAP_VC_MASK" => "1'b1",
+        "B" => "4",
+        "LB" => "16",
+        "Fpay" => "64",
+        "SSA_EN" => "1",
+        "SELF_LOOP_EN" => "1",
+    }
+}, 'ProNOC' );
\ No newline at end of file
diff --git a/mpsoc/Integration_test/synthetic_sim/configurations/general/fmesh_4x4_smart3 b/mpsoc/Integration_test/synthetic_sim/configurations/general/fmesh_4x4_smart3
new file mode 100644
index 0000000..ad8749e
--- /dev/null
+++ b/mpsoc/Integration_test/synthetic_sim/configurations/general/fmesh_4x4_smart3
@@ -0,0 +1,15 @@
+$model = bless( {
+    'noc_param'=> {
+        "SMART_MAX" => "3",
+        "TOPOLOGY"=> "\"FMESH\"",
+        "T1" => "4",
+        "T2" => "4",
+        "V" => "1",
+        "ESCAP_VC_MASK" => "1'b1",
+        "B" => "4",
+        "LB" => "16",
+        "Fpay" => "64",
+        "SSA_EN" => "0",
+        "SELF_LOOP_EN" => "1",
+    }
+}, 'ProNOC' );
\ No newline at end of file
diff --git a/mpsoc/Integration_test/synthetic_sim/configurations/general/fmesh_8x8_2cycle_xy b/mpsoc/Integration_test/synthetic_sim/configurations/general/fmesh_8x8_2cycle_xy
new file mode 100644
index 0000000..12a13c3
--- /dev/null
+++ b/mpsoc/Integration_test/synthetic_sim/configurations/general/fmesh_8x8_2cycle_xy
@@ -0,0 +1,6 @@
+$model = bless( {
+    'noc_param'=> {
+        "TOPOLOGY" => "\"FMESH\"",
+        "ROUTE_NAME" => "\"DOR\"",
+    }
+}, 'ProNOC' );
\ No newline at end of file
diff --git a/mpsoc/Integration_test/synthetic_sim/configurations/general/fmesh_8x8_openpiton b/mpsoc/Integration_test/synthetic_sim/configurations/general/fmesh_8x8_openpiton
new file mode 100644
index 0000000..37c19a2
--- /dev/null
+++ b/mpsoc/Integration_test/synthetic_sim/configurations/general/fmesh_8x8_openpiton
@@ -0,0 +1,14 @@
+$model = bless( {
+    'noc_param'=> {
+        "TOPOLOGY"=> "\"FMESH\"",
+        "T1" => "8",
+        "T2" => "8",
+        "V" => "1",
+        "ESCAP_VC_MASK" => "1'b1",
+        "B" => "4",
+        "LB" => "16",
+        "Fpay" => "64",
+        "SSA_EN" => "1",
+        "SELF_LOOP_EN" => "1",
+    }
+}, 'ProNOC' );
\ No newline at end of file
diff --git a/mpsoc/Integration_test/synthetic_sim/configurations/general/mesh_2x2_openpiton b/mpsoc/Integration_test/synthetic_sim/configurations/general/mesh_2x2_openpiton
new file mode 100644
index 0000000..4b61b2e
--- /dev/null
+++ b/mpsoc/Integration_test/synthetic_sim/configurations/general/mesh_2x2_openpiton
@@ -0,0 +1,13 @@
+$model = bless( {
+    'noc_param'=> {
+        "T1" => "2",
+        "T2" => "2",
+        "V" => "1",
+        "ESCAP_VC_MASK" => "1'b1",
+        "B" => "4",
+        "LB" => "16",
+        "Fpay" => "64",
+        "SSA_EN" => "1",
+        "SELF_LOOP_EN" => "1",
+    }
+}, 'ProNOC' );
\ No newline at end of file
diff --git a/mpsoc/Integration_test/synthetic_sim/configurations/general/mesh_3x3_v2_ssa b/mpsoc/Integration_test/synthetic_sim/configurations/general/mesh_3x3_v2_ssa
new file mode 100644
index 0000000..1383775
--- /dev/null
+++ b/mpsoc/Integration_test/synthetic_sim/configurations/general/mesh_3x3_v2_ssa
@@ -0,0 +1,12 @@
+$model = bless( {
+    'noc_param'=> {
+        "T1" => "3",
+        "T2" => "3",
+        "SELF_LOOP_EN" => "1",
+        "SSA_EN"=> "1",
+        "LB" => 16,
+        "DEBUG_EN" => "0",   
+        "MIN_PCK_SIZE"  => "1", 
+        "Fpay" => "64",   
+    }
+}, 'ProNOC' );
diff --git a/mpsoc/Integration_test/synthetic_sim/configurations/general/mesh_4x4_2cycle_mcast_f b/mpsoc/Integration_test/synthetic_sim/configurations/general/mesh_4x4_2cycle_mcast_f
new file mode 100644
index 0000000..975dea2
--- /dev/null
+++ b/mpsoc/Integration_test/synthetic_sim/configurations/general/mesh_4x4_2cycle_mcast_f
@@ -0,0 +1,8 @@
+$model = bless( {
+    'noc_param'=> {
+        "T1" => "4",
+        "T2" => "4",
+        "CAST_TYPE" => "\"MULTICAST_FULL\"",
+        "Fpay" => "64"
+    }
+}, 'ProNOC' );
diff --git a/mpsoc/Integration_test/synthetic_sim/configurations/general/mesh_4x4_v1_B15 b/mpsoc/Integration_test/synthetic_sim/configurations/general/mesh_4x4_v1_B15
new file mode 100644
index 0000000..a07a491
--- /dev/null
+++ b/mpsoc/Integration_test/synthetic_sim/configurations/general/mesh_4x4_v1_B15
@@ -0,0 +1,13 @@
+$model = bless( {
+    'noc_param'=> {
+        "T1" => "4",
+        "T2" => "4",
+        "V" => "1",
+        "ESCAP_VC_MASK" => "1'b1",
+        "B" => "15",
+        "LB" => "15",
+        "Fpay" => "64",
+        "SSA_EN" => "0",
+        "SELF_LOOP_EN" => "0",
+    }
+}, 'ProNOC' );
\ No newline at end of file
diff --git a/mpsoc/Integration_test/synthetic_sim/configurations/general/mesh_4x4x3_2cycle_xy b/mpsoc/Integration_test/synthetic_sim/configurations/general/mesh_4x4x3_2cycle_xy
new file mode 100644
index 0000000..ee47bc2
--- /dev/null
+++ b/mpsoc/Integration_test/synthetic_sim/configurations/general/mesh_4x4x3_2cycle_xy
@@ -0,0 +1,9 @@
+$model = bless( {
+    'noc_param'=> {
+        "T1" => "4",
+        "T2" => "4",
+        "T3" => "3",
+        "TOPOLOGY" => "\"MESH\"",
+        "ROUTE_NAME" => "\"DOR\"",
+    }
+}, 'ProNOC' );
\ No newline at end of file
diff --git a/mpsoc/Integration_test/synthetic_sim/configurations/general/mesh_8x8_2cycle_adaptive b/mpsoc/Integration_test/synthetic_sim/configurations/general/mesh_8x8_2cycle_adaptive
new file mode 100644
index 0000000..0aaa94e
--- /dev/null
+++ b/mpsoc/Integration_test/synthetic_sim/configurations/general/mesh_8x8_2cycle_adaptive
@@ -0,0 +1,6 @@
+$model = bless( {
+    'noc_param'=> {
+        "ROUTE_NAME" => "\"FULL_ADPT\"",
+        "ESCAP_VC_MASK" => "2'b01"
+    }
+}, 'ProNOC' );
\ No newline at end of file
diff --git a/mpsoc/Integration_test/synthetic_sim/configurations/general/mesh_8x8_2cycle_west_first b/mpsoc/Integration_test/synthetic_sim/configurations/general/mesh_8x8_2cycle_west_first
new file mode 100644
index 0000000..a794210
--- /dev/null
+++ b/mpsoc/Integration_test/synthetic_sim/configurations/general/mesh_8x8_2cycle_west_first
@@ -0,0 +1,5 @@
+$model = bless( {
+    'noc_param'=> {
+        "ROUTE_NAME" => "\"WEST_FIRST\"",
+    }
+}, 'ProNOC' );
\ No newline at end of file
diff --git a/mpsoc/Integration_test/synthetic_sim/configurations/general/mesh_8x8_2cycle_xy b/mpsoc/Integration_test/synthetic_sim/configurations/general/mesh_8x8_2cycle_xy
new file mode 100644
index 0000000..7107201
--- /dev/null
+++ b/mpsoc/Integration_test/synthetic_sim/configurations/general/mesh_8x8_2cycle_xy
@@ -0,0 +1,5 @@
+$model = bless( {
+    'noc_param'=> {
+        "ROUTE_NAME" => "\"DOR\"",
+    }
+}, 'ProNOC' );
\ No newline at end of file
diff --git a/mpsoc/Integration_test/synthetic_sim/configurations/general/mesh_8x8_4vc_4c b/mpsoc/Integration_test/synthetic_sim/configurations/general/mesh_8x8_4vc_4c
new file mode 100644
index 0000000..26296f7
--- /dev/null
+++ b/mpsoc/Integration_test/synthetic_sim/configurations/general/mesh_8x8_4vc_4c
@@ -0,0 +1,9 @@
+$model = bless( {
+    'noc_param'=> {
+        "ROUTE_NAME" => "\"DOR\"",
+        "V" => 4,
+        "C" => 4,
+        "CLASS_SETTING" => "16'b1000010000100001",
+        "ESCAP_VC_MASK" => "4'b1000"
+    }
+}, 'ProNOC' );
\ No newline at end of file
diff --git a/mpsoc/Integration_test/synthetic_sim/configurations/general/mesh_8x8_b2 b/mpsoc/Integration_test/synthetic_sim/configurations/general/mesh_8x8_b2
new file mode 100644
index 0000000..166ee7c
--- /dev/null
+++ b/mpsoc/Integration_test/synthetic_sim/configurations/general/mesh_8x8_b2
@@ -0,0 +1,7 @@
+$model = bless( {
+    'noc_param'=> {
+        "ROUTE_NAME" => "\"DOR\"",
+        "B"=> "2",
+        "LB"=> 2
+    }
+}, 'ProNOC' );
\ No newline at end of file
diff --git a/mpsoc/Integration_test/synthetic_sim/configurations/default/mesh_8x8_2cycle_xy b/mpsoc/Integration_test/synthetic_sim/configurations/general/mesh_8x8_sbp6_xy
similarity index 63%
rename from mpsoc/Integration_test/synthetic_sim/configurations/default/mesh_8x8_2cycle_xy
rename to mpsoc/Integration_test/synthetic_sim/configurations/general/mesh_8x8_sbp6_xy
index 4af7e61..8e2119a 100644
--- a/mpsoc/Integration_test/synthetic_sim/configurations/default/mesh_8x8_2cycle_xy
+++ b/mpsoc/Integration_test/synthetic_sim/configurations/general/mesh_8x8_sbp6_xy
@@ -1,5 +1,5 @@
 $model = bless( {
     'noc_param'=> {
-        "ROUTE_NAME" => "\"XY\"",
+        "SMART_MAX" => "6",
     }
 }, 'ProNOC' );
\ No newline at end of file
diff --git a/mpsoc/Integration_test/synthetic_sim/configurations/general/mesh_8x8_single_flit b/mpsoc/Integration_test/synthetic_sim/configurations/general/mesh_8x8_single_flit
new file mode 100644
index 0000000..fb793b8
--- /dev/null
+++ b/mpsoc/Integration_test/synthetic_sim/configurations/general/mesh_8x8_single_flit
@@ -0,0 +1,8 @@
+$model = bless( {
+    'noc_param'=> {
+        "B" => "5",
+        "LB" => "5",
+        "MIN_PCK_SIZE" => "1",
+        "PCK_TYPE" => "  \"SINGLE_FLIT\"",
+    }
+}, 'ProNOC' );
\ No newline at end of file
diff --git a/mpsoc/Integration_test/synthetic_sim/configurations/general/mesh_8x8_ssa_xy b/mpsoc/Integration_test/synthetic_sim/configurations/general/mesh_8x8_ssa_xy
new file mode 100644
index 0000000..02cf843
--- /dev/null
+++ b/mpsoc/Integration_test/synthetic_sim/configurations/general/mesh_8x8_ssa_xy
@@ -0,0 +1,5 @@
+$model = bless( {
+    'noc_param'=> {
+        "SSA_EN" => "1",
+    }
+}, 'ProNOC' );
\ No newline at end of file
diff --git a/mpsoc/Integration_test/synthetic_sim/configurations/general/star_6 b/mpsoc/Integration_test/synthetic_sim/configurations/general/star_6
new file mode 100644
index 0000000..06cc862
--- /dev/null
+++ b/mpsoc/Integration_test/synthetic_sim/configurations/general/star_6
@@ -0,0 +1,8 @@
+$model = bless( {
+    'noc_param'=> {
+        "TOPOLOGY" => "\"STAR\"",
+        "T1" => "6",
+        "T2" => "1",
+        "B"  => "5",
+    }
+}, 'ProNOC' );
\ No newline at end of file
diff --git a/mpsoc/Integration_test/synthetic_sim/configurations/general/torus_8x8_2cycle_xy b/mpsoc/Integration_test/synthetic_sim/configurations/general/torus_8x8_2cycle_xy
new file mode 100644
index 0000000..7d29733
--- /dev/null
+++ b/mpsoc/Integration_test/synthetic_sim/configurations/general/torus_8x8_2cycle_xy
@@ -0,0 +1,6 @@
+$model = bless( {
+    'noc_param'=> {
+        "TOPOLOGY" => "\"TORUS\"",
+        "ROUTE_NAME" => "\"TRANC_DOR\"",
+    }
+}, 'ProNOC' );
\ No newline at end of file
diff --git a/mpsoc/Integration_test/synthetic_sim/configurations/line-ring/Line_3x2_v2 b/mpsoc/Integration_test/synthetic_sim/configurations/line-ring/Line_3x2_v2
index af2aa51..07a06b4 100644
--- a/mpsoc/Integration_test/synthetic_sim/configurations/line-ring/Line_3x2_v2
+++ b/mpsoc/Integration_test/synthetic_sim/configurations/line-ring/Line_3x2_v2
@@ -8,6 +8,6 @@ $model = bless( {
         "B" => "4",
         "LB" => "4",
         "Fpay" => "32",
-        "ROUTE_NAME"=>"\"XY\""
+        "ROUTE_NAME"=>"\"DOR\""
     }
 }, 'ProNOC' );
\ No newline at end of file
diff --git a/mpsoc/Integration_test/synthetic_sim/configurations/line-ring/line2_openpiton b/mpsoc/Integration_test/synthetic_sim/configurations/line-ring/line2_openpiton
index 8be327c..a0c250a 100644
--- a/mpsoc/Integration_test/synthetic_sim/configurations/line-ring/line2_openpiton
+++ b/mpsoc/Integration_test/synthetic_sim/configurations/line-ring/line2_openpiton
@@ -7,8 +7,8 @@ $model = bless( {
         "B" => "4",
         "LB" => "16",
         "Fpay" => "64",
-        "SSA_EN" => "\"YES\"",
-        "SELF_LOOP_EN" => "\"YES\"",
+        "SSA_EN" => "1",
+        "SELF_LOOP_EN" => "1",
         "MCAST_ENDP_LIST" => "'b11",
     }
 }, 'ProNOC' );
\ No newline at end of file
diff --git a/mpsoc/Integration_test/synthetic_sim/configurations/line-ring/line4_smart3 b/mpsoc/Integration_test/synthetic_sim/configurations/line-ring/line4_smart3
index 9242ffb..548c123 100644
--- a/mpsoc/Integration_test/synthetic_sim/configurations/line-ring/line4_smart3
+++ b/mpsoc/Integration_test/synthetic_sim/configurations/line-ring/line4_smart3
@@ -9,8 +9,8 @@ $model = bless( {
         "B" => "4",
         "LB" => "16",
         "Fpay" => "64",
-        "SSA_EN" => "\"NO\"",
-        "SELF_LOOP_EN" => "\"YES\"",
+        "SSA_EN" => "0",
+        "SELF_LOOP_EN" => "1",
         "MCAST_ENDP_LIST" => "'b11",
     }
 }, 'ProNOC' );
\ No newline at end of file
diff --git a/mpsoc/Integration_test/synthetic_sim/configurations/line-ring/line_4_v1_B15 b/mpsoc/Integration_test/synthetic_sim/configurations/line-ring/line_4_v1_B15
index 0f205e5..5d00709 100644
--- a/mpsoc/Integration_test/synthetic_sim/configurations/line-ring/line_4_v1_B15
+++ b/mpsoc/Integration_test/synthetic_sim/configurations/line-ring/line_4_v1_B15
@@ -8,7 +8,7 @@ $model = bless( {
         "B" => "15",
         "LB" => "15",
         "Fpay" => "64",
-        "SSA_EN" => "\"NO\"",
-        "SELF_LOOP_EN" => "\"NO\"",
+        "SSA_EN" => "0",
+        "SELF_LOOP_EN" => "0",
     }
 }, 'ProNOC' );
\ No newline at end of file
diff --git a/mpsoc/Integration_test/synthetic_sim/configurations/line-ring/line_4x3_2cycle_xy b/mpsoc/Integration_test/synthetic_sim/configurations/line-ring/line_4x3_2cycle_xy
index 57133ba..15a1e84 100644
--- a/mpsoc/Integration_test/synthetic_sim/configurations/line-ring/line_4x3_2cycle_xy
+++ b/mpsoc/Integration_test/synthetic_sim/configurations/line-ring/line_4x3_2cycle_xy
@@ -4,6 +4,6 @@ $model = bless( {
         "T1" => "4",
         "T2" => "4",
         "T3" => "3",
-        "ROUTE_NAME" => "\"XY\"",
+        "ROUTE_NAME" => "\"DOR\"",
     }
 }, 'ProNOC' );
\ No newline at end of file
diff --git a/mpsoc/Integration_test/synthetic_sim/configurations/line-ring/line_8_2cycle_xy b/mpsoc/Integration_test/synthetic_sim/configurations/line-ring/line_8_2cycle_xy
index caa94b2..5a31cc4 100644
--- a/mpsoc/Integration_test/synthetic_sim/configurations/line-ring/line_8_2cycle_xy
+++ b/mpsoc/Integration_test/synthetic_sim/configurations/line-ring/line_8_2cycle_xy
@@ -1,6 +1,6 @@
 $model = bless( {
     'noc_param'=> {
         TOPOLOGY=>"\"LINE\"",
-        "ROUTE_NAME" => "\"XY\"",
+        "ROUTE_NAME" => "\"DOR\"",
     }
 }, 'ProNOC' );
\ No newline at end of file
diff --git a/mpsoc/Integration_test/synthetic_sim/configurations/line-ring/line_8_b2 b/mpsoc/Integration_test/synthetic_sim/configurations/line-ring/line_8_b2
index cdec6fb..8a39813 100644
--- a/mpsoc/Integration_test/synthetic_sim/configurations/line-ring/line_8_b2
+++ b/mpsoc/Integration_test/synthetic_sim/configurations/line-ring/line_8_b2
@@ -1,7 +1,7 @@
 $model = bless( {
     'noc_param'=> {
         TOPOLOGY=>"\"LINE\"",
-        "ROUTE_NAME" => "\"XY\"",
+        "ROUTE_NAME" => "\"DOR\"",
         "B"=> "2",
         "LB"=> 2
     }
diff --git a/mpsoc/Integration_test/synthetic_sim/configurations/failed-model/line_8_sbp6_xy b/mpsoc/Integration_test/synthetic_sim/configurations/line-ring/line_8_sbp6_xy
similarity index 100%
rename from mpsoc/Integration_test/synthetic_sim/configurations/failed-model/line_8_sbp6_xy
rename to mpsoc/Integration_test/synthetic_sim/configurations/line-ring/line_8_sbp6_xy
diff --git a/mpsoc/Integration_test/synthetic_sim/configurations/line-ring/line_8x8_ssa_xy b/mpsoc/Integration_test/synthetic_sim/configurations/line-ring/line_8x8_ssa_xy
index 436ec4b..5312f79 100644
--- a/mpsoc/Integration_test/synthetic_sim/configurations/line-ring/line_8x8_ssa_xy
+++ b/mpsoc/Integration_test/synthetic_sim/configurations/line-ring/line_8x8_ssa_xy
@@ -1,6 +1,6 @@
 $model = bless( {
     'noc_param'=> {
         TOPOLOGY=>"\"LINE\"",
-        "SSA_EN" => "\"YES\"",
+        "SSA_EN" => "1",
     }
 }, 'ProNOC' );
\ No newline at end of file
diff --git a/mpsoc/Integration_test/synthetic_sim/configurations/line-ring/linex8_4vc_4c b/mpsoc/Integration_test/synthetic_sim/configurations/line-ring/linex8_4vc_4c
index 5e7b123..e204644 100644
--- a/mpsoc/Integration_test/synthetic_sim/configurations/line-ring/linex8_4vc_4c
+++ b/mpsoc/Integration_test/synthetic_sim/configurations/line-ring/linex8_4vc_4c
@@ -1,7 +1,7 @@
 $model = bless( {
     'noc_param'=> {
         TOPOLOGY=>"\"LINE\"",
-        "ROUTE_NAME" => "\"XY\"",
+        "ROUTE_NAME" => "\"DOR\"",
         "V" => 4,
         "C" => 4,
         "CLASS_SETTING" => "16'b1000010000100001",
diff --git a/mpsoc/Integration_test/synthetic_sim/configurations/line-ring/ring_8x8_2cycle_xy b/mpsoc/Integration_test/synthetic_sim/configurations/line-ring/ring_8x8_2cycle_xy
index f75ef5b..d47e3d9 100644
--- a/mpsoc/Integration_test/synthetic_sim/configurations/line-ring/ring_8x8_2cycle_xy
+++ b/mpsoc/Integration_test/synthetic_sim/configurations/line-ring/ring_8x8_2cycle_xy
@@ -3,6 +3,6 @@ $model = bless( {
         'noc_param'=> {
         TOPOLOGY=>"\"RING\"",
         "TOPOLOGY" => "\"TORUS\"",
-        "ROUTE_NAME" => "\"TRANC_XY\"",
+        "ROUTE_NAME" => "\"TRANC_DOR\"",
     }
 }, 'ProNOC' );
diff --git a/mpsoc/Integration_test/synthetic_sim/configurations/mesh_3d/mesh_3d_2x2x2 b/mpsoc/Integration_test/synthetic_sim/configurations/mesh_3d/mesh_3d_2x2x2
new file mode 100644
index 0000000..b65c45c
--- /dev/null
+++ b/mpsoc/Integration_test/synthetic_sim/configurations/mesh_3d/mesh_3d_2x2x2
@@ -0,0 +1,10 @@
+$model = bless( {
+    'noc_param'=> {
+        "TOPOLOGY" => '"MESH_3D"',
+        "T1" => "2",
+        "T2" => "2",
+        "T3" => "2",
+        "T4" => "1",
+        "ROUTE_NAME" => '"DOR"',
+    }
+}, 'ProNOC' );
diff --git a/mpsoc/Integration_test/synthetic_sim/configurations/mesh_3d/mesh_3d_4x3x2x2 b/mpsoc/Integration_test/synthetic_sim/configurations/mesh_3d/mesh_3d_4x3x2x2
new file mode 100644
index 0000000..5893919
--- /dev/null
+++ b/mpsoc/Integration_test/synthetic_sim/configurations/mesh_3d/mesh_3d_4x3x2x2
@@ -0,0 +1,10 @@
+$model = bless( {
+    'noc_param'=> {
+        "TOPOLOGY" => '"MESH_3D"',
+        "T1" => "4",
+        "T2" => "3",
+        "T3" => "2",
+        "T4" => "2",
+        "ROUTE_NAME" => '"DOR"',
+    }
+}, 'ProNOC' );
diff --git a/mpsoc/Integration_test/synthetic_sim/configurations/mesh_3d/mesh_3d_4x3x2x2_smart b/mpsoc/Integration_test/synthetic_sim/configurations/mesh_3d/mesh_3d_4x3x2x2_smart
new file mode 100644
index 0000000..6c209c4
--- /dev/null
+++ b/mpsoc/Integration_test/synthetic_sim/configurations/mesh_3d/mesh_3d_4x3x2x2_smart
@@ -0,0 +1,12 @@
+$model = bless( {
+    'noc_param'=> {
+        "TOPOLOGY" => '"MESH_3D"',
+        "T1" => "4",
+        "T2" => "3",
+        "T3" => "2",
+        "T4" => "2",
+        "ROUTE_NAME" => '"DOR"',
+        "SSA_EN"=> "0",
+        "SMART_MAX" => "3",
+    }
+}, 'ProNOC' );
diff --git a/mpsoc/Integration_test/synthetic_sim/configurations/mesh_3d/mesh_3d_4x3x2x2_ssa b/mpsoc/Integration_test/synthetic_sim/configurations/mesh_3d/mesh_3d_4x3x2x2_ssa
new file mode 100644
index 0000000..29e38cc
--- /dev/null
+++ b/mpsoc/Integration_test/synthetic_sim/configurations/mesh_3d/mesh_3d_4x3x2x2_ssa
@@ -0,0 +1,11 @@
+$model = bless( {
+    'noc_param'=> {
+        "TOPOLOGY" => '"MESH_3D"',
+        "T1" => "4",
+        "T2" => "3",
+        "T3" => "2",
+        "T4" => "2",
+        "ROUTE_NAME" => '"DOR"',
+        "SSA_EN"=> "1",
+    }
+}, 'ProNOC' );
diff --git a/mpsoc/Integration_test/synthetic_sim/configurations/multicast/mesh_4x4_LB5_B4 b/mpsoc/Integration_test/synthetic_sim/configurations/multicast/mesh_4x4_LB5_B4
index d726f79..50ac90c 100644
--- a/mpsoc/Integration_test/synthetic_sim/configurations/multicast/mesh_4x4_LB5_B4
+++ b/mpsoc/Integration_test/synthetic_sim/configurations/multicast/mesh_4x4_LB5_B4
@@ -7,6 +7,6 @@ $model = bless( {
         "CAST_TYPE" => "\"MULTICAST_PARTIAL\"",
         "MCAST_ENDP_LIST" => "16'b110011000111101",
         "Fpay" => "64",
-        "SELF_LOOP_EN" => "\"YES\""
+        "SELF_LOOP_EN" => "1"
     }
 }, 'ProNOC' );
\ No newline at end of file
diff --git a/mpsoc/Integration_test/synthetic_sim/configurations/multicast/mesh_4x4_selflp_mcast_f b/mpsoc/Integration_test/synthetic_sim/configurations/multicast/mesh_4x4_selflp_mcast_f
index 1a9c662..5c5852e 100644
--- a/mpsoc/Integration_test/synthetic_sim/configurations/multicast/mesh_4x4_selflp_mcast_f
+++ b/mpsoc/Integration_test/synthetic_sim/configurations/multicast/mesh_4x4_selflp_mcast_f
@@ -4,6 +4,6 @@ $model = bless( {
         "T2" => "4",
         "CAST_TYPE" => "\"MULTICAST_FULL\"",
         "Fpay" => "64",
-        "SELF_LOOP_EN" => "\"YES\""
+        "SELF_LOOP_EN" => "1"
     }
 }, 'ProNOC' );
\ No newline at end of file
diff --git a/mpsoc/Integration_test/synthetic_sim/configurations/multicast/star6_2cycle_mcast_par b/mpsoc/Integration_test/synthetic_sim/configurations/multicast/star6_2cycle_mcast_par
index 815288d..3bf044e 100644
--- a/mpsoc/Integration_test/synthetic_sim/configurations/multicast/star6_2cycle_mcast_par
+++ b/mpsoc/Integration_test/synthetic_sim/configurations/multicast/star6_2cycle_mcast_par
@@ -6,6 +6,6 @@ $model = bless( {
         "CAST_TYPE" => "\"MULTICAST_PARTIAL\"",
         "Fpay" => "32",
         "MCAST_ENDP_LIST" => "'b001011",
-        "SELF_LOOP_EN" => "\"YES\""
+        "SELF_LOOP_EN" => "1"
     }
 }, 'ProNOC' );
\ No newline at end of file
diff --git a/mpsoc/Integration_test/synthetic_sim/configurations/tiny_topos/Fattree_k3_L2_st b/mpsoc/Integration_test/synthetic_sim/configurations/tiny_topos/Fattree_k3_L2_st
new file mode 100644
index 0000000..5a0726a
--- /dev/null
+++ b/mpsoc/Integration_test/synthetic_sim/configurations/tiny_topos/Fattree_k3_L2_st
@@ -0,0 +1,9 @@
+$model = bless( {
+    'noc_param'=> {
+        "TOPOLOGY" => "\"FATTREE\"",
+        "T1" => "3",
+        "T2" => "2",
+        "B"  => "6",
+        "ROUTE_NAME" => "\"NCA_STRAIGHT_UP\"",
+    }
+}, 'ProNOC' );
diff --git a/mpsoc/Integration_test/synthetic_sim/configurations/tiny_topos/Line_3x2_v2 b/mpsoc/Integration_test/synthetic_sim/configurations/tiny_topos/Line_3x2_v2
new file mode 100644
index 0000000..191a894
--- /dev/null
+++ b/mpsoc/Integration_test/synthetic_sim/configurations/tiny_topos/Line_3x2_v2
@@ -0,0 +1,13 @@
+$model = bless( {
+    'noc_param'=> {
+        "TOPOLOGY" => "\"LINE\"",
+        "T1" => "3",
+        "T2" => "1",
+        "T3" => "2",
+        "V" => "2",
+        "B" => "4",
+        "LB" => "4",
+        "Fpay" => "32",
+        "ROUTE_NAME"=>"\"DOR\""
+    }
+}, 'ProNOC' );
diff --git a/mpsoc/Integration_test/synthetic_sim/configurations/tiny_topos/fmesh_2x2_openpiton b/mpsoc/Integration_test/synthetic_sim/configurations/tiny_topos/fmesh_2x2_openpiton
new file mode 100644
index 0000000..449f321
--- /dev/null
+++ b/mpsoc/Integration_test/synthetic_sim/configurations/tiny_topos/fmesh_2x2_openpiton
@@ -0,0 +1,14 @@
+$model = bless( {
+    'noc_param'=> {
+        "TOPOLOGY"=> "\"FMESH\"",
+        "T1" => "2",
+        "T2" => "2",
+        "V" => "1",
+        "ESCAP_VC_MASK" => "1'b1",
+        "B" => "4",
+        "LB" => "16",
+        "Fpay" => "64",
+        "SSA_EN" => "1",
+        "SELF_LOOP_EN" => "1",
+    }
+}, 'ProNOC' );
\ No newline at end of file
diff --git a/mpsoc/Integration_test/synthetic_sim/configurations/tiny_topos/mesh_2x2_openpiton b/mpsoc/Integration_test/synthetic_sim/configurations/tiny_topos/mesh_2x2_openpiton
new file mode 100644
index 0000000..4b61b2e
--- /dev/null
+++ b/mpsoc/Integration_test/synthetic_sim/configurations/tiny_topos/mesh_2x2_openpiton
@@ -0,0 +1,13 @@
+$model = bless( {
+    'noc_param'=> {
+        "T1" => "2",
+        "T2" => "2",
+        "V" => "1",
+        "ESCAP_VC_MASK" => "1'b1",
+        "B" => "4",
+        "LB" => "16",
+        "Fpay" => "64",
+        "SSA_EN" => "1",
+        "SELF_LOOP_EN" => "1",
+    }
+}, 'ProNOC' );
\ No newline at end of file
diff --git a/mpsoc/Integration_test/synthetic_sim/configurations/tiny_topos/mesh_3d_2x2x2 b/mpsoc/Integration_test/synthetic_sim/configurations/tiny_topos/mesh_3d_2x2x2
new file mode 100644
index 0000000..b65c45c
--- /dev/null
+++ b/mpsoc/Integration_test/synthetic_sim/configurations/tiny_topos/mesh_3d_2x2x2
@@ -0,0 +1,10 @@
+$model = bless( {
+    'noc_param'=> {
+        "TOPOLOGY" => '"MESH_3D"',
+        "T1" => "2",
+        "T2" => "2",
+        "T3" => "2",
+        "T4" => "1",
+        "ROUTE_NAME" => '"DOR"',
+    }
+}, 'ProNOC' );
diff --git a/mpsoc/Integration_test/synthetic_sim/configurations/tiny_topos/ring_3_2 b/mpsoc/Integration_test/synthetic_sim/configurations/tiny_topos/ring_3_2
new file mode 100644
index 0000000..0238d96
--- /dev/null
+++ b/mpsoc/Integration_test/synthetic_sim/configurations/tiny_topos/ring_3_2
@@ -0,0 +1,10 @@
+$model = bless( {
+    'compile' => "verilate_mesh.sh",
+        'noc_param'=> {
+        "TOPOLOGY"=>"\"RING\"",
+        "ROUTE_NAME" => "\"TRANC_DOR\"",
+        "T1" => "3",
+        "T2" => "1",
+        "T3" => "2",
+    }
+}, 'ProNOC' );
diff --git a/mpsoc/Integration_test/synthetic_sim/configurations/tiny_topos/star_7 b/mpsoc/Integration_test/synthetic_sim/configurations/tiny_topos/star_7
new file mode 100644
index 0000000..2f38437
--- /dev/null
+++ b/mpsoc/Integration_test/synthetic_sim/configurations/tiny_topos/star_7
@@ -0,0 +1,8 @@
+$model = bless( {
+    'noc_param'=> {
+        "TOPOLOGY" => "\"STAR\"",
+        "T1" => "7",
+        "T2" => "1",
+        "B"  => "5",
+    }
+}, 'ProNOC' );
diff --git a/mpsoc/Integration_test/synthetic_sim/configurations/tiny_topos/torus_3x2_adaptive b/mpsoc/Integration_test/synthetic_sim/configurations/tiny_topos/torus_3x2_adaptive
new file mode 100644
index 0000000..5c9c6ec
--- /dev/null
+++ b/mpsoc/Integration_test/synthetic_sim/configurations/tiny_topos/torus_3x2_adaptive
@@ -0,0 +1,8 @@
+$model = bless( {
+    'noc_param'=> {
+        "TOPOLOGY" => "\"TORUS\"",
+        "ROUTE_NAME" => "\"TRANC_FULL_ADPT\"",
+         "T1" => "3",
+         "T2" => "2",
+    }
+}, 'ProNOC' );
diff --git a/mpsoc/Integration_test/synthetic_sim/configurations/tiny_topos/tree_k3_L2_st b/mpsoc/Integration_test/synthetic_sim/configurations/tiny_topos/tree_k3_L2_st
new file mode 100644
index 0000000..c535b87
--- /dev/null
+++ b/mpsoc/Integration_test/synthetic_sim/configurations/tiny_topos/tree_k3_L2_st
@@ -0,0 +1,9 @@
+$model = bless( {
+    'noc_param'=> {
+        "TOPOLOGY" => "\"TREE\"",
+        "T1" => "3",
+        "T2" => "2",
+        "B"  => "6",
+        "ROUTE_NAME" => "\"NCA_STRAIGHT_UP\"",
+    }
+}, 'ProNOC' );
diff --git a/mpsoc/Integration_test/synthetic_sim/configurations/vc_alloc/mesh_4x4x3_vc_nonspec b/mpsoc/Integration_test/synthetic_sim/configurations/vc_alloc/mesh_4x4x3_vc_nonspec
index 719d562..6bb1a40 100644
--- a/mpsoc/Integration_test/synthetic_sim/configurations/vc_alloc/mesh_4x4x3_vc_nonspec
+++ b/mpsoc/Integration_test/synthetic_sim/configurations/vc_alloc/mesh_4x4x3_vc_nonspec
@@ -4,7 +4,7 @@ $model = bless( {
 		"T2" => "4",	
 		"T3" => "3",							
 		"TOPOLOGY" => "\"MESH\"",						
-		"ROUTE_NAME" => "\"XY\"",
+		"ROUTE_NAME" => "\"DOR\"",
 		"COMBINATION_TYPE" => "\"COMB_NONSPEC\"",     					
 	}
 }, 'ProNOC' );
\ No newline at end of file
diff --git a/mpsoc/Integration_test/synthetic_sim/configurations/vc_alloc/mesh_4x4x3_vc_spec1 b/mpsoc/Integration_test/synthetic_sim/configurations/vc_alloc/mesh_4x4x3_vc_spec1
index 9d89499..1c5388c 100644
--- a/mpsoc/Integration_test/synthetic_sim/configurations/vc_alloc/mesh_4x4x3_vc_spec1
+++ b/mpsoc/Integration_test/synthetic_sim/configurations/vc_alloc/mesh_4x4x3_vc_spec1
@@ -4,7 +4,7 @@ $model = bless( {
 		"T2" => "4",	
 		"T3" => "3",							
 		"TOPOLOGY" => "\"MESH\"",						
-		"ROUTE_NAME" => "\"XY\"",
+		"ROUTE_NAME" => "\"DOR\"",
 		"COMBINATION_TYPE" => "\"COMB_SPEC1\"",  						  					
 	}
 }, 'ProNOC' );
\ No newline at end of file
diff --git a/mpsoc/Integration_test/synthetic_sim/configurations/vc_alloc/mesh_4x4x3_vc_spec2 b/mpsoc/Integration_test/synthetic_sim/configurations/vc_alloc/mesh_4x4x3_vc_spec2
index aea90d2..ed2a7f9 100644
--- a/mpsoc/Integration_test/synthetic_sim/configurations/vc_alloc/mesh_4x4x3_vc_spec2
+++ b/mpsoc/Integration_test/synthetic_sim/configurations/vc_alloc/mesh_4x4x3_vc_spec2
@@ -4,7 +4,7 @@ $model = bless( {
 		"T2" => "4",	
 		"T3" => "3",							
 		"TOPOLOGY" => "\"MESH\"",						
-		"ROUTE_NAME" => "\"XY\"",
+		"ROUTE_NAME" => "\"DOR\"",
 		"COMBINATION_TYPE" => "\"COMB_SPEC2\"",  						  					
 	}
 }, 'ProNOC' );
\ No newline at end of file
diff --git a/mpsoc/Integration_test/synthetic_sim/configurations/vc_alloc/mesh_8x8_4vc b/mpsoc/Integration_test/synthetic_sim/configurations/vc_alloc/mesh_8x8_4vc
new file mode 100644
index 0000000..1914e8b
--- /dev/null
+++ b/mpsoc/Integration_test/synthetic_sim/configurations/vc_alloc/mesh_8x8_4vc
@@ -0,0 +1,7 @@
+$model = bless( {
+    'noc_param'=> {
+        "ROUTE_NAME" => "\"DOR\"",
+        "ESCAP_VC_MASK" => "4'd1",
+        "V" => 4,
+    }
+}, 'ProNOC' );
diff --git a/mpsoc/Integration_test/synthetic_sim/configurations/vc_alloc/mesh_8x8_4vc_hetero1 b/mpsoc/Integration_test/synthetic_sim/configurations/vc_alloc/mesh_8x8_4vc_hetero1
new file mode 100644
index 0000000..89af385
--- /dev/null
+++ b/mpsoc/Integration_test/synthetic_sim/configurations/vc_alloc/mesh_8x8_4vc_hetero1
@@ -0,0 +1,77 @@
+$model = bless( {
+    'noc_param'=> {
+        "ROUTE_NAME" => "\"DOR\"",
+        "ESCAP_VC_MASK" => "4'd1",
+        "V" => 4,
+        "HETERO_VC"=> "1",
+        "MAX_ROUTER"=>"64",
+        "MAX_PORT"=>"1",
+        "int VC_CONFIG_TABLE [MAX_ROUTER][MAX_PORT]"=>"'{
+    //P0 P1 P2 P3 P4 
+    '{1}, // R0
+    '{2}, // R1
+    '{3}, // R2
+    '{4}, // R3
+    '{1}, // R4
+    '{2}, // R5
+    '{3}, // R6
+    '{4}, // R7
+    '{1}, // R8
+    '{2}, // R9
+    '{3}, // R10
+    '{4}, // R11
+    '{1}, // R12
+    '{2}, // R13
+    '{3}, // R14
+    '{1},  // R15
+    '{2}, // R16
+    '{3}, // R17
+    '{4}, // R18
+    '{1}, // R19
+    '{2}, // R20
+    '{3}, // R21
+    '{4}, // R22
+    '{1}, // R23
+    '{2}, // R24
+    '{3}, // R25
+    '{4}, // R26
+    '{1}, // R27
+    '{2}, // R28
+    '{3}, // R29
+    '{1}, // R30
+    '{2}, // R31
+    '{3}, // R32
+    '{4}, // R33
+    '{1}, // R34
+    '{2}, // R35
+    '{3}, // R36
+    '{4}, // R37
+    '{1}, // R38
+    '{2}, // R39
+    '{3}, // R40
+    '{4}, // R41
+    '{1}, // R42
+    '{2}, // R43
+    '{3}, // R44
+    '{1}, // R45
+    '{2}, // R46
+    '{3}, // R47
+    '{4}, // R48
+    '{1}, // R49
+    '{2}, // R50
+    '{3}, // R51
+    '{4}, // R52
+    '{1}, // R53
+    '{2}, // R54
+    '{3}, // R55
+    '{4}, // R56
+    '{1}, // R57
+    '{2}, // R58
+    '{3}, // R59
+    '{1}, // R60
+    '{2}, // R61
+    '{3}, // R62
+    '{4} // R63
+    }",
+    }
+}, 'ProNOC' );
diff --git a/mpsoc/Integration_test/synthetic_sim/configurations/vc_alloc/mesh_8x8_4vc_hetero2 b/mpsoc/Integration_test/synthetic_sim/configurations/vc_alloc/mesh_8x8_4vc_hetero2
new file mode 100644
index 0000000..bc13a6f
--- /dev/null
+++ b/mpsoc/Integration_test/synthetic_sim/configurations/vc_alloc/mesh_8x8_4vc_hetero2
@@ -0,0 +1,77 @@
+$model = bless( {
+    'noc_param'=> {
+        "ROUTE_NAME" => "\"DOR\"",
+        "V" => 4,
+        "ESCAP_VC_MASK" => "4'd1",
+        "HETERO_VC"=> "2",
+        "MAX_ROUTER"=>"64",
+        "MAX_PORT"=>"5",
+        "int VC_CONFIG_TABLE [MAX_ROUTER][MAX_PORT]"=>"'{
+	//P0 P1 P2 P3 P4 
+	'{1, 2, 3, 4, 1}, // R0
+	'{2, 3, 4, 1, 2}, // R1
+	'{3, 4, 1, 2, 3}, // R2
+	'{4, 1, 2, 3, 4}, // R3
+	'{1, 2, 3, 4, 1}, // R4
+	'{2, 3, 4, 1, 2}, // R5
+	'{3, 4, 1, 2, 3}, // R6
+	'{4, 1, 2, 3, 4}, // R7
+	'{1, 2, 3, 4, 1}, // R8
+	'{2, 3, 4, 1, 2}, // R9
+	'{3, 4, 1, 2, 3}, // R10
+	'{4, 1, 2, 3, 4}, // R11
+	'{1, 2, 3, 4, 1}, // R12
+	'{2, 3, 4, 1, 2}, // R13
+	'{3, 4, 1, 2, 3}, // R14
+	'{1, 2, 3, 4, 1},  // R15
+	'{2, 3, 4, 1, 2}, // R16
+	'{3, 4, 1, 2, 3}, // R17
+	'{4, 1, 2, 3, 4}, // R18
+	'{1, 2, 3, 4, 1}, // R19
+	'{2, 3, 4, 1, 2}, // R20
+	'{3, 4, 1, 2, 3}, // R21
+	'{4, 1, 2, 3, 4}, // R22
+	'{1, 2, 3, 4, 1}, // R23
+	'{2, 3, 4, 1, 2}, // R24
+	'{3, 4, 1, 2, 3}, // R25
+	'{4, 1, 2, 3, 4}, // R26
+	'{1, 2, 3, 4, 1}, // R27
+	'{2, 3, 4, 1, 2}, // R28
+	'{3, 4, 1, 2, 3}, // R29
+	'{1, 2, 3, 4, 1}, // R30
+	'{2, 3, 4, 1, 2}, // R31
+	'{3, 4, 1, 2, 3}, // R32
+	'{4, 1, 2, 3, 4}, // R33
+	'{1, 2, 3, 4, 1}, // R34
+	'{2, 3, 4, 1, 2}, // R35
+	'{3, 4, 1, 2, 3}, // R36
+	'{4, 1, 2, 3, 4}, // R37
+	'{1, 2, 3, 4, 1}, // R38
+	'{2, 3, 4, 1, 2}, // R39
+	'{3, 4, 1, 2, 3}, // R40
+	'{4, 1, 2, 3, 4}, // R41
+	'{1, 2, 3, 4, 1}, // R42
+	'{2, 3, 4, 1, 2}, // R43
+	'{3, 4, 1, 2, 3}, // R44
+	'{1, 2, 3, 4, 1}, // R45
+	'{2, 3, 4, 1, 2}, // R46
+	'{3, 4, 1, 2, 3}, // R47
+	'{4, 1, 2, 3, 4}, // R48
+	'{1, 2, 3, 4, 1}, // R49
+	'{2, 3, 4, 1, 2}, // R50
+	'{3, 4, 1, 2, 3}, // R51
+	'{4, 1, 2, 3, 4}, // R52
+	'{1, 2, 3, 4, 1}, // R53
+	'{2, 3, 4, 1, 2}, // R54
+	'{3, 4, 1, 2, 3}, // R55
+	'{4, 1, 2, 3, 4}, // R56
+	'{1, 2, 3, 4, 1}, // R57
+	'{2, 3, 4, 1, 2}, // R58
+	'{3, 4, 1, 2, 3}, // R59
+	'{1, 2, 3, 4, 1}, // R60
+	'{2, 3, 4, 1, 2}, // R61
+	'{3, 4, 1, 2, 3}, // R62
+	'{4, 1, 2, 3, 4}  // R63
+	}",
+    }
+}, 'ProNOC' );
diff --git a/mpsoc/Integration_test/synthetic_sim/reports/default_report_old b/mpsoc/Integration_test/synthetic_sim/golden_ref/conv_route
similarity index 50%
rename from mpsoc/Integration_test/synthetic_sim/reports/default_report_old
rename to mpsoc/Integration_test/synthetic_sim/golden_ref/conv_route
index 606a952..fe86e40 100644
--- a/mpsoc/Integration_test/synthetic_sim/reports/default_report_old
+++ b/mpsoc/Integration_test/synthetic_sim/golden_ref/conv_route
@@ -5,39 +5,25 @@ Verification Results:
 	 model is generated successfully.
 ****************************Fattree_k3_L3_st : Compile *******************************:
 	 model is generated successfully.
-****************************fmesh_1x1_openpiton : Compile *******************************:
-	 model is generated successfully.
 ****************************fmesh_2x2_openpiton : Compile *******************************:
 	 model is generated successfully.
-****************************fmesh_8x8_2cycle_xy : Compile *******************************:
-	 model is generated successfully.
-****************************fmesh_8x8_openpiton : Compile *******************************:
+****************************fmesh_4x4_smart3 : Compile *******************************:
 	 model is generated successfully.
-****************************mesh_2x2_openpiton : Compile *******************************:
+****************************mesh_3x3_v2_ssa : Compile *******************************:
 	 model is generated successfully.
 ****************************mesh_4x4_2cycle_mcast_f : Compile *******************************:
 	 model is generated successfully.
-****************************mesh_4x4_smart3 : Compile *******************************:
-	 model is generated successfully.
-****************************mesh_4x4_v1_B15 : Compile *******************************:
+****************************mesh_4x4_selflp_mcast_f : Compile *******************************:
 	 model is generated successfully.
-****************************mesh_4x4x3_2cycle_xy : Compile *******************************:
+****************************mesh_4x4x2_bcast_f : Compile *******************************:
 	 model is generated successfully.
 ****************************mesh_8x8_2cycle_adaptive : Compile *******************************:
 	 model is generated successfully.
-****************************mesh_8x8_2cycle_west_first : Compile *******************************:
-	 model is generated successfully.
-****************************mesh_8x8_2cycle_xy : Compile *******************************:
-	 model is generated successfully.
-****************************mesh_8x8_4vc_4c : Compile *******************************:
-	 model is generated successfully.
-****************************mesh_8x8_b2 : Compile *******************************:
-	 model is generated successfully.
 ****************************mesh_8x8_sbp6_xy : Compile *******************************:
 	 model is generated successfully.
 ****************************mesh_8x8_single_flit : Compile *******************************:
 	 model is generated successfully.
-****************************mesh_8x8_ssa_xy : Compile *******************************:
+****************************ring_8x8_2cycle_xy : Compile *******************************:
 	 model is generated successfully.
 ****************************star_6 : Compile *******************************:
 	 model is generated successfully.
@@ -49,40 +35,26 @@ Verification Results:
 	 Passed:   zero load (2,13.0626) saturation (42,65.4283)
 ****************************Fattree_k3_L3_st	: random traffic *******************************:
 	 Passed:   zero load (2,13.5991) saturation (62,98.8008)
-****************************fmesh_1x1_openpiton	: random traffic *******************************:
-	 Passed:   zero load (2,7.06202) saturation (66,51.0968)
 ****************************fmesh_2x2_openpiton	: random traffic *******************************:
 	 Passed:   zero load (2,8.27536) saturation (54,67.4686)
-****************************fmesh_8x8_2cycle_xy	: random traffic *******************************:
-	 Passed:   zero load (2,19.5638) saturation (18,137.798)
-****************************fmesh_8x8_openpiton	: random traffic *******************************:
-	 Passed:   zero load (2,14.4245) saturation (30,98.3569)
-****************************mesh_2x2_openpiton	: random traffic *******************************:
-	 Passed:   zero load (2,9.10156) saturation (66,72.3384)
+****************************fmesh_4x4_smart3	: random traffic *******************************:
+	 Passed:   zero load (2,10.1271) saturation (42,72.4117)
+****************************mesh_3x3_v2_ssa	: random traffic *******************************:
+	 Passed:   zero load (2,9.86859) saturation (70,77.4433)
 ****************************mesh_4x4_2cycle_mcast_f	: random traffic *******************************:
 	 Passed:   zero load (2,14.4623) saturation (22,261.684)
-****************************mesh_4x4_smart3	: random traffic *******************************:
-	 Passed:   zero load (2,10.1271) saturation (42,72.4117)
-****************************mesh_4x4_v1_B15	: random traffic *******************************:
-	 Passed:   zero load (6,12.719) saturation (58,93.2747)
-****************************mesh_4x4x3_2cycle_xy	: random traffic *******************************:
-	 Passed:   zero load (2,12.7475) saturation (26,188.161)
+****************************mesh_4x4_selflp_mcast_f	: random traffic *******************************:
+	 Passed:   zero load (2,14.366) saturation (22,257.065)
+****************************mesh_4x4x2_bcast_f	: random traffic *******************************:
+	 Passed:   zero load (2,20.5192) saturation (6,1071.58)
 ****************************mesh_8x8_2cycle_adaptive	: random traffic *******************************:
 	 Passed:   zero load (2,18.2154) saturation (34,186.128)
-****************************mesh_8x8_2cycle_west_first	: random traffic *******************************:
-	 Passed:   zero load (2,18.2239) saturation (34,154.392)
-****************************mesh_8x8_2cycle_xy	: random traffic *******************************:
-	 Passed:   zero load (2,18.2211) saturation (34,132.962)
-****************************mesh_8x8_4vc_4c	: random traffic *******************************:
-	 Passed:   zero load (2,18.0557) saturation (26,162.893)
-****************************mesh_8x8_b2	: random traffic *******************************:
-	 Passed:   zero load (2,22.1073) saturation (30,198.439)
 ****************************mesh_8x8_sbp6_xy	: random traffic *******************************:
 	 Passed:   zero load (2,11.1597) saturation (34,119.674)
 ****************************mesh_8x8_single_flit	: random traffic *******************************:
 	 Passed:   zero load (2,12.7369) saturation (58,65.8427)
-****************************mesh_8x8_ssa_xy	: random traffic *******************************:
-	 Passed:   zero load (2,14.769) saturation (34,111.6)
+****************************ring_8x8_2cycle_xy	: random traffic *******************************:
+	 Passed:   zero load (2,16.8517) saturation (38,120.208)
 ****************************star_6	: random traffic *******************************:
 	 Passed:   zero load (2,7.27692) saturation (62,57.3078)
 ****************************torus_8x8_2cycle_xy	: random traffic *******************************:
@@ -93,40 +65,26 @@ Verification Results:
 	 Passed:   zero load (2,12.6827) saturation (34,68.3986)
 ****************************Fattree_k3_L3_st	: transposed 1 traffic *******************************:
 	 Passed:   zero load (26,13.4638) saturation (100,-)
-****************************fmesh_1x1_openpiton	: transposed 1 traffic *******************************:
-	 Passed:   zero load (46,6.99433) saturation (100,-)
 ****************************fmesh_2x2_openpiton	: transposed 1 traffic *******************************:
-	 Passed:   zero load (2,8.99642) saturation (54,71.4902)
-****************************fmesh_8x8_2cycle_xy	: transposed 1 traffic *******************************:
-	 Passed:   zero load (2,21.6193) saturation (14,142.818)
-****************************fmesh_8x8_openpiton	: transposed 1 traffic *******************************:
-	 Passed:   zero load (2,15.916) saturation (26,118.048)
-****************************mesh_2x2_openpiton	: transposed 1 traffic *******************************:
-	 Passed:   zero load (2,8.7482) saturation (100,-)
+	 Passed:   zero load (2,8.44803) saturation (54,70.7567)
+****************************fmesh_4x4_smart3	: transposed 1 traffic *******************************:
+	 Passed:   zero load (2,9.95941) saturation (26,73.9415)
+****************************mesh_3x3_v2_ssa	: transposed 1 traffic *******************************:
+	 Passed:   zero load (6,9.72718) saturation (54,69.363)
 ****************************mesh_4x4_2cycle_mcast_f	: transposed 1 traffic *******************************:
 	 Passed:   zero load (2,14.8953) saturation (26,146.747)
-****************************mesh_4x4_smart3	: transposed 1 traffic *******************************:
-	 Passed:   zero load (2,10.5055) saturation (34,60.2796)
-****************************mesh_4x4_v1_B15	: transposed 1 traffic *******************************:
-	 Passed:   zero load (2,13.6902) saturation (38,106.686)
-****************************mesh_4x4x3_2cycle_xy	: transposed 1 traffic *******************************:
-	 Passed:   zero load (2,13.0755) saturation (14,126.234)
+****************************mesh_4x4_selflp_mcast_f	: transposed 1 traffic *******************************:
+	 Passed:   zero load (2,14.6488) saturation (22,166.723)
+****************************mesh_4x4x2_bcast_f	: transposed 1 traffic *******************************:
+	 Passed:   zero load (2,21.0549) saturation (6,863.495)
 ****************************mesh_8x8_2cycle_adaptive	: transposed 1 traffic *******************************:
 	 Passed:   zero load (2,19.3604) saturation (26,108.443)
-****************************mesh_8x8_2cycle_west_first	: transposed 1 traffic *******************************:
-	 Passed:   zero load (2,19.3588) saturation (22,102.056)
-****************************mesh_8x8_2cycle_xy	: transposed 1 traffic *******************************:
-	 Passed:   zero load (2,19.3582) saturation (18,124.569)
-****************************mesh_8x8_4vc_4c	: transposed 1 traffic *******************************:
-	 Passed:   zero load (2,19.2371) saturation (18,114.964)
-****************************mesh_8x8_b2	: transposed 1 traffic *******************************:
-	 Passed:   zero load (2,23.5649) saturation (18,118.423)
 ****************************mesh_8x8_sbp6_xy	: transposed 1 traffic *******************************:
 	 Passed:   zero load (2,11.3748) saturation (18,119.786)
 ****************************mesh_8x8_single_flit	: transposed 1 traffic *******************************:
 	 Passed:   zero load (2,14.0386) saturation (26,70.9042)
-****************************mesh_8x8_ssa_xy	: transposed 1 traffic *******************************:
-	 Passed:   zero load (2,15.3919) saturation (18,123.223)
+****************************ring_8x8_2cycle_xy	: transposed 1 traffic *******************************:
+	 Passed:   zero load (2,18.0133) saturation (18,134.597)
 ****************************star_6	: transposed 1 traffic *******************************:
 	 Passed:   zero load (2,6.83981) saturation (100,-)
 ****************************torus_8x8_2cycle_xy	: transposed 1 traffic *******************************:
diff --git a/mpsoc/Integration_test/synthetic_sim/reports/failed-model_report_old b/mpsoc/Integration_test/synthetic_sim/golden_ref/failed-model
similarity index 69%
rename from mpsoc/Integration_test/synthetic_sim/reports/failed-model_report_old
rename to mpsoc/Integration_test/synthetic_sim/golden_ref/failed-model
index 27e2a1b..c1744a2 100644
--- a/mpsoc/Integration_test/synthetic_sim/reports/failed-model_report_old
+++ b/mpsoc/Integration_test/synthetic_sim/golden_ref/failed-model
@@ -13,27 +13,26 @@ Verification Results:
 
 	 %Warning-WIDTH: /gpfs/home//pronoc_verify/mpsoc/Integration_test/synthetic_sim/../../mpsoc_work/verify/rtl/src_noc/multicast.sv:399:43: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS's VARREF 'dest_e_addr' generates 4 bits.
 
-****************************line_8_sbp6_xy : Compile *******************************:
-	 model is generated successfully.
 ****************************mesh_4x4_openpiton_mcast_f : Compile *******************************:
 	 model is generated successfully.
 ****************************line2_2cycle_mcast_f	: random traffic *******************************:
-	 Error in running simulation: ERROR: Multicast/Broadcast is not yet supported for LINE Topology
+	 Error in running simulation:
  ERROR: Multicast/Broadcast is not yet supported for LINE Topology
  
-****************************line_8_sbp6_xy	: random traffic *******************************:
-	 Error in running simulation:                 8000: ERROR: The destination port is not set for an active IVC request: d[R	
+ ERROR: Multicast/Broadcast is not yet supported for LINE Topology
  
 ****************************mesh_4x4_openpiton_mcast_f	: random traffic *******************************:
-	 Error in running simulation: ERROR: SMART or SAA do not support muticast/braodcast packets
+	 Error in running simulation:
+ ERROR: SMART or SAA do not support muticast/braodcast packets
  ERROR: SMART or SAA do not support muticast/braodcast packets
  
 ****************************line2_2cycle_mcast_f	: transposed 1 traffic *******************************:
-	 Error in running simulation: ERROR: Multicast/Broadcast is not yet supported for LINE Topology
+	 Error in running simulation:
+ ERROR: Multicast/Broadcast is not yet supported for LINE Topology
  ERROR: Multicast/Broadcast is not yet supported for LINE Topology
  
-****************************line_8_sbp6_xy	: transposed 1 traffic *******************************:
 ****************************mesh_4x4_openpiton_mcast_f	: transposed 1 traffic *******************************:
-	 Error in running simulation: ERROR: SMART or SAA do not support muticast/braodcast packets
+	 Error in running simulation:
  ERROR: SMART or SAA do not support muticast/braodcast packets
-
+ ERROR: SMART or SAA do not support muticast/braodcast packets
+ 
diff --git a/mpsoc/Integration_test/synthetic_sim/reports/default_report b/mpsoc/Integration_test/synthetic_sim/golden_ref/general
similarity index 90%
rename from mpsoc/Integration_test/synthetic_sim/reports/default_report
rename to mpsoc/Integration_test/synthetic_sim/golden_ref/general
index 606a952..e67bf42 100644
--- a/mpsoc/Integration_test/synthetic_sim/reports/default_report
+++ b/mpsoc/Integration_test/synthetic_sim/golden_ref/general
@@ -9,15 +9,17 @@ Verification Results:
 	 model is generated successfully.
 ****************************fmesh_2x2_openpiton : Compile *******************************:
 	 model is generated successfully.
+****************************fmesh_4x4_smart3 : Compile *******************************:
+	 model is generated successfully.
 ****************************fmesh_8x8_2cycle_xy : Compile *******************************:
 	 model is generated successfully.
 ****************************fmesh_8x8_openpiton : Compile *******************************:
 	 model is generated successfully.
 ****************************mesh_2x2_openpiton : Compile *******************************:
 	 model is generated successfully.
-****************************mesh_4x4_2cycle_mcast_f : Compile *******************************:
+****************************mesh_3x3_v2_ssa : Compile *******************************:
 	 model is generated successfully.
-****************************mesh_4x4_smart3 : Compile *******************************:
+****************************mesh_4x4_2cycle_mcast_f : Compile *******************************:
 	 model is generated successfully.
 ****************************mesh_4x4_v1_B15 : Compile *******************************:
 	 model is generated successfully.
@@ -50,19 +52,21 @@ Verification Results:
 ****************************Fattree_k3_L3_st	: random traffic *******************************:
 	 Passed:   zero load (2,13.5991) saturation (62,98.8008)
 ****************************fmesh_1x1_openpiton	: random traffic *******************************:
-	 Passed:   zero load (2,7.06202) saturation (66,51.0968)
+	 Passed:   zero load (2,6.28966) saturation (66,50.4578)
 ****************************fmesh_2x2_openpiton	: random traffic *******************************:
 	 Passed:   zero load (2,8.27536) saturation (54,67.4686)
+****************************fmesh_4x4_smart3	: random traffic *******************************:
+	 Passed:   zero load (2,10.1271) saturation (42,72.4117)
 ****************************fmesh_8x8_2cycle_xy	: random traffic *******************************:
 	 Passed:   zero load (2,19.5638) saturation (18,137.798)
 ****************************fmesh_8x8_openpiton	: random traffic *******************************:
 	 Passed:   zero load (2,14.4245) saturation (30,98.3569)
 ****************************mesh_2x2_openpiton	: random traffic *******************************:
 	 Passed:   zero load (2,9.10156) saturation (66,72.3384)
+****************************mesh_3x3_v2_ssa	: random traffic *******************************:
+	 Passed:   zero load (2,9.86859) saturation (70,77.4433)
 ****************************mesh_4x4_2cycle_mcast_f	: random traffic *******************************:
 	 Passed:   zero load (2,14.4623) saturation (22,261.684)
-****************************mesh_4x4_smart3	: random traffic *******************************:
-	 Passed:   zero load (2,10.1271) saturation (42,72.4117)
 ****************************mesh_4x4_v1_B15	: random traffic *******************************:
 	 Passed:   zero load (6,12.719) saturation (58,93.2747)
 ****************************mesh_4x4x3_2cycle_xy	: random traffic *******************************:
@@ -94,19 +98,21 @@ Verification Results:
 ****************************Fattree_k3_L3_st	: transposed 1 traffic *******************************:
 	 Passed:   zero load (26,13.4638) saturation (100,-)
 ****************************fmesh_1x1_openpiton	: transposed 1 traffic *******************************:
-	 Passed:   zero load (46,6.99433) saturation (100,-)
+	 Passed:   zero load (50,6.03057) saturation (100,-)
 ****************************fmesh_2x2_openpiton	: transposed 1 traffic *******************************:
-	 Passed:   zero load (2,8.99642) saturation (54,71.4902)
+	 Passed:   zero load (2,8.44803) saturation (54,70.7567)
+****************************fmesh_4x4_smart3	: transposed 1 traffic *******************************:
+	 Passed:   zero load (2,9.95941) saturation (26,73.9415)
 ****************************fmesh_8x8_2cycle_xy	: transposed 1 traffic *******************************:
-	 Passed:   zero load (2,21.6193) saturation (14,142.818)
+	 Passed:   zero load (2,21.0207) saturation (10,197.415)
 ****************************fmesh_8x8_openpiton	: transposed 1 traffic *******************************:
-	 Passed:   zero load (2,15.916) saturation (26,118.048)
+	 Passed:   zero load (2,15.1688) saturation (14,111.335)
 ****************************mesh_2x2_openpiton	: transposed 1 traffic *******************************:
 	 Passed:   zero load (2,8.7482) saturation (100,-)
+****************************mesh_3x3_v2_ssa	: transposed 1 traffic *******************************:
+	 Passed:   zero load (6,9.72718) saturation (54,69.363)
 ****************************mesh_4x4_2cycle_mcast_f	: transposed 1 traffic *******************************:
 	 Passed:   zero load (2,14.8953) saturation (26,146.747)
-****************************mesh_4x4_smart3	: transposed 1 traffic *******************************:
-	 Passed:   zero load (2,10.5055) saturation (34,60.2796)
 ****************************mesh_4x4_v1_B15	: transposed 1 traffic *******************************:
 	 Passed:   zero load (2,13.6902) saturation (38,106.686)
 ****************************mesh_4x4x3_2cycle_xy	: transposed 1 traffic *******************************:
diff --git a/mpsoc/Integration_test/synthetic_sim/reports/line-ring_report_old b/mpsoc/Integration_test/synthetic_sim/golden_ref/line-ring
similarity index 97%
rename from mpsoc/Integration_test/synthetic_sim/reports/line-ring_report_old
rename to mpsoc/Integration_test/synthetic_sim/golden_ref/line-ring
index 2196a90..933539f 100644
--- a/mpsoc/Integration_test/synthetic_sim/reports/line-ring_report_old
+++ b/mpsoc/Integration_test/synthetic_sim/golden_ref/line-ring
@@ -38,6 +38,7 @@ Verification Results:
 ****************************line_8_b2	: random traffic *******************************:
 	 Passed:   zero load (6,17.8996) saturation (34,105.723)
 ****************************line_8_sbp6_xy	: random traffic *******************************:
+	 Passed:   zero load (2,9.51163) saturation (38,99.1912)
 ****************************line_8_single_flit	: random traffic *******************************:
 	 Passed:   zero load (6,7.98062) saturation (38,41.7814)
 ****************************line_8x8_ssa_xy	: random traffic *******************************:
@@ -61,6 +62,7 @@ Verification Results:
 ****************************line_8_b2	: transposed 1 traffic *******************************:
 	 Passed:   zero load (2,19.2832) saturation (26,144.49)
 ****************************line_8_sbp6_xy	: transposed 1 traffic *******************************:
+	 Passed:   zero load (2,8.93525) saturation (26,114.013)
 ****************************line_8_single_flit	: transposed 1 traffic *******************************:
 	 Passed:   zero load (2,9.99617) saturation (26,65.1642)
 ****************************line_8x8_ssa_xy	: transposed 1 traffic *******************************:
diff --git a/mpsoc/Integration_test/synthetic_sim/golden_ref/mesh_3d b/mpsoc/Integration_test/synthetic_sim/golden_ref/mesh_3d
new file mode 100644
index 0000000..bc7f3bc
--- /dev/null
+++ b/mpsoc/Integration_test/synthetic_sim/golden_ref/mesh_3d
@@ -0,0 +1,22 @@
+
+Verification Results:
+****************************mesh_3d_2x2x2 : Compile *******************************:
+	 model is generated successfully.
+****************************mesh_3d_4x3x2x2 : Compile *******************************:
+	 model is generated successfully.
+****************************mesh_3d_4x3x2x2_smart : Compile *******************************:
+	 model is generated successfully.
+****************************mesh_3d_4x3x2x2_ssa : Compile *******************************:
+	 model is generated successfully.
+****************************mesh_3d_2x2x2	: random traffic *******************************:
+	 Passed:   zero load (6,10.8633) saturation (70,74.3971)
+****************************mesh_3d_4x3x2x2	: random traffic *******************************:
+	 Passed:   zero load (2,12.8413) saturation (38,75.3519)
+****************************mesh_3d_4x3x2x2_smart	: random traffic *******************************:
+	 Passed:   zero load (2,11.3919) saturation (38,73.7525)
+****************************mesh_3d_4x3x2x2_ssa	: random traffic *******************************:
+	 Passed:   zero load (2,12.1337) saturation (38,85.3049)
+****************************mesh_3d_2x2x2	: transposed 1 traffic *******************************:
+	 Passed:   zero load (2,9.82014) saturation (54,53.6323)
+****************************mesh_3d_4x3x2x2	: transposed 1 traffic *******************************:
+	 Passed:   zero load (2,12.6931) saturation (14,165.269)
diff --git a/mpsoc/Integration_test/synthetic_sim/reports/multicast_report b/mpsoc/Integration_test/synthetic_sim/golden_ref/multicast
similarity index 100%
rename from mpsoc/Integration_test/synthetic_sim/reports/multicast_report
rename to mpsoc/Integration_test/synthetic_sim/golden_ref/multicast
diff --git a/mpsoc/Integration_test/synthetic_sim/golden_ref/tiny_topos b/mpsoc/Integration_test/synthetic_sim/golden_ref/tiny_topos
new file mode 100644
index 0000000..062e4a2
--- /dev/null
+++ b/mpsoc/Integration_test/synthetic_sim/golden_ref/tiny_topos
@@ -0,0 +1,54 @@
+Verification Results:
+****************************Fattree_k3_L2_st : Compile *******************************:
+	 model is generated successfully.
+****************************fmesh_2x2_openpiton : Compile *******************************:
+	 model is generated successfully.
+****************************Line_3x2_v2 : Compile *******************************:
+	 model is generated successfully.
+****************************mesh_2x2_openpiton : Compile *******************************:
+	 model is generated successfully.
+
+****************************ring_3_2 : Compile *******************************:
+	 model is generated successfully.
+****************************star_7 : Compile *******************************:
+	 model is generated successfully.
+****************************torus_3x2_adaptive : Compile *******************************:
+	 model is generated successfully.
+****************************tree_k3_L2_st : Compile *******************************:
+	 model is generated successfully.
+****************************Fattree_k3_L2_st	: random traffic *******************************:
+	 Passed:   zero load (2,10.2953) saturation (70,87.4965)
+ 
+****************************fmesh_2x2_openpiton	: random traffic *******************************:
+	 Passed:   zero load (2,8.27536) saturation (54,67.4686)
+****************************Line_3x2_v2	: random traffic *******************************:
+	 Passed:   zero load (2,9.42564) saturation (50,78.1865)
+****************************mesh_2x2_openpiton	: random traffic *******************************:
+	 Passed:   zero load (2,9.10156) saturation (66,72.3384)
+
+****************************ring_3_2	: random traffic *******************************:
+	 Passed:   zero load (2,8.95385) saturation (62,50.9591)
+****************************star_7	: random traffic *******************************:
+	 Passed:   zero load (2,7.12609) saturation (62,63.5408)
+****************************torus_3x2_adaptive	: random traffic *******************************:
+	 Passed:   zero load (2,9.92821) saturation (70,66.6712)
+****************************tree_k3_L2_st	: random traffic *******************************:
+	 Passed:   zero load (2,10.5671) saturation (34,57.0081)
+ 
+****************************Fattree_k3_L2_st	: transposed 1 traffic *******************************:
+	 Passed:   zero load (26,9.97316) saturation (100,-)
+****************************fmesh_2x2_openpiton	: transposed 1 traffic *******************************:
+	 Passed:   zero load (2,8.99642) saturation (54,71.4902)
+****************************Line_3x2_v2	: transposed 1 traffic *******************************:
+	 Passed:   zero load (2,9.73786) saturation (54,94.5769)
+****************************mesh_2x2_openpiton	: transposed 1 traffic *******************************:
+	 Passed:   zero load (2,8.7482) saturation (100,-)
+ 
+****************************ring_3_2	: transposed 1 traffic *******************************:
+	 Passed:   zero load (6,8.3898) saturation (54,93.2034)
+****************************star_7	: transposed 1 traffic *******************************:
+	 Passed:   zero load (34,6.98688) saturation (100,-)
+****************************torus_3x2_adaptive	: transposed 1 traffic *******************************:
+	 Passed:   zero load (2,9.25728) saturation (54,79.8004)
+****************************tree_k3_L2_st	: transposed 1 traffic *******************************:
+	 Passed:   zero load (2,10.624) saturation (34,81.5377)
diff --git a/mpsoc/Integration_test/synthetic_sim/reports/vc_alloc_report b/mpsoc/Integration_test/synthetic_sim/golden_ref/vc_alloc
similarity index 50%
rename from mpsoc/Integration_test/synthetic_sim/reports/vc_alloc_report
rename to mpsoc/Integration_test/synthetic_sim/golden_ref/vc_alloc
index 526faa5..5fb8f91 100644
--- a/mpsoc/Integration_test/synthetic_sim/reports/vc_alloc_report
+++ b/mpsoc/Integration_test/synthetic_sim/golden_ref/vc_alloc
@@ -5,15 +5,34 @@ Verification Results:
 	 model is generated successfully.
 ****************************mesh_4x4x3_vc_spec2 : Compile *******************************:
 	 model is generated successfully.
+****************************mesh_8x8_4vc : Compile *******************************:
+	 model is generated successfully.
+****************************mesh_8x8_4vc_hetero1 : Compile *******************************:
+	 model is generated successfully.
+
+****************************mesh_8x8_4vc_hetero2 : Compile *******************************:
+	 model is generated successfully.	 
 ****************************mesh_4x4x3_vc_nonspec	: random traffic *******************************:
 	 Passed:   zero load (2,12.7475) saturation (26,188.161)
 ****************************mesh_4x4x3_vc_spec1	: random traffic *******************************:
 	 Passed:   zero load (2,12.53) saturation (22,78.2991)
 ****************************mesh_4x4x3_vc_spec2	: random traffic *******************************:
 	 Passed:   zero load (2,12.53) saturation (22,80.5533)
+****************************mesh_8x8_4vc	: random traffic *******************************:
+	 Passed:   zero load (2,18.2409) saturation (38,114.247)
+****************************mesh_8x8_4vc_hetero1	: random traffic *******************************:
+	 Passed:   zero load (2,18.273) saturation (30,162.17)
+****************************mesh_8x8_4vc_hetero2	: random traffic *******************************:
+	 Passed:   zero load (2,18.257) saturation (30,175.259)
 ****************************mesh_4x4x3_vc_nonspec	: transposed 1 traffic *******************************:
 	 Passed:   zero load (2,13.0755) saturation (14,126.234)
 ****************************mesh_4x4x3_vc_spec1	: transposed 1 traffic *******************************:
 	 Passed:   zero load (2,12.8699) saturation (14,134.914)
 ****************************mesh_4x4x3_vc_spec2	: transposed 1 traffic *******************************:
 	 Passed:   zero load (2,12.8699) saturation (14,137.797)
+****************************mesh_8x8_4vc	: transposed 1 traffic *******************************:
+	 Passed:   zero load (2,19.3785) saturation (18,146.718)
+****************************mesh_8x8_4vc_hetero1	: transposed 1 traffic *******************************:
+	 Passed:   zero load (2,19.449) saturation (18,150.624)
+****************************mesh_8x8_4vc_hetero2	: transposed 1 traffic *******************************:
+	 Passed:   zero load (2,19.3972) saturation (18,141.983)
diff --git a/mpsoc/Integration_test/synthetic_sim/reports/failed-model_report b/mpsoc/Integration_test/synthetic_sim/reports/failed-model_report
deleted file mode 100644
index 774f7dd..0000000
--- a/mpsoc/Integration_test/synthetic_sim/reports/failed-model_report
+++ /dev/null
@@ -1,39 +0,0 @@
-Verification Results:
-****************************line2_2cycle_mcast_f : Compile *******************************:
-	 model is generated successfully.
-	 %Error: Exiting due to 1 warning(s)
-
-	 %Error: Exiting due to 1 warning(s)
-
-	 %Error: Exiting due to 1 warning(s)
-
-	 %Warning-WIDTH: /gpfs/home//pronoc_verify/mpsoc_work/verify/rtl/src_noc/multicast.sv:447:48: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS's VARREF 'dest_e_addr' generates 4 bits.
-
-	 %Warning-WIDTH: /gpfs/home//pronoc_verify/mpsoc_work/verify/rtl/src_noc/multicast.sv:447:48: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS's VARREF 'dest_e_addr' generates 4 bits.
-
-	 %Warning-WIDTH: /gpfs/home//pronoc_verify/mpsoc_work/verify/rtl/src_noc/multicast.sv:447:48: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS's VARREF 'dest_e_addr' generates 4 bits.
-
-****************************line_8_sbp6_xy : Compile *******************************:
-	 model is generated successfully.
-****************************mesh_4x4_openpiton_mcast_f : Compile *******************************:
-	 model is generated successfully.
-****************************line2_2cycle_mcast_f	: random traffic *******************************:
-	 Error in running simulation: ERROR: Multicast/Broadcast is not yet supported for LINE Topology
- ERROR: Multicast/Broadcast is not yet supported for LINE Topology
- 
-****************************line_8_sbp6_xy	: random traffic *******************************:
-	 Error in running simulation:                 8000: ERROR: The destination port is not set for an active IVC request: d[R	
- 
-****************************mesh_4x4_openpiton_mcast_f	: random traffic *******************************:
-	 Error in running simulation: ERROR: SMART or SAA do not support muticast/braodcast packets
- ERROR: SMART or SAA do not support muticast/braodcast packets
- 
-****************************line2_2cycle_mcast_f	: transposed 1 traffic *******************************:
-	 Error in running simulation: ERROR: Multicast/Broadcast is not yet supported for LINE Topology
- ERROR: Multicast/Broadcast is not yet supported for LINE Topology
- 
-****************************line_8_sbp6_xy	: transposed 1 traffic *******************************:
-****************************mesh_4x4_openpiton_mcast_f	: transposed 1 traffic *******************************:
-	 Error in running simulation: ERROR: SMART or SAA do not support muticast/braodcast packets
- ERROR: SMART or SAA do not support muticast/braodcast packets
- 
diff --git a/mpsoc/Integration_test/synthetic_sim/reports/line-ring_report b/mpsoc/Integration_test/synthetic_sim/reports/line-ring_report
deleted file mode 100644
index ff14dcb..0000000
--- a/mpsoc/Integration_test/synthetic_sim/reports/line-ring_report
+++ /dev/null
@@ -1,67 +0,0 @@
-Verification Results:
-****************************line2_openpiton : Compile *******************************:
-	 model is generated successfully.
-****************************line4_smart3 : Compile *******************************:
-	 model is generated successfully.
-****************************Line_3x2_v2 : Compile *******************************:
-	 model is generated successfully.
-****************************line_4_v1_B15 : Compile *******************************:
-	 model is generated successfully.
-****************************line_4x3_2cycle_xy : Compile *******************************:
-	 model is generated successfully.
-****************************line_8_2cycle_xy : Compile *******************************:
-	 model is generated successfully.
-****************************line_8_b2 : Compile *******************************:
-	 model is generated successfully.
-****************************line_8_single_flit : Compile *******************************:
-	 model is generated successfully.
-****************************line_8x8_ssa_xy : Compile *******************************:
-	 model is generated successfully.
-****************************linex8_4vc_4c : Compile *******************************:
-	 model is generated successfully.
-****************************ring_8x8_2cycle_xy : Compile *******************************:
-	 model is generated successfully.
-****************************line2_openpiton	: random traffic *******************************:
-	 Passed:   zero load (2,8.28125) saturation (74,89.3628)
-****************************line4_smart3	: random traffic *******************************:
-	 Passed:   zero load (2,8.66406) saturation (62,115.304)
-****************************Line_3x2_v2	: random traffic *******************************:
-	 Passed:   zero load (2,9.40682) saturation (30,138.275)
-****************************line_4_v1_B15	: random traffic *******************************:
-	 Passed:   zero load (2,10.5781) saturation (62,84.8723)
-****************************line_4x3_2cycle_xy	: random traffic *******************************:
-	 Passed:   zero load (2,10.3202) saturation (26,59.0116)
-****************************line_8_2cycle_xy	: random traffic *******************************:
-	 Passed:   zero load (2,13.2248) saturation (38,122.456)
-****************************line_8_b2	: random traffic *******************************:
-	 Passed:   zero load (6,17.8996) saturation (34,105.723)
-****************************line_8_single_flit	: random traffic *******************************:
-	 Passed:   zero load (6,7.98062) saturation (38,41.7814)
-****************************line_8x8_ssa_xy	: random traffic *******************************:
-	 Passed:   zero load (2,11.3721) saturation (38,104.132)
-****************************linex8_4vc_4c	: random traffic *******************************:
-	 Passed:   zero load (2,13.1512) saturation (34,126.007)
-****************************ring_8x8_2cycle_xy	: random traffic *******************************:
-	 Passed:   zero load (2,16.8517) saturation (38,120.208)
-****************************line2_openpiton	: transposed 1 traffic *******************************:
-	 Passed:   zero load (2,8.28947) saturation (100,-)
-****************************line4_smart3	: transposed 1 traffic *******************************:
-	 Passed:   zero load (2,8.89928) saturation (54,147.034)
-****************************Line_3x2_v2	: transposed 1 traffic *******************************:
-	 Passed:   zero load (2,9.68116) saturation (26,117.311)
-****************************line_4_v1_B15	: transposed 1 traffic *******************************:
-	 Passed:   zero load (2,10.7986) saturation (54,150.53)
-****************************line_4x3_2cycle_xy	: transposed 1 traffic *******************************:
-	 Passed:   zero load (2,11.7295) saturation (18,217.171)
-****************************line_8_2cycle_xy	: transposed 1 traffic *******************************:
-	 Passed:   zero load (2,15.1871) saturation (26,126.551)
-****************************line_8_b2	: transposed 1 traffic *******************************:
-	 Passed:   zero load (2,19.2832) saturation (26,144.49)
-****************************line_8_single_flit	: transposed 1 traffic *******************************:
-	 Passed:   zero load (2,9.99617) saturation (26,65.1642)
-****************************line_8x8_ssa_xy	: transposed 1 traffic *******************************:
-	 Passed:   zero load (2,12.0755) saturation (26,125.579)
-****************************linex8_4vc_4c	: transposed 1 traffic *******************************:
-	 Passed:   zero load (2,15.1403) saturation (26,129.933)
-****************************ring_8x8_2cycle_xy	: transposed 1 traffic *******************************:
-	 Passed:   zero load (2,18.0133) saturation (18,134.597)
diff --git a/mpsoc/Integration_test/synthetic_sim/reports/multicast_report_old b/mpsoc/Integration_test/synthetic_sim/reports/multicast_report_old
deleted file mode 100644
index adccc74..0000000
--- a/mpsoc/Integration_test/synthetic_sim/reports/multicast_report_old
+++ /dev/null
@@ -1,43 +0,0 @@
-Verification Results:
-****************************mesh_4x4_2cycle_mcast_f : Compile *******************************:
-	 model is generated successfully.
-****************************mesh_4x4_LB5_B4 : Compile *******************************:
-	 model is generated successfully.
-****************************mesh_4x4_selflp_mcast_f : Compile *******************************:
-	 model is generated successfully.
-****************************mesh_4x4x2_bcast_f : Compile *******************************:
-	 model is generated successfully.
-****************************mesh_4x4x2_bcast_p : Compile *******************************:
-	 model is generated successfully.
-****************************mesh_4x4x2_mcast_p : Compile *******************************:
-	 model is generated successfully.
-****************************star6_2cycle_mcast_par : Compile *******************************:
-	 model is generated successfully.
-****************************mesh_4x4_2cycle_mcast_f	: random traffic *******************************:
-	 Passed:   zero load (2,14.4623) saturation (22,261.684)
-****************************mesh_4x4_LB5_B4	: random traffic *******************************:
-	 Passed:   zero load (2,13.234) saturation (26,78.9049)
-****************************mesh_4x4_selflp_mcast_f	: random traffic *******************************:
-	 Passed:   zero load (2,14.366) saturation (22,257.065)
-****************************mesh_4x4x2_bcast_f	: random traffic *******************************:
-	 Passed:   zero load (2,20.5192) saturation (6,1071.58)
-****************************mesh_4x4x2_bcast_p	: random traffic *******************************:
-	 Passed:   zero load (2,16.3674) saturation (6,317.19)
-****************************mesh_4x4x2_mcast_p	: random traffic *******************************:
-	 Passed:   zero load (2,13.544) saturation (14,177.748)
-****************************star6_2cycle_mcast_par	: random traffic *******************************:
-	 Passed:   zero load (2,6.531) saturation (42,82.0855)
-****************************mesh_4x4_2cycle_mcast_f	: transposed 1 traffic *******************************:
-	 Passed:   zero load (2,14.8953) saturation (26,146.747)
-****************************mesh_4x4_LB5_B4	: transposed 1 traffic *******************************:
-	 Passed:   zero load (2,13.3738) saturation (22,78.0417)
-****************************mesh_4x4_selflp_mcast_f	: transposed 1 traffic *******************************:
-	 Passed:   zero load (2,14.6488) saturation (22,166.723)
-****************************mesh_4x4x2_bcast_f	: transposed 1 traffic *******************************:
-	 Passed:   zero load (2,21.0549) saturation (6,863.495)
-****************************mesh_4x4x2_bcast_p	: transposed 1 traffic *******************************:
-	 Passed:   zero load (2,16.3766) saturation (6,371.293)
-****************************mesh_4x4x2_mcast_p	: transposed 1 traffic *******************************:
-	 Passed:   zero load (2,13.6081) saturation (10,78.461)
-****************************star6_2cycle_mcast_par	: transposed 1 traffic *******************************:
-	 Passed:   zero load (2,6.53488) saturation (42,35.6578)
diff --git a/mpsoc/Integration_test/synthetic_sim/reports/vc_alloc_report_old b/mpsoc/Integration_test/synthetic_sim/reports/vc_alloc_report_old
deleted file mode 100644
index 526faa5..0000000
--- a/mpsoc/Integration_test/synthetic_sim/reports/vc_alloc_report_old
+++ /dev/null
@@ -1,19 +0,0 @@
-Verification Results:
-****************************mesh_4x4x3_vc_nonspec : Compile *******************************:
-	 model is generated successfully.
-****************************mesh_4x4x3_vc_spec1 : Compile *******************************:
-	 model is generated successfully.
-****************************mesh_4x4x3_vc_spec2 : Compile *******************************:
-	 model is generated successfully.
-****************************mesh_4x4x3_vc_nonspec	: random traffic *******************************:
-	 Passed:   zero load (2,12.7475) saturation (26,188.161)
-****************************mesh_4x4x3_vc_spec1	: random traffic *******************************:
-	 Passed:   zero load (2,12.53) saturation (22,78.2991)
-****************************mesh_4x4x3_vc_spec2	: random traffic *******************************:
-	 Passed:   zero load (2,12.53) saturation (22,80.5533)
-****************************mesh_4x4x3_vc_nonspec	: transposed 1 traffic *******************************:
-	 Passed:   zero load (2,13.0755) saturation (14,126.234)
-****************************mesh_4x4x3_vc_spec1	: transposed 1 traffic *******************************:
-	 Passed:   zero load (2,12.8699) saturation (14,134.914)
-****************************mesh_4x4x3_vc_spec2	: transposed 1 traffic *******************************:
-	 Passed:   zero load (2,12.8699) saturation (14,137.797)
diff --git a/mpsoc/Integration_test/synthetic_sim/run.sh b/mpsoc/Integration_test/synthetic_sim/run.sh
index 67eb0a6..c103262 100755
--- a/mpsoc/Integration_test/synthetic_sim/run.sh
+++ b/mpsoc/Integration_test/synthetic_sim/run.sh
@@ -3,9 +3,9 @@
 servers=( 'mn5')
 #servers' shorthand name. They should be defined in ~/.ssh/config :
 # 
-#	Host your_short_name
-#		HostName server.on.the.web
-#		User user_to_user
+#    Host your_short_name
+#        HostName server.on.the.web
+#        User user_to_user
 
 
 my_ssh="ssh -t -o StrictHostKeyChecking=no"
@@ -34,11 +34,11 @@ ProNoC=$(realpath "$SCRPT_DIR_PATH/../..")
 
 my_srcs=( "rtl"
     "Integration_test"
-	"src_verilator"
-	"src_c/netrace-1.0"
-	"src_c/synfull"
-	"script"
-	"/perl_gui/lib/perl" )
+    "src_verilator"
+    "src_c/netrace-1.0"
+    "src_c/synfull"
+    "script"
+    "/perl_gui/lib/perl" )
 
 
 
@@ -50,14 +50,12 @@ PRUN=20
 MIN=2
 MAX=80
 STEP=4
-CONFS="default"
+CONFS="general"
+FLAT=""
 
 CONFS_path=$(realpath $SCRPT_DIR_PATH/configurations)
 
-
-
-
-while getopts "h?a:p:u:l:s:d:m:" opt; do
+while getopts "h?a:p:u:l:s:d:m:f" opt; do
   case "$opt" in
     h|\?)
       echo "
@@ -77,6 +75,9 @@ Options:
                     Default: 5.
   -s <int>          Step size for increasing injection ratio in percentage (%). 
                     Default: 25.
+  -f                Enable flat mode. Use NoC_top as the Verilator top module.
+                    If not set, Verilator will be run on internal router modules
+                    and they will be connected manually in testbench.c.
   -d <dir>          Name of the directory where simulation model configuration 
                     files are located. Default: \"$CONFS\".
   -m <models>       Comma-separated list of simulation model names in the 
@@ -123,6 +124,8 @@ Available Configuration Directories for -d Option:
       ;; 
     s) STEP=$OPTARG
       ;;  
+    f) FLAT="-f"
+      ;;
     d) CONFS=$OPTARG
       ;; 
     m) model="-m $OPTARG"
@@ -148,6 +151,9 @@ echo "  Step Size           : $STEP (Simulation starts at MIN and increments by"
 echo "                        STEP to reach MAX)"
 echo "  Target Directory    : $CONFS (The model target directory where simulation"
 echo "                        is running)"
+if  [[ $FLAT == "-f" ]]; then
+    echo "  flat mode is enabled" 
+fi
 if [ -n "$model" ]; then
     echo "  Model Under Test    : $model (The model name under test)"
 fi
@@ -156,13 +162,16 @@ if [ -n "$Leftovers" ]; then
 fi
 echo "---------------------------------------------"
 
-args="-p $PRUN -u $MAX -l $MIN -s $STEP -d $CONFS $model"
+args="-p $PRUN -u $MAX -l $MIN -s $STEP -d $CONFS $model $FLAT "
 
-report="${SCRPT_DIR_PATH}/reports/${CONFS}_report"
+log_dir="${SCRPT_DIR_PATH}/result_logs"
+log_file="${log_dir}/${CONFS}"
+golden_ref="${SCRPT_DIR_PATH}/golden_ref/${CONFS}"
 
+mkdir -p $log_dir
 
-if [ -f "$report" ]; then
-    rm "$report"
+if [ -f "$log_file" ]; then
+    rm "$log_file"
 fi
 
 
@@ -172,7 +181,7 @@ fi
 
 #step one login in the server and find how much is bussy 
 function get_server_load_percentage {
-	 # Retrieve uptime and core information from the server
+    # Retrieve uptime and core information from the server
     out=$($my_ssh "$1" "uptime")
     load_avg=$(echo "$out" | grep -oP '(?<=load average: )[\d.]+' | head -n 1)  # Extract 1-minute load average
     nproc=$($my_ssh "$1" "nproc" | tr -d '\r')  # Remove any extra characters (e.g., carriage return)
@@ -187,40 +196,40 @@ function get_server_load_percentage {
 
 
 function select_a_server {
-	min_load="100"	
-	for i in "${servers[@]}"; do
-	 		echo "get load average on $i server"        
-			get_server_load_percentage $i			
-			if [ $min_load  -gt $load_percentage ]
-			then
-				min_load=$load_percentage
-				my_server=$i
-			fi		
-	done
-	if [ $min_load -gt $max_allowed_server_load_percentage ] 
-	then
-		echo "[INFO] All servers are busy. Cannot continue"		
-		exit
-	fi
-	echo "[INFO] Server $my_server is selected for running the integration test."
+    min_load="100"    
+    for i in "${servers[@]}"; do
+            echo "get load average on $i server"        
+            get_server_load_percentage $i            
+            if [ $min_load  -gt $load_percentage ]
+            then
+                min_load=$load_percentage
+                my_server=$i
+            fi        
+    done
+    if [ $min_load -gt $max_allowed_server_load_percentage ] 
+    then
+        echo "[INFO] All servers are busy. Cannot continue"        
+        exit
+    fi
+    echo "[INFO] Server $my_server is selected for running the integration test."
 }
 
 
 function copy_sources {
-	$my_ssh $my_server  rm -rf  ${SERVER_ROOT_DIR}
-	$my_ssh $my_server  mkdir -p "${SERVER_ROOT_DIR}/mpsoc/perl_gui/lib/"
+    $my_ssh $my_server  rm -rf  ${SERVER_ROOT_DIR}
+    $my_ssh $my_server  mkdir -p "${SERVER_ROOT_DIR}/mpsoc/perl_gui/lib/"
     $my_ssh $my_server  mkdir -p "${SERVER_ROOT_DIR}/mpsoc/src_c/"
-	$my_ssh $my_server  mkdir -p "${SERVER_ROOT_DIR}/mpsoc_work"
-	for i in "${my_srcs[@]}"; do	
-		echo "Copy $i  on the server"        
-		$my_scp -r "$ProNoC/$i"  "$my_server:${SERVER_ROOT_DIR}/mpsoc/$i"
-	done	
+    $my_ssh $my_server  mkdir -p "${SERVER_ROOT_DIR}/mpsoc_work"
+    for i in "${my_srcs[@]}"; do    
+        echo "Copy $i  on the server"        
+        $my_scp -r "$ProNoC/$i"  "$my_server:${SERVER_ROOT_DIR}/mpsoc/$i"
+    done    
 }
 
 
 function run_test {
-	cmd="export PRONOC_WORK=${SERVER_ROOT_DIR}/mpsoc_work;" 
-	$my_ssh $my_server $cmd
+    cmd="export PRONOC_WORK=${SERVER_ROOT_DIR}/mpsoc_work;" 
+    $my_ssh $my_server $cmd
 
 }
 
@@ -232,15 +241,14 @@ if [ "${servers[0]}" != "local" ]; then
     copy_sources
     echo "source \"/etc/profile\"; bash server_run.sh $args"
 $my_ssh $my_server  "cd ${SERVER_ROOT_DIR}/mpsoc/Integration_test/synthetic_sim/src;  source \"/etc/profile\";  bash   server_run.sh $args;"
-    $my_scp -r   "$my_server:${SERVER_ROOT_DIR}/mpsoc/Integration_test/synthetic_sim/report"  "$report"
+    $my_scp -r   "$my_server:${SERVER_ROOT_DIR}/mpsoc/Integration_test/synthetic_sim/result_logs/${CONFS}"  "$log_file"
 
 else 
 
     cd $SCRPT_DIR_PATH/src; bash   server_run.sh $args
-    mv $SCRPT_DIR_PATH/report  $report
 
 fi
 
 
 wait
-meld "$report" "${report}_old" &
+meld "$golden_ref" "$log_file" &
diff --git a/mpsoc/Integration_test/synthetic_sim/src/check.pl b/mpsoc/Integration_test/synthetic_sim/src/check.pl
new file mode 100644
index 0000000..981f2ee
--- /dev/null
+++ b/mpsoc/Integration_test/synthetic_sim/src/check.pl
@@ -0,0 +1,131 @@
+#!/usr/bin/perl
+use strict;
+use warnings;
+
+my $tolerance=5;
+
+use Getopt::Std;
+
+# declare the perl command line flags/options we want to allow
+my %options=();
+getopts("hn:o:", \%options);
+
+# test for the existence of the options on the command line.
+# in a normal program you'd do more than just print these.
+
+
+
+# other things found on the command line
+print "Other things found on the command line:\n" if $ARGV[0];
+foreach (@ARGV)
+{
+  print "$_\n";
+}
+
+
+if (defined $options{h} ) {
+print " Usage: perl verify.pl [options]
+      -h show this help
+      -o <file name>  : Enter the golden refrence results file
+      -n <file name>  : Enter the newly obtained results file    
+";
+exit;
+}
+
+my $new_file= $options{n} // "result_new.txt";
+my $old_file= $options{o} // "result_old.txt";
+my $fail_report="$ENV{PRONOC_WORK}/failures.txt";
+# Track whether any failures or degradations were found
+my $has_failures = 0;
+
+my (%old_results, %new_results);
+my @failures=();
+
+# Parse result files
+parse_file($old_file, \%old_results);
+parse_file($new_file, \%new_results);
+
+
+
+foreach my $key (sort keys %new_results) {
+    my $new = $new_results{$key};
+    
+    if ($new->{status} eq "FAIL") {
+        print_error("[FAILURE] $key: Simulation failed");      
+        next;
+    }
+
+    unless (exists $old_results{$key}) {
+        print "[NEW ENTRY] $key: No reference in old file.\n";
+        next;
+    }
+
+    my $old = $old_results{$key};
+
+    my $zero_delay_change = percent_increase($old->{zero_delay}, $new->{zero_delay});
+    my $sat_inj_change    = percent_decrease($old->{sat_inj}, $new->{sat_inj});
+
+    if ($zero_delay_change > $tolerance || $sat_inj_change > $tolerance) {
+        my $err=sprintf("[DEGRADED] %-60s Zero delay ↑ %.2f%%, Sat inj ↓ %.2f%%\n",  $key, $zero_delay_change, $sat_inj_change);
+            print_error($err);
+    } else {
+        print "[OK] $key\n";
+    }
+}
+
+
+sub print_error {
+    my ($msg) = @_;  # Capture the argument
+    print "$msg.\n";
+    push @failures, $msg;
+    $has_failures = 1;
+}
+
+sub parse_file {
+    my ($file, $result_hash) = @_;
+    open my $fh, '<', $file or die "Cannot open $file: $!";
+    my $key = "";
+    while (<$fh>) {
+        if (/^\*+(.+?): (.*?) \*+:/) {
+            $key = "$1 : $2";
+        } elsif (/Error in running simulation|%Error:/) {
+            $$result_hash{$key}{status} = "FAIL";
+        } elsif (/Passed:\s+zero load \(\d+,([\d.]+)\)\s+saturation \((\d+),([\d.]+)\)/) {
+            $$result_hash{$key}{status} = "OK";
+            $$result_hash{$key}{zero_delay} = $1;  # Delay cycles
+            $$result_hash{$key}{sat_inj}    = $2;  # Injection ratio
+        }
+    }
+    close $fh;
+}
+
+sub percent_increase {
+    my ($old, $new) = @_;
+    return 0 unless defined $old && $old != 0;
+    return (($new - $old) / $old) * 100;
+}
+
+sub percent_decrease {
+    my ($old, $new) = @_;
+    return 0 unless defined $old && $old != 0;
+    return (($old - $new) / $old) * 100;
+}
+
+
+
+open my $out, ">>$fail_report" or die "could not open $fail_report: $!";
+open my $in, '<', $new_file or die "Cannot open $new_file: $!";
+
+foreach my $fail (@failures) {
+    print "$fail\n";
+    print $out "$fail\n";
+}
+
+while (my $line = <$in>) {
+    print $out $line;
+}
+
+close $in;
+close $out;
+
+exit($has_failures);
diff --git a/mpsoc/Integration_test/synthetic_sim/src/deafult_noc_param b/mpsoc/Integration_test/synthetic_sim/src/deafult_noc_param
deleted file mode 100644
index 7f2f3cd..0000000
--- a/mpsoc/Integration_test/synthetic_sim/src/deafult_noc_param
+++ /dev/null
@@ -1,87 +0,0 @@
-$model = bless( {
-                  'noc_param' => {
-"TOPOLOGY" => "\"MESH\"",
-"T1" => "8",
-"T2" => "8",
-"T3" => "1",
-"V" => "2",
-"B" => "4",
-"LB" => "B",
-"Fpay" => "32",
-"ROUTE_NAME" => "\"XY\"",
-"PCK_TYPE" => "  \"MULTI_FLIT\"",  
-"MIN_PCK_SIZE" => "2",
-"BYTE_EN" => "0",
-"SSA_EN" => "\"NO\"",
-"CONGESTION_INDEX" => "3",
-"ESCAP_VC_MASK" => "2'b01",
-"VC_REALLOCATION_TYPE" => "\"NONATOMIC\"",
-"COMBINATION_TYPE" => "\"COMB_NONSPEC\"",
-"MUX_TYPE" => "\"BINARY\"",
-"C" => "0",
-"CLASS_SETTING"=> "{V{1'b1}}",
-"DEBUG_EN" => "1",
-"ADD_PIPREG_AFTER_CROSSBAR" => "1'b0",
-"FIRST_ARBITER_EXT_P_EN" => "1",
-"SWA_ARBITER_TYPE" => "\"RRA\"",
-"WEIGHTw" => "4",
-"AVC_ATOMIC_EN" => "0",
-"CLASS_SETTING" => "{V{1'b1}}",
-"SMART_MAX" => "0",
-"SELF_LOOP_EN" => "\"NO\"",
-"MAX_PCK_NUM " => " 1000000000",
-"MAX_PCK_SIZ " => " 16383" ,
-"MAX_SIM_CLKs" => "  1000000000",
-"TIMSTMP_FIFO_NUM " => " 16",
-"CVw"=> "(C==0)? V : C * V",
-"CAST_TYPE" => "\"UNICAST\"",
-"MCAST_ENDP_LIST" => "'b1111",	
-
-
-                                 },
-
-
- 'parameters_order' => {
-'noc_param' =>
-[
-                                                              'TOPOLOGY',
-                                                              'T1',
-                                                              'T2',
-                                                              'T3',
-                                                              'V',
-                                                              'B',
-                                                              'LB',
-                                                              'Fpay',
-                                                              'ROUTE_NAME',
-                                                              'PCK_TYPE',
-                                                              'MIN_PCK_SIZE',
-                                                              'BYTE_EN',
-                                                              'SSA_EN',
-                                                              'SMART_MAX',
-                                                              'CONGESTION_INDEX',
-                                                              'ESCAP_VC_MASK',
-                                                              'VC_REALLOCATION_TYPE',
-                                                              'COMBINATION_TYPE',
-                                                              'MUX_TYPE',
-                                                              'C',
-'CLASS_SETTING',
-                                                              'DEBUG_EN',
-                                                              'ADD_PIPREG_AFTER_CROSSBAR',
-                                                              'FIRST_ARBITER_EXT_P_EN',
-                                                              'SWA_ARBITER_TYPE',
-                                                              'WEIGHTw',
-                                                              'SELF_LOOP_EN',
-                                                              'AVC_ATOMIC_EN',
-"MAX_PCK_NUM " ,
-"MAX_PCK_SIZ ",
-"MAX_SIM_CLKs",
-"TIMSTMP_FIFO_NUM ", 
-"CVw",
-"CAST_TYPE",
-"MCAST_ENDP_LIST"	
-                                                  ],
-
-}
-                  
-                },
-);
diff --git a/mpsoc/Integration_test/synthetic_sim/src/server_run.sh b/mpsoc/Integration_test/synthetic_sim/src/server_run.sh
index 5b9bd95..2be366c 100755
--- a/mpsoc/Integration_test/synthetic_sim/src/server_run.sh
+++ b/mpsoc/Integration_test/synthetic_sim/src/server_run.sh
@@ -7,7 +7,8 @@ SCRPT_DIR_PATH=$(dirname $SCRPT_FULL_PATH)
 
 
 export PRONOC_WORK=$(realpath "$SCRPT_DIR_PATH/../../../../mpsoc_work")
-export VERILATOR_ROOT=~/scratch/`whoami`/verilator_4_104
+export VERILATOR_ROOT=~/scratch/`whoami`/verilator_4_104 
+#export VERILATOR_ROOT=~/scratch/`whoami`/verilator_5_014
 export PATH=$PATH:$VERILATOR_ROOT/bin
 export C_INCLUDE_PATH=$VERILATOR_ROOT/include
 export CPLUS_INCLUDE_PATH=$VERILATOR_ROOT/include
diff --git a/mpsoc/Integration_test/synthetic_sim/src/src.pl b/mpsoc/Integration_test/synthetic_sim/src/src.pl
index ae2cce9..ae49515 100755
--- a/mpsoc/Integration_test/synthetic_sim/src/src.pl
+++ b/mpsoc/Integration_test/synthetic_sim/src/src.pl
@@ -1,13 +1,16 @@
 #!/usr/bin/perl -w
 
-use lib "../perl_lib";
+use strict;
+use warnings;
 
+use lib "../perl_lib";
 use List::MoreUtils qw(uniq);
 use Proc::Background;
 use File::Path qw( rmtree );
 use File::Path qw( make_path );
 use Cwd qw(realpath);
 use Cwd 'abs_path';
+use File::Copy;
 
 my $script_path = dirname(__FILE__);
 my $dirname = realpath("$script_path/..");
@@ -18,48 +21,36 @@
 print "confs_dir: $confs_dir\n";
 print "Root: $root\n";
 
-
 my $rtl_dir = "$ENV{PRONOC_WORK}/verify/rtl";
 my $work    = "$ENV{PRONOC_WORK}/verify/work";
 my $verify  = "$ENV{PRONOC_WORK}/verify";
 
-
-
 my $src_verilator = "$root/src_verilator";
 my $src_c = "$root/src_c";
 my $src = "$script_path";
-my $report = "$dirname/report";
+my $noc_default_param_file= "$root/Integration_test/default_noc_param";
 
 #require "$root/perl_gui/lib/perl/common.pl";
 require "$root/perl_gui/lib/perl/topology.pl";
 
-use strict;
-use warnings;
-
 my $pp;
-	$pp= do "$src/deafult_noc_param";
-	die "Error reading: $@" if $@;
-
-	my $param = $pp->{'noc_param'};
-	my %default_noc_param=%{$param};
-	my @params=object_get_attribute_order($pp,'noc_param');
+$pp= do $noc_default_param_file;
+die "Error reading: $@" if $@;
 
+my $param = $pp->{'noc_param'};
+my %default_noc_param=%{$param};
+my @params=object_get_attribute_order($pp,'noc_param');
 
 
 #read default param
-
-
 sub recompile_synful {
     # Define the command to recompile Synful
     my $cmd = "cd $src_c/synfull/traffic-generator/src && make; wait;";
-
     print "******************* Compile Synful *******************\n";
     print "Executing command: $cmd\n";
-
     # Run the command and capture its exit status
     my $output = `$cmd 2>&1`; # Capture both stdout and stderr
     my $exit_status = $? >> 8; # Extract exit code
-
     # Check for errors
     if ($exit_status != 0) {
         die "Error: Compilation of Synful failed with exit code $exit_status. Output:\n$output\n";
@@ -69,148 +60,137 @@ sub recompile_synful {
 }
 
 sub gen_noc_param_h{
-	my $mpsoc=shift;
-	my $param_h="\n\n//NoC parameters\n";
-	
-	my $topology = $mpsoc->object_get_attribute('noc_param','TOPOLOGY');
-	$topology =~ s/"//g;
-	$param_h.="\t#define  IS_${topology}\n";
-	
-	my ($NE, $NR, $RAw, $EAw, $Fw) = get_topology_info($mpsoc);
-	
-	my @params=$mpsoc->object_get_attribute_order('noc_param');
-	my $custom_topology = $mpsoc->object_get_attribute('noc_param','CUSTOM_TOPOLOGY_NAME');
-	foreach my $p (@params){
-		my $val=$mpsoc->object_get_attribute('noc_param',$p);
-		next if($p eq "CUSTOM_TOPOLOGY_NAME");
-		$val=$custom_topology if($p eq "TOPOLOGY" && $val eq "\"CUSTOM\"");
-		if($p eq "MCAST_ENDP_LIST" || $p eq "ESCAP_VC_MASK"){
-			$val="$NE".$val if($p eq 'MCAST_ENDP_LIST');
-			$val =~ s/\'/\\\'/g;
-			$val="\"$val\"";			
-		}
-		$param_h=$param_h."\t#define $p\t$val\n";
-		
-		#print "$p:$val\n";
-		
-	}
-	
-	 
-	my $v=$mpsoc->object_get_attribute('noc_param',"V")-1;
-	my $escape=$mpsoc->object_get_attribute('noc_param',"ESCAP_VC_MASK");
-	if (! defined $escape){
-		#add_text_to_string (\$param_h,"\tlocalparam [$v	:0] ESCAP_VC_MASK=1;\n");
-		#add_text_to_string (\$pass_param,".ESCAP_VC_MASK(ESCAP_VC_MASK),\n"); 
-	}
-	#add_text_to_string (\$param_h," \tlocalparam  CVw=(C==0)? V : C * V;\n");
-	#add_text_to_string (\$pass_param,".CVw(CVw)\n");
-	
-	#remove 'b and 'h
-	#$param_h =~ s/\d\'b/ /g;
-	#$param_h =~ s/\'h/ /g;
-	
-	
-	return  $param_h;	
+    my $mpsoc=shift;
+    my $param_h="\n\n//NoC parameters\n";
+    my $topology = $mpsoc->object_get_attribute('noc_param','TOPOLOGY');
+    $topology =~ s/"//g;
+    $param_h.="\t#define  IS_${topology}\n";
+    my ($NE, $NR, $RAw, $EAw, $Fw) = get_topology_info($mpsoc);
+    my @params=$mpsoc->object_get_attribute_order('noc_param');
+    my $custom_topology = $mpsoc->object_get_attribute('noc_param','CUSTOM_TOPOLOGY_NAME');
+    foreach my $p (@params){
+        my $val=$mpsoc->object_get_attribute('noc_param',$p);
+        next if($p eq "CUSTOM_TOPOLOGY_NAME");
+        next if($p eq "int VC_CONFIG_TABLE [MAX_ROUTER][MAX_PORT]");
+        $val=$custom_topology if($p eq "TOPOLOGY" && $val eq "\"CUSTOM\"");
+        if($p eq "MCAST_ENDP_LIST" || $p eq "ESCAP_VC_MASK"){
+            $val="$NE".$val if($p eq 'MCAST_ENDP_LIST');
+            $val =~ s/\'/\\\'/g;
+            $val="\"$val\"";
+        }
+        $param_h=$param_h."\t#define $p\t$val\n";
+        
+        #print "$p:$val\n";
+        
+    }
+    my $v=$mpsoc->object_get_attribute('noc_param',"V")-1;
+    my $escape=$mpsoc->object_get_attribute('noc_param',"ESCAP_VC_MASK");
+    if (! defined $escape){
+        #add_text_to_string (\$param_h,"\tlocalparam [$v    :0] ESCAP_VC_MASK=1;\n");
+        #add_text_to_string (\$pass_param,".ESCAP_VC_MASK(ESCAP_VC_MASK),\n"); 
+    }
+    #add_text_to_string (\$param_h," \tlocalparam  CVw=(C==0)? V : C * V;\n");
+    #add_text_to_string (\$pass_param,".CVw(CVw)\n");
+    
+    #remove 'b and 'h
+    #$param_h =~ s/\d\'b/ /g;
+    #$param_h =~ s/\'h/ /g;
+    return  $param_h;
 }
 
 
 sub gen_sim_parameter_h {
-	my ($param_h,$includ_h,$ne,$nr,$router_p,$fifow)=@_;
-	
-	$param_h =~ s/\d\'b/ /g;
-	my $text=  "
+    my ($param_h,$includ_h,$ne,$nr,$router_p,$fifow)=@_;
+    $param_h =~ s/\d\'b/ /g;
+    my $text=  "
 #ifndef     INCLUDE_PARAM
-	#define   INCLUDE_PARAM \n \n 
-
-	$param_h 
-	 	
- 	#define NE  $ne
- 	#define NR  $nr
- 	#define ROUTER_P_NUM $router_p
- 	
-	extern Vtraffic		*traffic[NE];
-	extern Vpck_inj     *pck_inj[NE];
-	extern int reset,clk;
-	
-	//simulation parameter	
-	#define MAX_RATIO   1000
-	#define AVG_LATENCY_METRIC \"HEAD_2_TAIL\"
-	#define TIMSTMP_FIFO_NUM   $fifow
-	
-	$includ_h
-\n \n \#endif" ; 
-	return $text;	
-}	
+    #define   INCLUDE_PARAM \n \n 
 
+    $param_h 
+    
+    #define NE  $ne
+    #define NR  $nr
+    #define ROUTER_P_NUM $router_p
+    
+    extern Vtraffic     *traffic[NE];
+    extern Vpck_inj     *pck_inj[NE];
+    extern int reset,clk;
+    
+    //simulation parameter
+    #define MAX_RATIO   1000
+    #define AVG_LATENCY_METRIC \"HEAD_2_TAIL\"
+    #define TIMSTMP_FIFO_NUM   $fifow
+    
+    $includ_h
+\n \n \#endif" ;
+    return $text;
+}
 
 sub extract_and_update_noc_sim_statistic {
-	my ($stdout)=@_;
-	my $avg_latency =capture_number_after("average packet latency =",$stdout);
-	my $avg_flit_latency =capture_number_after("average flit latency =",$stdout);
-	my $sd_latency =capture_number_after("standard_dev =",$stdout);
-	my $avg_thput =capture_number_after("Avg throughput is:",$stdout);
-	my $total_time =capture_number_after("simulation clock cycles:",$stdout);
-	my $latency_perhop = capture_number_after("average latency per hop =",$stdout);
-	my %packet_rsvd_per_core = capture_cores_data("total number of received packets:",$stdout);
-	my %worst_rsvd_delay_per_core = capture_cores_data('worst-case-delay of received packets \(clks\):',$stdout);
-	my %packet_sent_per_core = capture_cores_data("total number of sent packets:",$stdout);
-	my %worst_sent_delay_per_core = capture_cores_data('worst-case-delay of sent packets \(clks\):',$stdout);
-
-
+    my ($stdout)=@_;
+    my $avg_latency =capture_number_after("average packet latency =",$stdout);
+    my $avg_flit_latency =capture_number_after("average flit latency =",$stdout);
+    my $sd_latency =capture_number_after("standard_dev =",$stdout);
+    my $avg_thput =capture_number_after("Avg throughput is:",$stdout);
+    my $total_time =capture_number_after("simulation clock cycles:",$stdout);
+    my $latency_perhop = capture_number_after("average latency per hop =",$stdout);
+    my %packet_rsvd_per_core = capture_cores_data("total number of received packets:",$stdout);
+    my %worst_rsvd_delay_per_core = capture_cores_data('worst-case-delay of received packets \(clks\):',$stdout);
+    my %packet_sent_per_core = capture_cores_data("total number of sent packets:",$stdout);
+    my %worst_sent_delay_per_core = capture_cores_data('worst-case-delay of sent packets \(clks\):',$stdout);
 }
 
 sub get_model_parameter {
-	my $model =shift;	
-	my $o;
-	$o= do $model;
-	my %new_param=%{$o};
+    my $model =shift;
+    my $o;
+    $o= do $model;
+    my $pp = $o->{'noc_param'};
+    my %new_param=%{$pp};
     die "Error reading: $@" if $@;
-	my %temp;
-	foreach my $p (@params){
-		$temp{$p} = $default_noc_param{$p};       
-	}
-	foreach my $p (sort keys %new_param){
-		$temp{$p} = $new_param{$p};
-	}
-	return %temp;
+    my %temp;
+    foreach my $p (@params){
+        $temp{$p} = $default_noc_param{$p};
+    }
+    foreach my $p (sort keys %new_param){
+        $temp{$p} = $new_param{$p};
+    }
+    return %temp;
 }
 
 sub gen_noc_localparam_v {
-	my ($m,$ref) = @_;
-	my %model = %{$ref};
-	my %temp;
-
+    my ($m,$ref,$flat) = @_;
+    $flat//0; #if flat is 1, it use noc_top as top level modules otherwise it split verilator over internal modules
+    my %model = %{$ref};
+    my %temp;
     
-	foreach my $p (@params){
-		$temp{$p} = $default_noc_param{$p};
+    foreach my $p (@params){
+        $temp{$p} = $default_noc_param{$p};
         $m->{noc_param}{$p}=$default_noc_param{$p};
-	}
-	foreach my $p (sort keys %model){
-		$temp{$p} = $model{$p};
-		$m->{noc_param}{$p}=$model{$p};
-	}
-
-	object_add_attribute_order($m,'noc_param',@params);
-
-	my $param_v="`ifdef NOC_LOCAL_PARAM \n";
-	foreach my $p (@params){
-		$param_v.="localparam $p = $temp{$p};\n";
-	}
-	$param_v.="`endif\n";
-
-	my ($nr,$ne,$router_p,$ref_tops,$includ_h) = get_noc_verilator_top_modules_info($m);
-	my %tops = %{$ref_tops};	
-	$tops{Vtraffic} = "--top-module traffic_gen_top";	
-	$tops{Vpck_inj} = "--top-module packet_injector_verilator";	
-
-
-
-
-	my $param_h=gen_noc_param_h($m);
-	$includ_h = gen_sim_parameter_h($param_h,$includ_h,$ne,$nr,$router_p,'16');	
-
-	return ($param_v,$includ_h,\%tops);
+    }
+    foreach my $p (sort keys %model){
+        $temp{$p} = $model{$p};
+        $m->{noc_param}{$p}=$model{$p};
+    }
+    object_add_attribute_order($m,'noc_param',@params);
+    my $param_v="`ifdef NOC_LOCAL_PARAM \n";
+    foreach my $p (@params){
+        $param_v.="localparam $p = $temp{$p};\n";
+    }
+    $param_v.="`endif\n";
+    my ($nr,$ne,$router_p,$ref_tops,$includ_h) = get_noc_verilator_top_modules_info($m);
+    my %tops = (
+       Vtraffic  => "--top-module traffic_gen_top",
+       Vpck_inj  => "--top-module packet_injector_verilator",
+    );
 
+    if ($flat) {
+        $tops{Vnoc} = "--top-module noc_top_v";
+    } else {
+        %tops = (%{$ref_tops}, %tops);  # Merge ref_tops first so Vtraffic/Vpck_inj override if needed
+    }
+    my $param_h=gen_noc_param_h($m);
+    $includ_h = gen_sim_parameter_h($param_h,$includ_h,$ne,$nr,$router_p,'16');
+    return ($param_v,$includ_h,\%tops);
 }
 
 
@@ -225,13 +205,11 @@ sub copy_src_files {
     print "Creating working directory: $rtl_dir\n";
     make_path($rtl_dir, { mode => 0700 }) or die "Error: Cannot create directory $rtl_dir: $!\n";
     $rtl_dir=realpath ($rtl_dir);
-
     # Define source directories
     my %src_dirs = (
         "$root/rtl/src_noc"    => "$rtl_dir/src_noc",
         "$root/rtl/src_topology" => "$rtl_dir/src_topology",
     );
-
     # Copy source directories
     for my $src (keys %src_dirs) {
         my $dest = $src_dirs{$src};
@@ -239,503 +217,434 @@ sub copy_src_files {
             dircopy($src, $dest) or die "Error: Cannot copy $src to $dest: $!\n";
         }
     }
-
     # Remove specific file if it exists in the destination
     my $noc_localparam_file = "$rtl_dir/src_noc/noc_localparam.v";
     unlink $noc_localparam_file if -e $noc_localparam_file;
-
     # Copy individual Verilog files from root RTL directory
     for my $file (glob "$root/rtl/*.v") {
         copy($file, $rtl_dir) or die "Error: Cannot copy $file to $rtl_dir: $!\n";
     }
-
     print "Source files copied successfully.\n";
 }
 
 
-
-
-
 sub gen_file_list{
-	my $path=shift;
-	my $f="+incdir+$rtl_dir/
+    my $path=shift;
+    my $f="+incdir+$rtl_dir/
 +incdir+$rtl_dir/src_noc/
 +incdir+$path
 ";
 
-	my @files = File::Find::Rule->file()
-                          ->name( '*.v','*.V','*.sv' )
-                          ->in( "$rtl_dir" );
-
- 	#make sure source files have key word 'module' 
-	my @sources;
-	foreach my $p (@files){
-		push (@sources,$p)	if(check_file_has_string($p,'endpackage')); 
-	}
-	foreach my $p (@files){
-		push (@sources,$p)	if(check_file_has_string($p,'module')); 
-	}
-	my $files = join ("\n",@sources);
-	$f.=$files;
- 
-
-	open(FILE,  ">$path/file_list.f") || die "Can not open: $!";
-	print FILE $f;
-	close FILE;
+    my @files = File::Find::Rule->file()
+        ->name( '*.v','*.V','*.sv' )
+        ->in( "$rtl_dir" );
+    #make sure source files have key word 'module' 
+    my @sources;
+    foreach my $p (@files){
+        push (@sources,$p)    if(check_file_has_string($p,'endpackage')); 
+    }
+    foreach my $p (@files){
+        push (@sources,$p)    if(check_file_has_string($p,'module')); 
+    }
+    my $files = join ("\n",@sources);
+    $f.=$files;
+    open(FILE,  ">$path/file_list.f") || die "Can not open: $!";
+    print FILE $f;
+    close FILE;
 }
 
 sub gen_verilator_sh{
-	my ($ref,$file)=@_;
-	my %tops = %{$ref};
-	my $make_lib="";
+    my ($ref,$file,$flat)=@_;
+    my %tops = %{$ref};
+    my $make_lib="";
     my $jobs=0;
-	my $cmd= '#!/bin/bash
-	SCRPT_FULL_PATH=$(realpath ${BASH_SOURCE[0]})
-	SCRPT_DIR_PATH=$(dirname $SCRPT_FULL_PATH)
-
-	cmn="-O3  -CFLAGS -O3"
-	currentver=$(verilator --version | head -n1 | cut -d" " -f2)	
-	requiredver="4.0.0"
- 	if [ "$(printf \'%s\n\' "$requiredver" "$currentver" | sort -V | head -n1)" = "$requiredver" ]; then 
+    
+    # List of Verilator warnings to suppress
+    my @verilator_ignores=(
+    
+    "UNOPTFLAT"
+    );
+    
+    my $ignore_flags="";
+    if($flat){
+        foreach my $warn (@verilator_ignores){
+            $ignore_flags .= " --Wno-${warn}";
+        }
+    }
+    my $cmd= '#!/bin/bash
+    SCRPT_FULL_PATH=$(realpath ${BASH_SOURCE[0]})
+    SCRPT_DIR_PATH=$(dirname $SCRPT_FULL_PATH)
+    
+    cmn="-O3  -CFLAGS -O3"
+    currentver=$(verilator --version | head -n1 | cut -d" " -f2)
+    requiredver="4.0.0"
+    if [ "$(printf \'%s\n\' "$requiredver" "$currentver" | sort -V | head -n1)" = "$requiredver" ]; then 
         echo "Verilator vesrion Greater than or equal to ${requiredver}, compile with -Wno-TIMESCALEMOD flag"
-		cmn=" $cmn -Wno-TIMESCALEMOD";
- 	else
+        cmn=" $cmn -Wno-TIMESCALEMOD";
+    else
         echo "Verilator vesrion is Less than ${requiredver}"
- 	fi
+    fi
 ';
-
-	foreach my $top (sort keys %tops) {
-		$cmd.= "verilator  -f \$SCRPT_DIR_PATH/file_list.f --cc $tops{$top}  --prefix \"$top\" \$cmn & \n";
-	}
-	$cmd.="wait\n";
-	foreach my $top (sort keys %tops) {
-		
-		$cmd.=" 
-	if ! [ -f \$SCRPT_DIR_PATH/obj_dir/$top.cpp ]; then
-		echo  \"Failed to generate: \$SCRPT_DIR_PATH/obj_dir/$top.cpp \"
-		exit 1	
-	fi\n";
-		$make_lib.="make lib$jobs &\n";
-		$jobs++;
-	}
-
-
-	$cmd.="
+    foreach my $top (sort keys %tops) {
+        $cmd.= "verilator  $ignore_flags -DNO_HETRO_IVC=1 -f \$SCRPT_DIR_PATH/file_list.f --cc $tops{$top}  --prefix \"$top\" \$cmn & \n";
+    }
+    $cmd.="wait\n";
+    foreach my $top (sort keys %tops) {
+        
+        $cmd.=" 
+    if ! [ -f \$SCRPT_DIR_PATH/obj_dir/$top.cpp ]; then
+        echo  \"Failed to generate: \$SCRPT_DIR_PATH/obj_dir/$top.cpp \"
+        exit 1
+    fi\n";
+        $make_lib.="make lib$jobs &\n";
+        $jobs++;
+    }
+    $cmd.="
 cd \$SCRPT_DIR_PATH/obj_dir/
 $make_lib
 wait
-
-make sim
 ";
-	save_file("$file",$cmd);
-	
+    $cmd.=($flat)? "make sim_flat\n" : "make sim\n";
+
+    save_file("$file",$cmd);
 }
 
 sub get_model_names {
-	my ($mref,$inref) = @_;
-	my @models = @{$mref};
-	my ($paralel_run,$MIN,$MAX,$STEP,$model_dir)=@{$inref};
-	my $full_path;
-	$full_path = "$model_dir" if (-d "$model_dir");
-	$full_path = "$confs_dir/$model_dir" if (-d "$confs_dir/$model_dir");
-	if (!defined  $full_path){
-		 die "Error the model directory  $model_dir or $confs_dir/$model_dir is not found\n";	
-	}
-	my @m;
-	if(scalar @models == 0){
-		@m = glob("$full_path/*");
-		return @m;
-	}
-	foreach my $p (@models) {
-		push (@m,"$full_path/$p");
-	}
-	return @m;
+    my ($mref,$inref) = @_;
+    my @models = @{$mref};
+    my ($paralel_run,$MIN,$MAX,$STEP,$model_dir)=@{$inref};
+    my $full_path;
+    $full_path = "$model_dir" if (-d "$model_dir");
+    $full_path = "$confs_dir/$model_dir" if (-d "$confs_dir/$model_dir");
+    if (!defined  $full_path){
+        die "Error the model directory  $model_dir or $confs_dir/$model_dir is not found\n";    
+    }
+    my @m;
+    if(scalar @models == 0){
+        @m = glob("$full_path/*");
+        return @m;
+    }
+    foreach my $p (@models) {
+        push (@m,"$full_path/$p");
+    }
+    return @m;
 }
 
-
 sub check_models_are_exsited {
-	my ($mref, $inref) = @_;
-	my @models = get_model_names(@_);
-	foreach my $m (@models){
-		unless (-f $m ){
-			die "Error: no such file $m";
-		}
-	}
+    my ($mref, $inref) = @_;
+    my @models = get_model_names(@_);
+    foreach my $m (@models){
+        unless (-f $m ){
+            die "Error: no such file $m";
+        }
+    }
 }
 
 
 sub gen_models {
-	my ($mref, $inref) = @_;
-	my @models = get_model_names(@_);	
-
+    my ($mref, $inref) = @_;
+    my @models = get_model_names(@_);
+    my ($paralel_run,$MIN,$MAX,$STEP,$model_dir,$flat) = @{$inref};
     mkdir("$work", 0700);
     $work=realpath($work);
-    
-	foreach my $m (@models){
-		print "$m\n";
-		unless (-f $m ){
-			die "Error: no such file $m";
-		}
-		#make noc localparam
-		my $o;
-		$o= do $m;
+    foreach my $m (@models){
+        print "$m\n";
+        unless (-f $m ){
+            die "Error: no such file $m";
+        }
+        #make noc localparam
+        my $o;
+        $o= do $m;
         die "Error reading: $@" if $@;
-		my $param = $o->{'noc_param'};
-		my ($fname,$fpath,$fsuffix) = fileparse("$m",qr"\..[^.]*$");
-
-
-		my $name = $fname;
-		my $make =$o->{'makefile'};
-		
-        
-		my 	($param_v,$include_h,$tops)=   gen_noc_localparam_v( $o,$param);
-
-		mkdir("$work/$name", 0700);
-		rmtree("$work/$name/obj_dir");
+        my $param = $o->{'noc_param'};
+        my ($fname,$fpath,$fsuffix) = fileparse("$m",qr"\..[^.]*$");
+        my $name = $fname;
+        my $make =$o->{'makefile'};
+        my ($param_v,$include_h,$tops)=   gen_noc_localparam_v($o,$param,$flat);
+        mkdir("$work/$name", 0700);
+        rmtree("$work/$name/obj_dir");
         mkdir("$work/$name/obj_dir", 0700);
-		save_file("$work/$name/noc_localparam.v",$param_v);
-		
-		#generate file list		
-		gen_file_list("$work/$name");
-		gen_verilator_sh($tops,"$work/$name/verilator.sh");
-
-		#copy C files
-		my @files = File::Find::Rule->file()
-                          ->name( '*.h' )
-                          ->in( "$src_verilator" );
-		foreach my $p (@files){
-			copy $p, "$work/$name/obj_dir/";
-		}
-		copy "$src_verilator/simulator.cpp", "$work/$name/obj_dir/testbench.cpp";
-
-		#copy nettrace & synful
-	    dircopy("$src_c/netrace-1.0","$work/$name/obj_dir/netrace-1.0");
-	    dircopy("$src_c/synfull","$work/$name/obj_dir/synful");
-
-		#generate make file
-		gen_verilator_makefile($tops,"$work/$name/obj_dir/Makefile");
-		#generate param.h file
-		
-	
-		save_file("$work/$name/obj_dir/parameter.h",$include_h);
-		
-		 
-	}
-
+        save_file("$work/$name/noc_localparam.v",$param_v);
+        
+        #generate file list
+        gen_file_list("$work/$name");
+        gen_verilator_sh($tops,"$work/$name/verilator.sh",$flat);
+        #copy C files
+        my @files = File::Find::Rule->file()
+            ->name( '*.h' )
+            ->in( "$src_verilator" );
+        foreach my $p (@files){
+            copy $p, "$work/$name/obj_dir/";
+        }
+        copy "$src_verilator/simulator.cpp", "$work/$name/obj_dir/testbench.cpp";
+        #copy nettrace & synful
+        dircopy("$src_c/netrace-1.0","$work/$name/obj_dir/netrace-1.0");
+        dircopy("$src_c/synfull","$work/$name/obj_dir/synful");
+        #generate make file
+        gen_verilator_makefile($tops,"$work/$name/obj_dir/Makefile");
+        #generate param.h file
+        save_file("$work/$name/obj_dir/parameter.h",$include_h);
+    }
 }
 
-
-
-
-
-
 sub compile_models{
-	my($self,$inref,$mref)=@_;
+    my($self,$inref,$mref)=@_;
     my ($paralel_run,$MIN,$MAX,$STEP) = @{$inref};
-	
-
-	my @models = get_model_names($mref,$inref);
-	
-	#generate compile command
-	my $i=0;
-	my $cmd;
-	foreach my $m (@models){
-		my ($fname,$fpath,$fsuffix) = fileparse("$m",qr"\..[^.]*$");
-		$cmd.=" cd $work/$fname;  bash verilator.sh >  $work/$fname/out.log 2>&1  &\n";
-		$i++;
-		$cmd.="wait\n" if(($i % $paralel_run)==0) ;
-	}
-	$cmd.="wait\n" if(($i % $paralel_run)!=0) ;
-	#run command in terminal
-	print "*******************compile models******************\n$cmd\n";
-	my $proc1 = Proc::Background->new($cmd);
-	$proc1->alive;
-	$proc1->wait;
-	$proc1->die;
-
+    my @models = get_model_names($mref,$inref);
+    #generate compile command
+    my $i=0;
+    my $cmd;
+    foreach my $m (@models){
+        my ($fname,$fpath,$fsuffix) = fileparse("$m",qr"\..[^.]*$");
+        $cmd.=" cd $work/$fname;  bash verilator.sh >  $work/$fname/out.log 2>&1  &\n";
+        $i++;
+        $cmd.="wait\n" if(($i % $paralel_run)==0) ;
+    }
+    $cmd.="wait\n" if(($i % $paralel_run)!=0) ;
+    #run command in terminal
+    print "*******************compile models******************\n$cmd\n";
+    my $proc1 = Proc::Background->new($cmd);
+    $proc1->alive;
+    $proc1->wait;
+    $proc1->die;
 }
+
 sub check_compilation_log {
-	my ($name,$ref,$inref) = @_;
+    my ($name,$ref,$inref,$log_file) = @_;
     my @log_report_match =@{$ref};
-	my ($paralel_run,$MIN,$MAX,$STEP) = @{$inref};
-	my $logfile	= "$work/$name/out.log";	
-	
-	my @found;
-	foreach my $m (@log_report_match){ 
-		open my $INPUT, '<', $logfile;
-		push(@found , grep ( /$m/, <$INPUT>)) ;
-		close($INPUT);
-	}	
-	
-	foreach my $line (@found) {
-              append_text_to_file($report,"\t $line\n");
+    my ($paralel_run,$MIN,$MAX,$STEP) = @{$inref};
+    my $logfile    = "$work/$name/out.log";
+    my @found;
+    foreach my $m (@log_report_match){ 
+        open my $INPUT, '<', $logfile;
+        push(@found , grep ( /$m/, <$INPUT>)) ;
+        close($INPUT);
+    }
+    foreach my $line (@found) {
+        append_text_to_file($log_file,"\t $line\n");
     }
 }
 
-
-
-
-
 sub check_compilation {
-	my ($self,$ref1,$inref,$mref)=@_;
-	
-	my @models = get_model_names($mref,$inref);
-
-	foreach my $m (@models){
-		my ($name,$fpath,$fsuffix) = fileparse("$m",qr"\..[^.]*$");
-		append_text_to_file($report,"****************************$name : Compile *******************************:\n");
-		#check if testbench is generated successfully	
-		if(-f "$work/$name/obj_dir/testbench"){
-			append_text_to_file($report,"\t model is generated successfully.\n"); 
-			check_compilation_log($name,$ref1,$inref);
-
-		}else{
-			append_text_to_file($report,"\t model generation is FAILED.\n"); 
-			check_compilation_log($name,$ref1,$inref);
-		}
-
-	}
+    my ($self,$ref1,$inref,$mref,$log_file)=@_;
+    my @models = get_model_names($mref,$inref);
+    foreach my $m (@models){
+        my ($name,$fpath,$fsuffix) = fileparse("$m",qr"\..[^.]*$");
+        append_text_to_file($log_file,"****************************$name : Compile *******************************:\n");
+        #check if testbench is generated successfully
+        if(-f "$work/$name/obj_dir/testbench"){
+            append_text_to_file($log_file,"\t model is generated successfully.\n"); 
+            check_compilation_log($name,$ref1,$inref,$log_file);
+        }else{
+            append_text_to_file($log_file,"\t model generation is FAILED.\n"); 
+            check_compilation_log($name,$ref1,$inref,$log_file);
+        }
+    }
 }
 
-
 sub run_all_models {
-	my ($self,$inref,$mref) =@_;
+    my ($self,$inref,$mref,$log_file) =@_;
     my ($paralel_run,$MIN,$MAX,$STEP) = @{$inref};
-	my @models = get_model_names($mref,$inref);	
+    my @models = get_model_names($mref,$inref);
     foreach my $m (@models){
-		run_traffic ($self,$m,'random',$inref);
-	}
-	foreach my $m (@models){
-		run_traffic ($self,$m,'transposed 1',$inref);
-	}
+        run_traffic ($self,$m,'random',$inref,$log_file);
+    }
+    foreach my $m (@models){
+        run_traffic ($self,$m,'transposed 1',$inref,$log_file);
+    }
 }
 
-
-
 sub run_traffic {
-	my ($self,$model,$traffic,$inref)=@_;
-     my ($paralel_run,$MIN,$MAX,$STEP) = @{$inref};
-	my ($name,$fpath,$fsuffix) = fileparse("$model",qr"\..[^.]*$");
-	
-	my %param = get_model_parameter($model);
-	my $min_pck = $param{'MIN_PCK_SIZE'};
-	
-    append_text_to_file($report,"****************************$name	: $traffic traffic *******************************:\n");
-	unless (-f "$work/$name/obj_dir/testbench"){
-		append_text_to_file($report,"\t Failed. Simulation model is not avaialable\n");
-		return;
-	}
-
-	
-
-	my $file_name="${traffic}_results";
+    my ($self,$model,$traffic,$inref,$log_file)=@_;
+    my ($paralel_run,$MIN,$MAX,$STEP) = @{$inref};
+    my ($name,$fpath,$fsuffix) = fileparse("$model",qr"\..[^.]*$");
+    my %param = get_model_parameter($model);
+    my $min_pck = $param{'MIN_PCK_SIZE'};
+    append_text_to_file($log_file,"****************************$name\t: $traffic traffic *******************************:\n");
+    unless (-f "$work/$name/obj_dir/testbench"){
+        append_text_to_file($log_file,"\t Failed. Simulation model is not avaialable\n");
+        return;
+    }
+    my $file_name="${traffic}_results";
     $file_name =~ s/\s+//g;
-
-	mkdir("$work/$name/$file_name/", 0700);
-
-	my $i=0;
-	my $cmd;
-
-
-	for (my $inject=$MIN; $inject<=$MAX; $inject+=$STEP){
-		$cmd.="$work/$name/obj_dir/testbench -t \"$traffic\"   -m \"R,$min_pck,10\"  -n  20000  -c	10000   -i $inject -p \"100,0,0,0,0\" >  $work/$name/$file_name/sim$inject 2>&1  &\n";
-		$i++;
-		$cmd.="wait\n" if(($i % $paralel_run)==0) ;
-	}
-	$cmd.="wait\n" if(($i % $paralel_run)!=0) ;
-	#run command in terminal
-	print "*******************Run simulation for $name******************\n$cmd\n";
-	my $proc1 = Proc::Background->new($cmd);
-	$proc1->alive;
-	$proc1->wait;
-	$proc1->die; 
-
-	check_sim_results($self,$name,$traffic,$inref);
-
+    mkdir("$work/$name/$file_name/", 0700);
+    my $i=0;
+    my $cmd;
+    for (my $inject=$MIN; $inject<=$MAX; $inject+=$STEP){
+        $cmd.="$work/$name/obj_dir/testbench -t \"$traffic\"   -m \"R,$min_pck,10\"  -n  20000  -c    10000   -i $inject -p \"100,0,0,0,0\" >  $work/$name/$file_name/sim$inject 2>&1  &\n";
+        $i++;
+        $cmd.="wait\n" if(($i % $paralel_run)==0) ;
+    }
+    $cmd.="wait\n" if(($i % $paralel_run)!=0) ;
+    #run command in terminal
+    print "*******************Run simulation for $name******************\n$cmd\n";
+    my $proc1 = Proc::Background->new($cmd);
+    $proc1->alive;
+    $proc1->wait;
+    $proc1->die; 
+    check_sim_results($self,$name,$traffic,$inref,$log_file);
 }
 
-
 sub extract_result {
-	my ($self,$file,$filed)=@_;
-
-	my @r = unix_grep($file,$filed);
+    my ($self,$file,$filed)=@_;
+    my @r = unix_grep($file,$filed);
     my $string = $r[0];
     $string =~ s/[^0-9.]+//g;
-	return $string;
-
+    return $string;
 }
 
 sub get_zero_load_and_saturation{
-	my ($self,$name,$traffic,$path)=@_;
-	my %results;	
-	my $ref = $self->{'name'}{"$name"}{'traffic'}{$traffic}{"packet_latency"};
-	return if !defined $ref;
-	%results = %{$ref}; 
-	
-	my $zero_latency=9999999;	
+    my ($self,$name,$traffic,$path)=@_;
+    my %results;
+    my $ref = $self->{'name'}{"$name"}{'traffic'}{$traffic}{"packet_latency"};
+    return if !defined $ref;
+    %results = %{$ref}; 
+    my $zero_latency=9999999;
     my $saturat_inject=100;
     my $zero_inject;
     my $saturat_latency='-';
-
-	my $txt = "#name:$name\n";
-
-	foreach my $inj (sort {$a <=> $b} keys %results){
-		$txt.="$inj $results{$inj}\n";
-		if ($zero_latency > $results{$inj}) {
-			$zero_latency = $results{$inj};
-			$zero_inject  = $inj;
-		}
-	} 
-	# assum saturation happens when the latency is 5 times of zero load
-	foreach my $inj (sort {$a <=> $b} keys %results){
-		if($results{$inj} >= 5 * $zero_latency ) {
-			if($saturat_inject > $inj){
-				$saturat_inject	=$inj;	
-				$saturat_latency=$results{$inj};
-			}
-		}
-	} 
-	$txt.="\n";
-	save_file("$path/packet_latency.sv",$txt);
-
-
-	return ($zero_inject,$zero_latency, $saturat_inject,$saturat_latency);
+    my $txt = "#name:$name\n";
+    foreach my $inj (sort {$a <=> $b} keys %results){
+        $txt.="$inj $results{$inj}\n";
+        if ($zero_latency > $results{$inj}) {
+            $zero_latency = $results{$inj};
+            $zero_inject  = $inj;
+        }
+    } 
+    # assum saturation happens when the latency is 5 times of zero load
+    foreach my $inj (sort {$a <=> $b} keys %results){
+        if($results{$inj} >= 5 * $zero_latency ) {
+            if($saturat_inject > $inj){
+                $saturat_inject    =$inj;
+                $saturat_latency=$results{$inj};
+            }
+        }
+    } 
+    $txt.="\n";
+    save_file("$path/packet_latency.sv",$txt);
+    return ($zero_inject,$zero_latency, $saturat_inject,$saturat_latency);
 }
 
-
-
-
 sub check_sim_results{
-	my ($self,$name,$traffic,$inref)=@_;
+    my ($self,$name,$traffic,$inref,$log_file)=@_;
     my ($paralel_run,$MIN,$MAX,$STEP) = @{$inref};
     my $file_name="${traffic}_results";
     $file_name =~ s/\s+//g;
-	my $results_path = "$work/$name/$file_name";
-
-	#my @results = glob("$results_path/*");
-	#check for error
-	
-	for (my $inject=$MIN; $inject<=$MAX; $inject+=$STEP){
-		my $file = "$results_path/sim$inject";
-	
-		my @errors = unix_grep("$file","ERROR:");
-		if (scalar @errors  ){
-			append_text_to_file($report,"\t Error in running simulation: @errors \n");	
-			$self->{'name'}{"$name"}{'traffic'}{$traffic}{'overal_result'}="Failed";
-			$self->{'name'}{"$name"}{'traffic'}{$traffic}{'message'}="@errors";
-			return;						
-		}
-		my @r = unix_grep($file,"\ttotal,");
-    	my $string = $r[0];
-		my @fileds=split(',',$string);
-		my $val=$fileds[11];
-		$val =~ s/[^0-9.]+//g;
-	#	my $val = extract_result($self,$file,"average packet latency");		
-		if(length $val ==0){
-			$self->{'name'}{"$name"}{'traffic'}{$traffic}{'overal_result'}="Failed";
-			$self->{'name'}{"$name"}{'traffic'}{$traffic}{'message'}="The average packet latency is undefined for $inject";
-			return;						
-		}
-		$self->{'name'}{"$name"}{'traffic'}{$traffic}{"packet_latency"}{$inject}="$val";
-		
-	}
-	my  ($z,$zl, $s,$sl) = get_zero_load_and_saturation ($self,$name,$traffic,$results_path);
-	print "($z,$zl, $s,$sl)\n";
-
-	#save results in a text file 
-
-
-
-	append_text_to_file($report,"\t Passed:   zero load ($z,$zl) saturation ($s,$sl)\n");
-    $self->{'name'}{"$name"}{'traffic'}{$traffic}{'overal_result'}="passed";		
+    my $results_path = "$work/$name/$file_name";
+    #my @results = glob("$results_path/*");
+    #check for error
+    for (my $inject=$MIN; $inject<=$MAX; $inject+=$STEP){
+        my $file = "$results_path/sim$inject";
+        my @errors = unix_grep("$file","ERROR:");
+        if (scalar @errors  ){
+            append_text_to_file($log_file,"\t Error in running simulation:\n @errors \n");    
+            $self->{'name'}{"$name"}{'traffic'}{$traffic}{'overal_result'}="Failed";
+            $self->{'name'}{"$name"}{'traffic'}{$traffic}{'message'}="@errors";
+            return;
+        }
+        my @r = unix_grep($file,"\ttotal,");
+        my $string = $r[0];
+        my @fileds=split(',',$string);
+        my $val=$fileds[11];
+        $val =~ s/[^0-9.]+//g;
+        #    my $val = extract_result($self,$file,"average packet latency");
+        if(length $val ==0){
+            $self->{'name'}{"$name"}{'traffic'}{$traffic}{'overal_result'}="Failed";
+            $self->{'name'}{"$name"}{'traffic'}{$traffic}{'message'}="The average packet latency is undefined for $inject";
+            return;
+        }
+        $self->{'name'}{"$name"}{'traffic'}{$traffic}{"packet_latency"}{$inject}="$val";
+        
+    }
+    my  ($z,$zl, $s,$sl) = get_zero_load_and_saturation ($self,$name,$traffic,$results_path);
+    print "($z,$zl, $s,$sl)\n";
+    #save results in a text file 
+    append_text_to_file($log_file,"\t Passed:   zero load ($z,$zl) saturation ($s,$sl)\n");
+    $self->{'name'}{"$name"}{'traffic'}{$traffic}{'overal_result'}="passed";
 }
 
-
 sub object_get_attribute_order{
-	my ($self,$attribute)=@_;
-	return unless(defined $self->{parameters_order}{$attribute});
-	my @order=@{$self->{parameters_order}{$attribute}};
-	return uniq(@order)
+    my ($self,$attribute)=@_;
+    return unless(defined $self->{parameters_order}{$attribute});
+    my @order=@{$self->{parameters_order}{$attribute}};
+    return uniq(@order)
 }
 
 sub save_file {
-	my  ($file_path,$text)=@_;
-	open my $fd, ">$file_path" or die "could not open $file_path: $!";
-	print $fd $text;
-	close $fd;	
+    my  ($file_path,$text)=@_;
+    open my $fd, ">$file_path" or die "could not open $file_path: $!";
+    print $fd $text;
+    close $fd;
 }
 
 sub object_add_attribute_order{
-	my ($self,$attribute,@param)=@_;
-	my $r = $self->{'parameters_order'}{$attribute};
-	my @a;
-	@a = @{$r} if(defined $r);
-	push (@a,@param);
-	@a=uniq(@a);	
-	$self->{'parameters_order'}{$attribute} =\@a;
+    my ($self,$attribute,@param)=@_;
+    my $r = $self->{'parameters_order'}{$attribute};
+    my @a;
+    @a = @{$r} if(defined $r);
+    push (@a,@param);
+    @a=uniq(@a);
+    $self->{'parameters_order'}{$attribute} =\@a;
 }
 
 sub append_text_to_file {
-	my  ($file_path,$text)=@_;
-	open(my $fd, ">>$file_path") or die "could not open $file_path: $!";
-	print $fd $text;
-	close $fd;
+    my  ($file_path,$text)=@_;
+    open(my $fd, ">>$file_path") or die "could not open $file_path: $!";
+    print $fd $text;
+    close $fd;
 }
 
 sub object_add_attribute{
-	my ($self,$attribute1,$attribute2,$value)=@_;
-	if(!defined $attribute2){$self->{$attribute1}=$value;}
-	else {$self->{$attribute1}{$attribute2}=$value;}
+    my ($self,$attribute1,$attribute2,$value)=@_;
+    if(!defined $attribute2){$self->{$attribute1}=$value;}
+    else {$self->{$attribute1}{$attribute2}=$value;}
 
 }
 
-
-
 sub object_get_attribute{
-	my ($self,$attribute1,$attribute2)=@_;
-	if(!defined $attribute2) {return $self->{$attribute1};}
-	return $self->{$attribute1}{$attribute2};
+    my ($self,$attribute1,$attribute2)=@_;
+    if(!defined $attribute2) {return $self->{$attribute1};}
+    return $self->{$attribute1}{$attribute2};
 }
 
 sub powi{ # x^y
-	my ($x,$y)=@_; # compute x to the y
-	my $r=1;
-	for (my $i = 0; $i < $y; ++$i ) {
-    	$r *= $x;
-  	}
-  return $r;
+    my ($x,$y)=@_; # compute x to the y
+    my $r=1;
+    for (my $i = 0; $i < $y; ++$i ) {
+        $r *= $x;
+    }
+    return $r;
 }
 
 sub sum_powi{ # x^(y-1) + x^(y-2) + ...+ 1;
-	my ($x,$y)=@_; # compute x to the y
-	my $r = 0;
+    my ($x,$y)=@_; # compute x to the y
+    my $r = 0;
     for (my $i = 0; $i < $y; $i++){
-    	$r += powi( $x, $i );
+        $r += powi( $x, $i );
     }
-  	return $r;
-}	
+    return $r;
+}
 
 sub log2{
-	my $num=shift;
-	my $log=($num <=1) ? 1: 0;        
-	while( (1<< $log)  < $num) {    
-				$log++;    
-	}
-	return  $log;  
+    my $num=shift;
+    my $log=($num <=1) ? 1: 0;
+    while( (1<< $log)  < $num) {
+                $log++;
+    }
+    return  $log;
 }
 
-
 sub remove_not_hex {
-	my $s=shift;
-	$s =~ s/[^0-9a-fA-F]//g;
-	return $s;	
+    my $s=shift;
+    $s =~ s/[^0-9a-fA-F]//g;
+    return $s;
 }
 
 sub remove_not_number {
-	my $s=shift;
-	$s =~ s/[^0-9]//g;
-	return $s;		
-	
+    my $s=shift;
+    $s =~ s/[^0-9]//g;
+    return $s;
+    
 }
 
 sub check_file_has_string {
@@ -743,51 +652,46 @@ sub check_file_has_string {
     my $r;
     open(FILE,$file);
     if (grep{/$string/} <FILE>){
-       $r= 1; #print "word  found\n";
+        $r= 1; #print "word  found\n";
     }else{
-       $r= 0; #print "word not found\n";
+        $r= 0; #print "word not found\n";
     }
     close FILE;
     return $r;
 }
 
-
 sub gen_verilator_makefile{
-	my ($top_ref,$target_dir) =@_;
-	my %tops = %{$top_ref};
-	my $p='';
-	my $q='';
-	my $h='';
-	my $l;
-	my $lib_num=0;
-	my $all_lib="";
-	foreach my $top (sort keys %tops) {
-		$p = "$p ${top}__ALL.a ";
-		$q = $q."lib$lib_num:\n\t\$(MAKE) -f ${top}.mk\n"; 
-		$h = "$h ${top}.h "; 
-		$l = $top;
-		$all_lib=$all_lib." lib$lib_num";
-		$lib_num++;
-	}
-
-	my $make= "
-	
+    my ($top_ref,$target_dir) =@_;
+    my %tops = %{$top_ref};
+    my $p='';
+    my $q='';
+    my $h='';
+    my $l;
+    my $lib_num=0;
+    my $all_lib="";
+    foreach my $top (sort keys %tops) {
+        $p = "$p ${top}__ALL.a ";
+        $q = $q."lib$lib_num:\n\t\$(MAKE) -f ${top}.mk\n"; 
+        $h = "$h ${top}.h "; 
+        $l = $top;
+        $all_lib=$all_lib." lib$lib_num";
+        $lib_num++;
+    }
+    my $make= "
+    
 default: sim
 
-
-
 include $l.mk
 
 lib: $all_lib
 
 $q
 
-
 #######################################################################
 # Compile flags
 
 CPPFLAGS += -DVL_DEBUG=1
-ifeq (\$(CFG_WITH_CCWARN),yes)	# Local... Else don't burden users
+ifeq (\$(CFG_WITH_CCWARN),yes)\t# Local... Else don't burden users
 CPPFLAGS += -DVL_THREADED=1
 CPPFLAGS += -W -Werror -Wall
 endif
@@ -803,51 +707,52 @@ sub gen_verilator_makefile{
 # Linking final exe -- presumes have a sim_main.cpp
 
 
-sim:	testbench.o \$(VK_GLOBAL_OBJS) $p \$(SLIB)
-	\$(LINK) \$(LDFLAGS) -g \$^ \$(LOADLIBES) \$(LDLIBS) -o testbench \$(LIBS) -Wall -O3 -lpthread 2>&1 | c++filt
+sim:\ttestbench.o \$(VK_GLOBAL_OBJS) $p \$(SLIB)
+\t\$(LINK) \$(LDFLAGS) -g \$^ \$(LOADLIBES) \$(LDLIBS) -o testbench \$(LIBS) -Wall -O3 -lpthread 2>&1 | c++filt
+
+sim_flat:\tCPPFLAGS += -DFLAT_MODE
+sim_flat:\ttestbench.o \$(VK_GLOBAL_OBJS)  $p \$(SLIB)
+\t\$(LINK) \$(LDFLAGS) -g \$^ \$(LOADLIBES) \$(LDLIBS) -o testbench \$(LIBS) -Wall -O3 -lpthread 2>&1 | c++filt
 
 testbench.o: testbench.cpp $h  \$(HLIB)
 
 clean:
-	rm *.o *.a testbench	
+\trm *.o *.a testbench
 ";
 
-save_file ($target_dir,$make);
-
-}	
+    save_file ($target_dir,$make);
+}
 
 
 sub get_project_dir{ #mpsoc directory address
-	my $dir = Cwd::getcwd();
-	my @p=	split('/perl_gui',$dir);
-	@p=	split('/Integration_test',$p[0]);
-    my $d	  = abs_path("$p[0]/../"); 
-     
-	return $d;
+    my $dir = Cwd::getcwd();
+    my @p=    split('/perl_gui',$dir);
+    @p=    split('/Integration_test',$p[0]);
+    my $d      = abs_path("$p[0]/../"); 
+    return $d;
 }
 
 #return lines containig pattern in a givn file
 sub unix_grep {
-	my ($file,$pattern)=@_;
+    my ($file,$pattern)=@_;
     open(FILE,$file);
     my @arr = <FILE>;
     my @lines = grep /$pattern/, @arr;
-	return @lines;	
+    return @lines;
 }
 
-
 sub regen_object {
-	my $path=shift;
-	$path = get_full_path_addr($path);
-	my $pp= eval { do $path };
-	my $r= ($@ || !defined $pp);
-	return ($pp,$r,$@);
+    my $path=shift;
+    $path = get_full_path_addr($path);
+    my $pp= eval { do $path };
+    my $r= ($@ || !defined $pp);
+    return ($pp,$r,$@);
 }
 
 sub get_full_path_addr{
-	my $file=shift;
-	my $dir = Cwd::getcwd();
-	my $full_path = "$dir/$file";	
-	return $full_path  if -f ($full_path );
-	return $file;
+    my $file=shift;
+    my $dir = Cwd::getcwd();
+    my $full_path = "$dir/$file";
+    return $full_path  if -f ($full_path );
+    return $file;
 }
diff --git a/mpsoc/Integration_test/synthetic_sim/src/verify.perl b/mpsoc/Integration_test/synthetic_sim/src/verify.perl
index 8dcaac3..5e978b4 100755
--- a/mpsoc/Integration_test/synthetic_sim/src/verify.perl
+++ b/mpsoc/Integration_test/synthetic_sim/src/verify.perl
@@ -19,7 +19,7 @@ package ProNOC;
 use lib $FindBin::Bin;
 use constant::boolean;
 
-
+use File::Path qw(make_path);
 
 
 use strict;
@@ -31,7 +31,7 @@ package ProNOC;
 
 # declare the perl command line flags/options we want to allow
 my %options=();
-getopts("hp:u:l:s:m:d:", \%options);
+getopts("hp:u:l:s:m:d:f", \%options);
 
 # test for the existence of the options on the command line.
 # in a normal program you'd do more than just print these.
@@ -55,6 +55,9 @@ package ProNOC;
       -l <int number>  : Enter the minimum injection ratio in %. Default is 5
       -s <int number>  : Enter the injection step increase ratio in %.
                          Default value is 25.
+      -f               : Enable flat mode. Use NoC_top as the Verilator top module.
+                         If not set, Verilator will be run on internal router modules
+                         and they will be connected manually in testbench.c.
       -d <dir name>    : The dir name where the simulation models configuration
                          files are located in. The default dir is \"models\"
       -m <simulation model name1,simulation model name2,...> : Enter the
@@ -79,6 +82,7 @@ package ProNOC;
 $MIN = $options{l} if defined $options{l};
 $STEP = $options{s} if defined $options{s};
 $model_dir = $options{d} if defined $options{d};
+my $flat= (defined $options{f}) ? 1 : 0;
 
 if (defined $options{m}){
     @models = split(",",$options{m});
@@ -99,14 +103,14 @@ package ProNOC;
 
 
 
-my $dirname = dirname(__FILE__);
-require "$dirname/src.pl";
+my $script_path = dirname(__FILE__);
+require "$script_path/src.pl";
 
 
-my @inputs =($paralel_run,$MIN,$MAX,$STEP,$model_dir);
+my @inputs =($paralel_run,$MIN,$MAX,$STEP,$model_dir,$flat);
 
 
-print "Maximum number of parallel simulation is $paralel_run.\n The injection ratio is set as MIN=$MIN,MAX=$MAX,STEP=$STEP.\n";
+print "Maximum number of parallel simulation is $paralel_run.\n The injection ratio is set as MIN=$MIN,MAX=$MAX,STEP=$STEP, flat_mode=$flat.\n";
 print "\t The simulation models are taken from $model_dir\n";
 if (defined $options{m}){
     foreach my $p (@models ){
@@ -114,12 +118,24 @@ package ProNOC;
     }
 }
 
+
+my $dirname = realpath("$script_path/..");
+my $log_dir ="${dirname}/result_logs";
+my $log_file="${log_dir}/$model_dir";
+
+unless (-d "$log_dir") {
+    print "Creating working directory inside $log_dir\n";
+    mkdir("$log_dir", 0700) or die "Failed to create directory $log_dir: $!";
+}
+
+
+
 check_models_are_exsited(\@models,\@inputs);
 
-my @log_report_match =("Error","Warning" );
+my @log_report_match =("Error","Warning","fatal error","error:" );
 
 
-save_file ("$dirname/../report","Verification Results:\n");
+save_file ("$log_file","Verification Results:\n");
 
 recompile_synful();
 
@@ -129,9 +145,9 @@ package ProNOC;
 
 compile_models($app,\@inputs,\@models);
 
-check_compilation($app,\@log_report_match,\@inputs,\@models);
+check_compilation($app,\@log_report_match,\@inputs,\@models,$log_file);
 
-run_all_models($app,\@inputs,\@models);
+run_all_models($app,\@inputs,\@models,$log_file);
 
 
 
diff --git a/mpsoc/Integration_test/verilator_lint/configurations/Fattree_k3_L3_st b/mpsoc/Integration_test/verilator_lint/configurations/Fattree_k3_L3_st
new file mode 100644
index 0000000..e8816f6
--- /dev/null
+++ b/mpsoc/Integration_test/verilator_lint/configurations/Fattree_k3_L3_st
@@ -0,0 +1,9 @@
+$model = bless( {
+    'noc_param'=> {
+        "TOPOLOGY" => "\"FATTREE\"",
+        "T1" => "3",
+        "T2" => "3",
+        "B"  => "5",
+        "ROUTE_NAME" => "\"NCA_STRAIGHT_UP\"",
+    }
+}, 'ProNOC' );
diff --git a/mpsoc/Integration_test/verilator_lint/configurations/bintree_k3_L3_st b/mpsoc/Integration_test/verilator_lint/configurations/bintree_k3_L3_st
new file mode 100644
index 0000000..85fc4b5
--- /dev/null
+++ b/mpsoc/Integration_test/verilator_lint/configurations/bintree_k3_L3_st
@@ -0,0 +1,9 @@
+$model = bless( {
+    'noc_param'=> {
+        "TOPOLOGY" => "\"TREE\"",
+        "T1" => "3",
+        "T2" => "3",
+        "B"  => "5",
+        "ROUTE_NAME" => "\"NCA\"",
+    }
+}, 'ProNOC' );
diff --git a/mpsoc/Integration_test/verilator_lint/configurations/custom1_topology b/mpsoc/Integration_test/verilator_lint/configurations/custom1_topology
new file mode 100644
index 0000000..8b17d0e
--- /dev/null
+++ b/mpsoc/Integration_test/verilator_lint/configurations/custom1_topology
@@ -0,0 +1,10 @@
+$model = bless( {
+    'noc_param'=> {
+    "TOPOLOGY"=>"\"custom1\"",
+        "CUSTOM_TOPOLOGY_NAME"=>"\"custom1\"",
+        "T1" => "16",
+        "T2" => "16",
+        "T3" => "5",
+        "ROUTE_NAME" =>"\"custom\""
+    }
+}, 'ProNOC' );
\ No newline at end of file
diff --git a/mpsoc/Integration_test/verilator_lint/configurations/fmesh_1x1_openpiton b/mpsoc/Integration_test/verilator_lint/configurations/fmesh_1x1_openpiton
new file mode 100644
index 0000000..f80a7c7
--- /dev/null
+++ b/mpsoc/Integration_test/verilator_lint/configurations/fmesh_1x1_openpiton
@@ -0,0 +1,15 @@
+$model = bless( {
+    'noc_param'=> {
+        "TOPOLOGY"=> "\"FMESH\"",
+        "T1" => "1",
+        "T2" => "1",
+        "V" => "1",
+        "ESCAP_VC_MASK" => "1'b1",
+        "B" => "4",
+        "LB" => "16",
+        "Fpay" => "64",
+        "SSA_EN" => "1",
+        "SELF_LOOP_EN" => "1",
+        "MIN_PCK_SIZE" => "1"
+    }
+}, 'ProNOC' );
\ No newline at end of file
diff --git a/mpsoc/Integration_test/verilator_lint/configurations/fmesh_2x2_openpiton b/mpsoc/Integration_test/verilator_lint/configurations/fmesh_2x2_openpiton
new file mode 100644
index 0000000..449f321
--- /dev/null
+++ b/mpsoc/Integration_test/verilator_lint/configurations/fmesh_2x2_openpiton
@@ -0,0 +1,14 @@
+$model = bless( {
+    'noc_param'=> {
+        "TOPOLOGY"=> "\"FMESH\"",
+        "T1" => "2",
+        "T2" => "2",
+        "V" => "1",
+        "ESCAP_VC_MASK" => "1'b1",
+        "B" => "4",
+        "LB" => "16",
+        "Fpay" => "64",
+        "SSA_EN" => "1",
+        "SELF_LOOP_EN" => "1",
+    }
+}, 'ProNOC' );
\ No newline at end of file
diff --git a/mpsoc/Integration_test/verilator_lint/configurations/fmesh_8x8_2cycle_xy b/mpsoc/Integration_test/verilator_lint/configurations/fmesh_8x8_2cycle_xy
new file mode 100644
index 0000000..12a13c3
--- /dev/null
+++ b/mpsoc/Integration_test/verilator_lint/configurations/fmesh_8x8_2cycle_xy
@@ -0,0 +1,6 @@
+$model = bless( {
+    'noc_param'=> {
+        "TOPOLOGY" => "\"FMESH\"",
+        "ROUTE_NAME" => "\"DOR\"",
+    }
+}, 'ProNOC' );
\ No newline at end of file
diff --git a/mpsoc/Integration_test/verilator_lint/configurations/fmesh_8x8_openpiton b/mpsoc/Integration_test/verilator_lint/configurations/fmesh_8x8_openpiton
new file mode 100644
index 0000000..37c19a2
--- /dev/null
+++ b/mpsoc/Integration_test/verilator_lint/configurations/fmesh_8x8_openpiton
@@ -0,0 +1,14 @@
+$model = bless( {
+    'noc_param'=> {
+        "TOPOLOGY"=> "\"FMESH\"",
+        "T1" => "8",
+        "T2" => "8",
+        "V" => "1",
+        "ESCAP_VC_MASK" => "1'b1",
+        "B" => "4",
+        "LB" => "16",
+        "Fpay" => "64",
+        "SSA_EN" => "1",
+        "SELF_LOOP_EN" => "1",
+    }
+}, 'ProNOC' );
\ No newline at end of file
diff --git a/mpsoc/Integration_test/verilator_lint/configurations/line4_smart3 b/mpsoc/Integration_test/verilator_lint/configurations/line4_smart3
new file mode 100644
index 0000000..548c123
--- /dev/null
+++ b/mpsoc/Integration_test/verilator_lint/configurations/line4_smart3
@@ -0,0 +1,16 @@
+$model = bless( {
+    'noc_param'=> {
+        "SMART_MAX" => "3",
+        TOPOLOGY=>"\"LINE\"",
+        "T1" => "4",
+        "T2" => "4",
+        "V" => "1",
+        "ESCAP_VC_MASK" => "1'b1",
+        "B" => "4",
+        "LB" => "16",
+        "Fpay" => "64",
+        "SSA_EN" => "0",
+        "SELF_LOOP_EN" => "1",
+        "MCAST_ENDP_LIST" => "'b11",
+    }
+}, 'ProNOC' );
\ No newline at end of file
diff --git a/mpsoc/Integration_test/verilator_lint/configurations/line_4_v1_B15 b/mpsoc/Integration_test/verilator_lint/configurations/line_4_v1_B15
new file mode 100644
index 0000000..5d00709
--- /dev/null
+++ b/mpsoc/Integration_test/verilator_lint/configurations/line_4_v1_B15
@@ -0,0 +1,14 @@
+$model = bless( {
+    'noc_param'=> {
+        TOPOLOGY=>"\"LINE\"",
+        "T1" => "4",
+        "T2" => "4",
+        "V" => "1",
+        "ESCAP_VC_MASK" => "1'b1",
+        "B" => "15",
+        "LB" => "15",
+        "Fpay" => "64",
+        "SSA_EN" => "0",
+        "SELF_LOOP_EN" => "0",
+    }
+}, 'ProNOC' );
\ No newline at end of file
diff --git a/mpsoc/Integration_test/verilator_lint/configurations/line_8_single_flit b/mpsoc/Integration_test/verilator_lint/configurations/line_8_single_flit
new file mode 100644
index 0000000..a73600b
--- /dev/null
+++ b/mpsoc/Integration_test/verilator_lint/configurations/line_8_single_flit
@@ -0,0 +1,9 @@
+$model = bless( {
+    'noc_param'=> {
+        TOPOLOGY=>"\"LINE\"",
+        "B" => "5",
+        "LB" => "5",
+        "MIN_PCK_SIZE" => "1",
+        "PCK_TYPE" => "  \"SINGLE_FLIT\"",
+    }
+}, 'ProNOC' );
\ No newline at end of file
diff --git a/mpsoc/Integration_test/verilator_lint/configurations/mesh_2x2_openpiton b/mpsoc/Integration_test/verilator_lint/configurations/mesh_2x2_openpiton
new file mode 100644
index 0000000..4b61b2e
--- /dev/null
+++ b/mpsoc/Integration_test/verilator_lint/configurations/mesh_2x2_openpiton
@@ -0,0 +1,13 @@
+$model = bless( {
+    'noc_param'=> {
+        "T1" => "2",
+        "T2" => "2",
+        "V" => "1",
+        "ESCAP_VC_MASK" => "1'b1",
+        "B" => "4",
+        "LB" => "16",
+        "Fpay" => "64",
+        "SSA_EN" => "1",
+        "SELF_LOOP_EN" => "1",
+    }
+}, 'ProNOC' );
\ No newline at end of file
diff --git a/mpsoc/Integration_test/verilator_lint/configurations/mesh_3x3_v2_ssa b/mpsoc/Integration_test/verilator_lint/configurations/mesh_3x3_v2_ssa
new file mode 100644
index 0000000..1383775
--- /dev/null
+++ b/mpsoc/Integration_test/verilator_lint/configurations/mesh_3x3_v2_ssa
@@ -0,0 +1,12 @@
+$model = bless( {
+    'noc_param'=> {
+        "T1" => "3",
+        "T2" => "3",
+        "SELF_LOOP_EN" => "1",
+        "SSA_EN"=> "1",
+        "LB" => 16,
+        "DEBUG_EN" => "0",   
+        "MIN_PCK_SIZE"  => "1", 
+        "Fpay" => "64",   
+    }
+}, 'ProNOC' );
diff --git a/mpsoc/Integration_test/verilator_lint/configurations/mesh_4x4_2cycle_mcast_f b/mpsoc/Integration_test/verilator_lint/configurations/mesh_4x4_2cycle_mcast_f
new file mode 100644
index 0000000..975dea2
--- /dev/null
+++ b/mpsoc/Integration_test/verilator_lint/configurations/mesh_4x4_2cycle_mcast_f
@@ -0,0 +1,8 @@
+$model = bless( {
+    'noc_param'=> {
+        "T1" => "4",
+        "T2" => "4",
+        "CAST_TYPE" => "\"MULTICAST_FULL\"",
+        "Fpay" => "64"
+    }
+}, 'ProNOC' );
diff --git a/mpsoc/Integration_test/verilator_lint/configurations/mesh_4x4_LB5_B4 b/mpsoc/Integration_test/verilator_lint/configurations/mesh_4x4_LB5_B4
new file mode 100644
index 0000000..50ac90c
--- /dev/null
+++ b/mpsoc/Integration_test/verilator_lint/configurations/mesh_4x4_LB5_B4
@@ -0,0 +1,12 @@
+$model = bless( {
+    'noc_param'=> {
+        "T1" => "4",
+        "T2" => "4",
+        "B"  => "4",
+        "LB" => "5",
+        "CAST_TYPE" => "\"MULTICAST_PARTIAL\"",
+        "MCAST_ENDP_LIST" => "16'b110011000111101",
+        "Fpay" => "64",
+        "SELF_LOOP_EN" => "1"
+    }
+}, 'ProNOC' );
\ No newline at end of file
diff --git a/mpsoc/Integration_test/verilator_lint/configurations/mesh_4x4_selflp_mcast_f b/mpsoc/Integration_test/verilator_lint/configurations/mesh_4x4_selflp_mcast_f
new file mode 100644
index 0000000..5c5852e
--- /dev/null
+++ b/mpsoc/Integration_test/verilator_lint/configurations/mesh_4x4_selflp_mcast_f
@@ -0,0 +1,9 @@
+$model = bless( {
+    'noc_param'=> {
+        "T1" => "4",
+        "T2" => "4",
+        "CAST_TYPE" => "\"MULTICAST_FULL\"",
+        "Fpay" => "64",
+        "SELF_LOOP_EN" => "1"
+    }
+}, 'ProNOC' );
\ No newline at end of file
diff --git a/mpsoc/Integration_test/verilator_lint/configurations/mesh_4x4_smart3 b/mpsoc/Integration_test/verilator_lint/configurations/mesh_4x4_smart3
new file mode 100644
index 0000000..ad8749e
--- /dev/null
+++ b/mpsoc/Integration_test/verilator_lint/configurations/mesh_4x4_smart3
@@ -0,0 +1,15 @@
+$model = bless( {
+    'noc_param'=> {
+        "SMART_MAX" => "3",
+        "TOPOLOGY"=> "\"FMESH\"",
+        "T1" => "4",
+        "T2" => "4",
+        "V" => "1",
+        "ESCAP_VC_MASK" => "1'b1",
+        "B" => "4",
+        "LB" => "16",
+        "Fpay" => "64",
+        "SSA_EN" => "0",
+        "SELF_LOOP_EN" => "1",
+    }
+}, 'ProNOC' );
\ No newline at end of file
diff --git a/mpsoc/Integration_test/verilator_lint/configurations/mesh_4x4_v1_B15 b/mpsoc/Integration_test/verilator_lint/configurations/mesh_4x4_v1_B15
new file mode 100644
index 0000000..a07a491
--- /dev/null
+++ b/mpsoc/Integration_test/verilator_lint/configurations/mesh_4x4_v1_B15
@@ -0,0 +1,13 @@
+$model = bless( {
+    'noc_param'=> {
+        "T1" => "4",
+        "T2" => "4",
+        "V" => "1",
+        "ESCAP_VC_MASK" => "1'b1",
+        "B" => "15",
+        "LB" => "15",
+        "Fpay" => "64",
+        "SSA_EN" => "0",
+        "SELF_LOOP_EN" => "0",
+    }
+}, 'ProNOC' );
\ No newline at end of file
diff --git a/mpsoc/Integration_test/verilator_lint/configurations/mesh_4x4x2_bcast_f b/mpsoc/Integration_test/verilator_lint/configurations/mesh_4x4x2_bcast_f
new file mode 100644
index 0000000..dc24a2f
--- /dev/null
+++ b/mpsoc/Integration_test/verilator_lint/configurations/mesh_4x4x2_bcast_f
@@ -0,0 +1,10 @@
+$model = bless( {
+    'noc_param'=> {
+        "T1" => "4",
+        "T2" => "4",
+        "T3" => "2",
+        "CAST_TYPE" => "\"BROADCAST_FULL\"",
+        "MCAST_ENDP_LIST" => "32'b1100110001111",
+        "Fpay" => "64"
+    }
+}, 'ProNOC' );
\ No newline at end of file
diff --git a/mpsoc/Integration_test/verilator_lint/configurations/mesh_4x4x2_bcast_p b/mpsoc/Integration_test/verilator_lint/configurations/mesh_4x4x2_bcast_p
new file mode 100644
index 0000000..23c4749
--- /dev/null
+++ b/mpsoc/Integration_test/verilator_lint/configurations/mesh_4x4x2_bcast_p
@@ -0,0 +1,10 @@
+$model = bless( {
+    'noc_param'=> {
+        "T1" => "4",
+        "T2" => "4",
+        "T3" => "2",
+        "CAST_TYPE" => "\"BROADCAST_PARTIAL\"",
+        "MCAST_ENDP_LIST" => "32'b1100110001111",
+        "Fpay" => "64"
+    }
+}, 'ProNOC' );
\ No newline at end of file
diff --git a/mpsoc/Integration_test/verilator_lint/configurations/mesh_4x4x2_mcast_p b/mpsoc/Integration_test/verilator_lint/configurations/mesh_4x4x2_mcast_p
new file mode 100644
index 0000000..ad2854b
--- /dev/null
+++ b/mpsoc/Integration_test/verilator_lint/configurations/mesh_4x4x2_mcast_p
@@ -0,0 +1,10 @@
+$model = bless( {
+    'noc_param'=> {
+        "T1" => "4",
+        "T2" => "4",
+        "T3" => "2",
+        "CAST_TYPE" => "\"MULTICAST_PARTIAL\"",
+        "MCAST_ENDP_LIST" => "32'b1100110001111",
+        "Fpay" => "64"
+    }
+}, 'ProNOC' );
\ No newline at end of file
diff --git a/mpsoc/Integration_test/verilator_lint/configurations/mesh_4x4x3_2cycle_xy b/mpsoc/Integration_test/verilator_lint/configurations/mesh_4x4x3_2cycle_xy
new file mode 100644
index 0000000..ee47bc2
--- /dev/null
+++ b/mpsoc/Integration_test/verilator_lint/configurations/mesh_4x4x3_2cycle_xy
@@ -0,0 +1,9 @@
+$model = bless( {
+    'noc_param'=> {
+        "T1" => "4",
+        "T2" => "4",
+        "T3" => "3",
+        "TOPOLOGY" => "\"MESH\"",
+        "ROUTE_NAME" => "\"DOR\"",
+    }
+}, 'ProNOC' );
\ No newline at end of file
diff --git a/mpsoc/Integration_test/verilator_lint/configurations/mesh_4x4x3_vc_nonspec b/mpsoc/Integration_test/verilator_lint/configurations/mesh_4x4x3_vc_nonspec
new file mode 100644
index 0000000..6bb1a40
--- /dev/null
+++ b/mpsoc/Integration_test/verilator_lint/configurations/mesh_4x4x3_vc_nonspec
@@ -0,0 +1,10 @@
+$model = bless( {
+    'noc_param'=> {
+		"T1" => "4",
+		"T2" => "4",	
+		"T3" => "3",							
+		"TOPOLOGY" => "\"MESH\"",						
+		"ROUTE_NAME" => "\"DOR\"",
+		"COMBINATION_TYPE" => "\"COMB_NONSPEC\"",     					
+	}
+}, 'ProNOC' );
\ No newline at end of file
diff --git a/mpsoc/Integration_test/verilator_lint/configurations/mesh_4x4x3_vc_spec1 b/mpsoc/Integration_test/verilator_lint/configurations/mesh_4x4x3_vc_spec1
new file mode 100644
index 0000000..1c5388c
--- /dev/null
+++ b/mpsoc/Integration_test/verilator_lint/configurations/mesh_4x4x3_vc_spec1
@@ -0,0 +1,10 @@
+$model = bless( {
+    'noc_param'=> {
+		"T1" => "4",
+		"T2" => "4",	
+		"T3" => "3",							
+		"TOPOLOGY" => "\"MESH\"",						
+		"ROUTE_NAME" => "\"DOR\"",
+		"COMBINATION_TYPE" => "\"COMB_SPEC1\"",  						  					
+	}
+}, 'ProNOC' );
\ No newline at end of file
diff --git a/mpsoc/Integration_test/verilator_lint/configurations/mesh_4x4x3_vc_spec2 b/mpsoc/Integration_test/verilator_lint/configurations/mesh_4x4x3_vc_spec2
new file mode 100644
index 0000000..ed2a7f9
--- /dev/null
+++ b/mpsoc/Integration_test/verilator_lint/configurations/mesh_4x4x3_vc_spec2
@@ -0,0 +1,10 @@
+$model = bless( {
+    'noc_param'=> {
+		"T1" => "4",
+		"T2" => "4",	
+		"T3" => "3",							
+		"TOPOLOGY" => "\"MESH\"",						
+		"ROUTE_NAME" => "\"DOR\"",
+		"COMBINATION_TYPE" => "\"COMB_SPEC2\"",  						  					
+	}
+}, 'ProNOC' );
\ No newline at end of file
diff --git a/mpsoc/Integration_test/verilator_lint/configurations/mesh_8x8_2cycle_adaptive b/mpsoc/Integration_test/verilator_lint/configurations/mesh_8x8_2cycle_adaptive
new file mode 100644
index 0000000..0aaa94e
--- /dev/null
+++ b/mpsoc/Integration_test/verilator_lint/configurations/mesh_8x8_2cycle_adaptive
@@ -0,0 +1,6 @@
+$model = bless( {
+    'noc_param'=> {
+        "ROUTE_NAME" => "\"FULL_ADPT\"",
+        "ESCAP_VC_MASK" => "2'b01"
+    }
+}, 'ProNOC' );
\ No newline at end of file
diff --git a/mpsoc/Integration_test/verilator_lint/configurations/mesh_8x8_2cycle_west_first b/mpsoc/Integration_test/verilator_lint/configurations/mesh_8x8_2cycle_west_first
new file mode 100644
index 0000000..a794210
--- /dev/null
+++ b/mpsoc/Integration_test/verilator_lint/configurations/mesh_8x8_2cycle_west_first
@@ -0,0 +1,5 @@
+$model = bless( {
+    'noc_param'=> {
+        "ROUTE_NAME" => "\"WEST_FIRST\"",
+    }
+}, 'ProNOC' );
\ No newline at end of file
diff --git a/mpsoc/Integration_test/verilator_lint/configurations/mesh_8x8_2cycle_xy b/mpsoc/Integration_test/verilator_lint/configurations/mesh_8x8_2cycle_xy
new file mode 100644
index 0000000..7107201
--- /dev/null
+++ b/mpsoc/Integration_test/verilator_lint/configurations/mesh_8x8_2cycle_xy
@@ -0,0 +1,5 @@
+$model = bless( {
+    'noc_param'=> {
+        "ROUTE_NAME" => "\"DOR\"",
+    }
+}, 'ProNOC' );
\ No newline at end of file
diff --git a/mpsoc/Integration_test/verilator_lint/configurations/mesh_8x8_4vc b/mpsoc/Integration_test/verilator_lint/configurations/mesh_8x8_4vc
new file mode 100644
index 0000000..1914e8b
--- /dev/null
+++ b/mpsoc/Integration_test/verilator_lint/configurations/mesh_8x8_4vc
@@ -0,0 +1,7 @@
+$model = bless( {
+    'noc_param'=> {
+        "ROUTE_NAME" => "\"DOR\"",
+        "ESCAP_VC_MASK" => "4'd1",
+        "V" => 4,
+    }
+}, 'ProNOC' );
diff --git a/mpsoc/Integration_test/verilator_lint/configurations/mesh_8x8_4vc_4c b/mpsoc/Integration_test/verilator_lint/configurations/mesh_8x8_4vc_4c
new file mode 100644
index 0000000..26296f7
--- /dev/null
+++ b/mpsoc/Integration_test/verilator_lint/configurations/mesh_8x8_4vc_4c
@@ -0,0 +1,9 @@
+$model = bless( {
+    'noc_param'=> {
+        "ROUTE_NAME" => "\"DOR\"",
+        "V" => 4,
+        "C" => 4,
+        "CLASS_SETTING" => "16'b1000010000100001",
+        "ESCAP_VC_MASK" => "4'b1000"
+    }
+}, 'ProNOC' );
\ No newline at end of file
diff --git a/mpsoc/Integration_test/verilator_lint/configurations/mesh_8x8_4vc_hetero1 b/mpsoc/Integration_test/verilator_lint/configurations/mesh_8x8_4vc_hetero1
new file mode 100644
index 0000000..89af385
--- /dev/null
+++ b/mpsoc/Integration_test/verilator_lint/configurations/mesh_8x8_4vc_hetero1
@@ -0,0 +1,77 @@
+$model = bless( {
+    'noc_param'=> {
+        "ROUTE_NAME" => "\"DOR\"",
+        "ESCAP_VC_MASK" => "4'd1",
+        "V" => 4,
+        "HETERO_VC"=> "1",
+        "MAX_ROUTER"=>"64",
+        "MAX_PORT"=>"1",
+        "int VC_CONFIG_TABLE [MAX_ROUTER][MAX_PORT]"=>"'{
+    //P0 P1 P2 P3 P4 
+    '{1}, // R0
+    '{2}, // R1
+    '{3}, // R2
+    '{4}, // R3
+    '{1}, // R4
+    '{2}, // R5
+    '{3}, // R6
+    '{4}, // R7
+    '{1}, // R8
+    '{2}, // R9
+    '{3}, // R10
+    '{4}, // R11
+    '{1}, // R12
+    '{2}, // R13
+    '{3}, // R14
+    '{1},  // R15
+    '{2}, // R16
+    '{3}, // R17
+    '{4}, // R18
+    '{1}, // R19
+    '{2}, // R20
+    '{3}, // R21
+    '{4}, // R22
+    '{1}, // R23
+    '{2}, // R24
+    '{3}, // R25
+    '{4}, // R26
+    '{1}, // R27
+    '{2}, // R28
+    '{3}, // R29
+    '{1}, // R30
+    '{2}, // R31
+    '{3}, // R32
+    '{4}, // R33
+    '{1}, // R34
+    '{2}, // R35
+    '{3}, // R36
+    '{4}, // R37
+    '{1}, // R38
+    '{2}, // R39
+    '{3}, // R40
+    '{4}, // R41
+    '{1}, // R42
+    '{2}, // R43
+    '{3}, // R44
+    '{1}, // R45
+    '{2}, // R46
+    '{3}, // R47
+    '{4}, // R48
+    '{1}, // R49
+    '{2}, // R50
+    '{3}, // R51
+    '{4}, // R52
+    '{1}, // R53
+    '{2}, // R54
+    '{3}, // R55
+    '{4}, // R56
+    '{1}, // R57
+    '{2}, // R58
+    '{3}, // R59
+    '{1}, // R60
+    '{2}, // R61
+    '{3}, // R62
+    '{4} // R63
+    }",
+    }
+}, 'ProNOC' );
diff --git a/mpsoc/Integration_test/verilator_lint/configurations/mesh_8x8_4vc_hetero2 b/mpsoc/Integration_test/verilator_lint/configurations/mesh_8x8_4vc_hetero2
new file mode 100644
index 0000000..bc13a6f
--- /dev/null
+++ b/mpsoc/Integration_test/verilator_lint/configurations/mesh_8x8_4vc_hetero2
@@ -0,0 +1,77 @@
+$model = bless( {
+    'noc_param'=> {
+        "ROUTE_NAME" => "\"DOR\"",
+        "V" => 4,
+        "ESCAP_VC_MASK" => "4'd1",
+        "HETERO_VC"=> "2",
+        "MAX_ROUTER"=>"64",
+        "MAX_PORT"=>"5",
+        "int VC_CONFIG_TABLE [MAX_ROUTER][MAX_PORT]"=>"'{
+	//P0 P1 P2 P3 P4 
+	'{1, 2, 3, 4, 1}, // R0
+	'{2, 3, 4, 1, 2}, // R1
+	'{3, 4, 1, 2, 3}, // R2
+	'{4, 1, 2, 3, 4}, // R3
+	'{1, 2, 3, 4, 1}, // R4
+	'{2, 3, 4, 1, 2}, // R5
+	'{3, 4, 1, 2, 3}, // R6
+	'{4, 1, 2, 3, 4}, // R7
+	'{1, 2, 3, 4, 1}, // R8
+	'{2, 3, 4, 1, 2}, // R9
+	'{3, 4, 1, 2, 3}, // R10
+	'{4, 1, 2, 3, 4}, // R11
+	'{1, 2, 3, 4, 1}, // R12
+	'{2, 3, 4, 1, 2}, // R13
+	'{3, 4, 1, 2, 3}, // R14
+	'{1, 2, 3, 4, 1},  // R15
+	'{2, 3, 4, 1, 2}, // R16
+	'{3, 4, 1, 2, 3}, // R17
+	'{4, 1, 2, 3, 4}, // R18
+	'{1, 2, 3, 4, 1}, // R19
+	'{2, 3, 4, 1, 2}, // R20
+	'{3, 4, 1, 2, 3}, // R21
+	'{4, 1, 2, 3, 4}, // R22
+	'{1, 2, 3, 4, 1}, // R23
+	'{2, 3, 4, 1, 2}, // R24
+	'{3, 4, 1, 2, 3}, // R25
+	'{4, 1, 2, 3, 4}, // R26
+	'{1, 2, 3, 4, 1}, // R27
+	'{2, 3, 4, 1, 2}, // R28
+	'{3, 4, 1, 2, 3}, // R29
+	'{1, 2, 3, 4, 1}, // R30
+	'{2, 3, 4, 1, 2}, // R31
+	'{3, 4, 1, 2, 3}, // R32
+	'{4, 1, 2, 3, 4}, // R33
+	'{1, 2, 3, 4, 1}, // R34
+	'{2, 3, 4, 1, 2}, // R35
+	'{3, 4, 1, 2, 3}, // R36
+	'{4, 1, 2, 3, 4}, // R37
+	'{1, 2, 3, 4, 1}, // R38
+	'{2, 3, 4, 1, 2}, // R39
+	'{3, 4, 1, 2, 3}, // R40
+	'{4, 1, 2, 3, 4}, // R41
+	'{1, 2, 3, 4, 1}, // R42
+	'{2, 3, 4, 1, 2}, // R43
+	'{3, 4, 1, 2, 3}, // R44
+	'{1, 2, 3, 4, 1}, // R45
+	'{2, 3, 4, 1, 2}, // R46
+	'{3, 4, 1, 2, 3}, // R47
+	'{4, 1, 2, 3, 4}, // R48
+	'{1, 2, 3, 4, 1}, // R49
+	'{2, 3, 4, 1, 2}, // R50
+	'{3, 4, 1, 2, 3}, // R51
+	'{4, 1, 2, 3, 4}, // R52
+	'{1, 2, 3, 4, 1}, // R53
+	'{2, 3, 4, 1, 2}, // R54
+	'{3, 4, 1, 2, 3}, // R55
+	'{4, 1, 2, 3, 4}, // R56
+	'{1, 2, 3, 4, 1}, // R57
+	'{2, 3, 4, 1, 2}, // R58
+	'{3, 4, 1, 2, 3}, // R59
+	'{1, 2, 3, 4, 1}, // R60
+	'{2, 3, 4, 1, 2}, // R61
+	'{3, 4, 1, 2, 3}, // R62
+	'{4, 1, 2, 3, 4}  // R63
+	}",
+    }
+}, 'ProNOC' );
diff --git a/mpsoc/Integration_test/verilator_lint/configurations/mesh_8x8_b2 b/mpsoc/Integration_test/verilator_lint/configurations/mesh_8x8_b2
new file mode 100644
index 0000000..166ee7c
--- /dev/null
+++ b/mpsoc/Integration_test/verilator_lint/configurations/mesh_8x8_b2
@@ -0,0 +1,7 @@
+$model = bless( {
+    'noc_param'=> {
+        "ROUTE_NAME" => "\"DOR\"",
+        "B"=> "2",
+        "LB"=> 2
+    }
+}, 'ProNOC' );
\ No newline at end of file
diff --git a/mpsoc/Integration_test/verilator_lint/configurations/mesh_8x8_sbp6_xy b/mpsoc/Integration_test/verilator_lint/configurations/mesh_8x8_sbp6_xy
new file mode 100644
index 0000000..8e2119a
--- /dev/null
+++ b/mpsoc/Integration_test/verilator_lint/configurations/mesh_8x8_sbp6_xy
@@ -0,0 +1,5 @@
+$model = bless( {
+    'noc_param'=> {
+        "SMART_MAX" => "6",
+    }
+}, 'ProNOC' );
\ No newline at end of file
diff --git a/mpsoc/Integration_test/verilator_lint/configurations/mesh_8x8_single_flit b/mpsoc/Integration_test/verilator_lint/configurations/mesh_8x8_single_flit
new file mode 100644
index 0000000..fb793b8
--- /dev/null
+++ b/mpsoc/Integration_test/verilator_lint/configurations/mesh_8x8_single_flit
@@ -0,0 +1,8 @@
+$model = bless( {
+    'noc_param'=> {
+        "B" => "5",
+        "LB" => "5",
+        "MIN_PCK_SIZE" => "1",
+        "PCK_TYPE" => "  \"SINGLE_FLIT\"",
+    }
+}, 'ProNOC' );
\ No newline at end of file
diff --git a/mpsoc/Integration_test/verilator_lint/configurations/mesh_8x8_ssa_xy b/mpsoc/Integration_test/verilator_lint/configurations/mesh_8x8_ssa_xy
new file mode 100644
index 0000000..02cf843
--- /dev/null
+++ b/mpsoc/Integration_test/verilator_lint/configurations/mesh_8x8_ssa_xy
@@ -0,0 +1,5 @@
+$model = bless( {
+    'noc_param'=> {
+        "SSA_EN" => "1",
+    }
+}, 'ProNOC' );
\ No newline at end of file
diff --git a/mpsoc/Integration_test/verilator_lint/configurations/ring_8x8_2cycle_xy b/mpsoc/Integration_test/verilator_lint/configurations/ring_8x8_2cycle_xy
new file mode 100644
index 0000000..d47e3d9
--- /dev/null
+++ b/mpsoc/Integration_test/verilator_lint/configurations/ring_8x8_2cycle_xy
@@ -0,0 +1,8 @@
+$model = bless( {
+    'compile' => "verilate_mesh.sh",
+        'noc_param'=> {
+        TOPOLOGY=>"\"RING\"",
+        "TOPOLOGY" => "\"TORUS\"",
+        "ROUTE_NAME" => "\"TRANC_DOR\"",
+    }
+}, 'ProNOC' );
diff --git a/mpsoc/Integration_test/verilator_lint/configurations/star6_2cycle_mcast_par b/mpsoc/Integration_test/verilator_lint/configurations/star6_2cycle_mcast_par
new file mode 100644
index 0000000..3bf044e
--- /dev/null
+++ b/mpsoc/Integration_test/verilator_lint/configurations/star6_2cycle_mcast_par
@@ -0,0 +1,11 @@
+$model = bless( {
+    'noc_param'=> {
+        "TOPOLOGY"=>"\"STAR\"",
+        "ROUTE_NAME" =>"\"UNKNOWN\"",
+        "T1" => "6",
+        "CAST_TYPE" => "\"MULTICAST_PARTIAL\"",
+        "Fpay" => "32",
+        "MCAST_ENDP_LIST" => "'b001011",
+        "SELF_LOOP_EN" => "1"
+    }
+}, 'ProNOC' );
\ No newline at end of file
diff --git a/mpsoc/Integration_test/verilator_lint/configurations/star_6 b/mpsoc/Integration_test/verilator_lint/configurations/star_6
new file mode 100644
index 0000000..06cc862
--- /dev/null
+++ b/mpsoc/Integration_test/verilator_lint/configurations/star_6
@@ -0,0 +1,8 @@
+$model = bless( {
+    'noc_param'=> {
+        "TOPOLOGY" => "\"STAR\"",
+        "T1" => "6",
+        "T2" => "1",
+        "B"  => "5",
+    }
+}, 'ProNOC' );
\ No newline at end of file
diff --git a/mpsoc/Integration_test/verilator_lint/configurations/torus_8x8_2cycle_xy b/mpsoc/Integration_test/verilator_lint/configurations/torus_8x8_2cycle_xy
new file mode 100644
index 0000000..7d29733
--- /dev/null
+++ b/mpsoc/Integration_test/verilator_lint/configurations/torus_8x8_2cycle_xy
@@ -0,0 +1,6 @@
+$model = bless( {
+    'noc_param'=> {
+        "TOPOLOGY" => "\"TORUS\"",
+        "ROUTE_NAME" => "\"TRANC_DOR\"",
+    }
+}, 'ProNOC' );
\ No newline at end of file
diff --git a/mpsoc/Integration_test/verilator_lint/golden_ref/report.txt b/mpsoc/Integration_test/verilator_lint/golden_ref/report.txt
new file mode 100644
index 0000000..0806eae
--- /dev/null
+++ b/mpsoc/Integration_test/verilator_lint/golden_ref/report.txt
@@ -0,0 +1,40 @@
+Configuration                  | # Warnings | # Errors   | # Instants |
+bintree_k3_L3_st               | 125        | 0          | 5847       |
+custom1_topology               | 124        | 0          | 7076       |
+Fattree_k3_L3_st               | 126        | 0          | 15933      |
+fmesh_1x1_openpiton            | 136        | 0          | 430        |
+fmesh_2x2_openpiton            | 139        | 0          | 1671       |
+fmesh_8x8_2cycle_xy            | 119        | 0          | 38595      |
+fmesh_8x8_openpiton            | 139        | 0          | 26691      |
+line4_smart3                   | 161        | 0          | 1263       |
+line_4_v1_B15                  | 146        | 0          | 1071       |
+line_8_single_flit             | 142        | 0          | 3147       |
+mesh_2x2_openpiton             | 152        | 0          | 1751       |
+mesh_3x3_v2_ssa                | 138        | 0          | 5430       |
+mesh_4x4_2cycle_mcast_f        | 119        | 0          | 9811       |
+mesh_4x4_LB5_B4                | 117        | 0          | 9619       |
+mesh_4x4_selflp_mcast_f        | 118        | 0          | 9011       |
+mesh_4x4_smart3                | 138        | 0          | 7683       |
+mesh_4x4_v1_B15                | 133        | 0          | 6883       |
+mesh_4x4x2_bcast_f             | 119        | 0          | 12291      |
+mesh_4x4x2_bcast_p             | 119        | 0          | 12291      |
+mesh_4x4x2_mcast_p             | 118        | 0          | 12291      |
+mesh_4x4x3_2cycle_xy           | 126        | 0          | 14099      |
+mesh_4x4x3_vc_nonspec          | 126        | 0          | 14099      |
+mesh_4x4x3_vc_spec1            | 128        | 0          | 14707      |
+mesh_4x4x3_vc_spec2            | 134        | 0          | 14707      |
+mesh_8x8_2cycle_adaptive       | 125        | 0          | 43971      |
+mesh_8x8_2cycle_west_first     | 132        | 0          | 43267      |
+mesh_8x8_2cycle_xy             | 128        | 0          | 40323      |
+mesh_8x8_4vc                   | 128        | 0          | 60803      |
+mesh_8x8_4vc_4c                | 128        | 0          | 62083      |
+mesh_8x8_4vc_hetero1           | 137        | 0          | 54173      |
+mesh_8x8_4vc_hetero2           | 137        | 0          | 54485      |
+mesh_8x8_b2                    | 127        | 0          | 40323      |
+mesh_8x8_sbp6_xy               | 140        | 0          | 47363      |
+mesh_8x8_single_flit           | 129        | 0          | 40643      |
+mesh_8x8_ssa_xy                | 144        | 0          | 42755      |
+ring_8x8_2cycle_xy             | 136        | 0          | 40515      |
+star_6                         | 129        | 0          | 615        |
+star6_2cycle_mcast_par         | 121        | 0          | 691        |
+torus_8x8_2cycle_xy            | 136        | 0          | 40515      |
diff --git a/mpsoc/Integration_test/verilator_lint/run.sh b/mpsoc/Integration_test/verilator_lint/run.sh
new file mode 100644
index 0000000..a7731eb
--- /dev/null
+++ b/mpsoc/Integration_test/verilator_lint/run.sh
@@ -0,0 +1,111 @@
+#!/bin/bash
+
+SCRPT_FULL_PATH=$(realpath "${BASH_SOURCE[0]}")
+SCRPT_DIR_PATH=$(dirname "$SCRPT_FULL_PATH")
+
+# Paths
+conf_dir="${SCRPT_DIR_PATH}/configurations"
+log_dir="${SCRPT_DIR_PATH}/result_logs"
+work="${SCRPT_DIR_PATH}/work"
+file_list_f="${SCRPT_DIR_PATH}/src/file_list.f"
+report_file="${log_dir}/report.txt"
+
+mkdir -p "$work"
+mkdir -p "$log_dir"
+rm -rf "$report_file"
+printf "%-30s | %-10s | %-10s | %-10s | %s\n" "Configuration" "# Warnings" "# Errors" "# Instants" "Warning Summary">> "$report_file"
+
+
+# List of Verilator warnings to suppress
+verilator_ignores=(
+    EOFNEWLINE
+    DECLFILENAME
+    PINCONNECTEMPTY
+)
+
+
+verilator_lint () {
+    set -e
+    conf=$1
+    conf_file="${conf_dir}/$conf"
+    log_file="${log_dir}/${conf}.log"
+    xml_file="${log_dir}/${conf}.xml"
+    if [[ ! -f "$conf_file" ]]; then
+        echo "Configuration file $conf_file does not exist"
+        exit 1
+    fi
+
+    perl "${SCRPT_DIR_PATH}/src/param_gen.pl" "$conf_file"
+    
+    # Build warning suppression flags
+    ignore_flags=""
+    for warn in "${verilator_ignores[@]}"; do
+        ignore_flags+=" --Wno-${warn}"
+    done
+
+    # Lint using Verilator
+    verilator --xml-output $xml_file --lint-only -Wall $ignore_flags -Wno-fatal -f "$file_list_f" --top-module noc_top_v > "$log_file" 2>&1
+    perl "${SCRPT_DIR_PATH}/src/instant_export.pl" "$xml_file"  >> "$log_file" 
+
+}
+
+
+report_total_errors_warnings () {
+    conf="$1"
+    log_file="${log_dir}/${conf}.log"
+    warnings=$(grep '%Warning' "$log_file" | wc -l)
+    errors=$(grep '%Error' "$log_file" | wc -l)
+    warning_sep=$(grep -oP '^%Warning-\K[A-Z0-9_]+' "$log_file" | sort | uniq -c | awk '{printf "%s(%d), ", toupper($2), $1}')
+    # Remove trailing comma and space
+    #warning_sep=${ warning_sep%, }
+    instant=$(awk '/Total module instantiations:/ { print $NF }' "$log_file")
+    printf "%-30s | %-10s | %-10s | %-10s | %s\n" "$conf" "$warnings" "$errors" "$instant" "$warning_sep">> "$report_file"
+}
+
+run_config () {
+    conf="$1"
+    log_file="${log_dir}/${conf}.log"
+    echo "▶️  Linting configuration: $conf"
+    if ! verilator_lint "$conf"; then
+        echo "❌ Linting failed for $conf (check $log_file)"
+        rm -f "${SCRPT_DIR_PATH}/src/noc_localparam.v"
+        exit 1
+    else
+        echo "✅ Linting successful for $conf"
+        rm -f "${SCRPT_DIR_PATH}/src/noc_localparam.v"
+        report_total_errors_warnings "$conf"
+    fi
+}
+
+# === Main ===
+if [[ "$1" == "-h" || "$1" == "--help" ]]; then
+    echo "Usage: bash run.sh [config_name]"
+    echo
+    echo "If [config_name] is provided, only that configuration will be processed."
+    echo "If no argument is given, all configurations in the 'configurations/' directory will be processed."
+    echo
+    echo "Examples:"
+    echo "  bash run.sh         # Run all configurations"
+    echo "  bash run.sh conf1   # Run only conf1"
+    exit 0
+fi
+
+if [[ $# -eq 1 ]]; then
+    run_config "$1"
+else
+    for f in "$conf_dir"/*; do
+        [[ -d "$f" ]] && continue
+        conf=$(basename "$f")
+        run_config "$conf"
+    done
+fi
+
+echo "Report saved in $report_file"
+echo "Summary:"
+echo "-------------------------------|------------|------------|------------|"
+cat "$report_file"
+
+echo "Comparing with golden reference..."
+perl "${SCRPT_DIR_PATH}/../Altera/src/compare.pl" "${SCRPT_DIR_PATH}/golden_ref/report.txt" "$report_file"
+echo "All configurations processed. Results are in $report_file"
+
diff --git a/mpsoc/Integration_test/verilator_lint/src/file_list.f b/mpsoc/Integration_test/verilator_lint/src/file_list.f
new file mode 100644
index 0000000..1f5742d
--- /dev/null
+++ b/mpsoc/Integration_test/verilator_lint/src/file_list.f
@@ -0,0 +1,6 @@
++incdir+./src 
+
+-F ./../../rtl/src_noc/noc_filelist.f
+-F ./../../rtl/src_topology/custom_flist.f
+
+
diff --git a/mpsoc/Integration_test/verilator_lint/src/instant_export.pl b/mpsoc/Integration_test/verilator_lint/src/instant_export.pl
new file mode 100644
index 0000000..7e96b96
--- /dev/null
+++ b/mpsoc/Integration_test/verilator_lint/src/instant_export.pl
@@ -0,0 +1,41 @@
+#!/usr/bin/perl
+use strict;
+use warnings;
+
+die "Usage: $0 <verilator_xml_file>\n" unless @ARGV;
+my $xml_file = shift;
+
+open my $fh, '<', $xml_file or die "Could not open '$xml_file': $!";
+my $instants=0;
+my %insts;
+while (my $line = <$fh>) {
+    chomp $line;  # Remove the newline character
+    if ($line =~ /<cell /) {
+        if ($line =~ /submodname="([^"]+)"/) {
+           my $submodule= $1;
+           # Remove everything after "__"
+           $submodule =~ s/\s*__.*$//;
+           if (defined $insts{$submodule}){
+                $insts{$submodule}++;
+           }else{
+                $insts{$submodule}=1;
+           }
+        }
+        $instants++;
+    }
+    
+}
+
+print "\n\n-----------------------------------\nTotal module instantiations: $instants\n";
+print "Breakdown by module type:\n";
+# Determine the longest key length for alignment
+my $max_key_len = 0;
+$max_key_len = length($_) > $max_key_len ? length($_) : $max_key_len for keys %insts;
+
+# Print sorted by value, aligned
+foreach my $key (sort { $insts{$b} <=> $insts{$a} } keys %insts) {
+    printf "%-*s  %d\n", $max_key_len, $key, $insts{$key};
+}
+
+close $fh;
+
diff --git a/mpsoc/Integration_test/verilator_lint/src/param_gen.pl b/mpsoc/Integration_test/verilator_lint/src/param_gen.pl
new file mode 100644
index 0000000..1ad4763
--- /dev/null
+++ b/mpsoc/Integration_test/verilator_lint/src/param_gen.pl
@@ -0,0 +1,46 @@
+#!/usr/bin/perl  
+package ProNOC;
+use strict;
+use warnings;
+use File::Basename;
+
+
+#add home dir in perl 5.6
+use FindBin;
+use lib $FindBin::Bin;
+use Cwd qw(realpath);
+
+
+
+
+use File::Path qw(make_path);
+
+
+use strict;
+use warnings;
+
+
+
+
+my $script_path = dirname(__FILE__);
+
+require "$script_path/../../synthetic_sim/src/src.pl";
+use lib "../synthetic_sim/src/perl_lib";
+
+use constant::boolean;
+use base 'Class::Accessor::Fast';
+
+my $conf_file=$ARGV[0];
+
+
+sub create_noc_param_vv {
+    my ($conf_file)=@_;
+    my $o = do $conf_file;
+    die "Could not parse $conf_file: $@" if $@;
+    die "Could not read $conf_file: $!" unless defined $o;
+    my $param = $o->{'noc_param'};
+    my ($param_v,$include_h,$tops)=   gen_noc_localparam_v( $o,$param);
+    save_file("$script_path/noc_localparam.v",$param_v);
+}
+
+create_noc_param_vv ($conf_file);
diff --git a/mpsoc/clean.sh b/mpsoc/clean.sh
deleted file mode 100755
index 4b53aaa..0000000
--- a/mpsoc/clean.sh
+++ /dev/null
@@ -1,2 +0,0 @@
-find . -name '*~' -exec rm {} \;
-find . -name '*.o' -exec rm {} \;
diff --git a/mpsoc/perl_gui/icons/ProNoC.png b/mpsoc/perl_gui/icons/ProNoC.png
old mode 100755
new mode 100644
index 601c543..630dc3a
Binary files a/mpsoc/perl_gui/icons/ProNoC.png and b/mpsoc/perl_gui/icons/ProNoC.png differ
diff --git a/mpsoc/perl_gui/icons/yaml.png b/mpsoc/perl_gui/icons/yaml.png
new file mode 100644
index 0000000..7503924
Binary files /dev/null and b/mpsoc/perl_gui/icons/yaml.png differ
diff --git a/mpsoc/perl_gui/lib/emulate/tt.EML b/mpsoc/perl_gui/lib/emulate/tt.EML
index 0d1dcb3..8397dd3 100644
--- a/mpsoc/perl_gui/lib/emulate/tt.EML
+++ b/mpsoc/perl_gui/lib/emulate/tt.EML
@@ -21,7 +21,7 @@ $emulate = bless( {
                     'noc_param' => {
                                      'AVC_ATOMIC_EN' => 0,
                                      'LB' => '4',
-                                     'SSA_EN' => '"NO"',
+                                     'SSA_EN' => '0',
                                      'DEBUG_EN' => '0',
                                      'B' => '4',
                                      'COMBINATION_TYPE' => '"COMB_NONSPEC"',
@@ -30,7 +30,7 @@ $emulate = bless( {
                                      'WEIGHTw' => '4',
                                      'ESCAP_VC_MASK' => '2\'b01',
                                      'C' => 0,
-                                     'SELF_LOOP_EN' => '"NO"',
+                                     'SELF_LOOP_EN' => '0',
                                      'SWA_ARBITER_TYPE' => '"RRA"',
                                      'MUX_TYPE' => '"BINARY"',
                                      'V' => '2',
@@ -42,7 +42,7 @@ $emulate = bless( {
                                      'ADD_PIPREG_AFTER_CROSSBAR' => '1\'b0',
                                      'FIRST_ARBITER_EXT_P_EN' => 1,
                                      'MIN_PCK_SIZE' => '2',
-                                     'ROUTE_NAME' => '"XY"',
+                                     'ROUTE_NAME' => '"DOR"',
                                      'T1' => '2',
                                      'CONGESTION_INDEX' => 3,
                                      'SMART_MAX' => '0'
diff --git a/mpsoc/perl_gui/lib/ip/NoC/ni_slave.IP b/mpsoc/perl_gui/lib/ip/NoC/ni_slave.IP
index dd714c7..2a49a3e 100644
--- a/mpsoc/perl_gui/lib/ip/NoC/ni_slave.IP
+++ b/mpsoc/perl_gui/lib/ip/NoC/ni_slave.IP
@@ -101,7 +101,7 @@ The maximum data that can be sent via one packet will be 2 power of MAX_DMA_TRAN
                                                       'global_param' => 'Parameter',
                                                       'redefine_param' => 1,
                                                       'content' => '',
-                                                      'default' => '"XY"   '
+                                                      'default' => '"DOR"   '
                                                     },
                                     'Fpay' => {
                                                 'default' => ' 32',
diff --git a/mpsoc/perl_gui/lib/mpsoc/mor1k_mpsoc.MPSOC b/mpsoc/perl_gui/lib/mpsoc/mor1k_mpsoc.MPSOC
index 258ebe9..2e36799 100644
--- a/mpsoc/perl_gui/lib/mpsoc/mor1k_mpsoc.MPSOC
+++ b/mpsoc/perl_gui/lib/mpsoc/mor1k_mpsoc.MPSOC
@@ -589,7 +589,7 @@ $mpsoc = bless( {
                                    'LB' => '4',
                                    'MUX_TYPE' => '"BINARY"',
                                    'SWA_ARBITER_TYPE' => '"RRA"',
-                                   'SELF_LOOP_EN' => '"NO"',
+                                   'SELF_LOOP_EN' => '0',
                                    'CONGESTION_INDEX' => 3,
                                    'DEBUG_EN' => '0',
                                    'BYTE_EN' => '1',
@@ -598,7 +598,7 @@ $mpsoc = bless( {
                                    'FIRST_ARBITER_EXT_P_EN' => 1,
                                    'T3' => '1',
                                    'TOPOLOGY' => '"MESH"',
-                                   'ROUTE_NAME' => '"XY"',
+                                   'ROUTE_NAME' => '"DOR"',
                                    'VC_REALLOCATION_TYPE' => '"NONATOMIC"',
                                    'V' => '2',
                                    'COMBINATION_TYPE' => '"COMB_NONSPEC"',
@@ -607,7 +607,7 @@ $mpsoc = bless( {
                                    'WEIGHTw' => '4',
                                    'AVC_ATOMIC_EN' => 0,
                                    'B' => '4',
-                                   'SSA_EN' => '"NO"',
+                                   'SSA_EN' => '0',
                                    'ADD_PIPREG_AFTER_CROSSBAR' => '1\'b0',
                                    'MCAST_ENDP_LIST' => '\'hf',
                                    'T2' => '2',
diff --git a/mpsoc/perl_gui/lib/multi_nocs/test.phy b/mpsoc/perl_gui/lib/multi_nocs/test.phy
index b7f1132..7146d07 100644
--- a/mpsoc/perl_gui/lib/multi_nocs/test.phy
+++ b/mpsoc/perl_gui/lib/multi_nocs/test.phy
@@ -11,7 +11,7 @@
 
 $phy = bless( {
                 'noc_param1' => {
-                                  'SELF_LOOP_EN' => '"NO"',
+                                  'SELF_LOOP_EN' => '0',
                                   'ADD_PIPREG_AFTER_CROSSBAR' => '1\'b0',
                                   'V' => '2',
                                   'LB' => '4',
@@ -29,7 +29,7 @@ $phy = bless( {
                                   'AVC_ATOMIC_EN' => 0,
                                   'WEIGHTw' => '4',
                                   'PCK_TYPE' => '"MULTI_FLIT"',
-                                  'SSA_EN' => '"NO"',
+                                  'SSA_EN' => '0',
                                   'Fpay' => '32',
                                   'FIRST_ARBITER_EXT_P_EN' => 1,
                                   'CAST_TYPE' => '"UNICAST"',
@@ -37,7 +37,7 @@ $phy = bless( {
                                   'SWA_ARBITER_TYPE' => '"RRA"',
                                   'T2' => '2',
                                   'TOPOLOGY' => '"MESH"',
-                                  'ROUTE_NAME' => '"XY"',
+                                  'ROUTE_NAME' => '"DOR"',
                                   'BYTE_EN' => 0,
                                   'DEBUG_EN' => '0'
                                 },
@@ -59,8 +59,8 @@ $phy = bless( {
                                   'COMBINATION_TYPE' => '"COMB_NONSPEC"',
                                   'FIRST_ARBITER_EXT_P_EN' => 1,
                                   'Fpay' => '32',
-                                  'SSA_EN' => '"NO"',
-                                  'ROUTE_NAME' => '"XY"',
+                                  'SSA_EN' => '0',
+                                  'ROUTE_NAME' => '"DOR"',
                                   'T2' => '3',
                                   'TOPOLOGY' => '"MESH"',
                                   'SWA_ARBITER_TYPE' => '"RRA"',
@@ -71,7 +71,7 @@ $phy = bless( {
                                   'LB' => '4',
                                   'V' => '2',
                                   'ADD_PIPREG_AFTER_CROSSBAR' => '1\'b0',
-                                  'SELF_LOOP_EN' => '"NO"',
+                                  'SELF_LOOP_EN' => '0',
                                   'SMART_MAX' => '0',
                                   'CONGESTION_INDEX' => 3,
                                   'MIN_PCK_SIZE' => '2',
@@ -246,9 +246,9 @@ $phy = bless( {
                                   'TOPOLOGY' => '"MESH"',
                                   'SWA_ARBITER_TYPE' => '"RRA"',
                                   'T1' => '2',
-                                  'ROUTE_NAME' => '"XY"',
+                                  'ROUTE_NAME' => '"DOR"',
                                   'Fpay' => '32',
-                                  'SSA_EN' => '"NO"',
+                                  'SSA_EN' => '0',
                                   'FIRST_ARBITER_EXT_P_EN' => 1,
                                   'COMBINATION_TYPE' => '"COMB_NONSPEC"',
                                   'WEIGHTw' => '4',
@@ -264,7 +264,7 @@ $phy = bless( {
                                   'T3' => '1',
                                   'MIN_PCK_SIZE' => '2',
                                   'SMART_MAX' => '0',
-                                  'SELF_LOOP_EN' => '"NO"',
+                                  'SELF_LOOP_EN' => '0',
                                   'V' => '2',
                                   'ADD_PIPREG_AFTER_CROSSBAR' => '1\'b0',
                                   'LB' => '4'
@@ -282,17 +282,17 @@ $phy = bless( {
                                   'V' => '2',
                                   'ADD_PIPREG_AFTER_CROSSBAR' => '1\'b0',
                                   'LB' => '4',
-                                  'SELF_LOOP_EN' => '"NO"',
+                                  'SELF_LOOP_EN' => '0',
                                   'BYTE_EN' => 0,
                                   'DEBUG_EN' => '0',
                                   'SWA_ARBITER_TYPE' => '"RRA"',
                                   'T1' => '2',
                                   'T2' => '2',
                                   'TOPOLOGY' => '"MESH"',
-                                  'ROUTE_NAME' => '"XY"',
+                                  'ROUTE_NAME' => '"DOR"',
                                   'CAST_TYPE' => '"UNICAST"',
                                   'FIRST_ARBITER_EXT_P_EN' => 1,
-                                  'SSA_EN' => '"NO"',
+                                  'SSA_EN' => '0',
                                   'Fpay' => '32',
                                   'PCK_TYPE' => '"MULTI_FLIT"',
                                   'COMBINATION_TYPE' => '"COMB_NONSPEC"',
diff --git a/mpsoc/perl_gui/lib/multi_nocs/tt.phy b/mpsoc/perl_gui/lib/multi_nocs/tt.phy
index 2d46d0d..54885fe 100644
--- a/mpsoc/perl_gui/lib/multi_nocs/tt.phy
+++ b/mpsoc/perl_gui/lib/multi_nocs/tt.phy
@@ -36,14 +36,14 @@ $phy = bless( {
                                   'VC_REALLOCATION_TYPE' => '"NONATOMIC"',
                                   'AVC_ATOMIC_EN' => 0,
                                   'B' => '4',
-                                  'ROUTE_NAME' => '"XY"',
+                                  'ROUTE_NAME' => '"DOR"',
                                   'ESCAP_VC_MASK' => '2\'b01',
                                   'DEBUG_EN' => '0',
-                                  'SELF_LOOP_EN' => '"NO"',
+                                  'SELF_LOOP_EN' => '0',
                                   'WEIGHTw' => '4',
                                   'SWA_ARBITER_TYPE' => '"RRA"',
                                   'MIN_PCK_SIZE' => '2',
-                                  'SSA_EN' => '"NO"',
+                                  'SSA_EN' => '0',
                                   'TOPOLOGY' => '"MESH"',
                                   'PCK_TYPE' => '"MULTI_FLIT"'
                                 },
@@ -198,17 +198,17 @@ $phy = bless( {
                                   'SMART_MAX' => '0',
                                   'Fpay' => '32',
                                   'CAST_TYPE' => '"UNICAST"',
-                                  'SELF_LOOP_EN' => '"NO"',
+                                  'SELF_LOOP_EN' => '0',
                                   'WEIGHTw' => '4',
                                   'DEBUG_EN' => '0',
                                   'ESCAP_VC_MASK' => '2\'b01',
-                                  'ROUTE_NAME' => '"XY"',
+                                  'ROUTE_NAME' => '"DOR"',
                                   'B' => '4',
                                   'AVC_ATOMIC_EN' => 0,
                                   'VC_REALLOCATION_TYPE' => '"NONATOMIC"',
                                   'TOPOLOGY' => '"MESH"',
                                   'PCK_TYPE' => '"MULTI_FLIT"',
-                                  'SSA_EN' => '"NO"',
+                                  'SSA_EN' => '0',
                                   'MIN_PCK_SIZE' => '2',
                                   'SWA_ARBITER_TYPE' => '"RRA"'
                                 },
@@ -234,13 +234,13 @@ $phy = bless( {
                                   'SMART_MAX' => '0',
                                   'DEBUG_EN' => '0',
                                   'WEIGHTw' => '4',
-                                  'SELF_LOOP_EN' => '"NO"',
+                                  'SELF_LOOP_EN' => '0',
                                   'AVC_ATOMIC_EN' => 0,
                                   'VC_REALLOCATION_TYPE' => '"NONATOMIC"',
-                                  'ROUTE_NAME' => '"XY"',
+                                  'ROUTE_NAME' => '"DOR"',
                                   'ESCAP_VC_MASK' => '2\'b01',
                                   'B' => '4',
-                                  'SSA_EN' => '"NO"',
+                                  'SSA_EN' => '0',
                                   'PCK_TYPE' => '"MULTI_FLIT"',
                                   'TOPOLOGY' => '"MESH"',
                                   'SWA_ARBITER_TYPE' => '"RRA"',
@@ -306,7 +306,7 @@ $phy = bless( {
                                                    },
                                                    {
                                                      'param_name' => 'SSA_EN',
-                                                     'value' => '"NO"'
+                                                     'value' => 0
                                                    },
                                                    {
                                                      'param_name' => 'SWA_ARBITER_TYPE ',
diff --git a/mpsoc/perl_gui/lib/netwmaker/custom1.NWM b/mpsoc/perl_gui/lib/netwmaker/custom1.NWM
index caa3d56..cbbb6ec 100644
--- a/mpsoc/perl_gui/lib/netwmaker/custom1.NWM
+++ b/mpsoc/perl_gui/lib/netwmaker/custom1.NWM
@@ -318,7 +318,7 @@ $nwmaker = bless( {
                                                          'value' => '{CVw{1\'b1}}'
                                                        },
                                                        {
-                                                         'value' => '"NO"',
+                                                         'value' => 0,
                                                          'param_name' => 'SSA_EN'
                                                        },
                                                        {
diff --git a/mpsoc/perl_gui/lib/perl/ColorButton.pm b/mpsoc/perl_gui/lib/perl/ColorButton.pm
index a5e52ab..1d38a6b 100644
--- a/mpsoc/perl_gui/lib/perl/ColorButton.pm
+++ b/mpsoc/perl_gui/lib/perl/ColorButton.pm
@@ -39,48 +39,46 @@ use Glib::Object::Subclass
                 0xffff,
                 [qw/readable writable/]
         ),
-	 Glib::ParamSpec->string (
+    Glib::ParamSpec->string (
                 'label',
                 'Label',
                 'The lable of button',
                 "BBB",
                 [qw/readable writable/]
         ),
-
     ]
     ;
 
 sub INIT_INSTANCE {
-	my $self = shift;
-	$self->{red} = 0xffff;
-	$self->{green} = 0xffff;
-	$self->{blue} = 0xffff;
-	$self->{label} = "Colored_button";
-	
-
-	my $frame = Gtk2::Frame->new;
-	$frame->set_border_width (0);
-	$frame->set_shadow_type ('etched-in');
-	$self->add ($frame);
-	$frame->show;
-	my $event_box = Gtk2::EventBox->new;
-	# $event_box->set_size_request (140, 140);
-	my $label   = Gtk2::Label->new($self->{label});
-	$event_box->add($label);
-	
-	$frame->add ($event_box);
-	$event_box->show;
-	$self->{colorbox} = $event_box;
-	$self->{labelbox} = $label; 
+    my $self = shift;
+    $self->{red} = 0xffff;
+    $self->{green} = 0xffff;
+    $self->{blue} = 0xffff;
+    $self->{label} = "Colored_button";
+    
+    my $frame = Gtk2::Frame->new;
+    $frame->set_border_width (0);
+    $frame->set_shadow_type ('etched-in');
+    $self->add ($frame);
+    $frame->show;
+    my $event_box = Gtk2::EventBox->new;
+    # $event_box->set_size_request (140, 140);
+    my $label   = Gtk2::Label->new($self->{label});
+    $event_box->add($label);
+    
+    $frame->add ($event_box);
+    $event_box->show;
+    $self->{colorbox} = $event_box;
+    $self->{labelbox} = $label; 
 }
 
 sub on_show {
-        my $self = shift;
-        $self->set_color (red => $self->{red},
-                          green => $self->{green},
-                          blue => $self->{blue});
-	$self->{labelbox}->set_label ($self->{label});
-
+    my $self = shift;
+    $self->set_color (
+        red => $self->{red},
+        green => $self->{green},
+        blue => $self->{blue});
+    $self->{labelbox}->set_label ($self->{label});
         $self->signal_chain_from_overridden;
 }
 
@@ -88,16 +86,15 @@ sub set_color {
         my $self = shift;
         my %params = @_;
         my $color = Gtk2::Gdk::Color->new ($params{red},
-                                           $params{green},
-                                           $params{blue});
-     #   $self->{colorbox}->get_colormap->alloc_color ($color, 0, 1);
+                                        $params{green},
+                                        $params{blue});
+        #$self->{colorbox}->get_colormap->alloc_color ($color, 0, 1);
         $self->{colorbox}->modify_bg ('normal', $color);
-       # $self->{colorbox}->modify_bg ('active', $color);
-       # $self->{colorbox}->modify_bg ('prelight', $color);
+        #$self->{colorbox}->modify_bg ('active', $color);
+        #$self->{colorbox}->modify_bg ('prelight', $color);
         $self->{red} = $params{red};
         $self->{green} = $params{green};
         $self->{blue} = $params{blue};
         $self->signal_emit ('color-changed');
 }
- 
-1
+1
\ No newline at end of file
diff --git a/mpsoc/perl_gui/lib/perl/common.pl b/mpsoc/perl_gui/lib/perl/common.pl
index b7331c9..100e665 100644
--- a/mpsoc/perl_gui/lib/perl/common.pl
+++ b/mpsoc/perl_gui/lib/perl/common.pl
@@ -13,203 +13,168 @@
 use Cwd 'abs_path';
 use Term::ANSIColor qw(:constants);
 use IPC::Run qw(start pump finish timeout pumpable);
- 
+
 use FindBin;
 use lib $FindBin::Bin;
 use constant::boolean;
 use IO::CaptureOutput qw(capture qxx qxy);
 
-
 our %glob_setting;
 $glob_setting{'FONT_SIZE'}='default';
 $glob_setting{'ICON_SIZE'}='default';
 $glob_setting{'DSPLY_X'}  ='default';
 $glob_setting{'DSPLY_Y'}  ='default';
 
-
-
-
 sub log2{
-	my $num=shift;
-	my $log=($num <=1) ? 1: 0;        
-	while( (1<< $log)  < $num) {    
-				$log++;    
-	}
-	return  $log;  
+    my $num=shift;
+    my $log=($num <=1) ? 1: 0;
+    while( (1<< $log)  < $num) {
+                $log++;
+    }
+    return  $log;
 }
 
 sub find_the_most_similar_position{
-	my ($item ,@list)=@_;
-	my $most_similar_pos=0;
-	my $lastsim=0;
-	my $i=0;
-	# convert item to lowercase
-	$item = lc $item;
-	foreach my $p(@list){
-		my $similarity= similarity $item, $p;
-		if ($similarity > $lastsim){
-			$lastsim=$similarity;
-			$most_similar_pos=$i;
-		}
-		$i++;
-	}
-	return $most_similar_pos;
+    my ($item ,@list)=@_;
+    my $most_similar_pos=0;
+    my $lastsim=0;
+    my $i=0;
+    # convert item to lowercase
+    $item = lc $item;
+    foreach my $p(@list){
+        my $similarity= similarity $item, $p;
+        if ($similarity > $lastsim){
+            $lastsim=$similarity;
+            $most_similar_pos=$i;
+        }
+        $i++;
+    }
+    return $most_similar_pos;
 }
 
 sub is_integer {
-   defined $_[0] && $_[0] =~ /^[+-]?\d+$/;
+    defined $_[0] && $_[0] =~ /^[+-]?\d+$/;
 }
 
-
 ####################
-#	 verilog file
+#     verilog file
 ##################
-
-
 sub read_verilog_file{
-	my @files            = @_;
-	my %cmd_line_defines = ();
-	my $quiet            = 1;
-	my @inc_dirs         = ();
-	my @lib_dirs         = ();
-	my @lib_exts         = ();
-	my $vdb = rvp->read_verilog(\@files,[],\%cmd_line_defines,
-			  $quiet,\@inc_dirs,\@lib_dirs,\@lib_exts);
-
-	my @problems = $vdb->get_problems();
-	if (@problems) {
-	    foreach my $problem ($vdb->get_problems()) {
-		print STDERR "$problem.\n" unless ( $problem =~ /smartflit_chanel_t/);
-	    }
-	    # die "Warnings parsing files!";
-	}
-	return $vdb;
+    my @files            = @_;
+    my %cmd_line_defines = ();
+    my $quiet            = 1;
+    my @inc_dirs         = ();
+    my @lib_dirs         = ();
+    my @lib_exts         = ();
+    my $vdb = rvp->read_verilog(
+        \@files,[],\%cmd_line_defines,
+        $quiet,\@inc_dirs,\@lib_dirs,\@lib_exts);
+    my @problems = $vdb->get_problems();
+    if (@problems) {
+        foreach my $problem ($vdb->get_problems()) {
+        print STDERR "$problem.\n" unless ( $problem =~ /smartflit_chanel_t/);
+        }
+        # die "Warnings parsing files!";
+    }
+    return $vdb;
 }
 
-
 sub verilog_file_get_ports_list{
-	my ($vdb,$top_module)=@_;
-	my @ports;
-	
-	foreach my $sig (sort $vdb->get_modules_signals($top_module)) {
-	my ($line,$a_line,$i_line,$type,$file,$posedge,$negedge,
-	 $type2,$s_file,$s_line,$range,$a_file,$i_file,$dims) = 
-	   $vdb->get_module_signal($top_module,$sig);
-
-		if($type eq "input" or $type eq "inout" or $type eq "output" ){
-			push(@ports, $sig);
-			
-		}
-	}
-	return @ports;
+    my ($vdb,$top_module)=@_;
+    my @ports;
+    foreach my $sig (sort $vdb->get_modules_signals($top_module)) {
+    my ($line,$a_line,$i_line,$type,$file,$posedge,$negedge,
+    $type2,$s_file,$s_line,$range,$a_file,$i_file,$dims) = 
+    $vdb->get_module_signal($top_module,$sig);
+        if($type eq "input" or $type eq "inout" or $type eq "output" ){
+            push(@ports, $sig);
+        }
+    }
+    return @ports;
 }
 
-
-
 sub get_ports_type{
-	my ($vdb,$top_module)=@_;
-	my %ports;
-	
-	foreach my $sig (sort $vdb->get_modules_signals($top_module)) {
-	my ($line,$a_line,$i_line,$type,$file,$posedge,$negedge,
-	 $type2,$s_file,$s_line,$range,$a_file,$i_file,$dims) = 
-	   $vdb->get_module_signal($top_module,$sig);
-
-		if($type eq "input" or $type eq "inout" or $type eq "output" ){
-			$ports{$sig}=$type;
-			
-		}
-	}
-	return %ports;
+    my ($vdb,$top_module)=@_;
+    my %ports;
+    foreach my $sig (sort $vdb->get_modules_signals($top_module)) {
+    my ($line,$a_line,$i_line,$type,$file,$posedge,$negedge,
+    $type2,$s_file,$s_line,$range,$a_file,$i_file,$dims) = 
+    $vdb->get_module_signal($top_module,$sig);
+        if($type eq "input" or $type eq "inout" or $type eq "output" ){
+            $ports{$sig}=$type;
+        }
+    }
+    return %ports;
 }
 
 
-
 sub get_ports_rang{
-	my ($vdb,$top_module)=@_;
-	my %ports;
-	
-	foreach my $sig (sort $vdb->get_modules_signals($top_module)) {
-	my ($line,$a_line,$i_line,$type,$file,$posedge,$negedge,
-	 $type2,$s_file,$s_line,$range,$a_file,$i_file,$dims) = 
-	   $vdb->get_module_signal($top_module,$sig);
-
-		if($type eq "input" or $type eq "inout" or $type eq "output" ){
-		 
-		
-			
-			$ports{$sig}=remove_all_white_spaces($range);
-			
-		}
-	}
-	return %ports;
+    my ($vdb,$top_module)=@_;
+    my %ports;
+    foreach my $sig (sort $vdb->get_modules_signals($top_module)) {
+    my ($line,$a_line,$i_line,$type,$file,$posedge,$negedge,
+    $type2,$s_file,$s_line,$range,$a_file,$i_file,$dims) = 
+    $vdb->get_module_signal($top_module,$sig);
+        if($type eq "input" or $type eq "inout" or $type eq "output" ){
+            $ports{$sig}=remove_all_white_spaces($range);
+        }
+    }
+    return %ports;
 }
 
 
-
-
 sub get_param_list_in_order {
-   my $ref =shift;
-   return undef if (!defined $ref);
-   my %param=%{$ref};
-   my @array = sort keys %param;
-   my $l= scalar @array;
-   SCAN: {
-   foreach my $i (0..($l-2)) {     
-      my $str1=$array[$i];
-      foreach my $j ($i+1..($l-1)) {
-      my $str2=$array[$j];
-       	if ($param{$str1} =~ /\b$str2\b/ ) {
-      	
-        my $tmp = $array[$i];
-        $array[$i] =$array[$j];
-	$array[$j]=$tmp;
-        
-        redo SCAN;
-      }
+    my $ref =shift;
+    return undef if (!defined $ref);
+    my %param=%{$ref};
+    my @array = sort keys %param;
+    my $l= scalar @array;
+    SCAN: {
+        foreach my $i (0..($l-2)) {
+            my $str1=$array[$i];
+            foreach my $j ($i+1..($l-1)) {
+                my $str2=$array[$j];
+                if ($param{$str1} =~ /\b$str2\b/ ) {
+                    my $tmp = $array[$i];
+                    $array[$i] =$array[$j];
+                    $array[$j]=$tmp;
+                    redo SCAN;
+                }
+            }
+        }
     }
-    }
-  }
-
-  return @array;
+    return @array;
 }
 
 sub gen_verilator_makefile{
-	my ($top_ref,$target_dir) =@_;
-	my %tops = %{$top_ref};
-	my $p='';
-	my $q='';
-	my $h='';
-	my $l;
-	my $lib_num=0;
-	my $all_lib="";
-	foreach my $top (sort keys %tops) {
-		$p = "$p ${top}__ALL.a ";
-		$q = $q."lib$lib_num:\n\t\$(MAKE) -f ${top}.mk\n"; 
-		$h = "$h ${top}.h "; 
-		$l = $top;
-		$all_lib=$all_lib." lib$lib_num";
-		$lib_num++;
-	}
-
-	my $make= "
-	
+    my ($top_ref,$target_dir) =@_;
+    my %tops = %{$top_ref};
+    my $p='';
+    my $q='';
+    my $h='';
+    my $l;
+    my $lib_num=0;
+    my $all_lib="";
+    foreach my $top (sort keys %tops) {
+        $p = "$p ${top}__ALL.a ";
+        $q = $q."lib$lib_num:\n\t\$(MAKE) -f ${top}.mk\n"; 
+        $h = "$h ${top}.h "; 
+        $l = $top;
+        $all_lib=$all_lib." lib$lib_num";
+        $lib_num++;
+    }
+    my $make= "
 default: sim
-
-
-
 include $l.mk
 
 lib: $all_lib
-
 $q
 
-
 #######################################################################
 # Compile flags
 
 CPPFLAGS += -DVL_DEBUG=1
-ifeq (\$(CFG_WITH_CCWARN),yes)	# Local... Else don't burden users
+ifeq (\$(CFG_WITH_CCWARN),yes)    # Local... Else don't burden users
 CPPFLAGS += -DVL_THREADED=1
 CPPFLAGS += -W -Werror -Wall
 endif
@@ -225,135 +190,112 @@ sub gen_verilator_makefile{
 # Linking final exe -- presumes have a sim_main.cpp
 
 
-sim:	testbench.o \$(VK_GLOBAL_OBJS) $p \$(SLIB)
-	\$(LINK) \$(LDFLAGS) -g \$^ \$(LOADLIBES) \$(LDLIBS) -o testbench \$(LIBS) -Wall -O3 -lpthread 2>&1 | c++filt
+sim:    testbench.o \$(VK_GLOBAL_OBJS) $p \$(SLIB)
+\t\$(LINK) \$(LDFLAGS) -g \$^ \$(LOADLIBES) \$(LDLIBS) -o testbench \$(LIBS) -Wall -O3 -lpthread 2>&1 | c++filt
 
 testbench.o: testbench.cpp $h  \$(HLIB)
 
 clean:
-	rm *.o *.a testbench	
+\trm *.o *.a testbench
 ";
 
 save_file ($target_dir,$make);
-
-}	
+}
 
 
 ####################
-#	 file
+#     file
 ##################
-
-
 sub append_text_to_file {
-	my  ($file_path,$text)=@_;
-	open(my $fd, ">>$file_path") or die "could not open $file_path: $!";
-	print $fd $text;
-	close $fd;
+    my  ($file_path,$text)=@_;
+    open(my $fd, ">>$file_path") or die "could not open $file_path: $!";
+    print $fd $text;
+    close $fd;
 }
 
-
-
-
 sub save_file {
-	my  ($file_path,$text)=@_;
-	open my $fd, ">$file_path" or die "could not open $file_path: $!";
-	print $fd $text;
-	close $fd;	
+    my  ($file_path,$text)=@_;
+    open my $fd, ">$file_path" or die "could not open $file_path: $!";
+    print $fd $text;
+    close $fd;
 }
 
 sub load_file {
-	my $file_path=shift;
-	my $str;
-	if (-f "$file_path") { 
-				
-		$str = do {
-	    		local $/ = undef;
-	    		open my $fh, "<", $file_path
-			or die "could not open $file_path: $!";
-	    		<$fh>;
-		};
-
-	}
-	return $str;
+    my $file_path=shift;
+    my $str;
+    if (-f "$file_path") { 
+        $str = do {
+            local $/ = undef;
+            open my $fh, "<", $file_path  or die "could not open $file_path: $!";
+            <$fh>;
+        };
+    }
+    return $str;
 }
 
 sub merg_files {
-	my  ($source_file_path,$dest_file_path)=@_;
-	local $/=undef;
-  	open FILE, $source_file_path or die "Couldn't open file: $!";
-  	my $string = <FILE>;
-  	close FILE;
-	 append_text_to_file ($dest_file_path,$string);	
+    my  ($source_file_path,$dest_file_path)=@_;
+    local $/=undef;
+    open FILE, $source_file_path or die "Couldn't open file: $!";
+    my $string = <FILE>;
+    close FILE;
+    append_text_to_file ($dest_file_path,$string);    
 }
 
-
-
 sub copy_file_and_folders{
-	my ($file_ref,$project_dir,$target_dir)=@_;
-
-	foreach my $f(@{$file_ref}){
-		my $name= basename($f);	
-				
-		my $n="$project_dir$f";
-		if (-f "$n") { #copy file
-			copy ("$n","$target_dir/$name"); 		
-		}elsif(-f "$f" ){
-			copy ("$f","$target_dir/$name");     			 	
-		}elsif (-d "$n") {#copy folder
-			dircopy ("$n","$target_dir/$name"); 		
-		}elsif(-d "$f" ){
-			dircopy ("$f","$target_dir/$name"); 		
-    			 	
-		}
-	}
-
+    my ($file_ref,$project_dir,$target_dir)=@_;
+    foreach my $f(@{$file_ref}){
+        my $name= basename($f);
+        my $n="$project_dir$f";
+        if (-f "$n") { #copy file
+            copy ("$n","$target_dir/$name");
+        }elsif(-f "$f" ){
+            copy ("$f","$target_dir/$name");
+        }elsif (-d "$n") {#copy folder
+            dircopy ("$n","$target_dir/$name");
+        }elsif(-d "$f" ){
+            dircopy ("$f","$target_dir/$name");
+        }
+    }
 }
 
-
 sub remove_file_and_folders{
-	my ($file_ref,$project_dir)=@_;
-
-	foreach my $f(@{$file_ref}){
-		my $name= basename($f);				
-		my $n="$project_dir$f";
-		if (-f "$n") { #copy file
-			unlink ("$n");
-		}elsif(-f "$f" ){
-			unlink ("$f");     			 	
-		}elsif (-d "$n") {#copy folder
-			rmtree ("$n");
-		}elsif(-d "$f" ){
-			rmtree ("$f");    			 	
-		}
-	}
-
+    my ($file_ref,$project_dir)=@_;
+    foreach my $f(@{$file_ref}){
+        my $name= basename($f);
+        my $n="$project_dir$f";
+        if (-f "$n") { #copy file
+            unlink ("$n");
+        }elsif(-f "$f" ){
+            unlink ("$f");
+        }elsif (-d "$n") {#copy folder
+            rmtree ("$n");
+        }elsif(-d "$f" ){
+            rmtree ("$f");
+        }
+    }
 }
 
 sub read_file_cntent {
-	my ($f,$project_dir)=@_;
-	my $n="$project_dir$f";
-	my $str;
-	if (-f "$n") { 
-				
-		$str = do {
-	    		local $/ = undef;
-	    		open my $fh, "<", $n
-			or die "could not open $n: $!";
-	    		<$fh>;
-		};
-
-	}elsif(-f "$f" ){
-		$str = do {
-	    		local $/ = undef;
-	    		open my $fh, "<", $f
-			or die "could not open $f: $!";
-	    		<$fh>;
-		};
-		
-						 	
-	}
-	return $str;
-
+    my ($f,$project_dir)=@_;
+    my $n="$project_dir$f";
+    my $str;
+    if (-f "$n") { 
+        $str = do {
+                local $/ = undef;
+                open my $fh, "<", $n
+            or die "could not open $n: $!";
+                <$fh>;
+        };
+    }elsif(-f "$f" ){
+        $str = do {
+                local $/ = undef;
+                open my $fh, "<", $f
+            or die "could not open $f: $!";
+                <$fh>;
+        };
+    }
+    return $str;
 }
 
 
@@ -362,9 +304,9 @@ sub check_file_has_string {
     my $r;
     open(FILE,$file);
     if (grep{/$string/} <FILE>){
-       $r= 1; #print "word  found\n";
+        $r= 1; #print "word  found\n";
     }else{
-       $r= 0; #print "word not found\n";
+        $r= 0; #print "word not found\n";
     }
     close FILE;
     return $r;
@@ -372,11 +314,11 @@ sub check_file_has_string {
 
 #return lines containig pattern in a givn file
 sub unix_grep {
-	my ($file,$pattern)=@_;
+    my ($file,$pattern)=@_;
     open(FILE,$file);
     my @arr = <FILE>;
     my @lines = grep /$pattern/, @arr;
-	return @lines;	
+    return @lines;    
 }
 
 
@@ -385,74 +327,61 @@ sub count_file_line_num {
     open(FILE,$file);
     my $n=0;
     while (my $line = <FILE>) {
-	   $n++;
-	}
+        $n++;
+    }
     close FILE;
     return $n;
 }
 
 sub set_path_env{
-	my $project_dir	  = get_project_dir(); #mpsoc dir addr
-	my $paths_file= "$project_dir/mpsoc/perl_gui/lib/Paths";
-	#print "$paths_file\n";
-	my $paths= do $paths_file;
-	my $pronoc_work =object_get_attribute($paths,"PATH","PRONOC_WORK");	
-	my $quartus = object_get_attribute($paths,"PATH","QUARTUS_BIN");
-	my $vivado  = object_get_attribute($paths,"PATH","VIVADO_BIN");
-	my $sdk     = object_get_attribute($paths,"PATH","SDK_BIN");
-		
-	my $modelsim = object_get_attribute($paths,"PATH","MODELSIM_BIN");
-	$ENV{'PRONOC_WORK'}= $pronoc_work if( defined $pronoc_work);
-	$ENV{'QUARTUS_BIN'}= $quartus if( defined $quartus);
-	$ENV{'VIVADO_BIN'}= $vivado if( defined $vivado);
-	$ENV{'SDK_BIN'}= $vivado if( defined $sdk);
-	$ENV{'MODELSIM_BIN'}= $modelsim if( defined $modelsim);	
-	
-	if( defined $pronoc_work){if(-d $pronoc_work ){
-			mkpath("$pronoc_work/emulate",1,01777) unless -d "$pronoc_work/emulate";
-			mkpath("$pronoc_work/simulate",1,01777) unless -d "$pronoc_work/simulate";	
-			mkpath("$pronoc_work/tmp",1,01777) unless -d "$pronoc_work/tmp";			
-	}}
-	
-	#add quartus_bin to PATH linux environment if it does not exist in PATH
-	my $add;
-	if( defined $quartus){
-		my @q =split  (/:/,$ENV{'PATH'});
-		my $p=get_scolar_pos ($quartus,@q);
-		$ENV{'PATH'}= $ENV{'PATH'}.":$quartus" unless ( defined $p); 
-		$add=(defined $add)? $add.":$quartus" : $quartus unless ( defined $p);
-		
-	}
-	
-	if( defined $vivado){
-		my @q =split  (/:/,$ENV{'PATH'});
-		my $p=get_scolar_pos ($vivado,@q);
-		$ENV{'PATH'}= $ENV{'PATH'}.":$vivado" unless ( defined $p); 
-		$add=(defined $add)? $add.":$vivado" : $vivado unless ( defined $p);
-		
-	}
-	
-	if( defined $sdk){
-		my @q =split  (/:/,$ENV{'PATH'});
-		my $p=get_scolar_pos ($sdk,@q);
-		$ENV{'PATH'}= $ENV{'PATH'}.":$sdk" unless ( defined $p); 
-		$add=(defined $add)? $add.":$sdk" : $sdk unless ( defined $p);
-		   
-	}
-	if(defined $add){
-		print GREEN, "Info: $add has been added to linux PATH envirement.\n",RESET,"\n";
-		
-	}
-	
-	
+    my $project_dir      = get_project_dir(); #mpsoc dir addr
+    my $paths_file= "$project_dir/mpsoc/perl_gui/lib/Paths";
+    #print "$paths_file\n";
+    my $paths= do $paths_file;
+    my $pronoc_work =object_get_attribute($paths,"PATH","PRONOC_WORK");    
+    my $quartus = object_get_attribute($paths,"PATH","QUARTUS_BIN");
+    my $vivado  = object_get_attribute($paths,"PATH","VIVADO_BIN");
+    my $sdk     = object_get_attribute($paths,"PATH","SDK_BIN");
+    my $modelsim = object_get_attribute($paths,"PATH","MODELSIM_BIN");
+    $ENV{'PRONOC_WORK'}= $pronoc_work if( defined $pronoc_work);
+    $ENV{'QUARTUS_BIN'}= $quartus if( defined $quartus);
+    $ENV{'VIVADO_BIN'}= $vivado if( defined $vivado);
+    $ENV{'SDK_BIN'}= $vivado if( defined $sdk);
+    $ENV{'MODELSIM_BIN'}= $modelsim if( defined $modelsim);    
+    if( defined $pronoc_work){if(-d $pronoc_work ){
+            mkpath("$pronoc_work/emulate",1,01777) unless -d "$pronoc_work/emulate";
+            mkpath("$pronoc_work/simulate",1,01777) unless -d "$pronoc_work/simulate";    
+            mkpath("$pronoc_work/tmp",1,01777) unless -d "$pronoc_work/tmp";            
+    }}
+    #add quartus_bin to PATH linux environment if it does not exist in PATH
+    my $add;
+    if( defined $quartus){
+        my @q =split  (/:/,$ENV{'PATH'});
+        my $p=get_scolar_pos ($quartus,@q);
+        $ENV{'PATH'}= $ENV{'PATH'}.":$quartus" unless ( defined $p); 
+        $add=(defined $add)? $add.":$quartus" : $quartus unless ( defined $p);
+    }
+    if( defined $vivado){
+        my @q =split  (/:/,$ENV{'PATH'});
+        my $p=get_scolar_pos ($vivado,@q);
+        $ENV{'PATH'}= $ENV{'PATH'}.":$vivado" unless ( defined $p); 
+        $add=(defined $add)? $add.":$vivado" : $vivado unless ( defined $p);
+    }
+    if( defined $sdk){
+        my @q =split  (/:/,$ENV{'PATH'});
+        my $p=get_scolar_pos ($sdk,@q);
+        $ENV{'PATH'}= $ENV{'PATH'}.":$sdk" unless ( defined $p); 
+        $add=(defined $add)? $add.":$sdk" : $sdk unless ( defined $p);
+    }
+    if(defined $add){
+        print GREEN, "Info: $add has been added to linux PATH envirement.\n",RESET,"\n";
+    }
 }
 
 
-
 sub source_file {
     my $file = shift;
     open my $fh, "<", $file   or return  "could not open $file: $!";
-
     while (<$fh>) {
         chomp;
         #FIXME: this regex isn't quite good enough
@@ -462,176 +391,119 @@ sub source_file {
     return undef;
 }
 
-
-##############
-#  clone_obj
-#############
-
-sub clone_obj{
-	my ($self,$clone)=@_;
-	
-	foreach my $p (keys %$self){
-		delete ($self->{$p});
-	}
-	foreach my $p (keys %$clone){
-		$self->{$p}= $clone->{$p};
-		my $ref= ref ($clone->{$p});
-		if( $ref eq 'HASH' ){
-			
-			foreach my $q (keys %{$clone->{$p}}){
-				$self->{$p}{$q}= $clone->{$p}{$q};	
-				my $ref= ref ($self->{$p}{$q});
-				if( $ref eq 'HASH' ){
-				
-					foreach my $z (keys %{$clone->{$p}{$q}}){
-						$self->{$p}{$q}{$z}= $clone->{$p}{$q}{$z};	
-						my $ref= ref ($self->{$p}{$q}{$z});
-						if( $ref eq 'HASH' ){
-							
-							foreach my $w (keys %{$clone->{$p}{$q}{$z}}){
-								$self->{$p}{$q}{$z}{$w}= $clone->{$p}{$q}{$z}{$w};	
-								my $ref= ref ($self->{$p}{$q}{$z}{$w});
-								if( $ref eq 'HASH' ){
-									
-							
-									foreach my $m (keys %{$clone->{$p}{$q}{$z}{$w}}){
-										$self->{$p}{$q}{$z}{$w}{$m}= $clone->{$p}{$q}{$z}{$w}{$m};	
-										my $ref= ref ($self->{$p}{$q}{$z}{$w}{$m});
-										if( $ref eq 'HASH' ){
-											
-											foreach my $n (keys %{$clone->{$p}{$q}{$z}{$w}{$m}}){
-												$self->{$p}{$q}{$z}{$w}{$m}{$n}= $clone->{$p}{$q}{$z}{$w}{$m}{$n};	
-												my $ref= ref ($self->{$p}{$q}{$z}{$w}{$m}{$n});	
-												if( $ref eq 'HASH' ){
-												
-													foreach my $l (keys %{$clone->{$p}{$q}{$z}{$w}{$m}{$n}}){
-														$self->{$p}{$q}{$z}{$w}{$m}{$n}{$l}= $clone->{$p}{$q}{$z}{$w}{$m}{$n}{$l};	
-														my $ref= ref ($self->{$p}{$q}{$z}{$w}{$m}{$n}{$l});	
-														if( $ref eq 'HASH' ){
-														}
-													}
-												
-												}#if														
-											}#n
-										}#if
-									}#m							
-								}#if
-							}#w
-						}#if
-					}#z
-				}#if
-			}#q
-		}#if	
-	}#p
-}#sub	
-
+sub clone_obj {
+    my ($self, $clone) = @_;
+    # Clear the object
+    %$self = ();
+    # Recursively copy the structure
+    sub deep_clone {
+        my $src = shift;
+        return { map { $_ => (ref $src->{$_} eq 'HASH' ? deep_clone($src->{$_}) : $src->{$_}) } keys %$src };
+    }
+    %$self = %{ deep_clone($clone) };
+}
 
 sub get_project_dir{ #mpsoc directory address
-	my $dir = Cwd::getcwd();
-	my @p=	split('/perl_gui',$dir);
-	@p=	split('/Integration_test',$p[0]);
-    my $d	  = abs_path("$p[0]/../"); 
-     
-	return $d;
+    my $dir = Cwd::getcwd();
+    my @p=    split('/perl_gui',$dir);
+    @p=    split('/Integration_test',$p[0]);
+    my $d      = abs_path("$p[0]/../"); 
+    return $d;
 }
 
 sub cut_dir_path{ 
-	my ($dir,$folder_name) = @_;
-	my @p=  split (/\/$folder_name\//,$dir);
-	return $p[-1];
+    my ($dir,$folder_name) = @_;
+    my @p=  split (/\/$folder_name\//,$dir);
+    return $p[-1];
 }
 
-
 sub remove_project_dir_from_addr{
-	my $file=shift;	
-	my $project_dir	  = get_project_dir(); 
-	$file =~ s/$project_dir//; 
-	return $file;	
+    my $file=shift;    
+    my $project_dir      = get_project_dir(); 
+    $file =~ s/$project_dir//; 
+    return $file;    
 }
 
 sub add_project_dir_to_addr{
-	my $file=shift;
-	my $project_dir	  = get_project_dir(); 
-	return $file if(-f $file ); 
-	return "$project_dir/$file";	
-	
+    my $file=shift;
+    my $project_dir      = get_project_dir(); 
+    return $file if(-f $file ); 
+    return "$project_dir/$file";    
+    
 }
 
 sub get_full_path_addr{
-	my $file=shift;
-	my $dir = Cwd::getcwd();
-	my $full_path = "$dir/$file";	
-	return $full_path  if -f ($full_path );
-	return $file;
+    my $file=shift;
+    my $dir = Cwd::getcwd();
+    my $full_path = "$dir/$file";    
+    return $full_path  if -f ($full_path );
+    return $file;
 }
 
 sub regen_object {
-	my $path=shift;
-	$path = get_full_path_addr($path);
-	my $pp= eval { do $path };
-	my $r= ($@ || !defined $pp);
-	return ($pp,$r,$@);
+    my $path=shift;
+    $path = get_full_path_addr($path);
+    my $pp= eval { do $path };
+    my $r= ($@ || !defined $pp);
+    return ($pp,$r,$@);
 }
 
 
 ################
-#	general
+#    general
 #################
-
 sub remove_not_hex {
-	my $s=shift;
-	$s =~ s/[^0-9a-fA-F]//g;
-	return $s;	
+    my $s=shift;
+    $s =~ s/[^0-9a-fA-F]//g;
+    return $s; 
 }
 
 sub remove_not_number {
-	my $s=shift;
-	$s =~ s/[^0-9]//g;
-	return $s;		
-	
+    my $s=shift;
+    $s =~ s/[^0-9]//g;
+    return $s; 
 }
 
 sub  trim { my $s = shift;  $s=~s/[\n]//gs; return $s };
 
 sub remove_all_white_spaces($)
 {
-  my $string = shift;
-  $string =~ s/\s+//g;
-  return $string;
+    my $string = shift;
+    $string =~ s/\s+//g;
+    return $string;
 }
 
 
 sub check_scolar_exist_in_array{
-	my ($value,$ref)=@_;
-	my @array= @{$ref};
-	if ( grep( /^\Q$value\E$/, @array ) ) {
-	  return 1;
-	}
-	return 0
+    my ($value,$ref)=@_;
+    my @array= @{$ref};
+    if ( grep( /^\Q$value\E$/, @array ) ) {
+        return 1;
+    }
+    return 0
 }
 
 sub get_item_pos{#if not in return 0
-		my ($item,@list)=@_;
-		my $pos=0;
-		foreach my $p (@list){
-				#print "$p eq $item\n";
-				if ($p eq $item){return $pos;}
-				$pos++;
-		}	
-		return 0;
-	
-}	
+        my ($item,@list)=@_;
+        my $pos=0;
+        foreach my $p (@list){
+            #print "$p eq $item\n";
+            if ($p eq $item){return $pos;}
+            $pos++;
+        }
+        return 0;
+} 
 
 sub get_scolar_pos{
-	my ($item,@list)=@_;
-	my $pos;
-	my $i=0;
-	foreach my $c (@list)
-	{
-		if(  $c eq $item) {$pos=$i}
-		$i++;
-	}	
-	return $pos;	
+    my ($item,@list)=@_;
+    my $pos;
+    my $i=0;
+    foreach my $c (@list)
+    {
+        if(  $c eq $item) {$pos=$i}
+        $i++;
+    }    
+    return $pos;
 }
 
 sub get_pos{
@@ -641,738 +513,659 @@ sub get_pos{
                 #print "$p eq $item\n";
                 if ($p eq $item){return $pos;}
                 $pos++;
-        }    
+        }
         return undef;
-}    	
+} 
 
 sub remove_scolar_from_array{
-	my ($array_ref,$item)=@_;
-	my @array=@{$array_ref};
-	my @new;
-	foreach my $p (@array){
-		if($p ne $item ){
-			push(@new,$p);
-		}		
-	}
-	return @new;	
+    my ($array_ref,$item)=@_;
+    my @array=@{$array_ref};
+    my @new;
+    foreach my $p (@array){
+        if($p ne $item ){
+            push(@new,$p);
+        }
+    }
+    return @new;
 }
 
 sub replace_in_array{
-	my ($array_ref,$item1,$item2)=@_;
-	my @array=@{$array_ref};
-	my @new;
-	foreach my $p (@array){
-		if($p eq $item1 ){
-			push(@new,$item2);
-		}else{
-			push(@new,$p);
-		}		
-	}
-	return @new;	
+    my ($array_ref,$item1,$item2)=@_;
+    my @array=@{$array_ref};
+    my @new;
+    foreach my $p (@array){
+        if($p eq $item1 ){
+            push(@new,$item2);
+        }else{
+            push(@new,$p);
+        }
+    }
+    return @new;
 }
 
-
-
 # return an array of common elemnts between two input arays 
 sub get_common_array{
-	my ($a_ref,$b_ref)=@_;
-	my @A=@{$a_ref};
-	my @B=@{$b_ref};
-	my @C;
-	foreach my $p (@A){
-		if( grep (/^\Q$p\E$/,@B)){push(@C,$p)};
-	}
-	return  @C;	
+    my ($a_ref,$b_ref)=@_;
+    my @A=@{$a_ref};
+    my @B=@{$b_ref};
+    my @C;
+    foreach my $p (@A){
+        if( grep (/^\Q$p\E$/,@B)){push(@C,$p)};
+    }
+    return  @C;
 }
 
 #a-b
 sub get_diff_array{
-	my ($a_ref,$b_ref)=@_;
-	my @A=@{$a_ref};
-	my @B=@{$b_ref};
-	my @C;
-	foreach my $p (@A){
-		if( !grep  (/^\Q$p\E$/,@B)){push(@C,$p)};
-	}
-	return  @C;	
-	
+    my ($a_ref,$b_ref)=@_;
+    my @A=@{$a_ref};
+    my @B=@{$b_ref};
+    my @C;
+    foreach my $p (@A){
+        if( !grep  (/^\Q$p\E$/,@B)){push(@C,$p)};
+    }
+    return  @C;    
+    
 }
 
 
 sub return_not_unique_names_in_array{
-	my @array = @_;
-	my %seen;
-	my @r;
-	foreach my $value (@array) {
-  		if (! $seen{$value}) {
-    		$seen{$value} = 1;
-  		}else{
-  			push(@r,$value);
-  		}
-	}
-	return @r;
+    my @array = @_;
+    my %seen;
+    my @r;
+    foreach my $value (@array) {
+        if (! $seen{$value}) {
+            $seen{$value} = 1;
+        }else{
+            push(@r,$value);
+        }
+    }
+    return @r;
 }
 
-
 sub compress_nums{
-	my 	@nums=@_;
-	my @f=sort { $a <=> $b } @nums;
-	my $s;
-	my $ls;	
-	my $range=0;
-	my $x;	
-	
-
-	foreach my $p (@f){
-		if(!defined $x) {
-			$s="$p";
-			$ls=$p;		
-			
-		}
-		else{ 
-			if($p-$x>1){ #gap exist
-				if( $range){
-					$s=($x-$ls>1 )? "$s:$x,$p": "$s,$x,$p";
-					$ls=$p;
-					$range=0;
-				}else{
-				$s= "$s,$p";
-				$ls=$p;
-
-				}
-			
-			}else {$range=1;}
-
-
-		
-		}
-	
-		$x=$p
-	}
- 	if($range==1){ $s= ($x-$ls>1 )? "$s:$x":  "$s,$x";}
-	#update $s($ls,$hs);
-
-	return $s;
-	
+    my     @nums=@_;
+    my @f=sort { $a <=> $b } @nums;
+    my $s;
+    my $ls;
+    my $range=0;
+    my $x;
+    foreach my $p (@f){
+        if(!defined $x) {
+            $s="$p";
+            $ls=$p;
+        }
+        else{ 
+            if($p-$x>1){ #gap exist
+                if( $range){
+                    $s=($x-$ls>1 )? "$s:$x,$p": "$s,$x,$p";
+                    $ls=$p;
+                    $range=0;
+                }else{
+                $s= "$s,$p";
+                $ls=$p;
+                }
+            }else {$range=1;}
+        }
+        $x=$p
+    }
+    if($range==1){ $s= ($x-$ls>1 )? "$s:$x":  "$s,$x";}
+    #update $s($ls,$hs);
+    return $s;
 }
 
-
-
 sub metric_conversion{
-	my $size=shift;	
-	my $size_text=	$size<=0	 ? 'Error ': 
-			$size<(1 << 10)? $size:
-			$size<(1 << 20)? join (' ', ($size>>10,"K")) :
-			$size<(1 << 30)? join (' ', ($size>>20,"M")) :
-					 join (' ', ($size>>30,"G")) ;
+    my $size=shift;    
+    my $size_text=    $size<=0     ? 'Error ': 
+            $size<(1 << 10)? $size:
+            $size<(1 << 20)? join (' ', ($size>>10,"K")) :
+            $size<(1 << 30)? join (' ', ($size>>20,"M")) :
+            join (' ', ($size>>30,"G")) ;
 return $size_text;
 }
 
-
-
-
-
 ######
 #  state
 #####
 sub set_gui_status{
-	my ($object,$status,$timeout)=@_;
-	$object->object_add_attribute('gui_status','status',$status);
-	$object->object_add_attribute('gui_status','timeout',$timeout);
-}	
-
+    my ($object,$status,$timeout)=@_;
+    $object->object_add_attribute('gui_status','status',$status);
+    $object->object_add_attribute('gui_status','timeout',$timeout);
+}
 
 sub get_gui_status{
-	my ($object)=@_;
-	my $status= $object->object_get_attribute('gui_status','status');
-	my $timeout=$object->object_get_attribute('gui_status','timeout');
-	return ($status,$timeout);	
+    my ($object)=@_;
+    my $status= $object->object_get_attribute('gui_status','status');
+    my $timeout=$object->object_get_attribute('gui_status','timeout');
+    return ($status,$timeout);    
 }
 
 
-
-
 ###########
 #  color
 #########
-
-
-	
 sub get_color {
-	my $num=shift;
-	
-	my @colors=(
-	0x6495ED,#Cornflower Blue
-	0xFAEBD7,#Antiquewhite
-	0xC71585,#Violet Red
-	0xC0C0C0,#silver
-	0xADD8E6,#Lightblue	
-	0x6A5ACD,#Slate Blue
-	0x00CED1,#Dark Turquoise
-	0x008080,#Teal
-	0x2E8B57,#SeaGreen
-	0xFFB6C1,#Light Pink
-	0x008000,#Green
-	0xFF0000,#red
-	0x808080,#Gray
-	0x808000,#Olive
-	0xFF69B4,#Hot Pink
-	0xFFD700,#Gold
-	0xDAA520,#Goldenrod
-	0xFFA500,#Orange
-	0x32CD32,#LimeGreen
-	0x0000FF,#Blue
-	0xFF8C00,#DarkOrange
-	0xA0522D,#Sienna
-	0xFF6347,#Tomato
-	0x0000CD,#Medium Blue
-	0xFF4500,#OrangeRed
-	0xDC143C,#Crimson	
-	0x9932CC,#Dark Orchid
-	0x800000,#marron
-	0x800080,#Purple
-	0x4B0082,#Indigo
-	0xFFFFFF,#white	
-	0x000000, #Black		
-		#heatmap
-	0xbdff00, #	(189,255,0)
-	0xe3f018, #	(227,240,24)
-	0xffce00, #	(255,206,0)
-	0xff6612, #	(255,102,18)
-	0xc12424, #	(193,36,36)
-		);
-	
-	my $color= 	($num< scalar (@colors))? $colors[$num]: 0xFFFFFF;	
-	my $red= 	($color & 0xFF0000) >> 8;
-	my $green=	($color & 0x00FF00);
-	my $blue=	($color & 0x0000FF) << 8;
-	
-	return ($red,$green,$blue);
-	
+    my $num=shift;
+    my @colors=(
+    0x6495ED,#Cornflower Blue
+    0xFAEBD7,#Antiquewhite
+    0xC71585,#Violet Red
+    0xC0C0C0,#silver
+    0xADD8E6,#Lightblue    
+    0x6A5ACD,#Slate Blue
+    0x00CED1,#Dark Turquoise
+    0x008080,#Teal
+    0x2E8B57,#SeaGreen
+    0xFFB6C1,#Light Pink
+    0x008000,#Green
+    0xFF0000,#red
+    0x808080,#Gray
+    0x808000,#Olive
+    0xFF69B4,#Hot Pink
+    0xFFD700,#Gold
+    0xDAA520,#Goldenrod
+    0xFFA500,#Orange
+    0x32CD32,#LimeGreen
+    0x0000FF,#Blue
+    0xFF8C00,#DarkOrange
+    0xA0522D,#Sienna
+    0xFF6347,#Tomato
+    0x0000CD,#Medium Blue
+    0xFF4500,#OrangeRed
+    0xDC143C,#Crimson    
+    0x9932CC,#Dark Orchid
+    0x800000,#marron
+    0x800080,#Purple
+    0x4B0082,#Indigo
+    0xFFFFFF,#white    
+    0x000000, #Black        
+        #heatmap
+    0xbdff00, #    (189,255,0)
+    0xe3f018, #    (227,240,24)
+    0xffce00, #    (255,206,0)
+    0xff6612, #    (255,102,18)
+    0xc12424, #    (193,36,36)
+    );
+    
+    my $color=     ($num< scalar (@colors))? $colors[$num]: 0xFFFFFF;    
+    my $red=     ($color & 0xFF0000) >> 8;
+    my $green=    ($color & 0x00FF00);
+    my $blue=    ($color & 0x0000FF) << 8;
+    return ($red,$green,$blue);
 }
 
-
 sub get_color_hex_string {
-	my $num=shift;
-	
-	my @colors=(
-	"6495ED",#Cornflower Blue
-	"FAEBD7",#Antiquewhite
-	"C71585",#Violet Red
-	"C0C0C0",#silver
-	"ADD8E6",#Lightblue	
-	"6A5ACD",#Slate Blue
-	"00CED1",#Dark Turquoise
-	"008080",#Teal
-	"2E8B57",#SeaGreen
-	"FFB6C1",#Light Pink
-	"008000",#Green
-	"FF0000",#red
-	"808080",#Gray
-	"808000",#Olive
-	"FF69B4",#Hot Pink
-	"FFD700",#Gold
-	"DAA520",#Goldenrod
-	"FFA500",#Orange
-	"32CD32",#LimeGreen
-	"0000FF",#Blue
-	"FF8C00",#DarkOrange
-	"A0522D",#Sienna
-	"FF6347",#Tomato
-	"0000CD",#Medium Blue
-	"FF4500",#OrangeRed
-	"DC143C",#Crimson	
-	"9932CC",#Dark Orchid
-	"800000",#marron
-	"800080",#Purple
-	"4B0082",#Indigo
-	"FFFFFF",#white	
-	"000000", #Black	
-		#heatmap
-	"bdff00", #	(189,255,0)
-	"e3f018", #	(227,240,24)
-	"ffce00", #	(255,206,0)
-	"ff6612", #	(255,102,18)
-	"c12424", #	(193,36,36)
-	
-		
-		);
-	
-	my $color= 	($num< scalar (@colors))? $colors[$num]: "FFFFFF";	
-	return $color;
-	
+    my $num=shift;
+    my @colors=(
+    "6495ED",#Cornflower Blue
+    "FAEBD7",#Antiquewhite
+    "C71585",#Violet Red
+    "C0C0C0",#silver
+    "ADD8E6",#Lightblue    
+    "6A5ACD",#Slate Blue
+    "00CED1",#Dark Turquoise
+    "008080",#Teal
+    "2E8B57",#SeaGreen
+    "FFB6C1",#Light Pink
+    "008000",#Green
+    "FF0000",#red
+    "808080",#Gray
+    "808000",#Olive
+    "FF69B4",#Hot Pink
+    "FFD700",#Gold
+    "DAA520",#Goldenrod
+    "FFA500",#Orange
+    "32CD32",#LimeGreen
+    "0000FF",#Blue
+    "FF8C00",#DarkOrange
+    "A0522D",#Sienna
+    "FF6347",#Tomato
+    "0000CD",#Medium Blue
+    "FF4500",#OrangeRed
+    "DC143C",#Crimson    
+    "9932CC",#Dark Orchid
+    "800000",#marron
+    "800080",#Purple
+    "4B0082",#Indigo
+    "FFFFFF",#white    
+    "000000", #Black    
+        #heatmap
+    "bdff00", #    (189,255,0)
+    "e3f018", #    (227,240,24)
+    "ffce00", #    (255,206,0)
+    "ff6612", #    (255,102,18)
+    "c12424", #    (193,36,36)
+    );
+    my $color=     ($num< scalar (@colors))? $colors[$num]: "FFFFFF";    
+    return $color;
 }
 
 
-
-
-
 sub check_verilog_identifier_syntax {
-	my $in=shift;
-	my $error=0;
-	my $message='';
+    my $in=shift;
+    my $error=0;
+    my $message='';
 #check if $in is defined
-	if(!defined $in){
-		return "Identifier is not defined! An Identifier must begin with an alphabetic character.\n";	
-	}
+    if(!defined $in){
+        return "Identifier is not defined! An Identifier must begin with an alphabetic character.\n";    
+    }
 
-	if(length $in ==0){
-		return "Identifier length is zero! An Identifier must begin with an alphabetic character.\n";	
-	}
+    if(length $in ==0){
+        return "Identifier length is zero! An Identifier must begin with an alphabetic character.\n";    
+    }
 
 # an Identifiers must begin with an alphabetic character or the underscore character
-	if ($in =~ /^[0-9\$]/){
-		return "An Identifier must begin with an alphabetic character or the underscore character.\n";
-	}
-	
-
-#	Identifiers may contain alphabetic characters, numeric characters, the underscore, and the dollar sign (a-z A-Z 0-9 _ $ )
-	if ($in =~ /[^a-zA-Z0-9_\$]+/){
-		 #print "use of illegal character after\n" ;
-		 my @w= split /([^a-zA-Z0-9_\$]+)/, $in; 
-		 return "Contain illegal character of \"$w[1]\" after $w[0]. Identifiers may contain alphabetic characters, numeric characters, the underscore, and the dollar sign (a-z A-Z 0-9 _ \$ )\n";
-		
-	}
+    if ($in =~ /^[0-9\$]/){
+        return "An Identifier must begin with an alphabetic character or the underscore character.\n";
+    }
+    
 
+#    Identifiers may contain alphabetic characters, numeric characters, the underscore, and the dollar sign (a-z A-Z 0-9 _ $ )
+    if ($in =~ /[^a-zA-Z0-9_\$]+/){
+        #print "use of illegal character after\n" ;
+        my @w= split /([^a-zA-Z0-9_\$]+)/, $in; 
+        return "Contain illegal character of \"$w[1]\" after $w[0]. Identifiers may contain alphabetic characters, numeric characters, the underscore, and the dollar sign (a-z A-Z 0-9 _ \$ )\n";
+    }
 
 # check Verilog reserved words
-	my @keys =			("always","and","assign","automatic","begin","buf","bufif0","bufif1","case","casex","casez","cell","cmos","config","deassign","default","defparam","design","disable","edge","else","end","endcase","endconfig","endfunction","endgenerate","endmodule","endprimitive","endspecify","endtable","endtask","event","for","force","forever","fork","function","generate","genvar","highz0","highz1","if","ifnone","incdir","include","initial","inout","input","instance","integer","join","large","liblist","library","localparam","macromodule","medium","module","nand","negedge","nmos","nor","noshowcancelled","not","notif0","notif1","or","output","parameter","pmos","posedge","primitive","pull0","pull1","pulldown","pullup","pulsestyle_onevent","pulsestyle_ondetect","remos","real","realtime","reg","release","repeat","rnmos","rpmos","rtran","rtranif0","rtranif1","scalared","showcancelled","signed","small","specify","specparam","strong0","strong1","supply0","supply1","table","task","time","tran","tranif0","tranif1","tri","tri0","tri1","triand","trior","trireg","unsigned","use","vectored","wait","wand","weak0","weak1","while","wire","wor","xnor","xor");
-	if( grep (/^$in$/,@keys)){
-		return  "$in is a Verlig reserved word.\n";
-	}
-	return undef;
-	
+    my @keys =            ("always","and","assign","automatic","begin","buf","bufif0","bufif1","case","casex","casez","cell","cmos","config","deassign","default","defparam","design","disable","edge","else","end","endcase","endconfig","endfunction","endgenerate","endmodule","endprimitive","endspecify","endtable","endtask","event","for","force","forever","fork","function","generate","genvar","highz0","highz1","if","ifnone","incdir","include","initial","inout","input","instance","integer","join","large","liblist","library","localparam","macromodule","medium","module","nand","negedge","nmos","nor","noshowcancelled","not","notif0","notif1","or","output","parameter","pmos","posedge","primitive","pull0","pull1","pulldown","pullup","pulsestyle_onevent","pulsestyle_ondetect","remos","real","realtime","reg","release","repeat","rnmos","rpmos","rtran","rtranif0","rtranif1","scalared","showcancelled","signed","small","specify","specparam","strong0","strong1","supply0","supply1","table","task","time","tran","tranif0","tranif1","tri","tri0","tri1","triand","trior","trireg","unsigned","use","vectored","wait","wand","weak0","weak1","while","wire","wor","xnor","xor");
+    if( grep (/^$in$/,@keys)){
+        return  "$in is a Verlig reserved word.\n";
+    }
+    return undef;
 }
 
-
 sub capture_number_after {
-	my ($after,$text)=@_;
-	my @q =split  (/$after/,$text);
-	#my $d=$q[1];
-	my @d = split (/[^0-9. ]/,$q[1]);
-	return $d[0]; 
-
+    my ($after,$text)=@_;
+    my @q =split  (/$after/,$text);
+    #my $d=$q[1];
+    my @d = split (/[^0-9. ]/,$q[1]);
+    return $d[0]; 
 }
 
 sub capture_string_between {
-	my ($start,$text,$end)=@_;
-	my @q =split  (/$start/,$text);
-	my @d = split (/$end/,$q[1]);
-	return $d[0];
+    my ($start,$text,$end)=@_;
+    my @q =split  (/$start/,$text);
+    my @d = split (/$end/,$q[1]);
+    return $d[0];
 }
 
 sub capture_cores_data {
-	my ($data,$text)=@_;
-	my %result;
-	my @q =split  (/End_point/,$text);
-	my $i=0;
-	foreach my $p (@q){
-		if ($i!=0){
-			my @d = split (/[^0-9. ]/,$p);
-			my $n=	$d[0];
-			my $val = capture_number_after("$data",$p);
-			$result{remove_all_white_spaces($n)}=remove_all_white_spaces($val);
-		}
-		$i++;
-	}	
-	return %result; 
+    my ($data,$text)=@_;
+    my %result;
+    my @q =split  (/End_point/,$text);
+    my $i=0;
+    foreach my $p (@q){
+        if ($i!=0){
+            my @d = split (/[^0-9. ]/,$p);
+            my $n=    $d[0];
+            my $val = capture_number_after("$data",$p);
+            $result{remove_all_white_spaces($n)}=remove_all_white_spaces($val);
+        }
+        $i++;
+    }    
+    return %result; 
 }
 
 sub make_undef_as_string {
-	foreach my $p  (@_){
-		$$p= 'undef' if (! defined $$p);
-		
-	}	
+    foreach my $p  (@_){
+        $$p= 'undef' if (! defined $$p);
+        
+    }    
 }
 
 sub powi{ # x^y
-	my ($x,$y)=@_; # compute x to the y
-	my $r=1;
-	for (my $i = 0; $i < $y; ++$i ) {
-    	$r *= $x;
-  	}
-  return $r;
+    my ($x,$y)=@_; # compute x to the y
+    my $r=1;
+    for (my $i = 0; $i < $y; ++$i ) {
+        $r *= $x;
+    }
+    return $r;
 }
 
 sub sum_powi{ # x^(y-1) + x^(y-2) + ...+ 1;
-	my ($x,$y)=@_; # compute x to the y
-	my $r = 0;
+    my ($x,$y)=@_; # compute x to the y
+    my $r = 0;
     for (my $i = 0; $i < $y; $i++){
-    	$r += powi( $x, $i );
+        $r += powi( $x, $i );
     }
-  	return $r;
-}	
-
-
-
+    return $r;
+} 
 
 
 #############
 # object
 ############
-
 sub object_add_attribute{
-	my ($self,$attribute1,$attribute2,$value)=@_;
-	if(!defined $attribute2){$self->{$attribute1}=$value;}
-	else {$self->{$attribute1}{$attribute2}=$value;}
-
+    my ($self,$attribute1,$attribute2,$value)=@_;
+    if(!defined $attribute2){$self->{$attribute1}=$value;}
+    else {$self->{$attribute1}{$attribute2}=$value;}
 }
 
-
-
 sub object_get_attribute{
-	my ($self,$attribute1,$attribute2)=@_;
-	if(!defined $attribute2) {return $self->{$attribute1};}
-	return $self->{$attribute1}{$attribute2};
+    my ($self,$attribute1,$attribute2)=@_;
+    if(!defined $attribute2) {return $self->{$attribute1};}
+    return $self->{$attribute1}{$attribute2};
 }
 
 
 sub object_add_attribute_order{
-	my ($self,$attribute,@param)=@_;
-	my $r = $self->{'parameters_order'}{$attribute};
-	my @a;
-	@a = @{$r} if(defined $r);
-	push (@a,@param);
-	@a=uniq(@a);	
-	$self->{'parameters_order'}{$attribute} =\@a;
+    my ($self,$attribute,@param)=@_;
+    my $r = $self->{'parameters_order'}{$attribute};
+    my @a;
+    @a = @{$r} if(defined $r);
+    push (@a,@param);
+    @a=uniq(@a);    
+    $self->{'parameters_order'}{$attribute} =\@a;
 }
 
 sub object_remove_attribute_order{
-	my ($self,$attribute,$param)=@_;
-	my @r=@{$self->{parameters_order}{$attribute}};
-	my @n;
-	foreach my $p(@r){
-		if( $p ne $param) {push(@n,$p)};	
-
-	}
-	$self->{parameters_order}{$attribute}=\@n;
-
+    my ($self,$attribute,$param)=@_;
+    my @r=@{$self->{parameters_order}{$attribute}};
+    my @n;
+    foreach my $p(@r){
+        if( $p ne $param) {push(@n,$p)};    
+    }
+    $self->{parameters_order}{$attribute}=\@n;
 }
 
 sub object_get_attribute_order{
-	my ($self,$attribute)=@_;
-	return unless(defined $self->{parameters_order}{$attribute});
-	my @order=@{$self->{parameters_order}{$attribute}};
-	return uniq(@order)
+    my ($self,$attribute)=@_;
+    return unless(defined $self->{parameters_order}{$attribute});
+    my @order=@{$self->{parameters_order}{$attribute}};
+    return uniq(@order)
 }
 
 sub object_remove_attribute{
-	my ($self,$attribute1,$attribute2)=@_;
-	if(!defined $attribute2){
-		delete $self->{$attribute1} if ( exists( $self->{$attribute1})); 
-	}
-	else {
-		delete $self->{$attribute1}{$attribute2} if ( exists( $self->{$attribute1}{$attribute2})); ;
-	}
+    my ($self,$attribute1,$attribute2)=@_;
+    if(!defined $attribute2){
+        delete $self->{$attribute1} if ( exists( $self->{$attribute1})); 
+    }
+    else {
+        delete $self->{$attribute1}{$attribute2} if ( exists( $self->{$attribute1}{$attribute2})); ;
+    }
 }
 
 
 #############
 #  graphviz
 #############
-
-
 sub generate_and_show_graph_using_graphviz {
-	my ($self,$scrolled_win,$dotfile, $graph_name)=@_;
-	
-	
-	#empty the scrolled win 
-	if(defined $scrolled_win){
-		my @list = $scrolled_win->get_children();
-		foreach my $l (@list){ 
-			$scrolled_win->remove($l);			
-		}
-	}
-	
-	my $scale=$self->object_get_attribute($graph_name,"scale");
-	$scale= 1 if (!defined $scale);	
-	my $diagram;
-	
-	my $cmd = "echo \'$dotfile\' | dot -Tpng -q";
-	my ($stdout,$exit,$stderr)= run_cmd_in_back_ground_get_stdout ($cmd);
-	if ( length( $stderr || '' ) !=0)  {
-		message_dialog("$stderr\nHave you installed graphviz? If not run \n \t \"sudo apt-get install graphviz\" \n in terminal",'error');
-	}
-	$diagram =open_inline_image( $stdout,70*$scale,70*$scale,'percent');
-	if(defined $scrolled_win){
-		add_widget_to_scrolled_win($diagram,$scrolled_win);
-		$scrolled_win->show_all();	
-	}
+    my ($self,$scrolled_win,$dotfile, $graph_name)=@_;
+    #empty the scrolled win 
+    if(defined $scrolled_win){
+        my @list = $scrolled_win->get_children();
+        foreach my $l (@list){ 
+            $scrolled_win->remove($l);            
+        }
+    }
+    my $scale=$self->object_get_attribute($graph_name,"scale");
+    $scale= 1 if (!defined $scale);    
+    my $diagram;
+    my $cmd = "echo \'$dotfile\' | dot -Tpng -q";
+    my ($stdout,$exit,$stderr)= run_cmd_in_back_ground_get_stdout ($cmd);
+    if ( length( $stderr || '' ) !=0)  {
+        message_dialog("$stderr\nHave you installed graphviz? If not run \n \t \"sudo apt-get install graphviz\" \n in terminal",'error');
+    }
+    $diagram =open_inline_image( $stdout,70*$scale,70*$scale,'percent');
+    if(defined $scrolled_win){
+        add_widget_to_scrolled_win($diagram,$scrolled_win);
+        $scrolled_win->show_all();    
+    }
     my $save=$self->object_get_attribute("graph_save","enable");
-	$save=0 if(!defined $save);
-	if($save==1){
-		my $file = $self->object_get_attribute("graph_save","name");
-		my $ext  = $self->object_get_attribute("graph_save","extension");
-		my $pixbuff= $diagram->get_pixbuf;
-	    $pixbuff->save ("$file.$ext", "$ext");	
-	    $self->object_add_attribute("graph_save","enable",'0');	
-	}	
-		
-		
+    $save=0 if(!defined $save);
+    if($save==1){
+        my $file = $self->object_get_attribute("graph_save","name");
+        my $ext  = $self->object_get_attribute("graph_save","extension");
+        my $pixbuff= $diagram->get_pixbuf;
+        $pixbuff->save ("$file.$ext", "$ext");    
+        $self->object_add_attribute("graph_save","enable",'0');    
+    }    
 }
 
 
 ###########
-#	run_multiple_proc_in_background (@cmds)	
-#	run parallel application in background and return err, stdout
-#	return for $ith application i start from 0
-#		$pipes{$i}{"out"}= stdout;
-#		$pipes{$i}{"err"}= stderr;     
+#    run_multiple_proc_in_background (@cmds)    
+#    run parallel application in background and return err, stdout
+#    return for $ith application i start from 0
+#        $pipes{$i}{"out"}= stdout;
+#        $pipes{$i}{"err"}= stderr;     
 ###########
-
 sub run_multiple_proc_in_background
 {
-	my @cmds = @_;
-	my %pipes;
+    my @cmds = @_;
+    my %pipes;
     my $i=0;
-  	#open seprate pipe for each command
-	foreach my $cmd (@cmds){
-		#print "$cmd\n";
-		my ($pipe,$in, $out, $err,$r);
-		$pipes{$i}{"out"}=\$out;
-		$pipes{$i}{"err"}=\$err;
+    #open seprate pipe for each command
+    foreach my $cmd (@cmds){
+        #print "$cmd\n";
+        my ($pipe,$in, $out, $err,$r);
+        $pipes{$i}{"out"}=\$out;
+        $pipes{$i}{"err"}=\$err;
         $pipes{$i}{"pipe"}=\$pipe;
-	 	my @cat = split ('\s+', $cmd );
-		my $cmd_name=$cat[0];
-		#perevent pipe from crock	  	
-		if (!(-e $cmd_name)) {
-			$err= "file not found: $cmd_name";
-		}elsif (!(-f $cmd_name)) {    
-      		$err= "not a file: $cmd_name";       
-		}elsif (!(-x $cmd_name)) {       	
-			$err= "permission denied: $cmd_name";
-		}
-		if (defined  $err){
-			$i++;
-			next;
-		}
-
-		$pipe =start \@cat, \$in, \$out, \$err or $r=$?;
-		if(defined $r){
-			#add_colored_info($tview," quartus_stp got an Error: $r\n",'red');
-			$err= "Pipe got an Error: $r\n";	
-			$i++;		
-			next;		
-		}		
+        my @cat = split ('\s+', $cmd );
+        my $cmd_name=$cat[0];
+        #perevent pipe from crock          
+        if (!(-e $cmd_name)) {
+            $err= "file not found: $cmd_name";
+        }elsif (!(-f $cmd_name)) {    
+            $err= "not a file: $cmd_name";       
+        }elsif (!(-x $cmd_name)) {           
+            $err= "permission denied: $cmd_name";
+        }
+        if (defined  $err){
+            $i++;
+            next;
+        }
+        $pipe =start \@cat, \$in, \$out, \$err or $r=$?;
+        if(defined $r){
+            #add_colored_info($tview," quartus_stp got an Error: $r\n",'red');
+            $err= "Pipe got an Error: $r\n";    
+            $i++;        
+            next;        
+        }        
         $i++;
-	}
-	
-	my $pumpble=0;
-	my $cnt=0;
-	do{
-		$pumpble=0;		
-		for (my $i=0; $i< scalar @cmds; $i++){
-			my $pipe= ${$pipes{$i}{"pipe"}};
-			next if(!defined $pipe);
-			if (pumpable ($pipe)) { 
-				pump $pipe;
-			    $pumpble=1;
-			    print "pump $i\n";
-			} 			
-		}
-		#if($cnt==100) {
-		#		$cnt=0;			
-				refresh_gui();   
-		#}
-		#$cnt++
-	}while($pumpble);
-
-	
-	for (my $i=0; $i< scalar @cmds; $i++){
-		my $pipe= ${$pipes{$i}{"pipe"}};		
-		next if(!defined $pipe);
-		finish $pipe;
-	}
-	return %pipes;   	
+    }
+    my $pumpble=0;
+    my $cnt=0;
+    do{
+        $pumpble=0;        
+        for (my $i=0; $i< scalar @cmds; $i++){
+            my $pipe= ${$pipes{$i}{"pipe"}};
+            next if(!defined $pipe);
+            if (pumpable ($pipe)) { 
+                pump $pipe;
+                $pumpble=1;
+                print "pump $i\n";
+            }             
+        }
+        #if($cnt==100) {
+        #        $cnt=0;            
+                refresh_gui();   
+        #}
+        #$cnt++
+    }while($pumpble);
+    for (my $i=0; $i< scalar @cmds; $i++){
+        my $pipe= ${$pipes{$i}{"pipe"}};        
+        next if(!defined $pipe);
+        finish $pipe;
+    }
+    return %pipes;       
 }
 
 
 sub add_param_widget {
-	 my ($self,$name,$param, $default,$type,$content,$info, $table,$row,$column,$show,$attribut1,$ref_delay,$new_status,$loc)=@_;
-	 my $label;
-	 $label =gen_label_in_left(" $name") if(defined $name);
-	 my $widget;
-	 my $value=$self->object_get_attribute($attribut1,$param);
-	 if(! defined $value) {
-			$self->object_add_attribute($attribut1,$param,$default);
-			$self->object_add_attribute_order($attribut1,$param);
-			$value=$default;
-	 }
-	 if(! defined $new_status){
-		$new_status='ref';
-	 }
-	 if (! defined $loc){
-	 	 $loc = "vertical";
-	 }
-	 if ($type eq "Entry"){
-		$widget=gen_entry($value);
-		$widget-> signal_connect("changed" => sub{
-			my $new_param_value=$widget->get_text();
-			$self->object_add_attribute($attribut1,$param,$new_param_value);
-			set_gui_status($self,$new_status,$ref_delay) if(defined $ref_delay);
-		});		
-	 }
-	 elsif ($type eq "Combo-box"){
-		 my @combo_list=split(/\s*,\s*/,$content);
-		 my $pos=get_pos($value, @combo_list) if(defined $value);
-		 if(!defined $pos){
-		 	$self->object_add_attribute($attribut1,$param,$default);	
-		 	$pos=get_item_pos($default, @combo_list) if (defined $default);
-		 		 	
-		 }
-		#print " my $pos=get_item_pos($value, @combo_list);\n";
-		 $widget=gen_combo(\@combo_list, $pos);
-		 $widget-> signal_connect("changed" => sub{
-		 my $new_param_value=$widget->get_active_text();
-		 $self->object_add_attribute($attribut1,$param,$new_param_value);
-		 set_gui_status($self,$new_status,$ref_delay) if(defined $ref_delay);
-		 });
-		 
-	 }
-	 elsif ($type eq "EntryCombo"){
-	 	 my @combo_list;
-	 	 @combo_list=split(/\s*,\s*/,$content) if(defined $content);
-	 	 my $pos=get_pos($value, @combo_list) if(defined $value && defined $content);
-	 	 $widget= gen_combo_entry (\@combo_list,$pos);
-		 my $child = combo_entry_get_chiled($widget);
-	 	 $child->signal_connect('changed' => sub {
-				my ($entry) = @_;
-				my $new_param_value=$entry->get_text();
-				$self->object_add_attribute($attribut1,$param,$new_param_value);
-				set_gui_status($self,$new_status,$ref_delay) if(defined $ref_delay);
-	 	 });
-	 }
-	 
-	 elsif 	($type eq "Spin-button"){ 
-		my ($min,$max,$step,$digit)=split(/\s*,\s*/,$content);
-		
-		$value=~ s/[^0-9.\-]//g;
-		$min=~   s/[^0-9.\-]//g;
-		$max=~   s/[^0-9.\-]//g;
-		$step=~  s/[^0-9.\-]//g;
-		$digit=~ s/[^0-9.\-]//g if (defined $digit);
-		  #$max = $min if($max<$min);
-		  $widget=gen_spin($min,$max,$step,$digit);
-		  $widget->set_value($value);
-		  $widget-> signal_connect("value_changed" => sub{
-		  my $new_param_value=$widget->get_value();
-		  $self->object_add_attribute($attribut1,$param,$new_param_value);
-		  set_gui_status($self,$new_status,$ref_delay) if(defined $ref_delay);
-	      });
-		 
-		 # $box=def_label_spin_help_box ($param,$info, $value,$min,$max,$step, 2);
-	 }
-	
-	elsif ( $type eq "Check-box"){
-		$widget = def_hbox(FALSE,0);
-		my @check;
-		for (my $i=0;$i<$content;$i++){
-			$check[$i]= gen_checkbutton();
-		}
-		for (my $i=0;$i<$content;$i++){
-			$widget->pack_end(  $check[$i], FALSE, FALSE, 0);
-			
-			my @chars = split("",$value);
-			#check if saved value match the size of check box
-			if($chars[0] ne $content ) {
-				$self->object_add_attribute($attribut1,$param,$default);
-				$value=$default;
-				@chars = split("",$value);
-			}
-			#set initial value
-			
-			#print "\@chars=@chars\n";
-			for (my $i=0;$i<$content;$i++){
-				my $loc= (scalar @chars) -($i+1);
-					if( $chars[$loc] eq '1') {$check[$i]->set_active(TRUE);}
-					else {$check[$i]->set_active(FALSE);}
-			}
-
-
-			#get new value
-			$check[$i]-> signal_connect("toggled" => sub{
-				my $new_val="$content\'b";			
- 				
-				for (my $i=$content-1; $i >= 0; $i--){
-					if($check[$i]->get_active()) {$new_val="${new_val}1" ;}
-					else {$new_val="${new_val}0" ;}
-				}
-				$self->object_add_attribute($attribut1,$param,$new_val);
-				#print "\$new_val=$new_val\n";
-				set_gui_status($self,$new_status,$ref_delay) if(defined $ref_delay);
-			});
-		}
-
-	}
-	elsif ( $type eq "DIR_path"){
-			$widget =get_dir_in_object ($self,$attribut1,$param,$value,'ref',10,$default);
-			set_gui_status($self,$new_status,$ref_delay) if(defined $ref_delay);
-	}	
-	elsif ( $type eq "FILE_path"){ # use $content as extention
-			$widget =get_file_name_object ($self,$attribut1,$param,$content,undef,$new_status,$ref_delay);
-			
-	}	
-	elsif ( $type eq 'Fixed'){
-		 $self->object_add_attribute($attribut1,$param,$default);
-		 $widget =gen_label_in_left("$default");
-	}
-	else {
-		 $widget =gen_label_in_left("unsuported widget type!");
-	}
-
-	my $inf_bt= (defined $info)? gen_button_message ($info,"icons/help.png"):gen_label_in_left(" ");
-	if($show==1){
-		attach_widget_to_table ($table,$row,$label,$inf_bt,$widget,$column);
-		if ($loc eq "vertical"){
-			#print "$loc\n";
-			 $row ++;}
-		else {
-			
-			$column+=4;
-		}	 
-	}
+    my ($self,$name,$param, $default,$type,$content,$info, $table,$row,$column,$show,$attribut1,$ref_delay,$new_status,$loc)=@_;
+    my $label;
+    $label =gen_label_in_left(" $name") if(defined $name);
+    my $widget;
+    my $value=$self->object_get_attribute($attribut1,$param);
+    if(! defined $value) {
+            $self->object_add_attribute($attribut1,$param,$default);
+            $self->object_add_attribute_order($attribut1,$param);
+            $value=$default;
+    }
+    if(! defined $new_status){
+        $new_status='ref';
+    }
+    if (! defined $loc){
+        $loc = "vertical";
+    }
+    if ($type eq "Entry"){
+        $widget=gen_entry($value);
+        $widget-> signal_connect("changed" => sub{
+            my $new_param_value=$widget->get_text();
+            $self->object_add_attribute($attribut1,$param,$new_param_value);
+            set_gui_status($self,$new_status,$ref_delay) if(defined $ref_delay);
+        });        
+    }
+    elsif ($type eq "Combo-box"){
+        my @combo_list=split(/\s*,\s*/,$content);
+        my $pos=get_pos($value, @combo_list) if(defined $value);
+        if(!defined $pos){
+            $self->object_add_attribute($attribut1,$param,$default);    
+            $pos=get_item_pos($default, @combo_list) if (defined $default);
+        }
+        #print " my $pos=get_item_pos($value, @combo_list);\n";
+        $widget=gen_combo(\@combo_list, $pos);
+        $widget-> signal_connect("changed" => sub{
+        my $new_param_value=$widget->get_active_text();
+        $self->object_add_attribute($attribut1,$param,$new_param_value);
+        set_gui_status($self,$new_status,$ref_delay) if(defined $ref_delay);
+        });
+    }
+    elsif ($type eq "EntryCombo"){
+        my @combo_list;
+        @combo_list=split(/\s*,\s*/,$content) if(defined $content);
+        my $pos=get_pos($value, @combo_list) if(defined $value && defined $content);
+        $widget= gen_combo_entry (\@combo_list,$pos);
+        my $child = combo_entry_get_chiled($widget);
+        $child->signal_connect('changed' => sub {
+                my ($entry) = @_;
+                my $new_param_value=$entry->get_text();
+                $self->object_add_attribute($attribut1,$param,$new_param_value);
+                set_gui_status($self,$new_status,$ref_delay) if(defined $ref_delay);
+        });
+    }
+    elsif     ($type eq "Spin-button"){ 
+        my ($min,$max,$step,$digit)=split(/\s*,\s*/,$content);
+        $value=~ s/[^0-9.\-]//g;
+        $min=~   s/[^0-9.\-]//g;
+        $max=~   s/[^0-9.\-]//g;
+        $step=~  s/[^0-9.\-]//g;
+        $digit=~ s/[^0-9.\-]//g if (defined $digit);
+        #$max = $min if($max<$min);
+        $widget=gen_spin($min,$max,$step,$digit);
+        $widget->set_value($value);
+        $widget-> signal_connect("value_changed" => sub{
+            my $new_param_value=$widget->get_value();
+            $self->object_add_attribute($attribut1,$param,$new_param_value);
+            set_gui_status($self,$new_status,$ref_delay) if(defined $ref_delay);
+        });
+        # $box=def_label_spin_help_box ($param,$info, $value,$min,$max,$step, 2);
+    }
+    elsif ( $type eq "Check-box"){
+        $widget = def_hbox(FALSE,0);
+        my @check;
+        for (my $i=0;$i<$content;$i++){
+            $check[$i]= gen_checkbutton();
+        }
+        for (my $i=0;$i<$content;$i++){
+            $widget->pack_end(  $check[$i], FALSE, FALSE, 0);
+            
+            my @chars = split("",$value);
+            #check if saved value match the size of check box
+            if($chars[0] ne $content ) {
+                $self->object_add_attribute($attribut1,$param,$default);
+                $value=$default;
+                @chars = split("",$value);
+            }
+            #set initial value
+            #print "\@chars=@chars\n";
+            for (my $i=0;$i<$content;$i++){
+                my $loc= (scalar @chars) -($i+1);
+                    if( $chars[$loc] eq '1') {$check[$i]->set_active(TRUE);}
+                    else {$check[$i]->set_active(FALSE);}
+            }
+            #get new value
+            $check[$i]-> signal_connect("toggled" => sub{
+                my $new_val="$content\'b";            
+                for (my $i=$content-1; $i >= 0; $i--){
+                    if($check[$i]->get_active()) {$new_val="${new_val}1" ;}
+                    else {$new_val="${new_val}0" ;}
+                }
+                $self->object_add_attribute($attribut1,$param,$new_val);
+                #print "\$new_val=$new_val\n";
+                set_gui_status($self,$new_status,$ref_delay) if(defined $ref_delay);
+            });
+        }
+    }
+    elsif ( $type eq "DIR_path"){
+            $widget =get_dir_in_object ($self,$attribut1,$param,$value,'ref',10,$default);
+            set_gui_status($self,$new_status,$ref_delay) if(defined $ref_delay);
+    }    
+    elsif ( $type eq "FILE_path"){ # use $content for file extention:open_in
+        my ($ext, $open_in) = split(/:/, $content, 2);
+            $widget =get_file_name_object ($self,$attribut1,$param,$ext,$open_in,$new_status,$ref_delay);
+    }    
+    elsif ( $type eq 'Fixed'){
+        $self->object_add_attribute($attribut1,$param,$default);
+        $widget =gen_label_in_left("$default");
+    }
+    else {
+        $widget =gen_label_in_left("unsuported widget type!");
+    }
+    my $inf_bt= (defined $info)? gen_button_message ($info,"icons/help.png"):gen_label_in_left(" ");
+    if($show==1){
+        attach_widget_to_table ($table,$row,$label,$inf_bt,$widget,$column);
+        if ($loc eq "vertical"){
+            #print "$loc\n";
+            $row ++;}
+        else {
+            
+            $column+=4;
+        }     
+    }
     return ($row,$column,$widget);
 }
 
 
 #get the list of files matching the given extention
 sub get_file_list_by_extention {
-	my ($open_in, $ext)=@_;		
-	my @files = glob "$open_in/*";
-	my $file_list="";
-	foreach my $file (@files){
-		my ($name,$path,$suffix) = fileparse("$file",qr"\..[^.]*$");
-		if($suffix eq $ext || $suffix eq ".$ext" ){
-			$file_list.=",$name";
-		}		
-	}
-	return 	($file_list,\@files);
+    my ($open_in, $ext)=@_;        
+    my @files = glob "$open_in/*";
+    my $file_list="";
+    foreach my $file (@files){
+        my ($name,$path,$suffix) = fileparse("$file",qr"\..[^.]*$");
+        if($suffix eq $ext || $suffix eq ".$ext" ){
+            $file_list.=",$name";
+        }        
+    }
+    return     ($file_list,\@files);
 }
 
 
-
-
 sub set_gui_setting{
-	my $paths=shift;
-	my %p=%{$paths};
-	$glob_setting{'FONT_SIZE'}= $p{'GUI_SETTING'}{'FONT_SIZE'} if (defined $p{'GUI_SETTING'}{'FONT_SIZE'});
-	$glob_setting{'ICON_SIZE'}= $p{'GUI_SETTING'}{'ICON_SIZE'} if (defined $p{'GUI_SETTING'}{'ICON_SIZE'});
-	$glob_setting{'DSPLY_X'}  = $p{'GUI_SETTING'}{'DSPLY_X'}   if (defined $p{'GUI_SETTING'}{'DSPLY_X'});
-	$glob_setting{'DSPLY_Y'}  = $p{'GUI_SETTING'}{'DSPLY_Y'}   if (defined $p{'GUI_SETTING'}{'DSPLY_Y'});
+    my $paths=shift;
+    my %p=%{$paths};
+    $glob_setting{'FONT_SIZE'}= $p{'GUI_SETTING'}{'FONT_SIZE'} if (defined $p{'GUI_SETTING'}{'FONT_SIZE'});
+    $glob_setting{'ICON_SIZE'}= $p{'GUI_SETTING'}{'ICON_SIZE'} if (defined $p{'GUI_SETTING'}{'ICON_SIZE'});
+    $glob_setting{'DSPLY_X'}  = $p{'GUI_SETTING'}{'DSPLY_X'}   if (defined $p{'GUI_SETTING'}{'DSPLY_X'});
+    $glob_setting{'DSPLY_Y'}  = $p{'GUI_SETTING'}{'DSPLY_Y'}   if (defined $p{'GUI_SETTING'}{'DSPLY_Y'});
 }
 
 my ($screen_x,$screen_y);
 
 sub get_default_screen_size{
-	return  ($screen_x,$screen_y) if (defined $screen_x && defined $screen_y);
-	
-	my $fh= 'xrandr --current | awk \'$2~/\*/{print $1}\'' ;
-	my ($stdout, $stderr, $success) = qxx( ($fh) );
-	my @a = split ("\n",$stdout);
-	($screen_x,$screen_y) = split ("x",$a[0]);
-	$screen_x = 600 if(!defined $screen_x);
-	$screen_y = 800 if(!defined $screen_y);
-	return  ($screen_x,$screen_y);
+    return  ($screen_x,$screen_y) if (defined $screen_x && defined $screen_y);
+    
+    my $fh= 'xrandr --current | awk \'$2~/\*/{print $1}\'' ;
+    my ($stdout, $stderr, $success) = qxx( ($fh) );
+    my @a = split ("\n",$stdout);
+    ($screen_x,$screen_y) = split ("x",$a[0]);
+    $screen_x = 600 if(!defined $screen_x);
+    $screen_y = 800 if(!defined $screen_y);
+    return  ($screen_x,$screen_y);
 } 
 
 
@@ -1380,36 +1173,29 @@ sub get_default_screen_size{
 sub get_current_monitor_working_area{
     return ($Xaxis_max,$Yaxis_max) if(defined $Yaxis_max && defined $Yaxis_max);
     my $screen = get_default_screen();
-	my $hight = $screen->get_height(); 
-	my $active = $screen->get_active_window();
+    my $hight = $screen->get_height(); 
+    my $active = $screen->get_active_window();
     if (defined $active ){
-	    my $monitor =	$screen->get_monitor_at_window($active);
-	    my $warea = $screen->get_monitor_workarea($monitor);#get_width(); 
-	    ($Xaxis_max,$Yaxis_max)=($warea->{'width'},$warea->{'height'});
-	    #print  Data::Dumper->Dump ([$warea],['ttt']);  
-	    return ($Xaxis_max,$Yaxis_max);
-	}	
-	($Xaxis_max, $Yaxis_max)=get_default_screen_size();
-    return ($Xaxis_max,$Yaxis_max);	
+        my $monitor =    $screen->get_monitor_at_window($active);
+        my $warea = $screen->get_monitor_workarea($monitor);#get_width(); 
+        ($Xaxis_max,$Yaxis_max)=($warea->{'width'},$warea->{'height'});
+        #print  Data::Dumper->Dump ([$warea],['ttt']);  
+        return ($Xaxis_max,$Yaxis_max);
+    }    
+    ($Xaxis_max, $Yaxis_max)=get_default_screen_size();
+    return ($Xaxis_max,$Yaxis_max);    
 }
 
-
-
-
 sub max_win_size {
-	my ($x,$y);
-	$x= int($glob_setting{'DSPLY_X'}) if ($glob_setting{'DSPLY_X'} ne 'default');
-	$y= int($glob_setting{'DSPLY_Y'}) if ($glob_setting{'DSPLY_Y'} ne 'default');
-	if (!defined $x || !defined $y){
-		my ($X,$Y)=get_current_monitor_working_area();
-		$x=$X if (!defined $x);
-		$y=$Y if (!defined $y);
-	}
-	
-	return ($x,$y); 
-	 
-	
+    my ($x,$y);
+    $x= int($glob_setting{'DSPLY_X'}) if ($glob_setting{'DSPLY_X'} ne 'default');
+    $y= int($glob_setting{'DSPLY_Y'}) if ($glob_setting{'DSPLY_Y'} ne 'default');
+    if (!defined $x || !defined $y){
+        my ($X,$Y)=get_current_monitor_working_area();
+        $x=$X if (!defined $x);
+        $y=$Y if (!defined $y);
+    }
+    
+    return ($x,$y); 
 }
-
-
-1	 
+1;
diff --git a/mpsoc/perl_gui/lib/perl/compile.pl b/mpsoc/perl_gui/lib/perl/compile.pl
index fdd3378..637f04d 100644
--- a/mpsoc/perl_gui/lib/perl/compile.pl
+++ b/mpsoc/perl_gui/lib/perl/compile.pl
@@ -2,814 +2,642 @@
 use constant::boolean;
 use strict;
 use warnings;
-
 use FindBin;
 use lib $FindBin::Bin;
-
 use soc;
-
-
 use File::Path;
 use File::Find::Rule;
 use File::Copy;
 use File::Copy::Recursive qw(dircopy);
 use Cwd 'abs_path';
 use Verilog::EditFiles;
-
-
-
 use List::MoreUtils qw( minmax );
 
-
-
 ################
-#	Compile
+#    Compile
 #################
 
-
-
 sub is_capital_sensitive()
 {
-  my ($cell_layout, $cell, $tree_model, $iter, $data) = @_;
-  my $sensitive = !$tree_model->iter_has_child($iter);
-  $cell->set('sensitive', $sensitive);
+    my ($cell_layout, $cell, $tree_model, $iter, $data) = @_;
+    my $sensitive = !$tree_model->iter_has_child($iter);
+    $cell->set('sensitive', $sensitive);
 }
 
-
-
 sub get_range {
-	my ($board,$self,$porttype,$assignname,$portrange,$portname) =@_;
-	my $box= def_hbox(FALSE,0);
-	my @range=$board->board_get_pin_range($porttype,$assignname);
-	
-	
-	if ($range[0] ne '*undefine*'){
-		my $content = join(",", @range); 
-		my ($min, $max) = minmax @range;
-		if  (length($portrange)!=0){
-			my $range_hsb=gen_combobox_object($self,'compile_pin_range_hsb',$portname,$content,$max,undef,undef);
-			$box->pack_start( $range_hsb, FALSE, FALSE, 0);
-			$box->pack_start(gen_label_in_center(':'),, FALSE, FALSE, 0);
-		}
-
-		my $range_lsb=gen_combobox_object($self,'compile_pin_range_lsb',$portname,$content,$min,undef,undef);
-		$box->pack_start( $range_lsb, FALSE, FALSE, 0);
-		
-	}
-	return $box;
-
+    my ($board,$self,$porttype,$assignname,$portrange,$portname) =@_;
+    my $box= def_hbox(FALSE,0);
+    my @range=$board->board_get_pin_range($porttype,$assignname);
+    if ($range[0] ne '*undefine*'){
+        my $content = join(",", @range); 
+        my ($min, $max) = minmax @range;
+        if  (length($portrange)!=0){
+            my $range_hsb=gen_combobox_object($self,'compile_pin_range_hsb',$portname,$content,$max,undef,undef);
+            $box->pack_start( $range_hsb, FALSE, FALSE, 0);
+            $box->pack_start(gen_label_in_center(':'),, FALSE, FALSE, 0);
+        }
+        my $range_lsb=gen_combobox_object($self,'compile_pin_range_lsb',$portname,$content,$min,undef,undef);
+        $box->pack_start( $range_lsb, FALSE, FALSE, 0);
+        
+    }
+    return $box;
 }
 
-
 sub read_top_v_file{
-	my $top_v=shift;
-	my $board = soc->board_new(); 
-	my $vdb=read_verilog_file($top_v);
-	my @modules=sort $vdb->get_modules($top_v);
-	my %Ptypes=get_ports_type($vdb,$modules[0]);
-	my %Pranges=get_ports_rang($vdb,$modules[0]);
-	foreach my $p (sort keys %Ptypes){
-		my $Ptype=$Ptypes{$p};
-		my $Prange=$Pranges{$p};		
-		my $type=($Ptype eq "input")? "Input" : ($Ptype eq "output")? 'Output' : 'Bidir';
-		if (  $Prange ne ''){
-			my @r=split(":",$Prange);
-			my $a=($r[0]<$r[1])? $r[0] : $r[1];
-			my $b=($r[0]<$r[1])? $r[1] : $r[0];
-			for (my $i=$a; $i<=$b; $i++){
-				$board->board_add_pin ($type,"$p\[$i\]");
-				
-			}			
-		}
-		else {$board->board_add_pin ($type,$p);}			
-	}	
-	return $board;
+    my $top_v=shift;
+    my $board = soc->board_new(); 
+    my $vdb=read_verilog_file($top_v);
+    my @modules=sort $vdb->get_modules($top_v);
+    my %Ptypes=get_ports_type($vdb,$modules[0]);
+    my %Pranges=get_ports_rang($vdb,$modules[0]);
+    foreach my $p (sort keys %Ptypes){
+        my $Ptype=$Ptypes{$p};
+        my $Prange=$Pranges{$p};        
+        my $type=($Ptype eq "input")? "Input" : ($Ptype eq "output")? 'Output' : 'Bidir';
+        if (  $Prange ne ''){
+            my @r=split(":",$Prange);
+            my $a=($r[0]<$r[1])? $r[0] : $r[1];
+            my $b=($r[0]<$r[1])? $r[1] : $r[0];
+            for (my $i=$a; $i<=$b; $i++){
+                $board->board_add_pin ($type,"$p\[$i\]");
+                
+            }            
+        }
+        else {$board->board_add_pin ($type,$p);}            
+    }    
+    return $board;
 }
 
-
-
-
 sub gen_top_v{
-	my ($self,$board,$name,$top)=@_;
-
-	my $top_v=get_license_header("Top.v");
-	#read port list 
-	my $vdb=read_verilog_file($top);
-	my %port_type=get_ports_type($vdb,"${name}_top");
-	my %port_range=get_ports_rang($vdb,"${name}_top");
-	
-	
-	my $io='';
-	my $io_def='';
-	my $io_assign='';
-	my %board_io;
-	my $first=1;
-	foreach my $p (sort keys %port_type){
-		my $porttype=$port_type{$p};
-		my $portrange=$port_range{$p};
-		my $assign_type = $self->object_get_attribute('compile_assign_type',$p);
-		my $assign_name = $self->object_get_attribute('compile_pin',$p);
-		my $range_hsb   = $self->object_get_attribute('compile_pin_range_hsb',$p);
-		my $range_lsb   = $self->object_get_attribute('compile_pin_range_lsb',$p);
-		my $assign="\t";
-		if (defined $assign_name){
-			if($assign_name eq '*VCC'){
-				$assign= (length($portrange)!=0)? '{32{1\'b1}}' : '1\'b1';
-			} elsif ($assign_name eq '*GND'){
-				$assign= (length($portrange)!=0)? '{32{1\'b0}}' : '1\'b0';
-			}elsif ($assign_name eq '*NOCONNECT'){ 
-				$assign="\t";
-
-			}else{ 
-				
-				$board_io{$assign_name}=$porttype;
-				
-				
-				my $range = (defined $range_hsb) ? "[$range_hsb : $range_lsb]" : 
-					    (defined $range_lsb) ?  "[ $range_lsb]" : " ";
-				my $l=(defined $assign_type)? 
-					($assign_type eq 'Direct') ? '' : '~' : '';
-				$assign="$l $assign_name $range";
-			 	
-				
-			}	
-		}
-		$io_assign= ($first)? "$io_assign \t  .$p($assign)":"$io_assign,\n \t  .$p($assign)";		
-		$first=0;
-	}
-	$first=1;
-	foreach my $p (sort keys %board_io){
-			$io=($first)? "\t$p" : "$io,\n\t$p";
-			my $dir=$board_io{$p};
-			my $range;
-			my $type= ($dir eq  'input') ? 'Input' : 
-			  	  ($dir eq  'output')? 'Output' : 'Bidir';
-			my @r= $board->board_get_pin_range($type,$p);
-			if ($r[0] eq '*undefine*'){
-				$range="\t\t\t";
-			} else {
-				my ($min, $max) = minmax @r;
-				$range="\t[$max : $min]\t";
-			}
-			$io_def = "$io_def \t $dir $range $p;\n";
-			$first=0;	
-		
-	}
-	$top_v="$top_v 
+    my ($self,$board,$name,$top)=@_;
+    my $top_v=get_license_header("Top.v");
+    #read port list 
+    my $vdb=read_verilog_file($top);
+    my %port_type=get_ports_type($vdb,"${name}_top");
+    my %port_range=get_ports_rang($vdb,"${name}_top");
+    my $io='';
+    my $io_def='';
+    my $io_assign='';
+    my %board_io;
+    my $first=1;
+    foreach my $p (sort keys %port_type){
+        my $porttype=$port_type{$p};
+        my $portrange=$port_range{$p};
+        my $assign_type = $self->object_get_attribute('compile_assign_type',$p);
+        my $assign_name = $self->object_get_attribute('compile_pin',$p);
+        my $range_hsb   = $self->object_get_attribute('compile_pin_range_hsb',$p);
+        my $range_lsb   = $self->object_get_attribute('compile_pin_range_lsb',$p);
+        my $assign="\t";
+        if (defined $assign_name){
+            if($assign_name eq '*VCC'){
+                $assign= (length($portrange)!=0)? '{32{1\'b1}}' : '1\'b1';
+            } elsif ($assign_name eq '*GND'){
+                $assign= (length($portrange)!=0)? '{32{1\'b0}}' : '1\'b0';
+            }elsif ($assign_name eq '*NOCONNECT'){ 
+                $assign="\t";
+            }else{ 
+                $board_io{$assign_name}=$porttype;
+                my $range = (defined $range_hsb) ? "[$range_hsb : $range_lsb]" : 
+                        (defined $range_lsb) ?  "[ $range_lsb]" : " ";
+                my $l=(defined $assign_type)? 
+                    ($assign_type eq 'Direct') ? '' : '~' : '';
+                $assign="$l $assign_name $range";
+            }    
+        }
+        $io_assign= ($first)? "$io_assign \t  .$p($assign)":"$io_assign,\n \t  .$p($assign)";        
+        $first=0;
+    }
+    $first=1;
+    foreach my $p (sort keys %board_io){
+            $io=($first)? "\t$p" : "$io,\n\t$p";
+            my $dir=$board_io{$p};
+            my $range;
+            my $type= ($dir eq  'input') ? 'Input' : 
+                    ($dir eq  'output')? 'Output' : 'Bidir';
+            my @r= $board->board_get_pin_range($type,$p);
+            if ($r[0] eq '*undefine*'){
+                $range="\t\t\t";
+            } else {
+                my ($min, $max) = minmax @r;
+                $range="\t[$max : $min]\t";
+            }
+            $io_def = "$io_def \t $dir $range $p;\n";
+            $first=0;    
+    }
+    $top_v="$top_v 
 module Top (
 $io
 );
 $io_def
 
-	${name}_top uut(	
+    ${name}_top uut(    
 $io_assign
-	);
-
+    );
 
 endmodule
 ";
-	my ($fname,$fpath,$fsuffix) = fileparse("$top",qr"\..[^.]*$");
-	my $board_top_file= "$fpath/Top.v";
-	save_file($board_top_file,$top_v);
+    my ($fname,$fpath,$fsuffix) = fileparse("$top",qr"\..[^.]*$");
+    my $board_top_file= "$fpath/Top.v";
+    save_file($board_top_file,$top_v);
 }
 
-
-
-
 sub select_compiler {
-	my ($self,$name,$top,$target_dir,$end_func)=@_;
-	my $window = def_popwin_size(40,40,"Step 1: Select Compiler",'percent');
-	
-	my $table = def_table(2, 2, FALSE);
-	my $col=0;
-	my $row=0;
-
-	my $compilers=$self->object_get_attribute('compile','compilers');#"QuartusII,Vivado,Verilator,Modelsim"
-	
-	my $compiler=gen_combobox_object ($self,'compile','type',$compilers,"QuartusII",undef,undef);
-	$table->attach(gen_label_in_center("Compiler tool"),$col,$col+1,$row,$row+1,'fill','shrink',2,2);$col++;
-	$table->attach($compiler,$col,$col+1,$row,$row+1,'fill','shrink',2,2);$col++;
-	$row++;$col=0;
-	
-	my $old_board_name=$self->object_get_attribute('compile','board');
-	my $old_compiler=$self->object_get_attribute('compile','type');
-	my $vendor= ($old_compiler eq "QuartusII")? 'Altera' : 'Xilinx';
-	
-	#get the list of boards located in "boards/*" folder
-	my @dirs = grep {-d} glob("../boards/$vendor/*");
-	my ($fpgas,$init);
-	foreach my $dir (@dirs) {
-		my ($name,$path,$suffix) = fileparse("$dir",qr"\..[^.]*$");
-		$init=$name;
-		$fpgas= (defined $fpgas)? "$fpgas,$name" : "$name";		
-	}
-		
-	
-	my $compiler_options =
-		($old_compiler eq "QuartusII")? select_board  ($self,$name,$top,$target_dir,$vendor): 
-		($old_compiler eq "Vivado"   )? select_board  ($self,$name,$top,$target_dir,$vendor): 
-		($old_compiler eq "Modelsim" )? select_model_path  ($self,$name,$top,$target_dir): 
-		($old_compiler eq "Verilator")? select_parallel_process_num ($self,$name,$top,$target_dir):
-		gen_label_in_center(" ");
-	
-	$table->attach($compiler_options,$col,$col+2,$row,$row+1,'fill','shrink',2,2); $row++;
-
-	$col=1;
-	my $i;	
-	for ($i=$row; $i<5; $i++){
-		
-		my $temp=gen_label_in_center(" ");
-		$table->attach_defaults ($temp, 0, 1 , $i, $i+1);
-	}
-	$row=$i;	
-		
-
-	$window->add ($table);
-	$window->show_all();
-	my $next=def_image_button('icons/right.png','_Next',FALSE,1);
-	$table->attach($next,$col,$col+1,$row,$row+1,'shrink','shrink',2,2);$col++;
-	$next-> signal_connect("clicked" => sub{
-		my $compiler_type=$self->object_get_attribute('compile','type');		
-		if($compiler_type eq "QuartusII" || $compiler_type eq "Vivado"){
-			$vendor= ($compiler_type eq "QuartusII")? 'Altera' : 'Xilinx';
-			my $new_board_name=$self->object_get_attribute('compile','board');
-			if(defined $old_board_name) {
-				if ($old_board_name ne $new_board_name){
-					remove_pin_assignment($self); 
-					my ($fname,$fpath,$fsuffix) = fileparse("$top",qr"\..[^.]*$");
-					#delete jtag_intfc.sh file
-					unlink "${fpath}../sw/jtag_intfc.sh";
-					#program_device.sh file  
-					unlink "${fpath}../program_device.sh";
-				}
-
-				my ($fname,$fpath,$fsuffix) = fileparse("$top",qr"\..[^.]*$");
-				my $board_top_file= "$fpath/Top.v";
-				unlink $board_top_file if ($old_board_name ne $new_board_name);
-
-
-			}
-			if($new_board_name eq "Add New Board") {add_new_fpga_board($self,$name,$top,$target_dir,$end_func,$vendor);}
-			else {get_pin_assignment($self,$name,$top,$target_dir,$end_func,$vendor);}
-		}
-		
-		
-		
-		
-		
-		
-		elsif($compiler_type eq "Modelsim"){
-			modelsim_compilation($self,$name,$top,$target_dir,$vendor);
-
-		}else{#verilator
-			verilator_compilation_win($self,$name,$top,$target_dir,$vendor);
-
-		}
-
-		$window->destroy;
-		
-	});
-
-	$compiler->signal_connect("changed" => sub{
-		$compiler_options->destroy;
-		my $new_board_name=$self->object_get_attribute('compile','type');
-		$compiler_options =
-			($new_board_name eq "QuartusII")? select_board  ($self,$name,$top,$target_dir,"Altera"):
-			($new_board_name eq "Vivado")? select_board  ($self,$name,$top,$target_dir,"Xilinx"):
-			($new_board_name eq "Modelsim")?  select_model_path  ($self,$name,$top,$target_dir):
-			($new_board_name eq "Verilator")? select_parallel_process_num ($self,$name,$top,$target_dir):
-			gen_label_in_center(" ");
-		$table->attach($compiler_options,0,2,1,2,'fill','shrink',2,2); 	
-		$table->show_all;
-
-	});
-	
+    my ($self,$name,$top,$target_dir,$end_func)=@_;
+    my $window = def_popwin_size(40,40,"Step 1: Select Compiler",'percent');
+    my $table = def_table(2, 2, FALSE);
+    my $col=0;
+    my $row=0;
+    my $compilers=$self->object_get_attribute('compile','compilers');#"QuartusII,Vivado,Verilator,Modelsim"
+    my $compiler=gen_combobox_object ($self,'compile','type',$compilers,"QuartusII",undef,undef);
+    $table->attach(gen_label_in_center("Compiler tool"),$col,$col+1,$row,$row+1,'fill','shrink',2,2);$col++;
+    $table->attach($compiler,$col,$col+1,$row,$row+1,'fill','shrink',2,2);$col++;
+    $row++;$col=0;
+    my $old_board_name=$self->object_get_attribute('compile','board');
+    my $old_compiler=$self->object_get_attribute('compile','type');
+    my $vendor= ($old_compiler eq "QuartusII")? 'Altera' : 'Xilinx';
+    
+    #get the list of boards located in "boards/*" folder
+    my @dirs = grep {-d} glob("../boards/$vendor/*");
+    my ($fpgas,$init);
+    foreach my $dir (@dirs) {
+        my ($name,$path,$suffix) = fileparse("$dir",qr"\..[^.]*$");
+        $init=$name;
+        $fpgas= (defined $fpgas)? "$fpgas,$name" : "$name";        
+    }
+    
+    my $compiler_options =
+        ($old_compiler eq "QuartusII")? select_board  ($self,$name,$top,$target_dir,$vendor): 
+        ($old_compiler eq "Vivado"   )? select_board  ($self,$name,$top,$target_dir,$vendor): 
+        ($old_compiler eq "Modelsim" )? select_model_path  ($self,$name,$top,$target_dir): 
+        ($old_compiler eq "Verilator")? select_parallel_process_num ($self,$name,$top,$target_dir):
+    gen_label_in_center(" ");
+    $table->attach($compiler_options,$col,$col+2,$row,$row+1,'fill','shrink',2,2); $row++;
+    $col=1;
+    my $i;    
+    for ($i=$row; $i<5; $i++){
+        my $temp=gen_label_in_center(" ");
+        $table->attach_defaults ($temp, 0, 1 , $i, $i+1);
+    }
+    $row=$i;    
+    $window->add ($table);
+    $window->show_all();
+    my $next=def_image_button('icons/right.png','_Next',FALSE,1);
+    $table->attach($next,$col,$col+1,$row,$row+1,'shrink','shrink',2,2);$col++;
+    $next-> signal_connect("clicked" => sub{
+        my $compiler_type=$self->object_get_attribute('compile','type');        
+        if($compiler_type eq "QuartusII" || $compiler_type eq "Vivado"){
+            $vendor= ($compiler_type eq "QuartusII")? 'Altera' : 'Xilinx';
+            my $new_board_name=$self->object_get_attribute('compile','board');
+            if(defined $old_board_name) {
+                if ($old_board_name ne $new_board_name){
+                    remove_pin_assignment($self); 
+                    my ($fname,$fpath,$fsuffix) = fileparse("$top",qr"\..[^.]*$");
+                    #delete jtag_intfc.sh file
+                    unlink "${fpath}../sw/jtag_intfc.sh";
+                    #program_device.sh file  
+                    unlink "${fpath}../program_device.sh";
+                }
+                my ($fname,$fpath,$fsuffix) = fileparse("$top",qr"\..[^.]*$");
+                my $board_top_file= "$fpath/Top.v";
+                unlink $board_top_file if ($old_board_name ne $new_board_name);
+            }
+            if($new_board_name eq "Add New Board") {add_new_fpga_board($self,$name,$top,$target_dir,$end_func,$vendor);}
+            else {get_pin_assignment($self,$name,$top,$target_dir,$end_func,$vendor);}
+        }
+        elsif($compiler_type eq "Modelsim"){
+            modelsim_compilation($self,$name,$top,$target_dir,$vendor);
+        }else{#verilator
+            verilator_compilation_win($self,$name,$top,$target_dir,$vendor);
+        }
+        $window->destroy;
+    });
+    
+    $compiler->signal_connect("changed" => sub{
+        $compiler_options->destroy;
+        my $new_board_name=$self->object_get_attribute('compile','type');
+        $compiler_options =
+            ($new_board_name eq "QuartusII")? select_board  ($self,$name,$top,$target_dir,"Altera"):
+            ($new_board_name eq "Vivado")? select_board  ($self,$name,$top,$target_dir,"Xilinx"):
+            ($new_board_name eq "Modelsim")?  select_model_path  ($self,$name,$top,$target_dir):
+            ($new_board_name eq "Verilator")? select_parallel_process_num ($self,$name,$top,$target_dir):
+            gen_label_in_center(" ");
+        $table->attach($compiler_options,0,2,1,2,'fill','shrink',2,2);     
+        $table->show_all;
+    });
 }
 
-
-
-
-
-
 sub select_board {
-	my ($self,$name,$top,$target_dir,$vendor)=@_;
-	
-	#get the list of boards located in "boards/*" folder
-	my @dirs = grep {-d} glob("../boards/$vendor/*");
-	my ($fpgas,$init);
-	$fpgas="Add New Board";
-	
-	foreach my $dir (@dirs) {
-		my ($name,$path,$suffix) = fileparse("$dir",qr"\..[^.]*$");
-		
-		$fpgas= (defined $fpgas)? "$fpgas,$name" : "$name";	
-		$init="$name";	
-	}
-	my $table = def_table(2, 2, FALSE);
-	my $col=0;
-	my $row=0;
+    my ($self,$name,$top,$target_dir,$vendor)=@_;
+    #get the list of boards located in "boards/*" folder
+    my @dirs = grep {-d} glob("../boards/$vendor/*");
+    my ($fpgas,$init);
+    $fpgas="Add New Board";
+    foreach my $dir (@dirs) {
+        my ($name,$path,$suffix) = fileparse("$dir",qr"\..[^.]*$");
+        $fpgas= (defined $fpgas)? "$fpgas,$name" : "$name";    
+        $init="$name";    
+    }
+    my $table = def_table(2, 2, FALSE);
+    my $col=0;
+    my $row=0;
     my $compiler = ($vendor eq "Altera")? 'quartus' : 'vivado';
     my $bin_name = "$compiler bin";
     my $env = ($vendor eq "Altera")? "QUARTUS_BIN" : "VIVADO_BIN";
-	my $Fpga_bin=   $ENV{$env};
-	
-	my $old_board_name=$self->object_get_attribute('compile','board');
-	$table->attach(gen_label_help("The list of supported boards are obtained from \"mpsoc/boards/$vendor\" path. You can add your boards by adding its required files in aformentioned path. Note that currently Altera and Xilinx FPGAs are supported.",'Targeted Board:'),$col,$col+1,$row,$row+1,'fill','shrink',2,2);$col++;
-	$table->attach(gen_combobox_object ($self,'compile','board',$fpgas,$init,undef,undef),$col,$col+1,$row,$row+1,'fill','shrink',2,2);$row++;
-	my $bin =  $self->object_get_attribute('compile',$bin_name);
-	
-	$col=0;
-	$self->object_add_attribute('compile',$bin_name,$Fpga_bin) if (!defined $bin && defined $Fpga_bin);
-	$table->attach(gen_label_help("Path to $vendor/bin directory. You can set a default path as $env environment variable in ~/.bashrc file.
+    my $Fpga_bin=   $ENV{$env};
+    my $old_board_name=$self->object_get_attribute('compile','board');
+    $table->attach(gen_label_help("The list of supported boards are obtained from \"mpsoc/boards/$vendor\" path. You can add your boards by adding its required files in aformentioned path. Note that currently Altera and Xilinx FPGAs are supported.",'Targeted Board:'),$col,$col+1,$row,$row+1,'fill','shrink',2,2);$col++;
+    $table->attach(gen_combobox_object ($self,'compile','board',$fpgas,$init,undef,undef),$col,$col+1,$row,$row+1,'fill','shrink',2,2);$row++;
+    my $bin =  $self->object_get_attribute('compile',$bin_name);
+    $col=0;
+    $self->object_add_attribute('compile',$bin_name,$Fpga_bin) if (!defined $bin && defined $Fpga_bin);
+    $table->attach(gen_label_help("Path to $vendor/bin directory. You can set a default path as $env environment variable in ~/.bashrc file.
 e.g:  export $env=/home/alireza/$compiler/bin","$env:"),$col,$col+1,$row,$row+1,'fill','shrink',2,2);$col++;
-	$table->attach(get_dir_in_object ($self,'compile',$bin_name,undef,undef,undef),$col,$col+1,$row,$row+1,'fill','shrink',2,2);$row++;
-	
-	
-	
-	
-	
-	return $table;
-	
+    $table->attach(get_dir_in_object ($self,'compile',$bin_name,undef,undef,undef),$col,$col+1,$row,$row+1,'fill','shrink',2,2);$row++;
+    return $table;
 }
 
-
-
-
 sub select_model_path {
-	my ($self,$name,$top,$target_dir)=@_;
-	
-	
-	my $table = def_table(2, 2, FALSE);
-	my $col=0;
-	my $row=0;
-
-	
-	
-	
-	my $bin = $self->object_get_attribute('compile','modelsim_bin');
-	my $modelsim_bin=  $ENV{MODELSIM_BIN};
-	$col=0;
-	$self->object_add_attribute('compile','modelsim_bin',$modelsim_bin) if (!defined $bin && defined $modelsim_bin);
-	$table->attach(gen_label_help("Path to modelsim/bin directory. You can set a default path as MODELSIM_BIN environment variable in ~/.bashrc file.
+    my ($self,$name,$top,$target_dir)=@_;
+    my $table = def_table(2, 2, FALSE);
+    my $col=0;
+    my $row=0;
+    my $bin = $self->object_get_attribute('compile','modelsim_bin');
+    my $modelsim_bin=  $ENV{MODELSIM_BIN};
+    $col=0;
+    $self->object_add_attribute('compile','modelsim_bin',$modelsim_bin) if (!defined $bin && defined $modelsim_bin);
+    $table->attach(gen_label_help("Path to modelsim/bin directory. You can set a default path as MODELSIM_BIN environment variable in ~/.bashrc file.
 e.g.  export MODELSIM_BIN=/home/alireza/altera/modeltech/bin",'Modelsim  bin:'),$col,$col+1,$row,$row+1,'fill','shrink',2,2);$col++;
-	$table->attach(get_dir_in_object ($self,'compile','modelsim_bin',undef,undef,undef),$col,$col+1,$row,$row+1,'fill','shrink',2,2);$row++;
-	
-	return $table;
-	
+    $table->attach(get_dir_in_object ($self,'compile','modelsim_bin',undef,undef,undef),$col,$col+1,$row,$row+1,'fill','shrink',2,2);$row++;
+    return $table;
 }
 
 my $cpu_num;
 sub select_parallel_process_num {
-	my ($self,$name,$top,$target_dir)=@_;	
-	my $table = def_table(2, 2, FALSE);
-	my $col=0;
-	my $row=0;
-	
-	#get total number of processor in the system
-	my $cmd = "nproc\n";
-	if(!defined $cpu_num){
-		my ($stdout,$exit,$stderr)=run_cmd_in_back_ground_get_stdout($cmd);
-		if(length $stderr>1){			
-			#nproc command has failed. set default 4 paralel processor
-						
-		}else {
-			my ($number ) = $stdout =~ /(\d+)/;
-			if (defined  $number ){ 
-				$cpu_num =$number if  ($number > 0 );
-			}
-		}
-	}
-	($row,$col)= add_param_widget ($self,"Paralle run:" , "cpu_num", 1, 'Spin-button', "1,$cpu_num,1","specify the number of processors the Verilator can use at once to run parallel compilations/simulations", $table,$row,$col,1, 'compile', undef,undef,'vertical');
-	return $table;	
+    my ($self,$name,$top,$target_dir)=@_;    
+    my $table = def_table(2, 2, FALSE);
+    my $col=0;
+    my $row=0;
+    #get total number of processor in the system
+    my $cmd = "nproc";
+    if(!defined $cpu_num){
+        my ($stdout,$exit,$stderr)=run_cmd_in_back_ground_get_stdout($cmd);
+        if(length $stderr>1){            
+            #nproc command has failed. set default 4 paralel processor
+        }else {
+            my ($number ) = $stdout =~ /(\d+)/;
+            if (defined  $number ){ 
+                $cpu_num =$number if  ($number > 0 );
+            }
+        }
+    }
+    ($row,$col)= add_param_widget ($self,"Paralle run:" , "cpu_num", 1, 'Spin-button', "1,$cpu_num,1","specify the number of processors the Verilator can use at once to run parallel compilations/simulations", $table,$row,$col,1, 'compile', undef,undef,'vertical');
+    return $table;
 }
 
 sub select_parallel_thread_num {
-	my ($self,$name,$top,$target_dir)=@_;	
-	my $table = def_table(2, 2, FALSE);
-	my $col=0;
-	my $row=0;
-	
-	#get total number of processor in the system
-	my $cmd = "nproc\n";
-	if(!defined $cpu_num){
-		my ($stdout,$exit,$stderr)=run_cmd_in_back_ground_get_stdout($cmd);
-		if(length $stderr>1){			
-			#nproc command has failed. set default 4 paralel processor
-						
-		}else {
-			my ($number ) = $stdout =~ /(\d+)/;
-			if (defined  $number ){ 
-				$cpu_num =$number if  ($number > 0 );
-			}
-		}
-	}
-	($row,$col)= add_param_widget ($self,"Thread run:" , "thread_num", 1, 'Spin-button', "1,$cpu_num,1","specify the number of threads the Verilator can use at once in one simulation", $table,$row,$col,1, 'compile', undef,undef,'vertical');
-	return $table;	
+    my ($self,$name,$top,$target_dir)=@_;
+    my $table = def_table(2, 2, FALSE);
+    my $col=0;
+    my $row=0;
+    #get total number of processor in the system
+    my $cmd = "nproc";
+    if(!defined $cpu_num){
+        my ($stdout,$exit,$stderr)=run_cmd_in_back_ground_get_stdout($cmd);
+        if(length $stderr>1){
+            #nproc command has failed. set default 4 paralel processor
+        }else {
+            my ($number ) = $stdout =~ /(\d+)/;
+            if (defined  $number ){ 
+                $cpu_num =$number if  ($number > 0 );
+            }
+        }
+    }
+    ($row,$col)= add_param_widget ($self,"Thread run:" , "thread_num", 1, 'Spin-button', "1,$cpu_num,1","specify the number of threads the Verilator can use at once in one simulation", $table,$row,$col,1, 'compile', undef,undef,'vertical');
+    return $table;
 }
 
-
-
-
 sub remove_pin_assignment{
-	my $self=shift;
-	$self->object_remove_attribute('compile_pin_pos');
-	$self->object_remove_attribute('compile_pin');
-	$self->object_remove_attribute('compile_assign_type');
-	$self->object_remove_attribute('compile_pin_range_hsb');
-	$self->object_remove_attribute('compile_pin_range_lsb');
+    my $self=shift;
+    $self->object_remove_attribute('compile_pin_pos');
+    $self->object_remove_attribute('compile_pin');
+    $self->object_remove_attribute('compile_assign_type');
+    $self->object_remove_attribute('compile_pin_range_hsb');
+    $self->object_remove_attribute('compile_pin_range_lsb');
 }
 
-
-
 sub add_new_fpga_board{
-	
-	my ($self,$name,$top,$target_dir,$end_func,$vendor)=@_;	
-	
-	my $window = def_popwin_size(50,80,"Add New $vendor FPGA Board",'percent');
-	my $table = def_table(2, 2, FALSE);
-	my $scrolled_win=add_widget_to_scrolled_win($table);
-
-
-	my $mtable = def_table(10, 10, FALSE);
-	
-	my $next=def_image_button('icons/plus.png','Add');
-	my $back=def_image_button('icons/left.png','Previous'); 	
-	$mtable->attach_defaults($scrolled_win,0,10,0,9);
-	$mtable->attach($back,2,3,9,10,'shrink','shrink',2,2) if (defined $name);	
-	$mtable->attach($next,8,9,9,10,'shrink','shrink',2,2);
-	
-	
-	my ($Twin,$tview)=create_txview();
-	
-	
-	my $widgets=
-		($vendor eq 'Altera')? add_new_altera_fpga_board_widgets($self,$name,$top,$target_dir,$end_func,$vendor):
-		add_new_xilinx_fpga_board_widgets($self,$name,$top,$target_dir,$end_func,$vendor,$tview);
-	
-	
-
-	my $v1=gen_vpaned($widgets,0.3,$Twin);
-	
-	$table->attach_defaults($v1,0,3,0,2); 
-	#$table->attach_defaults( $Twin,0,3,1,2); 	
-	
-		
-	
-	
-	$back-> signal_connect("clicked" => sub{ 
-		
-		$window->destroy;
-		select_compiler($self,$name,$top,$target_dir,$end_func);
-		
-	});
-	
-	$next-> signal_connect("clicked" => sub{ 
-		my $result = ($vendor eq 'Altera')? 
-			add_new_altera_fpga_board_files($self,$vendor):
-			add_new_xilinx_fpga_board_files($self,$vendor); 
-			
-		if(! defined $result ){
-			select_compiler($self,$name,$top,$target_dir,$end_func) if (defined $name);	
-			$window->destroy;
-			message_dialog("The new board has been added successfully!");			
-		}else {
-			show_info($tview," ");
-			show_colored_info($tview,$result,'red');			
-		}	
-		
-	});
-	
-	
-	
-	if($vendor eq 'Altera'){
-	    my $auto=def_image_button('icons/advance.png','Auto-fill'); 
-	    set_tip($auto, "Auto-fill JTAG configuration. The board must be powered on and be connected to the PC."); 
-		$mtable->attach($auto,5,6,9,10,'shrink','shrink',2,2);
-		$auto-> signal_connect("clicked" => sub{ 
-			my $pid;
-			my $hw;
-			
-			my $project_dir	  = get_project_dir();		
-			my $command=  "$project_dir/mpsoc/src_c/jtag/jtag_libusb/list_usb_dev";
-			add_info($tview,"$command\n");
-			my ($stdout,$exit,$stderr)=run_cmd_in_back_ground_get_stdout($command);
-			if(length $stderr>1){			
-				add_colored_info($tview,"$stderr\n",'red');
-				add_colored_info($tview,"$command was not run successfully!\n",'red');
-			}else {
-	
-				if($exit){
-					add_colored_info($tview,"$stdout\n",'red');
-					add_colored_info($tview,"$command was not run successfully!\n",'red');
-				}else{
-					add_info($tview,"$stdout\n");
-					my @a=split /vid=9fb/, $stdout; 
-					if(defined $a[1]){
-						my @b=split /pid=/, $a[1]; 
-						my @c=split /\n/, $b[1]; 
-						$pid=$c[0]; 
-						$self->object_add_attribute('compile','quartus_pid',$pid);
-						add_colored_info($tview,"Detected PID: $pid\n",'blue');
-						
-					}else{
-						add_colored_info($tview,"The Altera vendor ID of 9fb is not detected. Make sure You have connected your Altera board to your USB port\n",'red');
-						return;
-					}
-				}
-			}
-			
-			
-			$command=  "$ENV{QUARTUS_BIN}/jtagconfig";
-			add_info($tview,"$command\n");
-			($stdout,$exit,$stderr)=run_cmd_in_back_ground_get_stdout($command);
-			if(length $stderr>1){			
-				add_colored_info($tview,"$stderr\n",'red');
-				add_colored_info($tview,"$command was not run successfully!\n",'red');
-			}else {
-	
-				if($exit){
-					add_colored_info($tview,"$stdout\n",'red');
-					add_colored_info($tview,"$command was not run successfully!\n",'red');
-				}else{
-					add_info($tview,"$stdout\n");
-					my @a=split /1\)\s+/, $stdout; 
-					if(defined $a[1]){
-						my @b=split /\s+/, $a[1]; 
-						$hw=$b[0];
-						$self->object_add_attribute('compile','quartus_hardware',$hw);
-						add_colored_info($tview,"Detected Hardware: $hw\n",'blue');
-						my $qsf=$self->object_get_attribute('compile','board_confg_file');	
-						if(!defined $qsf ){
-							add_colored_info ($tview,"Cannot detect device location in JTAG chin. Please enter the QSF file or fill in manually \n",'red'); 
-											
-						}else{
-							#search for device name in qsf file
-							$qsf=add_project_dir_to_addr($qsf);
-							if (!(-f $qsf)){
-								add_colored_info($tview, "Error Could not find $qsf file!\n");
-								return;
-							}
-							my $str=load_file($qsf);
-							my $dw= capture_string_between(' DEVICE ',$str,"\n");
-							if(defined $dw){
-						    	add_colored_info($tview,"Device name in qsf file is: $dw\n",'blue');
-						    	@b=split /\n/, $a[1];
-						    	
-						    	#capture device name in JTAG chain
-								my @f=(0);
-								foreach my $c (@b){
-									my @e=split /\s+/, $c;
-									push(@f,$e[2]) if(defined $e[2]);
-								} 
-								
-								my $pos=find_the_most_similar_position($dw ,@f);
-								$self->object_add_attribute('compile','quartus_device',$pos);
-						    	add_colored_info($tview,"$dw has the most similarity with $f[$pos] in JTAG chain\n",'blue');
-		
-							
-						    }else{
-						    	add_colored_info ($tview, "Could not find device name in the $qsf file!\n");
-						    }
-							
-						}
-						
-						
-					}else{
-						#add_colored_info($tview,"The Altera vendor ID of 9fb is not detected. Make sure You have connected your Altera board to your USB port\n",'red');
-					
-					}
-					
-				}
-			}
-			$widgets->destroy();
-			$widgets= add_new_altera_fpga_board_widgets($self,$name,$top,$target_dir,$end_func,$vendor);
-			$v1-> pack1($widgets, TRUE, TRUE); 	
-			#$table->attach_defaults($widgets,0,3,0,1); 
-			$table->show_all();		
-		 #	my $cmd=" $ENV{'QUARTUS_BIN'}"
-	 	
-		});
-	
-	
-	}
-	
-	
-	
-		
-	$window->add ($mtable);
-	$window->show_all();
-	
+    my ($self,$name,$top,$target_dir,$end_func,$vendor)=@_;    
+    my $window = def_popwin_size(50,80,"Add New $vendor FPGA Board",'percent');
+    my $table = def_table(2, 2, FALSE);
+    my $scrolled_win=add_widget_to_scrolled_win($table);
+    my $mtable = def_table(10, 10, FALSE);
+    my $next=def_image_button('icons/plus.png','Add');
+    my $back=def_image_button('icons/left.png','Previous');     
+    $mtable->attach_defaults($scrolled_win,0,10,0,9);
+    $mtable->attach($back,2,3,9,10,'shrink','shrink',2,2) if (defined $name);    
+    $mtable->attach($next,8,9,9,10,'shrink','shrink',2,2);
+    my ($Twin,$tview)=create_txview();
+    my $widgets=
+        ($vendor eq 'Altera')? add_new_altera_fpga_board_widgets($self,$name,$top,$target_dir,$end_func,$vendor):
+        add_new_xilinx_fpga_board_widgets($self,$name,$top,$target_dir,$end_func,$vendor,$tview);
+    my $v1=gen_vpaned($widgets,0.3,$Twin);
+    $table->attach_defaults($v1,0,3,0,2); 
+    #$table->attach_defaults( $Twin,0,3,1,2);     
+    $back-> signal_connect("clicked" => sub{ 
+        $window->destroy;
+        select_compiler($self,$name,$top,$target_dir,$end_func);
+    });
+    $next-> signal_connect("clicked" => sub{ 
+        my $result = ($vendor eq 'Altera')? 
+            add_new_altera_fpga_board_files($self,$vendor):
+            add_new_xilinx_fpga_board_files($self,$vendor); 
+            
+        if(! defined $result ){
+            select_compiler($self,$name,$top,$target_dir,$end_func) if (defined $name);    
+            $window->destroy;
+            message_dialog("The new board has been added successfully!");            
+        }else {
+            show_info($tview," ");
+            show_colored_info($tview,$result,'red');            
+        }    
+    });
+    
+    if($vendor eq 'Altera'){
+        my $auto=def_image_button('icons/advance.png','Auto-fill'); 
+        set_tip($auto, "Auto-fill JTAG configuration. The board must be powered on and be connected to the PC."); 
+        $mtable->attach($auto,5,6,9,10,'shrink','shrink',2,2);
+        $auto-> signal_connect("clicked" => sub{ 
+            my $pid;
+            my $hw;
+            my $project_dir      = get_project_dir();        
+            my $command=  "$project_dir/mpsoc/src_c/jtag/jtag_libusb/list_usb_dev";
+            add_info($tview,"$command\n");
+            my ($stdout,$exit,$stderr)=run_cmd_in_back_ground_get_stdout($command);
+            if(length $stderr>1){            
+                add_colored_info($tview,"$stderr\n",'red');
+                add_colored_info($tview,"$command was not run successfully!\n",'red');
+            }else {
+                if($exit){
+                    add_colored_info($tview,"$stdout\n",'red');
+                    add_colored_info($tview,"$command was not run successfully!\n",'red');
+                }else{
+                    add_info($tview,"$stdout\n");
+                    my @a=split /vid=9fb/, $stdout; 
+                    if(defined $a[1]){
+                        my @b=split /pid=/, $a[1]; 
+                        my @c=split /\n/, $b[1]; 
+                        $pid=$c[0]; 
+                        $self->object_add_attribute('compile','quartus_pid',$pid);
+                        add_colored_info($tview,"Detected PID: $pid\n",'blue');
+                    }else{
+                        add_colored_info($tview,"The Altera vendor ID of 9fb is not detected. Make sure You have connected your Altera board to your USB port\n",'red');
+                        return;
+                    }
+                }
+            }
+            $command=  "$ENV{QUARTUS_BIN}/jtagconfig";
+            add_info($tview,"$command\n");
+            ($stdout,$exit,$stderr)=run_cmd_in_back_ground_get_stdout($command);
+            if(length $stderr>1){            
+                add_colored_info($tview,"$stderr\n",'red');
+                add_colored_info($tview,"$command was not run successfully!\n",'red');
+            }else {
+                if($exit){
+                    add_colored_info($tview,"$stdout\n",'red');
+                    add_colored_info($tview,"$command was not run successfully!\n",'red');
+                }else{
+                    add_info($tview,"$stdout\n");
+                    my @a=split /1\)\s+/, $stdout; 
+                    if(defined $a[1]){
+                        my @b=split /\s+/, $a[1]; 
+                        $hw=$b[0];
+                        $self->object_add_attribute('compile','quartus_hardware',$hw);
+                        add_colored_info($tview,"Detected Hardware: $hw\n",'blue');
+                        my $qsf=$self->object_get_attribute('compile','board_confg_file');    
+                        if(!defined $qsf ){
+                            add_colored_info ($tview,"Cannot detect device location in JTAG chin. Please enter the QSF file or fill in manually \n",'red'); 
+                                            
+                        }else{
+                            #search for device name in qsf file
+                            $qsf=add_project_dir_to_addr($qsf);
+                            if (!(-f $qsf)){
+                                add_colored_info($tview, "Error Could not find $qsf file!\n");
+                                return;
+                            }
+                            my $str=load_file($qsf);
+                            my $dw= capture_string_between(' DEVICE ',$str,"\n");
+                            if(defined $dw){
+                                add_colored_info($tview,"Device name in qsf file is: $dw\n",'blue');
+                                @b=split /\n/, $a[1];
+                                
+                                #capture device name in JTAG chain
+                                my @f=(0);
+                                foreach my $c (@b){
+                                    my @e=split /\s+/, $c;
+                                    push(@f,$e[2]) if(defined $e[2]);
+                                } 
+                                my $pos=find_the_most_similar_position($dw ,@f);
+                                $self->object_add_attribute('compile','quartus_device',$pos);
+                                add_colored_info($tview,"$dw has the most similarity with $f[$pos] in JTAG chain\n",'blue');
+                            }else{
+                                add_colored_info ($tview, "Could not find device name in the $qsf file!\n");
+                            }
+                        }
+                    }else{
+                        #add_colored_info($tview,"The Altera vendor ID of 9fb is not detected. Make sure You have connected your Altera board to your USB port\n",'red');
+                    }
+                }
+            }
+            $widgets->destroy();
+            $widgets= add_new_altera_fpga_board_widgets($self,$name,$top,$target_dir,$end_func,$vendor);
+            $v1-> pack1($widgets, TRUE, TRUE);     
+            #$table->attach_defaults($widgets,0,3,0,1); 
+            $table->show_all();        
+            #my $cmd=" $ENV{'QUARTUS_BIN'}"
+        });
+    }
+    $window->add ($mtable);
+    $window->show_all();
 }
 
-
-
 sub add_new_xilinx_fpga_board_widgets{
-	my ($self,$name,$top,$target_dir,$end_func,$vendor,$tview)=@_;	
-	my $table = def_table(2, 2, FALSE);
-	
-	my $col=0;
-	my $row=0;
-		
-	my $help1="Your given FPGA Board name. Do not use any space in given name";
-	my $help2="Path to FPGA board xdc file. In your Xilinx board installation CD or in the Internet, search for a xdc file containing your FPGA device pin assignment constrain).";
-	my $help3="Path to FPGA_board_top.v file. A Verilog file containing all your FPGA device IO ports.";
-	my $help4="Your Board name (Board PART) e.g. digilentinc.com:arty-z7-20:part0:1.0";
-	my $help5="Your FPGA device name (PART) e.g. xc7z020clg400-1 ";
-	my $help6="The order number of target device in jtag chain. Run jtag targets after \"connect\" command in xsct terminal to list all available targets.";
-	my $help7="Path to Vivado board files repository. E.g download the repo from https://github.com/Digilent/vivado-boards and save in \$ProNoC_work/toolchain/board_files folder.";
-	my $help8="Hardware device name e.g. xc7z020_1. To find it you can connect your FPGA board to your PC. In tcl terminal run 
-		open_hw  
-		connect_hw_server 
-		open_hw_target
-		get_hw_devices
-It supposed to show the list of your hardware devices in your FPGA. Select the name represent your FPGA device		
-		";
-	
-	
-	my $repo ="$ENV{PRONOC_WORK}/toolchain/board_files";
-	
-	
-	$row++;
-	
-	my @info = ( 
-	{ label=>"FPGA board display name:",        param_name=>'fpga_board', type=>"Entry",     default_val=>undef, content=>undef, info=>$help1, param_parent=>'compile', ref_delay=> undef},  	
-   	{ label=>"Set board repo:", param_name=>'fpga_board_repo',  type=>"DIR_path", default_val=>"$repo", content=>undef, info=>$help7, param_parent=>'compile',ref_delay=>undef},	
-   	{ label=>"FPGA board part name:", param_name=>'fpga_board_part', type=>"EntryCombo",default_val=>undef, content=>undef, info =>$help4, param_parent=>'compile', ref_delay=> undef},
-   	{ label=>"FPGA part name:",       param_name=>'fpga_part', type=>"Entry",     default_val=>undef, content=>undef, info=>$help5, param_parent=>'compile', ref_delay=> undef},  
+    my ($self,$name,$top,$target_dir,$end_func,$vendor,$tview)=@_;    
+    my $table = def_table(2, 2, FALSE);
+    my $col=0;
+    my $row=0;
+    my $help1="Your given FPGA Board name. Do not use any space in given name";
+    my $help2="Path to FPGA board xdc file. In your Xilinx board installation CD or in the Internet, search for a xdc file containing your FPGA device pin assignment constrain).";
+    my $help3="Path to FPGA_board_top.v file. A Verilog file containing all your FPGA device IO ports.";
+    my $help4="Your Board name (Board PART) e.g. digilentinc.com:arty-z7-20:part0:1.0";
+    my $help5="Your FPGA device name (PART) e.g. xc7z020clg400-1 ";
+    my $help6="The order number of target device in jtag chain. Run jtag targets after \"connect\" command in xsct terminal to list all available targets.";
+    my $help7="Path to Vivado board files repository. E.g download the repo from https://github.com/Digilent/vivado-boards and save in \$ProNoC_work/toolchain/board_files folder.";
+    my $help8="Hardware device name e.g. xc7z020_1. To find it you can connect your FPGA board to your PC. In tcl terminal run 
+        open_hw  
+        connect_hw_server 
+        open_hw_target
+        get_hw_devices
+It supposed to show the list of your hardware devices in your FPGA. Select the name represent your FPGA device        
+        ";
+    my $repo ="$ENV{PRONOC_WORK}/toolchain/board_files";
+    $row++;
+    my @info = ( 
+    { label=>"FPGA board display name:",        param_name=>'fpga_board', type=>"Entry",     default_val=>undef, content=>undef, info=>$help1, param_parent=>'compile', ref_delay=> undef},      
+    { label=>"Set board repo:", param_name=>'fpga_board_repo',  type=>"DIR_path", default_val=>"$repo", content=>undef, info=>$help7, param_parent=>'compile',ref_delay=>undef},    
+    { label=>"FPGA board part name:", param_name=>'fpga_board_part', type=>"EntryCombo",default_val=>undef, content=>undef, info =>$help4, param_parent=>'compile', ref_delay=> undef},
+    { label=>"FPGA part name:",       param_name=>'fpga_part', type=>"Entry",     default_val=>undef, content=>undef, info=>$help5, param_parent=>'compile', ref_delay=> undef},  
     { label=>"FPGA Hardware device name:", param_name=>'fpga_hw_device', type=>"EntryCombo", default_val=>undef, content=>undef, info=>$help8, param_parent=>'compile', ref_delay=> undef},  
-  	{ label=>"Target device JTAG chain order number", param_name=>'fpga_board_order',  type=>"Spin-button", default_val=>1, content=>"0,256,1", info=>$help6, param_parent=>'compile',ref_delay=>undef},  	
-  	{ label=>'FPGA board xdc file:',    param_name=>'board_confg_file',   type=>"FILE_path", default_val=>undef, content=>"xdc", info=>$help2, param_parent=>'compile', ref_delay=>undef},
-	{ label=>"FPGA board golden top Verilog file", param_name=>'fpga_board_v',     type=>"FILE_path", default_val=>undef, content=>"v", info=>$help3, param_parent=>'compile',ref_delay=>undef},
-		);
-	my %widgets;
-	my %rows;
-	foreach my $d (@info) {
-		$rows{$d->{param_name}} =$row; 
-		($row,$col,$widgets{$d->{param_name}})=add_param_widget ($self, $d->{label}, $d->{param_name}, $d->{default_val}, $d->{type}, $d->{content}, $d->{info}, $table,$row,$col,1, $d->{param_parent}, $d->{ref_delay},undef,'vertical');
-	}
-	
-	my $icon = 'icons/advance.png';
-	my $search=def_image_button($icon,undef); 
-	my $search_board=def_image_button ($icon,undef); 
-	my $search_dev=def_image_button ($icon,undef);
-	my $search_chain=def_image_button ($icon,undef);  
-	
-	$table->attach($search,4,5,$rows{'fpga_board_part'},$rows{'fpga_board_part'}+1,'fill','shrink',2,2); 
-	$table->attach($search_board,4,5,$rows{'fpga_part'},$rows{'fpga_part'}+1,'fill','shrink',2,2); 
-	$table->attach($search_dev,4,5,$rows{'fpga_hw_device'},$rows{'fpga_hw_device'}+1,'fill','shrink',2,2);
-	$table->attach($search_chain,4,5,$rows{'fpga_board_order'},$rows{'fpga_board_order'}+1,'fill','shrink',2,2);
-	
-	
-	$search->signal_connect("clicked" => sub{
-			my $load= show_gif("icons/load.gif");
-			$table->attach ($load,5, 6, $rows{'fpga_board_part'},$rows{'fpga_board_part'}+ 1,'shrink','shrink',0,0);
-			$table->show_all;
-			my $result=	set_xilinx_board_from_repo($self,$tview);
-			update_combo_entry_content($widgets{'fpga_board_part'}, $result);
-			$load->destroy;
-			$table->show_all;
-		}); 
-	
-	
-	$search_board->signal_connect("clicked" => sub{
-			my $load= show_gif("icons/load.gif");
-			$table->attach ($load,5, 6, $rows{'fpga_part'},$rows{'fpga_part'}+1, 'shrink','shrink',0,0);
-			$table->show_all;
-			my $result=	get_xilinx_board_part($self,$tview);
-			$widgets{'fpga_part'}->set_text($result);			
-			#print "result = $result\n";
-			$load->destroy;
-			$table->show_all;
-		}); 
-	$search_dev->signal_connect("clicked" => sub{
-			my $load= show_gif("icons/load.gif");
-			$table->attach ($load,5, 6, $rows{'fpga_hw_device'},$rows{'fpga_hw_device'}+ 1,'shrink','shrink',0,0);
-			$table->show_all;
-			my $result=	get_xilinx_device_names($self,$tview);
-			update_combo_entry_content($widgets{'fpga_hw_device'}, $result);
-			$load->destroy;
-			$table->show_all;
-		}); 
-	$search_chain->signal_connect("clicked" => sub{
-		my $targets = show_all_xilinx_targets($self,$tview);
-		if(!defined $targets){
-			add_info($tview,"Unable to find the FPGA board target list. Make sure you have connected your FPGA board to your PC first and it is powered on.\n");
-			return;
-		}
-		
-		my @lines=split(/\r?\n/,$targets);
-		my @list1;
-		my @list2;
-		foreach my $p (@lines){
-			$p =~ s/^\s+//;#left trim
-			my @words=split(/\s+/,$p);
-			push (@list1,$words[0]);
-			push (@list2,$words[1]);
-		}
-		my $hw =  $self->object_get_attribute('compile','fpga_hw_device');
-		if( !defined $hw){
-			add_colored_info($tview,"Please define the FPGA hardware device name first!\n",'red');
-			return;
-		}
-		my $pos = find_the_most_similar_position ($hw ,@list2);
-		add_info($tview,"$hw matched with target $list1[$pos] $list2[$pos]  ");
-		$widgets{'fpga_board_order'}->set_value($list1[$pos]);
-	});
-	
-	return ($row, $col, $table);	
+    { label=>"Target device JTAG chain order number", param_name=>'fpga_board_order',  type=>"Spin-button", default_val=>1, content=>"0,256,1", info=>$help6, param_parent=>'compile',ref_delay=>undef},      
+    { label=>'FPGA board xdc file:',    param_name=>'board_confg_file',   type=>"FILE_path", default_val=>undef, content=>"xdc", info=>$help2, param_parent=>'compile', ref_delay=>undef},
+    { label=>"FPGA board golden top Verilog file", param_name=>'fpga_board_v',     type=>"FILE_path", default_val=>undef, content=>"v", info=>$help3, param_parent=>'compile',ref_delay=>undef},
+    );
+    my %widgets;
+    my %rows;
+    foreach my $d (@info) {
+        $rows{$d->{param_name}} =$row; 
+        ($row,$col,$widgets{$d->{param_name}})=add_param_widget ($self, $d->{label}, $d->{param_name}, $d->{default_val}, $d->{type}, $d->{content}, $d->{info}, $table,$row,$col,1, $d->{param_parent}, $d->{ref_delay},undef,'vertical');
+    }
+    my $icon = 'icons/advance.png';
+    my $search=def_image_button($icon,undef); 
+    my $search_board=def_image_button ($icon,undef); 
+    my $search_dev=def_image_button ($icon,undef);
+    my $search_chain=def_image_button ($icon,undef);  
+    
+    $table->attach($search,4,5,$rows{'fpga_board_part'},$rows{'fpga_board_part'}+1,'fill','shrink',2,2); 
+    $table->attach($search_board,4,5,$rows{'fpga_part'},$rows{'fpga_part'}+1,'fill','shrink',2,2); 
+    $table->attach($search_dev,4,5,$rows{'fpga_hw_device'},$rows{'fpga_hw_device'}+1,'fill','shrink',2,2);
+    $table->attach($search_chain,4,5,$rows{'fpga_board_order'},$rows{'fpga_board_order'}+1,'fill','shrink',2,2);
+    $search->signal_connect("clicked" => sub{
+            my $load= show_gif("icons/load.gif");
+            $table->attach ($load,5, 6, $rows{'fpga_board_part'},$rows{'fpga_board_part'}+ 1,'shrink','shrink',0,0);
+            $table->show_all;
+            my $result=    set_xilinx_board_from_repo($self,$tview);
+            update_combo_entry_content($widgets{'fpga_board_part'}, $result);
+            $load->destroy;
+            $table->show_all;
+        });    
+    $search_board->signal_connect("clicked" => sub{
+            my $load= show_gif("icons/load.gif");
+            $table->attach ($load,5, 6, $rows{'fpga_part'},$rows{'fpga_part'}+1, 'shrink','shrink',0,0);
+            $table->show_all;
+            my $result=    get_xilinx_board_part($self,$tview);
+            $widgets{'fpga_part'}->set_text($result);            
+            #print "result = $result\n";
+            $load->destroy;
+            $table->show_all;
+        }); 
+    $search_dev->signal_connect("clicked" => sub{
+            my $load= show_gif("icons/load.gif");
+            $table->attach ($load,5, 6, $rows{'fpga_hw_device'},$rows{'fpga_hw_device'}+ 1,'shrink','shrink',0,0);
+            $table->show_all;
+            my $result=    get_xilinx_device_names($self,$tview);
+            update_combo_entry_content($widgets{'fpga_hw_device'}, $result);
+            $load->destroy;
+            $table->show_all;
+        }); 
+    $search_chain->signal_connect("clicked" => sub{
+        my $targets = show_all_xilinx_targets($self,$tview);
+        if(!defined $targets){
+            add_info($tview,"Unable to find the FPGA board target list. Make sure you have connected your FPGA board to your PC first and it is powered on.\n");
+            return;
+        }
+        
+        my @lines=split(/\r?\n/,$targets);
+        my @list1;
+        my @list2;
+        foreach my $p (@lines){
+            $p =~ s/^\s+//;#left trim
+            my @words=split(/\s+/,$p);
+            push (@list1,$words[0]);
+            push (@list2,$words[1]);
+        }
+        my $hw =  $self->object_get_attribute('compile','fpga_hw_device');
+        if( !defined $hw){
+            add_colored_info($tview,"Please define the FPGA hardware device name first!\n",'red');
+            return;
+        }
+        my $pos = find_the_most_similar_position ($hw ,@list2);
+        add_info($tview,"$hw matched with target $list1[$pos] $list2[$pos]  ");
+        $widgets{'fpga_board_order'}->set_value($list1[$pos]);
+    });
+    return ($row, $col, $table);    
 }
 
-
-	
 sub set_xilinx_board_from_repo{
-	my ($self,$tview)=@_;
-	my $bin =  $self->object_get_attribute('compile',"vivado bin");
-	my $vivado =(defined $bin)?  "${bin}/vivado" :  "vivado";
-	my $result;
-	my $repo= $self->object_get_attribute('compile','fpga_board_repo');	
-	my $tcl= get_project_dir()."/mpsoc/perl_gui/lib/tcl/vivado_get_boards.tcl -tclargs $repo";
-	my $command = "cd $ENV{PRONOC_WORK}/tmp;   $vivado -mode tcl -source $tcl";
-	
-	add_info($tview,"$command\n");
-	my $stdout=run_cmd_textview_errors($command,$tview);
-	return if (!defined $stdout); 
-	add_info($tview,"$stdout\n");
-	my @boards=split(/\s+/,$stdout);
-	my $r=0;
-	foreach my $board (@boards){
-		my @pp=split(':',$board);
-		if(scalar @pp  == 4 && $pp[1] =~ /[a-zA-Z]+/) {
-			$r=1;
-			$result= (!defined $result)? "$board" : $result.",$board";
-		} 
-	}
-	add_colored_info($tview,"$stdout\n",'red') if($r==0);
-	return $result;
-}	
-
+    my ($self,$tview)=@_;
+    my $bin =  $self->object_get_attribute('compile',"vivado bin");
+    my $vivado =(defined $bin)?  "${bin}/vivado" :  "vivado";
+    my $result;
+    my $repo= $self->object_get_attribute('compile','fpga_board_repo');    
+    my $tcl= get_project_dir()."/mpsoc/perl_gui/lib/tcl/vivado_get_boards.tcl -tclargs $repo";
+    my $command = "cd $ENV{PRONOC_WORK}/tmp;   $vivado -mode tcl -source $tcl";
+    add_info($tview,"$command\n");
+    my $stdout=run_cmd_textview_errors($command,$tview);
+    return if (!defined $stdout); 
+    add_info($tview,"$stdout\n");
+    my @boards=split(/\s+/,$stdout);
+    my $r=0;
+    foreach my $board (@boards){
+        my @pp=split(':',$board);
+        if(scalar @pp  == 4 && $pp[1] =~ /[a-zA-Z]+/) {
+            $r=1;
+            $result= (!defined $result)? "$board" : $result.",$board";
+        } 
+    }
+    add_colored_info($tview,"$stdout\n",'red') if($r==0);
+    return $result;
+}  
 
 sub get_xilinx_device_names{
-	my ($self,$tview)=@_;
-	my $bin =  $self->object_get_attribute('compile',"vivado bin");
-	my $vivado =(defined $bin)?  "${bin}/vivado" :  "vivado";
-	my $result;
-	my $repo= $self->object_get_attribute('compile','fpga_board_repo');	
-	my $tcl= get_project_dir()."/mpsoc/perl_gui/lib/tcl/vivado_get_hw_device.tcl -tclargs";
-	my $command = "cd $ENV{PRONOC_WORK}/tmp;   $vivado -mode tcl -source $tcl";
-	
-	add_info($tview,"$command\n");
-	my $stdout=run_cmd_textview_errors($command,$tview);
-	if (!defined $stdout){
-		add_info($tview,"Unable to find the FPGA board devices list. Make sure you have connected your FPGA board to your PC first and it is powered on.\n");
-		return;
-	} 
-	add_info($tview,"$stdout\n");
-	my $devices =  capture_string_between ('\n\*RESULT:',$stdout,"\n");	
-	my @D=split(/\s+/,$devices);
-	return join ',', @D;
-}	
-
-
-
+    my ($self,$tview)=@_;
+    my $bin =  $self->object_get_attribute('compile',"vivado bin");
+    my $vivado =(defined $bin)?  "${bin}/vivado" :  "vivado";
+    my $result;
+    my $repo= $self->object_get_attribute('compile','fpga_board_repo');    
+    my $tcl= get_project_dir()."/mpsoc/perl_gui/lib/tcl/vivado_get_hw_device.tcl -tclargs";
+    my $command = "cd $ENV{PRONOC_WORK}/tmp;   $vivado -mode tcl -source $tcl";
+    add_info($tview,"$command\n");
+    my $stdout=run_cmd_textview_errors($command,$tview);
+    if (!defined $stdout){
+        add_info($tview,"Unable to find the FPGA board devices list. Make sure you have connected your FPGA board to your PC first and it is powered on.\n");
+        return;
+    } 
+    add_info($tview,"$stdout\n");
+    my $devices =  capture_string_between ('\n\*RESULT:',$stdout,"\n");    
+    my @D=split(/\s+/,$devices);
+    return join ',', @D;
+}  
 
+sub get_xilinx_board_part{
+    my ($self,$tview)=@_;
+    my $bin =  $self->object_get_attribute('compile',"vivado bin");
+    my $vivado =(defined $bin)?  "${bin}/vivado" :  "vivado";
+    my $result;
+    my $repo= $self->object_get_attribute('compile','fpga_board_repo');    
+    my $board_part= $self->object_get_attribute('compile' ,'fpga_board_part');
+    if (!defined $board_part  ){
+        add_colored_info($tview,"Please define the FPGA board part name first!\n",'red');
+        return;
+    }    
+    my $tcl= get_project_dir()."/mpsoc/perl_gui/lib/tcl/vivado_get_part.tcl -tclargs $board_part $repo ";
+    my $command = "cd $ENV{PRONOC_WORK}/tmp;   $vivado -mode tcl -source $tcl";
+    add_info($tview,"$command\n");
+    my $stdout=run_cmd_textview_errors($command,$tview);
+    return if (!defined $stdout); 
+    add_info($tview,"$stdout\n");
+    return capture_string_between ('\n\*RESULT:',$stdout,"\n");    
+}    
 
 
-sub get_xilinx_board_part{
-	my ($self,$tview)=@_;
-	my $bin =  $self->object_get_attribute('compile',"vivado bin");
-	my $vivado =(defined $bin)?  "${bin}/vivado" :  "vivado";
-	my $result;
-	my $repo= $self->object_get_attribute('compile','fpga_board_repo');	
-	my $board_part= $self->object_get_attribute('compile' ,'fpga_board_part');
-	if (!defined $board_part  ){
-		add_colored_info($tview,"Please define the FPGA board part name first!\n",'red');
-		return;
-	}
-	
-	my $tcl= get_project_dir()."/mpsoc/perl_gui/lib/tcl/vivado_get_part.tcl -tclargs $board_part $repo ";
-	
-	
-	my $command = "cd $ENV{PRONOC_WORK}/tmp;   $vivado -mode tcl -source $tcl";
-	
-	add_info($tview,"$command\n");
-	my $stdout=run_cmd_textview_errors($command,$tview);
-	return if (!defined $stdout); 
-	add_info($tview,"$stdout\n");
-	return capture_string_between ('\n\*RESULT:',$stdout,"\n");	
-}	
-
-
-	
 sub add_new_altera_fpga_board_widgets{
-	my ($self,$name,$top,$target_dir,$end_func,$vendor)=@_;	
-	my $table = def_table(2, 2, FALSE);
-		
-	my $help1="FPGA Board name. Do not use any space in given name";
-	my $help2="Path to FPGA board qsf file. In your Altra board installation CD or in the Internet search for a QSF file containing your FPGA device name with other necessary global project setting including the pin assignments (e.g DE10_Nano_golden_top.qsf).";
-	my $help3="Path to FPGA_board_top.v file. In your Altra board installation CD or in the Internet search for a Verilog file containing all your FPGA device IO ports (e.g DE10_Nano_golden_top.v).";
-	my $help4="FPGA Board USB-Blaster product ID (PID). Power on your FPGA board and connect it to your PC. Then press Auto-fill button to find PID. Optionally you can run mpsoc/
+    my ($self,$name,$top,$target_dir,$end_func,$vendor)=@_;    
+    my $table = def_table(2, 2, FALSE);
+    my $help1="FPGA Board name. Do not use any space in given name";
+    my $help2="Path to FPGA board qsf file. In your Altra board installation CD or in the Internet search for a QSF file containing your FPGA device name with other necessary global project setting including the pin assignments (e.g DE10_Nano_golden_top.qsf).";
+    my $help3="Path to FPGA_board_top.v file. In your Altra board installation CD or in the Internet search for a Verilog file containing all your FPGA device IO ports (e.g DE10_Nano_golden_top.v).";
+    my $help4="FPGA Board USB-Blaster product ID (PID). Power on your FPGA board and connect it to your PC. Then press Auto-fill button to find PID. Optionally you can run mpsoc/
 src_c/jtag/jtag_libusb/list_usb_dev to find your USB-Blaster PID. Search for PID of a device having 9fb (altera) Vendor ID (VID)";
-	my $help5="Power on your FPGA board and connect it to your PC. Then press Auto-fill button to find your hardware name. Optionally you can run \$QUARTUS_BIN/jtagconfig to find your programming hardware name. 
+    my $help5="Power on your FPGA board and connect it to your PC. Then press Auto-fill button to find your hardware name. Optionally you can run \$QUARTUS_BIN/jtagconfig to find your programming hardware name. 
 an example of output from the 'jtagconfig' command:
 \t  1) ByteBlasterMV on LPT1
 \t       090010DD   EPXA10
@@ -819,219 +647,173 @@ sub add_new_altera_fpga_board_widgets{
 \t       48A00477   SOCVHP5 
 \t       02D020DC   5CS(EBA6ES|XFC6c6ES)   
 ByteBlasterMV \& DE-SoC are the programming hardware name.";
-my $help6="Power on your FPGA board and connect it to your PC. Then press Auto-fill button to find your device location in jtag chain. Optionally you can run \$QUARTUS_BIN/jtagconfig to find your target device location in jtag chain."; 
-		   
-
-
-
-	my @info = (
-	{ label=>"FPGA Board Name:",                   param_name=>'fpga_board', type=>"Entry",     default_val=>undef, content=>undef, info=>$help1, param_parent=>'compile', ref_delay=> undef},
-  	{ label=>'FPGA Board Golden top QSF file:',    param_name=>'board_confg_file',   type=>"FILE_path", default_val=>undef, content=>"qsf", info=>$help2, param_parent=>'compile', ref_delay=>undef},
-	{ label=>"FPGA Board Golden top Verilog file", param_name=>'fpga_board_v',     type=>"FILE_path", default_val=>undef, content=>"v", info=>$help3, param_parent=>'compile',ref_delay=>undef },
-	);
-	
-	my @usb = (
-	{ label=>"FPGA Board USB Blaster PID:",        param_name=>'quartus_pid',   type=>"Entry",     default_val=>undef, content=>undef, info=>$help4, param_parent=>'compile', ref_delay=> undef},
-	{ label=>"FPGA Board Programming Hardware Name:", param_name=>'quartus_hardware',   type=>"Entry",     default_val=>undef, content=>undef, info=>$help5, param_parent=>'compile', ref_delay=> undef},
-	{ label=>"FPGA Board Device location in JTAG chain:", param_name=>'quartus_device',   type=>"Spin-button",     default_val=>0, content=>"0,100,1", info=>$help6, param_parent=>'compile', ref_delay=> undef},
-	);	
-	
-	
-	my $col=0;
-	my $row=0;
-	foreach my $d (@info) {
-		($row,$col)=add_param_widget ($self, $d->{label}, $d->{param_name}, $d->{default_val}, $d->{type}, $d->{content}, $d->{info}, $table,$row,$col,1, $d->{param_parent}, $d->{ref_delay},undef,"vertical");
-	}
-	
-	my $labl=def_pack_vbox(FALSE, 0,(gen_Hsep(),gen_label_in_center("FPGA Board JTAG Configuration"),gen_Hsep()));
-		
-	$table->attach( $labl,0,3,$row,$row+1,'fill','shrink',2,2); $row++; $col=0;
-	
-	foreach my $d (@usb) {
-		($row,$col)=add_param_widget ($self, $d->{label}, $d->{param_name}, $d->{default_val}, $d->{type}, $d->{content}, $d->{info}, $table,$row,$col,1, $d->{param_parent}, $d->{ref_delay},undef,"vertical");
-	}
-	
-	
-	return ($row, $col, $table);	
+    my $help6="Power on your FPGA board and connect it to your PC. Then press Auto-fill button to find your device location in jtag chain. Optionally you can run \$QUARTUS_BIN/jtagconfig to find your target device location in jtag chain."; 
+    my @info = (
+    { label=>"FPGA Board Name:",                   param_name=>'fpga_board', type=>"Entry",     default_val=>undef, content=>undef, info=>$help1, param_parent=>'compile', ref_delay=> undef},
+    { label=>'FPGA Board Golden top QSF file:',    param_name=>'board_confg_file',   type=>"FILE_path", default_val=>undef, content=>"qsf", info=>$help2, param_parent=>'compile', ref_delay=>undef},
+    { label=>"FPGA Board Golden top Verilog file", param_name=>'fpga_board_v',     type=>"FILE_path", default_val=>undef, content=>"v", info=>$help3, param_parent=>'compile',ref_delay=>undef },
+    );
+    my @usb = (
+    { label=>"FPGA Board USB Blaster PID:",        param_name=>'quartus_pid',   type=>"Entry",     default_val=>undef, content=>undef, info=>$help4, param_parent=>'compile', ref_delay=> undef},
+    { label=>"FPGA Board Programming Hardware Name:", param_name=>'quartus_hardware',   type=>"Entry",     default_val=>undef, content=>undef, info=>$help5, param_parent=>'compile', ref_delay=> undef},
+    { label=>"FPGA Board Device location in JTAG chain:", param_name=>'quartus_device',   type=>"Spin-button",     default_val=>0, content=>"0,100,1", info=>$help6, param_parent=>'compile', ref_delay=> undef},
+    );    
+    my $col=0;
+    my $row=0;
+    foreach my $d (@info) {
+        ($row,$col)=add_param_widget ($self, $d->{label}, $d->{param_name}, $d->{default_val}, $d->{type}, $d->{content}, $d->{info}, $table,$row,$col,1, $d->{param_parent}, $d->{ref_delay},undef,"vertical");
+    }
+    my $labl=def_pack_vbox(FALSE, 0,(gen_Hsep(),gen_label_in_center("FPGA Board JTAG Configuration"),gen_Hsep()));
+    $table->attach( $labl,0,3,$row,$row+1,'fill','shrink',2,2); $row++; $col=0;
+    foreach my $d (@usb) {
+        ($row,$col)=add_param_widget ($self, $d->{label}, $d->{param_name}, $d->{default_val}, $d->{type}, $d->{content}, $d->{info}, $table,$row,$col,1, $d->{param_parent}, $d->{ref_delay},undef,"vertical");
+    }
+    return ($row, $col, $table);    
 }
 
-
 sub add_new_xilinx_fpga_board_files{
-	my ($self,$vendor)=@_;	
-	#check the board name
-	my $board_name=$self->object_get_attribute('compile','fpga_board');
-	return "Please define the Board Name\n" if(! defined $board_name ); 
-	return "Please define the Board Name\n" if(length($board_name) ==0 ); 
-	my $r=check_verilog_identifier_syntax($board_name);	
-	return "Error in given Board Name: $r\n" if(defined $r ); 
-	
-	#check xdc file 
-	my $xdc=$self->object_get_attribute('compile','board_confg_file');	
-	return "Please define the xdc file\n" if(!defined $xdc );
-	$xdc=add_project_dir_to_addr($xdc);
-	
-	#check v file 
-	my $top=$self->object_get_attribute('compile','fpga_board_v');
-	return "Please define the verilog file file\n" if(!defined $top );
-	$top=add_project_dir_to_addr($top);
-	
-	#check board part 
-	my $part=$self->object_get_attribute('compile','fpga_part');
-	my $board_part=$self->object_get_attribute('compile','fpga_board_part');
-	return "Please define at least one of FPGA board part or FPGA part names"if(!defined $part && !defined $board_part  );   
-	
-	#make board directory
-	my $project_dir = get_project_dir();
-	my $path="$project_dir/mpsoc/boards/$vendor/$board_name";
-	mkpath($path,1,01777);
-	return "Error cannot make $path path" if ((-d $path)==0);
-	copy( $xdc,"$path/$board_name.xdc");
-	copy($top,"$path/$board_name.v");
-	
-
-	
-	my $a=$self->object_get_attribute('compile','fpga_board_order');
-	my $jtag_intfc="#!/bin/bash
+    my ($self,$vendor)=@_;    
+    #check the board name
+    my $board_name=$self->object_get_attribute('compile','fpga_board');
+    return "Please define the Board Name\n" if(! defined $board_name ); 
+    return "Please define the Board Name\n" if(length($board_name) ==0 ); 
+    my $r=check_verilog_identifier_syntax($board_name);    
+    return "Error in given Board Name: $r\n" if(defined $r ); 
+    #check xdc file 
+    my $xdc=$self->object_get_attribute('compile','board_confg_file');    
+    return "Please define the xdc file\n" if(!defined $xdc );
+    $xdc=add_project_dir_to_addr($xdc);
+    #check v file 
+    my $top=$self->object_get_attribute('compile','fpga_board_v');
+    return "Please define the verilog file file\n" if(!defined $top );
+    $top=add_project_dir_to_addr($top);
+    #check board part 
+    my $part=$self->object_get_attribute('compile','fpga_part');
+    my $board_part=$self->object_get_attribute('compile','fpga_board_part');
+    return "Please define at least one of FPGA board part or FPGA part names"if(!defined $part && !defined $board_part  );   
+    #make board directory
+    my $project_dir = get_project_dir();
+    my $path="$project_dir/mpsoc/boards/$vendor/$board_name";
+    mkpath($path,1,01777);
+    return "Error cannot make $path path" if ((-d $path)==0);
+    copy( $xdc,"$path/$board_name.xdc");
+    copy($top,"$path/$board_name.v");
+    my $a=$self->object_get_attribute('compile','fpga_board_order');
+    my $jtag_intfc="#!/bin/bash
 JTAG_INTFC=\"\$PRONOC_WORK/toolchain/bin/jtag_xilinx_xsct -a $a -b 36\"
 #it works only for 32-bit jtag data width for 64 pass -b 68 
 ";
-	save_file ("$path/jtag_intfc.sh",$jtag_intfc);	
-	
-	
-	my $bin =  $self->object_get_attribute('compile',"vivado bin");
+    save_file ("$path/jtag_intfc.sh",$jtag_intfc);    
+    my $bin =  $self->object_get_attribute('compile',"vivado bin");
     my $hw_dev=$self->object_get_attribute('compile',"fpga_hw_device");
     my $repo=  $self->object_get_attribute('compile','fpga_board_repo');
-	
-	
-	my $tcl="proc set_project_properties { } {\n";
-	if(-d $repo){
-		$tcl=$tcl."\tset_property  \"board_part_repo_paths\" [list \"$repo\"] [current_project]\n";
-	}else {
-		$tcl=$tcl."\tset_property  \"board_part_repo_paths\" [get_property LOCAL_ROOT_DIR [xhub::get_xstores xilinx_board_store]] [current_project]\n" if(defined $board_part);
-	}
-	$tcl=$tcl."\tset_property \"part\" \"$part\" [current_project]\n" if(defined $part);
-	$tcl=$tcl."\tset_property \"board_part\" \"$board_part\" [current_project]\n" if(defined $board_part);
-	$tcl=$tcl."\tset_property \"default_lib\" \"xil_defaultlib\" [current_project]\n}\n";
-
-
-	
-	if (defined $hw_dev){
-$tcl=$tcl."\n	
+    my $tcl="proc set_project_properties { } {\n";
+    if(-d $repo){
+        $tcl=$tcl."\tset_property  \"board_part_repo_paths\" [list \"$repo\"] [current_project]\n";
+    }else {
+        $tcl=$tcl."\tset_property  \"board_part_repo_paths\" [get_property LOCAL_ROOT_DIR [xhub::get_xstores xilinx_board_store]] [current_project]\n" if(defined $board_part);
+    }
+    $tcl=$tcl."\tset_property \"part\" \"$part\" [current_project]\n" if(defined $part);
+    $tcl=$tcl."\tset_property \"board_part\" \"$board_part\" [current_project]\n" if(defined $board_part);
+    $tcl=$tcl."\tset_property \"default_lib\" \"xil_defaultlib\" [current_project]\n}\n";
+    if (defined $hw_dev){
+$tcl=$tcl."\n    
 proc program_board {bit_file} {
-	open_hw
-	connect_hw_server
-	open_hw_target
-	set_property PROGRAM.FILE \$bit_file [get_hw_devices $hw_dev]
-	program_hw_devices [get_hw_devices $hw_dev]
-	refresh_hw_device [get_hw_devices $hw_dev]
+    open_hw
+    connect_hw_server
+    open_hw_target
+    set_property PROGRAM.FILE \$bit_file [get_hw_devices $hw_dev]
+    program_hw_devices [get_hw_devices $hw_dev]
+    refresh_hw_device [get_hw_devices $hw_dev]
 }
-";	
-	}	
-	save_file ("$path/board_property.tcl",$tcl);
-	
-	
-	$self->object_add_attribute('compile','board',$board_name);		
-	return undef;
-	
-	
+";    
+    }    
+    save_file ("$path/board_property.tcl",$tcl);
+    $self->object_add_attribute('compile','board',$board_name);        
+    return undef;
 }
 
-
 sub add_new_altera_fpga_board_files{
-	my ($self,$vendor)=@_;
-	
-	#check the board name
-	my $board_name=$self->object_get_attribute('compile','fpga_board');
-	return "Please define the Board Name\n" if(! defined $board_name ); 
-	return "Please define the Board Name\n" if(length($board_name) ==0 ); 
-	my $r=check_verilog_identifier_syntax($board_name);	
-	return "Error in given Board Name: $r\n" if(defined $r ); 
-	
-	#check qsf file 
-	my $qsf=$self->object_get_attribute('compile','board_confg_file');	
-	return "Please define the QSF file\n" if(!defined $qsf );
-	
-	#check v file 
-	my $top=$self->object_get_attribute('compile','fpga_board_v');
-	return "Please define the verilog file file\n" if(!defined $top );
-	
-	#check PID
-	my $pid=$self->object_get_attribute('compile','quartus_pid');
-	return "Please define the PID\n" if(! defined $pid ); 
-	return "Please define the PID\n" if(length($pid) ==0 ); 
-	
-	#check Hardware name
-	my $hw=$self->object_get_attribute('compile','quartus_hardware');
-	return "Please define the Hardware Name\n" if(! defined $hw ); 
-	return "Please define the Hardware Name\n" if(length($hw) ==0 ); 
-	
-	
-	#check Device name name
-	my $dw=$self->object_get_attribute('compile','quartus_device');
-	return "Please define targeted Device location in JTAG chain. The device location must be larger than zero.\n" if( $dw == 0 ); 
-	
-	
-	
-	#make board directory
-	my $project_dir = get_project_dir();
-	my $path="$project_dir/mpsoc/boards/$vendor/$board_name";
-	mkpath($path,1,01777);
-	return "Error cannot make $path path" if ((-d $path)==0);
-	
-	#generate new qsf file
-	$qsf=add_project_dir_to_addr($qsf);
-	$top=add_project_dir_to_addr($top);
-	open my $file, "<", $qsf or return "Error Could not open $qsf file in read mode!";
-	open my $newqsf, ">", "$path/$board_name.qsf" or return "Error Could not create $path/$board_name.qsf file in write mode!";
-	
-	#remove the lines contain following strings
-	my @p=("TOP_LEVEL_ENTITY","VERILOG_FILE","SYSTEMVERILOG_FILE","VHDL_FILE","AHDL_FILE","PROJECT_OUTPUT_DIRECTORY" );
-	while (my $line = <$file>){
-		if ($line =~ /\Q$p[0]\E/ || $line =~ /\Q$p[1]\E/ || $line =~ /\Q$p[2]\E/ ||  $line =~ /\Q$p[3]\E/ ||  $line =~ /\Q$p[4]\E/){#dont copy the line contain TOP_LEVEL_ENTITY
-		
-		}
-		
-		else{			
-			print $newqsf $line;
-		}
-		
-	}
-	print $newqsf "\nset_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files\n";
-
-	close $newqsf;
-	close $file;
-	copy($top,"$path/$board_name.v");
-	
-	#generate jtag_intfc.sh
-	open $file, ">", "$path/jtag_intfc.sh" or return "Error: Could not create $path/jtag_intfc.sh file in write mode!";
-	my $jtag;
-	if($pid eq 6001 || $pid eq 6002 || $pid eq 6003){
-		$jtag="JTAG_INTFC=\"\$PRONOC_WORK/toolchain/bin/jtag_libusb -a \$PRODUCT_ID\"";	
-		
-	}else{
-		$jtag="JTAG_INTFC=\"\$PRONOC_WORK/toolchain/bin/jtag_quartus_stp -a \$HARDWARE_NAME -b \$DEVICE_NAME\"";
-		
-	}
-	print $file "#!/bin/bash
+    my ($self,$vendor)=@_;
+    #check the board name
+    my $board_name=$self->object_get_attribute('compile','fpga_board');
+    return "Please define the Board Name\n" if(! defined $board_name ); 
+    return "Please define the Board Name\n" if(length($board_name) ==0 ); 
+    my $r=check_verilog_identifier_syntax($board_name);    
+    return "Error in given Board Name: $r\n" if(defined $r ); 
+    #check qsf file 
+    my $qsf=$self->object_get_attribute('compile','board_confg_file');    
+    return "Please define the QSF file\n" if(!defined $qsf );
+    #check v file 
+    my $top=$self->object_get_attribute('compile','fpga_board_v');
+    return "Please define the verilog file file\n" if(!defined $top );
+    #check PID
+    my $pid=$self->object_get_attribute('compile','quartus_pid');
+    return "Please define the PID\n" if(! defined $pid ); 
+    return "Please define the PID\n" if(length($pid) ==0 ); 
+    #check Hardware name
+    my $hw=$self->object_get_attribute('compile','quartus_hardware');
+    return "Please define the Hardware Name\n" if(! defined $hw ); 
+    return "Please define the Hardware Name\n" if(length($hw) ==0 ); 
+    #check Device name name
+    my $dw=$self->object_get_attribute('compile','quartus_device');
+    return "Please define targeted Device location in JTAG chain. The device location must be larger than zero.\n" if( $dw == 0 ); 
+    #make board directory
+    my $project_dir = get_project_dir();
+    my $path="$project_dir/mpsoc/boards/$vendor/$board_name";
+    mkpath($path,1,01777);
+    return "Error cannot make $path path" if ((-d $path)==0);
+    #generate new qsf file
+    $qsf=add_project_dir_to_addr($qsf);
+    $top=add_project_dir_to_addr($top);
+    open my $file, "<", $qsf or return "Error Could not open $qsf file in read mode!";
+    open my $newqsf, ">", "$path/$board_name.qsf" or return "Error Could not create $path/$board_name.qsf file in write mode!";
+    #remove the lines contain following strings
+    my @p=("TOP_LEVEL_ENTITY","VERILOG_FILE","SYSTEMVERILOG_FILE","VHDL_FILE","AHDL_FILE","PROJECT_OUTPUT_DIRECTORY" );
+    while (my $line = <$file>){
+        if ($line =~ /\Q$p[0]\E/ || $line =~ /\Q$p[1]\E/ || $line =~ /\Q$p[2]\E/ ||  $line =~ /\Q$p[3]\E/ ||  $line =~ /\Q$p[4]\E/){#dont copy the line contain TOP_LEVEL_ENTITY
+        
+        }
+        
+        else{            
+            print $newqsf $line;
+        }
+        
+    }
+    print $newqsf "\nset_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files\n";
+    close $newqsf;
+    close $file;
+    copy($top,"$path/$board_name.v");
+    #generate jtag_intfc.sh
+    open $file, ">", "$path/jtag_intfc.sh" or return "Error: Could not create $path/jtag_intfc.sh file in write mode!";
+    my $jtag;
+    if($pid eq 6001 || $pid eq 6002 || $pid eq 6003){
+        $jtag="JTAG_INTFC=\"\$PRONOC_WORK/toolchain/bin/jtag_libusb -a \$PRODUCT_ID\"";    
+        
+    }else{
+        $jtag="JTAG_INTFC=\"\$PRONOC_WORK/toolchain/bin/jtag_quartus_stp -a \$HARDWARE_NAME -b \$DEVICE_NAME\"";
+        
+    }
+    print $file "#!/bin/bash
 
 PRODUCT_ID=\"0x$pid\" 
 HARDWARE_NAME=\'$hw *\'
 DEVICE_NAME=\"\@$dw*\" 
-	
+    
 $jtag
-		
-	";	
-	close $file;
-	
-	
-	#generate program_device.sh
-	open $file, ">", "$path/program_device.sh" or return "Error: Could not create $path/program_device.sh file in write mode!";
-	
-	
-print $file "#!/bin/bash
+        
+    ";    
+    close $file;
+    
+    
+    #generate program_device.sh
+    open $file, ">", "$path/program_device.sh" or return "Error: Could not create $path/program_device.sh file in write mode!";
+    
+    
+    print $file "#!/bin/bash
 
 #usage: 
-#	bash program_device.sh  programming_file.sof
+#    bash program_device.sh  programming_file.sof
 
 #programming file 
 #given as an argument:  \$1
@@ -1048,16 +830,15 @@ sub add_new_altera_fpga_board_files{
 
 #programming command
 if [ -n "${QUARTUS_BIN+set}" ]; then
-  $QUARTUS_BIN/quartus_pgm -m $PROG_MODE -c "$NAME" -o "p;${1}${DEVICE}"
+    $QUARTUS_BIN/quartus_pgm -m $PROG_MODE -c "$NAME" -o "p;${1}${DEVICE}"
 else
-  quartus_pgm -m $PROG_MODE -c "$NAME" -o "p;${1}${DEVICE}"
+    quartus_pgm -m $PROG_MODE -c "$NAME" -o "p;${1}${DEVICE}"
 fi
-';	
-	
-close $file;	
-$self->object_add_attribute('compile','board',$board_name);		
-	
-	return undef;
+';    
+
+    close $file;    
+    $self->object_add_attribute('compile','board',$board_name);        
+    return undef;
 }
 
 
@@ -1065,271 +846,213 @@ sub add_new_altera_fpga_board_files{
 
 
 sub  get_pin_assignment{
-	my ($self,$name,$top,$target_dir,$end_func,$vendor)=@_;	
-	my $window = def_popwin_size(80,80,"Step 2: Pin Assignment",'percent');
-
-	my $table = def_table(2, 2, FALSE);
-	my $scrolled_win = add_widget_to_scrolled_win($table);
-
-	my $mtable = def_table(10, 10, FALSE);	
-	my $next=def_image_button('icons/right.png','Next');
-	my $back=def_image_button('icons/left.png','Previous');	
-	$mtable->attach_defaults($scrolled_win,0,10,0,9);
-	$mtable->attach($back,2,3,9,10,'shrink','shrink',2,2);
-	$mtable->attach($next,8,9,9,10,'shrink','shrink',2,2);
-	
-	my $board_name=$self->object_get_attribute('compile','board');
-	
-	#copy board jtag_intfc.sh file 
-	my ($fname,$fpath,$fsuffix) = fileparse("$top",qr"\..[^.]*$");
-	copy("../boards/$vendor/$board_name/jtag_intfc.sh","${fpath}../sw/jtag_intfc.sh");	
-	my $m= $self->object_get_attribute('mpsoc_name',undef);
-	if(defined $m){	# we are compiling a complete NoC-based mpsoc						
-		 my ($nr,$ne,$router_p,$ref_tops)= get_noc_verilator_top_modules_info($self);
-    	 for (my $tile_num=0;$tile_num<$ne;$tile_num++){
-		    #print "$tile_num\n";
-			my ($soc_name,$num)= $self->mpsoc_get_tile_soc_name($tile_num);
-			next if(!defined $soc_name);
-			copy("../boards/$vendor/$board_name/jtag_intfc.sh","${fpath}../sw/tile$tile_num/jtag_intfc.sh");
-		}
-		
-	}
-	
-	
-
-	#copy board program_device.sh file 
-	copy("../boards/$vendor/$board_name/program_device.sh","${fpath}../program_device.sh");
-
-	#get boards pin list
-	my $top_v= "../boards/$vendor/$board_name/$board_name.v";
-
-	if(!-f $top_v){
-		message_dialog("Error: Could not load the board pin list. The $top_v does not exist!",'error');
-		$window->destroy;
-	}
-	
-	my $board=read_top_v_file($top_v);
-
-	# Write object file
-	#open(FILE,  ">lib/soc/tttttttt") || die "Can not open: $!";
-	#print FILE Data::Dumper->Dump([\%$board],['board']);
-	#close(FILE) || die "Error closing file: $!";
-
-	my @dirs = ('Input', 'Bidir', 'Output');
-	my %models;
-	foreach my $p (@dirs){
-		my %pins=$board->board_get_pin($p);
-		$models{$p}=gen_combo_model(\%pins);
-		
-	}
-	
-	my $row=0;
-	my $col=0;
-	my @labels= ('Port Direction','Port Range     ','Port name      ','Assignment Type','Board Port name ','Board Port Range');
-	foreach my $p (@labels){
-		my $l=gen_label_in_left($p);		
-		$l->set_markup("<b>  $p    </b>");
-		$table->attach ($l, $col,$col+1, $row, $row+1,'fill','shrink',2,2); 
-		$col++
-	}
-	$row++;
-
-
-	#read port list 
-	my $vdb=read_verilog_file($top);
-	my %port_type=get_ports_type($vdb,"${name}_top");
-	my %port_range=get_ports_rang($vdb,"${name}_top");
-	my %param = $vdb->get_modules_parameters("${name}_top");
-	
-	foreach my $p (sort keys %port_type){
-		my $porttype=$port_type{$p};
-		my $portrange=$port_range{$p};
-
-		if  (length($portrange)!=0){	
-			#replace parameter with their values		
-			my @a= split (/\b/,$portrange);
-			
-			foreach my $l (@a){
-				my $value=$param{$l};
-				if(defined $value){
-					chomp $value;
-					($portrange=$portrange)=~ s/\b$l\b/$value/g      if(defined $param{$l});
-				#	print"($portrange=$portrange)=~ s/\b$l\b/$value/g      if(defined $param{$l})\n";
-				}
-			}
-					
-			my($s1,$s2)=split (":",$portrange);
-			{
-				no warnings 'numeric';
-				$s1 = eval $s1;
-				$s2 = eval $s2;
-			}
-			$portrange = "[ $portrange ]" ;	
-		    if(defined $s1 && defined $s2 ){
-		    	$portrange = "" if($s1 eq 0 && $s2 eq 0);			 #the upper and lower range are equal zero so remove it				
-			}
-		}	
-		
-		my $label1= gen_label_in_left("  $porttype");
-		my $label2= gen_label_in_left("  $portrange"); 
-		my $label3= gen_label_in_left("  $p");
-
-		$table->attach($label1, 0,1, $row, $row+1,'fill','shrink',2,2);
-		$table->attach($label2, 1,2, $row, $row+1,'fill','shrink',2,2); 
-		$table->attach($label3, 2,3, $row, $row+1,'fill','shrink',2,2); 
-		
-		my $assign_type= "Direct,Negate(~)";
-		if ($porttype eq  'input') {
-			my $assign_combo=gen_combobox_object($self,'compile_assign_type',$p,$assign_type,'Direct',undef,undef);
-			$table->attach( $assign_combo, 3,4, $row, $row+1,'fill','shrink',2,2); 
-		}
-
-		my $type= ($porttype eq  'input') ? 'Input' : 
-			  ($porttype eq  'output')? 'Output' : 'Bidir';
-
-		my $combo= gen_tree_combo($models{$type});
-		my $saved=$self->object_get_attribute('compile_pin_pos',$p);
-		my $box;
-		my $loc=$row;
-		if(defined $saved) {
-			  my @indices=@{$saved};
-			  my $path = TreePath_new_from_indices(@indices);
-			  my $iter = $models{$type}->get_iter($path);
-    			  undef $path;
-    			  $combo->set_active_iter($iter);
-			  $box->destroy if(defined $box);
-			  my $text=$self->object_get_attribute('compile_pin',$p);
-			  $box=get_range ($board,$self,$type,$text,$portrange,$p);
-			  $table->attach($box, 5,6, $loc, $loc+1,'fill','shrink',2,2);			 
-		}
-	
-		
-    		$combo->signal_connect("changed" => sub{ 
-			
-			#get and saved new value
-			my $treeiter=  $combo->get_active_iter();
-			my $text = $models{$type}->get_value($treeiter, 0);
-			$self->object_add_attribute('compile_pin',$p,$text);
-			#get and saved value position in model
-			my $treepath = $models{$type}->get_path ($treeiter);
-			my @indices=   $treepath->get_indices();
-			$self->object_add_attribute('compile_pin_pos',$p,\@indices);
-			#update borad port range
-			$box->destroy if(defined $box);
-			$box=get_range ($board,$self,$type,$text,$portrange,$p);
-			$table->attach($box, 5,6, $loc, $loc+1,'fill','shrink',2,2);
-			$table->show_all;
-
-		});
-   		
-    		$table->attach($combo, 4,5, $row, $row+1,'fill','shrink',2,2); 
-
-		$row++;
-
-	}
-	$next-> signal_connect("clicked" => sub{ 
-		
-		$window->destroy;
-		fpga_compilation($self,$board,$name,$top,$target_dir,$end_func,$vendor);
-		
-	});
-	$back-> signal_connect("clicked" => sub{ 
-		
-		$window->destroy;
-		select_compiler($self,$name,$top,$target_dir,$end_func,$vendor);
-		
-	});
-
-
-	$window->add ($mtable);
-	$window->show_all();
+    my ($self,$name,$top,$target_dir,$end_func,$vendor)=@_;    
+    my $window = def_popwin_size(80,80,"Step 2: Pin Assignment",'percent');
+    my $table = def_table(2, 2, FALSE);
+    my $scrolled_win = add_widget_to_scrolled_win($table);
+    my $mtable = def_table(10, 10, FALSE);    
+    my $next=def_image_button('icons/right.png','Next');
+    my $back=def_image_button('icons/left.png','Previous');    
+    $mtable->attach_defaults($scrolled_win,0,10,0,9);
+    $mtable->attach($back,2,3,9,10,'shrink','shrink',2,2);
+    $mtable->attach($next,8,9,9,10,'shrink','shrink',2,2);
+    my $board_name=$self->object_get_attribute('compile','board');
+    #copy board jtag_intfc.sh file 
+    my ($fname,$fpath,$fsuffix) = fileparse("$top",qr"\..[^.]*$");
+    copy("../boards/$vendor/$board_name/jtag_intfc.sh","${fpath}../sw/jtag_intfc.sh");    
+    my $m= $self->object_get_attribute('mpsoc_name',undef);
+    if(defined $m){    # we are compiling a complete NoC-based mpsoc                        
+        my ($nr,$ne,$router_p,$ref_tops)= get_noc_verilator_top_modules_info($self);
+        for (my $tile_num=0;$tile_num<$ne;$tile_num++){
+            #print "$tile_num\n";
+            my ($soc_name,$num)= $self->mpsoc_get_tile_soc_name($tile_num);
+            next if(!defined $soc_name);
+            copy("../boards/$vendor/$board_name/jtag_intfc.sh","${fpath}../sw/tile$tile_num/jtag_intfc.sh");
+        }
+    }
+    #copy board program_device.sh file 
+    copy("../boards/$vendor/$board_name/program_device.sh","${fpath}../program_device.sh");
+    #get boards pin list
+    my $top_v= "../boards/$vendor/$board_name/$board_name.v";
+    if(!-f $top_v){
+        message_dialog("Error: Could not load the board pin list. The $top_v does not exist!",'error');
+        $window->destroy;
+    }
+    my $board=read_top_v_file($top_v);
+    # Write object file
+    #open(FILE,  ">lib/soc/tttttttt") || die "Can not open: $!";
+    #print FILE Data::Dumper->Dump([\%$board],['board']);
+    #close(FILE) || die "Error closing file: $!";
+    my @dirs = ('Input', 'Bidir', 'Output');
+    my %models;
+    foreach my $p (@dirs){
+        my %pins=$board->board_get_pin($p);
+        $models{$p}=gen_combo_model(\%pins);
+        
+    }
+    my $row=0;
+    my $col=0;
+    my @labels= ('Port Direction','Port Range     ','Port name      ','Assignment Type','Board Port name ','Board Port Range');
+    foreach my $p (@labels){
+        my $l=gen_label_in_left($p);        
+        $l->set_markup("<b>  $p    </b>");
+        $table->attach ($l, $col,$col+1, $row, $row+1,'fill','shrink',2,2); 
+        $col++
+    }
+    $row++;
+    #read port list 
+    my $vdb=read_verilog_file($top);
+    my %port_type=get_ports_type($vdb,"${name}_top");
+    my %port_range=get_ports_rang($vdb,"${name}_top");
+    my %param = $vdb->get_modules_parameters("${name}_top");
+    foreach my $p (sort keys %port_type){
+        my $porttype=$port_type{$p};
+        my $portrange=$port_range{$p};
+        if  (length($portrange)!=0){    
+            #replace parameter with their values        
+            my @a= split (/\b/,$portrange);
+            foreach my $l (@a){
+                my $value=$param{$l};
+                if(defined $value){
+                    chomp $value;
+                    ($portrange=$portrange)=~ s/\b$l\b/$value/g      if(defined $param{$l});
+                #    print"($portrange=$portrange)=~ s/\b$l\b/$value/g      if(defined $param{$l})\n";
+                }
+            }
+            my($s1,$s2)=split (":",$portrange);
+            {
+                no warnings 'numeric';
+                $s1 = eval $s1;
+                $s2 = eval $s2;
+            }
+            $portrange = "[ $portrange ]" ;    
+            if(defined $s1 && defined $s2 ){
+                $portrange = "" if($s1 eq 0 && $s2 eq 0);             #the upper and lower range are equal zero so remove it                
+            }
+        }    
+        my $label1= gen_label_in_left("  $porttype");
+        my $label2= gen_label_in_left("  $portrange"); 
+        my $label3= gen_label_in_left("  $p");
+        $table->attach($label1, 0,1, $row, $row+1,'fill','shrink',2,2);
+        $table->attach($label2, 1,2, $row, $row+1,'fill','shrink',2,2); 
+        $table->attach($label3, 2,3, $row, $row+1,'fill','shrink',2,2); 
+        
+        my $assign_type= "Direct,Negate(~)";
+        if ($porttype eq  'input') {
+            my $assign_combo=gen_combobox_object($self,'compile_assign_type',$p,$assign_type,'Direct',undef,undef);
+            $table->attach( $assign_combo, 3,4, $row, $row+1,'fill','shrink',2,2); 
+        }
+        my $type= ($porttype eq  'input') ? 'Input' : 
+                ($porttype eq  'output')? 'Output' : 'Bidir';
+        my $combo= gen_tree_combo($models{$type});
+        my $saved=$self->object_get_attribute('compile_pin_pos',$p);
+        my $box;
+        my $loc=$row;
+        if(defined $saved) {
+            my @indices=@{$saved};
+            my $path = TreePath_new_from_indices(@indices);
+            my $iter = $models{$type}->get_iter($path);
+            undef $path;
+            $combo->set_active_iter($iter);
+            $box->destroy if(defined $box);
+            my $text=$self->object_get_attribute('compile_pin',$p);
+            $box=get_range ($board,$self,$type,$text,$portrange,$p);
+            $table->attach($box, 5,6, $loc, $loc+1,'fill','shrink',2,2);             
+        }
+            $combo->signal_connect("changed" => sub{ 
+            #get and saved new value
+            my $treeiter=  $combo->get_active_iter();
+            my $text = $models{$type}->get_value($treeiter, 0);
+            $self->object_add_attribute('compile_pin',$p,$text);
+            #get and saved value position in model
+            my $treepath = $models{$type}->get_path ($treeiter);
+            my @indices=   $treepath->get_indices();
+            $self->object_add_attribute('compile_pin_pos',$p,\@indices);
+            #update borad port range
+            $box->destroy if(defined $box);
+            $box=get_range ($board,$self,$type,$text,$portrange,$p);
+            $table->attach($box, 5,6, $loc, $loc+1,'fill','shrink',2,2);
+            $table->show_all;
+        });
+            $table->attach($combo, 4,5, $row, $row+1,'fill','shrink',2,2); 
+        $row++;
+    }
+    $next-> signal_connect("clicked" => sub{ 
+        $window->destroy;
+        fpga_compilation($self,$board,$name,$top,$target_dir,$end_func,$vendor);
+        
+    });
+    $back-> signal_connect("clicked" => sub{ 
+        
+        $window->destroy;
+        select_compiler($self,$name,$top,$target_dir,$end_func,$vendor);
+        
+    });
+    $window->add ($mtable);
+    $window->show_all();
 }
 
-
-
-
-
 sub fpga_compilation{
-	my ($self,$board,$name,$top,$target_dir,$end_func,$vendor)=@_;
-	
-	my $run=def_image_button('icons/gate.png','Compile');
-	my $back=def_image_button('icons/left.png','Previous');	
-	my $regen=def_image_button('icons/refresh.png','Regenerate Top.v');	
-	my $prog=def_image_button('icons/write.png','Program the board');	
-
-
-	my ($fname,$fpath,$fsuffix) = fileparse("$top",qr"\..[^.]*$");
-	my $board_top_file ="${fpath}Top.v";
-	unless (-e $board_top_file ){ 
-		gen_top_v($self,$board,$name,$top) ;		
-	}
-
-	my ($app,$table,$tview,$window) = software_main($fpath,'Top.v');
-	$table->attach($back,1,2,1,2,'shrink','shrink',2,2);
-	$table->attach($regen,4,5,1,2,'shrink','shrink',2,2);
-	$table->attach ($run,6, 7, 1,2,'shrink','shrink',2,2);
-	$table->attach($prog,9,10,1,2,'shrink','shrink',2,2);
-
-	
-	
-	$regen-> signal_connect("clicked" => sub{
-
-		my $response =  yes_no_dialog("Are you sure you want to regenerate the Top.v file? Note that any changes you have made will be lost");
-		if ($response eq 'yes') {
-			gen_top_v($self,$board,$name,$top);
-			$app->refresh_source("$board_top_file");	
-  		}		
-	});
-	
-	
-	
-	$back-> signal_connect("clicked" => sub{ 
-		
-		$window->destroy;
-		get_pin_assignment($self,$name,$top,$target_dir,$end_func,$vendor);
-		
-	});
-
-
-	#compile
-	$run-> signal_connect("clicked" => sub{
-		my $load= show_gif("icons/load.gif");
-		$table->attach ($load,8, 9, 1,2,'shrink','shrink',2,2);
-		$load->show_all;
-		
-		set_gui_status($self,'save_project',1);
-		$app->ask_to_save_changes();
-		
-		quartus_run_compile ($self,$app,$tview,$target_dir,$name,$window,$end_func,$vendor) if($vendor eq 'Altera');
-		xilinx_run_compile ($self,$app,$tview,$target_dir,$name,$window,$end_func,$vendor)  if($vendor eq 'Xilinx');
-		
-		$load->destroy;
-					
-	});
-
-
-	#Programe the board 
-	$prog-> signal_connect("clicked" => sub{ 
-		quartus_program_the_board($self,$tview,$target_dir,$name,$vendor) if($vendor eq 'Altera');
-		vivado_program_the_board($self,$tview,$target_dir,$name,$vendor) if($vendor eq 'Xilinx');
-	});	
-
+    my ($self,$board,$name,$top,$target_dir,$end_func,$vendor)=@_;
+    my $run=def_image_button('icons/gate.png','Compile');
+    my $back=def_image_button('icons/left.png','Previous');    
+    my $regen=def_image_button('icons/refresh.png','Regenerate Top.v');    
+    my $prog=def_image_button('icons/write.png','Program the board');    
+    my ($fname,$fpath,$fsuffix) = fileparse("$top",qr"\..[^.]*$");
+    my $board_top_file ="${fpath}Top.v";
+    unless (-e $board_top_file ){ 
+        gen_top_v($self,$board,$name,$top) ;        
+    }
+    my ($app,$table,$tview,$window) = software_main($fpath,'Top.v');
+    $table->attach($back,1,2,1,2,'shrink','shrink',2,2);
+    $table->attach($regen,4,5,1,2,'shrink','shrink',2,2);
+    $table->attach ($run,6, 7, 1,2,'shrink','shrink',2,2);
+    $table->attach($prog,9,10,1,2,'shrink','shrink',2,2);
+    $regen-> signal_connect("clicked" => sub{
+        my $response =  yes_no_dialog("Are you sure you want to regenerate the Top.v file? Note that any changes you have made will be lost");
+        if ($response eq 'yes') {
+            gen_top_v($self,$board,$name,$top);
+            $app->refresh_source("$board_top_file");    
+        }        
+    });
+    
+    $back-> signal_connect("clicked" => sub{ 
+        
+        $window->destroy;
+        get_pin_assignment($self,$name,$top,$target_dir,$end_func,$vendor);
+        
+    });
+
+    #compile
+    $run-> signal_connect("clicked" => sub{
+        my $load= show_gif("icons/load.gif");
+        $table->attach ($load,8, 9, 1,2,'shrink','shrink',2,2);
+        $load->show_all;
+        set_gui_status($self,'save_project',1);
+        $app->ask_to_save_changes();
+        quartus_run_compile ($self,$app,$tview,$target_dir,$name,$window,$end_func,$vendor) if($vendor eq 'Altera');
+        xilinx_run_compile ($self,$app,$tview,$target_dir,$name,$window,$end_func,$vendor)  if($vendor eq 'Xilinx');
+        $load->destroy;
+    });
+
+    #Programe the board 
+    $prog-> signal_connect("clicked" => sub{ 
+        quartus_program_the_board($self,$tview,$target_dir,$name,$vendor) if($vendor eq 'Altera');
+        vivado_program_the_board($self,$tview,$target_dir,$name,$vendor) if($vendor eq 'Xilinx');
+    });    
 }
 
 sub vivado_program_the_board {
-	my 	($self,$tview,$target_dir,$name,$vendor) =@_;
-	
-	my $bit_file="$target_dir/Vivado/xilinx_compile/${name}.runs/impl_1/Top.bit";
-	
-	
-	
-	unless (-f "$target_dir/Vivado/program_board.tcl"){	
-	#create tcl file
-	my $xpr = "\$tcl_path/xilinx_compile/${name}.xpr";
-	my $tcl="
+    my     ($self,$tview,$target_dir,$name,$vendor) =@_;
+    my $bit_file="$target_dir/Vivado/xilinx_compile/${name}.runs/impl_1/Top.bit";
+    
+    unless (-f "$target_dir/Vivado/program_board.tcl"){    
+    #create tcl file
+    my $xpr = "\$tcl_path/xilinx_compile/${name}.xpr";
+    my $tcl="
 #Get tcl shell path relative to current script
-set tcl_path	[file dirname [info script]] 
-	
+set tcl_path    [file dirname [info script]] 
+
 set projectName $name
 
 source \"\$tcl_path/board_property.tcl\"
@@ -1340,278 +1063,222 @@ sub vivado_program_the_board {
 close_project
 exit
 
-	";
-	save_file ("$target_dir/Vivado/program_board.tcl",$tcl);	
-	add_info($tview,"File $target_dir/Vivado/program_board.tcl is created\n");
-	}
-	
-	#check bit file existance
-	unless (-f $bit_file){	
-		add_colored_info($tview,"Could not find $bit_file. Click on project Compile button first and make sure it runs successfully.",'red');	
-		return	
-	}	
-	
-	
-	#run vivado using program_board.tcl
-	my $error =run_vivado ($self,$target_dir,$tview,"$target_dir/Vivado/program_board.tcl");	
-	add_colored_info($tview,"Board is programmed successfully!\n",'blue') if($error==0);
-	
-	
-}	
-
-
-
+    ";
+    save_file ("$target_dir/Vivado/program_board.tcl",$tcl);    
+    add_info($tview,"File $target_dir/Vivado/program_board.tcl is created\n");
+    }
+    
+    #check bit file existance
+    unless (-f $bit_file){    
+        add_colored_info($tview,"Could not find $bit_file. Click on project Compile button first and make sure it runs successfully.",'red');    
+        return    
+    }    
+    #run vivado using program_board.tcl
+    my $error =run_vivado ($self,$target_dir,$tview,"$target_dir/Vivado/program_board.tcl");    
+    add_colored_info($tview,"Board is programmed successfully!\n",'blue') if($error==0);
+}    
 
 sub quartus_program_the_board{
-	my ($self,$tview,$target_dir,$name,$vendor)=@_;
-	my $error = 0;
-	my $sof_file="$target_dir/Quartus/output_files/${name}.sof";
-	my $bash_file="$target_dir/program_device.sh";
-
-	add_info($tview,"Program the board using Quartus_pgm and $sof_file file\n");
-	#check if the programming file exists
-	unless (-f $sof_file) {
-		add_colored_info($tview,"\tThe $sof_file does not exists! Make sure you have compiled the code successfully.\n", 'red');
-		$error=1;
-	}
-	#check if the program_device.sh file exists
-	unless (-f $bash_file) {
-		add_colored_info($tview,"\tThe $bash_file does not exist! This file varies depending on your target board and must be available inside mpsoc/boards/$vendor/[board_name].\n", 'red');
-		$error=1;
-	}
-	return if($error);
-	my $command = "bash $bash_file $sof_file";
-	add_info($tview,"$command\n");
-	my ($stdout,$exit,$stderr)=run_cmd_in_back_ground_get_stdout($command);
-	if(length $stderr>1){			
-		add_colored_info($tview,"$stderr\n",'red');
-		add_colored_info($tview,"Board was not programmed successfully!\n",'red');
-	}else {
-		if($exit){
-			add_colored_info($tview,"$stdout\n",'red');
-			add_colored_info($tview,"Board was not programmed successfully!\n",'red');
-		}else{
-			add_info($tview,"$stdout\n");
-			add_colored_info($tview,"Board is programmed successfully!\n",'blue');
-		}
-			
-	}		
+    my ($self,$tview,$target_dir,$name,$vendor)=@_;
+    my $error = 0;
+    my $sof_file="$target_dir/Quartus/output_files/${name}.sof";
+    my $bash_file="$target_dir/program_device.sh";
+    add_info($tview,"Program the board using Quartus_pgm and $sof_file file\n");
+    #check if the programming file exists
+    unless (-f $sof_file) {
+        add_colored_info($tview,"\tThe $sof_file does not exists! Make sure you have compiled the code successfully.\n", 'red');
+        $error=1;
+    }
+    #check if the program_device.sh file exists
+    unless (-f $bash_file) {
+        add_colored_info($tview,"\tThe $bash_file does not exist! This file varies depending on your target board and must be available inside mpsoc/boards/$vendor/[board_name].\n", 'red');
+        $error=1;
+    }
+    return if($error);
+    my $command = "bash $bash_file $sof_file";
+    add_info($tview,"$command\n");
+    my ($stdout,$exit,$stderr)=run_cmd_in_back_ground_get_stdout($command);
+    if(length $stderr>1){            
+        add_colored_info($tview,"$stderr\n",'red');
+        add_colored_info($tview,"Board was not programmed successfully!\n",'red');
+    }else {
+        if($exit){
+            add_colored_info($tview,"$stdout\n",'red');
+            add_colored_info($tview,"Board was not programmed successfully!\n",'red');
+        }else{
+            add_info($tview,"$stdout\n");
+            add_colored_info($tview,"Board is programmed successfully!\n",'blue');
+        }
+    }        
 }
 
-
 sub quartus_run_compile{
-	my ($self,$app,$tview,$target_dir,$name,$window,$end_func,$vendor)=@_;	 
-	
-	my $error = 0;
-	add_info($tview,"CREATE: start creating Quartus project in $target_dir/Quartus folder\n");
-	
-	mkpath("$target_dir/Quartus",1,01777);
-
-	#get list of source file
-	add_info($tview,"        Read the list of all source files $target_dir/src_verilog\n");
-	my @files = File::Find::Rule->file()
-                          ->name( '*.v','*.V','*.sv' )
-                          ->in( "$target_dir/src_verilog" );
-
-	#make sure source files have key word 'module' 
-	my @sources;
-	foreach my $p (@files){
-		push (@sources,$p)	if(check_file_has_string($p,'endpackage')); 
-	}
-	foreach my $p (@files){
-		push (@sources,$p)	if(check_file_has_string($p,'module')); 
-	}
-	my $files = join ("\n",@sources);
-	add_info($tview,"$files\n");
-
-	#creat project qsf file
-	my $qsf_file="$target_dir/Quartus/${name}.qsf";
-	save_file ($qsf_file,"# Generated using ProNoC\n");
-
-	#append global assignets to qsf file
-	my $board_name=$self->object_get_attribute('compile','board');
-	my @qsfs =   glob("../boards/$vendor/$board_name/*.qsf");
-	if(!defined $qsfs[0]){
-		message_dialog("Error: ../boards/$vendor/$board_name folder does not contain the qsf file.!",'error');
-		$window->destroy;
-	}
-
-	my $assignment_file =  $qsfs[0];
-		
-	if(-f $assignment_file){
-		merg_files ($assignment_file,$qsf_file);
-	}
-	
-	my %paths;	
-
-	#add the list of source fils to qsf file
-	my $s="\n\n\n set_global_assignment -name TOP_LEVEL_ENTITY Top\n";
-	foreach my $p (@sources){
-		my ($name,$path,$suffix) = fileparse("$p",qr"\..[^.]*$");
-		$s="$s set_global_assignment -name VERILOG_FILE $p\n" if ($suffix eq ".v");
-		$s="$s set_global_assignment -name SYSTEMVERILOG_FILE $p\n" if ($suffix eq ".sv");
-		$paths{$path}=1;
-	}
-	
-	
-	
-	
-	
-	
-	foreach my $p (sort keys %paths){
-	 	$s="$s set_global_assignment -name SEARCH_PATH  $p\n";	
-	}
-	
-	append_text_to_file($qsf_file,$s);
-	add_info($tview,"\n Qsf file has been created\n");
-	
-	
-	
-	
-	#start compilation
-	my $Quartus_bin= $self->object_get_attribute('compile','quartus bin');
-	my @qfiles = ("quartus_map","quartus_fit","quartus_asm","quartus_sta");
-	foreach my $f (@qfiles){
-		unless(-f "$Quartus_bin/$f" ){
-			$error=1;
-			add_colored_info($tview, "$Quartus_bin/$f No such file or directory\n",'red');
-			last;
-		}
-		
-	}
-	
-	my $run_sh = "#!/bin/bash
+    my ($self,$app,$tview,$target_dir,$name,$window,$end_func,$vendor)=@_;     
+    my $error = 0;
+    add_info($tview,"CREATE: start creating Quartus project in $target_dir/Quartus folder\n");
+    mkpath("$target_dir/Quartus",1,01777);
+    #get list of source file
+    add_info($tview,"        Read the list of all source files $target_dir/src_verilog\n");
+    my @files = File::Find::Rule->file()
+            ->name( '*.v','*.V','*.sv' )
+            ->in( "$target_dir/src_verilog" );
+    #make sure source files have key word 'module' 
+    my @sources;
+    foreach my $p (@files){
+        push (@sources,$p)    if(check_file_has_string($p,'endpackage')); 
+    }
+    foreach my $p (@files){
+        push (@sources,$p)    if(check_file_has_string($p,'module')); 
+    }
+    my $files = join ("\n",@sources);
+    add_info($tview,"$files\n");
+    #creat project qsf file
+    my $qsf_file="$target_dir/Quartus/${name}.qsf";
+    save_file ($qsf_file,"# Generated using ProNoC\n");
+    #append global assignets to qsf file
+    my $board_name=$self->object_get_attribute('compile','board');
+    my @qsfs =   glob("../boards/$vendor/$board_name/*.qsf");
+    if(!defined $qsfs[0]){
+        message_dialog("Error: ../boards/$vendor/$board_name folder does not contain the qsf file.!",'error');
+        $window->destroy;
+    }
+    my $assignment_file =  $qsfs[0];
+    if(-f $assignment_file){
+        merg_files ($assignment_file,$qsf_file);
+    }
+    my %paths;    
+    #add the list of source fils to qsf file
+    my $s="\n\n\n set_global_assignment -name TOP_LEVEL_ENTITY Top\n";
+    foreach my $p (@sources){
+        my ($name,$path,$suffix) = fileparse("$p",qr"\..[^.]*$");
+        $s="$s set_global_assignment -name VERILOG_FILE $p\n" if ($suffix eq ".v");
+        $s="$s set_global_assignment -name SYSTEMVERILOG_FILE $p\n" if ($suffix eq ".sv");
+        $paths{$path}=1;
+    }
+    foreach my $p (sort keys %paths){
+        $s="$s set_global_assignment -name SEARCH_PATH  $p\n";    
+    }
+    append_text_to_file($qsf_file,$s);
+    add_info($tview,"\n Qsf file has been created\n");
+    #start compilation
+    my $Quartus_bin= $self->object_get_attribute('compile','quartus bin');
+    my @qfiles = ("quartus_map","quartus_fit","quartus_asm","quartus_sta");
+    foreach my $f (@qfiles){
+        unless(-f "$Quartus_bin/$f" ){
+            $error=1;
+            add_colored_info($tview, "$Quartus_bin/$f No such file or directory\n",'red');
+            last;
+        }
+    }
+    my $run_sh = "#!/bin/bash
 $Quartus_bin/quartus_map --64bit $name --read_settings_files=on
 $Quartus_bin/quartus_fit --64bit $name --read_settings_files=on 
 $Quartus_bin/quartus_asm --64bit $name --read_settings_files=on
-$Quartus_bin/quartus_sta --64bit $name	
-	";
-	
-	save_file("$target_dir/Quartus/run.sh",  $run_sh);
-		
-	add_info($tview, "Start Quartus compilation.....\n");
-	my @compilation_command =(
-		"cd \"$target_dir/Quartus\" \n xterm -e bash -c '$Quartus_bin/quartus_map --64bit $name --read_settings_files=on; echo \$? > status; sleep 1' ",
-		"cd \"$target_dir/Quartus\" \n xterm -e bash -c '$Quartus_bin/quartus_fit --64bit $name --read_settings_files=on; echo \$? > status; sleep 1' ",
-		"cd \"$target_dir/Quartus\" \n xterm -e bash -c '$Quartus_bin/quartus_asm --64bit $name --read_settings_files=on; echo \$? > status; sleep 1' ",
-		"cd \"$target_dir/Quartus\" \n xterm -e bash -c '$Quartus_bin/quartus_sta --64bit $name; echo \$? > status; sleep 1 ' ");
-	
-		foreach my $cmd (@compilation_command){
-			last if($error); 
-		add_info($tview,"$cmd\n");
-		unlink "$target_dir/Quartus/status";
-		my ($stdout,$exit,$stderr)=run_cmd_in_back_ground_get_stdout( $cmd);
-		if($exit){
-			add_colored_info($tview, "$stdout\n",'red') if(defined $stdout);
-			add_colored_info($tview, "$stderr\n",'red') if(defined $stderr);
-			$error=1;
-			last;			
-		}		
-		
-		open(my $fh,  "<$target_dir/Quartus/status") || die "Can not open: $!";
-		read($fh,my $status,1);
-		close($fh);
-		if("$status" != "0"){			
-			($stdout,$exit,$stderr)=run_cmd_in_back_ground_get_stdout("cd \"$target_dir/Quartus/output_files/\" \n grep -h \"Error (\" *");
-			add_colored_info($tview,"$stderr\n",'red') if(defined $stderr);
-			add_colored_info($tview,"$stdout\n",'red');
-			$error=1;
-			last;
-		}			
-	}
-	add_colored_info($tview,"Quartus compilation failed !\n",'red') if($error==1);
-	add_colored_info($tview,"Quartus compilation is done successfully in $target_dir/Quartus!\n", 'blue') if($error==0);
-	if (defined $end_func){
-		if ($error==0){
-			$end_func->($self);
-			$window->destroy;
-		}else {
-			message_dialog("Error in Quartus compilation!",'error');	
-		}
-	}
-	
-
-	
+$Quartus_bin/quartus_sta --64bit $name    
+    ";
+    save_file("$target_dir/Quartus/run.sh",  $run_sh);
+    add_info($tview, "Start Quartus compilation.....\n");
+    my @compilation_command =(
+        "cd \"$target_dir/Quartus\" \n xterm -e bash -c '$Quartus_bin/quartus_map --64bit $name --read_settings_files=on; echo \$? > status; sleep 1' ",
+        "cd \"$target_dir/Quartus\" \n xterm -e bash -c '$Quartus_bin/quartus_fit --64bit $name --read_settings_files=on; echo \$? > status; sleep 1' ",
+        "cd \"$target_dir/Quartus\" \n xterm -e bash -c '$Quartus_bin/quartus_asm --64bit $name --read_settings_files=on; echo \$? > status; sleep 1' ",
+        "cd \"$target_dir/Quartus\" \n xterm -e bash -c '$Quartus_bin/quartus_sta --64bit $name; echo \$? > status; sleep 1 ' ");
+        foreach my $cmd (@compilation_command){
+            last if($error); 
+        add_info($tview,"$cmd\n");
+        unlink "$target_dir/Quartus/status";
+        my ($stdout,$exit,$stderr)=run_cmd_in_back_ground_get_stdout( $cmd);
+        if($exit){
+            add_colored_info($tview, "$stdout\n",'red') if(defined $stdout);
+            add_colored_info($tview, "$stderr\n",'red') if(defined $stderr);
+            $error=1;
+            last;            
+        }        
+        open(my $fh,  "<$target_dir/Quartus/status") || die "Can not open: $!";
+        read($fh,my $status,1);
+        close($fh);
+        if("$status" != "0"){            
+            ($stdout,$exit,$stderr)=run_cmd_in_back_ground_get_stdout("cd \"$target_dir/Quartus/output_files/\" \n grep -h \"Error (\" *");
+            add_colored_info($tview,"$stderr\n",'red') if(defined $stderr);
+            add_colored_info($tview,"$stdout\n",'red');
+            $error=1;
+            last;
+        }            
+    }
+    add_colored_info($tview,"Quartus compilation failed !\n",'red') if($error==1);
+    add_colored_info($tview,"Quartus compilation is done successfully in $target_dir/Quartus!\n", 'blue') if($error==0);
+    if (defined $end_func){
+        if ($error==0){
+            $end_func->($self);
+            $window->destroy;
+        }else {
+            message_dialog("Error in Quartus compilation!",'error');    
+        }
+    }
 }
 
-
-
-
-
-
 sub xilinx_run_compile{
-	my ($self,$app,$tview,$target_dir,$name,$window,$end_func,$vendor)=@_;
-	
-	add_info($tview,"CREATE: start creating Vivado project in $target_dir/Vivado\n");
-	#get list of source file
-	add_info($tview,"        Read the list of all source files $target_dir/src_verilog\n");
-	my @files = File::Find::Rule->file()
-                          ->name( '*.v','*.V','*.sv' )
-                          ->in( "$target_dir/src_verilog" );
-
-	#make sure source files have key word 'module' 
-	my @sources;
-	foreach my $p (@files){
-		push (@sources,$p)	if(check_file_has_string($p,'endpackage')); 
-	}
-	foreach my $p (@files){
-		push (@sources,$p)	if(check_file_has_string($p,'module')); 
-	}
-	
-	my %paths;
-	foreach my $p (@files){
-		my ($name,$path,$suffix) = fileparse("$p",qr"\..[^.]*$");
-		#print "$path\n";
-		my $remove="$target_dir/";
-		$path =~ s/$remove//; 	
-		$paths{$path}=1;
-	}
-	
-	
-
-	
-	my $incdir="set include_dir_list [list";
-	foreach my $p (sort keys %paths){
-	 	$incdir.=" \$Dir/$p";	
-	 }
-	$incdir.="]";
-	
-	my $files = join ("\n",@sources);
-	
-	
-	
-	#add mem initial file to sources
-	my $mem_files="";
-	my @initial_files = File::Find::Rule->file()
-                          ->name( '*.mem')
-                          ->in( "$target_dir/sw" );
-	mkpath("$target_dir/Vivado/xilinx_mem",1,01777) unless -f "$target_dir/Vivado/xilinx_mem";
-	foreach my $f 	(@initial_files){
-		#	/home/alireza/work/hca_git/mpsoc_work/SOC/mor1k_soc/sw/RAM/ram0.mif  fpr soc
-		#   /home/alireza/work/hca_git/mpsoc_work/MPSOC/newAdder/sw/tile0/RAM/ram0.mif fpr mpsoc
-		my @m = split('\/sw\/',$f );
-		my $d = $m[-1];#take the last file path name after /sw/
-		$d=~ s/RAM//g; #remove RAM
-		$d=~ s/\///g; #remove /
-		$d = "tile0".$d unless($m[-1]=~/^tile/); #add tile0 to soc
-		copy($f,"$target_dir/Vivado/xilinx_mem/$d");
-		$mem_files="$mem_files \$tcl_path/xilinx_mem/$d"; 		
-	}
-	add_info($tview,"HDL sources:\n$files\nMem sources:\n$mem_files\n");
-	#make tcl file
-	my $tcl="
+    my ($self,$app,$tview,$target_dir,$name,$window,$end_func,$vendor)=@_;
+    add_info($tview,"CREATE: start creating Vivado project in $target_dir/Vivado\n");
+    #get list of source file
+    add_info($tview,"        Read the list of all source files $target_dir/src_verilog\n");
+    my @files = File::Find::Rule->file()
+            ->name( '*.v','*.V','*.sv' )
+            ->in( "$target_dir/src_verilog" );
+    #make sure source files have key word 'module' 
+    my @sources;
+    foreach my $p (@files){
+        push (@sources,$p)    if(check_file_has_string($p,'endpackage')); 
+    }
+    foreach my $p (@files){
+        push (@sources,$p)    if(check_file_has_string($p,'module')); 
+    }
+    my %paths;
+    foreach my $p (@files){
+        my ($name,$path,$suffix) = fileparse("$p",qr"\..[^.]*$");
+        #print "$path\n";
+        my $remove="$target_dir/";
+        $path =~ s/$remove//;     
+        $paths{$path}=1;
+    }
+    my $incdir="set include_dir_list [list";
+    foreach my $p (sort keys %paths){
+        $incdir.=" \$Dir/$p";    
+    }
+    $incdir.="]";
+    my $files = join ("\n",@sources);
+    #add mem initial file to sources
+    my $mem_files="";
+    my @initial_files = File::Find::Rule->file()
+        ->name( '*.mem')
+        ->in( "$target_dir/sw" );
+    mkpath("$target_dir/Vivado/xilinx_mem",1,01777) unless -f "$target_dir/Vivado/xilinx_mem";
+    foreach my $f     (@initial_files){
+        #    /home/alireza/work/hca_git/mpsoc_work/SOC/mor1k_soc/sw/RAM/ram0.mif  fpr soc
+        #   /home/alireza/work/hca_git/mpsoc_work/MPSOC/newAdder/sw/tile0/RAM/ram0.mif fpr mpsoc
+        my @m = split('\/sw\/',$f );
+        my $d = $m[-1];#take the last file path name after /sw/
+        $d=~ s/RAM//g; #remove RAM
+        $d=~ s/\///g; #remove /
+        $d = "tile0".$d unless($m[-1]=~/^tile/); #add tile0 to soc
+        copy($f,"$target_dir/Vivado/xilinx_mem/$d");
+        $mem_files="$mem_files \$tcl_path/xilinx_mem/$d";         
+    }
+    add_info($tview,"HDL sources:\n$files\nMem sources:\n$mem_files\n");
+    #make tcl file
+    my $tcl="
 #Get tcl shell path relative to current script
-set tcl_path	[file dirname [info script]] 
+set tcl_path    [file dirname [info script]] 
 set Dir \"\$tcl_path/..\"
 ";
-	
-	$tcl=$tcl."set projectName $name";
-	
-	$tcl =$tcl."
+    
+    $tcl=$tcl."set projectName $name";
+    
+    $tcl =$tcl."
 source \"\$tcl_path/board_property.tcl\" 
 #Create output directory and clear contents
 set outputdir \"\$tcl_path/xilinx_compile\"";
-	$tcl =$tcl.'
+    $tcl =$tcl.'
 file mkdir $outputdir
 set files [glob -nocomplain "$outputdir/*"]
 if {[llength $files] != 0} {
@@ -1626,267 +1293,217 @@ sub xilinx_run_compile{
 
 set_project_properties
 
-#add source files to Vivado project	
+#add source files to Vivado project    
 ';
 
-	#get top level port names
-	#get boards pin list
-	my $top_v= "$target_dir/src_verilog/Top.v";
-	if(!-f $top_v){
-		message_dialog("Error: Could not load the board pin list. The Top.v does not exist!",'error');
-		$window->destroy;
-	}
-	
-	
-	my @ports=verilog_file_get_ports_list(read_verilog_file($top_v),"Top");
-	
-	#get board tcl
-	my $board_name=$self->object_get_attribute('compile','board');
-	my @tcls= glob("../boards/$vendor/$board_name/*.tcl");
-	foreach my $f (@tcls){
-		copy($f,"$target_dir/Vivado");
-	}
-
-	#get board xdc
-	my @xdcs= glob("../boards/$vendor/$board_name/*.xdc");
-	my $i=1;
-		
-	foreach my $f (@xdcs){
-		my $out="";
-		#capture file content
-		my $string= load_file($f);
-		my @lines=split('\n',$string);
-		#make sure lines describing the port name are not comment
-		foreach my $l (@lines){
-			foreach my $p (@ports){
-				
-				$l=~ s/^\s*#/ /g if($l =~ /^\s*#/   && $l =~  /\[\s*get_ports\s*[{\s]\s*$p[\s\[\]\}]/ );#             /\[get_ports\s*{\s*$p[\s\}\[]/);
-				
-			}
-			$out=$out."$l\n";			
-		}	
-		my ($fname,$fpath,$fsuffix) = fileparse("$f",qr"\..[^.]*$");
-		my $xdc_file = "$target_dir/Vivado/$fname.xdc";
-		#save new xdc file
-		save_file($xdc_file,$out);				
-		#add xdc to tcl file
-		$tcl =$tcl."add_files -fileset constrs_1 \$tcl_path/$fname.xdc\n";
-		$i++;	
-	}	
-
-	#internal clock constrain
-	my $clk_xdc=get_clk_constrain_file($self);
-	#save_file ("$target_dir/clk.xdc",$clk_xdc);
-	#$tcl =$tcl."add_files -fileset constrs_1 \$tcl_path/clk.xdc\n";
-
-
-
-	$tcl =$tcl."add_files ";
-	#add hdl sources
-	foreach my $f (@sources){
-		my $p =cut_dir_path($f,'src_verilog');		
-		$tcl =$tcl." \$Dir/src_verilog/$p ";	
-	}	
-	$tcl =$tcl."\n";
-	
-	$tcl =$tcl."#add memory initial files to Vivado project
-	add_files -norecurse $mem_files" if(length($mem_files)>3);
-	
-	
-	$tcl =$tcl."\n set_property \"top\"  \"Top\" [current_fileset]\n";
-	$tcl =$tcl."
-	update_compile_order -fileset sources_1
-	#launch synthesis
-	
-	# Make all reset syncron 
-	set_property verilog_define {{SYNC_RESET_MODE}} [current_fileset]
-	
-	# include source dirs
-	$incdir
-	set_property include_dirs  \$include_dir_list [current_fileset]
-	
-	launch_runs synth_1
-	wait_on_run synth_1
-	#Run implementation and generate bitstream
-	set_property STEPS.PHYS_OPT_DESIGN.IS_ENABLED true [get_runs impl_1]
-	launch_runs impl_1 -to_step write_bitstream
-	wait_on_run impl_1
-	puts \"Implementation done!\"
-	";
-	
-
-	$tcl =$tcl."\nexit";	
-	#creat make_project tcl file
-	save_file ("$target_dir/Vivado/make_project.tcl",$tcl);	
-	
-	my $error =run_vivado ($self,$target_dir,$tview,"$target_dir/Vivado/make_project.tcl");
-	add_colored_info($tview,"Vivado compilation is done successfully in $target_dir/Vivado!\n", 'blue') if($error==0);
-	if (defined $end_func){
-		if ($error==0){
-			$end_func->($self);
-			$window->destroy;
-		}else {
-			message_dialog("Error in Vivado compilation!",'error');	
-		}
-	}
-	
-	
-}	
-
+    #get top level port names
+    #get boards pin list
+    my $top_v= "$target_dir/src_verilog/Top.v";
+    if(!-f $top_v){
+        message_dialog("Error: Could not load the board pin list. The Top.v does not exist!",'error');
+        $window->destroy;
+    }
+    my @ports=verilog_file_get_ports_list(read_verilog_file($top_v),"Top");
+    #get board tcl
+    my $board_name=$self->object_get_attribute('compile','board');
+    my @tcls= glob("../boards/$vendor/$board_name/*.tcl");
+    foreach my $f (@tcls){
+        copy($f,"$target_dir/Vivado");
+    }
+    #get board xdc
+    my @xdcs= glob("../boards/$vendor/$board_name/*.xdc");
+    my $i=1;
+    
+    foreach my $f (@xdcs){
+        my $out="";
+        #capture file content
+        my $string= load_file($f);
+        my @lines=split('\n',$string);
+        #make sure lines describing the port name are not comment
+        foreach my $l (@lines){
+            foreach my $p (@ports){
+                
+                $l=~ s/^\s*#/ /g if($l =~ /^\s*#/   && $l =~  /\[\s*get_ports\s*[{\s]\s*$p[\s\[\]\}]/ );#             /\[get_ports\s*{\s*$p[\s\}\[]/);
+                
+            }
+            $out=$out."$l\n";            
+        }    
+        my ($fname,$fpath,$fsuffix) = fileparse("$f",qr"\..[^.]*$");
+        my $xdc_file = "$target_dir/Vivado/$fname.xdc";
+        #save new xdc file
+        save_file($xdc_file,$out);                
+        #add xdc to tcl file
+        $tcl =$tcl."add_files -fileset constrs_1 \$tcl_path/$fname.xdc\n";
+        $i++;    
+    }    
+    #internal clock constrain
+    my $clk_xdc=get_clk_constrain_file($self);
+    #save_file ("$target_dir/clk.xdc",$clk_xdc);
+    #$tcl =$tcl."add_files -fileset constrs_1 \$tcl_path/clk.xdc\n";
+    $tcl =$tcl."add_files ";
+    #add hdl sources
+    foreach my $f (@sources){
+        my $p =cut_dir_path($f,'src_verilog');        
+        $tcl =$tcl." \$Dir/src_verilog/$p ";    
+    }    
+    $tcl =$tcl."\n";
+    $tcl =$tcl."#add memory initial files to Vivado project
+    add_files -norecurse $mem_files" if(length($mem_files)>3);
+    $tcl =$tcl."\n set_property \"top\"  \"Top\" [current_fileset]\n";
+    $tcl =$tcl."
+    update_compile_order -fileset sources_1
+    #launch synthesis
+    
+    # Make all reset syncron 
+    set_property verilog_define {{SYNC_RESET_MODE}} [current_fileset]
+    
+    # include source dirs
+    $incdir
+    set_property include_dirs  \$include_dir_list [current_fileset]
+    
+    launch_runs synth_1
+    wait_on_run synth_1
+    #Run implementation and generate bitstream
+    set_property STEPS.PHYS_OPT_DESIGN.IS_ENABLED true [get_runs impl_1]
+    launch_runs impl_1 -to_step write_bitstream
+    wait_on_run impl_1
+    puts \"Implementation done!\"
+    ";
+    $tcl =$tcl."\nexit";    
+    #creat make_project tcl file
+    save_file ("$target_dir/Vivado/make_project.tcl",$tcl);    
+    my $error =run_vivado ($self,$target_dir,$tview,"$target_dir/Vivado/make_project.tcl");
+    add_colored_info($tview,"Vivado compilation is done successfully in $target_dir/Vivado!\n", 'blue') if($error==0);
+    if (defined $end_func){
+        if ($error==0){
+            $end_func->($self);
+            $window->destroy;
+        }else {
+            message_dialog("Error in Vivado compilation!",'error');    
+        }
+    }
+}    
 
 sub run_vivado {
-	my ($self,$target_dir,$tview,$tcl)=@_;
-	my $error=0;
-	#start compilation
-	my $vivado_bin= $self->object_get_attribute('compile','vivado bin');
-	add_info($tview, "Start compilation using vivado.....\n");
-	my @compilation_command =(
-		"cd \"$target_dir/Vivado/\" \n xterm -e bash -c '$vivado_bin/vivado -mode tcl -source $tcl'"		
-	);
-	
-	save_file("$target_dir/Vivado/run.sh",  "#!/bin/bash \n $vivado_bin/vivado -mode tcl -source $tcl");
-	
-	
-	my $log="$target_dir/Vivado/vivado.log";	
-	#unlink $log;
-	
-	foreach my $cmd (@compilation_command){
-		add_info($tview,"$cmd\n");
-		
-		my ($stdout,$exit,$stderr)=run_cmd_in_back_ground_get_stdout( $cmd);
-		if($exit){
-			$error=1;
-			add_colored_info($tview, "$stdout\n",'red') if(defined $stdout);
-			add_colored_info($tview, "$stderr\n",'red') if(defined $stderr);			
-		}
-	
-	}	
-	
-	#check vivado.log for error
-	my $r;
-	open my $fd, "<" , $log or $r=$!;
-	if(defined $r ) {
-		add_colored_info($tview, "could not open $log to check errors: $r\n",'red');
-		$error=1;
-	}
-	else{
-	
-		#check error
-		while (my $line = <$fd>) {
-			chomp $line;
-			if( $line =~ /ERROR:/){
-				add_colored_info($tview, "$line\n",'red');
-				$error=1;
-			}
-		} 
-		
-		#check warning
-		close($fd);
-		open $fd, "<" , $log;
-		#print 	"$log\n";
-		if($error==0){
-			while (my $line = <$fd>) {
-				chomp $line;
-				if( $line =~ /^\s*WARNING:/){
-					add_info($tview, "$line\n");
-					
-				}
-			} 
-		}
-		
-		#check critical warning
-		close($fd);
-		open $fd, "<" , $log;
-		#print 	"$log\n";
-		if($error==0){
-			while (my $line = <$fd>) {
-				chomp $line;
-				if( $line =~ /^\s*CRITICAL WARNING:/){
-					add_colored_info($tview, "$line\n",'green');
-				}
-			} 
-		}
-		close($fd);	
-	}
-	return $error;	
+    my ($self,$target_dir,$tview,$tcl)=@_;
+    my $error=0;
+    #start compilation
+    my $vivado_bin= $self->object_get_attribute('compile','vivado bin');
+    add_info($tview, "Start compilation using vivado.....\n");
+    my @compilation_command =(
+        "cd \"$target_dir/Vivado/\" \n xterm -e bash -c '$vivado_bin/vivado -mode tcl -source $tcl'"        
+    );
+    save_file("$target_dir/Vivado/run.sh",  "#!/bin/bash \n $vivado_bin/vivado -mode tcl -source $tcl");
+    my $log="$target_dir/Vivado/vivado.log";    
+    #unlink $log;
+    foreach my $cmd (@compilation_command){
+        add_info($tview,"$cmd\n");
+        my ($stdout,$exit,$stderr)=run_cmd_in_back_ground_get_stdout( $cmd);
+        if($exit){
+            $error=1;
+            add_colored_info($tview, "$stdout\n",'red') if(defined $stdout);
+            add_colored_info($tview, "$stderr\n",'red') if(defined $stderr);            
+        }
+    }    
+    #check vivado.log for error
+    my $r;
+    open my $fd, "<" , $log or $r=$!;
+    if(defined $r ) {
+        add_colored_info($tview, "could not open $log to check errors: $r\n",'red');
+        $error=1;
+    }
+    else{
+        #check error
+        while (my $line = <$fd>) {
+            chomp $line;
+            if( $line =~ /ERROR:/){
+                add_colored_info($tview, "$line\n",'red');
+                $error=1;
+            }
+        } 
+        #check warning
+        close($fd);
+        open $fd, "<" , $log;
+        #print     "$log\n";
+        if($error==0){
+            while (my $line = <$fd>) {
+                chomp $line;
+                if( $line =~ /^\s*WARNING:/){
+                    add_info($tview, "$line\n");
+                }
+            } 
+        }
+        #check critical warning
+        close($fd);
+        open $fd, "<" , $log;
+        #print     "$log\n";
+        if($error==0){
+            while (my $line = <$fd>) {
+                chomp $line;
+                if( $line =~ /^\s*CRITICAL WARNING:/){
+                    add_colored_info($tview, "$line\n",'green');
+                }
+            } 
+        }
+        close($fd);    
+    }
+    return $error;    
 }
 
-
-
-
-
 sub modelsim_compilation{
-	my ($self,$name,$top,$target_dir,$vendor)=@_;
-	#my $window = def_popwin_size(80,80,"Step 2: Compile",'percent');
-	
-	
-	my $run=def_image_button('icons/run.png','_run',FALSE,1);
-	my $back=def_image_button('icons/left.png','Previous');	
-	my $regen=def_image_button('icons/refresh.png','Regenerate testbench.v');	
-	
-	
-	#creat modelsim dir
-	
-	my $model="$target_dir/Modelsim";
-	unlink("$model/model.tcl");
-	rmtree("$target_dir/rtl_work");
-	mkpath("$model/rtl_work",1,01777);
-	
-	my ($app,$table,$tview,$window) = software_main("$target_dir/Modelsim",undef);
-	#create testbench.v
-	gen_modelsim_soc_testbench ($self,$name,$top,$target_dir,$tview) unless (-f "$target_dir/Modelsim/testbench.v");
-	$app->refresh_source("$target_dir/Modelsim/testbench.v");	
-
-
-	
-	add_info($tview,"create Modelsim dir in $target_dir\n");
-	$table->attach($back,1,2,1,2,'shrink','shrink',2,2);
-	$table->attach($regen,4,5,1,2,'shrink','shrink',2,2);
-	$table->attach ($run,9, 10, 1,2,'shrink','shrink',0,0);
-	
-	
-	
-	$regen-> signal_connect("clicked" => sub{
-		my $response =  yes_no_dialog("Are you sure you want to regenerate the testbench.v file? Note that any changes you have made will be lost");
-		if ($response eq 'yes') {
-      			gen_modelsim_soc_testbench ($self,$name,$top,$target_dir,$tview);
-			$app->refresh_source("$target_dir/Modelsim/testbench.v");	
-  		}		
-	});
-	
-	$back-> signal_connect("clicked" => sub{ 
-		
-		$window->destroy;
-		select_compiler($self,$name,$top,$target_dir);
-		
-	});
-	
-	#Get the list of  all verilog files in src_verilog folder
-	add_info($tview,"Get the list of all Verilog files in src_verilog folder\n");
-	my @files = File::Find::Rule->file()
-		->name( '*.v','*.V','*.sv' )
-		->in( "$target_dir/src_verilog" );
-		
-	#get list of all verilog files in src_sim folder 
+    my ($self,$name,$top,$target_dir,$vendor)=@_;
+    #my $window = def_popwin_size(80,80,"Step 2: Compile",'percent');
+    my $run=def_image_button('icons/run.png','_run',FALSE,1);
+    my $back=def_image_button('icons/left.png','Previous');    
+    my $regen=def_image_button('icons/refresh.png','Regenerate testbench.v');    
+    #creat modelsim dir
+    my $model="$target_dir/Modelsim";
+    unlink("$model/model.tcl");
+    rmtree("$target_dir/rtl_work");
+    mkpath("$model/rtl_work",1,01777);
+    my ($app,$table,$tview,$window) = software_main("$target_dir/Modelsim",undef);
+    #create testbench.v
+    gen_modelsim_soc_testbench ($self,$name,$top,$target_dir,$tview) unless (-f "$target_dir/Modelsim/testbench.v");
+    $app->refresh_source("$target_dir/Modelsim/testbench.v");    
+    add_info($tview,"create Modelsim dir in $target_dir\n");
+    $table->attach($back,1,2,1,2,'shrink','shrink',2,2);
+    $table->attach($regen,4,5,1,2,'shrink','shrink',2,2);
+    $table->attach ($run,9, 10, 1,2,'shrink','shrink',0,0);
+    $regen-> signal_connect("clicked" => sub{
+        my $response =  yes_no_dialog("Are you sure you want to regenerate the testbench.v file? Note that any changes you have made will be lost");
+        if ($response eq 'yes') {
+            gen_modelsim_soc_testbench ($self,$name,$top,$target_dir,$tview);
+            $app->refresh_source("$target_dir/Modelsim/testbench.v");    
+        }        
+    });
+    $back-> signal_connect("clicked" => sub{ 
+        $window->destroy;
+        select_compiler($self,$name,$top,$target_dir);
+    });
+    
+    #Get the list of  all verilog files in src_verilog folder
+    add_info($tview,"Get the list of all Verilog files in src_verilog folder\n");
+    my @files = File::Find::Rule->file()
+        ->name( '*.v','*.V','*.sv' )
+        ->in( "$target_dir/src_verilog" );
+        
+    #get list of all verilog files in src_sim folder 
     my @sim_files = File::Find::Rule->file()
-		->name( '*.v','*.V','*.sv' )
-		->in( "$target_dir/src_sim" );		
-	push (@files, @sim_files);	
-	#add testnemch.v
-	push (@files, "$target_dir/Modelsim/testbench.v");
-	
-	#create a file list
-	my $tt =create_file_list($target_dir,\@files,'modelsim');	
-	save_file("$target_dir/Modelsim/file_list.f",  "$tt");
-	
-	
-	#create modelsim.tcl file
+        ->name( '*.v','*.V','*.sv' )
+        ->in( "$target_dir/src_sim" );        
+    push (@files, @sim_files);    
+    #add testnemch.v
+    push (@files, "$target_dir/Modelsim/testbench.v");
+    
+    #create a file list
+    my $tt =create_file_list($target_dir,\@files,'modelsim');    
+    save_file("$target_dir/Modelsim/file_list.f",  "$tt");
+    #create modelsim.tcl file
 my $tcl="#!/usr/bin/tclsh
 
-
 transcript on
 if {[file exists rtl_work]} {
-	vdel -lib rtl_work -all
+    vdel -lib rtl_work -all
 }
 vlib rtl_work
 vmap work rtl_work
@@ -1901,177 +1518,151 @@ sub modelsim_compilation{
 view signals
 run -all
 ";
-	add_info($tview,"Create model.tcl, run.sh files\n");
-	save_file ("$model/model.tcl",$tcl);
-	my $modelsim_bin= $self->object_get_attribute('compile','modelsim_bin');		
-	my $cmd="cd $target_dir/Modelsim; rm -Rf rtl_work; $modelsim_bin/vsim -do $model/model.tcl";
-	save_file ("$model/run.sh",'#!/bin/bash'."\n".$cmd);
-	
-	$run -> signal_connect("clicked" => sub{
-		set_gui_status($self,'save_project',1);
-		$app->ask_to_save_changes();
-		
-		
-		add_info($tview,"$cmd\n");
-		my ($stdout,$exit,$stderr)=run_cmd_in_back_ground_get_stdout($cmd);
-		if(length $stderr>1){	
-			add_colored_info($tview,"$stderr\n","red"); 		
-			
-		}else {
-			add_info($tview,"$stdout\n");
-		}			
-
-	});
-	
-	#$window->show_all();
+    add_info($tview,"Create model.tcl, run.sh files\n");
+    save_file ("$model/model.tcl",$tcl);
+    my $modelsim_bin= $self->object_get_attribute('compile','modelsim_bin');        
+    my $cmd="cd $target_dir/Modelsim; rm -Rf rtl_work; $modelsim_bin/vsim -do $model/model.tcl";
+    save_file ("$model/run.sh",'#!/bin/bash'."\n".$cmd);
+    $run -> signal_connect("clicked" => sub{
+        set_gui_status($self,'save_project',1);
+        $app->ask_to_save_changes();
+        add_info($tview,"$cmd\n");
+        my ($stdout,$exit,$stderr)=run_cmd_in_back_ground_get_stdout($cmd);
+        if(length $stderr>1){    
+            add_colored_info($tview,"$stderr\n","red");         
+        }else {
+            add_info($tview,"$stdout\n");
+        }            
+    });
+    #$window->show_all();
 }
 
-
 # source files : $target_dir/src_verilog
 # work dir : $target_dir/src_verilog
-
-
 sub create_file_list {
-	my ($target_dir,$files_ref, $platform)=@_;
-	my @ff=@{$files_ref} if(defined $files_ref);
-	my $pakages=""; 
-	my $file_list="";
-	my $include="";	
-	
-	my %paths;
-	my @files = File::Find::Rule->file()
-        	->name( '*.v','*.V','*.sv','*.vh')
+    my ($target_dir,$files_ref, $platform)=@_;
+    my @ff=@{$files_ref} if(defined $files_ref);
+    my $pakages=""; 
+    my $file_list="";
+    my $include="";    
+    my %paths;
+    my @files = File::Find::Rule->file()
+            ->name( '*.v','*.V','*.sv','*.vh')
             ->in( @ff );
-            
     @ff =uniq( @ff);        
-            
-	foreach my $file (@files) {
-		my ($name,$path,$suffix) = fileparse("$file",qr"\..[^.]*$");
-		#print "$path\n";
-		my $remove="$target_dir/";
-		$path =~ s/$remove//; 	
-		$paths{$path}=1;
-		
-		#put packages at the top of the list 
-		if(check_file_has_string($file,'endpackage')){
-			$pakages.="../${path}${name}$suffix\n" if($platform eq 'modelsim');
-			$pakages.="./${name}$suffix\n" if($platform eq 'verilator');
-		} else{
-			$file_list.= "../${path}${name}$suffix\n"if($platform eq 'modelsim');
-			$file_list.= "./${name}$suffix\n"if($platform eq 'verilator');
-		}		
-	}
-	 foreach my $p (sort keys %paths){
-	 	$include.="+incdir+../$p\n";	
-	 }
-	
-	return "$include\n$pakages\n$file_list";
+    foreach my $file (@files) {
+        my ($name,$path,$suffix) = fileparse("$file",qr"\..[^.]*$");
+        #print "$path\n";
+        my $remove="$target_dir/";
+        $path =~ s/$remove//;     
+        $paths{$path}=1;
+        #put packages at the top of the list 
+        if(check_file_has_string($file,'endpackage')){
+            $pakages.="../${path}${name}$suffix\n" if($platform eq 'modelsim');
+            $pakages.="./${name}$suffix\n" if($platform eq 'verilator');
+        } else{
+            $file_list.= "../${path}${name}$suffix\n"if($platform eq 'modelsim');
+            $file_list.= "./${name}$suffix\n"if($platform eq 'verilator');
+        }        
+    }
+    foreach my $p (sort keys %paths){
+        $include.="+incdir+../$p\n";    
+    }
+    return "$include\n$pakages\n$file_list";
 }
 
-
 sub verilator_compilation {
-	my ($top_ref,$target_dir,$outtext,$cpu_num)=@_;
-	$cpu_num = 1 if (!defined $cpu_num);
-	my %tops = %{$top_ref};
-	#creat verilator dir
-	add_info($outtext,"create verilator dir in $target_dir\n");
-	my $verilator="$target_dir/verilator";
-	
-	rmtree("$verilator");
-	mkpath("$verilator",1,01777);
-	
-	my @ff = ("$target_dir/src_verilog");
-	push (@ff,"$target_dir/src_verilator") if (-d "$target_dir/src_verilator");
-	push (@ff,"$target_dir/src_sim") if (-d "$target_dir/src_sim");
-	
-	#create a file list
-	add_info($outtext,"make a file list containig all RTL modules\n");
-	my $tt =create_file_list($target_dir,\@ff,'verilator');	
-	save_file("$verilator/file_list.f",  "$tt");
-   	
-   	#check if -Wno-TIMESCALEMOD flag is supported"
+    my ($top_ref,$target_dir,$outtext,$cpu_num)=@_;
+    $cpu_num = 1 if (!defined $cpu_num);
+    my %tops = %{$top_ref};
+    #creat verilator dir
+    add_info($outtext,"create verilator dir in $target_dir\n");
+    my $verilator="$target_dir/verilator";
+    rmtree("$verilator");
+    mkpath("$verilator",1,01777);
+    my @ff = ("$target_dir/src_verilog");
+    push (@ff,"$target_dir/src_verilator") if (-d "$target_dir/src_verilator");
+    push (@ff,"$target_dir/src_sim") if (-d "$target_dir/src_sim");
+    #create a file list
+    add_info($outtext,"make a file list containig all RTL modules\n");
+    my $tt =create_file_list($target_dir,\@ff,'verilator');    
+    save_file("$verilator/file_list.f",  "$tt");
+    #check if -Wno-TIMESCALEMOD flag is supported"
     my $flag="";
- #   my $cmd ="verilator --version | head -n1 | cut -d\" \" -f2";
-  # 	my ($stdout,$exit,$stderr)=run_cmd_in_back_ground_get_stdout($cmd);
-   
-   #	my $current_v=$stdout;
-   #	$current_v =~ s/[^0-9.]//g;
-   #	if (defined $current_v){
-   #		$cmd = "printf \'%s\n\' \"4.0.0\" \"$current_v\" | sort -V | head -n1";
-   #		my ($stdout,$exit,$stderr)=run_cmd_in_back_ground_get_stdout($cmd);
-   #		$stdout =~ s/[^0-9.]//g;
-   #		if ($stdout eq "4.0.0" ){
-   #			add_info($outtext, "Verilator vesrion $current_v is Greater than or equal to 4.0.0. So compile with -Wno-TIMESCALEMOD flag\n");
-   #			$flag.="-Wno-TIMESCALEMOD";
-   #		}else{
-   #     		add_info($outtext, "Verilator vesrion is $current_v\n");
-   #		}
-   # 	}
-  my $pdir	  = get_project_dir();
-  my $tmp = "$pdir/mpsoc/perl_gui/lib/verilog/tmp.v";
-  my $cmd = "verilator --lint-only $tmp  -Wno-TIMESCALEMOD";
-  my ($stdout,$exit,$stderr)=run_cmd_in_back_ground_get_stdout($cmd); 
- 
-  if(length $stderr>1){	#-Wno-TIMESCALEMOD not supported		
-		#add_info($outtext,"$stderr\n"); #verilator compain some ignoerabe warnning as error.  
-  }else {
-		#add_info($outtext,"compile verilator with -Wno-TIMESCALEMOD\n");
-		$flag.="-Wno-TIMESCALEMOD";
-  } 	
-   	
-	#run verilator
-	my $jobs=0; #a counter to limit the number of paralle process 
-	my $make_lib=""; 
-	$cmd="cd \"$verilator\"; ";
-	my $vrun="#!/bin/bash
+    #   my $cmd ="verilator --version | head -n1 | cut -d\" \" -f2";
+    #     my ($stdout,$exit,$stderr)=run_cmd_in_back_ground_get_stdout($cmd);
+    #    my $current_v=$stdout;
+    #    $current_v =~ s/[^0-9.]//g;
+    #    if (defined $current_v){
+    #        $cmd = "printf \'%s\n\' \"4.0.0\" \"$current_v\" | sort -V | head -n1";
+    #        my ($stdout,$exit,$stderr)=run_cmd_in_back_ground_get_stdout($cmd);
+    #        $stdout =~ s/[^0-9.]//g;
+    #        if ($stdout eq "4.0.0" ){
+    #            add_info($outtext, "Verilator vesrion $current_v is Greater than or equal to 4.0.0. So compile with -Wno-TIMESCALEMOD flag\n");
+    #            $flag.="-Wno-TIMESCALEMOD";
+    #        }else{
+    #             add_info($outtext, "Verilator vesrion is $current_v\n");
+    #        }
+    #     }
+    my $pdir      = get_project_dir();
+    my $tmp = "$pdir/mpsoc/perl_gui/lib/verilog/tmp.v";
+    my $cmd = "verilator --lint-only $tmp  -Wno-TIMESCALEMOD";
+    my ($stdout,$exit,$stderr)=run_cmd_in_back_ground_get_stdout($cmd); 
+    
+    if(length $stderr>1){    #-Wno-TIMESCALEMOD not supported        
+        #add_info($outtext,"$stderr\n"); #verilator compain some ignoerabe warnning as error.  
+    }else {
+        #add_info($outtext,"compile verilator with -Wno-TIMESCALEMOD\n");
+        $flag.="-Wno-TIMESCALEMOD";
+    }     
+    
+    #run verilator
+    my $jobs=0; #a counter to limit the number of paralle process 
+    my $make_lib=""; 
+    $cmd="cd \"$verilator\"; ";
+    my $vrun="#!/bin/bash
 cd \"$verilator\"
 ";
-	#my $cmd= "cd \"$verilator/processed_rtl\" \n xterm -e bash -c ' verilator  --cc $name.v --profile-cfuncs --prefix \"Vtop\" -O3  -CFLAGS -O3'";
-	my $length = scalar (keys %tops);
-	foreach my $top (sort keys %tops) {
-		add_colored_info($outtext,"Generate $top Verilator model from $tops{$top} file\n",'green');
-		$cmd.= "verilator  -f ./file_list.f --cc $tops{$top}  --prefix \"$top\" $flag -O3  -CFLAGS -O3 & ";
-		$vrun.="verilator  -f ./file_list.f --cc $tops{$top}  --prefix \"$top\" $flag -O3  -CFLAGS -O3 &\n";
-		
-		$make_lib.="make lib$jobs &\n";
-		$jobs++;
-		
-		if( $jobs % $cpu_num == 0 || $jobs == $length){
-			$vrun.="wait\n"; $make_lib.="wait\n"; $cmd.="wait\n";
-			add_info($outtext,"$cmd\n");	
-			my ($stdout,$exit,$stderr)=run_cmd_in_back_ground_get_stdout($cmd);
-			if(length $stderr>1){			
-				add_info($outtext,"$stderr\n"); #verilator compain some ignoerabe warnning as error.  
-			}else {
-				add_info($outtext,"$stdout\n");
-			}
-			$cmd="cd \"$verilator\"; ";
-		}			
-	}
-	
-
-
-	#check if verilator model has been generated 
-	foreach my $top (sort keys %tops) {
-		
-		$vrun.=" 
+    #my $cmd= "cd \"$verilator/processed_rtl\" \n xterm -e bash -c ' verilator  --cc $name.v --profile-cfuncs --prefix \"Vtop\" -O3  -CFLAGS -O3'";
+    my $length = scalar (keys %tops);
+    foreach my $top (sort keys %tops) {
+        add_colored_info($outtext,"Generate $top Verilator model from $tops{$top} file\n",'green');
+        $cmd.= "verilator -DNO_HETRO_IVC=1 -f ./file_list.f --cc $tops{$top}  --prefix \"$top\" $flag -O3  -CFLAGS -O3 & ";
+        $vrun.="verilator -DNO_HETRO_IVC=1 -f ./file_list.f --cc $tops{$top}  --prefix \"$top\" $flag -O3  -CFLAGS -O3 &\n";
+        
+        $make_lib.="make lib$jobs &\n";
+        $jobs++;
+        
+        if( $jobs % $cpu_num == 0 || $jobs == $length){
+            $vrun.="wait\n"; $make_lib.="wait\n"; $cmd.="wait\n";
+            add_info($outtext,"$cmd\n");    
+            my ($stdout,$exit,$stderr)=run_cmd_in_back_ground_get_stdout($cmd);
+            if(length $stderr>1){            
+                add_info($outtext,"$stderr\n"); #verilator compain some ignoerabe warnning as error.  
+            }else {
+                add_info($outtext,"$stdout\n");
+            }
+            $cmd="cd \"$verilator\"; ";
+        }            
+    }
+    #check if verilator model has been generated 
+    foreach my $top (sort keys %tops) {
+        
+        $vrun.=" 
 if ! [ -f $verilator/obj_dir/$top.cpp ]; then
-	echo  \"Failed to generate: $verilator/obj_dir/$top.cpp \"
-	exit 1	
+    echo  \"Failed to generate: $verilator/obj_dir/$top.cpp \"
+    exit 1    
 fi
 ";
-		
-		if (-f "$verilator/obj_dir/$top.cpp"){#succsess
-			
-			
-		}else {
-			return 0;
-		}	
-	}
-	#generate makefile
-	gen_verilator_makefile($top_ref,"$verilator/obj_dir/Makefile");
-	
-$vrun.="	echo  \"Verilator modules are generated successfully\". 
+        if (-f "$verilator/obj_dir/$top.cpp"){#succsess
+        }else {
+            return 0;
+        }    
+    }
+    #generate makefile
+    gen_verilator_makefile($top_ref,"$verilator/obj_dir/Makefile");
+    
+$vrun.="    echo  \"Verilator modules are generated successfully\". 
 
 cd $verilator/obj_dir/
 
@@ -2081,285 +1672,212 @@ sub verilator_compilation {
 make sim
 #done
 ";
-	
-	
-	save_file ("$verilator/verilate.sh",$vrun);
-	#copy topology connection header files
-	my $project_dir	= get_project_dir();
-	$project_dir= "$project_dir/mpsoc";
-	my $src_verilator_dir="$project_dir/src_verilator";
-	my @files = File::Find::Rule->file()
-        	->name( '*.h')
+    save_file ("$verilator/verilate.sh",$vrun);
+    #copy topology connection header files
+    my $project_dir    = get_project_dir();
+    $project_dir= "$project_dir/mpsoc";
+    my $src_verilator_dir="$project_dir/src_verilator";
+    my @files = File::Find::Rule->file()
+            ->name( '*.h')
             ->in( "$src_verilator_dir" );
-	copy_file_and_folders (\@files,$project_dir,"$verilator/obj_dir/");
-	
-	return 1;
+    copy_file_and_folders (\@files,$project_dir,"$verilator/obj_dir/");
+    
+    return 1;
 }
 
-
-
-
-
 sub verilator_compilation_win {
-	my ($self,$name,$top,$target_dir,$vendor)=@_;
-	my $window = def_popwin_size(80,80,"Step 2: Compile",'percent');
-	my $mtable = def_table(10, 10, FALSE);
-	my ($outbox,$outtext)= create_txview();
-	
-	
-	my $next=def_image_button('icons/run.png','Next');
-	my $back=def_image_button('icons/left.png','Previous');	
-	my $load= show_gif("icons/load.gif");
-	$mtable->attach($load,8,9,9,10,'shrink','shrink',2,2);
-	
-	$mtable->attach_defaults ($outbox ,0, 10, 4,9);
-	$mtable->attach($back,2,3,9,10,'shrink','shrink',2,2);
-	
-
-
-	
-	$back-> signal_connect("clicked" => sub{ 
-		
-		$window->destroy;
-		select_compiler($self,$name,$top,$target_dir);
-		
-	});
-	$next-> signal_connect("clicked" => sub{ 
-		
-		$window->destroy;
-		verilator_testbench($self,$name,$top,$target_dir,$vendor);
-		
-	});
-
-	$window->add ($mtable);
-	$window->show_all();
-
-	
-	my $result;
-	my $cpu_num = $self->object_get_attribute('compile', 'cpu_num');
-	
-	my $n= $self->object_get_attribute('soc_name',undef);
-	if(defined $n){	#we are compiling a single tile as SoC
-		my $sw_path 	= "$target_dir/sw";
-		my %params = soc_get_all_parameters($self);
-		my $verilator = soc_generate_verilator ($self,$sw_path,"verilator_$n",\%params);	
+    my ($self,$name,$top,$target_dir,$vendor)=@_;
+    my $window = def_popwin_size(80,80,"Step 2: Compile",'percent');
+    my $mtable = def_table(10, 10, FALSE);
+    my ($outbox,$outtext)= create_txview();   
+    
+    my $next=def_image_button('icons/run.png','Next');
+    my $back=def_image_button('icons/left.png','Previous');    
+    my $load= show_gif("icons/load.gif");
+    $mtable->attach($load,8,9,9,10,'shrink','shrink',2,2);
+    
+    $mtable->attach_defaults ($outbox ,0, 10, 4,9);
+    $mtable->attach($back,2,3,9,10,'shrink','shrink',2,2);    
+    $back-> signal_connect("clicked" => sub{ 
+        $window->destroy;
+        select_compiler($self,$name,$top,$target_dir);
+        
+    });
+    $next-> signal_connect("clicked" => sub{ 
+        
+        $window->destroy;
+        verilator_testbench($self,$name,$top,$target_dir,$vendor);
+        
+    });
+
+    $window->add ($mtable);
+    $window->show_all();
+    my $result;
+    my $cpu_num = $self->object_get_attribute('compile', 'cpu_num');
+    my $n= $self->object_get_attribute('soc_name',undef);
+    if(defined $n){    #we are compiling a single tile as SoC
+        my $sw_path     = "$target_dir/sw";
+        my %params = soc_get_all_parameters($self);
+        my $verilator = soc_generate_verilator ($self,$sw_path,"verilator_$n",\%params);    
         my %tops;
-		$tops{"Vtop"}= "--top-module verilator_$n";
-		my $target_verilator_dr ="$target_dir/src_verilator";
-     	mkpath("$target_verilator_dr",1,01777);
-     	save_file ("$target_verilator_dr/verilator_${n}.sv",$verilator);	
-	
-	
-	
-	
-		
-		#$tops{"Vtop"}= "--top-module $name";
-		$result = verilator_compilation (\%tops,$target_dir,$outtext,$cpu_num);	
-		$self->object_add_attribute('verilator','libs',\%tops);	
-	}
-	else { # we are compiling a complete NoC-based mpsoc
-		$result = gen_mpsoc_verilator_model ($self,$name,$top,$target_dir,$outtext,$cpu_num);		
-		
-		
-	}
-
-	
-	#check if verilator model has been generated 
-	if ($result){
-		add_colored_info($outtext,"Veriator model has been generated successfully!",'blue');
-		$load->destroy();
-		$mtable->attach($next,8,9,9,10,'shrink','shrink',2,2);
-	}else {
-		add_colored_info($outtext,"Verilator compilation failed!\n","red"); 
-		$load->destroy();
-		$next->destroy();
-	}			
+        $tops{"Vtop"}= "--top-module verilator_$n";
+        my $target_verilator_dr ="$target_dir/src_verilator";
+        mkpath("$target_verilator_dr",1,01777);
+        save_file ("$target_verilator_dr/verilator_${n}.sv",$verilator);    
+        #$tops{"Vtop"}= "--top-module $name";
+        $result = verilator_compilation (\%tops,$target_dir,$outtext,$cpu_num);    
+        $self->object_add_attribute('verilator','libs',\%tops);    
+    }
+    else { # we are compiling a complete NoC-based mpsoc
+        $result = gen_mpsoc_verilator_model ($self,$name,$top,$target_dir,$outtext,$cpu_num);        
+    }
+    #check if verilator model has been generated 
+    if ($result){
+        add_colored_info($outtext,"Veriator model has been generated successfully!",'blue');
+        $load->destroy();
+        $mtable->attach($next,8,9,9,10,'shrink','shrink',2,2);
+    }else {
+        add_colored_info($outtext,"Verilator compilation failed!\n","red"); 
+        $load->destroy();
+        $next->destroy();
+    }            
 }
 
-
-
-
-
 sub  gen_mpsoc_verilator_model{
-	my ($self,$name,$top,$target_dir,$outtext,$cpu_num)=@_;	
-	
-	my $project_dir	= get_project_dir();
-	$project_dir= "$project_dir/mpsoc";
-	my $src_verilator_dir="$project_dir/src_verilator";
-	my $target_verilog_dr ="$target_dir/src_verilog";
-	my $target_verilator_dr ="$target_dir/src_verilator";
-	
-	my $sw_dir 	= "$target_dir/sw";
-	my $src_noc_dir="$project_dir/rtl/src_noc";	
-	mkpath("$target_verilator_dr",1,01777);
-		
-	#copy src_verilator files
-	my @files_list = File::Find::Rule->file()
+    my ($self,$name,$top,$target_dir,$outtext,$cpu_num)=@_;    
+    my $project_dir    = get_project_dir();
+    $project_dir= "$project_dir/mpsoc";
+    my $src_verilator_dir="$project_dir/src_verilator";
+    my $target_verilog_dr ="$target_dir/src_verilog";
+    my $target_verilator_dr ="$target_dir/src_verilator";
+    
+    my $sw_dir     = "$target_dir/sw";
+    my $src_noc_dir="$project_dir/rtl/src_noc";    
+    mkpath("$target_verilator_dr",1,01777);
+    #copy src_verilator files
+    my @files_list = File::Find::Rule->file()
                             ->name( '*.v','*.V','*.sv' )
                             ->in( "$src_verilator_dir" );
 
-	#make sure source files have key word 'module' 
-	my @files;
-	foreach my $p (@files_list){
-		push (@files,$p)	if(check_file_has_string($p,'module')); 
-	}
-	copy_file_and_folders (\@files,$project_dir,$target_verilator_dr);
-	
-	
-	
-	#copy src_noc files
-	#my @files2;
-	#push (@files2,$src_noc_dir);
-	#copy_file_and_folders (\@files2,$project_dir,$target_verilog_dr);
-	
-		
-	#create each tile top module 	
+    #make sure source files have key word 'module' 
+    my @files;
+    foreach my $p (@files_list){
+        push (@files,$p)    if(check_file_has_string($p,'module')); 
+    }
+    copy_file_and_folders (\@files,$project_dir,$target_verilator_dr);
+    #copy src_noc files
+    #my @files2;
+    #push (@files2,$src_noc_dir);
+    #copy_file_and_folders (\@files2,$project_dir,$target_verilog_dr);
+    #create each tile top module     
     my $processors_en=0;
     my $mpsoc=$self;    
     my $lisence= get_license_header("verilator_tiles"); 
-	my $warning=autogen_warning();    
+    my $warning=autogen_warning();    
     my $verilator=$lisence.$warning;
+    # generate NoC parameter file
+    my ($noc_param,$pass_param)=gen_noc_param_v($self);
+    my $noc_param_v= " \`ifdef     INCLUDE_PARAM \n \n 
+    $noc_param  
     
+    //simulation parameter    
     
-    # generate NoC parameter file
-	my ($noc_param,$pass_param)=gen_noc_param_v($self);
-	
-	my $noc_param_v= " \`ifdef     INCLUDE_PARAM \n \n 
-	$noc_param  
-	
-	//simulation parameter	
-	
 \n \n \`endif" ; 
-	#save_file("$target_verilator_dr/parameter.v",$noc_param_v);
-	
-	
-	
-	
+    #save_file("$target_verilator_dr/parameter.v",$noc_param_v);
     my ($nr,$ne,$router_p,$ref_tops)= get_noc_verilator_top_modules_info($self);
     my %tops = %{$ref_tops};
-    	
     for (my $tile_num=0;$tile_num<$ne;$tile_num++){
-	
-		#print "$tile_num\n";
-		my ($soc_name,$num)= $mpsoc->mpsoc_get_tile_soc_name($tile_num);
-		
-		my $soc=eval_soc($mpsoc,$soc_name,$outtext);
-		
-		
-		my $top=$mpsoc->mpsoc_get_soc($soc_name);
-		my $soc_num= $tile_num;		
-		
-		
-		#update core id
-		$soc->object_add_attribute('global_param','CORE_ID',$tile_num);
-		
-		#update NoC param
-		my $nocparam =$mpsoc->object_get_attribute('noc_param',undef);
-		my ($NE, $NR, $RAw, $EAw, $Fw) = get_topology_info($mpsoc);
-		my %y=%{$nocparam};
-		$y{'EAw'} = $EAw;
-		$y{'RAw'} = $RAw;
-		$y{'Fw'}  = $Fw; 		
-		my @nis=get_NI_instance_list($top);
-		$soc->soc_add_instance_param($nis[0] ,\%y );
-		my %z;
-		
-		my %param_type=  $soc->soc_get_module_param_type($nis[0]); 
-		foreach my $p (sort keys %y){
-			$z{$p}=$param_type{$p}; #"Parameter";
-		}
-		
-		
-		
-				
-		$soc->soc_add_instance_param_type($nis[0] ,\%z );
-		
-		
-		my $tile=$tile_num;
-		my $setting=$mpsoc->mpsoc_get_tile_param_setting($tile);
-		my %params;
-		#if ($setting eq 'Custom'){
-			 %params= $top->top_get_custom_soc_param($tile);
-		#}else{
-		#	 %params=$top->top_get_default_soc_param();
-		#}
-				
-				
-		my $sw_path 	= "$sw_dir/tile$tile_num";
-		$verilator = $verilator.soc_generate_verilator ($soc,$sw_path,"tile_$tile",\%params);	
-		$tops{"Vtile$tile_num"}= "--top-module tile_$tile";
-				
-	
-	}
-	
-	save_file ("$target_verilator_dr/verilator_tiles.sv",$verilator);
-	my $result = verilator_compilation (\%tops,$target_dir,$outtext,$cpu_num);
-	$self->object_add_attribute('verilator','libs',\%tops);		
-	return $result;
-
+        #print "$tile_num\n";
+        my ($soc_name,$num)= $mpsoc->mpsoc_get_tile_soc_name($tile_num);
+        my $soc=eval_soc($mpsoc,$soc_name,$outtext);
+        my $top=$mpsoc->mpsoc_get_soc($soc_name);
+        my $soc_num= $tile_num;        
+        #update core id
+        $soc->object_add_attribute('global_param','CORE_ID',$tile_num);
+        #update NoC param
+        my $nocparam =$mpsoc->object_get_attribute('noc_param',undef);
+        my ($NE, $NR, $RAw, $EAw, $Fw) = get_topology_info($mpsoc);
+        my %y=%{$nocparam};
+        $y{'EAw'} = $EAw;
+        $y{'RAw'} = $RAw;
+        $y{'Fw'}  = $Fw;         
+        my @nis=get_NI_instance_list($top);
+        $soc->soc_add_instance_param($nis[0] ,\%y );
+        my %z;
+        my %param_type=  $soc->soc_get_module_param_type($nis[0]); 
+        foreach my $p (sort keys %y){
+            $z{$p}=$param_type{$p}; #"Parameter";
+        }
+        $soc->soc_add_instance_param_type($nis[0] ,\%z );
+        my $tile=$tile_num;
+        my $setting=$mpsoc->mpsoc_get_tile_param_setting($tile);
+        my %params;
+        #if ($setting eq 'Custom'){
+        %params= $top->top_get_custom_soc_param($tile);
+        #}else{
+        #     %params=$top->top_get_default_soc_param();
+        #}
+        my $sw_path     = "$sw_dir/tile$tile_num";
+        $verilator = $verilator.soc_generate_verilator ($soc,$sw_path,"tile_$tile",\%params);    
+        $tops{"Vtile$tile_num"}= "--top-module tile_$tile";
+    }
+    save_file ("$target_verilator_dr/verilator_tiles.sv",$verilator);
+    my $result = verilator_compilation (\%tops,$target_dir,$outtext,$cpu_num);
+    $self->object_add_attribute('verilator','libs',\%tops);        
+    return $result;
 }
 
-
 sub gen_verilator_soc_testbench {
-	my ($self,$name,$top,$target_dir)=@_;
-	my $verilator="$target_dir/verilator";
-	my $dir="$verilator/";
-	my $soc_top= $self->soc_get_top ();
-	
-	my $include='#include <stdlib.h>
+    my ($self,$name,$top,$target_dir)=@_;
+    my $verilator="$target_dir/verilator";
+    my $dir="$verilator/";
+    my $soc_top= $self->soc_get_top ();
+    my $include='#include <stdlib.h>
 #include <stdio.h>
 #include <unistd.h>
 #include <string.h>
 ';
-	my @intfcs=$soc_top->top_get_intfc_list();
-	my %PP;
-	my %rxds;
-	my $top_port_info="IO type\t  port_size\t  port_name\n";
-	foreach my $intfc (@intfcs){
-		my $key= ( $intfc eq 'plug:clk[0]')? 'clk' : 
-			 ( $intfc eq 'plug:reset[0]')? 'reset':
-			 ( $intfc eq 'plug:enable[0]')? 'en' : 
-			 ( $intfc eq  'socket:RxD_sim[0]')? 'rxd':
-			 'other';
-		 
-			 
-		my $key1="${key}1";
-		my $key0="${key}0";
-
-		my @ports=$soc_top->top_get_intfc_ports_list($intfc);
-		foreach my $p (@ports){
-			my($inst,$range,$type,$intfc_name,$intfc_port)= $soc_top->top_get_port($p);
-			$PP{$key1}= (defined $PP{$key1})? "$PP{$key1} top->$p=1;\n" : "top->$p=1;\n";
-			$PP{$key0}= (defined $PP{$key0})? "$PP{$key0} top->$p=0;\n" : "top->$p=0;\n";	
-			$top_port_info="$top_port_info $type  $range  top->$p \n";
-		}
-		if($key eq 'rxd'){
-			my @ports=$soc_top->top_get_intfc_ports_list($intfc);
-			foreach my $p (@ports){
-				my($id,$range,$type,$intfc_name,$intfc_port)= $soc_top->top_get_port($p);
-				my @q =split  (/RxD_ready_si/,$p);
-				$rxds{$id}{p}=$q[0]  if( defined $q[1]);
-				$rxds{$id}{top}='top'  if( defined $q[1]);
-			}			
-		}
-
-	}
-	
-
- my ($rxd_info, $rxd_num, $rxd_wr_cal,$rxd_cap_cal, $include1)=rxd_testbench_verilator_gen (\%rxds,$dir);
- my $include2="";
+    my @intfcs=$soc_top->top_get_intfc_list();
+    my %PP;
+    my %rxds;
+    my $top_port_info="IO type\t  port_size\t  port_name\n";
+    foreach my $intfc (@intfcs){
+        my $key= ( $intfc eq 'plug:clk[0]')? 'clk' : 
+            ( $intfc eq 'plug:reset[0]')? 'reset':
+            ( $intfc eq 'plug:enable[0]')? 'en' : 
+            ( $intfc eq  'socket:RxD_sim[0]')? 'rxd':
+            'other';
+        my $key1="${key}1";
+        my $key0="${key}0";
+        my @ports=$soc_top->top_get_intfc_ports_list($intfc);
+        foreach my $p (@ports){
+            my($inst,$range,$type,$intfc_name,$intfc_port)= $soc_top->top_get_port($p);
+            $PP{$key1}= (defined $PP{$key1})? "$PP{$key1} top->$p=1;\n" : "top->$p=1;\n";
+            $PP{$key0}= (defined $PP{$key0})? "$PP{$key0} top->$p=0;\n" : "top->$p=0;\n";    
+            $top_port_info="$top_port_info $type  $range  top->$p \n";
+        }
+        if($key eq 'rxd'){
+            my @ports=$soc_top->top_get_intfc_ports_list($intfc);
+            foreach my $p (@ports){
+                my($id,$range,$type,$intfc_name,$intfc_port)= $soc_top->top_get_port($p);
+                my @q =split  (/RxD_ready_si/,$p);
+                $rxds{$id}{p}=$q[0]  if( defined $q[1]);
+                $rxds{$id}{top}='top'  if( defined $q[1]);
+            }            
+        }
+    }
+    my ($rxd_info, $rxd_num, $rxd_wr_cal,$rxd_cap_cal, $include1)=rxd_testbench_verilator_gen (\%rxds,$dir);
+    my $include2="";
  $include2 .= '#include "RxDsim.h" // Header file for sending charactor to UART from STDIN' if($rxd_num > 0);
-	
+    
 my $main_c=get_license_header("testbench.cpp");
 
-
-
 $main_c="$main_c
 $include
 $include1
 #include <verilated.h>          // Defines common routines
 #include \"Vtop.h\"               // From Verilating \"$name.v\" file
-Vtop		 	*top;
+Vtop             *top;
 $include2
 /*
 $top_port_info
@@ -2371,74 +1889,71 @@ sub gen_verilator_soc_testbench {
 unsigned int main_time = 0; // Current simulation time
 
 int main(int argc, char** argv) {
-	$rxd_info
-	Verilated::commandArgs(argc, argv);   // Remember args
-	top	= new Vtop;
-
-	/********************
-	*	initialize input
-	*********************/
-
-	$PP{reset1}
-	$PP{en1}  
-	main_time=0;
-	printf(\"Start Simulation\\n\");
-	while (!Verilated::gotFinish()) {
-		$rxd_cap_cal
-	    if ((main_time & 0x3FF)==0) fflush(stdout); // fflush \$dispaly command each 1024 clock cycle 
-		if (main_time >= 10 ) { 
-			$PP{reset0}
-		}	
-
-
-		if ((main_time & 1) == 0) {
-			$PP{clk1}      // Toggle clock
-			// you can change the inputs and read the outputs here in case they are captured at posedge of clock 
-			$rxd_wr_cal
-
-
-		}//if
-		else
-		{
-			$PP{clk0}  
-			
-		
-
-		}//else
-			
-		
-		main_time ++;		 
-		top->eval(); 
-		}
-	top->final(); 
+    $rxd_info
+    Verilated::commandArgs(argc, argv);   // Remember args
+    top    = new Vtop;
+
+    /********************
+    *    initialize input
+    *********************/
+
+    $PP{reset1}
+    $PP{en1}  
+    main_time=0;
+    printf(\"Start Simulation\\n\");
+    while (!Verilated::gotFinish()) {
+        $rxd_cap_cal
+        if ((main_time & 0x3FF)==0) fflush(stdout); // fflush \$dispaly command each 1024 clock cycle 
+        if (main_time >= 10 ) { 
+            $PP{reset0}
+        }    
+
+        if ((main_time & 1) == 0) {
+            $PP{clk1}      // Toggle clock
+            // you can change the inputs and read the outputs here in case they are captured at posedge of clock 
+            $rxd_wr_cal
+
+
+        }//if
+        else
+        {
+            $PP{clk0}  
+            
+        
+
+        }//else
+            
+        
+        main_time ++;         
+        top->eval(); 
+        }
+    top->final(); 
 }
 
 double sc_time_stamp () {       // Called by \$time in Verilog
-	return main_time;
+    return main_time;
 }
 ";
-	save_file("$dir/testbench.cpp",$main_c);
-   
-	
+    save_file("$dir/testbench.cpp",$main_c);
+    
 
 }
 
 sub eval_soc{
-	my ($mpsoc,$soc_name,$outtext)=@_;
-	my $path=$mpsoc->object_get_attribute('setting','soc_path');	
-	$path=~ s/ /\\ /g;
-  	my $p = "$path/$soc_name.SOC";
-	my ($soc,$r,$err) = regen_object($p);
-	if ($r){		
-		show_info($outtext,"**Error reading  $p file: $err\n");
-	       next; 
-	} 
-	return $soc;	
+    my ($mpsoc,$soc_name,$outtext)=@_;
+    my $path=$mpsoc->object_get_attribute('setting','soc_path');    
+    $path=~ s/ /\\ /g;
+    my $p = "$path/$soc_name.SOC";
+    my ($soc,$r,$err) = regen_object($p);
+    if ($r){        
+        show_info($outtext,"**Error reading  $p file: $err\n");
+        next; 
+    } 
+    return $soc;    
 }
 
 sub rxd_testbench_verilator_gen {
-my 	($rxds_ref,$dir)=@_;
-
+my     ($rxds_ref,$dir)=@_;
 my $rxd_info='';
 my $rxd_num=0;
 my $rxd_func='';
@@ -2447,237 +1962,214 @@ sub rxd_testbench_verilator_gen {
 my $include='';
 
 my %rxds=%{$rxds_ref};
-	
 foreach my $rxd (sort keys %rxds){
-	my $n=$rxds{$rxd}{p};
-	my $top=$rxds{$rxd}{top};
-	$rxd_info.="\\t$rxd_num : ${top}_${n}RXD\\n";
-	
-	$rxd_func.="
-	// we have a character to send to interface $rxd_num
-	if (sent_table[$rxd_num]!=0 &&  $top->${n}RxD_ready_sim){ 
-		$top->${n}RxD_din_sim=sent_table[$rxd_num]; 
+    my $n=$rxds{$rxd}{p};
+    my $top=$rxds{$rxd}{top};
+    $rxd_info.="\\t$rxd_num : ${top}_${n}RXD\\n";
+    $rxd_func.="
+    // we have a character to send to interface $rxd_num
+    if (sent_table[$rxd_num]!=0 &&  $top->${n}RxD_ready_sim){ 
+        $top->${n}RxD_din_sim=sent_table[$rxd_num]; 
         $top->${n}RxD_wr_sim=1; 
         sent_table[$rxd_num]=0;
-	}else {
-		$top->${n}RxD_wr_sim=0; 
-	}
+    }else {
+        $top->${n}RxD_wr_sim=0; 
+    }
 ";
-	$rxd_num++;
+    $rxd_num++;
 } 
 
 
 
-if($rxd_num>0){	
+if($rxd_num>0){    
 $rxd_func="
 #ifndef RXD_SIM_H
 #define RXD_SIM_H
-	#define RXD_NUM  $rxd_num  // number of rxd input interfaces
-	char sent_table[RXD_NUM]={0};	
-	unsigned char active_rxd_num=0;	
-	void write_char_on_RXD( ) {			
-		$rxd_func	
-	}
-	
-	int kbhit(void) {
-	  struct termios oldt, newt;
-	  int ch;
-	  int oldf;
-	 
-	  tcgetattr(STDIN_FILENO, &oldt);
-	  newt = oldt;
-	  newt.c_lflag &= ~(ICANON | ECHO);
-	  tcsetattr(STDIN_FILENO, TCSANOW, &newt);
-	  oldf = fcntl(STDIN_FILENO, F_GETFL, 0);
-	  fcntl(STDIN_FILENO, F_SETFL, oldf | O_NONBLOCK);
-	 
-	  ch = getchar();	 
-	  
-	  tcsetattr(STDIN_FILENO, TCSANOW, &oldt);
-	  fcntl(STDIN_FILENO, F_SETFL, oldf);
-	 
-	  if(ch != EOF)
-	  {
-	    ungetc(ch, stdin);
-	    return 1;
-	  }	 
-	  return 0;
-	}
-	
-	void capture_char_on_RXD (){
-		char c;
-		if(kbhit()){
-			c=getchar();
-			if(c=='+'){
-				active_rxd_num++;				
-				if(active_rxd_num>=$rxd_num) active_rxd_num=0;
-				printf(\"The active input interface num is \%u\\n\",active_rxd_num);
-			}else if(c=='-'){
-				active_rxd_num--;				
-				if(active_rxd_num>=$rxd_num) active_rxd_num=($rxd_num-1);
-				printf(\"The active input interface num is \%u\\n\",active_rxd_num);
-			}else{
-				sent_table[active_rxd_num]=c;
-			}			
-  			
-		}	
-	}
-#endif	
-	";
-	
-	
-	$include .='#include <termios.h>
+    #define RXD_NUM  $rxd_num  // number of rxd input interfaces
+    char sent_table[RXD_NUM]={0};    
+    unsigned char active_rxd_num=0;    
+    void write_char_on_RXD( ) {            
+        $rxd_func    
+    }
+    
+    int kbhit(void) {
+        struct termios oldt, newt;
+        int ch;
+        int oldf;
+        
+        tcgetattr(STDIN_FILENO, &oldt);
+        newt = oldt;
+        newt.c_lflag &= ~(ICANON | ECHO);
+        tcsetattr(STDIN_FILENO, TCSANOW, &newt);
+        oldf = fcntl(STDIN_FILENO, F_GETFL, 0);
+        fcntl(STDIN_FILENO, F_SETFL, oldf | O_NONBLOCK);
+        
+        ch = getchar();     
+        
+        tcsetattr(STDIN_FILENO, TCSANOW, &oldt);
+        fcntl(STDIN_FILENO, F_SETFL, oldf);
+        
+        if(ch != EOF)
+        {
+            ungetc(ch, stdin);
+            return 1;
+        }     
+        return 0;
+    }
+    
+    void capture_char_on_RXD (){
+        char c;
+        if(kbhit()){
+            c=getchar();
+            if(c=='+'){
+                active_rxd_num++;                
+                if(active_rxd_num>=$rxd_num) active_rxd_num=0;
+                printf(\"The active input interface num is \%u\\n\",active_rxd_num);
+            }else if(c=='-'){
+                active_rxd_num--;                
+                if(active_rxd_num>=$rxd_num) active_rxd_num=($rxd_num-1);
+                printf(\"The active input interface num is \%u\\n\",active_rxd_num);
+            }else{
+                sent_table[active_rxd_num]=c;
+            }            
+        }    
+    }
+#endif    
+    ";
+    
+    
+    $include .='#include <termios.h>
 #include <fcntl.h>
 ';
-	$rxd_wr_cal="write_char_on_RXD( );";
-	$rxd_cap_cal="capture_char_on_RXD( );"; 
-	$rxd_info="printf(\"There are total of $rxd_num RXD (UART) interface ports in the top module:\\n${rxd_info}The default interfce is 0. You can switch to different interfaces by pressing + or - key.\\n\");"	
+    $rxd_wr_cal="write_char_on_RXD( );";
+    $rxd_cap_cal="capture_char_on_RXD( );"; 
+    $rxd_info="printf(\"There are total of $rxd_num RXD (UART) interface ports in the top module:\\n${rxd_info}The default interfce is 0. You can switch to different interfaces by pressing + or - key.\\n\");"    
 }
 
-	my $rxsim_c=get_license_header("RxDsim.h");
-	$rxsim_c.="$rxd_func";
-	save_file("$dir/RxDsim.h",$rxsim_c) if($rxd_num > 0);
-
-	return ($rxd_info, $rxd_num, $rxd_wr_cal,$rxd_cap_cal, $include);
-	
+    my $rxsim_c=get_license_header("RxDsim.h");
+    $rxsim_c.="$rxd_func";
+    save_file("$dir/RxDsim.h",$rxsim_c) if($rxd_num > 0);
+    return ($rxd_info, $rxd_num, $rxd_wr_cal,$rxd_cap_cal, $include);
+    
 }
 
-
-
 sub gen_verilator_mpsoc_testbench {
-	my ($mpsoc,$name,$top,$target_dir,$tview)=@_;
-	my $verilator="$target_dir/verilator";
-	my $dir="$verilator/";
-	my $parameter_h=gen_noc_param_h($mpsoc);
-	
-	
-	my ($nr,$ne,$router_p,$ref_tops,$includ_h)= get_noc_verilator_top_modules_info($mpsoc);
-	
-	$parameter_h.="
-	#define NE  $ne
- 	#define NR  $nr
-	";
-	$parameter_h=$parameter_h.$includ_h;
-	
+    my ($mpsoc,$name,$top,$target_dir,$tview)=@_;
+    my $verilator="$target_dir/verilator";
+    my $dir="$verilator/";
+    my $parameter_h=gen_noc_param_h($mpsoc);
+    
+    
+    my ($nr,$ne,$router_p,$ref_tops,$includ_h)= get_noc_verilator_top_modules_info($mpsoc);
+    
+    $parameter_h.="
+    #define NE  $ne
+    #define NR  $nr
+    ";
+    $parameter_h=$parameter_h.$includ_h;
+    
 
     
-	my $libh="";
-	my $inst= "";
-	my $newinst="";
-	
-	my $tile_addr="";
-	my $tile_flit_in="";
-	my $tile_flit_in_l="";
-	my $tile_credit="";
-	my $noc_credit="";
-	my $noc_flit_in="";
-	my $noc_flit_in_l="";	
-	my $noc_flit_in_wr="";
-	my $noc_flit_in_wr_l="";
-	my $tile_flit_in_wr="";	
-	my $tile_flit_in_wr_l="";
-	my $tile_eval="";
-	my $tile_final=""; 	
-	my $tile_reset="";	
-	my $tile_clk="";	
-	my $tile_en="";		
-	my $top_port_info="IO type\t  port_size\t  port_name\n";	
-	my $no_connected='';
-	my %rxds;
-	
-	my $tile_chans="";
-	my $tmp_reg='';
-	for (my $endp=0; $endp<$ne;$endp++){	
-			
-		
-		my $e_addr=endp_addr_encoder($mpsoc,$endp);
-		my $router_num = get_connected_router_id_to_endp($mpsoc,$endp);
-		my $r_addr=router_addr_encoder($mpsoc,$router_num);
-		
-		
-		my ($soc_name,$num)= $mpsoc->mpsoc_get_tile_soc_name($endp);		
-		if(defined $soc_name) {#we have a conncted tile
-		
-			#get ni instance name
-			my $ni_name;
-			my $soc=eval_soc($mpsoc,$soc_name,$tview);
-			my $soc_top=$soc->object_get_attribute('top_ip',undef);
-			my @intfcs=$soc_top->top_get_intfc_list();
-			my @instances=$soc->soc_get_all_instances();
-			foreach my $id (@instances){
-					my $category = $soc->soc_get_category($id);
-					if ($category eq 'NoC') {
-						 $ni_name=  $soc->soc_get_instance_name($id);
-					}
-			}
-		
-				$tile_chans.="\ttile_chan_out[$endp] = &tile$endp->ni_chan_out;\n\ttile_chan_in[$endp] = &tile$endp->ni_chan_in;\n";
-				$libh=$libh."#include \"Vtile${endp}.h\"\n";
-				$inst=$inst."Vtile${endp}\t*tile${endp};\t  // Instantiation of tile${endp}\n";
-				$newinst = $newinst."\ttile${endp}\t=\tnew Vtile${endp};\n"; 
-				$tile_flit_in = $tile_flit_in . "\ttile${endp}->${ni_name}_flit_in  = noc->ni_flit_out [${endp}];\n";	
-				$tile_flit_in_l = $tile_flit_in_l . "\t\ttile${endp}->${ni_name}_flit_in[j]  = noc->ni_flit_out [${endp}][j];\n";
-				$tile_credit= $tile_credit."\ttile${endp}->${ni_name}_credit_in= noc->ni_credit_out[${endp}];\n";
-				$noc_credit= $noc_credit."\tnoc->ni_credit_in[${endp}] = tile${endp}->${ni_name}_credit_out;\n";	
-				$noc_flit_in=$noc_flit_in."\tnoc->ni_flit_in [${endp}]  = tile${endp}->${ni_name}_flit_out;\n";
-				$noc_flit_in_l=$noc_flit_in_l."\t\t\tnoc->ni_flit_in [${endp}][j]  = tile${endp}->${ni_name}_flit_out[j];\n";
-				$noc_flit_in_wr= $noc_flit_in_wr."\tif(tile${endp}->${ni_name}_flit_out_wr) noc->ni_flit_in_wr = noc->ni_flit_in_wr | ((vluint64_t)1<<${endp});\n";
-				$tile_flit_in_wr=$tile_flit_in_wr."\ttile${endp}->${ni_name}_flit_in_wr= ((noc->ni_flit_out_wr >> ${endp}) & 0x01);\n";
-				$noc_flit_in_wr_l= $noc_flit_in_wr_l."\tif(tile${endp}->${ni_name}_flit_out_wr) MY_VL_SETBIT_W(noc->ni_flit_in_wr ,${endp});\n";
-				$tile_flit_in_wr_l=$tile_flit_in_wr_l."\ttile${endp}->${ni_name}_flit_in_wr=   (VL_BITISSET_W(noc->ni_flit_out_wr,${endp})>0);\n";
-				$tile_eval=$tile_eval."\ttile${endp}->eval();\n";
-				$tile_final=$tile_final."\ttile${endp}->final();\n"; 				
-				
-				
-				foreach my $intfc (@intfcs){
-					my $key=($intfc eq 'plug:clk[0]')? 'clk' : 
-			 				 ($intfc eq 'plug:reset[0]')? 'reset':
-			 				 ($intfc eq 'plug:enable[0]')? 'en' :
-			 				 ($intfc eq 'socket:RxD_sim[0]')? 'rxd': 
-			 				 'other';
-			 			
-			 		my @ports=$soc_top->top_get_intfc_ports_list($intfc);
-					foreach my $p (@ports){
-						my($inst,$range,$type,$intfc_name,$intfc_port)= $soc_top->top_get_port($p);
-						$tile_reset=$tile_reset."\t\ttile${endp}->$p=reset;\n" if $key eq 'reset';	
-						$tile_clk=$tile_clk."\t\ttile${endp}->$p=clk;\n" if $key eq 'clk';		
-						$tile_en=$tile_en."\t\ttile${endp}->$p=enable;\n" if $key eq 'en';	;		
-						$top_port_info="$top_port_info $type  $range  tile${endp}->$p \n";
-					}#ports
-					
-					if($key eq 'rxd'){
-						my @ports=$soc_top->top_get_intfc_ports_list($intfc);
-						foreach my $p (@ports){
-							my($id,$range,$type,$intfc_name,$intfc_port)= $soc_top->top_get_port($p);
-							my @q =split  (/RxD_ready_si/,$p);
-							$rxds{$endp.$id}{p}=$q[0]  if( defined $q[1]);
-							$rxds{$endp.$id}{top}="tile$endp"  if( defined $q[1]);
-						}			
-					}
-					
-			 				
-				}#interface
-		
-				$tile_addr= $tile_addr."\ttile${endp}->${ni_name}_current_r_addr=$r_addr; // noc->er_addr[${endp}];\n";
-				$tile_addr= $tile_addr."\ttile${endp}->${ni_name}_current_e_addr=$e_addr;\n";
-						
-			}else{
-				#this tile is not connected to any ip. the noc input ports will be connected to ground
-				$tmp_reg.="\tunsigned char tmp1 [1024]={0};\n \tunsigned char tmp2 [1024]={0};";
-				$tile_chans.="\n // Tile:$endp ($e_addr)   is not assigned to any ip. Connet coresponding chan to ground.\n";
-				$tile_chans.="\ttile_chan_out[$endp] = tmp1;\n\ttile_chan_in[$endp] = tmp2;\n";
-						
-			}
-		
-	
-	}
-	
-	my ($rxd_info, $rxd_num, $rxd_wr_cal,$rxd_cap_cal, $include1)=rxd_testbench_verilator_gen (\%rxds,$dir);
-	my $include2="";
-	$include2 .= '#include "RxDsim.h" // Header file for sending charactor to UART from STDIN' if($rxd_num > 0);
-	
-	my $main_c=get_license_header("testbench.cpp");
-	
+    my $libh="";
+    my $inst= "";
+    my $newinst="";
+    
+    my $tile_addr="";
+    my $tile_flit_in="";
+    my $tile_flit_in_l="";
+    my $tile_credit="";
+    my $noc_credit="";
+    my $noc_flit_in="";
+    my $noc_flit_in_l="";    
+    my $noc_flit_in_wr="";
+    my $noc_flit_in_wr_l="";
+    my $tile_flit_in_wr="";    
+    my $tile_flit_in_wr_l="";
+    my $tile_eval="";
+    my $tile_final="";     
+    my $tile_reset="";    
+    my $tile_clk="";    
+    my $tile_en="";        
+    my $top_port_info="IO type\t  port_size\t  port_name\n";    
+    my $no_connected='';
+    my %rxds;
+    
+    my $tile_chans="";
+    my $tmp_reg='';
+    for (my $endp=0; $endp<$ne;$endp++){    
+        my $e_addr=endp_addr_encoder($mpsoc,$endp);
+        my $router_num = get_connected_router_id_to_endp($mpsoc,$endp);
+        my $r_addr=router_addr_encoder($mpsoc,$router_num);
+        my ($soc_name,$num)= $mpsoc->mpsoc_get_tile_soc_name($endp);        
+        if(defined $soc_name) {#we have a conncted tile
+        
+            #get ni instance name
+            my $ni_name;
+            my $soc=eval_soc($mpsoc,$soc_name,$tview);
+            my $soc_top=$soc->object_get_attribute('top_ip',undef);
+            my @intfcs=$soc_top->top_get_intfc_list();
+            my @instances=$soc->soc_get_all_instances();
+            foreach my $id (@instances){
+                    my $category = $soc->soc_get_category($id);
+                    if ($category eq 'NoC') {
+                        $ni_name=  $soc->soc_get_instance_name($id);
+                    }
+            }
+                $tile_chans.="\ttile_chan_out[$endp] = &tile$endp->ni_chan_out;\n\ttile_chan_in[$endp] = &tile$endp->ni_chan_in;\n";
+                $libh=$libh."#include \"Vtile${endp}.h\"\n";
+                $inst=$inst."Vtile${endp}\t*tile${endp};\t  // Instantiation of tile${endp}\n";
+                $newinst = $newinst."\ttile${endp}\t=\tnew Vtile${endp};\n"; 
+                $tile_flit_in = $tile_flit_in . "\ttile${endp}->${ni_name}_flit_in  = noc->ni_flit_out [${endp}];\n";    
+                $tile_flit_in_l = $tile_flit_in_l . "\t\ttile${endp}->${ni_name}_flit_in[j]  = noc->ni_flit_out [${endp}][j];\n";
+                $tile_credit= $tile_credit."\ttile${endp}->${ni_name}_credit_in= noc->ni_credit_out[${endp}];\n";
+                $noc_credit= $noc_credit."\tnoc->ni_credit_in[${endp}] = tile${endp}->${ni_name}_credit_out;\n";    
+                $noc_flit_in=$noc_flit_in."\tnoc->ni_flit_in [${endp}]  = tile${endp}->${ni_name}_flit_out;\n";
+                $noc_flit_in_l=$noc_flit_in_l."\t\t\tnoc->ni_flit_in [${endp}][j]  = tile${endp}->${ni_name}_flit_out[j];\n";
+                $noc_flit_in_wr= $noc_flit_in_wr."\tif(tile${endp}->${ni_name}_flit_out_wr) noc->ni_flit_in_wr = noc->ni_flit_in_wr | ((vluint64_t)1<<${endp});\n";
+                $tile_flit_in_wr=$tile_flit_in_wr."\ttile${endp}->${ni_name}_flit_in_wr= ((noc->ni_flit_out_wr >> ${endp}) & 0x01);\n";
+                $noc_flit_in_wr_l= $noc_flit_in_wr_l."\tif(tile${endp}->${ni_name}_flit_out_wr) MY_VL_SETBIT_W(noc->ni_flit_in_wr ,${endp});\n";
+                $tile_flit_in_wr_l=$tile_flit_in_wr_l."\ttile${endp}->${ni_name}_flit_in_wr=   (VL_BITISSET_W(noc->ni_flit_out_wr,${endp})>0);\n";
+                $tile_eval=$tile_eval."\ttile${endp}->eval();\n";
+                $tile_final=$tile_final."\ttile${endp}->final();\n";                 
+                foreach my $intfc (@intfcs){
+                    my $key=($intfc eq 'plug:clk[0]')? 'clk' : 
+                            ($intfc eq 'plug:reset[0]')? 'reset':
+                            ($intfc eq 'plug:enable[0]')? 'en' :
+                            ($intfc eq 'socket:RxD_sim[0]')? 'rxd': 
+                            'other';
+
+                    my @ports=$soc_top->top_get_intfc_ports_list($intfc);
+                    foreach my $p (@ports){
+                        my($inst,$range,$type,$intfc_name,$intfc_port)= $soc_top->top_get_port($p);
+                        $tile_reset=$tile_reset."\t\ttile${endp}->$p=reset;\n" if $key eq 'reset';    
+                        $tile_clk=$tile_clk."\t\ttile${endp}->$p=clk;\n" if $key eq 'clk';        
+                        $tile_en=$tile_en."\t\ttile${endp}->$p=enable;\n" if $key eq 'en';    ;        
+                        $top_port_info="$top_port_info $type  $range  tile${endp}->$p \n";
+                    }#ports
+                    
+                    if($key eq 'rxd'){
+                        my @ports=$soc_top->top_get_intfc_ports_list($intfc);
+                        foreach my $p (@ports){
+                            my($id,$range,$type,$intfc_name,$intfc_port)= $soc_top->top_get_port($p);
+                            my @q =split  (/RxD_ready_si/,$p);
+                            $rxds{$endp.$id}{p}=$q[0]  if( defined $q[1]);
+                            $rxds{$endp.$id}{top}="tile$endp"  if( defined $q[1]);
+                        }            
+                    }
+                }#interface
+                $tile_addr= $tile_addr."\ttile${endp}->${ni_name}_current_r_addr=$r_addr; // noc->er_addr[${endp}];\n";
+                $tile_addr= $tile_addr."\ttile${endp}->${ni_name}_current_e_addr=$e_addr;\n";
+            }else{
+                #this tile is not connected to any ip. the noc input ports will be connected to ground
+                $tmp_reg.="\tunsigned char tmp1 [1024]={0};\n \tunsigned char tmp2 [1024]={0};";
+                $tile_chans.="\n // Tile:$endp ($e_addr)   is not assigned to any ip. Connet coresponding chan to ground.\n";
+                $tile_chans.="\ttile_chan_out[$endp] = tmp1;\n\ttile_chan_in[$endp] = tmp2;\n";
+            }
+    }
+    my ($rxd_info, $rxd_num, $rxd_wr_cal,$rxd_cap_cal, $include1)=rxd_testbench_verilator_gen (\%rxds,$dir);
+    my $include2="";
+    $include2 .= '#include "RxDsim.h" // Header file for sending charactor to UART from STDIN' if($rxd_num > 0);
+    my $main_c=get_license_header("testbench.cpp");
 $main_c="$main_c
 #include <stdlib.h>
 #include <stdio.h>
@@ -2704,14 +2196,14 @@ sub gen_verilator_mpsoc_testbench {
 #define CHAN_SIZE   sizeof(tile0->ni_chan_in)
 
 #define conect_r2r(T1,r1,p1,T2,r2,p2)  \\
-	memcpy(&router##T1 [r1]->chan_in[p1] , &router##T2 [r2]->chan_out[p2], CHAN_SIZE )
+    memcpy(&router##T1 [r1]->chan_in[p1] , &router##T2 [r2]->chan_out[p2], CHAN_SIZE )
 
 #define connect_r2gnd(T,r,p)\\
-	memset(&router##T [r]->chan_in [p],0x00,CHAN_SIZE)
+    memset(&router##T [r]->chan_in [p],0x00,CHAN_SIZE)
 
 #define connect_r2e(T,r,p,e) \\
-	memcpy(&router##T [r]->chan_in[p], tile_chan_out[e], CHAN_SIZE );\\
-	memcpy(tile_chan_in[e], &router##T [r]->chan_out[p], CHAN_SIZE )
+    memcpy(&router##T [r]->chan_in[p], tile_chan_out[e], CHAN_SIZE );\\
+    memcpy(tile_chan_in[e], &router##T [r]->chan_out[p], CHAN_SIZE )
 
 
 
@@ -2728,291 +2220,253 @@ sub gen_verilator_mpsoc_testbench {
 
 
 void connect_clk_reset_en_all(void){
-	//clk,reset,enable
+    //clk,reset,enable
 $tile_reset
-$tile_clk		
+$tile_clk        
 $tile_en
-	connect_routers_reset_clk();	
+    connect_routers_reset_clk();    
 }
 
 void sim_eval_all(void){
-   	routers_eval();
+        routers_eval();
 $tile_eval
 }
 
 void sim_final_all(void ){
-	routers_final();	
-$tile_final	
-}	
+    routers_final();    
+$tile_final    
+}    
 
 void clk_posedge_event(void) {
 
-	clk = 1;       // Toggle clock
-	// you can change the inputs and read the outputs here in case they are captured at posedge of clock 
-	$rxd_wr_cal	
-	connect_clk_reset_en_all();
-	sim_eval_all();
+    clk = 1;       // Toggle clock
+    // you can change the inputs and read the outputs here in case they are captured at posedge of clock 
+    $rxd_wr_cal    
+    connect_clk_reset_en_all();
+    sim_eval_all();
 }
 
 
 void clk_negedge_event(void){
 
-	clk = 0;
-	topology_connect_all_nodes ();
-	connect_clk_reset_en_all();
-	sim_eval_all();	
-}	
+    clk = 0;
+    topology_connect_all_nodes ();
+    connect_clk_reset_en_all();
+    sim_eval_all();    
+}    
 
 
 int main(int argc, char** argv) {
-	int i,j,x,y;
-	$rxd_info
-	Verilated::commandArgs(argc, argv);   // Remember args
-	Vrouter_new();             // Create instance
-	
+    int i,j,x,y;
+    $rxd_info
+    Verilated::commandArgs(argc, argv);   // Remember args
+    Vrouter_new();             // Create instance
+    
 $newinst
-	
-	/********************
-	*	initialize input
-	*********************/
-	$tile_chans
-	
-	reset=1;
-	enable=1;
-	topology_init();
-	
-	$no_connected
-	
+    
+    /********************
+    *    initialize input
+    *********************/
+    $tile_chans
+    
+    reset=1;
+    enable=1;
+    topology_init();
+    
+    $no_connected
+    
 $tile_addr
 
 
-	main_time=0;
-	printf(\"Start Simulation\\n\");
-	while (!Verilated::gotFinish()) {
-	    $rxd_cap_cal
-	    if ((main_time & 0x3FF)==0) fflush(stdout); // fflush \$dispaly command each 1024 clock cycle 
-		if (main_time >= 10 ) 	reset=0;
-		
-		clk_posedge_event( );
-		//The valus of all registers and input ports valuse change @ posedge of the clock. Once clk is deasserted,  as multiple modules are connected inside the testbench we need several eval for propogating combinational logic values 
-		//between modules when the clock . 
-		for (i=0;i<2*(SMART_MAX+1);i++) clk_negedge_event( );
-
-		main_time++;  
-	}//while
-	
-	// Simulation is done
-	sim_final_all();
+    main_time=0;
+    printf(\"Start Simulation\\n\");
+    while (!Verilated::gotFinish()) {
+        $rxd_cap_cal
+        if ((main_time & 0x3FF)==0) fflush(stdout); // fflush \$dispaly command each 1024 clock cycle 
+        if (main_time >= 10 )     reset=0;
+        
+        clk_posedge_event( );
+        //The valus of all registers and input ports valuse change @ posedge of the clock. Once clk is deasserted,  as multiple modules are connected inside the testbench we need several eval for propogating combinational logic values 
+        //between modules when the clock . 
+        for (i=0;i<2*(SMART_MAX+1);i++) clk_negedge_event( );
+
+        main_time++;  
+    }//while
+    
+    // Simulation is done
+    sim_final_all();
 }
 
 double sc_time_stamp () {       // Called by \$time in Verilog
-	return main_time;
+    return main_time;
 }
-			
+
 
 ";
 
-	save_file("$dir/parameter.h",$parameter_h);	
-	save_file("$dir/testbench.cpp",$main_c);	
+    save_file("$dir/parameter.h",$parameter_h);    
+    save_file("$dir/testbench.cpp",$main_c);    
 
 }
 
-
-
 sub soc_get_all_parameters {
-	my $soc=shift;	
-	my @instances=$soc->soc_get_all_instances();
-	
-	my %all_param; 
-	foreach my $id (@instances){
-		
-		my $module 	=$soc->soc_get_module($id);
-		my $category 	=$soc->soc_get_category($id);	
-		my $inst   	= $soc->soc_get_instance_name($id);
-		my %params	= $soc->soc_get_module_param($id);
-		my %params_type	= $soc->soc_get_module_param_type($id);
-		my $ip = ip->lib_new ();		
-		my @param_order=$soc->soc_get_instance_param_order($id);
-			
-		foreach my $p (sort keys %params){
-			my $inst_param= "$inst\_$p";
-			#add instance name to parameter value
-			$params{$p}=add_instantc_name_to_parameters(\%params,$inst,$params{$p});
-			my ($default,$type,$content,$info,$vfile_param_type,$redefine_param)= $ip->ip_get_parameter($category,$module,$p);
-			
-			$vfile_param_type= "Don't include" if (!defined $vfile_param_type );
-			if ($vfile_param_type eq "Localparam"){
-				my $type = $params_type{$p};
-				$type = "Localparam" if (! defined $type);	
-				$vfile_param_type = ($type eq 'Parameter')?  "Parameter" : "Localparam";
-			}
-						
-			#$vfile_param_type= "Parameter"  if ($vfile_param_type eq 1);
-			#$vfile_param_type= "Localparam" if ($vfile_param_type eq 0);		
-			$all_param{ $inst_param} = 	$params{ $p} if($vfile_param_type eq "Parameter" || $vfile_param_type eq "Localparam"  );	
-			#print"$all_param{ $inst_param} = 	$params{ $p} if($vfile_param_type eq \"Parameter\" || $vfile_param_type eq \"Localparam\"  );	\n";	
-		}
-	}
-	return %all_param;
+    my $soc=shift;    
+    my @instances=$soc->soc_get_all_instances();
+    my %all_param; 
+    foreach my $id (@instances){
+        
+        my $module     =$soc->soc_get_module($id);
+        my $category     =$soc->soc_get_category($id);    
+        my $inst       = $soc->soc_get_instance_name($id);
+        my %params    = $soc->soc_get_module_param($id);
+        my %params_type    = $soc->soc_get_module_param_type($id);
+        my $ip = ip->lib_new ();        
+        my @param_order=$soc->soc_get_instance_param_order($id);
+        foreach my $p (sort keys %params){
+            my $inst_param= "$inst\_$p";
+            #add instance name to parameter value
+            $params{$p}=add_instantc_name_to_parameters(\%params,$inst,$params{$p});
+            my ($default,$type,$content,$info,$vfile_param_type,$redefine_param)= $ip->ip_get_parameter($category,$module,$p);
+            
+            $vfile_param_type= "Don't include" if (!defined $vfile_param_type );
+            if ($vfile_param_type eq "Localparam"){
+                my $type = $params_type{$p};
+                $type = "Localparam" if (! defined $type);    
+                $vfile_param_type = ($type eq 'Parameter')?  "Parameter" : "Localparam";
+            }
+            #$vfile_param_type= "Parameter"  if ($vfile_param_type eq 1);
+            #$vfile_param_type= "Localparam" if ($vfile_param_type eq 0);        
+            $all_param{ $inst_param} =     $params{ $p} if($vfile_param_type eq "Parameter" || $vfile_param_type eq "Localparam"  );    
+            #print"$all_param{ $inst_param} =     $params{ $p} if($vfile_param_type eq \"Parameter\" || $vfile_param_type eq \"Localparam\"  );    \n";    
+        }
+    }
+    return %all_param;
 }
 
 sub soc_get_all_parameters_order {
-	my $soc=shift;	
-	my @instances=$soc->soc_get_all_instances();
-	my $ip = ip->lib_new ();		
-	my @all_order; 
-	foreach my $id (@instances){
-		my $module 	=$soc->soc_get_module($id);
-		my $category 	=$soc->soc_get_category($id);	
-		my $inst   	= $soc->soc_get_instance_name($id);
-		my @order	= $soc->soc_get_instance_param_order($id);
-		my %params_type	= $soc->soc_get_module_param_type($id);
-		foreach my $p ( @order){
-			my $inst_param= "$inst\_$p";
-			my ($default,$type,$content,$info,$vfile_param_type,$redefine_param)= $ip->ip_get_parameter($category,$module,$p);
-			$vfile_param_type= "Don't include" if (!defined $vfile_param_type );
-			if ($vfile_param_type eq "Localparam"){
-				my $type = $params_type{$p};
-				$type = "Localparam" if (! defined $type);	
-				$vfile_param_type = ($type eq 'Parameter')?  "Parameter" : "Localparam";
-			}
-			#$vfile_param_type= "Parameter"  if ($vfile_param_type eq 1);
-			#$vfile_param_type= "Localparam" if ($vfile_param_type eq 0);		
-			push(@all_order, $inst_param) if($vfile_param_type eq "Parameter" || $vfile_param_type eq "Localparam"  );				
-		}
-	}
-	return @all_order;
+    my $soc=shift;    
+    my @instances=$soc->soc_get_all_instances();
+    my $ip = ip->lib_new ();        
+    my @all_order; 
+    foreach my $id (@instances){
+        my $module     =$soc->soc_get_module($id);
+        my $category     =$soc->soc_get_category($id);    
+        my $inst       = $soc->soc_get_instance_name($id);
+        my @order    = $soc->soc_get_instance_param_order($id);
+        my %params_type    = $soc->soc_get_module_param_type($id);
+        foreach my $p ( @order){
+            my $inst_param= "$inst\_$p";
+            my ($default,$type,$content,$info,$vfile_param_type,$redefine_param)= $ip->ip_get_parameter($category,$module,$p);
+            $vfile_param_type= "Don't include" if (!defined $vfile_param_type );
+            if ($vfile_param_type eq "Localparam"){
+                my $type = $params_type{$p};
+                $type = "Localparam" if (! defined $type);    
+                $vfile_param_type = ($type eq 'Parameter')?  "Parameter" : "Localparam";
+            }
+            #$vfile_param_type= "Parameter"  if ($vfile_param_type eq 1);
+            #$vfile_param_type= "Localparam" if ($vfile_param_type eq 0);        
+            push(@all_order, $inst_param) if($vfile_param_type eq "Parameter" || $vfile_param_type eq "Localparam"  );                
+        }
+    }
+    return @all_order;
 }
 
-
-
 sub gen_modelsim_soc_testbench {
-	my ($self,$name,$top,$target_dir,$tview)=@_;
-	my $dir="$target_dir/Modelsim";
-	my $soc_top= $self->object_get_attribute('top_ip',undef);
-	
-	my @intfcs=$soc_top->top_get_intfc_list();
-	my %PP;
-	my $top_port_def="// ${name}.v IO definition \n";
-	my $pin_assign;
-	my $rst_inputs='';
-
-	
-	
-	
-	#add functions
-	my $project_dir	  = get_project_dir();
-	open my $file1, "<", "$project_dir/mpsoc/perl_gui/lib/verilog/functions.v" or die;
-	my $functions_all='';
-	while (my $f1 = readline ($file1)) {	
-		 $functions_all="$functions_all $f1 ";
-	}
-	close($file1);
-	
-	#get parameters
-	my $params_v="";
-	my $n= $self->object_get_attribute('soc_name',undef);
-	
-	if(defined $n){	#we are compiling a single tile as SoC
-		my $core_id= $self->object_get_attribute('global_param','CORE_ID');
-		my $sw_loc = $self->object_get_attribute('global_param','SW_LOC');	
-	
-			$params_v="\tlocalparam\tCORE_ID=$core_id;
+    my ($self,$name,$top,$target_dir,$tview)=@_;
+    my $dir="$target_dir/Modelsim";
+    my $soc_top= $self->object_get_attribute('top_ip',undef);
+    my @intfcs=$soc_top->top_get_intfc_list();
+    my %PP;
+    my $top_port_def="// ${name}.v IO definition \n";
+    my $pin_assign;
+    my $rst_inputs='';
+    #add functions
+    my $project_dir      = get_project_dir();
+    open my $file1, "<", "$project_dir/mpsoc/perl_gui/lib/verilog/functions.v" or die;
+    my $functions_all='';
+    while (my $f1 = readline ($file1)) {    
+        $functions_all="$functions_all $f1 ";
+    }
+    close($file1);
+    #get parameters
+    my $params_v="";
+    my $n= $self->object_get_attribute('soc_name',undef);
+    if(defined $n){    #we are compiling a single tile as SoC
+        my $core_id= $self->object_get_attribute('global_param','CORE_ID');
+        my $sw_loc = $self->object_get_attribute('global_param','SW_LOC');    
+    
+            $params_v="\tlocalparam\tCORE_ID=$core_id;
 \tlocalparam\tSW_LOC=\"$sw_loc\";\n";
-		my %params=soc_get_all_parameters($self);
-		my @order= soc_get_all_parameters_order($self);		
-		foreach my $p (@order){
-			add_text_to_string(\$params_v,"\tlocalparam  $p = $params{$p};\n") if(defined $params{$p} );			
-		}
-	}else{ # we are simulating a mpsoc
-		$params_v= gen_socs_param($self);		
-		
-		
-	}
-
-	foreach my $intfc (@intfcs){
-		my $key= ( $intfc eq 'plug:clk[0]')? 'clk' : 
-			 ( $intfc eq 'plug:reset[0]')? 'reset':
-			 ( $intfc eq 'plug:enable[0]')? 'en' : 'other';
-		my $key1="${key}1";
-		my $key0="${key}0";
-
-		my @ports=$soc_top->top_get_intfc_ports_list($intfc);
-		my $f=1;
-		foreach my $p (@ports){
-			my($inst,$range,$type,$intfc_name,$intfc_port)= $soc_top->top_get_port($p);
-			
-			$PP{$key1}= (defined $PP{$key1})? "$PP{$key1} $p=1;\n" : "$p=1;\n";
-			$PP{$key0}= (defined $PP{$key0})? "$PP{$key0} $p=0;\n" : "$p=0;\n";	
-
-
-			if  (length($range)!=0){	
-#				#replace parameter with their values		#
-#				my @a= split (/\b/,$range);
-#				print "a=@a\n";
-#				foreach my $l (@a){
-#					my $value=$params{$l};
-#					if(defined $value){
-#						chomp $value;
-#						($range=$range)=~ s/\b$l\b/$value/g      if(defined $params{$l});
-#						print "($range=$range)=~ s/\b$l\b/$value/g      if(defined $params{$l}); \n";
-#					}
-#				}
-				$range = "[ $range ]" ;
-			}	
-
-
-
-
-
-			if($type eq 'input'){
-				$top_port_def="$top_port_def  reg  $range  $p;\n" 
-			}else{
-				$top_port_def="$top_port_def  wire  $range  $p;\n" 
-			}
-			
-			
-			
-			
-			
-			
-			
-			
-			$pin_assign=(defined $pin_assign)? "$pin_assign,\n\t\t.$p($p)":  "\t\t.$p($p)";
-			$rst_inputs= "$rst_inputs $p=0;\n" if ($key eq 'other' && $type eq 'input' );
-		}
-		
-
-	}
-my $global_localparam=get_golal_param_v();	
+        my %params=soc_get_all_parameters($self);
+        my @order= soc_get_all_parameters_order($self);        
+        foreach my $p (@order){
+            add_text_to_string(\$params_v,"\tlocalparam  $p = $params{$p};\n") if(defined $params{$p} );            
+        }
+    }else{ # we are simulating a mpsoc
+        $params_v= gen_socs_param($self);        
+    }
+    foreach my $intfc (@intfcs){
+        my $key= ( $intfc eq 'plug:clk[0]')? 'clk' : 
+            ( $intfc eq 'plug:reset[0]')? 'reset':
+            ( $intfc eq 'plug:enable[0]')? 'en' : 'other';
+        my $key1="${key}1";
+        my $key0="${key}0";
+        my @ports=$soc_top->top_get_intfc_ports_list($intfc);
+        my $f=1;
+        foreach my $p (@ports){
+            my($inst,$range,$type,$intfc_name,$intfc_port)= $soc_top->top_get_port($p);
+            
+            $PP{$key1}= (defined $PP{$key1})? "$PP{$key1} $p=1;\n" : "$p=1;\n";
+            $PP{$key0}= (defined $PP{$key0})? "$PP{$key0} $p=0;\n" : "$p=0;\n";    
+            if  (length($range)!=0){    
+#                #replace parameter with their values        #
+#                my @a= split (/\b/,$range);
+#                print "a=@a\n";
+#                foreach my $l (@a){
+#                    my $value=$params{$l};
+#                    if(defined $value){
+#                        chomp $value;
+#                        ($range=$range)=~ s/\b$l\b/$value/g      if(defined $params{$l});
+#                        print "($range=$range)=~ s/\b$l\b/$value/g      if(defined $params{$l}); \n";
+#                    }
+#                }
+                $range = "[ $range ]" ;
+            }    
+            if($type eq 'input'){
+                $top_port_def="$top_port_def  reg  $range  $p;\n" 
+            }else{
+                $top_port_def="$top_port_def  wire  $range  $p;\n" 
+            }
+            $pin_assign=(defined $pin_assign)? "$pin_assign,\n\t\t.$p($p)":  "\t\t.$p($p)";
+            $rst_inputs= "$rst_inputs $p=0;\n" if ($key eq 'other' && $type eq 'input' );
+        }
+    }
+my $global_localparam=get_golal_param_v();    
 my $test_v= get_license_header("testbench.v");
 
 my $mpsoc_name=$self->object_get_attribute('mpsoc_name');
 #if(defined $mpsoc_name){
-	if(0){
-	
-	
-	my $top_ip=ip_gen->top_gen_new();
-	my $target_dir  = "$ENV{'PRONOC_WORK'}/MPSOC/$mpsoc_name";
+    if(0){
+    my $top_ip=ip_gen->top_gen_new();
+    my $target_dir  = "$ENV{'PRONOC_WORK'}/MPSOC/$mpsoc_name";
     my $hw_dir     = "$target_dir/src_verilog";
     my $sw_dir     = "$target_dir/sw";
-	my ($socs_v,$io_short,$io_full,$top_io_short,$top_io_full,$top_io_pass,$href)=gen_socs_v($self,$top_ip,$sw_dir,$tview);
-	my $socs_param= gen_socs_param($self);
-	my $global_localparam=get_golal_param_v();
-	my ($clk_set, $clk_io_sim,$clk_io_full, $clk_assigned_port)= get_top_clk_setting($self);
-  
-	
+    my ($socs_v,$io_short,$io_full,$top_io_short,$top_io_full,$top_io_pass,$href)=gen_socs_v($self,$top_ip,$sw_dir,$tview);
+    my $socs_param= gen_socs_param($self);
+    my $global_localparam=get_golal_param_v();
+    my ($clk_set, $clk_io_sim,$clk_io_full, $clk_assigned_port)= get_top_clk_setting($self);
+
 $test_v.="
 
 $clk_set, $clk_io_sim,$clk_io_full, $clk_assigned_port
 
-`timescale	 1ns/1ps
+`timescale     1ns/1ps
 
 module testbench;
 
 $functions_all
 
-$global_localparam	
+$global_localparam    
 
 $socs_param
 
@@ -3029,45 +2483,45 @@ sub gen_modelsim_soc_testbench {
 
 }
 
-$test_v	="$test_v
+$test_v    ="$test_v
 
-`timescale	 1ns/1ps
+`timescale     1ns/1ps
 
 module testbench;
 
 $functions_all
 
 $global_localparam
-	
+    
 $params_v
 
 $top_port_def
 
 
-	$name uut (
+    $name uut (
 $pin_assign
-	);
+    );
 
 //clock defination
 initial begin 
-	forever begin 
-	#5 $PP{clk0}
-	#5 $PP{clk1}
-	end	
+    forever begin 
+    #5 $PP{clk0}
+    #5 $PP{clk1}
+    end    
 end
 
 
 
 initial begin 
-	// reset $name module at the start up
-	$PP{reset1}	
-	$PP{en1}
-	$rst_inputs
-	// deasert the reset after 200 ns
-	#200
-	$PP{reset0}  
+    // reset $name module at the start up
+    $PP{reset1}    
+    $PP{en1}
+    $rst_inputs
+    // deasert the reset after 200 ns
+    #200
+    $PP{reset0}  
 
-	// write your testbench here
+    // write your testbench here
 
 
 
@@ -3076,136 +2530,100 @@ sub gen_modelsim_soc_testbench {
 
 endmodule
 ";
-	save_file("$dir/testbench.v",$test_v);
+    save_file("$dir/testbench.v",$test_v);
 
-	
+    
 
 }
 
 sub verilator_testbench{
-	my ($self,$name,$top,$target_dir,$vendor)=@_;
-	my $verilator="$target_dir/verilator";
-	my $dir="$verilator";
-	
-	my ($app,$table,$tview,$window) = software_main($dir,'testbench.cpp');
-	
-	my $n= $self->object_get_attribute('soc_name',undef);
-	if(defined $n){	#we are compiling a single tile as SoC
-		gen_verilator_soc_testbench (@_) if((-f "$dir/testbench.cpp")==0); 		
-	}
-	else { # we are compiling a complete NoC-based mpsoc
-		gen_verilator_mpsoc_testbench (@_,$tview) if((-f "$dir/testbench.cpp")==0); 		
-	
-	}
-	
-	#copy makefile
-	#copy("../script/verilator_soc_make", "$verilator/obj_dir/Makefile"); 
-	
-
-	
-
-
-	my $make = def_image_button('icons/gen.png','Compile');
-	my $regen=def_image_button('icons/refresh.png','Regenerate Testbench.cpp');	
-	my $run = def_image_button('icons/run.png','Run');
-	my $back=def_image_button('icons/left.png','Previous');	
-	
-	
-	
-	$table->attach ($back,1,2,1,2,'shrink','shrink',0,0);
-	$table->attach ($regen,3,4,1,2,'shrink','shrink',0,0);
-	$table->attach ($make,6, 7, 1,2,'shrink','shrink',0,0);	
-	$table->attach ($run,9, 10, 1,2,'shrink','shrink',0,0);
-
-	$back-> signal_connect("clicked" => sub{ 
-		
-		$window->destroy;
-		verilator_compilation_win($self,$name,$top,$target_dir,$vendor);
-		
-	});
-
-	$regen-> signal_connect("clicked" => sub{
-		my $response = yes_no_dialog("Are you sure you want to regenerate the testbench.cpp file? Note that any changes you have made will be lost");
-  		if ($response eq 'yes') {
-  			my $n= $self->object_get_attribute('soc_name',undef);
-			if(defined $n){	#we are compiling a single tile as SoC
-				gen_verilator_soc_testbench ($self,$name,$top,$target_dir); 		
-			}
-			else { # we are compiling a complete NoC-based mpsoc
-				gen_verilator_mpsoc_testbench ($self,$name,$top,$target_dir,$tview); 		
-	
-			}
-  			      			
-			$app->refresh_source("$dir/testbench.cpp");	
-  		}	
-	});
-	
-	
-	$make -> signal_connect("clicked" => sub{
-		$make->hide;
-		my $load= show_gif("icons/load.gif");
-		$table->attach ($load,8, 9, 1,2,'shrink','shrink',0,0);
-		$table->show_all;
-		$app->ask_to_save_changes();
-		copy("$dir/testbench.cpp", "$verilator/obj_dir/testbench.cpp"); 
-		copy("$dir/parameter.h", "$verilator/obj_dir/parameter.h") if(-f "$dir/parameter.h"); 
-		copy("$dir/RxDsim.h", "$verilator/obj_dir/RxDsim.h") if(-f "$dir/RxDsim.h");
-		
-		my $tops_ref=$self->object_get_attribute('verilator','libs');
-		my %tops=%{$tops_ref};
-		my $lib_num=0;
-		my $cpu_num = $self->object_get_attribute('compile', 'cpu_num');
-		$cpu_num = 1 if (!defined $cpu_num);
-		add_colored_info($tview,"Makefie will use the maximum number of $cpu_num core(s) in parallel for compilation\n",'green');
-		my $length=scalar (keys %tops);
-		my $cmd="";
-		foreach my $top (sort keys %tops) { 
-			$cmd.= "lib$lib_num & ";
-			$lib_num++;				
-			if( $lib_num % $cpu_num == 0 || $lib_num == $length){
-				$cmd.="wait\n";
-				run_make_file("$verilator/obj_dir/",$tview,$cmd);	
-				$cmd="";
-			}else {
-				$cmd.=" make ";
-			}	
-		}
-		
-		
-		#foreach my $top (sort keys %tops) { 
-		#		run_make_file("$verilator/obj_dir/",$tview,"lib$lib_num");	
-		#		$lib_num++;
-		#}
-		
-		
-		
-		run_make_file("$verilator/obj_dir/",$tview,"sim");	
-		$load->destroy;
-		$make->show_all;
-		
-	});
-
-	$run -> signal_connect("clicked" => sub{
-		my $bin="$verilator/obj_dir/testbench";
-		if (-f $bin){
-			my $cmd= "cd \"$verilator/obj_dir/\" \n xterm -e bash -c \"$bin; sleep 5\"";
-			add_info($tview,"$cmd\n");	
-			my ($stdout,$exit,$stderr)=run_cmd_in_back_ground_get_stdout($cmd);
-			if(length $stderr>1){			
-				add_colored_info($tview,"$stderr\n",'red');
-			}else {
-				add_info($tview,"$stdout\n");
-			}			
-
-		}else{
-			add_colored_info($tview,"Cannot find $bin executable binary file! make sure you have compiled the testbench successfully\n", 'red')
-		}	
-	
-		});
-
-
+    my ($self,$name,$top,$target_dir,$vendor)=@_;
+    my $verilator="$target_dir/verilator";
+    my $dir="$verilator";
+    
+    my ($app,$table,$tview,$window) = software_main($dir,'testbench.cpp');
+    
+    my $n= $self->object_get_attribute('soc_name',undef);
+    if(defined $n){    #we are compiling a single tile as SoC
+        gen_verilator_soc_testbench (@_) if((-f "$dir/testbench.cpp")==0);         
+    }
+    else { # we are compiling a complete NoC-based mpsoc
+        gen_verilator_mpsoc_testbench (@_,$tview) if((-f "$dir/testbench.cpp")==0);         
+    }
+    #copy makefile
+    #copy("../script/verilator_soc_make", "$verilator/obj_dir/Makefile"); 
+    my $make = def_image_button('icons/gen.png','Compile');
+    my $regen=def_image_button('icons/refresh.png','Regenerate Testbench.cpp');    
+    my $run = def_image_button('icons/run.png','Run');
+    my $back=def_image_button('icons/left.png','Previous');    
+    $table->attach ($back,1,2,1,2,'shrink','shrink',0,0);
+    $table->attach ($regen,3,4,1,2,'shrink','shrink',0,0);
+    $table->attach ($make,6, 7, 1,2,'shrink','shrink',0,0);    
+    $table->attach ($run,9, 10, 1,2,'shrink','shrink',0,0);
+    $back-> signal_connect("clicked" => sub{ 
+        $window->destroy;
+        verilator_compilation_win($self,$name,$top,$target_dir,$vendor);
+    });
+    $regen-> signal_connect("clicked" => sub{
+        my $response = yes_no_dialog("Are you sure you want to regenerate the testbench.cpp file? Note that any changes you have made will be lost");
+        if ($response eq 'yes') {
+            my $n= $self->object_get_attribute('soc_name',undef);
+            if(defined $n){    #we are compiling a single tile as SoC
+                gen_verilator_soc_testbench ($self,$name,$top,$target_dir);         
+            }
+            else { # we are compiling a complete NoC-based mpsoc
+                gen_verilator_mpsoc_testbench ($self,$name,$top,$target_dir,$tview);         
+            }
+            $app->refresh_source("$dir/testbench.cpp");    
+        }    
+    });
+    $make -> signal_connect("clicked" => sub{
+        $make->hide;
+        my $load= show_gif("icons/load.gif");
+        $table->attach ($load,8, 9, 1,2,'shrink','shrink',0,0);
+        $table->show_all;
+        $app->ask_to_save_changes();
+        copy("$dir/testbench.cpp", "$verilator/obj_dir/testbench.cpp"); 
+        copy("$dir/parameter.h", "$verilator/obj_dir/parameter.h") if(-f "$dir/parameter.h"); 
+        copy("$dir/RxDsim.h", "$verilator/obj_dir/RxDsim.h") if(-f "$dir/RxDsim.h");
+        my $tops_ref=$self->object_get_attribute('verilator','libs');
+        my %tops=%{$tops_ref};
+        my $lib_num=0;
+        my $cpu_num = $self->object_get_attribute('compile', 'cpu_num');
+        $cpu_num = 1 if (!defined $cpu_num);
+        add_colored_info($tview,"Makefie will use the maximum number of $cpu_num core(s) in parallel for compilation\n",'green');
+        my $length=scalar (keys %tops);
+        my $cmd="";
+        foreach my $top (sort keys %tops) { 
+            $cmd.= "lib$lib_num & ";
+            $lib_num++;                
+            if( $lib_num % $cpu_num == 0 || $lib_num == $length){
+                $cmd.="wait\n";
+                run_make_file("$verilator/obj_dir/",$tview,$cmd);    
+                $cmd="";
+            }else {
+                $cmd.=" make ";
+            }    
+        }
+        run_make_file("$verilator/obj_dir/",$tview,"sim");    
+        $load->destroy;
+        $make->show_all;
+        
+    });
+    $run -> signal_connect("clicked" => sub{
+        my $bin="$verilator/obj_dir/testbench";
+        if (-f $bin){
+            my $cmd= "cd \"$verilator/obj_dir/\" \n xterm -e bash -c \"$bin; sleep 5\"";
+            add_info($tview,"$cmd\n");    
+            my ($stdout,$exit,$stderr)=run_cmd_in_back_ground_get_stdout($cmd);
+            if(length $stderr>1){            
+                add_colored_info($tview,"$stderr\n",'red');
+            }else {
+                add_info($tview,"$stdout\n");
+            }
+        }else{
+            add_colored_info($tview,"Cannot find $bin executable binary file! make sure you have compiled the testbench successfully\n", 'red')
+        }
+    });
 }
-
-
-
 1;
diff --git a/mpsoc/perl_gui/lib/perl/diagram.pl b/mpsoc/perl_gui/lib/perl/diagram.pl
index 5670c28..d6194e6 100644
--- a/mpsoc/perl_gui/lib/perl/diagram.pl
+++ b/mpsoc/perl_gui/lib/perl/diagram.pl
@@ -2,1407 +2,1181 @@
 use constant::boolean;
 use strict;
 use warnings;
-
 use FindBin;
 use lib $FindBin::Bin;
-
 use soc;
 require "widget.pl"; 
 require "emulator.pl";
 use File::Copy;
-
 use Chart::Gnuplot;
 
 
 sub get_dot_file{
-	my $self= shift;
-	my $self_name=$self->object_get_attribute('soc_name');
-	my $remove_clk = $self->object_get_attribute("tile_diagram","show_clk");
-	my $remove_reset = $self->object_get_attribute("tile_diagram","show_reset");
-	my $remove_unused = $self->object_get_attribute("tile_diagram","show_unused");
-
-	my $dotfile=
+    my $self= shift;
+    my $self_name=$self->object_get_attribute('soc_name');
+    my $remove_clk = $self->object_get_attribute("tile_diagram","show_clk");
+    my $remove_reset = $self->object_get_attribute("tile_diagram","show_reset");
+    my $remove_unused = $self->object_get_attribute("tile_diagram","show_unused");
+    my $dotfile=
 "digraph G {
-	graph [rankdir = LR , splines=polyline, overlap = false]; 
-	node[shape=record];
+    graph [rankdir = LR , splines=polyline, overlap = false]; 
+    node[shape=record];
 ";
-
-	my @all_instances=$self->soc_get_all_instances();
-	#print "@all_instances\n";
-	my $graph_connect= '';
-	my $n=0;
-	#my %socket_color;
-	foreach my $instance_id (@all_instances){
-		my $first=1;
-		my $instance_name=$self->soc_get_instance_name($instance_id);
-		$dotfile="$dotfile \n\t$instance_id \[label=\"{  ";
-		
-		my @sockets= $self->soc_get_all_sockets_of_an_instance($instance_id);
-		@sockets = remove_scolar_from_array(\@sockets,'clk') if ($remove_clk);
-		@sockets = remove_scolar_from_array(\@sockets,'reset') if ($remove_reset);
-		
-
-		foreach my $socket (@sockets){
-
-			my @nums=$self->soc_list_socket_nums($instance_id,$socket);
-			foreach my $num (@nums){
-				my $name= $self->soc_get_socket_name ($instance_id,$socket,$num);
-				my  ($s_type,$s_value,$s_connection_num)=$self->soc_get_socket_of_instance($instance_id,$socket);
-				my $v=(defined $s_value) ? $self->soc_get_module_param_value($instance_id,$s_value) : 1;
-				$v=1 if ( length( $v || '' ) ==0);
-				#for(my $i=$v-1; $i>=0; $i--) {
-				for(my $i=0; $i<$v; $i++) {
-					#$socket_color{socket_${socket}\_$i}=$n;
-					#$n = ($n<30)? $n+1 : 0;
-					my ($ref1,$ref2)= $self->soc_get_modules_plug_connected_to_socket($instance_id,$socket,$i);
-					my %connected_plugs=%$ref1;
-					my %connected_plug_nums=%$ref2;
-					if(%connected_plugs || $remove_unused==0){ 
-						$dotfile= ($first)? "$dotfile\{<socket_${socket}\_$i>$name\_$i" : "$dotfile |<socket_${socket}_${i}>$name\_${i}";
-						$first=0;
-					}
-				}
-				
-			}
-		}	
-		
-		
-		$dotfile=($first)? "$dotfile $instance_name"  : "$dotfile}|$instance_name";
-		$first=1;
-		my @plugs= $self->soc_get_all_plugs_of_an_instance($instance_id);
-		@plugs = remove_scolar_from_array(\@plugs,'clk') if ($remove_clk);
-		@plugs = remove_scolar_from_array(\@plugs,'reset') if ($remove_reset);
-
-		my %plug_order;
-		my @noconnect;
-		foreach my $plug (@plugs){
-			
-			my @nums=$self->soc_list_plug_nums($instance_id,$plug);
-			foreach my $num (@nums){
-				my ($addr,$base,$end,$name,$connect_id,$connect_socket,$connect_socket_num)=$self->soc_get_plug($instance_id,$plug,$num);
-				
-				if(defined $connect_socket || $remove_unused==0){ 
-					#$dotfile= ($first)?  "$dotfile |{<plug_${plug}_${num}>$name" :  "$dotfile|<plug_${plug}_${num}>$name";
-					if(defined $connect_id && defined $connect_socket){
-						my @sockets= $self->soc_get_all_sockets_of_an_instance($connect_id);
-						my $order_val=0;
-						my $s1=get_pos($connect_id, @all_instances);
-						my $s2=get_pos($connect_socket,  @sockets);
-						$order_val=$s1*1000000+$s2*10000+$connect_socket_num;
-						$plug_order{$order_val}=  "<plug_${plug}_${num}>$name";
-					}else {push (@noconnect,"<plug_${plug}_${num}>$name");}
-				}
-				
-
-				#my $connect_name=$self->soc_get_instance_name($connect_id);
-				#my $color = get_color_hex_string($n);
-				#$n = ($n<30)? $n+1 : 0;
-				
-				$graph_connect="$graph_connect $instance_id:plug_${plug}_${num} ->  $connect_id:socket_${connect_socket}_${connect_socket_num} [  dir=none]\n" if(defined $connect_socket);
-				
-			}
-		}
-		foreach my $p (sort {$a<=>$b} keys %plug_order){
-					my $k=$plug_order{$p};
-					#print "$instance_name   : $k=\$plug_order{$p}\n";
-					$dotfile= ($first) ?   "$dotfile |{ ${k}": "$dotfile |${k}";
-					$first=0;
-
-				}
-
-		foreach my $k (@noconnect){
-			$dotfile= ($first) ?   "$dotfile |{ ${k}": "$dotfile |${k}";
-			$first=0;
-		}
-
-		$dotfile=  "$dotfile} }\"];";
-
-		
-	
-	}
-	$dotfile="$dotfile\n\n$graph_connect";
-	$dotfile="$dotfile\n\n}\n";
-
-
-	return $dotfile;
-
-
+    my @all_instances=$self->soc_get_all_instances();
+    #print "@all_instances\n";
+    my $graph_connect= '';
+    my $n=0;
+    #my %socket_color;
+    foreach my $instance_id (@all_instances){
+        my $first=1;
+        my $instance_name=$self->soc_get_instance_name($instance_id);
+        $dotfile="$dotfile \n\t$instance_id \[label=\"{  ";
+        
+        my @sockets= $self->soc_get_all_sockets_of_an_instance($instance_id);
+        @sockets = remove_scolar_from_array(\@sockets,'clk') if ($remove_clk);
+        @sockets = remove_scolar_from_array(\@sockets,'reset') if ($remove_reset);
+        foreach my $socket (@sockets){
+            my @nums=$self->soc_list_socket_nums($instance_id,$socket);
+            foreach my $num (@nums){
+                my $name= $self->soc_get_socket_name ($instance_id,$socket,$num);
+                my  ($s_type,$s_value,$s_connection_num)=$self->soc_get_socket_of_instance($instance_id,$socket);
+                my $v=(defined $s_value) ? $self->soc_get_module_param_value($instance_id,$s_value) : 1;
+                $v=1 if ( length( $v || '' ) ==0);
+                #for(my $i=$v-1; $i>=0; $i--) {
+                for(my $i=0; $i<$v; $i++) {
+                    #$socket_color{socket_${socket}\_$i}=$n;
+                    #$n = ($n<30)? $n+1 : 0;
+                    my ($ref1,$ref2)= $self->soc_get_modules_plug_connected_to_socket($instance_id,$socket,$i);
+                    my %connected_plugs=%$ref1;
+                    my %connected_plug_nums=%$ref2;
+                    if(%connected_plugs || $remove_unused==0){ 
+                        $dotfile= ($first)? "$dotfile\{<socket_${socket}\_$i>$name\_$i" : "$dotfile |<socket_${socket}_${i}>$name\_${i}";
+                        $first=0;
+                    }
+                }
+                
+            }
+        }    
+        
+        $dotfile=($first)? "$dotfile $instance_name"  : "$dotfile}|$instance_name";
+        $first=1;
+        my @plugs= $self->soc_get_all_plugs_of_an_instance($instance_id);
+        @plugs = remove_scolar_from_array(\@plugs,'clk') if ($remove_clk);
+        @plugs = remove_scolar_from_array(\@plugs,'reset') if ($remove_reset);
+        my %plug_order;
+        my @noconnect;
+        foreach my $plug (@plugs){
+            my @nums=$self->soc_list_plug_nums($instance_id,$plug);
+            foreach my $num (@nums){
+                my ($addr,$base,$end,$name,$connect_id,$connect_socket,$connect_socket_num)=$self->soc_get_plug($instance_id,$plug,$num);
+                if(defined $connect_socket || $remove_unused==0){ 
+                    #$dotfile= ($first)?  "$dotfile |{<plug_${plug}_${num}>$name" :  "$dotfile|<plug_${plug}_${num}>$name";
+                    if(defined $connect_id && defined $connect_socket){
+                        my @sockets= $self->soc_get_all_sockets_of_an_instance($connect_id);
+                        my $order_val=0;
+                        my $s1=get_pos($connect_id, @all_instances);
+                        my $s2=get_pos($connect_socket,  @sockets);
+                        $order_val=$s1*1000000+$s2*10000+$connect_socket_num;
+                        $plug_order{$order_val}=  "<plug_${plug}_${num}>$name";
+                    }else {push (@noconnect,"<plug_${plug}_${num}>$name");}
+                }
+                #my $connect_name=$self->soc_get_instance_name($connect_id);
+                #my $color = get_color_hex_string($n);
+                #$n = ($n<30)? $n+1 : 0;
+                $graph_connect="$graph_connect $instance_id:plug_${plug}_${num} ->  $connect_id:socket_${connect_socket}_${connect_socket_num} [  dir=none]\n" if(defined $connect_socket);
+            }
+        }
+        foreach my $p (sort {$a<=>$b} keys %plug_order){
+            my $k=$plug_order{$p};
+            #print "$instance_name   : $k=\$plug_order{$p}\n";
+            $dotfile= ($first) ?   "$dotfile |{ ${k}": "$dotfile |${k}";
+            $first=0;
+        }
+        foreach my $k (@noconnect){
+            $dotfile= ($first) ?   "$dotfile |{ ${k}": "$dotfile |${k}";
+            $first=0;
+        }
+        $dotfile=  "$dotfile} }\"];";
+    }
+    $dotfile="$dotfile\n\n$graph_connect";
+    $dotfile="$dotfile\n\n}\n";
+    return $dotfile;
 }
 
-
-
-
-
 sub show_tile_diagram {
-	my $self= shift;
-
-	my $table=def_table(20,20,FALSE);
-	
-	my $window=def_popwin_size(80,80,"Processing Tile functional block diagram",'percent');	
-	my $scrolled_win = add_widget_to_scrolled_win();
-	
-	$window->add ($table);
-	
-	my $plus = def_image_button('icons/plus.png',undef,TRUE);
-	my $minues = def_image_button('icons/minus.png',undef,TRUE);
-	my $unused = gen_check_box_object ($self,"tile_diagram","show_unused",0,undef,undef);
-	my $save = def_image_button('icons/save.png',undef,TRUE);
-	my $clk = gen_check_box_object ($self,"tile_diagram","show_clk",0,undef,undef);
-	my $reset = gen_check_box_object ($self,"tile_diagram","show_reset",0,undef,undef);
-	my $dot_file = def_image_button('icons/add-notes.png',undef,TRUE);	
-	set_tip($dot_file, "Show dot file.");
-	#my $save = def_image_button('icons/save.png',undef,TRUE);
-
-	my $scale=$self->object_get_attribute("tile_diagram","scale");
-	$scale= 1 if (!defined $scale);
-		
-		
-		
-	
-	my $col=0;
-	$table->attach ($plus ,  $col, $col+1,0,1,'shrink','shrink',2,2); $col++;
-	$table->attach ($minues,  $col, $col+1,0,1,'shrink','shrink',2,2); $col++;
-	$table->attach ($save,  $col, $col+1,0,1,'shrink','shrink',2,2); $col++;
-	$table->attach (gen_label_in_left("     Remove unconnected Interfaces"),  $col,  $col+1,0,1,'shrink','shrink',2,2); $col++;
-	$table->attach ($unused,  $col,  $col+1,0,1,'shrink','shrink',2,2); $col++;
-	$table->attach (gen_label_in_left("     Remove Clk Interfaces"),  $col,  $col+1,0,1,'shrink','shrink',2,2); $col++;
-	$table->attach ($clk,  $col,  $col+1,0,1,'shrink','shrink',2,2); $col++;
-	$table->attach (gen_label_in_left("     Remove Reset Interfaces"),  $col,  $col+1,0,1,'shrink','shrink',2,2); $col++;
-	$table->attach ($reset,  $col,  $col+1,0,1,'shrink','shrink',2,2); $col++;
-	$table->attach ($dot_file,  $col,  $col+1,0,1,'shrink','shrink',2,2); $col++;
-	
-	while ($col<20){
-		
-		my $tmp=gen_label_in_left('');
-		$table->attach_defaults ($tmp, $col,  $col+1,0,1);$col++;
-	}
-	
-	$table->attach_defaults ($scrolled_win, 0, 20, 1, 20); #,'fill','shrink',2,2);	
-	
-	$plus  -> signal_connect("clicked" => sub{ 
-		$scale*=1.1 if ($scale <10);
-		$self->object_add_attribute("tile_diagram","scale", $scale );
-		gen_show_diagram($self,$scrolled_win,'tile',"tile_diagram");	
-	});	
-	$minues  -> signal_connect("clicked" => sub{ 
-		$scale*=.9  if ($scale >0.1); ;
-		$self->object_add_attribute("tile_diagram","scale", $scale );
-		gen_show_diagram($self,$scrolled_win,'tile',"tile_diagram");	
-	});
-	$save-> signal_connect("clicked" => sub{ 
-			save_inline_diagram_as ($self);
-			show_tile_diagram($self);
-			$window->destroy;
-		});	
-	$unused-> signal_connect("toggled" => sub{
-		gen_show_diagram($self,$scrolled_win,'tile',"tile_diagram");	
-
-	});
-	$clk-> signal_connect("toggled" => sub{
-		gen_show_diagram($self,$scrolled_win,'tile',"tile_diagram");	
-
-	});
-	$reset-> signal_connect("toggled" => sub{
-		
-		gen_show_diagram($self,$scrolled_win,'tile',"tile_diagram");		
-
-	});
-	
-	$dot_file-> signal_connect("clicked" => sub{ 
-			my $dotfile = get_dot_file_text($self,'tile');	
-			show_text_in_scrolled_win($self,$scrolled_win, $dotfile);			
-	});
-	
-	
-	gen_show_diagram($self,$scrolled_win,'tile',"tile_diagram");	
-	$window->show_all();
+    my $self= shift;
+    my $table=def_table(20,20,FALSE);
+    my $window=def_popwin_size(80,80,"Processing Tile functional block diagram",'percent');    
+    my $scrolled_win = add_widget_to_scrolled_win();
+    $window->add ($table);
+    my $plus = def_image_button('icons/plus.png',undef,TRUE);
+    my $minues = def_image_button('icons/minus.png',undef,TRUE);
+    my $unused = gen_check_box_object ($self,"tile_diagram","show_unused",0,undef,undef);
+    my $save = def_image_button('icons/save.png',undef,TRUE);
+    my $clk = gen_check_box_object ($self,"tile_diagram","show_clk",0,undef,undef);
+    my $reset = gen_check_box_object ($self,"tile_diagram","show_reset",0,undef,undef);
+    my $dot_file = def_image_button('icons/add-notes.png',undef,TRUE);    
+    set_tip($dot_file, "Show dot file.");
+    #my $save = def_image_button('icons/save.png',undef,TRUE);
+    my $scale=$self->object_get_attribute("tile_diagram","scale");
+    $scale= 1 if (!defined $scale);
+    my $col=0;
+    $table->attach ($plus ,  $col, $col+1,0,1,'shrink','shrink',2,2); $col++;
+    $table->attach ($minues,  $col, $col+1,0,1,'shrink','shrink',2,2); $col++;
+    $table->attach ($save,  $col, $col+1,0,1,'shrink','shrink',2,2); $col++;
+    $table->attach (gen_label_in_left("     Remove unconnected Interfaces"),  $col,  $col+1,0,1,'shrink','shrink',2,2); $col++;
+    $table->attach ($unused,  $col,  $col+1,0,1,'shrink','shrink',2,2); $col++;
+    $table->attach (gen_label_in_left("     Remove Clk Interfaces"),  $col,  $col+1,0,1,'shrink','shrink',2,2); $col++;
+    $table->attach ($clk,  $col,  $col+1,0,1,'shrink','shrink',2,2); $col++;
+    $table->attach (gen_label_in_left("     Remove Reset Interfaces"),  $col,  $col+1,0,1,'shrink','shrink',2,2); $col++;
+    $table->attach ($reset,  $col,  $col+1,0,1,'shrink','shrink',2,2); $col++;
+    $table->attach ($dot_file,  $col,  $col+1,0,1,'shrink','shrink',2,2); $col++;
+    while ($col<20){
+        my $tmp=gen_label_in_left('');
+        $table->attach_defaults ($tmp, $col,  $col+1,0,1);$col++;
+    }
+    $table->attach_defaults ($scrolled_win, 0, 20, 1, 20); #,'fill','shrink',2,2);    
+    $plus  -> signal_connect("clicked" => sub{ 
+        $scale*=1.1 if ($scale <10);
+        $self->object_add_attribute("tile_diagram","scale", $scale );
+        gen_show_diagram($self,$scrolled_win,'tile',"tile_diagram");    
+    });    
+    $minues  -> signal_connect("clicked" => sub{ 
+        $scale*=.9  if ($scale >0.1); ;
+        $self->object_add_attribute("tile_diagram","scale", $scale );
+        gen_show_diagram($self,$scrolled_win,'tile',"tile_diagram");    
+    });
+    $save-> signal_connect("clicked" => sub{ 
+            save_inline_diagram_as ($self);
+            show_tile_diagram($self);
+            $window->destroy;
+        });    
+    $unused-> signal_connect("toggled" => sub{
+        gen_show_diagram($self,$scrolled_win,'tile',"tile_diagram");    
+    });
+    $clk-> signal_connect("toggled" => sub{
+        gen_show_diagram($self,$scrolled_win,'tile',"tile_diagram");    
+    });
+    $reset-> signal_connect("toggled" => sub{
+        
+        gen_show_diagram($self,$scrolled_win,'tile',"tile_diagram");        
+    });
+    $dot_file-> signal_connect("clicked" => sub{ 
+            my $dotfile = get_dot_file_text($self,'tile');    
+            show_text_in_scrolled_win($self,$scrolled_win, $dotfile);            
+    });
+    gen_show_diagram($self,$scrolled_win,'tile',"tile_diagram");    
+    $window->show_all();
 }
 
 
 sub gen_show_diagram{
-	my ($self,$scrolled_win,$type,$name)=@_;
-			
-	my $topology=$self->object_get_attribute('noc_param','TOPOLOGY');
-	if ($type eq 'topology' && $topology eq '"CUSTOM"'){
-		
-		 my $name=$self->object_get_attribute('noc_param','CUSTOM_TOPOLOGY_NAME');
-		 $name=~s/["]//gs;        		
-		 my $image=  get_project_dir()."/mpsoc/rtl/src_topology/$name/$name.png";
-		 my $tmp  = "$ENV{'PRONOC_WORK'}/tmp/diagram.png";
-		
-		 unlink $tmp; 
-		 return 0 unless (-f "$image");
-		 copy ($image,$tmp);
-		 return 0 unless (-f "$tmp");
-		 show_diagram ($self,$scrolled_win,$name);
-		 return 1;
-	}
-	
-	
-	
-	my $dotfile = get_dot_file_text($self,$type);	
-   	
-   	generate_and_show_graph_using_graphviz ($self,$scrolled_win,$dotfile, $name);	
-	
+    my ($self,$scrolled_win,$type,$name)=@_;
+    my $topology=$self->object_get_attribute('noc_param','TOPOLOGY');
+    if ($type eq 'topology' && $topology eq '"CUSTOM"'){
+        my $name=$self->object_get_attribute('noc_param','CUSTOM_TOPOLOGY_NAME');
+        $name=~s/["]//gs;                
+        my $image=  get_project_dir()."/mpsoc/rtl/src_topology/$name/$name.png";
+        my $tmp  = "$ENV{'PRONOC_WORK'}/tmp/diagram.png";
+        unlink $tmp; 
+        return 0 unless (-f "$image");
+        copy ($image,$tmp);
+        return 0 unless (-f "$tmp");
+        show_diagram ($self,$scrolled_win,$name);
+        return 1;
+    }
+    my $dotfile = get_dot_file_text($self,$type);    
+    generate_and_show_graph_using_graphviz ($self,$scrolled_win,$dotfile, $name);    
 }
 
 
 sub show_topology_diagram {
-	my ($self)= @_;
-	
-	my $table=def_table(20,20,FALSE);
-	
-	my $window=def_popwin_size(80,80,"NoC-based MPSoC topology block diagram",'percent');	
-	my $scrolled_win = add_widget_to_scrolled_win();
-	
-	
-	my $notebook = gen_notebook();
-	$notebook->set_tab_pos ('top');
-	$notebook->set_scrollable(TRUE);
-	$window->add($notebook);
-	
-	
-	
-	
-	my @data;	
-	my $ref =$self->object_get_attribute('noc_param');
-	if(defined $ref){
-		my %param=%{$ref};
-		foreach my $p (sort keys %param){
-			push (@data, {0 => "$p", 1 =>"$param{$p}"});
-		}		
-	}
-	
-	# create list store
-	my @clmn_type =  ('Glib::String',  'Glib::String'); 
-	my @clmns = (" Parameter Name   ", " Value ");
-	my $page2=add_widget_to_scrolled_win(gen_list_store (\@data,\@clmn_type,\@clmns));
-	
-	
-	
-	$notebook->append_page ($table,gen_label_with_mnemonic ("Topology diagram")) ;
-	$notebook->append_page ($page2,gen_label_with_mnemonic ("NoC parameters")) ;
-	
-	
-	
-	
-	
-	
-	
-
-
-	my $plus = def_image_button('icons/plus.png',undef,TRUE);
-	my $minues = def_image_button('icons/minus.png',undef,TRUE);
-	my $save = def_image_button('icons/save.png',undef,TRUE);
-	my $dot_file = def_image_button('icons/add-notes.png',undef,TRUE);		
-	set_tip($dot_file, "Show dot file.");
-	
-	my $gtype=$self->object_get_attribute("tile_diagram","gtype");
-	if (!defined $gtype){
-		$gtype='comp' ;
-		$self->object_add_attribute("tile_diagram","gtype",$gtype);
-	}		
-	my $graph_type= ($gtype eq 'comp')? def_colored_button('comp',17): def_colored_button('simple',4);
-	my $box=def_hbox(FALSE,0);
-	$box->pack_start( $graph_type, FALSE, FALSE, 0);
-	
-	
-	
-	
-	my $scale=$self->object_get_attribute("tile_diagram","scale");
-	$scale= 1 if (!defined $scale);
-		
-		
-		
-	
-	my $col=0;
-	$table->attach ($plus ,  $col, $col+1,0,1,'shrink','shrink',2,2); $col++;
-	$table->attach ($minues,  $col, $col+1,0,1,'shrink','shrink',2,2); $col++;
-	$table->attach ($save,  $col, $col+1,0,1,'shrink','shrink',2,2); $col++;
-	$table->attach ($dot_file,  $col, $col+1,0,1,'shrink','shrink',2,2); $col++;
-	$table->attach ($box,  $col, $col+1,0,1,'shrink','shrink',2,2); $col++;
-	#$table->attach (gen_label_in_left("     Remove unconnected Interfaces"),  $col,  $col+1,0,1,'shrink','shrink',2,2); $col++;
-	#$table->attach (gen_label_in_left("     Remove Clk Interfaces"),  $col,  $col+1,0,1,'shrink','shrink',2,2); $col++;
-	#$table->attach (gen_label_in_left("     Remove Reset Interfaces"),  $col,  $col+1,0,1,'shrink','shrink',2,2); $col++;
-	while ($col<20){		
-		my $tmp=gen_label_in_left('');
-		$table->attach_defaults ($tmp, $col,  $col+1,0,1);$col++;
-	}
-	
-	$table->attach_defaults ($scrolled_win, 0, 20, 1, 20); #,'fill','shrink',2,2);	
-	
-	$plus  -> signal_connect("clicked" => sub{ 
-		$scale*=1.1 if ($scale <10);
-		$self->object_add_attribute("topology_diagram","scale", $scale );
-		gen_show_diagram($self,$scrolled_win,'topology',"topology_diagram");	
-		
-	});	
-	$minues  -> signal_connect("clicked" => sub{ 
-		$scale*=.9  if ($scale >0.1);
-		$self->object_add_attribute("topology_diagram","scale", $scale );
-		gen_show_diagram($self,$scrolled_win,'topology',"topology_diagram");	
-	});
-	$save-> signal_connect("clicked" => sub{ 
-			save_inline_diagram_as ($self);			
-			show_topology_diagram($self);
-			$window->destroy;
-	});	
-	
-	$dot_file-> signal_connect("clicked" => sub{ 
-			my $dot_file=get_dot_file_text($self,'topology');
-			show_text_in_scrolled_win($self,$scrolled_win, $dot_file);			
-	});
-	
-	$graph_type-> signal_connect("clicked" => sub{ 
-			my $gtype=$self->object_get_attribute("tile_diagram","gtype");			
-			my $new = ($gtype eq "simple")? "comp" : "simple";
-			$self->object_add_attribute("tile_diagram","gtype",$new);	
-			$graph_type= ($new eq 'comp')? def_colored_button('comp',17): def_colored_button('simple',4);
-			show_topology_diagram($self);
-			$window->destroy;			
-	});	
-	
-	
-	gen_show_diagram($self,$scrolled_win,'topology',"topology_diagram");	
-	$window->show_all();
-	$notebook->set_current_page (0);
+    my ($self)= @_;
+    my $table=def_table(20,20,FALSE);
+    my $window=def_popwin_size(80,80,"NoC-based MPSoC topology block diagram",'percent');    
+    my $scrolled_win = add_widget_to_scrolled_win();
+    my $notebook = gen_notebook();
+    $notebook->set_tab_pos ('top');
+    $notebook->set_scrollable(TRUE);
+    $window->add($notebook);
+    my @data;    
+    my $ref =$self->object_get_attribute('noc_param');
+    if(defined $ref){
+        my %param=%{$ref};
+        foreach my $p (sort keys %param){
+            push (@data, {0 => "$p", 1 =>"$param{$p}"});
+        }        
+    }
+    
+    # create list store
+    my @clmn_type =  ('Glib::String',  'Glib::String'); 
+    my @clmns = (" Parameter Name   ", " Value ");
+    my $page2=add_widget_to_scrolled_win(gen_list_store (\@data,\@clmn_type,\@clmns));
+    $notebook->append_page ($table,gen_label_with_mnemonic ("Topology diagram")) ;
+    $notebook->append_page ($page2,gen_label_with_mnemonic ("NoC parameters")) ;
+    my $plus = def_image_button('icons/plus.png',undef,TRUE);
+    my $minues = def_image_button('icons/minus.png',undef,TRUE);
+    my $save = def_image_button('icons/save.png',undef,TRUE);
+    my $dot_file = def_image_button('icons/add-notes.png',undef,TRUE);        
+    set_tip($dot_file, "Show dot file.");
+    
+    my $gtype=$self->object_get_attribute("tile_diagram","gtype");
+    if (!defined $gtype){
+        $gtype='comp' ;
+        $self->object_add_attribute("tile_diagram","gtype",$gtype);
+    }        
+    my $graph_type= ($gtype eq 'comp')? def_colored_button('comp',17): def_colored_button('simple',4);
+    my $box=def_hbox(FALSE,0);
+    $box->pack_start( $graph_type, FALSE, FALSE, 0);
+    my $scale=$self->object_get_attribute("tile_diagram","scale");
+    $scale= 1 if (!defined $scale);
+    
+    my $col=0;
+    $table->attach ($plus ,  $col, $col+1,0,1,'shrink','shrink',2,2); $col++;
+    $table->attach ($minues,  $col, $col+1,0,1,'shrink','shrink',2,2); $col++;
+    $table->attach ($save,  $col, $col+1,0,1,'shrink','shrink',2,2); $col++;
+    $table->attach ($dot_file,  $col, $col+1,0,1,'shrink','shrink',2,2); $col++;
+    $table->attach ($box,  $col, $col+1,0,1,'shrink','shrink',2,2); $col++;
+    #$table->attach (gen_label_in_left("     Remove unconnected Interfaces"),  $col,  $col+1,0,1,'shrink','shrink',2,2); $col++;
+    #$table->attach (gen_label_in_left("     Remove Clk Interfaces"),  $col,  $col+1,0,1,'shrink','shrink',2,2); $col++;
+    #$table->attach (gen_label_in_left("     Remove Reset Interfaces"),  $col,  $col+1,0,1,'shrink','shrink',2,2); $col++;
+    while ($col<20){        
+        my $tmp=gen_label_in_left('');
+        $table->attach_defaults ($tmp, $col,  $col+1,0,1);$col++;
+    }
+    
+    $table->attach_defaults ($scrolled_win, 0, 20, 1, 20); #,'fill','shrink',2,2);    
+    $plus  -> signal_connect("clicked" => sub{ 
+        $scale*=1.1 if ($scale <10);
+        $self->object_add_attribute("topology_diagram","scale", $scale );
+        gen_show_diagram($self,$scrolled_win,'topology',"topology_diagram");    
+        
+    });    
+    $minues  -> signal_connect("clicked" => sub{ 
+        $scale*=.9  if ($scale >0.1);
+        $self->object_add_attribute("topology_diagram","scale", $scale );
+        gen_show_diagram($self,$scrolled_win,'topology',"topology_diagram");    
+    });
+    $save-> signal_connect("clicked" => sub{ 
+            save_inline_diagram_as ($self);            
+            show_topology_diagram($self);
+            $window->destroy;
+    });    
+    
+    $dot_file-> signal_connect("clicked" => sub{ 
+            my $dot_file=get_dot_file_text($self,'topology');
+            show_text_in_scrolled_win($self,$scrolled_win, $dot_file);            
+    });
+    
+    $graph_type-> signal_connect("clicked" => sub{ 
+            my $gtype=$self->object_get_attribute("tile_diagram","gtype");            
+            my $new = ($gtype eq "simple")? "comp" : "simple";
+            $self->object_add_attribute("tile_diagram","gtype",$new);    
+            $graph_type= ($new eq 'comp')? def_colored_button('comp',17): def_colored_button('simple',4);
+            show_topology_diagram($self);
+            $window->destroy;            
+    });    
+    gen_show_diagram($self,$scrolled_win,'topology',"topology_diagram");    
+    $window->show_all();
+    $notebook->set_current_page (0);
 }
 
 
 sub get_dot_file_text {
-	my ($self,$type)=@_;
-	my $dotfile;
-	$dotfile=   get_dot_file($self) if ($type eq 'tile');
-	$dotfile=   get_topology_dot_file($self) if ($type eq 'topology');
-	$dotfile=   generate_custom_topology_dot_file($self) if ($type eq 'custom_topology');	
-	$dotfile=   generate_trace_dot_file($self) if ($type eq 'trace');
-	$dotfile=   generate_merge_actor_dot_file	($self) if ($type eq 'merge-actor');
-	$dotfile=   generate_map_dot_file($self) if ($type eq 'map');
-	return $dotfile;	
+    my ($self,$type)=@_;
+    my $dotfile;
+    $dotfile=   get_dot_file($self) if ($type eq 'tile');
+    $dotfile=   get_topology_dot_file($self) if ($type eq 'topology');
+    $dotfile=   generate_custom_topology_dot_file($self) if ($type eq 'custom_topology');    
+    $dotfile=   generate_trace_dot_file($self) if ($type eq 'trace');
+    $dotfile=   generate_merge_actor_dot_file    ($self) if ($type eq 'merge-actor');
+    $dotfile=   generate_map_dot_file($self) if ($type eq 'map');
+    return $dotfile;    
 }
 
 
 sub gen_diagram {
-	my ($self,$type)=@_;
-	my $topology=$self->object_get_attribute('noc_param','TOPOLOGY');
-	if ($type eq 'topology' && $topology eq '"CUSTOM"'){
-		
-		 my $name=$self->object_get_attribute('noc_param','CUSTOM_TOPOLOGY_NAME');
-		 $name=~s/["]//gs;        		
-		 my $image=  get_project_dir()."/mpsoc/rtl/src_topology/$name/$name.png";
-		 my $tmp  = "$ENV{'PRONOC_WORK'}/tmp/diagram.png";
-		
-		 unlink $tmp; 
-		 return 0 unless (-f "$image");
-		 copy ($image,$tmp);
-		 return 0 unless (-f "$tmp");
-		 return 1;
-	}
-	
-	
-	
-	my $dotfile = get_dot_file_text(@_);									
-	
-	my $tmp_dir  = "$ENV{'PRONOC_WORK'}/tmp";
-	
-
-	my $cmd;
-	#$cmd=  "dot  $tmp_dir/diagram.txt | neato -n  -Tpng -o $tmp_dir/diagram.png" if ($type eq 'tile' || $type eq 'trace'  );
-	#$cmd = "dot  $tmp_dir/diagram.txt -Kfdp -n -Tpng -o $tmp_dir/diagram.png" if ( $type eq 'map' || $type eq 'topology' || $type eq 'custom_topology' );	
- 	$cmd=  " dot   | neato -n  -Tpng -o $tmp_dir/diagram.png" if ($type eq 'tile' || $type eq 'trace'  );
-	$cmd = " dot   -Kfdp -n -Tpng -o $tmp_dir/diagram.png" if ( $type eq 'map' || $type eq 'topology' || $type eq 'custom_topology' );	
+    my ($self,$type)=@_;
+    my $topology=$self->object_get_attribute('noc_param','TOPOLOGY');
+    if ($type eq 'topology' && $topology eq '"CUSTOM"'){
+        my $name=$self->object_get_attribute('noc_param','CUSTOM_TOPOLOGY_NAME');
+        $name=~s/["]//gs;                
+        my $image=  get_project_dir()."/mpsoc/rtl/src_topology/$name/$name.png";
+        my $tmp  = "$ENV{'PRONOC_WORK'}/tmp/diagram.png";
+        unlink $tmp; 
+        return 0 unless (-f "$image");
+        copy ($image,$tmp);
+        return 0 unless (-f "$tmp");
+        return 1;
+    }
+    my $dotfile = get_dot_file_text(@_);                                    
+    my $tmp_dir  = "$ENV{'PRONOC_WORK'}/tmp";
+    my $cmd;
+    #$cmd=  "dot  $tmp_dir/diagram.txt | neato -n  -Tpng -o $tmp_dir/diagram.png" if ($type eq 'tile' || $type eq 'trace'  );
+    #$cmd = "dot  $tmp_dir/diagram.txt -Kfdp -n -Tpng -o $tmp_dir/diagram.png" if ( $type eq 'map' || $type eq 'topology' || $type eq 'custom_topology' );    
+    $cmd=  " dot   | neato -n  -Tpng -o $tmp_dir/diagram.png" if ($type eq 'tile' || $type eq 'trace'  );
+    $cmd = " dot   -Kfdp -n -Tpng -o $tmp_dir/diagram.png" if ( $type eq 'map' || $type eq 'topology' || $type eq 'custom_topology' );    
     $cmd = "echo \'$dotfile\' | $cmd";
-
-	my ($stdout,$exit,$stderr)= run_cmd_in_back_ground_get_stdout ($cmd);
-
-	if ( length( $stderr || '' ) !=0)  {
-		message_dialog("$stderr\nHave you installed graphviz? If not run \n \t \"sudo apt-get install graphviz\" \n in terminal");
-		return 0 unless (-f "$tmp_dir/diagram.png");
-	}
-		return  1;
+    my ($stdout,$exit,$stderr)= run_cmd_in_back_ground_get_stdout ($cmd);
+    if ( length( $stderr || '' ) !=0)  {
+        message_dialog("$stderr\nHave you installed graphviz? If not run \n \t \"sudo apt-get install graphviz\" \n in terminal");
+        return 0 unless (-f "$tmp_dir/diagram.png");
+    }
+    return  1;
 }
 
 
-
 sub show_diagram {
-	my ($self,$scrolled_win,$name,$image_name)=@_;	
-	$image_name="diagram.png" if (!defined $image_name);
-	my @list = $scrolled_win->get_children();
-	foreach my $l (@list){ 
-		$scrolled_win->remove($l);			
-	}
-	
-		
-	my $scale=$self->object_get_attribute($name,"scale");
-	$scale= 1 if (!defined $scale);
-	my $tmp_dir  = "$ENV{'PRONOC_WORK'}/tmp";
-	my $diagram=open_image("$tmp_dir/$image_name",70*$scale,70*$scale,'percent');
-	
-	add_widget_to_scrolled_win($diagram,$scrolled_win);
-	$scrolled_win->show_all();	
-		
+    my ($self,$scrolled_win,$name,$image_name)=@_;    
+    $image_name="diagram.png" if (!defined $image_name);
+    my @list = $scrolled_win->get_children();
+    foreach my $l (@list){ 
+        $scrolled_win->remove($l);            
+    }
+    my $scale=$self->object_get_attribute($name,"scale");
+    $scale= 1 if (!defined $scale);
+    my $tmp_dir  = "$ENV{'PRONOC_WORK'}/tmp";
+    my $diagram=open_image("$tmp_dir/$image_name",70*$scale,70*$scale,'percent');
+    add_widget_to_scrolled_win($diagram,$scrolled_win);
+    $scrolled_win->show_all();    
 }
 
 sub show_text_in_scrolled_win {
-	my ($self,$scrolled_win, $text)=@_;
-	my @list = $scrolled_win->get_children();
-	foreach my $l (@list){ 
-		$scrolled_win->remove($l);			
-	}
-		
- 	
-	my ($u,$tview)=create_txview();
-	
-	show_info($tview, $text);
-	add_widget_to_scrolled_win($u,$scrolled_win);
-	$scrolled_win->show_all();		
+    my ($self,$scrolled_win, $text)=@_;
+    my @list = $scrolled_win->get_children();
+    foreach my $l (@list){ 
+        $scrolled_win->remove($l);            
+    }
+    my ($u,$tview)=create_txview();
+    show_info($tview, $text);
+    add_widget_to_scrolled_win($u,$scrolled_win);
+    $scrolled_win->show_all();        
 }
 
-
-
-
 sub save_diagram_as {
-	my $self= shift;
-	
-	my $file;
-	my $title ='Save as';
-
-
-
-	my @extensions=('png');
-	my $open_in=undef;
-	my $dialog = save_file_dialog  ( 'Save file',@extensions);
-	$dialog->set_current_folder ($open_in) if(defined  $open_in); 
-	
-		
-	if ( "ok" eq $dialog->run ) {
-	    	$file = $dialog->get_filename;
-			my $ext = $dialog->get_filter;
-			$ext=$ext->get_name;
-			my ($name,$path,$suffix) = fileparse("$file",qr"\..[^.]*$");
-			$file = ($suffix eq ".$ext" )? $file : "$file.$ext";
-			
-			$self->object_add_attribute("graph_save","name",$file);
-			$self->object_add_attribute("graph_save","extension",$ext);
-			my $tmp  = "$ENV{'PRONOC_WORK'}/tmp/diagram.png";
-			copy ($tmp,$file);
-
-
-					
-	}
-	$dialog->destroy;
+    my $self= shift;
+    my $file;
+    my $title ='Save as';
+    my @extensions=('png');
+    my $open_in=undef;
+    my $dialog = save_file_dialog  ( 'Save file',@extensions);
+    $dialog->set_current_folder ($open_in) if(defined  $open_in); 
+    if ( "ok" eq $dialog->run ) {
+        $file = $dialog->get_filename;
+        my $ext = $dialog->get_filter;
+        $ext=$ext->get_name;
+        my ($name,$path,$suffix) = fileparse("$file",qr"\..[^.]*$");
+        $file = ($suffix eq ".$ext" )? $file : "$file.$ext";
+        $self->object_add_attribute("graph_save","name",$file);
+        $self->object_add_attribute("graph_save","extension",$ext);
+        my $tmp  = "$ENV{'PRONOC_WORK'}/tmp/diagram.png";
+        copy ($tmp,$file);
+    }
+    $dialog->destroy;
 }
 
-
-
-
 sub save_inline_diagram_as {
-	my $self= shift;
-	
-	my $file;
-	my $title ='Save as';
-
-
-
-	my @extensions=('png','jpeg');
-	my $open_in=undef;
-	my $dialog = save_file_dialog  ('Save file',@extensions);
-	$dialog->set_current_folder ($open_in) if(defined  $open_in);
-	
-		
-	if ( "ok" eq $dialog->run ) {
-	    	$file = $dialog->get_filename;
-			my $ext = $dialog->get_filter;
-			$ext=$ext->get_name;
-			my ($name,$path,$suffix) = fileparse("$file",qr"\..[^.]*$");
-			
-			$file = ($suffix eq ".$ext" )? $file : "$file.$ext";
-			
-			$self->object_add_attribute("graph_save","name","$path/$name");
-			$self->object_add_attribute("graph_save","extension",$ext);
-			$self->object_add_attribute("graph_save","enable",1);
-			set_gui_status($self,"ref",5);				
-	}
-	$dialog->destroy;
+    my $self= shift;
+    my $file;
+    my $title ='Save as';
+    my @extensions=('png','jpeg');
+    my $open_in=undef;
+    my $dialog = save_file_dialog  ('Save file',@extensions);
+    $dialog->set_current_folder ($open_in) if(defined  $open_in);
+    if ( "ok" eq $dialog->run ) {
+        $file = $dialog->get_filename;
+        my $ext = $dialog->get_filter;
+        $ext=$ext->get_name;
+        my ($name,$path,$suffix) = fileparse("$file",qr"\..[^.]*$");
+        $file = ($suffix eq ".$ext" )? $file : "$file.$ext";
+        $self->object_add_attribute("graph_save","name","$path/$name");
+        $self->object_add_attribute("graph_save","extension",$ext);
+        $self->object_add_attribute("graph_save","enable",1);
+        set_gui_status($self,"ref",5);
+    }
+    $dialog->destroy;
 }
 
 
 
 sub generate_trace_dot_file{
-	my $self=shift;
-	my $dotfile=
+    my $self=shift;
+    my $dotfile=
 "digraph G {
-	graph [ layout = neato, rankdir = LR , splines=polyline, overlap = false]; 
-	
+    graph [ layout = neato, rankdir = LR , splines=polyline, overlap = false]; 
+    
 ";
-	
-
-	
 #add connections
-
-	my @traces= get_trace_list($self,'raw');
-	foreach my $p (@traces) {	
-		my ($src,$dst, $Mbytes, $file_id, $file_name)=get_trace($self,'raw',$p);
-		$dotfile=$dotfile."\"$src\" -> \"$dst\"  [label=\"$Mbytes\" ];\n";	
-	}
-	
-	$dotfile=$dotfile."\n}\n";
-	return $dotfile;
-	
+    my @traces= get_trace_list($self,'raw');
+    foreach my $p (@traces) {    
+        my ($src,$dst, $Mbytes, $file_id, $file_name)=get_trace($self,'raw',$p);
+        $dotfile=$dotfile."\"$src\" -> \"$dst\"  [label=\"$Mbytes\" ];\n";    
+    }
+    $dotfile=$dotfile."\n}\n";
+    return $dotfile;
 }
 
 
-
 sub generate_map_dot_file{
-	my $self=shift;
-	my $dotfile=
+    my $self=shift;
+    my $dotfile=
 "digraph G {
-	graph [layout = neato, rankdir = LR ,splines=spline,  overlap = false]; 
-	node[shape=record];
-	
-	";
-	
-#add nodes	
-	my @tasks=get_all_tasks($self,"merge");
-	my ($NE, $NR, $RAw, $EAw, $Fw) = get_topology_info($self);	
-	my %pos=get_endp_pos($self);	
-	my @mappedtasks;	
-	for(my $i=0; $i<$NE; $i++){ 
-					my $task=get_task_assigned_to_tile($self,$i);
-					push(@mappedtasks,$task) if (defined $task); 
-					
-					$task= "_" if (!defined $task); 
-					my $n =    "tile($i)" ;
-					my $m =    "tile($i)" ;
-					my $node = "\"$m\"";					
-					my $label =   "\"<S$task> $n|<R$task> $task\"" ;
-							
-					$dotfile=$dotfile."
+    graph [layout = neato, rankdir = LR ,splines=spline,  overlap = false]; 
+    node[shape=record];
+    
+    ";
+    
+#add nodes    
+    my @tasks=get_all_tasks($self,"merge");
+    my ($NE, $NR, $RAw, $EAw, $Fw) = get_topology_info($self);    
+    my %pos=get_endp_pos($self);    
+    my @mappedtasks;    
+    for(my $i=0; $i<$NE; $i++){ 
+        my $task=get_task_assigned_to_tile($self,$i);
+        push(@mappedtasks,$task) if (defined $task); 
+        $task= "_" if (!defined $task); 
+        my $n =    "tile($i)" ;
+        my $m =    "tile($i)" ;
+        my $node = "\"$m\"";                    
+        my $label =   "\"<S$task> $n|<R$task> $task\"" ;
+        $dotfile=$dotfile."
 $node\[
-	label = $label
+    label = $label
     pos = $pos{$i}
-];";					
-		
-	}					
-	$dotfile=$dotfile."\n\n";
-	#add connections
-	my @traces= get_trace_list($self,'merge');
-	my %src_dst;
-	
-	foreach my $p (@traces){
-		my ($src,$dst, $Mbytes, $file_id, $file_name)=get_trace($self,'merge',$p);		
-		my $src_tile=get_task_give_tile($self,"$src");
-		my $dst_tile=get_task_give_tile($self,"$dst");		
-		next if ($src_dst{"${src_tile}_$dst_tile"}); #make sure there will be only one arow betwenn each source destination tile
-		next if ( $src_tile eq "-" ||  $dst_tile eq "-" );			
-		$dotfile=$dotfile." \"$src_tile\" :  \"S$src\" ->  \"$dst_tile\" : \"R$dst\"  ;\n" if((defined $src_tile )&& (defined $dst_tile));
-		$src_dst{"${src_tile}_$dst_tile"}=1;
-	}
-	$dotfile=$dotfile."\n}\n";
-	return $dotfile;
+];";
+    }
+    $dotfile=$dotfile."\n\n";
+    #add connections
+    my @traces= get_trace_list($self,'merge');
+    my %src_dst;
+    foreach my $p (@traces){
+        my ($src,$dst, $Mbytes, $file_id, $file_name)=get_trace($self,'merge',$p);        
+        my $src_tile=get_task_give_tile($self,"$src");
+        my $dst_tile=get_task_give_tile($self,"$dst");        
+        next if ($src_dst{"${src_tile}_$dst_tile"}); #make sure there will be only one arow betwenn each source destination tile
+        next if ( $src_tile eq "-" ||  $dst_tile eq "-" );            
+        $dotfile=$dotfile." \"$src_tile\" :  \"S$src\" ->  \"$dst_tile\" : \"R$dst\"  ;\n" if((defined $src_tile )&& (defined $dst_tile));
+        $src_dst{"${src_tile}_$dst_tile"}=1;
+    }
+    $dotfile=$dotfile."\n}\n";
+    return $dotfile;
 }
 
 
-
-
-
 sub show_trace_diagram {
-	my ($self,$type)=@_;
-	my $table=def_table(20,20,FALSE);
-	
-	my $window=def_popwin_size(80,80,"Trace Diagram",'percent');	
-	my $scrolled_win =add_widget_to_scrolled_win();
-	
-	$window->add ($table);
-	
-	my $plus = def_image_button('icons/plus.png',undef,TRUE);
-	my $minues = def_image_button('icons/minus.png',undef,TRUE);
-	my $save = def_image_button('icons/save.png',undef,TRUE);
-	my $dot_file = def_image_button('icons/add-notes.png',undef,TRUE);	
-	set_tip($dot_file, "Show dot file.");
-	
-	
-
-	my $scale=$self->object_get_attribute("${type}_diagram","scale");
-	$scale= 1 if (!defined $scale);
-		
-		
-		
-	
-	my $col=0;
-	$table->attach ($plus ,  $col, $col+1,0,1,'shrink','shrink',2,2); $col++;
-	$table->attach ($minues,  $col, $col+1,0,1,'shrink','shrink',2,2); $col++;
-	$table->attach ($save,  $col, $col+1,0,1,'shrink','shrink',2,2); $col++;
-	$table->attach ($dot_file,  $col, $col+1,0,1,'shrink','shrink',2,2); $col++;
-	$table->attach_defaults ($scrolled_win, 0, 20, 1, 20); #,'fill','shrink',2,2);	
-	
-	while ($col<20){	
-		my $tmp=gen_label_in_left('');
-		$table->attach_defaults ($tmp, $col,  $col+1,0,1);$col++;
-	}
-	
-	$plus  -> signal_connect("clicked" => sub{ 
-		$scale*=1.1 if ($scale <10);
-		$self->object_add_attribute("${type}_diagram","scale", $scale );
-		my $dotfile = get_dot_file_text($self,$type);
-		generate_and_show_graph_using_graphviz ($self,$scrolled_win,$dotfile, "${type}_diagram");
-	});	
-	$minues  -> signal_connect("clicked" => sub{ 
-		$scale*=.9  if ($scale >0.1); ;
-		$self->object_add_attribute("${type}_diagram","scale", $scale );
-		gen_show_diagram ($self,$scrolled_win,$type,"${type}_diagram");
-	});
-	$save-> signal_connect("clicked" => sub{ 
-			save_inline_diagram_as ($self);
-			show_trace_diagram($self,$type);
-			$window->destroy;
-		});	
-	
-	$dot_file-> signal_connect("clicked" => sub{ 
-		my $dotfile = get_dot_file_text($self,$type);	
-		show_text_in_scrolled_win($self,$scrolled_win, $dotfile);		
-			
-	});
-
-	gen_show_diagram ($self,$scrolled_win,$type,"${type}_diagram");
-	
-	$window->show_all();
-}	
-
-
-
-
-
+    my ($self,$type)=@_;
+    my $table=def_table(20,20,FALSE);
+    my $window=def_popwin_size(80,80,"Trace Diagram",'percent');    
+    my $scrolled_win =add_widget_to_scrolled_win();
+    $window->add ($table);
+    my $plus = def_image_button('icons/plus.png',undef,TRUE);
+    my $minues = def_image_button('icons/minus.png',undef,TRUE);
+    my $save = def_image_button('icons/save.png',undef,TRUE);
+    my $dot_file = def_image_button('icons/add-notes.png',undef,TRUE);    
+    set_tip($dot_file, "Show dot file.");
+    my $scale=$self->object_get_attribute("${type}_diagram","scale");
+    $scale= 1 if (!defined $scale);
+    my $col=0;
+    $table->attach ($plus ,  $col, $col+1,0,1,'shrink','shrink',2,2); $col++;
+    $table->attach ($minues,  $col, $col+1,0,1,'shrink','shrink',2,2); $col++;
+    $table->attach ($save,  $col, $col+1,0,1,'shrink','shrink',2,2); $col++;
+    $table->attach ($dot_file,  $col, $col+1,0,1,'shrink','shrink',2,2); $col++;
+    $table->attach_defaults ($scrolled_win, 0, 20, 1, 20); #,'fill','shrink',2,2);    
+    
+    while ($col<20){    
+        my $tmp=gen_label_in_left('');
+        $table->attach_defaults ($tmp, $col,  $col+1,0,1);$col++;
+    }
+    
+    $plus  -> signal_connect("clicked" => sub{ 
+        $scale*=1.1 if ($scale <10);
+        $self->object_add_attribute("${type}_diagram","scale", $scale );
+        my $dotfile = get_dot_file_text($self,$type);
+        generate_and_show_graph_using_graphviz ($self,$scrolled_win,$dotfile, "${type}_diagram");
+    });    
+    $minues  -> signal_connect("clicked" => sub{ 
+        $scale*=.9  if ($scale >0.1); ;
+        $self->object_add_attribute("${type}_diagram","scale", $scale );
+        gen_show_diagram ($self,$scrolled_win,$type,"${type}_diagram");
+    });
+    $save-> signal_connect("clicked" => sub{ 
+            save_inline_diagram_as ($self);
+            show_trace_diagram($self,$type);
+            $window->destroy;
+        });    
+    
+    $dot_file-> signal_connect("clicked" => sub{ 
+        my $dotfile = get_dot_file_text($self,$type);    
+        show_text_in_scrolled_win($self,$scrolled_win, $dotfile);        
+            
+    });
+    gen_show_diagram ($self,$scrolled_win,$type,"${type}_diagram");
+    $window->show_all();
+}
 
 sub node_connection{
-	my ($sn,$sx,$sy,$sp,$dn,$dx,$dy,$dp,$gtype)=@_;
-	$gtype="comp" if(!defined $gtype);
-	
-	my $spp = (defined $sp  && $gtype eq "comp" ) ? ":\"p$sp\"" : " ";
-	my $dpp = (defined $dp  && $gtype eq "comp" ) ? ":\"p$dp\"" : " ";
-	my $sname = (defined $sy) ? "\"$sn${sx}_${sy}\"" : "\"$sn${sx}\"";
-	my $dname = (defined $dy) ? "\"$dn${dx}_${dy}\"" : "\"$dn${dx}\"";
-	
-	my $t= "$sname  $spp -> $dname  $dpp [  dir=none];\n"; 
-	return $t;	
+    my ($sn,$sx,$sy,$sp,$dn,$dx,$dy,$dp,$gtype)=@_;
+    $gtype="comp" if(!defined $gtype);
+    
+    my $spp = (defined $sp  && $gtype eq "comp" ) ? ":\"p$sp\"" : " ";
+    my $dpp = (defined $dp  && $gtype eq "comp" ) ? ":\"p$dp\"" : " ";
+    my $sname = (defined $sy) ? "\"$sn${sx}_${sy}\"" : "\"$sn${sx}\"";
+    my $dname = (defined $dy) ? "\"$dn${dx}_${dy}\"" : "\"$dn${dx}\"";
+    
+    my $t= "$sname  $spp -> $dname  $dpp [  dir=none];\n"; 
+    return $t;    
 }
 
 sub node_connection2{
-	my ($sn,$sx,$sp,$dn,$dx,$dy,$dp)=@_;
-	my $spp = (defined $sp) ? ":\"p$sp\"" : " ";
-	my $dpp = (defined $dp) ? ":\"p$dp\"" : " ";
-	my $sname =   "\"$sn${sx}\"";
-	my $dname =  "\"$dn${dx}\"";
-	
-	my $t= "$sname  $spp -> $dname  $dpp [  dir=none];\n"; 
-	return $t;	
+    my ($sn,$sx,$sp,$dn,$dx,$dy,$dp)=@_;
+    my $spp = (defined $sp) ? ":\"p$sp\"" : " ";
+    my $dpp = (defined $dp) ? ":\"p$dp\"" : " ";
+    my $sname =   "\"$sn${sx}\"";
+    my $dname =  "\"$dn${dx}\"";
+    my $t= "$sname  $spp -> $dname  $dpp [  dir=none];\n"; 
+    return $t;    
 }
 
 
-
-
 ##################################
 #
-##################################
-
-
-
-
+#################################
 sub generate_heat_map_table{
-	my ($d)=@_ ;
-	
-	return (def_table (1, 1, FALSE),def_table (1, 1, FALSE)) if (!defined $d);
-	my %data=%{$d};
-	my @xs = (sort {$a<=>$b} keys %data);
-	
-	
-	
-	
-	my $max=0;
-	#for(my $y=0; $y<$dim; $y++){ 		
-	#	for(my $x=0; $x<$dim; $x++){    
-		foreach my $y (@xs){
-			foreach my $x (@xs){
-			#$data{$x}{$y}=int(rand(50000));
-			#$data{$x}{$y}=$y*64+$x;
-			$max = $data{$x}{$y} if( $max < $data{$x}{$y});
-		}
-	}
-	
-
-	my $width_max = length int $max;
-	
-	my $table = def_table (1, 1, FALSE);
-	
-	#for(my $y=0; $y<$dim; $y++){ 
-	foreach my $y (@xs){
-		my $l=gen_label_in_center("$y");
-		$table->attach ($l,	$y+1,$y+2,0,1,'expand','shrink',2,2);  	
-	}			
-	#for(my $x=0; $x<$dim; $x++){
-	foreach my $x (@xs){
-		my $l=gen_label_in_center("$x");
-		$table->attach ($l,	0,1,$x+1,$x+2,'expand','shrink',2,2);  	
-	}
-	
-	#for(my $y=0; $y<$dim; $y++){ 		
-	#	for(my $x=0; $x<$dim; $x++){
-		foreach my $y (@xs){
-			foreach my $x (@xs){
-			my $d=$data{$x}{$y}; 
-			my $c = int (((5*$d))/($max+1));
-			my $v = length int $d;
-			until ($v >= $width_max){
-				$d="  ".$d;
-				$v++;
-			}   
-		
-  		my $l =gen_colored_label( "   " ,32+$c);	
-  		set_tip($l,"E[$x]->E[$y]=$d");
-  		$table->attach ($l, $y+1,$y+2,$x+1,$x+2,'expand','shrink',2,2);  		  
-  	}
-  
-  }   
-  
-  my $scale = def_table (1, 1, FALSE);
-  my $v=gen_label_in_center("0");	
-  $scale->attach ($v, 1,2,0,1,'expand','shrink',2,2); 
-  for (my $i=0; $i<5; $i++){
-  	my $l =gen_colored_label( "   " ,32+$i);
-  	my $val =int( (2*$i+1)*$max/10); 
-  	my $v=gen_label_in_center($val);	
-  	$scale->attach ($v, 0,1,$i+1,$i+2,'expand','shrink',2,2); 		  
-  	$scale->attach ($l, 1,2,$i+1,$i+2,'expand','shrink',2,2); 
-  	$scale->attach (gen_label_in_center("$max"), 1,2,$i+2,$i+3,'expand','shrink',2,2) if($i==4);
-  }
-  
-  
-   return ($table,$scale);
-  
-} 
-
+    my ($d)=@_ ;
+    return (def_table (1, 1, FALSE),def_table (1, 1, FALSE)) if (!defined $d);
+    my %data=%{$d};
+    my @xs = (sort {$a<=>$b} keys %data);
+    my $max=0;
+    #for(my $y=0; $y<$dim; $y++){         
+    #    for(my $x=0; $x<$dim; $x++){    
+        foreach my $y (@xs){
+            foreach my $x (@xs){
+            #$data{$x}{$y}=int(rand(50000));
+            #$data{$x}{$y}=$y*64+$x;
+            $max = $data{$x}{$y} if( $max < $data{$x}{$y});
+        }
+    }
+    my $width_max = length int $max;
+    my $table = def_table (1, 1, FALSE);
+    #for(my $y=0; $y<$dim; $y++){ 
+    foreach my $y (@xs){
+        my $l=gen_label_in_center("$y");
+        $table->attach ($l,    $y+1,$y+2,0,1,'expand','shrink',2,2);      
+    }
+    #for(my $x=0; $x<$dim; $x++){
+    foreach my $x (@xs){
+        my $l=gen_label_in_center("$x");
+        $table->attach ($l,    0,1,$x+1,$x+2,'expand','shrink',2,2);      
+    }
+    #for(my $y=0; $y<$dim; $y++){         
+    #    for(my $x=0; $x<$dim; $x++){
+    foreach my $y (@xs){
+        foreach my $x (@xs){
+            my $d=$data{$x}{$y}; 
+            my $c = int (((5*$d))/($max+1));
+            my $v = length int $d;
+            until ($v >= $width_max){
+                $d="  ".$d;
+                $v++;
+            }   
+            my $l =gen_colored_label( "   " ,32+$c);    
+            set_tip($l,"E[$x]->E[$y]=$d");
+            $table->attach ($l, $y+1,$y+2,$x+1,$x+2,'expand','shrink',2,2);            
+        }
+    }   
+    my $scale = def_table (1, 1, FALSE);
+    my $v=gen_label_in_center("0");    
+    $scale->attach ($v, 1,2,0,1,'expand','shrink',2,2); 
+    for (my $i=0; $i<5; $i++){
+        my $l =gen_colored_label( "   " ,32+$i);
+        my $val =int( (2*$i+1)*$max/10); 
+        my $v=gen_label_in_center($val);    
+        $scale->attach ($v, 0,1,$i+1,$i+2,'expand','shrink',2,2);           
+        $scale->attach ($l, 1,2,$i+1,$i+2,'expand','shrink',2,2); 
+        $scale->attach (gen_label_in_center("$max"), 1,2,$i+2,$i+3,'expand','shrink',2,2) if($i==4);
+    }
+    return ($table,$scale);
+}
 
 sub generate_heat_map_img_file{
-	my ($d,$image_file,$title)=@_ ;
-	return  if (!defined $d);
-	my %hash=%{$d};		
-	my @data;
-	my @xs = (sort {$a<=>$b} keys %hash);
-	foreach my $y (@xs){
-		my @b;
-  		push (@data ,\@b) if ($y!=0);   
-		foreach my $x (@xs){
-			my @a=($x,$y, $hash{$x}{$y});
-			push (@data ,\@a); 
-		}
-		 
-	}
-		
-my $length = @xs;
-$length+=1;
-
-my $chart = Chart::Gnuplot->new(
-    bg         => 'white',
-    view       => 'map',
-    palette    => 'defined (0 0 0 1, 1 1 1 0, 2 1 0 0)',
-    output     => "$image_file",
-    title      => "$title",
-    xlabel     => 'Endp-ID',
-    ylabel     => 'Endp-ID',
-    xrange	   => [-1, $length],
-    size       => 'ratio -1',
-    xtics      => {
-    	labels   => \@xs,
-    },
-    ytics      => {
-       labels   => \@xs,
-    },
-    mxtics => '2',
-    mytics => '2',
-    border => undef,
-    grid   => 'front mxtics mytics lw 1.5 lt -1 lc rgb \'white\'',
-        
-);
-my $dataSet = Chart::Gnuplot::DataSet->new(
-	points => \@data,
-	view   => 'map',
-  	type   => 'matrix',
-    using  => "1:2:3 with image",	 
-);
-
-
-$chart->plot2d($dataSet);
-	
-	
-	
-	
-	
+    my ($d,$image_file,$title)=@_ ;
+    return  if (!defined $d);
+    my %hash=%{$d};        
+    my @data;
+    my @xs = (sort {$a<=>$b} keys %hash);
+    foreach my $y (@xs){
+        my @b;
+        push (@data ,\@b) if ($y!=0);   
+        foreach my $x (@xs){
+            my @a=($x,$y, $hash{$x}{$y});
+            push (@data ,\@a); 
+        }
+    }
+    my $length = @xs;
+    $length+=1;
+    my $chart = Chart::Gnuplot->new(
+        bg         => 'white',
+        view       => 'map',
+        palette    => 'defined (0 0 0 1, 1 1 1 0, 2 1 0 0)',
+        output     => "$image_file",
+        title      => "$title",
+        xlabel     => 'Endp-ID',
+        ylabel     => 'Endp-ID',
+        xrange       => [-1, $length],
+        size       => 'ratio -1',
+        xtics      => {
+            labels   => \@xs,
+        },
+        ytics      => {
+            labels   => \@xs,
+        },
+        mxtics => '2',
+        mytics => '2',
+        border => undef,
+        grid   => 'front mxtics mytics lw 1.5 lt -1 lc rgb \'white\'',
+    );
+    my $dataSet = Chart::Gnuplot::DataSet->new(
+        points => \@data,
+        view   => 'map',
+        type   => 'matrix',
+        using  => "1:2:3 with image",     
+    );
+    $chart->plot2d($dataSet);
 }
 
 
-
 sub generate_heat_map_dot_file{
-	my ($data,$dim)=@_ ;
-	my $dotfile=
+    my ($data,$dim)=@_ ;
+    my $dotfile=
 "digraph G {
-	graph [layout = neato, rankdir = RL , splines = true, overlap = true]; 
-	node[shape=record];	
-	";
-	for(my $y=0; $y<$dim; $y++){ 		
-		for(my $x=0; $x<$dim; $x++){
-			my $tx=$x*2+0.5;
-			my $ty=($dim-$y-1)*2+0.5;		
-			my $w=2;
-		
-		    $tx/=2;
-			$ty/=2;		
-			$w/=2;
-		
-			
-			$dotfile.="
-					\"t${x}_$y\"[
-	label = \"8822255\"
+    graph [layout = neato, rankdir = RL , splines = true, overlap = true]; 
+    node[shape=record];    
+    ";
+    for(my $y=0; $y<$dim; $y++){         
+        for(my $x=0; $x<$dim; $x++){
+            my $tx=$x*2+0.5;
+            my $ty=($dim-$y-1)*2+0.5;        
+            my $w=2;
+            $tx/=2;
+            $ty/=2;        
+            $w/=2;
+            $dotfile.="
+                    \"t${x}_$y\"[
+    label = \"8822255\"
     pos = \"$tx,$ty!\"
     width =$w
     height=$w  
-	style=filled
-	fontsize=\"12\"
-	fillcolor=orange
+    style=filled
+    fontsize=\"12\"
+    fillcolor=orange
     
 ];
-"					
-		}
-	}
-	
-	$dotfile=$dotfile."\n}\n";
-	return $dotfile;
-	
+"
+        }
+    }
+    $dotfile=$dotfile."\n}\n";
+    return $dotfile;
 }
 
 
-
 sub generate_mesh_dot_file{
-	my $self=shift;
-	
-	my $gtype=$self->object_get_attribute("tile_diagram","gtype");	
-	
-	my $dotfile=
+    my $self=shift;
+    my $gtype=$self->object_get_attribute("tile_diagram","gtype");    
+    my $dotfile=
 "digraph G {
-	graph [layout = neato, rankdir = RL , splines = true, overlap = true]; 
-		
-	
-	node[shape=record];
-	
-	";
-		
+    graph [layout = neato, rankdir = RL , splines = true, overlap = true]; 
+        
+    
+    node[shape=record];
+    
+    ";
+    
 #five_port_router [
-#	label="{ |2| } | {3|R0|1} | { |4|0}"
-#	shape=record
-#	color=blue
-#	style=filled
-#	fillcolor=blue
-#];	
-	
+#    label="{ |2| } | {3|R0|1} | { |4|0}"
+#    shape=record
+#    color=blue
+#    style=filled
+#    fillcolor=blue
+#];    
+    
 #add nodes
-	my $nx=$self->object_get_attribute('noc_param','T1');
-	my $ny=$self->object_get_attribute('noc_param','T2');
-	my $nz=$self->object_get_attribute('noc_param','T3');
-	
-	my ($NE, $NR, $RAw, $EAw, $Fw)  = get_topology_info($self);
-	
-	
-	my $topology=$self->object_get_attribute('noc_param','TOPOLOGY');
-		
-	
-	my $btrace= ($topology eq '"TORUS"' || $topology eq '"RING"');
-	my $oned = ($topology eq '"RING"' || $topology eq '"LINE"');
-	
-	#generate endpoints
-	for(my $y=0; $y<$ny; $y++){ 		
-				for(my $x=0; $x<$nx; $x++){
-					for(my $z=0; $z<$nz; $z++){
-						my $id=($y*$nx+$x)*$nz+$z;						
-						my $offsetx = ($z==0 || $z==3) ? 1.05 : -1.05; 
-						my $offsety = ($z==0 || $z==1) ? -0.85 : +0.85; 
-						my $tx=$x*3+$offsetx;
-						my $ty=($ny-$y-1)*2.5+1+$offsety;
-						$dotfile.=get_record_endp_dot_file("T$id","T$id", "$tx,$ty!");	
-	}}}
-	
-	if($topology eq '"FMESH"' ) {
-		my $tmp = $ny*$nx*$nz;
-		for(my $x=0; $x<$nx; $x++){ 
-			    #top edges
-				my $id=$tmp + $x;
-				my $tx=$x*3;	
-				my $ty=($ny)*2.5-.5;				
-				$dotfile.=get_record_endp_dot_file("T$id","T$id", "$tx,$ty!");
-				get_connected_router_id_to_endp($self,$id);
-				
-				
-				
-				#down edges
-				$id= $tmp + $nx +$x;
-				$tx=$x*3;	
-				$ty=-.5;				
-				$dotfile.=get_record_endp_dot_file("T$id","T$id", "$tx,$ty!");
-		}
-		for(my $y=0; $y<$ny; $y++){ 
-			    #right edges
-				my $id= $tmp + 2*$nx +$y;
-				my $tx=-1.5;		
-				my $ty=($ny-$y-1)*2.5+1;			
-				$dotfile.=get_record_endp_dot_file("T$id","T$id", "$tx,$ty!");
-				
-				
-				#left edges
-				$id= $tmp + 2*$nx+$ny +$y;
-				$tx=$nx*3-1.5;				
-				$ty=($ny-$y-1)*2.5+1;			
-				$dotfile.=get_record_endp_dot_file("T$id","T$id", "$tx,$ty!");
-				
-		}
-	
-	}
-	
-	
-#generate routers	
-	for(my $y=0; $y<$ny; $y++){ 		
-				for(my $x=0; $x<$nx; $x++){
-					my $e0 = '0';
-					my $e1 = ($nz>1)? ( ($oned)? '3':'5') : ' ';
-					my $e2 = ($nz>2)? ( ($oned)? '4':'6') : ' ';
-					my $e3 = ($nz>3)? ( ($oned)? '5':'7') : ' ';
-					
-					my $id=$y*$nx+$x;									
-					my $n = "R${id}";								
-					my $label =  ($oned)?
-					 "\{<p7>$e2 |<p2> |<p8>$e3 \} | \{<p3>2|$n|<p1>1\} | \{<p6>$e1 |<p4> |<p5>$e0\}"
-					:"\{<p7>$e2 |<p2>2|<p8>$e3 \} | \{<p3>3|$n|<p1>1\} | \{<p6>$e1 |<p4>4|<p5>$e0\}";
-					my $xx=$x*3;
-					my $yy=($ny-$y-1)*2.5+1;
-					
-
-
-
-					$dotfile.=get_router_dot_file($n,$label,"$xx,$yy!",$gtype);
-				
-
-				}}							
-	
-
-	$dotfile=$dotfile."\n\n";
-	
-	#add connections
-	for(my $y=0; $y<$ny; $y++){ 		
-		for(my $x=0; $x<$nx; $x++){
-			 
-			 $dotfile=$dotfile.node_connection('R',get_router_num($self,$x,$y),undef,1,'R',get_router_num($self,($x+1),$y),undef,3,$gtype) if($x <$nx-1);	
-			 $dotfile=$dotfile.node_connection('R',get_router_num($self,$x,$y),undef,1,'R',get_router_num($self,0,$y),undef,3,$gtype) if($x == ($nx-1) && $btrace);
-			 $dotfile=$dotfile.node_connection('R',get_router_num($self,$x,$y),undef,2,'R',get_router_num($self,$x,($y-1)),undef,4,$gtype)if($y>0) ; 
-             $dotfile=$dotfile.node_connection('R',get_router_num($self,$x,$y),undef,2,'R',get_router_num($self,$x,($ny-1)),undef,4,$gtype) if($y ==0 && $btrace && !$oned);
-          #   $dotfile=$dotfile.node_connection('R',$x,$y,0,'T',$x,$y);               
-    }}
-if($topology eq '"FMESH"' ) {
-	for(my $id=0; $id<$NE; $id++){ 
-		my $rid= get_connected_router_id_to_endp($self,$id);
-		my $tmp = $nx*$ny*$nz;
-		my $p = ($id<$tmp)? $id%$nz+5 :
-		        ($id<$tmp+$nx)? 2 :
-		        ($id<$tmp+2*$nx)? 4 :
-		        ($id<$tmp+2*$nx+$ny)? 3:1;
-		$dotfile=$dotfile.node_connection('R',$rid,undef,$p,'T',$id,undef,undef,$gtype);               
-	
-	}
-	
-}else{	
-	for(my $id=0; $id<$NE; $id++){ 
-		my $rid=int($id/$nz);
-		my $p =  $id%$nz+5;
-		$dotfile=$dotfile.node_connection('R',$rid,undef,$p,'T',$id,undef,undef,$gtype);               
-	
-	}
-}	
-	$dotfile=$dotfile."\n}\n";
-	return $dotfile;
-
-
-
+    my $nx=$self->object_get_attribute('noc_param','T1');
+    my $ny=$self->object_get_attribute('noc_param','T2');
+    my $nz=$self->object_get_attribute('noc_param','T3');
+    my ($NE, $NR, $RAw, $EAw, $Fw)  = get_topology_info($self);
+    my $topology=$self->object_get_attribute('noc_param','TOPOLOGY');
+    my $btrace= ($topology eq '"TORUS"' || $topology eq '"RING"');
+    my $oned = ($topology eq '"RING"' || $topology eq '"LINE"');
+    #generate endpoints
+    for(my $y=0; $y<$ny; $y++){         
+                for(my $x=0; $x<$nx; $x++){
+                    for(my $z=0; $z<$nz; $z++){
+                        my $id=($y*$nx+$x)*$nz+$z;                        
+                        my $offsetx = ($z==0 || $z==3) ? 1.05 : -1.05; 
+                        my $offsety = ($z==0 || $z==1) ? -0.85 : +0.85; 
+                        my $tx=$x*3+$offsetx;
+                        my $ty=($ny-$y-1)*2.5+1+$offsety;
+                        $dotfile.=get_record_endp_dot_file("T$id","T$id", "$tx,$ty!");    
+    }}}
+    
+    if($topology eq '"FMESH"' ) {
+        my $tmp = $ny*$nx*$nz;
+        for(my $x=0; $x<$nx; $x++){ 
+            #top edges
+            my $id=$tmp + $x;
+            my $tx=$x*3;    
+            my $ty=($ny)*2.5-.5;                
+            $dotfile.=get_record_endp_dot_file("T$id","T$id", "$tx,$ty!");
+            get_connected_router_id_to_endp($self,$id);
+            #down edges
+            $id= $tmp + $nx +$x;
+            $tx=$x*3;    
+            $ty=-.5;                
+            $dotfile.=get_record_endp_dot_file("T$id","T$id", "$tx,$ty!");
+        }
+        for(my $y=0; $y<$ny; $y++){ 
+            #right edges
+            my $id= $tmp + 2*$nx +$y;
+            my $tx=-1.5;        
+            my $ty=($ny-$y-1)*2.5+1;
+            $dotfile.=get_record_endp_dot_file("T$id","T$id", "$tx,$ty!");
+            #left edges
+            $id= $tmp + 2*$nx+$ny +$y;
+            $tx=$nx*3-1.5;
+            $ty=($ny-$y-1)*2.5+1;
+            $dotfile.=get_record_endp_dot_file("T$id","T$id", "$tx,$ty!");
+        }
+    }
+    #generate routers
+    for(my $y=0; $y<$ny; $y++){
+        for(my $x=0; $x<$nx; $x++){
+            my $e0 = '0';
+            my $e1 = ($nz>1)? ( ($oned)? '3':'5') : ' ';
+            my $e2 = ($nz>2)? ( ($oned)? '4':'6') : ' ';
+            my $e3 = ($nz>3)? ( ($oned)? '5':'7') : ' ';
+            my $id=$y*$nx+$x;
+            my $n = "R${id}";
+            my $label =  ($oned)?
+            "\{<p7>$e2 |<p2> |<p8>$e3 \} | \{<p3>2|$n|<p1>1\} | \{<p6>$e1 |<p4> |<p5>$e0\}"
+            :"\{<p7>$e2 |<p2>2|<p8>$e3 \} | \{<p3>3|$n|<p1>1\} | \{<p6>$e1 |<p4>4|<p5>$e0\}";
+            my $xx=$x*3;
+            my $yy=($ny-$y-1)*2.5+1;
+            $dotfile.=get_router_dot_file($n,$label,"$xx,$yy!",$gtype);
+        }
+    }
+    $dotfile=$dotfile."\n\n";
+    #add connections
+    for(my $y=0; $y<$ny; $y++){         
+        for(my $x=0; $x<$nx; $x++){
+            $dotfile=$dotfile.node_connection('R',get_router_num($self,$x,$y),undef,1,'R',get_router_num($self,($x+1),$y),undef,3,$gtype) if($x <$nx-1);    
+            $dotfile=$dotfile.node_connection('R',get_router_num($self,$x,$y),undef,1,'R',get_router_num($self,0,$y),undef,3,$gtype) if($x == ($nx-1) && $btrace);
+            $dotfile=$dotfile.node_connection('R',get_router_num($self,$x,$y),undef,2,'R',get_router_num($self,$x,($y-1)),undef,4,$gtype)if($y>0) ; 
+            $dotfile=$dotfile.node_connection('R',get_router_num($self,$x,$y),undef,2,'R',get_router_num($self,$x,($ny-1)),undef,4,$gtype) if($y ==0 && $btrace && !$oned);
+            #   $dotfile=$dotfile.node_connection('R',$x,$y,0,'T',$x,$y);               
+        }
+    }
+    if($topology eq '"FMESH"' ) {
+        for(my $id=0; $id<$NE; $id++){ 
+            my $rid= get_connected_router_id_to_endp($self,$id);
+            my $tmp = $nx*$ny*$nz;
+            my $p = ($id<$tmp)? $id%$nz+5 :
+                    ($id<$tmp+$nx)? 2 :
+                    ($id<$tmp+2*$nx)? 4 :
+                    ($id<$tmp+2*$nx+$ny)? 3:1;
+            $dotfile=$dotfile.node_connection('R',$rid,undef,$p,'T',$id,undef,undef,$gtype);               
+        }
+    }else{
+        for(my $id=0; $id<$NE; $id++){ 
+            my $rid=int($id/$nz);
+            my $p =  $id%$nz+5;
+            $dotfile=$dotfile.node_connection('R',$rid,undef,$p,'T',$id,undef,undef,$gtype);               
+        }
+    }
+    $dotfile=$dotfile."\n}\n";
+    return $dotfile;
 }
 
+
 sub get_endp_pos {
-	my $self=shift;
-	my $topology=$self->object_get_attribute('noc_param','TOPOLOGY');
-	my ($NE, $NR, $RAw, $EAw, $Fw) = get_topology_info($self);
-	my %pos;
-	if($topology eq '"FATTREE"' || $topology eq '"TREE"'){
-		
-		for(my $i=0; $i<$NE; $i++){
-			    $pos{$i} = "\"$i,0!\"";
-	    }
-		return %pos;
-	}
-	#($topology eq '"TORUS"' || $topology eq '"RING"' || $topology eq '"RING"' || $topology eq '"LINE"');	
-	
-	my $nx=$self->object_get_attribute('noc_param','T1');
-	my $ny=$self->object_get_attribute('noc_param','T2');
-	my $nz=$self->object_get_attribute('noc_param','T3');		
-		
-	
-	#generate endpoints
-	for(my $y=0; $y<$ny; $y++){ 		
-				for(my $x=0; $x<$nx; $x++){
-					for(my $z=0; $z<$nz; $z++){
-						my $id=($y*$nx+$x)*$nz+$z;						
-						my $offsetx = ($z==0 || $z==3) ? 1.05 : -1.05; 
-						my $offsety = ($z==0 || $z==1) ? -0.85 : +0.85; 
-						my $tx=$x*3+$offsetx;
-						my $ty=($ny-$y-1)*2.5+1+$offsety;
-						$pos{$id} = "\"$tx,$ty!\"";
-					}
-				}
-	}
-		return %pos;
+    my $self=shift;
+    my $topology=$self->object_get_attribute('noc_param','TOPOLOGY');
+    my ($NE, $NR, $RAw, $EAw, $Fw) = get_topology_info($self);
+    my %pos;
+    if($topology eq '"FATTREE"' || $topology eq '"TREE"'){
+        for(my $i=0; $i<$NE; $i++){
+                $pos{$i} = "\"$i,0!\"";
+        }
+        return %pos;
+    }
+    #($topology eq '"TORUS"' || $topology eq '"RING"' || $topology eq '"RING"' || $topology eq '"LINE"');    
+    my $nx=$self->object_get_attribute('noc_param','T1');
+    my $ny=$self->object_get_attribute('noc_param','T2');
+    my $nz=$self->object_get_attribute('noc_param','T3');        
+    #generate endpoints
+    for(my $y=0; $y<$ny; $y++){         
+        for(my $x=0; $x<$nx; $x++){
+            for(my $z=0; $z<$nz; $z++){
+                my $id=($y*$nx+$x)*$nz+$z;                        
+                my $offsetx = ($z==0 || $z==3) ? 1.05 : -1.05; 
+                my $offsety = ($z==0 || $z==1) ? -0.85 : +0.85; 
+                my $tx=$x*3+$offsetx;
+                my $ty=($ny-$y-1)*2.5+1+$offsety;
+                $pos{$id} = "\"$tx,$ty!\"";
+            }
+        }
+    }
+    return %pos;
 }
 
 sub get_record_endp_dot_file {
-	my ($name,$label,$pos)=@_;
-
+    my ($name,$label,$pos)=@_;
 return "$name\[
-	label = \"$label\"
+    label = \"$label\"
     pos = \"$pos\"
     shape=record
-	color=orange
-	style=filled
-	fillcolor=orange
+    color=orange
+    style=filled
+    fillcolor=orange
 ];
-"
-;
+";
 }
 
 sub get_router_dot_file {
-	my ($name,$label,$pos,$type)=@_;
-	
-	
-	return ($type eq 'comp')? "\"$name\"\[
-	label=\"$label\"
+    my ($name,$label,$pos,$type)=@_;
+    return ($type eq 'comp')? "\"$name\"\[
+    label=\"$label\"
     pos = \"$pos\"
     shape=record
-	color=blue
-	style=filled
-	fillcolor=blue
-];	
+    color=blue
+    style=filled
+    fillcolor=blue
+];
 "
 : 
 "\"$name\"\[
-	label=\"$name\"
+    label=\"$name\"
     pos = \"$pos\"
     shape=circle
-	color=blue
-	style=filled
-	fillcolor=blue
-];	
-"
-;	
-	
-	
+    color=blue
+    style=filled
+    fillcolor=blue
+];
+";
 }
 
 sub generate_fattree_dot_file{
-	my $self=shift;
-	my $gtype=$self->object_get_attribute("tile_diagram","gtype");	
-	
-		
-	my $dotfile=
+    my $self=shift;
+    my $gtype=$self->object_get_attribute("tile_diagram","gtype");    
+    my $dotfile=
 "digraph G {
-	graph [layout = neato, rankdir = LR , splines = true, overlap = true]; 	
-	node[shape=record];	
-	";
-		
+    graph [layout = neato, rankdir = LR , splines = true, overlap = true];     
+    node[shape=record];    
+    ";
 #add nodes
     my ($NE, $NR, $RAw, $EAw, $Fw)=get_topology_info($self);
-
-	my $k=$self->object_get_attribute('noc_param','T1');
-	my $nl=$self->object_get_attribute('noc_param','T2');
-	my @bp;
-	my @hp;
-	for(my $p=0; $p<$k; $p++) {push (@bp,"<p$p>$p");}
-	for(my $p=$k; $p<2*$k; $p++) {push (@hp,"<p$p>$p");}
-	my $bp= join("|",@bp);
-	my $hp= join("|",@hp);
-	#my $NC= powi( $k,$nl  ); #total endpoints
-	my $NL= $NE/$k ; #number of nodes in  each layer 
-
-
-#add endpoints
-for(my $i=0; $i<$NE; $i++){
-	my $x=$i%$k;
-	my $y=int($i/$k); 		
-
+    my $k=$self->object_get_attribute('noc_param','T1');
+    my $nl=$self->object_get_attribute('noc_param','T2');
+    my @bp;
+    my @hp;
+    for(my $p=0; $p<$k; $p++) {push (@bp,"<p$p>$p");}
+    for(my $p=$k; $p<2*$k; $p++) {push (@hp,"<p$p>$p");}
+    my $bp= join("|",@bp);
+    my $hp= join("|",@hp);
+    #my $NC= powi( $k,$nl  ); #total endpoints
+    my $NL= $NE/$k ; #number of nodes in  each layer 
+    #add endpoints
+    for(my $i=0; $i<$NE; $i++){
+        my $x=$i%$k;
+        my $y=int($i/$k);
 $dotfile=$dotfile."T$i\[
-	label = \"T$i\"
+    label = \"T$i\"
     pos = \"$i,0!\"
     shape=house
     margin=0
-	color=orange
-	style=filled
-	fillcolor=orange
+    color=orange
+    style=filled
+    fillcolor=orange
 ];
 ";
-	}
-
-	#add roots
-	for(my $pos=0; $pos<$NL; $pos++){ 
-		my $x=($k)*$pos+($k/2)-0.5;	
-		my $y=	1.5*($nl-1)+1;	
-		my $r=$pos;
-		my $label = "\{R$r\}|\{$bp\}";
-		
-		$dotfile.=get_router_dot_file("R$r",$label,"$x,$y!",$gtype);
-		
-	}
-
-	#add leaves
-	for(my $l=1; $l<$nl; $l++){ 
-	for(my $pos=0; $pos<$NL; $pos++){ 
-		my $x=($k)*$pos+($k/2)-0.5;	
-		my $y=	1.5*($nl-$l-1)+1;	
-		my $r=$NL*$l+$pos;
-		my $label = "\{$hp\}|\{R$r\}|\{$bp\}";
-		
-		$dotfile.=get_router_dot_file("R$r",$label,"$x,$y!",$gtype);
-			 
-	}
-	}	
-
-
-
-	#connect all down input chanels
-	my $n=$nl;
-	my $nPos = powi( $k, $n-1);
-	my $chan_per_direction = ($k * powi( $k , $n-1 )); #up or down
-	my $chan_per_level = 2*($k * powi( $k , $n-1 )); #up+down
-	
-	for (my $level = 0; $level<$n-1; $level++){
-	    #input chanel are numbered interleavely, the interleaev depends on level
-	    my $routers_per_neighborhood = powi($k,$n-1-($level)); 
-	    my $routers_per_branch = powi($k,$n-1-($level+1)); 
-	    my $level_offset = $routers_per_neighborhood*$k;
-	    for ( my $pos = 0; $pos < $nPos; ++$pos ) {
-			my $neighborhood = int($pos/$routers_per_neighborhood);
-			my $neighborhood_pos = $pos % $routers_per_neighborhood;
-			for ( my $port = 0; $port < $k; ++$port ) {
-				my $link = 
-					(($level+1)*$chan_per_level - $chan_per_direction)  #which levellevel
-		  			+$neighborhood*$level_offset   #region in level
-		  			+$port*$routers_per_branch*$k  #sub region in region
-		 			+($neighborhood_pos)%$routers_per_branch*$k  #router in subregion
-		 			+($neighborhood_pos)/$routers_per_branch; #port on router
-	
-	#int link = (level*chan_per_level - chan_per_direction) + pos*k + port ;
-				my $connect_l= int(($link+$chan_per_direction)/$chan_per_level);
-				my $tmp=(($link+$chan_per_direction) % $chan_per_level);
-				my $connect_pos= int($tmp/$k);
-				my $connect_port= ($tmp%$k)+$k;
-				my $id1=$NL*$level+$pos;
-				my $connect_id=$NL*$connect_l+$connect_pos;
-				$dotfile=$dotfile.node_connection('R',$id1,undef,$port,'R',$connect_id,undef,$connect_port,$gtype);	
-			}
-	    }
-	}
-
-	#add endpoints connection
-	for(my $i=0; $i<$NE; $i++){ 
-		my $r= $NL*($nl-1)+int($i/$k);
-		 $dotfile=$dotfile.node_connection('T',$i,undef,undef,'R',$r,undef,$i%($k),$gtype);	
-	
-	}
-	$dotfile=$dotfile."\n}\n";
-	return $dotfile;
+    }
+    #add roots
+    for(my $pos=0; $pos<$NL; $pos++){ 
+        my $x=($k)*$pos+($k/2)-0.5;    
+        my $y=    1.5*($nl-1)+1;    
+        my $r=$pos;
+        my $label = "\{R$r\}|\{$bp\}";
+        $dotfile.=get_router_dot_file("R$r",$label,"$x,$y!",$gtype);
+    }
+    #add leaves
+    for(my $l=1; $l<$nl; $l++){ 
+        for(my $pos=0; $pos<$NL; $pos++){ 
+            my $x=($k)*$pos+($k/2)-0.5;    
+            my $y=    1.5*($nl-$l-1)+1;    
+            my $r=$NL*$l+$pos;
+            my $label = "\{$hp\}|\{R$r\}|\{$bp\}";
+            $dotfile.=get_router_dot_file("R$r",$label,"$x,$y!",$gtype);
+        }
+    }
+    #connect all down input chanels
+    my $n=$nl;
+    my $nPos = powi( $k, $n-1);
+    my $chan_per_direction = ($k * powi( $k , $n-1 )); #up or down
+    my $chan_per_level = 2*($k * powi( $k , $n-1 )); #up+down
+    for (my $level = 0; $level<$n-1; $level++){
+        #input chanel are numbered interleavely, the interleaev depends on level
+        my $routers_per_neighborhood = powi($k,$n-1-($level)); 
+        my $routers_per_branch = powi($k,$n-1-($level+1)); 
+        my $level_offset = $routers_per_neighborhood*$k;
+        for ( my $pos = 0; $pos < $nPos; ++$pos ) {
+            my $neighborhood = int($pos/$routers_per_neighborhood);
+            my $neighborhood_pos = $pos % $routers_per_neighborhood;
+            for ( my $port = 0; $port < $k; ++$port ) {
+                my $link = 
+                    (($level+1)*$chan_per_level - $chan_per_direction)  #which levellevel
+                    +$neighborhood*$level_offset   #region in level
+                    +$port*$routers_per_branch*$k  #sub region in region
+                    +($neighborhood_pos)%$routers_per_branch*$k  #router in subregion
+                    +($neighborhood_pos)/$routers_per_branch; #port on router
+    #int link = (level*chan_per_level - chan_per_direction) + pos*k + port ;
+                my $connect_l= int(($link+$chan_per_direction)/$chan_per_level);
+                my $tmp=(($link+$chan_per_direction) % $chan_per_level);
+                my $connect_pos= int($tmp/$k);
+                my $connect_port= ($tmp%$k)+$k;
+                my $id1=$NL*$level+$pos;
+                my $connect_id=$NL*$connect_l+$connect_pos;
+                $dotfile=$dotfile.node_connection('R',$id1,undef,$port,'R',$connect_id,undef,$connect_port,$gtype);    
+            }
+        }
+    }
+    #add endpoints connection
+    for(my $i=0; $i<$NE; $i++){ 
+        my $r= $NL*($nl-1)+int($i/$k);
+        $dotfile=$dotfile.node_connection('T',$i,undef,undef,'R',$r,undef,$i%($k),$gtype);    
+    }
+    $dotfile=$dotfile."\n}\n";
+    return $dotfile;
 }
 
 sub generate_star_dot_file{
-	my $self=shift;
-		
-	my $dotfile=
+    my $self=shift;
+    my $dotfile=
 "digraph G {
-	graph [layout = neato, fontsize=3, rankdir = LR , splines = true, overlap = false]; 	
-	node[shape=record];	
-	";
-	
-	my $pnum=$self->object_get_attribute('noc_param','T1');
-	$dotfile.=router_node_dot_sim($pnum,"R","R");	
-	
-	for(my $p=0; $p<$pnum; $p++) {
-	$dotfile.=endp_node_dot_sim ("T$p","T$p");
-	$dotfile.="R -> T$p [dir=none];\n";
-	$dotfile.='#'.node_connection('T',$p,undef,undef,'R',0,undef,$p);
-	}
-	
-	$dotfile.="\n}\n";
-	return $dotfile;
+    graph [layout = neato, fontsize=3, rankdir = LR , splines = true, overlap = false];     
+    node[shape=record];    
+    ";
+    my $pnum=$self->object_get_attribute('noc_param','T1');
+    $dotfile.=router_node_dot_sim($pnum,"R","R");    
+    for(my $p=0; $p<$pnum; $p++) {
+        $dotfile.=endp_node_dot_sim ("T$p","T$p");
+        $dotfile.="R -> T$p [dir=none];\n";
+        $dotfile.='#'.node_connection('T',$p,undef,undef,'R',0,undef,$p);
+    }
+    $dotfile.="\n}\n";
+    return $dotfile;
 }
 
 
-
-
-
-
-
-
-
-
-
-
 sub generate_tree_dot_file{
-	my $self=shift;
-	my $gtype=$self->object_get_attribute("tile_diagram","gtype");	
-		
-	my $dotfile=
+    my $self=shift;
+    my $gtype=$self->object_get_attribute("tile_diagram","gtype");    
+    my $dotfile=
 "digraph G {
-	graph [layout = neato, rankdir = LR , splines = true, overlap = true]; 	
-	node[shape=record];	
-	";
-		
-
-	my $k=$self->object_get_attribute('noc_param','T1');
-	my $nl=$self->object_get_attribute('noc_param','T2');
-	#generate routres port interface
-	my @bp;
-	my @hp;
-	for(my $p=0; $p<$k; $p++) {
-		push (@bp,"<n$p>") if(($k%2)==0 && $p==$k/2);#if k is odd number add one empty space in the middle
-		push (@bp,"<p$p>$p");
-		
-	}
-	for(my $p=$k; $p<2*$k; $p++) {
-		if($p==$k+int(($k-1)/2)){
-			push (@hp,"<n$p>") if(($k%2)==0);#if k is odd number add one empty space in the middle
-			push (@hp,"<p$k>$k");
-		}else{
-			push (@hp,"<n$p>"); 
-		}
-	}	
-	my $bp= join("|",@bp);
-	my $hp= join("|",@hp);
-#	my ($NE,$NR)=get_topology_info($self);
-	my ($NE, $NR, $RAw, $EAw, $Fw) = get_topology_info($self);
-
-
-	#add endpoints
-	for(my $i=0; $i<$NE; $i++){
-		$dotfile=$dotfile."T$i\[
-	label = \"T$i\"
+    graph [layout = neato, rankdir = LR , splines = true, overlap = true];     
+    node[shape=record];    
+    ";
+    my $k=$self->object_get_attribute('noc_param','T1');
+    my $nl=$self->object_get_attribute('noc_param','T2');
+    #generate routres port interface
+    my @bp;
+    my @hp;
+    for(my $p=0; $p<$k; $p++) {
+        push (@bp,"<n$p>") if(($k%2)==0 && $p==$k/2);#if k is odd number add one empty space in the middle
+        push (@bp,"<p$p>$p");
+    }
+    for(my $p=$k; $p<2*$k; $p++) {
+        if($p==$k+int(($k-1)/2)){
+            push (@hp,"<n$p>") if(($k%2)==0);#if k is odd number add one empty space in the middle
+            push (@hp,"<p$k>$k");
+        }else{
+            push (@hp,"<n$p>"); 
+        }
+    }
+    my $bp= join("|",@bp);
+    my $hp= join("|",@hp);
+    #    my ($NE,$NR)=get_topology_info($self);
+    my ($NE, $NR, $RAw, $EAw, $Fw) = get_topology_info($self);
+    # add endpoints
+    for(my $i=0; $i<$NE; $i++){
+        $dotfile=$dotfile."T$i\[
+    label = \"T$i\"
     pos = \"$i,0!\"
     shape=house
     margin=0
-	color=orange
-	style=filled
-	fillcolor=orange
+    color=orange
+    style=filled
+    fillcolor=orange
 ];
 ";
-	}
-
-	#add roots
-	my $label = "\{R0\}|\{$bp\}";
-	my $x=(($NE-1)/2);
-	my $y=	1.5*($nl-1)+1;
-	$dotfile.=get_router_dot_file("R0",$label,"$x,$y!",$gtype);
-	
-	
-	
-	#add leaves
-	my $t=1;
-	
-	for(my $l=$nl-1; $l>0; $l--){ 
-		my $NL = powi($k,$l);
-		$t*=$k;
-		for(my $pos=0; $pos<$NL; $pos++){ 			
-			my $x= 	$t*$pos + ($t-1)/2 ;
-			my $y=	1.5*($nl-$l)-.5;
-			my $r=sum_powi($k,$l)+$pos;
-	my $label = "\{$hp\}|\{R$r\}|\{$bp\}";
-	
-	$dotfile.=get_router_dot_file("R$r",$label,"$x,$y!",$gtype);
-	
-	 
-		}
-	}	
-	
-	#add leave connections
-	for(my $l=$nl-1; $l>0; $l--){ 
-		my $NL = powi($k,$l);
-		for(my $pos=0; $pos<$NL; $pos++){ 
-			my $id1=sum_powi($k,$l)+$pos;
-			my $id2=sum_powi($k,$l-1)+int($pos/$k);
-			$dotfile=$dotfile.node_connection('R',$id1,undef,$k,'R',$id2,undef,$pos % $k,$gtype);	
-		}
-	}
-	
-	#add endpoints connection
-	for(my $i=0; $i<$NE; $i++){ 
-		 my $r= sum_powi($k,$nl-1)+int($i/$k);
-		 $dotfile=$dotfile.node_connection('T',$i,undef,undef,'R',$r,undef,$i%($k),$gtype);	
-	
-	}
-	
-	
+    }
+    # add roots
+    my $label = "\{R0\}|\{$bp\}";
+    my $x=(($NE-1)/2);
+    my $y=    1.5*($nl-1)+1;
+    $dotfile.=get_router_dot_file("R0",$label,"$x,$y!",$gtype);
+    # add leaves
+    my $t=1;
+    for(my $l=$nl-1; $l>0; $l--){ 
+        my $NL = powi($k,$l);
+        $t*=$k;
+        for(my $pos=0; $pos<$NL; $pos++){             
+            my $x=     $t*$pos + ($t-1)/2 ;
+            my $y=    1.5*($nl-$l)-.5;
+            my $r=sum_powi($k,$l)+$pos;
+            my $label = "\{$hp\}|\{R$r\}|\{$bp\}";
+            $dotfile.=get_router_dot_file("R$r",$label,"$x,$y!",$gtype);
+        }
+    }
+    # add leave connections
+    for(my $l=$nl-1; $l>0; $l--){ 
+        my $NL = powi($k,$l);
+        for(my $pos=0; $pos<$NL; $pos++){ 
+            my $id1=sum_powi($k,$l)+$pos;
+            my $id2=sum_powi($k,$l-1)+int($pos/$k);
+            $dotfile=$dotfile.node_connection('R',$id1,undef,$k,'R',$id2,undef,$pos % $k,$gtype);    
+        }
+    }
+    # add endpoints connection
+    for(my $i=0; $i<$NE; $i++){ 
+        my $r= sum_powi($k,$nl-1)+int($i/$k);
+        $dotfile=$dotfile.node_connection('T',$i,undef,undef,'R',$r,undef,$i%($k),$gtype);    
+    }
+    $dotfile=$dotfile."\n}\n";
+    return $dotfile;
+}
 
-	$dotfile=$dotfile."\n}\n";
-	return $dotfile;
+sub generate_3d_mesh_dot_file {
+    my $self=shift;
+    my $x_dim=$self->object_get_attribute('noc_param','T1');
+    my $y_dim=$self->object_get_attribute('noc_param','T2');
+    my $z_dim=$self->object_get_attribute('noc_param','T3');
+    my $l_num=$self->object_get_attribute('noc_param','T4');  
+    # print "Generating 3D mesh dot file with dimensions: ${x_dim}x${y_dim}x${z_dim}, L_num=$l_num\n";  
+    my $dotfile.="digraph G {\n";
+    $dotfile.="    graph [ layout = neato, rankdir = LR , splines = true, overlap = false];\n";
+    $dotfile.="    node [shape=parallelogram, style=filled, color=orange, fillcolor=skyblue];\n";
+    $dotfile.="    graph [splines=line, overlap=true];\n\n";
+    my $node_size="width=1, height=.5, fixedsize=true";
+    my $x_shift_per_layer = 0;  # shift each layer slightly right
+    my $x_shift_per_row = .5;  # shift each row slightly right
+    my $x_gap_mulply = 1.3; # increase the gap between two adjacent nodes in x dir
+    my $y_gap_mulply = 1.1; # increase the gap between two adjacent nodes in y dir
+    # Generate nodes with pos attributes
+    my $v=$z_dim*$y_dim*$x_dim;
+    for my $zz (0..$z_dim-1) {
+        for my $yy (0..$y_dim-1) {
+            for my $xx (0..$x_dim-1) {
+                my $x = $xx;
+                my $y = $y_dim-$yy-1;
+                my $z = $z_dim-$zz-1;
+                my $node_name = "N_${xx}_${yy}_${zz}";               
+                # X shifted by layer index, Y shifted by row + layer offset
+                my $x_pos = $x*$x_gap_mulply + $z * $x_shift_per_layer - $y * $x_shift_per_row;
+                my $y_pos = $y*$y_gap_mulply + $z * ($y_dim*$y_gap_mulply +.25);  # space between layers
+                my $len = length("$v");
+                my $Rnum=$xx + ($yy*$x_dim) + ($zz * $x_dim * $y_dim);
+                my $Rlable = sprintf("R%-${len}d", $Rnum);
+                $dotfile.= "    $node_name [label=\"$Rlable\", pos=\"$x_pos,$y_pos!\" $node_size];\n";
+                for my $ll (0..$l_num-1){
+                    my $Tx_pos =($ll==0 || $ll==2)? $x_pos-0.4 : $x_pos+0.3;
+                    my $Ty_pos =($ll==0 || $ll==1)? $y_pos-0.3 : $y_pos+0.3;
+                    my $Tnum = $ll+($Rnum*$l_num);
+                    my $endp_name = "T_${xx}_${yy}_${zz}_$ll";
+                    $dotfile.=
+"   $endp_name [
+    label=\"T$Tnum\", 
+    pos=\"$Tx_pos,$Ty_pos!\",
+    shape=box,
+    style=filled,
+    fillcolor=orange,
+    width=0,       // 0 means auto
+    height=0,      // 0 means auto
+    fixedsize=false,
+    margin=0.01    // small margin around text
+];
+";
+                }             
+            }
+        }
+    }
+    $dotfile.= "\n";
+    # Connect nodes in X, Y, Z directions
+    for my $z (0..$z_dim-1) {
+        for my $y (0..$y_dim-1) {
+            for my $x (0..$x_dim-1) {
+                my $node = "N_${x}_${y}_${z}";
+                # X direction
+                if ($x < $x_dim-1) {
+                    my $neighbor = "N_" . ($x+1) . "_$y\_$z";
+                    $dotfile.= "    $node -> $neighbor [dir=none];\n";
+                }
+                # Y direction
+                if ($y < $y_dim-1) {
+                    my $neighbor = "N_${x}_" . ($y+1) . "_$z";
+                    $dotfile.= "    $node -> $neighbor [dir=none];\n";
+                }
+                # Z direction
+                if ($z < $z_dim-1) {
+                    my $neighbor = "N_${x}_${y}_" . ($z+1);
+                    $dotfile.= "    $node -> $neighbor [dir=none, style=dashed, constraint=false];\n";
+                }
+            }
+        }
+    }
+    $dotfile.= "\n";
+    # Invisible edges for column alignment
+    for my $z (0..$z_dim-1) {
+        for my $x (0..$x_dim-1) {
+            for my $y (0..$y_dim-2) {
+                my $from = "N_${x}_${y}_${z}";
+                my $to   = "N_${x}_" . ($y+1) . "_$z";
+                $dotfile.= "    $from -> $to [style=invis];\n";
+            }
+        }
+    }
+    $dotfile.= "}\n";
+    return $dotfile;
 }
 
 
 sub get_topology_dot_file{
-	my $self=shift;
-	my $topology=$self->object_get_attribute('noc_param','TOPOLOGY');
-	return generate_mesh_dot_file ($self) if($topology eq '"RING"' || $topology eq '"LINE"' || $topology eq '"MESH"'|| $topology eq '"FMESH"' || $topology eq '"TORUS"' );
-	return generate_fattree_dot_file ($self) if($topology eq '"FATTREE"');
-	return generate_tree_dot_file($self) if($topology eq '"TREE"');
-	return generate_star_dot_file($self) if($topology eq '"STAR"');
-	
+    my $self=shift;
+    my $topology=$self->object_get_attribute('noc_param','TOPOLOGY');
+    return generate_mesh_dot_file ($self) if($topology eq '"RING"' || $topology eq '"LINE"' || $topology eq '"MESH"'|| $topology eq '"FMESH"' || $topology eq '"TORUS"' );
+    return generate_fattree_dot_file ($self) if($topology eq '"FATTREE"');
+    return generate_tree_dot_file($self) if($topology eq '"TREE"');
+    return generate_star_dot_file($self) if($topology eq '"STAR"');
+    return generate_3d_mesh_dot_file($self) if($topology eq '"MESH_3D"');
 }
 
 
 sub generate_merge_actor_dot_file{
-	my $self=shift;
-	my $dotfile=
+    my $self=shift;
+    my $dotfile=
 "digraph G {
-	graph [ layout = neato, rankdir = LR , splines=polyline, overlap = false]; 
-	
+    graph [ layout = neato, rankdir = LR , splines=polyline, overlap = false]; 
+    
 ";
-	
-
-	
 #add connections
-
-	my @traces= get_trace_list($self,'merge');
-	my %src_dst;
-	my %dests= get_destport_constant_list ($self,'merge');
-	my %srcs = get_srcport_constant_list  ($self,'merge');
-	
-	
-	
-	foreach my $p (@traces){
-		my ($src,$dst, $Mbytes, $file_id, $file_name,$init_weight,$min_pck, $max_pck,  $burst, $injct_rate, $injct_rate_var,$src_port,$dst_port,$buff_size,$chanel,$vc,$class)
-				=get_trace($self,'merge',$p);
-				
-		
-						
-		$dotfile=$dotfile."\"$src\" -> \"$dst\"  [label=\"$srcs{$src}{$src_port}{$chanel}->$dests{$dst}{$dst_port}\" ];\n";	
-	}
-	
-	$dotfile=$dotfile."\n}\n";
-	return $dotfile;
-	
+    my @traces= get_trace_list($self,'merge');
+    my %src_dst;
+    my %dests= get_destport_constant_list ($self,'merge');
+    my %srcs = get_srcport_constant_list  ($self,'merge');
+    foreach my $p (@traces){
+        my ($src,$dst, $Mbytes, $file_id, $file_name,$init_weight,$min_pck, $max_pck,  $burst, $injct_rate, $injct_rate_var,$src_port,$dst_port,$buff_size,$chanel,$vc,$class)
+                =get_trace($self,'merge',$p);
+        $dotfile=$dotfile."\"$src\" -> \"$dst\"  [label=\"$srcs{$src}{$src_port}{$chanel}->$dests{$dst}{$dst_port}\" ];\n";    
+    }
+    $dotfile=$dotfile."\n}\n";
+    return $dotfile;
 }
-
-
-
-
-
-
-
-
-
-return 1;
+return 1;
\ No newline at end of file
diff --git a/mpsoc/perl_gui/lib/perl/drag_drop.pl b/mpsoc/perl_gui/lib/perl/drag_drop.pl
index 5055b6f..32714d0 100644
--- a/mpsoc/perl_gui/lib/perl/drag_drop.pl
+++ b/mpsoc/perl_gui/lib/perl/drag_drop.pl
@@ -1,185 +1,144 @@
 #! /usr/bin/perl -w
-
 use strict;
 use constant::boolean;
-
-
 use FindBin;
 use lib $FindBin::Bin;
 require "widget.pl";
 use POSIX qw(ceil floor);
-
-
 #Declare our columns
 use constant C_MARKUP               => 0;
 use constant C_PIXBUF               => 1;
-
-
 #Declare our IDENDTIFIER ID's
 use constant ID_ICONVIEW            => 48;
 
-
-
-
-
-
 sub drag_and_drop_page {
-	my ($self,$tview,$name,$items_ref, $ctrl_box)=@_;
+    my ($self,$tview,$name,$items_ref, $ctrl_box)=@_;
     my $vbox = def_vbox(FALSE,5);
-	my $group_num=$self->object_get_attribute($name,'group_num');
-	update_group_item_list($self,$group_num,$name,$items_ref);
-	my $ref_source = $self->object_get_attribute("$name",'ungrouped');
+    my $group_num=$self->object_get_attribute($name,'group_num');
+    update_group_item_list($self,$group_num,$name,$items_ref);
+    my $ref_source = $self->object_get_attribute("$name",'ungrouped');
     my $lb=$self->object_get_attribute($name,'lable');
     my ($win,$list_store)=create_iconview($self,"$lb",'NO', $ref_source,$name,'ungrouped',undef);
     my $table = def_table($group_num%8,$group_num/8,FALSE);
     my $dim_y = floor(sqrt($group_num));
-  	my $gname=$self->object_get_attribute("$name",'group_name_root');	
-	my $editable =$self->object_get_attribute("$name",'group_name_editble');	  	
-  	my $limit=$self->object_get_attribute($name,'map_limit');
-  	for (my $i=0; $i<$group_num;$i++){
-  		
-  			my $ref_grp = $self->object_get_attribute("$name","$gname($i)");  			
-  			
-    		my ($gwin,$list_store)=create_iconview($self,"$gname($i)",$editable,$ref_grp,$name,"$gname($i)",$limit );
-    		my $y= int($i/$dim_y);
-    		my $x= $i % $dim_y;    		
-	        $table->attach_defaults ($gwin, $x, $x+1 , $y, $y+1);
+    my $gname=$self->object_get_attribute("$name",'group_name_root');
+    my $editable =$self->object_get_attribute("$name",'group_name_editble');
+    my $limit=$self->object_get_attribute($name,'map_limit');
+    for (my $i=0; $i<$group_num;$i++){
+        my $ref_grp = $self->object_get_attribute("$name","$gname($i)");
+        my ($gwin,$list_store)=create_iconview($self,"$gname($i)",$editable,$ref_grp,$name,"$gname($i)",$limit );
+        my $y= int($i/$dim_y);
+        my $x= $i % $dim_y;
+        $table->attach_defaults ($gwin, $x, $x+1 , $y, $y+1);
     }
-   my $sw = add_widget_to_scrolled_win($table);
-   
-   my  $v_paned=gen_vpaned($win,.2,$sw);
-   my  $h_paned= (defined $ctrl_box)? gen_hpaned_adj($self,$v_paned,.5,$ctrl_box, "drag.$name") : $v_paned;   
-
-$vbox->add($h_paned);
-$vbox->show_all();
-return $vbox;
+    my $sw = add_widget_to_scrolled_win($table);
+    my  $v_paned=gen_vpaned($win,.2,$sw);
+    my  $h_paned= (defined $ctrl_box)? gen_hpaned_adj($self,$v_paned,.5,$ctrl_box, "drag.$name") : $v_paned;
+    $vbox->add($h_paned);
+    $vbox->show_all();
+    return $vbox;
 }
 
 sub get_item_group_name{
-	my ($self,$name,$item)=@_;
-	#print "($self,$name,$item)\n";
-	my $group_num=$self->object_get_attribute("$name",'group_num');
-	my $gname=$self->object_get_attribute("$name",'group_name_root');
-	for(my $i=0;$i<$group_num;$i=$i+1){
-		my $gref = $self->object_get_attribute("$name","$gname($i)");
-		next if(! defined $gref);
-		return $self->object_get_attribute("$name","$gname($i)".'_name') if( check_scolar_exist_in_array($item,$gref ));
-	}	
-	return $item;
+    my ($self,$name,$item)=@_;
+    #print "($self,$name,$item)\n";
+    my $group_num=$self->object_get_attribute("$name",'group_num');
+    my $gname=$self->object_get_attribute("$name",'group_name_root');
+    for(my $i=0;$i<$group_num;$i=$i+1){
+        my $gref = $self->object_get_attribute("$name","$gname($i)");
+        next if(! defined $gref);
+        return $self->object_get_attribute("$name","$gname($i)".'_name') if( check_scolar_exist_in_array($item,$gref ));
+    }
+    return $item;
 }
 
 sub get_items_in_a_group{
-	my ($self,$name,$group_name)=@_;
-	my $group_num=$self->object_get_attribute("$name",'group_num');
-	my $gname=$self->object_get_attribute("$name",'group_name_root');
-	for(my $i=0;$i<$group_num;$i=$i+1){
-		my $current_name= $self->object_get_attribute("$name","$gname($i)".'_name');
-		return  $self->object_get_attribute("$name","$gname($i)") if($current_name eq $group_name );
-	}	
-	return undef;	
+    my ($self,$name,$group_name)=@_;
+    my $group_num=$self->object_get_attribute("$name",'group_num');
+    my $gname=$self->object_get_attribute("$name",'group_name_root');
+    for(my $i=0;$i<$group_num;$i=$i+1){
+        my $current_name= $self->object_get_attribute("$name","$gname($i)".'_name');
+        return  $self->object_get_attribute("$name","$gname($i)") if($current_name eq $group_name );
+    }
+    return undef;
 }
 
-
 sub update_group_item_list{
-	my ($self,$group_num,$name,$items_ref)=@_;
-	#get the list of current items
-	my @items = (defined $items_ref) ? @{$items_ref}:();
-	my @items_grouped;
-	my $gname=$self->object_get_attribute("$name",'group_name_root');
-	#update groaped_list
-	for(my $i=0;$i<$group_num;$i=$i+1){
-		my $gref = $self->object_get_attribute("$name","$gname($i)");
-		next if(! defined $gref);
-		my @grouped =  @{$gref};
-		@grouped=get_common_array(\@grouped,\@items);		
-		$self->object_add_attribute("$name","$gname($i)",\@grouped);		
-		push (@items_grouped,@grouped);
-	}	
-	#@items_ungroaped= @items - @items_groaped
-	my @items_ungrouped= get_diff_array(\@items ,\@items_grouped);
-	$self->object_add_attribute("$name",'ungrouped',\@items_ungrouped);	
+    my ($self,$group_num,$name,$items_ref)=@_;
+    #get the list of current items
+    my @items = (defined $items_ref) ? @{$items_ref}:();
+    my @items_grouped;
+    my $gname=$self->object_get_attribute("$name",'group_name_root');
+    #update groaped_list
+    for(my $i=0;$i<$group_num;$i=$i+1){
+        my $gref = $self->object_get_attribute("$name","$gname($i)");
+        next if(! defined $gref);
+        my @grouped =  @{$gref};
+        @grouped=get_common_array(\@grouped,\@items);
+        $self->object_add_attribute("$name","$gname($i)",\@grouped);
+        push (@items_grouped,@grouped);
+    }
+    #@items_ungroaped= @items - @items_groaped
+    my @items_ungrouped= get_diff_array(\@items ,\@items_grouped);
+    $self->object_add_attribute("$name",'ungrouped',\@items_ungrouped);
 }
 
-
-
-
 sub create_iconview {
 #---------------------------------------------------
 #Creates an Iconview in a ScrolledWindow. This -----
 #Iconview has the ability to drag items off it  -----
 #---------------------------------------------------
-	my ($self,$label,$editable,$ref,$name,$param,$limit)=@_;
+    my ($self,$label,$editable,$ref,$name,$param,$limit)=@_;
     my $icon_string= undef;
     my $tree_model = create_iconview_model($self,$name,$ref);
-
     my $icon_view = gen_iconview($tree_model,C_MARKUP,C_PIXBUF);
-
     #Enable the IconView as a drag source
-	
     add_drag_source($icon_view,'STRING',[],ID_ICONVIEW);
     add_drop_source($icon_view,$tree_model,$name,$param,$self,$limit);
-
     #This is a nice to have. It changes the drag icon to that of the
     #icon which are now selected and dragged (single selection mode)
-	my $saved;
-
-    $icon_view->signal_connect('drag-begin' => sub { 
+    my $saved;
+    $icon_view->signal_connect('drag-begin' => sub {
         $icon_view->selected_foreach ( sub{
-                my $iter =$tree_model->get_iter($_[1]);
-				$saved=$iter;
-                #set the text and pixbuf
-                my $icon_pixbuf = $tree_model->get_value($iter,C_PIXBUF);
-				drag_set_icon_pixbuf($icon_view,$icon_pixbuf);
-				$icon_view->show_all();
+            my $iter =$tree_model->get_iter($_[1]);
+            $saved=$iter;
+            #set the text and pixbuf
+            my $icon_pixbuf = $tree_model->get_value($iter,C_PIXBUF);
+            drag_set_icon_pixbuf($icon_view,$icon_pixbuf);
+            $icon_view->show_all();
         } );
     });
-
     #set up the data which needs to be fed to the drag destination (drop)
-    $icon_view->signal_connect ('drag-data-get' => sub { 
-		return if(! defined $saved);
-		$icon_string = $tree_model->get_value($saved,C_MARKUP);		
-		#print "\$icon_string=$icon_string\n";
-		my $no_markup = $icon_string;
+    $icon_view->signal_connect ('drag-data-get' => sub {
+        return if(! defined $saved);
+        $icon_string = $tree_model->get_value($saved,C_MARKUP);
+        #print "\$icon_string=$icon_string\n";
+        my $no_markup = $icon_string;
         $no_markup =~ s/<[^>]*>//g;
-		
-		
-		my $gref = $self->object_get_attribute("$name",$param);		
-		$tree_model->remove($saved);
-		source_drag_data_get(@_,$icon_string); 
-		my @array=remove_scolar_from_array($gref,$no_markup );
-		$self->object_add_attribute("$name",$param,\@array);
-		set_gui_status($self,"drag-data-get",0);
-		
-	} );
-    
+        my $gref = $self->object_get_attribute("$name",$param);
+        $tree_model->remove($saved);
+        source_drag_data_get(@_,$icon_string);
+        my @array=remove_scolar_from_array($gref,$no_markup );
+        $self->object_add_attribute("$name",$param,\@array);
+        set_gui_status($self,"drag-data-get",0);
+    } );
     #Standard scrolledwindow to allow growth
     my $sw = add_widget_to_scrolled_win($icon_view);
     $sw->set_policy('never','automatic');
     $sw->set_border_width(6);
     my($width,$hight)=max_win_size();
-	$sw->set_size_request($width/10,$hight/10);
-    
-   
+    $sw->set_size_request($width/10,$hight/10);
     my $frame = gen_frame();
-	$frame->set_shadow_type ('in');
-	# Animation
-	$frame->add ($sw);
-	#$align->add ($frame);
-	
-	
-	
-	my $entry=gen_entry_object($self,$name,$param."_name",$label);
-	$frame->set_label_widget ($entry) if($editable eq 'YES');
-	$frame->set_label_widget (gen_label_in_center($label)) unless($editable eq 'YES');
-    
-    
+    $frame->set_shadow_type ('in');
+    # Animation
+    $frame->add ($sw);
+    #$align->add ($frame);
+    my $entry=gen_entry_object($self,$name,$param."_name",$label);
+    $frame->set_label_widget ($entry) if($editable eq 'YES');
+    $frame->set_label_widget (gen_label_in_center($label)) unless($editable eq 'YES');
     return ($frame,$tree_model);
 }
 
-
-
-
-
 sub target_drag_data_received {
 #---------------------------------------------------
 #Extract the data which was set up during the  -----
@@ -187,117 +146,75 @@ sub target_drag_data_received {
 #the 'drag-data-received' event. Also checks which--
 #source supplied the data, and handle accordingly----
 #---------------------------------------------------
-
     my ($widget, $context, $x, $y, $data, $info, $time,$ref) = @_;
-
-	my ($target,$name,$param,$self,$limit) = @{$ref};
+    my ($target,$name,$param,$self,$limit) = @{$ref};
     my @array;
-	my $icon=$self->object_get_attribute($name,'trace_icon');
-	my $pixbuf = get_icon_pixbuff ($icon );
-    
-
-   
-
-        my $no_markup = $data->get_text;
-		#print Dumper ($widget, $context, $x, $y, $data, $info, $time,$no_markup);
-
-        $no_markup =~ s/<[^>]*>//g;       
-
-	
-       
-
-        add_icon_to_tree($self,$name,$target,$no_markup) ;
-        my $r=$self->object_get_attribute("$name","$param");
-        
-        @array = defined ($r)? @{$r}:();
-        push (@array ,$no_markup);
-        $self->object_add_attribute("$name","$param",\@array); 
-      
-        
-        
-        
-   
-# check if the maximum number of dropped item is received
-$limit =655350 if(!defined $limit);
-if( scalar @array >= $limit){    
-    stop_drag_dest( $widget);
-}    
-
-	call_gtk_drag_finish($context, 0, 0, $time);
-   # $context->finish (0, 0, $time);
+    my $icon=$self->object_get_attribute($name,'trace_icon');
+    my $pixbuf = get_icon_pixbuff ($icon );
+    my $no_markup = $data->get_text;
+    #print Dumper ($widget, $context, $x, $y, $data, $info, $time,$no_markup);
+    $no_markup =~ s/<[^>]*>//g;
+    add_icon_to_tree($self,$name,$target,$no_markup) ;
+    my $r=$self->object_get_attribute("$name","$param");
+    @array = defined ($r)? @{$r}:();
+    push (@array ,$no_markup);
+    $self->object_add_attribute("$name","$param",\@array);
+    # check if the maximum number of dropped item is received
+    $limit =655350 if(!defined $limit);
+    if( scalar @array >= $limit){
+        stop_drag_dest( $widget);
+    }
+    call_gtk_drag_finish($context, 0, 0, $time);
+    # $context->finish (0, 0, $time);
 }
-
 sub source_drag_data_get {
 #---------------------------------------------------
 #This sets up the data of the drag source. It is ---
 #required before the 'drag-data-received' event ----
 #fires which can be used to extract this data ------
 #---------------------------------------------------
-
     my ($widget, $context, $data, $info, $time,$string) = @_;
-
     $data->set_text($string,-1) if defined $string;
     $data->set_text("Unknown-event-name",-1) unless defined $string;
-	
-	
-
 }
 
-
-
-
 sub add_icon_to_tree{
-	my ($self,$name,$list_store,$val)=@_;
-	
+    my ($self,$name,$list_store,$val)=@_;
     my $icon=$self->object_get_attribute($name,'trace_icon');
-	my $pixbuf = get_icon_pixbuff ($icon );
-	
-	
-        #if there was a valid icon in the iconset, add it
-        if( defined $pixbuf ){
-
-            my $iter = $list_store->append;
-            $list_store->set (
-                        $iter,
-                        C_MARKUP, "<b>$val</b>",
-                        C_PIXBUF, $pixbuf,
-             );
-
-        }
-
+    my $pixbuf = get_icon_pixbuff ($icon );
+    #if there was a valid icon in the iconset, add it
+    if( defined $pixbuf ){
+        my $iter = $list_store->append;
+        $list_store->set (
+            $iter,
+            C_MARKUP, "<b>$val</b>",
+            C_PIXBUF, $pixbuf,
+        );
+    }
 }
 
-
-
-
 sub stop_drag_dest {
-	my $widget=shift;
-	$widget->drag_dest_unset ();
+    my $widget=shift;
+    $widget->drag_dest_unset ();
 }
 
-
 sub add_drop_source {
-	my ($widget,$target,$name,$param,$self,$limit)=@_;	
-	
-	#Create a target table to receive drops
-	add_drag_dest_set($widget, 'STRING',[],ID_ICONVIEW);
-
+    my ($widget,$target,$name,$param,$self,$limit)=@_;
+    #Create a target table to receive drops
+    add_drag_dest_set($widget, 'STRING',[],ID_ICONVIEW);
     #make this the drag destination (drop) for various drag sources
     my $r=$self->object_get_attribute("$name","$param");
     my    @array = defined ($r)? @{$r}:();
-    
     # check if the maximum number of dropped item is received
-	$limit =655350 if(!defined $limit);
-	if( scalar @array >= $limit){    
-	    stop_drag_dest( $widget);
-	}    
-    
-
+    $limit =655350 if(!defined $limit);
+    if( scalar @array >= $limit){
+        stop_drag_dest( $widget);
+    }
     #do a callback as soon as drag data is received
     my @params=($target,$name,$param,$self,$limit);
     $widget->signal_connect ('drag-data-received' => \&target_drag_data_received,\@params );
     $widget->signal_connect ('drag-data-get' => sub {
-		add_drag_dest_set($widget, 'STRING',[],ID_ICONVIEW);
+        add_drag_dest_set($widget, 'STRING',[],ID_ICONVIEW);
     });
-	
 }
+1;
\ No newline at end of file
diff --git a/mpsoc/perl_gui/lib/perl/emulate_ram_gen.pl b/mpsoc/perl_gui/lib/perl/emulate_ram_gen.pl
index dc07e6a..c00195b 100755
--- a/mpsoc/perl_gui/lib/perl/emulate_ram_gen.pl
+++ b/mpsoc/perl_gui/lib/perl/emulate_ram_gen.pl
@@ -2,513 +2,393 @@
 use strict;
 use warnings;
 use List::Util 'shuffle';
-require "widget.pl"; 	
+require "widget.pl";
 require "traffic_pattern.pl";
 
-
-use constant SIM_RAM_GEN	=> 0;			
-
-use constant JTAG_STATIC_INDEX	=> 124;
-use constant JTAG_RAM_INDEX	=> 125;
+use constant SIM_RAM_GEN    => 0;
+use constant JTAG_STATIC_INDEX    => 124;
+use constant JTAG_RAM_INDEX    => 125;
 use constant JTAG_COUNTER_INDEX=>126;
-use constant JTAG_DONE_RESET_INDEX	=> 127;
+use constant JTAG_DONE_RESET_INDEX    => 127;
 use constant STATISTIC_NUM =>8;
-
-use constant CLK_CNTw=> 30; #log2(MAX_SIM_CLKs); 
-
-
-#use constant RESET_NOC 		=> " $ENV{'JTAG_INTFC'} -n ".JTAG_DONE_RESET_INDEX." -d \"I:1,D:2:1,I:0\" ";
-#use constant UNRESET_NOC 	=> " $ENV{'JTAG_INTFC'} -n ".JTAG_DONE_RESET_INDEX." -d \"I:1,D:2:0,I:0\" ";
-
-use constant READ_DONE_CMD 	=> " \" -n ".JTAG_DONE_RESET_INDEX." -d I:2,R:2:0,I:0 \" ";
+use constant CLK_CNTw=> 30; #log2(MAX_SIM_CLKs);
+#use constant RESET_NOC         => " $ENV{'JTAG_INTFC'} -n ".JTAG_DONE_RESET_INDEX." -d \"I:1,D:2:1,I:0\" ";
+#use constant UNRESET_NOC     => " $ENV{'JTAG_INTFC'} -n ".JTAG_DONE_RESET_INDEX." -d \"I:1,D:2:0,I:0\" ";
+use constant READ_DONE_CMD     => " \" -n ".JTAG_DONE_RESET_INDEX." -d I:2,R:2:0,I:0 \" ";
 use constant READ_COUNTER_CMD => " \" -n ".JTAG_COUNTER_INDEX." -d I:2,R:".CLK_CNTw.":0,I:0 \" ";
-
-
-use constant UPDATE_WB_ADDR  	=> 0x7; 
+use constant UPDATE_WB_ADDR      => 0x7;
 use constant UPDATE_WB_WR_DATA  => 0x6;
 use constant UPDATE_WB_RD_DATA  => 0x5;
-use constant RD_WR_STATUS	=> 0x4;
-use constant PROBE_ST 		=> 0x2;
-use constant SOURCE_ST		=> 0x1;
-use constant BYPAS_ST 		=> 0x0;
-#use constant RAM_BIN_FILE	=> "$ENV{'PRONOC_WORK'}/emulate/emulate_ram.bin";
-#use constant RAM_SIM_FILE	=> "$ENV{'PRONOC_WORK'}/emulate/ram";
-			
-
-
-
+use constant RD_WR_STATUS    => 0x4;
+use constant PROBE_ST         => 0x2;
+use constant SOURCE_ST        => 0x1;
+use constant BYPAS_ST         => 0x0;
+#use constant RAM_BIN_FILE    => "$ENV{'PRONOC_WORK'}/emulate/emulate_ram.bin";
+#use constant RAM_SIM_FILE    => "$ENV{'PRONOC_WORK'}/emulate/ram";
 
 sub reset_cmd {
-	my ($ctrl_reset, $noc_reset,$jtag_intfc)=@_;
-	my $reset_vector= (($ctrl_reset & 0x1) << 1) +  ($noc_reset & 0x1);
-	my $cmd = "bash $jtag_intfc \" -n ".JTAG_DONE_RESET_INDEX."  -d I:1,D:2:$reset_vector,I:0 \" ";
-	#print "$cmd\n";
-	return	$cmd;
+    my ($ctrl_reset, $noc_reset,$jtag_intfc)=@_;
+    my $reset_vector= (($ctrl_reset & 0x1) << 1) +  ($noc_reset & 0x1);
+    my $cmd = "bash $jtag_intfc \" -n ".JTAG_DONE_RESET_INDEX."  -d I:1,D:2:$reset_vector,I:0 \" ";
+    #print "$cmd\n";
+    return    $cmd;
 }
 
 sub set_time_limit_cmd {
-	my ($time_limit,$jtag_intfc)=@_;
-	my $hex = sprintf("0x%X", $time_limit);
-	my $cmd = "bash $jtag_intfc \" -n ".JTAG_COUNTER_INDEX."  -d I:1,D:".CLK_CNTw.":$hex,I:0 \" ";
-	#print "$cmd\n";
-	return	$cmd;
+    my ($time_limit,$jtag_intfc)=@_;
+    my $hex = sprintf("0x%X", $time_limit);
+    my $cmd = "bash $jtag_intfc \" -n ".JTAG_COUNTER_INDEX."  -d I:1,D:".CLK_CNTw.":$hex,I:0 \" ";
+    #print "$cmd\n";
+    return    $cmd;
 }
 
-
 sub help {
-		print 
-"	usage: ./ram_gen X  Y TRAFFIC
-		X:  number of node in X direction 2<x<=16
-		Y:  number of node in Y direction 2<y<=16
-		TRAFFIC : select one of the following traffic patterns :
-			tornado,
-			transposed 1,
-			transposed 2,
-			random, 
-			
-";	
-	
-}	
-
-
+        print
+"    usage: ./ram_gen X  Y TRAFFIC
+        X:  number of node in X direction 2<x<=16
+        Y:  number of node in Y direction 2<y<=16
+        TRAFFIC : select one of the following traffic patterns :
+            tornado,
+            transposed 1,
+            transposed 2,
+            random,
+";
+}
 
 sub random_dest_gen {
-	my $n=shift;
-	my @c=(0..$n-1);
-	my @o;	
-	for (my $i=0; $i<$n; $i++){
-		my @l= shuffle @c;
-		@l=remove_scolar_from_array(\@l,$i);
-		$o[$i]=\@l;
-		
-	}
-	return \@o;
+    my $n=shift;
+    my @c=(0..$n-1);
+    my @o;
+    for (my $i=0; $i<$n; $i++){
+        my @l= shuffle @c;
+        @l=remove_scolar_from_array(\@l,$i);
+        $o[$i]=\@l;
+    }
+    return \@o;
 }
 
 sub random_dest_gen_no_shuffle {
-	my $n=shift;
-	my @c=(0..$n-1);
-	my @o;	
-	for (my $i=0; $i<$n; $i++){
-		my @l=  @c;
-		@l=remove_scolar_from_array(\@l,$i);
-		$o[$i]=\@l;
-	}
-	return \@o;
+    my $n=shift;
+    my @c=(0..$n-1);
+    my @o;
+    for (my $i=0; $i<$n; $i++){
+        my @l=  @c;
+        @l=remove_scolar_from_array(\@l,$i);
+        $o[$i]=\@l;
+    }
+    return \@o;
 }
 
-
 sub run_cmd_update_info {
-	my ($cmd,$info)=@_;
-	my ($stdout,$exit,$stderr)=run_cmd_in_back_ground_get_stdout($cmd);
-		if($exit){
-			add_colored_info($info, "$stdout\n",'red') if(defined $stdout);
-			add_colored_info($info, "$stderr\n",'red') if(defined $stderr);
-			
-		}
-	#print	"\n$cmd \n $stdout";
-	return $exit;
+    my ($cmd,$info)=@_;
+    my ($stdout,$exit,$stderr)=run_cmd_in_back_ground_get_stdout($cmd);
+        if($exit){
+            add_colored_info($info, "$stdout\n",'red') if(defined $stdout);
+            add_colored_info($info, "$stderr\n",'red') if(defined $stderr);
+        }
+    #print    "\n$cmd \n $stdout";
+    return $exit;
 }
 
-
-
-
-
 sub synthetic_destination{
-	my($self,$sample,$traffic,$endp,$line_num,$rnd)=@_;
-	return  pck_dst_gen ($self,$sample,$traffic,$endp,$line_num,$rnd);
+    my($self,$sample,$traffic,$endp,$line_num,$rnd)=@_;
+    return  pck_dst_gen ($self,$sample,$traffic,$endp,$line_num,$rnd);
 }
 
-
-
-
-
-
 sub gen_synthetic_traffic_ram_line{
-	my ($emulate,  $endp,  $sample,$ratio ,$line_num,$rnd)=@_;	
-	
-	my ($topology, $T1, $T2, $T3, $V, $Fpay) = get_sample_emulation_param($emulate,$sample);	
-	my ($NE, $NR, $RAw, $EAw, $Fw) = get_topology_info_sub ($topology, $T1, $T2, $T3, $V, $Fpay);
-	
-	
-	
-	
-	my $traffic=$emulate->object_get_attribute($sample,"traffic"); 
-	
-	my $pck_num_to_send=$emulate->object_get_attribute($sample,"PCK_NUM_LIMIT");
-	my $pck_size=$emulate->object_get_attribute($sample,"PCK_SIZE");
-	my $pck_class_in=0;
-	
-	
-	if($line_num==0){ #first ram line shows how many times the ram content must be read 
-		 #In random traffic each node sends 2 packets to other NC-1  nodes for (pck_num_to_send/2) times 
-			my $ram_cnt=  ($traffic eq 'random')? ($pck_num_to_send/(2*($NE-1)))+1:0 ;
-			return (0,$ram_cnt);
-	
-	}
-	return (0,0) if($line_num>1  && $traffic ne 'random');	
-	return (0,0) if( $line_num>= $NE);  	
-
-	#assign {pck_num_to_send_in,ratio_in, pck_size_in,dest_x_in, dest_y_in,pck_class_in, last_adr_in}= q_a;
-	my $last_adr  = ( $traffic ne 'random') ? 1 : 
-			 ($line_num ==$NE-1)? 1 :0;
-
-	my $dest_e_addr=synthetic_destination($emulate,$sample,$traffic,$endp,$line_num,$rnd);
-	#print "$endp->$dest_e_addr\n";
-
-	my $vs= ( $traffic eq 'random')? 2 : $pck_num_to_send;
-	$vs=($vs << 2 )+ ($ratio >>5) ;
-
-	my $vl= ($ratio %32);
-	$vl=($vl << PCK_SIZw )+$pck_size;
-	$vl=($vl << MAX_EAw )+$dest_e_addr;
-	$vl=($vl << MAXCw )+$pck_class_in;
-	$vl=($vl << 1 )+$last_adr;	
-	return ($vs,$vl);
+    my ($emulate,  $endp,  $sample,$ratio ,$line_num,$rnd)=@_;
+    my ($NE, $NR, $RAw, $EAw, $Fw) = get_sample_topology_info ($emulate,$sample);
+    my $traffic=$emulate->object_get_attribute($sample,"traffic");
+    my $pck_num_to_send=$emulate->object_get_attribute($sample,"PCK_NUM_LIMIT");
+    my $pck_size=$emulate->object_get_attribute($sample,"PCK_SIZE");
+    my $pck_class_in=0;
+    if($line_num==0){ #first ram line shows how many times the ram content must be read
+        #In random traffic each node sends 2 packets to other NC-1  nodes for (pck_num_to_send/2) times
+            my $ram_cnt=  ($traffic eq 'random')? ($pck_num_to_send/(2*($NE-1)))+1:0 ;
+            return (0,$ram_cnt);
+    }
+    return (0,0) if($line_num>1  && $traffic ne 'random');
+    return (0,0) if( $line_num>= $NE);
+    #assign {pck_num_to_send_in,ratio_in, pck_size_in,dest_x_in, dest_y_in,pck_class_in, last_adr_in}= q_a;
+    my $last_adr  = ( $traffic ne 'random') ? 1 :
+            ($line_num ==$NE-1)? 1 :0;
+    my $dest_e_addr=synthetic_destination($emulate,$sample,$traffic,$endp,$line_num,$rnd);
+    #print "$endp->$dest_e_addr\n";
+    my $vs= ( $traffic eq 'random')? 2 : $pck_num_to_send;
+    $vs=($vs << 2 )+ ($ratio >>5) ;
+    my $vl= ($ratio %32);
+    $vl = ($vl << PCK_SIZw ) + $pck_size;
+    $vl = ($vl << MAX_EAw ) + $dest_e_addr;
+    $vl = ($vl << MAXCw ) + $pck_class_in;
+    $vl = ($vl << 1 ) + $last_adr;
+    return ($vs,$vl);
 }
 
 sub get_synthetic_traffic_pattern{
-	my ($self, $sample)=@_;
-	my ($topology, $T1, $T2, $T3, $V, $Fpay) = get_sample_emulation_param($self,$sample);
-	my ($NE, $NR, $RAw, $EAw, $Fw) = get_topology_info_sub ($topology, $T1, $T2, $T3, $V, $Fpay);
-	my $rnd=random_dest_gen_no_shuffle($NE); 
-	my $traffic=$self->object_get_attribute($sample,"traffic"); 
-	my @traffics=("tornado", "transposed 1", "transposed 2", "bit reverse", "bit complement","random", "hot spot", "shuffle", "neighbor", "bit rotation"  );	
-	
-	#generate each node ram data
-	my $pattern="source->\t destination\n";
-	$traffic=($traffic eq "hot spot") ? "random" : $traffic;
-	my $dest_num = ($traffic eq "hot spot" || $traffic eq "random" ) ? $NE-1 : 1;
-	for (my $endp=0; $endp<$NE; $endp++){
-		$pattern = $pattern."$endp->\n";
-		for (my $num= 0; $num<$dest_num; $num++ ) {		
-		my $dest_e_addr=synthetic_destination($self,$sample,$traffic,$endp,$num,$rnd);
-		my $des_id=endp_addr_decoder($self,$dest_e_addr);		
-		$pattern = ($des_id == $endp)?$pattern."\t$des_id (Off)\n" : $pattern."\t$des_id\n";		
-	}}	
-	return $pattern;
+    my ($self, $sample)=@_;
+    my ($NE, $NR, $RAw, $EAw, $Fw) = get_sample_topology_info ($self,$sample);
+    my $rnd=random_dest_gen_no_shuffle($NE);
+    my $traffic=$self->object_get_attribute($sample,"traffic");
+    my @traffics=("tornado", "transposed 1", "transposed 2", "bit reverse", "bit complement","random", "hot spot", "shuffle", "neighbor", "bit rotation"  );
+    #generate each node ram data
+    my $pattern="source->\t destination\n";
+    $traffic=($traffic eq "hot spot") ? "random" : $traffic;
+    my $dest_num = ($traffic eq "hot spot" || $traffic eq "random" ) ? $NE-1 : 1;
+    for (my $endp=0; $endp<$NE; $endp++){
+        $pattern = $pattern."$endp->\n";
+        for (my $num= 0; $num<$dest_num; $num++ ) {
+        my $dest_e_addr=synthetic_destination($self,$sample,$traffic,$endp,$num,$rnd);
+        my $des_id=endp_addr_decoder($self,$dest_e_addr);
+        $pattern = ($des_id == $endp)?$pattern."\t$des_id (Off)\n" : $pattern."\t$des_id\n";
+    }}
+    return $pattern;
 }
 
-
-
 sub generate_synthetic_traffic_ram{
-	my ($emulate,$endp,$sample,$ratio , $file,$rnd)=@_;
-		
-	my $line_num;
-	my $line_value;
-	my $ram;
-	if(SIM_RAM_GEN){
-		my $ext= sprintf("%02u.txt",$endp);
-		open( $ram, '>', "$ENV{'PRONOC_WORK'}/emulate/ram".$ext) || die "Can not create: \"$ENV{'PRONOC_WORK'}/emulate/ram.$ext\" $!";
-	}
-	for ($line_num= 0; $line_num<RAM_SIZE; $line_num++ ) {
-		my ($value_s,$value_l)=gen_synthetic_traffic_ram_line ($emulate,  $endp,  $sample, $ratio ,$line_num,$rnd);
-		
-		
-		#printf ("\n%08x\t",$value_s);
-		#printf ("%08x\t",$value_l);
-		if(SIM_RAM_GEN){
-			my $s=sprintf("%08X%08x",$value_s,$value_l);
-			print $ram "$s\n";
-		}
-		print_32_bit( $file, $value_s); # most significent 32 bit
-		print_32_bit( $file, $value_l); # list significent 32 bit
-
-	}
-	
-
-	if(SIM_RAM_GEN){
-		close($ram);
-	}
-	#print "\n";
-
-	#last ram three rows reserved for reading data from emulator
-
+    my ($emulate,$endp,$sample,$ratio , $file,$rnd)=@_;
+    my $line_num;
+    my $line_value;
+    my $ram;
+    if(SIM_RAM_GEN){
+        my $ext= sprintf("%02u.txt",$endp);
+        open( $ram, '>', "$ENV{'PRONOC_WORK'}/emulate/ram".$ext) || die "Can not create: \"$ENV{'PRONOC_WORK'}/emulate/ram.$ext\" $!";
+    }
+    for ($line_num= 0; $line_num<RAM_SIZE; $line_num++ ) {
+        my ($value_s,$value_l)=gen_synthetic_traffic_ram_line ($emulate,  $endp,  $sample, $ratio ,$line_num,$rnd);
+        #printf ("\n%08x\t",$value_s);
+        #printf ("%08x\t",$value_l);
+        if(SIM_RAM_GEN){
+            my $s=sprintf("%08X%08x",$value_s,$value_l);
+            print $ram "$s\n";
+        }
+        print_32_bit( $file, $value_s); # most significent 32 bit
+        print_32_bit( $file, $value_l); # list significent 32 bit
+    }
+    if(SIM_RAM_GEN){
+        close($ram);
+    }
+    #print "\n";
+    #last ram three rows reserved for reading data from emulator
 }
 
-
 sub print_32_bit {
-	my ($file,$v)=@_;
-	for (my $i= 24; $i >=0 ; $i-=8) {
-		my $byte= ($v >> $i ) & 0xFF;
-		print $file pack('C*',$byte);
-		#printf ("%02x\t",$byte);
-	}
+    my ($file,$v)=@_;
+    for (my $i= 24; $i >=0 ; $i-=8) {
+        my $byte= ($v >> $i ) & 0xFF;
+        print $file pack('C*',$byte);
+        #printf ("%02x\t",$byte);
+    }
 }
 
-
-
 sub generate_emulator_ram {
-	my ($emulate, $sample,$ratio_in,$info)=@_;
-	my ($topology, $T1, $T2, $T3, $V, $Fpay) = get_sample_emulation_param($emulate,$sample);
-	my ($NE, $NR, $RAw, $EAw, $Fw) = get_topology_info_sub ($topology, $T1, $T2, $T3, $V, $Fpay);
-	
-		
-	
-	my $rnd=random_dest_gen($NE); # generate a matrix of sudo random number
-	my $traffic=$emulate->object_get_attribute($sample,"traffic"); 
-	my @traffics=("tornado", "transposed 1", "transposed 2", "bit reverse", "bit complement","random", "hot spot", "shuffle", "neighbor", "bit rotation"   );
-	
-	#if ( !defined $xn || $xn!~ /\s*\d+\b/ ){ add_info($info,"programe_pck_gens:invalid X value\n"); help(); return 0;}
-	#if ( !defined $yn || $yn!~ /\s*\d+\b/ ){ add_info($info,"programe_pck_gens:invalid Y value\n"); help(); return 0;}
-	if ( !grep( /^$traffic$/, @traffics ) ){add_info($info,"programe_pck_gens:$traffic is an invalid Traffic name\n"); help(); return 0;}
-	if ( $EAw >8 ){ add_info($info,"Program_pck_gens:invalid EAw value: ($EAw). should be between 1 and 8 \n"); help(); return 0;}
-	#if ( $yn <2 || $yn >16 ){ add_info($info,"programe_pck_gens:invalid Y value:($yn). should be between 2 and 16 \n"); help(); return 0;}
-	#open file pointer
-	#open(my $file, '>', RAM_BIN_FILE) || die "Can not create: \">lib/emulate/emulate_ram.bin\" $!";
-	open(my $file, '>', "$ENV{'PRONOC_WORK'}/emulate/emulate_ram.bin") || die "Can not create: \"$ENV{'PRONOC_WORK'}/emulate/emulate_ram.bin\" $!";
-	
-	#generate each node ram data
-	for (my $endp=0; $endp<$NE; $endp++){
-		#print "generate_synthetic_traffic_ram($emulate,$endp,$sample,$ratio_in, $file,$rnd);\n";
-		generate_synthetic_traffic_ram($emulate,$endp,$sample,$ratio_in, $file,$rnd);
-	}
-	close($file);
-	return 1;
-
+    my ($emulate, $sample,$ratio_in,$info)=@_;
+    my ($NE, $NR, $RAw, $EAw, $Fw) = get_sample_topology_info ($emulate,$sample);
+    my $rnd=random_dest_gen($NE); # generate a matrix of sudo random number
+    my $traffic=$emulate->object_get_attribute($sample,"traffic");
+    my @traffics=("tornado", "transposed 1", "transposed 2", "bit reverse", "bit complement","random", "hot spot", "shuffle", "neighbor", "bit rotation"   );
+    #if ( !defined $xn || $xn!~ /\s*\d+\b/ ){ add_info($info,"programe_pck_gens:invalid X value\n"); help(); return 0;}
+    #if ( !defined $yn || $yn!~ /\s*\d+\b/ ){ add_info($info,"programe_pck_gens:invalid Y value\n"); help(); return 0;}
+    if ( !grep( /^$traffic$/, @traffics ) ){add_info($info,"programe_pck_gens:$traffic is an invalid Traffic name\n"); help(); return 0;}
+    if ( $EAw >8 ){ add_info($info,"Program_pck_gens:invalid EAw value: ($EAw). should be between 1 and 8 \n"); help(); return 0;}
+    #if ( $yn <2 || $yn >16 ){ add_info($info,"programe_pck_gens:invalid Y value:($yn). should be between 2 and 16 \n"); help(); return 0;}
+    #open file pointer
+    #open(my $file, '>', RAM_BIN_FILE) || die "Can not create: \">lib/emulate/emulate_ram.bin\" $!";
+    open(my $file, '>', "$ENV{'PRONOC_WORK'}/emulate/emulate_ram.bin") || die "Can not create: \"$ENV{'PRONOC_WORK'}/emulate/emulate_ram.bin\" $!";
+    #generate each node ram data
+    for (my $endp=0; $endp<$NE; $endp++){
+        #print "generate_synthetic_traffic_ram($emulate,$endp,$sample,$ratio_in, $file,$rnd);\n";
+        generate_synthetic_traffic_ram($emulate,$endp,$sample,$ratio_in, $file,$rnd);
+    }
+    close($file);
+    return 1;
 }
 
 sub programe_pck_gens{
-	my ($emulate, $sample,$ratio_in,$info,$jtag_intfc)= @_;
-	
-	 if(!generate_emulator_ram($emulate, $sample,$ratio_in,$info)){
-	 	add_colored_info($info, "Error in generate_emulator_ram function\n",'red');	
-	 	return 0;
-	 	
-	 }
-
-	#reset the FPGA board	
-	#run_cmd_in_back_ground("quartus_stp -t ./lib/tcl/mem.tcl reset");
-	#print "#reset both noc and jtag\n";
-	return 0 if(run_cmd_update_info(reset_cmd(1,1,$jtag_intfc),$info)); #reset both noc and jtag
-	#print "#enable jtag keep noc in reset\n";
-	return 0 if(run_cmd_update_info(reset_cmd(0,1,$jtag_intfc),$info)); #enable jtag keep noc in reset
-	#print "#set time limit\n";
-	#set time limit	
-	my $time_limit = $emulate->object_get_attribute($sample,"SIM_CLOCK_LIMIT");  
-	return 0 if(run_cmd_update_info(set_time_limit_cmd($time_limit,$jtag_intfc),$info));
-
-	
-
-	#program the packet generators rams
-	my $cmd= "bash $jtag_intfc \"-n ".JTAG_RAM_INDEX."  -w 8 -i $ENV{'PRONOC_WORK'}/emulate/emulate_ram.bin -c\" ";
-	#my ($result,$exit) = run_cmd_in_back_ground_get_stdout($cmd);
-	
-	return 0 if(run_cmd_update_info ($cmd,$info));
-	#print $result;
-	
-	return 0 if(run_cmd_update_info(reset_cmd(1,1,$jtag_intfc),$info)); #reset both
-	return 0 if(run_cmd_update_info(reset_cmd(0,0,$jtag_intfc),$info)); #enable both
+    my ($emulate, $sample,$ratio_in,$info,$jtag_intfc)= @_;
+    if(!generate_emulator_ram($emulate, $sample,$ratio_in,$info)){
+        add_colored_info($info, "Error in generate_emulator_ram function\n",'red');
+        return 0;
+    }
+    #reset the FPGA board
+    #run_cmd_in_back_ground("quartus_stp -t ./lib/tcl/mem.tcl reset");
+    #print "#reset both noc and jtag\n";
+    return 0 if(run_cmd_update_info(reset_cmd(1,1,$jtag_intfc),$info)); #reset both noc and jtag
+    #print "#enable jtag keep noc in reset\n";
+    return 0 if(run_cmd_update_info(reset_cmd(0,1,$jtag_intfc),$info)); #enable jtag keep noc in reset
+    #print "#set time limit\n";
+    #set time limit
+    my $time_limit = $emulate->object_get_attribute($sample,"SIM_CLOCK_LIMIT");
+    return 0 if(run_cmd_update_info(set_time_limit_cmd($time_limit,$jtag_intfc),$info));
+    #program the packet generators rams
+    my $cmd= "bash $jtag_intfc \"-n ".JTAG_RAM_INDEX."  -w 8 -i $ENV{'PRONOC_WORK'}/emulate/emulate_ram.bin -c\" ";
+    #my ($result,$exit) = run_cmd_in_back_ground_get_stdout($cmd);
+    return 0 if(run_cmd_update_info ($cmd,$info));
+    #print $result;
+    return 0 if(run_cmd_update_info(reset_cmd(1,1,$jtag_intfc),$info)); #reset both
+    return 0 if(run_cmd_update_info(reset_cmd(0,0,$jtag_intfc),$info)); #enable both
 #run_cmd_in_back_ground("quartus_stp -t ./lib/tcl/mem.tcl unreset");
 #add_info($info,"$r\n");
-
 return 1;
-
 }
 
-
 sub read_jtag_memory{
-	my ($addr,$jtag_intfc,$info)=@_;
-	my $cmd= "bash $jtag_intfc \" -n ".JTAG_STATIC_INDEX." -w 8 -d I:".UPDATE_WB_ADDR.",D:64:$addr,I:5,R:64:$addr,I:0\"";
-	#print "$cmd\n";	
-	my ($result,$exit,$stderr) = run_cmd_in_back_ground_get_stdout($cmd);
-	if($exit){
-			add_colored_info($info, "$result\n",'red') if(defined $result);
-			add_colored_info($info, "$stderr\n",'red') if(defined $stderr);
-			return undef;
-			
-	}
-	#print "$result\n";	
-	
-	my @q =split  (/###read data#/,$result);
-	my $d=$q[1];
-	my $s= substr $d,2;
-	#print "$s\n";
-	return hex($s);
+    my ($addr,$jtag_intfc,$info)=@_;
+    my $cmd= "bash $jtag_intfc \" -n ".JTAG_STATIC_INDEX." -w 8 -d I:".UPDATE_WB_ADDR.",D:64:$addr,I:5,R:64:$addr,I:0\"";
+    #print "$cmd\n";
+    my ($result,$exit,$stderr) = run_cmd_in_back_ground_get_stdout($cmd);
+    if($exit){
+            add_colored_info($info, "$result\n",'red') if(defined $result);
+            add_colored_info($info, "$stderr\n",'red') if(defined $stderr);
+            return undef;
+    }
+    #print "$result\n";
+    my @q =split  (/###read data#/,$result);
+    my $d=$q[1];
+    my $s= substr $d,2;
+    #print "$s\n";
+    return hex($s);
 }
 
-
 sub read_statistic_mem {
-	my($NE,$jtag_intfc,$info)=@_;
-	my %results;
-	my $sum_of_latency=0;
-	my $sum_of_pck=0;
-	my $total_router=0;
-	for (my $num=0; $num<$NE; $num++){
-				
-			my $read_addr=($num * STATISTIC_NUM);
-
-			my $sent_pck_addr=  sprintf ("%X",$read_addr);
-			my $got_pck_addr =  sprintf ("%X",$read_addr+1);
-			my $latency_addr =  sprintf ("%X",$read_addr+2);
-			my $worst_latency_addr =  sprintf ("%X",$read_addr+3);
-
-			$results{$num}{sent_pck}=read_jtag_memory($sent_pck_addr,$jtag_intfc,$info);
-			$results{$num}{got_pck}=read_jtag_memory($got_pck_addr,$jtag_intfc,$info);	
-			$results{$num}{latency}=read_jtag_memory($latency_addr,$jtag_intfc,$info);
-			$results{$num}{worst_latency}=read_jtag_memory($worst_latency_addr,$jtag_intfc,$info);
-			add_info($info, "$num, ");
-			
-			$sum_of_latency+=$results{$num}{latency};
-			$sum_of_pck+=$results{$num}{got_pck};
-			$total_router++ if($results{$num}{sent_pck}>0); 
-		#$i=$i+2;
-	}
-	
-	
-	
-	add_info($info, "\n");
-	
-	return (\%results,$sum_of_latency,$sum_of_pck,$total_router);
-	
+    my($NE,$jtag_intfc,$info)=@_;
+    my %results;
+    my $sum_of_latency=0;
+    my $sum_of_pck=0;
+    my $total_router=0;
+    for (my $num=0; $num<$NE; $num++){
+            my $read_addr=($num * STATISTIC_NUM);
+            my $sent_pck_addr=  sprintf ("%X",$read_addr);
+            my $got_pck_addr =  sprintf ("%X",$read_addr+1);
+            my $latency_addr =  sprintf ("%X",$read_addr+2);
+            my $worst_latency_addr =  sprintf ("%X",$read_addr+3);
+            $results{$num}{sent_pck}=read_jtag_memory($sent_pck_addr,$jtag_intfc,$info);
+            $results{$num}{got_pck}=read_jtag_memory($got_pck_addr,$jtag_intfc,$info);
+            $results{$num}{latency}=read_jtag_memory($latency_addr,$jtag_intfc,$info);
+            $results{$num}{worst_latency}=read_jtag_memory($worst_latency_addr,$jtag_intfc,$info);
+            add_info($info, "$num, ");
+            $sum_of_latency+=$results{$num}{latency};
+            $sum_of_pck+=$results{$num}{got_pck};
+            $total_router++ if($results{$num}{sent_pck}>0);
+        #$i=$i+2;
+    }
+    add_info($info, "\n");
+    return (\%results,$sum_of_latency,$sum_of_pck,$total_router);
 }
 
-
 sub read_statistic_mem_fast {
-	my($NE,$jtag_intfc,$info)=@_;
-	my %results;
-	my $sum_of_latency=0;
-	my $sum_of_pck=0;
-	my $total_router=0;
-	#read static memory
-	my $end= STATISTIC_NUM * 8 *$NE;
-	$end=sprintf ("%X",$end);
-	my $cmd= "bash $jtag_intfc \"-n ".JTAG_STATIC_INDEX."  -w 8 -r -s 0 -e $end\"";
-	#print "$cmd\n";
-	my ($result,$exit,$stderr) = run_cmd_in_back_ground_get_stdout($cmd);
-	if($exit){
-			add_colored_info($info, "$result\n",'red') if(defined $result);
-			add_colored_info($info, "$stderr\n",'red') if(defined $stderr);
-			return undef;
-			
-	}
-	#print "$result\n";
-	my @q =split  (/###read data#\n/,$result);
-	my @data= split  (/\n/,$q[1]);
-	#print "$data[0]\n";
-	
-	
-	
-	
-	for (my $endp=0; $endp<$NE; $endp=$endp+1){
-	
-			my $num=$endp; 
-			my $read_addr=($num * STATISTIC_NUM);
-
-			my $sent_pck_addr=  $read_addr;
-			my $got_pck_addr =  $read_addr+1;
-			my $latency_addr =  $read_addr+2;
-			my $worst_latency_addr =  $read_addr+3;
-
-			$results{$num}{sent_pck}=hex($data[$sent_pck_addr]);
-			$results{$num}{got_pck}=hex($data[$got_pck_addr]);
-			$results{$num}{latency}=hex($data[$latency_addr]);
-			$results{$num}{worst_latency}=hex($data[$worst_latency_addr]);
-			#add_info($info, "$num, ");
-			#print "$results{$num}{sent_pck}=hex($data[$sent_pck_addr]);\n";
-			
-			$sum_of_latency+=$results{$num}{latency};
-			$sum_of_pck+=$results{$num}{got_pck};
-			$total_router++ if($results{$num}{sent_pck}>0); 
-		#$i=$i+2;
-	}
-	
-	
-	
-	#add_info($info, "\n");
-	
-	return (\%results,$sum_of_latency,$sum_of_pck,$total_router);
-	
+    my($NE,$jtag_intfc,$info)=@_;
+    my %results;
+    my $sum_of_latency=0;
+    my $sum_of_pck=0;
+    my $total_router=0;
+    #read static memory
+    my $end= STATISTIC_NUM * 8 *$NE;
+    $end=sprintf ("%X",$end);
+    my $cmd= "bash $jtag_intfc \"-n ".JTAG_STATIC_INDEX."  -w 8 -r -s 0 -e $end\"";
+    #print "$cmd\n";
+    my ($result,$exit,$stderr) = run_cmd_in_back_ground_get_stdout($cmd);
+    if($exit){
+            add_colored_info($info, "$result\n",'red') if(defined $result);
+            add_colored_info($info, "$stderr\n",'red') if(defined $stderr);
+            return undef;
+    }
+    #print "$result\n";
+    my @q =split  (/###read data#\n/,$result);
+    my @data= split  (/\n/,$q[1]);
+    #print "$data[0]\n";
+    for (my $endp=0; $endp<$NE; $endp=$endp+1){
+            my $num=$endp;
+            my $read_addr=($num * STATISTIC_NUM);
+            my $sent_pck_addr=  $read_addr;
+            my $got_pck_addr =  $read_addr+1;
+            my $latency_addr =  $read_addr+2;
+            my $worst_latency_addr =  $read_addr+3;
+            $results{$num}{sent_pck}=hex($data[$sent_pck_addr]);
+            $results{$num}{got_pck}=hex($data[$got_pck_addr]);
+            $results{$num}{latency}=hex($data[$latency_addr]);
+            $results{$num}{worst_latency}=hex($data[$worst_latency_addr]);
+            #add_info($info, "$num, ");
+            #print "$results{$num}{sent_pck}=hex($data[$sent_pck_addr]);\n";
+            $sum_of_latency+=$results{$num}{latency};
+            $sum_of_pck+=$results{$num}{got_pck};
+            $total_router++ if($results{$num}{sent_pck}>0);
+        #$i=$i+2;
+    }
+    #add_info($info, "\n");
+    return (\%results,$sum_of_latency,$sum_of_pck,$total_router);
 }
 
-
-sub read_pack_gen{ 
-	my ($emulate,$sample,$info,$jtag_intfc,$ratio_in)= @_;
-	my $ref=$emulate->object_get_attribute($sample,"noc_info"); 
-	my ($topology, $T1, $T2, $T3, $V, $Fpay) = get_sample_emulation_param($emulate,$sample);
-	my ($NE, $NR, $RAw, $EAw, $Fw) = get_topology_info_sub ($topology, $T1, $T2, $T3, $V, $Fpay);
-#wait for done 
+sub read_pack_gen{
+    my ($emulate,$sample,$info,$jtag_intfc,$ratio_in)= @_;
+    my $ref=$emulate->object_get_attribute($sample,"noc_info");
+    my ($NE, $NR, $RAw, $EAw, $Fw) = get_sample_topology_info ($emulate,$sample);
+#wait for done
     add_info($info, "wait for done\n");
     my $done=0;
     my $counter=0;
     while ($done ==0){
-		usleep(300000);
-		#my ($result,$exit) = run_cmd_in_back_ground_get_stdout("quartus_stp -t ./lib/tcl/read.tcl done");
-		my ($result,$exit) = run_cmd_in_back_ground_get_stdout("bash $jtag_intfc".READ_DONE_CMD);
-		if($exit != 0 ){
-			add_colored_info($info,$result,'red');
-			return undef;
-		}
-		my @q =split  (/###read data#/,$result);
-		#print "\$result=$result\n";
-		
-		
-		$done=($q[1] eq "0x0")? 0 : 1;
-		#print "\$q[1]=$q[1] done=$done\n";
-		
-		$counter++;
-		if($counter == 15){ # 
-			add_info($info,"Done is not asserted. I reset the board and try again\n");
-			return if(run_cmd_update_info (reset_cmd(1,1,$jtag_intfc),$info));
-			#run_cmd_in_back_ground("quartus_stp -t ./lib/tcl/mem.tcl reset");
-			usleep(300000);
-			return if(run_cmd_update_info (reset_cmd(0,0,$jtag_intfc),$info));
-			#run_cmd_in_back_ground("quartus_stp -t ./lib/tcl/mem.tcl unreset");			
-		}
-		if($counter>30){
-			  #something is wrong
-			add_colored_info($info,"Done is not asserted again. I  am going to ignore this test case\n",'green'); 
-			return undef;
-		}
-	}
-    
-	add_info($info,"Done is asserted\nStart reading statistic data from cores:\n\t");
-	#print" Done is asserted\n";
-	#my $i=0;
-	#my ($results_ref,$sum_of_latency,$sum_of_pck,$total_router)= read_statistic_mem($NE,$jtag_intfc,$info);
-	my ($results_ref,$sum_of_latency,$sum_of_pck,$total_router)= read_statistic_mem_fast($NE,$jtag_intfc,$info);
-	my %results=%$results_ref;
-	
-	
-	foreach my $p (sort keys %results){
-		update_result($emulate,$sample,"packet_rsvd_result",$ratio_in,$p,$results{$p}{got_pck} );
-		update_result($emulate,$sample,"packet_sent_result",$ratio_in,$p,$results{$p}{sent_pck});
-		update_result($emulate,$sample,"worst_delay_rsvd_result",$ratio_in,$p,$results{$p}{worst_latency});
-		#print "$p  : \n latency: $results{$p}{latency}\n";
-		#print "got_pck : $results{$p}{got_pck}\n";
-		#print "sent_pck:$results{$p}{sent_pck}\n\n";
-		#print "worst_delay:$results{$p}{worst_latency}\n\n";
-
-	} 
-	#print "total active router=$total_router\n";
-	#read clock counter
-	my $clk_counter;
-	my ($result,$exit) = run_cmd_in_back_ground_get_stdout("bash $jtag_intfc".READ_COUNTER_CMD);
-	if($exit != 0 ){
-		add_colored_info($info,$result,'red');
-		
-	}else {
-		
-		my @q =split  (/###read data#/,$result);
-		my $d=$q[1];
-		my $s= substr $d,2;
-		$clk_counter= hex($s);
-		
-	}
-	
-	my $avg_latency= ($sum_of_pck>0)? $sum_of_latency/$sum_of_pck : 0;
-	my $packet_size=$emulate->object_get_attribute($sample,"PCK_SIZE");
-	my $avg_throughput= ($sum_of_pck>0 && $total_router>0 && $clk_counter>0 )? (($sum_of_pck * $packet_size *100)/ $total_router )/$clk_counter:0;
-	#print "($sum_of_pck * $packet_size *100)/ $total_router )/$clk_counter = $avg_throughput)";
-	
-	#print "$avg = $sum_of_latency/$sum_of_pck ";
-	$avg_latency= sprintf("%.1f", $avg_latency);
-	
-	 update_result ($emulate,$sample,"latency_result",$ratio_in,$avg_latency);
-	 update_result ($emulate,$sample,"throughput_result",$ratio_in,$avg_throughput);
-	 update_result ($emulate,$sample,"exe_time_result",$ratio_in,$clk_counter);
-	 
-	
-	return 1;
-}	
-
+        usleep(300000);
+        #my ($result,$exit) = run_cmd_in_back_ground_get_stdout("quartus_stp -t ./lib/tcl/read.tcl done");
+        my ($result,$exit) = run_cmd_in_back_ground_get_stdout("bash $jtag_intfc".READ_DONE_CMD);
+        if($exit != 0 ){
+            add_colored_info($info,$result,'red');
+            return undef;
+        }
+        my @q =split  (/###read data#/,$result);
+        #print "\$result=$result\n";
+        $done=($q[1] eq "0x0")? 0 : 1;
+        #print "\$q[1]=$q[1] done=$done\n";
+        $counter++;
+        if($counter == 15){ #
+            add_info($info,"Done is not asserted. I reset the board and try again\n");
+            return if(run_cmd_update_info (reset_cmd(1,1,$jtag_intfc),$info));
+            #run_cmd_in_back_ground("quartus_stp -t ./lib/tcl/mem.tcl reset");
+            usleep(300000);
+            return if(run_cmd_update_info (reset_cmd(0,0,$jtag_intfc),$info));
+            #run_cmd_in_back_ground("quartus_stp -t ./lib/tcl/mem.tcl unreset");
+        }
+        if($counter>30){
+            #something is wrong
+            add_colored_info($info,"Done is not asserted again. I  am going to ignore this test case\n",'green');
+            return undef;
+        }
+    }
+    add_info($info,"Done is asserted\nStart reading statistic data from cores:\n\t");
+    #print" Done is asserted\n";
+    #my $i=0;
+    #my ($results_ref,$sum_of_latency,$sum_of_pck,$total_router)= read_statistic_mem($NE,$jtag_intfc,$info);
+    my ($results_ref,$sum_of_latency,$sum_of_pck,$total_router)= read_statistic_mem_fast($NE,$jtag_intfc,$info);
+    my %results=%$results_ref;
+    foreach my $p (sort keys %results){
+        update_result($emulate,$sample,"packet_rsvd_result",$ratio_in,$p,$results{$p}{got_pck} );
+        update_result($emulate,$sample,"packet_sent_result",$ratio_in,$p,$results{$p}{sent_pck});
+        update_result($emulate,$sample,"worst_delay_rsvd_result",$ratio_in,$p,$results{$p}{worst_latency});
+        #print "$p  : \n latency: $results{$p}{latency}\n";
+        #print "got_pck : $results{$p}{got_pck}\n";
+        #print "sent_pck:$results{$p}{sent_pck}\n\n";
+        #print "worst_delay:$results{$p}{worst_latency}\n\n";
+    }
+    #print "total active router=$total_router\n";
+    #read clock counter
+    my $clk_counter;
+    my ($result,$exit) = run_cmd_in_back_ground_get_stdout("bash $jtag_intfc".READ_COUNTER_CMD);
+    if($exit != 0 ){
+        add_colored_info($info,$result,'red');
+    }else {
+        my @q =split  (/###read data#/,$result);
+        my $d=$q[1];
+        my $s= substr $d,2;
+        $clk_counter= hex($s);
+    }
+    my $avg_latency= ($sum_of_pck>0)? $sum_of_latency/$sum_of_pck : 0;
+    my $packet_size=$emulate->object_get_attribute($sample,"PCK_SIZE");
+    my $avg_throughput= ($sum_of_pck>0 && $total_router>0 && $clk_counter>0 )? (($sum_of_pck * $packet_size *100)/ $total_router )/$clk_counter:0;
+    #print "($sum_of_pck * $packet_size *100)/ $total_router )/$clk_counter = $avg_throughput)";
+    #print "$avg = $sum_of_latency/$sum_of_pck ";
+    $avg_latency= sprintf("%.1f", $avg_latency);
+    update_result ($emulate,$sample,"latency_result",$ratio_in,$avg_latency);
+    update_result ($emulate,$sample,"throughput_result",$ratio_in,$avg_throughput);
+    update_result ($emulate,$sample,"exe_time_result",$ratio_in,$clk_counter);
+    return 1;
+}
+1;
diff --git a/mpsoc/perl_gui/lib/perl/emulator.pl b/mpsoc/perl_gui/lib/perl/emulator.pl
index b418461..31c6e95 100755
--- a/mpsoc/perl_gui/lib/perl/emulator.pl
+++ b/mpsoc/perl_gui/lib/perl/emulator.pl
@@ -2,1349 +2,1024 @@
 use constant::boolean;
 use strict;
 use warnings;
-
 use FindBin;
 use lib $FindBin::Bin;
-
 use GD::Graph::Data;
 use emulator;
-
 use GD::Graph::colour qw/:colours/;
-
 use File::Basename;
 use File::Path qw/make_path/;
 use File::Copy;
 use File::Find::Rule;
-
-require "widget.pl"; 
-require "emulate_ram_gen.pl"; 
-require "mpsoc_gen.pl"; 
-require "mpsoc_verilog_gen.pl"; 
+require "widget.pl";
+require "emulate_ram_gen.pl";
+require "mpsoc_gen.pl";
+require "mpsoc_verilog_gen.pl";
 require "readme_gen.pl";
 require "graph.pl";
 require "topology.pl";
-
 use List::MoreUtils qw(uniq);
-
-
 # hardware parameters taken from noc_emulator.v
 use constant PCK_CNTw =>30;  # packet counter width in bits (results in maximum of 2^30 = 1  G packets)
 use constant PCK_SIZw =>14;  # packet size width in bits (results in maximum packet size of 2^14 = 16 K flit)
 use constant MAX_EAw    =>8;   # maximum  destination address width
-use constant MAXCw    =>4;   # 16 message classes  
+use constant MAXCw    =>4;   # 16 message classes
 use constant RATIOw   =>7;   # log2(100)
 use constant RAM_Aw   =>7;
 use constant RAM_RESERVED_ADDR_NUM=>8;
-use constant MAX_PATTERN => ((2**RAM_Aw)-(RAM_RESERVED_ADDR_NUM));  
-use constant RAM_SIZE => (2**RAM_Aw);       
-
-    
+use constant MAX_PATTERN => ((2**RAM_Aw)-(RAM_RESERVED_ADDR_NUM));
+use constant RAM_SIZE => (2**RAM_Aw);
 #use constant MAX_PCK_NUM => (2**PCK_CNTw)-1;
 use constant MAX_PCK_NUM => (2**PCK_CNTw)-1;
-use constant MAX_PCK_SIZ => (2**PCK_SIZw)-1; 
-use constant MAX_SIM_CLKs=> 1000000000; # simulation end at if clock counter reach this number 
-
-          
+use constant MAX_PCK_SIZ => (2**PCK_SIZw)-1;
+use constant MAX_SIM_CLKs=> 1000000000; # simulation end at if clock counter reach this number
 use constant MAX_RATIO => 1000;# 0->0 1->0.1 ...  1000->100
-
 use constant EMULATION_TOP => "/mpsoc/rtl/src_emulate/emulator_top.v";
-
-
 sub get_MAX_PCK_NUM(){MAX_PCK_NUM}
+
 sub get_MAX_SIM_CLKs(){MAX_SIM_CLKs}
+
 sub get_MAX_PCK_SIZ(){MAX_PCK_SIZ}
 
 sub check_inserted_ratios {
-		my $str=shift;
-		my @ratios;
-	    	
-	    my @chunks=split(/\s*,\s*/,$str);
-	    foreach my $p (@chunks){
-			if($p !~ /^[0-9.:,]+$/){ message_dialog ("$p has invalid character(S)" ); return undef; }
-			my @range=split(':',$p);
-			my $size= scalar @range;
-			if($size==1){ # its a number
-				if ( $range[0] <= 0 || $range[0] >100  ) { message_dialog ("Injection ratio $range[0] is out of bounds: 1<=ratio=<100" ); return undef; }
-				push(@ratios,$range[0]);
-			}elsif($size ==3){# its a range
-				my($min,$max,$step)=@range;
-				if ( $min <= 0 || $min >100  ) { message_dialog ("Injection ratio $min in  $p is out of bounds: 1<=ratio=<100" ); return undef; }
-				if ( $max <= 0 || $max >100  ) { message_dialog ("Injection ratio $max in  $p is out of bounds: 1<=ratio=<100" ); return undef; }
-				for (my $i=$min; $i<=$max; $i=$i+$step){
-						push(@ratios,$i);
-				}			
-				
-			}else{
-				 message_dialog ("Injection ratio $p has an invalid format. The correct format for range is \[min\]:\[max\]:\[step\]" );
-				 return undef;
-			}			
-			
-		}#foreach
-		my @r=uniq(sort {$a<=>$b} @ratios);
-		return \@r;
-			
+    my $str=shift;
+    my @ratios;
+    my @chunks=split(/\s*,\s*/,$str);
+    foreach my $p (@chunks){
+        if($p !~ /^[0-9.:,]+$/){ message_dialog ("$p has invalid character(S)" ); return undef; }
+        my @range=split(':',$p);
+        my $size= scalar @range;
+        if($size==1){ # its a number
+            if ( $range[0] <= 0 || $range[0] >100  ) { message_dialog ("Injection ratio $range[0] is out of bounds: 1<=ratio=<100" ); return undef; }
+            push(@ratios,$range[0]);
+        }elsif($size ==3){# its a range
+            my($min,$max,$step)=@range;
+            if ( $min <= 0 || $min >100  ) { message_dialog ("Injection ratio $min in  $p is out of bounds: 1<=ratio=<100" ); return undef; }
+            if ( $max <= 0 || $max >100  ) { message_dialog ("Injection ratio $max in  $p is out of bounds: 1<=ratio=<100" ); return undef; }
+            for (my $i=$min; $i<=$max; $i=$i+$step){
+                push(@ratios,$i);
+            }
+        }else{
+            message_dialog ("Injection ratio $p has an invalid format. The correct format for range is \[min\]:\[max\]:\[step\]" );
+            return undef;
+        }
+    }#foreach
+    my @r=uniq(sort {$a<=>$b} @ratios);
+    return \@r;
 }
 
-
 sub get_injection_ratios{
-		my ($emulate,$atrebute1,$atrebute2)=@_;
-		my $box =def_hbox(FALSE, 0);
-		my $init=$emulate->object_get_attribute($atrebute1,$atrebute2);
-		my $entry=gen_entry($init);
-		my $button=def_image_button("icons/right.png",'Check');		
-		$button->signal_connect("clicked" => sub {
-			my $text= $entry->get_text();
-			my $r=check_inserted_ratios($text);	
-			if(defined 	$r){	
-				my $all=  join (',',@$r);
-				message_dialog ("$all" );
-			}
-			
-			
-		});	
-		$entry->signal_connect ("changed" => sub {	
-			my $text= $entry->get_text();
-			$emulate->object_add_attribute($atrebute1,$atrebute2,$text);
-			
-		});	
-		$box->pack_start( $entry, 1,1, 0);
-		$box->pack_start( $button, 0, 1, 3);
-		return 	$box;
+    my ($emulate,$atrebute1,$atrebute2)=@_;
+    my $box =def_hbox(FALSE, 0);
+    my $init=$emulate->object_get_attribute($atrebute1,$atrebute2);
+    my $entry=gen_entry($init);
+    my $button=def_image_button("icons/right.png",'Check');
+    $button->signal_connect("clicked" => sub {
+        my $text= $entry->get_text();
+        my $r=check_inserted_ratios($text);
+        if(defined $r){
+            my $all=  join (',',@$r);
+            message_dialog ("$all" );
+        }
+    });
+    $entry->signal_connect ("changed" => sub {
+        my $text= $entry->get_text();
+        $emulate->object_add_attribute($atrebute1,$atrebute2,$text);
+    });
+    $box->pack_start( $entry, 1,1, 0);
+    $box->pack_start( $button, 0, 1, 3);
+    return $box;
 }
 
-
-
 sub get_noc_configuration{
-	my ($emulate,$mode,$sample,$set_win) =@_;	
-	if($mode eq "simulate") {get_simulator_noc_configuration(@_); return;} 
-	get_emulator_noc_configuration(@_);
+    my ($emulate,$mode,$sample,$set_win) =@_;
+    if($mode eq "simulate") {get_simulator_noc_configuration(@_); return;}
+    get_emulator_noc_configuration(@_);
 }
 
 sub get_sof_file_full_addr{
-	my ($emulate,$sample)=@_;
-	my $open_in	= $emulate->object_get_attribute($sample,"sof_path");	
-	my $board	= $emulate->object_get_attribute($sample,"FPGA_board");	
-	my $file	= $emulate->object_get_attribute($sample,"sof_file");
-	return undef if(!defined ${open_in} || !defined ${board} || !defined $file );
-	my $sof = "${open_in}/${board}/$file";
-	#print "\n$sof\n";
-	return $sof;
+    my ($emulate,$sample)=@_;
+    my $open_in    = $emulate->object_get_attribute($sample,"sof_path");
+    my $board    = $emulate->object_get_attribute($sample,"FPGA_board");
+    my $file    = $emulate->object_get_attribute($sample,"sof_file");
+    return undef if(!defined ${open_in} || !defined ${board} || !defined $file );
+    my $sof = "${open_in}/${board}/$file";
+    #print "\n$sof\n";
+    return $sof;
 }
 
-
 sub get_emulator_noc_configuration{
-	my ($emulate,$mode,$sample,$set_win) =@_;	
-	my $table=def_table(10,2,FALSE);
-	my $row=0;
-		
-	my $traffics="tornado,transposed 1,transposed 2,bit reverse,bit complement,random,shuffle,bit rotation,neighbor"; #TODO hot spot for emulator
-	
-	#search path	
-	my $dir = Cwd::getcwd();
-	my $open_in	  = abs_path("$ENV{PRONOC_WORK}/emulate/sof");		
-	attach_widget_to_table ($table,$row,gen_label_in_left("Search Path:"),gen_button_message ("Select the Path where the verilator simulation files are located. Different NoC verilated models can be generated using Generate NoC configuration tab.","icons/help.png"), 
-	get_dir_in_object ($emulate,$sample,"sof_path",undef,'ref_set_win',1,$open_in)); $row++;
-	$open_in	= $emulate->object_get_attribute($sample,"sof_path");	
-	
-	
-	
-	#select the board
-	my($label,$param,$default,$content,$type,$info);
-	my @dirs = grep {-d} glob("$open_in/*");
-	my $fpgas;
-	foreach my $dir (@dirs) {
-		my ($name,$path,$suffix) = fileparse("$dir",qr"\..[^.]*$");
-		$default=$name;
-		$fpgas= (defined $fpgas)? "$fpgas,$name" : "$name";		
-	}	
-	
-	attach_widget_to_table ($table,$row,gen_label_in_left("Select FPGA board:"),gen_button_message ("Select the FPGA board. You can add your own FPGA board by adding its configuration file to mpsoc/boards directory","icons/help.png"), 
-	gen_combobox_object ($emulate,$sample, "FPGA_board", $fpgas, undef,'ref_set_win',1)); $row++;
-	
-	
-	#select the sram object file
-	my $board	= $emulate->object_get_attribute($sample,"FPGA_board");	
-	my @files;
-	@files = glob "${open_in}/${board}/*" if(defined $board);
-	my $sof_files="";
-	foreach my $file (@files){
-		my ($name,$path,$suffix) = fileparse("$file",qr"\..[^.]*$");
-		$sof_files="$sof_files,$name" if($suffix eq '.sof');			
-	}		
-	attach_widget_to_table ($table,$row,gen_label_in_left("Sram Object File:"),gen_button_message ("Select the verilator simulation file. Different NoC simulators can be generated using Generate NoC configuration tab.","icons/help.png"), 
-	gen_combobox_object ($emulate,$sample, "sof_file", $sof_files, undef,undef,undef)); $row++;	
-		
-		
-		
-	#attach_widget_to_table ($table,$row,gen_label_in_left("SoF file:"),gen_button_message ("Select the SRAM Object File (sof) for this NoC configration.","icons/help.png"), get_file_name_object ($emulate,$sample,"sof_file",'sof',$open_in)); $row++;
-	
-
-   my @emulateinfo = (
-	{ label=>'Configuration name:', param_name=>'line_name', type=>'Entry', default_val=>$sample, content=>undef, info=>"NoC configration name. This name will be shown in load-latency graph for this configuration", param_parent=>$sample, ref_delay=> undef},
-
-  	{ label=>"Traffic name", param_name=>'traffic', type=>'Combo-box', default_val=>'random', content=>$traffics, info=>"Select traffic pattern", param_parent=>$sample, ref_delay=>undef},
-
-{ label=>"Packet size in flit:", param_name=>'PCK_SIZE', type=>'Spin-button', default_val=>4, content=>"2,".MAX_PCK_SIZ.",1", info=>undef, param_parent=>$sample, ref_delay=>undef},
-
-	{ label=>"Packet number limit per node:", param_name=>'PCK_NUM_LIMIT', type=>'Spin-button', default_val=>1000000, content=>"2,".MAX_PCK_NUM.",1", info=>"Each node stops sending packets when it reaches packet number limit  or simulation clock number limit", param_parent=>$sample, ref_delay=>undef},
-
-{ label=>"Emulation clocks limit:", param_name=>'SIM_CLOCK_LIMIT', type=>'Spin-button', default_val=>MAX_SIM_CLKs, content=>"2,".MAX_SIM_CLKs.",1", info=>"Each node stops sending packets when it reaches packet number limit  or simulation clock number limit", param_parent=>$sample, ref_delay=>undef},
-
-	
-);
-
-
-
-	my @siminfo = (
-	{ label=>'Configuration name:', param_name=>'line_name', type=>'Entry', default_val=>$sample, content=>undef, info=>"NoC configration name. This name will be shown in load-latency graph for this configuration", param_parent=>$sample, ref_delay=> undef, new_status=>undef},
-
-  	{ label=>"Traffic name", param_name=>'traffic', type=>'Combo-box', default_val=>'random', content=>$traffics, info=>"Select traffic pattern", param_parent=>$sample, ref_delay=>1, new_status=>'ref_set_win'},
-
-	{ label=>"Packet size in flit:", param_name=>'PCK_SIZE', type=>'Spin-button', default_val=>4, content=>"2,".MAX_PCK_SIZ.",1", info=>undef, param_parent=>$sample, ref_delay=>undef},
-
-	{ label=>"Total packet number limit:", param_name=>'PCK_NUM_LIMIT', type=>'Spin-button', default_val=>200000, content=>"2,".MAX_PCK_NUM.",1", info=>"Simulation will stop when total numbr of sent packets by all nodes reaches packet number limit  or total simulation clock reach its limit", param_parent=>$sample, ref_delay=>undef, new_status=>undef},
-
-	{ label=>"Simulator clocks limit:", param_name=>'SIM_CLOCK_LIMIT', type=>'Spin-button', default_val=>100000, content=>"2,".MAX_SIM_CLKs.",1", info=>"Each node stops sending packets when it reaches packet number limit  or simulation clock number limit", param_parent=>$sample, ref_delay=>undef,  new_status=>undef},
-	);
-
-
-my $hot_num=$emulate->object_get_attribute($sample,"HOTSPOT_NUM");
-$hot_num=1 if(!defined $hot_num); 
-my $max= ($hot_num>0)? 100/$hot_num: 20;
-
-my @hotspot_info=(
-	{ label=>'Hot Spot num:', param_name=>'HOTSPOT_NUM', type=>'Spin-button', default_val=>1, 
-	  content=>"1,5,1", info=>"Number of hot spot nodes in the network", 
-	  param_parent=>$sample, ref_delay=> 1, new_status=>'ref_set_win'},
-	{ label=>'Hot Spot traffic percentage:', param_name=>'HOTSPOT_PERCENTAGE', type=>'Spin-button', default_val=>1, 
-	  content=>"1, $max,1", info=>"If it is set as n then each node sends n % of its traffic to each hotspot node", 
-	  param_parent=>$sample, ref_delay=> undef, new_status=>undef},
-	  
-	{ label=>'Hot Spot nodes send enable:', param_name=>'HOTSPOT_SEND', type=>'Combo-box', default_val=>1, 
-	  content=>"0,1", info=>"If it is set as 0 then hot spot nodes only recieves packet from other nodes and do not send packets to others", 
-	  param_parent=>$sample, ref_delay=> undef, new_status=>undef},  
-	  
-	
-	);
-	
-		
-	my @info= ($mode eq "simulate")? @siminfo : @emulateinfo; 
-	
-	my $coltmp=0;	
-	foreach my $d ( @info) {
-		($row,$coltmp)=add_param_widget ($emulate, $d->{label}, $d->{param_name}, $d->{default_val}, $d->{type}, $d->{content}, $d->{info}, $table,$row,undef,1, $d->{param_parent}, $d->{ref_delay}, $d->{new_status});
-	}
-	my $traffic=$emulate->object_get_attribute($sample,"traffic");
-
-	if ($traffic eq 'hot spot'){
-		foreach my $d ( @hotspot_info) {
-			($row,$coltmp)=add_param_widget  ($emulate, $d->{label}, $d->{param_name}, $d->{default_val}, $d->{type}, $d->{content}, $d->{info}, $table,$row,1, $d->{param_parent}, $d->{ref_delay}, $d->{new_status});
-		}
-		my $num=$emulate->object_get_attribute($sample,"HOTSPOT_NUM");
-		for (my $i=0;$i<$num;$i++){
-			my $m=$i+1;
-			($row,$coltmp)=add_param_widget  ($emulate, "Hotspot $m tile num:", "HOTSPOT_CORE_$m", 0, 'Spin-button', "0,256,1",
-			 "Defne the tile number which is  hotspt. All other nodes will send [Hot Spot traffic percentage] of their traffic to this node ", $table,$row,undef,1,$sample);
-					
-		}
-	
-	}
-	my $l= "Injection ratios in flits/clk/Endpoint (%). 
-E.g. Injection ratio 10% means each endpoint inject one flit every 10 cycles. 
+    my ($emulate,$mode,$sample,$set_win) =@_;
+    my $table=def_table(10,2,FALSE);
+    my $row=0;
+    my $traffics="tornado,transposed 1,transposed 2,bit reverse,bit complement,random,shuffle,bit rotation,neighbor"; #TODO hot spot for emulator
+    #search path
+    my $dir = Cwd::getcwd();
+    my $open_in      = abs_path("$ENV{PRONOC_WORK}/emulate/sof");
+    attach_widget_to_table ($table,$row,gen_label_in_left("Search Path:"),gen_button_message ("Select the Path where the verilator simulation files are located. Different NoC verilated models can be generated using Generate NoC configuration tab.","icons/help.png"),
+    get_dir_in_object ($emulate,$sample,"sof_path",undef,'ref_set_win',1,$open_in)); $row++;
+    $open_in    = $emulate->object_get_attribute($sample,"sof_path");
+    #select the board
+    my($label,$param,$default,$content,$type,$info);
+    my @dirs = grep {-d} glob("$open_in/*");
+    my $fpgas;
+    foreach my $dir (@dirs) {
+        my ($name,$path,$suffix) = fileparse("$dir",qr"\..[^.]*$");
+        $default=$name;
+        $fpgas= (defined $fpgas)? "$fpgas,$name" : "$name";
+    }
+    attach_widget_to_table ($table,$row,gen_label_in_left("Select FPGA board:"),gen_button_message ("Select the FPGA board. You can add your own FPGA board by adding its configuration file to mpsoc/boards directory","icons/help.png"),
+    gen_combobox_object ($emulate,$sample, "FPGA_board", $fpgas, undef,'ref_set_win',1)); $row++;
+    #select the sram object file
+    my $board    = $emulate->object_get_attribute($sample,"FPGA_board");
+    my @files;
+    @files = glob "${open_in}/${board}/*" if(defined $board);
+    my $sof_files="";
+    foreach my $file (@files){
+        my ($name,$path,$suffix) = fileparse("$file",qr"\..[^.]*$");
+        $sof_files="$sof_files,$name" if($suffix eq '.sof');
+    }
+    attach_widget_to_table ($table,$row,gen_label_in_left("Sram Object File:"),gen_button_message ("Select the verilator simulation file. Different NoC simulators can be generated using Generate NoC configuration tab.","icons/help.png"),
+    gen_combobox_object ($emulate,$sample, "sof_file", $sof_files, undef,undef,undef)); $row++;
+    #attach_widget_to_table ($table,$row,gen_label_in_left("SoF file:"),gen_button_message ("Select the SRAM Object File (sof) for this NoC configration.","icons/help.png"), get_file_name_object ($emulate,$sample,"sof_file",'sof',$open_in)); $row++;
+    my @emulateinfo = (
+    { label=>'Configuration name:', param_name=>'line_name', type=>'Entry', default_val=>$sample, content=>undef, info=>"NoC configration name. This name will be shown in load-latency graph for this configuration", param_parent=>$sample, ref_delay=> undef},
+    { label=>"Traffic name", param_name=>'traffic', type=>'Combo-box', default_val=>'random', content=>$traffics, info=>"Select traffic pattern", param_parent=>$sample, ref_delay=>undef},
+    { label=>"Packet size in flit:", param_name=>'PCK_SIZE', type=>'Spin-button', default_val=>4, content=>"2,".MAX_PCK_SIZ.",1", info=>undef, param_parent=>$sample, ref_delay=>undef},
+    { label=>"Packet number limit per node:", param_name=>'PCK_NUM_LIMIT', type=>'Spin-button', default_val=>1000000, content=>"2,".MAX_PCK_NUM.",1", info=>"Each node stops sending packets when it reaches packet number limit  or simulation clock number limit", param_parent=>$sample, ref_delay=>undef},
+    { label=>"Emulation clocks limit:", param_name=>'SIM_CLOCK_LIMIT', type=>'Spin-button', default_val=>MAX_SIM_CLKs, content=>"2,".MAX_SIM_CLKs.",1", info=>"Each node stops sending packets when it reaches packet number limit  or simulation clock number limit", param_parent=>$sample, ref_delay=>undef},
+    );
+    my @siminfo = (
+    { label=>'Configuration name:', param_name=>'line_name', type=>'Entry', default_val=>$sample, content=>undef, info=>"NoC configration name. This name will be shown in load-latency graph for this configuration", param_parent=>$sample, ref_delay=> undef, new_status=>undef},
+    { label=>"Traffic name", param_name=>'traffic', type=>'Combo-box', default_val=>'random', content=>$traffics, info=>"Select traffic pattern", param_parent=>$sample, ref_delay=>1, new_status=>'ref_set_win'},
+    { label=>"Packet size in flit:", param_name=>'PCK_SIZE', type=>'Spin-button', default_val=>4, content=>"2,".MAX_PCK_SIZ.",1", info=>undef, param_parent=>$sample, ref_delay=>undef},
+    { label=>"Total packet number limit:", param_name=>'PCK_NUM_LIMIT', type=>'Spin-button', default_val=>200000, content=>"2,".MAX_PCK_NUM.",1", info=>"Simulation will stop when total numbr of sent packets by all nodes reaches packet number limit  or total simulation clock reach its limit", param_parent=>$sample, ref_delay=>undef, new_status=>undef},
+    { label=>"Simulator clocks limit:", param_name=>'SIM_CLOCK_LIMIT', type=>'Spin-button', default_val=>100000, content=>"2,".MAX_SIM_CLKs.",1", info=>"Each node stops sending packets when it reaches packet number limit  or simulation clock number limit", param_parent=>$sample, ref_delay=>undef,  new_status=>undef},
+    );
+    my $hot_num=$emulate->object_get_attribute($sample,"HOTSPOT_NUM");
+    $hot_num=1 if(!defined $hot_num);
+    my $max= ($hot_num>0)? 100/$hot_num: 20;
+    my @hotspot_info=(
+    {   label=>'Hot Spot num:', param_name=>'HOTSPOT_NUM', type=>'Spin-button', default_val=>1,
+        content=>"1,5,1", info=>"Number of hot spot nodes in the network",
+        param_parent=>$sample, ref_delay=> 1, new_status=>'ref_set_win'},
+    {   label=>'Hot Spot traffic percentage:', param_name=>'HOTSPOT_PERCENTAGE', type=>'Spin-button', default_val=>1,
+        content=>"1, $max,1", info=>"If it is set as n then each node sends n % of its traffic to each hotspot node",
+        param_parent=>$sample, ref_delay=> undef, new_status=>undef},
+    {   label=>'Hot Spot nodes send enable:', param_name=>'HOTSPOT_SEND', type=>'Combo-box', default_val=>1,
+        content=>"0,1", info=>"If it is set as 0 then hot spot nodes only recieves packet from other nodes and do not send packets to others",
+        param_parent=>$sample, ref_delay=> undef, new_status=>undef},
+    );
+    my @info= ($mode eq "simulate")? @siminfo : @emulateinfo;
+    my $coltmp=0;
+    foreach my $d ( @info) {
+        ($row,$coltmp)=add_param_widget ($emulate, $d->{label}, $d->{param_name}, $d->{default_val}, $d->{type}, $d->{content}, $d->{info}, $table,$row,undef,1, $d->{param_parent}, $d->{ref_delay}, $d->{new_status});
+    }
+    my $traffic=$emulate->object_get_attribute($sample,"traffic");
+    if ($traffic eq 'hot spot'){
+        foreach my $d ( @hotspot_info) {
+            ($row,$coltmp)=add_param_widget  ($emulate, $d->{label}, $d->{param_name}, $d->{default_val}, $d->{type}, $d->{content}, $d->{info}, $table,$row,1, $d->{param_parent}, $d->{ref_delay}, $d->{new_status});
+        }
+        my $num=$emulate->object_get_attribute($sample,"HOTSPOT_NUM");
+        for (my $i=0;$i<$num;$i++){
+            my $m=$i+1;
+            ($row,$coltmp)=add_param_widget  ($emulate, "Hotspot $m tile num:", "HOTSPOT_CORE_$m", 0, 'Spin-button', "0,256,1",
+            "Defne the tile number which is  hotspt. All other nodes will send [Hot Spot traffic percentage] of their traffic to this node ", $table,$row,undef,1,$sample);
+        }
+    }
+    my $l= "Injection ratios in flits/clk/Endpoint (%).
+E.g. Injection ratio 10% means each endpoint inject one flit every 10 cycles.
 You can define individual ratios seprating by comma (\',\') or define a range of injection ratios with \$min:\$max:\$step format.
 As an example defining 2,3,4:10:2 will result in (2,3,4,6,8,10) injection ratios.
 " ;
-	my $u=get_injection_ratios ($emulate,$sample,"ratios");
-		
-	attach_widget_to_table ($table,$row,gen_label_in_left("Injection ratios:"),gen_button_message ($l,"icons/help.png") , $u); $row++;
-	
-	my $scrolled_win = add_widget_to_scrolled_win($table);
-		
-	my $ok = def_image_button('icons/select.png','OK');
-	my $mtable = def_table(10, 1, TRUE);
-
-	$mtable->attach_defaults($scrolled_win,0,1,0,9);
-	$mtable-> attach ($ok , 0, 1,  9, 10,'expand','shrink',2,2); 
-	
-	add_widget_to_scrolled_win ($mtable,$set_win);
-	$set_win->show_all();
-
-	$set_win ->signal_connect (destroy => sub{
-		
-		$emulate->object_add_attribute("active_setting",undef,undef);
-	});
-
-	
-	
-	$ok->signal_connect("clicked"=> sub{
-		#check if sof file has been selected
-		my $s=get_sof_file_full_addr($emulate,$sample);
-		#check if injection ratios are valid
-		my $r=$emulate->object_get_attribute($sample,"ratios");
-		if(defined $s && defined $r) {	
-				$set_win->hide;
-				$emulate->object_add_attribute("active_setting",undef,undef);
-				set_gui_status($emulate,"ref",1);
-		} else {
-			
-			if(!defined $s){
-				my $m=($mode eq 'simulate') ? "Please select NoC verilated file" : "Please select sof file!";
-				message_dialog($m);  
-			} else {
-				 message_dialog("Please define valid injection ratio(s)!");
-			}
-		}
-	});
-	
-	
-}	
-	 
+    my $u=get_injection_ratios ($emulate,$sample,"ratios");
+    attach_widget_to_table ($table,$row,gen_label_in_left("Injection ratios:"),gen_button_message ($l,"icons/help.png") , $u); $row++;
+    my $scrolled_win = add_widget_to_scrolled_win($table);
+    my $ok = def_image_button('icons/select.png','OK');
+    my $mtable = def_table(10, 1, TRUE);
+    $mtable->attach_defaults($scrolled_win,0,1,0,9);
+    $mtable-> attach ($ok , 0, 1,  9, 10,'expand','shrink',2,2);
+    add_widget_to_scrolled_win ($mtable,$set_win);
+    $set_win->show_all();
+    $set_win ->signal_connect (destroy => sub{
+        $emulate->object_add_attribute("active_setting",undef,undef);
+    });
+    $ok->signal_connect("clicked"=> sub{
+        #check if sof file has been selected
+        my $s=get_sof_file_full_addr($emulate,$sample);
+        #check if injection ratios are valid
+        my $r=$emulate->object_get_attribute($sample,"ratios");
+        if(defined $s && defined $r) {
+                $set_win->hide;
+                $emulate->object_add_attribute("active_setting",undef,undef);
+                set_gui_status($emulate,"ref",1);
+        } else {
+            if(!defined $s){
+                my $m=($mode eq 'simulate') ? "Please select NoC verilated file" : "Please select sof file!";
+                message_dialog($m);
+            } else {
+                message_dialog("Please define valid injection ratio(s)!");
+            }
+        }
+    });
+}
 
-      
 #####################
-#		gen_widgets_column
-###################      
-      
+#      gen_widgets_column
+###################
 sub gen_emulation_column {
-	my ($emulate,$mode, $row_num,$info,$set_win,@charts)=@_;
-	my $table=def_table($row_num,10,FALSE);
-	if(!defined $set_win){
-	 	$set_win=def_popwin_size(40,80,"NoC configuration setting",'percent');	
-	 	$set_win->signal_connect (delete_event => sub {$emulate->object_add_attribute("active_setting",undef,undef); $set_win->hide_on_delete });
-	 	
-	} else{
-		my @childs = $set_win->get_children;
-		foreach my $c (@childs){ $c->destroy;}
-	}
-	my $scrolled_win = gen_scr_win_with_adjst ($emulate,"emulation_column");
-	add_widget_to_scrolled_win($table,$scrolled_win);	
-	my $row=0;
-	
-	#title	
-	my $title_l =($mode eq "simulate" ) ? "NoC Simulator" : "NoC Emulator";
-	my $title=gen_label_in_center($title_l);
-	$table->attach ($title , 0, 10,  $row, $row+1,'expand','shrink',2,2); $row++;
-	add_Hsep_to_table($table,0,10,$row);$row++;
-
-
-	
-	
-	my %order;
-	$order{'+/-'}=0;
-	$order{'Setting'}=1;
-	$order{'Run'}=2;
-	$order{'Name'}=3;
-	$order{'Color'}=4;
-	$order{'Clear'}=5;
-	$order{'Traffic'}=6;	
-	$order{'Done'}=7;
-	
-	foreach my $t (sort keys %order){		
-		$table->attach (gen_label_in_center($t), $order{$t}, $order{$t}+1, $row, $row+1,'expand','shrink',2,2);
-	}
-	
-	my $traffics="Random,Transposed 1,Transposed 2,Tornado";
-
-	
-	$row++;
-	
-
-	
-	#my $i=0;
-	my $active=$emulate->object_get_attribute("active_setting",undef);
-	my @samples; 
-	@samples =$emulate->object_get_attribute_order("samples");
-	
-	
-	
-	foreach my $ss (@samples){
-		
-		
-		my $sample=$ss;
-		#my $sample="sample$i";
-		#my $n=$i;
-		
-		my $name=$emulate->object_get_attribute($sample,"line_name");
-		my $l;
-		my $s=($mode eq "simulate" ) ? 1 : get_sof_file_full_addr($emulate,$sample);
-		#check if injection ratios are valid
-		my $r=$emulate->object_get_attribute($sample,"ratios");
-		if(defined $s  && defined $name){
-			
-			 $l=def_image_button('icons/diagram.png',$name);
-			 $l-> signal_connect("clicked" => sub{ 
-			 	
-			 	__PACKAGE__->mk_accessors(qw{noc_param});
-				my $temp = __PACKAGE__->new();
-			 
-			 	
-						 	
-			 	my $st = ($mode eq "simulate" )?  check_sim_sample($emulate,$sample,$info)   : check_sample($emulate,$sample,$info); 
-			 	return if $st==0;
-			 	my ($topology, $T1, $T2, $T3, $V, $Fpay) = get_sample_emulation_param($emulate,$sample);		
-			  	my $ref=$emulate->object_get_attribute($sample,"noc_info"); 
-			 	if (defined $ref){
-			 		my %noc_info= %$ref;			 	
-			 		foreach my $p (sort keys %noc_info){
-			 			$temp->object_add_attribute('noc_param',$p,$noc_info{$p});			 		
-			 		} 		
-			 	}			 	
-			 	
-        		show_topology_diagram ($temp);
-    		 });
-    		 
-    		 my $traffic = def_button("Pattern");
-    		 $traffic-> signal_connect("clicked" => sub{ 
-    		 	my $st = ($mode eq "simulate" )?  check_sim_sample($emulate,$sample,$info)   : check_sample($emulate,$sample,$info); 
-			 	return if $st==0;
-			 	my ($topology, $T1, $T2, $T3, $V, $Fpay) = get_sample_emulation_param($emulate,$sample);		
-			 	$emulate->object_add_attribute('noc_param','T1',$T1);
-			 	$emulate->object_add_attribute('noc_param','T2',$T2);
-			 	$emulate->object_add_attribute('noc_param','T3',$T3);
-			 	$emulate->object_add_attribute('noc_param','TOPOLOGY',$topology);
-			 	my $pattern="";
-			 	my $traffictype=$emulate->object_get_attribute($sample,"TRAFFIC_TYPE");
-				$pattern=get_synthetic_traffic_pattern($emulate, $sample) if($traffictype eq "Synthetic");
-				$pattern=" Custom traffic based on input file. " if($traffictype eq "Task-graph");
-							 	
-			 	my $window = def_popwin_size(40,40,"Traffic pattern",'percent');
-			 	my ($outbox,$tview)= create_txview();
-			 	show_info($tview,"$pattern");
-			 	$window->add ($outbox);
-				$window->show_all();	 
-			 	
-    		 });
-    		 
-    		 
-    		 $table->attach ($l, $order{'Name'}, $order{'Name'}+1, $row, $row+1,'expand','shrink',2,2);
-    		 $table->attach ($traffic, $order{'Traffic'}, $order{'Traffic'}+1, $row, $row+1,'expand','shrink',2,2);    
-    		
-			 
-		} else {
-			$l=gen_label_in_left("Define NoC configuration");
-			$l->set_markup("<span  foreground= 'red' ><b>Define NoC configuration</b></span>");	
-			$table->attach ($l, $order{'Name'}, $order{'Name'}+1, $row, $row+1,'expand','shrink',2,2);	 
-		}
-				
-
-		#remove 
-		my $remove=def_image_button("icons/cancel.png");
-		$table->attach ($remove,$order{'+/-'},$order{'+/-'}+1, $row, $row+1,'expand','shrink',2,2);
-		$remove->signal_connect("clicked"=> sub{
-			$emulate->object_delete_attribute_order("samples",$sample);
-			set_gui_status($emulate,"ref",2);
-		});
-
-		#setting
-		my $set=def_image_button("icons/setting.png");
-		$table->attach ($set, $order{'Setting'}, $order{'Setting'}+1, $row, $row+1,'expand','shrink',2,2);
-
-		
-		if(defined $active){#The setting windows ask for refershing so open it again
-			get_noc_configuration($emulate,$mode,$sample,$set_win) if	($active eq $sample);
-		}
-		
-		
-		
-		$set->signal_connect("clicked"=> sub{
-			$emulate->object_add_attribute("active_setting",undef,$sample);
-			get_noc_configuration($emulate,$mode,$sample,$set_win);
-		});
-		
-		
-		
-		my $color_num=$emulate->object_get_attribute($sample,"color");
-		if(!defined $color_num){
-			$color_num = (scalar @samples) +1;
-			$emulate->object_add_attribute($sample,"color",$color_num);
-		}
-		my $color=def_colored_button("   ",$color_num);
-		$table->attach ($color, $order{'Color'}, $order{'Color'}+1, $row, $row+1,'fill','fill',2,2);
-		
-		$color->signal_connect("clicked"=> sub{
-			get_color_window($emulate,$sample,"color");
-		});
-		
-		#clear line
-		my $clear = def_image_button('icons/clear.png');
-		$clear->signal_connect("clicked"=> sub{
-			foreach my $chart (@charts){	
-				$emulate->object_add_attribute ($sample,"$chart->{result_name}",undef);
-				
-				#print "\$emulate->object_add_attribute ($sample,$chart->{result_name}_result,undef);";
-				
-			}
-			set_gui_status($emulate,"ref",2);
-		});
-		$table->attach ($clear, $order{'Clear'}, $order{'Clear'}+1, $row, $row+1,'expand','shrink',2,2);
-		#run/pause
-		my $run = def_image_button('icons/run.png',undef);
-		$table->attach ($run, $order{'Run'}, $order{'Run'}+1, $row, $row+1,'expand','shrink',2,2);
-		$run->signal_connect("clicked"=> sub{
-			$emulate->object_add_attribute ($sample,"status","run");
-			#start the emulator if it is not running	
-			my $status= $emulate->object_get_attribute('status',undef);
-			if($status ne 'run'){
-				
-				run_emulator($emulate,$info) if($mode eq 'emulate');
-				run_simulator($emulate,$info) if($mode eq 'simulate');  
-				set_gui_status($emulate,"ref",2);
-			}
-			
-		});
-		
-		my $image = gen_noc_status_image($emulate,$sample);		
-		$table->attach ($image, $order{'Done'},$order{'Done'}+1, $row, $row+1,'expand','shrink',2,2);
-				
-		$row++;
-		
-	}
-	# add new simulation
-
-	my $add=def_image_button("icons/plus.png",' A_dd ',FALSE,1);
-	$table->attach ($add, $order{'+/-'},$order{'+/-'}+2, $row, $row+1,'expand','shrink',2,2);
-
-	  
-
-	$add->signal_connect("clicked"=> sub{
-		my $n=$emulate->object_get_attribute("id",undef);
-		$n=0 if (!defined $n);
-		my $sample="sample$n";
-		$n++;
-		$emulate->object_add_attribute("id",undef,$n);
-		$emulate->object_add_attribute("active_setting",undef,$sample);
-		#get_noc_configuration($emulate,$mode,$sample,$set_win);
-		$emulate->object_add_attribute_order("samples",$sample);
-		set_gui_status($emulate,"ref",1);		
-			
-	});	
-
-	
-	 
-	return ($scrolled_win,$set_win);
-}	      
-
-
+    my ($emulate,$mode, $row_num,$info,$set_win,@charts)=@_;
+    my $table=def_table($row_num,10,FALSE);
+    if(!defined $set_win){
+        $set_win=def_popwin_size(40,80,"NoC configuration setting",'percent');
+        $set_win->signal_connect (delete_event => sub {$emulate->object_add_attribute("active_setting",undef,undef); $set_win->hide_on_delete });
+    } else{
+        my @childs = $set_win->get_children;
+        foreach my $c (@childs){ $c->destroy;}
+    }
+    my $scrolled_win = gen_scr_win_with_adjst ($emulate,"emulation_column");
+    add_widget_to_scrolled_win($table,$scrolled_win);
+    my $row=0;
+    #title
+    my $title_l =($mode eq "simulate" ) ? "NoC Simulator" : "NoC Emulator";
+    my $title=gen_label_in_center($title_l);
+    $table->attach ($title , 0, 10,  $row, $row+1,'expand','shrink',2,2); $row++;
+    add_Hsep_to_table($table,0,10,$row);$row++;
+    my %order;
+    $order{'+/-'}=0;
+    $order{'Setting'}=1;
+    $order{'Run'}=2;
+    $order{'Name'}=3;
+    $order{'Color'}=4;
+    $order{'Clear'}=5;
+    $order{'Traffic'}=6;
+    $order{'Done'}=7;
+    foreach my $t (sort keys %order){
+        $table->attach (gen_label_in_center($t), $order{$t}, $order{$t}+1, $row, $row+1,'expand','shrink',2,2);
+    }
+    my $traffics="Random,Transposed 1,Transposed 2,Tornado";
+    $row++;
+    #my $i=0;
+    my $active=$emulate->object_get_attribute("active_setting",undef);
+    my @samples;
+    @samples =$emulate->object_get_attribute_order("samples");
+    foreach my $ss (@samples){
+        my $sample=$ss;
+        #my $sample="sample$i";
+        #my $n=$i;
+        my $name=$emulate->object_get_attribute($sample,"line_name");
+        my $l;
+        my $s=($mode eq "simulate" ) ? 1 : get_sof_file_full_addr($emulate,$sample);
+        #check if injection ratios are valid
+        my $r=$emulate->object_get_attribute($sample,"ratios");
+        if(defined $s  && defined $name){
+            $l=def_image_button('icons/diagram.png',$name);
+            $l-> signal_connect("clicked" => sub{
+                __PACKAGE__->mk_accessors(qw{noc_param});
+                my $temp = __PACKAGE__->new();
+                my $st = ($mode eq "simulate" )?  check_sim_sample($emulate,$sample,$info)   : check_sample($emulate,$sample,$info);
+                return if $st==0;
+                my ($topology, $T1, $T2, $T3, $T4, $V, $Fpay) = get_sample_emulation_param($emulate,$sample);
+                my $ref=$emulate->object_get_attribute($sample,"noc_info");
+                if (defined $ref){
+                    my %noc_info= %$ref;
+                    foreach my $p (sort keys %noc_info){
+                        $temp->object_add_attribute('noc_param',$p,$noc_info{$p});
+                    }
+                }
+                show_topology_diagram ($temp);
+            });
+            my $traffic = def_button("Pattern");
+            $traffic-> signal_connect("clicked" => sub{
+                my $st = ($mode eq "simulate" )?  check_sim_sample($emulate,$sample,$info)   : check_sample($emulate,$sample,$info);
+                return if $st==0;
+                my ($topology, $T1, $T2, $T3, $T4, $V, $Fpay) = get_sample_emulation_param($emulate,$sample);
+                $emulate->object_add_attribute('noc_param','T1',$T1);
+                $emulate->object_add_attribute('noc_param','T2',$T2);
+                $emulate->object_add_attribute('noc_param','T3',$T3);
+                $emulate->object_add_attribute('noc_param','T4',$T4);
+                $emulate->object_add_attribute('noc_param','TOPOLOGY',$topology);
+                my $pattern="";
+                my $traffictype=$emulate->object_get_attribute($sample,"TRAFFIC_TYPE");
+                $pattern=get_synthetic_traffic_pattern($emulate, $sample) if($traffictype eq "Synthetic");
+                $pattern=" Custom traffic based on input file. " if($traffictype eq "Task-graph");
+                my $window = def_popwin_size(40,40,"Traffic pattern",'percent');
+                my ($outbox,$tview)= create_txview();
+                show_info($tview,"$pattern");
+                $window->add ($outbox);
+                $window->show_all();
+            });
+            $table->attach ($l, $order{'Name'}, $order{'Name'}+1, $row, $row+1,'expand','shrink',2,2);
+            $table->attach ($traffic, $order{'Traffic'}, $order{'Traffic'}+1, $row, $row+1,'expand','shrink',2,2);
+        } else {
+            $l=gen_label_in_left("Define NoC configuration");
+            $l->set_markup("<span  foreground= 'red' ><b>Define NoC configuration</b></span>");
+            $table->attach ($l, $order{'Name'}, $order{'Name'}+1, $row, $row+1,'expand','shrink',2,2);
+        }
+        #remove
+        my $remove=def_image_button("icons/cancel.png");
+        $table->attach ($remove,$order{'+/-'},$order{'+/-'}+1, $row, $row+1,'expand','shrink',2,2);
+        $remove->signal_connect("clicked"=> sub{
+            $emulate->object_delete_attribute_order("samples",$sample);
+            set_gui_status($emulate,"ref",2);
+        });
+        #setting
+        my $set=def_image_button("icons/setting.png");
+        $table->attach ($set, $order{'Setting'}, $order{'Setting'}+1, $row, $row+1,'expand','shrink',2,2);
+        if(defined $active){#The setting windows ask for refershing so open it again
+            get_noc_configuration($emulate,$mode,$sample,$set_win) if    ($active eq $sample);
+        }
+        $set->signal_connect("clicked"=> sub{
+            $emulate->object_add_attribute("active_setting",undef,$sample);
+            get_noc_configuration($emulate,$mode,$sample,$set_win);
+        });
+        my $color_num=$emulate->object_get_attribute($sample,"color");
+        if(!defined $color_num){
+            $color_num = (scalar @samples) +1;
+            $emulate->object_add_attribute($sample,"color",$color_num);
+        }
+        my $color=def_colored_button("   ",$color_num);
+        $table->attach ($color, $order{'Color'}, $order{'Color'}+1, $row, $row+1,'fill','fill',2,2);
+        $color->signal_connect("clicked"=> sub{
+            get_color_window($emulate,$sample,"color");
+        });
+        #clear line
+        my $clear = def_image_button('icons/clear.png');
+        $clear->signal_connect("clicked"=> sub{
+            foreach my $chart (@charts){
+                $emulate->object_add_attribute ($sample,"$chart->{result_name}",undef);
+                #print "\$emulate->object_add_attribute ($sample,$chart->{result_name}_result,undef);";
+            }
+            set_gui_status($emulate,"ref",2);
+        });
+        $table->attach ($clear, $order{'Clear'}, $order{'Clear'}+1, $row, $row+1,'expand','shrink',2,2);
+        #run/pause
+        my $run = def_image_button('icons/run.png',undef);
+        $table->attach ($run, $order{'Run'}, $order{'Run'}+1, $row, $row+1,'expand','shrink',2,2);
+        $run->signal_connect("clicked"=> sub{
+            $emulate->object_add_attribute ($sample,"status","run");
+            #start the emulator if it is not running
+            my $status= $emulate->object_get_attribute('status',undef);
+            if($status ne 'run'){
+                run_emulator($emulate,$info) if($mode eq 'emulate');
+                run_simulator($emulate,$info) if($mode eq 'simulate');
+                set_gui_status($emulate,"ref",2);
+            }
+        });
+        my $image = gen_noc_status_image($emulate,$sample);
+        $table->attach ($image, $order{'Done'},$order{'Done'}+1, $row, $row+1,'expand','shrink',2,2);
+        $row++;
+    }
+    # add new simulation
+    my $add=def_image_button("icons/plus.png",' A_dd ',FALSE,1);
+    $table->attach ($add, $order{'+/-'},$order{'+/-'}+2, $row, $row+1,'expand','shrink',2,2);
+    $add->signal_connect("clicked"=> sub{
+        my $n=$emulate->object_get_attribute("id",undef);
+        $n=0 if (!defined $n);
+        my $sample="sample$n";
+        $n++;
+        $emulate->object_add_attribute("id",undef,$n);
+        $emulate->object_add_attribute("active_setting",undef,$sample);
+        #get_noc_configuration($emulate,$mode,$sample,$set_win);
+        $emulate->object_add_attribute_order("samples",$sample);
+        set_gui_status($emulate,"ref",1);
+    });
+    return ($scrolled_win,$set_win);
+}
 
 ##########
 # check_sample
 ##########
-
 sub check_sample{
-	my ($emulate,$sample,$info)=@_;
-	my $status=1;
-	my $sof=get_sof_file_full_addr($emulate,$sample);
-	
-	
-	
-	# ckeck if sample have sof file
-	if(!defined $sof){
-		#add_info($info, "Error: SoF file has not set for $sample!\n");
-		add_colored_info($info, "Error: SoF file has not set for $sample!\n",'red');
-		$emulate->object_add_attribute ($sample,"status","failed");	
-		$status=0;
-	} else {
-		# ckeck if sof file has info file 
-		my ($name,$path,$suffix) = fileparse("$sof",qr"\..[^.]*$");
-		my $sof_info= "$path$name.inf";
-		
-	#	print "\n $sof \t $sof_info\n";
-		
-		if(!(-f $sof_info)){
-			add_colored_info($info, "Error: Could not find $name.inf file in $path. An information file is required for each sof file containig the device name and  NoC configuration. Press F3 for more help.\n",'red');
-			$emulate->object_add_attribute ($sample,"status","failed");	
-			$status=0;
-		}else { #add info
-			my $pp= do $sof_info ;
-
-			my $p=$pp->{'noc_param'};
-			
-			$status=0 if $@;
-			message_dialog("Error reading: $@",'error') if $@;
-			if ($status==1){
-				$emulate->object_add_attribute ($sample,"noc_info",$p) ;
-					
-			
-			}			
-		}		
-	}
-				
-	return $status;
+    my ($emulate,$sample,$info)=@_;
+    my $status=1;
+    my $sof=get_sof_file_full_addr($emulate,$sample);
+    # ckeck if sample have sof file
+    if(!defined $sof){
+        #add_info($info, "Error: SoF file has not set for $sample!\n");
+        add_colored_info($info, "Error: SoF file has not set for $sample!\n",'red');
+        $emulate->object_add_attribute ($sample,"status","failed");
+        $status=0;
+    } else {
+        # ckeck if sof file has info file
+        my ($name,$path,$suffix) = fileparse("$sof",qr"\..[^.]*$");
+        my $sof_info= "$path$name.inf";
+    #    print "\n $sof \t $sof_info\n";
+        if(!(-f $sof_info)){
+            add_colored_info($info, "Error: Could not find $name.inf file in $path. An information file is required for each sof file containig the device name and  NoC configuration. Press F3 for more help.\n",'red');
+            $emulate->object_add_attribute ($sample,"status","failed");
+            $status=0;
+        }else { #add info
+            my $pp= do $sof_info ;
+            my $p=$pp->{'noc_param'};
+            $status=0 if $@;
+            message_dialog("Error reading: $@",'error') if $@;
+            if ($status==1){
+                $emulate->object_add_attribute ($sample,"noc_info",$p) ;
+            }
+        }
+    }
+    return $status;
 }
 
-
-
-
-
-
-
-
-
 #############
 #  images
 ##########
 sub get_status_gif{
-		my $emulate=shift;
-		my $status= $emulate->object_get_attribute('status',undef);
-		if($status eq 'ideal'){
-			return show_gif ("icons/ProNoC.png");
-		} elsif ($status eq 'run') {
-			my($width,$hight)=max_win_size();
-			my $image=($width>=1600)? "icons/hamster_l.gif":
-			          ($width>=1200)? "icons/hamster_m.gif": "icons/hamster_s.gif"; 
-				  
-			return show_gif ($image);			
-		} elsif ($status eq 'programmer_failed') {
-			return show_gif ("icons/Error.png");			
-		}
-	
-}	
-
-
-
+        my $emulate=shift;
+        my $status= $emulate->object_get_attribute('status',undef);
+        if($status eq 'ideal'){
+            return show_gif ("icons/ProNoC.png");
+        } elsif ($status eq 'run') {
+            my($width,$hight)=max_win_size();
+            my $image=($width>=1600)? "icons/hamster_l.gif":
+                    ($width>=1200)? "icons/hamster_m.gif": "icons/hamster_s.gif";
+            return show_gif ($image);
+        } elsif ($status eq 'programmer_failed') {
+            return show_gif ("icons/Error.png");
+        }
+}
 
 sub gen_noc_status_image {
-	my ($emulate,$sample)=@_;
-	my   $status= $emulate->object_get_attribute ($sample,"status");	
-	$status='' if(!defined  $status);
-	my $image;
-	my $box = def_hbox(TRUE,1);
-	$image = new_image_from_file ("icons/load.gif") if($status eq "run");
-	$image = def_icon("icons/button_ok.png") if($status eq "done");
-	$image = def_icon("icons/warning.png") if($status eq "failed");
-		
-	if (defined $image) {		
-		$box->pack_start (add_frame_to_image($image), FALSE, FALSE, 0);
-	}
-	return $box;
-	
+    my ($emulate,$sample)=@_;
+    my   $status= $emulate->object_get_attribute ($sample,"status");
+    $status='' if(!defined  $status);
+    my $image;
+    my $box = def_hbox(TRUE,1);
+    $image = new_image_from_file ("icons/load.gif") if($status eq "run");
+    $image = def_icon("icons/button_ok.png") if($status eq "done");
+    $image = def_icon("icons/warning.png") if($status eq "failed");
+    if (defined $image) {
+        $box->pack_start (add_frame_to_image($image), FALSE, FALSE, 0);
+    }
+    return $box;
 }
 
-
 ############
-#	run_emulator
+#    run_emulator
 ###########
-
 sub run_emulator {
-	my ($emulate,$info)=@_;
-	#my $graph_name="latency_ratio";
-	#return if(!check_samples($emulate,$info));
-	$emulate->object_add_attribute('status',undef,'run');
-	set_gui_status($emulate,"ref",1);
-	show_colored_info($info, "start emulation\n",'blue');
-
-#	#search for available usb blaster
-#	my $cmd = "jtagconfig";
-#	my ($stdout,$exit)=run_cmd_in_back_ground_get_stdout("$cmd");
-#	my @matches= ($stdout =~ /USB-Blaster.*/g);
-#	my $usb_blaster=$matches[0];
-# 	if (!defined $usb_blaster){
-#		add_info($info, "jtagconfig could not find any USB blaster cable: $stdout \n");
-#		$emulate->object_add_attribute('status',undef,'programmer_failed');
-#		set_gui_status($emulate,"ref",2);
-#		#/***/
-#		return;	
-#	}else{
-#		add_info($info, "find $usb_blaster\n");
-#	}
-	my @samples =$emulate->object_get_attribute_order("samples");
-	foreach my $sample (@samples){
-		my $status=$emulate->object_get_attribute ($sample,"status");	
-		next if($status ne "run");
-		next if(!check_sample($emulate,$sample,$info));
-		my $r= $emulate->object_get_attribute($sample,"ratios");
-		my @ratios=@{check_inserted_ratios($r)};
-		#$emulate->object_add_attribute ("sample$i","status","run");			
-		my $sof=get_sof_file_full_addr($emulate,$sample);	
-		add_info($info, "Programe FPGA device using $sof.sof\n");
-		my ($name,$path,$suffix) = fileparse("$sof",qr"\..[^.]*$");
-		my $programmer="$path/program_device.sh";
-		my $jtag_intfc="$path/jtag_intfc.sh";
-		if((-f $programmer)==0){
-			add_colored_info ($info, " Error: file  \"$programmer\"  dose not exist. \n",'red'); 
-			$emulate->object_add_attribute('status',undef,'programmer_failed');
-			$emulate->object_add_attribute ($sample,"status","failed");	
-			set_gui_status($emulate,"ref",2);
-			last;		
-		}
-		if((-f $jtag_intfc)==0){
-			add_colored_info ($info, " Error: file  \"$jtag_intfc\"  dose not exist. \n",'red'); 
-			$emulate->object_add_attribute('status',undef,'programmer_failed');
-			$emulate->object_add_attribute ($sample,"status","failed");	
-			set_gui_status($emulate,"ref",2);
-			last;		
-		}
-		my $cmd =  "bash $programmer $sof.sof";
-		
-		
-		#my $Quartus_bin=  $ENV{QUARTUS_BIN};
-			
-
-		#my $cmd = "$Quartus_bin/quartus_pgm -c \"$usb_blaster\" -m jtag -o \"p;$sof\"";
-	
-		#my $output = `$cmd 2>&1 1>/dev/null`;           # either with backticks
-
-		#/***/
-		my ($stdout,$exit)=run_cmd_in_back_ground_get_stdout("$cmd");	
-		if($exit){#programming FPGA board has failed
-			$emulate->object_add_attribute('status',undef,'programmer_failed');
-			add_colored_info($info, "$stdout\n",'red');
-			$emulate->object_add_attribute ($sample,"status","failed");	
-			set_gui_status($emulate,"ref",2);
-			next;			
-		}
-		#print "$stdout\n";
-		
-		# load noc configuration 
-		foreach  my $ratio_in (@ratios){						
-	    	
-		    	add_info($info, "Configure packet generators for  injection ratio of $ratio_in \% \n");
-		    	if(!programe_pck_gens($emulate,$sample,$ratio_in,$info,$jtag_intfc)){
-		    		add_colored_info($info, "Error in programe_pck_gens function\n",'red');		    		
-		    		next;
-		    	}
-		    	
-		    	
-		    	my $r=read_pack_gen($emulate,$sample,$info,$jtag_intfc,$ratio_in);
-			    next if (!defined $r);
-			    
-			   
-	
-		    	set_gui_status($emulate,"ref",2);
-	    		    	
-		}
-		$emulate->object_add_attribute ($sample,"status","done");	
-    	
-	}
-	
-	add_colored_info($info, "End emulation!\n",'blue');
-	$emulate->object_add_attribute('status',undef,'ideal');
-	set_gui_status($emulate,"ref",1);
+    my ($emulate,$info)=@_;
+    #my $graph_name="latency_ratio";
+    #return if(!check_samples($emulate,$info));
+    $emulate->object_add_attribute('status',undef,'run');
+    set_gui_status($emulate,"ref",1);
+    show_colored_info($info, "start emulation\n",'blue');
+#    #search for available usb blaster
+#    my $cmd = "jtagconfig";
+#    my ($stdout,$exit)=run_cmd_in_back_ground_get_stdout("$cmd");
+#    my @matches= ($stdout =~ /USB-Blaster.*/g);
+#    my $usb_blaster=$matches[0];
+#     if (!defined $usb_blaster){
+#        add_info($info, "jtagconfig could not find any USB blaster cable: $stdout \n");
+#        $emulate->object_add_attribute('status',undef,'programmer_failed');
+#        set_gui_status($emulate,"ref",2);
+#        #/***/
+#        return;
+#    }else{
+#        add_info($info, "find $usb_blaster\n");
+#    }
+    my @samples =$emulate->object_get_attribute_order("samples");
+    foreach my $sample (@samples){
+        my $status=$emulate->object_get_attribute ($sample,"status");
+        next if($status ne "run");
+        next if(!check_sample($emulate,$sample,$info));
+        my $r= $emulate->object_get_attribute($sample,"ratios");
+        my @ratios=@{check_inserted_ratios($r)};
+        #$emulate->object_add_attribute ("sample$i","status","run");
+        my $sof=get_sof_file_full_addr($emulate,$sample);
+        add_info($info, "Programe FPGA device using $sof.sof\n");
+        my ($name,$path,$suffix) = fileparse("$sof",qr"\..[^.]*$");
+        my $programmer="$path/program_device.sh";
+        my $jtag_intfc="$path/jtag_intfc.sh";
+        if((-f $programmer)==0){
+            add_colored_info ($info, " Error: file  \"$programmer\"  dose not exist. \n",'red');
+            $emulate->object_add_attribute('status',undef,'programmer_failed');
+            $emulate->object_add_attribute ($sample,"status","failed");
+            set_gui_status($emulate,"ref",2);
+            last;
+        }
+        if((-f $jtag_intfc)==0){
+            add_colored_info ($info, " Error: file  \"$jtag_intfc\"  dose not exist. \n",'red');
+            $emulate->object_add_attribute('status',undef,'programmer_failed');
+            $emulate->object_add_attribute ($sample,"status","failed");
+            set_gui_status($emulate,"ref",2);
+            last;
+        }
+        my $cmd =  "bash $programmer $sof.sof";
+        #my $Quartus_bin=  $ENV{QUARTUS_BIN};
+        #my $cmd = "$Quartus_bin/quartus_pgm -c \"$usb_blaster\" -m jtag -o \"p;$sof\"";
+        #my $output = `$cmd 2>&1 1>/dev/null`;         # either with backticks
+        #/***/
+        my ($stdout,$exit)=run_cmd_in_back_ground_get_stdout("$cmd");
+        if($exit){#programming FPGA board has failed
+            $emulate->object_add_attribute('status',undef,'programmer_failed');
+            add_colored_info($info, "$stdout\n",'red');
+            $emulate->object_add_attribute ($sample,"status","failed");
+            set_gui_status($emulate,"ref",2);
+            next;
+        }
+        #print "$stdout\n";
+        # load noc configuration
+        foreach  my $ratio_in (@ratios){
+                add_info($info, "Configure packet generators for  injection ratio of $ratio_in \% \n");
+                if(!programe_pck_gens($emulate,$sample,$ratio_in,$info,$jtag_intfc)){
+                    add_colored_info($info, "Error in programe_pck_gens function\n",'red');
+                    next;
+                }
+                my $r=read_pack_gen($emulate,$sample,$info,$jtag_intfc,$ratio_in);
+                next if (!defined $r);
+                set_gui_status($emulate,"ref",2);
+        }
+        $emulate->object_add_attribute ($sample,"status","done");
+    }
+    add_colored_info($info, "End emulation!\n",'blue');
+    $emulate->object_add_attribute('status',undef,'ideal');
+    set_gui_status($emulate,"ref",1);
 }
 
-
-
-
-
-
 ##############
-#	 process_notebook_gen
+#     process_notebook_gen
 ##############
-
-
 sub process_notebook_gen{
-		my ($emulate,$info,$mode,$set_win,@charts)=@_;
-		my $notebook = gen_notebook();
-		$notebook->set_tab_pos ('left');
-		$notebook->set_scrollable(TRUE);
-		#$notebook->can_focus(FALSE);
-
-		my $page1;
-		($page1,$set_win)=gen_emulation_column($emulate, $mode,10,$info,$set_win,@charts);
-		$notebook->append_page ($page1,gen_label_with_mnemonic ("  _Run emulator  ")) if($mode eq "emulate");
-		$notebook->append_page ($page1,gen_label_with_mnemonic ("  _Run simulator ")) if($mode eq "simulate");
-		
-		
-		my $page2=get_noc_setting_gui ($emulate,$info,$mode);
-		my $tt=($mode eq "emulate")? "  _Generate NoC \nEmulation Model" : "  _Generate NoC \nSimulation Model" ;
-		$notebook->append_page ($page2,gen_label_with_mnemonic ($tt));
-		
-		
-		
-		my $scrolled_win = add_widget_to_scrolled_win($notebook,gen_scr_win_with_adjst($emulate,"process_sc_win"));	
-		$scrolled_win->show_all;	
-		my $page_num=$emulate->object_get_attribute ("process_notebook","currentpage");		
-		$notebook->set_current_page ($page_num) if(defined $page_num);
-		$notebook->signal_connect( 'switch-page'=> sub{			
-			$emulate->object_add_attribute ("process_notebook","currentpage",$_[2]);	#save the new pagenumber
-					
-		});
-		
-		return ($scrolled_win,$set_win);
-	
+        my ($emulate,$info,$mode,$set_win,@charts)=@_;
+        my $notebook = gen_notebook();
+        $notebook->set_tab_pos ('left');
+        $notebook->set_scrollable(TRUE);
+        #$notebook->can_focus(FALSE);
+        my $page1;
+        ($page1,$set_win)=gen_emulation_column($emulate, $mode,10,$info,$set_win,@charts);
+        $notebook->append_page ($page1,gen_label_with_mnemonic ("  _Run emulator  ")) if($mode eq "emulate");
+        $notebook->append_page ($page1,gen_label_with_mnemonic ("  _Run simulator ")) if($mode eq "simulate");
+        my $page2=get_noc_setting_gui ($emulate,$info,$mode);
+        my $tt=($mode eq "emulate")? "  _Generate NoC \nEmulation Model" : "  _Generate NoC \nSimulation Model" ;
+        $notebook->append_page ($page2,gen_label_with_mnemonic ($tt));
+        my $scrolled_win = add_widget_to_scrolled_win($notebook,gen_scr_win_with_adjst($emulate,"process_sc_win"));
+        $scrolled_win->show_all;
+        my $page_num=$emulate->object_get_attribute ("process_notebook","currentpage");
+        $notebook->set_current_page ($page_num) if(defined $page_num);
+        $notebook->signal_connect( 'switch-page'=> sub{
+            $emulate->object_add_attribute ("process_notebook","currentpage",$_[2]);    #save the new pagenumber
+        });
+        return ($scrolled_win,$set_win);
 }
 
-
 sub get_noc_setting_gui {
-	my ($emulate,$info_text,$mode)=@_;
-	my $table=def_table(20,10,FALSE);#	my ($row,$col,$homogeneous)=@_;
-	
-	
-	my $scrolled_win = gen_scr_win_with_adjst ($emulate,"noc_setting_gui");
-	add_widget_to_scrolled_win($table,$scrolled_win);
-	my $row=noc_config ($emulate,$table,$info_text);
-	    
-	my($label,$param,$default,$content,$type,$info);
-	my @dirs = grep {-d} glob("../boards/Altera/*");
-	my $fpgas;
-	foreach my $dir (@dirs) {
-		my ($name,$path,$suffix) = fileparse("$dir",qr"\..[^.]*$");
-		$default=$name;
-		$fpgas= (defined $fpgas)? "$fpgas,$name" : "$name";		
-	}
-	
-	my @fpgainfo;
-	if($mode eq "emulate"){	
-		@fpgainfo = (
-		{ label=>'Pck. injector FIFO Width:', param_name=>'TIMSTMP_FIFO_NUM', type=>'Spin-button', default_val=>16, content=>"2,128,2", info=>"Packet injectors' timestamp FIFO width. In case a packet cannot be injected according to the desired injection ratio, the current system time is saved in a FIFO and then at injection time it will be read and attached to the packet. The larger FIFO width results in more accurate latency calculation at the cost of higher area overhead." , param_parent=>'fpga_param', ref_delay=> undef},
-	  	{ label=>'Save as:', param_name=>'SAVE_NAME', type=>"Entry", default_val=>'emulate1', content=>undef, info=>undef, param_parent=>'fpga_param', ref_delay=>undef},
-		{ label=>"Project directory", param_name=>"SOF_DIR", type=>"DIR_path", default_val=>"$ENV{'PRONOC_WORK'}/emulate", content=>undef, info=>"Define the working directory for generating .sof file", param_parent=>'fpga_param',ref_delay=>undef },
-		);	
-
-	}
-	else {
-		@fpgainfo = (
-		{ label=>'Pck. injector FIFO Width:', param_name=>'TIMSTMP_FIFO_NUM', type=>'Spin-button', default_val=>16, content=>"2,128,2", info=>"Packet injectors' timestamp FIFO width. In case a packet cannot be injected according to the desired injection ratio, the current system time is saved in a FIFO and then at injection time it will be read and attached to the packet. The larger FIFO width results in more accurate latency calculation." , param_parent=>'fpga_param', ref_delay=> undef},
-  		{ label=>'Save as:', param_name=>'SAVE_NAME', type=>"Entry", default_val=>'simulate1', content=>undef, info=>undef, param_parent=>'sim_param', ref_delay=>undef},
-		{ label=>"Project directory", param_name=>"BIN_DIR", type=>"DIR_path", default_val=>"$ENV{'PRONOC_WORK'}/simulate", content=>undef, info=>"Define the working directory for generating simulation executable binarry file", param_parent=>'sim_param',ref_delay=>undef },
-		
-		);	
-	}
-	
-	my $coltmp=0;
-	foreach my $d (@fpgainfo) {		
-		($row,$coltmp)=add_param_widget  ($emulate, $d->{label}, $d->{param_name}, $d->{default_val}, $d->{type}, $d->{content}, $d->{info}, $table,$row,undef,1, $d->{param_parent}, $d->{ref_delay});
-	}   
-	  
-	my $maintable=def_table(20,10,FALSE);#	my ($row,$col,$homogeneous)=@_;
-	   
-	my $generate = def_image_button('icons/gen.png','Gener_ate',FALSE,1);
-	my $diagram  = def_image_button('icons/diagram.png','Diagram');
-	my $import   = def_image_button('icons/import.png','I_mport',FALSE,1);
-	set_tip($import ,"Import NoC configuration from file");
-	
-	$maintable->attach_defaults ($scrolled_win, 0,10, 0, 9);
-	$maintable->attach_defaults (gen_Hsep(), 0,10, 8, 9);
-	$maintable->attach ($generate, 0,2, 9, 10,'expand','shrink',2,2);
-	$maintable->attach ($diagram, 2,4, 9, 10,'expand','shrink',2,2);
-	$maintable->attach ($import, 4,6, 9, 10,'expand','shrink',2,2);
-	
-	
-    $diagram-> signal_connect("clicked" => sub{ 
+    my ($emulate,$info_text,$mode)=@_;
+    my $table=def_table(20,10,FALSE);#    my ($row,$col,$homogeneous)=@_;
+    my $scrolled_win = gen_scr_win_with_adjst ($emulate,"noc_setting_gui");
+    add_widget_to_scrolled_win($table,$scrolled_win);
+    my $row=noc_config ($emulate,$table,$info_text);
+    my($label,$param,$default,$content,$type,$info);
+    my @dirs = grep {-d} glob("../boards/Altera/*");
+    my $fpgas;
+    foreach my $dir (@dirs) {
+        my ($name,$path,$suffix) = fileparse("$dir",qr"\..[^.]*$");
+        $default=$name;
+        $fpgas= (defined $fpgas)? "$fpgas,$name" : "$name";
+    }
+    my @fpgainfo;
+    if($mode eq "emulate"){
+        @fpgainfo = (
+        { label=>'Pck. injector FIFO Width:', param_name=>'TIMSTMP_FIFO_NUM', type=>'Spin-button', default_val=>16, content=>"2,128,2", info=>"Packet injectors' timestamp FIFO width. In case a packet cannot be injected according to the desired injection ratio, the current system time is saved in a FIFO and then at injection time it will be read and attached to the packet. The larger FIFO width results in more accurate latency calculation at the cost of higher area overhead." , param_parent=>'fpga_param', ref_delay=> undef},
+        { label=>'Save as:', param_name=>'SAVE_NAME', type=>"Entry", default_val=>'emulate1', content=>undef, info=>undef, param_parent=>'fpga_param', ref_delay=>undef},
+        { label=>"Project directory", param_name=>"SOF_DIR", type=>"DIR_path", default_val=>"$ENV{'PRONOC_WORK'}/emulate", content=>undef, info=>"Define the working directory for generating .sof file", param_parent=>'fpga_param',ref_delay=>undef },
+        );
+    }
+    else {
+        @fpgainfo = (
+        { label=>'Pck. injector FIFO Width:', param_name=>'TIMSTMP_FIFO_NUM', type=>'Spin-button', default_val=>16, content=>"2,128,2", info=>"Packet injectors' timestamp FIFO width. In case a packet cannot be injected according to the desired injection ratio, the current system time is saved in a FIFO and then at injection time it will be read and attached to the packet. The larger FIFO width results in more accurate latency calculation." , param_parent=>'fpga_param', ref_delay=> undef},
+        { label=>'Save as:', param_name=>'SAVE_NAME', type=>"Entry", default_val=>'simulate1', content=>undef, info=>undef, param_parent=>'sim_param', ref_delay=>undef},
+        { label=>"Project directory", param_name=>"BIN_DIR", type=>"DIR_path", default_val=>"$ENV{'PRONOC_WORK'}/simulate", content=>undef, info=>"Define the working directory for generating simulation executable binarry file", param_parent=>'sim_param',ref_delay=>undef },
+        );
+    }
+    my $coltmp=0;
+    foreach my $d (@fpgainfo) {
+        ($row,$coltmp)=add_param_widget  ($emulate, $d->{label}, $d->{param_name}, $d->{default_val}, $d->{type}, $d->{content}, $d->{info}, $table,$row,undef,1, $d->{param_parent}, $d->{ref_delay});
+    }
+    my $maintable=def_table(20,10,FALSE);#    my ($row,$col,$homogeneous)=@_;
+    my $generate = def_image_button('icons/gen.png','Gener_ate',FALSE,1);
+    my $diagram  = def_image_button('icons/diagram.png','Diagram');
+    my $import   = def_image_button('icons/import.png','I_mport',FALSE,1);
+    set_tip($import ,"Import NoC configuration from file");
+    $maintable->attach_defaults ($scrolled_win, 0,10, 0, 9);
+    $maintable->attach_defaults (gen_Hsep(), 0,10, 8, 9);
+    $maintable->attach ($generate, 0,2, 9, 10,'expand','shrink',2,2);
+    $maintable->attach ($diagram, 2,4, 9, 10,'expand','shrink',2,2);
+    $maintable->attach ($import, 4,6, 9, 10,'expand','shrink',2,2);
+    $diagram-> signal_connect("clicked" => sub{
         show_topology_diagram ($emulate);
-    });			
+    });
     $generate->signal_connect ('clicked'=> sub{
-		generate_sof_file($emulate,$info_text) if($mode eq "emulate");
-		generate_sim_bin_file($emulate,$info_text) if($mode eq "simulate");
-		
-	});
-	
-	$import-> signal_connect("clicked" => sub{ 
-		import_noc_info_file($emulate,$mode);
-	});
-	
-	$scrolled_win->show_all;	    
-	return $maintable;	
+        generate_sof_file($emulate,$info_text) if($mode eq "emulate");
+        generate_sim_bin_file($emulate,$info_text) if($mode eq "simulate");
+    });
+    $import-> signal_connect("clicked" => sub{
+        import_noc_info_file($emulate,$mode);
+    });
+    $scrolled_win->show_all;
+    return $maintable;
 }
 
 sub import_noc_info_file{
-	my ($self,$mode)=@_;
-	my $file;
-	my $dialog = gen_file_dialog(undef,'inf');
-	
-	my $open_in	  = ($mode ne "emulate" ) ? abs_path("$ENV{'PRONOC_WORK'}/simulate") : abs_path("$ENV{'PRONOC_WORK'}/emulate");
-	$dialog->set_current_folder ($open_in); 
-	if ( "ok" eq $dialog->run ) {
-		my $status=1;
-		$file = $dialog->get_filename;
-		my $pp= do $file ;
-		my $p=$pp->{'noc_param'};
-		$status=0 if $@;
-		message_dialog("Error reading: $@") if $@;
-		if ($status==1){
-			$self->object_add_attribute ("noc_param",undef,$p);
-			my ($name,$path,$suffix) = fileparse("$file",qr"\..[^.]*$");
-			my $attr1 = ($mode ne "emulate" ) ? 'sim_param' : 'fpga_param';
-			$self->object_add_attribute ($attr1,'SAVE_NAME',$name);
-						
-			set_gui_status($self,"ref",1);
-		}			
-	}
-	$dialog->destroy;	
+    my ($self,$mode)=@_;
+    my $file;
+    my $dialog = gen_file_dialog(undef,'inf');
+    my $open_in      = ($mode ne "emulate" ) ? abs_path("$ENV{'PRONOC_WORK'}/simulate") : abs_path("$ENV{'PRONOC_WORK'}/emulate");
+    $dialog->set_current_folder ($open_in);
+    if ( "ok" eq $dialog->run ) {
+        my $status=1;
+        $file = $dialog->get_filename;
+        my $pp= do $file ;
+        my $p=$pp->{'noc_param'};
+        $status=0 if $@;
+        message_dialog("Error reading: $@") if $@;
+        if ($status==1){
+            $self->object_add_attribute ("noc_param",undef,$p);
+            my ($name,$path,$suffix) = fileparse("$file",qr"\..[^.]*$");
+            my $attr1 = ($mode ne "emulate" ) ? 'sim_param' : 'fpga_param';
+            $self->object_add_attribute ($attr1,'SAVE_NAME',$name);
+            set_gui_status($self,"ref",1);
+        }
+    }
+    $dialog->destroy;
 }
 
 ##########
-#	generate_sof_file
+#    generate_sof_file
 ##########
-
-
 sub generate_sof_file {
-	my ($self,$info)=@_;
-	my $name=$self->object_get_attribute ('fpga_param',"SAVE_NAME"); 
-	my $target_dir  = "$ENV{'PRONOC_WORK'}/emulate/$name";
-	my $top 	= "$target_dir/src_verilog/${name}_top.v";
-	
-	if (!defined $name){
-		message_dialog("Please define the Save as filed!");
-		return;
-	}
-
-	#copy all noc source codes
-	my @files = (
-'/mpsoc/rtl/src_emulate/rtl/', 
-'/mpsoc/rtl/src_peripheral/jtag/jtag_wb/', 
+    my ($self,$info)=@_;
+    my $name=$self->object_get_attribute ('fpga_param',"SAVE_NAME");
+    my $target_dir  = "$ENV{'PRONOC_WORK'}/emulate/$name";
+    my $top     = "$target_dir/src_verilog/${name}_top.v";
+    if (!defined $name){
+        message_dialog("Please define the Save as filed!");
+        return;
+    }
+    #copy all noc source codes
+    my @files = (
+'/mpsoc/rtl/src_emulate/rtl/',
+'/mpsoc/rtl/src_peripheral/jtag/jtag_wb/',
 '/mpsoc/rtl/src_peripheral/ram/',
 '/mpsoc/rtl/main_comp.v',
 '/mpsoc/rtl/arbiter.v',
 '/mpsoc/rtl/pronoc_def.v',
 '/mpsoc/rtl/src_topology/',
 '/mpsoc/rtl/src_noc/');
-
-	my $dir = Cwd::getcwd();
-	my $project_dir	  = abs_path("$dir/../../");
-	my ($stdout,$exit)=run_cmd_in_back_ground_get_stdout("mkdir -p $target_dir/src_verilog" );
-	copy_file_and_folders(\@files,$project_dir,"$target_dir/src_verilog/lib/");
-	
-
-	#generate parameters for emulator_top.v file
-	gen_noc_localparam_v_file($self,"$target_dir/src_verilog/lib/src_noc/");
-	
-	open(FILE,  ">$top") || die "Can not open: $!";
-	print FILE create_emulate_top($self,$name,$top);
-	close(FILE) || die "Error closing file: $!";
-	select_compiler($self,$name,$top,$target_dir,\&save_the_sof_file);
-	
+    my $dir = Cwd::getcwd();
+    my $project_dir      = abs_path("$dir/../../");
+    my ($stdout,$exit)=run_cmd_in_back_ground_get_stdout("mkdir -p $target_dir/src_verilog" );
+    copy_file_and_folders(\@files,$project_dir,"$target_dir/src_verilog/lib/");
+    #generate parameters for emulator_top.v file
+    gen_noc_localparam_v_file($self,"$target_dir/src_verilog/lib/src_noc/");
+    open(FILE,  ">$top") || die "Can not open: $!";
+    print FILE create_emulate_top($self,$name,$top);
+    close(FILE) || die "Error closing file: $!";
+    select_compiler($self,$name,$top,$target_dir,\&save_the_sof_file);
 return;
 }
 
 sub create_emulate_top{
-	my ($self,$name,$top)=@_;
-	my $top_v= get_license_header("$top");
-
-$top_v	="$top_v
-
-`timescale	 1ns/1ps
-
+    my ($self,$name,$top)=@_;
+    my $top_v= get_license_header("$top");
+$top_v    ="$top_v
+`timescale     1ns/1ps
 module ${name}_top(
-	output done_led,
-	output noc_reset_led,
-	output jtag_reset_led,
-	input  reset,
-	input  clk
-); 
-
-
-	localparam
-		STATISTIC_VJTAG_INDEX=124,  
-		PATTERN_VJTAG_INDEX=125,
-   		COUNTER_VJTAG_INDEX=126,
-		DONE_RESET_VJTAG_INDEX=127;
-				
-
-	
- 	
-	wire  reset_noc, reset_injector, reset_noc_sync, reset_injector_sync, done;
-	wire jtag_reset_injector, jtag_reset_noc;
-	wire start_o;
-	wire done_time_limit;
-		
-	assign done_led	= done | done_time_limit; 
-	assign noc_reset_led= reset_noc;
-	assign jtag_reset_led	= reset_injector;
-
-	
-
-	//  two reset sources which can be controled using jtag. One for reseting NoC another packet injectors
-	jtag_source_probe #(
-		.VJTAG_INDEX(DONE_RESET_VJTAG_INDEX),
-	 	.Dw(2)	//source/probe width in bits
- 	)the_reset(
-		.probe({done_time_limit,done}),
-		.source({jtag_reset_injector,jtag_reset_noc})
-	);
-
-
-	assign  reset_noc		=	(jtag_reset_noc | reset);
-	assign  reset_injector		=	(jtag_reset_injector | reset);	
-
-	altera_reset_synchronizer noc_rst_sync
-	(
-		.reset_in(reset_noc), 
-		.clk(clk),
-		.reset_out(reset_noc_sync)
-	);
-
-
-	altera_reset_synchronizer inject_rst_sync
-	(
-		.reset_in(reset_injector), 
-		.clk(clk),
-		.reset_out(reset_injector_sync)
-	);
-	
-	//noc emulator
-	
-	noc_emulator #(
-		.STATISTIC_VJTAG_INDEX(STATISTIC_VJTAG_INDEX),  
-		.PATTERN_VJTAG_INDEX(PATTERN_VJTAG_INDEX),
-		.NOC_ID(0)		 
-	)
-	noc_emulate_top
-	(
-		.reset(reset_noc_sync),
-		.jtag_ctrl_reset(reset_injector_sync),
-		.clk(clk),
-		.start_o(start_o),
-		.done(done)
-	);
-	
-	
-	
-	//clock counter
-	
-	function integer log2;
-      input integer number; begin   
-         log2=(number <=1) ? 1: 0;    
-         while(2**log2<number) begin    
-            log2=log2+1;    
-         end 	   
-      end   
-    endfunction // log2 
-	
-	localparam   MAX_SIM_CLKs  = 1_000_000_000;
-	localparam   CLK_CNTw = log2(MAX_SIM_CLKs+1);
-	
-	reg     [CLK_CNTw-1             :   0] clk_counter;
-	wire    [CLK_CNTw-1             :   0] clk_limit;
-	reg start;
-	always @(posedge clk or posedge reset_injector_sync) begin 
-		if(reset_injector_sync)begin 
-			clk_counter <= {CLK_CNTw{1'b0}};
-			start<=1'b0;		
-		end else begin 
-			if(start_o) start<=1'b1;
-			if(done==1'b0 && start ) clk_counter<=clk_counter +1'b1;
-		end	
-	end
-	
-	jtag_source_probe #(
-		.VJTAG_INDEX(COUNTER_VJTAG_INDEX),
-	 	.Dw(CLK_CNTw)	//source/probe width in bits
- 	)the_clk_counter(
-		.probe(clk_counter),
-		.source(clk_limit)
-	);
-	
-	assign done_time_limit = (clk_counter >= clk_limit);
+    output done_led,
+    output noc_reset_led,
+    output jtag_reset_led,
+    input  reset,
+    input  clk
+);
+    localparam
+        STATISTIC_VJTAG_INDEX=124,
+        PATTERN_VJTAG_INDEX=125,
+        COUNTER_VJTAG_INDEX=126,
+        DONE_RESET_VJTAG_INDEX=127;
+    wire  reset_noc, reset_injector, reset_noc_sync, reset_injector_sync, done;
+    wire jtag_reset_injector, jtag_reset_noc;
+    wire start_o;
+    wire done_time_limit;
+    assign done_led    = done | done_time_limit;
+    assign noc_reset_led= reset_noc;
+    assign jtag_reset_led    = reset_injector;
+    //  two reset sources which can be controled using jtag. One for reseting NoC another packet injectors
+    jtag_source_probe #(
+        .VJTAG_INDEX(DONE_RESET_VJTAG_INDEX),
+         .Dw(2)    //source/probe width in bits
+    )the_reset(
+        .probe({done_time_limit,done}),
+        .source({jtag_reset_injector,jtag_reset_noc})
+    );
+    assign  reset_noc        =    (jtag_reset_noc | reset);
+    assign  reset_injector        =    (jtag_reset_injector | reset);
+    altera_reset_synchronizer noc_rst_sync
+    (
+        .reset_in(reset_noc),
+        .clk(clk),
+        .reset_out(reset_noc_sync)
+    );
+    altera_reset_synchronizer inject_rst_sync
+    (
+        .reset_in(reset_injector),
+        .clk(clk),
+        .reset_out(reset_injector_sync)
+    );
+    //noc emulator
+    noc_emulator #(
+        .STATISTIC_VJTAG_INDEX(STATISTIC_VJTAG_INDEX),
+        .PATTERN_VJTAG_INDEX(PATTERN_VJTAG_INDEX)
+    )
+    noc_emulate_top
+    (
+        .reset(reset_noc_sync),
+        .jtag_ctrl_reset(reset_injector_sync),
+        .clk(clk),
+        .start_o(start_o),
+        .done(done)
+    );
+    //clock counter
+    function integer log2;
+    input integer number; begin
+        log2=(number <=1) ? 1: 0;
+        while(2**log2<number) begin
+        log2=log2+1;
+        end
+    end
+    endfunction // log2
+    localparam   MAX_SIM_CLKs  = 1_000_000_000;
+    localparam   CLK_CNTw = log2(MAX_SIM_CLKs+1);
+    reg    [CLK_CNTw-1           :   0] clk_counter;
+    wire    [CLK_CNTw-1           :   0] clk_limit;
+    reg start;
+    always @(posedge clk or posedge reset_injector_sync) begin
+        if(reset_injector_sync)begin
+            clk_counter <= {CLK_CNTw{1'b0}};
+            start<=1'b0;
+        end else begin
+            if(start_o) start<=1'b1;
+            if(done==1'b0 && start ) clk_counter<=clk_counter +1'b1;
+        end
+    end
+    jtag_source_probe #(
+        .VJTAG_INDEX(COUNTER_VJTAG_INDEX),
+         .Dw(CLK_CNTw)    //source/probe width in bits
+    )the_clk_counter(
+        .probe(clk_counter),
+        .source(clk_limit)
+    );
+    assign done_time_limit = (clk_counter >= clk_limit);
 endmodule
 ";
-	return $top_v;
+    return $top_v;
 }
 
 sub save_the_sof_file{
-
-	my $self=shift;
-	my $name=$self->object_get_attribute ('fpga_param',"SAVE_NAME"); 
-	my $sofdir="$ENV{PRONOC_WORK}/emulate/sof";
-	my $fpga_board=$self->object_get_attribute('compile','board');
-	my $target_dir  = "$ENV{'PRONOC_WORK'}/emulate/$name";
-
-	mkpath("$sofdir/$fpga_board/",1,01777);
-	open(FILE,  ">$sofdir/$fpga_board/$name.inf") || die "Can not open: $!";
-	print FILE perl_file_header("$name.inf");
-	my %pp;
-	$pp{'noc_param'}= $self->{'noc_param'};
-	$pp{'fpga_param'}= $self->{'fpga_param'};
-	print FILE Data::Dumper->Dump([\%pp],["emulate_info"]);
-	close(FILE) || die "Error closing file: $!";	
-
-
-	#find  $dir_name -name \*.sof -exec cp '{}' $sofdir/$fpga_board/$save_name.sof" 
-	my @files = File::Find::Rule->file()
-                 ->name( '*.sof' )
-                 ->in( "$target_dir" );
-	copy($files[0],"$sofdir/$fpga_board/$name.sof") or do { 
-		my $err= "Error copy($files[0] , $sofdir/$fpga_board/$name.sof";	
-		print "$err\n"; 	
-		message_dialog($err,'error'); 
-		return;
-	};
-	#copy the board's programming and jtag interface files
-	
-	my $board_name=$self->object_get_attribute('compile','board');
-	#copy board jtag_intfc.sh file 
-	copy("../boards/Altera/$board_name/jtag_intfc.sh","$sofdir/$fpga_board/jtag_intfc.sh");
-	#print "../boards/$board_name/jtag_intfc.sh","$sofdir/$fpga_board/jtag_intfc.sh\n";
-	#add argument run to jtag_interface file 
-	my $runarg='
-
+    my $self=shift;
+    my $name=$self->object_get_attribute ('fpga_param',"SAVE_NAME");
+    my $sofdir="$ENV{PRONOC_WORK}/emulate/sof";
+    my $fpga_board=$self->object_get_attribute('compile','board');
+    my $target_dir  = "$ENV{'PRONOC_WORK'}/emulate/$name";
+    mkpath("$sofdir/$fpga_board/",1,01777);
+    open(FILE,  ">$sofdir/$fpga_board/$name.inf") || die "Can not open: $!";
+    print FILE perl_file_header("$name.inf");
+    my %pp;
+    $pp{'noc_param'}= $self->{'noc_param'};
+    $pp{'fpga_param'}= $self->{'fpga_param'};
+    print FILE Data::Dumper->Dump([\%pp],["emulate_info"]);
+    close(FILE) || die "Error closing file: $!";
+    #find  $dir_name -name \*.sof -exec cp '{}' $sofdir/$fpga_board/$save_name.sof"
+    my @files = File::Find::Rule->file()
+        ->name( '*.sof' )
+        ->in( "$target_dir" );
+    copy($files[0],"$sofdir/$fpga_board/$name.sof") or do {
+        my $err= "Error copy($files[0] , $sofdir/$fpga_board/$name.sof";
+        print "$err\n";
+        message_dialog($err,'error');
+        return;
+    };
+    #copy the board's programming and jtag interface files
+    my $board_name=$self->object_get_attribute('compile','board');
+    #copy board jtag_intfc.sh file
+    copy("../boards/Altera/$board_name/jtag_intfc.sh","$sofdir/$fpga_board/jtag_intfc.sh");
+    #print "../boards/$board_name/jtag_intfc.sh","$sofdir/$fpga_board/jtag_intfc.sh\n";
+    #add argument run to jtag_interface file
+    my $runarg='
 if [ $# -ne 0 ]
-  then
+    then
     $JTAG_INTFC $1
 fi
 ';
-	append_text_to_file ("$sofdir/$fpga_board/jtag_intfc.sh",$runarg );
-	
-	
-	
-
-	#copy board program_device.sh file 
-	copy("../boards/Altera/$board_name/program_device.sh","$sofdir/$fpga_board/program_device.sh");
-	
-	
-
-	message_dialog("sof file has been generated successfully");	
+    append_text_to_file ("$sofdir/$fpga_board/jtag_intfc.sh",$runarg );
+    #copy board program_device.sh file
+    copy("../boards/Altera/$board_name/program_device.sh","$sofdir/$fpga_board/program_device.sh");
+    message_dialog("sof file has been generated successfully");
 }
 
-
-
 ##########
-#	save_emulation
+#    save_emulation
 ##########
 sub save_emulation {
-	my ($emulate)=@_;
-	# read emulation name
-	my $name=$emulate->object_get_attribute ("emulate_name",undef);	
-	my $s= (!defined $name)? 0 : (length($name)==0)? 0 :1;	
-	if ($s == 0){
-		message_dialog("Please set emulation name!");
-		return 0;
-	}
-	# Write object file
-	open(FILE,  ">lib/emulate/$name.EML") || die "Can not open: $!";
-	print FILE perl_file_header("$name.EML");
-	print FILE Data::Dumper->Dump([\%$emulate],["emulate"]);
-	close(FILE) || die "Error closing file: $!";
-	message_dialog("Emulation saved as lib/emulate/$name.EML!");
-	return 1;
+    my ($emulate)=@_;
+    # read emulation name
+    my $name=$emulate->object_get_attribute ("emulate_name",undef);
+    my $s= (!defined $name)? 0 : (length($name)==0)? 0 :1;
+    if ($s == 0){
+        message_dialog("Please set emulation name!");
+        return 0;
+    }
+    # Write object file
+    open(FILE,  ">lib/emulate/$name.EML") || die "Can not open: $!";
+    print FILE perl_file_header("$name.EML");
+    print FILE Data::Dumper->Dump([\%$emulate],["emulate"]);
+    close(FILE) || die "Error closing file: $!";
+    message_dialog("Emulation saved as lib/emulate/$name.EML!");
+    return 1;
 }
 
 #############
-#	load_emulation
+#    load_emulation
 ############
-
 sub load_emulation {
-	my ($emulate,$info)=@_;
-	my $file;
-	my $dialog =  gen_file_dialog (undef, 'EML');	
-	my $dir = Cwd::getcwd();
-	$dialog->set_current_folder ("$dir/lib/emulate");			
-
-	if ( "ok" eq $dialog->run ) {
-		$file = $dialog->get_filename;
-		my ($name,$path,$suffix) = fileparse("$file",qr"\..[^.]*$");
-		if($suffix eq '.EML'){
-			
-			my ($pp,$r,$err) = regen_object($file);
-			if ($r ){		
-				add_colored_info($info,"**Error reading  $file file: $err\n",'red');
-				 $dialog->destroy;
-				return;
-			} 
-
-			clone_obj($emulate,$pp);
-			#message_dialog("done!");				
-		}					
-     }
-     $dialog->destroy;
+    my ($emulate,$info)=@_;
+    my $file;
+    my $dialog =  gen_file_dialog (undef, 'EML');
+    my $dir = Cwd::getcwd();
+    $dialog->set_current_folder ("$dir/lib/emulate");
+    if ( "ok" eq $dialog->run ) {
+        $file = $dialog->get_filename;
+        my ($name,$path,$suffix) = fileparse("$file",qr"\..[^.]*$");
+        if($suffix eq '.EML'){
+            my ($pp,$r,$err) = regen_object($file);
+            if ($r ){
+                add_colored_info($info,"**Error reading  $file file: $err\n",'red');
+                $dialog->destroy;
+                return;
+            }
+            clone_obj($emulate,$pp);
+            #message_dialog("done!");
+        }
+    }
+    $dialog->destroy;
 }
 
-
-
 sub update_result {
-	my ($self,$sample,$name,$x,$y,$z)=@_;
-	my $ref=$self->object_get_attribute ($sample,$name);
-	my %results;
-	%results= %{$ref} if(defined $ref);
-	if(!defined $z) {$results{$x}=$y;}
-	else {$results{$x}{$y}=$z;}	
-	$self->object_add_attribute ($sample,$name,\%results);
-}	
-
-
-
+    my ($self,$sample,$name,$x,$y,$z)=@_;
+    my $ref=$self->object_get_attribute ($sample,$name);
+    my %results;
+    %results= %{$ref} if(defined $ref);
+    if(!defined $z) {$results{$x}=$y;}
+    else {$results{$x}{$y}=$z;}
+    $self->object_add_attribute ($sample,$name,\%results);
+}
 
 sub gen_sim_parameter_h {
-	my ($param_h,$includ_h,$ne,$nr,$router_p,$fifow)=@_;
-	
-	$param_h =~ s/\d\'b/ /g;
-	my $text=  "
-#ifndef     INCLUDE_PARAM
-	#define   INCLUDE_PARAM \n \n 
-
-	$param_h 
-	 	
- 	#define NE  $ne
- 	#define NR  $nr
- 	#define ROUTER_P_NUM $router_p
- 	
-	extern Vtraffic		*traffic[NE];
-	extern Vpck_inj     *pck_inj[NE];
-	extern int reset,clk;
-	
-	//simulation parameter	
-	#define MAX_RATIO   ".MAX_RATIO."
-	#define AVG_LATENCY_METRIC \"HEAD_2_TAIL\"
-	#define TIMSTMP_FIFO_NUM   $fifow
-	
-	$includ_h
-\n \n \#endif" ; 
-	return $text;	
-}	
+    my ($param_h,$includ_h,$ne,$nr,$router_p,$fifow)=@_;
+    $param_h =~ s/\d\'b/ /g;
+    my $text=  "
+#ifndef    INCLUDE_PARAM
+    #define   INCLUDE_PARAM \n \n
+    $param_h
+    #define NE  $ne
+    #define NR  $nr
+    #define ROUTER_P_NUM $router_p
+    extern Vtraffic        *traffic[NE];
+    extern Vpck_inj    *pck_inj[NE];
+    extern int reset,clk;
+    //simulation parameter
+    #define MAX_RATIO   ".MAX_RATIO."
+    #define AVG_LATENCY_METRIC \"HEAD_2_TAIL\"
+    #define TIMSTMP_FIFO_NUM   $fifow
+    $includ_h
+\n \n \#endif" ;
+    return $text;
+}
 
 sub gen_noc_sim_param {
-	my $simulate=shift;
-	my $fifow=$simulate->object_get_attribute('fpga_param','TIMSTMP_FIFO_NUM');
-	
-	$fifow= '16' if (!defined $fifow);
-	
-	return "
-	//simulation parameter	
-	//localparam MAX_RATIO = ".MAX_RATIO.";
-	localparam MAX_PCK_NUM = ".MAX_SIM_CLKs.";
-	localparam MAX_PCK_SIZ = ".MAX_PCK_SIZ."; 
-	localparam MAX_SIM_CLKs=  ".MAX_SIM_CLKs.";
-	localparam TIMSTMP_FIFO_NUM = $fifow;	
-	";
-	
+    my $simulate=shift;
+    my $fifow=$simulate->object_get_attribute('fpga_param','TIMSTMP_FIFO_NUM');
+    $fifow= '16' if (!defined $fifow);
+    return "
+    //simulation parameter
+    //localparam MAX_RATIO = ".MAX_RATIO.";
+    localparam MAX_PCK_NUM = ".MAX_SIM_CLKs.";
+    localparam MAX_PCK_SIZ = ".MAX_PCK_SIZ.";
+    localparam MAX_SIM_CLKs=  ".MAX_SIM_CLKs.";
+    localparam TIMSTMP_FIFO_NUM = $fifow;
+    ";
 }
 
-
 sub gen_noc_localparam_v_file {
-	my ($self,$dst_path,$sample,$noc_id)=@_;
-	$noc_id="" if(!defined $noc_id);	
-	# generate NoC parameter file
-	my ($noc_param,$pass_param)=gen_noc_param_v($self,$sample,$noc_id);
-	my $header=autogen_warning().get_license_header("noc_localparam.v");
-	open(FILE,  ">${dst_path}/noc_localparam.v") || die "Can not open: $!";
-	my $sim =gen_noc_sim_param($self);
-	print FILE  "$header
-	
-	\`ifdef   NOC_LOCAL_PARAM \n \n 
-	$noc_param  
-	
-	$sim
-		
-\n \n \`endif"; 
-	close FILE;	
+    my ($self,$dst_path,$sample,$noc_id)=@_;
+    $noc_id="" if(!defined $noc_id);
+    # generate NoC parameter file
+    my ($noc_param,$pass_param)=gen_noc_param_v($self,$sample,$noc_id);
+    my $header=autogen_warning().get_license_header("noc_localparam.v");
+    open(FILE,  ">${dst_path}/noc_localparam.v") || die "Can not open: $!";
+    my $sim =gen_noc_sim_param($self);
+    print FILE  "$header
+    \`ifdef   NOC_LOCAL_PARAM \n \n
+    $noc_param
+    $sim
+\n \n \`endif";
+    close FILE;
 }
 
+sub noc_emulate_ctrl{
+    my ($self,$info)=@_;
+    my $generate = def_image_button('icons/forward.png','Run all',FALSE,1);
+    my ($entrybox,$entry ) =gen_save_load_widget (
+        $self, #the object
+        "Name",#the label shown for setting configuration
+        "emulate_name",#the key name for saveing the setting configuration in object
+        "Experiment name",#the label full name show in tool tips
+        undef,#Where the generted RTL files are loacted. Undef if not aplicaple
+        0,#check the given name match the SoC or mpsoc name rules
+        "lib/emulate/",#where the current configuration seting file is saved
+        "EML",#the extenstion given for configuration seting file
+        \&load_emulation,
+        $info);
+    $generate-> signal_connect("clicked" => sub{
+        my @samples =$self->object_get_attribute_order("samples");
+        foreach my $sample (@samples){
+            $self->object_add_attribute ($sample,"status","run");
+        }
+        run_emulator($self,$info);
+    });
+    my $table = def_table (1, 12, FALSE);
+    $table->attach ($entrybox, 0, 5, 0,1,'expand','shrink',2,2);
+    $table->attach ($generate, 5, 8, 0,1,'expand','shrink',2,2);
+    return add_widget_to_scrolled_win($table,gen_scr_win_with_adjst($self,"ctrl_emul_win"));
+}
 
 ############
 #    main
 ############
 sub emulator_main{
-		
-	add_color_to_gd();
-	my $emulate= emulator->emulator_new();
-	set_gui_status($emulate,"ideal",0);
-	$emulate->object_add_attribute('compile','compilers',"QuartusII");
-	my $left_table = def_table (25, 6, FALSE);
-	my $right_table =def_table (25, 6, FALSE);
-	my $main_table = def_table (25, 12, FALSE);
-	my ($infobox,$info)= create_txview();
-	
-	
-		
-	my @pages =(
-		{page_name=>" Avg. throughput/latency", page_num=>0},
-		{page_name=>" Injected Packet ", page_num=>1},
-		{page_name=>" Worst-Case Delay ",page_num=>2},
-		{page_name=>" Execution Time ",page_num=>3},
-	);
-
-	my @charts = (
-		{ type=>"2D_line", page_num=>0, graph_name=> "Latency", result_name => "latency_result", X_Title=> 'Desired Avg. Injected Load Per Router (flits/clock (%))', Y_Title=>'Avg. Latency (clock)', Z_Title=>undef, Y_Max=>100},
-  		{ type=>"2D_line", page_num=>0, graph_name=> "Throughput", result_name => "throughput_result", X_Title=> 'Desired Avg. Injected Load Per Router (flits/clock (%))', Y_Title=>'Avg. Throughput (flits/clock (%))', Z_Title=>undef},
-  		{ type=>"3D_bar",  page_num=>1, graph_name=> "Received", result_name => "packet_rsvd_result", X_Title=>'Core ID' , Y_Title=>'Received Packets Per Router', Z_Title=>undef},
-		{ type=>"3D_bar",  page_num=>1, graph_name=> "Sent", result_name => "packet_sent_result", X_Title=>'Core ID' , Y_Title=>'Sent Packets Per Router', Z_Title=>undef},
-  		{ type=>"3D_bar",  page_num=>2, graph_name=> "Received", result_name => "worst_delay_rsvd_result",X_Title=>'Core ID' , Y_Title=>'Worst-Case Delay (clk)', Z_Title=>undef},
-  		{ type=>"2D_line", page_num=>3, graph_name=> "-", result_name => "exe_time_result",X_Title=>'Desired Avg. Injected Load Per Router (flits/clock (%))' , Y_Title=>'Total Emulation Time (clk)', Z_Title=>undef},
-  	);
-		
-	my ($conf_box,$set_win)=process_notebook_gen($emulate,$info,"emulate", undef,@charts);
-	my $chart   =gen_multiple_charts ($emulate,\@pages,\@charts,.4);
-    
-	$main_table->set_row_spacings (4);
-	$main_table->set_col_spacings (1);
-		
-	my $generate = def_image_button('icons/forward.png','Run all');
-	my $open = def_image_button('icons/browse.png','Load');
-	my $diagram  = def_image_button('icons/diagram.png','Diagram');
-		
-	my ($entrybox,$entry) = def_h_labeled_entry('Save as:',undef);
-	
-	$entry->signal_connect( 'changed'=> sub{
-		my $name=$entry->get_text();
-		$emulate->object_add_attribute ("emulate_name",undef,$name);	
-	});	
-	my $save = def_image_button('icons/save.png','Save');
-	$entrybox->pack_end($save,   FALSE, FALSE,0);
-		
-	my $image = get_status_gif($emulate);	
-	my $v1=gen_vpaned($conf_box,.45,$image);
-	my $v2=gen_vpaned($infobox,.2,$chart);
-	my $h1=gen_hpaned($v1,.4,$v2);
-	
-	#$table->attach_defaults ($event_box, $col, $col+1, $row, $row+1);
-	$main_table->attach_defaults ($h1  , 0, 12, 0,24);
-	$main_table->attach ($open,0, 2, 24,25,'expand','shrink',2,2);
-#	$main_table->attach ($diagram, 2, 4, 24,25,'expand','shrink',2,2);
-	$main_table->attach ($entrybox,4, 7, 24,25,'expand','shrink',2,2);
-	$main_table->attach ($generate, 7, 9, 24,25,'expand','shrink',2,2);
-		
-	#check soc status every 0.5 second. referesh device table if there is any changes 
-	Glib::Timeout->add (100, sub{ 	 
-		my ($state,$timeout)= get_gui_status($emulate);
-		
-		if ($timeout>0){
-			$timeout--;
-			set_gui_status($emulate,$state,$timeout);	
-			return TRUE;
-		}
-		if($state eq "ideal"){
-			return TRUE;
-			 
-		}
-		
-		
-		#refresh GUI
-		my $name=$emulate->object_get_attribute ("emulate_name",undef);	
-		$entry->set_text($name) if(defined $name);
-		$conf_box->destroy();
-		$chart->destroy();
-		$image->destroy(); 
-		$image = get_status_gif($emulate);
-		($conf_box,$set_win)=process_notebook_gen($emulate,$info,"emulate",$set_win, @charts);
-		$chart   =gen_multiple_charts  ($emulate,\@pages,\@charts,.4);
-		$v1 -> pack1($conf_box, TRUE, TRUE); 	
-		$v1 -> pack2($image, TRUE, TRUE); 
-		$v2 -> pack2($chart, TRUE, TRUE); 
-		$conf_box->show_all();
-		$main_table->show_all();
-		set_gui_status($emulate,"ideal",0);
-		
-		return TRUE;
-		
-	} );
-	
-	 $diagram-> signal_connect("clicked" => sub{ 
-        show_topology_diagram ($emulate);
-    });	
-		
-	$generate-> signal_connect("clicked" => sub{ 
-		my @samples =$emulate->object_get_attribute_order("samples");
-		foreach my $sample (@samples){
-			$emulate->object_add_attribute ($sample,"status","run");	
-		}
-		run_emulator($emulate,$info);
-	});
-
-
-	$open-> signal_connect("clicked" => sub{ 
-		load_emulation($emulate,$info);
-		set_gui_status($emulate,"ref",5);
-	});	
-
-	$save-> signal_connect("clicked" => sub{ 
-		save_emulation($emulate);		
-		set_gui_status($emulate,"ref",5);
-	});	
-
-	
-
-	return add_widget_to_scrolled_win($main_table);
+    add_color_to_gd();
+    my $emulate= emulator->emulator_new();
+    set_gui_status($emulate,"ideal",0);
+    $emulate->object_add_attribute('compile','compilers',"QuartusII");
+    my $left_table = def_table (25, 6, FALSE);
+    my $right_table =def_table (25, 6, FALSE);
+    my $main_table = def_table (25, 12, FALSE);
+    my ($infobox,$info)= create_txview();
+    my @pages =(
+        {page_name=>" Avg. throughput/latency", page_num=>0},
+        {page_name=>" Injected Packet ", page_num=>1},
+        {page_name=>" Worst-Case Delay ",page_num=>2},
+        {page_name=>" Execution Time ",page_num=>3},
+    );
+    my @charts = (
+        { type=>"2D_line", page_num=>0, graph_name=> "Latency", result_name => "latency_result", X_Title=> 'Desired Avg. Injected Load Per Router (flits/clock (%))', Y_Title=>'Avg. Latency (clock)', Z_Title=>undef, Y_Max=>100},
+        { type=>"2D_line", page_num=>0, graph_name=> "Throughput", result_name => "throughput_result", X_Title=> 'Desired Avg. Injected Load Per Router (flits/clock (%))', Y_Title=>'Avg. Throughput (flits/clock (%))', Z_Title=>undef},
+        { type=>"3D_bar",  page_num=>1, graph_name=> "Received", result_name => "packet_rsvd_result", X_Title=>'Core ID' , Y_Title=>'Received Packets Per Router', Z_Title=>undef},
+        { type=>"3D_bar",  page_num=>1, graph_name=> "Sent", result_name => "packet_sent_result", X_Title=>'Core ID' , Y_Title=>'Sent Packets Per Router', Z_Title=>undef},
+        { type=>"3D_bar",  page_num=>2, graph_name=> "Received", result_name => "worst_delay_rsvd_result",X_Title=>'Core ID' , Y_Title=>'Worst-Case Delay (clk)', Z_Title=>undef},
+        { type=>"2D_line", page_num=>3, graph_name=> "-", result_name => "exe_time_result",X_Title=>'Desired Avg. Injected Load Per Router (flits/clock (%))' , Y_Title=>'Total Emulation Time (clk)', Z_Title=>undef},
+    );
+    my ($conf_box,$set_win)=process_notebook_gen($emulate,$info,"emulate", undef,@charts);
+    my $chart   =gen_multiple_charts ($emulate,\@pages,\@charts,.4);
+    $main_table->set_row_spacings (4);
+    $main_table->set_col_spacings (1);
+    my $ctrl = noc_emulate_ctrl($emulate,$info);
+    my $image = get_status_gif($emulate);
+    my $v1=gen_vpaned($conf_box,.45,$image);
+    my $v2=gen_vpaned($infobox,.2,$chart);
+    my $h1=gen_hpaned($v1,.4,$v2);
+    #$table->attach_defaults ($event_box, $col, $col+1, $row, $row+1);
+    $main_table->attach_defaults ($h1  , 0, 12, 0,24);
+    $main_table->attach ($ctrl, 0,12, 24,25,'fill','fill',2,2);
+    #check soc status every 0.5 second. referesh device table if there is any changes
+    Glib::Timeout->add (100, sub{
+        my ($state,$timeout)= get_gui_status($emulate);
+        if ($timeout>0){
+            $timeout--;
+            set_gui_status($emulate,$state,$timeout);
+            return TRUE;
+        }
+        if($state eq "ideal"){
+            return TRUE;
+        }
+        #refresh GUI
+        $ctrl->destroy();
+        $conf_box->destroy();
+        $chart->destroy();
+        $image->destroy();
+        $image = get_status_gif($emulate);
+        ($conf_box,$set_win)=process_notebook_gen($emulate,$info,"emulate",$set_win, @charts);
+        $chart   =gen_multiple_charts  ($emulate,\@pages,\@charts,.4);
+        $ctrl = noc_emulate_ctrl($emulate,$info);
+        $main_table->attach ($ctrl, 0,12, 24,25,'fill','fill',2,2);
+        $v1 -> pack1($conf_box, TRUE, TRUE);
+        $v1 -> pack2($image, TRUE, TRUE);
+        $v2 -> pack2($chart, TRUE, TRUE);
+        $conf_box->show_all();
+        $main_table->show_all();
+        set_gui_status($emulate,"ideal",0);
+        return TRUE;
+    } );
+    return add_widget_to_scrolled_win($main_table);
 }
-
-
-
+1;
\ No newline at end of file
diff --git a/mpsoc/perl_gui/lib/perl/emulator.pm b/mpsoc/perl_gui/lib/perl/emulator.pm
index 9b83acb..ad66939 100755
--- a/mpsoc/perl_gui/lib/perl/emulator.pm
+++ b/mpsoc/perl_gui/lib/perl/emulator.pm
@@ -1,126 +1,97 @@
 #!/usr/bin/perl -w -I ..
 ###############################################################################
-#
 # File:         emulator.pm
-# 
-#
 ###############################################################################
+
 use warnings;
 use strict;
 
-
-
-
 package emulator;
 
 sub uniq {
-  my %seen;
-  return grep { !$seen{$_}++ } @_;
+    my %seen;
+    return grep { !$seen{$_}++ } @_;
 }
 
 sub emulator_new {
     # be backwards compatible with non-OO call
     my $class = ("ARRAY" eq ref $_[0]) ? "mpsoc" : shift;
     my $self;
-
-   
     $self = {};
     $self->{file_name}        = (); # information on each file
     $self->{samples} = ();
     emulator_initial_setting($self);
-	
-
     bless($self,$class);
-
-   
     return $self;
-} 
+}
 
 sub emulator_initial_setting{
-	my $self=shift;
-	$self->{status}="ideal";
-	$self->{setting}{show_noc_setting}=1;
-	$self->{setting}{show_adv_setting}=0;
-	$self->{setting}{show_tile_setting}=0;	
-	$self->{setting}{soc_path}="lib/soc";
-	
+    my $self=shift;
+    $self->{status}="ideal";
+    $self->{setting}{show_noc_setting}=1;
+    $self->{setting}{show_adv_setting}=0;
+    $self->{setting}{show_tile_setting}=0;
+    $self->{setting}{soc_path}="lib/soc";
 }
 
-
-
-
-
-
-
-
 sub object_add_attribute{
-	my ($self,$attribute1,$attribute2,$value)=@_;
-	if(!defined $attribute2){$self->{$attribute1}=$value;}
-	else {$self->{$attribute1}{$attribute2}=$value;}
-
+    my ($self,$attribute1,$attribute2,$value)=@_;
+    if(!defined $attribute2){$self->{$attribute1}=$value;}
+    else {$self->{$attribute1}{$attribute2}=$value;}
 }
 
 sub object_get_attribute{
-	my ($self,$attribute1,$attribute2)=@_;
-	if(!defined $attribute2) {return $self->{$attribute1};}
-	return $self->{$attribute1}{$attribute2};
-
-
+    my ($self,$attribute1,$attribute2)=@_;
+    if(!defined $attribute2) {return $self->{$attribute1};}
+    return $self->{$attribute1}{$attribute2};
 }
 
 sub object_add_attribute_order{
-	my ($self,$attribute,@param)=@_;
-	my $r = $self->{'parameters_order'}{$attribute};
-	my @a;
-	@a = @{$r} if(defined $r);
-	push (@a,@param);
-	@a=uniq(@a);	
-	$self->{'parameters_order'}{$attribute} =\@a;
+    my ($self,$attribute,@param)=@_;
+    my $r = $self->{'parameters_order'}{$attribute};
+    my @a;
+    @a = @{$r} if(defined $r);
+    push (@a,@param);
+    @a=uniq(@a);
+    $self->{'parameters_order'}{$attribute} =\@a;
 }
 
 sub object_get_attribute_order{
-	my ($self,$attribute)=@_;
-	my @array;
-	@array =  @{$self->{parameters_order}{$attribute}} if (defined $self->{parameters_order}{$attribute});
-	return uniq (@array);
+    my ($self,$attribute)=@_;
+    my @array;
+    @array =  @{$self->{parameters_order}{$attribute}} if (defined $self->{parameters_order}{$attribute});
+    return uniq (@array);
 }
 
-
 sub object_delete_attribute_order{
-	my ($self,$attribute,@param)=@_;
-	my @array=object_get_attribute_order($self,$attribute);
-	foreach my $p (@param){
-		@array=remove_scolar_from_array(\@array,$p);
-
-	}
-	$self->{'parameters_order'}{$attribute}=[];
-	object_add_attribute_order($self,$attribute,@array);
+    my ($self,$attribute,@param)=@_;
+    my @array=object_get_attribute_order($self,$attribute);
+    foreach my $p (@param){
+        @array=remove_scolar_from_array(\@array,$p);
+    }
+    $self->{'parameters_order'}{$attribute}=[];
+    object_add_attribute_order($self,$attribute,@array);
 }
 
 sub object_remove_attribute{
-	my ($self,$attribute1,$attribute2)=@_;
-	if(!defined $attribute2){
-		delete $self->{$attribute1} if ( exists( $self->{$attribute1})); 
-	}
-	else {
-		delete $self->{$attribute1}{$attribute2} if ( exists( $self->{$attribute1}{$attribute2})); ;
-
-	}
-
+    my ($self,$attribute1,$attribute2)=@_;
+    if(!defined $attribute2){
+        delete $self->{$attribute1} if ( exists( $self->{$attribute1}));
+    }
+    else {
+        delete $self->{$attribute1}{$attribute2} if ( exists( $self->{$attribute1}{$attribute2})); ;
+    }
 }
-	
-sub remove_scolar_from_array{
-	my ($array_ref,$item)=@_;
-	my @array=@{$array_ref};
-	my @new;
-	foreach my $p (@array){
-		if($p ne $item ){
-			push(@new,$p);
-		}		
-	}
-	return @new;	
-}	
-
 
-
-1
+sub remove_scolar_from_array{
+    my ($array_ref,$item)=@_;
+    my @array=@{$array_ref};
+    my @new;
+    foreach my $p (@array){
+        if($p ne $item ){
+            push(@new,$p);
+        }
+    }
+    return @new;
+}
+1;
diff --git a/mpsoc/perl_gui/lib/perl/gdown.pl b/mpsoc/perl_gui/lib/perl/gdown.pl
index 2b62e76..ac520e9 100755
--- a/mpsoc/perl_gui/lib/perl/gdown.pl
+++ b/mpsoc/perl_gui/lib/perl/gdown.pl
@@ -11,94 +11,72 @@
 #
 use strict;
 #use POSIX;
-
 use FindBin;
 use lib $FindBin::Bin;
 
-
-
-
 sub execute_command {
-	my ($TEMP,$FILENAME,$URL)=@_;
+    my ($TEMP,$FILENAME,$URL)=@_;
     my $COMMAND="wget --progress=dot:giga --no-check-certificate --load-cookie $TEMP --save-cookie $TEMP \"$URL\"";
     $COMMAND.=" -O \"$FILENAME\"" if $FILENAME ne '';
     my $cmd = "xterm -e bash -c \'$COMMAND; sleep 5\'";
-    
     #print "command = $cmd\n";
-    
     my ($stdout,$exit,$stderr)=run_cmd_in_back_ground_get_stdout($cmd);
-    if(length $stderr>1){			
-			message_dialog("Error: $stderr",'error');
+    if(length $stderr>1){
+            message_dialog("Error: $stderr",'error');
     }
     return 1;
 }
 
 sub download_from_google_drive{
-	my ($URL,$FILENAME)=@_;
-	my ($name,$path,$suffix) = fileparse("$FILENAME",qr"\..[^.]*$");     
-	my $TEMP="$ENV{PRONOC_WORK}/tmp/$name.cookie.temp";
-	my $COMMAND;
-	my $confirm;
-	my $check;
-	
-	
-	die "\n./gdown.pl 'gdrive file url' [desired file name]\n\n" if $URL eq '';
-
-
-
-	
-	$FILENAME='gdown.'.strftime("%Y%m%d%H%M%S", localtime).'.'.substr(rand,2) if $FILENAME eq '';
-
-	if ($URL=~m#^https?://drive.google.com/file/d/([^/]+)#) {
-	    $URL="https://docs.google.com/uc?id=$1&export=download";
-	}
-	elsif ($URL=~m#^https?://drive.google.com/open\?id=([^/]+)#) {
-	    $URL="https://docs.google.com/uc?id=$1&export=download";
-	}
-
-	execute_command($TEMP,$FILENAME,$URL);
-
-	while (-s $FILENAME < 100000) { # only if the file isn't download yet
-	    open fFILENAME, '<', $FILENAME;
-	    $check=0;
-	    foreach (<fFILENAME>) {
-			if (/href="(\/uc\?export=download[^"]+)/) {
-			    $URL='https://docs.google.com'.$1;
-			    $URL=~s/&amp;/&/g;
-			    $confirm='';
-			    $check=1;
-			    last;
-			}
-			if (/confirm=([^;&]+)/) {
-			    $confirm=$1;
-			    $check=1;
-			    last;
-			}
-			if (/"downloadUrl":"([^"]+)/) {
-			    $URL=$1;
-			    $URL=~s/\\u003d/=/g;
-			    $URL=~s/\\u0026/&/g;
-			    $confirm='';
-			    $check=1;
-			    last;
-			}
-    	}
-		close fFILENAME;
-	    #die "Couldn't download the file :-(\n" if ($check==0);
-		if($check == 0 ) {
-			message_dialog("Error: Couldn't download the file :-(",'error');
-			return;
-		}
-
-
-		
-	    $URL=~s/confirm=([^;&]+)/confirm=$confirm/ if $confirm ne '';
-
-	    execute_command($TEMP,$FILENAME,$URL);
-	}
-
-	unlink $TEMP;
-
+    my ($URL,$FILENAME)=@_;
+    my ($name,$path,$suffix) = fileparse("$FILENAME",qr"\..[^.]*$");
+    my $TEMP="$ENV{PRONOC_WORK}/tmp/$name.cookie.temp";
+    my $COMMAND;
+    my $confirm;
+    my $check;
+    die "\n./gdown.pl 'gdrive file url' [desired file name]\n\n" if $URL eq '';
+    $FILENAME='gdown.'.strftime("%Y%m%d%H%M%S", localtime).'.'.substr(rand,2) if $FILENAME eq '';
+    if ($URL=~m#^https?://drive.google.com/file/d/([^/]+)#) {
+        $URL="https://docs.google.com/uc?id=$1&export=download";
+    }
+    elsif ($URL=~m#^https?://drive.google.com/open\?id=([^/]+)#) {
+        $URL="https://docs.google.com/uc?id=$1&export=download";
+    }
+    execute_command($TEMP,$FILENAME,$URL);
+    while (-s $FILENAME < 100000) { # only if the file isn't download yet
+        open fFILENAME, '<', $FILENAME;
+        $check=0;
+        foreach (<fFILENAME>) {
+            if (/href="(\/uc\?export=download[^"]+)/) {
+                $URL='https://docs.google.com'.$1;
+                $URL=~s/&amp;/&/g;
+                $confirm='';
+                $check=1;
+                last;
+            }
+            if (/confirm=([^;&]+)/) {
+                $confirm=$1;
+                $check=1;
+                last;
+            }
+            if (/"downloadUrl":"([^"]+)/) {
+                $URL=$1;
+                $URL=~s/\\u003d/=/g;
+                $URL=~s/\\u0026/&/g;
+                $confirm='';
+                $check=1;
+                last;
+            }
+        }
+        close fFILENAME;
+        #die "Couldn't download the file :-(\n" if ($check==0);
+        if($check == 0 ) {
+            message_dialog("Error: Couldn't download the file :-(",'error');
+            return;
+        }
+        $URL=~s/confirm=([^;&]+)/confirm=$confirm/ if $confirm ne '';
+        execute_command($TEMP,$FILENAME,$URL);
+    }
+    unlink $TEMP;
 }
-
 1;
diff --git a/mpsoc/perl_gui/lib/perl/graph.pl b/mpsoc/perl_gui/lib/perl/graph.pl
index f3d7c4b..29b983d 100755
--- a/mpsoc/perl_gui/lib/perl/graph.pl
+++ b/mpsoc/perl_gui/lib/perl/graph.pl
@@ -5,520 +5,390 @@
 use GD::Graph::linespoints;
 use constant::boolean;
 
-
-
-
 sub gen_multiple_charts{
-	my ($self,$pageref,$charts_ref,$image_scale)=@_;
-	my @pages=@{$pageref};
-	my @charts=@{$charts_ref};
-	my $notebook = gen_notebook();
-	$notebook->set_scrollable(TRUE);
-	
-
-	#check if we need to save all graph results
-	my $save_all_status = $self->object_get_attribute ("graph_save","save_all_result");
-	$save_all_status=0 if (!defined $save_all_status);
-	$self->object_add_attribute ("graph_save","save_all_result",0);
-	if ($save_all_status ==1){
-		my $save_path = $self->object_get_attribute ('sim_param','ALL_RESULT_DIR');
-		if (-d $save_path){
-			my $results_path = "$save_path/all_results";
-			rmtree("$results_path");
-			mkpath("$results_path",1,01777);
-			save_all_results($self,$pageref,$charts_ref,$results_path);
-			
-		}
-	}
-	
-	foreach my $page (@pages){	
-		my @selects;
-		my $page_id= "P$page->{page_num}";
-		my $active = $self->object_get_attribute ($page_id,'active');	
-		
-		foreach my $chart (@charts){	
-			push (@selects,$chart->{graph_name})if($page->{page_num} == $chart->{page_num} );
-			
-		}
-		$active =$selects[0] if (!defined $active);
-		
-		foreach my $chart (@charts){
-			my $graph_id= $page_id."$chart->{graph_name}";
-				
-			if($active eq $chart->{graph_name} && $page->{page_num} == $chart->{page_num}){
-				
-				my $p=  gen_graph  ($self,$chart,$image_scale,@selects);
-				$notebook->append_page ($p,gen_label_with_mnemonic ($page->{page_name})); 
-				$self->object_add_attribute ($graph_id,'type',$chart->{type});	
-			}
-			
-		}
-		
-		
-		#print "$page->{page_name} : @selects \n";
-		
-	}	
-	
-		
-		
-		
-	my $scrolled_win = add_widget_to_scrolled_win($notebook,gen_scr_win_with_adjst($self,"chart_sc_win"));	
-	$scrolled_win->show_all;
-	
-	my $page_num=$self->object_get_attribute ("chart_notebook","currentpage");
-	$notebook->set_current_page ($page_num) if(defined $page_num);
-	$notebook->signal_connect( 'switch-page'=> sub{			
-		$self->object_add_attribute ("chart_notebook","currentpage",$_[2]);	#save the new pagenumber
-		#print "$self->object_add_attribute (\"chart_notebook\",\"currentpage\",$_[2]);\n";			
-	});
-		
-	#return ($scrolled_win,$set_win);
-	return $scrolled_win;
-
-
-	
-
+    my ($self,$pageref,$charts_ref,$image_scale)=@_;
+    my @pages=@{$pageref};
+    my @charts=@{$charts_ref};
+    my $notebook = gen_notebook();
+    $notebook->set_scrollable(TRUE);
+    #check if we need to save all graph results
+    my $save_all_status = $self->object_get_attribute ("graph_save","save_all_result");
+    $save_all_status=0 if (!defined $save_all_status);
+    $self->object_add_attribute ("graph_save","save_all_result",0);
+    if ($save_all_status ==1){
+        my $save_path = $self->object_get_attribute ('sim_param','ALL_RESULT_DIR');
+        if (-d $save_path){
+            my $results_path = "$save_path/all_results";
+            rmtree("$results_path");
+            mkpath("$results_path",1,01777);
+            save_all_results($self,$pageref,$charts_ref,$results_path);
+        }
+    }
+    foreach my $page (@pages){
+        my @selects;
+        my $page_id= "P$page->{page_num}";
+        my $active = $self->object_get_attribute ($page_id,'active');
+        foreach my $chart (@charts){
+            push (@selects,$chart->{graph_name})if($page->{page_num} == $chart->{page_num} );
+        }
+        $active =$selects[0] if (!defined $active);
+        foreach my $chart (@charts){
+            my $graph_id= $page_id."$chart->{graph_name}";
+            if($active eq $chart->{graph_name} && $page->{page_num} == $chart->{page_num}){
+                my $p=  gen_graph  ($self,$chart,$image_scale,@selects);
+                $notebook->append_page ($p,gen_label_with_mnemonic ($page->{page_name}));
+                $self->object_add_attribute ($graph_id,'type',$chart->{type});
+            }
+        }
+        #print "$page->{page_name} : @selects \n";
+    }
+    my $scrolled_win = add_widget_to_scrolled_win($notebook,gen_scr_win_with_adjst($self,"chart_sc_win"));
+    $scrolled_win->show_all;
+    my $page_num=$self->object_get_attribute ("chart_notebook","currentpage");
+    $notebook->set_current_page ($page_num) if(defined $page_num);
+    $notebook->signal_connect( 'switch-page'=> sub{
+        $self->object_add_attribute ("chart_notebook","currentpage",$_[2]);    #save the new pagenumber
+        #print "$self->object_add_attribute (\"chart_notebook\",\"currentpage\",$_[2]);\n";
+    });
+    #return ($scrolled_win,$set_win);
+    return $scrolled_win;
 }
 
-
 sub save_all_results{
-	my ($self,$pageref,$charts_ref,$results_path)=@_;
-	my @pages=@{$pageref};
-	my @charts=@{$charts_ref};
-	foreach my $chart (@charts){
-			my $result_name= "$chart->{result_name}";
-			my $charttype=  "$chart->{type}";	
-			
-			if($charttype eq '2D_line'){
-				my $file_name = "$results_path/${result_name}.txt"; 
-				write_graph_results_in_file($self,$file_name,$result_name,undef,$charttype);
-				next;
-			};#3d
-					
-			my @ratios;			
-			my @x;
-			
-			
-			my @samples =$self->object_get_attribute_order("samples");	
-			foreach my $sample (@samples){
-				
-				my $ref=$self->object_get_attribute ($sample,$result_name);
-				if(defined $ref){
-					@ratios=get_uniq_keys($ref,@ratios);
-					
-				}
-				
-				foreach my $ratio (@ratios){
-					
-					my @results;
-					foreach my $sample2 (@samples){
-						my $ref=$self->object_get_attribute ($sample2,"$result_name");
-						@x=get_uniq_keys($ref->{$ratio},@x) if(defined $ref);	
-											
-					}
-				
-					my $i=1;
-					foreach my $sample (@samples){
-						my @y;
-						my $ref=$self->object_get_attribute ($sample,"$result_name");
-						if(defined $ref){
-							foreach my $v (@x){
-								my $w=$ref->{$ratio}->{$v};
-								push(@y,$w);							
-							}#for v
-							$results[$i]=\@y if(scalar @x);
-							$i++;
-						}#if
-					}#sample
-					$results[0]=\@x if(scalar @x);
-					my $file_name = "$results_path/${result_name}_r$ratio.txt"; 
-					write_graph_results_in_file($self,$file_name,$result_name,\@results,$charttype);
-					
-				}#ratio
-			}#sample				
-	}#chart	
-	#done saving clear the saving status
-	
-	
-}	
+    my ($self,$pageref,$charts_ref,$results_path)=@_;
+    my @pages=@{$pageref};
+    my @charts=@{$charts_ref};
+    foreach my $chart (@charts){
+            my $result_name= "$chart->{result_name}";
+            my $charttype=  "$chart->{type}";
+            if($charttype eq '2D_line'){
+                my $file_name = "$results_path/${result_name}.txt";
+                write_graph_results_in_file($self,$file_name,$result_name,undef,$charttype);
+                next;
+            };#3d
+            my @ratios;
+            my @x;
+            my @samples =$self->object_get_attribute_order("samples");
+            foreach my $sample (@samples){
+                my $ref=$self->object_get_attribute ($sample,$result_name);
+                if(defined $ref){
+                    @ratios=get_uniq_keys($ref,@ratios);
+                }
+                foreach my $ratio (@ratios){
+                    my @results;
+                    foreach my $sample2 (@samples){
+                        my $ref=$self->object_get_attribute ($sample2,"$result_name");
+                        @x=get_uniq_keys($ref->{$ratio},@x) if(defined $ref);
+                    }
+                    my $i=1;
+                    foreach my $sample (@samples){
+                        my @y;
+                        my $ref=$self->object_get_attribute ($sample,"$result_name");
+                        if(defined $ref){
+                            foreach my $v (@x){
+                                my $w=$ref->{$ratio}->{$v};
+                                push(@y,$w);
+                            }#for v
+                            $results[$i]=\@y if(scalar @x);
+                            $i++;
+                        }#if
+                    }#sample
+                    $results[0]=\@x if(scalar @x);
+                    my $file_name = "$results_path/${result_name}_r$ratio.txt";
+                    write_graph_results_in_file($self,$file_name,$result_name,\@results,$charttype);
+                }#ratio
+            }#sample
+    }#chart
+    #done saving clear the saving status
+}
 use Scalar::Util qw(looks_like_number);
 sub check_numeric {
-	my ($ref)=@_;	
-	my %r=%$ref;
-	foreach my $p (sort keys %r){
-		return 0 unless (looks_like_number($p));
-	}
-	return 1;
-}	
+    my ($ref)=@_;
+    my %r=%$ref;
+    foreach my $p (sort keys %r){
+        return 0 unless (looks_like_number($p));
+    }
+    return 1;
+}
 
 sub get_uniq_keys {
-	my ($ref,@x)=@_;		
-		
-	if(defined $ref) {
-		my %r=%$ref;
-		my $n = check_numeric($ref);
-		
-		
-		push(@x, sort {$a<=>$b} keys %r) if ($n);
-		push(@x, sort {$a cmp $b} keys %r) unless ($n);
-		
-		my  @x2;
-		@x2 =  uniq(sort {$a<=>$b} @x) if (scalar @x && $n == 1);
-		@x2 =  uniq(sort {$a cmp $b} @x) if (scalar @x && $n==0);
-		
-		return @x2;	
-	}
-	return @x;
+    my ($ref,@x)=@_;
+    if(defined $ref) {
+        my %r=%$ref;
+        my $n = check_numeric($ref);
+        push(@x, sort {$a<=>$b} keys %r) if ($n);
+        push(@x, sort {$a cmp $b} keys %r) unless ($n);
+        my  @x2;
+        @x2 =  uniq(sort {$a<=>$b} @x) if (scalar @x && $n == 1);
+        @x2 =  uniq(sort {$a cmp $b} @x) if (scalar @x && $n==0);
+        return @x2;
+    }
+    return @x;
 }
 
-
 sub gen_graph {
-	my ($self,$chart,$image_scale,@selects)=@_;	
-	if($chart->{type} eq '2D_line') {return gen_2D_line($self,$chart,@selects);}
-	if($chart->{type} eq 'Heat-map') {return gen_heat_map($self,$chart,@selects);}
-	return  gen_3D_bar($self,$chart,$image_scale,@selects);
+    my ($self,$chart,$image_scale,@selects)=@_;
+    if($chart->{type} eq '2D_line') {return gen_2D_line($self,$chart,@selects);}
+    if($chart->{type} eq 'Heat-map') {return gen_heat_map($self,$chart,@selects);}
+    return  gen_3D_bar($self,$chart,$image_scale,@selects);
 }
 
-
-
-
 sub gen_heat_map{
-	my ($self,$chart,@selects)=@_;
-	
-	my $page_id= "P$chart->{page_num}";
-	my $graph_id= $page_id."$chart->{graph_name}";
-	my $result_name= $chart->{result_name};
-	
-	
-	my $table = def_table (25, 10, FALSE);
-	
-	my $plus = def_image_button('icons/plus.png',undef,TRUE);
-	my $minues = def_image_button('icons/minus.png',undef,TRUE);
-	my $setting = def_image_button('icons/setting.png',undef,TRUE);
-	my $save = def_image_button('icons/save.png',undef,TRUE);
-	
-	my $type_combo=gen_combobox_object ($self,"${graph_id}","type","Table,Image",'Table','ref',2);
-	
-	
-	my @samples =$self->object_get_attribute_order("samples");	
-	@samples = ('-') if (scalar @samples == 0);
-	my $sample_combx=gen_combobox_object ($self,${graph_id},"sample_sel",join(",", @samples),$samples[0],'ref',2);
-	my $sample = $self->object_get_attribute("${graph_id}","sample_sel");
-	my $ref=$self->object_get_attribute ($sample,$result_name);
-	my @ratios;
-	@ratios = get_uniq_keys($ref,@ratios);
-	@ratios = ('-') if (!defined $ratios[0]);
-	my $rcnt = join(",", @ratios); 
-	my $ratio_combx=gen_combobox_object ($self,${graph_id},"ratio_sel",$rcnt,$ratios[0],'ref',2);
-	my $content=join( ',', @selects); 
-    my $active_page=gen_combobox_object ($self,$page_id,"active",$content,$selects[0],'ref',2); 
-	
-	
-	
-	my $t = def_table (25, 10, FALSE);
-	#my $dotfile= generate_heat_map_dot_file(undef,40);
-	
-	
-	
-	my $r_sel = $self->object_get_attribute("${graph_id}","ratio_sel"); 
-	my $dat;
-	$dat=  $ref->{$r_sel} if (defined $ref->{$r_sel});	 
-	my $scrolled_win = add_widget_to_scrolled_win($t);
-	
-	
-	my $heatmap_type =$self->object_get_attribute("${graph_id}","type");
-	$heatmap_type = 'Table' if (!defined $heatmap_type);
-
-   my $scale= $self->object_get_attribute("${graph_id}","scale");
-   if(!defined $scale){
-		 	$scale = .5; 
-		 	$self->object_add_attribute("${graph_id}","scale", $scale );
-	}
-
-	my $diagram;
-	my $map_info;
+    my ($self,$chart,@selects)=@_;
+    my $page_id= "P$chart->{page_num}";
+    my $graph_id= $page_id."$chart->{graph_name}";
+    my $result_name= $chart->{result_name};
+    my $table = def_table (25, 10, FALSE);
+    my $plus = def_image_button('icons/plus.png',undef,TRUE);
+    my $minues = def_image_button('icons/minus.png',undef,TRUE);
+    my $setting = def_image_button('icons/setting.png',undef,TRUE);
+    my $save = def_image_button('icons/save.png',undef,TRUE);
+    my $type_combo=gen_combobox_object ($self,"${graph_id}","type","Table,Image",'Table','ref',2);
+    my @samples =$self->object_get_attribute_order("samples");
+    my @sample_names;
+    for my $i (0..$#samples) {
+        my $name=$self->object_get_attribute($samples[$i],"line_name");
+        $sample_names[$i]=$name if(defined $name);
+    }
+    @sample_names = ('-') if (scalar @samples == 0);
+    my $sample_combx=gen_combobox_object ($self,${graph_id},"sample_sel",join(",", @sample_names),$sample_names[0],'ref',2);
+    my $sample = $self->object_get_attribute("${graph_id}","sample_sel");
+    for my $i (0..$#samples) {
+        if ($sample_names[$i] eq $sample){
+            $sample = $samples[$i];
+            last;
+        }
+    }
+    my $ref=$self->object_get_attribute ($sample,$result_name);
+    my @ratios;
+    @ratios = get_uniq_keys($ref,@ratios);
+    @ratios = ('-') if (!defined $ratios[0]);
+    my $rcnt = join(",", @ratios);
+    my $ratio_combx=gen_combobox_object ($self,${graph_id},"ratio_sel",$rcnt,$ratios[0],'ref',2);
+    my $content=join( ',', @selects);
+    my $active_page=gen_combobox_object ($self,$page_id,"active",$content,$selects[0],'ref',2);
+    my $t = def_table (25, 10, FALSE);
+    #my $dotfile= generate_heat_map_dot_file(undef,40);
+    my $r_sel = $self->object_get_attribute("${graph_id}","ratio_sel");
+    my $dat;
+    $dat=  $ref->{$r_sel} if (defined $ref->{$r_sel});
+    my $scrolled_win = add_widget_to_scrolled_win($t);
+    my $heatmap_type =$self->object_get_attribute("${graph_id}","type");
+    $heatmap_type = 'Table' if (!defined $heatmap_type);
+    my $scale= $self->object_get_attribute("${graph_id}","scale");
+    if(!defined $scale){
+        $scale = .5;
+        $self->object_add_attribute("${graph_id}","scale", $scale );
+    }
+    my $diagram;
+    my $map_info;
     my $image ="$ENV{PRONOC_WORK}/tmp/heatmap.png";
-	if($chart->{'graph_name'} ne 'Select'){
-		if ($heatmap_type eq 'Image'){
-			
-			my $regen_img= $self->object_get_attribute("${graph_id}","regen_img");
-			$regen_img = 0 if (!defined $regen_img);
-			if ($regen_img==1){				
-				my $title= $self->object_get_attribute($page_id,"active");
-				generate_heat_map_img_file($dat,$image,$title);
-				$self->object_add_attribute("${graph_id}","regen_img",0);
-			}	
-					
-			show_diagram ($self,$scrolled_win,${graph_id},"heatmap.png") if(-f $image);
-		
-			$minues -> signal_connect("clicked" => sub{ 
-				$scale*=.9  if ($scale >0.1);
-				$self->object_add_attribute("${graph_id}","scale", $scale );
-				show_diagram ($self,$scrolled_win,${graph_id},"heatmap.png") if(-f $image);									
-			});	
-
-			$plus  -> signal_connect("clicked" => sub{ 
-				$scale*=1.1 if ($scale <10);		
-				$self->object_add_attribute("${graph_id}","scale", $scale );
-				show_diagram ($self,$scrolled_win,${graph_id},"heatmap.png") if(-f $image);	
-			});	  
-		
-			$save-> signal_connect("clicked" => sub{ 
-				my $file;
-				my $title ='Save as';
-				my @extensions=('png');
-				my $open_in=undef;
-				my $dialog=save_file_dialog  ($title, @extensions);
-				$dialog->set_current_folder ($open_in) if(defined  $open_in);
-				if ( "ok" eq $dialog->run ) {
-	    			$file = $dialog->get_filename;
-					my $ext = $dialog->get_filter;
-					$ext=$ext->get_name;
-					my ($name,$path,$suffix) = fileparse("$file",qr"\..[^.]*$");
-					$file = ($suffix eq ".$ext" )? $file : "$file.$ext";
-					copy("$image","$file");
-					
-				}
-				$dialog->destroy;
-			});	
-			set_tip($save, "Save graph");
-		
-		
-		
-		}
-		else{		#heatmap table
-		   my $t;
-		   ($t,$map_info)=generate_heat_map_table($dat);
-			add_widget_to_scrolled_win($t ,$scrolled_win);
-			$scrolled_win->show_all();	
-		}
-	}  
-	
-	      
-     
-     
-   #  my $scrolled_win = add_widget_to_scrolled_win($t);
-	# show_diagram ($self,$scrolled_win,${graph_id},"heatmap.png");	
-      
-      
-   
-    
-    
-  
-    
-   
+    if($chart->{'graph_name'} ne 'Select'){
+        if ($heatmap_type eq 'Image'){
+            my $regen_img= $self->object_get_attribute("${graph_id}","regen_img");
+            $regen_img = 0 if (!defined $regen_img);
+            if ($regen_img==1){
+                my $title= $self->object_get_attribute($page_id,"active");
+                generate_heat_map_img_file($dat,$image,$title);
+                $self->object_add_attribute("${graph_id}","regen_img",0);
+            }
+            show_diagram ($self,$scrolled_win,${graph_id},"heatmap.png") if(-f $image);
+            $minues -> signal_connect("clicked" => sub{
+                $scale*=.9  if ($scale >0.1);
+                $self->object_add_attribute("${graph_id}","scale", $scale );
+                show_diagram ($self,$scrolled_win,${graph_id},"heatmap.png") if(-f $image);
+            });
+            $plus  -> signal_connect("clicked" => sub{
+                $scale*=1.1 if ($scale <10);
+                $self->object_add_attribute("${graph_id}","scale", $scale );
+                show_diagram ($self,$scrolled_win,${graph_id},"heatmap.png") if(-f $image);
+            });
+            $save-> signal_connect("clicked" => sub{
+                my $file;
+                my $title ='Save as';
+                my @extensions=('png');
+                my $open_in=undef;
+                my $dialog=save_file_dialog  ($title, @extensions);
+                $dialog->set_current_folder ($open_in) if(defined  $open_in);
+                if ( "ok" eq $dialog->run ) {
+                    $file = $dialog->get_filename;
+                    my $ext = $dialog->get_filter;
+                    $ext=$ext->get_name;
+                    my ($name,$path,$suffix) = fileparse("$file",qr"\..[^.]*$");
+                    $file = ($suffix eq ".$ext" )? $file : "$file.$ext";
+                    copy("$image","$file");
+                }
+                $dialog->destroy;
+            });
+            set_tip($save, "Save graph");
+        }
+        else{        #heatmap table
+            my $t;
+            ($t,$map_info)=generate_heat_map_table($dat);
+            add_widget_to_scrolled_win($t ,$scrolled_win);
+            $scrolled_win->show_all();
+        }
+    }
+    #  my $scrolled_win = add_widget_to_scrolled_win($t);
+    # show_diagram ($self,$scrolled_win,${graph_id},"heatmap.png");
     $table->attach_defaults ($scrolled_win , 0, 9, 0, 24);
-	my $row=0;
-	
-	
-	$type_combo-> signal_connect("changed" => sub{
-		$self->object_add_attribute("${graph_id}","regen_img",1);
-		
-	});
-	
-	
-	$table->attach ($active_page, 9, 10, $row, $row+1,'shrink','shrink',2,2);$row++;
-	$table->attach ($sample_combx, 9, 10, $row, $row+1,'shrink','shrink',2,2); $row++;
-	$table->attach (gen_label_in_center("Injection-Ratio/"), 9, 10, $row, $row+1,'shrink','shrink',2,2); $row++;
-	$table->attach (gen_label_in_center("Task-file index"), 9, 10, $row, $row+1,'shrink','shrink',2,2); $row++;
-	$table->attach ($ratio_combx, 9, 10, $row, $row+1,'shrink','shrink',2,2); $row++;
+    my $row=0;
+    $type_combo-> signal_connect("changed" => sub{
+        $self->object_add_attribute("${graph_id}","regen_img",1);
+    });
+    $table->attach ($active_page, 9, 10, $row, $row+1,'shrink','shrink',2,2);$row++;
+    $table->attach ($sample_combx, 9, 10, $row, $row+1,'shrink','shrink',2,2); $row++;
+    $table->attach (gen_label_in_center("Injection-Ratio/"), 9, 10, $row, $row+1,'shrink','shrink',2,2); $row++;
+    $table->attach (gen_label_in_center("Task-file index"), 9, 10, $row, $row+1,'shrink','shrink',2,2); $row++;
+    $table->attach ($ratio_combx, 9, 10, $row, $row+1,'shrink','shrink',2,2); $row++;
     $table->attach (gen_label_in_center("Graph-Type"), 9, 10, $row, $row+1,'shrink','shrink',2,2); $row++;
     $table->attach ($type_combo, 9, 10, $row, $row+1,'shrink','shrink',2,2); $row++;
-	
-	if ($heatmap_type eq 'Image'){
-		$table->attach ($plus , 9, 10, $row, $row+1,'shrink','shrink',2,2); $row++;
-		$table->attach ($minues, 9, 10, $row, $row+1,'shrink','shrink',2,2); $row++;
-		$table->attach ($save, 9, 10, $row,  $row+1,'shrink','shrink',2,2); $row++;
-	}elsif(defined $map_info){
-		$table->attach ($map_info , 9, 10, $row, $row+1,'shrink','shrink',2,2); $row+=6;
-		
-	}
-	#$table->attach ($setting, 9, 10, $row,  $row+1,'shrink','shrink',2,2); $row++;
-	
-	while ($row<10){
-		my $tmp=gen_label_in_left('');
-		$table->attach_defaults ($tmp, 9, 10, $row,  $row+1);$row++;
-	}
-		
+    if ($heatmap_type eq 'Image'){
+        $table->attach ($plus , 9, 10, $row, $row+1,'shrink','shrink',2,2); $row++;
+        $table->attach ($minues, 9, 10, $row, $row+1,'shrink','shrink',2,2); $row++;
+        $table->attach ($save, 9, 10, $row,  $row+1,'shrink','shrink',2,2); $row++;
+    }elsif(defined $map_info){
+        $table->attach ($map_info , 9, 10, $row, $row+1,'shrink','shrink',2,2); $row+=6;
+    }
+    #$table->attach ($setting, 9, 10, $row,  $row+1,'shrink','shrink',2,2); $row++;
+    while ($row<10){
+        my $tmp=gen_label_in_left('');
+        $table->attach_defaults ($tmp, 9, 10, $row,  $row+1);$row++;
+    }
     return $table;
-    
-	
-	
-	
-	
 }
 
-
 sub gen_3D_bar{
-	my ($self,$chart,$image_scale,@selects)=@_;
-   # $image_scale = .4 if (!defined $image_scale);
-	my($width,$hight)=max_win_size();
-	my $page_id= "P$chart->{page_num}";
-	my $graph_id= $page_id."$chart->{graph_name}";
-	#my $graph_name=$chart->{graph_name};
-	my $result_name= $chart->{result_name};
-	
-	my @legend_keys;    
-	
-	
-	my @results;
-	$results[0]= [0];
-	$results[1]= [0];
-	#$results[2]= [0];
-
-	
-
-	my $legend_info="This attribute controls placement of the legend within the graph image. The value is supplied as a two-letter string, where the first letter is placement (a B or an R for bottom or right, respectively) and the second is alignment (L, R, C, T, or B for left, right, center, top, or bottom, respectively). ";
-	
-my $fontsize="Tiny,Small,MediumBold,Large,Giant";
-
-
-
-my @ginfo = (
-#{ label=>"Graph Title", param_name=>"G_Title", type=>"Entry", default_val=>undef, content=>undef, info=>undef, param_parent=>"${graph_name}_param"    , ref_delay=>undef },  
-{ label=>"Y Axix Title", param_name=>"Y_Title", type=>"Entry", default_val=>$chart->{"Y_Title"}, content=>undef, info=>undef, param_parent=>"${graph_id}_param"    , ref_delay=>undef },
-  { label=>"X Axix Title", param_name=>"X_Title", type=>"Entry", default_val=>$chart->{"X_Title"}, content=>undef, info=>undef, param_parent=>"${graph_id}_param"    ,ref_delay=>undef },
-  { label=>"legend placement", param_name=>"legend_placement", type=>'Combo-box', default_val=>'BL', content=>"BL,BC,BR,RT,RC,RB", info=>$legend_info, param_parent=>"${graph_id}_param"    , ref_delay=>1},
- 
- { label=>"Y min", param_name=>"Y_MIN", type=>'Spin-button', default_val=>0, content=>"0,1024,1", info=>"Y axix minimum value", param_parent=>"${graph_id}_param"    , ref_delay=> 5},
- { label=>"X min", param_name=>"X_MIN", type=>'Spin-button', default_val=>0, content=>"0,1024,1", info=>"X axix minimum value", param_parent=>"${graph_id}_param"    , ref_delay=> 5},
-{ label=>"X max", param_name=>"X_MAX", type=>'Spin-button', default_val=>100, content=>"0,1024,1", info=>"X axix maximum value", param_parent=>"${graph_id}_param"    , ref_delay=> 5},
- { label=>"Line Width", param_name=>"LINEw", type=>'Spin-button', default_val=>3, content=>"1,20,1", info=>undef, param_parent=>"${graph_id}_param"    , ref_delay=> 5},
-#{ label=>"Y Axis Values", param_name=>"y_value", type=>'Combo-box', default_val=>'Original', content=>"Original,Normalized to 1,Normalized to 100", info=>undef, param_parent=>"${graph_name}_param"    , ref_delay=>1},
-{ label=>"legend font size", param_name=>"legend_font", type=>'Combo-box', default_val=>'MediumBold', content=>$fontsize, info=>undef, param_parent=>"${graph_id}_param"    , ref_delay=>1}, 
-{ label=>"label font size", param_name=>"label_font", type=>'Combo-box', default_val=>'MediumBold', content=>$fontsize, info=>undef, param_parent=>"${graph_id}_param"    , ref_delay=>1},
-  { label=>"label font size", param_name=>"x_axis_font", type=>'Combo-box', default_val=>'MediumBold', content=>$fontsize, info=>undef, param_parent=>"${graph_id}_param"    , ref_delay=>1},
-);	
-
+    my ($self,$chart,$image_scale,@selects)=@_;
+    # $image_scale = .4 if (!defined $image_scale);
+    my($width,$hight)=max_win_size();
+    my $page_id= "P$chart->{page_num}";
+    my $graph_id= $page_id."$chart->{graph_name}";
+    #my $graph_name=$chart->{graph_name};
+    my $result_name= $chart->{result_name};
+    my @legend_keys;
+    my @results;
+    $results[0]= [0];
+    $results[1]= [0];
+    #$results[2]= [0];
+    my $legend_info="This attribute controls placement of the legend within the graph image. The value is supplied as a two-letter string, where the first letter is placement (a B or an R for bottom or right, respectively) and the second is alignment (L, R, C, T, or B for left, right, center, top, or bottom, respectively). ";
+    my $fontsize="Tiny,Small,MediumBold,Large,Giant";
+    my @ginfo = (
+    #{ label=>"Graph Title", param_name=>"G_Title", type=>"Entry", default_val=>undef, content=>undef, info=>undef, param_parent=>"${graph_name}_param"    , ref_delay=>undef },
+    { label=>"Y Axix Title", param_name=>"Y_Title", type=>"Entry", default_val=>$chart->{"Y_Title"}, content=>undef, info=>undef, param_parent=>"${graph_id}_param"    , ref_delay=>undef },
+    { label=>"X Axix Title", param_name=>"X_Title", type=>"Entry", default_val=>$chart->{"X_Title"}, content=>undef, info=>undef, param_parent=>"${graph_id}_param"    ,ref_delay=>undef },
+    { label=>"legend placement", param_name=>"legend_placement", type=>'Combo-box', default_val=>'BL', content=>"BL,BC,BR,RT,RC,RB", info=>$legend_info, param_parent=>"${graph_id}_param"    , ref_delay=>1},
+    { label=>"Y min", param_name=>"Y_MIN", type=>'Spin-button', default_val=>0, content=>"0,1024,1", info=>"Y axix minimum value", param_parent=>"${graph_id}_param"    , ref_delay=> 5},
+    { label=>"X min", param_name=>"X_MIN", type=>'Spin-button', default_val=>0, content=>"0,1024,1", info=>"X axix minimum value", param_parent=>"${graph_id}_param"    , ref_delay=> 5},
+    { label=>"X max", param_name=>"X_MAX", type=>'Spin-button', default_val=>100, content=>"0,1024,1", info=>"X axix maximum value", param_parent=>"${graph_id}_param"    , ref_delay=> 5},
+    { label=>"Line Width", param_name=>"LINEw", type=>'Spin-button', default_val=>3, content=>"1,20,1", info=>undef, param_parent=>"${graph_id}_param"    , ref_delay=> 5},
+    #{ label=>"Y Axis Values", param_name=>"y_value", type=>'Combo-box', default_val=>'Original', content=>"Original,Normalized to 1,Normalized to 100", info=>undef, param_parent=>"${graph_name}_param"    , ref_delay=>1},
+    { label=>"legend font size", param_name=>"legend_font", type=>'Combo-box', default_val=>'MediumBold', content=>$fontsize, info=>undef, param_parent=>"${graph_id}_param"    , ref_delay=>1},
+    { label=>"label font size", param_name=>"label_font", type=>'Combo-box', default_val=>'MediumBold', content=>$fontsize, info=>undef, param_parent=>"${graph_id}_param"    , ref_delay=>1},
+    { label=>"label font size", param_name=>"x_axis_font", type=>'Combo-box', default_val=>'MediumBold', content=>$fontsize, info=>undef, param_parent=>"${graph_id}_param"    , ref_delay=>1},
+);
 my $content=join( ',', @selects);
-
 my $dimension=gen_combobox_object ($self,$graph_id,"dimension","2D,3D","3D",'ref',2);
 my $active_page=gen_combobox_object ($self,$page_id,"active",$content,$selects[0],'ref',2);
-
-
-#print "${graph_name}_${dir}_result\n";		
-		my @ratios;
-		my @color;
-		my $min_y=200;
-		my $i=0;
-		my @samples =$self->object_get_attribute_order("samples");	
-		@samples = ('no_name') if (scalar @samples == 0);
-		foreach my $sample (@samples){
-			
-			my $color_num=$self->object_get_attribute($sample,"color");
-			my $l_name= $self->object_get_attribute($sample,"line_name");
-			
-			
-			#push(@color, "my_color$color_num");
-			my $ref=$self->object_get_attribute ($sample,$result_name);
-			if(defined $ref){
-				$i++;
-				@ratios=get_uniq_keys($ref,@ratios);
-				$color_num=$i+1 if(!defined $color_num);
-				push(@color, "my_color$color_num");
-				$legend_keys[$i-1]= (defined $l_name)? $l_name : $sample;
-			}
-			
-						
-		}#for
-	$content = join(",", @ratios); 
-	my $ratio_combx=gen_combobox_object ($self,${graph_id},"ratio",$content,$ratios[0],'ref',2);
-	
-	@color= ("my_color0") if ((scalar @color) ==0);
-	@legend_keys=("-")  if ((scalar @legend_keys) ==0);
-
-
-	my $ymax=10;
-	my $ratio = $self->object_get_attribute ($graph_id,"ratio");
-	
-	
-	my @x;
-	if (defined $ratio){
-		
-		foreach my $sample (@samples){
-			my $ref=$self->object_get_attribute ($sample,"$result_name");
-			if(defined $ref){
-				@x=get_uniq_keys($ref->{$ratio},@x);
-			}
-		}
-		my $i=1;
-		foreach my $sample (@samples){
-			my @y;
-			my $ref=$self->object_get_attribute ($sample,"$result_name");
-			if(defined $ref){
-				foreach my $v (@x){
-					my $w=$ref->{$ratio}->{$v};
-					push(@y,$w);
-					if (defined $w){$ymax=$w+1 if($w>$ymax);}
-				}
-				$results[$i]=\@y if(scalar @x);
-				$i++;
-			}
-		}
-		
-		
-		
-		
-	}
-	
-	$results[0]=\@x if(scalar @x);
-	
-	$i=1;
-	
-	# all results which is larger than ymax will be changed to ymax,
-	$i=0;
-	
-	#foreach my $sample (@samples){
-		#$i++;
-		#for (my $j=1;$j<=$s; $j++) {
-		#	$results[$i][$j]=($results[$i][$j]>$max_y)? $max_y: $results[$i][$j] if (defined $results[$i][$j]);
-		#}	
-	#}
-	
-	
-	my $graphs_info;
-	foreach my $d ( @ginfo){
-		$graphs_info->{$d->{param_name}}=$self->object_get_attribute( "${graph_id}_param"    ,$d->{param_name});
-		if(!defined $graphs_info->{$d->{param_name}}){
-			$graphs_info->{$d->{param_name}}= $d->{default_val}; 
-			$self->object_add_attribute( "${graph_id}_param"    ,$d->{param_name},$d->{default_val} );
-		}
-	}
-	
-	my $graph_w=$width*$image_scale;
-	my $graph_h=$hight*$image_scale;
-	my $graph = new GD::Graph::bars3d($graph_w, $graph_h);
-	my $dim = $self->object_get_attribute (${graph_id},"dimension");
-	#my $dir = $self->object_get_attribute ($graph_name,"direction"); 
-	my $over= ($dim eq "2D")? 0 : 1;
-	$graph->set(
-	    overwrite => $over,
-	    x_label => $graphs_info->{X_Title},
-	    y_label => $graphs_info->{Y_Title},
-	    title   => $graphs_info->{G_Title},
-	    y_max_value => $ymax,
-	    y_tick_number => 18,
-	    y_label_skip => 2,
-	    x_label_skip => 1,
-	    x_all_ticks => 1,
-	    x_labels_vertical => 1,
-	    box_axis => 0,
-	    y_long_ticks => 1,
-	    legend_placement => $graphs_info->{legend_placement},
-		dclrs=>\@color,
-		y_number_format=>"%.1f",
-		
-		transparent       => '0',
-	   	bgclr             => 'white',
-	   	boxclr            => 'white',
-	   	fgclr             => 'black',
-		textclr		  => 'black',
-		labelclr	  => 'black',
-		axislabelclr	  => 'black',
-		legendclr	  =>  'black',
-	    #cycle_clrs        => '1',
-		
-		 # Draw bars with width 3 pixels
+#print "${graph_name}_${dir}_result\n";
+        my @ratios;
+        my @color;
+        my $min_y=200;
+        my $i=0;
+        my @samples =$self->object_get_attribute_order("samples");
+        @samples = ('no_name') if (scalar @samples == 0);
+        foreach my $sample (@samples){
+            my $color_num=$self->object_get_attribute($sample,"color");
+            my $l_name= $self->object_get_attribute($sample,"line_name");
+            #push(@color, "my_color$color_num");
+            my $ref=$self->object_get_attribute ($sample,$result_name);
+            if(defined $ref){
+                $i++;
+                @ratios=get_uniq_keys($ref,@ratios);
+                $color_num=$i+1 if(!defined $color_num);
+                push(@color, "my_color$color_num");
+                $legend_keys[$i-1]= (defined $l_name)? $l_name : $sample;
+            }
+        }#for
+    $content = join(",", @ratios);
+    my $ratio_combx=gen_combobox_object ($self,${graph_id},"ratio",$content,$ratios[0],'ref',2);
+    @color= ("my_color0") if ((scalar @color) ==0);
+    @legend_keys=("-")  if ((scalar @legend_keys) ==0);
+    my $ymax=10;
+    my $ratio = $self->object_get_attribute ($graph_id,"ratio");
+    my @x;
+    if (defined $ratio){
+        foreach my $sample (@samples){
+            my $ref=$self->object_get_attribute ($sample,"$result_name");
+            if(defined $ref){
+                @x=get_uniq_keys($ref->{$ratio},@x);
+            }
+        }
+        my $i=1;
+        foreach my $sample (@samples){
+            my @y;
+            my $ref=$self->object_get_attribute ($sample,"$result_name");
+            if(defined $ref){
+                foreach my $v (@x){
+                    my $w=$ref->{$ratio}->{$v};
+                    push(@y,$w);
+                    if (defined $w){$ymax=$w+1 if($w>$ymax);}
+                }
+                $results[$i]=\@y if(scalar @x);
+                $i++;
+            }
+        }
+    }
+    $results[0]=\@x if(scalar @x);
+    $i=1;
+    # all results which is larger than ymax will be changed to ymax,
+    $i=0;
+    #foreach my $sample (@samples){
+        #$i++;
+        #for (my $j=1;$j<=$s; $j++) {
+        #    $results[$i][$j]=($results[$i][$j]>$max_y)? $max_y: $results[$i][$j] if (defined $results[$i][$j]);
+        #}
+    #}
+    my $graphs_info;
+    foreach my $d ( @ginfo){
+        $graphs_info->{$d->{param_name}}=$self->object_get_attribute( "${graph_id}_param"    ,$d->{param_name});
+        if(!defined $graphs_info->{$d->{param_name}}){
+            $graphs_info->{$d->{param_name}}= $d->{default_val};
+            $self->object_add_attribute( "${graph_id}_param"    ,$d->{param_name},$d->{default_val} );
+        }
+    }
+    my $graph_w=$width*$image_scale;
+    my $graph_h=$hight*$image_scale;
+    my $graph = new GD::Graph::bars3d($graph_w, $graph_h);
+    my $dim = $self->object_get_attribute (${graph_id},"dimension");
+    #my $dir = $self->object_get_attribute ($graph_name,"direction");
+    my $over= ($dim eq "2D")? 0 : 1;
+    $graph->set(
+        overwrite => $over,
+        x_label => $graphs_info->{X_Title},
+        y_label => $graphs_info->{Y_Title},
+        title   => $graphs_info->{G_Title},
+        y_max_value => $ymax,
+        y_tick_number => 18,
+        y_label_skip => 2,
+        x_label_skip => 1,
+        x_all_ticks => 1,
+        x_labels_vertical => 1,
+        box_axis => 0,
+        y_long_ticks => 1,
+        legend_placement => $graphs_info->{legend_placement},
+        dclrs=>\@color,
+        y_number_format=>"%.1f",
+        transparent       => '0',
+        bgclr             => 'white',
+        boxclr            => 'white',
+        fgclr             => 'black',
+        textclr          => 'black',
+        labelclr      => 'black',
+        axislabelclr      => 'black',
+        legendclr      =>  'black',
+        #cycle_clrs        => '1',
+        # Draw bars with width 3 pixels
     bar_width   => 3,
     # Separate the bars with 4 pixels
     bar_spacing => 10,
@@ -527,672 +397,493 @@ sub gen_3D_bar{
     # Show values on top of each bar
     #show_values => 1,
     );
-    
-   
-	$graph->set_legend(@legend_keys);
-	
-	my $font;
-	
-	$font=  $self->object_get_attribute( "${graph_id}_param"    ,'label_font');
-	$graph->set_x_label_font(GD::Font->$font);
-  	$graph->set_y_label_font(GD::Font->$font);
-	$font=  $self->object_get_attribute( "${graph_id}_param"    ,'legend_font');
-	$graph->set_legend_font(GD::Font->$font);
-
-	$font=  $self->object_get_attribute( "${graph_id}_param"    ,'x_axis_font');
-  	#$graph->set_values_font(GD::gdGiantFont);
-	$graph->set_x_axis_font(GD::Font->$font);
-	$graph->set_y_axis_font(GD::Font->$font);
-	
-	#@results=reorder_result(@results);
-	
-	my $gd =  $graph->plot( \@results );
-	my $image =open_inline_image($gd->png);
-
-	write_image ($self,$graph_id,$gd);
-	write_image_result	($self,$graph_id,$graph,$result_name,$chart->{type},\@results);
-   
-        
-        
-        
-	my $table = def_table (25, 10, FALSE);
+    $graph->set_legend(@legend_keys);
+    my $font;
+    $font=  $self->object_get_attribute( "${graph_id}_param"    ,'label_font');
+    $graph->set_x_label_font(GD::Font->$font);
+    $graph->set_y_label_font(GD::Font->$font);
+    $font=  $self->object_get_attribute( "${graph_id}_param"    ,'legend_font');
+    $graph->set_legend_font(GD::Font->$font);
+    $font=  $self->object_get_attribute( "${graph_id}_param"    ,'x_axis_font');
+    #$graph->set_values_font(GD::gdGiantFont);
+    $graph->set_x_axis_font(GD::Font->$font);
+    $graph->set_y_axis_font(GD::Font->$font);
+    #@results=reorder_result(@results);
+    my $gd =  $graph->plot( \@results );
+    my $image =open_inline_image($gd->png);
+    write_image ($self,$graph_id,$gd);
+    write_image_result    ($self,$graph_id,$graph,$result_name,$chart->{type},\@results);
+    my $table = def_table (25, 10, FALSE);
     my $filename;
-	my $align= add_frame_to_image($image);
-
-		
-		
-		
-	my $plus = def_image_button('icons/plus.png',undef,TRUE);
-	my $minues = def_image_button('icons/minus.png',undef,TRUE);
-	my $setting = def_image_button('icons/setting.png',undef,TRUE);
-	my $save = def_image_button('icons/save.png',undef,TRUE);
-	my $scale= $self->object_get_attribute("${graph_id}_graph_scale",undef);
-	$scale = 5 if(!defined $scale);
-	$minues -> signal_connect("clicked" => sub{ 
-		$self->object_add_attribute("${graph_id}_graph_scale",undef,$scale*1.05);
-			set_gui_status($self,"ref",1);	
-	});	
-
-	$plus  -> signal_connect("clicked" => sub{ 
-		$self->object_add_attribute("${graph_id}_graph_scale",undef,$scale*0.95) if( $scale>0.5);
-			set_gui_status($self,"ref",5);
-	});	
-
-	$setting -> signal_connect("clicked" => sub{ 
-		get_graph_setting ($self,\@ginfo);
-	});
-	set_tip($setting, "Setting");		
-		
-	$save-> signal_connect("clicked" => sub{ 
-			# my @imags=$graph->export_format();
-			 my @imags=('png');   
-			 save_graph_as ($self,\@imags,$graph_id);
-	});	
-	set_tip($save, "Save graph");
-		
-		
-		
-	$table->attach_defaults ($align , 0, 9, 0, 24);
-	my $row=0;
-	$table->attach ($active_page, 0, 9, 24, 25,'shrink','shrink',2,2);	
-	$table->attach (gen_label_in_center("Injection-Ratio/"), 9, 10, $row, $row+1,'shrink','shrink',2,2); $row++;
-	$table->attach (gen_label_in_center("Task-file index"), 9, 10, $row, $row+1,'shrink','shrink',2,2); $row++;
-	$table->attach ($ratio_combx, 9, 10, $row, $row+1,'shrink','shrink',2,2); $row++;	
-	$table->attach ($dimension, 9, 10, $row, $row+1,'shrink','shrink',2,2); $row++;
-		
-	#$table->attach ($plus , 9, 10, $row, $row+1,'shrink','shrink',2,2); $row++;
-	#$table->attach ($minues, 9, 10, $row, $row+1,'shrink','shrink',2,2); $row++;
-	$table->attach ($setting, 9, 10, $row,  $row+1,'shrink','shrink',2,2); $row++;
-	$table->attach ($save, 9, 10, $row,  $row+1,'shrink','shrink',2,2); $row++;
-		
-	while ($row<10){
-		my $tmp=gen_label_in_left('');
-		$table->attach_defaults ($tmp, 9, 10, $row,  $row+1);$row++;
-	}
-		
-	
-		
+    my $align= add_frame_to_image($image);
+    my $plus = def_image_button('icons/plus.png',undef,TRUE);
+    my $minues = def_image_button('icons/minus.png',undef,TRUE);
+    my $setting = def_image_button('icons/setting.png',undef,TRUE);
+    my $save = def_image_button('icons/save.png',undef,TRUE);
+    my $scale= $self->object_get_attribute("${graph_id}_graph_scale",undef);
+    $scale = 5 if(!defined $scale);
+    $minues -> signal_connect("clicked" => sub{
+        $self->object_add_attribute("${graph_id}_graph_scale",undef,$scale*1.05);
+            set_gui_status($self,"ref",1);
+    });
+    $plus  -> signal_connect("clicked" => sub{
+        $self->object_add_attribute("${graph_id}_graph_scale",undef,$scale*0.95) if( $scale>0.5);
+            set_gui_status($self,"ref",5);
+    });
+    $setting -> signal_connect("clicked" => sub{
+        get_graph_setting ($self,\@ginfo);
+    });
+    set_tip($setting, "Setting");
+    $save-> signal_connect("clicked" => sub{
+            # my @imags=$graph->export_format();
+            my @imags=('png');
+            save_graph_as ($self,\@imags,$graph_id);
+    });
+    set_tip($save, "Save graph");
+    $table->attach_defaults ($align , 0, 9, 0, 24);
+    my $row=0;
+    $table->attach ($active_page, 0, 9, 24, 25,'shrink','shrink',2,2);
+    $table->attach (gen_label_in_center("Injection-Ratio/"), 9, 10, $row, $row+1,'shrink','shrink',2,2); $row++;
+    $table->attach (gen_label_in_center("Task-file index"), 9, 10, $row, $row+1,'shrink','shrink',2,2); $row++;
+    $table->attach ($ratio_combx, 9, 10, $row, $row+1,'shrink','shrink',2,2); $row++;
+    $table->attach ($dimension, 9, 10, $row, $row+1,'shrink','shrink',2,2); $row++;
+    #$table->attach ($plus , 9, 10, $row, $row+1,'shrink','shrink',2,2); $row++;
+    #$table->attach ($minues, 9, 10, $row, $row+1,'shrink','shrink',2,2); $row++;
+    $table->attach ($setting, 9, 10, $row,  $row+1,'shrink','shrink',2,2); $row++;
+    $table->attach ($save, 9, 10, $row,  $row+1,'shrink','shrink',2,2); $row++;
+    while ($row<10){
+        my $tmp=gen_label_in_left('');
+        $table->attach_defaults ($tmp, 9, 10, $row,  $row+1);$row++;
+    }
     return $table;
 }
 
-
-
-
-
-
-
-
-
-
-
-
-
-
 sub gen_2D_line {
-
-	my ($self,$chart,@selects)=@_;	
-	my($width,$hight)=max_win_size();
-	my $page_id= "P$chart->{page_num}";
-	my $graph_id=  $page_id."$chart->{graph_name}";
-	#my $graph_name=$chart->{graph_name};
-	my $result_name= $chart->{result_name};
-	my @x;
-	my @legend_keys;    
-	
-	
-	my @results;
-	$results[0]=[0];
-	$results[1]= [0];
-	my $legend_info="This attribute controls placement of the legend within the graph image. The value is supplied as a two-letter string, where the first letter is placement (a B or an R for bottom or right, respectively) and the second is alignment (L, R, C, T, or B for left, right, center, top, or bottom, respectively). ";
-	
-	my $fontsize="Tiny,Small,MediumBold,Large,Giant";
-
+    my ($self,$chart,@selects)=@_;
+    my($width,$hight)=max_win_size();
+    my $page_id= "P$chart->{page_num}";
+    my $graph_id=  $page_id."$chart->{graph_name}";
+    #my $graph_name=$chart->{graph_name};
+    my $result_name= $chart->{result_name};
+    my @x;
+    my @legend_keys;
+    my @results;
+    $results[0]=[0];
+    $results[1]= [0];
+    my $legend_info="This attribute controls placement of the legend within the graph image. The value is supplied as a two-letter string, where the first letter is placement (a B or an R for bottom or right, respectively) and the second is alignment (L, R, C, T, or B for left, right, center, top, or bottom, respectively). ";
+    my $fontsize="Tiny,Small,MediumBold,Large,Giant";
 my $content=join( ',', @selects);
 my $active_page=gen_combobox_object ($self,$page_id,"active",$content,$selects[0],'ref',2);
-
-
-
 my @ginfo = (
-#{ label=>"Graph Title", param_name=>"G_Title", type=>"Entry", default_val=>undef, content=>undef, info=>undef, param_parent=>"${graph_name}_param"    , ref_delay=>undef },  
-{ label=>"Y Axis Title", param_name=>"Y_Title", type=>"Entry", default_val=>$chart->{"Y_Title"}, content=>undef, info=>undef, param_parent=>"${graph_id}_param"    , ref_delay=>undef },
-  { label=>"X Axis Title", param_name=>"X_Title", type=>"Entry", default_val=>$chart->{"X_Title"}, content=>undef, info=>undef, param_parent=>"${graph_id}_param"    ,ref_delay=>undef },
-  { label=>"legend placement", param_name=>"legend_placement", type=>'Combo-box', default_val=>'BL', content=>"BL,BC,BR,RT,RC,RB", info=>$legend_info, param_parent=>"${graph_id}_param"    , ref_delay=>1},
- 
- { label=>"Y min", param_name=>"Y_MIN", type=>'Spin-button', default_val=>0, content=>"0,1024,1", info=>"Y axis minimum value", param_parent=>"${graph_id}_param"    , ref_delay=> 5},
- { label=>"X min", param_name=>"X_MIN", type=>'Spin-button', default_val=>0, content=>"0,1024,1", info=>"X axis minimum value", param_parent=>"${graph_id}_param"    , ref_delay=> 5},
-{ label=>"X max", param_name=>"X_MAX", type=>'Spin-button', default_val=>100, content=>"0,1024,1", info=>"X axis maximum value", param_parent=>"${graph_id}_param"    , ref_delay=> 5},
- { label=>"Line Width", param_name=>"LINEw", type=>'Spin-button', default_val=>3, content=>"1,20,1", info=>undef, param_parent=>"${graph_id}_param"    , ref_delay=> 5},
-#{ label=>"Y Axis Values", param_name=>"y_value", type=>'Combo-box', default_val=>'Original', content=>"Original,Normalized to 1,Normalized to 100", info=>undef, param_parent=>"${graph_name}_param"    , ref_delay=>1},
-
-{ label=>"legend font size", param_name=>"legend_font", type=>'Combo-box', default_val=>'MediumBold', content=>$fontsize, info=>undef, param_parent=>"{$graph_id}_param"    , ref_delay=>1}, 
-{ label=>"label font size", param_name=>"label_font", type=>'Combo-box', default_val=>'MediumBold', content=>$fontsize, info=>undef, param_parent=>"${graph_id}_param"    , ref_delay=>1},
-  { label=>"label font size", param_name=>"x_axis_font", type=>'Combo-box', default_val=>'MediumBold', content=>$fontsize, info=>undef, param_parent=>"${graph_id}_param"    , ref_delay=>1},
-);	
-
-
-
-
-
-		my @color;
-		my $min_y;#=200;
-		my $i=0;
-		my @samples =$self->object_get_attribute_order("samples");	
-		@samples = ('no_name') if (scalar @samples == 0);
-		foreach my $sample (@samples){
-			my $ref=$self->object_get_attribute ($sample,$result_name);
-			$i++;
-			my $color_num=$self->object_get_attribute($sample,"color");
-			my $l_name= $self->object_get_attribute($sample,"line_name");
-			$legend_keys[$i-1]= (defined $l_name)? $l_name : $sample;
-			$color_num=$i+1 if(!defined $color_num);
-			push(@color, "my_color$color_num");
-			
-			if(defined $ref) {
-				push(@x, sort {$a<=>$b} keys %{$ref});
-					    	
-		    	}
-						
-		}#for
-		
-	my  @x2;
-	@x2 =  uniq(sort {$a<=>$b} @x) if (scalar @x);
-	
-	my  @x1; #remove x values larger than x_max
-	my $x_max= $self->object_get_attribute( "${graph_id}_param"    ,'X_MAX');
-	foreach  my $p (@x2){
-		if(defined $x_max) {push (@x1,$p) if($p<$x_max);}
-		else {push (@x1,$p);}
-	}
-
-	#print "\@x1=@x1\n";
-	if (scalar @x1){
-		$results[0]=\@x1;
-		$i=0;
-		foreach my $sample (@samples){
-			$i++;
-			my $j=0;
-			my $ref=$self->object_get_attribute ($sample,$result_name);
-			if(defined $ref){
-				#print "$i\n";
-				my %line=%$ref;
-				foreach my $k (@x1){
-					$results[$i][$j]=$line{$k};
-					if(defined $line{$k}){
-						$min_y = $line{$k} if (!defined $min_y);
-						$min_y= $line{$k} if ($line{$k}!=0 && $min_y > $line{$k});
-						$j++;
-					}
-				}#$k
-			}#if
-			else {
-				$results[$i][$j]=undef;
-			}					
-		}#$i		
-	}#if
-	
-	$min_y = 200 if (!defined $min_y);
-	my $scale= $self->object_get_attribute("${graph_id}_graph_scale",undef);
-	$scale = 5 if(!defined $scale);
-
-	my $max_y=$min_y* $scale;
-	my $s=scalar @x1;
-	
-	# all results which is larger than ymax will be changed to ymax,
-	$i=0;
-	
-	foreach my $sample (@samples){
-		$i++;
-		for (my $j=1;$j<=$s; $j++) {
-			$results[$i][$j]=($results[$i][$j]>$max_y)? $max_y: $results[$i][$j] if (defined $results[$i][$j]);
-		}	
-	}
-	
-	
-	my $graphs_info;
-	foreach my $d ( @ginfo){
-		$graphs_info->{$d->{param_name}}=$self->object_get_attribute( "${graph_id}_param"    ,$d->{param_name});
-		if(!defined $graphs_info->{$d->{param_name}}){
-			$graphs_info->{$d->{param_name}}= $d->{default_val}; 
-			$self->object_add_attribute( "${graph_id}_param"    ,$d->{param_name},$d->{default_val} );
-		}
-	}
-	
-	my $graph_w=$width/2.5;
-	my $graph_h=$hight/2.5;
-	my $graph = GD::Graph::linespoints->new($graph_w, $graph_h);
-
-	$graph->set (
-            	x_label         => $graphs_info->{X_Title},
-               	y_label         => $graphs_info->{Y_Title},
-               	y_max_value     => $max_y,
-               	y_min_value		=> $graphs_info->{Y_MIN},
-				y_tick_number   => 8,
-               #	x_min_value     => $graphs_info->{X_MIN}, # dosent work?
-               	title           => $graphs_info->{G_Title},
-               	bar_spacing     => 1,
-                shadowclr       => 'dred',
-
-
-		 
-		box_axis       => 0,
-		skip_undef=> 1,
-	   # transparent     => 1,
-	 	transparent       => '0',
-	   	bgclr             => 'white',
-	   	boxclr            => 'white',
-	   	fgclr             => 'black',
-		textclr		  => 'black',
-		labelclr	  => 'black',
-		axislabelclr	  => 'black',
-		legendclr	  =>  'black',
-	    cycle_clrs        => '1',
-		line_width 		=> $graphs_info->{LINEw},
-	#	cycle_clrs		=> 'black',
-		legend_placement => $graphs_info->{legend_placement},
-		dclrs=>\@color,
-		y_number_format=>"%.1f",
-		BACKGROUND=>'black', 
-		
-       		);
-    
-   
-	$graph->set_legend(@legend_keys);
-	
-	
-
-
-	
-
-
-	my $data = GD::Graph::Data->new(\@results) or die GD::Graph::Data->error;
-	$data->make_strict();
-	
+    #{ label=>"Graph Title", param_name=>"G_Title", type=>"Entry", default_val=>undef, content=>undef, info=>undef, param_parent=>"${graph_name}_param"    , ref_delay=>undef },
+    { label=>"Y Axis Title", param_name=>"Y_Title", type=>"Entry", default_val=>$chart->{"Y_Title"}, content=>undef, info=>undef, param_parent=>"${graph_id}_param"    , ref_delay=>undef },
+    { label=>"X Axis Title", param_name=>"X_Title", type=>"Entry", default_val=>$chart->{"X_Title"}, content=>undef, info=>undef, param_parent=>"${graph_id}_param"    ,ref_delay=>undef },
+    { label=>"legend placement", param_name=>"legend_placement", type=>'Combo-box', default_val=>'BL', content=>"BL,BC,BR,RT,RC,RB", info=>$legend_info, param_parent=>"${graph_id}_param"    , ref_delay=>1},
+    { label=>"Y min", param_name=>"Y_MIN", type=>'Spin-button', default_val=>0, content=>"0,1024,1", info=>"Y axis minimum value", param_parent=>"${graph_id}_param"    , ref_delay=> 5},
+    { label=>"X min", param_name=>"X_MIN", type=>'Spin-button', default_val=>0, content=>"0,1024,1", info=>"X axis minimum value", param_parent=>"${graph_id}_param"    , ref_delay=> 5},
+    { label=>"X max", param_name=>"X_MAX", type=>'Spin-button', default_val=>100, content=>"0,1024,1", info=>"X axis maximum value", param_parent=>"${graph_id}_param"    , ref_delay=> 5},
+    { label=>"Line Width", param_name=>"LINEw", type=>'Spin-button', default_val=>3, content=>"1,20,1", info=>undef, param_parent=>"${graph_id}_param"    , ref_delay=> 5},
+    #{ label=>"Y Axis Values", param_name=>"y_value", type=>'Combo-box', default_val=>'Original', content=>"Original,Normalized to 1,Normalized to 100", info=>undef, param_parent=>"${graph_name}_param"    , ref_delay=>1},
+    { label=>"legend font size", param_name=>"legend_font", type=>'Combo-box', default_val=>'MediumBold', content=>$fontsize, info=>undef, param_parent=>"{$graph_id}_param"    , ref_delay=>1},
+    { label=>"label font size", param_name=>"label_font", type=>'Combo-box', default_val=>'MediumBold', content=>$fontsize, info=>undef, param_parent=>"${graph_id}_param"    , ref_delay=>1},
+    { label=>"label font size", param_name=>"x_axis_font", type=>'Combo-box', default_val=>'MediumBold', content=>$fontsize, info=>undef, param_parent=>"${graph_id}_param"    , ref_delay=>1},
+    );
+        my @color;
+        my $min_y;#=200;
+        my $i=0;
+        my @samples =$self->object_get_attribute_order("samples");
+        @samples = ('no_name') if (scalar @samples == 0);
+        foreach my $sample (@samples){
+            my $ref=$self->object_get_attribute ($sample,$result_name);
+            $i++;
+            my $color_num=$self->object_get_attribute($sample,"color");
+            my $l_name= $self->object_get_attribute($sample,"line_name");
+            $legend_keys[$i-1]= (defined $l_name)? $l_name : $sample;
+            $color_num=$i+1 if(!defined $color_num);
+            push(@color, "my_color$color_num");
+            if(defined $ref) {
+                push(@x, sort {$a<=>$b} keys %{$ref});
+                }
+        }#for
+    my  @x2;
+    @x2 =  uniq(sort {$a<=>$b} @x) if (scalar @x);
+    my  @x1; #remove x values larger than x_max
+    my $x_max= $self->object_get_attribute( "${graph_id}_param"    ,'X_MAX');
+    foreach  my $p (@x2){
+        if(defined $x_max) {push (@x1,$p) if($p<$x_max);}
+        else {push (@x1,$p);}
+    }
+    #print "\@x1=@x1\n";
+    if (scalar @x1){
+        $results[0]=\@x1;
+        $i=0;
+        foreach my $sample (@samples){
+            $i++;
+            my $j=0;
+            my $ref=$self->object_get_attribute ($sample,$result_name);
+            if(defined $ref){
+                #print "$i\n";
+                my %line=%$ref;
+                foreach my $k (@x1){
+                    $results[$i][$j]=$line{$k};
+                    if(defined $line{$k}){
+                        $min_y = $line{$k} if (!defined $min_y);
+                        $min_y= $line{$k} if ($line{$k}!=0 && $min_y > $line{$k});
+                        $j++;
+                    }
+                }#$k
+            }#if
+            else {
+                $results[$i][$j]=undef;
+            }
+        }#$i
+    }#if
+    $min_y = 200 if (!defined $min_y);
+    my $scale= $self->object_get_attribute("${graph_id}_graph_scale",undef);
+    $scale = 5 if(!defined $scale);
+    my $max_y=$min_y* $scale;
+    my $s=scalar @x1;
+    # all results which is larger than ymax will be changed to ymax,
+    $i=0;
+    foreach my $sample (@samples){
+        $i++;
+        for (my $j=1;$j<=$s; $j++) {
+            $results[$i][$j]=($results[$i][$j]>$max_y)? $max_y: $results[$i][$j] if (defined $results[$i][$j]);
+        }
+    }
+    my $graphs_info;
+    foreach my $d ( @ginfo){
+        $graphs_info->{$d->{param_name}}=$self->object_get_attribute( "${graph_id}_param"    ,$d->{param_name});
+        if(!defined $graphs_info->{$d->{param_name}}){
+            $graphs_info->{$d->{param_name}}= $d->{default_val};
+            $self->object_add_attribute( "${graph_id}_param"    ,$d->{param_name},$d->{default_val} );
+        }
+    }
+    my $graph_w=$width/2.5;
+    my $graph_h=$hight/2.5;
+    my $graph = GD::Graph::linespoints->new($graph_w, $graph_h);
+    $graph->set (
+        x_label         => $graphs_info->{X_Title},
+        y_label         => $graphs_info->{Y_Title},
+        y_max_value     => $max_y,
+        y_min_value        => $graphs_info->{Y_MIN},
+        y_tick_number   => 8,
+        # x_min_value     => $graphs_info->{X_MIN}, # dosent work?
+        title           => $graphs_info->{G_Title},
+        bar_spacing     => 1,
+        shadowclr       => 'dred',
+        box_axis       => 0,
+        skip_undef=> 1,
+        # transparent     => 1,
+        transparent       => '0',
+        bgclr             => 'white',
+        boxclr            => 'white',
+        fgclr             => 'black',
+        textclr          => 'black',
+        labelclr      => 'black',
+        axislabelclr      => 'black',
+        legendclr      =>  'black',
+        cycle_clrs        => '1',
+        line_width         => $graphs_info->{LINEw},
+        #cycle_clrs        => 'black',
+        legend_placement => $graphs_info->{legend_placement},
+        dclrs=>\@color,
+        y_number_format=>"%.1f",
+        BACKGROUND=>'black',
+        );
+    $graph->set_legend(@legend_keys);
+    my $data = GD::Graph::Data->new(\@results) or die GD::Graph::Data->error;
+    $data->make_strict();
     my $image = my_get_image($self,$graph,$data,$graph_id,$result_name,$chart->{type});
-        
-	
-        
-      # print  Data::Dumper->Dump ([\@results],['ttt']); 
-        
-        
-        
-        
+        # print  Data::Dumper->Dump ([\@results],['ttt']);
         my $table = def_table (25, 10, FALSE);
-        
-           
-		
-		my $filename;
-		
-		my   $align = add_frame_to_image($image);
-		
-		
-		my $plus = def_image_button('icons/plus.png',undef,TRUE);
-		my $minues = def_image_button('icons/minus.png',undef,TRUE);
-		my $setting = def_image_button('icons/setting.png',undef,TRUE);
-		my $save = def_image_button('icons/save.png',undef,TRUE);
-		
-
-		$minues -> signal_connect("clicked" => sub{ 
-			$scale*=1.05;
-			$self->object_add_attribute("${graph_id}_graph_scale",undef,$scale);
-			set_gui_status($self,"ref",5);	
-		});
-		set_tip($minues, "Zoom out");	
-
-		$plus  -> signal_connect("clicked" => sub{ 
-			$scale*=0.95  if( $scale>0.5);
-			$self->object_add_attribute("${graph_id}_graph_scale",undef,$scale); 
-			set_gui_status($self,"ref",5);
-		});
-		set_tip($plus, "Zoom in");
-
-		$setting -> signal_connect("clicked" => sub{ 
-			get_graph_setting ($self,\@ginfo);
-		});	
-		set_tip($setting, "Setting");			
-
-		$save-> signal_connect("clicked" => sub{ 
-			# my $G = $graph->{graph};
-			# my @imags=$G->export_format(); 
-			my @imags=('png'); 
-			save_graph_as ($self,\@imags,$graph_id);
-		});	
-		set_tip($save, "Save graph");
-		
-		
-		
-		$table->attach_defaults ($align , 0, 9, 0, 24);
-		my $row=0;
-		$table->attach ($active_page, 0, 9, 24, 25,'shrink','shrink',2,2);# $row++;
-		$table->attach ($plus , 9, 10, $row, $row+1,'shrink','shrink',2,2); $row++;
-		$table->attach ($minues, 9, 10, $row, $row+1,'shrink','shrink',2,2); $row++;
-		$table->attach ($setting, 9, 10, $row,  $row+1,'shrink','shrink',2,2); $row++;
-		$table->attach ($save, 9, 10, $row,  $row+1,'shrink','shrink',2,2); $row++;
-		while ($row<10){
-			
-			my $tmp=gen_label_in_left('');
-			$table->attach_defaults ($tmp, 9, 10, $row,  $row+1);$row++;
-		}
-		
+        my $filename;
+        my   $align = add_frame_to_image($image);
+        my $plus = def_image_button('icons/plus.png',undef,TRUE);
+        my $minues = def_image_button('icons/minus.png',undef,TRUE);
+        my $setting = def_image_button('icons/setting.png',undef,TRUE);
+        my $save = def_image_button('icons/save.png',undef,TRUE);
+        $minues -> signal_connect("clicked" => sub{
+            $scale*=1.05;
+            $self->object_add_attribute("${graph_id}_graph_scale",undef,$scale);
+            set_gui_status($self,"ref",5);
+        });
+        set_tip($minues, "Zoom out");
+        $plus  -> signal_connect("clicked" => sub{
+            $scale*=0.95  if( $scale>0.5);
+            $self->object_add_attribute("${graph_id}_graph_scale",undef,$scale);
+            set_gui_status($self,"ref",5);
+        });
+        set_tip($plus, "Zoom in");
+        $setting -> signal_connect("clicked" => sub{
+            get_graph_setting ($self,\@ginfo);
+        });
+        set_tip($setting, "Setting");
+        $save-> signal_connect("clicked" => sub{
+            # my $G = $graph->{graph};
+            # my @imags=$G->export_format();
+            my @imags=('png');
+            save_graph_as ($self,\@imags,$graph_id);
+        });
+        set_tip($save, "Save graph");
+        $table->attach_defaults ($align , 0, 9, 0, 24);
+        my $row=0;
+        $table->attach ($active_page, 0, 9, 24, 25,'shrink','shrink',2,2);# $row++;
+        $table->attach ($plus , 9, 10, $row, $row+1,'shrink','shrink',2,2); $row++;
+        $table->attach ($minues, 9, 10, $row, $row+1,'shrink','shrink',2,2); $row++;
+        $table->attach ($setting, 9, 10, $row,  $row+1,'shrink','shrink',2,2); $row++;
+        $table->attach ($save, 9, 10, $row,  $row+1,'shrink','shrink',2,2); $row++;
+        while ($row<10){
+            my $tmp=gen_label_in_left('');
+            $table->attach_defaults ($tmp, 9, 10, $row,  $row+1);$row++;
+        }
         return $table;
-
 }
 
-
 ##############
-#	save_graph_as
+#    save_graph_as
 ##############
-
 sub save_graph_as {
-	my ($self,$ref,$graph_name)=@_;
-	
-	my $file;
-	my $title ='Save as';
-	my @extensions=@$ref;
-	my $open_in=undef;
-	my $dialog=save_file_dialog  ($title, @extensions);
-
-	$dialog->set_current_folder ($open_in) if(defined  $open_in);
-		
-		
-	if ( "ok" eq $dialog->run ) {
-	    	$file = $dialog->get_filename;
-			my $ext = $dialog->get_filter;
-			$ext=$ext->get_name;
-			my ($name,$path,$suffix) = fileparse("$file",qr"\..[^.]*$");
-			$file = ($suffix eq ".$ext" )? $file : "$file.$ext";
-			
-			$self->object_add_attribute("graph_save","name",$file);
-			$self->object_add_attribute("graph_save","extension",$ext);
-			$self->object_add_attribute("graph_save","save",1);
-			$self->object_add_attribute("graph_save","save_result",1);
-			$self->object_add_attribute("graph_save","graph_name",$graph_name);
-			set_gui_status($self,"ref",1);
-					
-	}
-	$dialog->destroy;
+    my ($self,$ref,$graph_name)=@_;
+    my $file;
+    my $title ='Save as';
+    my @extensions=@$ref;
+    my $open_in=undef;
+    my $dialog=save_file_dialog  ($title, @extensions);
+    $dialog->set_current_folder ($open_in) if(defined  $open_in);
+    if ( "ok" eq $dialog->run ) {
+            $file = $dialog->get_filename;
+            my $ext = $dialog->get_filter;
+            $ext=$ext->get_name;
+            my ($name,$path,$suffix) = fileparse("$file",qr"\..[^.]*$");
+            $file = ($suffix eq ".$ext" )? $file : "$file.$ext";
+            $self->object_add_attribute("graph_save","name",$file);
+            $self->object_add_attribute("graph_save","extension",$ext);
+            $self->object_add_attribute("graph_save","save",1);
+            $self->object_add_attribute("graph_save","save_result",1);
+            $self->object_add_attribute("graph_save","graph_name",$graph_name);
+            set_gui_status($self,"ref",1);
+    }
+    $dialog->destroy;
 }
 
-
-
 sub my_get_image {
-	my ($self,$exgraph, $data, $graph_name, $result_name,$charttype) = @_;
-	$exgraph->{graphdata} = $data;
-	my $graph = $exgraph;#->{graph};
-	my $font;
-	
-	$font=  $self->object_get_attribute( "${graph_name}_param"    ,'label_font');
-	$graph->set_x_label_font(GD::Font->$font);
-  	$graph->set_y_label_font(GD::Font->$font);
-	$font=  $self->object_get_attribute( "${graph_name}_param"    ,'legend_font');
-	$graph->set_legend_font(GD::Font->$font);
-
-	$font=  $self->object_get_attribute( "${graph_name}_param"    ,'x_axis_font');
-  	#$graph->set_values_font(GD::gdGiantFont);
-	$graph->set_x_axis_font(GD::Font->$font);
-	$graph->set_y_axis_font(GD::Font->$font);
-
-	my $gd2=$graph->plot($data) or warn $graph->error;
-	
-	
-	
-	#cut the upper side of the image to remove the straight line created by changing large results to ymax       
-	
-	my $gd1=  GD::Image->new($gd2->getBounds);
-	my $white= $gd1->colorAllocate(255,255,254);
-	my ($x,$h)=$gd2->getBounds;
-	$gd1->transparent($white);
-	$gd1->copy( $gd2, 0, 0, 0, ,$h*0.05, $x ,$h*.95 );
-	
-	write_image ($self,$graph_name,$gd1);
-	write_image_result	($self,$graph_name,$graph,$result_name,$charttype);	
-
-	my $image  =open_inline_image($gd1->png);
-	return $image;
-	
+    my ($self,$exgraph, $data, $graph_name, $result_name,$charttype) = @_;
+    $exgraph->{graphdata} = $data;
+    my $graph = $exgraph;#->{graph};
+    my $font;
+    $font=  $self->object_get_attribute( "${graph_name}_param"    ,'label_font');
+    $graph->set_x_label_font(GD::Font->$font);
+    $graph->set_y_label_font(GD::Font->$font);
+    $font=  $self->object_get_attribute( "${graph_name}_param"    ,'legend_font');
+    $graph->set_legend_font(GD::Font->$font);
+    $font=  $self->object_get_attribute( "${graph_name}_param"    ,'x_axis_font');
+    #$graph->set_values_font(GD::gdGiantFont);
+    $graph->set_x_axis_font(GD::Font->$font);
+    $graph->set_y_axis_font(GD::Font->$font);
+    my $gd2=$graph->plot($data) or warn $graph->error;
+    #cut the upper side of the image to remove the straight line created by changing large results to ymax
+    my $gd1=  GD::Image->new($gd2->getBounds);
+    my $white= $gd1->colorAllocate(255,255,254);
+    my ($x,$h)=$gd2->getBounds;
+    $gd1->transparent($white);
+    $gd1->copy( $gd2, 0, 0, 0, ,$h*0.05, $x ,$h*.95 );
+    write_image ($self,$graph_name,$gd1);
+    write_image_result    ($self,$graph_name,$graph,$result_name,$charttype);
+    my $image  =open_inline_image($gd1->png);
+    return $image;
 }
 
-
-
 ############
-#	get_graph_setting
+#    get_graph_setting
 ###########
-
 sub get_graph_setting {
-	my ($self,$ref)=@_;
-	my $window=def_popwin_size(33,33,'Graph Setting','percent');
-	my $table = def_table(10, 2, FALSE);
-	my $row=0;
-
-
-my @data=@$ref;
-my $coltmp;
-foreach my $d (@data) {
-	#$row=noc_param_widget ($self, $d->{label}, $d->{param_name}, $d->{default_val}, $d->{type}, $d->{content}, $d->{info}, $table,$row,      1, $d->{param_parent}, $d->{ref_delay});
-    ($row,$coltmp)=add_param_widget ($self, $d->{label}, $d->{param_name}, $d->{default_val}, $d->{type}, $d->{content}, $d->{info}, $table,$row,undef,1, $d->{param_parent}, $d->{ref_delay} ,undef,undef);
+    my ($self,$ref)=@_;
+    my $window=def_popwin_size(33,33,'Graph Setting','percent');
+    my $table = def_table(10, 2, FALSE);
+    my $row=0;
+    my @data=@$ref;
+    my $coltmp;
+    foreach my $d (@data) {
+        #$row=noc_param_widget ($self, $d->{label}, $d->{param_name}, $d->{default_val}, $d->{type}, $d->{content}, $d->{info}, $table,$row,      1, $d->{param_parent}, $d->{ref_delay});
+        ($row,$coltmp)=add_param_widget ($self, $d->{label}, $d->{param_name}, $d->{default_val}, $d->{type}, $d->{content}, $d->{info}, $table,$row,undef,1, $d->{param_parent}, $d->{ref_delay} ,undef,undef);
+    }
+    my $scrolled_win = add_widget_to_scrolled_win($table);
+    my $ok = def_image_button('icons/select.png',' OK ');
+    my $mtable = def_table(10, 1, FALSE);
+    $mtable->attach_defaults($scrolled_win,0,1,0,9);
+    $mtable->attach($ok,0,1,9,10,'shrink','shrink',2,2);
+    $window->add ($mtable);
+    $window->show_all();
+    $ok-> signal_connect("clicked" => sub{
+        $window->destroy;
+        set_gui_status($self,"ref",1);
+    });
 }
-	
-	
-	
-	
-	my $scrolled_win = add_widget_to_scrolled_win($table);
-	my $ok = def_image_button('icons/select.png',' OK ');
-	
-	
-	my $mtable = def_table(10, 1, FALSE);
-	$mtable->attach_defaults($scrolled_win,0,1,0,9);
-	$mtable->attach($ok,0,1,9,10,'shrink','shrink',2,2);
-	$window->add ($mtable);
-	$window->show_all();
-	
-	$ok-> signal_connect("clicked" => sub{ 
-		$window->destroy;
-		set_gui_status($self,"ref",1);
-	});
-
-
-
-}
-
-
 
 sub write_image {
-	my ($self,$graph_name,$image)=@_;
-	my $save=$self->object_get_attribute("graph_save","save");	
-	
-	my $active_graph=$self->object_get_attribute("graph_save","graph_name");
-	$save=0 if (!defined $save);
-	$active_graph = 0 if(!defined $active_graph);
-	
-	if ($save ==1 && $active_graph eq $graph_name){
-		my $file=$self->object_get_attribute("graph_save","name");
-		my $ext=$self->object_get_attribute("graph_save","extension");
-		$self->object_add_attribute("graph_save","save",0);
-
-		#image
-		open(my $out, '>', $file);
-		if (tell $out )
-		{
-			warn "Cannot open '$file' to write: $!";  
-		}else
-		{	
-			#my @extens=$graph->export_format();
-			binmode $out;
-			print $out $image->$ext;# if($ext eq 'png');
-			#print $out  $gd1->gif  if($ext eq 'gif');
-			close $out;
-		}
-	}
-	
+    my ($self,$graph_name,$image)=@_;
+    my $save=$self->object_get_attribute("graph_save","save");
+    my $active_graph=$self->object_get_attribute("graph_save","graph_name");
+    $save=0 if (!defined $save);
+    $active_graph = 0 if(!defined $active_graph);
+    if ($save ==1 && $active_graph eq $graph_name){
+        my $file=$self->object_get_attribute("graph_save","name");
+        my $ext=$self->object_get_attribute("graph_save","extension");
+        $self->object_add_attribute("graph_save","save",0);
+        #image
+        open(my $out, '>', $file);
+        if (tell $out )
+        {
+            warn "Cannot open '$file' to write: $!";
+        }else
+        {
+            #my @extens=$graph->export_format();
+            binmode $out;
+            print $out $image->$ext;# if($ext eq 'png');
+            #print $out  $gd1->gif  if($ext eq 'gif');
+            close $out;
+        }
+    }
 }
 
-
 sub write_image_result {
-	my ($self,$graph_name,$graph,$result_name,$charttype,$result_ref)=@_;
-	my $save=$self->object_get_attribute("graph_save","save_result");
-	my $active_graph=$self->object_get_attribute("graph_save","graph_name");
-	$save=0 if (!defined $save);
-	$active_graph = 0 if(!defined $active_graph);	
-		
-	if ($save ==1 && $active_graph eq $graph_name){
-		my $file=$self->object_get_attribute("graph_save","name");
-		$self->object_add_attribute("graph_save","save_result",0);
-		write_graph_results_in_file($self,"$file.txt",$result_name,$result_ref,$charttype);	
-	}
+    my ($self,$graph_name,$graph,$result_name,$charttype,$result_ref)=@_;
+    my $save=$self->object_get_attribute("graph_save","save_result");
+    my $active_graph=$self->object_get_attribute("graph_save","graph_name");
+    $save=0 if (!defined $save);
+    $active_graph = 0 if(!defined $active_graph);
+    if ($save ==1 && $active_graph eq $graph_name){
+        my $file=$self->object_get_attribute("graph_save","name");
+        $self->object_add_attribute("graph_save","save_result",0);
+        write_graph_results_in_file($self,"$file.txt",$result_name,$result_ref,$charttype);
+    }
 }
 
 sub write_graph_results_in_file{
-	my ($self,$file_name,$result_name,$result_ref,$charttype)=@_;	
-	
-	open( my $out, '>', $file_name);
-	if (tell $out )
-	{
-		warn "Cannot open $file_name to write: $!";  
-		return;
-	}
-	else
-	{	
-		if($charttype eq '2D_line'){			
-			write_2d_graph_results($self,$out,$result_name);	
-		} else{
-			write_3d_graph_results($self,$out,$result_ref);	
-		}
-		close $out;
-	}		 
-}	
-
+    my ($self,$file_name,$result_name,$result_ref,$charttype)=@_;
+    open( my $out, '>', $file_name);
+    if (tell $out )
+    {
+        warn "Cannot open $file_name to write: $!";
+        return;
+    }
+    else
+    {
+        if($charttype eq '2D_line'){
+            write_2d_graph_results($self,$out,$result_name);
+        } else{
+            write_3d_graph_results($self,$out,$result_ref);
+        }
+        close $out;
+    }
+}
 
 sub write_2d_graph_results{
-	my ($self,$out,$result_name)=@_;	
-	my @samples =$self->object_get_attribute_order("samples");
-	foreach my $sample (@samples){
-		my $l_name= $self->object_get_attribute($sample,"line_name");
-		my $ref=$self->object_get_attribute ($sample,$result_name);
-		my @x;
-		if(defined $ref) {
-			print $out "$l_name\n";
-			foreach my $x (sort {$a<=>$b} keys %{$ref}) {
-				my $y=$ref->{$x};
-				print $out "\t$x , $y\n";
-			}
-			print $out "\n\n";
-		}				
-	}#for
-}	
-
+    my ($self,$out,$result_name)=@_;
+    my @samples =$self->object_get_attribute_order("samples");
+    foreach my $sample (@samples){
+        my $l_name= $self->object_get_attribute($sample,"line_name");
+        my $ref=$self->object_get_attribute ($sample,$result_name);
+        my @x;
+        if(defined $ref) {
+            print $out "$l_name\n";
+            foreach my $x (sort {$a<=>$b} keys %{$ref}) {
+                my $y=$ref->{$x};
+                print $out "\t$x , $y\n";
+            }
+            print $out "\n\n";
+        }
+    }#for
+}
 
 sub write_3d_graph_results{
-	my ($self,$out,$result_ref)=@_;
-	
-	my @r=@{$result_ref};
-	
-	my @samples =$self->object_get_attribute_order("samples");
-	my $i=0;
-	if(defined $r[$i]){
-		my @k=@{$r[$i]};
-		print $out "@k\n\n";
-	}
-				
-	foreach my $sample (@samples){
-		$i++;
-		my $l_name= $self->object_get_attribute($sample,"line_name");
-		print $out "$l_name:\n";
-		if(defined $r[$i]){
-			my @k=@{$r[$i]};
-			print $out "@k\n\n";
-		}	
-	}
-}				
-
-
-
- ################
- # get_color_window
- ###############
- 
- sub get_color_window{
-	 my ($self,$atrebute1,$atrebute2)=@_;     
-	 my $window=def_popwin_size(40,40,"Select line color",'percent');
-	 my ($r,$c)=(4,8);	 
-	 my $table= def_table(5,6,TRUE);
-	 for (my $col=0;$col<$c;$col++){
-		  for (my $row=0;$row<$r;$row++){
-			my $color_num=$row*$c+$col;
-			my $color=def_colored_button("    ",$color_num);
-			$table->attach_defaults ($color, $col, $col+1, $row, $row+1); 
-			$color->signal_connect("clicked"=> sub{
-				$self->object_add_attribute($atrebute1,$atrebute2,$color_num);
-				#print "$self->object_add_attribute($atrebute1,$atrebute2,$color_num);\n";
-				set_gui_status($self,"ref",1);
-				$window->destroy;
-			});
-		 }
-	 }
-	 
-	 $window->add($table);
-	
-	$window->show_all();
-
+    my ($self,$out,$result_ref)=@_;
+    my @r=@{$result_ref};
+    my @samples =$self->object_get_attribute_order("samples");
+    my $i=0;
+    if(defined $r[$i]){
+        my @k=@{$r[$i]};
+        print $out "@k\n\n";
+    }
+    foreach my $sample (@samples){
+        $i++;
+        my $l_name= $self->object_get_attribute($sample,"line_name");
+        print $out "$l_name:\n";
+        if(defined $r[$i]){
+            my @k=@{$r[$i]};
+            print $out "@k\n\n";
+        }
+    }
 }
 
+################
+# get_color_window
+###############
+sub get_color_window{
+    my ($self,$atrebute1,$atrebute2)=@_;
+    my $window=def_popwin_size(40,40,"Select line color",'percent');
+    my ($r,$c)=(4,8);
+    my $table= def_table(5,6,TRUE);
+    for (my $col=0;$col<$c;$col++){
+        for (my $row=0;$row<$r;$row++){
+            my $color_num=$row*$c+$col;
+            my $color=def_colored_button("    ",$color_num);
+            $table->attach_defaults ($color, $col, $col+1, $row, $row+1);
+            $color->signal_connect("clicked"=> sub{
+                $self->object_add_attribute($atrebute1,$atrebute2,$color_num);
+                #print "$self->object_add_attribute($atrebute1,$atrebute2,$color_num);\n";
+                set_gui_status($self,"ref",1);
+                $window->destroy;
+            });
+        }
+    }
+    $window->add($table);
+    $window->show_all();
+}
 
 sub reorder_result{
-	my @results=@_;
-	
-	my @app=(
-	"a0","a1","a2","a3","a4","a5","a6","a7","a8","a9","a10","a11"," "," "," "," ",
-	"b0","b1","b2","b3","b4","b5","b6","b7","b8","b9","b10","b11","b12","b13","b14","b15"," "," "," "," ",
-	"c0","c1","c2","c3","c4","c5","c6","c7","c8","c9","c10","c11"," "," "," "," ",
-	"d0","d1","d2","d3","d4","d5","d6","d7","d8");
-	
-	
-	
-	my %nmap=(
-	"b7" => 0 ,"b9" => 1 ,"b8" => 2 ,"a11"=> 3 ,"b11"=> 4 ,"b12"=> 5 ,"b13"=> 6 ,
-	"b6" => 7 ,"b5" => 8 ,"a10"=> 9 ,"a8" => 10,"a9" => 11,"b14"=> 12,"b10"=> 13,
-	"b3" => 14,"b4" => 15,"a5" => 16,"a7" => 17,"a2" => 18,"d8" => 19,"d0" => 20, 
-	"b2" => 21,"a3" => 22,"a6" => 23,"a0" => 24,"a1" => 25,"d1" => 26,"d2" => 27,
-	"b1" => 28,"b15"=> 29,"c2" => 30,"a4" => 31,"d4" => 32,"d3" => 33,"d5" => 34,
-	"b0" => 35,"c9" => 36,"c8" => 37,"c3" => 38,"d7" => 39,"d6" => 40,"c7" => 41,
-	"c11"=> 42,"c10"=> 43,"c5" => 44,"c4" => 45,"c1" => 46,"c0" => 47,"c6" => 48);
-	
-	my %worst=(
-	"a0" => 0 ,"a8" => 1 ,"b7" => 2 ,"d8"=> 3 ,"b1"=> 4 ,"b5"=> 5 ,"b8"=> 6 ,
-	"a5" => 7 ,"c2" => 8 ,"c10"=> 9 ,"c3" => 10,"c5" => 11,"b12"=> 12,"b3"=> 13,
-	"d1" => 14,"d7" => 15,"c1" => 16,"c7" => 17,"c0" => 18,"c8" => 19,"b10" => 20, 
-	"b15" => 21,"d2" => 22,"c4" => 23,"c6" => 24,"c9" => 25,"d3" => 26,"a4" => 27,
-	"b2" => 28,"b13"=> 29,"d4" => 30,"c11" => 31,"d5" => 32,"a2" => 33,"a10" => 34,
-	"b6" => 35,"b0" => 36,"d0" => 37,"d6" => 38,"a3" => 39,"a9" => 40,"a6" => 41,
-	"b9"=> 42,"b4"=> 43,"b11" => 44,"b14" => 45,"a1" => 46,"a11" => 47,"a7" => 48);
-	
-	my %rnd=(
-	"d3" => 0 ,"d6" => 1 ,"b8" => 2 ,"c10"=> 3 ,"d5" => 4 ,"d8" => 5 ,"a3" => 6 ,
-	"b15"=> 7 ,"a9" => 8 ,"c3" => 9 ,"b12"=> 10,"a4" => 11,"b9" => 12,"b6" => 13,
-	"d2" => 14,"c2" => 15,"b0" => 16,"b13"=> 17,"a5" => 18,"c9" => 19,"a2" => 20, 
-	"c0" => 21,"c7" => 22,"c5" => 23,"b14"=> 24,"b7" => 25,"c4" => 26,"b10"=> 27,
-	"d1" => 28,"c6" => 29,"b11"=> 30,"a10"=> 31,"b1" => 32,"c1" => 33,"b5" => 34,
-	"d7" => 35,"d4" => 36,"a6" => 37,"a11"=> 38,"a7" => 39,"b2" => 40,"c11" => 41,
-	"c8" => 42,"a1" => 43,"a0" => 44,"d0" => 45,"a8" => 46,"b3" => 47,"b4" => 48);
-	
-	my @r;
-	
-	my $tile=0;
-	foreach my $p (@app){
-		
-		
-		#my $l=$nmap{$p};
-		#my $l=$rnd{$p};
-		my $l=$worst{$p};
-		
-		
-		$r[0][$tile]=$p;
-		$r[1][$tile]=(defined $l)? $results[1][$l]: undef;
-		$r[2][$tile]=(defined $l)? $results[2][$l]: undef;
-		$tile++;
-	}
-	
-	
-	
-	return @r;
-}	
-
-1;
+    my @results=@_;
+    my @app=(
+    "a0","a1","a2","a3","a4","a5","a6","a7","a8","a9","a10","a11"," "," "," "," ",
+    "b0","b1","b2","b3","b4","b5","b6","b7","b8","b9","b10","b11","b12","b13","b14","b15"," "," "," "," ",
+    "c0","c1","c2","c3","c4","c5","c6","c7","c8","c9","c10","c11"," "," "," "," ",
+    "d0","d1","d2","d3","d4","d5","d6","d7","d8");
+    my %nmap=(
+    "b7" => 0 ,"b9" => 1 ,"b8" => 2 ,"a11"=> 3 ,"b11"=> 4 ,"b12"=> 5 ,"b13"=> 6 ,
+    "b6" => 7 ,"b5" => 8 ,"a10"=> 9 ,"a8" => 10,"a9" => 11,"b14"=> 12,"b10"=> 13,
+    "b3" => 14,"b4" => 15,"a5" => 16,"a7" => 17,"a2" => 18,"d8" => 19,"d0" => 20,
+    "b2" => 21,"a3" => 22,"a6" => 23,"a0" => 24,"a1" => 25,"d1" => 26,"d2" => 27,
+    "b1" => 28,"b15"=> 29,"c2" => 30,"a4" => 31,"d4" => 32,"d3" => 33,"d5" => 34,
+    "b0" => 35,"c9" => 36,"c8" => 37,"c3" => 38,"d7" => 39,"d6" => 40,"c7" => 41,
+    "c11"=> 42,"c10"=> 43,"c5" => 44,"c4" => 45,"c1" => 46,"c0" => 47,"c6" => 48);
+    my %worst=(
+    "a0" => 0 ,"a8" => 1 ,"b7" => 2 ,"d8"=> 3 ,"b1"=> 4 ,"b5"=> 5 ,"b8"=> 6 ,
+    "a5" => 7 ,"c2" => 8 ,"c10"=> 9 ,"c3" => 10,"c5" => 11,"b12"=> 12,"b3"=> 13,
+    "d1" => 14,"d7" => 15,"c1" => 16,"c7" => 17,"c0" => 18,"c8" => 19,"b10" => 20,
+    "b15" => 21,"d2" => 22,"c4" => 23,"c6" => 24,"c9" => 25,"d3" => 26,"a4" => 27,
+    "b2" => 28,"b13"=> 29,"d4" => 30,"c11" => 31,"d5" => 32,"a2" => 33,"a10" => 34,
+    "b6" => 35,"b0" => 36,"d0" => 37,"d6" => 38,"a3" => 39,"a9" => 40,"a6" => 41,
+    "b9"=> 42,"b4"=> 43,"b11" => 44,"b14" => 45,"a1" => 46,"a11" => 47,"a7" => 48);
+    my %rnd=(
+    "d3" => 0 ,"d6" => 1 ,"b8" => 2 ,"c10"=> 3 ,"d5" => 4 ,"d8" => 5 ,"a3" => 6 ,
+    "b15"=> 7 ,"a9" => 8 ,"c3" => 9 ,"b12"=> 10,"a4" => 11,"b9" => 12,"b6" => 13,
+    "d2" => 14,"c2" => 15,"b0" => 16,"b13"=> 17,"a5" => 18,"c9" => 19,"a2" => 20,
+    "c0" => 21,"c7" => 22,"c5" => 23,"b14"=> 24,"b7" => 25,"c4" => 26,"b10"=> 27,
+    "d1" => 28,"c6" => 29,"b11"=> 30,"a10"=> 31,"b1" => 32,"c1" => 33,"b5" => 34,
+    "d7" => 35,"d4" => 36,"a6" => 37,"a11"=> 38,"a7" => 39,"b2" => 40,"c11" => 41,
+    "c8" => 42,"a1" => 43,"a0" => 44,"d0" => 45,"a8" => 46,"b3" => 47,"b4" => 48);
+    my @r;
+    my $tile=0;
+    foreach my $p (@app){
+        #my $l=$nmap{$p};
+        #my $l=$rnd{$p};
+        my $l=$worst{$p};
+        $r[0][$tile]=$p;
+        $r[1][$tile]=(defined $l)? $results[1][$l]: undef;
+        $r[2][$tile]=(defined $l)? $results[2][$l]: undef;
+        $tile++;
+    }
+    return @r;
+}
+1;
\ No newline at end of file
diff --git a/mpsoc/perl_gui/lib/perl/hdr_file_gen.pl b/mpsoc/perl_gui/lib/perl/hdr_file_gen.pl
index a7b854d..3df6e5c 100755
--- a/mpsoc/perl_gui/lib/perl/hdr_file_gen.pl
+++ b/mpsoc/perl_gui/lib/perl/hdr_file_gen.pl
@@ -1,5 +1,4 @@
 use lib 'lib/perl';
-
 use strict;
 use warnings;
 use FindBin;
@@ -7,187 +6,137 @@
 use soc;
 use ip;
 
-
-
 ##################
 #     header file gen
 ##################
-
-
-
 sub get_instance_global_variable{
-	my ($soc,$id)	= @_;
-	my $module 	=$soc->soc_get_module($id);
-	my $module_name	=$soc->soc_get_module_name($id);
-	my $category 	=$soc->soc_get_category($id);
-	my $inst   	=$soc->soc_get_instance_name($id);
-	my @plugs= $soc->soc_get_all_plugs_of_an_instance($id);
-	my %params= $soc->soc_get_module_param($id);
-	#add two extra variable the instance name and base addresses
-	my $core_id= $soc->object_get_attribute('global_param','CORE_ID');
-	$params{CORE_ID}=(defined $core_id)? $core_id: 0;
-	$params{IP}=$inst;
-	$params{CORE}=$id;
-	foreach my $plug (@plugs){
-		my @nums=$soc->soc_list_plug_nums($id,$plug);
-		foreach my $num (@nums){
-			my ($addr,$base,$end,$name,$connect_id,$connect_socket,$connect_socket_num)=$soc->soc_get_plug($id,$plug,$num);
-			#wishbone slave address
-			if((defined $connect_socket) && ($connect_socket eq 'wb_slave')){
-				#print "$addr,$base,$end,$connect_id,$connect_socket,$connect_socket_num\n";
-				my $base_hex=sprintf("0X%08x", $base);
-				my $end_hex=sprintf("0X%08x", $end);
-				my $val="BASE".$num;
-				$params{$val}=$base_hex;
-		
-			}
-					
-					
-		}
-	}
-	$params{BASE}=$params{BASE0} if(defined $params{BASE0});
-	
-
-	return (\%params);
+    my ($soc,$id)    = @_;
+    my $module     =$soc->soc_get_module($id);
+    my $module_name    =$soc->soc_get_module_name($id);
+    my $category     =$soc->soc_get_category($id);
+    my $inst       =$soc->soc_get_instance_name($id);
+    my @plugs= $soc->soc_get_all_plugs_of_an_instance($id);
+    my %params= $soc->soc_get_module_param($id);
+    #add two extra variable the instance name and base addresses
+    my $core_id= $soc->object_get_attribute('global_param','CORE_ID');
+    $params{CORE_ID}=(defined $core_id)? $core_id: 0;
+    $params{IP}=$inst;
+    $params{CORE}=$id;
+    foreach my $plug (@plugs){
+        my @nums=$soc->soc_list_plug_nums($id,$plug);
+        foreach my $num (@nums){
+            my ($addr,$base,$end,$name,$connect_id,$connect_socket,$connect_socket_num)=$soc->soc_get_plug($id,$plug,$num);
+            #wishbone slave address
+            if((defined $connect_socket) && ($connect_socket eq 'wb_slave')){
+                #print "$addr,$base,$end,$connect_id,$connect_socket,$connect_socket_num\n";
+                my $base_hex=sprintf("0X%08x", $base);
+                my $end_hex=sprintf("0X%08x", $end);
+                my $val="BASE".$num;
+                $params{$val}=$base_hex;
+            }
+        }
+    }
+    $params{BASE}=$params{BASE0} if(defined $params{BASE0});
+    return (\%params);
 }
 
-
 sub replace_golb_var{
-	my ($hdr,$ref)=@_;
-	my %params= %{$ref};
-	foreach my $p (sort keys %params){
-		my $pattern=  '\$\{?' . $p . '(\}|\b)';
-		($hdr=$hdr)=~s/$pattern/$params{$p}/g;
-	}
-	return $hdr;
-
+    my ($hdr,$ref)=@_;
+    my %params= %{$ref};
+    foreach my $p (sort keys %params){
+        my $pattern=  '\$\{?' . $p . '(\}|\b)';
+        ($hdr=$hdr)=~s/$pattern/$params{$p}/g;
+    }
+    return $hdr;
 }
 
-
-
-sub generate_header_file{ 
-	my ($soc,$project_dir,$sw_path,$hw_path,$dir)= @_;
-	my $soc_name=$soc->object_get_attribute('soc_name');
-	$soc_name = uc($soc_name);
-	if(!defined $soc_name){$soc_name='soc'};
-	
-	my $name=$soc->object_get_attribute('soc_name');
-	
-	my @instances=$soc->soc_get_all_instances();
-	my $system_h="#ifndef $soc_name\_SYSTEM_H\n\t#define $soc_name\_SYSTEM_H\n";
-	my $system_c="#include \"$name.h\"\n\n";
-	
-	#add_text_to_string(\$system_h, "\n #include <stdio.h> \n #include <stdlib.h> \n #include \"aemb/core.hh\"");
-
-
-	my $ip = ip->lib_new ();
-	
-	
-	foreach my $id (@instances){
-		my $module 		=$soc->soc_get_module($id);
-		my $module_name	=$soc->soc_get_module_name($id);
-		my $category 	=$soc->soc_get_category($id);
-		my $inst   		=$soc->soc_get_instance_name($id);
-
-		add_text_to_string(\$system_h,"\n \n /*  $inst   */ \n");
-		$system_c = $system_c . "\n \n /*  $inst   */ \n";
-			
-		#$inst=uc($inst);
-		# print base address
-		my @plugs= $soc->soc_get_all_plugs_of_an_instance($id);
-
-
-		my %params= %{get_instance_global_variable($soc,$id)};
-		
-
-		foreach my $plug (@plugs){
-			my @nums=$soc->soc_list_plug_nums($id,$plug);
-			foreach my $num (@nums){
-				my ($addr,$base,$end,$name,$connect_id,$connect_socket,$connect_socket_num)=$soc->soc_get_plug($id,$plug,$num);
-					#intrrupt 
-					if((defined $connect_socket) && ($connect_socket eq 'interrupt_peripheral')){
-						add_text_to_string(\$system_h,"//intrrupt flag location\n");
-						add_text_to_string(\$system_h," #define $inst\_INT (1<<$connect_socket_num)\n") if(scalar (@nums)==1);
-						add_text_to_string(\$system_h," #define $inst\_$num\_INT    (1<<$connect_socket_num)\n") if(scalar (@nums)>1);
-						add_text_to_string(\$system_h," #define $inst\_INT_PIN $connect_socket_num\n") if(scalar (@nums)==1);
-						add_text_to_string(\$system_h," #define $inst\_$num\_INT_PIN    $connect_socket_num\n") if(scalar (@nums)>1);
-					}
-					
-			}
-		}
-		
-		
-		my $hdr_h=$ip->ip_get($category,$module,"system_h");
-		if(defined $hdr_h){
-			$hdr_h=replace_golb_var($hdr_h,\%params);
-			add_text_to_string(\$system_h,"$hdr_h\n");
-		}
-		
-		
-		my $hdr_c=$ip->ip_get($category,$module,"system_c");
-		if(defined $hdr_c){
-			$hdr_c=replace_golb_var($hdr_c,\%params);
-			$system_c=$system_c."$hdr_c\n";
-		}
-		
-
-		# Write Software gen files
-		my @sw_file_gen = $ip->ip_get_list($category,$module,"gen_sw_files");		
-		foreach my $file (@sw_file_gen){
-			if(defined $file ){
-				my ($path,$rename)=split('frename_sep_t',$file);
-				$rename=replace_golb_var($rename,\%params);
-				#read the file content
-				my $content=read_file_cntent($path,$project_dir);
-				$content=replace_golb_var($content,\%params);
-
-				if(defined $rename){			
-					open(FILE,  ">$sw_path/$rename") || die "Can not open: $!";
-					print FILE $content;
-					close(FILE) || die "Error closing file: $!";				
-				}
-			}
-		}
-
-		# Write Hardware gen files
-		my @hw_file_gen = $ip->ip_get_list($category,$module,"gen_hw_files");		
-		foreach my $file (@hw_file_gen){
-			if(defined $file ){
-				my ($path,$rename)=split('frename_sep_t',$file);
-				$rename=replace_golb_var($rename,\%params);
-				#read the file content
-				my $content=read_file_cntent($path,$project_dir);
-				$content=replace_golb_var($content,\%params);
-
-				if(defined $rename){			
-					open(FILE,  ">$hw_path/$rename") || die "Can not open: $!";
-					print FILE $content;
-					close(FILE) || die "Error closing file: $!";			
-				}
-			}
-		}
-
-
-		
-	}
-	
-	add_text_to_string(\$system_h,"#endif\n");
-	
-	#write sytem.h file
-	open(FILE,  ">$sw_path/$name.h") || die "Can not open: $!";
-	print FILE $system_h;
-	close(FILE) || die "Error closing file: $!";
-
-	#write system.c file
-	open(FILE,  ">$sw_path/$name.c") || die "Can not open: $!";
-	print FILE $system_c;
-	close(FILE) || die "Error closing file: $!";		
-	
-	
-		
-
-
+sub generate_header_file{
+    my ($soc,$project_dir,$sw_path,$hw_path,$dir)= @_;
+    my $soc_name=$soc->object_get_attribute('soc_name');
+    $soc_name = uc($soc_name);
+    if(!defined $soc_name){$soc_name='soc'};
+    my $name=$soc->object_get_attribute('soc_name');
+    my @instances=$soc->soc_get_all_instances();
+    my $system_h="#ifndef $soc_name\_SYSTEM_H\n\t#define $soc_name\_SYSTEM_H\n";
+    my $system_c="#include \"$name.h\"\n\n";
+    #add_text_to_string(\$system_h, "\n #include <stdio.h> \n #include <stdlib.h> \n #include \"aemb/core.hh\"");
+    my $ip = ip->lib_new ();
+    foreach my $id (@instances){
+        my $module         =$soc->soc_get_module($id);
+        my $module_name    =$soc->soc_get_module_name($id);
+        my $category     =$soc->soc_get_category($id);
+        my $inst           =$soc->soc_get_instance_name($id);
+        add_text_to_string(\$system_h,"\n \n /*  $inst   */ \n");
+        $system_c = $system_c . "\n \n /*  $inst   */ \n";
+        #$inst=uc($inst);
+        # print base address
+        my @plugs= $soc->soc_get_all_plugs_of_an_instance($id);
+        my %params= %{get_instance_global_variable($soc,$id)};
+        foreach my $plug (@plugs){
+            my @nums=$soc->soc_list_plug_nums($id,$plug);
+            foreach my $num (@nums){
+                my ($addr,$base,$end,$name,$connect_id,$connect_socket,$connect_socket_num)=$soc->soc_get_plug($id,$plug,$num);
+                    #intrrupt
+                    if((defined $connect_socket) && ($connect_socket eq 'interrupt_peripheral')){
+                        add_text_to_string(\$system_h,"//intrrupt flag location\n");
+                        add_text_to_string(\$system_h," #define $inst\_INT (1<<$connect_socket_num)\n") if(scalar (@nums)==1);
+                        add_text_to_string(\$system_h," #define $inst\_$num\_INT    (1<<$connect_socket_num)\n") if(scalar (@nums)>1);
+                        add_text_to_string(\$system_h," #define $inst\_INT_PIN $connect_socket_num\n") if(scalar (@nums)==1);
+                        add_text_to_string(\$system_h," #define $inst\_$num\_INT_PIN    $connect_socket_num\n") if(scalar (@nums)>1);
+                    }
+            }
+        }
+        my $hdr_h=$ip->ip_get($category,$module,"system_h");
+        if(defined $hdr_h){
+            $hdr_h=replace_golb_var($hdr_h,\%params);
+            add_text_to_string(\$system_h,"$hdr_h\n");
+        }
+        my $hdr_c=$ip->ip_get($category,$module,"system_c");
+        if(defined $hdr_c){
+            $hdr_c=replace_golb_var($hdr_c,\%params);
+            $system_c=$system_c."$hdr_c\n";
+        }
+        # Write Software gen files
+        my @sw_file_gen = $ip->ip_get_list($category,$module,"gen_sw_files");
+        foreach my $file (@sw_file_gen){
+            if(defined $file ){
+                my ($path,$rename)=split('frename_sep_t',$file);
+                $rename=replace_golb_var($rename,\%params);
+                #read the file content
+                my $content=read_file_cntent($path,$project_dir);
+                $content=replace_golb_var($content,\%params);
+                if(defined $rename){
+                    open(FILE,  ">$sw_path/$rename") || die "Can not open: $!";
+                    print FILE $content;
+                    close(FILE) || die "Error closing file: $!";
+                }
+            }
+        }
+        # Write Hardware gen files
+        my @hw_file_gen = $ip->ip_get_list($category,$module,"gen_hw_files");
+        foreach my $file (@hw_file_gen){
+            if(defined $file ){
+                my ($path,$rename)=split('frename_sep_t',$file);
+                $rename=replace_golb_var($rename,\%params);
+                #read the file content
+                my $content=read_file_cntent($path,$project_dir);
+                $content=replace_golb_var($content,\%params);
+                if(defined $rename){
+                    open(FILE,  ">$hw_path/$rename") || die "Can not open: $!";
+                    print FILE $content;
+                    close(FILE) || die "Error closing file: $!";
+                }
+            }
+        }
+    }
+    add_text_to_string(\$system_h,"#endif\n");
+    #write sytem.h file
+    open(FILE,  ">$sw_path/$name.h") || die "Can not open: $!";
+    print FILE $system_h;
+    close(FILE) || die "Error closing file: $!";
+    #write system.c file
+    open(FILE,  ">$sw_path/$name.c") || die "Can not open: $!";
+    print FILE $system_c;
+    close(FILE) || die "Error closing file: $!";
 }
-
-
-1
+1;
\ No newline at end of file
diff --git a/mpsoc/perl_gui/lib/perl/interface.pm b/mpsoc/perl_gui/lib/perl/interface.pm
index be71cb7..92dd951 100755
--- a/mpsoc/perl_gui/lib/perl/interface.pm
+++ b/mpsoc/perl_gui/lib/perl/interface.pm
@@ -2,302 +2,238 @@
 ###############################################################################
 #
 # File:         interface.pm
-# 
+#
 #
 ###############################################################################
 use warnings;
 use strict;
 use intfc_gen;
 use Data::Dumper;
-
 use Cwd;
-  
-
-
 package interface;
 
-
-
-
-
 sub interface_new {
     # be backwards compatible with non-OO call
     my $class = ("ARRAY" eq ref $_[0]) ? "interface" : shift;
     my $self;
-
-   
     $self = {};
-    $self->{plugs}        = {}; 
-    $self->{sockets}      = {}; 
-    $self->{categories}   = {}; 
-    
-    
-	my $dir = Cwd::getcwd();
-	$dir =~ s/ /\\ /g;
-	my @files = glob "$dir/lib/interface/*.ITC";
-	for my $p (@files){
-		#print "$p\n"; 
-		#my $infc_gen = Storable::retrieve($p);
-	# Read
-	my  $infc_gen;
-	$infc_gen = eval { do $p };
- 	# Might need "no strict;" before and "use strict;" after "do"
-	die "Error reading: $@" if $@;
-	
-	add_intfc($self,$infc_gen);
-	}
-	
-
+    $self->{plugs}        = {};
+    $self->{sockets}      = {};
+    $self->{categories}   = {};
+    my $dir = Cwd::getcwd();
+    $dir =~ s/ /\\ /g;
+    my @files = glob "$dir/lib/interface/*.ITC";
+    for my $p (@files){
+        #print "$p\n";
+        #my $infc_gen = Storable::retrieve($p);
+    # Read
+    my  $infc_gen;
+    $infc_gen = eval { do $p };
+    # Might need "no strict;" before and "use strict;" after "do"
+    die "Error reading: $@" if $@;
+    add_intfc($self,$infc_gen);
+    }
     bless($self,$class);
-
-   
     return $self;
-} 
-
+}
 
 sub add_category{
-	my ($self,$category,$intfc_name,$info)=@_;
-	$self->{categories}{$category}{names}{$intfc_name}{info}=$info; 
-	
-}	
+    my ($self,$category,$intfc_name,$info)=@_;
+    $self->{categories}{$category}{names}{$intfc_name}{info}=$info;
+}
 
 sub get_description{
-	my ($self,$category,$name)=@_;
-	my $info;
-	if(exists ($self->{categories}{$category}{names}{$name})){
-		$info= $self->{categories}{$category}{names}{$name}{info};
-	}	
-	return $info;	
-}	
-
+    my ($self,$category,$name)=@_;
+    my $info;
+    if(exists ($self->{categories}{$category}{names}{$name})){
+        $info= $self->{categories}{$category}{names}{$name}{info};
+    }
+    return $info;
+}
 
 sub add_plug{
-		my($self,$plug,$info,$category,$connection_num,$connect_to)=@_; 
-		$self->{plugs}{$plug}={};	
-		$self->{plugs}{$plug}{connection_num}=$connection_num;
-		$self->{plugs}{$plug}{connect_to}=$connect_to;
-		$self->{plugs}{$plug}{info}=$info;
-		$self->{plugs}{$plug}{category}=$category;
+        my($self,$plug,$info,$category,$connection_num,$connect_to)=@_;
+        $self->{plugs}{$plug}={};
+        $self->{plugs}{$plug}{connection_num}=$connection_num;
+        $self->{plugs}{$plug}{connect_to}=$connect_to;
+        $self->{plugs}{$plug}{info}=$info;
+        $self->{plugs}{$plug}{category}=$category;
 }
 
 sub get_plug{
-		my($self,$plug)=@_; 
-		my ($connection_num,$connect_to,$info,$category);
-		if(exists ($self->{plugs}{$plug})){
-			$connection_num	=$self->{plugs}{$plug}{connection_num};
-			$connect_to		=$self->{plugs}{$plug}{connect_to};
-			$info			=$self->{plugs}{$plug}{info};
-			$category		=$self->{plugs}{$plug}{category};
-			
-		}
-		return ($connection_num,$connect_to,$info,$category);
-}	
-
-
+        my($self,$plug)=@_;
+        my ($connection_num,$connect_to,$info,$category);
+        if(exists ($self->{plugs}{$plug})){
+            $connection_num    =$self->{plugs}{$plug}{connection_num};
+            $connect_to        =$self->{plugs}{$plug}{connect_to};
+            $info            =$self->{plugs}{$plug}{info};
+            $category        =$self->{plugs}{$plug}{category};
+        }
+        return ($connection_num,$connect_to,$info,$category);
+}
 
 sub add_socket{
-		my($self,$socket,$info,$category,$connection_num,$connect_to)=@_; 
-		$self->{sockets}{$socket}={};	
-		$self->{sockets}{$socket}{connection_num}=$connection_num;
-		$self->{sockets}{$socket}{connect_to}=$connect_to;
-		$self->{sockets}{$socket}{info}=$info;
-		$self->{sockets}{$socket}{category}=$category;
-}	
-	
-	
+        my($self,$socket,$info,$category,$connection_num,$connect_to)=@_;
+        $self->{sockets}{$socket}={};
+        $self->{sockets}{$socket}{connection_num}=$connection_num;
+        $self->{sockets}{$socket}{connect_to}=$connect_to;
+        $self->{sockets}{$socket}{info}=$info;
+        $self->{sockets}{$socket}{category}=$category;
+}
+
 sub get_socket{
-		my($self,$socket)=@_; 
-		my ($connection_num,$connect_to,$info,$category);
-		if(exists ($self->{sockets}{$socket})){
-			$connection_num	=$self->{sockets}{$socket}{connection_num};
-			$connect_to		=$self->{sockets}{$socket}{connect_to};
-			$info			=$self->{sockets}{$socket}{info};
-			$category		=$self->{sockets}{$socket}{category}=$category;
-		}
-		return ($connection_num,$connect_to,$info,$category);
-}		
-	
+        my($self,$socket)=@_;
+        my ($connection_num,$connect_to,$info,$category);
+        if(exists ($self->{sockets}{$socket})){
+            $connection_num    =$self->{sockets}{$socket}{connection_num};
+            $connect_to        =$self->{sockets}{$socket}{connect_to};
+            $info            =$self->{sockets}{$socket}{info};
+            $category        =$self->{sockets}{$socket}{category}=$category;
+        }
+        return ($connection_num,$connect_to,$info,$category);
+}
 
 sub add_param_to_plug{
-		my($self,$interface,$param,$value)=@_;
-		$self->{plugs}{$interface}{parameters}{$param}=$value;		
-	
+        my($self,$interface,$param,$value)=@_;
+        $self->{plugs}{$interface}{parameters}{$param}=$value;
 }
 
-
 sub add_param_to_socket{
-		my($self,$interface,$param,$value)=@_;
-		$self->{sockets}{$interface}{parameters}{$param}=$value;		
-	
-}		
-
-
+        my($self,$interface,$param,$value)=@_;
+        $self->{sockets}{$interface}{parameters}{$param}=$value;
+}
 
 sub add_port_to_plug{
-	my($self,$interface,$port,$range,$type,$outport_type,$connect,$default_out)=@_;
-	$self->{plugs}{$interface}{ports}{$port}={};
-	$self->{plugs}{$interface}{ports}{$port}{range}=$range;
-	$self->{plugs}{$interface}{ports}{$port}{type}=$type;
-	$self->{plugs}{$interface}{ports}{$port}{outport_type}=$outport_type;
-	$self->{plugs}{$interface}{ports}{$port}{connect}=$connect;
-	$self->{plugs}{$interface}{ports}{$port}{default_out}=$default_out;
-	
+    my($self,$interface,$port,$range,$type,$outport_type,$connect,$default_out)=@_;
+    $self->{plugs}{$interface}{ports}{$port}={};
+    $self->{plugs}{$interface}{ports}{$port}{range}=$range;
+    $self->{plugs}{$interface}{ports}{$port}{type}=$type;
+    $self->{plugs}{$interface}{ports}{$port}{outport_type}=$outport_type;
+    $self->{plugs}{$interface}{ports}{$port}{connect}=$connect;
+    $self->{plugs}{$interface}{ports}{$port}{default_out}=$default_out;
 }
 
-
 sub get_port_info_of_socket{
-	my($self,$socket,$port)=@_;
-	my($range,$type,$connect,$default_out);
-	if(exists ($self->{sockets}{$socket}{ports}{$port})){
-		$range=$self->{sockets}{$socket}{ports}{$port}{range};
-		$type=$self->{sockets}{$socket}{ports}{$port}{type};
-		$connect=$self->{sockets}{$socket}{ports}{$port}{connect};
-		$default_out=$self->{sockets}{$socket}{ports}{$port}{default_out};
-	}
-	return ($range,$type,$connect,$default_out);
+    my($self,$socket,$port)=@_;
+    my($range,$type,$connect,$default_out);
+    if(exists ($self->{sockets}{$socket}{ports}{$port})){
+        $range=$self->{sockets}{$socket}{ports}{$port}{range};
+        $type=$self->{sockets}{$socket}{ports}{$port}{type};
+        $connect=$self->{sockets}{$socket}{ports}{$port}{connect};
+        $default_out=$self->{sockets}{$socket}{ports}{$port}{default_out};
+    }
+    return ($range,$type,$connect,$default_out);
 }
 
 sub get_port_info_of_plug{
-	my($self,$plug,$port)=@_;
-	my($range,$type,$connect,$default_out);
-	if(exists ($self->{plugs}{$plug}{ports}{$port})){
-		$range=$self->{plugs}{$plug}{ports}{$port}{range};
-		$type=$self->{plugs}{$plug}{ports}{$port}{type};
-		$connect=$self->{plugs}{$plug}{ports}{$port}{connect};
-		$default_out=$self->{plugs}{$plug}{ports}{$port}{default_out};
-
-	}
-	return ($range,$type,$connect,$default_out);
+    my($self,$plug,$port)=@_;
+    my($range,$type,$connect,$default_out);
+    if(exists ($self->{plugs}{$plug}{ports}{$port})){
+        $range=$self->{plugs}{$plug}{ports}{$port}{range};
+        $type=$self->{plugs}{$plug}{ports}{$port}{type};
+        $connect=$self->{plugs}{$plug}{ports}{$port}{connect};
+        $default_out=$self->{plugs}{$plug}{ports}{$port}{default_out};
+    }
+    return ($range,$type,$connect,$default_out);
 }
 
-
 sub add_port_to_socket{
-	my($self,$socket,$port,$range,$type,$outport_type,$connect,$default_out)=@_;
-	$self->{sockets}{$socket}{ports}{$port}={};
-	$self->{sockets}{$socket}{ports}{$port}{range}=$range;
-	$self->{sockets}{$socket}{ports}{$port}{type}=$type;
-	$self->{sockets}{$socket}{ports}{$port}{outport_type}=$outport_type;
-	$self->{sockets}{$socket}{ports}{$port}{connect}=$connect;
-	$self->{sockets}{$socket}{ports}{$port}{default_out}=$default_out;
-	
+    my($self,$socket,$port,$range,$type,$outport_type,$connect,$default_out)=@_;
+    $self->{sockets}{$socket}{ports}{$port}={};
+    $self->{sockets}{$socket}{ports}{$port}{range}=$range;
+    $self->{sockets}{$socket}{ports}{$port}{type}=$type;
+    $self->{sockets}{$socket}{ports}{$port}{outport_type}=$outport_type;
+    $self->{sockets}{$socket}{ports}{$port}{connect}=$connect;
+    $self->{sockets}{$socket}{ports}{$port}{default_out}=$default_out;
 }
 
-
 sub get_socket_port_list{
-	my($self,$socket)=@_;
-	my @ports;
-	if(exists ($self->{sockets}{$socket}{ports})){
-		foreach my $p(keys %{$self->{sockets}{$socket}{ports}}){
-			push (@ports,$p);
-		}
-	}
-	return @ports;		
+    my($self,$socket)=@_;
+    my @ports;
+    if(exists ($self->{sockets}{$socket}{ports})){
+        foreach my $p(keys %{$self->{sockets}{$socket}{ports}}){
+            push (@ports,$p);
+        }
+    }
+    return @ports;
 }
 
 sub get_plug_port_list{
-	my($self,$plug)=@_;
-	my @ports;
-	if(exists ($self->{plugs}{$plug}{ports})){
-		foreach my $p(keys %{$self->{plugs}{$plug}{ports}}){
-			push (@ports,$p);
-		}
-	}
-	return @ports;		
+    my($self,$plug)=@_;
+    my @ports;
+    if(exists ($self->{plugs}{$plug}{ports})){
+        foreach my $p(keys %{$self->{plugs}{$plug}{ports}}){
+            push (@ports,$p);
+        }
+    }
+    return @ports;
 }
 
-
-
 sub get_interfaces{
-	my $self=shift;
-	my @interfaces;
-	if(exists ($self->{plugs})){
-		foreach my $p (sort keys %{$self->{plugs}}){
-			push (@interfaces,$p);
-		}	
-	}
-	return @interfaces;
-	
-	
-}	
+    my $self=shift;
+    my @interfaces;
+    if(exists ($self->{plugs})){
+        foreach my $p (sort keys %{$self->{plugs}}){
+            push (@interfaces,$p);
+        }
+    }
+    return @interfaces;
+}
 
 sub get_categories{
-	my $self=shift;
-	my @categories;
-	if(exists ($self->{categories})){
-		foreach my $p (sort keys %{$self->{categories}}){
-			push (@categories,$p);
-		}	
-	}
-	return @categories;	
-	
-}	
-	
-sub get_intfcs_of_category{
-	my ($self,$category)=@_;
-	my @list;
-	if(exists ($self->{categories}{$category}{names})){
-		foreach my $p (sort keys %{$self->{categories}{$category}{names}}){
-			push (@list,$p);
-		}
-		
-	}
-	return @list;
-}	
+    my $self=shift;
+    my @categories;
+    if(exists ($self->{categories})){
+        foreach my $p (sort keys %{$self->{categories}}){
+            push (@categories,$p);
+        }
+    }
+    return @categories;
+}
 
+sub get_intfcs_of_category{
+    my ($self,$category)=@_;
+    my @list;
+    if(exists ($self->{categories}{$category}{names})){
+        foreach my $p (sort keys %{$self->{categories}{$category}{names}}){
+            push (@list,$p);
+        }
+    }
+    return @list;
+}
 
 sub add_intfc{
-
-	my ($self,$infc_gen) =@_;
-	
-	my $intfc_name=$infc_gen->object_get_attribute('name');
-	my $connection_num=$infc_gen->object_get_attribute('connection_num');
-	my $intfc_type=$infc_gen->object_get_attribute('type');
-	my $intfc_info=$infc_gen->object_get_attribute('description');
-	my $intfc_category=$infc_gen->object_get_attribute('category');
-	
-	
-	my(%types,%ranges,%names,%connect_types,%connect_ranges,%connect_names,%outport_types,%default_outs);
-	
-	
-	add_socket($self,$intfc_name,$intfc_info,$intfc_category,$connection_num,$intfc_name);
-	add_plug($self,$intfc_name,$intfc_info,$intfc_category,$connection_num,$intfc_name);
-	
-	add_category($self,$intfc_category,$intfc_name,$intfc_info);
-	
-	
-	$infc_gen->intfc_get_ports(\%types,\%ranges,\%names,\%connect_types,\%connect_ranges,\%connect_names,\%outport_types,\%default_outs);	
-	foreach my $id (sort keys %ranges){
-			my $type=$types{$id};
-			my $range=$ranges{$id};
-			my $name=$names{$id};
-			my $connect_type=$connect_types{$id};
-			my $connect_range=$connect_ranges{$id};
-			my $connect_name=$connect_names{$id};
-			my $outport_type=$outport_types{$id};
-			my $default_out=$default_outs{$id};
-			if($intfc_type eq 'plug'){
-				
-				 #my($self,$interface,$port,$range,$type,$outport_type)
-				add_port_to_plug	($self,$intfc_name,$name,$range,$type,$outport_type,$connect_name,$default_out);
-				#print "add_port_to_plug(\$self,$intfc_name,$name,$range,$type,,$outport_type);\n";
-				add_port_to_socket	($self,$intfc_name,$connect_name,$connect_range,$connect_type,$outport_type,$name,$default_out);
-				#print "add_port_to_socket(\$self,$connect_name,$connect_range,$connect_type);\n";
-			}	
-			else{
-				add_port_to_socket($self,$intfc_name,$name,$range,$type,$outport_type,$connect_name,$default_out);
-				add_port_to_plug($self,$intfc_name,$connect_name,$connect_range,$connect_type,$outport_type,$name,$default_out);
-			}	
-	}		
-	
-}	
-
-
-
-
-
-
-
-
-
-
-1
+    my ($self,$infc_gen) =@_;
+    my $intfc_name=$infc_gen->object_get_attribute('name');
+    my $connection_num=$infc_gen->object_get_attribute('connection_num');
+    my $intfc_type=$infc_gen->object_get_attribute('type');
+    my $intfc_info=$infc_gen->object_get_attribute('description');
+    my $intfc_category=$infc_gen->object_get_attribute('category');
+    my(%types,%ranges,%names,%connect_types,%connect_ranges,%connect_names,%outport_types,%default_outs);
+    add_socket($self,$intfc_name,$intfc_info,$intfc_category,$connection_num,$intfc_name);
+    add_plug($self,$intfc_name,$intfc_info,$intfc_category,$connection_num,$intfc_name);
+    add_category($self,$intfc_category,$intfc_name,$intfc_info);
+    $infc_gen->intfc_get_ports(\%types,\%ranges,\%names,\%connect_types,\%connect_ranges,\%connect_names,\%outport_types,\%default_outs);
+    foreach my $id (sort keys %ranges){
+            my $type=$types{$id};
+            my $range=$ranges{$id};
+            my $name=$names{$id};
+            my $connect_type=$connect_types{$id};
+            my $connect_range=$connect_ranges{$id};
+            my $connect_name=$connect_names{$id};
+            my $outport_type=$outport_types{$id};
+            my $default_out=$default_outs{$id};
+            if($intfc_type eq 'plug'){
+                #my($self,$interface,$port,$range,$type,$outport_type)
+                add_port_to_plug    ($self,$intfc_name,$name,$range,$type,$outport_type,$connect_name,$default_out);
+                #print "add_port_to_plug(\$self,$intfc_name,$name,$range,$type,,$outport_type);\n";
+                add_port_to_socket    ($self,$intfc_name,$connect_name,$connect_range,$connect_type,$outport_type,$name,$default_out);
+                #print "add_port_to_socket(\$self,$connect_name,$connect_range,$connect_type);\n";
+            }
+            else{
+                add_port_to_socket($self,$intfc_name,$name,$range,$type,$outport_type,$connect_name,$default_out);
+                add_port_to_plug($self,$intfc_name,$connect_name,$connect_range,$connect_type,$outport_type,$name,$default_out);
+            }
+    }
+}
+1;
\ No newline at end of file
diff --git a/mpsoc/perl_gui/lib/perl/interface_gen.pl b/mpsoc/perl_gui/lib/perl/interface_gen.pl
index 065faec..64a4699 100755
--- a/mpsoc/perl_gui/lib/perl/interface_gen.pl
+++ b/mpsoc/perl_gui/lib/perl/interface_gen.pl
@@ -2,749 +2,507 @@
 use constant::boolean;
 use strict;
 use warnings;
-
 use FindBin;
 use lib $FindBin::Bin;
-
 use Data::Dumper;
 use intfc_gen;
 use rvp;
-
-
-
-
-require "widget.pl"; 
-
+require "widget.pl";
 
 sub read_file_modules{
-	my ($file,$intfc_gen,$info)=@_;
-	
-	if (!defined $file) {
-		add_colored_info($info,"No input file is given. Please set an input Verilog fle first.\n", 'red');	
-		return;
-	 }
-	 
-	my $f=add_project_dir_to_addr($file); 
-	if (-e $f) { 
-		my $vdb =  read_verilog_file($f);
-		my @modules=sort $vdb->get_modules($f);
-		#foreach my $p(@module_list) {print "$p\n"}
-		$intfc_gen->intfc_set_interface_file($file);
-		$intfc_gen->intfc_set_module_name($modules[0]);
-		$intfc_gen->intfc_add_module_list(@modules);
-		
-		set_gui_status($intfc_gen,"file_selected",1);
-		add_info($info,"$f is loaded\n");	
-	    
-	}
-	else { 
-		add_colored_info($info,"File $file does not exist!\n", 'red');		
-		
-	}	
-}	
-
+    my ($file,$intfc_gen,$info)=@_;
+    if (!defined $file) {
+        add_colored_info($info,"No input file is given. Please set an input Verilog fle first.\n", 'red');
+        return;
+    }
+    my $f=add_project_dir_to_addr($file);
+    if (-e $f) {
+        my $vdb =  read_verilog_file($f);
+        my @modules=sort $vdb->get_modules($f);
+        #foreach my $p(@module_list) {print "$p\n"}
+        $intfc_gen->intfc_set_interface_file($file);
+        $intfc_gen->intfc_set_module_name($modules[0]);
+        $intfc_gen->intfc_add_module_list(@modules);
+        set_gui_status($intfc_gen,"file_selected",1);
+        add_info($info,"$f is loaded\n");
+    }
+    else {
+        add_colored_info($info,"File $file does not exist!\n", 'red');
+    }
+}
 
 ################
 #  check_input_intfc_file
 ################
-
 sub check_input_intfc_file{
-	my ($file,$intfc_gen,$info)=@_;
-	my ($name,$path,$suffix) = fileparse("$file",qr"\..[^.]*$");
-	if($suffix eq '.ITC'){
-		$intfc_gen->intfc_set_interface_file($file);
-		set_gui_status($intfc_gen,"load_file",0);
-		
-		
-	}else{
-		read_file_modules($file,$intfc_gen,$info);
-	
-	}	
-	
-	
-}	
+    my ($file,$intfc_gen,$info)=@_;
+    my ($name,$path,$suffix) = fileparse("$file",qr"\..[^.]*$");
+    if($suffix eq '.ITC'){
+        $intfc_gen->intfc_set_interface_file($file);
+        set_gui_status($intfc_gen,"load_file",0);
+    }else{
+        read_file_modules($file,$intfc_gen,$info);
+    }
+}
 
 sub file_box {
-	my ($intfc_gen,$info)=@_;
-	my $label = gen_label_in_left("Select file:");
-	my $entry = gen_entry();
-	my $open= def_image_button("icons/select.png","Open");
-	my $browse= def_image_button("icons/browse.png","Browse");
-	my $file= $intfc_gen->intfc_get_interface_file();
-	my $intfc_info= def_image_button("icons/add_info.png","Description");
-	my $table = def_table(1,10,FALSE);
-	$intfc_info->signal_connect("clicked"=> sub{
-		get_intfc_description($intfc_gen,$info);
-		
-		
-	});	
-	
-	if(defined $file){$entry->set_text($file);}
-	else {show_info($info,"Please select the Verilog file containing the interface\n");}
-
-
-	$browse->signal_connect("clicked"=> sub{
-		my $entry_ref=$_[1];
- 		my $file;
+    my ($intfc_gen,$info)=@_;
+    my $label = gen_label_in_left("Select file:");
+    my $entry = gen_entry();
+    my $open= def_image_button("icons/select.png","Open");
+    my $browse= def_image_button("icons/browse.png","Browse");
+    my $file= $intfc_gen->intfc_get_interface_file();
+    my $intfc_info= def_image_button("icons/add_info.png","Description");
+    my $table = def_table(1,10,FALSE);
+    $intfc_info->signal_connect("clicked"=> sub{
+        get_intfc_description($intfc_gen,$info);
+    });
+    if(defined $file){$entry->set_text($file);}
+    else {show_info($info,"Please select the Verilog file containing the interface\n");}
+    $browse->signal_connect("clicked"=> sub{
+        my $entry_ref=$_[1];
+        my $file;
         my $dialog = gen_file_dialog (undef, 'v','ITC');
-		if ( "ok" eq $dialog->run ) {
-           		$file = $dialog->get_filename;
-				$$entry_ref->set_text($file);
-				check_input_intfc_file($file,$intfc_gen,$info);
-		}
-       	$dialog->destroy;
-	} , \$entry);
-	
-	$open->signal_connect("clicked"=> sub{
-		my $file_name=$entry->get_text();
-		check_input_intfc_file($file,$intfc_gen,$info);
-		#read_file_modules($file_name,$intfc_gen,$info);
-		
-		});
-	$entry->signal_connect("activate"=>sub{
-		my $file_name=$entry->get_text();
-		read_file_modules($file_name,$intfc_gen,$info);
-	});
-		
-	$entry->signal_connect("changed"=>sub{
-		#show_info($info,"Please select the verilog file containing the interface\n");
-	});
-	
-	my $row=0;
-	$table->attach_defaults ($label, 0, 1 , $row, $row+1);
-	$table->attach_defaults ($entry, 1, 7 , $row, $row+1);
-	$table->attach ($browse, 7, 8, $row, $row+1,'shrink','shrink',2,2);
-	$table->attach ($intfc_info, 8, 9 , $row, $row+1,'shrink','shrink',2,2);
-	#$table->attach_defaults ($open,  9, 10, $row, $row+1);
-	#$table->attach_defaults ($entry, $col, $col+1, $row, $row+1);
-	return $table;
-	
-	
+        if ( "ok" eq $dialog->run ) {
+                $file = $dialog->get_filename;
+                $$entry_ref->set_text($file);
+                check_input_intfc_file($file,$intfc_gen,$info);
+        }
+        $dialog->destroy;
+    } , \$entry);
+    $open->signal_connect("clicked"=> sub{
+        my $file_name=$entry->get_text();
+        check_input_intfc_file($file,$intfc_gen,$info);
+        #read_file_modules($file_name,$intfc_gen,$info);
+        });
+    $entry->signal_connect("activate"=>sub{
+        my $file_name=$entry->get_text();
+        read_file_modules($file_name,$intfc_gen,$info);
+    });
+    $entry->signal_connect("changed"=>sub{
+        #show_info($info,"Please select the verilog file containing the interface\n");
+    });
+    my $row=0;
+    $table->attach_defaults ($label, 0, 1 , $row, $row+1);
+    $table->attach_defaults ($entry, 1, 7 , $row, $row+1);
+    $table->attach ($browse, 7, 8, $row, $row+1,'shrink','shrink',2,2);
+    $table->attach ($intfc_info, 8, 9 , $row, $row+1,'shrink','shrink',2,2);
+    #$table->attach_defaults ($open,  9, 10, $row, $row+1);
+    #$table->attach_defaults ($entry, $col, $col+1, $row, $row+1);
+    return $table;
 }
 
-
-
-
-
 sub get_interface_ports {
-	my ($intfc_gen,$info)=@_;
-	my $window=def_popwin_size(60,60,"Import Ports",'percent');
-
-	my $file=$intfc_gen->intfc_get_interface_file();
-	if (!defined $file){show_info($info,"File name has not been defined yet!");  return;}
-	my $module=$intfc_gen->intfc_get_module_name();
-	if (!defined $module){  show_info($info,"Module name has not been selected yet!");  return;}
-	my $f=add_project_dir_to_addr($file);
-	my $vdb=read_verilog_file($f);
-	my %port_type=get_ports_type($vdb,$module);
-	my %port_range=get_ports_rang($vdb,$module);
-	
-	my $table=def_table(8,8,TRUE);
-	my $scrolled_win = add_widget_to_scrolled_win($table);
-	
-	
-	my $title=gen_label_in_center("Select the ports included in the interface");
-	my $title1=gen_label_in_center("Type");
-	my $title2=gen_label_in_center("Range");
-	my $title3=gen_label_in_center("Name");
-	my $title4=gen_label_in_center("Select");
-	
-	my $row	=0;
-	$table->attach_defaults($title, 0,8, $row, $row+1); 
-	$row++;
-	$table->attach_defaults($title1, 0,1, $row, $row+1); 
-	$table->attach_defaults($title2, 1,4, $row, $row+1); 
-	$table->attach_defaults($title3, 4,7, $row, $row+1); 
-	$table->attach_defaults($title4, 7,8, $row, $row+1); 
-	$row++;
-	
-	add_Hsep_to_table($table, 0, 8 , $row);	$row++;
-	
-	$intfc_gen->intfc_remove_ports();
-	foreach my $p (sort keys %port_type){
-		my $port_id= $p;
-		my $porttype=$port_type{$p};
-		my $label1= gen_label_in_center("$porttype");
-		$table->attach_defaults($label1, 0,1, $row, $row+1); 
-		my $portrange=$port_range{$p};
-		if (  $port_range{$p} ne ''){
-			
-			my $label2= gen_label_in_center("\[$portrange\]");
-			$table->attach_defaults($label2, 1,4, $row, $row+1);
-		}
-		
-		my $label3= gen_label_in_center($p);
-		$table->attach_defaults($label3, 4,7, $row, $row+1); 
-		
-		my $check= gen_checkbutton();
-		$table->attach_defaults($check, 7,8, $row, $row+1); 
-		
-		$row++;
-		if($row>8){$table->resize ($row, 8);}
-		#print "$p\:$port_type{$p}\n";
-		
-		$check->signal_connect("toggled"=>sub{
-			my $widget=shift;
-			my $in=$widget->get_active();
-			if ($in eq 1){
-				my $connect_type=($porttype eq "input")? "output" : ($porttype eq "output")? "input" : $porttype;
-				$intfc_gen->intfc_add_port($port_id,$porttype,$portrange,$p,$connect_type,$portrange,$p,"concatenate","Active low");
-				
-				
-				
-				#print "chanhed to $in \n";
-			}else {
-				$intfc_gen->intfc_remove_port($port_id);
-				
-				#print "chanhed to 0 \n";
-				
-			}	
-			
-			
-		});
-		
-	}
-	
-	
-	my $ok= def_image_button("icons/select.png","ok");
-	$table->attach($ok, 3,5, $row, $row+1,'shrink','shrink',2,2); 
-	
-	$ok->signal_connect("clicked"=>sub{
-		$window->destroy;
-		set_gui_status($intfc_gen,"refresh",1);
-		
-		
-		});
-	
-	$window->add($scrolled_win);
-	
-	$window->show_all();
-}	
-
-
-
-
-
+    my ($intfc_gen,$info)=@_;
+    my $window=def_popwin_size(60,60,"Import Ports",'percent');
+    my $file=$intfc_gen->intfc_get_interface_file();
+    if (!defined $file){show_info($info,"File name has not been defined yet!");  return;}
+    my $module=$intfc_gen->intfc_get_module_name();
+    if (!defined $module){  show_info($info,"Module name has not been selected yet!");  return;}
+    my $f=add_project_dir_to_addr($file);
+    my $vdb=read_verilog_file($f);
+    my %port_type=get_ports_type($vdb,$module);
+    my %port_range=get_ports_rang($vdb,$module);
+    my $table=def_table(8,8,TRUE);
+    my $scrolled_win = add_widget_to_scrolled_win($table);
+    my $title=gen_label_in_center("Select the ports included in the interface");
+    my $title1=gen_label_in_center("Type");
+    my $title2=gen_label_in_center("Range");
+    my $title3=gen_label_in_center("Name");
+    my $title4=gen_label_in_center("Select");
+    my $row    =0;
+    $table->attach_defaults($title, 0,8, $row, $row+1);
+    $row++;
+    $table->attach_defaults($title1, 0,1, $row, $row+1);
+    $table->attach_defaults($title2, 1,4, $row, $row+1);
+    $table->attach_defaults($title3, 4,7, $row, $row+1);
+    $table->attach_defaults($title4, 7,8, $row, $row+1);
+    $row++;
+    add_Hsep_to_table($table, 0, 8 , $row);    $row++;
+    $intfc_gen->intfc_remove_ports();
+    foreach my $p (sort keys %port_type){
+        my $port_id= $p;
+        my $porttype=$port_type{$p};
+        my $label1= gen_label_in_center("$porttype");
+        $table->attach_defaults($label1, 0,1, $row, $row+1);
+        my $portrange=$port_range{$p};
+        if (  $port_range{$p} ne ''){
+            my $label2= gen_label_in_center("\[$portrange\]");
+            $table->attach_defaults($label2, 1,4, $row, $row+1);
+        }
+        my $label3= gen_label_in_center($p);
+        $table->attach_defaults($label3, 4,7, $row, $row+1);
+        my $check= gen_checkbutton();
+        $table->attach_defaults($check, 7,8, $row, $row+1);
+        $row++;
+        if($row>8){$table->resize ($row, 8);}
+        #print "$p\:$port_type{$p}\n";
+        $check->signal_connect("toggled"=>sub{
+            my $widget=shift;
+            my $in=$widget->get_active();
+            if ($in eq 1){
+                my $connect_type=($porttype eq "input")? "output" : ($porttype eq "output")? "input" : $porttype;
+                $intfc_gen->intfc_add_port($port_id,$porttype,$portrange,$p,$connect_type,$portrange,$p,"concatenate","Active low");
+                #print "chanhed to $in \n";
+            }else {
+                $intfc_gen->intfc_remove_port($port_id);
+                #print "chanhed to 0 \n";
+            }
+        });
+    }
+    my $ok= def_image_button("icons/select.png","ok");
+    $table->attach($ok, 3,5, $row, $row+1,'shrink','shrink',2,2);
+    $ok->signal_connect("clicked"=>sub{
+        $window->destroy;
+        set_gui_status($intfc_gen,"refresh",1);
+        });
+    $window->add($scrolled_win);
+    $window->show_all();
+}
 
 sub module_select{
-	my ($intfc_gen,$info)=@_;
-	#my $file= $intfc_gen->intfc_get_interface_file();
-	
-	my $table = def_table(1,10,FALSE);
-
-	
-	
-	my @modules= $intfc_gen->intfc_get_module_list();
-	my $combo=gen_combobox_object($intfc_gen,'module_name',undef,join(',', @modules),undef,'refresh',1);
-	my $modul_name=gen_label_info(" Select module:",$combo);
-
-
-	my $port= def_image_button("icons/import.png","Import Ports");
-	my $category_entry=gen_entry_object($intfc_gen,'category',undef,undef,undef,undef);
-	my $category=gen_label_info(" Select Category:",$category_entry,'Define the Interface category:e.g RAM, wishbone,...');
-
-	
-	
-	
-	my $row=0;
-	#$table->attach_defaults ($label, 0, 1 , $row, $row+1);
-	$table->attach  ($modul_name, 0, 3 , $row,$row+1,'shrink','shrink',2,2);
-	$table->attach ($port, 4, 6 , $row, $row+1,'shrink','shrink',2,2);
-	$table->attach_defaults ($category, 7, 10 , $row, $row+1);
-	
-	
-	
-	
-	$port->signal_connect("clicked"=> sub{
-		get_interface_ports($intfc_gen,$info);
-		
-		
-	});	
-	
-	
-	
-	return $table;
-	
-	
-}	
+    my ($intfc_gen,$info)=@_;
+    #my $file= $intfc_gen->intfc_get_interface_file();
+    my $table = def_table(1,10,FALSE);
+    my @modules= $intfc_gen->intfc_get_module_list();
+    my $combo=gen_combobox_object($intfc_gen,'module_name',undef,join(',', @modules),undef,'refresh',1);
+    my $modul_name=gen_label_info(" Select module:",$combo);
+    my $port= def_image_button("icons/import.png","Import Ports");
+    my $category_entry=gen_entry_object($intfc_gen,'category',undef,undef,undef,undef);
+    my $category=gen_label_info(" Select Category:",$category_entry,'Define the Interface category:e.g RAM, wishbone,...');
+    my $row=0;
+    #$table->attach_defaults ($label, 0, 1 , $row, $row+1);
+    $table->attach  ($modul_name, 0, 3 , $row,$row+1,'shrink','shrink',2,2);
+    $table->attach ($port, 4, 6 , $row, $row+1,'shrink','shrink',2,2);
+    $table->attach_defaults ($category, 7, 10 , $row, $row+1);
+    $port->signal_connect("clicked"=> sub{
+        get_interface_ports($intfc_gen,$info);
+    });
+    return $table;
+}
 
 sub interface_type_select {
-	my ($intfc_gen,$info,$table,$row)=@_;		
-
-	my $entry=gen_entry_object($intfc_gen,'name',undef,undef,"refresh",50);
-	my $entrybox=gen_label_info(" Interface name:",$entry);
-
-	my $combo=gen_combobox_object($intfc_gen,'connection_num',undef,"single connection,multi connection","single connection",'refresh',1);
-	my $combo_box=gen_label_info(" Select socket type:",$combo,'Define the socket as multi connection if only if all interfaces ports are output oprts and they can feed more than one plug interface. E.g. clk is defined as multi connection');
-	
-	$table->attach ($entrybox, 0, 2 , $row, $row+1,'expand','shrink',2,2);
-	$table->attach ($combo_box, 3, 6 , $row, $row+1,'expand','shrink',2,2);
-	
-}	
-
-
-
-
-
+    my ($intfc_gen,$info,$table,$row)=@_;
+    my $entry=gen_entry_object($intfc_gen,'name',undef,undef,"refresh",50);
+    my $entrybox=gen_label_info(" Interface name:",$entry);
+    my $combo=gen_combobox_object($intfc_gen,'connection_num',undef,"single connection,multi connection","single connection",'refresh',1);
+    my $combo_box=gen_label_info(" Select socket type:",$combo,'Define the socket as multi connection if only if all interfaces ports are output oprts and they can feed more than one plug interface. E.g. clk is defined as multi connection');
+    $table->attach ($entrybox, 0, 2 , $row, $row+1,'expand','shrink',2,2);
+    $table->attach ($combo_box, 3, 6 , $row, $row+1,'expand','shrink',2,2);
+}
 
 sub port_select{
-	my ($intfc_gen,$info,$table,$row)=@_;	
-	my(%types,%ranges,%names,%connect_types,%connect_ranges,%connect_names,%outport_types,%default_outs);
-	$intfc_gen->intfc_get_ports(\%types,\%ranges,\%names,\%connect_types,\%connect_ranges,\%connect_names,\%outport_types,\%default_outs);
-
-	my $size = keys %types;
-	if($size >0){
-		
-		add_Hsep_to_table($table, 0, 10 , $row);	$row++;
-		
-		my $swap= def_image_button("icons/swap.png","swap");
-			
-		$swap->signal_connect('clicked'=>sub{
-			my $type=$intfc_gen->intfc_get_interface_type();
-			if($type eq 'plug'){
-					$intfc_gen->intfc_set_interface_type('socket');
-			}
-			else {
-					$intfc_gen->intfc_set_interface_type('plug');
-			}	
-			set_gui_status($intfc_gen,"refresh",1);			
-			
-		});
-		
-		
-		my @intfcs=("plug","socket");
-		my $inttype=$intfc_gen->intfc_get_interface_type();
-		if (!defined $inttype){
-			$inttype='plug';
-			$intfc_gen->intfc_set_interface_type($inttype);
-		}	
-				
-		#my $lab1= gen_label_in_center($inttype);
-		my ($lab1,$lab2);
-		if ($inttype eq 'plug'){
-			$lab1=def_image_label('icons/plug.png'  ,'plug  ');
-			$lab2=def_image_label('icons/socket.png','socket');
-		}else {
-			$lab2=def_image_label('icons/plug.png','plug');
-			$lab1=def_image_label('icons/socket.png','socket');
-			
-		}	
-		
-	
-		
-		
-		$table->attach ($lab1, 1, 2 , $row, $row+1,'expand','shrink',2,2);
-		$table->attach ($swap, 3, 4 , $row, $row+1,'expand','shrink',2,2);
-		$table->attach ($lab2, 5, 6 , $row, $row+1,'expand','shrink',2,2);	$row++;		
-		
-		
-		add_Hsep_to_table($table, 0, 9 , $row);	$row++;
-		
-		
-		my $lab3= gen_label_in_center("Type");
-		my $lab4= gen_label_in_center("Range");
-		my $lab5= gen_label_in_center("Name");
-		$table->attach ($lab3, 0, 1 , $row, $row+1,'expand','shrink',2,2);
-		$table->attach ($lab4, 1, 2 , $row, $row+1,'expand','shrink',2,2);
-		$table->attach ($lab5, 2, 3 , $row, $row+1,'expand','shrink',2,2);
-		my $lab6= gen_label_in_center("Type");
-		my $lab7= gen_label_in_center("Range");
-		my $lab8= gen_label_in_center("Name");
-		$table->attach ($lab6, 4, 5 , $row, $row+1,'expand','shrink',2,2);
-		$table->attach ($lab7, 5, 6 , $row, $row+1,'expand','shrink',2,2);
-		$table->attach ($lab8, 6, 7 , $row, $row+1,'expand','shrink',2,2);
-		my $lab9= gen_label_help ("When an IP core does not have any of interface output port, the default value will be send to the IP core's input port which is supposed to be connected to that port","Output port Default ");
-		$table->attach ($lab9, 8, 9 , $row, $row+1,'expand','shrink',2,2);
-		$row++;
-	
-		foreach my $id (sort keys %ranges){
-			my $type=$types{$id};
-			my $range=$ranges{$id};
-			my $name=$names{$id};
-			my $connect_type=$connect_types{$id};
-			my $connect_range=$connect_ranges{$id};
-			my $connect_name=$connect_names{$id};
-			my $outport_type=$outport_types{$id};
-			my $default_out=$default_outs{$id};
-			if(! defined $default_out){
-				$default_out = "Active low"; # port_width_repeat($connect_range,"1\'b0");
-				$intfc_gen->intfc_add_port($id,$type,$range,$name,$connect_type,$connect_range,$connect_name,$outport_type,$default_out);
-				print "\$default_out is set to: $default_out\n ";
-			}
-			
-			#my $box=def_hbox(FALSE,0);
-			
-			my @ports_type=("input","output","inout");
-			my $pos=get_scolar_pos($type,@ports_type);
-			my $combo1=gen_combo(\@ports_type,$pos);
-			my $entry2=gen_entry($range);
-			my $entry3=gen_entry($name);
-			
-			my $connect_type_lable= gen_label_in_center($connect_type);
-			my $entry4=gen_entry($connect_range);
-			my $entry5=gen_entry($connect_name);
-			my @outport_types=("shared","concatenate");
-			my $pos2=get_scolar_pos($outport_type,@outport_types);			
-			my $combo2=gen_combo(\@outport_types,$pos2);
-							
-			
-			#my @list=(port_width_repeat($range,"1\'b0"),port_width_repeat($range,"1\'b1"),port_width_repeat($range,"1\'bx"));
-			my @list=("Active low","Active high","Don't care");
-			
-			my $combentry=gen_combo_entry(\@list);
-			my $combochiled = combo_entry_get_chiled($combentry);
-			$pos2=get_scolar_pos($default_out,@list);		 
-			if( defined $pos2){
-				$combentry->set_active($pos2);
-			} else {
-				
-				$combochiled->set_text($default_out); 
-			} 
-			
-			
-			#$box->pack_start($entry3,TRUE,FALSE,3);
-			#$box->pack_start($separator,TRUE,FALSE,3);
-		
-			$table->attach ($combo1, 0, 1 , $row, $row+1,'expand','shrink',2,2);
-			$table->attach ($entry2, 1, 2 , $row, $row+1,'expand','shrink',2,2);
-			$table->attach ($entry3, 2, 3 , $row, $row+1,'expand','shrink',2,2);
-		
-			
-			$table->attach ($connect_type_lable, 4, 5 , $row, $row+1,'expand','shrink',2,2);
-			$table->attach ($entry4, 5, 6 , $row, $row+1,'expand','shrink',2,2);
-			$table->attach ($entry5, 6, 7 , $row, $row+1,'expand','shrink',2,2);
-			$table->attach ($combentry, 8, 9 , $row, $row+1,'expand','shrink',2,2);
-		
-			$combo1->signal_connect("changed"=>sub{
-				my $new_type=$combo1->get_active_text();
-				my $new_connect_type=($new_type eq "input")? "output" : ($new_type eq "output")? "input" : $new_type;
-				$intfc_gen->intfc_add_port($id,$new_type,$range,$name,$new_connect_type,$connect_range,$connect_name,$outport_type,$default_out);
-				set_gui_status($intfc_gen,"refresh",1);
-			
-			});
-			$entry2->signal_connect("changed"=>sub{
-				$range=$entry2->get_text(); 
-				$intfc_gen->intfc_add_port($id,$type,$range,$name,$connect_type,$connect_range,$connect_name,$outport_type,$default_out);
-				set_gui_status($intfc_gen,"refresh",50);
-				
-			});	
-			$entry3->signal_connect("changed"=>sub{
-				$name=$entry3->get_text(); 
-				$intfc_gen->intfc_add_port($id,$type,$range,$name,$connect_type,$connect_range,$connect_name,$outport_type,$default_out);
-				set_gui_status($intfc_gen,"refresh",50);
-				
-			});	
-			
-			$entry4->signal_connect("changed"=>sub{
-				$connect_range=$entry4->get_text(); 
-				$intfc_gen->intfc_add_port($id,$type,$range,$name,$connect_type,$connect_range,$connect_name,$outport_type,$default_out);
-				set_gui_status($intfc_gen,"refresh",50);
-				
-			});	
-			$entry5->signal_connect("changed"=>sub{
-				$connect_name=$entry5->get_text(); 
-				$intfc_gen->intfc_add_port($id,$type,$range,$name,$connect_type,$connect_range,$connect_name,$outport_type,$default_out);
-				set_gui_status($intfc_gen,"refresh",50);
-				
-			});	
-			$combo2->signal_connect("changed"=>sub{
-				my $new_outport_type=$combo2->get_active_text();
-				$intfc_gen->intfc_add_port($id,$type,$range,$name,$connect_type,$connect_range,$connect_name,$new_outport_type,$default_out);
-				set_gui_status($intfc_gen,"refresh",1);
-			
-			});
-			$combochiled->signal_connect('changed' => sub {
-				my ($entry) = @_;
-				$default_out=$entry->get_text();
-				$intfc_gen->intfc_add_port($id,$type,$range,$name,$connect_type,$connect_range,$connect_name,$outport_type,$default_out);
-			
-				
-			});
-			
-			
-			
-			$row++;
-		
-		
-		}#foreach port	
-	
-	
-	}
-	return $row;
+    my ($intfc_gen,$info,$table,$row)=@_;
+    my(%types,%ranges,%names,%connect_types,%connect_ranges,%connect_names,%outport_types,%default_outs);
+    $intfc_gen->intfc_get_ports(\%types,\%ranges,\%names,\%connect_types,\%connect_ranges,\%connect_names,\%outport_types,\%default_outs);
+    my $size = keys %types;
+    if($size >0){
+        add_Hsep_to_table($table, 0, 10 , $row);    $row++;
+        my $swap= def_image_button("icons/swap.png","swap");
+        $swap->signal_connect('clicked'=>sub{
+            my $type=$intfc_gen->intfc_get_interface_type();
+            if($type eq 'plug'){
+                    $intfc_gen->intfc_set_interface_type('socket');
+            }
+            else {
+                    $intfc_gen->intfc_set_interface_type('plug');
+            }
+            set_gui_status($intfc_gen,"refresh",1);
+        });
+        my @intfcs=("plug","socket");
+        my $inttype=$intfc_gen->intfc_get_interface_type();
+        if (!defined $inttype){
+            $inttype='plug';
+            $intfc_gen->intfc_set_interface_type($inttype);
+        }
+        #my $lab1= gen_label_in_center($inttype);
+        my ($lab1,$lab2);
+        if ($inttype eq 'plug'){
+            $lab1=def_image_label('icons/plug.png'  ,'plug  ');
+            $lab2=def_image_label('icons/socket.png','socket');
+        }else {
+            $lab2=def_image_label('icons/plug.png','plug');
+            $lab1=def_image_label('icons/socket.png','socket');
+        }
+        $table->attach ($lab1, 1, 2 , $row, $row+1,'expand','shrink',2,2);
+        $table->attach ($swap, 3, 4 , $row, $row+1,'expand','shrink',2,2);
+        $table->attach ($lab2, 5, 6 , $row, $row+1,'expand','shrink',2,2);    $row++;
+        add_Hsep_to_table($table, 0, 9 , $row);    $row++;
+        my $lab3= gen_label_in_center("Type");
+        my $lab4= gen_label_in_center("Range");
+        my $lab5= gen_label_in_center("Name");
+        $table->attach ($lab3, 0, 1 , $row, $row+1,'expand','shrink',2,2);
+        $table->attach ($lab4, 1, 2 , $row, $row+1,'expand','shrink',2,2);
+        $table->attach ($lab5, 2, 3 , $row, $row+1,'expand','shrink',2,2);
+        my $lab6= gen_label_in_center("Type");
+        my $lab7= gen_label_in_center("Range");
+        my $lab8= gen_label_in_center("Name");
+        $table->attach ($lab6, 4, 5 , $row, $row+1,'expand','shrink',2,2);
+        $table->attach ($lab7, 5, 6 , $row, $row+1,'expand','shrink',2,2);
+        $table->attach ($lab8, 6, 7 , $row, $row+1,'expand','shrink',2,2);
+        my $lab9= gen_label_help ("When an IP core does not have any of interface output port, the default value will be send to the IP core's input port which is supposed to be connected to that port","Output port Default ");
+        $table->attach ($lab9, 8, 9 , $row, $row+1,'expand','shrink',2,2);
+        $row++;
+        foreach my $id (sort keys %ranges){
+            my $type=$types{$id};
+            my $range=$ranges{$id};
+            my $name=$names{$id};
+            my $connect_type=$connect_types{$id};
+            my $connect_range=$connect_ranges{$id};
+            my $connect_name=$connect_names{$id};
+            my $outport_type=$outport_types{$id};
+            my $default_out=$default_outs{$id};
+            if(! defined $default_out){
+                $default_out = "Active low"; # port_width_repeat($connect_range,"1\'b0");
+                $intfc_gen->intfc_add_port($id,$type,$range,$name,$connect_type,$connect_range,$connect_name,$outport_type,$default_out);
+                print "\$default_out is set to: $default_out\n ";
+            }
+            #my $box=def_hbox(FALSE,0);
+            my @ports_type=("input","output","inout");
+            my $pos=get_scolar_pos($type,@ports_type);
+            my $combo1=gen_combo(\@ports_type,$pos);
+            my $entry2=gen_entry($range);
+            my $entry3=gen_entry($name);
+            my $connect_type_lable= gen_label_in_center($connect_type);
+            my $entry4=gen_entry($connect_range);
+            my $entry5=gen_entry($connect_name);
+            my @outport_types=("shared","concatenate");
+            my $pos2=get_scolar_pos($outport_type,@outport_types);
+            my $combo2=gen_combo(\@outport_types,$pos2);
+            #my @list=(port_width_repeat($range,"1\'b0"),port_width_repeat($range,"1\'b1"),port_width_repeat($range,"1\'bx"));
+            my @list=("Active low","Active high","Don't care");
+            my $combentry=gen_combo_entry(\@list);
+            my $combochiled = combo_entry_get_chiled($combentry);
+            $pos2=get_scolar_pos($default_out,@list);
+            if( defined $pos2){
+                $combentry->set_active($pos2);
+            } else {
+                $combochiled->set_text($default_out);
+            }
+            #$box->pack_start($entry3,TRUE,FALSE,3);
+            #$box->pack_start($separator,TRUE,FALSE,3);
+            $table->attach ($combo1, 0, 1 , $row, $row+1,'expand','shrink',2,2);
+            $table->attach ($entry2, 1, 2 , $row, $row+1,'expand','shrink',2,2);
+            $table->attach ($entry3, 2, 3 , $row, $row+1,'expand','shrink',2,2);
+            $table->attach ($connect_type_lable, 4, 5 , $row, $row+1,'expand','shrink',2,2);
+            $table->attach ($entry4, 5, 6 , $row, $row+1,'expand','shrink',2,2);
+            $table->attach ($entry5, 6, 7 , $row, $row+1,'expand','shrink',2,2);
+            $table->attach ($combentry, 8, 9 , $row, $row+1,'expand','shrink',2,2);
+            $combo1->signal_connect("changed"=>sub{
+                my $new_type=$combo1->get_active_text();
+                my $new_connect_type=($new_type eq "input")? "output" : ($new_type eq "output")? "input" : $new_type;
+                $intfc_gen->intfc_add_port($id,$new_type,$range,$name,$new_connect_type,$connect_range,$connect_name,$outport_type,$default_out);
+                set_gui_status($intfc_gen,"refresh",1);
+            });
+            $entry2->signal_connect("changed"=>sub{
+                $range=$entry2->get_text();
+                $intfc_gen->intfc_add_port($id,$type,$range,$name,$connect_type,$connect_range,$connect_name,$outport_type,$default_out);
+                set_gui_status($intfc_gen,"refresh",50);
+            });
+            $entry3->signal_connect("changed"=>sub{
+                $name=$entry3->get_text();
+                $intfc_gen->intfc_add_port($id,$type,$range,$name,$connect_type,$connect_range,$connect_name,$outport_type,$default_out);
+                set_gui_status($intfc_gen,"refresh",50);
+            });
+            $entry4->signal_connect("changed"=>sub{
+                $connect_range=$entry4->get_text();
+                $intfc_gen->intfc_add_port($id,$type,$range,$name,$connect_type,$connect_range,$connect_name,$outport_type,$default_out);
+                set_gui_status($intfc_gen,"refresh",50);
+            });
+            $entry5->signal_connect("changed"=>sub{
+                $connect_name=$entry5->get_text();
+                $intfc_gen->intfc_add_port($id,$type,$range,$name,$connect_type,$connect_range,$connect_name,$outport_type,$default_out);
+                set_gui_status($intfc_gen,"refresh",50);
+            });
+            $combo2->signal_connect("changed"=>sub{
+                my $new_outport_type=$combo2->get_active_text();
+                $intfc_gen->intfc_add_port($id,$type,$range,$name,$connect_type,$connect_range,$connect_name,$new_outport_type,$default_out);
+                set_gui_status($intfc_gen,"refresh",1);
+            });
+            $combochiled->signal_connect('changed' => sub {
+                my ($entry) = @_;
+                $default_out=$entry->get_text();
+                $intfc_gen->intfc_add_port($id,$type,$range,$name,$connect_type,$connect_range,$connect_name,$outport_type,$default_out);
+            });
+            $row++;
+        }#foreach port
+    }
+    return $row;
 }
 
-
-
-
-
-
-
-
-
-
-
-
-
 sub dev_box_show{
-	my($intfc_gen,$info)=@_;
-	
-	my $table = def_table(20,10,FALSE);
-	
-	
-	interface_type_select($intfc_gen,$info,$table,0);	
-	my $row=port_select($intfc_gen,$info,$table,1);	
-	for (my $i=$row; $i<20; $i++){
-		my $temp=gen_label_in_center(" ");
-		#$table->attach_defaults ($temp, 0, 1 , $i, $i+1);
-	}	
-
-
-	my $scrolled_win = add_widget_to_scrolled_win($table);
-	
-	return $scrolled_win;
-	
-}	
-
-
-
+    my($intfc_gen,$info)=@_;
+    my $table = def_table(20,10,FALSE);
+    interface_type_select($intfc_gen,$info,$table,0);
+    my $row=port_select($intfc_gen,$info,$table,1);
+    for (my $i=$row; $i<20; $i++){
+        my $temp=gen_label_in_center(" ");
+        #$table->attach_defaults ($temp, 0, 1 , $i, $i+1);
+    }
+    my $scrolled_win = add_widget_to_scrolled_win($table);
+    return $scrolled_win;
+}
 
 sub check_intfc{
-	my $intfc_gen=shift;
-	my $result;
-	my $message;
-	
-		
-	$result=$intfc_gen->intfc_ckeck_ports_available();
-	if(!defined $result){$message="No port connection has been selected for this interface!";}
-	$result=$intfc_gen->intfc_get_interface_name();
-	if(!defined $result){$message="The interface name is empty!";}
-	$result=$intfc_gen->intfc_get_interface_file();
-	if(!defined $result){$message="The Verilog file containing the interface has not been selected!";}
-	
-	if(!defined $message){return 1;}
-	else {message_dialog($message); return 0;}
-		
-	
-}	
-
-
+    my $intfc_gen=shift;
+    my $result;
+    my $message;
+    $result=$intfc_gen->intfc_ckeck_ports_available();
+    if(!defined $result){$message="No port connection has been selected for this interface!";}
+    $result=$intfc_gen->intfc_get_interface_name();
+    if(!defined $result){$message="The interface name is empty!";}
+    $result=$intfc_gen->intfc_get_interface_file();
+    if(!defined $result){$message="The Verilog file containing the interface has not been selected!";}
+    if(!defined $message){return 1;}
+    else {message_dialog($message); return 0;}
+}
 
 sub generate_lib{
-	my $intfc_gen=shift;
-	my $name=$intfc_gen->intfc_get_interface_name();
-	my $category=$intfc_gen->object_get_attribute('category');
-	# Write
-	if(defined ($category)){
-		open(FILE,  ">lib/interface/$name.ITC") || die "Can not open: $!";
-		print FILE perl_file_header("$name.ITC");
-		print FILE Data::Dumper->Dump([\%$intfc_gen],["HashRef"]);
-		close(FILE) || die "Error closing file: $!";
-		#store \%$intfc_gen, "lib/$name.ITC";
-		
-		my $message="Interface $name has been generated successfully. In order to see this interface in IP generator you need to reset the ProNoC. Do you want to reset the ProNoC now?" ;
-			
-		my $response =  yes_no_dialog($message);
-		if ($response eq 'yes') {
-			exec($^X, $0, @ARGV);# reset ProNoC to apply changes	
-  		}
-  		
-
-		
-	}else{
-		my $message="Category must be defined!";
-		message_dialog($message);
-		
-	}	
-	
-	
-return 1;	
-}	
-
-
+    my $intfc_gen=shift;
+    my $name=$intfc_gen->intfc_get_interface_name();
+    my $category=$intfc_gen->object_get_attribute('category');
+    # Write
+    if(defined ($category)){
+        open(FILE,  ">lib/interface/$name.ITC") || die "Can not open: $!";
+        print FILE perl_file_header("$name.ITC");
+        print FILE Data::Dumper->Dump([\%$intfc_gen],["HashRef"]);
+        close(FILE) || die "Error closing file: $!";
+        #store \%$intfc_gen, "lib/$name.ITC";
+        my $message="Interface $name has been generated successfully. In order to see this interface in IP generator you need to reset the ProNoC. Do you want to reset the ProNoC now?" ;
+        my $response =  yes_no_dialog($message);
+        if ($response eq 'yes') {
+            exec($^X, $0, @ARGV);# reset ProNoC to apply changes
+        }
+    }else{
+        my $message="Category must be defined!";
+        message_dialog($message);
+    }
+return 1;
+}
 
 ###########
-#	get description
+#    get description
 #########
-
 sub get_intfc_description{
-	my ($intfc_gen,$info)=@_;
-	my $description = $intfc_gen->intfc_get_description();	
-	my $table = def_table(15,15,TRUE);
-	my $window=def_popwin_size(50,50,"Add description",'percent');
-	my ($scrwin,$text_view)=create_txview();
-	#my $buffer = $textbox->get_buffer();
-	my $ok=def_image_button("icons/select.png",' Ok ');
-	
-	$table->attach_defaults($scrwin,0,15,0,14);
-	$table->attach_defaults($ok,6,9,14,15);
-	my $text_buffer = $text_view->get_buffer;
-	if(defined $description) {$text_buffer->set_text($description)};
-	
-	$ok->signal_connect("clicked"=> sub {
-		$window->destroy;
-		 
-		 my $text = $text_buffer->get_text($text_buffer->get_bounds, TRUE);
-		 $intfc_gen->intfc_set_description($text);	
-		#print "$text\n";
-		
-	});
-	
-	$window->add($table);
-	$window->show_all();
-	
-}	
-
-
+    my ($intfc_gen,$info)=@_;
+    my $description = $intfc_gen->intfc_get_description();
+    my $table = def_table(15,15,TRUE);
+    my $window=def_popwin_size(50,50,"Add description",'percent');
+    my ($scrwin,$text_view)=create_txview();
+    #my $buffer = $textbox->get_buffer();
+    my $ok=def_image_button("icons/select.png",' Ok ');
+    $table->attach_defaults($scrwin,0,15,0,14);
+    $table->attach_defaults($ok,6,9,14,15);
+    my $text_buffer = $text_view->get_buffer;
+    if(defined $description) {$text_buffer->set_text($description)};
+    $ok->signal_connect("clicked"=> sub {
+        $window->destroy;
+        my $text = $text_buffer->get_text($text_buffer->get_bounds, TRUE);
+        $intfc_gen->intfc_set_description($text);
+        #print "$text\n";
+    });
+    $window->add($table);
+    $window->show_all();
+}
 
 sub load_interface{
-	my ($intfc_gen)=@_;
-	my $file;
-	my $dialog =  gen_file_dialog (undef, 'ITC');
-	my $dir = Cwd::getcwd();
-	$dialog->set_current_folder ("$dir/lib/interface")	;			
-
-
-	if ( "ok" eq $dialog->run ) {
-		$file = $dialog->get_filename;
-		my ($name,$path,$suffix) = fileparse("$file",qr"\..[^.]*$");
-		if($suffix eq '.ITC'){
-			$intfc_gen->intfc_set_interface_file($file);
-			set_gui_status($intfc_gen,"load_file",0);
-		}					
-     }
-     $dialog->destroy;
+    my ($intfc_gen)=@_;
+    my $file;
+    my $dialog =  gen_file_dialog (undef, 'ITC');
+    my $dir = Cwd::getcwd();
+    $dialog->set_current_folder ("$dir/lib/interface")    ;
+    if ( "ok" eq $dialog->run ) {
+        $file = $dialog->get_filename;
+        my ($name,$path,$suffix) = fileparse("$file",qr"\..[^.]*$");
+        if($suffix eq '.ITC'){
+            $intfc_gen->intfc_set_interface_file($file);
+            set_gui_status($intfc_gen,"load_file",0);
+        }
+    }
+    $dialog->destroy;
 }
 
-
-
 ############
 #    main
 ############
 sub intfc_main{
-	
-	my $intfc_gen= intfc_gen->interface_generator();
-	set_gui_status($intfc_gen,"ideal",0);	
-	my $main_table =def_table(15, 12, FALSE);
-
-	$main_table->set_row_spacings (4);
-	$main_table->set_col_spacings (1);
-	# The box which holds the info, warning, error ...  mesages
-	my ($infobox,$info)= create_txview();	
-	
-	
-	my $generate = def_image_button('icons/gen.png','Generate');
-	
-
-
-	my $fbox=file_box($intfc_gen,$info);	
-	my $sbox=module_select($intfc_gen,$info);	
-	
-	
-	my $devbox=dev_box_show($intfc_gen,$info);
-	
-	#$main_table->attach_defaults ($fbox , 0, 12, 0,1);
-	#$main_table->attach_defaults ($sbox , 0, 12, 1,2);
-	#$main_table->attach_defaults ($devbox , 0, 12, 2,12);
-	#$main_table->attach_defaults ($infobox  , 0, 12, 12,14);
+    my $intfc_gen= intfc_gen->interface_generator();
+    set_gui_status($intfc_gen,"ideal",0);
+    my $main_table =def_table(15, 12, FALSE);
+    $main_table->set_row_spacings (4);
+    $main_table->set_col_spacings (1);
+    # The box which holds the info, warning, error ...  mesages
+    my ($infobox,$info)= create_txview();
+    my $generate = def_image_button('icons/gen.png','Generate');
+    my $fbox=file_box($intfc_gen,$info);
+    my $sbox=module_select($intfc_gen,$info);
+    my $devbox=dev_box_show($intfc_gen,$info);
+    #$main_table->attach_defaults ($fbox , 0, 12, 0,1);
+    #$main_table->attach_defaults ($sbox , 0, 12, 1,2);
+    #$main_table->attach_defaults ($devbox , 0, 12, 2,12);
+    #$main_table->attach_defaults ($infobox  , 0, 12, 12,14);
     my $table=def_table(2,11,FALSE);
     $table->attach($fbox,0,11,0,1,'fill','shrink',2,2);
-	$table->attach($sbox,0,11,1,2,'fill','shrink',2,2);
-    
-	#my $v1=def_pack_vbox(TRUE,0,$fbox,$sbox);
-	my $v2=gen_vpaned($table,.12,$devbox);
-	my $v3=gen_vpaned($v2,.6,$infobox);
-	$main_table->attach_defaults ($v3  , 0, 12, 0,14);
-
-
-	$main_table->attach ($generate	, 6, 8, 14,15,'shrink','shrink',2,2);
-
-
-	my $open = def_image_button('icons/browse.png','Load Interface');
-	my $openbox=def_hbox(TRUE,0);
-	$openbox->pack_start($open,   FALSE, FALSE,0);
-	$main_table->attach ($openbox,0, 2, 14,15,'shrink','shrink',2,2);
-
-	
-
-
-
-
-	#check soc status every 0.5 second. referesh gui if there is any changes 
-Glib::Timeout->add (100, sub{ 
-	 
-		my ($state,$timeout)= get_gui_status($intfc_gen);
-		if ($timeout>0){
-			$timeout--;
-			set_gui_status($intfc_gen,$state,$timeout);		
-		}
-		elsif($state eq "load_file"){
-			my $file=$intfc_gen->intfc_get_interface_file();
-			my ($pp,$r,$err) = regen_object($file);
-			if ($r){		
-				add_info($info,"**Error reading  $file file: $err\n");
-				return;
-			} 			
-			clone_obj($intfc_gen,$pp);
-			show_info($info,"$file is loaded!\n ");			
-			set_gui_status($intfc_gen,"ref",1);
-			
-			
-		}
-		elsif( $state ne "ideal" ){
-			$devbox->destroy();
-			$fbox->destroy();
-			$sbox->destroy();
-			
-			select(undef, undef, undef, 0.1); #wait 10 ms
-			$devbox=dev_box_show($intfc_gen,$info);
-			$fbox=file_box($intfc_gen,$info);	
-			$sbox=module_select($intfc_gen,$info);
-			$table->attach($fbox,0,11,0,1,'fill','shrink',2,2);
-			$table->attach($sbox,0,11,1,2,'fill','shrink',2,2);
-			
-			$v2->pack2($devbox,TRUE, TRUE); 	
-			$v3-> pack1($v2, TRUE, TRUE); 	
-			#$main_table->attach_defaults ($v3  , 0, 12, 0,14);				
-			$v3->show_all();
-			set_gui_status($intfc_gen,"ideal",0);
-			
-		}	
-		return TRUE;
-		
-		} );
-	
-	$open-> signal_connect("clicked" => sub{ 
-		load_interface($intfc_gen);
-	
-	});		
-		
-	$generate-> signal_connect("clicked" => sub{ 
-		if( check_intfc($intfc_gen)) {
-			generate_lib($intfc_gen); 
-			
-		}
-		set_gui_status($intfc_gen,"ref",1);
-		
-	
-});
-
-	#show_selected_dev($info,\@active_dev,\$dev_list_refresh,\$dev_table);
-
-
-
-#$box->show;
-	#$window->add ($main_table);
-	#$window->show_all;
-	#return $main_table;
-
-
-	return  add_widget_to_scrolled_win($main_table);
-
+    $table->attach($sbox,0,11,1,2,'fill','shrink',2,2);
+    #my $v1=def_pack_vbox(TRUE,0,$fbox,$sbox);
+    my $v2=gen_vpaned($table,.12,$devbox);
+    my $v3=gen_vpaned($v2,.6,$infobox);
+    $main_table->attach_defaults ($v3  , 0, 12, 0,14);
+    $main_table->attach ($generate    , 6, 8, 14,15,'shrink','shrink',2,2);
+    my $open = def_image_button('icons/browse.png','Load Interface');
+    my $openbox=def_hbox(TRUE,0);
+    $openbox->pack_start($open,   FALSE, FALSE,0);
+    $main_table->attach ($openbox,0, 2, 14,15,'shrink','shrink',2,2);
+    #check soc status every 0.5 second. referesh gui if there is any changes
+    Glib::Timeout->add (100, sub{
+        my ($state,$timeout)= get_gui_status($intfc_gen);
+        if ($timeout>0){
+            $timeout--;
+            set_gui_status($intfc_gen,$state,$timeout);
+        }
+        elsif($state eq "load_file"){
+            my $file=$intfc_gen->intfc_get_interface_file();
+            my ($pp,$r,$err) = regen_object($file);
+            if ($r){
+                add_info($info,"**Error reading  $file file: $err\n");
+                return;
+            }
+            clone_obj($intfc_gen,$pp);
+            show_info($info,"$file is loaded!\n ");
+            set_gui_status($intfc_gen,"ref",1);
+        }
+        elsif( $state ne "ideal" ){
+            $devbox->destroy();
+            $fbox->destroy();
+            $sbox->destroy();
+            select(undef, undef, undef, 0.1); #wait 10 ms
+            $devbox=dev_box_show($intfc_gen,$info);
+            $fbox=file_box($intfc_gen,$info);
+            $sbox=module_select($intfc_gen,$info);
+            $table->attach($fbox,0,11,0,1,'fill','shrink',2,2);
+            $table->attach($sbox,0,11,1,2,'fill','shrink',2,2);
+            $v2->pack2($devbox,TRUE, TRUE);
+            $v3-> pack1($v2, TRUE, TRUE);
+            #$main_table->attach_defaults ($v3  , 0, 12, 0,14);
+            $v3->show_all();
+            set_gui_status($intfc_gen,"ideal",0);
+        }
+        return TRUE;
+        } );
+    $open-> signal_connect("clicked" => sub{
+        load_interface($intfc_gen);
+    });
+    $generate-> signal_connect("clicked" => sub{
+        if( check_intfc($intfc_gen)) {
+            generate_lib($intfc_gen);
+        }
+        set_gui_status($intfc_gen,"ref",1);
+    });
+    #show_selected_dev($info,\@active_dev,\$dev_list_refresh,\$dev_table);
+    #$box->show;
+    #$window->add ($main_table);
+    #$window->show_all;
+    #return $main_table;
+    return  add_widget_to_scrolled_win($main_table);
 }
-
-
-
-
-
-1
-
+1;
\ No newline at end of file
diff --git a/mpsoc/perl_gui/lib/perl/intfc_gen.pm b/mpsoc/perl_gui/lib/perl/intfc_gen.pm
index 01a1d77..a1a29f7 100755
--- a/mpsoc/perl_gui/lib/perl/intfc_gen.pm
+++ b/mpsoc/perl_gui/lib/perl/intfc_gen.pm
@@ -2,68 +2,58 @@
 ###############################################################################
 #
 # File:         interface.pm
-# 
+#
 #
 ###############################################################################
 use warnings;
 use strict;
-
-
-
 package intfc_gen;
 
 sub uniq {
-  my %seen;
-  return grep { !$seen{$_}++ } @_;
+    my %seen;
+    return grep { !$seen{$_}++ } @_;
 }
 
-
 sub interface_generator {
 		my $class = "intfc_gen";
 		my $self;
 		$self->{file_name}=();
 		$self->{modules}={};
 		$self->{module_name}=();
-		$self->{type}=();	
+		$self->{type}=();
 		$self->{name}=();
 		bless($self,$class);
 		return $self;
-}	
+}
 
 sub intfc_set_interface_file {
 	my ($self,$file)= @_;
-	if (defined $file){ 
+	if (defined $file){
 		#print "file name has been changed to $file\n";
 		$self->{file_name}=$file;
 		#delete old data
 		if(exists ($self->{modules})) {delete $self->{modules}; } ;
 		if(exists ($self->{module_name})) {delete $self->{module_name}; } ;
 		if(exists ($self->{ports})){ delete $self->{ports}};
-		
-		
-		
 		}
-}	
+}
 
 sub intfc_get_interface_file {
 	my ($self)=@_;
 	my $file;
 	if (exists ($self->{file_name})){
-		$file=$self->{file_name};	
+		$file=$self->{file_name};
 	}
-	return $file;	
-}	
+	return $file;
+}
 
 sub intfc_add_module_list{
 		my ($self,@list)=@_;
 		$self->{modules}={};
-		foreach my $p(@list) {			
-			$self->{modules}{$p}={};	
-			
+		foreach my $p(@list) {
+			$self->{modules}{$p}={};
 		}
-	
-}	
-
+}
 
 sub intfc_get_module_list{
 		my ($self)=@_;
@@ -71,43 +61,40 @@ sub intfc_get_module_list{
 		if(exists($self->{modules})){
 			@modules=keys %{$self->{modules}};
 		}
-		return @modules;	
-}	
+		return @modules;
+}
 
 sub intfc_set_module_name{
-	my ($self,$module)= @_;	
+	my ($self,$module)= @_;
 	$self->{module_name}=$module;
-	if(exists ($self->{ports})){ delete $self->{ports}};		
-}	
+	if(exists ($self->{ports})){ delete $self->{ports}};
+}
 
 sub intfc_remove_ports{
 	my $self=shift;
 	if(exists ($self->{ports})){ delete $self->{ports}};
 }
 
-
-
 sub intfc_get_module_name {
 	my ($self)=@_;
 	my $module;
 	if (exists ($self->{module_name})){
-		$module=$self->{module_name};	
+		$module=$self->{module_name};
 	}
-	return $module;	
-}	
-
+	return $module;
+}
 
 sub intfc_add_port{
 	my ($self,$port_id,$type,$range,$name,$connect_type,$connect_range,$connect_name,$outport_type,$default_out)=@_;
 	$self->{ports}{$port_id}{name}=$name;
 	$self->{ports}{$port_id}{range}=$range;
 	$self->{ports}{$port_id}{type}=$type;
-	$self->{ports}{$port_id}{connect_name}=$connect_name;	
+	$self->{ports}{$port_id}{connect_name}=$connect_name;
 	$self->{ports}{$port_id}{connect_range}=$connect_range;
-	$self->{ports}{$port_id}{connect_type}=$connect_type;	
+	$self->{ports}{$port_id}{connect_type}=$connect_type;
 	$self->{ports}{$port_id}{outport_type}=$outport_type;
-	$self->{ports}{$port_id}{default_out}=$default_out;	
-}	
+	$self->{ports}{$port_id}{default_out}=$default_out;
+}
 
 sub intfc_get_ports{
 	my ($self,$types_ref,$ranges_ref,$names_ref,$connect_types_ref,$connect_ranges_ref,$connect_name_ref,$outport_type_ref,$default_out_ref)=@_;
@@ -130,16 +117,14 @@ sub intfc_ckeck_ports_available{
 	my $result;
 	if(exists ($self->{ports})){$result=1;}
 	return $result;
-	
-}	
+}
 
 sub intfc_remove_port{
 		my ($self,$port_id)=@_;
 		if(exists ($self->{ports}{$port_id})){
 			delete $self->{ports}{$port_id};
-		}	
-}	
-
+		}
+}
 
 sub intfc_get_ports_type{
 	my ($self)=@_;
@@ -147,18 +132,15 @@ sub intfc_get_ports_type{
 	if(exists ($self->{ports})){
 		foreach my $p (sort keys %{$self->{ports}}){
 			$ports_type{$p}= $self->{ports}{$p}{type};
-			
 		}
 	}
 	return %ports_type;
-}	
-
-
+}
 
 sub intfc_set_interface_name{
 	my ($self,$name)=@_;
 	$self->{name}=$name;
-}	
+}
 
 sub intfc_get_interface_name {
 	my ($self)=@_;
@@ -169,15 +151,11 @@ sub intfc_get_interface_name {
 	return $name;
 }
 
-
-
-
 sub intfc_set_interface_type {
 	my ($self,$intfc_type)=@_;
 	$self->{type}=$intfc_type;
 }
 
-
 sub intfc_get_interface_type {
 	my ($self)=@_;
 	my $type;
@@ -187,13 +165,11 @@ sub intfc_get_interface_type {
 	return $type;
 }
 
-
 sub intfc_set_connection_num {
 	my ($self,$connection_num)=@_;
 	$self->{connection_num}=$connection_num;
 }
 
-
 sub intfc_get_connection_num {
 	my ($self)=@_;
 	my $connection_num;
@@ -203,42 +179,30 @@ sub intfc_get_connection_num {
 	return $connection_num;
 }
 
-
-
-
-
 sub intfc_set_description{
 	my  ($self,$description)=@_;
-	$self->{description}=$description;	
+	$self->{description}=$description;
 }
-	
-
 
 sub intfc_get_description{
-my ($self)=@_;
+	my ($self)=@_;
 	my $des;
 	if(exists ($self->{description})){
 		$des=$self->{description};
 	}
 	return $des;
-}	
-
-
-
+}
 
 sub object_add_attribute{
 	my ($self,$attribute1,$attribute2,$value)=@_;
 	if(!defined $attribute2){$self->{$attribute1}=$value;}
 	else {$self->{$attribute1}{$attribute2}=$value;}
-
 }
 
 sub object_get_attribute{
 	my ($self,$attribute1,$attribute2)=@_;
 	if(!defined $attribute2) {return $self->{$attribute1};}
 	return $self->{$attribute1}{$attribute2};
-
-
 }
 
 sub object_add_attribute_order{
@@ -247,7 +211,7 @@ sub object_add_attribute_order{
 	my @a;
 	@a = @{$r} if(defined $r);
 	push (@a,@param);
-	@a=uniq(@a);	
+	@a=uniq(@a);
 	$self->{'parameters_order'}{$attribute} =\@a;
 }
 
@@ -255,9 +219,4 @@ sub object_get_attribute_order{
 	my ($self,$attribute)=@_;
 	return @{$self->{parameters_order}{$attribute}};
 }
-	
-
-
-
-
-1
+1;
\ No newline at end of file
diff --git a/mpsoc/perl_gui/lib/perl/ip.pm b/mpsoc/perl_gui/lib/perl/ip.pm
index 614ec81..8043633 100755
--- a/mpsoc/perl_gui/lib/perl/ip.pm
+++ b/mpsoc/perl_gui/lib/perl/ip.pm
@@ -2,7 +2,7 @@
 ###############################################################################
 #
 # File:         ip.pm
-# 
+#
 #
 ###############################################################################
 use warnings;
@@ -11,484 +11,374 @@ use FindBin;
 use lib $FindBin::Bin;
 use ip_gen;
 use Cwd;
-
-
 package ip;
 
-
 sub lib_new {
-	
     my $class = ("ARRAY" eq ref $_[0]) ? "ip" : shift;
     my $self;
     $self = {};
-  	my $dir = Cwd::getcwd();
-	$dir =~ s/ /\\ /g;
-	my @files = glob "$dir/lib/ip/*/*.IP";
-	for my $p (@files){
-		
-		# Read
-		my  $ipgen;
-		$ipgen = eval { do $p };
-		# Might need "no strict;" before and "use strict;" after "do"
-		 if ($@ || !defined $ipgen){		
-			print  "\n**Warning: skipping  $p file due to error in reading: $@\n";
-		       next; 
-		} 
-			add_ip($self,$ipgen);
-		
-	}
-  
-
+    my $dir = Cwd::getcwd();
+    $dir =~ s/ /\\ /g;
+    my @files = glob "$dir/lib/ip/*/*.IP";
+    for my $p (@files){
+        # Read
+        my  $ipgen;
+        $ipgen = eval { do $p };
+        # Might need "no strict;" before and "use strict;" after "do"
+        if ($@ || !defined $ipgen){
+            print  "\n**Warning: skipping  $p file due to error in reading: $@\n";
+            next;
+        }
+            add_ip($self,$ipgen);
+    }
     bless($self,$class);
-
-   
     return $self;
-} 
-
+}
 
 sub ip_add_parameter {
-	my ($self,$category,$module,$parameter,$default,$type,$content,$info,$glob_param,$redefine_param)=@_;
-	if (!defined($category) ) {return 0;} 
-	if ( exists ($self->{categories}{$category}{names}{$module}) ){
-		$self->{categories}{$category}{names}{$module}{parameters}{$parameter}={};
-		$self->{categories}{$category}{names}{$module}{parameters}{$parameter}{"default"}=$default;
-		$self->{categories}{$category}{names}{$module}{parameters}{$parameter}{type}=$type;
-		$self->{categories}{$category}{names}{$module}{parameters}{$parameter}{content}=$content;
-		$self->{categories}{$category}{names}{$module}{parameters}{$parameter}{info}=$info;
-		$self->{categories}{$category}{names}{$module}{parameters}{$parameter}{glob_param}=$glob_param;
-		$self->{categories}{$category}{names}{$module}{parameters}{$parameter}{redefine_param}=$redefine_param;
-	}
+    my ($self,$category,$module,$parameter,$default,$type,$content,$info,$glob_param,$redefine_param)=@_;
+    if (!defined($category) ) {return 0;}
+    if ( exists ($self->{categories}{$category}{names}{$module}) ){
+        $self->{categories}{$category}{names}{$module}{parameters}{$parameter}={};
+        $self->{categories}{$category}{names}{$module}{parameters}{$parameter}{"default"}=$default;
+        $self->{categories}{$category}{names}{$module}{parameters}{$parameter}{type}=$type;
+        $self->{categories}{$category}{names}{$module}{parameters}{$parameter}{content}=$content;
+        $self->{categories}{$category}{names}{$module}{parameters}{$parameter}{info}=$info;
+        $self->{categories}{$category}{names}{$module}{parameters}{$parameter}{glob_param}=$glob_param;
+        $self->{categories}{$category}{names}{$module}{parameters}{$parameter}{redefine_param}=$redefine_param;
+    }
 }
 
-
 sub ip_remove_parameter {
-	my ($self,$category,$module,$parameter)=@_;
-	if (!defined($category) ) {return 0;} 
-	if ( exists ($self->{categories}{$category}{names}{$module}) ){
-		delete $self->{categories}{$category}{names}{$module}{parameters}{$parameter};
-		
-	}else{ return 0;}
-	return 1;
+    my ($self,$category,$module,$parameter)=@_;
+    if (!defined($category) ) {return 0;}
+    if ( exists ($self->{categories}{$category}{names}{$module}) ){
+        delete $self->{categories}{$category}{names}{$module}{parameters}{$parameter};
+    }else{ return 0;}
+    return 1;
 }
 
-
-
 sub ip_get_parameter {
-	my ($self,$category,$module,$parameter)=@_;
-	my ($default,$type,$content,$info,$glob_param,$redefine_param);
-	if ( exists ($self->{categories}{$category}{names}{$module}) ){
-		$default	=$self->{categories}{$category}{names}{$module}{parameters}{$parameter}{"default"};
-		$type		=$self->{categories}{$category}{names}{$module}{parameters}{$parameter}{type};
-		$content	=$self->{categories}{$category}{names}{$module}{parameters}{$parameter}{content};
-		$info		=$self->{categories}{$category}{names}{$module}{parameters}{$parameter}{info};
-		$glob_param	=$self->{categories}{$category}{names}{$module}{parameters}{$parameter}{glob_param};
-		$redefine_param	=$self->{categories}{$category}{names}{$module}{parameters}{$parameter}{redefine_param};
-	}
-	return ($default,$type,$content,$info,$glob_param,$redefine_param); 
+    my ($self,$category,$module,$parameter)=@_;
+    my ($default,$type,$content,$info,$glob_param,$redefine_param);
+    if ( exists ($self->{categories}{$category}{names}{$module}) ){
+        $default    =$self->{categories}{$category}{names}{$module}{parameters}{$parameter}{"default"};
+        $type        =$self->{categories}{$category}{names}{$module}{parameters}{$parameter}{type};
+        $content    =$self->{categories}{$category}{names}{$module}{parameters}{$parameter}{content};
+        $info        =$self->{categories}{$category}{names}{$module}{parameters}{$parameter}{info};
+        $glob_param    =$self->{categories}{$category}{names}{$module}{parameters}{$parameter}{glob_param};
+        $redefine_param    =$self->{categories}{$category}{names}{$module}{parameters}{$parameter}{redefine_param};
+    }
+    return ($default,$type,$content,$info,$glob_param,$redefine_param);
 }
 
-
 sub ip_add_socket {
-	my ($self,$category,$module,$interface,$type,$value,$connection_num)=@_;
-	if ( exists ($self->{categories}{$category}{names}{$module}) ){
-		$self->{categories}{$category}{names}{$module}{sockets}{$interface}{type}=$type;
-		$self->{categories}{$category}{names}{$module}{sockets}{$interface}{value}=$value;
-		if(defined $connection_num){$self->{categories}{$category}{names}{$module}{sockets}{$interface}{connection_num}=$connection_num;}
-		
-		
-	}
+    my ($self,$category,$module,$interface,$type,$value,$connection_num)=@_;
+    if ( exists ($self->{categories}{$category}{names}{$module}) ){
+        $self->{categories}{$category}{names}{$module}{sockets}{$interface}{type}=$type;
+        $self->{categories}{$category}{names}{$module}{sockets}{$interface}{value}=$value;
+        if(defined $connection_num){$self->{categories}{$category}{names}{$module}{sockets}{$interface}{connection_num}=$connection_num;}
+    }
 }
 
-
 sub ip_get_socket {
-	my ($self,$category,$module,$socket)=@_;
-	my ($type,$value,$connection_num);
-	if ( exists ($self->{categories}{$category}{names}{$module}) ){
-		$type			=$self->{categories}{$category}{names}{$module}{sockets}{$socket}{type};
-		$value			=$self->{categories}{$category}{names}{$module}{sockets}{$socket}{value};
-		$connection_num	=$self->{categories}{$category}{names}{$module}{sockets}{$socket}{connection_num};
-	}
-	return ($type,$value,$connection_num);
+    my ($self,$category,$module,$socket)=@_;
+    my ($type,$value,$connection_num);
+    if ( exists ($self->{categories}{$category}{names}{$module}) ){
+        $type            =$self->{categories}{$category}{names}{$module}{sockets}{$socket}{type};
+        $value            =$self->{categories}{$category}{names}{$module}{sockets}{$socket}{value};
+        $connection_num    =$self->{categories}{$category}{names}{$module}{sockets}{$socket}{connection_num};
+    }
+    return ($type,$value,$connection_num);
 }
 
 sub ip_get_module_sockets_list {
-	my ($self,$category,$module)=@_;
-	my @r;	
-	if ( exists ($self->{categories}{$category}{names}{$module}) ){
-		foreach my $p (sort keys %{$self->{categories}{$category}{names}{$module}{sockets}}){
-			push (@r,$p);
-		}
-	}
-	return @r;
-}	
-
-
+    my ($self,$category,$module)=@_;
+    my @r;
+    if ( exists ($self->{categories}{$category}{names}{$module}) ){
+        foreach my $p (sort keys %{$self->{categories}{$category}{names}{$module}{sockets}}){
+            push (@r,$p);
+        }
+    }
+    return @r;
+}
 
 sub ip_add_plug {
-	my ($self,$category,$module,$interface,$type,$value,$connection_num)=@_;
-	if ( exists ($self->{categories}{$category}{names}{$module}) ){
-		$self->{categories}{$category}{names}{$module}{plugs}{$interface}{type}=$type;
-		$self->{categories}{$category}{names}{$module}{plugs}{$interface}{value}=$value;
-		if(defined $connection_num){ $self->{categories}{$category}{names}{$module}{plugs}{$interface}{connection_num}=$connection_num;}
-		
-	}
+    my ($self,$category,$module,$interface,$type,$value,$connection_num)=@_;
+    if ( exists ($self->{categories}{$category}{names}{$module}) ){
+        $self->{categories}{$category}{names}{$module}{plugs}{$interface}{type}=$type;
+        $self->{categories}{$category}{names}{$module}{plugs}{$interface}{value}=$value;
+        if(defined $connection_num){ $self->{categories}{$category}{names}{$module}{plugs}{$interface}{connection_num}=$connection_num;}
+    }
 }
 
 sub ip_get_plug {
-	my ($self,$category,$module,$plug)=@_;
-	my ($type,$value,$connection_num);
-	if ( exists ($self->{categories}{$category}{names}{$module}) ){
-		$type			=$self->{categories}{$category}{names}{$module}{plugs}{$plug}{type};
-		$value			=$self->{categories}{$category}{names}{$module}{plugs}{$plug}{value};
-		$connection_num	=$self->{categories}{$category}{names}{$module}{plugs}{$plug}{connection_num};
-	}
-	return ($type,$value,$connection_num);
+    my ($self,$category,$module,$plug)=@_;
+    my ($type,$value,$connection_num);
+    if ( exists ($self->{categories}{$category}{names}{$module}) ){
+        $type            =$self->{categories}{$category}{names}{$module}{plugs}{$plug}{type};
+        $value            =$self->{categories}{$category}{names}{$module}{plugs}{$plug}{value};
+        $connection_num    =$self->{categories}{$category}{names}{$module}{plugs}{$plug}{connection_num};
+    }
+    return ($type,$value,$connection_num);
 }
 
 sub ip_get_module_plugs_list {
-	my ($self,$category,$module)=@_;
-	my @r;	
-	if ( exists ($self->{categories}{$category}{names}{$module}) ){
-		foreach my $p (sort keys %{$self->{categories}{$category}{names}{$module}{plugs}}){
-			push (@r,$p);
-		}
-	}
-	return @r;
-}	
-	
-	
-	
-
+    my ($self,$category,$module)=@_;
+    my @r;
+    if ( exists ($self->{categories}{$category}{names}{$module}) ){
+        foreach my $p (sort keys %{$self->{categories}{$category}{names}{$module}{plugs}}){
+            push (@r,$p);
+        }
+    }
+    return @r;
+}
 
 sub ip_add_port{
-	my ($self,$category,$module,$port,$type,$range,$intfc_name,$intfc_port)=@_;
-	if (!defined($category) ) {return 0;} 
-	if ( exists ($self->{categories}{$category}{names}{$module}) ){
-		$self->{categories}{$category}{names}{$module}{ports}{$port}={};
-		$self->{categories}{$category}{names}{$module}{ports}{$port}{type}=$type;
-		$self->{categories}{$category}{names}{$module}{ports}{$port}{range}=$range;
-		$self->{categories}{$category}{names}{$module}{ports}{$port}{intfc_name}=$intfc_name;
-		$self->{categories}{$category}{names}{$module}{ports}{$port}{intfc_port}=$intfc_port;
-	}
+    my ($self,$category,$module,$port,$type,$range,$intfc_name,$intfc_port)=@_;
+    if (!defined($category) ) {return 0;}
+    if ( exists ($self->{categories}{$category}{names}{$module}) ){
+        $self->{categories}{$category}{names}{$module}{ports}{$port}={};
+        $self->{categories}{$category}{names}{$module}{ports}{$port}{type}=$type;
+        $self->{categories}{$category}{names}{$module}{ports}{$port}{range}=$range;
+        $self->{categories}{$category}{names}{$module}{ports}{$port}{intfc_name}=$intfc_name;
+        $self->{categories}{$category}{names}{$module}{ports}{$port}{intfc_port}=$intfc_port;
+    }
 }
 
-
 sub ip_get_port{
-	my ($self,$category,$module,$port)=@_;
-	my ($type,$range,$intfc_name,$intfc_port);
-	if ( exists ($self->{categories}{$category}{names}{$module}{ports}{$port}) ){
-		$type		=$self->{categories}{$category}{names}{$module}{ports}{$port}{type};
-		$range		=$self->{categories}{$category}{names}{$module}{ports}{$port}{range};
-		$intfc_name	=$self->{categories}{$category}{names}{$module}{ports}{$port}{intfc_name};
-		$intfc_port	=$self->{categories}{$category}{names}{$module}{ports}{$port}{intfc_port};
-	}
-	return ($type,$range,$intfc_name,$intfc_port);
+    my ($self,$category,$module,$port)=@_;
+    my ($type,$range,$intfc_name,$intfc_port);
+    if ( exists ($self->{categories}{$category}{names}{$module}{ports}{$port}) ){
+        $type        =$self->{categories}{$category}{names}{$module}{ports}{$port}{type};
+        $range        =$self->{categories}{$category}{names}{$module}{ports}{$port}{range};
+        $intfc_name    =$self->{categories}{$category}{names}{$module}{ports}{$port}{intfc_name};
+        $intfc_port    =$self->{categories}{$category}{names}{$module}{ports}{$port}{intfc_port};
+    }
+    return ($type,$range,$intfc_name,$intfc_port);
 }
 
 sub ip_list_ports{
-	my ($self,$category,$module)=@_;
-	my @ports;
-	
-	if ( exists ($self->{categories}{$category}{names}{$module}) ){
-		
-		foreach my $p (sort keys %{$self->{categories}{$category}{names}{$module}{ports}}){
-			push (@ports,$p);
-		}
-	}
-	return @ports;
+    my ($self,$category,$module)=@_;
+    my @ports;
+    if ( exists ($self->{categories}{$category}{names}{$module}) ){
+        foreach my $p (sort keys %{$self->{categories}{$category}{names}{$module}{ports}}){
+            push (@ports,$p);
+        }
+    }
+    return @ports;
 }
 
-
-
 sub ip_get_categories{
-	my $self=shift;
-	my @r;	
-	if  (exists ($self->{categories})){
-		foreach my $p (sort keys %{$self->{categories}}){
-			push (@r,$p);
-		}
-	}
-	return @r;
+    my $self=shift;
+    my @r;
+    if  (exists ($self->{categories})){
+        foreach my $p (sort keys %{$self->{categories}}){
+            push (@r,$p);
+        }
+    }
+    return @r;
 }
 
-
 sub get_modules{
-	my ($self,$category)=@_;
-	my @r;
-	if  (exists ($self->{categories}{$category})){
-		foreach my $p (sort keys %{$self->{categories}{$category}{names}}){
-			push (@r,$p);
-		}
-	}
-	return @r;
+    my ($self,$category)=@_;
+    my @r;
+    if  (exists ($self->{categories}{$category})){
+        foreach my $p (sort keys %{$self->{categories}{$category}{names}}){
+            push (@r,$p);
+        }
+    }
+    return @r;
 }
 
-
 sub get_param_default{
-	my ($self,$category,$module)=@_;
-	my %r;
-	if (!defined($module) ) {return %r;} 
-	foreach my $p (sort keys %{$self->{categories}{$category}{names}{$module}{parameters}}){
-			$r{$p}=$self->{categories}{$category}{names}{$module}{parameters}{$p}{"default"};
-			#print "$p=$r{$p}\n";
-		}
-	return %r;
-
+    my ($self,$category,$module)=@_;
+    my %r;
+    if (!defined($module) ) {return %r;}
+    foreach my $p (sort keys %{$self->{categories}{$category}{names}{$module}{parameters}}){
+            $r{$p}=$self->{categories}{$category}{names}{$module}{parameters}{$p}{"default"};
+            #print "$p=$r{$p}\n";
+        }
+    return %r;
 }
 
-
-
 sub ip_add_socket_names{
-	my($self,$ipgen,$category,$module, $socket)=@_;
-	my $num=0;
-	if ( exists ($self->{categories}{$category}{names}{$module}) ){
-		
-		my $name=	$ipgen->ipgen_get_socket_name($socket,$num);
-		do{
-			$self->{categories}{$category}{names}{$module}{sockets}{$socket}{$num}{name}=$name;
-			++$num;
-			$name=	$ipgen->ipgen_get_socket_name($socket,$num);
-		}while(defined $name);
-	
-	}
-}		
+    my($self,$ipgen,$category,$module, $socket)=@_;
+    my $num=0;
+    if ( exists ($self->{categories}{$category}{names}{$module}) ){
+        my $name=    $ipgen->ipgen_get_socket_name($socket,$num);
+        do{
+            $self->{categories}{$category}{names}{$module}{sockets}{$socket}{$num}{name}=$name;
+            ++$num;
+            $name=    $ipgen->ipgen_get_socket_name($socket,$num);
+        }while(defined $name);
+    }
+}
 
 sub ip_get_socket_name{
-	my($self,$category,$module, $socket,$num)=@_;
-	my $name;
-	if ( exists (   $self->{categories}{$category}{names}{$module}{sockets}{$socket}{$num}{name}) ){
-		$name=	$self->{categories}{$category}{names}{$module}{sockets}{$socket}{$num}{name};
-		
-	}
-	return $name;
-}		
-
-
+    my($self,$category,$module, $socket,$num)=@_;
+    my $name;
+    if ( exists (   $self->{categories}{$category}{names}{$module}{sockets}{$socket}{$num}{name}) ){
+        $name=    $self->{categories}{$category}{names}{$module}{sockets}{$socket}{$num}{name};
+    }
+    return $name;
+}
 
 sub ip_add_plug_names{
-	my($self,$ipgen,$category,$module, $plug)=@_;
-	my $num=0;
-	if ( exists ($self->{categories}{$category}{names}{$module}) ){
-		
-		my $name=	$ipgen->ipgen_get_plug_name($plug,$num);
-		do{
-			$self->{categories}{$category}{names}{$module}{plugs}{$plug}{$num}{name}=$name;
-			my ($addr,$width)= $ipgen->ipgen_get_wb_addr($plug,$num);
-			if (defined $addr){
-					$self->{categories}{$category}{names}{$module}{plugs}{$plug}{$num}{addr}=$addr;
-					$self->{categories}{$category}{names}{$module}{plugs}{$plug}{$num}{width}=$width;
-			}	
-			++$num;
-			$name=	$ipgen->ipgen_get_plug_name($plug,$num);
-				
-			
-		}while(defined $name);
-	
-	}	
+    my($self,$ipgen,$category,$module, $plug)=@_;
+    my $num=0;
+    if ( exists ($self->{categories}{$category}{names}{$module}) ){
+        my $name=    $ipgen->ipgen_get_plug_name($plug,$num);
+        do{
+            $self->{categories}{$category}{names}{$module}{plugs}{$plug}{$num}{name}=$name;
+            my ($addr,$width)= $ipgen->ipgen_get_wb_addr($plug,$num);
+            if (defined $addr){
+                    $self->{categories}{$category}{names}{$module}{plugs}{$plug}{$num}{addr}=$addr;
+                    $self->{categories}{$category}{names}{$module}{plugs}{$plug}{$num}{width}=$width;
+            }
+            ++$num;
+            $name=    $ipgen->ipgen_get_plug_name($plug,$num);
+        }while(defined $name);
+    }
 }
 
 sub ip_get_wb_addr{
-	my($self,$category,$module,$plug,$num)=@_;
-	my ($addr , $width); 
-	if(exists($self->{categories}{$category}{names}{$module}{plugs}{$plug}{$num}{addr})){
-		$addr  = $self->{categories}{$category}{names}{$module}{plugs}{$plug}{$num}{addr};
-		$width = $self->{categories}{$category}{names}{$module}{plugs}{$plug}{$num}{width};
-	}
-	return ($addr , $width); 
-}	
-
-
+    my($self,$category,$module,$plug,$num)=@_;
+    my ($addr , $width);
+    if(exists($self->{categories}{$category}{names}{$module}{plugs}{$plug}{$num}{addr})){
+        $addr  = $self->{categories}{$category}{names}{$module}{plugs}{$plug}{$num}{addr};
+        $width = $self->{categories}{$category}{names}{$module}{plugs}{$plug}{$num}{width};
+    }
+    return ($addr , $width);
+}
 
 sub ip_get_plug_name{
-	my($self,$category,$module, $plug,$num)=@_;
-	my $name;
-	if ( exists ($self->{categories}{$category}{names}{$module}{plugs}{$plug}{$num}{name})){
-		$name=$self->{categories}{$category}{names}{$module}{plugs}{$plug}{$num}{name};
-	}
-	return $name;
+    my($self,$category,$module, $plug,$num)=@_;
+    my $name;
+    if ( exists ($self->{categories}{$category}{names}{$module}{plugs}{$plug}{$num}{name})){
+        $name=$self->{categories}{$category}{names}{$module}{plugs}{$plug}{$num}{name};
+    }
+    return $name;
 }
 
-
-
-
 sub get_module_sokets_value{
-	my ($self,$category,$module)=@_;
-	if (!defined($category) ) {return 0;} 
-	my %r;
-	if ( exists ($self->{categories}{$category}{names}{$module}) ){
-		foreach my $p (sort keys %{$self->{categories}{$category}{names}{$module}{sockets}}){
-			$r{$p}=$self->{categories}{$category}{names}{$module}{sockets}{$p}{value};
-		}
-		
-	}
-	return %r;	
-}	
-
+    my ($self,$category,$module)=@_;
+    if (!defined($category) ) {return 0;}
+    my %r;
+    if ( exists ($self->{categories}{$category}{names}{$module}) ){
+        foreach my $p (sort keys %{$self->{categories}{$category}{names}{$module}{sockets}}){
+            $r{$p}=$self->{categories}{$category}{names}{$module}{sockets}{$p}{value};
+        }
+    }
+    return %r;
+}
 
 sub get_module_sokets_type{
-	my ($self,$category,$module)=@_;
-	if (!defined($category) ) {return 0;} 
-	my %r;
-	if ( exists ($self->{categories}{$category}{names}{$module}) ){
-		foreach my $p (sort keys %{$self->{categories}{$category}{names}{$module}{sockets}}){
-			$r{$p}=$self->{categories}{$category}{names}{$module}{sockets}{$p}{type};
-		}
-		
-	}
-	return %r;	
-}	
-
+    my ($self,$category,$module)=@_;
+    if (!defined($category) ) {return 0;}
+    my %r;
+    if ( exists ($self->{categories}{$category}{names}{$module}) ){
+        foreach my $p (sort keys %{$self->{categories}{$category}{names}{$module}{sockets}}){
+            $r{$p}=$self->{categories}{$category}{names}{$module}{sockets}{$p}{type};
+        }
+    }
+    return %r;
+}
 
 sub get_module_plugs_value{
-	my ($self,$category,$module)=@_;
-	if (!defined($category) ) {return 0;} 
-	my %r;
-	if ( exists ($self->{categories}{$category}{names}{$module}) ){
-		foreach my $p (sort keys %{$self->{categories}{$category}{names}{$module}{plugs}}){
-			$r{$p}=$self->{categories}{$category}{names}{$module}{plugs}{$p}{value};
-		}
-		
-	}
-	return %r;	
-}	
+    my ($self,$category,$module)=@_;
+    if (!defined($category) ) {return 0;}
+    my %r;
+    if ( exists ($self->{categories}{$category}{names}{$module}) ){
+        foreach my $p (sort keys %{$self->{categories}{$category}{names}{$module}{plugs}}){
+            $r{$p}=$self->{categories}{$category}{names}{$module}{plugs}{$p}{value};
+        }
+    }
+    return %r;
+}
 
 sub ip_get_param_order{
-	my ($self,$category,$module)=@_;
-	my @r;
-	if(exists $self->{categories}{$category}{names}{$module}{parameters_order}) {
-		@r=@{$self->{categories}{$category}{names}{$module}{parameters_order}};
-
-	}
-	return @r;
+    my ($self,$category,$module)=@_;
+    my @r;
+    if(exists $self->{categories}{$category}{names}{$module}{parameters_order}) {
+        @r=@{$self->{categories}{$category}{names}{$module}{parameters_order}};
+    }
+    return @r;
 }
 
-
-
-
-
-
-
 sub ip_add{
-	my ($self,$category,$module,$filed_name,$filed_data)=@_;
-	$self->{categories}{$category}{names}{$module}{$filed_name}=$filed_data;		
+    my ($self,$category,$module,$filed_name,$filed_data)=@_;
+    $self->{categories}{$category}{names}{$module}{$filed_name}=$filed_data;
 }
 
-
 sub ip_get{
-	my ($self,$category,$module,$filed_name)=@_;
-	return $self->{categories}{$category}{names}{$module}{$filed_name};
+    my ($self,$category,$module,$filed_name)=@_;
+    return $self->{categories}{$category}{names}{$module}{$filed_name};
 }
 
-
 sub ip_get_list{
-	my ($self,$category,$module,$filed_name)=@_;
-	my @l;
-	if( defined $self->{categories}{$category}{names}{$module}{$filed_name}){
-		@l=@{$self->{categories}{$category}{names}{$module}{$filed_name}};		
-	}
-	return @l;
+    my ($self,$category,$module,$filed_name)=@_;
+    my @l;
+    if( defined $self->{categories}{$category}{names}{$module}{$filed_name}){
+        @l=@{$self->{categories}{$category}{names}{$module}{$filed_name}};
+    }
+    return @l;
 }
 
-
 sub ip_remove{
-	my ($self,$category,$module,$filed_name)=@_;
-	delete 	$self->{categories}{$category}{names}{$module}{$filed_name};
+    my ($self,$category,$module,$filed_name)=@_;
+    delete     $self->{categories}{$category}{names}{$module}{$filed_name};
 }
 
-
-
-
 sub add_ip{
-
-	my ($self,$ipgen) =@_;
-	my $module;
-	$module	=	$ipgen->ipgen_get("ip_name");
-	my $module_name =$ipgen->ipgen_get("module_name");
-	if(!defined $module){ $module	=	$module_name}
-	my $category=	$ipgen->ipgen_get("category");
-	
-	
-	$self->{categories}{$category}{names}{$module}={};
-	
-	$self->{categories}{$category}{names}{$module}{module_name}=$module_name;
-	my @plugs= $ipgen->ipgen_list_plugs();
-	#print "$module:@plugs\n";
-	foreach my $plug (@plugs){
-		my ($type,$value,$connection_num)= $ipgen->ipgen_get_plug($plug);
-		ip_add_plug($self,$category,$module,$plug,$type,$value,$connection_num);
-		ip_add_plug_names($self,$ipgen,$category,$module, $plug);
-		
-	}	
-	my @sockets= $ipgen->ipgen_list_sokets();
-	#print "$module:@sockets\n";
-	foreach my $socket (@sockets){
-		my ($type,$value,$connection_num)= $ipgen->ipgen_get_socket($socket);
-		ip_add_socket($self,$category,$module, $socket,$type,$value,$connection_num);
-		ip_add_socket_names($self,$ipgen,$category,$module, $socket);
-	}	
-	my @parameters=  $ipgen->ipgen_get_all_parameters_list();
-	foreach my $param (@parameters){
-		my ($default,$type,$content,$info,$glob_param,$redefine_param)=$ipgen->ipgen_get_parameter_detail($param);
-		ip_add_parameter($self,$category,$module,$param,$default,$type,$content,$info,$glob_param,$redefine_param);
-				
-	}
-	
-	my @ports= $ipgen->ipgen_list_ports();
-	foreach my $port (@ports){
-		my($range,$type,$intfc_name,$intfc_port)=$ipgen->ipgen_get_port($port);
-		ip_add_port($self,$category,$module,$port,$type,$range,$intfc_name,$intfc_port);
-	}
-	
-	my @fileds =("system_c","system_h","hdl_files","hdl_files_ticked","sw_files","gen_sw_files","gen_hw_files","sw_params_list","unused","parameters_order","description","version",'description_pdf');
-	foreach my $p (@fileds){
-		my $val=$ipgen->ipgen_get($p);
-		$self->{categories}{$category}{names}{$module}{$p}=$ipgen->ipgen_get($p) if(defined $val );	
-	}
-	
-	
-	
-}		
-	
-
+    my ($self,$ipgen) =@_;
+    my $module;
+    $module    =    $ipgen->ipgen_get("ip_name");
+    my $module_name =$ipgen->ipgen_get("module_name");
+    if(!defined $module){ $module    =    $module_name}
+    my $category=    $ipgen->ipgen_get("category");
+    $self->{categories}{$category}{names}{$module}={};
+    $self->{categories}{$category}{names}{$module}{module_name}=$module_name;
+    my @plugs= $ipgen->ipgen_list_plugs();
+    #print "$module:@plugs\n";
+    foreach my $plug (@plugs){
+        my ($type,$value,$connection_num)= $ipgen->ipgen_get_plug($plug);
+        ip_add_plug($self,$category,$module,$plug,$type,$value,$connection_num);
+        ip_add_plug_names($self,$ipgen,$category,$module, $plug);
+    }
+    my @sockets= $ipgen->ipgen_list_sokets();
+    #print "$module:@sockets\n";
+    foreach my $socket (@sockets){
+        my ($type,$value,$connection_num)= $ipgen->ipgen_get_socket($socket);
+        ip_add_socket($self,$category,$module, $socket,$type,$value,$connection_num);
+        ip_add_socket_names($self,$ipgen,$category,$module, $socket);
+    }
+    my @parameters=  $ipgen->ipgen_get_all_parameters_list();
+    foreach my $param (@parameters){
+        my ($default,$type,$content,$info,$glob_param,$redefine_param)=$ipgen->ipgen_get_parameter_detail($param);
+        ip_add_parameter($self,$category,$module,$param,$default,$type,$content,$info,$glob_param,$redefine_param);
+    }
+    my @ports= $ipgen->ipgen_list_ports();
+    foreach my $port (@ports){
+        my($range,$type,$intfc_name,$intfc_port)=$ipgen->ipgen_get_port($port);
+        ip_add_port($self,$category,$module,$port,$type,$range,$intfc_name,$intfc_port);
+    }
+    my @fileds =("system_c","system_h","hdl_files","hdl_files_ticked","sw_files","gen_sw_files","gen_hw_files","sw_params_list","unused","parameters_order","description","version",'description_pdf');
+    foreach my $p (@fileds){
+        my $val=$ipgen->ipgen_get($p);
+        $self->{categories}{$category}{names}{$module}{$p}=$ipgen->ipgen_get($p) if(defined $val );
+    }
+}
 
 sub object_add_attribute{
-	my ($self,$attribute1,$attribute2,$value)=@_;
-	if(!defined $attribute2){$self->{$attribute1}=$value;}
-	else {$self->{$attribute1}{$attribute2}=$value;}
-
+    my ($self,$attribute1,$attribute2,$value)=@_;
+    if(!defined $attribute2){$self->{$attribute1}=$value;}
+    else {$self->{$attribute1}{$attribute2}=$value;}
 }
 
 sub object_get_attribute{
-	my ($self,$attribute1,$attribute2)=@_;
-	if(!defined $attribute2) {return $self->{$attribute1};}
-	return $self->{$attribute1}{$attribute2};
-
-
+    my ($self,$attribute1,$attribute2)=@_;
+    if(!defined $attribute2) {return $self->{$attribute1};}
+    return $self->{$attribute1}{$attribute2};
 }
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-1
+1;
diff --git a/mpsoc/perl_gui/lib/perl/ip_gen.pl b/mpsoc/perl_gui/lib/perl/ip_gen.pl
index fd36ba0..ce9e72f 100755
--- a/mpsoc/perl_gui/lib/perl/ip_gen.pl
+++ b/mpsoc/perl_gui/lib/perl/ip_gen.pl
@@ -2,10 +2,8 @@
 use constant::boolean;
 use strict;
 use warnings;
-
 use FindBin;
 use lib $FindBin::Bin;
-
 use wb_addr;
 use interface;
 use intfc_gen;
@@ -13,1934 +11,1355 @@
 use ip;
 use rvp;
 use Cwd 'abs_path';
-
 use File::Basename;
 use File::Path qw/make_path/;
-
-
-
-
-require "widget.pl"; 
+require "widget.pl";
 require "readme_gen.pl";
 
-
-
-
 ################
 #  check_input_file
 ################
-
 sub check_input_file{
-	my ($file,$ipgen,$info)=@_;
-	my ($name,$path,$suffix) = fileparse("$file",qr"\..[^.]*$");
-	if($suffix eq '.IP'){
-		$ipgen->ipgen_add("file_name",$file);
-		set_gui_status($ipgen,"load_file",0);
-		
-		
-	}else{
-		read_all_module ($file,$ipgen,$info);
-	
-	}	
-	
-	
-}		
-
+    my ($file,$ipgen,$info)=@_;
+    my ($name,$path,$suffix) = fileparse("$file",qr"\..[^.]*$");
+    if($suffix eq '.IP'){
+        $ipgen->ipgen_add("file_name",$file);
+        set_gui_status($ipgen,"load_file",0);
+    }else{
+        read_all_module ($file,$ipgen,$info);
+    }
+}
 
 sub read_all_module{
-	my ($file,$ipgen,$info)=@_;
-	
-	if (!defined $file) {
-		add_colored_info($info,"No input file is given. Please set an input Verilog fle first.\n", 'red');	
-		
-		return; 
-	}
-	
-	my $f=add_project_dir_to_addr($file);
-	
-	if (-f $f) { 
-		my $vdb =  read_verilog_file($f);
-		my @modules=sort $vdb->get_modules($f);
-		#foreach my $p(@module_list) {print "$p\n"}
-		$ipgen->ipgen_add("file_name",$file);
-
-
-
-		$ipgen->ipgen_add("module_name",$modules[0]);
-		$ipgen->ipgen_set_module_list(@modules);
-		load_default_setting($ipgen,$modules[0]);
-		
-		
-		set_gui_status($ipgen,"file_selected",1);
-		add_info($info,"$f is loaded\n");		
-	    
-	}
-	else { 
-		add_colored_info($info,"File $file does not exist!\n", 'red');			
-	}	
-}	
-
-
-
+    my ($file,$ipgen,$info)=@_;
+    if (!defined $file) {
+        add_colored_info($info,"No input file is given. Please set an input Verilog fle first.\n", 'red');
+        return;
+    }
+    my $f=add_project_dir_to_addr($file);
+    if (-f $f) {
+        my $vdb =  read_verilog_file($f);
+        my @modules=sort $vdb->get_modules($f);
+        #foreach my $p(@module_list) {print "$p\n"}
+        $ipgen->ipgen_add("file_name",$file);
+        $ipgen->ipgen_add("module_name",$modules[0]);
+        $ipgen->ipgen_set_module_list(@modules);
+        load_default_setting($ipgen,$modules[0]);
+        set_gui_status($ipgen,"file_selected",1);
+        add_info($info,"$f is loaded\n");
+    }
+    else {
+        add_colored_info($info,"File $file does not exist!\n", 'red');
+    }
+}
 
 sub save_ports_all{
-	my ($ipgen,$vdb,$top_module)=@_;
-	
-	foreach my $sig (sort $vdb->get_modules_signals($top_module)) {
-	my ($line,$a_line,$i_line,$type,$file,$posedge,$negedge,
-	 $type2,$s_file,$s_line,$range,$a_file,$i_file,$dims) = 
-	   $vdb->get_module_signal($top_module,$sig);
-
-		if($type eq "input" or $type eq "inout" or $type eq "output" ){
-			$ipgen->ipgen_add_port($sig,$range,$type,'IO','IO');
-			#print "$sig,$range,$type,'IO','IO'\n";
-			
-		}
-			
-
-	}
-
+    my ($ipgen,$vdb,$top_module)=@_;
+    foreach my $sig (sort $vdb->get_modules_signals($top_module)) {
+    my ($line,$a_line,$i_line,$type,$file,$posedge,$negedge,
+    $type2,$s_file,$s_line,$range,$a_file,$i_file,$dims) =
+    $vdb->get_module_signal($top_module,$sig);
+        if($type eq "input" or $type eq "inout" or $type eq "output" ){
+            $ipgen->ipgen_add_port($sig,$range,$type,'IO','IO');
+            #print "$sig,$range,$type,'IO','IO'\n";
+        }
+    }
 }
 
-
 ############
-#	file_info
+#    file_info
 #############
-
 sub ip_file_box {
-	my ($ipgen,$info,$table,$row)=@_;
-	my $label = gen_label_in_left(" Select file:");
-	my $entry = gen_entry();
-	#my $open= def_image_button("icons/select.png","Open");
-	my $browse= def_image_button("icons/browse.png","Browse");
-	my $file= $ipgen->ipgen_get("file_name");
-	if(defined $file){$entry->set_text($file);}
+    my ($ipgen,$info,$table,$row)=@_;
+    my $label = gen_label_in_left(" Select file:");
+    my $entry = gen_entry();
+    #my $open= def_image_button("icons/select.png","Open");
+    my $browse= def_image_button("icons/browse.png","Browse");
+    my $file= $ipgen->ipgen_get("file_name");
+    if(defined $file){$entry->set_text($file);}
     else {show_info($info,"Please select the verilog file containing the top level IP core\n");}
-
-	
-	my $entry2=gen_label_info(" IP name:",gen_entry_object($ipgen,'ip_name',undef,undef,undef,undef));
-
-
-
-	#show_info($info,"Please select the verilog file containing the ip module\n");
-	$browse->signal_connect("clicked"=> sub{
-		my $entry_ref=$_[1];
- 		my $file;
-		my $dialog = gen_file_dialog (undef, 'v','IP');
-           	if ( "ok" eq $dialog->run ) {
-            		$file = $dialog->get_filename;
-					$$entry_ref->set_text($file);
-					check_input_file($file,$ipgen,$info);            		
-       		 }
-       		$dialog->destroy;
-	} , \$entry);
-		
-	$entry->signal_connect("activate"=>sub{
-		my $file_name=$entry->get_text();
-		check_input_file($file_name,$ipgen,$info);
-	});
-		
-	$entry->signal_connect("changed"=>sub{
-		#my $file_name=$entry->get_text();
-		#check_input_file($file_name,$ipgen,$info);
-	});
-	
-	$table->attach_defaults ($label, 0, 1 , $row, $row+1);
-	$table->attach_defaults ($entry, 1, 8 , $row, $row+1);
-	$table->attach ($browse, 8, 9, $row, $row+1,,'expand','shrink',2,2);
-	$table->attach_defaults ($entry2,  9, 11, $row, $row+1);
-	
-	
-	
+    my $entry2=gen_label_info(" IP name:",gen_entry_object($ipgen,'ip_name',undef,undef,undef,undef));
+    #show_info($info,"Please select the verilog file containing the ip module\n");
+    $browse->signal_connect("clicked"=> sub{
+        my $entry_ref=$_[1];
+        my $file;
+        my $dialog = gen_file_dialog (undef, 'v','IP');
+            if ( "ok" eq $dialog->run ) {
+                    $file = $dialog->get_filename;
+                    $$entry_ref->set_text($file);
+                    check_input_file($file,$ipgen,$info);
+                }
+            $dialog->destroy;
+    } , \$entry);
+    $entry->signal_connect("activate"=>sub{
+        my $file_name=$entry->get_text();
+        check_input_file($file_name,$ipgen,$info);
+    });
+    $entry->signal_connect("changed"=>sub{
+        #my $file_name=$entry->get_text();
+        #check_input_file($file_name,$ipgen,$info);
+    });
+    $table->attach_defaults ($label, 0, 1 , $row, $row+1);
+    $table->attach_defaults ($entry, 1, 8 , $row, $row+1);
+    $table->attach ($browse, 8, 9, $row, $row+1,,'expand','shrink',2,2);
+    $table->attach_defaults ($entry2,  9, 11, $row, $row+1);
 }
 
-
-
-
 sub select_module{
-	my ($ipgen,$info,$table,$row)=@_;
-
-	
-	my @modules= $ipgen->ipgen_get_module_list();
-	my $saved_module=$ipgen->ipgen_get("module_name");
-	my $pos=(defined $saved_module ) ? get_scolar_pos( $saved_module,@modules) : 0;
-	my $combo = gen_combo(\@modules, $pos);
-	my $top_module=gen_label_info("  Select\n module:",$combo);
-
-
-
-
-	my $param= def_image_button("icons/setting.png","Parameter\n   setting");
-	my $def= def_image_button("icons/setting.png","Definition\n file setting");
-	
-	
-	
-	#Category	
-	my $ip = ip->lib_new ();
-	my @categories= $ip->ip_get_categories();
-	$ip =undef;
-	my $saved_category=$ipgen->ipgen_get("category");
-	if(defined $saved_category ){	push(@categories,$saved_category) if(!( grep /^$saved_category$/, @categories ));}
-	my $content=join( ',', @categories);	
-	my $combentry=gen_comboentry_object ($ipgen,'category',undef,$content,$saved_category,undef,undef);
-	my $category=gen_label_info("  Select\n Category:",$combentry,"Select the IP category form the given list or you can add a new category.");
-
-
-	
-	my $ipinfo= def_image_button("icons/add_info.png","    IP\n Description");
-	my $header_h= def_image_button("icons/h_file.png","Add Software\n      files");
-	my $lib_hdl= def_image_button("icons/add-notes.png","Add HDL\n     files");
-	
-
-	#$table->attach_defaults ($top_module, 0, 1 , $row, $row+1);
-	$table->attach ($top_module, 0, 4 , $row,$row+1,'fill','shrink',2,2);
-	$table->attach ($param, 4, 6 , $row, $row+1,'expand','shrink',2,2);
-		
-	$table->attach ($category, 6, 8 , $row, $row+1,'expand','shrink',2,2);
-	$table->attach ($ipinfo, 8, 9 , $row, $row+1,'expand','shrink',2,2);
-	$table->attach ($header_h, 9, 10 , $row, $row+1,'expand','shrink',2,2);
-	$table->attach ($lib_hdl, 10, 11 , $row, $row+1,'expand','shrink',2,2);
-	
-	
-	$combo->signal_connect("changed"=> sub{
-		
-		my $module= $combo->get_active_text();
-		load_default_setting($ipgen,$module); 
-		set_gui_status($ipgen,'intfc_changed',0);
-		
-		
-	});
-	
-	$param->signal_connect("clicked"=> sub{
-		get_parameter_setting($ipgen,$info);
-		
-		
-	});	
-
-	$def->signal_connect("clicked"=> sub{
-		get_def_setting($ipgen,$info);
-		
-		
-	});	
-	
-	$ipinfo->signal_connect("clicked"=> sub{
-		get_Description($ipgen,$info);		
-		
-	});	
-	$header_h->signal_connect("clicked"=> sub{
-		my %page_info;
-		my $help1="The files and folder that selected here will be copied in generated processing tile SW folder.";
-		my $help2="The file listed here can contain some variable with \${var_name} format. The file generator will replace them with their values during file generation. The variable can be selected from above listed global variables";
-		my $help3='Define the header file for this peripheral device. You can use global variables listed at the top.  This file contains peripheral device functions\' deceleration, memory-mapped register address definition,  definitions of data types, and  C preprocessor commands. Do not put function definitions in the header file. Functions should be defined in add to tile.c section. 
-  		
-header file example 
-   
- #define ${IP}_REG_0   (*((volatile unsigned int *) ($BASE)))   
- #define ${IP}_REG_1   (*((volatile unsigned int *) ($BASE+4)))
-   
-   
- #define ${IP}_WRITE_REG1(value)  ${IP}_REG_1=value	
- #define ${IP}_READ_REG1()  	${IP}_REG_1	    
-  ';	
-  
-  my $help4='Define peripheral device\'s functions in this file. You can use global variables listed at the top.  
-';	
-  
-
-		$page_info{0}{page_name} = "_Add existing file/folder";
-		$page_info{0}{filed_name}= "sw_files";
-		$page_info{0}{filed_type}= "existing_file/folder";
-		$page_info{0}{rename_file}=undef; 
-		$page_info{0}{folder_en}=1;
-		$page_info{0}{help}=$help1;
-
-		$page_info{1}{page_name} = "_Add files contain variables";
-		$page_info{1}{filed_name}= "gen_sw_files";
-		$page_info{1}{filed_type}= "file_with_variables";
-		$page_info{1}{rename_file}=1; 
-		$page_info{1}{folder_en}=0;
-		$page_info{1}{help}=$help2;
-
-		$page_info{2}{page_name} = "_Add to tile.h";
-		$page_info{2}{filed_name}= "system_h";
-		$page_info{2}{filed_type}= "file_content";
-		$page_info{2}{rename_file}=undef; 
-		$page_info{2}{folder_en}=0;
-		$page_info{2}{help}=$help3;
-		
-		
-		$page_info{3}{page_name} = "_Add to tile.c";
-		$page_info{3}{filed_name}= "system_c";
-		$page_info{3}{filed_type}= "file_content";
-		$page_info{3}{rename_file}=undef; 
-		$page_info{3}{folder_en}=0;
-		$page_info{3}{help}=$help4;
-		
-		
-		
-
-
-		get_source_file($ipgen,$info,0,"Add software file(s)","SW",\%page_info);
-		#get_software_file($ipgen,$info,0);		
-		
-	});	
-	$lib_hdl->signal_connect("clicked"=> sub{
-		my $help1="The files and folder that selected here will be copied in the generated processing tile src_verilog folder. If you tick simulation only option for each file/folder, they will be copied in src_sim folder instead and will only be used for simulation.";
-		my $help2="The files listed here can contain some variables with \${var_name} format. The file generator will replace them with their values during file generation. The variable can be selected from the above listed global variables.";
-		my $help3='The content here will be added to the generated tile.v file. You can define functions/tasks etc...';
-		  
-		my %page_info;
-		$page_info{0}{page_name} = "_Add existing HDL file/folder";
-		$page_info{0}{filed_name}= "hdl_files";
-		$page_info{0}{filed_type}= "existing_file/folder";
-		$page_info{0}{rename_file}=undef;
-		$page_info{0}{folder_en}=1; 
-		$page_info{0}{help}=$help1;
-		$page_info{0}{tick}="Used only for Simulation";
-
-		$page_info{1}{page_name} = "_Add files contain variables";
-		$page_info{1}{filed_name}= "gen_hw_files";
-		$page_info{1}{filed_type}= "file_with_variables";
-		$page_info{1}{rename_file}=1; 
-		$page_info{1}{folder_en}=0;
-		$page_info{1}{help}=$help2;
-		
-		$page_info{2}{page_name} = "_Add to tile.v";
-		$page_info{2}{filed_name}= "system_v";
-		$page_info{2}{filed_type}= "file_content";
-		$page_info{2}{rename_file}=undef; 
-		$page_info{2}{folder_en}=0;
-		$page_info{2}{help}=$help3;
-		
-
-		get_source_file($ipgen,$info,0,"Add HDL file(s)", "hw",\%page_info);
-
-		#get_hdl_file($ipgen,$info);
-				
-		
-	});	
+    my ($ipgen,$info,$table,$row)=@_;
+    my @modules= $ipgen->ipgen_get_module_list();
+    my $saved_module=$ipgen->ipgen_get("module_name");
+    my $pos=(defined $saved_module ) ? get_scolar_pos( $saved_module,@modules) : 0;
+    my $combo = gen_combo(\@modules, $pos);
+    my $top_module=gen_label_info("  Select\n module:",$combo);
+    my $param= def_image_button("icons/setting.png","Parameter\n   setting");
+    my $def= def_image_button("icons/setting.png","Definition\n file setting");
+    #Category
+    my $ip = ip->lib_new ();
+    my @categories= $ip->ip_get_categories();
+    $ip =undef;
+    my $saved_category=$ipgen->ipgen_get("category");
+    if(defined $saved_category ){    push(@categories,$saved_category) if(!( grep /^$saved_category$/, @categories ));}
+    my $content=join( ',', @categories);
+    my $combentry=gen_comboentry_object ($ipgen,'category',undef,$content,$saved_category,undef,undef);
+    my $category=gen_label_info("  Select\n Category:",$combentry,"Select the IP category form the given list or you can add a new category.");
+    my $ipinfo= def_image_button("icons/add_info.png","    IP\n Description");
+    my $header_h= def_image_button("icons/h_file.png","Add Software\n      files");
+    my $lib_hdl= def_image_button("icons/add-notes.png","Add HDL\n     files");
+    #$table->attach_defaults ($top_module, 0, 1 , $row, $row+1);
+    $table->attach ($top_module, 0, 4 , $row,$row+1,'fill','shrink',2,2);
+    $table->attach ($param, 4, 6 , $row, $row+1,'expand','shrink',2,2);
+    $table->attach ($category, 6, 8 , $row, $row+1,'expand','shrink',2,2);
+    $table->attach ($ipinfo, 8, 9 , $row, $row+1,'expand','shrink',2,2);
+    $table->attach ($header_h, 9, 10 , $row, $row+1,'expand','shrink',2,2);
+    $table->attach ($lib_hdl, 10, 11 , $row, $row+1,'expand','shrink',2,2);
+    $combo->signal_connect("changed"=> sub{
+        my $module= $combo->get_active_text();
+        load_default_setting($ipgen,$module);
+        set_gui_status($ipgen,'intfc_changed',0);
+    });
+    $param->signal_connect("clicked"=> sub{
+        get_parameter_setting($ipgen,$info);
+    });
+    $def->signal_connect("clicked"=> sub{
+        get_def_setting($ipgen,$info);
+    });
+    $ipinfo->signal_connect("clicked"=> sub{
+        get_Description($ipgen,$info);
+    });
+    $header_h->signal_connect("clicked"=> sub{
+        my %page_info;
+        my $help1="The files and folder that selected here will be copied in generated processing tile SW folder.";
+        my $help2="The file listed here can contain some variable with \${var_name} format. The file generator will replace them with their values during file generation. The variable can be selected from above listed global variables";
+        my $help3='Define the header file for this peripheral device. You can use global variables listed at the top.  This file contains peripheral device functions\' deceleration, memory-mapped register address definition,  definitions of data types, and  C preprocessor commands. Do not put function definitions in the header file. Functions should be defined in add to tile.c section.
+header file example
+    #define ${IP}_REG_0   (*((volatile unsigned int *) ($BASE)))
+    #define ${IP}_REG_1   (*((volatile unsigned int *) ($BASE+4)))
+    #define ${IP}_WRITE_REG1(value)  ${IP}_REG_1=value
+    #define ${IP}_READ_REG1()      ${IP}_REG_1
+    ';
+    my $help4='Define peripheral device\'s functions in this file. You can use global variables listed at the top.
+';
+        $page_info{0}{page_name} = "_Add existing file/folder";
+        $page_info{0}{filed_name}= "sw_files";
+        $page_info{0}{filed_type}= "existing_file/folder";
+        $page_info{0}{rename_file}=undef;
+        $page_info{0}{folder_en}=1;
+        $page_info{0}{help}=$help1;
+        $page_info{1}{page_name} = "_Add files contain variables";
+        $page_info{1}{filed_name}= "gen_sw_files";
+        $page_info{1}{filed_type}= "file_with_variables";
+        $page_info{1}{rename_file}=1;
+        $page_info{1}{folder_en}=0;
+        $page_info{1}{help}=$help2;
+        $page_info{2}{page_name} = "_Add to tile.h";
+        $page_info{2}{filed_name}= "system_h";
+        $page_info{2}{filed_type}= "file_content";
+        $page_info{2}{rename_file}=undef;
+        $page_info{2}{folder_en}=0;
+        $page_info{2}{help}=$help3;
+        $page_info{3}{page_name} = "_Add to tile.c";
+        $page_info{3}{filed_name}= "system_c";
+        $page_info{3}{filed_type}= "file_content";
+        $page_info{3}{rename_file}=undef;
+        $page_info{3}{folder_en}=0;
+        $page_info{3}{help}=$help4;
+        get_source_file($ipgen,$info,0,"Add software file(s)","SW",\%page_info);
+        #get_software_file($ipgen,$info,0);
+    });
+    $lib_hdl->signal_connect("clicked"=> sub{
+        my $help1="The files and folder that selected here will be copied in the generated processing tile src_verilog folder. If you tick simulation only option for each file/folder, they will be copied in src_sim folder instead and will only be used for simulation.";
+        my $help2="The files listed here can contain some variables with \${var_name} format. The file generator will replace them with their values during file generation. The variable can be selected from the above listed global variables.";
+        my $help3='The content here will be added to the generated tile.v file. You can define functions/tasks etc...';
+        my %page_info;
+        $page_info{0}{page_name} = "_Add existing HDL file/folder";
+        $page_info{0}{filed_name}= "hdl_files";
+        $page_info{0}{filed_type}= "existing_file/folder";
+        $page_info{0}{rename_file}=undef;
+        $page_info{0}{folder_en}=1;
+        $page_info{0}{help}=$help1;
+        $page_info{0}{tick}="Used only for Simulation";
+        $page_info{1}{page_name} = "_Add files contain variables";
+        $page_info{1}{filed_name}= "gen_hw_files";
+        $page_info{1}{filed_type}= "file_with_variables";
+        $page_info{1}{rename_file}=1;
+        $page_info{1}{folder_en}=0;
+        $page_info{1}{help}=$help2;
+        $page_info{2}{page_name} = "_Add to tile.v";
+        $page_info{2}{filed_name}= "system_v";
+        $page_info{2}{filed_type}= "file_content";
+        $page_info{2}{rename_file}=undef;
+        $page_info{2}{folder_en}=0;
+        $page_info{2}{help}=$help3;
+        get_source_file($ipgen,$info,0,"Add HDL file(s)", "hw",\%page_info);
+        #get_hdl_file($ipgen,$info);
+    });
 }
 
 sub load_default_setting{
-	my ($ipgen,$module)=@_; 
-	my $file= $ipgen->ipgen_get("file_name");
-	$file=add_project_dir_to_addr($file);
-	$ipgen->ipgen_add("module_name",$module);
-	my $vdb =read_verilog_file($file);
-	my %parameters = $vdb->get_modules_parameters_not_local($module);
-	my @parameters_order= $vdb->get_modules_parameters_not_local_order($module);
-	my @ports_order=$vdb->get_module_ports_order($module);
-	#print "@port_order\n";
-	
-	#add default parameter setting
-	$ipgen->ipgen_remove_all_parameters();
-	foreach my $p (keys %parameters){
-			#print "$p\n";
-			my $v = $parameters{$p};
-			$v =~s/[\n]//gs;
-			$ipgen->ipgen_add_parameter($p,$v,'Fixed','','Parameter',1);
-			
-	}
-	#add parameter order. 
-	$ipgen->ipgen_add("parameters_order",\@parameters_order); 
-	#add port order.
-	$ipgen->ipgen_add_ports_order(@ports_order); 
-	#add ports 
-	$ipgen->ipgen_remove_all_ports();	
-	save_ports_all($ipgen,$vdb,$module);
-
-	
-
+    my ($ipgen,$module)=@_;
+    my $file= $ipgen->ipgen_get("file_name");
+    $file=add_project_dir_to_addr($file);
+    $ipgen->ipgen_add("module_name",$module);
+    my $vdb =read_verilog_file($file);
+    my %parameters = $vdb->get_modules_parameters_not_local($module);
+    my @parameters_order= $vdb->get_modules_parameters_not_local_order($module);
+    my @ports_order=$vdb->get_module_ports_order($module);
+    #print "@port_order\n";
+    #add default parameter setting
+    $ipgen->ipgen_remove_all_parameters();
+    foreach my $p (keys %parameters){
+            #print "$p\n";
+            my $v = $parameters{$p};
+            $v =~s/[\n]//gs;
+            $ipgen->ipgen_add_parameter($p,$v,'Fixed','','Parameter',1);
+    }
+    #add parameter order.
+    $ipgen->ipgen_add("parameters_order",\@parameters_order);
+    #add port order.
+    $ipgen->ipgen_add_ports_order(@ports_order);
+    #add ports
+    $ipgen->ipgen_remove_all_ports();
+    save_ports_all($ipgen,$vdb,$module);
 }
 
 sub file_info_box {
-	my($ipgen,$info)=@_;
-	my $table=def_table(2,11,FALSE);
-	my $table1=def_table(1,11,FALSE);
-	my $table2=def_table(1,11,FALSE);
-	ip_file_box ($ipgen,$info,$table1,0);
-	select_module($ipgen,$info,$table2,0);
-	$table->attach($table1,0,11,0,1,'fill','shrink',2,2);
-	$table->attach($table2,0,11,1,2,'fill','shrink',2,2);
-	return add_widget_to_scrolled_win($table);
-	
-	
+    my($ipgen,$info)=@_;
+    my $table=def_table(2,11,FALSE);
+    my $table1=def_table(1,11,FALSE);
+    my $table2=def_table(1,11,FALSE);
+    ip_file_box ($ipgen,$info,$table1,0);
+    select_module($ipgen,$info,$table2,0);
+    $table->attach($table1,0,11,0,1,'fill','shrink',2,2);
+    $table->attach($table2,0,11,1,2,'fill','shrink',2,2);
+    return add_widget_to_scrolled_win($table);
 }
 
-
-
-
-
-
-
 sub show_port_info{
-	my($intfc,$ipgen,$info,$refresh_ref)=@_;
-	my $table = port_info_box($intfc,$ipgen,$info,$info);
-	my $scrolled_win = add_widget_to_scrolled_win($table);
-	
-
-
-	$$refresh_ref-> signal_connect("clicked" => sub{ 
-		$table->destroy;
-		$table = port_info_box($intfc,$ipgen,$info,$info);
-		
-		add_widget_to_scrolled_win($table,$scrolled_win);
-		$table->show;
-		$scrolled_win->show_all;
-		
-		
-		
-		
-	});
-	
-	return $scrolled_win;
-	
+    my($intfc,$ipgen,$info,$refresh_ref)=@_;
+    my $table = port_info_box($intfc,$ipgen,$info,$info);
+    my $scrolled_win = add_widget_to_scrolled_win($table);
+    $$refresh_ref-> signal_connect("clicked" => sub{
+        $table->destroy;
+        $table = port_info_box($intfc,$ipgen,$info,$info);
+        add_widget_to_scrolled_win($table,$scrolled_win);
+        $table->show;
+        $scrolled_win->show_all;
+    });
+    return $scrolled_win;
 }
 
-
-
-
-
-
-
-
-
 ############
 #  get_parameter_setting
 ##########
-sub get_parameter_setting { 
-	my ($ipgen,$info)=@_;
-	
-	
-	my $file= $ipgen->ipgen_get("file_name");
-	if (!defined $file) {
-			message_dialog("The input Verilog file is empty");
-			#return;
-			
-	}		
-	my $module = $ipgen->ipgen_get("module_name");
-	
-	
-	my $window =  def_popwin_size(85,50,"Define parameters detail",'percent');	
-	
-	
-	
-	
-	my @widget_type_list=("Fixed","Entry","Combo-box","Spin-button");
-	my @param_type_list=("Parameter","Localparam","Don't include");
-	my $type_info="Define the parameter type: 
-
+sub get_parameter_setting {
+    my ($ipgen,$info)=@_;
+    my $file= $ipgen->ipgen_get("file_name");
+    if (!defined $file) {
+            message_dialog("The input Verilog file is empty");
+            #return;
+    }
+    my $module = $ipgen->ipgen_get("module_name");
+    my $window =  def_popwin_size(85,50,"Define parameters detail",'percent');
+    my @widget_type_list=("Fixed","Entry","Combo-box","Spin-button");
+    my @param_type_list=("Parameter","Localparam","Don't include");
+    my $type_info="Define the parameter type:
 Fixed: The parameter is fixed and get the default value. Users can not see or change the parameter value.
-
 Entry: The parameter value is received via entry. The user can type anything.
-
 Combo-box: The parameter value can be selected from a list of predefined value.
-
 Spin-button: The parameter is numeric and will be obtained using spin button.";
-	my $content_info='
+    my $content_info='
 For Fixed and Entry leave it empty.
 For Combo box define the parameters which must be shown in combo box as: "PAEAMETER1","PARAMETER2"...,"PARAMETERn".
 For Spin button define it as "minimum, maximum, step" e.g 0,10,1.';
-	my $param_info='Define how parameter is included in the top module containig this IP core.';
-
-	my $redefine_info='
-	If checked, the defined parameter/localparam in SoC will be passed to the IP core';
-
-	#TABLE
-	my $table = def_table(12,8,FALSE);
-	my @positions=(0,1,2,3,4,5,6,7,8);
-	my $col=0;
-	#title
-	my @title;
-	$title[0]=gen_label_in_center("Parameter name");
-	$title[1]=gen_label_in_center("Default value");
-	$title[2]=gen_label_help($type_info,"Widget type");
-	$title[3]=gen_label_help($content_info,"Widget content");
-	$title[4]=gen_label_help($param_info,"Type");
-	$title[5]=gen_label_help($redefine_info,"");
-	$title[6]=gen_label_help("You can add additional information about this parameter.","info");
-	$title[7]=gen_label_in_center("add/remove");
-	
-	
-	foreach my $t (@title){
-		$table->attach ($title[$col], $positions[$col], $positions[$col+1], 0, 1,'expand','shrink',2,2); $col++;
-
-	}
-	
-
-	my @parameters=$ipgen->ipgen_get_all_parameters_list();
-	my @params_order= $ipgen->ipgen_get_list("parameters_order");
-	if((@params_order)) {@parameters=@params_order;}
-	
-	my $ok = def_image_button('icons/select.png','OK');
-	
-
-	my ($b,$new_param)= def_h_labeled_entry("Add new parameter name:");
-	my $add = def_image_button('icons/plus.png','Add parameter');
-	my $addbox=def_hbox(FALSE,0);
-	$addbox->pack_start($b,FALSE, FALSE,0);
-	$addbox->pack_start($add,   FALSE, FALSE,0);
-	
-	my @allowed;
-	
-	my $row=1;
-	my $error;
-	push(@parameters,"#new#");
-	foreach my $p (@parameters) {
-		my ($saved_default,$saved_widget_type,$saved_content,$saved_info,$vfile_param_type,$redefine_param)=  $ipgen->ipgen_get_parameter_detail($p);
-		#print 	"($saved_default,$saved_type,$saved_content)\n";
-		my $parameter_box = def_hbox(TRUE,5);
-		my $param_name;
-		my $add_remove;
-		if($p ne "#new#"){
-			$param_name= def_label($p);
-			$add_remove=def_image_button("icons/cancel.png","remove");
-		} else { 
-			$param_name= gen_entry();
-			$add_remove=def_image_button("icons/plus.png","add");
-		}
-
-		my $default_entry= gen_entry($saved_default);
-		my $pos=(defined $saved_widget_type ) ? get_scolar_pos( $saved_widget_type,@widget_type_list) : 0;
-		my $widget_type_combo=gen_combo(\@widget_type_list, $pos);
-		my $content_entry= gen_entry($saved_content);
-
-
-		
-		$vfile_param_type= "Don't include" if (!defined $vfile_param_type );
-		$vfile_param_type= "Parameter"  if ($vfile_param_type eq 1);
-		$vfile_param_type= "Localparam" if ($vfile_param_type eq 0);
-		$pos=get_scolar_pos($vfile_param_type,@param_type_list);
-		my $check_param= gen_combo(\@param_type_list, $pos);
-
-
-		#$check_param->set_active($vfile_param_type) if(defined $vfile_param_type );
-		my $check_redefine= gen_checkbutton('Redefine');
-		$check_redefine->set_active(1) ;
-		$check_redefine->set_active($redefine_param) if(defined $redefine_param );		
-		
-		my $info=def_image_button("icons/add_info.png");
-		#print "\$vfile_param_type =$vfile_param_type\n";
-		
-		$col=0;
-		my @all_widget=($param_name,$default_entry,$widget_type_combo,$content_entry,$check_param,$check_redefine,$info,$add_remove);
-		foreach my $t (@all_widget){
-			$table->attach ($t, $positions[$col], $positions[$col+1], $row, $row+1,'expand','shrink',2,2);$col++;
-
-		}		
-		
-		
-		$info->signal_connect (clicked => sub{
-			
-			get_param_info($ipgen,\$saved_info);
-		});
-		
-				
-		$ok->signal_connect (clicked => sub{
-			if($p ne "#new#"){		
-				my $default=$default_entry->get_text();
-				my $type= $widget_type_combo->get_active_text();
-				my $content=$content_entry->get_text();
-				my $vfile_param_type=$check_param->get_active_text();					
-				my $check_result=$check_redefine->get_active();
-				my $redefine_param=($check_result eq 1)? 1:0;
-				$ipgen->ipgen_add_parameter($p,$default,$type,$content,$saved_info,$vfile_param_type,$redefine_param);
-				
-				if 	($type eq "Spin-button"){ 
-					my @d=split(/\s*,\s*/,$content);
-					 if( scalar @d != 3){
-						$error=$error."wrong content setting for parameter $p\n" ;
-						print "$error";
-					}
-				}
-
-
-			}
-		});
-		$add_remove->signal_connect (clicked => sub{
-			if($p eq "#new#"){ #add new parameter
-				my $param= $param_name->get_text();
-				$param=remove_all_white_spaces($param);
-			        
-				if( length($param) ){
-					my $default=$default_entry->get_text();
-					my $type=$widget_type_combo->get_active_text();
-					my $content=$content_entry->get_text();
-					my $vfile_param_type=$check_param->get_active_text();	
-					my $check_result=$check_redefine->get_active();
-					my $redefine_param=($check_result eq 1)? 1:0;
-					$ipgen->ipgen_add_parameter($param,$default,$type,$content,$saved_info,$vfile_param_type,$redefine_param);
-					$ipgen->ipgen_push_parameters_order($param);
-					set_gui_status($ipgen,"change_parameter",0);
-					$ok->clicked;
-					#$window->destroy();
-				}
-
-			} else { #remove the parameter
-				$ipgen->ipgen_remove_parameter($p);
-				$ipgen->ipgen_remove_parameters_order($p);
-				$p = "#new#";
-				set_gui_status($ipgen,"change_parameter",0);
-				$ok->clicked;
-					#$window->destroy();
-	
-			}
-			#my $param_name=$new_param->get_text();
-			#	if( length($param_name) ){
-			#		print "$param_name\n";
-			#		$ipgen->ipgen_add_parameter($param_name,undef);
-			#		set_gui_status($ipgen,"change_parameter",0);
-			#		$window->destroy();
-			
-		});
-
-		
-		
-	$row++;	
-	}
-	
-
-
-
-	
-	my $scrolled_win = add_widget_to_scrolled_win($table);
-
-
-
-
-	
-	
-	
-
-	$add->signal_connect (clicked => sub{
-		my $param_name=$new_param->get_text();
-		if( length($param_name) ){
-			#print "$param_name\n";
-			$ipgen->ipgen_add_parameter($param_name,undef);
-			set_gui_status($ipgen,"change_parameter",0);
-			$window->destroy();
-		}
-
+    my $param_info='Define how parameter is included in the top module containig this IP core.';
+    my $redefine_info='
+    If checked, the defined parameter/localparam in SoC will be passed to the IP core';
+    #TABLE
+    my $table = def_table(12,8,FALSE);
+    my @positions=(0,1,2,3,4,5,6,7,8);
+    my $col=0;
+    #title
+    my @title;
+    $title[0]=gen_label_in_center("Parameter name");
+    $title[1]=gen_label_in_center("Default value");
+    $title[2]=gen_label_help($type_info,"Widget type");
+    $title[3]=gen_label_help($content_info,"Widget content");
+    $title[4]=gen_label_help($param_info,"Type");
+    $title[5]=gen_label_help($redefine_info,"");
+    $title[6]=gen_label_help("You can add additional information about this parameter.","info");
+    $title[7]=gen_label_in_center("add/remove");
+    foreach my $t (@title){
+        $table->attach ($title[$col], $positions[$col], $positions[$col+1], 0, 1,'expand','shrink',2,2); $col++;
+    }
+    my @parameters=$ipgen->ipgen_get_all_parameters_list();
+    my @params_order= $ipgen->ipgen_get_list("parameters_order");
+    if((@params_order)) {@parameters=@params_order;}
+    my $ok = def_image_button('icons/select.png','OK');
+    my ($b,$new_param)= def_h_labeled_entry("Add new parameter name:");
+    my $add = def_image_button('icons/plus.png','Add parameter');
+    my $addbox=def_hbox(FALSE,0);
+    $addbox->pack_start($b,FALSE, FALSE,0);
+    $addbox->pack_start($add,   FALSE, FALSE,0);
+    my @allowed;
+    my $row=1;
+    my $error;
+    push(@parameters,"#new#");
+    foreach my $p (@parameters) {
+        my ($saved_default,$saved_widget_type,$saved_content,$saved_info,$vfile_param_type,$redefine_param)=  $ipgen->ipgen_get_parameter_detail($p);
+        #print     "($saved_default,$saved_type,$saved_content)\n";
+        my $parameter_box = def_hbox(TRUE,5);
+        my $param_name;
+        my $add_remove;
+        if($p ne "#new#"){
+            $param_name= def_label($p);
+            $add_remove=def_image_button("icons/cancel.png","remove");
+        } else {
+            $param_name= gen_entry();
+            $add_remove=def_image_button("icons/plus.png","add");
+        }
+        my $default_entry= gen_entry($saved_default);
+        my $pos=(defined $saved_widget_type ) ? get_scolar_pos( $saved_widget_type,@widget_type_list) : 0;
+        my $widget_type_combo=gen_combo(\@widget_type_list, $pos);
+        my $content_entry= gen_entry($saved_content);
+        $vfile_param_type= "Don't include" if (!defined $vfile_param_type );
+        $vfile_param_type= "Parameter"  if ($vfile_param_type eq 1);
+        $vfile_param_type= "Localparam" if ($vfile_param_type eq 0);
+        $pos=get_scolar_pos($vfile_param_type,@param_type_list);
+        my $check_param= gen_combo(\@param_type_list, $pos);
+        #$check_param->set_active($vfile_param_type) if(defined $vfile_param_type );
+        my $check_redefine= gen_checkbutton('Redefine');
+        $check_redefine->set_active(1) ;
+        $check_redefine->set_active($redefine_param) if(defined $redefine_param );
+        my $info=def_image_button("icons/add_info.png");
+        #print "\$vfile_param_type =$vfile_param_type\n";
+        $col=0;
+        my @all_widget=($param_name,$default_entry,$widget_type_combo,$content_entry,$check_param,$check_redefine,$info,$add_remove);
+        foreach my $t (@all_widget){
+            $table->attach ($t, $positions[$col], $positions[$col+1], $row, $row+1,'expand','shrink',2,2);$col++;
+        }
+        $info->signal_connect (clicked => sub{
+            get_param_info($ipgen,\$saved_info);
+        });
+        $ok->signal_connect (clicked => sub{
+            if($p ne "#new#"){
+                my $default=$default_entry->get_text();
+                my $type= $widget_type_combo->get_active_text();
+                my $content=$content_entry->get_text();
+                my $vfile_param_type=$check_param->get_active_text();
+                my $check_result=$check_redefine->get_active();
+                my $redefine_param=($check_result eq 1)? 1:0;
+                $ipgen->ipgen_add_parameter($p,$default,$type,$content,$saved_info,$vfile_param_type,$redefine_param);
+                if     ($type eq "Spin-button"){
+                    my @d=split(/\s*,\s*/,$content);
+                    if( scalar @d != 3){
+                        $error=$error."wrong content setting for parameter $p\n" ;
+                        print "$error";
+                    }
+                }
+            }
+        });
+        $add_remove->signal_connect (clicked => sub{
+            if($p eq "#new#"){ #add new parameter
+                my $param= $param_name->get_text();
+                $param=remove_all_white_spaces($param);
+                if( length($param) ){
+                    my $default=$default_entry->get_text();
+                    my $type=$widget_type_combo->get_active_text();
+                    my $content=$content_entry->get_text();
+                    my $vfile_param_type=$check_param->get_active_text();
+                    my $check_result=$check_redefine->get_active();
+                    my $redefine_param=($check_result eq 1)? 1:0;
+                    $ipgen->ipgen_add_parameter($param,$default,$type,$content,$saved_info,$vfile_param_type,$redefine_param);
+                    $ipgen->ipgen_push_parameters_order($param);
+                    set_gui_status($ipgen,"change_parameter",0);
+                    $ok->clicked;
+                    #$window->destroy();
+                }
+            } else { #remove the parameter
+                $ipgen->ipgen_remove_parameter($p);
+                $ipgen->ipgen_remove_parameters_order($p);
+                $p = "#new#";
+                set_gui_status($ipgen,"change_parameter",0);
+                $ok->clicked;
+                    #$window->destroy();
+            }
+            #my $param_name=$new_param->get_text();
+            #    if( length($param_name) ){
+            #        print "$param_name\n";
+            #        $ipgen->ipgen_add_parameter($param_name,undef);
+            #        set_gui_status($ipgen,"change_parameter",0);
+            #        $window->destroy();
+        });
+    $row++;
+    }
+    my $scrolled_win = add_widget_to_scrolled_win($table);
+    $add->signal_connect (clicked => sub{
+        my $param_name=$new_param->get_text();
+        if( length($param_name) ){
+            #print "$param_name\n";
+            $ipgen->ipgen_add_parameter($param_name,undef);
+            set_gui_status($ipgen,"change_parameter",0);
+            $window->destroy();
+        }
 #/*******************************************************************************************************************************/
-
-	});
-	
-	$ok->signal_connect (clicked => sub{
-
-		
-
-
-				
-		
-		if (defined $error){
-			message_dialog("$error",'error');
-			$error=undef;
-		}else {
-			$window->destroy();
-		}
-
-	});
-	
-	my $mtable = def_table(10, 1, FALSE);
-	$mtable->attach_defaults($scrolled_win,0,1,0,9);
-	$mtable->attach($ok,0,1,9,10,'expand','shrink',2,2);
-	
-	$window->add ($mtable);
-	$window->show_all();
-	
-	
-	
+    });
+    $ok->signal_connect (clicked => sub{
+        if (defined $error){
+            message_dialog("$error",'error');
+            $error=undef;
+        }else {
+            $window->destroy();
+        }
+    });
+    my $mtable = def_table(10, 1, FALSE);
+    $mtable->attach_defaults($scrolled_win,0,1,0,9);
+    $mtable->attach($ok,0,1,9,10,'expand','shrink',2,2);
+    $window->add ($mtable);
+    $window->show_all();
 }
 
-
-
-
 ############
 #  get_def_setting
 ##########
-sub get_def_setting { 
-	my ($ipgen,$info)=@_;
-	my $table  = def_table (15, 15, TRUE);
-	my $table2 = def_table (15, 15, TRUE);
-	my $window = def_popwin_size(70,70,"Add definition file",'percent');
-	my $ok=def_image_button("icons/select.png",' Ok ');
-
-	my $scrwin = add_widget_to_scrolled_win($table2);
-
-	my $label=gen_label_help("You ","Select the Verilog file containing the definitions."); 
-	my $brows=def_image_button("icons/browse.png",' Browse');
-	$table->attach_defaults($label,0,10,0,1);
-	$table->attach($brows,10,12,1,2,'expand','shrink',2,2);
-	$table->attach_defaults($scrwin,0,15,2,14);
-	$table->attach($ok,6,9,14,15,'expand','shrink',2,2);
-
-	$window->add($table);
-	$window->show_all;
-
-
+sub get_def_setting {
+    my ($ipgen,$info)=@_;
+    my $table  = def_table (15, 15, TRUE);
+    my $table2 = def_table (15, 15, TRUE);
+    my $window = def_popwin_size(70,70,"Add definition file",'percent');
+    my $ok=def_image_button("icons/select.png",' Ok ');
+    my $scrwin = add_widget_to_scrolled_win($table2);
+    my $label=gen_label_help("You ","Select the Verilog file containing the definitions.");
+    my $brows=def_image_button("icons/browse.png",' Browse');
+    $table->attach_defaults($label,0,10,0,1);
+    $table->attach($brows,10,12,1,2,'expand','shrink',2,2);
+    $table->attach_defaults($scrwin,0,15,2,14);
+    $table->attach($ok,6,9,14,15,'expand','shrink',2,2);
+    $window->add($table);
+    $window->show_all;
 }
 
-
 ###########
-#	get description
+#    get description
 #########
-
 sub get_Description{
-	my ($ipgen,$info)=@_;
-	my $description = $ipgen->ipgen_get("description");	
-	my $table = def_table (15, 15, FALSE);
-	my $window =  def_popwin_size(40,40, "Add description",'percent');
-	my ($scrwin,$text_view)=create_txview();
-	#my $buffer = $textbox->get_buffer();
-	my $ok=def_image_button("icons/select.png",' Ok ');
-	$table->attach_defaults(gen_label_help("User can open the PDF file when opening IP parameter setting","IP Documentation file in PDF"),0,7,0,1);
-	$table->attach_defaults(gen_label_help("Description will be shown on IP generator text view when selecting this IP","Short Description"),5,10,1,2);
-	$table->attach_defaults(get_file_name_object ( $ipgen, 'description_pdf',undef,"pdf",undef),7,15,0,1);
-	$table->attach_defaults($scrwin,0,15,2,14);
-	$table->attach($ok,6,9,14,15,'expand','shrink',2,2);
-	my $text_buffer = $text_view->get_buffer;
-	if(defined $description) {$text_buffer->set_text($description)};
-	
-	$ok->signal_connect("clicked"=> sub {
-		$window->destroy;
-		 
-		 my $text = $text_buffer->get_text($text_buffer->get_bounds, TRUE);
-		 $ipgen->ipgen_add("description",$text);	
-		#print "$text\n";
-		
-	});
-	
-	$window->add($table);
-	$window->show_all();
-	
-}	
-
-
-
-
-
+    my ($ipgen,$info)=@_;
+    my $description = $ipgen->ipgen_get("description");
+    my $table = def_table (15, 15, FALSE);
+    my $window =  def_popwin_size(40,40, "Add description",'percent');
+    my ($scrwin,$text_view)=create_txview();
+    #my $buffer = $textbox->get_buffer();
+    my $ok=def_image_button("icons/select.png",' Ok ');
+    $table->attach_defaults(gen_label_help("User can open the PDF file when opening IP parameter setting","IP Documentation file in PDF"),0,7,0,1);
+    $table->attach_defaults(gen_label_help("Description will be shown on IP generator text view when selecting this IP","Short Description"),5,10,1,2);
+    $table->attach_defaults(get_file_name_object ( $ipgen, 'description_pdf',undef,"pdf",undef),7,15,0,1);
+    $table->attach_defaults($scrwin,0,15,2,14);
+    $table->attach($ok,6,9,14,15,'expand','shrink',2,2);
+    my $text_buffer = $text_view->get_buffer;
+    if(defined $description) {$text_buffer->set_text($description)};
+    $ok->signal_connect("clicked"=> sub {
+        $window->destroy;
+        my $text = $text_buffer->get_text($text_buffer->get_bounds, TRUE);
+        $ipgen->ipgen_add("description",$text);
+        #print "$text\n";
+    });
+    $window->add($table);
+    $window->show_all();
+}
 
 ##########
-#	gen_file_list
+#    gen_file_list
 #########
-
 sub gen_file_list{
-	my ($ipgen,$list_name,$window,$rename_file_en,$tick)=@_;
-	
-
-	my $table=def_table(10,10,FALSE);#	my ($row,$col,$homogeneous)=@_;
-	my $ok=def_image_button("icons/select.png",' Ok ');
-	my $scrolled_win = add_widget_to_scrolled_win($table);
-
-	$table->attach  (gen_label_in_center("File path"), 0, 5 , 0, 1,'expand','shrink',2,2);
-   	$table->attach (gen_label_help("The target name can contain any of Global variables e.g \$IP\$.h","Copy as"), 5, 9 , 0, 1,'expand','shrink',2,2) if(defined $rename_file_en);
-	$table->attach  (gen_label_in_center("$tick"), 9, 10 , 0, 1,'expand','shrink',2,2) if (defined $tick);
-	my $col=0;
+    my ($ipgen,$list_name,$window,$rename_file_en,$tick)=@_;
+    my $table=def_table(10,10,FALSE);#    my ($row,$col,$homogeneous)=@_;
+    my $ok=def_image_button("icons/select.png",' Ok ');
+    my $scrolled_win = add_widget_to_scrolled_win($table);
+    $table->attach  (gen_label_in_center("File path"), 0, 5 , 0, 1,'expand','shrink',2,2);
+    $table->attach (gen_label_help("The target name can contain any of Global variables e.g \$IP\$.h","Copy as"), 5, 9 , 0, 1,'expand','shrink',2,2) if(defined $rename_file_en);
+    $table->attach  (gen_label_in_center("$tick"), 9, 10 , 0, 1,'expand','shrink',2,2) if (defined $tick);
+    my $col=0;
     my $row=1;
-	my @files=  $ipgen->ipgen_get_list($list_name); #@{$ref};
-	my $file_num= scalar @files;	
-	foreach my $p(@files){
-			my ($path,$rename)=split('frename_sep_t',$p); 
-			my $entry=gen_entry($path);
-			my $entry2=gen_entry($rename);
-			
-			my $remove=def_image_button("icons/cancel.png");
-			$table->attach  ($entry, 0, 5 , $row, $row+1,'fill','shrink',2,2);
-			$table->attach  ($entry2, 5, 9 , $row, $row+1,'fill','shrink',2,2) if(defined $rename_file_en);
-			$table->attach ($remove, 10,11 , $row, $row+1,'expand','shrink',2,2);
-			my $check= gen_checkbutton();
-			if (defined $tick){				
-				$table->attach ($check, 9,10 , $row, $row+1,'expand','shrink',2,2);
-				$check-> signal_connect("toggled" => sub{
-					my @ticked_files=$ipgen->ipgen_get_list($list_name."_ticked");
-					@ticked_files =() if (!@ticked_files);
-					
-					
-					if($check->get_active()){
-						push(@ticked_files,$p);
-					}else{
-						@ticked_files=remove_scolar_from_array(\@ticked_files,$p);
-					}
-					$ipgen->ipgen_add($list_name."_ticked",\@ticked_files);
-				});	
-			
-			}
-			$row++;		
-			
-			
-			$remove->signal_connect("clicked"=> sub {
-				my @saved_files=$ipgen->ipgen_get_list($list_name);
-				@saved_files=remove_scolar_from_array(\@saved_files,$p);
-				$ipgen->ipgen_add($list_name,\@saved_files);
-				
-				my @ticked_files=$ipgen->ipgen_get_list($list_name."_ticked");
-				@ticked_files=remove_scolar_from_array(\@ticked_files,$p);
-				$ipgen->ipgen_add($list_name."_ticked",\@ticked_files);
-				
-				
-				$entry->destroy;
-				$entry2->destroy if(defined $rename_file_en);
-				$remove->destroy;
-			
-			});
-			$ok->signal_connect("clicked"=> sub {
-				if(defined $entry){
-					my $n= $entry->get_text();
-					   if(defined $rename_file_en){
-						$n= $n.'frename_sep_t'.$entry2->get_text() ;
-					   }
-					if($p ne $n){
-						my @saved_files=$ipgen->ipgen_get_list($list_name);
-						@saved_files=replace_in_array(\@saved_files,$p, $n);
-						$ipgen->ipgen_add($list_name,\@saved_files);
-					}
-				
-				}
-			
-			
-			
-			});
-		
-				
-		
-	}
-	
-	
-
-	$ok->signal_connect("clicked"=> sub {
-		$window->destroy;
-	});
-
+    my @files=  $ipgen->ipgen_get_list($list_name); #@{$ref};
+    my $file_num= scalar @files;
+    foreach my $p(@files){
+            my ($path,$rename)=split('frename_sep_t',$p);
+            my $entry=gen_entry($path);
+            my $entry2=gen_entry($rename);
+            my $remove=def_image_button("icons/cancel.png");
+            $table->attach  ($entry, 0, 5 , $row, $row+1,'fill','shrink',2,2);
+            $table->attach  ($entry2, 5, 9 , $row, $row+1,'fill','shrink',2,2) if(defined $rename_file_en);
+            $table->attach ($remove, 10,11 , $row, $row+1,'expand','shrink',2,2);
+            my $check= gen_checkbutton();
+            if (defined $tick){
+                $table->attach ($check, 9,10 , $row, $row+1,'expand','shrink',2,2);
+                $check-> signal_connect("toggled" => sub{
+                    my @ticked_files=$ipgen->ipgen_get_list($list_name."_ticked");
+                    @ticked_files =() if (!@ticked_files);
+                    if($check->get_active()){
+                        push(@ticked_files,$p);
+                    }else{
+                        @ticked_files=remove_scolar_from_array(\@ticked_files,$p);
+                    }
+                    $ipgen->ipgen_add($list_name."_ticked",\@ticked_files);
+                });
+            }
+            $row++;
+            $remove->signal_connect("clicked"=> sub {
+                my @saved_files=$ipgen->ipgen_get_list($list_name);
+                @saved_files=remove_scolar_from_array(\@saved_files,$p);
+                $ipgen->ipgen_add($list_name,\@saved_files);
+                my @ticked_files=$ipgen->ipgen_get_list($list_name."_ticked");
+                @ticked_files=remove_scolar_from_array(\@ticked_files,$p);
+                $ipgen->ipgen_add($list_name."_ticked",\@ticked_files);
+                $entry->destroy;
+                $entry2->destroy if(defined $rename_file_en);
+                $remove->destroy;
+            });
+            $ok->signal_connect("clicked"=> sub {
+                if(defined $entry){
+                    my $n= $entry->get_text();
+                    if(defined $rename_file_en){
+                        $n= $n.'frename_sep_t'.$entry2->get_text() ;
+                    }
+                    if($p ne $n){
+                        my @saved_files=$ipgen->ipgen_get_list($list_name);
+                        @saved_files=replace_in_array(\@saved_files,$p, $n);
+                        $ipgen->ipgen_add($list_name,\@saved_files);
+                    }
+                }
+            });
+    }
+    $ok->signal_connect("clicked"=> sub {
+        $window->destroy;
+    });
 #   while( $row<10){
-	#	my $label=gen_label_in_left(' ');
-	   # $table->attach_defaults ($label, 0, 1 , $row, $row+1);$row++;
-	#}
-
-	
-	return ($scrolled_win,$ok);
+    #    my $label=gen_label_in_left(' ');
+    # $table->attach_defaults ($label, 0, 1 , $row, $row+1);$row++;
+    #}
+    return ($scrolled_win,$ok);
 }
 
-
-
 sub get_param_info{
-	my ($ipgen,$saved_info)=@_;
-	my $table = def_table (15, 15, FALSE);
-	my $window =  def_popwin_size(50,50,"Add description",'percent');
-	my ($scrwin,$text_view)=create_txview();
-	my $ok=def_image_button("icons/select.png",' Ok ');
-	
-	$table->attach_defaults($scrwin,0,15,0,14);
-	$table->attach($ok,6,9,14,15,'expand','shrink',2,2);
-	my $text_buffer = $text_view->get_buffer;
-	if(defined $$saved_info) {$text_buffer->set_text($$saved_info)};
-	
-	$ok->signal_connect("clicked"=> sub {
-		$window->destroy;
-		 
-		 $$saved_info = $text_buffer->get_text($text_buffer->get_bounds, TRUE);
-		 
-		
-	});
-	
-	$window->add($table);
-	$window->show_all();
-	
-	
-}	
-
-
+    my ($ipgen,$saved_info)=@_;
+    my $table = def_table (15, 15, FALSE);
+    my $window =  def_popwin_size(50,50,"Add description",'percent');
+    my ($scrwin,$text_view)=create_txview();
+    my $ok=def_image_button("icons/select.png",' Ok ');
+    $table->attach_defaults($scrwin,0,15,0,14);
+    $table->attach($ok,6,9,14,15,'expand','shrink',2,2);
+    my $text_buffer = $text_view->get_buffer;
+    if(defined $$saved_info) {$text_buffer->set_text($$saved_info)};
+    $ok->signal_connect("clicked"=> sub {
+        $window->destroy;
+        $$saved_info = $text_buffer->get_text($text_buffer->get_bounds, TRUE);
+    });
+    $window->add($table);
+    $window->show_all();
+}
 
 sub interface_info_box {
-	my($intfc,$ipgen,$info)=@_;
-	my $table=def_table(7,7,FALSE);
-	my @sokets=$ipgen->ipgen_list_sokets;
-	my @plugs=$ipgen->ipgen_list_plugs;
-	
-	my @positions=(0,1,2,4,5,6,7);
-	
-	
-	my $row=0;
-	my $col=0;
-	$table->attach (gen_label_in_center(" Interface name"), $positions[0], $positions[1], $row, $row+1,'expand','shrink',2,2);
-	$table->attach (gen_label_in_center("Type"), $positions[1], $positions[2], $row, $row+1,'expand','shrink',2,2);
-	$table->attach (gen_label_in_left("Interface Num"), $positions[2], $positions[3], $row, $row+1,'expand','shrink',2,2);
-	
-	$row++;
-	my @type_list=('plug','socket');
-	
-	foreach my $p( @sokets){
-		#my ($range,$type,$intfc_name,$intfc_port)=$ipgen->ipgen_get_port($p);
-		my ($type,$value,$connection_num)= $ipgen->ipgen_get_socket($p);
-		my $label_name=gen_label_in_center($p);
-		my $combo_type=gen_combo(\@type_list,1);
-		my $remove=	def_image_button('icons/cancel.png','Remove');
-		my $name_setting=def_image_button('icons/setting.png');
-		$remove->signal_connect ('clicked'=> sub{
-			$ipgen->ipgen_remove_socket($p);
-			set_gui_status($ipgen,'intfc_changed',0);		
-			
-			}  );
-		$name_setting->signal_connect ('clicked'=> sub{
-			get_intfc_setting($ipgen,$p,'socket');
-			
-			
-		});	
-		$combo_type	->signal_connect ('changed'=> sub{
-			$ipgen->ipgen_remove_socket($p);
-			add_intfc_to_ip($intfc,$ipgen,$p,'plug',$info);
-				
-			}  );
-		$table->attach ($remove, $positions[4], $positions[5], $row, $row+1,'expand','shrink',2,2);
+    my($intfc,$ipgen,$info)=@_;
+    my $table=def_table(7,7,FALSE);
+    my @sokets=$ipgen->ipgen_list_sokets;
+    my @plugs=$ipgen->ipgen_list_plugs;
+    my @positions=(0,1,2,4,5,6,7);
+    my $row=0;
+    my $col=0;
+    $table->attach (gen_label_in_center(" Interface name"), $positions[0], $positions[1], $row, $row+1,'expand','shrink',2,2);
+    $table->attach (gen_label_in_center("Type"), $positions[1], $positions[2], $row, $row+1,'expand','shrink',2,2);
+    $table->attach (gen_label_in_left("Interface Num"), $positions[2], $positions[3], $row, $row+1,'expand','shrink',2,2);
+    $row++;
+    my @type_list=('plug','socket');
+    foreach my $p( @sokets){
+        #my ($range,$type,$intfc_name,$intfc_port)=$ipgen->ipgen_get_port($p);
+        my ($type,$value,$connection_num)= $ipgen->ipgen_get_socket($p);
+        my $label_name=gen_label_in_center($p);
+        my $combo_type=gen_combo(\@type_list,1);
+        my $remove=    def_image_button('icons/cancel.png','Remove');
+        my $name_setting=def_image_button('icons/setting.png');
+        $remove->signal_connect ('clicked'=> sub{
+            $ipgen->ipgen_remove_socket($p);
+            set_gui_status($ipgen,'intfc_changed',0);
+            }  );
+        $name_setting->signal_connect ('clicked'=> sub{
+            get_intfc_setting($ipgen,$p,'socket');
+        });
+        $combo_type    ->signal_connect ('changed'=> sub{
+            $ipgen->ipgen_remove_socket($p);
+            add_intfc_to_ip($intfc,$ipgen,$p,'plug',$info);
+            }  );
+        $table->attach ($remove, $positions[4], $positions[5], $row, $row+1,'expand','shrink',2,2);
+        if ($type eq 'num'){
+            my ($type_box,$type_spin)=gen_spin_help ('Define the number of this interface in module', 1,1024,1);
+            $type_box->pack_start($name_setting,FALSE,FALSE,0);
+            $type_spin->set_value($value);
+            my $advance_button=def_image_button('icons/advance.png','separate');
+            $table->attach ($type_box, $positions[2], $positions[3], $row, $row+1,'expand','shrink',2,2);
+            $table->attach ($advance_button, $positions[3], $positions[4], $row, $row+1,'expand','shrink',2,2);
+            $type_spin->signal_connect("value_changed"=>sub{
+                my $wiget=shift;
+                my $num=$wiget->get_value_as_int();
+                $ipgen->ipgen_add_soket($p,'num',$num);
+                set_gui_status($ipgen,'intfc_changed',0);
+            });
+            $advance_button->signal_connect("clicked"=>sub{
+                $ipgen->ipgen_add_soket($p,'param');
+                set_gui_status($ipgen,'intfc_changed',0);
+            });
+        }
+        else {
+            my @parameters=$ipgen->ipgen_get_all_parameters_list();
+            my $pos= get_scolar_pos( $value,@parameters);
+            if(!defined $pos){
+                $pos=0;
+                $ipgen->ipgen_add_soket($p,'param',$parameters[0]);
+            }
+            my ($type_box,$type_combo)=gen_combo_help ('Define the parameter which determine the number of this interface in module',\@parameters,$pos);
+            $type_box->pack_start($name_setting,FALSE,FALSE,0);
+            my $advance_button=def_image_button('icons/advance.png','concatenate');
+            $table->attach ($type_box, $positions[2], $positions[3], $row, $row+1,'expand','shrink',2,2);
+            $table->attach ($advance_button, $positions[3], $positions[4], $row, $row+1,'expand','shrink',2,2);
+            $type_combo->signal_connect("changed"=>sub{
+                my $wiget=shift;
+                my $value=$wiget->get_active_text();
+                $ipgen->ipgen_add_soket($p,'param',$value);
+                set_gui_status($ipgen,'intfc_changed',0);
+            });
+            $advance_button->signal_connect("clicked"=>sub{
+                $ipgen->ipgen_add_soket($p,'num',0);
+                set_gui_status($ipgen,'intfc_changed',0);
+            });
+        }
+        $table->attach ($label_name, $positions[0], $positions[1], $row, $row+1,'expand','shrink',2,2);
+        $table->attach ($combo_type, $positions[1], $positions[2], $row, $row+1,'expand','shrink',2,2);
+        $row++;
+    }
+    foreach my $q( @plugs){
+        #my ($range,$type,$intfc_name,$intfc_port)=$ipgen->ipgen_get_port($p);
+        my ($type,$value)= $ipgen->ipgen_get_plug($q);
+        my $label_name=gen_label_in_center($q);
+        my $combo_type=gen_combo(\@type_list,0);
+        my $remove=    def_image_button('icons/cancel.png','Remove');
+        my $name_setting=def_image_button('icons/setting.png');
+        $table->attach ($remove, $positions[4], $positions[5], $row, $row+1,'expand','shrink',2,2);
+        $remove->signal_connect ('clicked'=> sub{
+            $ipgen->ipgen_remove_plug($q);
+            set_gui_status($ipgen,'intfc_changed',0);
+            }  );
+        $name_setting->signal_connect ('clicked'=> sub{
+            get_intfc_setting($ipgen,$q,'plug');
+        }    );
+        $combo_type    ->signal_connect ('changed'=> sub{
+            $ipgen->ipgen_remove_plug($q);
+            add_intfc_to_ip($intfc,$ipgen,$q,'socket',$info);
+            }  );
+        #my $range_entry=gen_entry($range);
+        if ($type eq 'num'){
+            my ($type_box,$type_spin)=gen_spin_help ('Define the number of this interface in module', 1,1024,1);
+            $type_box->pack_start($name_setting,FALSE,FALSE,0);
+            $type_spin->set_value($value);
+            $table->attach ($type_box, $positions[2], $positions[3], $row, $row+1,'expand','shrink',2,2);
+            $type_spin->signal_connect("value_changed"=>sub{
+                my $wiget=shift;
+                my $num=$wiget->get_value_as_int();
+                $ipgen->ipgen_add_plug($q,'num',$num);
+                set_gui_status($ipgen,'intfc_changed',0);
+            });
+        }
+        $table->attach ($label_name, $positions[0], $positions[1], $row, $row+1,'expand','shrink',2,2);
+        $table->attach ($combo_type, $positions[1], $positions[2], $row, $row+1,'expand','shrink',2,2);
+        #$table->attach_defaults ($range_entry, 2, 4, $row, $row+1);
+        #wishbone address seting
+        #print "$q eq 'wb_slave'\n";
+        if($q eq 'wb_slave'){
+            my ($saved_addr,$saved_width)=$ipgen->ipgen_get_wb_addr($q,0);
+            my $addr;
+            if(!defined $saved_addr){
+                $addr=    def_image_button('icons/warning.png');
+                $addr->signal_connect ('clicked'=> sub{
+                    message_dialog("Wishbone slave address range has not been set yet! ");
+                }  );
+            }else{
+                $addr=    def_image_button('icons/select.png');
+            }
+            $table->attach ($addr, $positions[5], $positions[6], $row, $row+1,'expand','shrink',2,2);
+        }
+        $row++;
+    }
+    return add_widget_to_scrolled_win($table);
+}
 
-	
-		if ($type eq 'num'){
-			my ($type_box,$type_spin)=gen_spin_help ('Define the number of this interface in module', 1,1024,1);
-			$type_box->pack_start($name_setting,FALSE,FALSE,0);
-			$type_spin->set_value($value);
-			my $advance_button=def_image_button('icons/advance.png','separate');
-			$table->attach ($type_box, $positions[2], $positions[3], $row, $row+1,'expand','shrink',2,2);
-			$table->attach ($advance_button, $positions[3], $positions[4], $row, $row+1,'expand','shrink',2,2);
-			$type_spin->signal_connect("value_changed"=>sub{
-				my $wiget=shift;
-				my $num=$wiget->get_value_as_int();
-				$ipgen->ipgen_add_soket($p,'num',$num);
-				set_gui_status($ipgen,'intfc_changed',0);
-				
-			});
-			$advance_button->signal_connect("clicked"=>sub{
-				$ipgen->ipgen_add_soket($p,'param');
-				set_gui_status($ipgen,'intfc_changed',0);
-				
-			});	
-			
-		}
-		else {
-			my @parameters=$ipgen->ipgen_get_all_parameters_list();
-			my $pos= get_scolar_pos( $value,@parameters);
-			if(!defined $pos){
-				$pos=0;
-				$ipgen->ipgen_add_soket($p,'param',$parameters[0]);
-			}
-			my ($type_box,$type_combo)=gen_combo_help ('Define the parameter which determine the number of this interface in module',\@parameters,$pos);
-			$type_box->pack_start($name_setting,FALSE,FALSE,0);
-			my $advance_button=def_image_button('icons/advance.png','concatenate');
-			$table->attach ($type_box, $positions[2], $positions[3], $row, $row+1,'expand','shrink',2,2);
-			$table->attach ($advance_button, $positions[3], $positions[4], $row, $row+1,'expand','shrink',2,2);	
-			$type_combo->signal_connect("changed"=>sub{
-				my $wiget=shift;
-				my $value=$wiget->get_active_text();
-				$ipgen->ipgen_add_soket($p,'param',$value);
-				set_gui_status($ipgen,'intfc_changed',0);
-				
-			});
-			$advance_button->signal_connect("clicked"=>sub{
-				$ipgen->ipgen_add_soket($p,'num',0);
-				set_gui_status($ipgen,'intfc_changed',0);
-				
-			});	
-			
-		}	
-		
-		
-		
-		
-		
-		
-		$table->attach ($label_name, $positions[0], $positions[1], $row, $row+1,'expand','shrink',2,2);
-		$table->attach ($combo_type, $positions[1], $positions[2], $row, $row+1,'expand','shrink',2,2);
-		
-		
-		
-			
-		$row++;
-	}	
-	foreach my $q( @plugs){
-		#my ($range,$type,$intfc_name,$intfc_port)=$ipgen->ipgen_get_port($p);
-		my ($type,$value)= $ipgen->ipgen_get_plug($q);
-		my $label_name=gen_label_in_center($q);
-		my $combo_type=gen_combo(\@type_list,0);
-		my $remove=	def_image_button('icons/cancel.png','Remove');
-		my $name_setting=def_image_button('icons/setting.png');
-		
-		$table->attach ($remove, $positions[4], $positions[5], $row, $row+1,'expand','shrink',2,2);
-		$remove->signal_connect ('clicked'=> sub{
-			$ipgen->ipgen_remove_plug($q);
-			set_gui_status($ipgen,'intfc_changed',0);		
-			
-			}  );
-		$name_setting->signal_connect ('clicked'=> sub{
-			get_intfc_setting($ipgen,$q,'plug');
-			
-			
-		}	);	
-		$combo_type	->signal_connect ('changed'=> sub{
-			$ipgen->ipgen_remove_plug($q);
-			add_intfc_to_ip($intfc,$ipgen,$q,'socket',$info);
-				
-			}  );	
-		#my $range_entry=gen_entry($range);
-		if ($type eq 'num'){
-			my ($type_box,$type_spin)=gen_spin_help ('Define the number of this interface in module', 1,1024,1);
-			$type_box->pack_start($name_setting,FALSE,FALSE,0);
-			$type_spin->set_value($value);
-			$table->attach ($type_box, $positions[2], $positions[3], $row, $row+1,'expand','shrink',2,2);
-			$type_spin->signal_connect("value_changed"=>sub{
-				my $wiget=shift;
-				my $num=$wiget->get_value_as_int();
-				$ipgen->ipgen_add_plug($q,'num',$num);
-				set_gui_status($ipgen,'intfc_changed',0);
-				
-			});
-			
-		}	
-		$table->attach ($label_name, $positions[0], $positions[1], $row, $row+1,'expand','shrink',2,2);
-		$table->attach ($combo_type, $positions[1], $positions[2], $row, $row+1,'expand','shrink',2,2);
-		#$table->attach_defaults ($range_entry, 2, 4, $row, $row+1);
-		
-		#wishbone address seting
-		#print "$q eq 'wb_slave'\n";
-		if($q eq 'wb_slave'){
-			my ($saved_addr,$saved_width)=$ipgen->ipgen_get_wb_addr($q,0);
-			my $addr;
-			if(!defined $saved_addr){
-				 $addr=	def_image_button('icons/warning.png');
-				 $addr->signal_connect ('clicked'=> sub{
-				     message_dialog("Wishbone slave address range has not been set yet! ");		
-				
-				}  );
-			}else{
-				 $addr=	def_image_button('icons/select.png');
-				
-			}	
-			$table->attach ($addr, $positions[5], $positions[6], $row, $row+1,'expand','shrink',2,2);
-			
-			
-		}	
-		
-			
-		$row++;
-	}		
-	
-	return add_widget_to_scrolled_win($table);
-	
-}	
 ########
-#	get_intfc_setting
+#    get_intfc_setting
 ########
-
 sub get_intfc_setting{
-	
-	my ($ipgen,$intfc_name, $intfc_type)=@_;
-	my $window =  def_popwin_size(70,70,"Interface parameter setting",'percent');
-	my $table=def_table(7,6,FALSE);
-	my $ok = def_image_button('icons/select.png','OK');
-	
-	my $scrolled_win = add_widget_to_scrolled_win($table);
-	
-	#title
-	my $label1=gen_label_in_left("interface name");
-	$table->attach ( $label1,0,2,0,1,'expand','shrink',2,2);
-	
-	
-	
-	
-	my ($type,$value);
-	if($intfc_type eq 'plug'){
-		 ($type,$value)= $ipgen->ipgen_get_plug($intfc_name);
-	}else {
-		 ($type,$value)= $ipgen->ipgen_get_socket($intfc_name);
-		
-	}		
-	if ($type ne 'num'){ $value=1;}
-	my $i=0;
-	for ( $i=0; $i < $value; $i++) {
-		#intfc name
-		my $saved_name;
-		my $number=$i;
-		if($intfc_type eq 'plug')	{$saved_name= $ipgen->ipgen_get_plug_name($intfc_name,$number);}
-		else						{$saved_name= $ipgen->ipgen_get_socket_name($intfc_name,$number);}
-		my  $entry_name=gen_entry($saved_name);
-		
-		$table->attach($entry_name,0,2,$i+1,$i+2,'expand','shrink',2,2);
-		$ok->signal_connect('clicked'=>sub{
-				my $new_name=$entry_name->get_text();
-				#print "my new name is: $new_name\n";
-				if($intfc_type eq 'plug'){ $ipgen->ipgen_set_plug_name($intfc_name,$number,$new_name); }
-				else { 					   $ipgen->ipgen_set_socket_name($intfc_name,$number,$new_name);}
-			
-			});
-		
-	
-	}	
-
-	
-	#wishbone addr
-	if($intfc_name eq 'wb_slave' &&  $intfc_type eq 'plug'){ 
-		my $label2=gen_label_in_center("address range: (start end name)");
-		my $label3=gen_label_help("This field defines the total memory_map address  which is required by this module in byte. ( =2 ^ block_address_width).
+    my ($ipgen,$intfc_name, $intfc_type)=@_;
+    my $window =  def_popwin_size(70,70,"Interface parameter setting",'percent');
+    my $table=def_table(7,6,FALSE);
+    my $ok = def_image_button('icons/select.png','OK');
+    my $scrolled_win = add_widget_to_scrolled_win($table);
+    #title
+    my $label1=gen_label_in_left("interface name");
+    $table->attach ( $label1,0,2,0,1,'expand','shrink',2,2);
+    my ($type,$value);
+    if($intfc_type eq 'plug'){
+        ($type,$value)= $ipgen->ipgen_get_plug($intfc_name);
+    }else {
+        ($type,$value)= $ipgen->ipgen_get_socket($intfc_name);
+    }
+    if ($type ne 'num'){ $value=1;}
+    my $i=0;
+    for ( $i=0; $i < $value; $i++) {
+        #intfc name
+        my $saved_name;
+        my $number=$i;
+        if($intfc_type eq 'plug')    {$saved_name= $ipgen->ipgen_get_plug_name($intfc_name,$number);}
+        else                        {$saved_name= $ipgen->ipgen_get_socket_name($intfc_name,$number);}
+        my  $entry_name=gen_entry($saved_name);
+        $table->attach($entry_name,0,2,$i+1,$i+2,'expand','shrink',2,2);
+        $ok->signal_connect('clicked'=>sub{
+                my $new_name=$entry_name->get_text();
+                #print "my new name is: $new_name\n";
+                if($intfc_type eq 'plug'){ $ipgen->ipgen_set_plug_name($intfc_name,$number,$new_name); }
+                else {                        $ipgen->ipgen_set_socket_name($intfc_name,$number,$new_name);}
+            });
+    }
+    #wishbone addr
+    if($intfc_name eq 'wb_slave' &&  $intfc_type eq 'plug'){
+        my $label2=gen_label_in_center("address range: (start end name)");
+        my $label3=gen_label_help("This field defines the total memory_map address  which is required by this module in byte. ( =2 ^ block_address_width).
 You can define a fixed value or assign it to any of module parameter","block address width");
-
-		$table->attach ( $label2,2,5,0,1,'expand','shrink',2,2);
-		$table->attach ( $label3,5,6,0,1,'expand','shrink',2,2);
-		
-		my $plug=$intfc_name;
-		my $wb= wb_addr->wb_addr_new();
-		my @ip_names=$wb->wb_list_names();
-		my @list;
-		foreach my $p(@ip_names){
-			my($start,$end,$cashed,$size)=$wb->wb_get_addr_info($p);
-			push (@list,"$start\t$end\t\t$p");
-		
-		}
-		
-		my ($type,$value,$connection_num)=$ipgen->ipgen_get_plug($plug);
-		   $i=0;
-		
-		for ( $i=0; $i < $value; $i++) {
-			my ($saved_addr,$saved_width)=$ipgen->ipgen_get_wb_addr($plug,$i);
-			my $num=$i;
-			my $pos;
-			if(!defined $saved_addr){
-				$pos=0;
-				$saved_width=1;
-				$ipgen->ipgen_save_wb_addr($plug,$num,$list[0],1);
-			}
-			else{
-				$pos= get_scolar_pos($saved_addr,@list);	
-			}	
-			
-			my $name_combo=gen_combo(\@list,$pos);
-			my $sbox=def_hbox(FALSE,0);
-			my $widget;
-			my $size_lab;
-			my @l=("Fixed","Parameterizable");
-
-			if(!defined $saved_width){
-				$pos=0;
-				$saved_width=1;
-
-			}
-			else{
-				if(is_integer($saved_width)){
-			 		 $pos= 0; 
-					 $widget=gen_spin(1,31,1);
-					 $widget->set_value($saved_width);
-					 my $d=2**$saved_width;
-					 $size_lab=gen_label_in_left(metric_conversion($d). " Bytes");
-				} else{
-					$pos= 1; 
-					my @parameters=$ipgen->ipgen_get_all_parameters_list();
-					my $p=get_scolar_pos($saved_width,@parameters);
-
-					$widget=gen_combo(\@parameters, $p); 
-					$size_lab=gen_label_in_left(" ");
-
-				}
-
-
-			}
-
-
-			
-			my $comb=gen_combo(\@l, $pos); 
-			#$widget->set_value($saved_width);
-			$sbox->pack_start($comb,FALSE,FALSE,3);
-			$sbox->pack_end($widget,FALSE,FALSE,3);
-			$sbox->pack_end($size_lab,FALSE,FALSE,3);
-			$comb->signal_connect('changed'=>sub{			
-				my $condition=$comb->get_active_text();
-				$widget->destroy;
-				$size_lab->destroy;
-				my @parameters=$ipgen->ipgen_get_all_parameters_list();
-				$widget=($condition eq "Fixed" )? gen_spin(1,31,1):gen_combo(\@parameters, 0); 
-				$size_lab=($condition eq "Fixed" )? gen_label_in_left("2 Bytes"):  gen_label_in_left(" ");
-				$sbox->pack_end($widget,FALSE,FALSE,3);
-				$sbox->pack_end($size_lab,FALSE,FALSE,3);
-				$sbox->show_all();
-				$widget->signal_connect('changed'=>sub{	
-					$size_lab->destroy;
-					my $in=$comb->get_active_text();
-					my $width=($in eq "Fixed" )? $widget->get_value_as_int(): $widget->get_active_text() ;
-					my $d=($in eq "Fixed" )? 2**$width:0;
-				
-					$size_lab=($in eq "Fixed" )? gen_label_in_left( metric_conversion($d). " Bytes"):gen_label_in_left(" ");
-					$sbox->pack_end($size_lab,FALSE,FALSE,3);
-					$sbox->show_all();
-				});
-			});
-			$widget->signal_connect('changed'=>sub{	
-				$size_lab->destroy;
-				my $in=$comb->get_active_text();
-				my $width=($in eq "Fixed" )? $widget->get_value_as_int(): $widget->get_active_text() ;
-				my $d=($in eq "Fixed" )? 2**$width:0;
-				
-				$size_lab=($in eq "Fixed" )? gen_label_in_left(metric_conversion($d). " Bytes"):gen_label_in_left(" ");
-				$sbox->pack_end($size_lab,FALSE,FALSE,3);
-				$sbox->show_all();
-			});
-		
-			$table->attach ($name_combo,2,5,$i+1,$i+2 ,'expand','shrink',2,2);
-			$table->attach ($sbox,5,6,$i+1,$i+2,'expand','shrink',2,2);
-			$ok->signal_connect('clicked'=>sub{
-				my $addr=$name_combo->get_active_text();
-				my $in=$comb->get_active_text();
-				my $width=($in eq "Fixed" )? $widget->get_value_as_int(): $widget->get_active_text() ;
-				$ipgen->ipgen_save_wb_addr($plug,$num,$addr,$width);
-			
-			});
-		
-
-		}
-		
-		
-	
-	}
-
-	
-
-	
-
-	my $mtable = def_table(10, 1, FALSE);
-	$mtable->attach_defaults($scrolled_win,0,1,0,9);
-	$mtable->attach($ok,0,1,9,10,'expand','shrink',2,2);
-	
-	$window->add ($mtable);
-	$window->show_all();
-
-
-
-
-	 $ok->signal_connect('clicked'=>sub{
-			$window->destroy;
-			set_gui_status($ipgen,"interface_selected",1);
-			 
-		 } );
-
-	
-
-
+        $table->attach ( $label2,2,5,0,1,'expand','shrink',2,2);
+        $table->attach ( $label3,5,6,0,1,'expand','shrink',2,2);
+        my $plug=$intfc_name;
+        my $wb= wb_addr->wb_addr_new();
+        my @ip_names=$wb->wb_list_names();
+        my @list;
+        foreach my $p(@ip_names){
+            my($start,$end,$cashed,$size)=$wb->wb_get_addr_info($p);
+            push (@list,"$start\t$end\t\t$p");
+        }
+        my ($type,$value,$connection_num)=$ipgen->ipgen_get_plug($plug);
+        $i=0;
+        for ( $i=0; $i < $value; $i++) {
+            my ($saved_addr,$saved_width)=$ipgen->ipgen_get_wb_addr($plug,$i);
+            my $num=$i;
+            my $pos;
+            if(!defined $saved_addr){
+                $pos=0;
+                $saved_width=1;
+                $ipgen->ipgen_save_wb_addr($plug,$num,$list[0],1);
+            }
+            else{
+                $pos= get_scolar_pos($saved_addr,@list);
+            }
+            my $name_combo=gen_combo(\@list,$pos);
+            my $sbox=def_hbox(FALSE,0);
+            my $widget;
+            my $size_lab;
+            my @l=("Fixed","Parameterizable");
+            if(!defined $saved_width){
+                $pos=0;
+                $saved_width=1;
+            }
+            else{
+                if(is_integer($saved_width)){
+                    $pos= 0;
+                    $widget=gen_spin(1,31,1);
+                    $widget->set_value($saved_width);
+                    my $d=2**$saved_width;
+                    $size_lab=gen_label_in_left(metric_conversion($d). " Bytes");
+                } else{
+                    $pos= 1;
+                    my @parameters=$ipgen->ipgen_get_all_parameters_list();
+                    my $p=get_scolar_pos($saved_width,@parameters);
+                    $widget=gen_combo(\@parameters, $p);
+                    $size_lab=gen_label_in_left(" ");
+                }
+            }
+            my $comb=gen_combo(\@l, $pos);
+            #$widget->set_value($saved_width);
+            $sbox->pack_start($comb,FALSE,FALSE,3);
+            $sbox->pack_end($widget,FALSE,FALSE,3);
+            $sbox->pack_end($size_lab,FALSE,FALSE,3);
+            $comb->signal_connect('changed'=>sub{
+                my $condition=$comb->get_active_text();
+                $widget->destroy;
+                $size_lab->destroy;
+                my @parameters=$ipgen->ipgen_get_all_parameters_list();
+                $widget=($condition eq "Fixed" )? gen_spin(1,31,1):gen_combo(\@parameters, 0);
+                $size_lab=($condition eq "Fixed" )? gen_label_in_left("2 Bytes"):  gen_label_in_left(" ");
+                $sbox->pack_end($widget,FALSE,FALSE,3);
+                $sbox->pack_end($size_lab,FALSE,FALSE,3);
+                $sbox->show_all();
+                $widget->signal_connect('changed'=>sub{
+                    $size_lab->destroy;
+                    my $in=$comb->get_active_text();
+                    my $width=($in eq "Fixed" )? $widget->get_value_as_int(): $widget->get_active_text() ;
+                    my $d=($in eq "Fixed" )? 2**$width:0;
+                    $size_lab=($in eq "Fixed" )? gen_label_in_left( metric_conversion($d). " Bytes"):gen_label_in_left(" ");
+                    $sbox->pack_end($size_lab,FALSE,FALSE,3);
+                    $sbox->show_all();
+                });
+            });
+            $widget->signal_connect('changed'=>sub{
+                $size_lab->destroy;
+                my $in=$comb->get_active_text();
+                my $width=($in eq "Fixed" )? $widget->get_value_as_int(): $widget->get_active_text() ;
+                my $d=($in eq "Fixed" )? 2**$width:0;
+                $size_lab=($in eq "Fixed" )? gen_label_in_left(metric_conversion($d). " Bytes"):gen_label_in_left(" ");
+                $sbox->pack_end($size_lab,FALSE,FALSE,3);
+                $sbox->show_all();
+            });
+            $table->attach ($name_combo,2,5,$i+1,$i+2 ,'expand','shrink',2,2);
+            $table->attach ($sbox,5,6,$i+1,$i+2,'expand','shrink',2,2);
+            $ok->signal_connect('clicked'=>sub{
+                my $addr=$name_combo->get_active_text();
+                my $in=$comb->get_active_text();
+                my $width=($in eq "Fixed" )? $widget->get_value_as_int(): $widget->get_active_text() ;
+                $ipgen->ipgen_save_wb_addr($plug,$num,$addr,$width);
+            });
+        }
+    }
+    my $mtable = def_table(10, 1, FALSE);
+    $mtable->attach_defaults($scrolled_win,0,1,0,9);
+    $mtable->attach($ok,0,1,9,10,'expand','shrink',2,2);
+    $window->add ($mtable);
+    $window->show_all();
+    $ok->signal_connect('clicked'=>sub{
+            $window->destroy;
+            set_gui_status($ipgen,"interface_selected",1);
+    } );
 }
 
-
-
-
-
-
 #############
 #  add_intfc_to_ip
 ##############
-
-
 sub add_intfc_to_ip{
-	my ($intfc,$ipgen,$infc_name,$infc_type,$info)=@_;
-	if($infc_type eq 'socket'){ 
-		my ($connection_num,$connect_to)=$intfc->get_socket($infc_name);
-		$ipgen->ipgen_add_soket($infc_name,'num',1,$connection_num);
-	}
-	else { $ipgen->ipgen_add_plug($infc_name,'num',1);}
-	set_gui_status($ipgen,"interface_selected",1);
-	
-}	
-
+    my ($intfc,$ipgen,$infc_name,$infc_type,$info)=@_;
+    if($infc_type eq 'socket'){
+        my ($connection_num,$connect_to)=$intfc->get_socket($infc_name);
+        $ipgen->ipgen_add_soket($infc_name,'num',1,$connection_num);
+    }
+    else { $ipgen->ipgen_add_plug($infc_name,'num',1);}
+    set_gui_status($ipgen,"interface_selected",1);
+}
 
 sub add_plug_interface_from_tree{
-	my ($ipgen,$category,$infc_name,$info)=@_;
-	$ipgen->ipgen_add_plug($infc_name,'num',1);
-	set_gui_status($ipgen,"interface_selected",1);	
+    my ($ipgen,$category,$infc_name,$info)=@_;
+    $ipgen->ipgen_add_plug($infc_name,'num',1);
+    set_gui_status($ipgen,"interface_selected",1);
 }
 
 sub show_interface_description {
-	my ($soc,$category,$infc_name,$info)=@_;
-	my $intfc=interface->interface_new();
-	my $describ=$intfc->get_description($category,$infc_name);  	
-	if($describ){
-		show_info($info,$describ);		
-	}
-	undef $intfc;
+    my ($soc,$category,$infc_name,$info)=@_;
+    my $intfc=interface->interface_new();
+    my $describ=$intfc->get_description($category,$infc_name);
+    if($describ){
+        show_info($info,$describ);
+    }
+    undef $intfc;
 }
 
 #################
-#	get_list_of_all_interfaces
+#    get_list_of_all_interfaces
 ################
-
 sub get_list_of_all_interfaces{
-	my ($ipgen)=@_;
-	my @sockets	=$ipgen->ipgen_list_sokets();
-	my @plugs	=$ipgen->ipgen_list_plugs();
-	my @interfaces=('IO');
-	my @interfaces_name=('IO');
-	foreach my $p( @sockets){
-		my ($type,$value)=  $ipgen->ipgen_get_socket($p);
-		if($type eq 'num'){
-				for(my $i=0; $i<$value; $i++){
-					push(@interfaces,"socket:$p\[$i\]");
-					my $socket_name=$ipgen->ipgen_get_socket_name($p,$i);
-					push(@interfaces_name,"socket:$socket_name");
-				}#for	
-			
-		}#if
-		else {
-			push(@interfaces,"socket:$p\[array\]");
-			my $socket_name=$ipgen->ipgen_get_socket_name($p,0);
-			push(@interfaces_name,"socket:$socket_name");
-			
-			
-		}#else		
-		
-	}#foreach	
-	foreach my $p( @plugs){
-		my ($type,$value)=  $ipgen->ipgen_get_plug($p);
-		if($type eq 'num'){
-				for(my $i=0; $i<$value; $i++){
-					push(@interfaces,"plug:$p\[$i\]");
-					my $plug_name=$ipgen->ipgen_get_plug_name($p,$i);
-					push(@interfaces_name,"plug:$plug_name");
-					
-				}#for	
-			
-		}#if
-		else {
-			my $plug_name=$ipgen->ipgen_get_plug_name($p,0);
-			push(@interfaces,"plug:$p\[array\]");
-			push(@interfaces_name,"plug:$plug_name");
-			
-			
-		}#else		
-		
-	}#foreach	
-	return (\@interfaces_name,\@interfaces);
-	
-}	
+    my ($ipgen)=@_;
+    my @sockets    =$ipgen->ipgen_list_sokets();
+    my @plugs    =$ipgen->ipgen_list_plugs();
+    my @interfaces=('IO');
+    my @interfaces_name=('IO');
+    foreach my $p( @sockets){
+        my ($type,$value)=  $ipgen->ipgen_get_socket($p);
+        if($type eq 'num'){
+                for(my $i=0; $i<$value; $i++){
+                    push(@interfaces,"socket:$p\[$i\]");
+                    my $socket_name=$ipgen->ipgen_get_socket_name($p,$i);
+                    push(@interfaces_name,"socket:$socket_name");
+                }#for
+        }#if
+        else {
+            push(@interfaces,"socket:$p\[array\]");
+            my $socket_name=$ipgen->ipgen_get_socket_name($p,0);
+            push(@interfaces_name,"socket:$socket_name");
+        }#else
+    }#foreach
+    foreach my $p( @plugs){
+        my ($type,$value)=  $ipgen->ipgen_get_plug($p);
+        if($type eq 'num'){
+                for(my $i=0; $i<$value; $i++){
+                    push(@interfaces,"plug:$p\[$i\]");
+                    my $plug_name=$ipgen->ipgen_get_plug_name($p,$i);
+                    push(@interfaces_name,"plug:$plug_name");
+                }#for
+        }#if
+        else {
+            my $plug_name=$ipgen->ipgen_get_plug_name($p,0);
+            push(@interfaces,"plug:$p\[array\]");
+            push(@interfaces_name,"plug:$plug_name");
+        }#else
+    }#foreach
+    return (\@interfaces_name,\@interfaces);
+}
 
 sub gen_intfc_port_combo{
-	my ($intfc,$ipgen,$intfc_name,$porttype,$portname)=@_;
-	
-	my($type,$name,$num)= split("[:\[ \\]]", $intfc_name);
-	my @all_ports;
-	my @ports;
-	
-	if($type eq 'socket'){
-		@all_ports= $intfc->get_socket_port_list($name);
-		foreach my $p(@all_ports){
-			my ($r,$t,$c)=$intfc->get_port_info_of_socket($name,$p);
-			if ($t eq $porttype){ push (@ports,$p);}
-		}	
-		
-	}elsif($type eq 'plug'){
-		@all_ports= $intfc->get_plug_port_list($name);
-		
-		foreach my $p(@all_ports){
-			my ($r,$t,$c)=$intfc->get_port_info_of_plug($name,$p);
-			#print "($t eq $porttype)\n";
-			if ($t eq $porttype){ push (@ports,$p);}
-		}	
-		
-	}
-	else  {
-		@ports=('IO','NC');
-	}
-	my $saved_intfc_port=$ipgen->ipgen_get_port_intfc_port($portname);	
-	my $pos=(defined $saved_intfc_port ) ? get_scolar_pos( $saved_intfc_port,@ports) : undef;
-	if (!defined $pos){
-		$pos=find_the_most_similar_position( $portname       ,@ports);
-		$ipgen->ipgen_set_port_intfc_port($portname,$ports[$pos]);
-		#print "$ports[$pos]\n;"
-	}		
-	my $intfc_port_combo=gen_combo(\@ports,$pos);	
-	$intfc_port_combo->signal_connect('changed'=> sub {
-		my $intfc_port=$intfc_port_combo->get_active_text();
-		$ipgen->ipgen_set_port_intfc_port($portname,$intfc_port);
-		
-	});
-	
-	
-	return  $intfc_port_combo;
+    my ($intfc,$ipgen,$intfc_name,$porttype,$portname)=@_;
+    my($type,$name,$num)= split("[:\[ \\]]", $intfc_name);
+    my @all_ports;
+    my @ports;
+    if($type eq 'socket'){
+        @all_ports= $intfc->get_socket_port_list($name);
+        foreach my $p(@all_ports){
+            my ($r,$t,$c)=$intfc->get_port_info_of_socket($name,$p);
+            if ($t eq $porttype){ push (@ports,$p);}
+        }
+    }elsif($type eq 'plug'){
+        @all_ports= $intfc->get_plug_port_list($name);
+        foreach my $p(@all_ports){
+            my ($r,$t,$c)=$intfc->get_port_info_of_plug($name,$p);
+            #print "($t eq $porttype)\n";
+            if ($t eq $porttype){ push (@ports,$p);}
+        }
+    }
+    else  {
+        @ports=('IO','NC');
+    }
+    my $saved_intfc_port=$ipgen->ipgen_get_port_intfc_port($portname);
+    my $pos=(defined $saved_intfc_port ) ? get_scolar_pos( $saved_intfc_port,@ports) : undef;
+    if (!defined $pos){
+        $pos=find_the_most_similar_position( $portname       ,@ports);
+        $ipgen->ipgen_set_port_intfc_port($portname,$ports[$pos]);
+        #print "$ports[$pos]\n;"
+    }
+    my $intfc_port_combo=gen_combo(\@ports,$pos);
+    $intfc_port_combo->signal_connect('changed'=> sub {
+        my $intfc_port=$intfc_port_combo->get_active_text();
+        $ipgen->ipgen_set_port_intfc_port($portname,$intfc_port);
+    });
+    return  $intfc_port_combo;
 }
 
-
-
 sub port_info_box {
-	my($intfc,$ipgen,$info)=@_;
-	my $table=def_table(8,10,FALSE);
-	my @ports=$ipgen->ipgen_list_ports;
-	my $row=0;
-	my ($name_ref,$ref)=get_list_of_all_interfaces($ipgen);
-	my @interfaces_name=@{$name_ref};
-	my @interfaces=@{$ref};
-	#print "@interfaces_name\n";
-	
-	$table->attach  (gen_label_in_left(" Type "), 0, 1, $row, $row+1,'expand','shrink',2,2);
-	$table->attach  (gen_label_in_left(" Port name "), 1, 3, $row, $row+1,'expand','shrink',2,2);
-	$table->attach  (gen_label_in_left(" Interface name "), 3, 5, $row, $row+1,'expand','shrink',2,2);
-	$table->attach  (gen_label_in_center(" Interface port  "), 5, 7, $row, $row+1,'fill','shrink',2,2);
-	$table->attach  (gen_label_in_left("  Port Range "), 7, 9, $row, $row+1,'expand','shrink',2,2);
-	$row++;
-	#print  @interfaces;
-	my @ports_order=$ipgen->ipgen_get_ports_order();
-	if(scalar(@ports_order) >1 ){ @ports= @ports_order}
-	
-
-
-
-	foreach my $p( @ports){
-		my ($range,$type,$intfc_name,$intfc_port)=$ipgen->ipgen_get_port($p);
-		#my $label_name=gen_label_in_left(" $p ");
-		my $name_entry=gen_label_in_left($p);
-		my $label_type=gen_label_in_left(" $type ");
-		my $range_entry=gen_entry($range);
-		my $pos=(defined $intfc_name ) ? get_scolar_pos( $intfc_name,@interfaces) : 0;
-		if (!defined $pos){
-			$pos=0;
-			$ipgen->ipgen_set_port_intfc_name($p,'IO');
-		};
-		my $intfc_name_combo=gen_combo(\@interfaces_name,$pos);
-		my $intfc_port_combo=gen_intfc_port_combo($intfc,$ipgen,$intfc_name,$type,$p);
-		
-		
-		$table->attach ($label_type, 0, 1, $row, $row+1,'expand','shrink',2,2);
-		$table->attach ($name_entry, 1, 3, $row, $row+1,'expand','shrink',2,2);
-		$table->attach ($intfc_name_combo,3, 5, $row, $row+1,'expand','shrink',2,2);
-		$table->attach ($intfc_port_combo, 5, 7, $row, $row+1,'fill','shrink',2,2);
-		$table->attach ($range_entry ,7, 9, $row, $row+1,'fill','shrink',2,2);
-				
-		$intfc_name_combo->signal_connect('changed'=>sub{
-			my $intfc_name=$intfc_name_combo->get_active_text();
-			my $pos=  get_scolar_pos( $intfc_name,@interfaces_name);
-			#my($type,$name,$num)= split("[:\[ \\]]", $intfc_name);
-			#print "$type,$name,$num\n";
-			$ipgen->ipgen_set_port_intfc_name($p,$interfaces[$pos]);
-			set_gui_status($ipgen,"interface_selected",1);
-		});
-		$range_entry->signal_connect('changed'=>sub{
-			my $new_range=$range_entry->get_text();
-			$ipgen->ipgen_add_port($p,$new_range,$type,$intfc_name,$intfc_port);
-		});
-			
-		$row++;
-	}	
-	
-	
-	
-	
-	return add_widget_to_scrolled_win($table);
-	
-	
+    my($intfc,$ipgen,$info)=@_;
+    my $table=def_table(8,10,FALSE);
+    my @ports=$ipgen->ipgen_list_ports;
+    my $row=0;
+    my ($name_ref,$ref)=get_list_of_all_interfaces($ipgen);
+    my @interfaces_name=@{$name_ref};
+    my @interfaces=@{$ref};
+    #print "@interfaces_name\n";
+    $table->attach  (gen_label_in_left(" Type "), 0, 1, $row, $row+1,'expand','shrink',2,2);
+    $table->attach  (gen_label_in_left(" Port name "), 1, 3, $row, $row+1,'expand','shrink',2,2);
+    $table->attach  (gen_label_in_left(" Interface name "), 3, 5, $row, $row+1,'expand','shrink',2,2);
+    $table->attach  (gen_label_in_center(" Interface port  "), 5, 7, $row, $row+1,'fill','shrink',2,2);
+    $table->attach  (gen_label_in_left("  Port Range "), 7, 9, $row, $row+1,'expand','shrink',2,2);
+    $row++;
+    #print  @interfaces;
+    my @ports_order=$ipgen->ipgen_get_ports_order();
+    if(scalar(@ports_order) >1 ){ @ports= @ports_order}
+    foreach my $p( @ports){
+        my ($range,$type,$intfc_name,$intfc_port)=$ipgen->ipgen_get_port($p);
+        #my $label_name=gen_label_in_left(" $p ");
+        my $name_entry=gen_label_in_left($p);
+        my $label_type=gen_label_in_left(" $type ");
+        my $range_entry=gen_entry($range);
+        my $pos=(defined $intfc_name ) ? get_scolar_pos( $intfc_name,@interfaces) : 0;
+        if (!defined $pos){
+            $pos=0;
+            $ipgen->ipgen_set_port_intfc_name($p,'IO');
+        };
+        my $intfc_name_combo=gen_combo(\@interfaces_name,$pos);
+        my $intfc_port_combo=gen_intfc_port_combo($intfc,$ipgen,$intfc_name,$type,$p);
+        $table->attach ($label_type, 0, 1, $row, $row+1,'expand','shrink',2,2);
+        $table->attach ($name_entry, 1, 3, $row, $row+1,'expand','shrink',2,2);
+        $table->attach ($intfc_name_combo,3, 5, $row, $row+1,'expand','shrink',2,2);
+        $table->attach ($intfc_port_combo, 5, 7, $row, $row+1,'fill','shrink',2,2);
+        $table->attach ($range_entry ,7, 9, $row, $row+1,'fill','shrink',2,2);
+        $intfc_name_combo->signal_connect('changed'=>sub{
+            my $intfc_name=$intfc_name_combo->get_active_text();
+            my $pos=  get_scolar_pos( $intfc_name,@interfaces_name);
+            #my($type,$name,$num)= split("[:\[ \\]]", $intfc_name);
+            #print "$type,$name,$num\n";
+            $ipgen->ipgen_set_port_intfc_name($p,$interfaces[$pos]);
+            set_gui_status($ipgen,"interface_selected",1);
+        });
+        $range_entry->signal_connect('changed'=>sub{
+            my $new_range=$range_entry->get_text();
+            $ipgen->ipgen_add_port($p,$new_range,$type,$intfc_name,$intfc_port);
+        });
+        $row++;
+    }
+    return add_widget_to_scrolled_win($table);
 }
 
-
 sub write_ip{
-	my $ipgen=shift;	
-	my $name=$ipgen->ipgen_get("module_name");
-	my $category=$ipgen->ipgen_get("category");
-	my $ip_name= $ipgen->ipgen_get("ip_name");
-	my $dir = Cwd::getcwd();
-
-	#Increase IP version
-	my $v=$ipgen->object_get_attribute("version",undef);
-	$v = 0 if(!defined $v);
-	$v++;
-	$ipgen->object_add_attribute("version",undef,$v);
-	#print "$v\n";
-
-	# Write
-	mkpath("$dir/lib/ip/$category/",1,01777);	
-	open(FILE,  ">lib/ip/$category/$ip_name.IP") || die "Can not open: $!";
-	print FILE perl_file_header("$ip_name.IP");
-	print FILE Data::Dumper->Dump([\%$ipgen],["ipgen"]);
-	close(FILE) || die "Error closing file: $!";
-	my $message="IP $ip_name has been generated successfully. In order to see the generated IP in processing tile generator you need to reset the ProNoC. Do you want to reset the ProNoC now?" ;
-		
-	my $response =  yes_no_dialog($message);
-	if ($response eq 'yes') {
-			exec($^X, $0, @ARGV);# reset ProNoC to apply changes	
-  	}
+    my $ipgen=shift;
+    my $name=$ipgen->ipgen_get("module_name");
+    my $category=$ipgen->ipgen_get("category");
+    my $ip_name= $ipgen->ipgen_get("ip_name");
+    my $dir = Cwd::getcwd();
+    #Increase IP version
+    my $v=$ipgen->object_get_attribute("version",undef);
+    $v = 0 if(!defined $v);
+    $v++;
+    $ipgen->object_add_attribute("version",undef,$v);
+    #print "$v\n";
+    # Write
+    mkpath("$dir/lib/ip/$category/",1,01777);
+    open(FILE,  ">lib/ip/$category/$ip_name.IP") || die "Can not open: $!";
+    print FILE perl_file_header("$ip_name.IP");
+    print FILE Data::Dumper->Dump([\%$ipgen],["ipgen"]);
+    close(FILE) || die "Error closing file: $!";
+    my $message="IP $ip_name has been generated successfully. In order to see the generated IP in processing tile generator you need to reset the ProNoC. Do you want to reset the ProNoC now?" ;
+    my $response =  yes_no_dialog($message);
+    if ($response eq 'yes') {
+            exec($^X, $0, @ARGV);# reset ProNoC to apply changes
+    }
 }
 
-
-
 sub generate_ip{
-	my $ipgen=shift;
-	my $name=$ipgen->ipgen_get("module_name");
-	my $category=$ipgen->ipgen_get("category");
-	my $ip_name= $ipgen->ipgen_get("ip_name");
-	my $dir = Cwd::getcwd();
-	
-	
-
-	#check if name has been set
-	if(defined ($name) && defined ($category)){
-		if (!defined $ip_name) {$ip_name= $name}
-		my $error = check_verilog_identifier_syntax($ip_name);
-		if ( defined $error ){
-			message_dialog("The IP name \"$ip_name\" is given with an unacceptable formatting. This name will be used as a verilog module name so it must follow Verilog identifier declaration formatting:\n $error");
-			return ;
-		}
-
-
-
-		#check if any source file has been added for this ip
-		my @l=$ipgen->ipgen_get_list("hdl_files");
-		if( scalar @l ==0){
-			my $mwindow;
-			my $response =  yes_no_dialog("No HDL library file has been set for this IP. Do you want to generate this IP?");
-			
-			if ($response eq 'yes') {
-	      			write_ip($ipgen);
-  			}
-			
-		}else{
-			write_ip($ipgen);
-		}
-	}else{
-		my $message;
-		if(!defined ($name)){ $message="Input file has not been selected yet.\nNothing has been generated!";}
-		elsif(!defined ($category)){ $message="Category must be defined!" ;}
-		message_dialog($message);
-		
-	}		
+    my $ipgen=shift;
+    my $name=$ipgen->ipgen_get("module_name");
+    my $category=$ipgen->ipgen_get("category");
+    my $ip_name= $ipgen->ipgen_get("ip_name");
+    my $dir = Cwd::getcwd();
+    #check if name has been set
+    if(defined ($name) && defined ($category)){
+        if (!defined $ip_name) {$ip_name= $name}
+        my $error = check_verilog_identifier_syntax($ip_name);
+        if ( defined $error ){
+            message_dialog("The IP name \"$ip_name\" is given with an unacceptable formatting. This name will be used as a verilog module name so it must follow Verilog identifier declaration formatting:\n $error");
+            return ;
+        }
+        #check if any source file has been added for this ip
+        my @l=$ipgen->ipgen_get_list("hdl_files");
+        if( scalar @l ==0){
+            my $mwindow;
+            my $response =  yes_no_dialog("No HDL library file has been set for this IP. Do you want to generate this IP?");
+            if ($response eq 'yes') {
+                write_ip($ipgen);
+            }
+        }else{
+            write_ip($ipgen);
+        }
+    }else{
+        my $message;
+        if(!defined ($name)){ $message="Input file has not been selected yet.\nNothing has been generated!";}
+        elsif(!defined ($category)){ $message="Category must be defined!" ;}
+        message_dialog($message);
+    }
 #$hashref = retrieve('file');
-	
-	
-	
-return 1;	
-}	
-
-
-
+return 1;
+}
 
 #########
-#	load_ip
+#    load_ip
 ########
-
 sub load_ip{
-	my ($ipgen)=@_;
-	my $file;
-	my $dialog =  gen_file_dialog (undef, 'IP');
-	my $dir = Cwd::getcwd();
-	$dialog->set_current_folder ("$dir/lib/ip");		
-
-	if ( "ok" eq $dialog->run ) {
-		$file = $dialog->get_filename;
-		my ($name,$path,$suffix) = fileparse("$file",qr"\..[^.]*$");
-		if($suffix eq '.IP'){
-			$ipgen->ipgen_add("file_name",$file);	
-			set_gui_status($ipgen,"load_file",0);
-		}					
-     }
-     $dialog->destroy;
+    my ($ipgen)=@_;
+    my $file;
+    my $dialog =  gen_file_dialog (undef, 'IP');
+    my $dir = Cwd::getcwd();
+    $dialog->set_current_folder ("$dir/lib/ip");
+    if ( "ok" eq $dialog->run ) {
+        $file = $dialog->get_filename;
+        my ($name,$path,$suffix) = fileparse("$file",qr"\..[^.]*$");
+        if($suffix eq '.IP'){
+            $ipgen->ipgen_add("file_name",$file);
+            set_gui_status($ipgen,"load_file",0);
+        }
+    }
+    $dialog->destroy;
 }
 
-
-
 ############
-#	get_source_file
+#    get_source_file
 ###########
-
-
-
 sub get_source_file{
-	my($ipgen,$info,$page,$title,$dest,$page_info_ref)=@_;
-
-		
-	my $var_list='${parameter_name}: Verilog module parameter values.
- 
+    my($ipgen,$info,$page,$title,$dest,$page_info_ref)=@_;
+    my $var_list='${parameter_name}: Verilog module parameter values.
 ${CORE_ID} Each wishbone bus based SoC will have a unique CORE_ID that represents its location in NoC topology. CORE_ID=((y * number_of_nodes_in_x_ dimension) + x) where (x,y) are the node location in x and y axes. If the generated tile is used as top level module CORE_ID will take the default value of zero.
-      
 ${IP}: is the peripheral device instance name.
-
 ${CORE}: is the peripheral device module name.
-
-${BASE}: is the wishbone base address(s) and will be added during soc generation to system.h. If more than one slave wishbone bus are used  define them as ${BASE0}, ${BASE1}... . 
+${BASE}: is the wishbone base address(s) and will be added during soc generation to system.h. If more than one slave wishbone bus are used  define them as ${BASE0}, ${BASE1}... .
 '
 ;
-	my $var_help=gen_button_message($var_list,"icons/info.png","Global variables");
-	
-	
-	my $window = def_popwin_size(75,75,$title,'percent');
-	
-	my $notebook=source_notebook($ipgen,$info,$window,$page,$dest,$page_info_ref);
-	my $table=def_table (15, 15, FALSE);						
-	
-		
-	$table->attach ($var_help, 5, 7, 0, 1,'expand','shrink',2,2);
-	$table->attach_defaults ($notebook , 0, 15, 1, 15);
-		
-	$window->add($table);
-	$window->show_all;	
-	return $window;	  
-	
+    my $var_help=gen_button_message($var_list,"icons/info.png","Global variables");
+    my $window = def_popwin_size(75,75,$title,'percent');
+    my $notebook=source_notebook($ipgen,$info,$window,$page,$dest,$page_info_ref);
+    my $table=def_table (15, 15, FALSE);
+    $table->attach ($var_help, 5, 7, 0, 1,'expand','shrink',2,2);
+    $table->attach_defaults ($notebook , 0, 15, 1, 15);
+    $window->add($table);
+    $window->show_all;
+    return $window;
 }
 
 ##########
 # source_notebook
 ##########
-
 sub source_notebook{
-	my($ipgen,$info,$window,$page,$dest,$page_info_ref)=@_;
-	my $notebook = gen_notebook();
-	my %page_info=%{$page_info_ref};
-	foreach my $p (sort keys %page_info){
-		my $page_ref;
-		$page_ref=get_file_folder($ipgen,$info,$window,$p,$page_info_ref) if($page_info{$p}{filed_type} eq "existing_file/folder"); 
-		$page_ref=get_file_folder($ipgen,$info,$window,$p,$page_info_ref) if($page_info{$p}{filed_type} eq "file_with_variables"); 
-		$page_ref=get_file_content($ipgen,$info,$window,$page_info{$p},$page_info_ref) if($page_info{$p}{filed_type} eq "file_content"); 
-		$notebook->append_page ($page_ref,gen_label_with_mnemonic ($page_info{$p}{page_name}));
-
-	}	
-	$notebook->show_all;	
-	$notebook->set_current_page($page) if(defined $page);
-	return $notebook;
-
+    my($ipgen,$info,$window,$page,$dest,$page_info_ref)=@_;
+    my $notebook = gen_notebook();
+    my %page_info=%{$page_info_ref};
+    foreach my $p (sort keys %page_info){
+        my $page_ref;
+        $page_ref=get_file_folder($ipgen,$info,$window,$p,$page_info_ref) if($page_info{$p}{filed_type} eq "existing_file/folder");
+        $page_ref=get_file_folder($ipgen,$info,$window,$p,$page_info_ref) if($page_info{$p}{filed_type} eq "file_with_variables");
+        $page_ref=get_file_content($ipgen,$info,$window,$page_info{$p},$page_info_ref) if($page_info{$p}{filed_type} eq "file_content");
+        $notebook->append_page ($page_ref,gen_label_with_mnemonic ($page_info{$p}{page_name}));
+    }
+    $notebook->show_all;
+    $notebook->set_current_page($page) if(defined $page);
+    return $notebook;
 }
 
 ##########
 #  get_file_folder
 #########
-
 sub get_file_folder{
-	my ($ipgen,$info,$window,$page,$page_info_ref)=@_;
-	my %page_info=%{$page_info_ref};
-	my @sw_dir = $ipgen->ipgen_get_list($page_info{$page}{filed_name});
-	my $table = def_table (15, 15, FALSE);	
-	my $help=gen_label_help($page_info{$page}{help});	
-	$table->attach ($help,0,2,0,1,'expand','shrink',2,2);	
-	my $tick = $page_info{$page}{'tick'};
-	my ($scrwin,$ok)=gen_file_list($ipgen,$page_info{$page}{filed_name},$window,$page_info{$page}{rename_file},$tick);
-	
-	my $label=gen_label_in_left("Select file(s):"); 
-	my $brows=def_image_button("icons/browse.png",' Browse');
-	$table->attach ($label,2,4,0,1,'expand','shrink',2,2);
-	$table->attach($brows,4,6,0,1,'expand','shrink',2,2);
-	
-	my $dir = Cwd::getcwd();
-	my $project_dir	  = abs_path("$dir/../../"); #mpsoc directory address
-	
-	
-	$brows->signal_connect("clicked"=> sub {
-		my @files;
-		my $dialog =  gen_file_dialog (undef);
-		my $dir = Cwd::getcwd();
-		$dialog->set_current_folder ("$dir/..")	;	
-		$dialog->set_select_multiple(TRUE);
-
-       	if ( "ok" eq $dialog->run ) {
-           		@files = get_filenames_from_dialog($dialog);	
-           		@sw_dir=$ipgen->ipgen_get_list($page_info{$page}{filed_name});
-           		foreach my $p (@files){
-           			#remove $project_dir form beginning of each file
-					$p =~ s/$project_dir//; 
-					my ($name,$path,$suffix) = fileparse("$p",qr"\..[^.]*$");
-					$p=$p.'frename_sep_t'.$name.$suffix if (defined $page_info{$page}{rename_file}); 
-					if(! grep (/^$p$/,@sw_dir)){push(@sw_dir,$p)};           			
-           		}            		
-           		$ipgen->ipgen_add($page_info{$page}{filed_name},\@sw_dir);
-           		get_source_file($ipgen,$info,$page,"Add software file(s)","SW",$page_info_ref);
-           		$window->destroy;
-            		
-      	 }
-       	$dialog->destroy;
-	} );# # ,\$entry);
-	
-	if($page_info{$page}{folder_en} eq 1){
-		my $label2=gen_label_in_left("Select folder(s):"); 
-		my $brows2=def_image_button("icons/browse.png",' Browse');
-		$table->attach($label2,7,9,0,1,'expand','shrink',2,2);
-		$table->attach($brows2,9,11,0,1,'expand','shrink',2,2);
-
-		$brows2->signal_connect("clicked"=> sub {
-			my @files;
-			my $dialog =  gen_folder_dialog ('Select Folder(s)');
-			my $dir = Cwd::getcwd();
-			$dialog->set_current_folder ("$dir/..")	;	
-			$dialog->set_select_multiple(TRUE);
-
-			if ( "ok" eq $dialog->run ) {
-		    		@files = get_filenames_from_dialog($dialog);
-		    		
-		    		@sw_dir=$ipgen->ipgen_get_list($page_info{$page}{filed_name});
-		    		foreach my $p (@files){
-		    			#remove $project_dir form beginning of each file
-		    			$p =~ s/$project_dir//;  
-		    			if(! grep (/^$p$/,@sw_dir)){push(@sw_dir,$p)};
-		    			
-		    		}
-		    		
-		    		$ipgen->ipgen_add($page_info{$page}{filed_name},\@sw_dir);
-		    		get_source_file($ipgen,$info,$page,"Add software file(s)","SW",$page_info_ref);
-		    		$window->destroy;
-		    		
-		    		
-						#$$entry_ref->set_text($file);
-					
-		    		#print "file = $file\n";
-	       		 }
-	       		$dialog->destroy;
-	       		
-
-
-		} );# # ,\$entry);
-	}	
-	
-	
-	
-	
-	
-	
-	$table->attach_defaults($scrwin,0,15,1,14);
-	$table->attach($ok,6,9,14,15,'expand','shrink',2,2);
-	
-	return ($table)
-
-	
-}	
-
-
+    my ($ipgen,$info,$window,$page,$page_info_ref)=@_;
+    my %page_info=%{$page_info_ref};
+    my @sw_dir = $ipgen->ipgen_get_list($page_info{$page}{filed_name});
+    my $table = def_table (15, 15, FALSE);
+    my $help=gen_label_help($page_info{$page}{help});
+    $table->attach ($help,0,2,0,1,'expand','shrink',2,2);
+    my $tick = $page_info{$page}{'tick'};
+    my ($scrwin,$ok)=gen_file_list($ipgen,$page_info{$page}{filed_name},$window,$page_info{$page}{rename_file},$tick);
+    my $label=gen_label_in_left("Select file(s):");
+    my $brows=def_image_button("icons/browse.png",' Browse');
+    $table->attach ($label,2,4,0,1,'expand','shrink',2,2);
+    $table->attach($brows,4,6,0,1,'expand','shrink',2,2);
+    my $dir = Cwd::getcwd();
+    my $project_dir      = abs_path("$dir/../../"); #mpsoc directory address
+    $brows->signal_connect("clicked"=> sub {
+        my @files;
+        my $dialog =  gen_file_dialog (undef);
+        my $dir = Cwd::getcwd();
+        $dialog->set_current_folder ("$dir/..")    ;
+        $dialog->set_select_multiple(TRUE);
+        if ( "ok" eq $dialog->run ) {
+                @files = get_filenames_from_dialog($dialog);
+                @sw_dir=$ipgen->ipgen_get_list($page_info{$page}{filed_name});
+                foreach my $p (@files){
+                    #remove $project_dir form beginning of each file
+                    $p =~ s/$project_dir//;
+                    my ($name,$path,$suffix) = fileparse("$p",qr"\..[^.]*$");
+                    $p=$p.'frename_sep_t'.$name.$suffix if (defined $page_info{$page}{rename_file});
+                    if(! grep (/^$p$/,@sw_dir)){push(@sw_dir,$p)};
+                }
+                $ipgen->ipgen_add($page_info{$page}{filed_name},\@sw_dir);
+                get_source_file($ipgen,$info,$page,"Add software file(s)","SW",$page_info_ref);
+                $window->destroy;
+        }
+        $dialog->destroy;
+    } );# # ,\$entry);
+    if($page_info{$page}{folder_en} eq 1){
+        my $label2=gen_label_in_left("Select folder(s):");
+        my $brows2=def_image_button("icons/browse.png",' Browse');
+        $table->attach($label2,7,9,0,1,'expand','shrink',2,2);
+        $table->attach($brows2,9,11,0,1,'expand','shrink',2,2);
+        $brows2->signal_connect("clicked"=> sub {
+            my @files;
+            my $dialog =  gen_folder_dialog ('Select Folder(s)');
+            my $dir = Cwd::getcwd();
+            $dialog->set_current_folder ("$dir/..")    ;
+            $dialog->set_select_multiple(TRUE);
+            if ( "ok" eq $dialog->run ) {
+                    @files = get_filenames_from_dialog($dialog);
+                    @sw_dir=$ipgen->ipgen_get_list($page_info{$page}{filed_name});
+                    foreach my $p (@files){
+                        #remove $project_dir form beginning of each file
+                        $p =~ s/$project_dir//;
+                        if(! grep (/^$p$/,@sw_dir)){push(@sw_dir,$p)};
+                    }
+                    $ipgen->ipgen_add($page_info{$page}{filed_name},\@sw_dir);
+                    get_source_file($ipgen,$info,$page,"Add software file(s)","SW",$page_info_ref);
+                    $window->destroy;
+                        #$$entry_ref->set_text($file);
+                    #print "file = $file\n";
+                    }
+                $dialog->destroy;
+        } );# # ,\$entry);
+    }
+    $table->attach_defaults($scrwin,0,15,1,14);
+    $table->attach($ok,6,9,14,15,'expand','shrink',2,2);
+    return ($table)
+}
 
 ###########
-#	get_file_content
+#    get_file_content
 #########
-
 sub get_file_content{
-	my ($ipgen,$info,$window,$page_info_ref)=@_;
-	my %page_info=%{$page_info_ref};
-	#my $hdr = $ipgen->ipgen_get_hdr();
-	my  $hdr = $ipgen-> ipgen_get($page_info{filed_name});	
-	my $table = def_table (14, 15, FALSE);
-	my ($scrwin,$text_view)=create_txview();
-
-	my $help=gen_label_help($page_info{help}); 
-	$table->attach ($help,0,8,0,1,'expand','shrink',2,2);
-	$table->attach_defaults($scrwin,0,15,1,14);
-	my $text_buffer = $text_view->get_buffer;
-	if(defined $hdr) {$text_buffer->set_text($hdr)};	
-	
-	my $ok=def_image_button("icons/select.png",' Save ');
-	$ok->signal_connect("clicked"=> sub {#		  
-		 my $text = $text_buffer->get_text($text_buffer->get_bounds, TRUE);
-		 $ipgen->ipgen_add($page_info{filed_name},$text);	
-		 $window->destroy;
-				
-	});
-
-	$table->attach($ok,6,7,14,15,'expand','shrink',2,2);
-	return ($table);
-	
-}	
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+    my ($ipgen,$info,$window,$page_info_ref)=@_;
+    my %page_info=%{$page_info_ref};
+    #my $hdr = $ipgen->ipgen_get_hdr();
+    my  $hdr = $ipgen-> ipgen_get($page_info{filed_name});
+    my $table = def_table (14, 15, FALSE);
+    my ($scrwin,$text_view)=create_txview();
+    my $help=gen_label_help($page_info{help});
+    $table->attach ($help,0,8,0,1,'expand','shrink',2,2);
+    $table->attach_defaults($scrwin,0,15,1,14);
+    my $text_buffer = $text_view->get_buffer;
+    if(defined $hdr) {$text_buffer->set_text($hdr)};
+    my $ok=def_image_button("icons/select.png",' Save ');
+    $ok->signal_connect("clicked"=> sub {#
+        my $text = $text_buffer->get_text($text_buffer->get_bounds, TRUE);
+        $ipgen->ipgen_add($page_info{filed_name},$text);
+        $window->destroy;
+    });
+    $table->attach($ok,6,7,14,15,'expand','shrink',2,2);
+    return ($table);
+}
 
 ############
-#	get_unused_intfc_ports_list
+#    get_unused_intfc_ports_list
 ###########
-
 sub get_unused_intfc_ports_list {
-	my($intfc,$ipgen,$info)=@_;
-	my @ports=$ipgen->ipgen_list_ports;
-	my ($name_ref,$ref)=get_list_of_all_interfaces($ipgen);
-	my @interfaces_name=@{$name_ref};
-	my @interfaces=@{$ref};
-	$ipgen->ipgen_remove("unused");
-	foreach my $intfc_name (@interfaces)
-	{
-		#print "$intfc_name\n";
-		my($type,$name,$num)= split("[:\[ \\]]", $intfc_name);
-		my @all_ports;
-		if($type eq 'socket'){
-			@all_ports= $intfc->get_socket_port_list($name);
-			
-		}elsif($type eq 'plug'){
-			@all_ports= $intfc->get_plug_port_list($name);
-		}
-		foreach my $p(@all_ports){
-				my $r= check_intfc_port_exits($intfc,$ipgen,$info,$intfc_name,$p);
-				if ($r eq "0"){
-					$ipgen->ipgen_add_unused_intfc_port( $intfc_name,$p );
-				}
-				
-		}	
-
-	}
+    my($intfc,$ipgen,$info)=@_;
+    my @ports=$ipgen->ipgen_list_ports;
+    my ($name_ref,$ref)=get_list_of_all_interfaces($ipgen);
+    my @interfaces_name=@{$name_ref};
+    my @interfaces=@{$ref};
+    $ipgen->ipgen_remove("unused");
+    foreach my $intfc_name (@interfaces)
+    {
+        #print "$intfc_name\n";
+        my($type,$name,$num)= split("[:\[ \\]]", $intfc_name);
+        my @all_ports;
+        if($type eq 'socket'){
+            @all_ports= $intfc->get_socket_port_list($name);
+        }elsif($type eq 'plug'){
+            @all_ports= $intfc->get_plug_port_list($name);
+        }
+        foreach my $p(@all_ports){
+                my $r= check_intfc_port_exits($intfc,$ipgen,$info,$intfc_name,$p);
+                if ($r eq "0"){
+                    $ipgen->ipgen_add_unused_intfc_port( $intfc_name,$p );
+                }
+        }
+    }
 }
 
 sub check_intfc_port_exits{
-	my($intfc,$ipgen,$info,$intfc_name,$intfc_port)=@_;
-	my @ports=$ipgen->ipgen_list_ports;
-	
-	
-	my $result="0";
-	foreach my $p( @ports){
-		my ($range,$type,$assigned_intfc_name,$assigned_intfc_port)=$ipgen->ipgen_get_port($p);
-		#print "if($intfc_name eq $assigned_intfc_name && $intfc_port eq $assigned_intfc_port);\n";
-		
-		if($intfc_name eq $assigned_intfc_name && $intfc_port eq $assigned_intfc_port){
-			if($result eq "1"){# one interface port has been connected to multiple IP port
-				
-			} 
-			$result = "1";
-						
-		}
-	}
-	return $result;
-	
+    my($intfc,$ipgen,$info,$intfc_name,$intfc_port)=@_;
+    my @ports=$ipgen->ipgen_list_ports;
+    my $result="0";
+    foreach my $p( @ports){
+        my ($range,$type,$assigned_intfc_name,$assigned_intfc_port)=$ipgen->ipgen_get_port($p);
+        #print "if($intfc_name eq $assigned_intfc_name && $intfc_port eq $assigned_intfc_port);\n";
+        if($intfc_name eq $assigned_intfc_name && $intfc_port eq $assigned_intfc_port){
+            if($result eq "1"){# one interface port has been connected to multiple IP port
+            }
+            $result = "1";
+        }
+    }
+    return $result;
 }
 
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
 ############
 #    main
 ############
 sub ipgen_main{
-	my $ipgen=shift;
-	my $intfc=interface->interface_new();
-	if(!defined $ipgen) { $ipgen=ip_gen->ip_gen_new();}
-	set_gui_status($ipgen,"ideal",0);	
-	
-	#  The main table containing the lib tree, selected modules and info section 
-	my $main_table = def_table (15, 12, FALSE);
-
-
-	
-	
-	# The box which holds the info, warning, error ...  mesages
-	my ($infobox,$info)= create_txview();	
-	my $generate = def_image_button('icons/gen.png','Generate');
-	
-	
-	# A tree view for holding a library
-	my %tree_text;
-	my @categories= $intfc->get_categories();
-	foreach my $p (@categories)
-   	{
-   		my @intfc_names=  $intfc->get_intfcs_of_category($p);
-   		$tree_text{$p}=\@intfc_names;
-	
-   	}
-	
-	
-	my $tree_box = create_tree  ($ipgen,'Interfaces list',$info,\%tree_text,\&show_interface_description  ,\&add_plug_interface_from_tree);
-
-
-	my $file_info=file_info_box($ipgen,$info);
-	my $port_info=port_info_box($intfc,$ipgen,$info);
-	my $intfc_info=interface_info_box($intfc,$ipgen,$info);
-	
-	
-	my $open = def_image_button('icons/browse.png','Load IP');
-	
-
-	$main_table->set_row_spacings (4);
-	$main_table->set_col_spacings (1);
-	
-	
-	
-	
-	#$table->attach_defaults ($event_box, $col, $col+1, $row, $row+1);
-
-	my $v1=gen_vpaned($file_info,.2,$intfc_info);
-	my $v2=gen_vpaned($v1,.4,$port_info);
-	my $h1=gen_hpaned($tree_box,.15,$v2);
-	my $v3=gen_vpaned($h1,.6,$infobox);
-
-	
-	$main_table->attach_defaults  ($v3, 0, 12, 0,14);
-	$main_table->attach ($generate, 6, 8, 14,15,'expand','shrink',2,2);
-	$main_table->attach ($open,0, 1, 14,15,'expand','shrink',2,2);
-
-	#check soc status every 0.5 second. refresh device table if there is any changes 
-Glib::Timeout->add (100, sub{ 
-	 
-		my ($state,$timeout)= get_gui_status($ipgen);
-		if($state eq "load_file"){
-			my $file=$ipgen->ipgen_get("file_name");
-			my ($pp,$r,$err) = regen_object($file);
-			if ($r){		
-				add_colored_info($info,"**Error reading  $file file: $err\n",'red');
-				
-				return;
-			} 			
-			clone_obj($ipgen,$pp);
-			show_info($info,"$file is loaded!\n ");
-			set_gui_status($ipgen,"ref",1);
-			
-			
-		}elsif ($timeout>0){
-			$timeout--;
-			set_gui_status($ipgen,$state,$timeout);		
-		}
-		elsif( $state eq "change_parameter" ){
-			get_parameter_setting($ipgen,$info);
-			set_gui_status($ipgen,"ideal",0);
-			
-			
-			
-		}
-		elsif( $state ne "ideal" ){
-			$file_info->destroy;
-			$port_info->destroy;
-			$intfc_info->destroy;
-			$file_info=file_info_box($ipgen,$info);
-			$port_info=port_info_box($intfc,$ipgen,$info);
-			$intfc_info=interface_info_box($intfc,$ipgen,$info);
-			
-			$v1 -> pack1($file_info, TRUE, TRUE);     
-            $v1 -> pack2($intfc_info, TRUE, TRUE); 
-			$v2 -> pack2($port_info, TRUE, TRUE);      
-			$v1->show_all;
-			$v2->show_all;
-			set_gui_status($ipgen,"ideal",0);
-			
-			
-		}	
-		return TRUE;
-		
-		} );
-
-
-
-
-	$open-> signal_connect("clicked" => sub{ 
-		load_ip($ipgen);
-	
-	});		
-		
-	$generate-> signal_connect("clicked" => sub{ 
-		get_unused_intfc_ports_list ($intfc,$ipgen,$info);
-		generate_ip($ipgen);
-		
-		set_gui_status($ipgen,"ref",1);
-	
-	});
-
-	return add_widget_to_scrolled_win($main_table);
-
+    my $ipgen=shift;
+    my $intfc=interface->interface_new();
+    if(!defined $ipgen) { $ipgen=ip_gen->ip_gen_new();}
+    set_gui_status($ipgen,"ideal",0);
+    #  The main table containing the lib tree, selected modules and info section
+    my $main_table = def_table (15, 12, FALSE);
+    # The box which holds the info, warning, error ...  mesages
+    my ($infobox,$info)= create_txview();
+    my $generate = def_image_button('icons/gen.png','Generate');
+    # A tree view for holding a library
+    my %tree_text;
+    my @categories= $intfc->get_categories();
+    foreach my $p (@categories)
+    {
+        my @intfc_names=  $intfc->get_intfcs_of_category($p);
+        $tree_text{$p}=\@intfc_names;
+    }
+    my $tree_box = create_tree  ($ipgen,'Interfaces list',$info,\%tree_text,\&show_interface_description  ,\&add_plug_interface_from_tree);
+    my $file_info=file_info_box($ipgen,$info);
+    my $port_info=port_info_box($intfc,$ipgen,$info);
+    my $intfc_info=interface_info_box($intfc,$ipgen,$info);
+    my $open = def_image_button('icons/browse.png','Load IP');
+    $main_table->set_row_spacings (4);
+    $main_table->set_col_spacings (1);
+    #$table->attach_defaults ($event_box, $col, $col+1, $row, $row+1);
+    my $v1=gen_vpaned($file_info,.2,$intfc_info);
+    my $v2=gen_vpaned($v1,.4,$port_info);
+    my $h1=gen_hpaned($tree_box,.15,$v2);
+    my $v3=gen_vpaned($h1,.6,$infobox);
+    $main_table->attach_defaults  ($v3, 0, 12, 0,14);
+    $main_table->attach ($generate, 6, 8, 14,15,'expand','shrink',2,2);
+    $main_table->attach ($open,0, 1, 14,15,'expand','shrink',2,2);
+    #check soc status every 0.5 second. refresh device table if there is any changes
+    Glib::Timeout->add (100, sub{
+        my ($state,$timeout)= get_gui_status($ipgen);
+        if($state eq "load_file"){
+            my $file=$ipgen->ipgen_get("file_name");
+            my ($pp,$r,$err) = regen_object($file);
+            if ($r){
+                add_colored_info($info,"**Error reading  $file file: $err\n",'red');
+                return;
+            }
+            clone_obj($ipgen,$pp);
+            show_info($info,"$file is loaded!\n ");
+            set_gui_status($ipgen,"ref",1);
+        }elsif ($timeout>0){
+            $timeout--;
+            set_gui_status($ipgen,$state,$timeout);
+        }
+        elsif( $state eq "change_parameter" ){
+            get_parameter_setting($ipgen,$info);
+            set_gui_status($ipgen,"ideal",0);
+        }
+        elsif( $state ne "ideal" ){
+            $file_info->destroy;
+            $port_info->destroy;
+            $intfc_info->destroy;
+            $file_info=file_info_box($ipgen,$info);
+            $port_info=port_info_box($intfc,$ipgen,$info);
+            $intfc_info=interface_info_box($intfc,$ipgen,$info);
+            $v1 -> pack1($file_info, TRUE, TRUE);
+            $v1 -> pack2($intfc_info, TRUE, TRUE);
+            $v2 -> pack2($port_info, TRUE, TRUE);
+            $v1->show_all;
+            $v2->show_all;
+            set_gui_status($ipgen,"ideal",0);
+        }
+        return TRUE;
+        } );
+    $open-> signal_connect("clicked" => sub{
+        load_ip($ipgen);
+    });
+    $generate-> signal_connect("clicked" => sub{
+        get_unused_intfc_ports_list ($intfc,$ipgen,$info);
+        generate_ip($ipgen);
+        set_gui_status($ipgen,"ref",1);
+    });
+    return add_widget_to_scrolled_win($main_table);
 }
-
-
-
+1;
\ No newline at end of file
diff --git a/mpsoc/perl_gui/lib/perl/ip_gen.pm b/mpsoc/perl_gui/lib/perl/ip_gen.pm
index 6633db6..2f28270 100755
--- a/mpsoc/perl_gui/lib/perl/ip_gen.pm
+++ b/mpsoc/perl_gui/lib/perl/ip_gen.pm
@@ -1,692 +1,567 @@
 #!/usr/bin/perl -w -I ..
 ###############################################################################
-#
 # File:         interface.pm
-# 
-#
 ###############################################################################
+
 use warnings;
 use strict;
-
-
-
 package ip_gen;
 #use Clone 'clone';
 
-
-
 sub ip_gen_new {
     # be backwards compatible with non-OO call
     my $class = ("ARRAY" eq ref $_[0]) ? "ip_gen" : shift;
     my $self;
-
-   
     $self = {};
-    $self->{file_name}        = (); 
+    $self->{file_name}        = ();
     $self->{parameters_order}=[];
     $self->{ports_order}=[];
     $self->{hdl_files}=[];
-	$self->{hdl_files_ticked}=[];
-	
-
+    $self->{hdl_files_ticked}=[];
     bless($self,$class);
-
-   
     return $self;
-} 
-
-
+}
 
 sub ipgen_set_module_list{
-	my ($self,@list)=@_;
-	$self->{modules}={};
-	foreach my $p(@list) {			
-		$self->{modules}{$p}={};	
-	}
-	
-}	
-
-
+    my ($self,@list)=@_;
+    $self->{modules}={};
+    foreach my $p(@list) {
+        $self->{modules}{$p}={};
+    }
+}
 
 sub ipgen_get_module_list{
-		my ($self)=@_;
-		my @modules;
-		if(exists($self->{modules})){
-			@modules=keys %{$self->{modules}};
-		}
-		return @modules;
-}		
-
-
+        my ($self)=@_;
+        my @modules;
+        if(exists($self->{modules})){
+            @modules=keys %{$self->{modules}};
+        }
+        return @modules;
+}
 
 sub ipgen_add_parameter{
-	my ($self,$parameter,$default,$type,$content,$info,$global_param,$redefine)=@_;
-	$self->{parameters}{$parameter}{"default"}=$default;	
-	$self->{parameters}{$parameter}{type}=$type;
-	$self->{parameters}{$parameter}{content}=$content;
-	$self->{parameters}{$parameter}{info}=$info;
-	$self->{parameters}{$parameter}{global_param}=$global_param;
-	$self->{parameters}{$parameter}{redefine_param}=$redefine;						
-}	
-
-
-
-
-
+    my ($self,$parameter,$default,$type,$content,$info,$global_param,$redefine)=@_;
+    $self->{parameters}{$parameter}{"default"}=$default;
+    $self->{parameters}{$parameter}{type}=$type;
+    $self->{parameters}{$parameter}{content}=$content;
+    $self->{parameters}{$parameter}{info}=$info;
+    $self->{parameters}{$parameter}{global_param}=$global_param;
+    $self->{parameters}{$parameter}{redefine_param}=$redefine;
+}
 
 sub ipgen_push_parameters_order{
-	my ($self,$param)=@_;
-	if(defined $param){
-		push(@{$self->{parameters_order}},$param);
-	}
-
+    my ($self,$param)=@_;
+    if(defined $param){
+        push(@{$self->{parameters_order}},$param);
+    }
 }
 
 sub ipgen_remove_parameters_order{
-	my ($self,$param)=@_;
-	my @r=@{$self->{parameters_order}};
-	my @n;
-	foreach my $p(@r){
-		if( $p ne $param) {push(@n,$p)};	
-
-	}
-	$self->{parameters_order}=\@n;
-
+    my ($self,$param)=@_;
+    my @r=@{$self->{parameters_order}};
+    my @n;
+    foreach my $p(@r){
+        if( $p ne $param) {push(@n,$p)};
+    }
+    $self->{parameters_order}=\@n;
 }
 
-
 sub ipgen_add_ports_order{
-	my ($self,@ports_order) =@_;
-	$self->{ports_order}=\@ports_order;
+    my ($self,@ports_order) =@_;
+    $self->{ports_order}=\@ports_order;
 }
 
-
-
 sub ipgen_get_ports_order{
-	my $self =shift;
-	my @order=(defined $self->{ports_order})?  @{$self->{ports_order}} : undef;
+    my $self =shift;
+    my @order=(defined $self->{ports_order})?  @{$self->{ports_order}} : undef;
     return  @order;
 }
 
-
-
-
 sub ipgen_remove_parameter{
-	my ($self,$parameter)=@_;
-	if(exists ( $self->{parameters}{$parameter})){
-		delete $self->{parameters}{$parameter};	
-	}
-}	
-	
+    my ($self,$parameter)=@_;
+    if(exists ( $self->{parameters}{$parameter})){
+        delete $self->{parameters}{$parameter};
+    }
+}
+
 sub ipgen_get_parameter_detail{
-	my ($self,$parameter)=@_;
-	my ($default,$type,$content,$info,$global_param,$redefine);
-	if(exists ($self->{parameters}{$parameter})){
-		$default		=$self->{parameters}{$parameter}{"default"};
-		$type 			=$self->{parameters}{$parameter}{type};
-		$content 		=$self->{parameters}{$parameter}{content};
-		$info			=$self->{parameters}{$parameter}{info};
-		$global_param		=$self->{parameters}{$parameter}{global_param};
-		$redefine		=$self->{parameters}{$parameter}{redefine_param};	
-		
-	}		
-	return ($default,$type,$content,$info,$global_param,$redefine);	
-}		
+    my ($self,$parameter)=@_;
+    my ($default,$type,$content,$info,$global_param,$redefine);
+    if(exists ($self->{parameters}{$parameter})){
+        $default        =$self->{parameters}{$parameter}{"default"};
+        $type             =$self->{parameters}{$parameter}{type};
+        $content         =$self->{parameters}{$parameter}{content};
+        $info            =$self->{parameters}{$parameter}{info};
+        $global_param        =$self->{parameters}{$parameter}{global_param};
+        $redefine        =$self->{parameters}{$parameter}{redefine_param};
+    }
+    return ($default,$type,$content,$info,$global_param,$redefine);
+}
 
 sub ipgen_get_all_parameters_list{
-	my ($self)=@_;
-	my @parameters;
-	if(exists ($self->{parameters})){
-		foreach my $p ( keys %{$self->{parameters}}){
-			push(@parameters,$p);
-		}	
-	}		
-	return @parameters;
-}		
+    my ($self)=@_;
+    my @parameters;
+    if(exists ($self->{parameters})){
+        foreach my $p ( keys %{$self->{parameters}}){
+            push(@parameters,$p);
+        }
+    }
+    return @parameters;
+}
 
 sub ipgen_remove_all_parameters{
-	my ($self)=@_;
-	if (exists ($self->{parameters})){
-		delete $self->{parameters};
-	}
-}	
-
-
+    my ($self)=@_;
+    if (exists ($self->{parameters})){
+        delete $self->{parameters};
+    }
+}
 
 sub ipgen_add_port{
-	my($self,$port,$range,$type,$intfc_name,$intfc_port)=@_;
-	$self->{ports}{$port}{range}=$range;
-	$self->{ports}{$port}{type}=$type;
-	$self->{ports}{$port}{intfc_name}=$intfc_name;
-	$self->{ports}{$port}{intfc_port}=$intfc_port;
+    my($self,$port,$range,$type,$intfc_name,$intfc_port)=@_;
+    $self->{ports}{$port}{range}=$range;
+    $self->{ports}{$port}{type}=$type;
+    $self->{ports}{$port}{intfc_name}=$intfc_name;
+    $self->{ports}{$port}{intfc_port}=$intfc_port;
 }
 
 sub ipgen_get_port{
-	my($self,$port)=@_;
-	my($range,$type,$intfc_name,$intfc_port);
-	if(exists ($self->{ports}{$port})){
-		$range=$self->{ports}{$port}{range};
-		$type=$self->{ports}{$port}{type};
-		$intfc_name=$self->{ports}{$port}{intfc_name};
-		$intfc_port=$self->{ports}{$port}{intfc_port};
-	}
-	return ($range,$type,$intfc_name,$intfc_port);
+    my($self,$port)=@_;
+    my($range,$type,$intfc_name,$intfc_port);
+    if(exists ($self->{ports}{$port})){
+        $range=$self->{ports}{$port}{range};
+        $type=$self->{ports}{$port}{type};
+        $intfc_name=$self->{ports}{$port}{intfc_name};
+        $intfc_port=$self->{ports}{$port}{intfc_port};
+    }
+    return ($range,$type,$intfc_name,$intfc_port);
 }
 
-
 sub ipgen_list_ports{
-	my($self)=@_;
-	my @ports;
-	foreach my $p (keys %{$self->{ports}}){
-		push (@ports,$p);
-	}	
-	return @ports;
+    my($self)=@_;
+    my @ports;
+    foreach my $p (keys %{$self->{ports}}){
+        push (@ports,$p);
+    }
+    return @ports;
 }
 
-
-
 sub ipgen_remove_all_ports{
-	my $self=shift;
-	if (exists ($self->{ports})){
-		delete $self->{ports};
-	}
-	
-}		
+    my $self=shift;
+    if (exists ($self->{ports})){
+        delete $self->{ports};
+    }
+}
 
 sub ipgen_add_soket{
-	my ($self,$socket,$type,$value,$connection_num)=@_;
-	$self->{sockets}{$socket}{type}=$type;
-	if(defined $value) {
-		$self->{sockets}{$socket}{value}=$value;
-		
-	}
-	if(defined $connection_num) {$self->{sockets}{$socket}{connection_num}=$connection_num;}	
-	if($type eq 'num'){
-		if($value == 1) {ipgen_set_socket_name($self,$socket,0,$socket);}
-		else{
-				for (my $i=0; $i<$value; $i++){
-					my $name="$socket\_$i";
-					ipgen_set_socket_name($self,$socket,$i,$name);
-				}
-			
-		}	
-		
-	}
-	else{ipgen_set_socket_name($self,$socket,0,$socket);}		
-	
-	#print "\$self->{sockets}{$socket}{type}=$type;\n"
+    my ($self,$socket,$type,$value,$connection_num)=@_;
+    $self->{sockets}{$socket}{type}=$type;
+    if(defined $value) {
+        $self->{sockets}{$socket}{value}=$value;
+    }
+    if(defined $connection_num) {$self->{sockets}{$socket}{connection_num}=$connection_num;}
+    if($type eq 'num'){
+        if($value == 1) {ipgen_set_socket_name($self,$socket,0,$socket);}
+        else{
+                for (my $i=0; $i<$value; $i++){
+                    my $name="$socket\_$i";
+                    ipgen_set_socket_name($self,$socket,$i,$name);
+                }
+        }
+    }
+    else{ipgen_set_socket_name($self,$socket,0,$socket);}
+    #print "\$self->{sockets}{$socket}{type}=$type;\n"
 }
 
 sub ipgen_add_plug{
-	my ($self,$plug,$type,$value)=@_;
-	$self->{plugs}{$plug}{type}=$type;
-	if(defined $value){$self->{plugs}{$plug}{value}=$value};
-	if($type eq 'num'){
-		if($value == 1) {ipgen_set_plug_name($self,$plug,0,$plug);}
-		else{
-				for (my $i=0; $i<$value; $i++){
-					my $name="$plug\_$i";
-					ipgen_set_plug_name($self,$plug,$i,$name);
-				}
-			
-		}	
-		
-	}
-	else{ipgen_set_plug_name($self,$plug,0,$plug);}		
-	
-}		
+    my ($self,$plug,$type,$value)=@_;
+    $self->{plugs}{$plug}{type}=$type;
+    if(defined $value){$self->{plugs}{$plug}{value}=$value};
+    if($type eq 'num'){
+        if($value == 1) {ipgen_set_plug_name($self,$plug,0,$plug);}
+        else{
+                for (my $i=0; $i<$value; $i++){
+                    my $name="$plug\_$i";
+                    ipgen_set_plug_name($self,$plug,$i,$name);
+                }
+        }
+    }
+    else{ipgen_set_plug_name($self,$plug,0,$plug);}
+}
 
 sub ipgen_list_sokets{
-	my ($self)=@_;
-	my @sokets;
-	
-	if(exists ($self->{sockets})){
-		foreach my $p(keys %{$self->{sockets}}){
-			push (@sokets,$p);
-		}
-	}	
-	return @sokets;	
+    my ($self)=@_;
+    my @sokets;
+    if(exists ($self->{sockets})){
+        foreach my $p(keys %{$self->{sockets}}){
+            push (@sokets,$p);
+        }
+    }
+    return @sokets;
 }
 
-
 sub ipgen_list_plugs{
-	my ($self)=@_;
-	my @plugs;
-	if(exists ($self->{plugs})){
-		foreach my $p(keys %{$self->{plugs}}){
-			push (@plugs,$p);
-		}
-	}	
-	return @plugs;	
+    my ($self)=@_;
+    my @plugs;
+    if(exists ($self->{plugs})){
+        foreach my $p(keys %{$self->{plugs}}){
+            push (@plugs,$p);
+        }
+    }
+    return @plugs;
 }
-	
-
 
 sub ipgen_get_socket{
-	my ($self,$socket)=@_;
-	my ($type,$value,$connection_num);
-	if(exists ($self->{sockets}{$socket})){		
-		$type	=$self->{sockets}{$socket}{type};
-		$value	=$self->{sockets}{$socket}{value};
-		$connection_num= $self->{sockets}{$socket}{connection_num};
-		#print "$type,$value\n"
-	} 
-	return ($type,$value,$connection_num);
+    my ($self,$socket)=@_;
+    my ($type,$value,$connection_num);
+    if(exists ($self->{sockets}{$socket})){
+        $type    =$self->{sockets}{$socket}{type};
+        $value    =$self->{sockets}{$socket}{value};
+        $connection_num= $self->{sockets}{$socket}{connection_num};
+        #print "$type,$value\n"
+    }
+    return ($type,$value,$connection_num);
 }
 
 sub ipgen_get_plug{
-	my ($self,$plug)=@_;
-	my ($type,$value,$connection_num);
-	if(exists ($self->{plugs}{$plug})){
-		$type	=$self->{plugs}{$plug}{type};
-		$value	=$self->{plugs}{$plug}{value};
-		$connection_num=$self->{plugs}{$plug}{connection_num};
-	}
-	return ($type,$value,$connection_num);
+    my ($self,$plug)=@_;
+    my ($type,$value,$connection_num);
+    if(exists ($self->{plugs}{$plug})){
+        $type    =$self->{plugs}{$plug}{type};
+        $value    =$self->{plugs}{$plug}{value};
+        $connection_num=$self->{plugs}{$plug}{connection_num};
+    }
+    return ($type,$value,$connection_num);
 }
 
 sub ipgen_remove_socket{
-		my ($self,$socket)=@_;
-		if(exists ($self->{sockets}{$socket})) {
-				delete $self->{sockets}{$socket};
-		}	
-}	
+        my ($self,$socket)=@_;
+        if(exists ($self->{sockets}{$socket})) {
+                delete $self->{sockets}{$socket};
+        }
+}
 
 sub ipgen_remove_plug{
-		my ($self,$plug)=@_;
-		if(exists ($self->{plugs}{$plug})) {
-				delete $self->{plugs}{$plug};
-		}	
-}	
-	
-	
+        my ($self,$plug)=@_;
+        if(exists ($self->{plugs}{$plug})) {
+                delete $self->{plugs}{$plug};
+        }
+}
 
 sub ipgen_set_port_intfc_name{
-	my ($self,$port,$intfc_name)=@_;	
-	if(exists ($self->{ports}{$port})){
-		$self->{ports}{$port}{intfc_name}=$intfc_name;
-	}
-
+    my ($self,$port,$intfc_name)=@_;
+    if(exists ($self->{ports}{$port})){
+        $self->{ports}{$port}{intfc_name}=$intfc_name;
+    }
 }
 
 sub ipgen_get_port_intfc_name{
-	my ($self,$port)=@_;
-	my $intfc_name;
-	if(exists ($self->{ports}{$port}{intfc_name})){
-		$intfc_name=$self->{ports}{$port}{intfc_name};
-	}
-	return ($intfc_name);
-}	
+    my ($self,$port)=@_;
+    my $intfc_name;
+    if(exists ($self->{ports}{$port}{intfc_name})){
+        $intfc_name=$self->{ports}{$port}{intfc_name};
+    }
+    return ($intfc_name);
+}
 
 sub ipgen_set_port_intfc_port{
-	my ($self,$port,$intfc_port)=@_;	
-	if(exists ($self->{ports}{$port})){
-		$self->{ports}{$port}{intfc_port}=$intfc_port;
-	}
-
+    my ($self,$port,$intfc_port)=@_;
+    if(exists ($self->{ports}{$port})){
+        $self->{ports}{$port}{intfc_port}=$intfc_port;
+    }
 }
 
 sub ipgen_get_port_intfc_port{
-	my ($self,$port)=@_;
-	my $intfc_port;
-	if(exists ($self->{ports}{$port}{intfc_port})){
-		$intfc_port=$self->{ports}{$port}{intfc_port};
-	}
-	return ($intfc_port);
-}	
-	
-
+    my ($self,$port)=@_;
+    my $intfc_port;
+    if(exists ($self->{ports}{$port}{intfc_port})){
+        $intfc_port=$self->{ports}{$port}{intfc_port};
+    }
+    return ($intfc_port);
+}
 
 sub ipgen_save_wb_addr{
-	my ($self,$plug,$num,$addr,$width)=@_;
-	$self->{plugs}{$plug}{$num}{addr}=$addr;
-	$self->{plugs}{$plug}{$num}{width}=$width;	
-	
-}	
-	
+    my ($self,$plug,$num,$addr,$width)=@_;
+    $self->{plugs}{$plug}{$num}{addr}=$addr;
+    $self->{plugs}{$plug}{$num}{width}=$width;
+}
+
 sub ipgen_get_wb_addr{
-	my ($self,$plug,$num)=@_;
-	my($addr,$width);
-	if(exists ($self->{plugs}{$plug}{$num})){
-		$addr= $self->{plugs}{$plug}{$num}{addr};
-		$width=$self->{plugs}{$plug}{$num}{width};
-	}
-	return 	($addr,$width); 
-}		
-	
-sub ipgen_set_plug_name{
-	my ($self,$plug,$num,$name)=@_;
-	if(exists ($self->{plugs}{$plug})){
-		$self->{plugs}{$plug}{$num}{name}=$name;
-		
-	}	
-	
-}	
+    my ($self,$plug,$num)=@_;
+    my($addr,$width);
+    if(exists ($self->{plugs}{$plug}{$num})){
+        $addr= $self->{plugs}{$plug}{$num}{addr};
+        $width=$self->{plugs}{$plug}{$num}{width};
+    }
+    return     ($addr,$width);
+}
 
+sub ipgen_set_plug_name{
+    my ($self,$plug,$num,$name)=@_;
+    if(exists ($self->{plugs}{$plug})){
+        $self->{plugs}{$plug}{$num}{name}=$name;
+    }
+}
 
 sub ipgen_get_plug_name{
-	my ($self,$plug,$num)=@_;
-	my $name;
-	if(exists ($self->{plugs}{$plug}{$num}{name})){
-		 $name=$self->{plugs}{$plug}{$num}{name};
-		
-	}
-	return 	$name;	
+    my ($self,$plug,$num)=@_;
+    my $name;
+    if(exists ($self->{plugs}{$plug}{$num}{name})){
+        $name=$self->{plugs}{$plug}{$num}{name};
+    }
+    return     $name;
 }
 
 sub ipgen_set_socket_name {
-	my ($self,$socket,$num,$name)= @_;
-	if(exists ($self->{sockets}{$socket})){
-		$self->{sockets}{$socket}{$num}{name}=$name;
-		
-	}	
-	
-}	
+    my ($self,$socket,$num,$name)= @_;
+    if(exists ($self->{sockets}{$socket})){
+        $self->{sockets}{$socket}{$num}{name}=$name;
+    }
+}
 
 sub ipgen_get_socket_name{
-	my ($self,$socket,$num)=@_;
-	my $name;
-	if(exists ($self->{sockets}{$socket}{$num}{name})){
-		$name=$self->{sockets}{$socket}{$num}{name};
-		
-	}	
-	return $name;
-	
-}		
-
-	
+    my ($self,$socket,$num)=@_;
+    my $name;
+    if(exists ($self->{sockets}{$socket}{$num}{name})){
+        $name=$self->{sockets}{$socket}{$num}{name};
+    }
+    return $name;
+}
 
 sub ipgen_add_unused_intfc_port{
-	my ($self,$intfc_name,$port)=@_;
-	push(@{$self->{unused}{$intfc_name}},$port);	
+    my ($self,$intfc_name,$port)=@_;
+    push(@{$self->{unused}{$intfc_name}},$port);
 }
-
-
-
-
-
 #add,read,remove object fileds
-
 sub ipgen_add{
-	my ($self,$filed_name,$filed_data)=@_;
-	$self->{$filed_name}=$filed_data;		
+    my ($self,$filed_name,$filed_data)=@_;
+    $self->{$filed_name}=$filed_data;
 }
 
 sub ipgen_remove{
-	my ($self,$filed_name)=@_;
-	$self->{$filed_name}=undef;		
+    my ($self,$filed_name)=@_;
+    $self->{$filed_name}=undef;
 }
 
 sub ipgen_get{
-	my ($self,$filed_name)=@_;
-	return $self->{$filed_name}		
+    my ($self,$filed_name)=@_;
+    return $self->{$filed_name}
 }
 
 sub ipgen_get_list{
-	my ($self,$list_name)=@_;
-	my @l;
-	if ( defined $self->{$list_name} ){
-		@l=@{$self->{$list_name}};		
-	}	
-	
-	return @l;
+    my ($self,$list_name)=@_;
+    my @l;
+    if ( defined $self->{$list_name} ){
+        @l=@{$self->{$list_name}};
+    }
+    return @l;
 }
-
-
-
-
 ######################################
-
-
-
-
 sub top_gen_new {
     # be backwards compatible with non-OO call
     my $class =  shift;
     my $self;
-
-   
     $self = {};
     $self->{instance_ids}={};
     bless($self,$class);
-
-   
     return $self;
-} 
+}
 
 sub top_add_def_to_instance {
-	my ($self,$inst,$def,$value )=@_;
-		$self->{instance_ids}{$inst}{$def}=$value;
+    my ($self,$inst,$def,$value )=@_;
+        $self->{instance_ids}{$inst}{$def}=$value;
 }
 
 sub top_get_def_of_instance {
-	my ($self,$inst,$def)=@_;
-	my $val;
-	$val=$self->{instance_ids}{$inst}{$def} if(exists $self->{instance_ids}{$inst}{$def})	;
-	return $val;
+    my ($self,$inst,$def)=@_;
+    my $val;
+    $val=$self->{instance_ids}{$inst}{$def} if(exists $self->{instance_ids}{$inst}{$def})    ;
+    return $val;
 }
 
-
 sub top_add_port{
-	my($self,$inst,$port,$range,$type,$intfc_name,$intfc_port)=@_;
-	
-	#all ports
-	$self->{ports}{$port}{range}=$range;
-	$self->{ports}{$port}{type}=$type;
-	$self->{ports}{$port}{intfc_name}=$intfc_name;
-	$self->{ports}{$port}{intfc_port}=$intfc_port;
-	$self->{ports}{$port}{instance_name}=$inst;
-	
-	
-	#based on instance name	
-	$self->{instance_ids}{$inst}{ports}{$port}{range}=$range;
-	$self->{instance_ids}{$inst}{ports}{$port}{type}=$type;
-	$self->{instance_ids}{$inst}{ports}{$port}{intfc_name}=$intfc_name;
-	$self->{instance_ids}{$inst}{ports}{$port}{intfc_port}=$intfc_port;
-	
-	#based on interface name
-	$self->{interface}{$intfc_name}{ports}{$port}{range}=$range;
-	$self->{interface}{$intfc_name}{ports}{$port}{type}=$type;
-	$self->{interface}{$intfc_name}{ports}{$port}{instance_name}=$inst;
-	$self->{interface}{$intfc_name}{ports}{$port}{intfc_port}=$intfc_port;
+    my($self,$inst,$port,$range,$type,$intfc_name,$intfc_port)=@_;
+    #all ports
+    $self->{ports}{$port}{range}=$range;
+    $self->{ports}{$port}{type}=$type;
+    $self->{ports}{$port}{intfc_name}=$intfc_name;
+    $self->{ports}{$port}{intfc_port}=$intfc_port;
+    $self->{ports}{$port}{instance_name}=$inst;
+    #based on instance name
+    $self->{instance_ids}{$inst}{ports}{$port}{range}=$range;
+    $self->{instance_ids}{$inst}{ports}{$port}{type}=$type;
+    $self->{instance_ids}{$inst}{ports}{$port}{intfc_name}=$intfc_name;
+    $self->{instance_ids}{$inst}{ports}{$port}{intfc_port}=$intfc_port;
+    #based on interface name
+    $self->{interface}{$intfc_name}{ports}{$port}{range}=$range;
+    $self->{interface}{$intfc_name}{ports}{$port}{type}=$type;
+    $self->{interface}{$intfc_name}{ports}{$port}{instance_name}=$inst;
+    $self->{interface}{$intfc_name}{ports}{$port}{intfc_port}=$intfc_port;
 }
 
-
 sub top_get_interface{
-	my($self,$intfc_name,$port)=@_;
-	my $range= $self->{interface}{$intfc_name}{ports}{$port}{range};
-	my $type=  $self->{interface}{$intfc_name}{ports}{$port}{type};
-	my $inst = $self->{interface}{$intfc_name}{ports}{$port}{instance_name};
-	my $intfc_port=$self->{interface}{$intfc_name}{ports}{$port}{intfc_port};
-	return ($range,$type,$inst,$intfc_port);
+    my($self,$intfc_name,$port)=@_;
+    my $range= $self->{interface}{$intfc_name}{ports}{$port}{range};
+    my $type=  $self->{interface}{$intfc_name}{ports}{$port}{type};
+    my $inst = $self->{interface}{$intfc_name}{ports}{$port}{instance_name};
+    my $intfc_port=$self->{interface}{$intfc_name}{ports}{$port}{intfc_port};
+    return ($range,$type,$inst,$intfc_port);
 }
 
-
 sub top_get_port{
-	my($self,$port)=@_;
-	my($inst,$range,$type,$intfc_name,$intfc_port);
-	$inst		=$self->{ports}{$port}{instance_name};
-	$range		=$self->{ports}{$port}{range};
-	$type		=$self->{ports}{$port}{type};
-	$intfc_name	=$self->{ports}{$port}{intfc_name};
-	$intfc_port	=$self->{ports}{$port}{intfc_port};
-	return ($inst,$range,$type,$intfc_name,$intfc_port);	
+    my($self,$port)=@_;
+    my($inst,$range,$type,$intfc_name,$intfc_port);
+    $inst        =$self->{ports}{$port}{instance_name};
+    $range        =$self->{ports}{$port}{range};
+    $type        =$self->{ports}{$port}{type};
+    $intfc_name    =$self->{ports}{$port}{intfc_name};
+    $intfc_port    =$self->{ports}{$port}{intfc_port};
+    return ($inst,$range,$type,$intfc_name,$intfc_port);
 }
 
 sub top_get_port_list{
-	my$self=shift;
-	my @l;
-	if(exists $self->{ports}){
-		@l= sort keys %{$self->{ports}};
-	}
-	return @l;
+    my$self=shift;
+    my @l;
+    if(exists $self->{ports}){
+        @l= sort keys %{$self->{ports}};
+    }
+    return @l;
 }
 
-
-
 sub top_add_parameter{
-	my ($self,$inst,$parameter,$default,$type,$content,$info,$global_param,$redefine)=@_;
-	$self->{instance_ids}{$inst}{parameters}{$parameter}{"default"}=$default;	
-	$self->{instance_ids}{$inst}{parameters}{$parameter}{type}=$type;
-	$self->{instance_ids}{$inst}{parameters}{$parameter}{content}=$content;
-	$self->{instance_ids}{$inst}{parameters}{$parameter}{info}=$info;
-	$self->{instance_ids}{$inst}{parameters}{$parameter}{global_param}=$global_param;
-	$self->{instance_ids}{$inst}{parameters}{$parameter}{redefine_param}=$redefine;						
-}	
+    my ($self,$inst,$parameter,$default,$type,$content,$info,$global_param,$redefine)=@_;
+    $self->{instance_ids}{$inst}{parameters}{$parameter}{"default"}=$default;
+    $self->{instance_ids}{$inst}{parameters}{$parameter}{type}=$type;
+    $self->{instance_ids}{$inst}{parameters}{$parameter}{content}=$content;
+    $self->{instance_ids}{$inst}{parameters}{$parameter}{info}=$info;
+    $self->{instance_ids}{$inst}{parameters}{$parameter}{global_param}=$global_param;
+    $self->{instance_ids}{$inst}{parameters}{$parameter}{redefine_param}=$redefine;
+}
 
 sub top_add_localparam{
-	my ($self,$inst,$parameter,$default,$type,$content,$info,$global_param,$redefine)=@_;
-	$self->{instance_ids}{$inst}{localparam}{$parameter}{"default"}=$default;	
-	$self->{instance_ids}{$inst}{localparam}{$parameter}{type}=$type;
-	$self->{instance_ids}{$inst}{localparam}{$parameter}{content}=$content;
-	$self->{instance_ids}{$inst}{localparam}{$parameter}{info}=$info;
-	$self->{instance_ids}{$inst}{localparam}{$parameter}{global_param}=$global_param;
-	$self->{instance_ids}{$inst}{localparam}{$parameter}{redefine_param}=$redefine;						
-}	
-
+    my ($self,$inst,$parameter,$default,$type,$content,$info,$global_param,$redefine)=@_;
+    $self->{instance_ids}{$inst}{localparam}{$parameter}{"default"}=$default;
+    $self->{instance_ids}{$inst}{localparam}{$parameter}{type}=$type;
+    $self->{instance_ids}{$inst}{localparam}{$parameter}{content}=$content;
+    $self->{instance_ids}{$inst}{localparam}{$parameter}{info}=$info;
+    $self->{instance_ids}{$inst}{localparam}{$parameter}{global_param}=$global_param;
+    $self->{instance_ids}{$inst}{localparam}{$parameter}{redefine_param}=$redefine;
+}
 
 sub top_get_parameter{
-	my ($self,$inst,$parameter)=@_;
-	my ($default,$type,$content,$info,$global_param,$redefine);
-	$default=$self->{instance_ids}{$inst}{parameters}{$parameter}{"default"};	
-	$type=$self->{instance_ids}{$inst}{parameters}{$parameter}{type};
-	$content=$self->{instance_ids}{$inst}{parameters}{$parameter}{content};
-	$info=$self->{instance_ids}{$inst}{parameters}{$parameter}{info};
-	$global_param=$self->{instance_ids}{$inst}{parameters}{$parameter}{global_param};
-	$redefine=$self->{instance_ids}{$inst}{parameters}{$parameter}{redefine_param};	
-	return  ($default,$type,$content,$info,$global_param,$redefine);					
-}	
+    my ($self,$inst,$parameter)=@_;
+    my ($default,$type,$content,$info,$global_param,$redefine);
+    $default=$self->{instance_ids}{$inst}{parameters}{$parameter}{"default"};
+    $type=$self->{instance_ids}{$inst}{parameters}{$parameter}{type};
+    $content=$self->{instance_ids}{$inst}{parameters}{$parameter}{content};
+    $info=$self->{instance_ids}{$inst}{parameters}{$parameter}{info};
+    $global_param=$self->{instance_ids}{$inst}{parameters}{$parameter}{global_param};
+    $redefine=$self->{instance_ids}{$inst}{parameters}{$parameter}{redefine_param};
+    return  ($default,$type,$content,$info,$global_param,$redefine);
+}
 
 sub top_get_parameter_list{
-	my($self,$inst)=@_;
-	my @l;
-	if(exists $self->{instance_ids}{$inst}{parameters}){
-		@l= sort keys %{$self->{instance_ids}{$inst}{parameters}};
-	}
-	return @l;
+    my($self,$inst)=@_;
+    my @l;
+    if(exists $self->{instance_ids}{$inst}{parameters}){
+        @l= sort keys %{$self->{instance_ids}{$inst}{parameters}};
+    }
+    return @l;
 }
 
-
-
-
 sub top_add_default_soc_param{
-	my ($self,$param_ref)=@_;
-	my %l=%{$param_ref};
-	foreach my $p (sort keys %l){	
-		$self->{parameters}{$p}=$l{$p};
-		#print"$self->{parameters}{$p}=$l{$p};\n";
-	}	
-}	
+    my ($self,$param_ref)=@_;
+    my %l=%{$param_ref};
+    foreach my $p (sort keys %l){
+        $self->{parameters}{$p}=$l{$p};
+        #print"$self->{parameters}{$p}=$l{$p};\n";
+    }
+}
 
 sub top_get_default_soc_param{
-	my $self=shift;
-	my %l;
-	if(exists $self->{parameters}){
-		 %l=%{$self->{parameters}};
-	}
-	return  %l;
-}	
-	
-	
-sub top_get_all_instances{
-	my ($self)=shift;
-	my @r= keys %{$self->{instance_ids}};
-	return @r;	
-	
+    my $self=shift;
+    my %l;
+    if(exists $self->{parameters}){
+        %l=%{$self->{parameters}};
+    }
+    return  %l;
 }
 
+sub top_get_all_instances{
+    my ($self)=shift;
+    my @r= keys %{$self->{instance_ids}};
+    return @r;
+}
 
 sub top_get_intfc_list{
-	my ($self)=shift;
-	my @intfcs;
-	if(exists $self->{interface}){
-		@intfcs= sort keys %{$self->{interface}};
-	}
-	
-	return 	@intfcs;
+    my ($self)=shift;
+    my @intfcs;
+    if(exists $self->{interface}){
+        @intfcs= sort keys %{$self->{interface}};
+    }
+    return     @intfcs;
 }
 
-
-
-
 sub top_get_intfc_ports_list{
-	my($self,$intfc_name)=@_;
-	my @ports;
-	if( exists $self->{interface}{$intfc_name}{ports}){
-		@ports= sort keys %{$self->{interface}{$intfc_name}{ports}};
-	}
-	return @ports;
+    my($self,$intfc_name)=@_;
+    my @ports;
+    if( exists $self->{interface}{$intfc_name}{ports}){
+        @ports= sort keys %{$self->{interface}{$intfc_name}{ports}};
+    }
+    return @ports;
 }
 
-
 sub top_add_custom_soc_param{
-	my ($self,$param_ref,$tile)=@_;
-	my %l=%{$param_ref};
-	foreach my $p (sort keys %l){	
-		$self->{tiles}{$tile}{parameters}{$p}=$l{$p};
-		#print"$self->{parameters}{$p}=$l{$p};\n";
-	}	
-}	
-
+    my ($self,$param_ref,$tile)=@_;
+    my %l=%{$param_ref};
+    foreach my $p (sort keys %l){
+        $self->{tiles}{$tile}{parameters}{$p}=$l{$p};
+        #print"$self->{parameters}{$p}=$l{$p};\n";
+    }
+}
 
 sub top_get_custom_tile_list{
-	my ($self)=@_;
-	my %tiles_hash;
-	%tiles_hash=%{$self->{'tiles'}} if(defined $self->{'tiles'} );
-	my @tiles = sort keys %tiles_hash;
-	return  @tiles;	 
-}	
-
-
+    my ($self)=@_;
+    my %tiles_hash;
+    %tiles_hash=%{$self->{'tiles'}} if(defined $self->{'tiles'} );
+    my @tiles = sort keys %tiles_hash;
+    return  @tiles;
+}
 
-	
-	
-	
-	
 sub top_get_custom_soc_param{
-	my ($self,$tile)=@_;
-	my %l;
-	if(exists $self->{tiles}{$tile}{parameters}){#get custom param
-		 %l=%{$self->{tiles}{$tile}{parameters}};
-	}elsif (exists $self->{parameters}){#get default param
-		 %l=%{$self->{parameters}};
-	}
-	return  %l;
-	
-}		
-
-
+    my ($self,$tile)=@_;
+    my %l;
+    if(exists $self->{tiles}{$tile}{parameters}){#get custom param
+        %l=%{$self->{tiles}{$tile}{parameters}};
+    }elsif (exists $self->{parameters}){#get default param
+        %l=%{$self->{parameters}};
+    }
+    return  %l;
+}
 
 sub object_add_attribute{
-	my ($self,$attribute1,$attribute2,$value)=@_;
-	if(!defined $attribute2){$self->{$attribute1}=$value;}
-	else {$self->{$attribute1}{$attribute2}=$value;}
-
+    my ($self,$attribute1,$attribute2,$value)=@_;
+    if(!defined $attribute2){$self->{$attribute1}=$value;}
+    else {$self->{$attribute1}{$attribute2}=$value;}
 }
 
 sub object_get_attribute{
-	my ($self,$attribute1,$attribute2)=@_;
-	if(!defined $attribute2) {return $self->{$attribute1};}
-	return $self->{$attribute1}{$attribute2};
-
-
+    my ($self,$attribute1,$attribute2)=@_;
+    if(!defined $attribute2) {return $self->{$attribute1};}
+    return $self->{$attribute1}{$attribute2};
 }
 
 sub object_add_attribute_order{
-	my ($self,$attribute,@param)=@_;
-	my $r = $self->{'parameters_order'}{$attribute};
-	my @a;
-	@a = @{$r} if(defined $r);
-	push (@a,@param);
-	@a=List::MoreUtils(@a);	
-	$self->{'parameters_order'}{$attribute} =\@a;
+    my ($self,$attribute,@param)=@_;
+    my $r = $self->{'parameters_order'}{$attribute};
+    my @a;
+    @a = @{$r} if(defined $r);
+    push (@a,@param);
+    @a=List::MoreUtils(@a);
+    $self->{'parameters_order'}{$attribute} =\@a;
 }
 
 sub object_get_attribute_order{
-	my ($self,$attribute)=@_;
-	return @{$self->{parameters_order}{$attribute}};
+    my ($self,$attribute)=@_;
+    return @{$self->{parameters_order}{$attribute}};
 }
-	
-
-
-	1
+1;
diff --git a/mpsoc/perl_gui/lib/perl/mpsoc_gen.pl b/mpsoc/perl_gui/lib/perl/mpsoc_gen.pl
index a628f8b..0d8fd1c 100755
--- a/mpsoc/perl_gui/lib/perl/mpsoc_gen.pl
+++ b/mpsoc/perl_gui/lib/perl/mpsoc_gen.pl
@@ -25,6 +25,7 @@
 require "diagram.pl";
 require "orcc.pl";
 
+my %noc_param_comment;
 
 sub initial_default_param{
     my $mpsoc=shift;
@@ -50,19 +51,18 @@ sub initial_default_param{
 #############
 #    get_soc_lists
 ############
-
 sub get_soc_list {
     my ($mpsoc,$info)=@_;    
-    my $path=$mpsoc->object_get_attribute('setting','soc_path');        
+    my $path=$mpsoc->object_get_attribute('setting','soc_path');
     $path =~ s/ /\\ /g;
     my @socs;
     my @files = glob "$path/*.SOC";
     for my $p (@files){
-       my ($soc,$r,$err) = regen_object($p);
-        # Read       
-         if ($r){        
+        my ($soc,$r,$err) = regen_object($p);
+        # Read
+        if ($r){
             add_info($info,"**Error reading  $p file: $err\n");
-                 next; 
+            next; 
         } 
         my $top=$soc->soc_get_top();
         if (defined $top){
@@ -78,26 +78,23 @@ sub get_soc_list {
                     copy_back_custom_soc_param($top,$old_top) if(defined $old_top);
                     $mpsoc->mpsoc_add_soc($name,$top);
                     #print" $name\n";
-                }        
+                } 
             }            
-        
         }        
     }# files
-    
     # initial  default soc parameter
     initial_default_param($mpsoc);    
     return $mpsoc->mpsoc_get_soc_list;
 }
 
 sub copy_back_custom_soc_param{
-	my ($new,$old)=@_;
-	my @tiles = $old->top_get_custom_tile_list();
-	foreach my $tile (@tiles){
-		my %l =$old->top_get_custom_soc_param($tile);
-		$new->top_add_custom_soc_param (\%l,$tile);
-	}
-	 
-}	
+    my ($new,$old)=@_;
+    my @tiles = $old->top_get_custom_tile_list();
+    foreach my $tile (@tiles){
+        my %l =$old->top_get_custom_soc_param($tile);
+        $new->top_add_custom_soc_param (\%l,$tile);
+    }
+}
 
 sub get_NI_instance_list {
     my $top=shift;
@@ -107,7 +104,7 @@ sub get_NI_instance_list {
     #check if the soc has ni port
     foreach my $instanc(@instance_list){
             my $category=$top->top_get_def_of_instance($instanc,'category');
-             push(@nis,$instanc) if($category eq 'NoC') ;
+            push(@nis,$instanc) if($category eq 'NoC') ;
     }
     return @nis;
 }
@@ -115,29 +112,21 @@ sub get_NI_instance_list {
 ####################
 # get_conflict_decision
 ###########################
-
-
 sub get_conflict_decision{
     my ($mpsoc,$name,$inserted,$conflicts,$msg)=@_;
     $msg="\tThe inserted tile number(s) have been mapped previously to \n\t\t\"$msg\".\n\tDo you want to remove the conflicted tiles number(s) in newly \n\tinserted range or remove them from the previous ones? ";
-    
     my $wind=def_popwin_size(10,30,"warning",'percent');
     my $label= gen_label_in_left($msg);    
     my $table=def_table(2,6,FALSE);
     $table->attach_defaults ($label , 0, 6, 0,1);
     $wind->add($table);
-
     my $b1= def_button("Remove Previous");
     my $b2= def_button("Remove Current");
     my $b3= def_button("Cancel");
-    
     $table->attach ($b1 , 0, 1, 1,2,'fill','fill',2,2);
     $table->attach ($b2 , 3, 4, 1,2,'fill','fill',2,2);
     $table->attach ($b3 , 5, 6, 1,2,'fill','fill',2,2);
-
-
     $wind->show_all();
-    
     $b1->signal_connect( "clicked"=> sub{ #Remove Previous
         my @socs=$mpsoc->mpsoc_get_soc_list();        
         foreach my $p (@socs){
@@ -152,9 +141,7 @@ sub get_conflict_decision{
         #set_gui_status($mpsoc,"ref",1);        
         $wind->destroy();        
         get_soc_parameter_setting($mpsoc,$name, $inserted)if(defined $inserted  );
-            
     });
-    
     $b2->signal_connect( "clicked"=> sub{#Remove Current
         my @new= get_diff_array($inserted,$conflicts);    
         $mpsoc->mpsoc_add_soc_tiles_num($name,\@new) if(scalar @new  );
@@ -162,9 +149,7 @@ sub get_conflict_decision{
         #set_gui_status($mpsoc,"ref",1);        
         $wind->destroy(); 
         get_soc_parameter_setting($mpsoc,$name, \@new) if(scalar @new  );       
-        
     });
-    
     $b3->signal_connect( "clicked"=> sub{
         $wind->destroy();        
         
@@ -179,7 +164,6 @@ sub check_inserted_ip_nums{
     my  ($mpsoc,$name,$str)=@_;
     my @all_num=();
     $str= remove_all_white_spaces ($str);
-    
     if($str !~ /^[0-9.:,]+$/){ message_dialog ("The Ip numbers contains invalid character" ); return; }
     my @chunks=split(/\s*,\s*/,$str);
     foreach my $p (@chunks){
@@ -194,16 +178,12 @@ sub check_inserted_ip_nums{
             for (my $i=$min; $i<=$max; $i++){
                 if ( grep( /^$i$/, @all_num ) ) { message_dialog ("Multiple definition for IP number $i in $p" ); return; }
                 push(@all_num,$i);
-                
             }
-            
         }else{message_dialog ("invalid range: [$p]" ); return; }    
-        
     }
     #check if range does not exceed the tile numbers
     my ($NE, $NR, $RAw, $EAw, $Fw)=get_topology_info($mpsoc);
     my $max_tile_num=$NE;
-    
     my @f=sort { $a <=> $b }  @all_num;
     my @l;
     foreach my $num (@f){
@@ -211,12 +191,9 @@ sub check_inserted_ip_nums{
         
     }
     @all_num=@l;
-    
     #check if any ip number exists in the rest
     my $conflicts_msg;
     my @conflicts;
-    
-    
     my @socs=$mpsoc->mpsoc_get_soc_list();
     foreach my $p (@socs){
         if($p ne $name){
@@ -230,18 +207,16 @@ sub check_inserted_ip_nums{
         }#if
     }
     if (defined $conflicts_msg) {
-       get_conflict_decision($mpsoc,$name,\@all_num,\@conflicts,$conflicts_msg);
-       
-        
+        get_conflict_decision($mpsoc,$name,\@all_num,\@conflicts,$conflicts_msg);
     }else {
         #save the entered ips
         if( scalar @all_num>0){ 
-        	$mpsoc->mpsoc_add_soc_tiles_num($name,\@all_num);
-        	return \@all_num;
+            $mpsoc->mpsoc_add_soc_tiles_num($name,\@all_num);
+            return \@all_num;
         }
         else {
-        	$mpsoc->mpsoc_add_soc_tiles_num($name,undef);
-        	return undef;
+            $mpsoc->mpsoc_add_soc_tiles_num($name,undef);
+            return undef;
         }
         #set_gui_status($mpsoc,"ref",1);
     }
@@ -252,18 +227,14 @@ sub check_inserted_ip_nums{
 #################
 # get_soc_parameter_setting
 ################
-
-
-
-
 sub get_soc_parameter_setting{
     my ($mpsoc,$soc_name,$tiles_ref)=@_;
     my @tiles = @{$tiles_ref} if defined ($tiles_ref);
     my $string = join (',',@tiles );
     my $window =  def_popwin_size(40,40,"Parameter setting for $soc_name mapped to tile( $string ) ",'percent');
     my $table = get_soc_parameter_setting_table($mpsoc,$soc_name,$window,$tiles_ref);
-	$window->add($table);
-	$window->show_all;
+    $window->add($table);
+    $window->show_all;
 }
 
 
@@ -271,18 +242,15 @@ sub get_soc_parameter_setting_table{
     my ($mpsoc,$soc_name,$window,$tiles_ref)=@_;
     my @tiles;
     @tiles = @{$tiles_ref} if defined ($tiles_ref);
-   # my $window =  def_popwin_size(40,40,"Parameter setting for $soc_name mapped to tile(@tiles) ",'percent');
+    # my $window =  def_popwin_size(40,40,"Parameter setting for $soc_name mapped to tile(@tiles) ",'percent');
     my $table = def_table(10, 7, FALSE);
-    
     my $scrolled_win = add_widget_to_scrolled_win($table);
     my $row=0;
     my $column=0;
     my $top=$mpsoc->mpsoc_get_soc($soc_name);
-    
     #read soc parameters
     my %param_value=(scalar @tiles ==1 ) ? $top->top_get_custom_soc_param($tiles[0])  : $top->top_get_default_soc_param();
     $mpsoc->object_add_attribute('current_tile_param',undef,\%param_value);
-     
     my @insts=$top->top_get_all_instances();
     my @exceptions=get_NI_instance_list($top);
     @insts=get_diff_array(\@insts,\@exceptions);
@@ -291,85 +259,71 @@ sub get_soc_parameter_setting_table{
         foreach my $p (@params){    
             my  ($default,$type,$content,$info,$global_param,$redefine)=$top->top_get_parameter($inst,$p);
             my $show = ($type ne "Fixed");
-			$default= $param_value{$p} if(defined $param_value{$p});
-			($row,$column)=add_param_widget($mpsoc,$p,$p, $default,$type,$content,$info, $table,$row,$column,$show,'current_tile_param',undef,undef,'vertical');
-		}
-           
-            
-  #          if ($type eq "Entry"){
-  #              my $entry=gen_entry($param_value{$p});
-  #              $table->attach_defaults ($entry, 3, 6, $row, $row+1);
-  #              $entry-> signal_connect("changed" => sub{$param_value{$p}=$entry->get_text();});
-  #          }
-  #          elsif ($type eq "Combo-box"){
-  #              my @combo_list=split(/\s*,\s*/,$content);
-  #              my $pos=get_item_pos($param_value{$p}, @combo_list) if(defined $param_value{$p});
-  #              my $combo=gen_combo(\@combo_list, $pos);
-  #              $table->attach_defaults ($combo, 3, 6, $row, $row+1);
-  #              $combo-> signal_connect("changed" => sub{$param_value{$p}=$combo->get_active_text();});
-  #              
-  #          }
-  #          elsif     ($type eq "Spin-button"){ 
-  #                my ($min,$max,$step)=split(/\s*,\s*/,$content);
-  #                $param_value{$p}=~ s/\D//g;
-  #                $min=~ s/\D//g;
-  #                $max=~ s/\D//g;    
-  #                $step=~ s/\D//g;
-  #                my $spin=gen_spin($min,$max,$step);
-  #                $spin->set_value($param_value{$p});
-  #                $table->attach_defaults ($spin, 3, 4, $row, $row+1);
-  #                $spin-> signal_connect("value_changed" => sub{$param_value{$p}=$spin->get_value_as_int();});
-  #       
-  #       # $box=def_label_spin_help_box ($param,$info, $value,$min,$max,$step, 2);
-  #          }
-  #          my $label =gen_label_in_center($p);
-  #          $table->attach_defaults ($label, 0, 3, $row, $row+1);
-  #          if (defined $info){
-  #          my $info_button=def_image_button('icons/help.png');
-  #          $table->attach_defaults ($info_button, 6, 7, $row, $row+1);    
-  #          $info_button->signal_connect('clicked'=>sub{
-  #              message_dialog($info);
-  #              
-  #          });
-  #          
-  #      }       
-  #      $row++;
-  #                      
-  #      
-  #      }
+            $default= $param_value{$p} if(defined $param_value{$p});
+            ($row,$column)=add_param_widget($mpsoc,$p,$p, $default,$type,$content,$info, $table,$row,$column,$show,'current_tile_param',undef,undef,'vertical');
+        }
+    #          if ($type eq "Entry"){
+    #              my $entry=gen_entry($param_value{$p});
+    #              $table->attach_defaults ($entry, 3, 6, $row, $row+1);
+    #              $entry-> signal_connect("changed" => sub{$param_value{$p}=$entry->get_text();});
+    #          }
+    #          elsif ($type eq "Combo-box"){
+    #              my @combo_list=split(/\s*,\s*/,$content);
+    #              my $pos=get_item_pos($param_value{$p}, @combo_list) if(defined $param_value{$p});
+    #              my $combo=gen_combo(\@combo_list, $pos);
+    #              $table->attach_defaults ($combo, 3, 6, $row, $row+1);
+    #              $combo-> signal_connect("changed" => sub{$param_value{$p}=$combo->get_active_text();});
+    #              
+    #          }
+    #          elsif     ($type eq "Spin-button"){ 
+    #                my ($min,$max,$step)=split(/\s*,\s*/,$content);
+    #                $param_value{$p}=~ s/\D//g;
+    #                $min=~ s/\D//g;
+    #                $max=~ s/\D//g;    
+    #                $step=~ s/\D//g;
+    #                my $spin=gen_spin($min,$max,$step);
+    #                $spin->set_value($param_value{$p});
+    #                $table->attach_defaults ($spin, 3, 4, $row, $row+1);
+    #                $spin-> signal_connect("value_changed" => sub{$param_value{$p}=$spin->get_value_as_int();});
+    #       
+    #       # $box=def_label_spin_help_box ($param,$info, $value,$min,$max,$step, 2);
+    #          }
+    #          my $label =gen_label_in_center($p);
+    #          $table->attach_defaults ($label, 0, 3, $row, $row+1);
+    #          if (defined $info){
+    #          my $info_button=def_image_button('icons/help.png');
+    #          $table->attach_defaults ($info_button, 6, 7, $row, $row+1);    
+    #          $info_button->signal_connect('clicked'=>sub{
+    #              message_dialog($info);
+    #              
+    #          });
+    #      }
+    #      $row++;
+    #      }
     }
     
     my $ok = def_image_button('icons/select.png','OK');
     my $okbox=def_hbox(TRUE,0);
     $okbox->pack_start($ok, FALSE, FALSE,0);
-    
-    
     my $mtable = def_table(10, 1, TRUE);
-
     $mtable->attach_defaults($scrolled_win,0,1,0,9);
     $mtable->attach_defaults($okbox,0,1,9,10);
-    
-   
-    
     $ok-> signal_connect("clicked" => sub{ 
         $window->destroy if(defined $window);
         #save new values 
         my $ref=$mpsoc->object_get_attribute('current_tile_param');
-		%param_value=%{$ref};
-             
-       # if(!defined $tile ) {
+        %param_value=%{$ref};
+        # if(!defined $tile ) {
         #    $top->top_add_default_soc_param(\%param_value);
         #    $mpsoc->object_add_attribute('soc_param',"default",\%param_value);      
-       # }
-       # else {
-       	foreach my $tile (@tiles){
+        # }
+        # else {
+        foreach my $tile (@tiles){
             $top->top_add_custom_soc_param(\%param_value,$tile);
             $mpsoc->object_add_attribute('soc_param',"custom_${soc_name}",\%param_value);            
         }
         $mpsoc->object_add_attribute('current_tile_param',undef,undef);
         set_gui_status($mpsoc,"refresh_soc",1);
-             
-        
         });  
     $mtable->show_all();    
     return  $mtable;    
@@ -378,7 +332,6 @@ sub get_soc_parameter_setting_table{
 ################
 #    tile_set_widget
 ################
-
 sub tile_set_widget{
     my ($mpsoc,$soc_name,$num,$table,$show,$row)=@_;
     #my $label=gen_label_in_left($soc);
@@ -390,54 +343,38 @@ sub tile_set_widget{
     my $set= def_image_button('icons/right.png');
     my $remove= def_image_button('icons/cancel.png');
     #my $setting= def_image_button('icons/setting.png','setting');
-                
-                
     my $button = def_colored_button($soc_name,$num);    
     $button->signal_connect("clicked"=> sub{
-       # get_soc_parameter_setting($mpsoc,$soc_name,undef);        
+        # get_soc_parameter_setting($mpsoc,$soc_name,undef);        
     });        
     
     $set->signal_connect("clicked"=> sub{
         my $data=$entry->get_text();
         my $r=check_inserted_ip_nums($mpsoc,$soc_name,$data);
         if(defined $r){
-        	my @all_num = @{$r};
-        	get_soc_parameter_setting($mpsoc,$soc_name,\@all_num);
+            my @all_num = @{$r};
+            get_soc_parameter_setting($mpsoc,$soc_name,\@all_num);
         }        
     });
-    
     $remove->signal_connect("clicked"=> sub{
         $mpsoc->mpsoc_remove_soc($soc_name);
         set_gui_status($mpsoc,"ref",1);
     });
-
-    
-if($show){
-    $table->attach ( $button, 0, 1, $row,$row+1,'fill','fill',2,2);
-    $table->attach ( $remove, 1, 2, $row,$row+1,'fill','shrink',2,2);
-    $table->attach ( $entry , 2, 3, $row,$row+1,'fill','shrink',2,2);    
-    $table->attach ( $set, 3, 4, $row,$row+1,'fill','shrink',2,2);
-    
-
-        
-    $row++;
-}        
-    
+    if($show){
+        $table->attach ( $button, 0, 1, $row,$row+1,'fill','fill',2,2);
+        $table->attach ( $remove, 1, 2, $row,$row+1,'fill','shrink',2,2);
+        $table->attach ( $entry , 2, 3, $row,$row+1,'fill','shrink',2,2);    
+        $table->attach ( $set, 3, 4, $row,$row+1,'fill','shrink',2,2);
+        $row++;
+    }        
     return $row;    
-    
-    
-}        
-
-
-
+}
 
 ##################
 #    defualt_tilles_setting
 ###################
-
 sub defualt_tilles_setting {
     my ($mpsoc,$table,$show,$row,$info)=@_;
-        
     #title    
     my $separator1 = gen_Hsep();
     my $separator2 = gen_Hsep();
@@ -447,33 +384,26 @@ sub defualt_tilles_setting {
     $box1->pack_start( $title2, FALSE, FALSE, 3);
     $box1->pack_start( $separator2, FALSE, FALSE, 3);
     if($show){$table->attach_defaults ($box1 ,0,4, $row,$row+1);$row++;}
-     
-    
     my $label = gen_label_in_left("Tiles path:");
     my $entry = gen_entry();
     my $browse= def_image_button("icons/browse.png");
     my $file= $mpsoc->object_get_attribute('setting','soc_path');
     if(defined $file){$entry->set_text($file);}
-    
-    
-	$browse->signal_connect("clicked"=> sub{
-		my $entry_ref=$_[1];
-		my $file;
-		my $dialog = gen_folder_dialog('Select tile directory');
-		if ( "ok" eq $dialog->run ) {
-			$file = $dialog->get_filename;
+    $browse->signal_connect("clicked"=> sub{
+        my $entry_ref=$_[1];
+        my $file;
+        my $dialog = gen_folder_dialog('Select tile directory');
+        if ( "ok" eq $dialog->run ) {
+            $file = $dialog->get_filename;
             $$entry_ref->set_text($file);
             $mpsoc->object_add_attribute('setting','soc_path',$file);
             $mpsoc->mpsoc_remove_all_soc();
             set_gui_status($mpsoc,"ref",1);            
             #check_input_file($file,$socgen,$info);
-                    #print "file = $file\n";
-		}
+            #print "file = $file\n";
+        }
         $dialog->destroy;
-
     } , \$entry);
-        
-    
     $entry->signal_connect("activate"=>sub{
         my $file_name=$entry->get_text();
         $mpsoc->object_add_attribute('setting','soc_path',$file_name);
@@ -481,9 +411,6 @@ sub defualt_tilles_setting {
         set_gui_status($mpsoc,"ref",1);    
         #check_input_file($file_name,$socgen,$info);
     });
-        
-    
-    
     if($show){
         my $tmp=gen_label_in_left(" "); 
         $table->attach  ($label, 0, 1 , $row,$row+1,'fill','shrink',2,2);
@@ -492,20 +419,12 @@ sub defualt_tilles_setting {
         $table->attach ($browse, 3, 4, $row,$row+1,'fill','shrink',2,2);
         $row++;
     }
-    
-    
-    
     my @socs=$mpsoc->mpsoc_get_soc_list();
-    if( scalar @socs == 0){        
+    if( scalar @socs == 0){
         @socs=get_soc_list($mpsoc,$info); 
-                
     }
     @socs=$mpsoc->mpsoc_get_soc_list();
-   
-    
-    
     my $lab1=gen_label_in_center(' Tile name');
-    
     my $lab2=gen_label_help('Define the tile numbers that each IP is mapped to.
 you can add individual numbers or ranges as follow 
     e.g. individual numbers: 5,6,7,8,9,10
@@ -515,130 +434,147 @@ sub defualt_tilles_setting {
         $table->attach_defaults ($lab1 ,0,1, $row,$row+1);
         $table->attach_defaults ($lab2 ,2,3, $row,$row+1);$row++;
     }    
-    
     my $soc_num=0;
-    foreach my $soc_name (@socs){    
+    foreach my $soc_name (@socs){
         $row=tile_set_widget ($mpsoc,$soc_name,$soc_num,$table,$show,$row);    
-        $soc_num++;        
-        
-    }    
+        $soc_num++;
+    }
     return $row;
-    
 }
 
 
-
-
 #######################
 #   noc_config
 ######################
-
-
 sub noc_topology_setting_gui {
-	my ($mpsoc,$table,$txview,$row,$show_noc,$noc_id)=@_;
+    my ($mpsoc,$table,$txview,$row,$show_noc,$noc_id)=@_;
     my $noc_param="noc_param$noc_id";
-	my $coltmp=0;
-	#  topology
-	my  $label='Topology';
-	my  $param='TOPOLOGY';
-	my  $default='"MESH"';
-	my  $content='"MESH","FMESH","TORUS","RING","LINE","FATTREE","TREE","STAR","CUSTOM"';
-	my  $type='Combo-box';
-	my  $info="NoC topology"; 
-	($row,$coltmp)=add_param_widget ($mpsoc,$label,$param, $default,$type,$content,$info, $table,$row,undef,$show_noc,$noc_param,1);
-            
+    my $noc_type="noc_type$noc_id";
+    my $coltmp=0;
+    #  topology
+    my  $label='Topology';
+    my  $param='TOPOLOGY';
+    my  $default='"MESH"';
+    my  $content='"MESH","FMESH","MESH_3D","TORUS","RING","LINE","FATTREE","TREE","STAR","CUSTOM","MULTI_MESH"';
+    my  $type='Combo-box';
+    my  $info="Specifies the NoC topology. 
+    Options include $content"; 
+    $noc_param_comment{$param}="$info";
+    ($row,$coltmp)=add_param_widget ($mpsoc,$label,$param, $default,$type,$content,$info, $table,$row,undef,$show_noc,$noc_param,1);
     my $topology=$mpsoc->object_get_attribute($noc_param,'TOPOLOGY');
-
-	if($topology ne '"CUSTOM"' ){
+    if ($topology eq '"MULTI_MESH"') {
+        # Multi-Mesh requires YAML configuration file selection
+        $label= "Select yaml file";
+        $param= 'YAML_FILE';
+        $info= "Select the YAML file containing the Multi-Mesh configuration settings";
+        $type= 'FILE_path';
+        $default = undef;
+        my $dir  = "$ENV{PITON_ROOT}/configs";
+        $content = "yaml:$dir";
+        ($row,$coltmp)= add_param_widget ($mpsoc,$label,$param, $default,$type,$content,$info, $table,$row,undef,$show_noc,$noc_type,1);
+    } elsif ($topology ne '"CUSTOM"') {
     #topology T1 parameter
-	    $label= 
-	    	($topology eq '"FATTREE"' || $topology eq '"TREE"')? 'K' :
-	     	($topology eq '"STAR"')? "Total Endpoint number" : 'Routers per row';
-	    $param= 'T1';
-		$default= '2';
-	    $content=
-	    ($topology eq '"MESH"'  || $topology eq '"TORUS"') ? '2,16,1':
-	    ($topology eq '"FMESH"')? '1,16,1':
-		($topology eq '"FATTREE"' || $topology eq '"TREE"' )? '2,6,1':'2,64,1';
-	    $info= ($topology eq '"FATTREE"' || $topology eq '"TREE"' )? 'number of last level individual router`s endpoints.' :'Number of NoC routers in row (X dimension)';
-	    $type= 'Spin-button';             
-	    ($row,$coltmp)=add_param_widget ($mpsoc,$label,$param, $default,$type,$content,$info, $table,$row,undef,$show_noc,$noc_param,1);
-
+        $label= 
+            ($topology eq '"FATTREE"' || $topology eq '"TREE"')? 'K' :
+            ($topology eq '"STAR"')? "Total Endpoint number" : 'Routers per row';
+        $param= 'T1';
+        $default= '2';
+        $content=
+        ($topology eq '"MESH"'  || $topology eq '"TORUS"' || $topology eq '"MESH_3D"') ? '2,16,1':
+        ($topology eq '"FMESH"')? '1,16,1':
+        ($topology eq '"FATTREE"' || $topology eq '"TREE"' )? '2,6,1':'2,64,1';
+        $info= ($topology eq '"FATTREE"' || $topology eq '"TREE"' )? 'number of last level individual router`s endpoints.' :'Number of NoC routers in row (X dimension)';
+        $type= 'Spin-button'; 
+        $noc_param_comment{$param}="$info";
+        ($row,$coltmp)=add_param_widget ($mpsoc,$label,$param, $default,$type,$content,$info, $table,$row,undef,$show_noc,$noc_param,1);
     
     #Topology T2 parameter
-    if($topology eq '"MESH"' || $topology eq '"FMESH"' || $topology eq '"TORUS"' || $topology eq '"FATTREE"' || $topology eq '"TREE"' ) {
+    if($topology eq '"MESH"' || $topology eq '"FMESH"' || $topology eq '"TORUS"' || $topology eq '"FATTREE"' || $topology eq '"TREE"' ||  $topology eq '"MESH_3D"') {
         $label= ($topology eq '"FATTREE"' || $topology eq '"TREE"')?  'L' :'Routers per column';
         $param= 'T2';
         $default='2';
         $content=  ($topology eq '"FMESH"')? '1,16,1': '2,16,1';
         $info= ($topology eq '"FATTREE"' || $topology eq '"TREE"')? 'Fattree layer number (The height of FT)':'Number of NoC routers in column (Y dimension)';
-        $type= 'Spin-button';             
+        $type= 'Spin-button'; 
+        $noc_param_comment{$param}="$info";
         ($row,$coltmp)=add_param_widget ($mpsoc,$label,$param, $default,$type,$content,$info, $table,$row,undef,$show_noc,$noc_param,1);
     } else {
-        $mpsoc->object_add_attribute($noc_param,'T2',1);        
+        $mpsoc->object_add_attribute($noc_param,'T2',1);
     }
     
     #Topology T3 parameter
-    if($topology eq '"MESH"' || $topology eq '"FMESH"' || $topology eq '"TORUS"' || $topology eq '"RING"' || $topology eq '"LINE"') {
-    	$label="Router's endpoint number";
-		$param= 'T3';
+    if($topology eq '"MESH_3D"') {
+        $label= 'Routers per layer';
+        $param= 'T3';
+        $default='1';
+        $content=  '1,16,1';
+        $info= 'Number of NoC layers (Z dimension)';
+        $type= 'Spin-button'; 
+        $noc_param_comment{$param}="$info";
+        ($row,$coltmp)=add_param_widget ($mpsoc,$label,$param, $default,$type,$content,$info, $table,$row,undef,$show_noc,$noc_param,1);
+    } else {
+        $mpsoc->object_add_attribute($noc_param,'T4',1);
+        $mpsoc->object_add_attribute_order($noc_param,"T4");
+    }
+    #Topology T3/T4 parameter
+    if($topology eq '"MESH"' || $topology eq '"FMESH"' || $topology eq '"TORUS"' || $topology eq '"RING"' || $topology eq '"LINE"' || $topology eq '"MESH_3D"') {
+        $label="Router's endpoint number";
+        $param=  $topology eq '"MESH_3D"' ? 'T4' : 'T3';
         $default='1';
         $content='1,4,1';
-        $info= "In $topology topology, each router can have up to 4 endpoint processing tile.";
-        $type= 'Spin-button';             
+        $info= "Number of endpoints per router. In $topology topology, each router
+        can have up to 4 endpoint processing tile.";
+        $type= 'Spin-button'; 
+        $noc_param_comment{$param}="$info";
         ($row,$coltmp)=add_param_widget ($mpsoc,$label,$param, $default,$type,$content,$info, $table,$row,undef,$show_noc,$noc_param,1);
     }
-    
-       
-    
-    
-	}else{#its a custom Topology
-		($row,$coltmp)=config_custom_topology_gui($mpsoc,$table,$txview,$row,$noc_id);
-	}
-	return ($row,$coltmp);
-
+    }else{#its a custom Topology
+        ($row,$coltmp)=config_custom_topology_gui($mpsoc,$table,$txview,$row,$noc_id);
+    }
+    return ($row,$coltmp);
 }
 
 
-
 sub noc_config{
     my ($mpsoc,$table,$txview,$noc_id)=@_;   
     $noc_id = "" if(!defined $noc_id);    
     my $noc_param="noc_param$noc_id";
     my $noc_type="noc_type$noc_id"; 
-
     #title    
     my $row=0;
     my $title=gen_label_in_center("NoC Configuration");
     $table->attach ($title , 0, 4,  $row, $row+1,'expand','shrink',2,2); $row++;
-	add_Hsep_to_table ($table,0,4,$row); $row++;
-   
+    add_Hsep_to_table ($table,0,4,$row); $row++;
     my $label;
     my $param;
     my $default;
     my $type;
     my $content;
     my $info;
-    
-    
     #parameter start
     my $b1;
     my $show_noc=$mpsoc->object_get_attribute('setting','show_noc_setting');
     if(!defined $show_noc){
         $show_noc=1;
         $mpsoc->object_add_attribute('setting','show_noc_setting',$show_noc);
-        
     }
     if($show_noc == 0){    
         $b1= def_image_button("icons/down.png","NoC Parameters");
         $label=gen_label_in_center(' ');
         $table->attach  ( $label , 2, 3, $row,$row+1 ,'fill','shrink',2,2);
         $table->attach  ( $b1 , 0, 2, $row,$row+1,'fill','shrink',2,2);
-        $row++;    
+        $row++;
     }
-    
     my $coltmp=0;
-    
+    #NoC_ID
+    $label='NoC ID';
+    $param='NOC_ID';
+    $default='0';
+    $content='0,255,1';
+    $type='Spin-button';
+    $info="Unique identifier for the NoC. Will be modified by phy_noc_gen.pl script.";
+    $noc_param_comment{'NOC_ID'}="Unique identifier for the NoC. Will be modified by phy_noc_gen.pl script";
+    ($row,$coltmp)=add_param_widget ($mpsoc,$label,$param, $default,$type,$content,$info, $table,$row,undef,0,$noc_param,1);
     #Router type
     $label='Router Type';
     $param='ROUTER_TYPE';
@@ -649,11 +585,8 @@ sub noc_config{
     VC-based routers offer higher performance, fully adaptive routing  and traffic isolation for different packet classes."; 
     ($row,$coltmp)=add_param_widget ($mpsoc,$label,$param, $default,$type,$content,$info, $table,$row,undef,$show_noc,$noc_type,1);
     my $router_type=$mpsoc->object_get_attribute($noc_type,"ROUTER_TYPE");
-    
-    
     ($row,$coltmp) =noc_topology_setting_gui($mpsoc,$table,$txview,$row,$show_noc,$noc_id);
-     my $topology=$mpsoc->object_get_attribute($noc_param,'TOPOLOGY');  
-  
+    my $topology=$mpsoc->object_get_attribute($noc_param,'TOPOLOGY');  
     #VC number per port
     if($router_type eq '"VC_BASED"'){    
         my $v=$mpsoc->object_get_attribute($noc_param,'V');
@@ -664,39 +597,39 @@ sub noc_config{
         $type='Spin-button';
         $content='2,16,1';
         $info='Number of Virtual chanel per each router port';
+        $noc_param_comment{$param}="$info";
         ($row,$coltmp)=add_param_widget ($mpsoc,$label,$param, $default,$type,$content,$info, $table,$row,undef,$show_noc,$noc_param,1);
     } else {
+        $noc_param_comment{'V'}="Number of Virtual chanel per each router port. V is equal to 1 means there is no VC.";
         $mpsoc->object_add_attribute($noc_param,'V',1);
-        $mpsoc->object_add_attribute($noc_param,'C',0);        
+        $mpsoc->object_add_attribute($noc_param,'C',0);
     }
     
     #buffer width per VC
     $label=($router_type eq '"VC_BASED"')? 'Buffer flits per VC': "Buffer flits";
     $param='B';
-    $default='4';                                  
+    $default='4';
     $content='2,256,1';
     $type='Spin-button';
     $info=($router_type eq '"VC_BASED"')?  'Buffer queue size per VC in flits' : 'Buffer queue size in flits';
+    $noc_param_comment{$param}="$info";
     ($row,$coltmp)=add_param_widget ($mpsoc,$label,$param, $default,$type,$content,$info, $table,$row,undef,$show_noc,$noc_param,undef);
-    
-    
     #Local port buffer width per VC
     $label=($router_type eq '"VC_BASED"')? 'Local port Buffer flits per VC': "Local Port Buffer flits";
     $param='LB';
-    $default='4';                                  
+    $default='4';
     $content='2,256,1';
     $type='Spin-button';
-    $info = "The Local router ports buffer width (LB) is the width of the ports connected to the endpoints and can take different buffer sizes than other routers ports buffer width (B) connected to neighboring routers .It is valid only for MESH,FMESH, TORUS,LINE and RING topologies. In FMESH topology, this parameter does not affect the  width of extra endpoints connected to edge routers.";
-    
+    $info = "Buffer width for local router ports connected to endpoints. 
+    May differ from B, which is for neighboring router ports. 
+    Applicable to MESH, FMESH, TORUS, LINE, and RING topologies. 
+    In FMESH, LB does not affect extra endpoints on edge routers.";
+    $noc_param_comment{$param}="$info";
     if ($topology eq '"MESH"' || $topology eq '"FMESH"' || $topology eq '"TORUS"' || $topology eq '"RING"' || $topology eq '"LINE"'){
-   		($row,$coltmp)=add_param_widget ($mpsoc,$label,$param, $default,$type,$content,$info, $table,$row,undef,$show_noc,$noc_param,undef);
+        ($row,$coltmp)=add_param_widget ($mpsoc,$label,$param, $default,$type,$content,$info, $table,$row,undef,$show_noc,$noc_param,undef);
     }else{
-    	$mpsoc->object_add_attribute($noc_param,'LB','B');
-    }
-    
-    
-    
-    
+        $mpsoc->object_add_attribute($noc_param,'LB','B');
+    }    
     #packet payload width
     $label='Payload width';
     $param='Fpay';
@@ -704,164 +637,182 @@ sub noc_config{
     $content='32,256,32';
     $type='Spin-button';
     $info="The packet payload width in bits"; 
+    $noc_param_comment{$param}="$info";
     ($row,$coltmp)=add_param_widget ($mpsoc,$label,$param, $default,$type,$content,$info,$table,$row,undef,$show_noc,$noc_param,undef);
-
-if($topology ne '"CUSTOM"' ){
-    #routing algorithm
-    $label='Routing Algorithm';
-    $param="ROUTE_NAME";
-    $type="Combo-box";
-    if($router_type eq '"VC_BASED"'){
-        $content=($topology eq '"MESH"' || $topology eq '"FMESH"')?  '"XY","WEST_FIRST","NORTH_LAST","NEGETIVE_FIRST","ODD_EVEN","DUATO"' :
-                 ($topology eq '"TORUS"')? '"TRANC_XY","TRANC_WEST_FIRST","TRANC_NORTH_LAST","TRANC_NEGETIVE_FIRST","TRANC_DUATO"':
-                 ($topology eq '"RING"')? '"TRANC_XY"' :
-                 ($topology eq '"LINE"')?  '"XY"':
-                 ($topology eq '"FATTREE"')? '"NCA_RND_UP","NCA_STRAIGHT_UP","NCA_DST_UP"':
-                 ($topology eq '"TREE"')? '"NCA"' : '"UNKNOWN"';   
-    }else{
-        $content=($topology eq '"MESH"' || $topology eq '"FMESH"')?  '"XY","WEST_FIRST","NORTH_LAST","NEGETIVE_FIRST","ODD_EVEN"' :
-                 ($topology eq '"TORUS"')? '"TRANC_XY","TRANC_WEST_FIRST","TRANC_NORTH_LAST","TRANC_NEGETIVE_FIRST"':
-                 ($topology eq '"RING"')? '"TRANC_XY"' : 
-				 ($topology eq '"LINE"')?  '"XY"':
-                 ($topology eq '"FATTREE"')? '"NCA_RND_UP","NCA_STRAIGHT_UP","NCA_DST_UP"' : 
-				 ($topology eq '"TREE"')? '"NCA"' : '"UNKNOWN"';    
-        
-    }
-    $default=($topology eq '"MESH"' || $topology eq '"FMESH"' || $topology eq '"LINE"' )? '"XY"':
-    		 ($topology eq '"TORUS"'|| $topology eq '"RING"')?  '"TRANC_XY"' : 
-    		 ($topology eq '"FATTREE"')? '"NCA_STRAIGHT_UP"' :
-    		 ($topology eq '"TREE"')? '"NCA"' : '"UNKNOWN"';
-    		 
-    my $info_mesh="Select the routing algorithm: XY(DoR) , partially adaptive (Turn models). Fully adaptive (Duato) "; 
-    my $info_fat="Nearest common ancestor (NCA) where the up port is selected randomly (RND), based on destination endpoint address (DST) or it is the top port that is located in front of the port which has received the packet (STRAIGHT) "; 
     
-    $info=($topology eq '"FATTREE"')? $info_fat : 
-    	  ($topology eq '"TREE"') ? "Nearest common ancestor": $info_mesh;
+    if($topology ne '"CUSTOM"' ){
+        #routing algorithm
+        $label='Routing Algorithm';
+        $param="ROUTE_NAME";
+        $type="Combo-box";
+        if($router_type eq '"VC_BASED"'){
+            $content=
+                ($topology eq '"MESH_3D"') ? '"DOR"' :
+                ($topology eq '"MESH"' || $topology eq '"FMESH"')?  '"DOR","WEST_FIRST","NORTH_LAST","NEGETIVE_FIRST","ODD_EVEN","FULL_ADPT"' :
+                ($topology eq '"TORUS"')? '"TRANC_DOR","TRANC_WEST_FIRST","TRANC_NORTH_LAST","TRANC_NEGETIVE_FIRST","TRANC_FULL_ADPT"':
+                ($topology eq '"RING"')? '"TRANC_DOR"' :
+                ($topology eq '"LINE"')?  '"DOR"':
+                ($topology eq '"FATTREE"')? '"NCA_RND_UP","NCA_STRAIGHT_UP","NCA_DST_UP"':
+                ($topology eq '"TREE"')? '"NCA"' : '"UNKNOWN"';
+        }else{
+            $content=
+                ($topology eq '"MESH_3D"') ? '"DOR"' :
+                ($topology eq '"MESH"' || $topology eq '"FMESH"')?  '"DOR","WEST_FIRST","NORTH_LAST","NEGETIVE_FIRST","ODD_EVEN"' :
+                ($topology eq '"TORUS"')? '"TRANC_DOR","TRANC_WEST_FIRST","TRANC_NORTH_LAST","TRANC_NEGETIVE_FIRST"':
+                ($topology eq '"RING"')? '"TRANC_DOR"' : 
+                ($topology eq '"LINE"')?  '"DOR"':
+                ($topology eq '"FATTREE"')? '"NCA_RND_UP","NCA_STRAIGHT_UP","NCA_DST_UP"' : 
+                ($topology eq '"TREE"')? '"NCA"' : '"UNKNOWN"';
+        }
+        $default=
+            ($topology eq '"MESH"' || $topology eq '"FMESH"' || $topology eq '"LINE"'|| $topology eq '"MESH_3D"' )? '"DOR"':
+            ($topology eq '"TORUS"'|| $topology eq '"RING"')?  '"TRANC_DOR"' : 
+            ($topology eq '"FATTREE"')? '"NCA_STRAIGHT_UP"' :
+            ($topology eq '"TREE"')? '"NCA"' : '"UNKNOWN"';
+    my $info_mesh="Select the routing algorithm. Options are: 
+    - DOR: Dimension-Order Deterministic routing (XY).
+    - WEST_FIRST, NORTH_LAST, NEGATIVE_FIRST, ODD_EVEN:  Partially adaptive routing algorithms based on turn model restrictions.
+    - FULL_ADPT:  Fully adaptive routing based on Duato's algorithm; requires at least two virtual channels (VCs) per port.";
+    my $info_fat="Nearest common ancestor (NCA) where the up port is selected randomly (RND), 
+    based on destination endpoint address (DST) or it is the top port that is located in front 
+    of the port which has received the packet (STRAIGHT) "; 
+    $info=
+        ($topology eq '"FATTREE"')? $info_fat : 
+        ($topology eq '"TREE"') ? "Nearest common ancestor": $info_mesh;
+    $noc_param_comment{$param}="$info
+    options are $content";
     my $show_routing =($topology eq '"STAR"' )? 0 : $show_noc;
     ($row,$coltmp)=add_param_widget ($mpsoc,$label,$param, $default,$type,$content,$info, $table,$row,undef,$show_routing,$noc_param,1);
-
+    #routing_mode
+    $label='Routing Mode';
+    $param="ROUTE_MODE";
+    $type="Combo-box";
+    $content='"LOOKAHEAD","CONVENTIONAL"';
+    $default='"LOOKAHEAD"';
+    $info = "Select the routing algorithm mode:
+    -CONVENTIONAL: 
+        The destination output port is computed 
+        in the same cycle, prior to VC/SW allocation.
+    -LOOKAHEAD: 
+        The routing decision is performed one router
+        ahead, in parallel with VC/SW allocation.";
+    $noc_param_comment{$param}="$info";
+    ($row,$coltmp)=add_param_widget ($mpsoc,$label,$param, $default,$type,$content,$info, $table,$row,undef,1,$noc_param,1);
 }
-
-	#PCK_TYPE
-	$label='Packet type'; 
+    #PCK_TYPE
+    $label='Packet type'; 
     $param='PCK_TYPE';
     $default='"MULTI_FLIT"';
     $content='"MULTI_FLIT","SINGLE_FLIT"';
     $type="Combo-box";
-    $info="Define packet type: SINGLE_FLIT: all packets send to NoC are single-flit sized. 
-    Multi-flit: packets can be consists of one or several flits. A multi-flit packet can be 
-    	a)single-flit sized : both headr and tail flag must be asserted for this flit, 
-    	b)two-flit sized: a header flit and a tail flit, or 
-    	c)more than 2 fits: start with a headr flit, continued with one or more body flits and end up with a tail flit
-    	For MULTI-FLIT packet you need to defin ethe minum size of a paket that can be injecte to the NoC.
-    ";
-     
+    $info="Packet type.
+    - SINGLE_FLIT: All packets are single-flit sized.
+    - MULTI_FLIT: Packets can be single-flit, two-flit, or multi-flit sized:
+        a) Single-flit: Head and tail flags set on one flit.
+        b) Two-flit: Separate header and tail flits.
+        c) Multi-flit: Header, one or more body flits, and a tail flit.";
+    $noc_param_comment{$param}="$info";
     ($row,$coltmp)=add_param_widget ($mpsoc,$label,$param, $default,$type,$content,$info, $table,$row,undef,$show_noc,$noc_param,1);
-	
-	 my $pck_type=$mpsoc->object_get_attribute($noc_param,'PCK_TYPE');  
-  
-	if($pck_type eq '"MULTI_FLIT"'){
-
-		#MIN_PCK_SIZE 
-		# 2 //minimum packet size in flits. The minimum value is 1. 
-		$label='Minimum packet size'; 
-	    $param='MIN_PCK_SIZE';
-	    $default='2';
-	    $content='1,65535,1';
-	    $type='Spin-button';
-	    $info="The minimum packet size in flits. In atomic VC re-allocation, it is just important to define if the single-flit sized packets are allowed to be injected to the NoC by defining this parameter value as one.  Setting any larger value than one results in the same architecture and the NoC works correctly even if it receives smaller packets size as while as they are not single flit -sized packets.  However, for non-atomic VC reallocation NoCs, you have to define the exact value as it defines the NoC control registers' internal buffers. The NoC may crash once it receives  packets having smaler size than the defined  minimum packet size."; 
-	    ($row,$coltmp)=add_param_widget ($mpsoc,$label,$param, $default,$type,$content,$info, $table,$row,undef,$show_noc,$noc_param,undef);
-	}else{
-		 $mpsoc->object_add_attribute($noc_param,'MIN_PCK_SIZE',1);   
-	}
-
+    my $pck_type=$mpsoc->object_get_attribute($noc_param,'PCK_TYPE');  
+    if($pck_type eq '"MULTI_FLIT"'){
+        #MIN_PCK_SIZE 
+        # 2 //minimum packet size in flits. The minimum value is 1. 
+        $label='Minimum packet size'; 
+        $param='MIN_PCK_SIZE';
+        $default='2';
+        $content='1,65535,1';
+        $type='Spin-button';
+        $info="Minimum packet size in flits.
+    - For atomic VC reallocation, any value ≥1 is valid.
+    - For non-atomic VC reallocation, this value defines buffer behavior.
+    Note: Setting a value smaller than received packet size may cause crashes."; 
+        $noc_param_comment{$param}="$info";
+        ($row,$coltmp)=add_param_widget ($mpsoc,$label,$param, $default,$type,$content,$info, $table,$row,undef,$show_noc,$noc_param,undef);
+    }else{
+        $mpsoc->object_add_attribute($noc_param,'MIN_PCK_SIZE',1);   
+    }
     # BYTE_EN
     $label='Byte Enable';
     $param='BYTE_EN';
     $default= 0;
-    $info='0:disable, 1: enable. Add byte enable (BE) filed to header flit which shows the location of last valid byte in tail flit. It is needed once the send data unit is smaller than Fpay.'; 
+    $info='0 - Disable, 1 - Enable. 
+    Adds a Byte Enable (BE) field to the header flit, indicating the location of 
+    the last valid byte in the tail flit. This is required when the data unit being 
+    sent is smaller than the Fpay value.'; 
     $content='0,1';
     $type="Combo-box";
+    $noc_param_comment{$param}="$info";
     ($row,$coltmp)=add_param_widget ($mpsoc,$label,$param, $default,$type,$content,$info, $table,$row,undef,$show_noc,$noc_param);
-    
-    
-  
-    
-    
     #CAST_TYPE
     $label='Casting Type';
     $param='CAST_TYPE';
     $default= '"UNICAST"';
-    $info='Configure a NoC as Unicast, Multicast, or Broadcast NoC. In Unicast NoC, a packet can be sent to only one destination. In  Multicast, a single packet can have multiple target destination nodes, whereas,  Broadcast packets are sent to all other destination nodes. For Multicast and Broadcast NoC, only one copy of a packet must be injected into the source router. The routers in the path then fork the packets to different output ports when necessary. Multicast and Broadcast can be selected as FULL, where all destinations can be included in packet destination list, or as PARTIAL where a user-defined subset of nodes (defined with MCAST_ENDP_LIST parameter) can be targeted in destination lists. The other nodes not marked in MCAST_ENDP_LIST can only receive unicast packets. '; 
     $content='"UNICAST","MULTICAST_PARTIAL","MULTICAST_FULL","BROADCAST_PARTIAL","BROADCAST_FULL"';
+    $info="Specifies NoC communication type.
+    - UNICAST: A packet targets a single destination.
+    - MULTICAST/BROADCAST: A single packet targets multiple/all destinations.
+    Options: FULL (all nodes) or PARTIAL (defined by MCAST_ENDP_LIST).
+    Select one of $content"; 
+    
     $type="Combo-box";
+    $noc_param_comment{$param}="$info";
     ($row,$coltmp)=add_param_widget ($mpsoc,$label,$param, $default,$type,$content,$info, $table,$row,undef,$show_noc,$noc_param,1);
     
-   
     my $cast_type=$mpsoc->object_get_attribute($noc_param,'CAST_TYPE');  
-    my ($NE, $NR, $RAw, $EAw, $Fw) = get_topology_info($mpsoc,$noc_id);
+    my ($NE, $NR, $RAw, $EAw, $Fw, $MAX_P) = get_topology_info($mpsoc,$noc_id);
     
-    my $cast = $mpsoc->object_get_attribute($noc_param,"MCAST_ENDP_LIST");	
+    my $cast = $mpsoc->object_get_attribute($noc_param,"MCAST_ENDP_LIST");    
     if(!defined $cast){
-	    my $h=0;
-	    my $n="";
-	    for (my $i=0; $i<$NE; $i++){
-			$h+= (1<<$i%4); 	
-			if(($i+1) % 4==0){
-				$n="$h".$n if($h<10);
-				$n=chr($h-10+97).$n if($h>9);
-				$h=0;
-			}
-		}	
-		$n="$h".$n if($h!=0);
-		$n="'h".$n;  
-		$mpsoc->object_add_attribute($noc_param,"MCAST_ENDP_LIST",$n);
-		$mpsoc->object_add_attribute_order($noc_param,"MCAST_ENDP_LIST");
-	#	$mpsoc->object_add_attribute($noc_param,"MCAST_PRTLw",$NE);
-	#	$mpsoc->object_add_attribute_order($noc_param,"MCAST_PRTLw");
-		$cast=$n;
+        my $h=0;
+        my $n="";
+        for (my $i=0; $i<$NE; $i++){
+            $h+= (1<<$i%4);     
+            if(($i+1) % 4==0){
+                $n="$h".$n if($h<10);
+                $n=chr($h-10+97).$n if($h>9);
+                $h=0;
+            }
+        }    
+        $n="$h".$n if($h!=0);
+        $n="'h".$n;  
+        $mpsoc->object_add_attribute($noc_param,"MCAST_ENDP_LIST",$n);
+        $mpsoc->object_add_attribute_order($noc_param,"MCAST_ENDP_LIST");
+    #    $mpsoc->object_add_attribute($noc_param,"MCAST_PRTLw",$NE);
+    #    $mpsoc->object_add_attribute_order($noc_param,"MCAST_PRTLw");
+        $cast=$n;
     }
     
     if($cast_type eq '"MULTICAST_PARTIAL"' || $cast_type eq '"BROADCAST_PARTIAL"') {
-    	#$table->attach  ( gen_label_help($info,"Muticast Node list"),0 , 2, $row,$row+1,'fill','shrink',2,2);    
-    	$info='MCAST_ENDP_LIST is a one-hot coded number where the asserted bit indicates that the corresponding destination ID can be targeted in multicast/broadcast packets. The corresponding destinations with zero bit can only receive unicast packets.'; 
-  
-    	my $b1= def_image_button("icons/setting.png","Set");
-    	my $bb= def_pack_hbox(FALSE,0,gen_label_in_left("$cast"),$b1);
-    	my $label=gen_label_in_left("Muticast Node list");
-    	my $inf_bt= (defined $info)? gen_button_message ($info,"icons/help.png"):gen_label_in_left(" ");
-		attach_widget_to_table ($table,$row,$label,$inf_bt,$bb,0);
-    	
-    	
-       # $table->attach  ( $bb , 2, 3, $row,$row+1,'fill','shrink',2,2);
+        #$table->attach  ( gen_label_help($info,"Muticast Node list"),0 , 2, $row,$row+1,'fill','shrink',2,2);    
+        $info='A one-hot encoded value where each asserted bit indicates that the corresponding destination ID 
+    can be targeted in multicast or broadcast packets. Destinations represented by bits set to zero are restricted 
+    to receiving only unicast packets.'; 
+        $noc_param_comment{$param}="$info";
+        my $b1= def_image_button("icons/setting.png","Set");
+        my $bb= def_pack_hbox(FALSE,0,gen_label_in_left("$cast"),$b1);
+        my $label=gen_label_in_left("Muticast Node list");
+        my $inf_bt= (defined $info)? gen_button_message ($info,"icons/help.png"):gen_label_in_left(" ");
+        attach_widget_to_table ($table,$row,$label,$inf_bt,$bb,0);
+        
+        
+        # $table->attach  ( $bb , 2, 3, $row,$row+1,'fill','shrink',2,2);
         $row++;  
         
-         $b1->signal_connect("clicked" => sub{ 
-      		set_multicast_list($mpsoc,$noc_id);
-   		
-   		 });    	
-    }
-    
-    
-    
-    #advance parameter start
-   # my $advc;
-   # my $adv_set=$mpsoc->object_get_attribute('setting','show_adv_setting');
-   #
-   # if($adv_set == 0){    
-   #     $advc= def_image_button("icons/down.png","Advance Parameters");
-   #     $table->attach ( $advc , 0, 2, $row,$row+1,'fill','shrink',2,2);
-   #     $row++;    
-   # }
+        $b1->signal_connect("clicked" => sub{ 
+            set_multicast_list($mpsoc,$noc_id);        
+        });        
+    }    
     
     my $adv_set= $show_noc;
     #SSA
     $label='SSA Enable'; 
     $param='SSA_EN';
-    $default='"NO"';
-    $content='"YES","NO"';
+    $default='0';
+    $content='0,1';
     $type='Combo-box';
-    $info="Enable single cycle latency on packets traversing in the same direction using static straight allocator (SSA)"; 
+    $info="Enable single cycle latency on packets traversing in the same direction using 
+    static straight allocator (SSA)"; 
+    $noc_param_comment{$param}="$info";
     ($row,$coltmp)=add_param_widget ($mpsoc,$label,$param, $default,$type,$content,$info, $table,$row,undef,$adv_set,$noc_param,undef);
     
     #SMART
@@ -870,28 +821,30 @@ sub noc_config{
     $default='0';
     $content="0,1,2,3,4,5,6,7,8,9";
     $type='Combo-box';
-    $info="If Max Straight Bypass (SMART_MAX) is defined as n>0 then packets are allowed to bypass Maximum of n routers in Straight direction in single cycle."; 
+    $info="Maximum number of routers a packet can bypass in a straight direction
+    in a single cycle (0 = no bypass)"; 
+    $noc_param_comment{$param}="$info";
     ($row,$coltmp)=add_param_widget ($mpsoc,$label,$param, $default,$type,$content,$info, $table,$row,undef,$adv_set,$noc_param,undef);
-   
-    
-    
+
     #Fully and partially adaptive routing setting
     my $route=$mpsoc->object_get_attribute($noc_param,"ROUTE_NAME");
     $label="Congestion index";    
     $param="CONGESTION_INDEX";
     $type="Spin-button";
     $content="0,12,1";
-    $info="Congestion index determines how congestion information is collected from neighboring routers. Please refer to the usere manual for more information";
+    $info="Congestion index determines how congestion information is collected 
+    from neighboring routers. Please refer to the usere manual for more information";
+    $noc_param_comment{$param}="$info";
     $default=3;
-    if($topology ne '"CUSTOM"' && $route ne '"XY"' && $route ne '"TRANC_XY"' ){
-           ($row,$coltmp)=add_param_widget ($mpsoc,$label,$param, $default,$type,$content,$info, $table,$row,undef,$adv_set,$noc_param,undef);
+    if($topology ne '"CUSTOM"' && $route ne '"DOR"' && $route ne '"TRANC_DOR"' ){
+        ($row,$coltmp)=add_param_widget ($mpsoc,$label,$param, $default,$type,$content,$info, $table,$row,undef,$adv_set,$noc_param,undef);
     } else {
         ($row,$coltmp)=add_param_widget ($mpsoc,$label,$param, $default,$type,$content,$info, $table,$row,undef,0,$noc_param,undef);
     }
     
     #Fully adaptive routing setting
     my $v=$mpsoc->object_get_attribute($noc_param,"V");
-    $label="Select Escap VC";    
+    $label="Select Escap VC";
     $param="ESCAP_VC_MASK";
     $type="Check-box";
     $content=$v;
@@ -899,34 +852,40 @@ sub noc_config{
     for (my $i=1; $i<=$v-1; $i++){$default=  "${default}0";}
     $default=  "${default}1";
     $info="Select the escap VC for fully adaptive routing.";
-    if( $route eq '"TRANC_DUATO"' or $route eq '"DUATO"'  ){
-           ($row,$coltmp)=add_param_widget ($mpsoc,$label,$param, $default,$type,$content,$info, $table,$row,undef,$adv_set, $noc_param,undef);
-     }
+    $noc_param_comment{$param}="$info";
+    if( $route eq '"TRANC_FULL_ADPT"' or $route eq '"FULL_ADPT"'  ){
+        ($row,$coltmp)=add_param_widget ($mpsoc,$label,$param, $default,$type,$content,$info, $table,$row,undef,$adv_set, $noc_param,undef);
+    }
     else{
-         ($row,$coltmp)=add_param_widget ($mpsoc,$label,$param, $default,$type,$content,$info, $table,$row,undef,0, $noc_param,undef);
+        ($row,$coltmp)=add_param_widget ($mpsoc,$label,$param, $default,$type,$content,$info, $table,$row,undef,0, $noc_param,undef);
     }
         
     # VC reallocation type
     $label=($router_type eq '"VC_BASED"')? 'VC reallocation type': 'Queue reallocation type';    
     $param='VC_REALLOCATION_TYPE';
-    $info="VC reallocation type: If set as atomic only empty VCs can be allocated for new packets. Whereas, in non-atomic a non-empty VC which has received the last packet tail flit can accept a new  packet"; 
+    $info="VC reallocation policy.
+    - ATOMIC: Only empty VCs can be reallocated.
+    - NONATOMIC: Non-empty VCs with completed packets can accept new packets.";
     $default='"NONATOMIC"';  
     $content='"ATOMIC","NONATOMIC"';
     $type='Combo-box';
+    $noc_param_comment{$param}="$info";
     ($row,$coltmp)=add_param_widget ($mpsoc,$label,$param, $default,$type,$content,$info, $table,$row,undef,$adv_set,$noc_param,undef);                                           
-
-
     #vc/sw allocator type
     $label = 'VC/SW combination type';
     $param='COMBINATION_TYPE';
     $default='"COMB_NONSPEC"';
-    $content='"BASELINE","COMB_SPEC1","COMB_SPEC2","COMB_NONSPEC"';
+    $content='"COMB_SPEC1","COMB_SPEC2","COMB_NONSPEC"';
     $type='Combo-box';
-    $info="The joint VC/ switch allocator type. using canonical combination is not recommended";   
+    $info="Specifies the joint VC/Switch allocator type as either speculative or non-speculative. 
+Options are: 
+    - SPEC: Speculative allocation.
+    - NONSPEC: Non-speculative allocation.";   
+    $noc_param_comment{$param}="$info";
     if ($router_type eq '"VC_BASED"'){                 
         ($row,$coltmp)=add_param_widget ($mpsoc,$label,$param, $default,$type,$content,$info, $table,$row,undef,$adv_set,$noc_param,undef);                   
     } else{
-         ($row,$coltmp)=add_param_widget ($mpsoc,$label,$param, $default,$type,$content,$info, $table,$row,undef,0,$noc_param,undef);  
+        ($row,$coltmp)=add_param_widget ($mpsoc,$label,$param, $default,$type,$content,$info, $table,$row,undef,0,$noc_param,undef);  
     }
     
     # Crossbar mux type 
@@ -936,6 +895,7 @@ sub noc_config{
     $content='"ONE_HOT","BINARY"';
     $type='Combo-box';
     $info="Crossbar multiplexer type";
+    $noc_param_comment{$param}="$info";
     ($row,$coltmp)=add_param_widget ($mpsoc,$label,$param, $default,$type,$content,$info, $table,$row,undef,$adv_set,$noc_param,undef);             
     
     #class   
@@ -947,8 +907,6 @@ sub noc_config{
         $content='0,16,1';
         $type='Spin-button';
         ($row,$coltmp)=add_param_widget ($mpsoc,$label,$param, $default,$type,$content,$info, $table,$row,undef,$adv_set,$noc_param,5);                             
-        
-
         my $class=$mpsoc->object_get_attribute($noc_param,"C");
         my $v=$mpsoc->object_get_attribute($noc_param,"V");
         $default= "$v\'b";
@@ -957,19 +915,15 @@ sub noc_config{
         }    
         #print "\$default=$default\n";
         for (my $i=0; $i<=$class-1; $i++){
-            
-             $label="Class $i Permitted VCs";    
-               $param="Cn_$i";
-               $type="Check-box";
-               $content=$v;
-               $info="Select the permitted VCs which the message class $i can be sent via them.";
-               ($row,$coltmp)=add_param_widget ($mpsoc,$label,$param, $default,$type,$content,$info, $table,$row,undef,$adv_set,'class_param',undef);
+        
+            $label="Class $i Permitted VCs";    
+            $param="Cn_$i";
+            $type="Check-box";
+            $content=$v;
+            $info="Select the permitted VCs which the message class $i can be sent via them.";
+            ($row,$coltmp)=add_param_widget ($mpsoc,$label,$param, $default,$type,$content,$info, $table,$row,undef,$adv_set,'class_param',undef);
         }
-    
     }#($router_type eq '"VC_BASED"')
-     
-     
-
     #simulation debuge enable     
     $label='Debug enable';
     $param='DEBUG_EN';
@@ -977,8 +931,8 @@ sub noc_config{
     $default='0';
     $content='0,1';
     $type='Combo-box';
+    $noc_param_comment{$param}="$info";
     ($row,$coltmp)=add_param_widget ($mpsoc,$label,$param, $default,$type,$content,$info, $table,$row,undef,$adv_set,$noc_param);  
-
     
     #pipeline reg    
     $label="Add pipeline reg after crossbar";    
@@ -987,44 +941,34 @@ sub noc_config{
     $content=1;
     $default="1\'b0";
     $info="If is enabled it adds a pipeline register at the output port of the router.";
+    $noc_param_comment{$param}="$info";
     ($row,$coltmp)=add_param_widget ($mpsoc,$label,$param, $default,$type,$content,$info, $table,$row,undef,$adv_set,$noc_param);
-    
-    
-    #MAX_SMART_NUM = 4 // 
-    $label="Number of multiple router bypassing ";    
-    $param="MAX_SMART_NUM ";
-    $type='Spin-button';
-    $content='0,1,1';
-    $default=0;
-    $info="maximum number of routers which a packet can by pass during one clock cycle. Define it as zero will disable bypassing.";
-    #($row,$coltmp)=add_param_widget ($mpsoc,$label,$param, $default,$type,$content,$info, $table,$row,$adv_set,$noc_param);
-    
-     
+
     #FIRST_ARBITER_EXT_P_EN
     $label='Swich allocator first level 
 arbiters external priority enable';
     $param='FIRST_ARBITER_EXT_P_EN';
     $default= 1;
-    $info='If set as 1 then the switch allocator\'s input (first) arbiters\' priority registers are enabled only when a request get both input and output arbiters\' grants'; 
+    $info='Enables switch allocator\'s input priority registers 
+    only when a request gets grants from both input and output arbiters.'; 
     $content='0,1';
     $type="Combo-box";
+    $noc_param_comment{$param}="$info";
     ($row,$coltmp)=add_param_widget ($mpsoc,$label,$param, $default,$type,$content,$info,$table,$row,undef,$adv_set,$noc_param);     
-          
     
     #Arbiter type
     $label='SW allocator arbitration type'; 
     $param='SWA_ARBITER_TYPE';
     $default='"RRA"';
-    $content='"RRA","WRRA"'; #,"WRRA_CLASSIC"';
+    $content='"RRA","WRRA"'; 
     $type='Combo-box';
-    $info="Switch allocator arbiter type: 
-    RRA: Round robin arbiter. Only local fairness in a router. 
-    WRRA: Weighted round robin arbiter. Results in global fairness in the NoC. 
-          Switch allocation requests are grated according to their weight which increases due to contention"; 
+    $info="Switch allocator arbitration type.
+    - RRA: Round Robin Arbiter (local fairness only).
+    - WRRA: Weighted Round Robin Arbiter (global fairness based on contention).
+"; 
+    $noc_param_comment{$param}="$info";
     ($row,$coltmp)=add_param_widget ($mpsoc,$label,$param, $default,$type,$content,$info, $table,$row,undef,$adv_set,$noc_param,1);
     
-          
-    
     my $arbiter=$mpsoc->object_get_attribute($noc_param,"SWA_ARBITER_TYPE");
     my $wrra_show = ($arbiter ne  '"RRA"' && $adv_set == 1 )? 1 : 0;
     # weight width
@@ -1033,21 +977,19 @@ sub noc_config{
     $default='4';
     $content='2,7,1';
     $info= 'Maximum weight width';
+    $noc_param_comment{$param}="$info";
     $type= 'Spin-button';  
     ($row,$coltmp)=add_param_widget ($mpsoc,$label,$param, $default,$type,$content,$info, $table,$row,undef,$wrra_show,$noc_param,undef);  
-    
-    
-    
     $label='Self loop enable'; 
     $param='SELF_LOOP_EN';
-    $default='"NO"';
-    $content='"NO","YES"';
+    $default='0';
+    $content='0,1';
     $type='Combo-box';
-    $info="If the self loop is enabled, it allows a router input port sends packet to its own output port. Enabling it allows a tile to be able to sent packet to itself too."; 
+    $info="Allows a router input port to send packets to its own output port, 
+    enabling self-communication for tiles."; 
+    $noc_param_comment{$param}="$info";
     ($row,$coltmp)=add_param_widget ($mpsoc,$label,$param, $default,$type,$content,$info, $table,$row,undef,$adv_set,$noc_param,1);
     
-    
-    
     #WRRA_CONFIG_INDEX
     $label='Weight configuration index';
     $param='WRRA_CONFIG_INDEX';
@@ -1059,7 +1001,55 @@ sub noc_config{
     $type= 'Spin-button';  
     #($row,$coltmp)=add_param_widget ($mpsoc,$label,$param, $default,$type,$content,$info, $table,$row,$wrra_show,$noc_param,undef);  
     
-    
+    #HETERO_VC
+    $label='Heterogeneous VC En'; 
+    $param='HETERO_VC';
+    $default='0';
+    $content='0,1,2';
+    $type='Combo-box';
+    $info="Configures the VC (Virtual Channel) distribution across routers and ports in the NoC.
+    0 : Uniform VC distribution. All routers in the NoC have an equal number of VCs.
+    1 : Router-specific VC distribution. All ports in a specific router have the same number of VCs, 
+    but different routers in the NoC can have different numbers of VCs.
+    2 : Fully heterogeneous VC distribution. Each port in any router can have a unique number of VCs."; 
+    $noc_param_comment{$param}="$info";
+    ($row,$coltmp)=add_param_widget ($mpsoc,$label,$param, $default,$type,$content,$info, $table,$row,undef,$adv_set,$noc_param,1);
+    $noc_param_comment{$param}="$info";
+    
+    #VC_CONFIG_TABLE
+    my $hetero_en=$mpsoc->object_get_attribute($noc_param,'HETERO_VC');
+    $label='Heterogeneous VC setting'; 
+    $param='int VC_CONFIG_TABLE [MAX_ROUTER][MAX_PORT]';
+    $default='\'{\'{0}}';
+    $content='0,1,2';
+    $type='Combo-box';
+    $info='Defines how a heterogeneous number of VCs are distributed in the NoC.
+    - HETERO_VC= 0: Uniform VC configuration. All routers and ports have 
+        the same number of VCs, and this parameter is not used.
+    - HETERO_VC= 1,2 : Specifies the VC count in a 2D parameter array, where:
+        * The first dimension represents the router ID.
+        * The second dimension represents the port number.
+    - For HETERO_VC = 1: All ports within a router have the same number of VCs, 
+        so only the first element of each row is considered valid.
+    - For HETERO_VC = 2: Each port in every router can have a unique VC count.';
+    $noc_param_comment{$param}="$info";
+    if($hetero_en eq '0'){
+        $mpsoc->object_add_attribute($noc_param,"MAX_ROUTER",1);
+        $mpsoc->object_add_attribute($noc_param,"MAX_PORT",1);
+        $mpsoc->object_add_attribute($noc_param,$param,$default);
+        
+    }elsif($hetero_en eq '1'){
+        $mpsoc->object_add_attribute($noc_param,"MAX_ROUTER",$NR);
+        $mpsoc->object_add_attribute($noc_param,"MAX_PORT",1);        
+        $row=hetero_vc_widget($mpsoc,$row,$NR,1,$label,$info,$table,$noc_id,$param,$v);
+    }else{
+        $mpsoc->object_add_attribute($noc_param,"MAX_ROUTER",$NR);
+        $mpsoc->object_add_attribute($noc_param,"MAX_PORT",$MAX_P);
+        $row=hetero_vc_widget($mpsoc,$row,$NR,$MAX_P,$label,$info,$table,$noc_id,$param,$v);
+    }
+    $mpsoc->object_add_attribute_order($noc_param,"MAX_ROUTER");
+    $mpsoc->object_add_attribute_order($noc_param,"MAX_PORT");
+    $mpsoc->object_add_attribute_order($noc_param,$param);
     if($show_noc == 1){    
         $b1= def_image_button("icons/up.png","NoC Parameters");
         $table->attach  ( $b1 , 0, 2, $row,$row+1,'fill','shrink',2,2);
@@ -1070,25 +1060,7 @@ sub noc_config{
         $mpsoc->object_add_attribute('setting','show_noc_setting',$show_noc);
         set_gui_status($mpsoc,"ref",1);
     });
-    
-    
-    
-    
-  #  if($adv_set == 1){    
-  #      $advc= def_image_button("icons/up.png","Advance Parameters");
-  #      $table->attach ( $advc , 0, 2, $row,$row+1,'fill','shrink',2,2);
-  #      $row++;
-  #  }
-  #  $advc->signal_connect("clicked" => sub{ 
-  #      $adv_set=($adv_set==1)?0:1;
-  #      $mpsoc->object_add_attribute('setting','show_adv_setting',$adv_set);
-   #     set_gui_status($mpsoc,"ref",1);
-  #  });
-    
-    
     #other fixed parameters       
-       
-    
     # AVC_ATOMIC_EN
     $label='AVC_ATOMIC_EN';
     $param='AVC_ATOMIC_EN';
@@ -1096,238 +1068,270 @@ sub noc_config{
     $info='AVC_ATOMIC_EN'; 
     $content='0,1';
     $type="Combo-box";
+    $noc_param_comment{$param}="$info";
     ($row,$coltmp)=add_param_widget ($mpsoc,$label,$param, $default,$type,$content,$info, $table,$row,undef,0,$noc_param);
-    
-    
-    #ROUTE_SUBFUNC
-    #$label='ROUTE_SUBFUNC';
-    #$param='ROUTE_SUBFUNC';
-    #$default= '"XY"';
-    #$info='ROUTE_SUBFUNC'; 
-    #$content='"XY"';
-    #$type="Combo-box";
-    #($row,$coltmp)=add_param_widget ($mpsoc,$label,$param, $default,$type,$content,$info, $table,$row,undef,0,$noc_param);
-    
+    $mpsoc->object_add_attribute('noc_param_comments',undef,\%noc_param_comment);
     return $row;
 }
 
+sub hetero_vc_widget{
+    my ($mpsoc,$row,$nr,$np,$label_text,$info,$table,$noc_id,$param,$v)=@_;
+    my $b1= def_image_button("icons/setting.png","Set");
+    my $label=gen_label_in_left($label_text);
+    my $inf_bt= (defined $info)? gen_button_message ($info,"icons/help.png"):gen_label_in_left(" ");
+    attach_widget_to_table ($table,$row,$label,$inf_bt,$b1,0);
+    $row++;  
+    update_vc_list($mpsoc,$noc_id,$nr,$np,$v,$param,$info);
+    $b1->signal_connect("clicked" => sub{ 
+            set_hetero_vc_list($mpsoc,$noc_id,$nr,$np,$param,$v,$info);        
+    });
+    return $row;
+}
 
+sub set_hetero_vc_list{
+    my($mpsoc,$noc_id,$nr,$np,$param,$v,$info)=@_;    
+    my $noc_param="noc_param$noc_id";
+    my $vc_param="vc_param$noc_id";
+    my $title=($np==1)? "Specify number of VCs in each router" : "Specify number of VCs in each router port";
+    my $window = def_popwin_size(50,40,$title,'percent');
+    my $table= def_table(10,10,FALSE);
+    my $row=0;
+    my $col=0;
+    my $init = $mpsoc->object_get_attribute($noc_param,$param);
+    my $label = "$param=";
+    my ($Ebox,$entry) = def_h_labeled_entry ($label);    
+    $entry->set_sensitive (FALSE);
+    $entry->set_text("$init");
+    my $content="1";
+    for(my $r=2;$r<=$v;$r++){ $content.=",$r" }
+    for(my $p=0;$p<$np;$p++){
+        if  ($p==0){
+            my $label= gen_label_in_center("R/P");
+            $table->attach ($label , $col, $col+4, $row,$row+1,'fill','shrink',2,2);$col+=4;	
+        }
+        my $label= gen_label_in_center("P$p");
+        $table->attach ($label , $col, $col+4, $row,$row+1,'fill','shrink',2,2);$col+=4;    
+    }
+    $row++;$col=0;
+    for(my $r=0;$r<$nr;$r++){
+        my $label= gen_label_in_center("R$r");
+        $table->attach ($label , $col, $col+4, $row,$row+1,'fill','shrink',2,2);$col+=4;
+        for(my $p=0;$p<$np;$p++){
+            my $w;
+            ($row,$col,$w)=add_param_widget ($mpsoc,undef,"R$r-P$p", $v,"Combo-box",$content,undef, $table,$row,$col,1,$vc_param,undef,undef,"horizental");
+            set_tip($w,"R$r-P$p");
+        } 
+        $row++;
+        $col=0;
+    }
+    #$table->attach ($Ebox , $row, 10, $row,$row+1,'fill','shrink',2,2);$row++;
+    
+    my $main_table=def_table(10,10,FALSE);
+    my $ok = def_image_button('icons/select.png','OK');    
+    $main_table->attach_defaults ($table  , 0, 12, 0,11);
+    $main_table->attach ($ok,5, 6, 11,12,'shrink','shrink',0,0);
+    $ok->signal_connect('clicked', sub {
+        update_vc_list($mpsoc,$noc_id,$nr,$np,$v,$param,$info);
+        set_gui_status($mpsoc,"ref",1);    
+        $window->destroy;
+    });   
+    my $scrolled_win = gen_scr_win_with_adjst($mpsoc,'gen_multicast');
+    add_widget_to_scrolled_win($main_table,$scrolled_win);
+    $window->add($scrolled_win);
+    $window->show_all();
+}
 
+sub update_vc_list{
+    my ($mpsoc,$noc_id,$nr,$np,$v,$param_in)=@_;
+    my $noc_param="noc_param$noc_id";
+    my $vc_param="vc_param$noc_id";
+    my $out="'{\n\t//";
+    for(my $p=0;$p<$np;$p++){$out.="P$p ";};
+    for(my $r=0;$r<$nr;$r++){
+        $out.="\n\t\'{";
+        for(my $p=0;$p<$np;$p++){
+            my $param   ="R$r-P$p";
+            my $val=$mpsoc->object_get_attribute($vc_param,$param) //$v;
+            $out.=($p <$np-1 )? "$val, " : "$val";           
+        }
+         $out.=($r<$nr-1)? "}, // R$r" : "}  // R$r"
+    }
+    $out.="\n\t}";
+    $mpsoc->object_add_attribute($noc_param,$param_in,$out)
+}
 
 sub set_multicast_list{
-	my($mpsoc,$noc_id)=@_;	
+    my($mpsoc,$noc_id)=@_;    
     my $noc_param="noc_param$noc_id";
-	my $window = def_popwin_size(50,40,"Select nodes invlove in multicasting ",'percent');
-	my $table= def_table(10,10,FALSE);
-	my $row=0;
-	my $col=0;
-	
-	my $init = $mpsoc->object_get_attribute($noc_param,"MCAST_ENDP_LIST");
-	$init =~ s/'h//g;
-	my @arr= reverse split (//, $init);
-		
-	
-	my $label = "Multicast Node list (hex fromat)";    
-    my ($Ebox,$entry) = def_h_labeled_entry ($label);	
-	$entry->set_sensitive (FALSE);
-		
-	my @sel_options= ("Select","All","None","2n","3n","4n","2n+1","3n+1","3n+2","4n+1","4n+2","4n+3");
-	my $combo= gen_combo(\@sel_options, 0);
-	$table->attach ($combo , 0, 1, $row,$row+1,'fill','shrink',2,2);
-	#get the number of endpoints
-	my ($NE, $NR, $RAw, $EAw, $Fw) = get_topology_info($mpsoc,$noc_id);
-	my @check;
-	
-	
-	
-	my $sel_val="Init";
-	for (my $i=0; $i<$NE; $i++){
-		if($i%10 == 0){	$row++;$col=0;}		
-		my $box;
-		my $l=$NE -$i-1;
-		
-		my $char = $arr[$l/4];
-		$char=0 if (!defined $char);
-		my $hex = hex($char);		
-		my $bit = ($hex >> ($l%4)) & 1;
-		($box,$check[$l])=def_h_labeled_checkbutton("$l");
-		$table->attach ($box , $col, $col+1, $row,$row+1,'fill','shrink',2,2);
-		$col++;	
-		
-		if($bit==1){
-			$check[$l]->set_active(TRUE);
-		}
-		
-		$check[$l]-> signal_connect("toggled" => sub{						
-			get_multicast_val ($mpsoc,$entry,$NE,@check)if($sel_val eq "Select");
-		});	
-	}	
-	$row++;
-	$col=0;
-	
-	$sel_val="Select";
-	get_multicast_val ($mpsoc,$entry,$NE,@check);
-	
-	$combo-> signal_connect("changed" => sub{
-		$sel_val=$combo->get_active_text();		
-		my $n=1;
-		my $r=0;
-		return if ($sel_val eq "Select");		
-		if ($sel_val eq "None"){		
-			for (my $i=0; $i<$NE; $i++){$check[$i]->set_active(FALSE)};
-			get_multicast_val ($mpsoc,$entry,$NE,@check);
-			$combo->set_active(0);
-			return;
-		}
-		($n,$r)=sscanf("%dn+%d",$sel_val);
-		if(!defined $r){
-			($n,$r)=sscanf("%dn",$sel_val);
-			$r=0;
-			$n=1 if(!defined $n);
-		}
-		
-		for (my $i=0; $i<$NE; $i++){
-			if($i % $n == $r){  $check[$i]->set_active(TRUE);}
-		}
-		$combo->set_active(0);
-		get_multicast_val ($mpsoc,$entry,$NE,@check);
-		
-	 });
-	
-	
-	
-	$table->attach ($Ebox , 0, 10, $row,$row+1,'fill','shrink',2,2);$row++;
-	
-	my $main_table=def_table(10,10,FALSE);
-	  
-	my $ok = def_image_button('icons/select.png','OK');	
-	$main_table->attach_defaults ($table  , 0, 12, 0,11);
+    my $window = def_popwin_size(50,40,"Select nodes invlove in multicasting ",'percent');
+    my $table= def_table(10,10,FALSE);
+    my $row=0;
+    my $col=0;
+    
+    my $init = $mpsoc->object_get_attribute($noc_param,"MCAST_ENDP_LIST");
+    $init =~ s/'h//g;
+    my @arr= reverse split (//, $init);
+    my $label = "Multicast Node list (hex fromat)";    
+    my ($Ebox,$entry) = def_h_labeled_entry ($label);    
+    $entry->set_sensitive (FALSE);
+    my @sel_options= ("Select","All","None","2n","3n","4n","2n+1","3n+1","3n+2","4n+1","4n+2","4n+3");
+    my $combo= gen_combo(\@sel_options, 0);
+    $table->attach ($combo , 0, 1, $row,$row+1,'fill','shrink',2,2);
+    #get the number of endpoints
+    my ($NE, $NR, $RAw, $EAw, $Fw) = get_topology_info($mpsoc,$noc_id);
+    my @check;
+    my $sel_val="Init";
+    for (my $i=0; $i<$NE; $i++){
+        if($i%10 == 0){    $row++;$col=0;}        
+        my $box;
+        my $l=$NE -$i-1;
+        my $char = $arr[$l/4];
+        $char=0 if (!defined $char);
+        my $hex = hex($char);        
+        my $bit = ($hex >> ($l%4)) & 1;
+        ($box,$check[$l])=def_h_labeled_checkbutton("$l");
+        $table->attach ($box , $col, $col+1, $row,$row+1,'fill','shrink',2,2);
+        $col++;    
+        if($bit==1){
+            $check[$l]->set_active(TRUE);
+        }
+        $check[$l]-> signal_connect("toggled" => sub{                        
+            get_multicast_val ($mpsoc,$entry,$NE,@check)if($sel_val eq "Select");
+        });    
+    }    
+    $row++;
+    $col=0;
+    $sel_val="Select";
+    get_multicast_val ($mpsoc,$entry,$NE,@check);
+    $combo-> signal_connect("changed" => sub{
+        $sel_val=$combo->get_active_text();        
+        my $n=1;
+        my $r=0;
+        return if ($sel_val eq "Select");        
+        if ($sel_val eq "None"){        
+            for (my $i=0; $i<$NE; $i++){$check[$i]->set_active(FALSE)};
+            get_multicast_val ($mpsoc,$entry,$NE,@check);
+            $combo->set_active(0);
+            return;
+        }
+        ($n,$r)=sscanf("%dn+%d",$sel_val);
+        if(!defined $r){
+            ($n,$r)=sscanf("%dn",$sel_val);
+            $r=0;
+            $n=1 if(!defined $n);
+        }
+        for (my $i=0; $i<$NE; $i++){
+            if($i % $n == $r){  $check[$i]->set_active(TRUE);}
+        }
+        $combo->set_active(0);
+        get_multicast_val ($mpsoc,$entry,$NE,@check);
+    });
+    $table->attach ($Ebox , 0, 10, $row,$row+1,'fill','shrink',2,2);$row++;
+    my $main_table=def_table(10,10,FALSE);
+    my $ok = def_image_button('icons/select.png','OK');    
+    $main_table->attach_defaults ($table  , 0, 12, 0,11);
     $main_table->attach ($ok,5, 6, 11,12,'shrink','shrink',0,0);
-	
-	$ok->signal_connect('clicked', sub {
-		my $s=get_multicast_val ($mpsoc,$entry,$NE,@check);
-		my $n=$entry->get_text( );
-		$mpsoc->object_add_attribute($noc_param,"MCAST_ENDP_LIST",$n);	
-	#	$mpsoc->object_add_attribute($noc_param,"MCAST_PRTLw",$s);
-		set_gui_status($mpsoc,"ref",1);	
-		$window->destroy;
-	});
-	
-	
-	
-	
-	my $scrolled_win = gen_scr_win_with_adjst($mpsoc,'gen_multicast');
-	add_widget_to_scrolled_win($main_table,$scrolled_win);
-	$window->add($scrolled_win);
-	$window->show_all();
+    $ok->signal_connect('clicked', sub {
+        my $s=get_multicast_val ($mpsoc,$entry,$NE,@check);
+        my $n=$entry->get_text( );
+        $mpsoc->object_add_attribute($noc_param,"MCAST_ENDP_LIST",$n);    
+    #    $mpsoc->object_add_attribute($noc_param,"MCAST_PRTLw",$s);
+        set_gui_status($mpsoc,"ref",1);    
+        $window->destroy;
+    });
+    my $scrolled_win = gen_scr_win_with_adjst($mpsoc,'gen_multicast');
+    add_widget_to_scrolled_win($main_table,$scrolled_win);
+    $window->add($scrolled_win);
+    $window->show_all();
 }
 
 sub get_multicast_val {
-	my ($mpsoc,$entry,$NE,@check)=@_;
-	my $n="";
-	my $h=0;
-	my $s=0;
-	for (my $i=0; $i<$NE; $i++){
-			if($check[$i]->get_active()){$h+= (1<<$i%4);$s++;} 
-		if(($i+1) % 4==0){
-			$n="$h".$n if($h<10);
-			$n=chr($h-10+97).$n if($h>9);
-			$h=0;
-		}
-	}
-	
-	$n="$h".$n if($NE%4!=0);
-	$n="'h".$n;
-	$entry->set_text("$n");
-	return $s;
-	
+    my ($mpsoc,$entry,$NE,@check)=@_;
+    my $n="";
+    my $h=0;
+    my $s=0;
+    for (my $i=0; $i<$NE; $i++){
+            if($check[$i]->get_active()){$h+= (1<<$i%4);$s++;} 
+        if(($i+1) % 4==0){
+            $n="$h".$n if($h<10);
+            $n=chr($h-10+97).$n if($h>9);
+            $h=0;
+        }
+    }
+    $n="$h".$n if($NE%4!=0);
+    $n="'h".$n;
+    $entry->set_text("$n");
+    return $s;
 }
 #############
 # config_custom_topology_gui
 ############
-
 sub config_custom_topology_gui{
-	my($mpsoc,$table,$txview,$row,$noc_id)=@_;
+    my($mpsoc,$table,$txview,$row,$noc_id)=@_;
 my $noc_param="noc_param$noc_id";
 my $coltmp=0;
 #read param.obj file to load cutom topology info
-	my $dir =get_project_dir()."/mpsoc/rtl/src_topology";
-	my $file="$dir/param.obj";
-	unless (-f $file){
-		 add_colored_info($txview,"No Custom topology find in $dir. You can define a Custom Topology using ProNoC Topology maker.\n",'red');
-		 return;		
-	}	
-	
-	my %param;	
+    my $dir =get_project_dir()."/mpsoc/rtl/src_topology";
+    my $file="$dir/param.obj";
+    unless (-f $file){
+        add_colored_info($txview,"No Custom topology find in $dir. You can define a Custom Topology using ProNoC Topology maker.\n",'red');
+        return;
+    }
+    
+    my %param;
     my ($pp,$r,$err) = regen_object($file );
-    if ($r){        
-         add_colored_info($txview,"Error: cannot open $file file: $err\n",'red');
-         return;  
-    } 		
-	
-	%param=%{$pp};
-	my @topologies=sort keys %param;
-			
-	my $label='Topology_name';
+    if ($r){
+        add_colored_info($txview,"Error: cannot open $file file: $err\n",'red');
+        return;  
+    }
+    %param=%{$pp};
+    my @topologies=sort keys %param;
+    my $label='Topology_name';
     my $param='CUSTOM_TOPOLOGY_NAME';
     my $default=$topologies[0];
     my $content= join(",", @topologies);  
     my $type='Combo-box';
     my $info="Custom topology name"; 
     ($row,$coltmp)=add_param_widget ($mpsoc,$label,$param, $default,$type,$content,$info, $table,$row,undef,1,$noc_param,1);
-    
-    my $topology_name=$mpsoc->object_get_attribute($noc_param,'CUSTOM_TOPOLOGY_NAME');        		
-	
-	
-	$label='Routing Algorithm';
+    my $topology_name=$mpsoc->object_get_attribute($noc_param,'CUSTOM_TOPOLOGY_NAME');
+    $label='Routing Algorithm';
     $param="ROUTE_NAME";
     $type="Combo-box";
-    $content=$param{$topology_name}{'ROUTE_NAME'};    		 
+    $content=$param{$topology_name}{'ROUTE_NAME'};
     my @rr=split(/\s*,\s*/,$content);
     $default=$rr[0];
     $info="Select the routing algorithm";
     ($row,$coltmp)=add_param_widget ($mpsoc,$label,$param, $default,$type,$content,$info, $table,$row,undef,1,$noc_param,1);
-  
-	$mpsoc->object_add_attribute($noc_param,'T1',$param{$topology_name}{'T1'});    
-	$mpsoc->object_add_attribute($noc_param,'T2',$param{$topology_name}{'T2'}); 
-	$mpsoc->object_add_attribute($noc_param,'T3',$param{$topology_name}{'T3'});     
-  	$mpsoc->object_add_attribute('noc_connection','er_addr',$param{$topology_name}{'er_addr'});  		
-			
-            	
-	return ($row,$coltmp);
-
+    $mpsoc->object_add_attribute($noc_param,'T1',$param{$topology_name}{'T1'});
+    $noc_param_comment{"T1"} = "Total number of endpoints in the CUSTOM topology.";
+    $mpsoc->object_add_attribute($noc_param,'T2',$param{$topology_name}{'T2'});
+    $noc_param_comment{"T2"} = "Total number of routers in the CUSTOM topology.";
+    $mpsoc->object_add_attribute($noc_param,'T3',$param{$topology_name}{'T3'});
+    $noc_param_comment{"T3"} = "Maximum number of ports in a router in the CUSTOM topology.";
+    $mpsoc->object_add_attribute($noc_param,'T4',0);
+    $noc_param_comment{"T4"} = "Unused in the CUSTOM topology.";
+    $mpsoc->object_add_attribute('noc_connection','er_addr',$param{$topology_name}{'er_addr'});
+    $noc_param_comment{"ROUTE_NAME"} = "Source-destination routing name for the CUSTOM topology.";
+    return ($row,$coltmp);
 }
 
-
-
-
 #######################
 #   get_config
 ######################
-
 sub get_config{
     my ($mpsoc,$info)=@_;
     my $table=def_table(20,10,FALSE);#    my ($row,$col,$homogeneous)=@_;
-   
-
     #noc_setting
     my $row=noc_config ($mpsoc,$table,$info);
-    
-        
     #tiles setting 
     my $tile_set;
     my $show=$mpsoc->object_get_attribute('setting','show_tile_setting');
-    
     if($show == 0){    
         $tile_set= def_image_button("icons/down.png","Tiles setting");
         $table->attach ( $tile_set , 0, 2, $row,$row+1,'fill','shrink',2,2);
         $row++;
-    
     }
-    
     $row=defualt_tilles_setting($mpsoc,$table,$show,$row,$info);
-    
-
     #end tile setting
     if($show == 1){    
         $tile_set= def_image_button("icons/up.png","Tiles setting");
@@ -1338,41 +1342,34 @@ sub get_config{
         $show=($show==1)?0:1;
         $mpsoc->object_add_attribute('setting','show_tile_setting',$show);
         set_gui_status($mpsoc,"ref",1);
-
-
     });
-
     my $scrolled_win = gen_scr_win_with_adjst($mpsoc,'get_config_adj');
-	add_widget_to_scrolled_win($table,$scrolled_win);
-	return $scrolled_win;
+    add_widget_to_scrolled_win($table,$scrolled_win);
+    return $scrolled_win;
 }
 
 
 #############
 #  gen_all_tiles
 ###########
-
 sub gen_all_tiles{
     my ($mpsoc,$info, $hw_dir,$sw_dir)=@_;
-    my ($NE, $NR, $RAw, $EAw, $Fw)=get_topology_info($mpsoc);	
+    my ($NE, $NR, $RAw, $EAw, $Fw)=get_topology_info($mpsoc);
     my $mpsoc_name=$mpsoc->object_get_attribute('mpsoc_name');
-    my $target_dir  = "$ENV{'PRONOC_WORK'}/MPSOC/$mpsoc_name";   
+    my $target_dir  = "$ENV{'PRONOC_WORK'}/MPSOC/$mpsoc_name";
     my @generated_tiles;
     for (my $tile_num=0;$tile_num<$NE;$tile_num++){
         #print "$tile_num\n";
         my ($soc_name,$num)= $mpsoc->mpsoc_get_tile_soc_name($tile_num);
         next if(!defined $soc_name);
-        
-        
-        my $path=$mpsoc->object_get_attribute('setting','soc_path');    
+        my $path=$mpsoc->object_get_attribute('setting','soc_path');
         $path=~ s/ /\\ /g;
         my $p = "$path/$soc_name.SOC";
-	    my ($soc,$r,$err) = regen_object($p);
-        if ($r){        
+        my ($soc,$r,$err) = regen_object($p);
+        if ($r){
             show_info($info,"**Error reading  $p file: $err\n");
             next; 
         } 
-        
         #update core id
         $soc->object_add_attribute('global_param','CORE_ID',$tile_num);
         #update NoC param
@@ -1383,14 +1380,12 @@ sub gen_all_tiles{
         $soc->soc_add_instance_param($nis[0] ,$nocparam );
         my %z;
         foreach my $p (sort keys %{$nocparam}){
-			$z{$p}="Parameter";
-		}		
-		$soc->soc_add_instance_param_type($nis[0] ,\%z);
+            $z{$p}="Parameter";
+        }
+        $soc->soc_add_instance_param_type($nis[0] ,\%z);
         #foreach my $p ( sort keys %nocparam ) {
-            
-        #    print "$p = $nocparam{$p} \n";
+        #  print "$p = $nocparam{$p} \n";
         #}
-
         my $sw_path     = "$sw_dir/tile$tile_num";
         #print "$sw_path\n";
         if( grep (/^$soc_name$/,@generated_tiles)){ # This soc is generated before only create the software file
@@ -1399,24 +1394,19 @@ sub gen_all_tiles{
             generate_soc($soc,$info,$target_dir,$hw_dir,$sw_path,0,1,"merge",1);
             move ("$hw_dir/$soc_name.sv","$hw_dir/tiles/");
             my @tmp= ("$hw_dir/tiles/$soc_name.sv");
-            add_to_project_file_list(\@tmp,"$hw_dir/tiles",$hw_dir);       
-            
-        }      
+            add_to_project_file_list(\@tmp,"$hw_dir/tiles",$hw_dir);
+        }
     }#$tile_num
-    
-    
 }
 
 
 ################
 #    generate_soc
 #################
-
 sub generate_soc_files{
     my ($mpsoc,$soc,$info)=@_;
     my $mpsoc_name=$mpsoc->object_get_attribute('mpsoc_name');
     my $soc_name=$soc->object_get_attribute('soc_name');
-    
     # copy all files in project work directory
     my $dir = Cwd::getcwd();
     my $project_dir      = abs_path("$dir/../../");
@@ -1425,98 +1415,76 @@ sub generate_soc_files{
     mkpath("$target_dir/src_verilog/lib/",1,0755);
     mkpath("$target_dir/src_verilog/tiles/",1,0755);
     mkpath("$target_dir/sw",1,0755);
-
     my ($file_v,$tmp)=soc_generate_verilog($soc,"$target_dir/sw",$info);
-        
     # Write object file
     open(FILE,  ">lib/soc/$soc_name.SOC") || die "Can not open: $!";
     print FILE perl_file_header("$soc_name.SOC");
     print FILE Data::Dumper->Dump([\%$soc],['soc']);
     close(FILE) || die "Error closing file: $!";
-        
     # Write verilog file
     open(FILE,  ">lib/verilog/$soc_name.sv") || die "Can not open: $!";
     print FILE $file_v;
     close(FILE) || die "Error closing file: $!";
-            
-     
-            
     #copy hdl codes in src_verilog         
     my ($hdl_ref,$warnings)= get_all_files_list($soc,"hdl_files");
     my ($sim_ref,$warnings2)= get_all_files_list($soc,"hdl_files_ticked");
-	#hdl_ref-sim_ref
-	my @n= get_diff_array($hdl_ref,$sim_ref);
-	$hdl_ref=\@n;
-			
-    foreach my $f(@{$hdl_ref}){    
+    #hdl_ref-sim_ref
+    my @n= get_diff_array($hdl_ref,$sim_ref);
+    $hdl_ref=\@n;
+    foreach my $f(@{$hdl_ref}){
         my $n="$project_dir$f";
-         if (-f "$n") {
-                 copy ("$n","$target_dir/src_verilog/lib");         
-         }elsif(-f "$f" ){
-                 copy ("$f","$target_dir/src_verilog/lib");                     
-         }            
+        if (-f "$n") {
+            copy ("$n","$target_dir/src_verilog/lib");
+        }elsif(-f "$f" ){
+            copy ("$f","$target_dir/src_verilog/lib");
+        }
     }
-    show_colored_info($info,$warnings,'green')             if(defined $warnings); 
-    
-    
-    
-	foreach my $f(@{$sim_ref}){    
-         my $n="$project_dir$f";
-         if (-f "$n") {
-                 copy ("$n","$target_dir/src_sim");         
-         }elsif(-f "$f" ){
-                 copy ("$f","$target_dir/src_sim");                     
-         }            
-    }
-    show_colored_info($info,$warnings2,'green')             if(defined $warnings2); 
-    
-    
+    show_colored_info($info,$warnings,'green')  if(defined $warnings); 
+    foreach my $f(@{$sim_ref}){
+        my $n="$project_dir$f";
+        if (-f "$n") {
+            copy ("$n","$target_dir/src_sim");
+        }elsif(-f "$f" ){
+            copy ("$f","$target_dir/src_sim");
+        }
+    }
+    show_colored_info($info,$warnings2,'green')   if(defined $warnings2); 
     #save project hdl file/folder list
     my @new_file_ref;
     foreach my $f(@{$hdl_ref}){
-            my ($name,$path,$suffix) = fileparse("$f",qr"\..[^.]*$");
-            push(@new_file_ref,"$target_dir/src_verilog/lib/$name$suffix");
+        my ($name,$path,$suffix) = fileparse("$f",qr"\..[^.]*$");
+        push(@new_file_ref,"$target_dir/src_verilog/lib/$name$suffix");
     }
     foreach my $f(@{$sim_ref}){
-            my ($name,$path,$suffix) = fileparse("$f",qr"\..[^.]*$");
-            push(@new_file_ref,"$target_dir/src_sim/$name$suffix");
+        my ($name,$path,$suffix) = fileparse("$f",qr"\..[^.]*$");
+        push(@new_file_ref,"$target_dir/src_sim/$name$suffix");
     }
     open(FILE,  ">$target_dir/src_verilog/file_list") || die "Can not open: $!";
     print FILE Data::Dumper->Dump([\@new_file_ref],['files']);
     close(FILE) || die "Error closing file: $!";            
-            
-            
-            
-            
-	move ("$dir/lib/verilog/$soc_name.sv","$target_dir/src_verilog/tiles/");     
-	copy_noc_files($project_dir,"$target_dir/src_verilog/lib");
-            
-            
-	# Write header file
-	generate_header_file($soc,$project_dir,$target_dir,$target_dir,$dir);
-	#use File::Copy::Recursive qw(dircopy);
-	#dircopy("$dir/../src_processor/aeMB/compiler","$target_dir/sw/") or die("$!\n");
-	my $msg="SoC \"$soc_name\" has been created successfully at $target_dir/ ";
-	return $msg;    
-}    
-
+    move ("$dir/lib/verilog/$soc_name.sv","$target_dir/src_verilog/tiles/");     
+    copy_noc_files($project_dir,"$target_dir/src_verilog/lib");
+    # Write header file
+    generate_header_file($soc,$project_dir,$target_dir,$target_dir,$dir);
+    #use File::Copy::Recursive qw(dircopy);
+    #dircopy("$dir/../src_processor/aeMB/compiler","$target_dir/sw/") or die("$!\n");
+    my $msg="SoC \"$soc_name\" has been created successfully at $target_dir/ ";
+    return $msg;
+}
 
 sub generate_mpsoc_lib_file {
     my ($mpsoc,$info) = @_;
     my $tmp = $mpsoc;
     my $name=$mpsoc->object_get_attribute('mpsoc_name');
-    
     open(FILE,  ">lib/mpsoc/$name.MPSOC") || die "Can not open: $!";
     print FILE perl_file_header("$name.MPSOC");
     print FILE Data::Dumper->Dump([\%$tmp],['mpsoc']);
     close(FILE) || die "Error closing file: $!";
-     
     #get_soc_list($mpsoc,$info); 
-    
-}    
+}
 
 sub check_mpsoc_name {
-	my ($name,$info,$label)= @_;
+    my ($name,$info,$label)= @_;
     $label="MPSoC" if (!defined $label);
     my $error = check_verilog_identifier_syntax($name);
     if ( defined $error ){
@@ -1530,63 +1498,53 @@ sub check_mpsoc_name {
         message_dialog("Please define the $label filed!");
         return 1;
     }
-	return 0;	
+    return 0;
 }
 
 
 ################
 #    generate_mpsoc
 #################
-
 sub generate_mpsoc{
     my ($mpsoc,$info,$show_sucess_msg)=@_;
     my $name=$mpsoc->object_get_attribute('mpsoc_name');
     return 0 if (check_mpsoc_name($name,$info));
-     
     # make target dir
     my $dir = Cwd::getcwd();
     my $target_dir  = "$ENV{'PRONOC_WORK'}/MPSOC/$name";
     my $hw_dir     = "$target_dir/src_verilog";
     my $sw_dir     = "$target_dir/sw";
-    
     # rmtree ($hw_dir);
-	mkpath("$hw_dir",1,01777);    
+    mkpath("$hw_dir",1,01777);    
     mkpath("$hw_dir/lib/",1,0755);
     mkpath("$hw_dir/tiles",1,0755);
     mkpath("$sw_dir",1,0755);
-     
     #remove old rtl files that were copied by ProNoC
     my ($old_file_ref,$r,$err) = regen_object("$hw_dir/file_list");
     if (defined $old_file_ref){        
         remove_file_and_folders($old_file_ref,$target_dir);
     }    
     unlink "$hw_dir/file_list";
-    
     #generate/copy all tiles HDL/SW codes
     gen_all_tiles($mpsoc,$info, $hw_dir,$sw_dir );
-    
     #copy clk setting hdl codes in src_verilog
-	my $project_dir	  = abs_path("$dir/../../"); 		 
+    my $project_dir      = abs_path("$dir/../../");          
     my $sc_soc =get_source_set_top($mpsoc,'mpsoc');  
-  	my ($file_ref,$warnings)= get_all_files_list($sc_soc,"hdl_files");	
-  	my ($sim_ref,$warnings2)= get_all_files_list($sc_soc,"hdl_files_ticked");
-	#file_ref-sim_ref
-	my @n= get_diff_array($file_ref,$sim_ref);
-	$file_ref=\@n;
-  	
-	copy_file_and_folders($file_ref,$project_dir,"$hw_dir/lib");
-	show_colored_info($info,$warnings,'green')     		if(defined $warnings);			
-	add_to_project_file_list($file_ref,"$hw_dir/lib/",$hw_dir);
-		 	
-	copy_file_and_folders($sim_ref,$project_dir,"$hw_dir/../src_sim");
-	show_colored_info($info,$warnings2,'green')     if(defined $warnings2);			
-	add_to_project_file_list($sim_ref,"$hw_dir/../src_sim",$hw_dir);
-    	  	
-	
-     
+    my ($file_ref,$warnings)= get_all_files_list($sc_soc,"hdl_files");    
+    my ($sim_ref,$warnings2)= get_all_files_list($sc_soc,"hdl_files_ticked");
+    #file_ref-sim_ref
+    my @n= get_diff_array($file_ref,$sim_ref);
+    $file_ref=\@n;
+    copy_file_and_folders($file_ref,$project_dir,"$hw_dir/lib");
+    show_colored_info($info,$warnings,'green')             if(defined $warnings);            
+    add_to_project_file_list($file_ref,"$hw_dir/lib/",$hw_dir);
+    
+    copy_file_and_folders($sim_ref,$project_dir,"$hw_dir/../src_sim");
+    show_colored_info($info,$warnings2,'green')     if(defined $warnings2);            
+    add_to_project_file_list($sim_ref,"$hw_dir/../src_sim",$hw_dir);
+    
     #generate header file containig the tiles physical addresses
     gen_tiles_physical_addrsses_header_file($mpsoc,"$sw_dir/phy_addr.h");
-        
     #copy all NoC HDL files    
     #my @files = glob( "$dir/../rtl/src_noc/*.v" );
     #copy_file_and_folders(\@files,$project_dir,"$hw_dir/lib/");  
@@ -1595,32 +1553,30 @@ sub generate_mpsoc{
     
     #if Topology is custom copy custom topology files
     my $topology=$mpsoc->object_get_attribute('noc_param','TOPOLOGY');
-	if ($topology eq '"CUSTOM"'){ 
-		my $Tname=$mpsoc->object_get_attribute('noc_param','CUSTOM_TOPOLOGY_NAME');
-		$Tname=~s/["]//gs;     
-		my $dir1=  get_project_dir()."/mpsoc/rtl/src_topology/$Tname";
-		my $dir2=  get_project_dir()."/mpsoc/rtl/src_topology/common";
-		my @files = File::Find::Rule->file()
+    if ($topology eq '"CUSTOM"'){ 
+        my $Tname=$mpsoc->object_get_attribute('noc_param','CUSTOM_TOPOLOGY_NAME');
+        $Tname=~s/["]//gs;     
+        my $dir1=  get_project_dir()."/mpsoc/rtl/src_topology/$Tname";
+        my $dir2=  get_project_dir()."/mpsoc/rtl/src_topology/common";
+        my @files = File::Find::Rule->file()
                             ->name( '*.v','*.V')
                             ->in( "$dir1" );
-		copy_file_and_folders (\@files,$project_dir,"$hw_dir/lib/");
-		
-		@files = File::Find::Rule->file()
+        copy_file_and_folders (\@files,$project_dir,"$hw_dir/lib/");
+        
+        @files = File::Find::Rule->file()
                             ->name( '*.v','*.V')
                             ->in( "$dir2" );
-                         
-		copy_file_and_folders (\@files,$project_dir,"$hw_dir/lib/");	
-	}
-     
-        
+        copy_file_and_folders (\@files,$project_dir,"$hw_dir/lib/");    
+    }
+    
     # Write object file
     generate_mpsoc_lib_file($mpsoc,$info);
-       
+    
     # Write verilog file
     open(FILE,  ">$target_dir/src_verilog/$name.sv") || die "Can not open: $!";
     print FILE $file_v;
     close(FILE) || die "Error closing file: $!";
-            
+    
     my $l=autogen_warning().get_license_header("${name}_top.v");
     open(FILE,  ">$target_dir/src_verilog/${name}_top.v") || die "Can not open: $!";
     print FILE "$l\n$top_v";
@@ -1628,16 +1584,10 @@ sub generate_mpsoc{
     
     gen_noc_localparam_v_file($mpsoc,"$target_dir/src_verilog/lib/src_noc");
     
-   
-     
-    
-         
-    
-  #  $l=autogen_warning().get_license_header("${name}_mp.v");
-  #  open(FILE,  ">$target_dir/src_verilog/${name}_mp.v") || die "Can not open: $!";
-  #  print FILE "$l\n$mp_v";
-  #  close(FILE) || die "Error closing file: $!";   
-        
+    #  $l=autogen_warning().get_license_header("${name}_mp.v");
+    #  open(FILE,  ">$target_dir/src_verilog/${name}_mp.v") || die "Can not open: $!";
+    #  print FILE "$l\n$mp_v";
+    #  close(FILE) || die "Error closing file: $!";   
     
     #generate makefile
     open(FILE,  ">$sw_dir/Makefile") || die "Can not open: $!";
@@ -1650,26 +1600,25 @@ sub generate_mpsoc{
     open(FILE,  ">$sw_dir/program.sh") || die "Can not open: $!";
     print FILE mpsoc_mem_prog($m_chain);
     close(FILE) || die "Error closing file: $!";
-      
+    
     my @ff= ("$target_dir/src_verilog/$name.sv","$target_dir/src_verilog/${name}_top.v");       
     add_to_project_file_list(\@ff,"$hw_dir/lib/",$hw_dir);   
     
     #write perl_object_file 
-	mkpath("$target_dir/perl_lib/",1,01777);
-	open(FILE,  ">$target_dir/perl_lib/$name.MPSOC") || die "Can not open: $!";
-	print FILE perl_file_header("$name.MPSOC");
-	print FILE Data::Dumper->Dump([\%$mpsoc],['mpsoc']);                 
+    mkpath("$target_dir/perl_lib/",1,01777);
+    open(FILE,  ">$target_dir/perl_lib/$name.MPSOC") || die "Can not open: $!";
+    print FILE perl_file_header("$name.MPSOC");
+    print FILE Data::Dumper->Dump([\%$mpsoc],['mpsoc']);                 
     
     #regenerate linker var file
     create_linker_var_file($mpsoc);
-      
-   	  
+    
     message_dialog("MPSoC \"$name\" has been created successfully at $target_dir/ " ) if($show_sucess_msg);
-	return 1;    
-}    
+    return 1;    
+}
 
 sub mpsoc_sw_make {
-     my $make="TOPTARGETS := all clean
+    my $make="TOPTARGETS := all clean
 SUBDIRS := \$(wildcard */.)
 \$(TOPTARGETS): \$(SUBDIRS)
 \$(SUBDIRS):
@@ -1677,15 +1626,13 @@ sub mpsoc_sw_make {
 
 .PHONY: \$(TOPTARGETS) \$(SUBDIRS)    
 ";
-	return $make;
+    return $make;
 }
 
 
 sub mpsoc_mem_prog {
     my $chain=shift;
-    
-     my $string="#!/bin/bash
-
+    my $string="#!/bin/bash
 
 #JTAG_INTFC=\"\$PRONOC_WORK/toolchain/bin/JTAG_INTFC\"
 source ./jtag_intfc.sh
@@ -1715,14 +1662,14 @@ sub mpsoc_mem_prog {
     bash write_memory.sh 
     cd ..
 done
- 
+
 #Enable the cpu
 \$JTAG_INTFC -t $chain -n 127  -d  \"I:1,D:2:0,I:0\"
 # I:1  set jtag_enable  in active mode
 # D:2:0 load jtag_enable data register with 0x0 reset=0 disable=0
 # I:0  set jtag_enable  in bypass mode
 ";
-	return $string;
+    return $string;
 }
 
 
@@ -1771,39 +1718,33 @@ sub get_tile{
     }
     
     $button->signal_connect("clicked" => sub{ 
-       get_tile_setting ($mpsoc,$tile);
-    });    
-  
+        get_tile_setting ($mpsoc,$tile);
+    });
     #$button->show_all;
     return $button;
 }
 
 sub define_empty_param_setting {
-	my ($mpsoc,$window)=@_;
-	my $ok = def_image_button('icons/select.png','OK');
+    my ($mpsoc,$window)=@_;
+    my $ok = def_image_button('icons/select.png','OK');
     my $okbox=def_hbox(TRUE,0);
     $okbox->pack_start($ok, FALSE, FALSE,0);
     $ok-> signal_connect("clicked" => sub{ 
-             set_gui_status($mpsoc,"refresh_soc",1);
-             $window->destroy;          
-        
-     });
-     my $param_table = def_table(1, 1, TRUE);
-	 $param_table->attach_defaults($okbox,0,1,3,4);
-	 return $param_table;
-	
-	
+        set_gui_status($mpsoc,"refresh_soc",1);
+        $window->destroy;          
+    });
+    my $param_table = def_table(1, 1, TRUE);
+    $param_table->attach_defaults($okbox,0,1,3,4);
+    return $param_table;
 }
 
 sub get_tile_setting {
-		my($mpsoc,$tile)=@_;
-		my $window = def_popwin_size(50,40,"Parameter setting for Tile $tile ",'percent');
+        my($mpsoc,$tile)=@_;
+        my $window = def_popwin_size(50,40,"Parameter setting for Tile $tile ",'percent');
         my $table = def_table(6, 2, FALSE);
-    
         my $scrolled_win = add_widget_to_scrolled_win($table);
         my $row=0;
         my ($soc_name,$g,$t)=$mpsoc->mpsoc_get_tile_soc_name($tile);
-       
         my @socs=$mpsoc->mpsoc_get_soc_list();
         my @list=(' ',@socs);
         my $pos=(defined $soc_name)? get_scolar_pos($soc_name,@list): 0;
@@ -1811,15 +1752,13 @@ sub get_tile_setting {
         my $label=gen_label_in_left("  Processing tile name:");
         $table->attach($label,0,2,$row,$row+1,'shrink','shrink',2,2);
         $table->attach($combo,2,3,$row,$row+1,'shrink','shrink',2,2);$row++;
-		add_Hsep_to_table($table,0,3,$row);$row++;
-		$soc_name = ' ' if (!defined $soc_name);
-        my $param_table =  ($soc_name eq ' ')? define_empty_param_setting($mpsoc,$window) :
-     		  get_soc_parameter_setting_table($mpsoc,$soc_name,$window,[$tile]); 
-     
-     	$table->attach_defaults($param_table,0,3,2,3);
-     	
-     	
-     	$combo->signal_connect('changed'=>sub{
+        add_Hsep_to_table($table,0,3,$row);$row++;
+        $soc_name = ' ' if (!defined $soc_name);
+        my $param_table =  ($soc_name eq ' ')? 
+            define_empty_param_setting($mpsoc,$window) :
+            get_soc_parameter_setting_table($mpsoc,$soc_name,$window,[$tile]); 
+        $table->attach_defaults($param_table,0,3,2,3);
+        $combo->signal_connect('changed'=>sub{
             my $new_soc=$combo->get_active_text();
             if ($new_soc eq ' '){
                 #unconnect tile
@@ -1840,517 +1779,419 @@ sub get_tile_setting {
         $window->show_all;
 }
 
-
 ##########
 # gen_tiles
 #########
 sub gen_tiles{
     my ($mpsoc)=@_;
-	my ($NE, $NR, $RAw, $EAw, $Fw)=get_topology_info($mpsoc);
+    my ($NE, $NR, $RAw, $EAw, $Fw)=get_topology_info($mpsoc);
     my $table;
     my $dim_y = floor(sqrt($NE));
-   	$table=def_table($NE%8,$NE/8,FALSE);#    my ($row,$col,$homogeneous)=@_;
-   	for (my $i=0; $i<$NE;$i++){
-   		my $tile=get_tile($mpsoc,$i);
-   		my $y= int($i/$dim_y);
-   		my $x= $i % $dim_y;    		
+    $table=def_table($NE%8,$NE/8,FALSE);#    my ($row,$col,$homogeneous)=@_;
+    for (my $i=0; $i<$NE;$i++){
+        my $tile=get_tile($mpsoc,$i);
+        my $y= int($i/$dim_y);
+        my $x= $i % $dim_y;            
         $table->attach_defaults ($tile, $x, $x+1 , $y, $y+1);
-   	}
-   	
-   	my $scrolled_win = gen_scr_win_with_adjst($mpsoc,'gen_tiles_adj');
-	add_widget_to_scrolled_win($table,$scrolled_win);
-	return $scrolled_win;   
+    }
+    my $scrolled_win = gen_scr_win_with_adjst($mpsoc,'gen_tiles_adj');
+    add_widget_to_scrolled_win($table,$scrolled_win);
+    return $scrolled_win;   
 }
 
 
 sub get_elf_file_addr_range {
-	my ($file,$tview)=@_;	
-	#my $command=  "size  -A $file";
-	my $command=  "nm  $file";
-	#add_info($tview,"$command\n");
-	my	($stdout,$exit,$stderr)=run_cmd_in_back_ground_get_stdout($command);
-	if(length $stderr>1){			
-		add_colored_info($tview,"$stderr\n",'red');
-		add_colored_info($tview,"$command was not run successfully!\n",'red');
-		return ("Err","Err");
-	}	
-	if($exit){
-		add_colored_info($tview,"$stdout\n",'red');
-		add_colored_info($tview,"$command was not run successfully!\n",'red');
-		return ("Err","Err");
-	}
-							
-	my @lines = split ("\n" ,$stdout);
-	my $max_addr=0;
-	my $sec_name;	
-
-	foreach my $p (@lines ){
-		$p =~ s/\s+/ /g; # remove extra spaces
-	    $p =~ s/^\s+//; #ltrim
-		my ($addr,$type,$name)= sscanf("%x %s %s","$p");
-		if(defined $addr && defined $name){
-			if($max_addr < $addr) {
-				$max_addr = $addr;
-				$sec_name = $name;		
-			}
-		} 
-	}
-	return ($max_addr,$sec_name);	
+    my ($file,$tview)=@_;    
+    #my $command=  "size  -A $file";
+    my $command=  "nm  $file";
+    #add_info($tview,"$command\n");
+    my ($stdout,$exit,$stderr)=run_cmd_in_back_ground_get_stdout($command);
+    if(length $stderr>1){            
+        add_colored_info($tview,"$stderr\n",'red');
+        add_colored_info($tview,"$command was not run successfully!\n",'red');
+        return ("Err","Err");
+    }
+    if($exit){
+        add_colored_info($tview,"$stdout\n",'red');
+        add_colored_info($tview,"$command was not run successfully!\n",'red');
+        return ("Err","Err");
+    }
+    my @lines = split ("\n" ,$stdout);
+    my $max_addr=0;
+    my $sec_name;    
+    foreach my $p (@lines ){
+        $p =~ s/\s+/ /g; # remove extra spaces
+        $p =~ s/^\s+//; #ltrim
+        my ($addr,$type,$name)= sscanf("%x %s %s","$p");
+        if(defined $addr && defined $name){
+            if($max_addr < $addr) {
+                $max_addr = $addr;
+                $sec_name = $name;        
+            }
+        } 
+    }
+    return ($max_addr,$sec_name);    
 }
 
 
 sub show_reqired_brams{
-	my ($self,$tview)=@_;
-	my $win=def_popwin_size (50,50,"BRAM info", 'percent');
-	my $sc_win = gen_scr_win_with_adjst($self,'liststore');
-	my $table= def_table(10,10,FALSE);
-	add_widget_to_scrolled_win($table,$sc_win);	
-	my $row=0;
-	my $col=0;		
-	
-	my  @clmns =('Tile#', 'Section located in Upper Bound Address (UBA) ','UBA in Bytes','UBA in Words','Minimum Memory Address Width');	
-	my $target_dir;
-	my @data;
+    my ($self,$tview)=@_;
+    my $win=def_popwin_size (50,50,"BRAM info", 'percent');
+    my $sc_win = gen_scr_win_with_adjst($self,'liststore');
+    my $table= def_table(10,10,FALSE);
+    add_widget_to_scrolled_win($table,$sc_win);    
+    my $row=0;
+    my $col=0;
+    
+    my  @clmns =('Tile#', 'Section located in Upper Bound Address (UBA) ','UBA in Bytes','UBA in Words','Minimum Memory Address Width');    
+    my $target_dir;
+    my @data;
     
     my $mpsoc_name=$self->object_get_attribute('mpsoc_name');
-	if(defined $mpsoc_name){#it is an soc
-
-		my ($NE, $NR, $RAw, $EAw, $Fw)=get_topology_info($self);	
-   
-	    $target_dir  = "$ENV{'PRONOC_WORK'}/MPSOC/$mpsoc_name"; 	  
-	   
-	    for (my $tile_num=0;$tile_num<$NE;$tile_num++){           
-			my $ram_file     = "$target_dir/sw/tile$tile_num/image";	        
-	        my ($size,$sec) = get_elf_file_addr_range($ram_file,$tview);
-	        my %clmn;
-	        $clmn{0}="tile$tile_num";
-	        $clmn{1}= "$sec";
-	        $clmn{2}="$size";
-	        my $w=$size/4;
-	        $clmn{3}="$w";
-	        $clmn{4}=ceil(log($w)/log(2));
-	        push(@data,\%clmn);
-	        
-	    }#$tile_num	
-	} 
-	else 
-	{
-		my $soc_name=$self->object_get_attribute('soc_name');
-		$target_dir  = "$ENV{'PRONOC_WORK'}/SOC/$soc_name";
-		my $ram_file     = "$target_dir/sw/image";	    	        
-	    my ($size,$sec) = get_elf_file_addr_range($ram_file,$tview);	        
-	    my %clmn;
-	    $clmn{0}="$soc_name";
-	    $clmn{1}= "$sec";
-	    $clmn{2}="$size";
-	    my $w=$size/4;
-	    $clmn{3}="$w";
-	    $clmn{4}=ceil(log($w)/log(2));
-	    push(@data,\%clmn);		
-	}	
-
-	my @clmn_type = (#'Glib::Boolean', # => G_TYPE_BOOLEAN
-                                    #'Glib::Uint',    # => G_TYPE_UINT
-                                    'Glib::String',  # => G_TYPE_STRING
-                                  'Glib::String',
-                                   'Glib::String',
-                                   'Glib::String',
-                                   'Glib::String'); # you get the idea
-	
-	my $list=	gen_list_store (\@data,\@clmn_type,\@clmns);
-	$table-> attach  ($list, $col, $col+1,  $row, $row+1,'shrink','shrink',2,2); $row++; 
-	
-	$win->add($sc_win);
-	$win->show_all();	
+    if(defined $mpsoc_name){#it is an soc
+        my ($NE, $NR, $RAw, $EAw, $Fw)=get_topology_info($self);    
+        $target_dir  = "$ENV{'PRONOC_WORK'}/MPSOC/$mpsoc_name";       
+        for (my $tile_num=0;$tile_num<$NE;$tile_num++){           
+            my $ram_file     = "$target_dir/sw/tile$tile_num/image";            
+            my ($size,$sec) = get_elf_file_addr_range($ram_file,$tview);
+            my %clmn;
+            $clmn{0}="tile$tile_num";
+            $clmn{1}= "$sec";
+            $clmn{2}="$size";
+            my $w=$size/4;
+            $clmn{3}="$w";
+            $clmn{4}=ceil(log($w)/log(2));
+            push(@data,\%clmn);
+        }#$tile_num
+    } 
+    else 
+    {
+        my $soc_name=$self->object_get_attribute('soc_name');
+        $target_dir  = "$ENV{'PRONOC_WORK'}/SOC/$soc_name";
+        my $ram_file     = "$target_dir/sw/image";                    
+        my ($size,$sec) = get_elf_file_addr_range($ram_file,$tview);            
+        my %clmn;
+        $clmn{0}="$soc_name";
+        $clmn{1}= "$sec";
+        $clmn{2}="$size";
+        my $w=$size/4;
+        $clmn{3}="$w";
+        $clmn{4}=ceil(log($w)/log(2));
+        push(@data,\%clmn);        
+    }    
+
+    my @clmn_type = (
+        #'Glib::Boolean', # => G_TYPE_BOOLEAN
+        #'Glib::Uint',    # => G_TYPE_UINT
+        'Glib::String',  # => G_TYPE_STRING
+        'Glib::String',
+        'Glib::String',
+        'Glib::String',
+        'Glib::String'
+    ); 
+    
+    my $list=    gen_list_store (\@data,\@clmn_type,\@clmns);
+    $table-> attach  ($list, $col, $col+1,  $row, $row+1,'shrink','shrink',2,2); $row++; 
+    $win->add($sc_win);
+    $win->show_all();    
 }
 
 sub check_conflict {
-	my ($self,$tile_num,$label)=@_;	
-	
-	my $r1 =$self->object_get_attribute("ROM$tile_num",'end'); 
-	my $r2 =$self->object_get_attribute("RAM$tile_num",'start');
-	
-	if(defined $r1 && defined $r2){
-		if(hex($r1)> hex($r2)){
-			$label->set_markup("<span  foreground= 'red' ><b>RAM-ROM range Conflict</b></span>");
-			
-		}else {	 
-			$label->set_label(" ");
-		
-		}
-	}else {
-		$label->set_label(" ");
-	
-	} 	
+    my ($self,$tile_num,$label)=@_;    
+    my $r1 =$self->object_get_attribute("ROM$tile_num",'end'); 
+    my $r2 =$self->object_get_attribute("RAM$tile_num",'start');
+    if(defined $r1 && defined $r2){
+        if(hex($r1)> hex($r2)){
+            $label->set_markup("<span  foreground= 'red' ><b>RAM-ROM range Conflict</b></span>");
+            
+        }else {     
+            $label->set_label(" ");
+        
+        }
+    }else {
+        $label->set_label(" ");
+    
+    }     
 }
 
 
 sub update_ram_rom_size {
-	my ($self,$tile_num,$name,$label,$start,$end,$conflict)=@_;	
-	my $s = $start->get_value();
-	my $e = $end->get_value();
-
-	$self->object_add_attribute($name.$tile_num,'start',$start->get_value());
-	$self->object_add_attribute($name.$tile_num,'end',$end->get_value());
-	if($e <= $s){
-		#$label->set_label("Invalid range" );
-		$label->set_markup("<span  foreground= 'red' ><b>Invalid range</b></span>");
-		
-	}else {
-		$label->set_label( metric_conversion($e - $s) . "B");
-	
-	}
-	
-	check_conflict($self,$tile_num,$conflict);
-	
-	
-	
+    my ($self,$tile_num,$name,$label,$start,$end,$conflict)=@_;    
+    my $s = $start->get_value();
+    my $e = $end->get_value();
+    $self->object_add_attribute($name.$tile_num,'start',$start->get_value());
+    $self->object_add_attribute($name.$tile_num,'end',$end->get_value());
+    if($e <= $s){
+        #$label->set_label("Invalid range" );
+        $label->set_markup("<span  foreground= 'red' ><b>Invalid range</b></span>");
+        
+    }else {
+        $label->set_label( metric_conversion($e - $s) . "B");
+    }
+    check_conflict($self,$tile_num,$conflict);
 }
 
 sub get_tile_peripheral_patameter {
-	my ($mpsoc,$tile_num,$peripheral,$param_name)=@_;  
-	my ($soc_name,$n,$soc_num)=$mpsoc->mpsoc_get_tile_soc_name($tile_num);
-	if(defined $soc_name) {
-		my $top=$mpsoc->mpsoc_get_soc($soc_name);
-		my @insts=$top->top_get_all_instances();
-		foreach my $id (@insts){					
-			if ($id =~/$peripheral[0-9]/){
-				my $name=$top->top_get_def_of_instance($id,'instance');
-				
-				my  %params;
-				my $setting=$mpsoc->mpsoc_get_tile_param_setting($tile_num);
-				#if ($setting eq 'Custom'){
-					%params= $top->top_get_custom_soc_param($tile_num);
-				#}else{
-				#	%params=$top->top_get_default_soc_param();
-				#}
-				return $params{"${name}_$param_name"};
-			}	
-		}
-	}
-	return undef;		
-							
+    my ($mpsoc,$tile_num,$peripheral,$param_name)=@_;  
+    my ($soc_name,$n,$soc_num)=$mpsoc->mpsoc_get_tile_soc_name($tile_num);
+    if(defined $soc_name) {
+        my $top=$mpsoc->mpsoc_get_soc($soc_name);
+        my @insts=$top->top_get_all_instances();
+        foreach my $id (@insts){                    
+            if ($id =~/$peripheral[0-9]/){
+                my $name=$top->top_get_def_of_instance($id,'instance');
+                
+                my  %params;
+                my $setting=$mpsoc->mpsoc_get_tile_param_setting($tile_num);
+                #if ($setting eq 'Custom'){
+                    %params= $top->top_get_custom_soc_param($tile_num);
+                #}else{
+                #    %params=$top->top_get_default_soc_param();
+                #}
+                return $params{"${name}_$param_name"};
+            }    
+        }
+    }
+    return undef;
 }
 
 sub get_soc_peripheral_parameter {
-	my ($soc,$peripheral,$param_nam)=@_;	
-	my @instances=$soc->soc_get_all_instances();
-	foreach my $id (@instances){
-		if ($id =~/$peripheral[0-9]/){	
-			return $soc->soc_get_module_param_value ($id,$param_nam) if (defined $param_nam);		
-		}
-	}	
-	return undef;
+    my ($soc,$peripheral,$param_nam)=@_;    
+    my @instances=$soc->soc_get_all_instances();
+    foreach my $id (@instances){
+        if ($id =~/$peripheral[0-9]/){    
+            return $soc->soc_get_module_param_value ($id,$param_nam) if (defined $param_nam);        
+        }
+    }    
+    return undef;
 }
 
-
 sub linker_initial_setting {
-	my ($self,$tview)=@_;	
-	my $mpsoc_name=$self->object_get_attribute('mpsoc_name');
+    my ($self,$tview)=@_;    
+    my $mpsoc_name=$self->object_get_attribute('mpsoc_name');
     my $tnum;
     my $target_dir;
-	if(defined $mpsoc_name){#it is an mpsoc
-
-		my ($NE, $NR, $RAw, $EAw, $Fw)=get_topology_info($self);	
-   	
-	    $target_dir  = "$ENV{'PRONOC_WORK'}/MPSOC/$mpsoc_name";
-	    for (my $tile_num=0;$tile_num<$NE;$tile_num++){      
-	    	
-	    	my $v=get_tile_peripheral_patameter($self,$tile_num,"_ram","Aw");
-	    	$v = 13 if (!defined $v);
-	    	$self->object_add_attribute('MEM'.$tile_num,'width',$v);
-	    	$self->object_add_attribute('MEM'.$tile_num,'percent',75);
-	    	
-	    	my $s =(1 << ($v+2)) ;
-			my $p = 75;
-			
-			my $rom_start = 0;
-			my $rom_end= int ( ($s*$p)/100);
-			my $ram_start= int (($s*$p)/100);
-			my $ram_end= $s;
-			
-			$self->object_add_attribute('ROM'.$tile_num,'start',$rom_start);
-			$self->object_add_attribute('ROM'.$tile_num,'end',$rom_end);
-			$self->object_add_attribute('RAM'.$tile_num,'start',$ram_start);
-			$self->object_add_attribute('RAM'.$tile_num,'end',$ram_end);
-	    	
-	    
-	    }	
-	    
-	     	  
-	}
-	else 
-	{
-		my $v=get_soc_peripheral_parameter ($self,"_ram","Aw");
-		$v = 13 if (!defined $v);
-		$self->object_add_attribute('MEM0','width',$v);
-		$self->object_add_attribute('MEM0','percent',75);
-		my $s =(1 << ($v+2)) ;
-		my $p = 75;
-			
-		my $rom_start = 0;
-		my $rom_end= int ( ($s*$p)/100);
-		my $ram_start= int (($s*$p)/100);
-		my $ram_end= $s;
-			
-		$self->object_add_attribute('ROM0','start',$rom_start);
-		$self->object_add_attribute('ROM0','end',$rom_end);
-		$self->object_add_attribute('RAM0','start',$ram_start);
-		$self->object_add_attribute('RAM0','end',$ram_end);
-	}  
-	
-	
+    if(defined $mpsoc_name){#it is an mpsoc
+
+        my ($NE, $NR, $RAw, $EAw, $Fw)=get_topology_info($self);    
+        $target_dir  = "$ENV{'PRONOC_WORK'}/MPSOC/$mpsoc_name";
+        for (my $tile_num=0;$tile_num<$NE;$tile_num++){      
+            my $v=get_tile_peripheral_patameter($self,$tile_num,"_ram","Aw");
+            $v = 13 if (!defined $v);
+            $self->object_add_attribute('MEM'.$tile_num,'width',$v);
+            $self->object_add_attribute('MEM'.$tile_num,'percent',75);
+            my $s =(1 << ($v+2)) ;
+            my $p = 75;
+            my $rom_start = 0;
+            my $rom_end= int ( ($s*$p)/100);
+            my $ram_start= int (($s*$p)/100);
+            my $ram_end= $s;
+            $self->object_add_attribute('ROM'.$tile_num,'start',$rom_start);
+            $self->object_add_attribute('ROM'.$tile_num,'end',$rom_end);
+            $self->object_add_attribute('RAM'.$tile_num,'start',$ram_start);
+            $self->object_add_attribute('RAM'.$tile_num,'end',$ram_end);
+        }    
+    }
+    else 
+    {
+        my $v=get_soc_peripheral_parameter ($self,"_ram","Aw");
+        $v = 13 if (!defined $v);
+        $self->object_add_attribute('MEM0','width',$v);
+        $self->object_add_attribute('MEM0','percent',75);
+        my $s =(1 << ($v+2)) ;
+        my $p = 75;
+        my $rom_start = 0;
+        my $rom_end= int ( ($s*$p)/100);
+        my $ram_start= int (($s*$p)/100);
+        my $ram_end= $s;
+        $self->object_add_attribute('ROM0','start',$rom_start);
+        $self->object_add_attribute('ROM0','end',$rom_end);
+        $self->object_add_attribute('RAM0','start',$ram_start);
+        $self->object_add_attribute('RAM0','end',$ram_end);
+    }  
 }
 
-
-
 sub linker_setting{
-	my ($self,$tview)=@_;
-	my $win=def_popwin_size (80,50,"BRAM info", 'percent');
-	my $sc_win = gen_scr_win_with_adjst($self,'liststore');
-	my $table= def_table(10,10,FALSE);
-	
-	
-	my $row=0;
-	my $col=0;		
-	
-	$table-> attach  (gen_label_in_center("Tile"), $col, $col+1,  $row, $row+1,'shrink','shrink',2,2); $col+=1;
-	$table-> attach  (gen_label_in_center("Memory Addr"), $col, $col+1,  $row, $row+1,'shrink','shrink',2,2); $col+=1;
-	$table-> attach  (gen_label_in_center("ROM/(ROM+RAM)"), $col, $col+1,  $row, $row+1,'shrink','shrink',2,2); $col+=1;
-	
-	$table-> attach  (gen_label_in_center("ROM index addr (hex)"), $col, $col+2,  $row, $row+1,'shrink','shrink',2,2); $col+=3;
-	$table-> attach  (gen_label_in_center("RAM index addr (hex)"), $col, $col+2,  $row, $row+1,'shrink','shrink',2,2); $col+=3;
-
-	
-	$col=0;$row++; 
-	$table-> attach  (gen_label_in_center("#"), $col, $col+1,  $row, $row+1,'shrink','shrink',2,2); $col++;
-	$table-> attach  (gen_label_in_center("Width"), $col, $col+1,  $row, $row+1,'shrink','shrink',2,2); $col++;
-	$table-> attach  (gen_label_in_center("(%)"), $col, $col+1,  $row, $row+1,'shrink','shrink',2,2); $col++;
-	
-	$table-> attach  (gen_label_in_center("Beginning"), $col, $col+1,  $row, $row+1,'shrink','shrink',2,2); $col+=1;
-	$table-> attach  (gen_label_in_center("End"), $col, $col+1,  $row, $row+1,'shrink','shrink',2,2); $col++;
-	$table-> attach  (gen_label_in_center("Size"), $col, $col+1,  $row, $row+1,'shrink','shrink',2,2); $col++;
-	
-	$table-> attach  (gen_label_in_center("Beginning"), $col, $col+1,  $row, $row+1,'shrink','shrink',2,2); $col+=1;
-	$table-> attach  (gen_label_in_center("End"), $col, $col+1,  $row, $row+1,'shrink','shrink',2,2); $col++;
-	$table-> attach  (gen_label_in_center("Size"), $col, $col+1,  $row, $row+1,'shrink','shrink',2,2); $col++;
-	
-		
-	$col=0;$row++; 	
-	
-	my $target_dir;
-	my @data;
-    
+    my ($self,$tview)=@_;
+    my $win=def_popwin_size (80,50,"BRAM info", 'percent');
+    my $sc_win = gen_scr_win_with_adjst($self,'liststore');
+    my $table= def_table(10,10,FALSE);
+    my $row=0;
+    my $col=0;        
+    $table-> attach  (gen_label_in_center("Tile"), $col, $col+1,  $row, $row+1,'shrink','shrink',2,2); $col+=1;
+    $table-> attach  (gen_label_in_center("Memory Addr"), $col, $col+1,  $row, $row+1,'shrink','shrink',2,2); $col+=1;
+    $table-> attach  (gen_label_in_center("ROM/(ROM+RAM)"), $col, $col+1,  $row, $row+1,'shrink','shrink',2,2); $col+=1;
+    $table-> attach  (gen_label_in_center("ROM index addr (hex)"), $col, $col+2,  $row, $row+1,'shrink','shrink',2,2); $col+=3;
+    $table-> attach  (gen_label_in_center("RAM index addr (hex)"), $col, $col+2,  $row, $row+1,'shrink','shrink',2,2); $col+=3;
+    $col=0;$row++; 
+    $table-> attach  (gen_label_in_center("#"), $col, $col+1,  $row, $row+1,'shrink','shrink',2,2); $col++;
+    $table-> attach  (gen_label_in_center("Width"), $col, $col+1,  $row, $row+1,'shrink','shrink',2,2); $col++;
+    $table-> attach  (gen_label_in_center("(%)"), $col, $col+1,  $row, $row+1,'shrink','shrink',2,2); $col++;
+    $table-> attach  (gen_label_in_center("Beginning"), $col, $col+1,  $row, $row+1,'shrink','shrink',2,2); $col+=1;
+    $table-> attach  (gen_label_in_center("End"), $col, $col+1,  $row, $row+1,'shrink','shrink',2,2); $col++;
+    $table-> attach  (gen_label_in_center("Size"), $col, $col+1,  $row, $row+1,'shrink','shrink',2,2); $col++;
+    $table-> attach  (gen_label_in_center("Beginning"), $col, $col+1,  $row, $row+1,'shrink','shrink',2,2); $col+=1;
+    $table-> attach  (gen_label_in_center("End"), $col, $col+1,  $row, $row+1,'shrink','shrink',2,2); $col++;
+    $table-> attach  (gen_label_in_center("Size"), $col, $col+1,  $row, $row+1,'shrink','shrink',2,2); $col++;
+    $col=0;$row++;     
+    my $target_dir;
+    my @data;
     my $mpsoc_name=$self->object_get_attribute('mpsoc_name');
     my $tnum;
-	if(defined $mpsoc_name){#it is an mpsoc
-
-		my ($NE, $NR, $RAw, $EAw, $Fw)=get_topology_info($self);	
-   		$tnum=$NE;
-	    $target_dir  = "$ENV{'PRONOC_WORK'}/MPSOC/$mpsoc_name"; 	  
-	}
-	else 
-	{
-		my $soc_name=$self->object_get_attribute('soc_name');
-		$target_dir  = "$ENV{'PRONOC_WORK'}/SOC/$soc_name";
-		$tnum=1;
-	}   
-	for (my $j=0;$j<$tnum;$j++){           
-			my $tile_num=$j;
-			my $conflict =gen_label_in_center(" ") ;
-			
-			$table-> attach  (gen_label_in_center("$tile_num"), $col, $col+1,  $row, $row+1,'shrink','shrink',2,2);$col++; 
-			my $ram_width = gen_spin(2,64,1);
-			my $width = $self->object_get_attribute('MEM'.$tile_num,'width');
-			if(!defined $width){
-				linker_initial_setting ($self,$tview);
-				$width = $self->object_get_attribute('MEM'.$tile_num,'width');
-			}
-			$ram_width->set_value($width);	
-			my $size =gen_label_in_center(metric_conversion(1 << 15). "B") ;
-			
-			
-			$table-> attach  (def_pack_hbox('FALSE',0,$ram_width,$size), $col, $col+1,  $row, $row+1,'shrink','shrink',2,2); $col++; 
-			
-			
-			
-			
-			my $percent = gen_spin_float(6.25,93.75,6.25,2);
-			my $p=$self->object_get_attribute('MEM'.$tile_num,'percent');
-			$percent->set_value($p);
-			
-			my $enter= def_image_button("icons/enter.png"); 
-			$table-> attach  (def_pack_hbox('FALSE',0,$percent,$enter), $col, $col+1,  $row, $row+1,'shrink','shrink',2,2); $col++; 
-			
-			my $rom_start_v =$self->object_get_attribute('ROM'.$tile_num,'start');
-			my $rom_end_v = $self->object_get_attribute('ROM'.$tile_num,'end');
-			my $ram_start_v = $self->object_get_attribute('RAM'.$tile_num,'start');
-			my $ram_end_v = $self->object_get_attribute('RAM'.$tile_num,'end');
-			
-			
-			
-			my $rom_start = HexSpin->new ( $rom_start_v, 0, 0xffffffff ,4);
-			$rom_start->set_digits(8);
-			$table-> attach  ($rom_start, $col, $col+1,  $row, $row+1,'shrink','shrink',2,2); $col++; 
-			
-			
-			
-			my $rom_end = HexSpin->new ( $rom_end_v, 0, 0xffffffff ,4);
-			$rom_end->set_digits(8);
-			$table-> attach  ($rom_end, $col, $col+1,  $row, $row+1,'shrink','shrink',2,2); $col++; 
-			
-			my $rom_size =gen_label_in_center(" ") ;
-			$table-> attach  ($rom_size, $col, $col+1,  $row, $row+1,'shrink','shrink',2,2); $col++; 
-			update_ram_rom_size($self,$tile_num,'ROM',$rom_size,$rom_start,$rom_end,$conflict);
-			$rom_start->signal_connect ( 'changed', sub {update_ram_rom_size($self,$tile_num,'ROM',$rom_size,$rom_start,$rom_end,$conflict);});
-			$rom_end->signal_connect ( 'changed', sub {update_ram_rom_size($self,$tile_num,'ROM',$rom_size,$rom_start,$rom_end,$conflict);});
-		
-			my $ram_start = HexSpin->new ( $ram_start_v, 0, 0xffffffff ,4);
-			$ram_start->set_digits(8);
-			$table-> attach  ($ram_start, $col, $col+1,  $row, $row+1,'shrink','shrink',2,2); $col++; 
-			
-			
-			my $ram_end = HexSpin->new ( $ram_end_v, 0, 0xffffffff ,4);
-			$ram_end->set_digits(8);
-			$table-> attach  ($ram_end, $col, $col+1,  $row, $row+1,'shrink','shrink',2,2); $col++; 
-		
-			my $ram_size =gen_label_in_center(" ") ;
-			$table-> attach  ($ram_size, $col, $col+1,  $row, $row+1,'shrink','shrink',2,2); $col++; 
-			
-			
-			
-			
-			update_ram_rom_size($self,$tile_num,'RAM',$ram_size,$ram_start,$ram_end,$conflict);
-			
-			$ram_start->signal_connect ( 'changed', sub {update_ram_rom_size($self,$tile_num,'RAM',$ram_size,$ram_start,$ram_end,$conflict);});
-			$ram_end->signal_connect ( 'changed', sub {update_ram_rom_size($self,$tile_num,'RAM',$ram_size,$ram_start,$ram_end,$conflict);});
-		
-		    $ram_width->signal_connect("value_changed" => sub{
-				my $w=$ram_width->get_value();
-				$self->object_add_attribute('MEM'.$tile_num,'width',$w);
-				$size->set_label (metric_conversion(1 << ($w+2)). "B") ;
-				$size->show_all;
-				$enter->clicked; 
-			});	
-		    $percent->signal_connect("value_changed" => sub{
-		    	$self->object_add_attribute('MEM'.$tile_num,'percent',$percent->get_value());
-		    });
-		    
-		    $table-> attach  ($conflict, $col, $col+1,  $row, $row+1,'shrink','shrink',2,2); $col++; 
-		
-		   
-		
-			
-			$enter-> signal_connect ( 'clicked' , sub {
-				my $w=$ram_width->get_value();
-				my $s =(1 << ($w+2));
-				my $p = $percent->get_value();
-				
-				my $rom_start_v = 0;
-				my $rom_end_v= int ( ($s*$p)/100);
-				my $ram_start_v= int (($s*$p)/100);
-				my $ram_end_v= $s;
-				
-				$rom_start->set_value($rom_start_v);
-				$rom_end->set_value($rom_end_v);
-				$ram_start->set_value($ram_start_v);
-				$ram_end->set_value($ram_end_v);
-				update_ram_rom_size($self,$tile_num,'ROM',$rom_size,$rom_start,$rom_end,$conflict);
-				update_ram_rom_size($self,$tile_num,'RAM',$ram_size,$ram_start,$ram_end,$conflict);
-				
-			});
-			
-			$col=0; $row++; 
-	        
-	}#$tile_num	
-	 
-	my $main_table=def_table(10,10,FALSE);
-	  
-	my $ok = def_image_button('icons/select.png','OK');	
-	$main_table->attach_defaults ($table  , 0, 12, 0,11);
+    if(defined $mpsoc_name){#it is an mpsoc
+        my ($NE, $NR, $RAw, $EAw, $Fw)=get_topology_info($self);    
+        $tnum=$NE;
+        $target_dir  = "$ENV{'PRONOC_WORK'}/MPSOC/$mpsoc_name";       
+    }
+    else 
+    {
+        my $soc_name=$self->object_get_attribute('soc_name');
+        $target_dir  = "$ENV{'PRONOC_WORK'}/SOC/$soc_name";
+        $tnum=1;
+    }   
+    for (my $j=0;$j<$tnum;$j++){
+        my $tile_num=$j;
+        my $conflict =gen_label_in_center(" ") ;
+        $table-> attach  (gen_label_in_center("$tile_num"), $col, $col+1,  $row, $row+1,'shrink','shrink',2,2);$col++; 
+        my $ram_width = gen_spin(2,64,1);
+        my $width = $self->object_get_attribute('MEM'.$tile_num,'width');
+        if(!defined $width){
+            linker_initial_setting ($self,$tview);
+            $width = $self->object_get_attribute('MEM'.$tile_num,'width');
+        }
+        $ram_width->set_value($width);    
+        my $size =gen_label_in_center(metric_conversion(1 << 15). "B") ;
+        $table-> attach  (def_pack_hbox('FALSE',0,$ram_width,$size), $col, $col+1,  $row, $row+1,'shrink','shrink',2,2); $col++; 
+        my $percent = gen_spin_float(6.25,93.75,6.25,2);
+        my $p=$self->object_get_attribute('MEM'.$tile_num,'percent');
+        $percent->set_value($p);
+        my $enter= def_image_button("icons/enter.png"); 
+        $table-> attach  (def_pack_hbox('FALSE',0,$percent,$enter), $col, $col+1,  $row, $row+1,'shrink','shrink',2,2); $col++; 
+        my $rom_start_v =$self->object_get_attribute('ROM'.$tile_num,'start');
+        my $rom_end_v = $self->object_get_attribute('ROM'.$tile_num,'end');
+        my $ram_start_v = $self->object_get_attribute('RAM'.$tile_num,'start');
+        my $ram_end_v = $self->object_get_attribute('RAM'.$tile_num,'end');
+        my $rom_start = HexSpin->new ( $rom_start_v, 0, 0xffffffff ,4);
+        $rom_start->set_digits(8);
+        $table-> attach  ($rom_start, $col, $col+1,  $row, $row+1,'shrink','shrink',2,2); $col++; 
+        my $rom_end = HexSpin->new ( $rom_end_v, 0, 0xffffffff ,4);
+        $rom_end->set_digits(8);
+        $table-> attach  ($rom_end, $col, $col+1,  $row, $row+1,'shrink','shrink',2,2); $col++; 
+        my $rom_size =gen_label_in_center(" ") ;
+        $table-> attach  ($rom_size, $col, $col+1,  $row, $row+1,'shrink','shrink',2,2); $col++; 
+        update_ram_rom_size($self,$tile_num,'ROM',$rom_size,$rom_start,$rom_end,$conflict);
+        $rom_start->signal_connect ( 'changed', sub {update_ram_rom_size($self,$tile_num,'ROM',$rom_size,$rom_start,$rom_end,$conflict);});
+        $rom_end->signal_connect ( 'changed', sub {update_ram_rom_size($self,$tile_num,'ROM',$rom_size,$rom_start,$rom_end,$conflict);});
+        my $ram_start = HexSpin->new ( $ram_start_v, 0, 0xffffffff ,4);
+        $ram_start->set_digits(8);
+        $table-> attach  ($ram_start, $col, $col+1,  $row, $row+1,'shrink','shrink',2,2); $col++; 
+        my $ram_end = HexSpin->new ( $ram_end_v, 0, 0xffffffff ,4);
+        $ram_end->set_digits(8);
+        $table-> attach  ($ram_end, $col, $col+1,  $row, $row+1,'shrink','shrink',2,2); $col++; 
+        my $ram_size =gen_label_in_center(" ") ;
+        $table-> attach  ($ram_size, $col, $col+1,  $row, $row+1,'shrink','shrink',2,2); $col++; 
+        update_ram_rom_size($self,$tile_num,'RAM',$ram_size,$ram_start,$ram_end,$conflict);
+        $ram_start->signal_connect ( 'changed', sub {update_ram_rom_size($self,$tile_num,'RAM',$ram_size,$ram_start,$ram_end,$conflict);});
+        $ram_end->signal_connect ( 'changed', sub {update_ram_rom_size($self,$tile_num,'RAM',$ram_size,$ram_start,$ram_end,$conflict);});
+        $ram_width->signal_connect("value_changed" => sub{
+            my $w=$ram_width->get_value();
+            $self->object_add_attribute('MEM'.$tile_num,'width',$w);
+            $size->set_label (metric_conversion(1 << ($w+2)). "B") ;
+            $size->show_all;
+            $enter->clicked; 
+        });    
+        $percent->signal_connect("value_changed" => sub{
+            $self->object_add_attribute('MEM'.$tile_num,'percent',$percent->get_value());
+        });
+        $table-> attach  ($conflict, $col, $col+1,  $row, $row+1,'shrink','shrink',2,2); $col++; 
+        $enter-> signal_connect ( 'clicked' , sub {
+            my $w=$ram_width->get_value();
+            my $s =(1 << ($w+2));
+            my $p = $percent->get_value();
+            my $rom_start_v = 0;
+            my $rom_end_v= int ( ($s*$p)/100);
+            my $ram_start_v= int (($s*$p)/100);
+            my $ram_end_v= $s;
+            $rom_start->set_value($rom_start_v);
+            $rom_end->set_value($rom_end_v);
+            $ram_start->set_value($ram_start_v);
+            $ram_end->set_value($ram_end_v);
+            update_ram_rom_size($self,$tile_num,'ROM',$rom_size,$rom_start,$rom_end,$conflict);
+            update_ram_rom_size($self,$tile_num,'RAM',$ram_size,$ram_start,$ram_end,$conflict);
+        });
+        $col=0; $row++; 
+    }#$tile_num    
+    my $main_table=def_table(10,10,FALSE);
+    my $ok = def_image_button('icons/select.png','OK');    
+    $main_table->attach_defaults ($table  , 0, 12, 0,11);
     $main_table->attach ($ok,5, 6, 11,12,'shrink','shrink',0,0);
-	
-	$ok->signal_connect('clicked', sub {
-		for (my $t=0;$t<$tnum;$t++){      
-			my $r0 =$self->object_get_attribute("ROM$t",'start');
-			my $r1 =$self->object_get_attribute("ROM$t",'end'); 
-			my $r2 =$self->object_get_attribute("RAM$t",'start');
-			my $r3 =$self->object_get_attribute("RAM$t",'end'); 
-			if(hex($r1) <hex($r0)  || hex($r3) <hex($r2)   ){
-				 message_dialog("Please fix tile $t invalid range !");
-				 return ;
-				
-			}
-			
-			if(hex($r1) > hex($r2)  ){
-				 message_dialog("Please fix tile $t conflict range !");
-				 return ;
-				
-			}
-			
-			
-			
-		}
-		create_linker_var_file($self);	
-		$win->destroy();
-	
-	
-	});
-	
-	
-	add_widget_to_scrolled_win($main_table,$sc_win);
-	$win->add($sc_win);
-	$win->show_all();	
-	
+    $ok->signal_connect('clicked', sub {
+        for (my $t=0;$t<$tnum;$t++){      
+            my $r0 =$self->object_get_attribute("ROM$t",'start');
+            my $r1 =$self->object_get_attribute("ROM$t",'end'); 
+            my $r2 =$self->object_get_attribute("RAM$t",'start');
+            my $r3 =$self->object_get_attribute("RAM$t",'end'); 
+            if(hex($r1) <hex($r0)  || hex($r3) <hex($r2)   ){
+                message_dialog("Please fix tile $t invalid range !");
+                return ;
+            }
+            if(hex($r1) > hex($r2)  ){
+                message_dialog("Please fix tile $t conflict range !");
+                return ;
+            }
+        }
+        create_linker_var_file($self);    
+        $win->destroy();
+    });
+    add_widget_to_scrolled_win($main_table,$sc_win);
+    $win->add($sc_win);
+    $win->show_all();    
 }
 
 
 sub create_linker_var_file{
-	my ($self)=@_;
-	my $mpsoc_name=$self->object_get_attribute('mpsoc_name');
+    my ($self)=@_;
+    my $mpsoc_name=$self->object_get_attribute('mpsoc_name');
     my $tnum;
     
     my $width = $self->object_get_attribute('MEM0','width');
-	if(!defined $width){
+    if(!defined $width){
         linker_initial_setting ($self);
-	}
+    }
+    
+    if(defined $mpsoc_name){#it is an mpsoc
+        my ($NE, $NR, $RAw, $EAw, $Fw)=get_topology_info($self);    
+        $tnum=$NE;       
+    }
+    else 
+    {
+        $tnum=1;        
+    }   
+    for (my $t=0;$t<$tnum;$t++){       
+        my $r0 =$self->object_get_attribute("ROM$t",'start');
+        my $r1 =$self->object_get_attribute("ROM$t",'end'); 
+        my $r2 =$self->object_get_attribute("RAM$t",'start');
+        my $r3 =$self->object_get_attribute("RAM$t",'end'); 
+        my $file=sprintf("        
     
-	if(defined $mpsoc_name){#it is an mpsoc
-		my ($NE, $NR, $RAw, $EAw, $Fw)=get_topology_info($self);	
-   		$tnum=$NE;	   
-	}
-	else 
-	{
-		
-		$tnum=1;		
-	}   
-	
-	for (my $t=0;$t<$tnum;$t++){       
-		my $r0 =$self->object_get_attribute("ROM$t",'start');
-		my $r1 =$self->object_get_attribute("ROM$t",'end'); 
-		my $r2 =$self->object_get_attribute("RAM$t",'start');
-		my $r3 =$self->object_get_attribute("RAM$t",'end'); 
-						
-		my $file=sprintf("		
-	
 MEMORY
-{	
-	rom (rx)    : ORIGIN = 0x%x , LENGTH = 0x%x  /* %s B- Rom space  */
-	ram (wrx)   : ORIGIN = 0x%x , LENGTH = 0x%x  /* %s B- Ram space  */
-}		
-
-			",$r0,$r1 - $r0, metric_conversion($r1 - $r0),$r2,$r3- $r2,metric_conversion($r3 - $r2));
-			
-		if(defined $mpsoc_name){			
-			save_file ("$ENV{'PRONOC_WORK'}/MPSOC/$mpsoc_name/sw/tile$t/linkvar.ld",$file) if(-d "$ENV{'PRONOC_WORK'}/MPSOC/$mpsoc_name/sw/tile$t/"); 
-		}else{
-			my $soc_name=$self->object_get_attribute('soc_name');
-			my $p1="$ENV{'PRONOC_WORK'}/SOC/$soc_name/sw/";
-			mkpath("$p1",1,0755) unless (-d "$p1");		
-			save_file ("$p1/linkvar.ld",$file) 
-		}
-	}
-	
+{    
+    rom (rx)    : ORIGIN = 0x%x , LENGTH = 0x%x  /* %s B- Rom space  */
+    ram (wrx)   : ORIGIN = 0x%x , LENGTH = 0x%x  /* %s B- Ram space  */
+}        
+
+            ",$r0,$r1 - $r0, metric_conversion($r1 - $r0),$r2,$r3- $r2,metric_conversion($r3 - $r2));
+            
+        if(defined $mpsoc_name){            
+            save_file ("$ENV{'PRONOC_WORK'}/MPSOC/$mpsoc_name/sw/tile$t/linkvar.ld",$file) if(-d "$ENV{'PRONOC_WORK'}/MPSOC/$mpsoc_name/sw/tile$t/"); 
+        }else{
+            my $soc_name=$self->object_get_attribute('soc_name');
+            my $p1="$ENV{'PRONOC_WORK'}/SOC/$soc_name/sw/";
+            mkpath("$p1",1,0755) unless (-d "$p1");        
+            save_file ("$p1/linkvar.ld",$file) 
+        }
+    }
+    
 }
 
 
@@ -2370,7 +2211,7 @@ sub software_edit_mpsoc {
     my @pages_lables=($orcc_lable);
     my ($app,$table,$tview) = software_main($sw,undef,\@pages,\@pages_lables);    
     
-	my $prog= def_image_button('icons/write.png','Program FPGA\'s BRAMs');
+    my $prog= def_image_button('icons/write.png','Program FPGA\'s BRAMs');
     my $linker = def_image_button('icons/setting.png','LD Linker',FALSE,1);
     my $make = def_image_button('icons/gen.png','_Compile',FALSE,1);
     my $ram = def_image_button('icons/info.png',"Required BRAMs\' size",FALSE,1);
@@ -2380,12 +2221,10 @@ sub software_edit_mpsoc {
     $table->attach ($make,5, 6, 1,2,'shrink','shrink',0,0);
     $table->attach ($prog,9, 10, 1,2,'shrink','shrink',0,0); 
     
-	$ram -> signal_connect("clicked" => sub{
-		show_reqired_brams($self,$tview);
-	});
-	 
-	  my $load;
-	 
+    $ram -> signal_connect("clicked" => sub{
+        show_reqired_brams($self,$tview);
+    });
+    my $load;
     $make -> signal_connect("clicked" => sub{
         $load->destroy   if(defined $load);
         $load= show_gif("icons/load.gif");
@@ -2394,33 +2233,29 @@ sub software_edit_mpsoc {
         $app->ask_to_save_changes();
         add_info($tview,' ');
         unless (run_make_file($sw,$tview,'clean')){
-        	$load->destroy;    
-        	$load=def_icon("icons/cancel.png");
-        	$table->attach ($load,7, 8, 1,2,'shrink','shrink',0,0); 
-        	$load->show_all; 
-        	return;
+            $load->destroy;    
+            $load=def_icon("icons/cancel.png");
+            $table->attach ($load,7, 8, 1,2,'shrink','shrink',0,0); 
+            $load->show_all; 
+            return;
         };
-         unless (run_make_file($sw,$tview)){
-         	$load->destroy;    
-         	$load=def_icon("icons/cancel.png");
-         	$table->attach ($load,7, 8, 1,2,'shrink','shrink',0,0); 
-         	$load->show_all; 
-         	return;
-         }
+        unless (run_make_file($sw,$tview)){
+            $load->destroy;    
+            $load=def_icon("icons/cancel.png");
+            $table->attach ($load,7, 8, 1,2,'shrink','shrink',0,0); 
+            $load->show_all; 
+            return;
+        }
         $load->destroy; 
         $load=def_icon("icons/button_ok.png");
         $table->attach ($load,7, 8, 1,2,'shrink','shrink',0,0); 
         $load->show_all; 
-        
-
     });
-    
     #Programe the board 
     $prog-> signal_connect("clicked" => sub{ 
         my $error = 0;
         my $bash_file="$sw/program.sh";
         my $jtag_intfc="$sw/jtag_intfc.sh";
-        
         add_info($tview,"Program the board using quartus_pgm and $bash_file file\n");
         #check if the programming file exists
         unless (-f $bash_file) {
@@ -2432,7 +2267,6 @@ sub software_edit_mpsoc {
             add_colored_info($tview,"\tThe $jtag_intfc does not exists!. Press the compile button and select your FPGA board first to generate $jtag_intfc file\n", 'red');
             $error=1;
         }
-        
         return if($error);
         my $command = "cd $sw; bash program.sh";
         add_info($tview,"$command\n");
@@ -2441,36 +2275,26 @@ sub software_edit_mpsoc {
             add_colored_info($tview,"$stderr\n",'red');
             add_colored_info($tview,"Memory was not programmed successfully!\n",'red');
         }else {
-
             if($exit){
                 add_colored_info($tview,"$stdout\n",'red');
                 add_colored_info($tview,"Memory was not programmed successfully!\n",'red');
             }else{
                 add_info($tview,"$stdout\n");
                 add_colored_info($tview,"Memory is programmed successfully!\n",'blue');
-
             }
-            
         }        
     });
-    
-    
     $linker -> signal_connect("clicked" => sub{
-		linker_setting($self,$tview);
-	});
-
+        linker_setting($self,$tview);
+    });
 }
-
-
-
 #############
 #    load_mpsoc
 #############
-
 sub load_mpsoc{
     my ($mpsoc,$info)=@_;
     my $file;
-    my $dialog =  gen_file_dialog (undef, 'MPSOC');	
+    my $dialog =  gen_file_dialog (undef, 'MPSOC');    
     my $dir = Cwd::getcwd();
     $dialog->set_current_folder ("$dir/lib/mpsoc")    ;
     my @newsocs=$mpsoc->mpsoc_get_soc_list();
@@ -2485,13 +2309,10 @@ sub load_mpsoc{
                 $dialog->destroy;
                 return;
             } 
-            
-
             clone_obj($mpsoc,$pp);
             #read save mpsoc socs
             my @oldsocs=$mpsoc->mpsoc_get_soc_list();
             #add existing SoCs and add them to mpsoc
-            
             my $error;
             #print "old: @oldsocs\n new @newsocs \n"; 
             foreach my $p (@oldsocs) {
@@ -2499,618 +2320,514 @@ sub load_mpsoc{
                 my @num= $mpsoc->mpsoc_get_soc_tiles_num($p);
                 if (scalar @num && ( grep (/^$p$/,@newsocs)==0)){
                     my $m="Processing tile $p that has been used for ties  @num but is not located in library anymore\n";
-                     $error = (defined $error ) ? "$error $m" : $m;
+                    $error = (defined $error ) ? "$error $m" : $m;
                 } 
                 $mpsoc->mpsoc_remove_soc ($p) if (grep (/^$p$/,@newsocs)==0); 
-                     
-
             }
             @newsocs=get_soc_list($mpsoc,$info); # add all existing socs
             add_info($info,"**Error:  \n $error\n") if(defined $error);
-
             set_gui_status($mpsoc,"load_file",0);
-                    
-        }                    
-     }
-     $dialog->destroy;
+        } 
+    }
+    $dialog->destroy;
 }
 
 #######
-#	CLK setting
+#    CLK setting
 #######
-
 sub clk_setting_win1{
-	my ($self,$info,$type)=@_;
-
-	my $window = def_popwin_size(80,80,"CLK setting",'percent');
-   
-    my $next=def_image_button('icons/right.png','Next'); 	
-	my $mtable = def_table(10, 1, FALSE);
-	#get the list of all tiles clk sources
-	
-	my @sources=('clk','reset');
-	
-	my $table = def_table(10, 7, FALSE);
-	my $notebook = gen_notebook();
-	$notebook->set_scrollable(TRUE);
-	#$notebook->can_focus(FALSE);
-	$notebook->set_tab_pos ('left'); 
-	
-	
-	
-	my($row,$column)=(0,0);
-	
-	my %all = ($type eq 'mpsoc') ? get_all_tiles_clk_sources_list($self): get_soc_clk_source_list($self) ;
-	foreach my $s (@sources){
-		 my $spin;	
-		 ($row,$column,$spin)=  add_param_widget($self,"$s number","${s}_number", 1,'Spin-button',"1,1024,1","Define total number of ${s} input ports  mpsoc", $table,$row,$column,1,'SOURCE_SET',undef,undef,'horizontal');
-		 
-		 my $w=get_source_assignment_win($self,$s,$all{$s},$type);
-		 my $box=def_hbox(FALSE,0);
-		 $box->pack_start($w, TRUE, TRUE, 0);
-		 $notebook->append_page ($box,gen_label_in_center ($s)); 
-		 $spin->signal_connect("value_changed" => sub{
-		 	$self->object_add_attribute('SOURCE_SET',"REDEFINE_TOP",1);    
-		 	$w->destroy;
-		 	$w=get_source_assignment_win($self,$s,$all{$s},$type);
-		 	$box->pack_start($w, TRUE, TRUE, 0);
-		 	$box->show_all; 
-		 	
-		 });
-		
-	}	
-
-	$mtable->attach_defaults($table,0,1,0,1);
-	$mtable->attach_defaults( $notebook,0,1,1,20);
-	$mtable->attach($next,0,1,20,21,'expand','fill',2,2);	
-	$window->add ($mtable);
-	$window->show_all();	
-	$next-> signal_connect("clicked" => sub{ 			
-		clk_setting_win2($self,$info,$type);
-		$window->destroy;	
-					
-	});	
-
+    my ($self,$info,$type)=@_;
+    my $window = def_popwin_size(80,80,"CLK setting",'percent');
+    my $next=def_image_button('icons/right.png','Next');     
+    my $mtable = def_table(10, 1, FALSE);
+    #get the list of all tiles clk sources
+    my @sources=('clk','reset');
+    my $table = def_table(10, 7, FALSE);
+    my $notebook = gen_notebook();
+    $notebook->set_scrollable(TRUE);
+    #$notebook->can_focus(FALSE);
+    $notebook->set_tab_pos ('left'); 
+    my($row,$column)=(0,0);
+    my %all = ($type eq 'mpsoc') ? get_all_tiles_clk_sources_list($self): get_soc_clk_source_list($self) ;
+    foreach my $s (@sources){
+        my $spin;    
+        ($row,$column,$spin)=  add_param_widget($self,"$s number","${s}_number", 1,'Spin-button',"1,1024,1","Define total number of ${s} input ports  mpsoc", $table,$row,$column,1,'SOURCE_SET',undef,undef,'horizontal');
+        my $w=get_source_assignment_win($self,$s,$all{$s},$type);
+        my $box=def_hbox(FALSE,0);
+        $box->pack_start($w, TRUE, TRUE, 0);
+        $notebook->append_page ($box,gen_label_in_center ($s)); 
+        $spin->signal_connect("value_changed" => sub{
+            $self->object_add_attribute('SOURCE_SET',"REDEFINE_TOP",1);    
+            $w->destroy;
+            $w=get_source_assignment_win($self,$s,$all{$s},$type);
+            $box->pack_start($w, TRUE, TRUE, 0);
+            $box->show_all; 
+         });
+    }    
+    $mtable->attach_defaults($table,0,1,0,1);
+    $mtable->attach_defaults( $notebook,0,1,1,20);
+    $mtable->attach($next,0,1,20,21,'expand','fill',2,2);    
+    $window->add ($mtable);
+    $window->show_all();    
+    $next-> signal_connect("clicked" => sub{             
+        clk_setting_win2($self,$info,$type);
+        $window->destroy;    
+    });    
 }
 
 
 sub update_wave_form {
-	my ($period,$rise,$fall,$r_lab,$f_lab)=@_;
-	my $p =$period->get_value();
-	my $n =$rise->get_value();
-	my $v= ($p * $n)/100;
-	$r_lab->set_text("=$v ns");			 
-	$n =$fall->get_value();
-	$v= ($p * $n)/100;
-	$f_lab->set_text("=$v ns");	
+    my ($period,$rise,$fall,$r_lab,$f_lab)=@_;
+    my $p =$period->get_value();
+    my $n =$rise->get_value();
+    my $v= ($p * $n)/100;
+    $r_lab->set_text("=$v ns");             
+    $n =$fall->get_value();
+    $v= ($p * $n)/100;
+    $f_lab->set_text("=$v ns");    
 }
 
 sub get_source_assignment_win{
-	my ($mpsoc,$s,$ports_ref,$type)=@_;
-	my$row=0;
-	my $column=0;
-	my $num = $mpsoc->object_get_attribute('SOURCE_SET',"${s}_number");	
-	my $table1 = def_table(20, 20, FALSE);
-	my $win1=add_widget_to_scrolled_win($table1);
-	my $win2;
-	my $v2;
-	
-	#if($s eq 'clk'){
-	#	my @labels=("clk name", 'Frequency MHz', 'Period ns', 'rise edge times ns', 'fall edge times ns');
-	#	foreach my $l (@labels){
-			#  $table1->attach  (gen_label_in_center($l),$column,$column+1,$row,$row+1,'fill','shrink',2,2);$column+=5;
-	#	}
-		#$row++;
-		#$column=0;
-	#}
-	
-	#get source signal names	
-	my $loc =  'vertical';
-	for(my $n=0;$n<$num; $n++ ){
-		my $entry;
-		my $enter= def_image_button("icons/enter.png");
-		my $box=def_hbox(FALSE,0);
-		$box->pack_start( $enter, FALSE, FALSE, 0);	
-
-		($row,$column,$entry)=  add_param_widget($mpsoc,"$n-","${s}_${n}_name", "${s}$n",'Entry',undef,undef, $table1,$row,$column,1,'SOURCE_SET',undef,undef,'horizontal');
-	    $table1->attach  ($box,$column,$column+1,$row,$row+1,'fill','shrink',2,2);$column++;
-	       
-		$enter->signal_connect ("clicked"  => sub{
-			$mpsoc->object_add_attribute('SOURCE_SET',"REDEFINE_TOP",1); 
-			$win2->destroy;
-			$win2= get_source_assignment_win2($mpsoc,$s,$ports_ref,$type);
-			$v2-> pack2($win2, TRUE, TRUE);  
-			$v2->show_all;			
-		});
-		
-		
-		if($s eq 'clk'){
-			($column,$row)=get_clk_constrain_widget($mpsoc,$table1,$column,$row, $s,$n);		 		
-		}
-		
-			
-	    
-	   # if((($n+1) % 4)==0){
-		  	$column=0;
-		  	$row++;
-	   #}		  
-	}	
-     	
-   	#source assigmnmet
+    my ($mpsoc,$s,$ports_ref,$type)=@_;
+    my$row=0;
+    my $column=0;
+    my $num = $mpsoc->object_get_attribute('SOURCE_SET',"${s}_number");    
+    my $table1 = def_table(20, 20, FALSE);
+    my $win1=add_widget_to_scrolled_win($table1);
+    my $win2;
+    my $v2;
+    
+    #if($s eq 'clk'){
+    #    my @labels=("clk name", 'Frequency MHz', 'Period ns', 'rise edge times ns', 'fall edge times ns');
+    #    foreach my $l (@labels){
+            #  $table1->attach  (gen_label_in_center($l),$column,$column+1,$row,$row+1,'fill','shrink',2,2);$column+=5;
+    #    }
+        #$row++;
+        #$column=0;
+    #}
+    
+    #get source signal names    
+    my $loc =  'vertical';
+    for(my $n=0;$n<$num; $n++ ){
+        my $entry;
+        my $enter= def_image_button("icons/enter.png");
+        my $box=def_hbox(FALSE,0);
+        $box->pack_start( $enter, FALSE, FALSE, 0);    
+        ($row,$column,$entry)=  add_param_widget($mpsoc,"$n-","${s}_${n}_name", "${s}$n",'Entry',undef,undef, $table1,$row,$column,1,'SOURCE_SET',undef,undef,'horizontal');
+        $table1->attach  ($box,$column,$column+1,$row,$row+1,'fill','shrink',2,2);$column++;
+        $enter->signal_connect ("clicked"  => sub{
+            $mpsoc->object_add_attribute('SOURCE_SET',"REDEFINE_TOP",1); 
+            $win2->destroy;
+            $win2= get_source_assignment_win2($mpsoc,$s,$ports_ref,$type);
+            $v2-> pack2($win2, TRUE, TRUE);  
+            $v2->show_all;            
+        });
+        if($s eq 'clk'){
+            ($column,$row)=get_clk_constrain_widget($mpsoc,$table1,$column,$row, $s,$n);                 
+        }
+        # if((($n+1) % 4)==0){
+            $column=0;
+            $row++;
+        #}
+    }
+    #source assigmnmet
     $win2= get_source_assignment_win2($mpsoc,$s,$ports_ref,$type);
-	$v2=gen_vpaned($win1,.2,$win2);	
-   	return $v2;	
+    $v2=gen_vpaned($win1,.2,$win2);
+        return $v2;
 }
 
 
 sub get_clk_constrain_widget {
-	my ($self,$table,$column,$row, $s,$n)=@_;
-	$table->attach (gen_Vsep() , $column,$column+1,$row,$row+1,'fill','fill',2,2);$column+=1;
-	return ($column,$row);
-	my $frequency;	
-	($row,$column,$frequency)=  add_param_widget($self,"Frequency(MHz)","${s}_${n}_mhz", 100,'Spin-button',"1,1024,0.01",undef, $table,$row,$column,1,'SOURCE_SET',undef,undef,'horizontal');
-	$table->attach (gen_Vsep() , $column,$column+1,$row,$row+1,'fill','fill',2,2);$column+=1;
-	my $period;
-	($row,$column,$period)=  add_param_widget($self,"Period(ns)","${s}_${n}_period", 10,'Spin-button',"0,1024,0.01",undef, $table,$row,$column,1,'SOURCE_SET',undef,undef,'horizontal');
-	$table->attach (gen_Vsep() , $column,$column+1,$row,$row+1,'fill','fill',2,2);$column+=1;
-	my $rise;	
-	($row,$column,$rise)=  add_param_widget($self,"rising edge(%)","${s}_${n}_rise", 0,'Spin-button',"0,100,0.1",undef, $table,$row,$column,1,'SOURCE_SET',undef,undef,'horizontal');
-	my $r_lab=gen_label_in_center('=0 ns');
-	$table->attach  ($r_lab,$column,$column+1,$row,$row+1,'fill','shrink',2,2);$column+=1;
-	$table->attach (gen_Vsep() , $column,$column+1,$row,$row+1,'fill','fill',2,2);$column+=1;
-	my $fall;	
-	($row,$column,$fall)=  add_param_widget($self,"falling edge(%)","${s}_${n}_fall", 50,'Spin-button',"0,100,0.1",undef, $table,$row,$column,1,'SOURCE_SET',undef,undef,'horizontal');
-	my $f_lab=gen_label_in_center('=5 ns');
-	$table->attach  ($f_lab,$column,$column+1,$row,$row+1,'fill','shrink',2,2);$column+=1;
-	update_wave_form($period,$rise,$fall,$r_lab,$f_lab);
-	$frequency-> signal_connect("value_changed" => sub{
-	 	my $fr =$frequency->get_value();
-		my $p = 1000/$fr;
-	 	$period->set_value($p);
-	 	update_wave_form($period,$rise,$fall,$r_lab,$f_lab);
-	});	
-	$period-> signal_connect("value_changed" => sub{
-		my $p =$period->get_value();
-		my $fr = 1000/$p;
-		$frequency->set_value($fr);
-		update_wave_form($period,$rise,$fall,$r_lab,$f_lab);
-	});	
-	$rise-> signal_connect("value_changed" => sub{
-	 	update_wave_form($period,$rise,$fall,$r_lab,$f_lab);		 	
-	});	
-	$fall-> signal_connect("value_changed" => sub{
-	   update_wave_form($period,$rise,$fall,$r_lab,$f_lab);
-	});	
-	return ($column,$row);
+    my ($self,$table,$column,$row, $s,$n)=@_;
+    $table->attach (gen_Vsep() , $column,$column+1,$row,$row+1,'fill','fill',2,2);$column+=1;
+    return ($column,$row);
+    my $frequency;    
+    ($row,$column,$frequency)=  add_param_widget($self,"Frequency(MHz)","${s}_${n}_mhz", 100,'Spin-button',"1,1024,0.01",undef, $table,$row,$column,1,'SOURCE_SET',undef,undef,'horizontal');
+    $table->attach (gen_Vsep() , $column,$column+1,$row,$row+1,'fill','fill',2,2);$column+=1;
+    my $period;
+    ($row,$column,$period)=  add_param_widget($self,"Period(ns)","${s}_${n}_period", 10,'Spin-button',"0,1024,0.01",undef, $table,$row,$column,1,'SOURCE_SET',undef,undef,'horizontal');
+    $table->attach (gen_Vsep() , $column,$column+1,$row,$row+1,'fill','fill',2,2);$column+=1;
+    my $rise;    
+    ($row,$column,$rise)=  add_param_widget($self,"rising edge(%)","${s}_${n}_rise", 0,'Spin-button',"0,100,0.1",undef, $table,$row,$column,1,'SOURCE_SET',undef,undef,'horizontal');
+    my $r_lab=gen_label_in_center('=0 ns');
+    $table->attach  ($r_lab,$column,$column+1,$row,$row+1,'fill','shrink',2,2);$column+=1;
+    $table->attach (gen_Vsep() , $column,$column+1,$row,$row+1,'fill','fill',2,2);$column+=1;
+    my $fall;    
+    ($row,$column,$fall)=  add_param_widget($self,"falling edge(%)","${s}_${n}_fall", 50,'Spin-button',"0,100,0.1",undef, $table,$row,$column,1,'SOURCE_SET',undef,undef,'horizontal');
+    my $f_lab=gen_label_in_center('=5 ns');
+    $table->attach  ($f_lab,$column,$column+1,$row,$row+1,'fill','shrink',2,2);$column+=1;
+    update_wave_form($period,$rise,$fall,$r_lab,$f_lab);
+    $frequency-> signal_connect("value_changed" => sub{
+        my $fr =$frequency->get_value();
+        my $p = 1000/$fr;
+        $period->set_value($p);
+        update_wave_form($period,$rise,$fall,$r_lab,$f_lab);
+    });
+    $period-> signal_connect("value_changed" => sub{
+        my $p =$period->get_value();
+        my $fr = 1000/$p;
+        $frequency->set_value($fr);
+        update_wave_form($period,$rise,$fall,$r_lab,$f_lab);
+    });    
+    $rise-> signal_connect("value_changed" => sub{
+        update_wave_form($period,$rise,$fall,$r_lab,$f_lab);             
+    });    
+    $fall-> signal_connect("value_changed" => sub{
+        update_wave_form($period,$rise,$fall,$r_lab,$f_lab);
+    });
+    return ($column,$row);
 }
 
 
-
 sub get_source_assignment_win2{
-	my ($mpsoc,$s,$ports_ref,$type)=@_;
-	my $num = $mpsoc->object_get_attribute('SOURCE_SET',"${s}_number");
-	my $table2 = def_table(10, 7, FALSE);
-   	my $win2=add_widget_to_scrolled_win($table2);
-   	my %ports = %{$ports_ref} if(defined $ports_ref);   
-   
-	my $contents;
-	for(my $n=0;$n<$num; $n++ ){
-   		my $m=$mpsoc->object_get_attribute('SOURCE_SET',"${s}_${n}_name");
-   		$contents=(defined $contents)? "$contents,$m":$m;   
-	}
-	my $default=$mpsoc->object_get_attribute('SOURCE_SET',"${s}_0_name");	
-	my $n=0;
-	my($row,$column)=(0,0);
-	if($type eq 'mpsoc' ) {
-		add_param_widget($mpsoc,"    NoC $s","NoC_${s}", $default,'Combo-box',$contents,undef, $table2,$row,$column,1,'SOURCE_SET_CONNECT',undef,undef,'horizontal');
-		($row,$column)=(1,0);
-	}	
-
-	foreach my $p (sort keys %ports){
-   		my @array=@{$ports{$p}};
-   		foreach my $q (@array){
-   			my $param="${p}_$q"; 
-   			my $label="  ${p}_$q";    			  			
-   			($row,$column)=  add_param_widget($mpsoc,$label,$param, $default,'Combo-box',$contents,undef, $table2,$row,$column,1,'SOURCE_SET_CONNECT',undef,undef,'horizontal');
-   			if((($n+1) % 4)==0){$column=0;$row++;}$n++;
-   		}		
-	}
-	return $win2;
-	
+    my ($mpsoc,$s,$ports_ref,$type)=@_;
+    my $num = $mpsoc->object_get_attribute('SOURCE_SET',"${s}_number");
+    my $table2 = def_table(10, 7, FALSE);
+    my $win2=add_widget_to_scrolled_win($table2);
+    my %ports = %{$ports_ref} if(defined $ports_ref);   
+    my $contents;
+    for(my $n=0;$n<$num; $n++ ){
+        my $m=$mpsoc->object_get_attribute('SOURCE_SET',"${s}_${n}_name");
+        $contents=(defined $contents)? "$contents,$m":$m;   
+    }
+    my $default=$mpsoc->object_get_attribute('SOURCE_SET',"${s}_0_name");    
+    my $n=0;
+    my($row,$column)=(0,0);
+    if($type eq 'mpsoc' ) {
+        add_param_widget($mpsoc,"    NoC $s","NoC_${s}", $default,'Combo-box',$contents,undef, $table2,$row,$column,1,'SOURCE_SET_CONNECT',undef,undef,'horizontal');
+        ($row,$column)=(1,0);
+    }    
+    foreach my $p (sort keys %ports){
+        my @array=@{$ports{$p}};
+        foreach my $q (@array){
+            my $param="${p}_$q"; 
+            my $label="  ${p}_$q";                              
+            ($row,$column)=  add_param_widget($mpsoc,$label,$param, $default,'Combo-box',$contents,undef, $table2,$row,$column,1,'SOURCE_SET_CONNECT',undef,undef,'horizontal');
+            if((($n+1) % 4)==0){$column=0;$row++;}$n++;
+        }        
+    }
+    return $win2;
 }
 
 
 sub get_all_tiles_clk_sources_list{
-	my $mpsoc=shift;
-	my ($NE, $NR, $RAw, $EAw, $Fw)= get_topology_info ($mpsoc); 
-    my %all_sources;	
-	for (my $tile_num=0;$tile_num<$NE;$tile_num++){
-		my ($soc_name,$n,$soc_num)=$mpsoc->mpsoc_get_tile_soc_name($tile_num);
-		next if(!defined $soc_name); 	
-		my $top=$mpsoc->mpsoc_get_soc($soc_name);
-		my @intfcs=$top->top_get_intfc_list();
-		
-		my @sources=('clk','reset');
-			
-		foreach my $intfc (@intfcs){
-			my($type,$name,$num)= split("[:\[ \\]]", $intfc);
-			foreach my $s (@sources){
-				if ($intfc =~ /plug:$s/){ 
-					my @ports=$top->top_get_intfc_ports_list($intfc);				
-					$all_sources{$s}{"T$tile_num"}=\@ports;
-				}	
-			}
-		
-		}
-	}
-		return  %all_sources;	
+    my $mpsoc=shift;
+    my ($NE, $NR, $RAw, $EAw, $Fw)= get_topology_info ($mpsoc); 
+    my %all_sources;    
+    for (my $tile_num=0;$tile_num<$NE;$tile_num++){
+        my ($soc_name,$n,$soc_num)=$mpsoc->mpsoc_get_tile_soc_name($tile_num);
+        next if(!defined $soc_name);     
+        my $top=$mpsoc->mpsoc_get_soc($soc_name);
+        my @intfcs=$top->top_get_intfc_list();
+        my @sources=('clk','reset');
+        foreach my $intfc (@intfcs){
+            my($type,$name,$num)= split("[:\[ \\]]", $intfc);
+            foreach my $s (@sources){
+                if ($intfc =~ /plug:$s/){ 
+                    my @ports=$top->top_get_intfc_ports_list($intfc);                
+                    $all_sources{$s}{"T$tile_num"}=\@ports;
+                }    
+            }
+        }
+    }
+    return  %all_sources;    
 }
 
-
-
 sub clk_setting_win2{
-	my ($self,$info,$type)=@_;
-		
-	my $window = def_popwin_size(70,70,"CLK setting",'percent');
+    my ($self,$info,$type)=@_;
+    my $window = def_popwin_size(70,70,"CLK setting",'percent');
     my $table = def_table(10, 7, FALSE);
     my $scrolled_win=add_widget_to_scrolled_win($table);
-    my $ok = def_image_button('icons/select.png','OK');	
+    my $ok = def_image_button('icons/select.png','OK');    
     my $back = def_image_button('icons/left.png',undef);
-    my $diagram  = def_image_button('icons/diagram.png','Diagram');	
+    my $diagram  = def_image_button('icons/diagram.png','Diagram');    
     my $ip = ip->lib_new ();
     #print "get_top_ip(\$self,$type);\n";
     my $mpsoc_ip=get_top_ip($self,$type);
-  
-	$ip->add_ip($mpsoc_ip);			
+    $ip->add_ip($mpsoc_ip);            
     my $soc =get_source_set_top($self,$type);    
     my $infc = interface->interface_new(); 
-           
-    
     set_gui_status($soc,"ideal",0);
     # A tree view for holding a library
-	my %tree_text;
-	my @categories= ('Source');
+    my %tree_text;
+    my @categories= ('Source');
     foreach my $p (@categories)
     {
-   		my @modules= $ip->get_modules($p);
-   		$tree_text{$p}=\@modules;	
+        my @modules= $ip->get_modules($p);
+        $tree_text{$p}=\@modules;    
     }
-   
-	my $tree_box = create_tree ($soc,'IP list', $info,\%tree_text,\&tmp,\&add_module_to_mpsoc);
+    my $tree_box = create_tree ($soc,'IP list', $info,\%tree_text,\&tmp,\&add_module_to_mpsoc);
     my  $device_win=show_active_dev($soc,$ip,$infc,$info); 
     my $h1=gen_hpaned($tree_box,.15,$device_win);
     $table->attach_defaults ($h1,0, 10, 0, 10);
-	
     my $event =Event->timer (after => 1, interval => 1, cb => sub { 
-
-my ($state,$timeout)= get_gui_status($soc);
-	        
-	
-	        if ($timeout>0){
-	            $timeout--;
-	            set_gui_status($soc,$state,$timeout);                        
-	        }
-	        elsif( $state ne "ideal" ){
-	          
-	           #check if top is removed add it
-				my @instances=$soc->soc_get_all_instances();
-				my $redefine =1;
-				foreach my $inst (@instances){
-					$redefine = 0 if ($inst eq 'TOP');
-				}
-				if($redefine == 1){
-					my $ip = ip->lib_new ();
-					#print "get_top_ip(\$self,$type);\n";
-			    	my $mpsoc_ip=get_top_ip($self,$type);
-			    	
-					$ip->add_ip($mpsoc_ip);	
-			    	$soc ->object_add_attribute('SOURCE_SET',"IP",$mpsoc_ip);    	
-			    	$self->object_add_attribute('SOURCE_SET',"REDEFINE_TOP",0);  
-			    	add_mpsoc_to_device($soc,$ip); 
-			    	$self->object_add_attribute('SOURCE_SET',"SOC",$soc);					
-				}
-				
-	            $device_win->destroy;
-	           
-	            $device_win=show_active_dev($soc,$ip,$infc,$info); 
-	            $h1 -> pack2($device_win, TRUE, TRUE);  
-				$h1 -> show_all; 
-	            $table->show_all();	
-	            $device_win->show_all();
-	             
-	            $self->object_add_attribute('SOURCE_SET',"SOC",$soc);       
-	            set_gui_status($soc,"ideal",0);
-	             
-	        }    
-	        return TRUE;
-
-
- });
-  
- 	my $mtable = def_table(10, 5, FALSE);
-	$mtable->attach_defaults($scrolled_win,0,5,0,9);
-	$mtable->attach($back,0,1,9,10,'expand','fill',2,2) if($type ne 'soc');
-	$mtable->attach($diagram,2,4,9,10,'expand','fill',2,2);
-	$mtable->attach($ok,4,5,9,10,'expand','fill',2,2);
-	
-	$window->add ($mtable);
-	$window->show_all();
-	$self->object_add_attribute('SOURCE_SET',"SOC",$soc);
-	$back-> signal_connect("clicked" => sub{ 			
-		$self->object_add_attribute('SOURCE_SET',"SOC",$soc);		
-		clk_setting_win1($self,$info,$type);
-		$window->destroy;
-		$event->cancel;				
-	});	
-	
-	$diagram-> signal_connect("clicked" => sub{ 
-		show_tile_diagram ($soc);
-	});
-	
-	$ok-> signal_connect("clicked" => sub{ 	
-		set_gui_status($self,"ref",1); 			
-		$window->destroy;
-        $event->cancel;						
-	});	
-	
-	  
- 
-	
-	
-	
+        my ($state,$timeout)= get_gui_status($soc);
+        if ($timeout>0){
+            $timeout--;
+            set_gui_status($soc,$state,$timeout);
+        }
+        elsif( $state ne "ideal" ){
+            #check if top is removed add it
+            my @instances=$soc->soc_get_all_instances();
+            my $redefine =1;
+            foreach my $inst (@instances){
+                $redefine = 0 if ($inst eq 'TOP');
+            }
+            if($redefine == 1){
+                my $ip = ip->lib_new ();
+                #print "get_top_ip(\$self,$type);\n";
+                my $mpsoc_ip=get_top_ip($self,$type);
+                $ip->add_ip($mpsoc_ip);    
+                $soc ->object_add_attribute('SOURCE_SET',"IP",$mpsoc_ip);        
+                $self->object_add_attribute('SOURCE_SET',"REDEFINE_TOP",0);  
+                add_mpsoc_to_device($soc,$ip); 
+                $self->object_add_attribute('SOURCE_SET',"SOC",$soc);
+            }
+            $device_win->destroy;
+            $device_win=show_active_dev($soc,$ip,$infc,$info); 
+            $h1 -> pack2($device_win, TRUE, TRUE);  
+            $h1 -> show_all; 
+            $table->show_all();
+            $device_win->show_all();
+            $self->object_add_attribute('SOURCE_SET',"SOC",$soc);       
+            set_gui_status($soc,"ideal",0);
+        }
+        return TRUE;
+    });
+    my $mtable = def_table(10, 5, FALSE);
+    $mtable->attach_defaults($scrolled_win,0,5,0,9);
+    $mtable->attach($back,0,1,9,10,'expand','fill',2,2) if($type ne 'soc');
+    $mtable->attach($diagram,2,4,9,10,'expand','fill',2,2);
+    $mtable->attach($ok,4,5,9,10,'expand','fill',2,2);
+    $window->add ($mtable);
+    $window->show_all();
+    $self->object_add_attribute('SOURCE_SET',"SOC",$soc);
+    $back-> signal_connect("clicked" => sub{             
+        $self->object_add_attribute('SOURCE_SET',"SOC",$soc);        
+        clk_setting_win1($self,$info,$type);
+        $window->destroy;
+        $event->cancel;
+    });
+    $diagram-> signal_connect("clicked" => sub{ 
+        show_tile_diagram ($soc);
+    });
+    
+    $ok-> signal_connect("clicked" => sub{     
+        set_gui_status($self,"ref",1);             
+        $window->destroy;
+        $event->cancel;                        
+    });
 }
 
 sub tmp{
-	
+    
 }
 
 sub add_module_to_mpsoc{
-	my ($soc,$category,$module,$info)=@_;
-	my $ip = ip->lib_new ();
-	
-	my ($instance_id,$id)= get_instance_id($soc,$category,$module);
-	
-	#add module instance
-	my $result=$soc->soc_add_instance($instance_id,$category,$module,$ip);
-	
-	if($result == 0){
-		my $info_text= "Failed to add \"$instance_id\" to SoC. $instance_id is already exist.";	 
-		show_info($info,$info_text); 
-		return;
-	}
-	$soc->soc_add_instance_order($instance_id);
-	# Add IP version 
-	my $v=$ip->ip_get($category,$module,"version"); 
-	$v = 0 if(!defined $v);
-	#print "$v\n";
-	$soc->object_add_attribute($instance_id,"version",$v);
-	# Read default parameter from lib and add them to soc
-	my %param_default= $ip->get_param_default($category,$module);
-	
-	my $rr=$soc->soc_add_instance_param($instance_id,\%param_default);
-	if($rr == 0){
-		my $info_text= "Failed to add default parameter to \"$instance_id\".  $instance_id does not exist.";	 
-		show_info($info,$info_text); 
-		return;
-	}
-	my @r=$ip->ip_get_param_order($category,$module);
-	$soc->soc_add_instance_param_order($instance_id,\@r);
-	
-	get_module_parameter($soc,$ip,$instance_id);
-	undef $ip;
-	set_gui_status($soc,"refresh_soc",0);	
+    my ($soc,$category,$module,$info)=@_;
+    my $ip = ip->lib_new ();
+    my ($instance_id,$id)= get_instance_id($soc,$category,$module);
+    # add module instance
+    my $result=$soc->soc_add_instance($instance_id,$category,$module,$ip);
+    if($result == 0){
+        my $info_text= "Failed to add \"$instance_id\" to SoC. $instance_id is already exist.";     
+        show_info($info,$info_text); 
+        return;
+    }
+    $soc->soc_add_instance_order($instance_id);
+    # Add IP version 
+    my $v=$ip->ip_get($category,$module,"version"); 
+    $v = 0 if(!defined $v);
+    #print "$v\n";
+    $soc->object_add_attribute($instance_id,"version",$v);
+    # Read default parameter from lib and add them to soc
+    my %param_default= $ip->get_param_default($category,$module);
+    my $rr=$soc->soc_add_instance_param($instance_id,\%param_default);
+    if($rr == 0){
+        my $info_text= "Failed to add default parameter to \"$instance_id\".  $instance_id does not exist.";     
+        show_info($info,$info_text); 
+        return;
+    }
+    my @r=$ip->ip_get_param_order($category,$module);
+    $soc->soc_add_instance_param_order($instance_id,\@r);
+    get_module_parameter($soc,$ip,$instance_id);
+    undef $ip;
+    set_gui_status($soc,"refresh_soc",0);    
 } 
 
-
-
-
 #$mpsoc,$top_ip,$sw_dir,$soc_name,$id,$soc_num,$txview
 sub get_top_ip{
-	my ($self,$type)=@_;	
-	
-	my $mpsoc_ip=ip_gen->ip_gen_new();
-	$mpsoc_ip->ipgen_add("module_name",'TOP');
-	$mpsoc_ip->ipgen_add("ip_name",'TOP');
-	$mpsoc_ip->ipgen_add("category",'TOP');
-	$mpsoc_ip->ipgen_add('GUI_REMOVE_SET','DISABLE');
-	if($type eq 'mpsoc'){
-		my @sources=('clk','reset');
-		foreach my $s (@sources){
-			my $num = $self->object_get_attribute('SOURCE_SET',"${s}_number");
-			$num=1 if(!defined $num);
-			$mpsoc_ip->ipgen_add_plug("$s",'num',$num);
-			for (my $n=0; $n<$num; $n++ ){
-				
-				my $name=$self->object_get_attribute('SOURCE_SET',"${s}_${n}_name");
-				$mpsoc_ip->ipgen_set_plug_name($s,$n,$name);			
-				$mpsoc_ip->ipgen_add_port($name,undef,'input',"plug:${s}\[$n\]","${s}_i");	
-								
-			}	
-		}
-	# add_mpsoc_ip_other_interfaces($mpsoc,$mpsoc_ip);	
-	}
-	else{
-		my %sources = get_soc_clk_source_list($self);
-		foreach my $s (sort keys %sources){
-			my @ports = @{$sources{$s}} if (defined $sources{$s});
-			my $num=scalar @ports;
-			$mpsoc_ip->ipgen_add_plug("$s",'num',$num);
-			my $n=0;	
-			foreach my $p (@ports){
-				$mpsoc_ip->ipgen_set_plug_name($s,$n,$p);
-				$mpsoc_ip->ipgen_add_port($p,undef,'input',"plug:${s}\[$n\]","${s}_i");
-				$n++;
-			} 
-		}
-	}
-	return $mpsoc_ip;			
+    my ($self,$type)=@_;    
+    my $mpsoc_ip=ip_gen->ip_gen_new();
+    $mpsoc_ip->ipgen_add("module_name",'TOP');
+    $mpsoc_ip->ipgen_add("ip_name",'TOP');
+    $mpsoc_ip->ipgen_add("category",'TOP');
+    $mpsoc_ip->ipgen_add('GUI_REMOVE_SET','DISABLE');
+    if($type eq 'mpsoc'){
+        my @sources=('clk','reset');
+        foreach my $s (@sources){
+            my $num = $self->object_get_attribute('SOURCE_SET',"${s}_number");
+            $num=1 if(!defined $num);
+            $mpsoc_ip->ipgen_add_plug("$s",'num',$num);
+            for (my $n=0; $n<$num; $n++ ){
+                my $name=$self->object_get_attribute('SOURCE_SET',"${s}_${n}_name");
+                $mpsoc_ip->ipgen_set_plug_name($s,$n,$name);            
+                $mpsoc_ip->ipgen_add_port($name,undef,'input',"plug:${s}\[$n\]","${s}_i");    
+            }    
+        }
+    # add_mpsoc_ip_other_interfaces($mpsoc,$mpsoc_ip);    
+    }
+    else{
+        my %sources = get_soc_clk_source_list($self);
+        foreach my $s (sort keys %sources){
+            my @ports = @{$sources{$s}} if (defined $sources{$s});
+            my $num=scalar @ports;
+            $mpsoc_ip->ipgen_add_plug("$s",'num',$num);
+            my $n=0;    
+            foreach my $p (@ports){
+                $mpsoc_ip->ipgen_set_plug_name($s,$n,$p);
+                $mpsoc_ip->ipgen_add_port($p,undef,'input',"plug:${s}\[$n\]","${s}_i");
+                $n++;
+            } 
+        }
+    }
+    return $mpsoc_ip;
 }
 
 
 sub add_mpsoc_ip_other_interfaces{
-	my ($mpsoc,$mpsoc_ip)=@_;	
-my ($NE, $NR, $RAw, $EAw, $Fw)= get_topology_info ($mpsoc); 
+    my ($mpsoc,$mpsoc_ip)=@_;    
+    my ($NE, $NR, $RAw, $EAw, $Fw)= get_topology_info ($mpsoc); 
     my $processors_en=0;
     my %intfc_num;
     my @parameters_order;
-	for (my $tile_num=0;$tile_num<$NE;$tile_num++){
-			my ($soc_name,$n,$soc_num)=$mpsoc->mpsoc_get_tile_soc_name($tile_num);	
-	
-	
-			my $top=$mpsoc->mpsoc_get_soc($soc_name);
-			my @nis=get_NI_instance_list($top);
-			my @noc_param=$top->top_get_parameter_list($nis[0]);
-			my $inst_name=$top->top_get_def_of_instance($nis[0],'instance');
-	
-			#other parameters
-			my %params=$top->top_get_default_soc_param();
-	
-			my @intfcs=$top->top_get_intfc_list();
-			
-			my $i=0;
-		
-			my $dir = Cwd::getcwd();
-			my $mpsoc_name=$mpsoc->object_get_attribute('mpsoc_name');
-			my $target_dir  = "$ENV{'PRONOC_WORK'}/MPSOC/$mpsoc_name";
-			my $soc_file="$target_dir/src_verilog/tiles/$soc_name.sv";
-					
-			my $vdb =read_verilog_file($soc_file);
-				
-			my %soc_localparam = $vdb->get_modules_parameters($soc_name);
-		
-			
-			foreach my $intfc (@intfcs){
-		
-				# Auto connected/not connected interface	
-				if( $intfc eq 'socket:ni[0]' || ($intfc =~ /plug:clk\[/) ||  ( $intfc =~ /plug:reset\[/)|| ($intfc =~ /socket:RxD_sim\[/ )  || $intfc =~ /plug:enable\[/){
-					#do nothing
-				}
-				elsif( $intfc eq 'IO' ){
-					my @ports=$top->top_get_intfc_ports_list($intfc);
-					foreach my $p (@ports){
-						my ($io_port,$type,$new_range,$intfc_name,$intfc_port)=	get_top_port_io_info($top,$p,$tile_num,\%params,\%soc_localparam);
-						$mpsoc_ip->ipgen_add_port($io_port,$new_range,$type,'IO','IO');	
-						
-								
-					}			
-					
-				}
-	
-				else {
-				#other interface
-				    my($if_type,$if_name,$if_num)= split("[:\[ \\]]", $intfc); 
-				    print "my($if_type,$if_name,$if_num)= split(, $intfc); \n";
-				    my $num = (defined $intfc_num{"$if_type:$if_name"})? $intfc_num{"$if_type:$if_name"}+1:0;
-				    $intfc_num{"$if_type:$if_name"}=$num;
-				    $mpsoc_ip->ipgen_add_plug("$if_name",'num',$num) if ($if_type eq 'plug');
-				    $mpsoc_ip->ipgen_add_soket("$if_name",'num',$num) if ($if_type eq 'socket');
-				   				    
-					my @ports=$top->top_get_intfc_ports_list($intfc);
-					foreach my $p (@ports){
-						my ($io_port,$type,$new_range,$intfc_name,$intfc_port)=	get_top_port_io_info($top,$p,$tile_num,\%params,\%soc_localparam);
-						$mpsoc_ip->ipgen_add_port($io_port,$new_range,$type,"$if_type:$if_name\[$num\]",$intfc_port);	
-									
-					}			
-				}			
-			}
-			
-			
-		my $setting=$mpsoc->mpsoc_get_tile_param_setting($tile_num);
-		#if ($setting eq 'Custom'){
-			 %params= $top->top_get_custom_soc_param($tile_num);
-		#}else{
-		#	 %params=$top->top_get_default_soc_param();
-		#}
-		
-		foreach my $p (sort keys %params){
-			$params{$p}=add_instantc_name_to_parameters(\%params,"T$tile_num",$params{$p});	
-			$params{$p}=add_instantc_name_to_parameters(\%soc_localparam,"T$tile_num",$params{$p});	
-			my $pname="T${tile_num}_$p";
-			$mpsoc_ip->	ipgen_add_parameter ($pname,$params{$p},'Fixed',undef,undef,'Localparam',1);	
-			push (@parameters_order,$pname);
-		
-		}		
-		foreach my $p (sort keys %soc_localparam){
-			$soc_localparam{$p}=add_instantc_name_to_parameters(\%params,"T$tile_num",$soc_localparam{$p});		
-			$soc_localparam{$p}=add_instantc_name_to_parameters(\%soc_localparam,"T$tile_num",$soc_localparam{$p});		
-			my $pname="T${tile_num}_$p";
-			$mpsoc_ip->	ipgen_add_parameter ($pname,$soc_localparam{$p},'Fixed',undef,undef,'Localparam',0);	
-			push (@parameters_order,$pname);
-			
-		}
-			
-	
-	
-	}	
-	#TODO get parameter order
-	$mpsoc_ip->ipgen_add("parameters_order",\@parameters_order); 	
-	
+    for (my $tile_num=0;$tile_num<$NE;$tile_num++){
+            my ($soc_name,$n,$soc_num)=$mpsoc->mpsoc_get_tile_soc_name($tile_num);    
+            my $top=$mpsoc->mpsoc_get_soc($soc_name);
+            my @nis=get_NI_instance_list($top);
+            my @noc_param=$top->top_get_parameter_list($nis[0]);
+            my $inst_name=$top->top_get_def_of_instance($nis[0],'instance');
+            #other parameters
+            my %params=$top->top_get_default_soc_param();
+            my @intfcs=$top->top_get_intfc_list();
+            my $i=0;
+            my $dir = Cwd::getcwd();
+            my $mpsoc_name=$mpsoc->object_get_attribute('mpsoc_name');
+            my $target_dir  = "$ENV{'PRONOC_WORK'}/MPSOC/$mpsoc_name";
+            my $soc_file="$target_dir/src_verilog/tiles/$soc_name.sv";
+            my $vdb =read_verilog_file($soc_file);
+            my %soc_localparam = $vdb->get_modules_parameters($soc_name);
+            foreach my $intfc (@intfcs){
+                # Auto connected/not connected interface    
+                if( $intfc eq 'socket:ni[0]' || ($intfc =~ /plug:clk\[/) ||  ( $intfc =~ /plug:reset\[/)|| ($intfc =~ /socket:RxD_sim\[/ )  || $intfc =~ /plug:enable\[/){
+                    #do nothing
+                }
+                elsif( $intfc eq 'IO' ){
+                    my @ports=$top->top_get_intfc_ports_list($intfc);
+                    foreach my $p (@ports){
+                        my ($io_port,$type,$new_range,$intfc_name,$intfc_port)=    get_top_port_io_info($top,$p,$tile_num,\%params,\%soc_localparam);
+                        $mpsoc_ip->ipgen_add_port($io_port,$new_range,$type,'IO','IO');    
+                    }            
+                }
+                else {
+                #other interface
+                    my($if_type,$if_name,$if_num)= split("[:\[ \\]]", $intfc); 
+                    print "my($if_type,$if_name,$if_num)= split(, $intfc); \n";
+                    my $num = (defined $intfc_num{"$if_type:$if_name"})? $intfc_num{"$if_type:$if_name"}+1:0;
+                    $intfc_num{"$if_type:$if_name"}=$num;
+                    $mpsoc_ip->ipgen_add_plug("$if_name",'num',$num) if ($if_type eq 'plug');
+                    $mpsoc_ip->ipgen_add_soket("$if_name",'num',$num) if ($if_type eq 'socket');
+                    my @ports=$top->top_get_intfc_ports_list($intfc);
+                    foreach my $p (@ports){
+                        my ($io_port,$type,$new_range,$intfc_name,$intfc_port)=    get_top_port_io_info($top,$p,$tile_num,\%params,\%soc_localparam);
+                        $mpsoc_ip->ipgen_add_port($io_port,$new_range,$type,"$if_type:$if_name\[$num\]",$intfc_port);    
+                    }            
+                }            
+            }
+        my $setting=$mpsoc->mpsoc_get_tile_param_setting($tile_num);
+        #if ($setting eq 'Custom'){
+        %params= $top->top_get_custom_soc_param($tile_num);
+        #}else{
+        #     %params=$top->top_get_default_soc_param();
+        #}
+        foreach my $p (sort keys %params){
+            $params{$p}=add_instantc_name_to_parameters(\%params,"T$tile_num",$params{$p});    
+            $params{$p}=add_instantc_name_to_parameters(\%soc_localparam,"T$tile_num",$params{$p});    
+            my $pname="T${tile_num}_$p";
+            $mpsoc_ip->    ipgen_add_parameter ($pname,$params{$p},'Fixed',undef,undef,'Localparam',1);    
+            push (@parameters_order,$pname);
+        }        
+        foreach my $p (sort keys %soc_localparam){
+            $soc_localparam{$p}=add_instantc_name_to_parameters(\%params,"T$tile_num",$soc_localparam{$p});        
+            $soc_localparam{$p}=add_instantc_name_to_parameters(\%soc_localparam,"T$tile_num",$soc_localparam{$p});        
+            my $pname="T${tile_num}_$p";
+            $mpsoc_ip->    ipgen_add_parameter ($pname,$soc_localparam{$p},'Fixed',undef,undef,'Localparam',0);    
+            push (@parameters_order,$pname);
+            
+        }
+    }    
+    #TODO get parameter order
+    $mpsoc_ip->ipgen_add("parameters_order",\@parameters_order);     
 }
 
 sub get_source_set_top{
-	my ($self,$type)=@_;
-	my $soc =$self->object_get_attribute('SOURCE_SET',"SOC");
+    my ($self,$type)=@_;
+    my $soc =$self->object_get_attribute('SOURCE_SET',"SOC");
     my $redefine =$self->object_get_attribute('SOURCE_SET',"REDEFINE_TOP");
     $redefine=1 if(!defined $redefine);
     if(!defined $soc){
-    	$soc = soc->soc_new();     	
-    	$soc->object_add_attribute('soc_name','TOP'); 
-    	$redefine=1;    	
+        $soc = soc->soc_new();         
+        $soc->object_add_attribute('soc_name','TOP'); 
+        $redefine=1;        
     }
     if($redefine==1){
-    	my $ip = ip->lib_new ();
-    	#print "get_top_ip(\$self,$type);\n";
-    	my $mpsoc_ip=get_top_ip($self,$type);
-    	
-		$ip->add_ip($mpsoc_ip);	
-    	$soc ->object_add_attribute('SOURCE_SET',"IP",$mpsoc_ip);    	
-    	$self->object_add_attribute('SOURCE_SET',"REDEFINE_TOP",0);  
-    	add_mpsoc_to_device($soc,$ip); 
-    	$self->object_add_attribute('SOURCE_SET',"SOC",$soc);
-    }		
-	return $soc;	
+        my $ip = ip->lib_new ();
+        #print "get_top_ip(\$self,$type);\n";
+        my $mpsoc_ip=get_top_ip($self,$type);
+        $ip->add_ip($mpsoc_ip);    
+        $soc ->object_add_attribute('SOURCE_SET',"IP",$mpsoc_ip);        
+        $self->object_add_attribute('SOURCE_SET',"REDEFINE_TOP",0);  
+        add_mpsoc_to_device($soc,$ip); 
+        $self->object_add_attribute('SOURCE_SET',"SOC",$soc);
+    }        
+    return $soc;    
 }
 
 
 sub add_mpsoc_to_device{
-	my ($soc,$ip)=@_;
-	my $category='TOP';
-	my $module='TOP';
-	my ($instance_id,$id) =('TOP',1);
-	
-	#my ($instance_id,$id)= get_instance_id($soc,$category,$module);
-	
-	remove_instance_from_soc($soc,$instance_id);
-	
-	#add module instanance
-	my $result=$soc->soc_add_instance($instance_id,$category,$module,$ip);
-	
-	if($result == 0){
-		my $info_text= "Failed to add \"$instance_id\" to SoC. $instance_id is already exist.";	 
-	#	show_info($info,$info_text); 
-		return;
-	}
-	$soc->soc_add_instance_order($instance_id);
-	# Add IP version 
-	my $v=$ip->ip_get($category,$module,"version"); 
-	$v = 0 if(!defined $v);
-	#print "$v\n";
-	$soc->object_add_attribute($instance_id,"version",$v);
-	# Read default parameter from lib and add them to soc
-	my %param_default= $ip->get_param_default($category,$module);
-	
-	my $rr=$soc->soc_add_instance_param($instance_id,\%param_default);
-	if($rr == 0){
-		my $info_text= "Failed to add default parameter to \"$instance_id\".  $instance_id does not exist.";	 
-	#	show_info($info,$info_text); 
-		return;
-	}
-	my @r=$ip->ip_get_param_order($category,$module);
-	$soc->soc_add_instance_param_order($instance_id,\@r);
-	
-	#get_module_parameter($soc,$ip,$instance_id);
-	undef $ip;
-	set_gui_status($soc,"refresh_soc",0);	
+    my ($soc,$ip)=@_;
+    my $category='TOP';
+    my $module='TOP';
+    my ($instance_id,$id) =('TOP',1);
+    #my ($instance_id,$id)= get_instance_id($soc,$category,$module);
+    remove_instance_from_soc($soc,$instance_id);
+    # add module instanance
+    my $result=$soc->soc_add_instance($instance_id,$category,$module,$ip);
+    if($result == 0){
+        my $info_text= "Failed to add \"$instance_id\" to SoC. $instance_id is already exist.";     
+    #    show_info($info,$info_text); 
+        return;
+    }
+    $soc->soc_add_instance_order($instance_id);
+    # Add IP version 
+    my $v=$ip->ip_get($category,$module,"version"); 
+    $v = 0 if(!defined $v);
+    #print "$v\n";
+    $soc->object_add_attribute($instance_id,"version",$v);
+    # Read default parameter from lib and add them to soc
+    my %param_default= $ip->get_param_default($category,$module);
+    my $rr=$soc->soc_add_instance_param($instance_id,\%param_default);
+    if($rr == 0){
+        my $info_text= "Failed to add default parameter to \"$instance_id\".  $instance_id does not exist.";     
+    #    show_info($info,$info_text); 
+        return;
+    }
+    my @r=$ip->ip_get_param_order($category,$module);
+    $soc->soc_add_instance_param_order($instance_id,\@r);
+    
+    #get_module_parameter($soc,$ip,$instance_id);
+    undef $ip;
+    set_gui_status($soc,"refresh_soc",0);    
 } 
 
 ######
@@ -3118,19 +2835,16 @@ sub add_mpsoc_to_device{
 ######
 
 sub ctrl_box{
-	my ($mpsoc,$info)=@_;
-	my $table = def_table (1, 12, FALSE);	 
-	my $generate = def_image_button('icons/gen.png','_Generate RTL',FALSE,1);  
+    my ($mpsoc,$info)=@_;
+    my $table = def_table (1, 12, FALSE);     
+    my $generate = def_image_button('icons/gen.png','_Generate RTL',FALSE,1);
     my $compile  = def_image_button('icons/gate.png','_Compile RTL',FALSE,1);
-    my $software = def_image_button('icons/binary.png','_Software',FALSE,1);   
+    my $software = def_image_button('icons/binary.png','_Software',FALSE,1);
     my $diagram  = def_image_button('icons/diagram.png','Diagram');
-    my $clk=  def_image_button('icons/clk.png','CLK setting');	
-
-	my $row=0;
-
-
-	my $target_dir= "$ENV{'PRONOC_WORK'}/MPSOC";    
-	my ($entrybox,$entry ) =gen_save_load_widget (
+    my $clk=  def_image_button('icons/clk.png','CLK setting');
+    my $row=0;
+    my $target_dir= "$ENV{'PRONOC_WORK'}/MPSOC";
+    my ($entrybox,$entry ) =gen_save_load_widget (
         $mpsoc, #the object 
         "MPSoC name",#the label shown for setting configuration
         'mpsoc_name',#the key name for saveing the setting configuration in object 
@@ -3139,22 +2853,19 @@ sub ctrl_box{
         'mpsoc',#check the given name match the SoC or mpsoc name rules
         'lib/mpsoc',#where the current configuration seting file is saved
         'MPSOC',#the extenstion given for configuration seting file
-		\&load_mpsoc,#refrence to load function
-		$info
+        \&load_mpsoc,#refrence to load function
+        $info
         );
-  
     $table->attach ($entrybox,$row, $row+2, 0,1,'expand','shrink',2,2);$row+=2;
     $table->attach ($diagram, $row, $row+1, 0,1,'expand','shrink',2,2);$row++;
     $table->attach ($clk, $row, $row+1, 0,1,'expand','shrink',2,2);$row++;    
     $table->attach ($generate, $row, $row+1, 0,1,'expand','shrink',2,2);$row++;
     $table->attach ($software, $row, $row+1, 0,1,'expand','shrink',2,2);$row++;    
     $table->attach ($compile, $row, $row+1, 0,1,'expand','shrink',2,2);$row++;
-	
-	$generate-> signal_connect("clicked" => sub{ 
+    $generate-> signal_connect("clicked" => sub{ 
         generate_mpsoc($mpsoc,$info,1);
         set_gui_status($mpsoc,"refresh_soc",1);
     });
-
     $compile -> signal_connect("clicked" => sub{ 
         $mpsoc->object_add_attribute('compile','compilers',"QuartusII,Vivado,Verilator,Modelsim");
         my $name=$mpsoc->object_get_attribute('mpsoc_name');
@@ -3166,45 +2877,39 @@ sub ctrl_box{
         my $target_dir  = "$ENV{'PRONOC_WORK'}/MPSOC/$name";
         my $top_file     = "$target_dir/src_verilog/${name}_top.v";
         if (-f $top_file){  
-        	my $answer = yes_no_dialog ("Do you want to Regenearte the MPSoC RTL code too?");  
+            my $answer = yes_no_dialog ("Do you want to Regenearte the MPSoC RTL code too?");  
             generate_mpsoc($mpsoc,$info,0) if ($answer eq 'yes');
             select_compiler($mpsoc,$name,$top_file,$target_dir);
         } else {
             message_dialog("Cannot find $top_file file. Please run RTL Generator first!");
             return;
         }
-    });    
-    
+    });
     $software -> signal_connect("clicked" => sub{
-    	my $name=$mpsoc->object_get_attribute('mpsoc_name');
-    	$name="" if (!defined $name);
-    	if (length($name)==0){
+        my $name=$mpsoc->object_get_attribute('mpsoc_name');
+        $name="" if (!defined $name);
+        if (length($name)==0){
             message_dialog("Please define the MPSoC name!");
             return ;
         }
-    	my $target_dir  = "$ENV{'PRONOC_WORK'}/MPSOC/$name";
-    	my $sw_folder = "$target_dir/sw";
-    	unless (-d $sw_folder){  
-    		message_dialog("Cannot find $sw_folder. Please run RTL Generator first!");
-    		return;
-    	}
+        my $target_dir  = "$ENV{'PRONOC_WORK'}/MPSOC/$name";
+        my $sw_folder = "$target_dir/sw";
+        unless (-d $sw_folder){  
+            message_dialog("Cannot find $sw_folder. Please run RTL Generator first!");
+            return;
+        }
         software_edit_mpsoc($mpsoc);
-
     });
-
     $diagram-> signal_connect("clicked" => sub{ 
         show_topology_diagram ($mpsoc);
     });
     
-	
-	$clk-> signal_connect("clicked" => sub{ 
-			clk_setting_win1($mpsoc,$info,'mpsoc');	
-	});
-	
-	return $table;	
+    $clk-> signal_connect("clicked" => sub{ 
+        clk_setting_win1($mpsoc,$info,'mpsoc');
+    });
+    return $table;
 }
 
-
 sub gen_save_load_widget {
     my (
         $self, #the object 
@@ -3217,64 +2922,57 @@ sub gen_save_load_widget {
         $extention,#the extenstion given for configuration seting file
         $load_func,
         $info
-        )=@_;
+    )=@_;
     my $load = def_image_button('icons/load2.png');
     my $entry=gen_entry_object($self,$param_name,undef,undef,undef,undef);
     my $entrybox=gen_label_info("$label:",$entry);
-    my $save      = def_image_button('icons/save.png');	
+    my $save  = def_image_button('icons/save.png');    
     my $open_dir  = def_image_button('icons/open-folder.png') if (defined $target_dir);
     set_tip($save, "Save current $full_name configuration setting");
-	set_tip($load, "Load a saved $full_name configuration setting");
-	set_tip($open_dir, "Open target $full_name folder") if (defined $target_dir);
-    	
-	$entrybox->pack_start( $save, FALSE, FALSE, 0);
-	$entrybox->pack_start( $load, FALSE, FALSE, 0);
-	$entrybox->pack_start( $open_dir , FALSE, FALSE, 0) if (defined $target_dir);
-
-    $open_dir-> signal_connect("clicked" => sub{     	
-		my $name=$self->object_get_attribute($param_name);
+    set_tip($load, "Load a saved $full_name configuration setting");
+    set_tip($open_dir, "Open target $full_name folder") if (defined $target_dir);
+    $entrybox->pack_start( $save, FALSE, FALSE, 0);
+    $entrybox->pack_start( $load, FALSE, FALSE, 0);
+    $entrybox->pack_start( $open_dir , FALSE, FALSE, 0) if (defined $target_dir);
+    $open_dir-> signal_connect("clicked" => sub{
+        my $name=$self->object_get_attribute($param_name);
         $name="" if (!defined $name);
         if (length($name)==0){
             message_dialog("Please define the $label!");
             return ;
         }
         return if(check_mpsoc_name($name,$label) && $check=='mpsoc') ;
-		return if(check_soc_name($name,$label) && $check=='soc') ;	
+        return if(check_soc_name($name,$label) && $check=='soc') ;    
         unless (-d "$target_dir/$name"){
-			message_dialog("Cannot find $target_dir/$name.\n Please run RTL Generator first!",'error');
-			return;
-		}
-		system "xdg-open   $target_dir/$name";
-	})  if (defined $target_dir);
-
+            message_dialog("Cannot find $target_dir/$name.\n Please run RTL Generator first!",'error');
+            return;
+        }
+        system "xdg-open   $target_dir/$name";
+    })  if (defined $target_dir);
     $save-> signal_connect("clicked" => sub{ 
-    	my $name=$self->object_get_attribute($param_name);	
-         if (length($name)==0){
+        my $name=$self->object_get_attribute($param_name);    
+        if (length($name)==0){
             message_dialog("Please define the $label!");
             return ;
-        }	
-		return if(check_mpsoc_name($name,$label) && $check=='mpsoc') ;
-		return if(check_soc_name($name,$label) && $check=='soc') ;	
-		# Write object file
+        }
+        return if(check_mpsoc_name($name,$label) && $check=='mpsoc') ;
+        return if(check_soc_name($name,$label) && $check=='soc') ;    
+        # Write object file
         my $config_file = "${config_dir}/${name}.$extention";
-		open(FILE,  ">$config_file") || die "Can not open $config_file: $!";
-		print FILE perl_file_header("${name}.$extention");
-		print FILE Data::Dumper->Dump([\%$self],[$extention]);
-		close(FILE) || die "Error closing file: $!";
-		message_dialog("Current configuration  \"$name\" is saved as $config_file.");		
-    
+        open(FILE,  ">$config_file") || die "Can not open $config_file: $!";
+        print FILE perl_file_header("${name}.$extention");
+        print FILE Data::Dumper->Dump([\%$self],[$extention]);
+        close(FILE) || die "Error closing file: $!";
+        message_dialog("Current configuration  \"$name\" is saved as $config_file.");
     });
-
     $entry->signal_connect( 'changed'=> sub{
-		my $name=$entry->get_text();
-		$self->object_add_attribute ("save_as",undef,$name);	
-	});	
-
-    $load-> signal_connect("clicked" => sub{ 
+        my $name=$entry->get_text();
+        $self->object_add_attribute ("save_as",undef,$name);
+    });
+    $load-> signal_connect("clicked" => sub{
+        &$load_func($self,$info);
         set_gui_status($self,"ref",5);
-        &$load_func($self,$info);    
     });
-
     return ($entrybox,$entry);
 }
 
@@ -3285,68 +2983,55 @@ sub mpsocgen_main{
     my $infc = interface->interface_new(); 
     my $soc = ip->lib_new ();
     my $mpsoc= mpsoc->mpsoc_new();
-       
     set_gui_status($mpsoc,"ideal",0);
     my $main_table = def_table (25, 12, FALSE);
-    
     # The box which holds the info, warning, error ...  messages
-    my ($infobox,$info)= create_txview();    
-        
+    my ($infobox,$info)= create_txview();
     my $noc_conf_box=get_config ($mpsoc,$info);
     my $noc_tiles=gen_tiles($mpsoc);
-   
-
     $main_table->set_row_spacings (4);
     $main_table->set_col_spacings (1);
-    my $ctrl=ctrl_box($mpsoc,$info);    
+    my $ctrl=ctrl_box($mpsoc,$info);
     my $h1=gen_hpaned($noc_conf_box,.3,$noc_tiles);
     my $v2=gen_vpaned($h1,.55,$infobox);
-	my $row=0;
+    my $row=0;
     $main_table->attach_defaults ($v2  , 0, 12, 0,24);
     #$main_table->attach_defaults ($ctrl,0, 12, 24,25);
     $main_table->attach ($ctrl,0, 12, 24,25, 'fill','fill',2,2);
-
     #check soc status every 0.5 second. refresh device table if there is any changes 
     Glib::Timeout->add (100, sub{ 
         my ($state,$timeout)= get_gui_status($mpsoc);
         if ($timeout>0){
             $timeout--;
-            set_gui_status($mpsoc,$state,$timeout);                        
+            set_gui_status($mpsoc,$state,$timeout); 
         }elsif ($state eq 'save_project'){
             # Write object file
             my $name=$mpsoc->object_get_attribute('mpsoc_name');
             open(FILE,  ">lib/mpsoc/$name.MPSOC") || die "Can not open: $!";
             print FILE perl_file_header("$name.MPSOC");
             print FILE Data::Dumper->Dump([\%$mpsoc],[$name]);
-            close(FILE) || die "Error closing file: $!";           
-            set_gui_status($mpsoc,"ideal",0);    
+            close(FILE) || die "Error closing file: $!";
+            set_gui_status($mpsoc,"ideal",0);
         }
         elsif( $state ne "ideal" ){
             $noc_conf_box->destroy();
             $noc_conf_box=get_config ($mpsoc,$info);
             $noc_tiles->destroy();
-            $noc_tiles=gen_tiles($mpsoc);            
-            $h1 -> pack1($noc_conf_box, TRUE, TRUE);     
-            $h1 -> pack2($noc_tiles, TRUE, TRUE);         
-            $v2-> pack1($h1, TRUE, TRUE);     
+            $noc_tiles=gen_tiles($mpsoc);
+            $h1 -> pack1($noc_conf_box, TRUE, TRUE);
+            $h1 -> pack2($noc_tiles, TRUE, TRUE);
+            $v2-> pack1($h1, TRUE, TRUE);
             $h1->show_all;
             $ctrl->destroy;
             $ctrl=ctrl_box($mpsoc,$info);
             $main_table->attach ($ctrl,0, 12, 24,25,'fill','fill',2,2);
             $main_table->show_all();
-                   
-            
             set_gui_status($mpsoc,"ideal",0);
-            
-            
-        }    
+        }
         return TRUE;
-        
     } );
-    
-    my $sc_win = add_widget_to_scrolled_win($main_table);    
-
+    my $sc_win = add_widget_to_scrolled_win($main_table);
     return $sc_win;
 }
 
-
+1
diff --git a/mpsoc/perl_gui/lib/perl/mpsoc_verilog_gen.pl b/mpsoc/perl_gui/lib/perl/mpsoc_verilog_gen.pl
index b025947..dc4a644 100755
--- a/mpsoc/perl_gui/lib/perl/mpsoc_verilog_gen.pl
+++ b/mpsoc/perl_gui/lib/perl/mpsoc_verilog_gen.pl
@@ -2,7 +2,6 @@
 use warnings;
 use FindBin;
 use lib $FindBin::Bin;
-
 use mpsoc;
 use soc;
 use ip;
@@ -10,959 +9,753 @@
 use Cwd;
 use rvp;
 
-
 sub mpsoc_generate_verilog{
-	my ($mpsoc,$sw_dir,$txview)=@_;
-	my $mpsoc_name=$mpsoc->object_get_attribute('mpsoc_name');
-	my $top_ip=ip_gen->top_gen_new();
-	
-	                                                                     
-	
-	
-	my $param_as_in_v;
-	# generate top 
-	
-	
-	
-	#generate socs_parameter
-	my $socs_param= gen_socs_param($mpsoc);
-	
-	#generate noc_parameter
-	my ($noc_param,$pass_param)=gen_noc_param_v($mpsoc);
-	
-	#generate the noc
-	my $noc_v=gen_noc_v($mpsoc,$pass_param);
-	
-	#generate socs	
-	my ($socs_v,$io_short,$io_full,$top_io_short,$top_io_full,$top_io_pass,$href)=gen_socs_v($mpsoc,$top_ip,$sw_dir,$txview);
-	my %jtag_info=%{$href};
-	my $jtag_v=add_jtag_ctrl (\%jtag_info,$txview); 
-	
-	my ($clk_set, $clk_io_sim,$clk_io_full, $clk_assigned_port)= get_top_clk_setting($mpsoc);
-   
-	$top_io_short=$top_io_short.",\n$clk_io_sim" if (defined $clk_io_sim);
-    $top_io_full=$top_io_full."\n$clk_io_full";            
+    my ($mpsoc,$sw_dir,$txview)=@_;
+    my $mpsoc_name=$mpsoc->object_get_attribute('mpsoc_name');
+    my $top_ip=ip_gen->top_gen_new();
+    my $param_as_in_v;
+    # generate top
+    #generate socs_parameter
+    my $socs_param= gen_socs_param($mpsoc);
+    #generate noc_parameter
+    my ($noc_param,$pass_param)=gen_noc_param_v($mpsoc);
+    #generate the noc
+    my $noc_v=gen_noc_v($mpsoc,$pass_param);
+    #generate socs
+    my ($socs_v,$io_short,$io_full,$top_io_short,$top_io_full,$top_io_pass,$href)=gen_socs_v($mpsoc,$top_ip,$sw_dir,$txview);
+    my %jtag_info=%{$href};
+    my $jtag_v=add_jtag_ctrl (\%jtag_info,$txview);
+    my ($clk_set, $clk_io_sim,$clk_io_full, $clk_assigned_port)= get_top_clk_setting($mpsoc);
+    $top_io_short=$top_io_short.",\n$clk_io_sim" if (defined $clk_io_sim);
+    $top_io_full=$top_io_full."\n$clk_io_full";
     $top_io_pass=$top_io_pass.",\n$clk_assigned_port" if (defined $clk_assigned_port);
-	
-	#functions
-	my $functions=get_functions();
-	$param_as_in_v = (defined $param_as_in_v)? "$param_as_in_v,\nparameter NOC_ID=0\n" : "parameter NOC_ID=0\n";
-	my $global_localparam=get_golal_param_v();	
-	my $pdef = "`include \"pronoc_def.v\"";
-	my $mpsoc_v = (defined $param_as_in_v )? " $pdef\nmodule $mpsoc_name\n\t  #(\n $param_as_in_v)(\n$io_short\n);\n\t`NOC_CONF": "$pdef\nmodule $mpsoc_name\n \t (\n$io_short\n);\n\t`NOC_CONF";
-	$mpsoc_v=$mpsoc_v. "
-$global_localparam	
+    #functions
+    my $functions=get_functions();
+    $param_as_in_v = (defined $param_as_in_v)? "$param_as_in_v,\nparameter NOC_ID=0\n" : "parameter NOC_ID=0\n";
+    my $global_localparam=get_golal_param_v();
+    my $pdef = "`include \"pronoc_def.v\"";
+    my $mpsoc_v = (defined $param_as_in_v )? " $pdef\nmodule $mpsoc_name\n\t  #(\n $param_as_in_v)(\n$io_short\n);\n\timport pronoc_pkg::*;": "$pdef\nmodule $mpsoc_name\n \t (\n$io_short\n);\n\timport pronoc_pkg::*;";
+    $mpsoc_v=$mpsoc_v. "
+$global_localparam
 $socs_param
 $io_full
 $noc_v
 $socs_v
 endmodule
 ";
-	
-	
-	my $top_v = (defined $param_as_in_v )? "$pdef\nmodule ${mpsoc_name}_top #(\n $param_as_in_v\n)(\n$top_io_short\n);\n": "$pdef\nmodule ${mpsoc_name}_top (\n $top_io_short\n);\n";
-
+    my $top_v = (defined $param_as_in_v )? "$pdef\nmodule ${mpsoc_name}_top #(\n $param_as_in_v\n)(\n$top_io_short\n);\n": "$pdef\nmodule ${mpsoc_name}_top (\n $top_io_short\n);\n";
 $top_v=$top_v."
-$global_localparam	
+$global_localparam
 $socs_param
 $top_io_full
 $clk_set
-$jtag_v	
+$jtag_v
 \t${mpsoc_name} the_${mpsoc_name} (
 $top_io_pass
-
 \t);
 endmodule
-";	
-
-
-
-	
-	
-#	my $mp=get_top_ip($mpsoc,'mpsoc');
-	
-#	mkpath("$dir/lib/ip/mpsoc/",1,01777);	
-#	open(FILE,  ">$dir/lib/ip/mpsoc/MPSOC.IP") || die "Can not open: $!";
-#	print FILE perl_file_header("MPSOC.IP");
-#	print FILE Data::Dumper->Dump([\%$mp],["ipgen"]);
-#	close(FILE) || die "Error closing file: $!";
-	
-	
-#	my ($mp_v,$top_v)=soc_generate_verilog($top_soc,"target_dir/sw1",$txview);
-
-
-	
-	#my $ins= gen_mpsoc_instance_v($mpsoc,$mpsoc_name,$param_pass_v);
-
-	#add_text_to_string(\$top_v,$local_param_v_all."\n".$io_full_v_all);
-	#add_text_to_string(\$top_v,$ins);
-	$mpsoc->object_add_attribute('top_ip',undef,$top_ip);
-	
-	my @chains = (sort { $b <=> $a } keys  %jtag_info);
-	$mpsoc->object_add_attribute('JTAG','M_CHAIN',$chains[0]);
-	
-	return ($mpsoc_v,$top_v,$noc_param);
+";
+#    my $mp=get_top_ip($mpsoc,'mpsoc');
+#    mkpath("$dir/lib/ip/mpsoc/",1,01777);
+#    open(FILE,  ">$dir/lib/ip/mpsoc/MPSOC.IP") || die "Can not open: $!";
+#    print FILE perl_file_header("MPSOC.IP");
+#    print FILE Data::Dumper->Dump([\%$mp],["ipgen"]);
+#    close(FILE) || die "Error closing file: $!";
+#    my ($mp_v,$top_v)=soc_generate_verilog($top_soc,"target_dir/sw1",$txview);
+    #my $ins= gen_mpsoc_instance_v($mpsoc,$mpsoc_name,$param_pass_v);
+    #add_text_to_string(\$top_v,$local_param_v_all."\n".$io_full_v_all);
+    #add_text_to_string(\$top_v,$ins);
+    $mpsoc->object_add_attribute('top_ip',undef,$top_ip);
+    my @chains = (sort { $b <=> $a } keys  %jtag_info);
+    $mpsoc->object_add_attribute('JTAG','M_CHAIN',$chains[0]);
+    return ($mpsoc_v,$top_v,$noc_param);
 }
 
 sub add_sources_to_top_ip{
-	my ($mpsoc,$top_ip)=@_;
-	my $sourc_short;
-	my $source_full="";
-	my @sources=('clk','reset');
-	foreach my $s (@sources){
-		my $num = $mpsoc->object_get_attribute('SOURCE_SET',"${s}_number");
-		$num=1 if (!defined $num);
-		for (my $n=0;$n<$num;$n++){ 
-			my $name=$mpsoc->object_get_attribute('SOURCE_SET',"${s}_${n}_name");
-			$name=$s if(!defined $name);
-			$top_ip->top_add_port('IO',$name,'', 'input' ,"plug:$s\[$n\]","${s}_i");
-			$sourc_short= (defined $sourc_short)? $sourc_short.",\n\t$name" : "\t$name"; 
-			#$source_full=$source_full. "// synthesis attribute keep of $name is true;\n" if($s eq 'clk');
-			$source_full=$source_full."\tinput $name;\n";
-		}
-		#$top_ip->top_add_port('IO','clk','', 'input' ,'plug:clk[0]','clk_i');
-	}	
-	return ($sourc_short, $source_full);
+    my ($mpsoc,$top_ip)=@_;
+    my $sourc_short;
+    my $source_full="";
+    my @sources=('clk','reset');
+    foreach my $s (@sources){
+        my $num = $mpsoc->object_get_attribute('SOURCE_SET',"${s}_number");
+        $num=1 if (!defined $num);
+        for (my $n=0;$n<$num;$n++){
+            my $name=$mpsoc->object_get_attribute('SOURCE_SET',"${s}_${n}_name");
+            $name=$s if(!defined $name);
+            $top_ip->top_add_port('IO',$name,'', 'input' ,"plug:$s\[$n\]","${s}_i");
+            $sourc_short= (defined $sourc_short)? $sourc_short.",\n\t$name" : "\t$name";
+            #$source_full=$source_full. "// synthesis attribute keep of $name is true;\n" if($s eq 'clk');
+            $source_full=$source_full."\tinput $name;\n";
+        }
+        #$top_ip->top_add_port('IO','clk','', 'input' ,'plug:clk[0]','clk_i');
+    }
+    return ($sourc_short, $source_full);
 }
 
-
 sub get_clk_constrain_file{
-	my ($self)=@_;
-	my $s='clk';
-	my $num = $self->object_get_attribute('SOURCE_SET',"${s}_number");
-	my $top_name=$self->object_get_attribute('mpsoc_name');
-	$top_name=$self->object_get_attribute('soc_name') if(!defined $top_name);
-	my $xdc="";
-	return  if (!defined $num);
-	for (my $n=0;$n<$num;$n++){ 
-		my $clk_name=$self->object_get_attribute('SOURCE_SET',"${s}_${n}_name");
-		my $period=$self->object_get_attribute('SOURCE_SET',"${s}_${n}_period");
-		my $fall=$self->object_get_attribute('SOURCE_SET',"${s}_${n}_fall");
-		my $rise=$self->object_get_attribute('SOURCE_SET',"${s}_${n}_rise");
-		my $fal_ns=  ($period * $fall)/100;
-		my $rise_ns= ($period * $rise)/100;
-		
-		$xdc=$xdc."create_clock -period $period -name internal_clk$n -waveform {$rise_ns $fal_ns} -add \[get_nets uut/the_${top_name}/${clk_name}\]\n";
-		
-	}
-	return $xdc;
-		
+    my ($self)=@_;
+    my $s='clk';
+    my $num = $self->object_get_attribute('SOURCE_SET',"${s}_number");
+    my $top_name=$self->object_get_attribute('mpsoc_name');
+    $top_name=$self->object_get_attribute('soc_name') if(!defined $top_name);
+    my $xdc="";
+    return  if (!defined $num);
+    for (my $n=0;$n<$num;$n++){
+        my $clk_name=$self->object_get_attribute('SOURCE_SET',"${s}_${n}_name");
+        my $period=$self->object_get_attribute('SOURCE_SET',"${s}_${n}_period");
+        my $fall=$self->object_get_attribute('SOURCE_SET',"${s}_${n}_fall");
+        my $rise=$self->object_get_attribute('SOURCE_SET',"${s}_${n}_rise");
+        my $fal_ns=  ($period * $fall)/100;
+        my $rise_ns= ($period * $rise)/100;
+        $xdc=$xdc."create_clock -period $period -name internal_clk$n -waveform {$rise_ns $fal_ns} -add \[get_nets uut/the_${top_name}/${clk_name}\]\n";
+    }
+    return $xdc;
 }
 
-
-
 sub add_jtag_ctrl {
-	my ($ref,$txview)=@_;
-	my %jtag_info=%{$ref};
-
-	my $jtag_v="\t//Allow software to remote reset/enable the cpu via jtag
-\twire jtag_cpu_en, jtag_system_reset;	
+    my ($ref,$txview)=@_;
+    my %jtag_info=%{$ref};
+    my $jtag_v="\t//Allow software to remote reset/enable the cpu via jtag
+\twire jtag_cpu_en, jtag_system_reset;
+";
+    my @chains = (sort { $b <=> $a } keys  %jtag_info);
+    my $altera=0;
+    my $xilinx=0;
+    my $glob_en;
+    foreach my $c (@chains){
+        my $xilinx_jtag_ctrl_in;
+        my $xilinx_jtag_ctrl_out;
+        my $r = $jtag_info{$c}{'wire'};
+        my $index = $jtag_info{$c}{'index'};
+        my @array = (defined $r)? @{$r} :();
+        my $wires_def = join ("\n",@array);
+        $jtag_v=$jtag_v."\n//\tJtag chain $c Wire def\n$wires_def\n" if(@array);
+        $r= $jtag_info{$c}{'altera_num'};
+        @array = (defined $r)? @{$r} :();
+        my $altera_jtag_ctrl =(@array)? scalar @array : 0;
+        $r= $jtag_info{$c}{'xilinx_num'};
+        @array = (defined $r)? @{$r} :();
+        my $xilinx_jtag_ctrl =(@array)? scalar @array : 0;
+        $altera+=$altera_jtag_ctrl;
+        $xilinx+=$xilinx_jtag_ctrl;
+        if ($xilinx_jtag_ctrl>0){
+            $r=$jtag_info{$c}{'input'};
+            @array = (defined $r)? @{$r} :();
+            $xilinx_jtag_ctrl_in = ($xilinx_jtag_ctrl!=1)? '{'.join(',',@array).'}' : $array[0];
+            $r=$jtag_info{$c}{'output'};
+            @array = (defined $r)? @{$r} :();
+            $xilinx_jtag_ctrl_out= ($xilinx_jtag_ctrl!=1)? '{'.join(',',@array).'}' : $array[0];
+            my $ctrl = (defined $glob_en)? "
+        .system_reset( ),
+        .cpu_en( ),
+    " : "//The global reset/enable signals are connected to the tap with the largest jtag chain number
+        .system_reset(jtag_system_reset),
+        .cpu_en(jtag_cpu_en),
+    ";
+            $glob_en=1;
+            $jtag_v=$jtag_v."
+    xilinx_jtag_wb  #(
+        .JTAG_CHAIN($c),
+        .JWB_NUM($xilinx_jtag_ctrl)
+    )
+    jwb_$c
+    (
+        $ctrl
+        .reset(jtag_debug_reset_in),
+        .wb_to_jtag_all($xilinx_jtag_ctrl_out),
+        .jtag_to_wb_all($xilinx_jtag_ctrl_in)
+    );
 ";
-	my @chains = (sort { $b <=> $a } keys  %jtag_info);
-	my $altera=0;
-	my $xilinx=0;
-	my $glob_en;
-	foreach my $c (@chains){
-		my $xilinx_jtag_ctrl_in;
-		my $xilinx_jtag_ctrl_out;
-		my $r = $jtag_info{$c}{'wire'};
-		my $index = $jtag_info{$c}{'index'};
-		
-		my @array = (defined $r)? @{$r} :();		
-		my $wires_def = join ("\n",@array); 
-		$jtag_v=$jtag_v."\n//\tJtag chain $c Wire def\n$wires_def\n" if(@array);		
-		$r= $jtag_info{$c}{'altera_num'};
-		@array = (defined $r)? @{$r} :();	
-		my $altera_jtag_ctrl =(@array)? scalar @array : 0;
-		$r= $jtag_info{$c}{'xilinx_num'};
-		@array = (defined $r)? @{$r} :();	
-		my $xilinx_jtag_ctrl =(@array)? scalar @array : 0;
-		$altera+=$altera_jtag_ctrl;
-		$xilinx+=$xilinx_jtag_ctrl;
-		if ($xilinx_jtag_ctrl>0){
-			$r=$jtag_info{$c}{'input'};
-			@array = (defined $r)? @{$r} :();	
-			$xilinx_jtag_ctrl_in = ($xilinx_jtag_ctrl!=1)? '{'.join(',',@array).'}' : $array[0];
-			$r=$jtag_info{$c}{'output'};
-			@array = (defined $r)? @{$r} :();	
-			$xilinx_jtag_ctrl_out= ($xilinx_jtag_ctrl!=1)? '{'.join(',',@array).'}' : $array[0];
-			my $ctrl = (defined $glob_en)? "
-		.system_reset( ),
-		.cpu_en( ),
-	" : "//The global reset/enable signals are connected to the tap with the largest jtag chain number 
-		.system_reset(jtag_system_reset),
-		.cpu_en(jtag_cpu_en),
-	";	
-	
-	
-	
-		
-			$glob_en=1;			
-			$jtag_v=$jtag_v."
-	xilinx_jtag_wb  #(
-		.JTAG_CHAIN($c),
-		.JWB_NUM($xilinx_jtag_ctrl)		
-	)
-	jwb_$c
-	(		
-		$ctrl
-		.reset(jtag_debug_reset_in),		
-		.wb_to_jtag_all($xilinx_jtag_ctrl_out),
-		.jtag_to_wb_all($xilinx_jtag_ctrl_in)
-	);		
-";	
-			
-		
-		}
-		
-	}#for
-	
-	if($altera>0 && $xilinx>0){
-		my $r = $jtag_info{0}{'inst'};
-		my @array = (defined $r)? @{$r} :();	
-		my $inst=join ("\n\t",@array);
-		add_colored_info($txview,"Found JTAG communication ports from different FPGA vendors:\n$inst.",'red');			
-	}
-	elsif($altera>0){
-		$jtag_v=$jtag_v."	
-		jtag_system_en #(
-			.FPGA_VENDOR(\"ALTERA\")
-		) jtag_en (
-			.cpu_en(jtag_cpu_en),
-			.system_reset(jtag_system_reset)
-		
-		);	
-	";		
-	}
-	
-	elsif($altera==0 && $xilinx==0){
-		$jtag_v=$jtag_v."
-    	//No jtag connection has found in the design	
-		jtag_system_en #(
-			.FPGA_VENDOR(FPGA_VENDOR)
-		) jtag_en (
-			.cpu_en(jtag_cpu_en),
-			.system_reset(jtag_system_reset)
-		
-		);	
-";	
-	
-	
-	}
-			
-return $jtag_v;	
-	
+        }
+    }#for
+    if($altera>0 && $xilinx>0){
+        my $r = $jtag_info{0}{'inst'};
+        my @array = (defined $r)? @{$r} :();
+        my $inst=join ("\n\t",@array);
+        add_colored_info($txview,"Found JTAG communication ports from different FPGA vendors:\n$inst.",'red');
+    }
+    elsif($altera>0){
+        $jtag_v=$jtag_v."
+        jtag_system_en #(
+            .FPGA_VENDOR(\"ALTERA\")
+        ) jtag_en (
+            .cpu_en(jtag_cpu_en),
+            .system_reset(jtag_system_reset)
+        );
+    ";
+    }
+    elsif($altera==0 && $xilinx==0){
+        $jtag_v=$jtag_v."
+        //No jtag connection has found in the design
+        jtag_system_en #(
+            .FPGA_VENDOR(FPGA_VENDOR)
+        ) jtag_en (
+            .cpu_en(jtag_cpu_en),
+            .system_reset(jtag_system_reset)
+        );
+";
+    }
+return $jtag_v;
 }
 
-
-
-
 sub get_functions{
-	my $p='
-//functions	
-	function integer log2;
-		input integer number; begin   
-			log2=0;    
-			while(2**log2<number) begin    
-				log2=log2+1;    
-			end    
-	end   
-	endfunction // log2 
-				
-	';
-	
-	return $p;
+    my $p='
+//functions
+    function integer log2;
+        input integer number; begin
+            log2=0;
+            while(2**log2<number) begin
+                log2=log2+1;
+            end
+    end
+    endfunction // log2
+    ';
+    return $p;
 }
 
-
 sub  gen_socs_param{
-	my $mpsoc=shift;
-	my $socs_param="
+    my $mpsoc=shift;
+    my $socs_param="
 //SOC parameters\n";
-	my ($NE, $NR, $RAw,  $EAw, $Fw) = get_topology_info($mpsoc);
-	my $processors_en=0;
+    my ($NE, $NR, $RAw,  $EAw, $Fw) = get_topology_info($mpsoc);
+    my $processors_en=0;
     for (my $tile=0;$tile<$NE;$tile++){
-			my ($soc_name,$n,$soc_num)=$mpsoc->mpsoc_get_tile_soc_name($tile);
-			if(defined $soc_name) {
-				my $param=	gen_soc_param($mpsoc,$soc_name,$soc_num,$tile);
-				$socs_param=$socs_param.$param;
-			}	
-	}#$tile
-	$socs_param="$socs_param \n";
-	return $socs_param;	
+            my ($soc_name,$n,$soc_num)=$mpsoc->mpsoc_get_tile_soc_name($tile);
+            if(defined $soc_name) {
+                my $param=    gen_soc_param($mpsoc,$soc_name,$soc_num,$tile);
+                $socs_param=$socs_param.$param;
+            }
+    }#$tile
+    $socs_param="$socs_param \n";
+    return $socs_param;
 }
 
-
 sub  gen_soc_param {
-	my ($mpsoc,$soc_name,$soc_num,$tile_num)=@_;
-	my $top=$mpsoc->mpsoc_get_soc($soc_name);
-	my $setting=$mpsoc->mpsoc_get_tile_param_setting($tile_num);
-	my %params;
-	#if ($setting eq 'Custom'){
-	%params= $top->top_get_custom_soc_param($tile_num);
-	#}else{
-	#	 %params=$top->top_get_default_soc_param();
-	#}
-	my $params="\n\t //Parameter setting for $soc_name  located in tile: $tile_num \n";
-	$params{'CORE_ID'}=$tile_num;
-	foreach my $p (get_param_list_in_order(\%params)){
-			$params{$p}=add_instantc_name_to_parameters(\%params,"T$tile_num",$params{$p});
-			
-			$params="$params\t localparam T${tile_num}_$p=$params{$p};\n";
-	}
-	return $params;
+    my ($mpsoc,$soc_name,$soc_num,$tile_num)=@_;
+    my $top=$mpsoc->mpsoc_get_soc($soc_name);
+    my $setting=$mpsoc->mpsoc_get_tile_param_setting($tile_num);
+    my %params;
+    #if ($setting eq 'Custom'){
+    %params= $top->top_get_custom_soc_param($tile_num);
+    #}else{
+    #     %params=$top->top_get_default_soc_param();
+    #}
+    my $params="\n\t //Parameter setting for $soc_name  located in tile: $tile_num \n";
+    $params{'CORE_ID'}=$tile_num;
+    foreach my $p (get_param_list_in_order(\%params)){
+            $params{$p}=add_instantc_name_to_parameters(\%params,"T$tile_num",$params{$p});
+            $params="$params\t localparam T${tile_num}_$p=$params{$p};\n";
+    }
+    return $params;
 }
 
-
-
 sub gen_noc_param_v{
-	my ($mpsoc,$sample,$noc_id)=@_;
-	$noc_id="" if(!defined $noc_id);
-	my $noc_param = "noc_param$noc_id";	
-	my $param_v="\n\n//NoC parameters\n";
-	my $pass_param="";
-	my @params=$mpsoc->object_get_attribute_order($noc_param);
-	my $custom_topology = $mpsoc->object_get_attribute($noc_param,'CUSTOM_TOPOLOGY_NAME');
-	my ($NE, $NR, $RAw, $EAw, $Fw) = get_topology_info($mpsoc,$noc_id);
-	my %noc_info;
-	if(defined $sample ){
-		my $ref=$mpsoc->object_get_attribute($sample,"noc_info"); 
-		%noc_info= %$ref;	
-		($NE, $NR, $RAw, $EAw, $Fw) = get_topology_info_from_parameters($ref);			
-	}
-	
-	foreach my $p (@params){
-		
-		my $val= (defined $sample) ? $noc_info{$p} :$mpsoc->object_get_attribute($noc_param,$p);
-		next if($p eq "CUSTOM_TOPOLOGY_NAME");
-		$val=$custom_topology if($p eq "TOPOLOGY" && $val eq "\"CUSTOM\"");
-		if($p eq 'MCAST_ENDP_LIST'){
-			
-			$val="$NE".$val;
-		}
-		$param_v= $param_v."\tlocalparam $p=$val;\n";
-		$pass_param=$pass_param."\t\t.$p($p),\n";
-		#print "$p:$val\n";
-		
-	}
-	my $class=$mpsoc->object_get_attribute($noc_param,"C");
-	my $str;
-	if( $class > 1){
-		for (my $i=0; $i<=$class-1; $i++){
-			my $n="Cn_$i";
-			my $val=$mpsoc->object_get_attribute('class_param',$n);
-			$param_v=$param_v."\tlocalparam $n=$val;\n";
-		}
-		$str="CLASS_SETTING={";
-		for (my $i=$class-1; $i>=0;$i--){
-			$str=($i==0)?  "${str}Cn_0};\n " : "${str}Cn_$i,";
-		}
-	}else {
-		$str="CLASS_SETTING={V{1\'b1}};\n";
-	}	
-	$param_v=$param_v."\tlocalparam $str";
-	$pass_param=$pass_param."\t\t.CLASS_SETTING(CLASS_SETTING),\n";
-	my $v=$mpsoc->object_get_attribute($noc_param,"V")-1;
-	my $escape=$mpsoc->object_get_attribute($noc_param,"ESCAP_VC_MASK");
-	if (! defined $escape){
-		$param_v=$param_v."\tlocalparam [$v	:0] ESCAP_VC_MASK=1;\n";
-		$pass_param=$pass_param.".\t\tESCAP_VC_MASK(ESCAP_VC_MASK),\n"; 
-	}
-	$param_v=$param_v." \tlocalparam  CVw=(C==0)? V : C * V;\n";
-	$pass_param=$pass_param."\t\t.CVw(CVw)\n";	
-	return ($param_v,$pass_param);	
-	
+    my ($mpsoc,$sample,$noc_id)=@_;
+    $noc_id="" if(!defined $noc_id);
+    my $noc_param = "noc_param$noc_id";
+    my $param_v="\n\n//NoC parameters\n";
+    my $pass_param="";
+    my @params=$mpsoc->object_get_attribute_order($noc_param);
+    my $custom_topology = $mpsoc->object_get_attribute($noc_param,'CUSTOM_TOPOLOGY_NAME');
+    my ($NE, $NR, $RAw, $EAw, $Fw) = get_topology_info($mpsoc,$noc_id);
+    my %noc_info;
+    my $hashref= $mpsoc->object_get_attribute('noc_param_comments');
+    my %comments = %{$hashref} if defined $hashref;
+    if(defined $sample ){
+        my $ref=$mpsoc->object_get_attribute($sample,"noc_info");
+        %noc_info= %$ref;
+        ($NE, $NR, $RAw, $EAw, $Fw) = get_topology_info_from_parameters($ref);
+    }
+    foreach my $p (@params){
+        my $val= (defined $sample) ? $noc_info{$p} :$mpsoc->object_get_attribute($noc_param,$p);
+        next if($p eq "CUSTOM_TOPOLOGY_NAME");
+        $val=$custom_topology if($p eq "TOPOLOGY" && $val eq "\"CUSTOM\"");
+        if($p eq 'MCAST_ENDP_LIST'){
+            $val="$NE".$val;
+        }
+        $param_v= $param_v."\tlocalparam $p=$val;\n";
+        my $comment=$comments{$p};
+        if(defined $comment){
+            $comment=~ s/\n/\n            \/\//g;
+            $param_v.="            //$p : $comment\n\n";
+        }
+        $pass_param=$pass_param."\t\t.$p($p),\n";
+        #print "$p:$val\n";
+    }
+    my $class=$mpsoc->object_get_attribute($noc_param,"C");
+    my $str;
+    if( $class > 1){
+        for (my $i=0; $i<=$class-1; $i++){
+            my $n="Cn_$i";
+            my $val=$mpsoc->object_get_attribute('class_param',$n);
+            $param_v=$param_v."\tlocalparam $n=$val;\n";
+        }
+        $str="CLASS_SETTING={";
+        for (my $i=$class-1; $i>=0;$i--){
+            $str=($i==0)?  "${str}Cn_0};\n " : "${str}Cn_$i,";
+        }
+    }else {
+        $str="CLASS_SETTING={V{1\'b1}};\n";
+    }
+    $param_v=$param_v."\tlocalparam $str";
+    $pass_param=$pass_param."\t\t.CLASS_SETTING(CLASS_SETTING),\n";
+    my $v=$mpsoc->object_get_attribute($noc_param,"V")-1;
+    my $escape=$mpsoc->object_get_attribute($noc_param,"ESCAP_VC_MASK");
+    if (! defined $escape){
+        $param_v=$param_v."\tlocalparam [$v    :0] ESCAP_VC_MASK=1;\n";
+        $pass_param=$pass_param.".\t\tESCAP_VC_MASK(ESCAP_VC_MASK),\n";
+    }
+    $param_v=$param_v." \tlocalparam  CVw=(C==0)? V : C * V;\n";
+    $pass_param=$pass_param."\t\t.CVw(CVw)\n";
+    return ($param_v,$pass_param);
 }
 
-
 sub gen_noc_param_h{
-	my $mpsoc=shift;
-	my $param_h="\n\n//NoC parameters\n";
-	
-	my $topology = $mpsoc->object_get_attribute('noc_param','TOPOLOGY');
-	$topology =~ s/"//g;
-	$param_h.="\t#define  IS_${topology}\n";
-	
-	my ($NE, $NR, $RAw, $EAw, $Fw) = get_topology_info($mpsoc);
-	
-	
-	
-	
-	my @params=$mpsoc->object_get_attribute_order('noc_param');
-	my $custom_topology = $mpsoc->object_get_attribute('noc_param','CUSTOM_TOPOLOGY_NAME');
-	foreach my $p (@params){
-		my $val=$mpsoc->object_get_attribute('noc_param',$p);
-		next if($p eq "CUSTOM_TOPOLOGY_NAME");
-		$val=$custom_topology if($p eq "TOPOLOGY" && $val eq "\"CUSTOM\"");
-		if($p eq "MCAST_ENDP_LIST" || $p eq "ESCAP_VC_MASK"){
-			$val="$NE".$val if($p eq 'MCAST_ENDP_LIST');
-			$val =~ s/\'/\\\'/g;
-			$val="\"$val\"";			
-		}
-		
-		$param_h=$param_h."\t#define $p\t$val\n";
-		
-		#print "$p:$val\n";
-		
-	}
-	my $class=$mpsoc->object_get_attribute('noc_param',"C");
-	my $str;
-	if( $class > 1){
-		for (my $i=0; $i<=$class-1; $i++){
-			my $n="Cn_$i";
-			my $val=$mpsoc->object_get_attribute('class_param',$n);
-			$param_h=$param_h."\t#define $n\t$val\n";
-		}
-		$str="CLASS_SETTING  {";
-		for (my $i=$class-1; $i>=0;$i--){
-			$str=($i==0)?  "${str}Cn_0};\n " : "${str}Cn_$i,";
-		}
-	}else {
-		$str="CLASS_SETTING={V{1\'b1}}\n";
-	}	
-	#add_text_to_string (\$param_h,"\t#define $str");
-	 
-	my $v=$mpsoc->object_get_attribute('noc_param',"V")-1;
-	my $escape=$mpsoc->object_get_attribute('noc_param',"ESCAP_VC_MASK");
-	if (! defined $escape){
-		#add_text_to_string (\$param_h,"\tlocalparam [$v	:0] ESCAP_VC_MASK=1;\n");
-		#add_text_to_string (\$pass_param,".ESCAP_VC_MASK(ESCAP_VC_MASK),\n"); 
-	}
-	#add_text_to_string (\$param_h," \tlocalparam  CVw=(C==0)? V : C * V;\n");
-	#add_text_to_string (\$pass_param,".CVw(CVw)\n");
-	
-	
-	#remove 'b and 'h
-	#$param_h =~ s/\d\'b/ /g;
-	#$param_h =~ s/\'h/ /g;
-	
-	return  $param_h;	
+    my $mpsoc=shift;
+    my $param_h="\n\n//NoC parameters\n";
+    my $topology = $mpsoc->object_get_attribute('noc_param','TOPOLOGY');
+    $topology =~ s/"//g;
+    $param_h.="\t#define  IS_${topology}\n";
+    my ($NE, $NR, $RAw, $EAw, $Fw) = get_topology_info($mpsoc);
+    my @params=$mpsoc->object_get_attribute_order('noc_param');
+    my $custom_topology = $mpsoc->object_get_attribute('noc_param','CUSTOM_TOPOLOGY_NAME');
+    foreach my $p (@params){
+        my $val=$mpsoc->object_get_attribute('noc_param',$p);
+        next if($p eq "CUSTOM_TOPOLOGY_NAME");
+        next if($p eq "int VC_CONFIG_TABLE [MAX_ROUTER][MAX_PORT]");
+        $val=$custom_topology if($p eq "TOPOLOGY" && $val eq "\"CUSTOM\"");
+        if($p eq "MCAST_ENDP_LIST" || $p eq "ESCAP_VC_MASK"){
+            $val="$NE".$val if($p eq 'MCAST_ENDP_LIST');
+            $val =~ s/\'/\\\'/g;
+            $val="\"$val\"";
+        }
+        $param_h=$param_h."\t#define $p\t$val\n";
+        #print "$p:$val\n";
+    }
+    my $class=$mpsoc->object_get_attribute('noc_param',"C");
+    my $str;
+    if( $class > 1){
+        for (my $i=0; $i<=$class-1; $i++){
+            my $n="Cn_$i";
+            my $val=$mpsoc->object_get_attribute('class_param',$n);
+            $param_h=$param_h."\t#define $n\t$val\n";
+        }
+        $str="CLASS_SETTING  {";
+        for (my $i=$class-1; $i>=0;$i--){
+            $str=($i==0)?  "${str}Cn_0};\n " : "${str}Cn_$i,";
+        }
+    }else {
+        $str="CLASS_SETTING={V{1\'b1}}\n";
+    }
+    #add_text_to_string (\$param_h,"\t#define $str");
+    my $v=$mpsoc->object_get_attribute('noc_param',"V")-1;
+    my $escape=$mpsoc->object_get_attribute('noc_param',"ESCAP_VC_MASK");
+    if (! defined $escape){
+        #add_text_to_string (\$param_h,"\tlocalparam [$v    :0] ESCAP_VC_MASK=1;\n");
+        #add_text_to_string (\$pass_param,".ESCAP_VC_MASK(ESCAP_VC_MASK),\n");
+    }
+    #add_text_to_string (\$param_h," \tlocalparam  CVw=(C==0)? V : C * V;\n");
+    #add_text_to_string (\$pass_param,".CVw(CVw)\n");
+    #remove 'b and 'h
+    #$param_h =~ s/\d\'b/ /g;
+    #$param_h =~ s/\'h/ /g;
+    return  $param_h;
 }
 
-
-
-
-
 sub gen_noc_v{
-	my ($mpsoc,$pass_param) = @_;
-	my ($NE, $NR, $RAw, $EAw, $Fw) = get_topology_info($mpsoc);
-	
-
+    my ($mpsoc,$pass_param) = @_;
+    my ($NE, $NR, $RAw, $EAw, $Fw) = get_topology_info($mpsoc);
     my $noc_clk   =  $mpsoc->object_get_attribute('SOURCE_SET_CONNECT',"NoC_clk");
-	my $noc_reset =  $mpsoc->object_get_attribute('SOURCE_SET_CONNECT',"NoC_reset");
-	$noc_clk   = 'clk0'   if(!defined $noc_clk  );
-	$noc_reset = 'reset0' if(!defined $noc_reset);
-
-	my $noc_v="
-
-	//connection wire to NoC
-	smartflit_chanel_t ni_chan_in  [NE-1 : 0];
-	smartflit_chanel_t ni_chan_out [NE-1 : 0];
-	
-	wire 					noc_clk_in,noc_reset_in;    
-   
+    my $noc_reset =  $mpsoc->object_get_attribute('SOURCE_SET_CONNECT',"NoC_reset");
+    $noc_clk   = 'clk0'   if(!defined $noc_clk  );
+    $noc_reset = 'reset0' if(!defined $noc_reset);
+    my $noc_v="
+    //connection wire to NoC
+    smartflit_chanel_t ni_chan_in  [NE-1 : 0];
+    smartflit_chanel_t ni_chan_out [NE-1 : 0];
+    wire   noc_clk_in,noc_reset_in;
     //NoC
- 	noc_top # ( 
-		.NOC_ID(NOC_ID)
-	) the_noc (
-		.reset(noc_reset_in),
-		.clk(noc_clk_in),    
-		.chan_in_all(ni_chan_out),
-		.chan_out_all(ni_chan_in),
-		.router_event( )  
-	);	
-	
-	clk_source  src 	(
-		.clk_in($noc_clk),
-		.clk_out(noc_clk_in),
-		.reset_in($noc_reset),
-		.reset_out(noc_reset_in)
-	);    
+    noc_top  the_noc (
+        .reset(noc_reset_in),
+        .clk(noc_clk_in),
+        .chan_in_all(ni_chan_out),
+        .chan_out_all(ni_chan_in),
+        .router_event( )
+    );
+    clk_source  src   (
+        .clk_in($noc_clk),
+        .clk_out(noc_clk_in),
+        .reset_in($noc_reset),
+        .reset_out(noc_reset_in)
+    );
 ";
-
-;
-	return $noc_v;
-	
+    return $noc_v;
 }
 
-
-
-
 sub gen_socs_v{
-	my ($mpsoc,$top_ip,$sw_dir,$txview)=@_;
-	
-	#add clk reset signals
-	my ($sourc_short, $source_full)=add_sources_to_top_ip($mpsoc,$top_ip);
-	
-	   
-	my $io_short=$sourc_short;
-	my $top_io_short="\tjtag_debug_reset_in";   
-	
-	
-#	my $jtag_def="// Allow software to remote reset/enable the cpu via jtag
-#\twire jtag_cpu_en, jtag_system_reset;	
+    my ($mpsoc,$top_ip,$sw_dir,$txview)=@_;
+    #add clk reset signals
+    my ($sourc_short, $source_full)=add_sources_to_top_ip($mpsoc,$top_ip);
+    my $io_short=$sourc_short;
+    my $top_io_short="\tjtag_debug_reset_in";
+#    my $jtag_def="// Allow software to remote reset/enable the cpu via jtag
+#\twire jtag_cpu_en, jtag_system_reset;
 #\twire processors_en_anded_jtag = processors_en & jtag_cpu_en;
-#	
+#
 #";
-	
-	my $io_full=$source_full;
-	my $top_io_full= "\tinput jtag_debug_reset_in;\n";   
-	my $top_io_pass="//";
-	
-	my %jtag_info;
-	%jtag_info=append_to_hash (\%jtag_info,0,'wire',"wire processors_en_anded_jtag = processors_en & jtag_cpu_en;\n"); 
-	#my $altera_jtag_ctrl=0;
-	#my $xilinx_jtag_ctrl=0; #if it becomes larger than 0 then add jtag to wb module 
-	#my $jtag_insts="";
-	#my $xilinx_jtag_ctrl_in="";
-	#my $xilinx_jtag_ctrl_out=""; 
-	
-	   
-	my $socs_v=""; 
-	my ($NE, $NR, $RAw, $EAw, $Fw)= get_topology_info ($mpsoc); 
-    
-  
-	my $processors_en=0;
-	for (my $tile_num=0;$tile_num<$NE;$tile_num++){
-			my ($soc_name,$n,$soc_num)=$mpsoc->mpsoc_get_tile_soc_name($tile_num);
-			
-			if(defined $soc_name) {				
-				my ($soc_v,$en,$io_short1,$io_full1,$top_io_short1,$top_io_full1,$top_io_pass1,$ref)= 
-				gen_soc_v($mpsoc,$top_ip,$sw_dir,$soc_name,$tile_num,$soc_num,$txview,\%jtag_info);
-				%jtag_info=%{$ref};
-				$socs_v=$socs_v.$soc_v;
-				$io_short    = $io_short    .$io_short1;
-				$io_full     = $io_full     .$io_full1;
-				$top_io_short= $top_io_short.$top_io_short1;
-				$top_io_full = $top_io_full. $top_io_full1;
-				$top_io_pass = $top_io_pass. $top_io_pass1;
-			#	$jtag_def    = $jtag_def    .$jtag_def1;
-			#	$jtag_insts=$jtag_insts.$jtag_insts1; 
-			#	$altera_jtag_ctrl+=$altera_jtag_ctrl1;
-			#	$xilinx_jtag_ctrl+=$xilinx_jtag_ctrl1;
-			#	$xilinx_jtag_ctrl_in =(length ($xilinx_jtag_ctrl_in )>2)? "$xilinx_jtag_ctrl_in,$xilinx_jtag_ctrl_in1"  : $xilinx_jtag_ctrl_in.$xilinx_jtag_ctrl_in1;
-			#	$xilinx_jtag_ctrl_out=(length ($xilinx_jtag_ctrl_out)>2)? "$xilinx_jtag_ctrl_out,$xilinx_jtag_ctrl_out1" :$xilinx_jtag_ctrl_out.$xilinx_jtag_ctrl_out1;
-		
-				$processors_en|=$en;
-			
-			}else{
-				#this tile is not connected to any ip. the noc input ports will be connected to ground
-				my $soc_v="\n\n // Tile:$tile_num    is not assigned to any ip\n";
-				$soc_v="$soc_v
-	
-	assign ni_credit_out[$tile_num]={V{1'b0}}; 
-	assign ni_flit_out[$tile_num]={Fw{1'b0}}; 
-	assign ni_flit_out_wr[$tile_num]=1'b0; 
-	";
-		$socs_v=$socs_v.$soc_v;			
-				
-			}
-	
-	}
-                
+    my $io_full=$source_full;
+    my $top_io_full= "\tinput jtag_debug_reset_in;\n";
+    my $top_io_pass="//";
+    my %jtag_info;
+    %jtag_info=append_to_hash (\%jtag_info,0,'wire',"wire processors_en_anded_jtag = processors_en & jtag_cpu_en;\n");
+    #my $altera_jtag_ctrl=0;
+    #my $xilinx_jtag_ctrl=0; #if it becomes larger than 0 then add jtag to wb module
+    #my $jtag_insts="";
+    #my $xilinx_jtag_ctrl_in="";
+    #my $xilinx_jtag_ctrl_out="";
+    my $socs_v="";
+    my ($NE, $NR, $RAw, $EAw, $Fw)= get_topology_info ($mpsoc);
+    my $processors_en=0;
+    for (my $tile_num=0;$tile_num<$NE;$tile_num++){
+            my ($soc_name,$n,$soc_num)=$mpsoc->mpsoc_get_tile_soc_name($tile_num);
+            if(defined $soc_name) {
+                my ($soc_v,$en,$io_short1,$io_full1,$top_io_short1,$top_io_full1,$top_io_pass1,$ref)=
+                gen_soc_v($mpsoc,$top_ip,$sw_dir,$soc_name,$tile_num,$soc_num,$txview,\%jtag_info);
+                %jtag_info=%{$ref};
+                $socs_v=$socs_v.$soc_v;
+                $io_short    = $io_short    .$io_short1;
+                $io_full     = $io_full     .$io_full1;
+                $top_io_short= $top_io_short.$top_io_short1;
+                $top_io_full = $top_io_full. $top_io_full1;
+                $top_io_pass = $top_io_pass. $top_io_pass1;
+            #    $jtag_def    = $jtag_def    .$jtag_def1;
+            #    $jtag_insts=$jtag_insts.$jtag_insts1;
+            #    $altera_jtag_ctrl+=$altera_jtag_ctrl1;
+            #    $xilinx_jtag_ctrl+=$xilinx_jtag_ctrl1;
+            #    $xilinx_jtag_ctrl_in =(length ($xilinx_jtag_ctrl_in )>2)? "$xilinx_jtag_ctrl_in,$xilinx_jtag_ctrl_in1"  : $xilinx_jtag_ctrl_in.$xilinx_jtag_ctrl_in1;
+            #    $xilinx_jtag_ctrl_out=(length ($xilinx_jtag_ctrl_out)>2)? "$xilinx_jtag_ctrl_out,$xilinx_jtag_ctrl_out1" :$xilinx_jtag_ctrl_out.$xilinx_jtag_ctrl_out1;
+                $processors_en|=$en;
+            }else{
+                #this tile is not connected to any ip. the noc input ports will be connected to ground
+                my $soc_v="\n\n // Tile:$tile_num    is not assigned to any ip\n";
+                $soc_v="$soc_v
+    assign ni_credit_out[$tile_num]={V{1'b0}};
+    assign ni_flit_out[$tile_num]={Fw{1'b0}};
+    assign ni_flit_out_wr[$tile_num]=1'b0;
+    ";
+        $socs_v=$socs_v.$soc_v;
+            }
+    }
     if($processors_en){
-    	$io_short=$io_short.",\n\tprocessors_en";
-    	$io_full=$io_full."\tinput processors_en;";
-    	$top_io_short=$top_io_short.",\n\tprocessors_en";
-    	$top_io_full=$top_io_full."\t input processors_en;";
-    	$top_io_pass=$top_io_pass.",\n\t\t.processors_en(processors_en_anded_jtag)";
-		$top_ip->top_add_port('IO','processors_en','' ,'input','plug:enable[0]','enable_i');
-    	
-    }            
-    
- #  $io_short=$io_short.",\n\tjtag_system_reset";
- #  $io_full=$io_full."\n\tinput jtag_system_reset;"; 
- #  $top_io_pass=$top_io_pass.",\n\t\t.jtag_system_reset(jtag_system_reset)";
-    
-   
-	return ($socs_v,$io_short,$io_full,$top_io_short,$top_io_full,$top_io_pass,\%jtag_info);
-
+        $io_short=$io_short.",\n\tprocessors_en";
+        $io_full=$io_full."\tinput processors_en;";
+        $top_io_short=$top_io_short.",\n\tprocessors_en";
+        $top_io_full=$top_io_full."\t input processors_en;";
+        $top_io_pass=$top_io_pass.",\n\t\t.processors_en(processors_en_anded_jtag)";
+        $top_ip->top_add_port('IO','processors_en','' ,'input','plug:enable[0]','enable_i');
+    }
+    #  $io_short=$io_short.",\n\tjtag_system_reset";
+    #  $io_full=$io_full."\n\tinput jtag_system_reset;";
+    #  $top_io_pass=$top_io_pass.",\n\t\t.jtag_system_reset(jtag_system_reset)";
+    return ($socs_v,$io_short,$io_full,$top_io_short,$top_io_full,$top_io_pass,\%jtag_info);
 }
 
-
-
 ##############
-#	gen_soc_v
+#    gen_soc_v
 ##############
-
-
 #$mpsoc,$top_ip,$sw_dir,$soc_name,$id,$soc_num,$txview
 sub   gen_soc_v{
-	my ($mpsoc,$top_ip,$sw_path,$soc_name,$tile_num,$soc_num,$txview,$href)=@_;
-	my %jtag_info = %{$href};
-		
-	my $io_short="";
-	my $io_full="";
-	my $top_io_short="";
-	my $top_io_full="";
-	my $top_io_pass="";
-
-	
-	
-	my $processor_en=0;
-
-	
-	
-	
-	
-	my ($NE, $NR, $RAw, $EAw, $Fw)= get_topology_info ($mpsoc); 
-	my $e_addr=endp_addr_encoder($mpsoc,$tile_num);
-	my $router_num = get_connected_router_id_to_endp($mpsoc,$tile_num);
-	my $r_addr=router_addr_encoder($mpsoc,$router_num);
-	
-	
-	
-	my $soc_v="\n\n // Tile:$tile_num ($e_addr)\n   \t$soc_name #(\n";
-	
-	# Global parameter
-	$soc_v=$soc_v."\t\t.CORE_ID($tile_num),\n\t\t.SW_LOC(\"$sw_path/tile$tile_num\")";
-	
-		
-	# ni parameter
-	my $top=$mpsoc->mpsoc_get_soc($soc_name);
-	my @nis=get_NI_instance_list($top);
-	my @noc_param=$top->top_get_parameter_list($nis[0]);
-	my $inst_name=$top->top_get_def_of_instance($nis[0],'instance');
-	
-	#other parameters
-	my %params=$top->top_get_default_soc_param();
-	
-	
-	
-	foreach my $p (@noc_param){
-		my $parm_next = $p;
-		$parm_next =~ s/${inst_name}_//;
-		my $param=  ",\n\t\t.$p($parm_next)"; 
-		$soc_v=$soc_v.$param;		
-	}
-	foreach my $p (sort keys %params){
-		my $parm_next= "T${tile_num}_$p";
-		my $param=  ",\n\t\t.$p($parm_next)"; 
-		$soc_v=$soc_v.$param;			
-		
-	}	
-	
-	$soc_v=$soc_v."\n\t)the_${soc_name}_$soc_num(\n";
-	
-	my @intfcs=$top->top_get_intfc_list();
-	
-	my $i=0;
-
-	my $dir = Cwd::getcwd();
-	my $mpsoc_name=$mpsoc->object_get_attribute('mpsoc_name');
-	my $target_dir  = "$ENV{'PRONOC_WORK'}/MPSOC/$mpsoc_name";
-	my $soc_file="$target_dir/src_verilog/tiles/$soc_name.sv";
-			
-	my $vdb =read_verilog_file($soc_file);
-		
-	my %soc_localparam = $vdb->get_modules_parameters($soc_name);
-	
-
-	foreach my $intfc (@intfcs){
-		
-		# ni intfc	
-		if( $intfc eq 'socket:ni[0]'){
-			my @ports=$top->top_get_intfc_ports_list($intfc);
-		
-			foreach my $p (@ports){
-				my($inst,$range,$type,$intfc_name,$intfc_port)= $top->top_get_port($p);
-				my $q=	($intfc_port eq "current_e_addr")? "$EAw\'d$e_addr" : 
-						($intfc_port eq "current_r_addr")? "$RAw\'d$r_addr" :						
-						"ni_$intfc_port\[$tile_num\]";
-				$soc_v=$soc_v.',' if ($i);	
-				$soc_v=$soc_v."\n\t\t.$p($q)";
-				$i=1;
-			
-				
-			}			
-		}
-		# clk source
-		elsif( $intfc =~ /plug:clk\[/ ){
-			my @ports=$top->top_get_intfc_ports_list($intfc);
-			foreach my $p (@ports){
-				my($inst,$range,$type,$intfc_name,$intfc_port)= $top->top_get_port($p);
-				$soc_v=$soc_v.',' if ($i);	
-				my $src =  $mpsoc->object_get_attribute('SOURCE_SET_CONNECT',"T${tile_num}_$p");				
-				$src = 'clk0' if(!defined $src);
-				$soc_v=$soc_v."\n\t\t.$p($src)";					
-			    $i=1;	
-				
-			}	
-		}		
-		#reset
-		elsif( $intfc =~ /plug:reset\[/){
-			my @ports=$top->top_get_intfc_ports_list($intfc);
-			foreach my $p (@ports){
-				my($inst,$range,$type,$intfc_name,$intfc_port)= $top->top_get_port($p);
-				$soc_v=$soc_v.',' if ($i);	
-				my $src =  $mpsoc->object_get_attribute('SOURCE_SET_CONNECT',"T${tile_num}_$p");
-				$src = 'reset0' if(!defined $src);
-				$soc_v=$soc_v."\n\t\t.$p(${src} )";#| jtag_system_reset)";				
-			    $i=1;		
-				
-			}		
-		}
-		#enable
-		elsif( $intfc =~ /plug:enable\[/){
-			my @ports=$top->top_get_intfc_ports_list($intfc);
-			foreach my $p (@ports){
-				my($inst,$range,$type,$intfc_name,$intfc_port)= $top->top_get_port($p);
-				$soc_v=$soc_v.',' if ($i);	
-				$soc_v=$soc_v."\n\t\t.$p(processors_en)";
-			    $processor_en=1;
-			    $i=1;			
-			}			
-		}
-		#RxD_sim
-		elsif( $intfc eq 'socket:RxD_sim[0]'){
-			#This interface is for simulation only donot include it in top module
-			my @ports=$top->top_get_intfc_ports_list($intfc);
-			foreach my $p (@ports){
-				$soc_v=$soc_v.',' if ($i);	
-				$soc_v=$soc_v."\n\t\t.$p( )";
-				$i=1;
-			}		
-		
-		}		
-		#jtag_to_wb	
-		elsif( $intfc =~ /socket:jtag_to_wb\[/){ #check JTAG connect parameter. if it is XILINX then connect it to jtag tap
-			my @ports=$top->top_get_intfc_ports_list($intfc);
-			
-			my $setting=$mpsoc->mpsoc_get_tile_param_setting($tile_num);
-			my %topparams;
-			#if ($setting eq 'Custom'){
-				 %topparams= $top->top_get_custom_soc_param($tile_num);
-		#	}else{
-			#	 %topparams=$top->top_get_default_soc_param();
-			#}
-		
-		
-			#my $JTAG_CONNECT=$soc->soc_get_module_param_value ($id,'JTAG_CONNECT');
-			
-			foreach my $p (@ports){
-				my($id,$range,$type,$intfc_name,$intfc_port)= $top->top_get_port($p);
-				my $inst_name=$top->top_get_def_of_instance($id,'instance');
-				my $JTAG_CONNECT=  $topparams{"${inst_name}_JTAG_CONNECT"};
-				my $chain=$topparams{"${inst_name}_JTAG_CHAIN"};	
-				my $index=$topparams{"${inst_name}_JTAG_INDEX"};	
-				#print Dumper (\%topparams);
-				#print "my $JTAG_CONNECT=  \$topparams{${inst_name}_JTAG_CONNECT}\n"; 
-				
-				#print "$inst,$range,$type,$intfc_name,$intfc_port-> $JTAG_CONNECT;";
-				if($JTAG_CONNECT  =~ /XILINX_JTAG_WB/){
-					
-					my ($io_port,$type,$new_range,$intfc_name,$intfc_port)=	get_top_port_io_info($top,$p,$tile_num,\%params,\%soc_localparam);
-					my $port_def=(length ($new_range)>1 )? 	"\t$type\t [ $new_range    ] $io_port;\n": "\t$type\t\t\t$io_port;\n";			 
-					$top_ip->top_add_port("T${tile_num}" ,$io_port, $new_range ,$type,$intfc_name,$intfc_port);
-					
-					my $wire_def=(length ($new_range)>1 )? 	"\twire\t [ $new_range    ] $io_port;": "\twire\t\t\t$io_port;";			 
-				#	my $new_range = add_instantc_name_to_parameters(\%params,"${soc_name}_$soc_num",$range);
-					
-				#	$jtag_def=$jtag_def."$wire_def";
-					%jtag_info=append_to_hash (\%jtag_info,$chain,'wire',"$wire_def");
-					
-					
-					$soc_v=$soc_v.',' if ($i);	
-					$soc_v=$soc_v."\n\t\t.$p($io_port)";
-					$i=1;	
-					if($type eq 'input'){
-						%jtag_info=check_jtag_indexs(\%jtag_info,$chain,$index,$txview,$inst_name,$tile_num);
-						#$jtag_insts=$jtag_insts."$id XILINX JTAG,";
-						%jtag_info=append_to_hash (\%jtag_info,0,'inst',"$id XILINX JTAG");
-						#$xilinx_jtag_ctrl++;
-						%jtag_info=append_to_hash (\%jtag_info,$chain,'xilinx_num',1);
-						#$xilinx_jtag_ctrl_in=(length ($xilinx_jtag_ctrl_in)>2)? "$xilinx_jtag_ctrl_in,$io_port" : "$io_port";
-						%jtag_info=append_to_hash (\%jtag_info,$chain,'input',$io_port);
-					}else {
-						#$xilinx_jtag_ctrl_out=(length($xilinx_jtag_ctrl_out)>2)? "$xilinx_jtag_ctrl_out,$io_port" : "$io_port";
-						%jtag_info=append_to_hash (\%jtag_info,$chain,'output',$io_port);
-					}
-					$io_short=$io_short.",\n\t$io_port";
-					$io_full=$io_full."$port_def";
-					$top_io_pass=$top_io_pass.",\n\t\t.$io_port($io_port)";
-#					
-				}else{#Dont not connect 
-					$soc_v=$soc_v.',' if ($i);	
-					$soc_v=$soc_v."\n\t\t.$p( )";
-					$i=1;
-				}
-			
-				if($JTAG_CONNECT =~ /ALTERA_JTAG_WB/){
-					if($type eq 'input'){
-						#$jtag_insts=$jtag_insts."$id ALTERA JTAG,";
-						#$altera_jtag_ctrl++;
-						%jtag_info=append_to_hash (\%jtag_info,0,'inst',"$id ALTERA JTAG");
-						%jtag_info=append_to_hash (\%jtag_info,0,'altera_num',1);
-						%jtag_info=check_jtag_indexs(\%jtag_info,0,$index,$txview,$inst_name,$tile_num);
-						
-					}
-				}	
-				
-			}		
-		
-		}
-		
-		else {
-		#other interface
-			my @ports=$top->top_get_intfc_ports_list($intfc);
-			foreach my $p (@ports){
-				my ($io_port,$type,$new_range,$intfc_name,$intfc_port)=	get_top_port_io_info($top,$p,$tile_num,\%params,\%soc_localparam);
-				
-				$io_short=$io_short.",\n\t$io_port";
-				$top_io_short=$top_io_short.",\n\t$io_port";
-				$top_io_pass=$top_io_pass.",\n\t\t.$io_port($io_port)";
-				#io definition
-				#my $new_range = add_instantc_name_to_parameters(\%params,"${soc_name}_$soc_num",$range);
-				my $port_def=(length ($new_range)>1 )? 	"\t$type\t [ $new_range    ] $io_port;\n": "\t$type\t\t\t$io_port;\n";			 
-				$top_ip->top_add_port("T${tile_num}" ,$io_port, $new_range ,$type,$intfc_name,$intfc_port);
-				
-				$io_full=$io_full."$port_def";
-				$top_io_full=$top_io_full."$port_def";
-				$soc_v=$soc_v.',' if ($i);	
-				$soc_v=$soc_v."\n\t\t.$p($io_port)";	
-				$i=1;	
-				
-			}			
-		}			
-	}
-	
-	
-	
-	$soc_v=$soc_v."\n\t);\n";
-	
-			
-	return ($soc_v,$processor_en,$io_short,$io_full,$top_io_short,	$top_io_full,$top_io_pass,\%jtag_info);
-
+    my ($mpsoc,$top_ip,$sw_path,$soc_name,$tile_num,$soc_num,$txview,$href)=@_;
+    my %jtag_info = %{$href};
+    my $io_short="";
+    my $io_full="";
+    my $top_io_short="";
+    my $top_io_full="";
+    my $top_io_pass="";
+    my $processor_en=0;
+    my ($NE, $NR, $RAw, $EAw, $Fw)= get_topology_info ($mpsoc);
+    my $e_addr=endp_addr_encoder($mpsoc,$tile_num);
+    my $router_num = get_connected_router_id_to_endp($mpsoc,$tile_num);
+    my $r_addr=router_addr_encoder($mpsoc,$router_num);
+    my $soc_v="\n\n // Tile:$tile_num ($e_addr)\n   \t$soc_name #(\n";
+    # Global parameter
+    $soc_v=$soc_v."\t\t.CORE_ID($tile_num),\n\t\t.SW_LOC(\"$sw_path/tile$tile_num\")";
+    # ni parameter
+    my $top=$mpsoc->mpsoc_get_soc($soc_name);
+    my @nis=get_NI_instance_list($top);
+    my @noc_param=$top->top_get_parameter_list($nis[0]);
+    my $inst_name=$top->top_get_def_of_instance($nis[0],'instance');
+    #other parameters
+    my %params=$top->top_get_default_soc_param();
+    foreach my $p (@noc_param){
+        my $parm_next = $p;
+        $parm_next =~ s/${inst_name}_//;
+        my $param=  ",\n\t\t.$p($parm_next)";
+        $soc_v=$soc_v.$param;
+    }
+    foreach my $p (sort keys %params){
+        my $parm_next= "T${tile_num}_$p";
+        my $param=  ",\n\t\t.$p($parm_next)";
+        $soc_v=$soc_v.$param;
+    }
+    $soc_v=$soc_v."\n\t)the_${soc_name}_$soc_num(\n";
+    my @intfcs=$top->top_get_intfc_list();
+    my $i=0;
+    my $dir = Cwd::getcwd();
+    my $mpsoc_name=$mpsoc->object_get_attribute('mpsoc_name');
+    my $target_dir  = "$ENV{'PRONOC_WORK'}/MPSOC/$mpsoc_name";
+    my $soc_file="$target_dir/src_verilog/tiles/$soc_name.sv";
+    my $vdb =read_verilog_file($soc_file);
+    my %soc_localparam = $vdb->get_modules_parameters($soc_name);
+    foreach my $intfc (@intfcs){
+        # ni intfc
+        if( $intfc eq 'socket:ni[0]'){
+            my @ports=$top->top_get_intfc_ports_list($intfc);
+            foreach my $p (@ports){
+                my($inst,$range,$type,$intfc_name,$intfc_port)= $top->top_get_port($p);
+                my $q=    ($intfc_port eq "current_e_addr")? "$EAw\'d$e_addr" :
+                        ($intfc_port eq "current_r_addr")? "$RAw\'d$r_addr" :
+                        "ni_$intfc_port\[$tile_num\]";
+                $soc_v=$soc_v.',' if ($i);
+                $soc_v=$soc_v."\n\t\t.$p($q)";
+                $i=1;
+            }
+        }
+        # clk source
+        elsif( $intfc =~ /plug:clk\[/ ){
+            my @ports=$top->top_get_intfc_ports_list($intfc);
+            foreach my $p (@ports){
+                my($inst,$range,$type,$intfc_name,$intfc_port)= $top->top_get_port($p);
+                $soc_v=$soc_v.',' if ($i);
+                my $src =  $mpsoc->object_get_attribute('SOURCE_SET_CONNECT',"T${tile_num}_$p");
+                $src = 'clk0' if(!defined $src);
+                $soc_v=$soc_v."\n\t\t.$p($src)";
+                $i=1;
+            }
+        }
+        #reset
+        elsif( $intfc =~ /plug:reset\[/){
+            my @ports=$top->top_get_intfc_ports_list($intfc);
+            foreach my $p (@ports){
+                my($inst,$range,$type,$intfc_name,$intfc_port)= $top->top_get_port($p);
+                $soc_v=$soc_v.',' if ($i);
+                my $src =  $mpsoc->object_get_attribute('SOURCE_SET_CONNECT',"T${tile_num}_$p");
+                $src = 'reset0' if(!defined $src);
+                $soc_v=$soc_v."\n\t\t.$p(${src} )";#| jtag_system_reset)";
+                $i=1;
+            }
+        }
+        #enable
+        elsif( $intfc =~ /plug:enable\[/){
+            my @ports=$top->top_get_intfc_ports_list($intfc);
+            foreach my $p (@ports){
+                my($inst,$range,$type,$intfc_name,$intfc_port)= $top->top_get_port($p);
+                $soc_v=$soc_v.',' if ($i);
+                $soc_v=$soc_v."\n\t\t.$p(processors_en)";
+                $processor_en=1;
+                $i=1;
+            }
+        }
+        #RxD_sim
+        elsif( $intfc eq 'socket:RxD_sim[0]'){
+            #This interface is for simulation only donot include it in top module
+            my @ports=$top->top_get_intfc_ports_list($intfc);
+            foreach my $p (@ports){
+                $soc_v=$soc_v.',' if ($i);
+                $soc_v=$soc_v."\n\t\t.$p( )";
+                $i=1;
+            }
+        }
+        #jtag_to_wb
+        elsif( $intfc =~ /socket:jtag_to_wb\[/){ #check JTAG connect parameter. if it is XILINX then connect it to jtag tap
+            my @ports=$top->top_get_intfc_ports_list($intfc);
+            my $setting=$mpsoc->mpsoc_get_tile_param_setting($tile_num);
+            my %topparams;
+            #if ($setting eq 'Custom'){
+                %topparams= $top->top_get_custom_soc_param($tile_num);
+        #    }else{
+            #     %topparams=$top->top_get_default_soc_param();
+            #}
+            #my $JTAG_CONNECT=$soc->soc_get_module_param_value ($id,'JTAG_CONNECT');
+            foreach my $p (@ports){
+                my($id,$range,$type,$intfc_name,$intfc_port)= $top->top_get_port($p);
+                my $inst_name=$top->top_get_def_of_instance($id,'instance');
+                my $JTAG_CONNECT=  $topparams{"${inst_name}_JTAG_CONNECT"};
+                my $chain=$topparams{"${inst_name}_JTAG_CHAIN"};
+                my $index=$topparams{"${inst_name}_JTAG_INDEX"};
+                #print Dumper (\%topparams);
+                #print "my $JTAG_CONNECT=  \$topparams{${inst_name}_JTAG_CONNECT}\n";
+                #print "$inst,$range,$type,$intfc_name,$intfc_port-> $JTAG_CONNECT;";
+                if($JTAG_CONNECT  =~ /XILINX_JTAG_WB/){
+                    my ($io_port,$type,$new_range,$intfc_name,$intfc_port)=    get_top_port_io_info($top,$p,$tile_num,\%params,\%soc_localparam);
+                    my $port_def=(length ($new_range)>1 )?     "\t$type\t [ $new_range    ] $io_port;\n": "\t$type\t\t\t$io_port;\n";
+                    $top_ip->top_add_port("T${tile_num}" ,$io_port, $new_range ,$type,$intfc_name,$intfc_port);
+                    my $wire_def=(length ($new_range)>1 )?     "\twire\t [ $new_range    ] $io_port;": "\twire\t\t\t$io_port;";
+                #    my $new_range = add_instantc_name_to_parameters(\%params,"${soc_name}_$soc_num",$range);
+                #    $jtag_def=$jtag_def."$wire_def";
+                    %jtag_info=append_to_hash (\%jtag_info,$chain,'wire',"$wire_def");
+                    $soc_v=$soc_v.',' if ($i);
+                    $soc_v=$soc_v."\n\t\t.$p($io_port)";
+                    $i=1;
+                    if($type eq 'input'){
+                        %jtag_info=check_jtag_indexs(\%jtag_info,$chain,$index,$txview,$inst_name,$tile_num);
+                        #$jtag_insts=$jtag_insts."$id XILINX JTAG,";
+                        %jtag_info=append_to_hash (\%jtag_info,0,'inst',"$id XILINX JTAG");
+                        #$xilinx_jtag_ctrl++;
+                        %jtag_info=append_to_hash (\%jtag_info,$chain,'xilinx_num',1);
+                        #$xilinx_jtag_ctrl_in=(length ($xilinx_jtag_ctrl_in)>2)? "$xilinx_jtag_ctrl_in,$io_port" : "$io_port";
+                        %jtag_info=append_to_hash (\%jtag_info,$chain,'input',$io_port);
+                    }else {
+                        #$xilinx_jtag_ctrl_out=(length($xilinx_jtag_ctrl_out)>2)? "$xilinx_jtag_ctrl_out,$io_port" : "$io_port";
+                        %jtag_info=append_to_hash (\%jtag_info,$chain,'output',$io_port);
+                    }
+                    $io_short=$io_short.",\n\t$io_port";
+                    $io_full=$io_full."$port_def";
+                    $top_io_pass=$top_io_pass.",\n\t\t.$io_port($io_port)";
+#
+                }else{#Dont not connect
+                    $soc_v=$soc_v.',' if ($i);
+                    $soc_v=$soc_v."\n\t\t.$p( )";
+                    $i=1;
+                }
+                if($JTAG_CONNECT =~ /ALTERA_JTAG_WB/){
+                    if($type eq 'input'){
+                        #$jtag_insts=$jtag_insts."$id ALTERA JTAG,";
+                        #$altera_jtag_ctrl++;
+                        %jtag_info=append_to_hash (\%jtag_info,0,'inst',"$id ALTERA JTAG");
+                        %jtag_info=append_to_hash (\%jtag_info,0,'altera_num',1);
+                        %jtag_info=check_jtag_indexs(\%jtag_info,0,$index,$txview,$inst_name,$tile_num);
+                    }
+                }
+            }
+        }
+        else {
+        #other interface
+            my @ports=$top->top_get_intfc_ports_list($intfc);
+            foreach my $p (@ports){
+                my ($io_port,$type,$new_range,$intfc_name,$intfc_port)=    get_top_port_io_info($top,$p,$tile_num,\%params,\%soc_localparam);
+                $io_short=$io_short.",\n\t$io_port";
+                $top_io_short=$top_io_short.",\n\t$io_port";
+                $top_io_pass=$top_io_pass.",\n\t\t.$io_port($io_port)";
+                #io definition
+                #my $new_range = add_instantc_name_to_parameters(\%params,"${soc_name}_$soc_num",$range);
+                my $port_def=(length ($new_range)>1 )?     "\t$type\t [ $new_range    ] $io_port;\n": "\t$type\t\t\t$io_port;\n";
+                $top_ip->top_add_port("T${tile_num}" ,$io_port, $new_range ,$type,$intfc_name,$intfc_port);
+                $io_full=$io_full."$port_def";
+                $top_io_full=$top_io_full."$port_def";
+                $soc_v=$soc_v.',' if ($i);
+                $soc_v=$soc_v."\n\t\t.$p($io_port)";
+                $i=1;
+            }
+        }
+    }
+    $soc_v=$soc_v."\n\t);\n";
+    return ($soc_v,$processor_en,$io_short,$io_full,$top_io_short,    $top_io_full,$top_io_pass,\%jtag_info);
 }
 
-
 sub check_jtag_indexs{
-	my ($ref,$chain,$index,$txview,$inst_name,$core_id)=@_;
-	my %jtag_info = %{$ref} if (defined $ref);
-	
-	chomp $index;   
-	# replace coreid parameter  	
-	($index=$index)=~ s/CORE_ID/$core_id/g; 
-	$index = eval $index;
-	my $inst1 =$jtag_info{$chain}{'index'}{$index};
-	my $id1 = $jtag_info{$chain}{'core_id'}{$index};
-	if (defined $inst1){
-		add_colored_info($txview,"Error: The JTAG INDEX number $index in JTAG Chain $chain is not unique. The same index number is used in tile($id1):$inst1  & tile($core_id):$inst_name  IPs. It should be used in only one module.\n",'red');				
-	}
-	$jtag_info{$chain}{'index'}{$index}=$inst_name;
-	$jtag_info{$chain}{'core_id'}{$index}=$core_id;
-	#print "\$jtag_info{$chain}{'index'}{$index}=$inst_name\n";
-	return %jtag_info;
+    my ($ref,$chain,$index,$txview,$inst_name,$core_id)=@_;
+    my %jtag_info = %{$ref} if (defined $ref);
+    chomp $index;
+    # replace coreid parameter
+    ($index=$index)=~ s/CORE_ID/$core_id/g;
+    $index = eval $index;
+    my $inst1 =$jtag_info{$chain}{'index'}{$index};
+    my $id1 = $jtag_info{$chain}{'core_id'}{$index};
+    if (defined $inst1){
+        add_colored_info($txview,"Error: The JTAG INDEX number $index in JTAG Chain $chain is not unique. The same index number is used in tile($id1):$inst1  & tile($core_id):$inst_name  IPs. It should be used in only one module.\n",'red');
+    }
+    $jtag_info{$chain}{'index'}{$index}=$inst_name;
+    $jtag_info{$chain}{'core_id'}{$index}=$core_id;
+    #print "\$jtag_info{$chain}{'index'}{$index}=$inst_name\n";
+    return %jtag_info;
 }
 
-
-
 sub get_top_clk_setting{
-	my $mpsoc=shift;
+    my $mpsoc=shift;
     #get mpsoc with clock setting interface
-	my $dir = Cwd::getcwd();
-	my $soc =get_source_set_top($mpsoc);
-	
+    my $dir = Cwd::getcwd();
+    my $soc =get_source_set_top($mpsoc);
     my @instances=$soc->soc_get_all_instances();
     my $top_ip=ip_gen->top_gen_new();
     my $body_v;
-    my $param_pass_v="";	
+    my $param_pass_v="";
     my $io_sim_v;
-	my $io_top_sim_v;
-	my $core_id= 0 ;
-	my $param_as_in_v="";
-	my $local_param_v_all="";
-	my $inst_v_all="";
+    my $io_top_sim_v;
+    my $core_id= 0 ;
+    my $param_as_in_v="";
+    my $local_param_v_all="";
+    my $inst_v_all="";
     my $param_v_all="";
     my $wire_def_v_all="";
-	my $plugs_assign_v_all="";
-	my $sockets_assign_v_all="";
-	my $io_full_v_all="";
-	my $io_top_full_v_all="";
-	my $io_sim_v_all;
-	my $system_v_all="";
-	
-	my $wires=soc->new_wires();
-	my $intfc=interface->interface_new();
-	my $clk_assigned_port;
+    my $plugs_assign_v_all="";
+    my $sockets_assign_v_all="";
+    my $io_full_v_all="";
+    my $io_top_full_v_all="";
+    my $io_sim_v_all;
+    my $system_v_all="";
+    my $wires=soc->new_wires();
+    my $intfc=interface->interface_new();
+    my $clk_assigned_port;
     foreach my $id (@instances){
-    	my ($param_v, $local_param_v, $wire_def_v, $inst_v, $plugs_assign_v, $sockets_assign_v,$io_full_v,$io_top_full_v,$io_sim_v,
-		$top_io_short,$param_as_in_v,$param_pass_v,$system_v,$assigned_ports,$top_io_pass,$src_io_short, $src_io_full)=gen_module_inst($id,$soc,$top_ip,$intfc,$wires);
-    	
-		#my ($param_v, $local_param_v, $wire_def_v, $inst_v, $plugs_assign_v, $sockets_assign_v,$io_full_v,$io_top_full_v,$system_v,$assigned_ports)=gen_module_inst($id,$soc,\$io_sim_v,\$io_top_sim_v,\$param_as_in_v,$top_ip,$intfc,$wires,\$param_pass_v,\$system_v);
-   		my $inst   	= $soc->soc_get_instance_name($id);
-		if ($id ne 'TOP'){
-			add_text_to_string(\$body_v,"/*******************\n*\n*\t$inst\n*\n*\n*********************/\n");
-			add_text_to_string(\$system_v_all,"$system_v\n")   	if(defined($system_v)); 
-			add_text_to_string(\$local_param_v_all,"$local_param_v\n")   	if(defined($local_param_v)); 
-			add_text_to_string(\$wire_def_v_all,"$wire_def_v\n")		 	if(defined($wire_def_v));
-			add_text_to_string(\$inst_v_all,$inst_v)					 	if(defined($inst_v));
-			add_text_to_string(\$plugs_assign_v_all,"$plugs_assign_v\n") 	if(defined($plugs_assign_v));
-			add_text_to_string(\$sockets_assign_v_all,"$sockets_assign_v\n")if(defined($sockets_assign_v));
-			add_text_to_string(\$io_full_v_all,"$io_full_v\n")				if(length($io_full_v)>3);
-			add_text_to_string(\$io_top_full_v_all,"$io_top_full_v\n")		if(length($io_top_full_v)>3);
-			$io_sim_v_all     = (defined $io_sim_v_all    )? "$io_sim_v_all,\n$io_sim_v"         : $io_sim_v  	    	if(defined($io_sim_v)); 
-		}else{
-			add_text_to_string(\$system_v_all,"$system_v\n")   	if(defined($system_v)); 
-			add_text_to_string(\$wire_def_v_all,"$wire_def_v\n")		 	if(defined($wire_def_v));
-			add_text_to_string(\$plugs_assign_v_all,"$plugs_assign_v\n") 	if(defined($plugs_assign_v));
-			add_text_to_string(\$sockets_assign_v_all,"$sockets_assign_v\n")if(defined($sockets_assign_v));
-			add_text_to_string(\$io_full_v_all,"$io_full_v\n")				if(length($io_full_v)>3);
-			$io_sim_v_all     = (defined $io_sim_v_all    )? "$io_sim_v_all,\n$io_sim_v"         : $io_sim_v  	    	if(defined($io_sim_v)); 
-			add_text_to_string(\$io_top_full_v_all,"$io_top_full_v\n")			if(length($io_top_full_v)>3);		
-			$clk_assigned_port= (defined $clk_assigned_port)? "$clk_assigned_port,\n$assigned_ports"  : $assigned_ports if(defined $assigned_ports);
-		} 
-   
-    }	
-    
-    
-       
-    
-    
-    
+        my ($param_v, $local_param_v, $wire_def_v, $inst_v, $plugs_assign_v, $sockets_assign_v,$io_full_v,$io_top_full_v,$io_sim_v,
+        $top_io_short,$param_as_in_v,$param_pass_v,$system_v,$assigned_ports,$top_io_pass,$src_io_short, $src_io_full)=gen_module_inst($id,$soc,$top_ip,$intfc,$wires);
+        #my ($param_v, $local_param_v, $wire_def_v, $inst_v, $plugs_assign_v, $sockets_assign_v,$io_full_v,$io_top_full_v,$system_v,$assigned_ports)=gen_module_inst($id,$soc,\$io_sim_v,\$io_top_sim_v,\$param_as_in_v,$top_ip,$intfc,$wires,\$param_pass_v,\$system_v);
+        my $inst       = $soc->soc_get_instance_name($id);
+        if ($id ne 'TOP'){
+            add_text_to_string(\$body_v,"/*******************\n*\n*\t$inst\n*\n*\n*********************/\n");
+            add_text_to_string(\$system_v_all,"$system_v\n")       if(defined($system_v));
+            add_text_to_string(\$local_param_v_all,"$local_param_v\n")       if(defined($local_param_v));
+            add_text_to_string(\$wire_def_v_all,"$wire_def_v\n")             if(defined($wire_def_v));
+            add_text_to_string(\$inst_v_all,$inst_v)                         if(defined($inst_v));
+            add_text_to_string(\$plugs_assign_v_all,"$plugs_assign_v\n")     if(defined($plugs_assign_v));
+            add_text_to_string(\$sockets_assign_v_all,"$sockets_assign_v\n")if(defined($sockets_assign_v));
+            add_text_to_string(\$io_full_v_all,"$io_full_v\n")                if(length($io_full_v)>3);
+            add_text_to_string(\$io_top_full_v_all,"$io_top_full_v\n")        if(length($io_top_full_v)>3);
+            $io_sim_v_all     = (defined $io_sim_v_all    )? "$io_sim_v_all,\n$io_sim_v"         : $io_sim_v              if(defined($io_sim_v));
+        }else{
+            add_text_to_string(\$system_v_all,"$system_v\n")       if(defined($system_v));
+            add_text_to_string(\$wire_def_v_all,"$wire_def_v\n")             if(defined($wire_def_v));
+            add_text_to_string(\$plugs_assign_v_all,"$plugs_assign_v\n")     if(defined($plugs_assign_v));
+            add_text_to_string(\$sockets_assign_v_all,"$sockets_assign_v\n")if(defined($sockets_assign_v));
+            add_text_to_string(\$io_full_v_all,"$io_full_v\n")                if(length($io_full_v)>3);
+            $io_sim_v_all     = (defined $io_sim_v_all    )? "$io_sim_v_all,\n$io_sim_v"         : $io_sim_v              if(defined($io_sim_v));
+            add_text_to_string(\$io_top_full_v_all,"$io_top_full_v\n")            if(length($io_top_full_v)>3);
+            $clk_assigned_port= (defined $clk_assigned_port)? "$clk_assigned_port,\n$assigned_ports"  : $assigned_ports if(defined $assigned_ports);
+        }
+    }
     my $unused_wiers_v=assign_unconnected_wires($wires,$intfc);
     $unused_wiers_v= "" if(!defined $unused_wiers_v);
-    
-   my $soc_v = "
-   $system_v_all
-   $local_param_v_all  
-   $wire_def_v_all
-   $unused_wiers_v
-   $inst_v_all
-   $plugs_assign_v_all
-   $sockets_assign_v_all
-
-";
-	my $clk_io_full= $io_full_v_all;
-	my $clk_io_sim=$io_sim_v_all;
-	return ($soc_v,$clk_io_sim,$clk_io_full,$clk_assigned_port);
-
+    my $soc_v = "
+    $system_v_all
+    $local_param_v_all
+    $wire_def_v_all
+    $unused_wiers_v
+    $inst_v_all
+    $plugs_assign_v_all
+    $sockets_assign_v_all
+    ";
+    my $clk_io_full= $io_full_v_all;
+    my $clk_io_sim=$io_sim_v_all;
+    return ($soc_v,$clk_io_sim,$clk_io_full,$clk_assigned_port);
 }
 
 sub get_top_port_io_info{
-	my ($top,$port,$tile_num,$params_ref,$local_param_ref)=@_;
-	my %params =%{$params_ref} if(defined $params_ref);
-	my %localparams=%{$local_param_ref} if(defined $local_param_ref);
-	my($inst,$range,$type,$intfc_name,$intfc_port)= $top->top_get_port($port);
-	my $io_port="T${tile_num}_${port}";
+    my ($top,$port,$tile_num,$params_ref,$local_param_ref)=@_;
+    my %params =%{$params_ref} if(defined $params_ref);
+    my %localparams=%{$local_param_ref} if(defined $local_param_ref);
+    my($inst,$range,$type,$intfc_name,$intfc_port)= $top->top_get_port($port);
+    my $io_port="T${tile_num}_${port}";
     #resolve range parameter
-	if (defined $range ){
-			my @a= split (/\b/,$range);			
-			foreach my $l (@a){
-				#if defined in parameter list ignore it
-				next  if(defined $params{$l});
-				($range=$range)=~ s/\b$l\b/$localparams{$l}/g      if(defined $localparams{$l});
-			}
-	}
-	my $new_range = add_instantc_name_to_parameters(\%params,"T${tile_num}",$range);
-	return ($io_port,$type,$new_range,$intfc_name,$intfc_port);
+    if (defined $range ){
+            my @a= split (/\b/,$range);
+            foreach my $l (@a){
+                #if defined in parameter list ignore it
+                next  if(defined $params{$l});
+                ($range=$range)=~ s/\b$l\b/$localparams{$l}/g      if(defined $localparams{$l});
+            }
+    }
+    my $new_range = add_instantc_name_to_parameters(\%params,"T${tile_num}",$range);
+    return ($io_port,$type,$new_range,$intfc_name,$intfc_port);
 }
-
-
-
-
-
-	
-
-
 1
diff --git a/mpsoc/perl_gui/lib/perl/network_maker.pl b/mpsoc/perl_gui/lib/perl/network_maker.pl
index c2b83cb..6f1a589 100644
--- a/mpsoc/perl_gui/lib/perl/network_maker.pl
+++ b/mpsoc/perl_gui/lib/perl/network_maker.pl
@@ -2,2688 +2,2040 @@
 use strict;
 use warnings;
 use constant::boolean;
-
 use Cwd 'abs_path';
 use base 'Class::Accessor::Fast';
-require "widget.pl"; 
+require "widget.pl";
 require "diagram.pl";
 require "topology_verilog_gen.pl";
-
 use String::Scanf; # imports sscanf()
-
 use FindBin;
 use lib $FindBin::Bin;
 use tsort;
-
 use File::Basename;
 use Cwd 'abs_path';
+use YAML::PP;
+use YAML::PP::Common;
+use Data::Dumper;
 
 __PACKAGE__->mk_accessors(qw{
-	window
-	sourceview		
+    window
+    sourceview
 });
 
 my $NAME = 'Network_maker';
 exit network_maker_main() unless caller;
 
-
 sub network_maker_main {
-	my $app = __PACKAGE__->new();
-	
-	my @parameters = (
-	{param_name=> "V ", value=>2},    
-    {param_name=> "B ", value=>4},    
-    {param_name=> "C ", value=>2},     
+    my $app = __PACKAGE__->new();
+    my @parameters = (
+    {param_name=> "V ", value=>2},
+    {param_name=> "B ", value=>4},
+    {param_name=> "C ", value=>2},
     {param_name=> "Fpay ", value=>32},
-    {param_name=> "MUX_TYPE", value=>'"ONE_HOT"'},    
+    {param_name=> "MUX_TYPE", value=>'"ONE_HOT"'},
     {param_name=> "VC_REALLOCATION_TYPE ", value=>'"NONATOMIC"'},
     {param_name=> "COMBINATION_TYPE", value=>'"COMB_NONSPEC"'},
-    {param_name=> "FIRST_ARBITER_EXT_P_EN ", value=>1},  
+    {param_name=> "FIRST_ARBITER_EXT_P_EN ", value=>1},
     {param_name=> "CONGESTION_INDEX ", value=>7},
     {param_name=> "DEBUG_EN", value=>0},
     {param_name=> "AVC_ATOMIC_EN", value=>0},
     {param_name=> "ADD_PIPREG_AFTER_CROSSBAR", value=>0},
     {param_name=> "CVw", value=>"(C==0)? V : C * V"},
-    {param_name=> "CLASS_SETTING ", value=>"{CVw{1\'b1}}"}, 
-    {param_name=> "SSA_EN", value=>'"NO"'},
-    {param_name=> "SWA_ARBITER_TYPE ", value=>'"RRA"'}, 
-    {param_name=> "WEIGHTw ", value=>7},  
+    {param_name=> "CLASS_SETTING ", value=>"{CVw{1\'b1}}"},
+    {param_name=> "SSA_EN", value=>'0'},
+    {param_name=> "SWA_ARBITER_TYPE ", value=>'"RRA"'},
+    {param_name=> "WEIGHTw ", value=>7},
     {param_name=> "MIN_PCK_SIZE", value=>2},
     {param_name=> "BYTE_EN", value=>0}
-); 
-
-my @ports =(
-	{name=> "flit_in_all", type=>"input", width=>"PFw", connect=>"flit_out_all",  pwidth=>"Fw", pname=> "flit_in", pconnect=>"flit_out", endp=>"yes"},
-	{name=> "flit_in_wr_all", type=>"input", width=>"P", connect=>"flit_out_wr_all",  pwidth=>1, pname=> "flit_in_wr", pconnect=>"flit_out_wr",endp=>"yes"},
-	{name=> "congestion_in_all", type=>"input", width=>"CONG_ALw", connect=>"congestion_out_all",  pwidth=>"CONGw", pname=> "congestion_in", pconnect=>"congestion_out",endp=>"no"},
-	{name=> "credit_out_all", type=>"output", width=>"PV", connect=>"credit_in_all",  pwidth=>"V" ,pname=> "credit_out", pconnect=>"credit_in",endp=>"yes"}
-);
-
-  
-  $app->object_add_attribute ('Verilog','Router_param',\@parameters);
-  $app->object_add_attribute ('Verilog','Router_ports',\@ports);
- 
-  
-
-	
-	my $table=$app->build_network_maker_gui();
-	return $table;
+    );
+    my @ports =(
+    {name=> "flit_in_all", type=>"input", width=>"PFw", connect=>"flit_out_all",  pwidth=>"Fw", pname=> "flit_in", pconnect=>"flit_out", endp=>"yes"},
+    {name=> "flit_in_wr_all", type=>"input", width=>"P", connect=>"flit_out_wr_all",  pwidth=>1, pname=> "flit_in_wr", pconnect=>"flit_out_wr",endp=>"yes"},
+    {name=> "congestion_in_all", type=>"input", width=>"CONG_ALw", connect=>"congestion_out_all",  pwidth=>"CONGw", pname=> "congestion_in", pconnect=>"congestion_out",endp=>"no"},
+    {name=> "credit_out_all", type=>"output", width=>"PV", connect=>"credit_in_all",  pwidth=>"V" ,pname=> "credit_out", pconnect=>"credit_in",endp=>"yes"}
+    );
+    $app->object_add_attribute ('Verilog','Router_param',\@parameters);
+    $app->object_add_attribute ('Verilog','Router_ports',\@ports);
+    my $table=$app->build_network_maker_gui();
+    return $table;
 }
 
-
 sub custom_topology_diagram {
-	my $self= shift;
-	
-	
-	
-	my $table=def_table(20,20,FALSE);
-	my $scrolled_win = add_widget_to_scrolled_win();	
-	
-	
-	my ($col,$row)=(0,0);
-	
-	
-	
-	
-	my $plus = def_image_button('icons/plus.png',undef,TRUE);
-	my $minues = def_image_button('icons/minus.png',undef,TRUE);
-	my $save = def_image_button('icons/save.png',undef,TRUE);
-	my $dot_file = def_image_button('icons/add-notes.png',undef,TRUE);	
-	set_tip($dot_file, "Show dot file.");
-	
-	my $scale=$self->object_get_attribute("tile_diagram","scale");
-	$scale= 1 if (!defined $scale);	
-	
-	my $state=$self->object_get_attribute("tile_diagram","auto_draw");
-	if (!defined $state){
-		$state='ON' ;
-		$self->object_add_attribute("tile_diagram","auto_draw",$state);
-	}		
-	my $auto= ($state eq 'ON')? def_colored_button('ON',17): def_colored_button('OFF',4);
-	
-	
-	my $gtype=$self->object_get_attribute("tile_diagram","gtype");
-	if (!defined $gtype){
-		$gtype='comp' ;
-		$self->object_add_attribute("tile_diagram","gtype",$gtype);
-	}		
-	my $graph_type= ($gtype eq 'comp')? def_colored_button('comp',17): def_colored_button('simple',4);
-	
-	
-	
-	
-	
-	
-	$table->attach (gen_label_in_center  ("Auto Draw") ,  $col, $col+1,$row,$row+1,'shrink','shrink',2,2); $row++;
-	$table->attach ($auto ,  $col, $col+1,$row,$row+1,'shrink','shrink',2,2); $row++;
-	$table->attach ($graph_type ,  $col, $col+1,$row,$row+1,'shrink','shrink',2,2); $row++;
-	$table->attach ($plus ,  $col, $col+1,$row,$row+1,'shrink','shrink',2,2); $row++;
-	$table->attach ($minues,  $col, $col+1,$row,$row+1,'shrink','shrink',2,2); $row++;
-	$table->attach ($save,  $col, $col+1,$row,$row+1,'shrink','shrink',2,2); $row++;
-	$table->attach ($dot_file,  $col, $col+1,$row,$row+1,'shrink','shrink',2,2); $row++;
-	
-	$table->attach_defaults ($scrolled_win, 1, 20, 0, 20); #,'fill','shrink',2,2);
-	
- 	($col,$row)=(1,0);
-	while ($row<20){		
-		my $tmp=gen_label_in_left('');
-		$table->attach_defaults ($tmp, $col,  $col+1,$row,$row+1);$row++;
-	}
-	
-	$plus  -> signal_connect("clicked" => sub{ 
-		$scale*=1.1 if ($scale <10);
-		$self->object_add_attribute("topology_diagram","scale", $scale );
-		show_custom_topology_diagram ($self,$scrolled_win,"topology_diagram");
-	});	
-	$minues  -> signal_connect("clicked" => sub{ 
-		$scale*=.9  if ($scale >0.1); ;
-		$self->object_add_attribute("topology_diagram","scale", $scale );
-		show_custom_topology_diagram ($self,$scrolled_win,"topology_diagram");
-	});
-	$save-> signal_connect("clicked" => sub{ 
-			save_inline_diagram_as ($self);
-		});	
-	
-	$dot_file-> signal_connect("clicked" => sub{ 
-			my $dotfile = generate_custom_topology_dot_file($self);
-			show_text_in_scrolled_win($self,$scrolled_win, $dotfile);		
-	});
-	
-	
-	$auto -> signal_connect("clicked" => sub{ 
-			my $state=$self->object_get_attribute("tile_diagram","auto_draw");
-			
-			
-			my $new = ($state eq "ON")? "OFF" : "ON";
-			$self->object_add_attribute("tile_diagram","auto_draw",$new);	
-			set_gui_status($self,"ref",1);		
-		});	
-	
-	$graph_type-> signal_connect("clicked" => sub{ 
-			my $state=$self->object_get_attribute("tile_diagram","gtype");
-			
-			
-			my $new = ($state eq "simple")? "comp" : "simple";
-			$self->object_add_attribute("tile_diagram","gtype",$new);	
-			set_gui_status($self,"ref",1);		
-		});	
-	
-	if ($state eq 'ON'){
-		show_custom_topology_diagram ($self,$scrolled_win,"topology_diagram");
-	}
-	
-	return add_widget_to_scrolled_win ($table);
-	
+    my $self= shift;
+    my $table=def_table(20,20,FALSE);
+    my $scrolled_win = add_widget_to_scrolled_win();
+    my ($col,$row)=(0,0);
+    my $plus = def_image_button('icons/plus.png',undef,TRUE);
+    my $minues = def_image_button('icons/minus.png',undef,TRUE);
+    my $save = def_image_button('icons/save.png',undef,TRUE);
+    my $dot_file = def_image_button('icons/add-notes.png',undef,TRUE);
+    set_tip($dot_file, "Show dot file.");
+    my $scale=$self->object_get_attribute("tile_diagram","scale");
+    $scale= 1 if (!defined $scale);
+    my $state=$self->object_get_attribute("tile_diagram","auto_draw");
+    if (!defined $state){
+        $state='ON' ;
+        $self->object_add_attribute("tile_diagram","auto_draw",$state);
+    }
+    my $auto= ($state eq 'ON')? def_colored_button('ON',17): def_colored_button('OFF',4);
+    my $gtype=$self->object_get_attribute("tile_diagram","gtype");
+    if (!defined $gtype){
+        $gtype='comp' ;
+        $self->object_add_attribute("tile_diagram","gtype",$gtype);
+    }
+    my $graph_type= ($gtype eq 'comp')? def_colored_button('comp',17): def_colored_button('simple',4);
+    $table->attach (gen_label_in_center  ("Auto Draw") ,  $col, $col+1,$row,$row+1,'shrink','shrink',2,2); $row++;
+    $table->attach ($auto ,  $col, $col+1,$row,$row+1,'shrink','shrink',2,2); $row++;
+    $table->attach ($graph_type ,  $col, $col+1,$row,$row+1,'shrink','shrink',2,2); $row++;
+    $table->attach ($plus ,  $col, $col+1,$row,$row+1,'shrink','shrink',2,2); $row++;
+    $table->attach ($minues,  $col, $col+1,$row,$row+1,'shrink','shrink',2,2); $row++;
+    $table->attach ($save,  $col, $col+1,$row,$row+1,'shrink','shrink',2,2); $row++;
+    $table->attach ($dot_file,  $col, $col+1,$row,$row+1,'shrink','shrink',2,2); $row++;
+    $table->attach_defaults ($scrolled_win, 1, 20, 0, 20); #,'fill','shrink',2,2);
+    ($col,$row)=(1,0);
+    while ($row<20){
+        my $tmp=gen_label_in_left('');
+        $table->attach_defaults ($tmp, $col,  $col+1,$row,$row+1);$row++;
+    }
+    $plus  -> signal_connect("clicked" => sub{
+        $scale*=1.1 if ($scale <10);
+        $self->object_add_attribute("topology_diagram","scale", $scale );
+        show_custom_topology_diagram ($self,$scrolled_win,"topology_diagram");
+    });
+    $minues  -> signal_connect("clicked" => sub{
+        $scale*=.9  if ($scale >0.1); ;
+        $self->object_add_attribute("topology_diagram","scale", $scale );
+        show_custom_topology_diagram ($self,$scrolled_win,"topology_diagram");
+    });
+    $save-> signal_connect("clicked" => sub{
+            save_inline_diagram_as ($self);
+        });
+    $dot_file-> signal_connect("clicked" => sub{
+            my $dotfile = generate_custom_topology_dot_file($self);
+            show_text_in_scrolled_win($self,$scrolled_win, $dotfile);
+    });
+    $auto -> signal_connect("clicked" => sub{
+            my $state=$self->object_get_attribute("tile_diagram","auto_draw");
+            my $new = ($state eq "ON")? "OFF" : "ON";
+            $self->object_add_attribute("tile_diagram","auto_draw",$new);
+            set_gui_status($self,"ref",1);
+        });
+    $graph_type-> signal_connect("clicked" => sub{
+            my $state=$self->object_get_attribute("tile_diagram","gtype");
+            my $new = ($state eq "simple")? "comp" : "simple";
+            $self->object_add_attribute("tile_diagram","gtype",$new);
+            set_gui_status($self,"ref",1);
+        });
+    if ($state eq 'ON'){
+        show_custom_topology_diagram ($self,$scrolled_win,"topology_diagram");
+    }
+    return add_widget_to_scrolled_win ($table);
 }
 
-
-
-
-
 sub gen_right_paned {
-	my ($self,$info) =@_;
-	my $page_num=$self->object_get_attribute ("process_notebook","currentpage");
-	
-	return route_info_window($self,$info) if($page_num==3);
-	return custom_topology_diagram ($self,$info);
-	
+    my ($self,$info) =@_;
+    my $page_num=$self->object_get_attribute ("process_notebook","currentpage");
+    return route_info_window($self,$info) if($page_num==3);
+    return custom_topology_diagram ($self,$info);
 }
 
-
-
-
 sub endp_node_dot_comp {
-	my ($T,$instance)=@_;
-	
-	
-	return 
-	"
-	$T\[
-	label = \"$instance\"
+    my ($T,$instance)=@_;
+    return
+    "
+    $T\[
+    label = \"$instance\"
     shape=house
     margin=0
-	color=orange
-	style=filled
-	fillcolor=orange
+    color=orange
+    style=filled
+    fillcolor=orange
 ];
-";	
+";
 }
 
 sub router_node_dot_comp{
-	my ($Pnum,$R,$instance)=@_;	
-	$Pnum=1 if(!defined $Pnum);
-	my $label =
-		($Pnum==2)? "                        \{<p1>1|$instance|<p0>0\}":
-		($Pnum==3)? "\{     |<p2>2|     \} | \{<p1>1|$instance|<p0>0\} ":
-		($Pnum==4)? "\{     |<p3>3|     \} | \{<p2>2|$instance|<p0>0\} | \{  <p1>1\}":
-		($Pnum==5)? "\{     |<p3>3|     \} | \{<p2>2|$instance|<p4>4\} | \{ |<p1>1|<p0>0\}":
-		($Pnum==6)? "\{<p3>3|<p4>4|     \} | \{<p2>2|$instance|<p5>5\} | \{ |<p1>1|<p0>0\}":
-		($Pnum==7)? "\{<p4>4|<p5>5|     \} | \{<p3>3|$instance|<p6>6\} | \{<p2>2 |<p1>1|<p0>0\}":
-		($Pnum==8)? "\{<p4>4|<p5>5|<p6>6\} | \{<p3>3|$instance|<p7>7\} | \{<p2>2 |<p1>1|<p0>0\}":
-		($Pnum==9)? "\{<p5>5|<p6>6|<p7>7\} | \{<p4>4|$instance|<p8>8\} | \{<p3>3 |<p2>2|<p1>1|<p0>0\}":
-		($Pnum==10)? "\{<p5>5|<p6>6|<p7>7|<p8>8\} | \{<p4>4|$instance|<p9>9\} | \{<p3>3 |<p2>2|<p1>1|<p0>0\}":
-		($Pnum==11)? "\{<p6>6|<p7>7|<p8>8|<p9>9\}| \{<p5>5| | |<p10>10\}  | \{<p4>4|$instance| \} | \{<p3>3 |<p2>2|<p1>1|<p0>0\}":
-		($Pnum==12)? "\{<p6>6|<p7>7|<p8>8|<p9>9\}| \{<p5>5| | |<p10>10\}  | \{<p4>4|$instance|<p11>11\} | \{<p3>3 |<p2>2|<p1>1|<p0>0\}":
-		  "\{ |<p2>2| \} | \{<p3>3|$instance|<p1>1\} | \{ |<p4>4|<p0>0\}";	
-	
-	
-	return 
-	"$R\[
-	label = \"$label\"
+    my ($Pnum,$R,$instance)=@_;
+    $Pnum=1 if(!defined $Pnum);
+    my $label =
+        ($Pnum==2)? "                        \{<p1>1|$instance|<p0>0\}":
+        ($Pnum==3)? "\{     |<p2>2|     \} | \{<p1>1|$instance|<p0>0\} ":
+        ($Pnum==4)? "\{     |<p3>3|     \} | \{<p2>2|$instance|<p0>0\} | \{  <p1>1\}":
+        ($Pnum==5)? "\{     |<p3>3|     \} | \{<p2>2|$instance|<p4>4\} | \{ |<p1>1|<p0>0\}":
+        ($Pnum==6)? "\{<p3>3|<p4>4|     \} | \{<p2>2|$instance|<p5>5\} | \{ |<p1>1|<p0>0\}":
+        ($Pnum==7)? "\{<p4>4|<p5>5|     \} | \{<p3>3|$instance|<p6>6\} | \{<p2>2 |<p1>1|<p0>0\}":
+        ($Pnum==8)? "\{<p4>4|<p5>5|<p6>6\} | \{<p3>3|$instance|<p7>7\} | \{<p2>2 |<p1>1|<p0>0\}":
+        ($Pnum==9)? "\{<p5>5|<p6>6|<p7>7\} | \{<p4>4|$instance|<p8>8\} | \{<p3>3 |<p2>2|<p1>1|<p0>0\}":
+        ($Pnum==10)? "\{<p5>5|<p6>6|<p7>7|<p8>8\} | \{<p4>4|$instance|<p9>9\} | \{<p3>3 |<p2>2|<p1>1|<p0>0\}":
+        ($Pnum==11)? "\{<p6>6|<p7>7|<p8>8|<p9>9\}| \{<p5>5| | |<p10>10\}  | \{<p4>4|$instance| \} | \{<p3>3 |<p2>2|<p1>1|<p0>0\}":
+        ($Pnum==12)? "\{<p6>6|<p7>7|<p8>8|<p9>9\}| \{<p5>5| | |<p10>10\}  | \{<p4>4|$instance|<p11>11\} | \{<p3>3 |<p2>2|<p1>1|<p0>0\}":
+        "\{ |<p2>2| \} | \{<p3>3|$instance|<p1>1\} | \{ |<p4>4|<p0>0\}";
+    return
+    "$R\[
+    label = \"$label\"
     shape=record
-	color=blue
-	style=filled
-	fillcolor=blue
+    color=blue
+    style=filled
+    fillcolor=blue
 ];
 ";
-
 }
 
 sub router_node_dot_sim{
-	my ($Pnum,$R,$instance)=@_;	
-	$Pnum=1 if(!defined $Pnum);
-	my $label =	 "$instance";
-		
-	
-	return 
-	"$R\[
-	label = \"$label\"
+    my ($Pnum,$R,$instance)=@_;
+    $Pnum=1 if(!defined $Pnum);
+    my $label =     "$instance";
+    return
+    "$R\[
+    label = \"$label\"
     shape=circle
-	color=blue
-	style=filled
-	fillcolor=blue
+    color=blue
+    style=filled
+    fillcolor=blue
 ];
 ";
-
 }
 
-
 sub endp_node_dot_sim {
-	my ($T,$instance)=@_;
-	
-	
-	return 
-	"
-	$T\[
-	label = \"$instance\"
+    my ($T,$instance)=@_;
+    return
+    "
+    $T\[
+    label = \"$instance\"
     shape=circle
     margin=0
-	color=orange
-	style=filled
-	fillcolor=orange
+    color=orange
+    style=filled
+    fillcolor=orange
 ];
-";	
+";
 }
 
-
-
-
-
-
-
-
-
-
-
-
 sub generate_custom_topology_dot_file{
-	my $self=shift;
-	
-	my $gtype=$self->object_get_attribute("tile_diagram","gtype");
-	$gtype = "simple" if (!defined $gtype);
-		
-	my $dotfile=
+    my $self=shift;
+    my $gtype=$self->object_get_attribute("tile_diagram","gtype");
+    $gtype = "simple" if (!defined $gtype);
+    my $dotfile=
 "digraph G {
-	graph [layout = twopi, rankdir = RL , splines = true, overlap = false]; 	
-	node[shape=record];	
-	";	
-	#Add endpoints
-	my @nodes=get_list_of_all_endpoints($self);
-	my $i=0;
-	foreach my $p (@nodes){
-		my $instance= $self->object_get_attribute("$p","NAME");
-		$instance = "T$i" if(!defined $instance);
-		$dotfile.= ($gtype eq 'simple')? endp_node_dot_sim($p,$instance) : endp_node_dot_comp($p,$instance);		
-		$i++;
-	}
-	
-	
-	
-	#add routers
-	@nodes=get_list_of_all_routers($self);
-	$i=0;
-	foreach my $p (@nodes){
-		my $instance= $self->object_get_attribute("$p","NAME");
-		$instance = "R$i" if(!defined $instance);
-		my $pnum=$self->object_get_attribute("$p",'PNUM');
-		$dotfile.=($gtype eq 'simple')? router_node_dot_sim($pnum,$p,$instance): router_node_dot_comp($pnum,$p,$instance);	
-		$i++;
-	}
-		
-	
-	#add connections
-	my @all_nodes=get_list_of_all_nodes($self);
-	my @draw;
-	foreach my $p (@all_nodes){
-   	   	my $pnum=$self->object_get_attribute("$p",'PNUM');
-   	   #	my $inst=$self->object_get_attribute("$p",'NAME');
-   	   	my $type = $self->object_get_attribute("$p",'TYPE');   	   
-   	   	$pnum = 0 if(!defined $pnum);
-   	   	for (my $i=0;$i<$pnum; $i++){ 
-   	   		my $src_port = "Port[${i}]";
-   	   		my $connect = $self->{$p}{'PCONNECT'}{$src_port};
-			
-			if (defined $connect) { 
-				my $pos = get_scolar_pos($connect,@draw);
-				if ( !defined $pos ){
-				
-				
-				my ($node,$pnode)=split(/\s*,\s*/,$connect);
-				# check if $node exist
-				if ( defined get_scolar_pos($node, @all_nodes)){
-				 
-	   	   		    my ($cp)= sscanf("Port[%u]","$pnode");
-	   	   		    # my $cinst=$self->object_get_attribute("$node",'NAME');
-	   	   		    my $ctype = $self->object_get_attribute("$node",'TYPE');
-	   	   		  
-	   	   		  
-	   	   		  
-	   	   		  	my ($t2, $t1);
-	   	   		  	
-	   	   		  	if ($gtype eq 'simple'){
-	   	   		  		$t2 =  "\"$p\""; 
-	   	   		  		$t1 =  "\"$node\"";
-	   	   		  	} else {
-	   	   		  		$t2 = ($type eq "ENDP" )? "\"$p\"" : "\"$p\" : \"p$i\"";
-	   	   		  	    $t1 = ($ctype eq "ENDP" )? "\"$node\"" : "\"$node\" : \"p$cp\"";
-	   	   		  		
-	   	   		  	}
-	   	   			my $t= "$t1 -> $t2 [ dir=none];\n"; 
-	   	   			$dotfile=$dotfile."$t";
-				}
-   	   			push(@draw,$connect);
-   	   			push(@draw,"$p,$src_port");
-   	   			#print "@draw\n";
-   	   		}
-   	   		
-	
-   	   	}}
-	}
-	$dotfile=$dotfile."\n}\n";
-	#print  $dotfile;
-	return $dotfile;
+    graph [layout = twopi, rankdir = RL , splines = true, overlap = false];
+    node[shape=record];
+    ";
+    # Add endpoints
+    my @nodes=get_list_of_all_endpoints($self);
+    my $i=0;
+    foreach my $p (@nodes){
+        my $instance= $self->object_get_attribute("$p","NAME");
+        $instance = "T$i" if(!defined $instance);
+        $dotfile.= ($gtype eq 'simple')? endp_node_dot_sim($p,$instance) : endp_node_dot_comp($p,$instance);
+        $i++;
+    }
+    # add routers
+    @nodes=get_list_of_all_routers($self);
+    $i=0;
+    foreach my $p (@nodes){
+        my $instance= $self->object_get_attribute("$p","NAME");
+        $instance = "R$i" if(!defined $instance);
+        my $pnum=$self->object_get_attribute("$p",'PNUM');
+        $dotfile.=($gtype eq 'simple')? router_node_dot_sim($pnum,$p,$instance): router_node_dot_comp($pnum,$p,$instance);
+        $i++;
+    }
+    # add connections
+    my @all_nodes=get_list_of_all_nodes($self);
+    my @draw;
+    foreach my $p (@all_nodes){
+        my $pnum=$self->object_get_attribute("$p",'PNUM');
+        #    my $inst=$self->object_get_attribute("$p",'NAME');
+        my $type = $self->object_get_attribute("$p",'TYPE');
+        $pnum = 0 if(!defined $pnum);
+        for (my $i=0;$i<$pnum; $i++){
+            my $src_port = "Port[${i}]";
+            my $connect = $self->{$p}{'PCONNECT'}{$src_port};
+            if (defined $connect) {
+                my $pos = get_scolar_pos($connect,@draw);
+                if ( !defined $pos ){
+                    my ($node,$pnode)=split(/\s*,\s*/,$connect);
+                    # check if $node exist
+                    if ( defined get_scolar_pos($node, @all_nodes)){
+                        my ($cp)= sscanf("Port[%u]","$pnode");
+                        # my $cinst=$self->object_get_attribute("$node",'NAME');
+                        my $ctype = $self->object_get_attribute("$node",'TYPE');
+                        my ($t2, $t1);
+                        if ($gtype eq 'simple'){
+                            $t2 =  "\"$p\"";
+                            $t1 =  "\"$node\"";
+                        } else {
+                            $t2 = ($type eq "ENDP" )? "\"$p\"" : "\"$p\" : \"p$i\"";
+                            $t1 = ($ctype eq "ENDP" )? "\"$node\"" : "\"$node\" : \"p$cp\"";
+                        }
+                        my $t= "$t1 -> $t2 [ dir=none];\n";
+                        $dotfile=$dotfile."$t";
+                    }
+                    push(@draw,$connect);
+                    push(@draw,"$p,$src_port");
+                    #print "@draw\n";
+                }
+            }
+        }
+    }
+    $dotfile=$dotfile."\n}\n";
+    #print  $dotfile;
+    return $dotfile;
 }
 
 sub get_connection_port_num_between_two_nodes{
-	my ($self,$n1,$n2)=@_;
-	my $PNUM=$self->object_get_attribute($n1,"PNUM");
-	
-	for (my $p1=0; $p1<$PNUM; $p1++){
-		my $connect=$self->{$n1}{"PCONNECT"}{"Port[$p1]"};
-		next if(!defined $connect);
-		my ($node,$pnode)=split(/\s*,\s*/,$connect);
-		my ($p2)= sscanf("Port[%u]","$pnode");
-		return ($p1,$p2) if($node eq $n2 );		
-	}
-	return undef;
+    my ($self,$n1,$n2)=@_;
+    my $PNUM=$self->object_get_attribute($n1,"PNUM");
+    for (my $p1=0; $p1<$PNUM; $p1++){
+        my $connect=$self->{$n1}{"PCONNECT"}{"Port[$p1]"};
+        next if(!defined $connect);
+        my ($node,$pnode)=split(/\s*,\s*/,$connect);
+        my ($p2)= sscanf("Port[%u]","$pnode");
+        return ($p1,$p2) if($node eq $n2 );
+    }
+    return undef;
 }
 
-
 sub show_custom_topology_diagram {
-	my ($self,$scrolled_win, $name)=@_;
-	
-	my $state=$self->object_get_attribute("tile_diagram","auto_draw");
-	if( $state eq "ON") {
-		my $dotfile = generate_custom_topology_dot_file($self);
-		generate_and_show_graph_using_graphviz($self,$scrolled_win,$dotfile,$name);
-	}
-	else {
-		my @list = $scrolled_win->get_children();
-		foreach my $l (@list){ 
-			$scrolled_win->remove($l);			
-		}
-	}
-	
-	return;
+    my ($self,$scrolled_win, $name)=@_;
+    my $state=$self->object_get_attribute("tile_diagram","auto_draw");
+    if( $state eq "ON") {
+        my $dotfile = generate_custom_topology_dot_file($self);
+        generate_and_show_graph_using_graphviz($self,$scrolled_win,$dotfile,$name);
+    }
+    else {
+        my @list = $scrolled_win->get_children();
+        foreach my $l (@list){
+            $scrolled_win->remove($l);
+        }
+    }
+    return;
 }
 
-
-
-
-
 sub take_node_num_page{
-	my ($self)=@_;		
-	my $table= def_table(2,10,FALSE);
-	my $row=0;
-	my $col=4;
-	$table->attach (def_label('Network Element'),$col,$col+1,$row,$row+1,'fill','shrink',2,2);$col+=2;
-	$table->attach (def_label('Number'),$col,$col+1,$row,$row+1,'fill','shrink',2,2);
-	$row++;$col=0;
-	
-	$table->attach (def_icon('icons/e.png'),$col,$col+1,$row,$row+1,'fill','shrink',2,2);$col++;
-	($row,$col)=add_param_widget ($self,"# Endpoints","NUM", 0,'Spin-button','0,1024,1',undef, $table,$row,$col,1,'ENDP',10,'redraw');$col=0;
-	for ( my $i=2;$i<=12; $i++){
-		$table->attach (def_icon('icons/r.png'),$col,$col+1,$row,$row+1,'fill','shrink',2,2);$col++;
-		($row,$col)=add_param_widget ($self,"# $i-Port Routers","NUM", 0,'Spin-button','0,1024,1',undef, $table,$row,$col,1,"ROUTER${i}",10,'redraw');$col=0;		
-	}	
-	return $table;
+    my ($self)=@_;
+    my $table= def_table(2,10,FALSE);
+    my $row=0;
+    my $col=4;
+    # $table->attach (def_label('Network Element'),$col,$col+1,$row,$row+1,'fill','shrink',2,2);$col+=2;
+    # $table->attach (def_label('Number'),$col,$col+1,$row,$row+1,'fill','shrink',2,2);
+    $row++;$col=0;
+    $table->attach (def_icon('icons/e.png'),$col,$col+1,$row,$row+1,'fill','shrink',2,2);$col++;
+    ($row,$col)=add_param_widget ($self,"# Endpoints","NUM", 0,'Spin-button','0,1024,1',undef, $table,$row,$col,1,'ENDP',10,'redraw');$col=0;
+    for ( my $i=2;$i<=12; $i++){
+        $table->attach (def_icon('icons/r.png'),$col,$col+1,$row,$row+1,'fill','shrink',2,2);$col++;
+        ($row,$col)=add_param_widget ($self,"# $i-Port Routers","NUM", 0,'Spin-button','0,1024,1',undef, $table,$row,$col,1,"ROUTER${i}",10,'redraw');$col=0;
+    }
+    return $table;
 }
 
-
-
 sub take_instance_page{
-	my ($self)=@_;		
-	my $table= def_table(2,10,FALSE);
-	
-	initial_node_info($self);
-	
-	my $row=0;
-	my $col=0;
-	
-	
-	$table->attach (def_label(' Network Element '),$col,$col+1,$row,$row+1,'fill','shrink',2,2);$col+=2;
-	$table->attach (def_label(' Instance name '),$col,$col+1,$row,$row+1,'fill','shrink',2,2);
-	$row++;$col=0;
-	
-	
-	my $EN= $self->object_get_attribute('ENDP','NUM');
-	$EN = 0 if(!defined $EN);
-	for (my $i=0;$i<$EN; $i++){	
-		
-		 my $d=get_default_instance_name($self,"ENDP_$i");	                            
-		($row,$col)=add_param_widget ($self,"Endpoint $i","NAME",$d ,'Entry',undef,"router instance name", $table,$row,$col,1,"ENDP_$i",10,'redraw');$col=0;
-		
-	}	
-	
-	#routers
-	my $Rnum=0;
-	for ( my $i=2;$i<=12; $i++){
-		my $n= $self->object_get_attribute("ROUTER${i}","NUM");
-		$n=0 if(!defined $n);
-		 for ( my $j=0;$j<$n; $j++){
-		 	my $d=get_default_instance_name($self,"ROUTER${i}_$j");
-		 	($row,$col)=add_param_widget ($self,"Router $Rnum","NAME", "$d",'Entry',undef,"router instance name", $table,$row,$col,1,"ROUTER${i}_$j",10,'redraw');$col=0;
-					 
-			 $Rnum++;
-		 }
-	}	
-	return $table;
-	
+    my ($self)=@_;
+    my $table= def_table(2,10,FALSE);
+    initial_node_info($self);
+    my $row=0;
+    my $col=0;
+    $table->attach (def_label(' Network Element '),$col,$col+1,$row,$row+1,'fill','shrink',2,2);$col+=2;
+    $table->attach (def_label(' Instance name '),$col,$col+1,$row,$row+1,'fill','shrink',2,2);
+    $row++;$col=0;
+    my $EN= $self->object_get_attribute('ENDP','NUM');
+    $EN = 0 if(!defined $EN);
+    for (my $i=0;$i<$EN; $i++){
+        my $d=get_default_instance_name($self,"ENDP_$i");
+        ($row,$col)=add_param_widget ($self,"Endpoint $i","NAME",$d ,'Entry',undef,"router instance name", $table,$row,$col,1,"ENDP_$i",10,'redraw');$col=0;
+    }
+    #routers
+    my $Rnum=0;
+    for ( my $i=2;$i<=12; $i++){
+        my $n= $self->object_get_attribute("ROUTER${i}","NUM");
+        $n=0 if(!defined $n);
+        for ( my $j=0;$j<$n; $j++){
+            my $d=get_default_instance_name($self,"ROUTER${i}_$j");
+            ($row,$col)=add_param_widget ($self,"${i}-PortRouter${j}","NAME", "$d",'Entry',undef,"router instance name", $table,$row,$col,1,"ROUTER${i}_$j",10,'redraw');$col=0;
+            $Rnum++;
+        }
+    }
+    return $table;
 }
 
 sub initial_node_info {
-	my ($self)=@_;		
-	
-	my $EN= $self->object_get_attribute('ENDP','NUM');
-	$EN = 0 if(!defined $EN);
-	for (my $i=0;$i<$EN; $i++){	
-		 $self->object_add_attribute("ENDP_$i",'PNUM',1);
-		 $self->object_add_attribute("ENDP_$i",'TYPE',"ENDP");
-		 my $inst=$self->object_get_attribute("ENDP_$i",'NAME');
-		 if(!defined $inst){
-		 	$inst=get_default_instance_name ($self,"ENDP_$i");
-		 	$self->object_add_attribute("ENDP_$i",'NAME',$inst);
-		 }
-	}	
-	
-	#routers
-	my $Rnum=0;
-	for ( my $i=2;$i<=12; $i++){
-		my $n= $self->object_get_attribute("ROUTER${i}","NUM");
-		$n=0 if(!defined $n);
-		 for ( my $j=0;$j<$n; $j++){
-		 	 $self->object_add_attribute("ROUTER${i}_$j",'PNUM',${i});
-			 $self->object_add_attribute("ROUTER${i}_$j",'RNUM',$Rnum);
-			 $self->object_add_attribute("ROUTER${i}_$j",'TYPE',"ROUTER");
-			 my $inst=$self->object_get_attribute("ROUTER${i}_$j",'NAME');
-			 if(!defined $inst){
-			 	$inst=get_default_instance_name ($self,"ROUTER${i}_$j");
-			 	$self->object_add_attribute("ROUTER${i}_$j",'NAME',$inst);
-			 }
-		 	 $Rnum++;
-		 }
-	}	
-	
+    my ($self)=@_;
+    my $EN= $self->object_get_attribute('ENDP','NUM');
+    $EN = 0 if(!defined $EN);
+    for (my $i=0;$i<$EN; $i++){
+        $self->object_add_attribute("ENDP_$i",'PNUM',1);
+        $self->object_add_attribute("ENDP_$i",'TYPE',"ENDP");
+        my $inst=$self->object_get_attribute("ENDP_$i",'NAME');
+        if(!defined $inst){
+            $inst=get_default_instance_name ($self,"ENDP_$i");
+            $self->object_add_attribute("ENDP_$i",'NAME',$inst);
+        }
+    }
+    #routers
+    my $Rnum=0;
+    for ( my $i=2;$i<=12; $i++){
+        my $n= $self->object_get_attribute("ROUTER${i}","NUM");
+        $n=0 if(!defined $n);
+        for ( my $j=0;$j<$n; $j++){
+            $self->object_add_attribute("ROUTER${i}_$j",'PNUM',${i});
+            $self->object_add_attribute("ROUTER${i}_$j",'RNUM',$Rnum);
+            $self->object_add_attribute("ROUTER${i}_$j",'TYPE',"ROUTER");
+            my $inst=$self->object_get_attribute("ROUTER${i}_$j",'NAME');
+            if(!defined $inst){
+                $inst=get_default_instance_name ($self,"ROUTER${i}_$j");
+                $self->object_add_attribute("ROUTER${i}_$j",'NAME',$inst);
+            }
+            $Rnum++;
+        }
+    }
 }
 
-
-
-
 sub get_default_instance_name {
-	my ($self,$name)=@_;
-	my $type = $self->object_get_attribute($name,'TYPE');
-	my @nodes =($type eq 'ENDP')? get_list_of_all_endpoints($self):get_list_of_all_routers($self);
-		
-	my @R=("--");
-	foreach my $p (@nodes){
-		my $n= $self->object_get_attribute("$p","NAME");
-		push( @R, $n) if(defined $n);			
-	}	
-	
-	my $i=0;
-	my $inst = 	($type eq 'ENDP')? "T$i": "R$i";
-	my $pos= get_scolar_pos($inst,@R);
-	while (defined $pos){
-		$i++;	
-		$inst = 	($type eq 'ENDP')? "T$i": "R$i";
-		$pos= get_scolar_pos($inst,@R);				
-	}
-		
-	
-	return 	$inst;	
-}	
-	
-	
-
+    my ($self,$name)=@_;
+    my $type = $self->object_get_attribute($name,'TYPE');
+    my @nodes =($type eq 'ENDP')? get_list_of_all_endpoints($self):get_list_of_all_routers($self);
+    my @R=("--");
+    foreach my $p (@nodes){
+        my $n= $self->object_get_attribute("$p","NAME");
+        push( @R, $n) if(defined $n);
+    }
+    my $i=0;
+    my $inst = ($type eq 'ENDP')? "T$i": "R$i";
+    my $pos= get_scolar_pos($inst,@R);
+    while (defined $pos){
+        $i++;
+        $inst = ($type eq 'ENDP')? "T$i": "R$i";
+        $pos= get_scolar_pos($inst,@R);
+    }
+    return     $inst;
+}
 
 sub get_list_of_all_routers {
-	my ($self)=@_;	
-	my @R;
-	for ( my $i=2;$i<=12; $i++){
-		 my $n= $self->object_get_attribute("ROUTER${i}","NUM");
-		 $n=0 if(!defined $n);
-		 for ( my $j=0;$j<$n; $j++){
-		 	push( @R, "ROUTER${i}_$j");		 	
-		 }
-	}	
-	return @R;
+    my ($self)=@_;
+    my @R;
+    for ( my $i=2;$i<=12; $i++){
+        my $n= $self->object_get_attribute("ROUTER${i}","NUM");
+        $n=0 if(!defined $n);
+        for ( my $j=0;$j<$n; $j++){
+            push( @R, "ROUTER${i}_$j");
+        }
+    }
+    return @R;
 }
 
 sub get_list_of_all_endpoints {
-	my ($self)=@_;	
-	my @E;
-	my $EN= $self->object_get_attribute('ENDP','NUM');
-	$EN = 0 if(!defined $EN);
-	for (my $i=0;$i<$EN; $i++){	
-		push( @E, "ENDP_$i");		
-	}
-	return @E;
+    my ($self)=@_;
+    my @E;
+    my $EN= $self->object_get_attribute('ENDP','NUM');
+    $EN = 0 if(!defined $EN);
+    for (my $i=0;$i<$EN; $i++){
+        push( @E, "ENDP_$i");
+    }
+    return @E;
 }
 
 sub get_list_of_all_nodes {
-	my ($self)=@_;	
-	my @R=get_list_of_all_routers($self);
+    my ($self)=@_;
+    my @R=get_list_of_all_routers($self);
     my @E=get_list_of_all_endpoints($self);
     my @all_nodes= (@E,@R);
-	return @all_nodes;
-}	
+    return @all_nodes;
+}
 
 sub remove_connected_port{
-	my ($self,$node,$port,$info)=@_;
-	my @all_nodes=get_list_of_all_nodes($self);
-	foreach my $p (@all_nodes){
-   	   	my $pnum=$self->object_get_attribute("$p",'PNUM');
-   	   	my $inst=$self->object_get_attribute("$p",'NAME');
-   	   
-   	   	$pnum = 0 if(!defined $pnum);
-   	   	for (my $i=0;$i<$pnum; $i++){ 
-   	   		my $src_port = "Port[${i}]";
-   	   		if(defined $self->{$p}{'PCONNECT'}{$src_port}){ if ($self->{$p}{'PCONNECT'}{$src_port} eq "$node,$port"){
-   	   			delete $self->{$p}{'PCONNECT'}{$src_port};
-   	   			my $con_inst=$self->object_get_attribute("$node",'NAME');
-   	   			add_info($info,"** $inst  $src_port is disconnected from $con_inst $port \n") if (defined $info);
-   	   		
-   	   		}}
-   	   	} 
-	}	   	 	
-}	
-
+    my ($self,$node,$port,$info)=@_;
+    my @all_nodes=get_list_of_all_nodes($self);
+    foreach my $p (@all_nodes){
+        my $pnum=$self->object_get_attribute("$p",'PNUM');
+        my $inst=$self->object_get_attribute("$p",'NAME');
+        $pnum = 0 if(!defined $pnum);
+        for (my $i=0;$i<$pnum; $i++){
+            my $src_port = "Port[${i}]";
+            if(defined $self->{$p}{'PCONNECT'}{$src_port}){ if ($self->{$p}{'PCONNECT'}{$src_port} eq "$node,$port"){
+                delete $self->{$p}{'PCONNECT'}{$src_port};
+                my $con_inst=$self->object_get_attribute("$node",'NAME');
+                add_info($info,"** $inst  $src_port is disconnected from $con_inst $port \n") if (defined $info);
+            }}
+        }
+    }
+}
 
 sub get_instance_to_node_name {
-	my $self=shift;
-	my @all_nodes=get_list_of_all_nodes($self);
+    my $self=shift;
+    my @all_nodes=get_list_of_all_nodes($self);
     my %par;
     foreach my $p (@all_nodes){
-   	   	my $inst=$self->object_get_attribute("$p",'NAME');
-   	   	$par{$inst}= $p;
+        my $inst=$self->object_get_attribute("$p",'NAME');
+        $par{$inst}= $p;
     }
-    return %par;	
+    return %par;
 }
-
-
 ##############
-#	create_tree 
+#    create_tree
 ##############
 sub create_tree_view {
-   my ($self,$source,$src_port,$info)=@_;  
-   my $window = def_popwin_size(30,85,"Select Connection Element and Port",'percent');
-     
-
-   my ($model,$tree_view,$column) =create_tree_model_network_maker();
-      
-   my @all_nodes=get_list_of_all_nodes($self);
- 
-   unshift(@all_nodes,"-");
-   my %par;
- 
-   foreach my $p (@all_nodes){
-   	    my @childs;
-   	   	my $pnum=$self->object_get_attribute("$p",'PNUM');
-   	   	my $inst=$self->object_get_attribute("$p",'NAME');
-   	   	
-   	   	$pnum = 0 if(!defined $pnum);
-   	   	$inst = "-" if(!defined $inst);
-   	   	
-   	   	$par{$inst}= $p;
-   	   	for (my $i=0;$i<$pnum; $i++){ 
-   	   		#donot add the source port itself to connection list
-   	   		if(($source ne $p)|| ($src_port ne "Port[${i}]")){
-   				push(@childs, "Port[${i}]");
-   	   		}
-   	   	}  	
-		my $iter = $model->append (undef);
-	    $model->set ($iter, 0, $inst, 1, $inst || '', 2, 0 || '', 3,   FALSE);
-		foreach my $v ( @childs){
-			 my $child_iter = $model->append ($iter);
-			 $model->set ($child_iter, 0, $v, 1, $inst|| '', 2, $v || '', 3,   FALSE);
-		}	
-   }
-	
-  
-   $tree_view->append_column ($column);
-   
-   
-   
-   $tree_view->signal_connect (row_activated => sub{
-
-		my ($tree_view, $path, $column) = @_;
-		my $model = $tree_view->get_model;
-		my $iter = $model->get_iter ($path);
-		my $parent = $model->get ($iter, 1);
-		my $child = $model->get ($iter, 2);
-		
-		if ($child){ 
-			   	my $node=$par{$parent};
-			   	connect_nodes ($self,$node,$child,$source,$src_port,$info);
-		  		
-		  		
-		  		
-		  
-		  		set_gui_status($self,'ref',1);		
-		  		$window->destroy;
-		  		
-				#add parent child
-			}
-		elsif($parent ){
-			
-			my $node=$par{$parent};
-			if ($node eq "-"){
-				remove_connected_port($self,$source,$src_port);
-				delete $self->{$source}{'PCONNECT'}{$src_port};
-			}
-			
-			
-			
-			set_gui_status($self,'ref',1);		
-		  	$window->destroy;
-		  		
-			
-		}
-	
-  
-	#add parent child
-
-	});
-
-  #$tree_view->expand_all;
-
-  my $scrolled_window = add_widget_to_scrolled_win($tree_view);
-
-  my $hbox = def_hbox (FALSE, 0);
-  $hbox->pack_start ( $scrolled_window, TRUE, TRUE, 0);
-  $window ->add($hbox);
-  $window->show_all;
+    my ($self,$source,$src_port,$info)=@_;
+    my $window = def_popwin_size(30,85,"Select Connection Element and Port",'percent');
+    my ($model,$tree_view,$column) =create_tree_model_network_maker();
+    my @all_nodes=get_list_of_all_nodes($self);
+    unshift(@all_nodes,"-");
+    my %par;
+    foreach my $p (@all_nodes){
+        my @childs;
+        my $pnum=$self->object_get_attribute("$p",'PNUM');
+        my $inst=$self->object_get_attribute("$p",'NAME');
+        $pnum = 0 if(!defined $pnum);
+        $inst = "-" if(!defined $inst);
+        $par{$inst}= $p;
+        for (my $i=0;$i<$pnum; $i++){
+        #donot add the source port itself to connection list
+            if(($source ne $p)|| ($src_port ne "Port[${i}]")){
+                push(@childs, "Port[${i}]");
+            }
+        }
+        my $iter = $model->append (undef);
+        $model->set ($iter, 0, $inst, 1, $inst || '', 2, 0 || '', 3,   FALSE);
+        foreach my $v ( @childs){
+            my $child_iter = $model->append ($iter);
+            $model->set ($child_iter, 0, $v, 1, $inst|| '', 2, $v || '', 3,   FALSE);
+        }
+    }
+    $tree_view->append_column ($column);
+    $tree_view->signal_connect (row_activated => sub{
+        my ($tree_view, $path, $column) = @_;
+        my $model = $tree_view->get_model;
+        my $iter = $model->get_iter ($path);
+        my $parent = $model->get ($iter, 1);
+        my $child = $model->get ($iter, 2);
+        if ($child){
+            my $node=$par{$parent};
+            connect_nodes ($self,$node,$child,$source,$src_port,$info);
+            set_gui_status($self,'ref',1);
+            $window->destroy;
+            #add parent child
+        }
+        elsif($parent ){
+            my $node=$par{$parent};
+            if ($node eq "-"){
+                remove_connected_port($self,$source,$src_port);
+                delete $self->{$source}{'PCONNECT'}{$src_port};
+            }
+            set_gui_status($self,'ref',1);
+            $window->destroy;
+        }
+        #add parent child
+    });
+    #$tree_view->expand_all;
+    my $scrolled_window = add_widget_to_scrolled_win($tree_view);
+    my $hbox = def_hbox (FALSE, 0);
+    $hbox->pack_start ( $scrolled_window, TRUE, TRUE, 0);
+    $window ->add($hbox);
+    $window->show_all;
 }
 
 sub connect_nodes {
-	my ($self,$node1,$src_port1,$node2,$src_port2,$info)=@_;
-	
-		
-		
-	#add_colored_info($info,"$node1,$src_port1,$node2,$src_port2;\n","red") if (defined $info);	
-	
-	#check if the selected port has been connected to another port before and remove the connection
-	remove_connected_port($self,$node1,$src_port1,$info);
-	remove_connected_port($self,$node2,$src_port2,$info);
-		  		
-	$self->{$node1}{'PCONNECT'}{$src_port1}="$node2,$src_port2";
-	$self->{$node2}{'PCONNECT'}{$src_port2}="$node1,$src_port1";
-	
+    my ($self,$node1,$src_port1,$node2,$src_port2,$info)=@_;
+    #add_colored_info($info,"$node1,$src_port1,$node2,$src_port2;\n","red") if (defined $info);
+    #check if the selected port has been connected to another port before and remove the connection
+    remove_connected_port($self,$node1,$src_port1,$info);
+    remove_connected_port($self,$node2,$src_port2,$info);
+    $self->{$node1}{'PCONNECT'}{$src_port1}="$node2,$src_port2";
+    $self->{$node2}{'PCONNECT'}{$src_port2}="$node1,$src_port1";
 }
 
 sub remove_all_connection {
-	my ($self)=@_;
-	my @all_nodes=get_list_of_all_nodes($self);
-	foreach  my $node  (@all_nodes ){
-		$self->{$node}{'PCONNECT'}=undef;	
-	}	
-	set_gui_status($self,"ref",1);
+    my ($self)=@_;
+    my @all_nodes=get_list_of_all_nodes($self);
+    foreach  my $node  (@all_nodes ){
+        $self->{$node}{'PCONNECT'}=undef;
+    }
+    set_gui_status($self,"ref",1);
 }
 
 sub list_node_all_port{
-	my ($self,$node)=@_;
-	my @l;
-	my $pnum =  $self->object_get_attribute($node,'PNUM');
-	for (my $i=0;$i<$pnum; $i++){
-		push(@l,"Port[${i}]");
-	}
-	return @l;
+    my ($self,$node)=@_;
+    my @l;
+    my $pnum =  $self->object_get_attribute($node,'PNUM');
+    for (my $i=0;$i<$pnum; $i++){
+        push(@l,"Port[${i}]");
+    }
+    return @l;
 }
 
-
-
 sub list_node_connected_port {
-	my ($self,$node)=@_;
-	my $r = $self->{$node}{'PCONNECT'};
-	my %c =(defined $r)? %{$r} : undef;
-	return sort keys %c;
+    my ($self,$node)=@_;
+    my $r = $self->{$node}{'PCONNECT'};
+    my %c =(defined $r)? %{$r} : undef;
+    return sort keys %c;
 }
 
 sub list_node_unconnected_port {
-	my ($self,$node)=@_;
-	my @p = list_node_all_port($self,$node);
-	my @cp = list_node_connected_port ($self,$node);
-	#@p - @cp;
+    my ($self,$node)=@_;
+    my @p = list_node_all_port($self,$node);
+    my @cp = list_node_connected_port ($self,$node);
+    #@p - @cp;
     my @np =get_diff_array(\@p,\@cp);
-	return @np;
+    return @np;
 }
 
-
 sub connection_page{
-	my ($self,$info)=@_;		
-	my $table= def_table(2,10,FALSE);
-	my $row=0;
-	my $col=0;
-	
-	initial_node_info($self);
-	
-	
-	
-	my $eq = def_table(1,8,TRUE);
-	
-	my $label = gen_label_help("Eg: R[i]P[0]->T[i]P[0];i[0,10,1]","Equation:");
-	my $entry = gen_entry();
-	my $open= def_image_button("icons/enter.png",undef,TRUE);
-	$eq->attach ($label,0,2,  $row, $row+1,'fill','fill',2,2);
-	$eq->attach_defaults ($entry,2, 9,  $row, $row+1);
-	$eq->attach ($open,9, 10,  $row, $row+1,'fill','shrink',2,2);
-	$table->attach ($eq,0, 20,  $row, $row+1,'expand','fill',2,2);$row++;	
-	
-	$open->signal_connect("clicked" => sub {
-				evaluate_eqation($self,$entry->get_text(),$info);
-				
-	});
-	
-	$row++;
-	
-	
-	
-	add_Hsep_to_table($table,0, 20,  $row);$row++;	
-	my $savr=$row;$row++;	
-	
-	my $maxp=1;	
-	
-	my @all_nodes=get_list_of_all_nodes($self);
-		
-	foreach  my $p  (@all_nodes ){	
-		my $inst=$self->object_get_attribute("$p",'NAME');
-		my $pnum=$self->object_get_attribute("$p",'PNUM');
-   	   	$maxp=	$pnum if($pnum > $maxp );  	   		
-   	   
-   	   	
-   	   	
-		my $label =gen_label_in_left("$inst:");
-		attach_widget_to_table ($table,$row,undef,undef,$label,$col);  $col+=4;
-		
-		for (my $i=0;$i<$pnum; $i++){ 
-			my $pname= "Port[${i}]";
-			my $connect = $self->{$p}{'PCONNECT'}{$pname};
-			my $button =  def_button(" -> ");
-			if (defined $connect) { 
-				my ($node,$pnode)=split(/\s*,\s*/,$connect);
-		    	my $e=$self->object_get_attribute("$node",'NAME');
-				$button = def_button("$e->$pnode") if(defined $e);
-			}
-			$button->signal_connect("clicked" => sub {
-				create_tree_view($self,$p,$pname,$info);
-				
-			});
-			attach_widget_to_table ($table,$row,undef,undef,$button,$col);  $col+=4;
-		}   
-		$col=0;
-			                            
-		#($row,$col)=add_param_widget ($self,"$instance","CNNT", undef,"Combo-box",$list,"router instance name", $table,$row,$col,1,"ENDP_$i",1,'ref','horizontal');
-		# my $connect_r= $self->object_get_attribute("ENDP_$i","CNNT");
-		# if( defined $connect_r){
-		# 	print "cponnection is $R{$connect_r}\n";
-		# 	my $conr= $R{$connect_r};
-		# 	my $p=0;
-		# 	($row,$col)=add_param_widget ($self,"P$p","P_$p", undef,"Combo-box",$list,undef, $table,$row,$col,1,"ENDP_$i",1,'ref','horizontal');
-		 	
-		 	
-		 	
-		# }
-		 $row++;$col=0;
-		
-	}	
-	
-	#routers
+    my ($self,$info)=@_;
+    my $table= def_table(2,10,FALSE);
+    my $row=0;
+    my $col=0;
+    initial_node_info($self);
+    my $eq = def_table(1,8,TRUE);
+    my $label = gen_label_help("Eg: R[i]P[0]->T[i]P[0];i[0,10,1]","Equation:");
+    my $entry = gen_entry();
+    my $open= def_image_button("icons/enter.png",undef,TRUE);
+    $eq->attach ($label,0,2,  $row, $row+1,'fill','fill',2,2);
+    $eq->attach_defaults ($entry,2, 9,  $row, $row+1);
+    $eq->attach ($open,9, 10,  $row, $row+1,'fill','shrink',2,2);
+    $table->attach ($eq,0, 20,  $row, $row+1,'expand','fill',2,2);$row++;
+    $open->signal_connect("clicked" => sub {
+        evaluate_eqation($self,$entry->get_text(),$info);
+    });
+    $row++;
+    add_Hsep_to_table($table,0, 20,  $row);$row++;
+    my $savr=$row;$row++;
+    my $maxp=1;
+    my @all_nodes=get_list_of_all_nodes($self);
+    foreach  my $p  (@all_nodes ){
+        my $inst=$self->object_get_attribute("$p",'NAME');
+        my $pnum=$self->object_get_attribute("$p",'PNUM');
+        $maxp=    $pnum if($pnum > $maxp );
+        my $label =gen_label_in_left("$inst:");
+        attach_widget_to_table ($table,$row,undef,undef,$label,$col);  $col+=4;
+        for (my $i=0;$i<$pnum; $i++){
+            my $pname= "Port[${i}]";
+            my $connect = $self->{$p}{'PCONNECT'}{$pname};
+            my $button =  def_button(" -> ");
+            if (defined $connect) {
+                my ($node,$pnode)=split(/\s*,\s*/,$connect);
+                my $e=$self->object_get_attribute("$node",'NAME');
+                $button = def_button("$e->$pnode") if(defined $e);
+            }
+            $button->signal_connect("clicked" => sub {
+                create_tree_view($self,$p,$pname,$info);
+            });
+            attach_widget_to_table ($table,$row,undef,undef,$button,$col);  $col+=4;
+        }
+        $col=0;
+        #($row,$col)=add_param_widget ($self,"$instance","CNNT", undef,"Combo-box",$list,"router instance name", $table,$row,$col,1,"ENDP_$i",1,'ref','horizontal');
+        # my $connect_r= $self->object_get_attribute("ENDP_$i","CNNT");
+        # if( defined $connect_r){
+        #     print "cponnection is $R{$connect_r}\n";
+        #     my $conr= $R{$connect_r};
+        #     my $p=0;
+        #     ($row,$col)=add_param_widget ($self,"P$p","P_$p", undef,"Combo-box",$list,undef, $table,$row,$col,1,"ENDP_$i",1,'ref','horizontal');
+        # }
+        $row++;$col=0;
+    }
+    #routers
     for ( my $i=2;$i<=12; $i++){
-		 my $n= $self->object_get_attribute("ROUTER${i}","NUM");
-		 $n=0 if(!defined $n);
-		 for ( my $j=0;$j<$n; $j++){
-			my $pnum=	 $self->object_get_attribute("ROUTER${i}_$j",'PNUM');
-			 for ( my $p=0;$p<$pnum; $p++){
-			 	#	($row,$col)=add_param_widget ($self,"P$p","P_$p", undef,"Combo-box",$list,undef, $table,$row,$col,1,"ROUTER${i}_$j",1,'ref','horizontal');
-		 	
-			 }
-			  $row++;$col=0;
-			
-		 }
-	}	
-	
-	
-	
-	
-	#add lables
-	$row=$savr;$col=0;
-	$table->attach (def_label(' Network Element '),$col,$col+1,$row,$row+1,'fill','shrink',2,2);$col+=4;
-	for (my $i=0;$i<$maxp; $i++){ 
-		$table->attach (def_label(" P$i "),$col,$col+1,$row,$row+1,'fill','shrink',2,2);$col+=4;
-		
-	}
-	return $table;
-	
+        my $n= $self->object_get_attribute("ROUTER${i}","NUM");
+        $n=0 if(!defined $n);
+        for ( my $j=0;$j<$n; $j++){
+            my $pnum=     $self->object_get_attribute("ROUTER${i}_$j",'PNUM');
+            for ( my $p=0;$p<$pnum; $p++){
+                #    ($row,$col)=add_param_widget ($self,"P$p","P_$p", undef,"Combo-box",$list,undef, $table,$row,$col,1,"ROUTER${i}_$j",1,'ref','horizontal');
+            }
+            $row++;$col=0;
+        }
+    }
+    #add lables
+    $row=$savr;$col=0;
+    $table->attach (def_label(' Network Element '),$col,$col+1,$row,$row+1,'fill','shrink',2,2);$col+=4;
+    for (my $i=0;$i<$maxp; $i++){
+        $table->attach (def_label(" P$i "),$col,$col+1,$row,$row+1,'fill','shrink',2,2);$col+=4;
+    }
+    return $table;
 }
 
-
 sub evaluate_eqation{
-	my ($self,$exp,$info)=@_;
-
-	my @str=split /;/, $exp; 
-	my $eq_exp;
-	
-	my $f=0;
-	my %vname;
-	my %vars;
-	
-	my %nodes_name=get_instance_to_node_name($self);
-	
-	foreach my $p (@str) {
-		
-		if($f==0){
-			$eq_exp= $p;
-					
-		}	
-		else{
-			my ($v, $start, $end, $step) = sscanf("%s[%d,%d,%d]", $p);
-			print "($v, $start, $end, $step)\n";
-			my @a;
-			for (my $i=$start; $i<$end;$i++){
-				push (@a,$i);
-			} 
-			$vars{$f}=\@a;
-			$vname{$f}=$v;
-			
-		}
-		$f++;
-	
-	}
-	
-	
-	my %vars2;
-	my $v1=$vname{1};
-	foreach my $i (@{$vars{1}}){
-		$vars2{$v1}=$i;
-		my $v2=$vname{2};
-		if (defined $v2) {
-			foreach my $j (@{$vars{2}}){
-				$vars2{$v2}=$j;
-				my $v3=$vname{3};
-				if (defined $v3) {
-					foreach my $k (@{$vars{3}}){
-						$vars2{$v3}=$k;
-						eval_exp($self,$eq_exp,\%vars2,\%nodes_name,$info);	
-					}
-						
-				}
-				else {eval_exp($self,$eq_exp,\%vars2,\%nodes_name,$info)};	
-			
-			
-			}
-		}
-		else {eval_exp($self,$eq_exp,\%vars2,\%nodes_name,$info)};	
-		
-	}
-
-set_gui_status($self,'ref',1);	
+    my ($self,$exp,$info)=@_;
+    my @str=split /;/, $exp;
+    my $eq_exp;
+    my $f=0;
+    my %vname;
+    my %vars;
+    my %nodes_name=get_instance_to_node_name($self);
+    foreach my $p (@str) {
+        if($f==0){
+            $eq_exp= $p;
+        }
+        else{
+            my ($v, $start, $end, $step) = sscanf("%s[%d,%d,%d]", $p);
+            #print "($v, $start, $end, $step)\n";
+            my @a;
+            for (my $i=$start; $i<$end;$i++){
+                push (@a,$i);
+            }
+            $vars{$f}=\@a;
+            $vname{$f}=$v;
+        }
+        $f++;
+    }
+    my %vars2;
+    my $v1=$vname{1};
+    foreach my $i (@{$vars{1}}){
+        $vars2{$v1}=$i;
+        my $v2=$vname{2};
+        if (defined $v2) {
+            foreach my $j (@{$vars{2}}){
+                $vars2{$v2}=$j;
+                my $v3=$vname{3};
+                if (defined $v3) {
+                    foreach my $k (@{$vars{3}}){
+                        $vars2{$v3}=$k;
+                        eval_exp($self,$eq_exp,\%vars2,\%nodes_name,$info);
+                    }
+                }
+                else {eval_exp($self,$eq_exp,\%vars2,\%nodes_name,$info)};
+            }
+        }
+        else {eval_exp($self,$eq_exp,\%vars2,\%nodes_name,$info)};
+    }
+    set_gui_status($self,'ref',1);
 }
 
-
-
-
 sub eval_exp {
-	my ($self,$exp,$ref,$ref2,$info)=@_;
-	my  %vars = %{$ref};
-	my %nodes_name =%{$ref2};
+    my ($self,$exp,$ref,$ref2,$info)=@_;
+    my  %vars = %{$ref};
+    my %nodes_name =%{$ref2};
     foreach my $p (sort keys %vars){
-    	
-    	chomp $exp;    	
-		($exp=$exp)=~ s/\b$p\b/$vars{$p}/g; 
-    	   	
-    	
+        chomp $exp;
+        ($exp=$exp)=~ s/\b$p\b/$vars{$p}/g;
     }
-    
     my ($s1, $n1, $p1,$s2, $n2, $p2 ) = sscanf("%s[%s]P[%s]->%s[%s]P[%s]", $exp);
+    $n1 = eval $n1;
+    $p1 = eval $p1;
+    $n2 = eval $n2;
+    $p2 = eval $p2;
+    my $string= "$s1 [$n1] P [$p1] -> $s2 [$n2] P [$p2]\n";
+    my $node1=$nodes_name{$s1.$n1};
+    my $node2=$nodes_name{$s2.$n2};
+    if(!defined $node1 ){
+        add_colored_info($info,"No instance is named as \"$s1$n1\";\n","red") if (defined $info);
+        return;
+    }
+    if( !defined $node2 ){
+        add_colored_info($info,"No instance is named as \"$s2$n2\";\n","red") if (defined $info);
+        return;
+    }
+    connect_nodes ($self,$node1,"Port[$p1]",$node2,"Port[$p2]",$info);
+    add_info($info,"$string") if (defined $info);
+}
 
-
-$n1 = eval $n1;
-$p1 = eval $p1;
-
-$n2 = eval $n2;
-$p2 = eval $p2;
-
-
-my $string= "$s1 [$n1] P [$p1] -> $s2 [$n2] P [$p2]\n";
-
-my $node1=$nodes_name{$s1.$n1};
-my $node2=$nodes_name{$s2.$n2};
-
-if(!defined $node1 ){
-		add_colored_info($info,"No instance is named as \"$s1$n1\";\n","red") if (defined $info);
-		return;
-	}
-	if( !defined $node2 ){
-		add_colored_info($info,"No instance is named as \"$s2$n2\";\n","red") if (defined $info);
-		return;
-	}	
-
-
- connect_nodes ($self,$node1,"Port[$p1]",$node2,"Port[$p2]",$info);
-
-
-add_info($info,"$string") if (defined $info);
-
-		
-}	
-	
 ###########
 # connection_page_auto
-##########	
-	
+##########
 sub connection_page_auto{
-	my ($self,$info)=@_;		
-	my $table= def_table(2,10,FALSE);
-	my $row=0;
-	my $col=0;
-	
-	initial_node_info($self);
-	
-	my $help1 =  "Define the minimum number of endpoints that can be connected to a single router. Routers in the topology will have either at least a minum endpoint number or they will have no endpoints at all.";
-	my $help2 =  "Define the manimum number of endpoints that can be connected to a single router."; 
-	my $help3 =  undef; 
-	
-	
-	
-	my @widgets = (
-	{ label=>"Minimum Endp per Router",        param_name=>'MIN_ENDP_PER_ROUTER',   type=>"Spin-button",     default_val=>1, content=>"1,1024,1", info=>$help1, param_parent=>'connection_auto', ref_delay=> undef},
-	{ label=>"Maximum Endp per Router",        param_name=>'MAX_ENDP_PER_ROUTER',   type=>"Spin-button",     default_val=>1, content=>"1,1024,1", info=>$help2, param_parent=>'connection_auto', ref_delay=> undef},
-	{ label=>"Endp per Router distribution",   param_name=>'ENDP_PER_ROUTER_DIST',   type=>"Combo-box",     default_val=>"uniform", content=>"uniform,random", info=>$help3, param_parent=>'connection_auto', ref_delay=> undef},
-	{ label=>"Topology Dimention",             param_name=>'DIMENTION',   type=>"Combo-box",     default_val=>"2D", content=>"2D,3D", info=>undef, param_parent=>'connection_auto', ref_delay=> undef},
-	
-		);	
-	
-	
-
-	foreach my $d (@widgets) {
-		my $w;
-		($row,$col,$w)=add_param_widget ($self, $d->{label}, $d->{param_name}, $d->{default_val}, $d->{type}, $d->{content}, $d->{info}, $table,$row,$col,1, $d->{param_parent}, $d->{ref_delay},undef,"vertical");
-		
-	}#foreach
-	
-	
-	
-	
-	my $auto = def_image_button('icons/gen.png','Auto Connect');
-	$table->attach ($auto,1, 2,  $row, $row+1,'fill','fill',2,2);
-	$auto-> signal_connect("clicked" => sub{
-			auto_connect($self,$info);	
-	});
-	
-	my $clean = def_image_button('icons/clear.png','Remove All Connection');
-	$table->attach ($clean,0,1 ,  $row, $row+1,'fill','fill',2,2);
-	$clean-> signal_connect("clicked" => sub{
-			remove_all_connection($self); 
-	});
-	
-	
-	
-	return $table;	
+    my ($self,$info)=@_;
+    my $table= def_table(2,10,FALSE);
+    my $row=0;
+    my $col=0;
+    initial_node_info($self);
+    my $help1 =  "Define the minimum number of endpoints that can be connected to a single router. Routers in the topology will have either at least a minum endpoint number or they will have no endpoints at all.";
+    my $help2 =  "Define the manimum number of endpoints that can be connected to a single router.";
+    my $help3 =  undef;
+    my @widgets = (
+    { label=>"Minimum Endp per Router",        param_name=>'MIN_ENDP_PER_ROUTER',   type=>"Spin-button",     default_val=>1, content=>"1,1024,1", info=>$help1, param_parent=>'connection_auto', ref_delay=> undef},
+    { label=>"Maximum Endp per Router",        param_name=>'MAX_ENDP_PER_ROUTER',   type=>"Spin-button",     default_val=>1, content=>"1,1024,1", info=>$help2, param_parent=>'connection_auto', ref_delay=> undef},
+    { label=>"Endp per Router distribution",   param_name=>'ENDP_PER_ROUTER_DIST',   type=>"Combo-box",     default_val=>"uniform", content=>"uniform,random", info=>$help3, param_parent=>'connection_auto', ref_delay=> undef},
+    { label=>"Topology Dimention",             param_name=>'DIMENTION',   type=>"Combo-box",     default_val=>"2D", content=>"2D,3D", info=>undef, param_parent=>'connection_auto', ref_delay=> undef},
+    );
+    foreach my $d (@widgets) {
+        my $w;
+        ($row,$col,$w)=add_param_widget ($self, $d->{label}, $d->{param_name}, $d->{default_val}, $d->{type}, $d->{content}, $d->{info}, $table,$row,$col,1, $d->{param_parent}, $d->{ref_delay},undef,"vertical");
+    }#foreach
+    my $auto = def_image_button('icons/gen.png','Auto Connect');
+    $table->attach ($auto,1, 2,  $row, $row+1,'fill','fill',2,2);
+    $auto-> signal_connect("clicked" => sub{
+        auto_connect($self,$info);
+    });
+    my $clean = def_image_button('icons/clear.png','Remove All Connection');
+    $table->attach ($clean,0,1 ,  $row, $row+1,'fill','fill',2,2);
+    $clean-> signal_connect("clicked" => sub{
+        remove_all_connection($self);
+    });
+    return $table;
 }
 
 sub get_new_val_based_on_dist {
-	my ($total_router,$total_endp, $router_Pnum,$min_endp,$max_endp,$dist_endp)=@_;
-
-	if($dist_endp eq "uniform"){
-		my $a = int($total_endp/$total_router);
-		return $a if($a >= $min_endp && $a <$router_Pnum ); 
-		return $min_endp if($a < $min_endp  );       
-		return $router_Pnum -1 if($a >= $router_Pnum ) ;                                
-	}		
-	#random distribution	
-	my $a = int(rand($max_endp - $min_endp +1)) + $min_endp;
-	return $a if($a >= $min_endp && $a <$router_Pnum ); 
-	return $min_endp if($a < $min_endp  );       
-	return $router_Pnum -1 if($a >= $router_Pnum) ;	
+    my ($total_router,$total_endp, $router_Pnum,$min_endp,$max_endp,$dist_endp)=@_;
+    if($dist_endp eq "uniform"){
+        my $a = int($total_endp/$total_router);
+        return $a if($a >= $min_endp && $a <$router_Pnum );
+        return $min_endp if($a < $min_endp  );
+        return $router_Pnum -1 if($a >= $router_Pnum ) ;
+    }
+    #random distribution
+    my $a = int(rand($max_endp - $min_endp +1)) + $min_endp;
+    return $a if($a >= $min_endp && $a <$router_Pnum );
+    return $min_endp if($a < $min_endp  );
+    return $router_Pnum -1 if($a >= $router_Pnum) ;
 }
 
-
 sub assign_endp_num_based_on_dist {
-	my ($self,$routers_ref,$total_endp, $min_endp,$max_endp,$dist_endp,$info)=@_;
-	my @routers = @{$routers_ref};
-	my %assigned;
-	my $total_router = scalar @routers;
-	my $valid=1;
-	while ($total_endp > 0 && $valid ==1){
-		$valid =0;
-		foreach my $r (reverse @routers) {
-			my $router_Pnum=$self->object_get_attribute("$r",'PNUM');
-			my $val  = $assigned{$r};
-			if (!defined $val) {
-				$val=0;
-				$assigned{$r}=0;
-			}
-			if ($min_endp >=$router_Pnum || $total_endp ==0 ){
-				
-			} else{      
-		    	my $new =get_new_val_based_on_dist ($total_router,$total_endp, $router_Pnum,$min_endp,$max_endp,$dist_endp);
-				$new =$val + $total_endp  if(($new - $val) > $total_endp);
-				if  ($new<$min_endp){
-					
-				}
-				elsif ($new > $val){
-					$assigned{$r} = $new;
-					$total_endp-=($new - $val);
-					$valid = 1;				
-				} elsif ($val < $router_Pnum-2 && $val +1 <=$max_endp ){
-					$assigned{$r} = $val +1;
-					$total_endp-=1;
-					$valid = 1;				
-				}
-			}#else
-		}#for		
-		
-	}#while
-	  
-	if ($total_endp > 0) {
-		add_colored_info($info, "Error: Unable to assign all endpoits to routers using requested configuration. Total of $total_endp endpoints left unconnected\n",'red');
-		return (\%assigned,0);
-	}
-	
-	return (\%assigned,1);
-
+    my ($self,$routers_ref,$total_endp, $min_endp,$max_endp,$dist_endp,$info)=@_;
+    my @routers = @{$routers_ref};
+    my %assigned;
+    my $total_router = scalar @routers;
+    my $valid=1;
+    while ($total_endp > 0 && $valid ==1){
+        $valid =0;
+        foreach my $r (reverse @routers) {
+            my $router_Pnum=$self->object_get_attribute("$r",'PNUM');
+            my $val  = $assigned{$r};
+            if (!defined $val) {
+                $val=0;
+                $assigned{$r}=0;
+            }
+            if ($min_endp >=$router_Pnum || $total_endp ==0 ){
+            } else{
+                my $new =get_new_val_based_on_dist ($total_router,$total_endp, $router_Pnum,$min_endp,$max_endp,$dist_endp);
+                $new =$val + $total_endp  if(($new - $val) > $total_endp);
+                if  ($new<$min_endp){
+                }
+                elsif ($new > $val){
+                    $assigned{$r} = $new;
+                    $total_endp-=($new - $val);
+                    $valid = 1;
+                } elsif ($val < $router_Pnum-2 && $val +1 <=$max_endp ){
+                    $assigned{$r} = $val +1;
+                    $total_endp-=1;
+                    $valid = 1;
+                }
+            }#else
+        }#for
+    }#while
+    if ($total_endp > 0) {
+        add_colored_info($info, "Error: Unable to assign all endpoits to routers using requested configuration. Total of $total_endp endpoints left unconnected\n",'red');
+        return (\%assigned,0);
+    }
+    return (\%assigned,1);
 }
-
 #list the manhatan distance of all nodes in dimention ($xd,$yd,$zd) to the node located in ($xm,$ym,$zm)
 sub list_manhatan_distance {
-	my ($xd,$yd,$zd,$xm,$ym,$zm)=@_;
-	my %manhatan;
-	for( my $x=0; $x<$xd;$x++){
-		for( my $y=0; $y<$yd;$y++){
-			for( my $z=0; $z<$zd;$z++){
-				$manhatan{"$x,$y,$z"} = abs($x-$xm) + abs($y-$ym) + abs($z-$zm);
-			}
-		}
-	} 
-	return %manhatan;
+    my ($xd,$yd,$zd,$xm,$ym,$zm)=@_;
+    my %manhatan;
+    for( my $x=0; $x<$xd;$x++){
+        for( my $y=0; $y<$yd;$y++){
+            for( my $z=0; $z<$zd;$z++){
+                $manhatan{"$x,$y,$z"} = abs($x-$xm) + abs($y-$ym) + abs($z-$zm);
+            }
+        }
+    }
+    return %manhatan;
 }
 
-
-
 sub auto_connect {
-	my ($self,$info)=@_;
-	show_colored_info($info, "Start auto connecting Nodes\n",'blue');
-	add_info($info, "Step 1: Connect endpoints to the routers:\n");
-	
-	                                     
-	my $min_endp  = $self->object_get_attribute('connection_auto','MIN_ENDP_PER_ROUTER');                     
-	my $max_endp  = $self->object_get_attribute('connection_auto','MAX_ENDP_PER_ROUTER');    
-	my $dist_endp = $self->object_get_attribute('connection_auto','ENDP_PER_ROUTER_DIST');
-	my $dimention = $self->object_get_attribute('connection_auto','DIMENTION');
-	
-	 
-	#check min and max is correct
-	if($min_endp > $max_endp ){
-		add_colored_info($info, "Error: Invalid Min & Max range for endpoint router numbr per router. MAX_ENDP_PER_ROUTER shuld >= MIN_ENDP_PER_ROUTER\n",'red');
-	}                                     
-	
-	initial_node_info($self);
-	
-	my @all_endpoints=get_list_of_all_endpoints($self);
-	my @routers=get_list_of_all_routers($self);
-	
-	#connect endpoints
-	my ($ref,$result)  = assign_endp_num_based_on_dist ($self,\@routers,scalar @all_endpoints, $min_endp,$max_endp,$dist_endp,$info);
-	my %assign = %{$ref};
-	my %router_free_port;
-	foreach my $r (reverse @routers) {		
-		$router_free_port{$r}=$self->object_get_attribute("$r",'PNUM');
-		my $num = $assign{$r};
-		for (my $p=0; $p<$num;$p++){
-			my $e = pop (@all_endpoints);
-			connect_nodes ($self,$r,"Port[$p]",$e,"Port[0]",$info);
-			my $rinst=$self->object_get_attribute("$r",'NAME');
-			my $einst=$self->object_get_attribute("$e",'NAME');
-			add_info($info,"\t connect $rinst-Port[$p] -> $einst-Port[0]\n",$info);
-			$router_free_port{$r}=$router_free_port{$r}-1;
-		}		
-	}
-	
-	#get dimention 
-	my $routers_num =scalar @routers;
-	my ($xd,$yd,$zd)=(1,1,1);
-	($xd,$yd)= network_dim_cal ($routers_num) if ($dimention eq '2D');
-	($xd,$yd,$zd)=network_3dim_cal ($routers_num) if ($dimention eq '3D');
-	add_info($info, "Step 2: Map $routers_num routers in (x=$xd , y=$yd , z=$zd) dimention. Routers with higher number of free ports located in center:\n");
-	
-	#obtain routers location 
-	#center loc
-	my $xmid =int($xd/2); 
-	my $ymid =int($yd/2);
-	my $zmid =int($zd/2);
-	
-	#sort location based on manhatan distanc from the center
-	my %manhatan = list_manhatan_distance ($xd,$yd,$zd,$xmid,$ymid,$zmid);
-	my @sort_locs = (sort { $manhatan{$a} <=> $manhatan{$b} } keys %manhatan);
-	
-	#sort routers based on avilable ports
-	my @sort_routers = (sort { $router_free_port{$b} <=> $router_free_port{$a} } keys %router_free_port);
-	
-	#assign sorted routers to sorted locations 
-	my %locations;
-	foreach my $r (@sort_routers){
-    	my $loc = shift @sort_locs;
-    	my $inst=$self->object_get_attribute("$r",'NAME');
-    	add_info($info, "\t $inst with $router_free_port{$r} free port placed in $loc location\n");
-    	$self->object_add_attribute("$r",'LOC_ASIC',$loc);
-    	$locations{$loc}=$r;    	
-	}
-	
-	#start from the center and connect each router to the N nearest router
-	add_info($info,"Step3 : start from the center and connect each router to the N nearest router\n",$info);
-	foreach my $r (@sort_routers){
-		
-		my $avb_P_num =$router_free_port{$r};
-		my @up = list_node_unconnected_port($self,$r);
-		my @cp = list_node_connected_port ($self,$r);
-		my $loc = $self->object_get_attribute("$r",'LOC_ASIC');
-		my ($xc,$yc,$zc)=split(',',$loc);
-		my %manhatan = list_manhatan_distance ($xd,$yd,$zd,$xc,$yc,$zc);
-		my @sort_locs = (sort { $manhatan{$a} <=> $manhatan{$b} } keys %manhatan);
-		
-		while (scalar @up && scalar @sort_locs){
-			#select one unconnected port from current router
-			my $p = shift @up;
-			my $cr;
-			my $cp;
-			while (scalar @sort_locs && !defined $cp){			
-				#select the nearest router to current one
-				my $cl =shift @sort_locs;
-				$cr=$locations{$cl};
-				next if(!defined $cr);
-				next if ($cr eq $r); #thes two routers are identical
-				#check if they are not connected
-				my $line =get_connection_port_num_between_two_nodes($self,$r,$cr);
-				next if (defined $line); #these two routers are already connected
-				my @up_cr = list_node_unconnected_port($self,$cr);	
-				next if (scalar @up_cr == 0); # the target router has no free port
-				$cp=$up_cr[0];
-			}
-			last if(!defined $cp);
-			my $rinst=$self->object_get_attribute("$r",'NAME');
-			my $einst=$self->object_get_attribute("$cr",'NAME');
-			add_info($info,"\t connect $rinst-$p -> $einst-$cp\n",$info);
-			connect_nodes ($self,$r,"$p",$cr,"$cp",$info);
-		}	
-		
-	}	
-	
-	
-	
-	
-	
-	
-	set_gui_status($self,"ref",1);
-	
-	  
-	
-	
-	
+    my ($self,$info)=@_;
+    show_colored_info($info, "Start auto connecting Nodes\n",'blue');
+    add_info($info, "Step 1: Connect endpoints to the routers:\n");
+    my $min_endp  = $self->object_get_attribute('connection_auto','MIN_ENDP_PER_ROUTER');
+    my $max_endp  = $self->object_get_attribute('connection_auto','MAX_ENDP_PER_ROUTER');
+    my $dist_endp = $self->object_get_attribute('connection_auto','ENDP_PER_ROUTER_DIST');
+    my $dimention = $self->object_get_attribute('connection_auto','DIMENTION');
+    #check min and max is correct
+    if($min_endp > $max_endp ){
+        add_colored_info($info, "Error: Invalid Min & Max range for endpoint router numbr per router. MAX_ENDP_PER_ROUTER shuld >= MIN_ENDP_PER_ROUTER\n",'red');
+    }
+    initial_node_info($self);
+    my @all_endpoints=get_list_of_all_endpoints($self);
+    my @routers=get_list_of_all_routers($self);
+    #connect endpoints
+    my ($ref,$result)  = assign_endp_num_based_on_dist ($self,\@routers,scalar @all_endpoints, $min_endp,$max_endp,$dist_endp,$info);
+    my %assign = %{$ref};
+    my %router_free_port;
+    foreach my $r (reverse @routers) {
+        $router_free_port{$r}=$self->object_get_attribute("$r",'PNUM');
+        my $num = $assign{$r};
+        for (my $p=0; $p<$num;$p++){
+            my $e = pop (@all_endpoints);
+            connect_nodes ($self,$r,"Port[$p]",$e,"Port[0]",$info);
+            my $rinst=$self->object_get_attribute("$r",'NAME');
+            my $einst=$self->object_get_attribute("$e",'NAME');
+            add_info($info,"\t connect $rinst-Port[$p] -> $einst-Port[0]\n",$info);
+            $router_free_port{$r}=$router_free_port{$r}-1;
+        }
+    }
+    #get dimention
+    my $routers_num =scalar @routers;
+    my ($xd,$yd,$zd)=(1,1,1);
+    ($xd,$yd)= network_dim_cal ($routers_num) if ($dimention eq '2D');
+    ($xd,$yd,$zd)=network_3dim_cal ($routers_num) if ($dimention eq '3D');
+    add_info($info, "Step 2: Map $routers_num routers in (x=$xd , y=$yd , z=$zd) dimention. Routers with higher number of free ports located in center:\n");
+    #obtain routers location
+    #center loc
+    my $xmid =int($xd/2);
+    my $ymid =int($yd/2);
+    my $zmid =int($zd/2);
+    #sort location based on manhatan distanc from the center
+    my %manhatan = list_manhatan_distance ($xd,$yd,$zd,$xmid,$ymid,$zmid);
+    my @sort_locs = (sort { $manhatan{$a} <=> $manhatan{$b} } keys %manhatan);
+    #sort routers based on avilable ports
+    my @sort_routers = (sort { $router_free_port{$b} <=> $router_free_port{$a} } keys %router_free_port);
+    #assign sorted routers to sorted locations
+    my %locations;
+    foreach my $r (@sort_routers){
+        my $loc = shift @sort_locs;
+        my $inst=$self->object_get_attribute("$r",'NAME');
+        add_info($info, "\t $inst with $router_free_port{$r} free port placed in $loc location\n");
+        $self->object_add_attribute("$r",'LOC_ASIC',$loc);
+        $locations{$loc}=$r;
+    }
+    #start from the center and connect each router to the N nearest router
+    add_info($info,"Step3 : start from the center and connect each router to the N nearest router\n",$info);
+    foreach my $r (@sort_routers){
+        my $avb_P_num =$router_free_port{$r};
+        my @up = list_node_unconnected_port($self,$r);
+        my @cp = list_node_connected_port ($self,$r);
+        my $loc = $self->object_get_attribute("$r",'LOC_ASIC');
+        my ($xc,$yc,$zc)=split(',',$loc);
+        my %manhatan = list_manhatan_distance ($xd,$yd,$zd,$xc,$yc,$zc);
+        my @sort_locs = (sort { $manhatan{$a} <=> $manhatan{$b} } keys %manhatan);
+        while (scalar @up && scalar @sort_locs){
+            #select one unconnected port from current router
+            my $p = shift @up;
+            my $cr;
+            my $cp;
+            while (scalar @sort_locs && !defined $cp){
+                #select the nearest router to current one
+                my $cl =shift @sort_locs;
+                $cr=$locations{$cl};
+                next if(!defined $cr);
+                next if ($cr eq $r); #thes two routers are identical
+                #check if they are not connected
+                my $line =get_connection_port_num_between_two_nodes($self,$r,$cr);
+                next if (defined $line); #these two routers are already connected
+                my @up_cr = list_node_unconnected_port($self,$cr);
+                next if (scalar @up_cr == 0); # the target router has no free port
+                $cp=$up_cr[0];
+            }
+            last if(!defined $cp);
+            my $rinst=$self->object_get_attribute("$r",'NAME');
+            my $einst=$self->object_get_attribute("$cr",'NAME');
+            add_info($info,"\t connect $rinst-$p -> $einst-$cp\n",$info);
+            connect_nodes ($self,$r,"$p",$cr,"$cp",$info);
+        }
+    }
+    set_gui_status($self,"ref",1);
 }
 
 sub routing_page_auto{
-	my ($self,$info)=@_;		
-	my $table= def_table(2,10,FALSE);
-	my $row=0;
-	my $col=0;
-	
-	
-	$self->object_add_attribute('routing','type','turn_model');
-	
-	
-	
-	my $auto = def_image_button('icons/gen.png','AutoGenerate');
-	#$table->attach ($auto,0, 1,  $row, $row+1,'fill','fill',2,2);
-	my $clear = def_image_button('icons/clear.png','Clear');
-	#$table->attach ($clear,2,3 ,  $row, $row+1,'fill','fill',2,2);$row++;
-	
-	my $box= def_pack_hbox( FALSE, 0 , $auto,$clear);
-	$table->attach ($box,0,5 ,  $row, $row+1,'fill','fill',2,2);$row++;
-	
-	$auto-> signal_connect("clicked" => sub{
-			auto_route($self,$info);	
-	});
-	
-	$clear-> signal_connect("clicked" => sub{
-			clean_route($self,$info);	
-	});
-	
-	my $manual = get_route_manual ($self,$info);
-	
-	my $mtable= def_table(2,2,FALSE);
-	
-	$mtable->attach_defaults ($table  , 0, 1, 0,1);
-	$mtable->attach_defaults ($manual  , 0, 1, 1,2);
-	
-	return $mtable;
+    my ($self,$info)=@_;
+    my $table= def_table(2,10,FALSE);
+    my $row=0;
+    my $col=0;
+    $self->object_add_attribute('routing','type','turn_model');
+    my $auto = def_image_button('icons/gen.png','AutoGenerate');
+    #$table->attach ($auto,0, 1,  $row, $row+1,'fill','fill',2,2);
+    my $clear = def_image_button('icons/clear.png','Clear');
+    #$table->attach ($clear,2,3 ,  $row, $row+1,'fill','fill',2,2);$row++;
+    my $box= def_pack_hbox( FALSE, 0 , $auto,$clear);
+    $table->attach ($box,0,5 ,  $row, $row+1,'fill','fill',2,2);$row++;
+    $auto-> signal_connect("clicked" => sub{
+        auto_route($self,$info);
+    });
+    $clear-> signal_connect("clicked" => sub{
+        clean_route($self,$info);
+    });
+    my $manual = get_route_manual ($self,$info);
+    my $mtable= def_table(2,2,FALSE);
+    $mtable->attach_defaults ($table  , 0, 1, 0,1);
+    $mtable->attach_defaults ($manual  , 0, 1, 1,2);
+    return $mtable;
 }
 
 sub update_acycle_model {
-	my ($self,$alg_name,$info)=@_; 
-	my $tmp_dir  = "$ENV{'PRONOC_WORK'}/tmp";
-	my $model_file = "$tmp_dir/$alg_name.alg";	
-	my ($pp,$r,$err) = regen_object($model_file);
-	if ($r){        
-		add_colored_info($info,"**Error: cannot open $model_file file: $err\n",'red');
-		$self->object_add_attribute('routing_auto','acyclic_turns_model',undef);
-		return;
-	} else {
-		add_info($info,"Use $alg_name algorithm for obtaing acyclic paths\n");
-	}
-
-	my @acyclic_turns = @{$pp};			
-	$self->object_add_attribute('routing_auto','acyclic_turns_model',\@acyclic_turns);
-			
-}			
-
+    my ($self,$alg_name,$info)=@_;
+    my $tmp_dir  = "$ENV{'PRONOC_WORK'}/tmp";
+    my $model_file = "$tmp_dir/$alg_name.alg";
+    my ($pp,$r,$err) = regen_object($model_file);
+    if ($r){
+        add_colored_info($info,"**Error: cannot open $model_file file: $err\n",'red');
+        $self->object_add_attribute('routing_auto','acyclic_turns_model',undef);
+        return;
+    } else {
+        add_info($info,"Use $alg_name algorithm for obtaing acyclic paths\n");
+    }
+    my @acyclic_turns = @{$pp};
+    $self->object_add_attribute('routing_auto','acyclic_turns_model',\@acyclic_turns);
+}
 
 sub routing_page_manual{
-	my ($self,$info)=@_;		
-	my $table= def_table(2,10,FALSE);
-	my $row=0;
-	my $col=0;
-	
-	$self->object_add_attribute('routing','type','minimal');
-	
-	initial_node_info($self);
-	my $help1 =  "Define the offset path value that is the maximum difference between the lentght of all paths which are extracted for any specefic source-destination endpoints pair. Define this valuse as zero for Minimal-path (MIN) routing algorithms.";  
-	my $help2 =  "Define the maximum number of routers (path length) paths which should be extracted for any specefic source-destination endpoints pair."; 
-	my $help3 =  "Define how to extract paths between two endpoints: all-paths: extract all paths between two specific endpoints that match the offset size and maximum size parameters. Cycle-free: only paths which do not generate a cyclic dependency in routing graph are extracted.";
-	
-	
-	my @widgets = (
-	{ label=>"Route path offset size ",        param_name=>'OFFSET',   type=>"Spin-button",     default_val=>1, content=>"0,1024,1", info=>$help1, param_parent=>'routing_auto', ref_delay=>"1",ref_state=> undef},
-	{ label=>"Route path maximum size",        param_name=>'MAX_LENGTH',   type=>"Spin-button",     default_val=>1000, content=>"1,1024,1", info=>$help2, param_parent=>'routing_auto', ref_delay=>"1",ref_state=> undef},
-	{ label=>"Route paths select",        param_name=>'PATH_SELECT',   type=>"Combo-box",     default_val=>"Cycle-free paths", content=>"all-paths,Cycle-free paths", info=>$help3, param_parent=>'routing_auto', ref_delay=>"1",ref_state=> undef },
-	
-	);	
-	
-		
-	foreach my $d (@widgets) {
-		my $w;
-		($row,$col,$w)=add_param_widget ($self, $d->{label}, $d->{param_name}, $d->{default_val}, $d->{type}, $d->{content}, $d->{info}, $table,$row,$col,1, $d->{param_parent}, $d->{ref_delay},$d->{ref_state},"vertical");
-		
-	}#foreach
-	my $offset = $self->object_get_attribute('routing_auto','OFFSET');
-	my $max_len = $self->object_get_attribute('routing_auto','MAX_LENGTH');	
-	
-	my $auto = def_image_button('icons/gen.png','AutoGenerate');
-	
-	my $path_select= $self->object_get_attribute("routing_auto",'PATH_SELECT');
-	if($path_select eq "Cycle-free paths") {
-		my %algorithms;
-		my $ref  =$self->object_get_attribute('routing_auto','acyclic_algorithms');
-		%algorithms = %{$ref} if defined $ref;
-		my @algs = sort { $algorithms{$a} <=> $algorithms{$b} } keys(%algorithms);
-		my ($content,$default);
-		foreach my $alg (@algs){
-			$content.="$alg  --  $algorithms{$alg},";
-			$default= "$alg  --  $algorithms{$alg};";
-						
-		}
-		if (!defined $content){
-			$content='-';
-			$default='-';
-			
-		}
-		
-		my $alg;
-		($row,$col,$alg)=add_param_widget ($self,"cycle-remove algorithm:" , "CYCLE_FREE_ALG",$default , "Combo-box", $content, undef, $table,$row,$col,1,'routing_auto', undef,undef,"vertical");
-		
-		$alg->signal_connect("changed" => sub{
-			my $comb_text = $alg->get_active_text();
-			my ($alg_name,$line) = split (/\s+--\s+/,$comb_text);
-			update_acycle_model ($self,$alg_name,$info);
-			#print "bbbb:@acyclic_turns\n";	
-		});
-		
-		$auto-> signal_connect("clicked" => sub{
-			auto_route($self,$info);	
-		});
-		
-		
-	}
-	
-	
-	
-	
-	my $clear = def_image_button('icons/clear.png','Clear');
-	my $gen_cycle_free = def_image_button('icons/turn.png','Generate Cycle-free Paths');
-	
-	if($path_select eq 'Cycle-free paths') {
-		$table->attach ($gen_cycle_free,0,2 ,  $row, $row+1,'fill','fill',2,2);$row++;
-		$table->attach ($auto,2, 3,  $row, $row+1,'fill','fill',2,2);
-		
-	}
-	$table->attach ($clear,0,2 ,  $row, $row+1,'fill','fill',2,2);$row++;		
-	
-	
-	$clear-> signal_connect("clicked" => sub{
-			clean_route($self,$info);	
-	});
-	
-	$gen_cycle_free -> signal_connect("clicked" => sub{
-			gen_aciclic_turn_graph($self,$info);
-			my %algorithms;
-			my $ref  =$self->object_get_attribute('routing_auto','acyclic_algorithms');
-			%algorithms = %{$ref} if defined $ref;
-			my @algs = sort { $algorithms{$a} <=> $algorithms{$b} } keys(%algorithms);
-			update_acycle_model ($self,$algs[0],$info);
-			set_gui_status($self,'ref',1);		
-	});
-	
-	my $manual = get_route_manual ($self,$info);
-	
-	my $mtable= def_table(2,2,FALSE);
-	
-	$mtable->attach_defaults ($table  , 0, 1, 0,1);
-	$mtable->attach_defaults ($manual  , 0, 1, 1,2);
-	
-	return $mtable;
+    my ($self,$info)=@_;
+    my $table= def_table(2,10,FALSE);
+    my $row=0;
+    my $col=0;
+    $self->object_add_attribute('routing','type','minimal');
+    initial_node_info($self);
+    my $help1 =  "Define the offset path value that is the maximum difference between the lentght of all paths which are extracted for any specefic source-destination endpoints pair. Define this valuse as zero for Minimal-path (MIN) routing algorithms.";
+    my $help2 =  "Define the maximum number of routers (path length) paths which should be extracted for any specefic source-destination endpoints pair.";
+    my $help3 =  "Define how to extract paths between two endpoints: all-paths: extract all paths between two specific endpoints that match the offset size and maximum size parameters. Cycle-free: only paths which do not generate a cyclic dependency in routing graph are extracted.";
+    my @widgets = (
+    { label=>"Route path offset size ",        param_name=>'OFFSET',   type=>"Spin-button",     default_val=>1, content=>"0,1024,1", info=>$help1, param_parent=>'routing_auto', ref_delay=>"1",ref_state=> undef},
+    { label=>"Route path maximum size",        param_name=>'MAX_LENGTH',   type=>"Spin-button",     default_val=>1000, content=>"1,1024,1", info=>$help2, param_parent=>'routing_auto', ref_delay=>"1",ref_state=> undef},
+    { label=>"Route paths select",        param_name=>'PATH_SELECT',   type=>"Combo-box",     default_val=>"Cycle-free paths", content=>"all-paths,Cycle-free paths", info=>$help3, param_parent=>'routing_auto', ref_delay=>"1",ref_state=> undef },
+    );
+    foreach my $d (@widgets) {
+        my $w;
+        ($row,$col,$w)=add_param_widget ($self, $d->{label}, $d->{param_name}, $d->{default_val}, $d->{type}, $d->{content}, $d->{info}, $table,$row,$col,1, $d->{param_parent}, $d->{ref_delay},$d->{ref_state},"vertical");
+    }#foreach
+    my $offset = $self->object_get_attribute('routing_auto','OFFSET');
+    my $max_len = $self->object_get_attribute('routing_auto','MAX_LENGTH');
+    my $auto = def_image_button('icons/gen.png','AutoGenerate');
+    my $path_select= $self->object_get_attribute("routing_auto",'PATH_SELECT');
+    if($path_select eq "Cycle-free paths") {
+        my %algorithms;
+        my $ref  =$self->object_get_attribute('routing_auto','acyclic_algorithms');
+        %algorithms = %{$ref} if defined $ref;
+        my @algs = sort { $algorithms{$a} <=> $algorithms{$b} } keys(%algorithms);
+        my ($content,$default);
+        foreach my $alg (@algs){
+            $content.="$alg  --  $algorithms{$alg},";
+            $default= "$alg  --  $algorithms{$alg};";
+        }
+        if (!defined $content){
+            $content='-';
+            $default='-';
+        }
+        my $alg;
+        ($row,$col,$alg)=add_param_widget ($self,"cycle-remove algorithm:" , "CYCLE_FREE_ALG",$default , "Combo-box", $content, undef, $table,$row,$col,1,'routing_auto', undef,undef,"vertical");
+        $alg->signal_connect("changed" => sub{
+            my $comb_text = $alg->get_active_text();
+            my ($alg_name,$line) = split (/\s+--\s+/,$comb_text);
+            update_acycle_model ($self,$alg_name,$info);
+            #print "bbbb:@acyclic_turns\n";
+        });
+        $auto-> signal_connect("clicked" => sub{
+            auto_route($self,$info);
+        });
+    }
+    my $clear = def_image_button('icons/clear.png','Clear');
+    my $gen_cycle_free = def_image_button('icons/turn.png','Generate Cycle-free Paths');
+    if($path_select eq 'Cycle-free paths') {
+        $table->attach ($gen_cycle_free,0,2 ,  $row, $row+1,'fill','fill',2,2);$row++;
+        $table->attach ($auto,2, 3,  $row, $row+1,'fill','fill',2,2);
+    }
+    $table->attach ($clear,0,2 ,  $row, $row+1,'fill','fill',2,2);$row++;
+    $clear-> signal_connect("clicked" => sub{
+        clean_route($self,$info);
+    });
+    $gen_cycle_free -> signal_connect("clicked" => sub{
+        gen_aciclic_turn_graph($self,$info);
+        my %algorithms;
+        my $ref  =$self->object_get_attribute('routing_auto','acyclic_algorithms');
+        %algorithms = %{$ref} if defined $ref;
+        my @algs = sort { $algorithms{$a} <=> $algorithms{$b} } keys(%algorithms);
+        update_acycle_model ($self,$algs[0],$info);
+        set_gui_status($self,'ref',1);
+    });
+    my $manual = get_route_manual ($self,$info);
+    my $mtable= def_table(2,2,FALSE);
+    $mtable->attach_defaults ($table  , 0, 1, 0,1);
+    $mtable->attach_defaults ($manual  , 0, 1, 1,2);
+    return $mtable;
 }
 
-
-
-
 sub get_route_manual {
-	my ($self,$info)=@_;	
-	
-	my $row=0;
-	my $col=0;
-		
-	my $table= def_table(2,10,FALSE);
-	
-	add_Hsep_to_table ($table,0, 200,  $row);$row++;
-	
-	my $refresh = def_image_button('icons/refresh.png','Refresh');
-	$table->attach ($refresh,0,5 ,  $row, $row+1,'fill','fill',2,2);$row++;
-		
-
-	$table->attach (gen_colored_label('Not selected',17),5,10,$row,$row+1,'fill','shrink',2,2);	
-	$table->attach (gen_colored_label('Selected',0),10,15,$row,$row+1,'fill','shrink',2,2);	
-	$table->attach (gen_colored_label('Not Existed',11),15,20,$row,$row+1,'fill','shrink',2,2);	
-	$row++;	
-	
-	$table->attach (def_label(' source -> destination '),10,15,$row,$row+1,'fill','shrink',2,2);	
-    $row++;	
-	
-		
-	my @all_endpoints=get_list_of_all_endpoints($self);
-		
-	foreach  my $src  (@all_endpoints ){	
-		foreach  my $dst  (@all_endpoints ){	
-			my $src_inst=$self->object_get_attribute("$src",'NAME');
-			my $dst_inst=$self->object_get_attribute("$dst",'NAME');
-		   	my $select = $self->object_get_attribute('Route',"${src}::$dst");
-		   	
-		  	#my ($paths_to_dst,$ports_to_dst); #= get_all_paths_between_two_endps($self,$src, $dst);
-		  	#my $color =(scalar @{$paths_to_dst}==0)? 11 :  (defined $select)? 0 : 17;		   		   	
-		   	#my $button = ($src_inst ne $dst_inst )?  def_colored_button("${src_inst}->$dst_inst",$color): gen_label_in_center(' - ');	
-		   	
-		   	my $color = (defined $select)? 0 :17;		   		   	
-		   	my $button = ($src_inst ne $dst_inst )?  def_colored_button("${src_inst}->$dst_inst",$color): gen_label_in_center(' - ');	
-		   
-		   	
-		   	attach_widget_to_table ($table,$row,undef,undef,$button,$col);  $col+=4;	
-		   	
-		   	
-		   	
-		   	$button->signal_connect("clicked" => sub {
-		   		$self->object_add_attribute("SELECT_PATH","src",$src);
-		   		$self->object_add_attribute("SELECT_PATH","dst",$dst);		   		
-		   		set_gui_status($self,"redraw",1);
-				
-			}) if($src_inst ne $dst_inst );	
-		   		
-   	   
-		}$row++;$col=0;
-	} 
-	
-	
-	$refresh->signal_connect("clicked" => sub{
-			refresh_route_manual($self,$info);	
-	});
-			
-	return $table;
+    my ($self,$info)=@_;
+    my $row=0;
+    my $col=0;
+    my $table= def_table(2,10,FALSE);
+    add_Hsep_to_table ($table,0, 200,  $row);$row++;
+    my $refresh = def_image_button('icons/refresh.png','Refresh');
+    $table->attach ($refresh,0,5 ,  $row, $row+1,'fill','fill',2,2);$row++;
+    $table->attach (gen_colored_label('Not selected',17),5,10,$row,$row+1,'fill','shrink',2,2);
+    $table->attach (gen_colored_label('Selected',0),10,15,$row,$row+1,'fill','shrink',2,2);
+    $table->attach (gen_colored_label('Not Existed',11),15,20,$row,$row+1,'fill','shrink',2,2);
+    $row++;
+    $table->attach (def_label(' source -> destination '),10,15,$row,$row+1,'fill','shrink',2,2);
+    $row++;
+    my @all_endpoints=get_list_of_all_endpoints($self);
+    foreach  my $src  (@all_endpoints ){
+        foreach  my $dst  (@all_endpoints ){
+            my $src_inst=$self->object_get_attribute("$src",'NAME');
+            my $dst_inst=$self->object_get_attribute("$dst",'NAME');
+            my $select = $self->object_get_attribute('Route',"${src}::$dst");
+            #my ($paths_to_dst,$ports_to_dst); #= get_all_paths_between_two_endps($self,$src, $dst);
+            #my $color =(scalar @{$paths_to_dst}==0)? 11 :  (defined $select)? 0 : 17;
+            #my $button = ($src_inst ne $dst_inst )?  def_colored_button("${src_inst}->$dst_inst",$color): gen_label_in_center(' - ');
+            my $color = (defined $select)? 0 :17;
+            my $button = ($src_inst ne $dst_inst )?  def_colored_button("${src_inst}->$dst_inst",$color): gen_label_in_center(' - ');
+            attach_widget_to_table ($table,$row,undef,undef,$button,$col);  $col+=4;
+            $button->signal_connect("clicked" => sub {
+                $self->object_add_attribute("SELECT_PATH","src",$src);
+                $self->object_add_attribute("SELECT_PATH","dst",$dst);
+                set_gui_status($self,"redraw",1);
+            }) if($src_inst ne $dst_inst );
+        }$row++;$col=0;
+    }
+    $refresh->signal_connect("clicked" => sub{
+        refresh_route_manual($self,$info);
+    });
+    return $table;
 }
 
-
 sub refresh_route_manual {
-	my ($self,$info)=@_;
-	my @all_endpoints=get_list_of_all_endpoints($self);
-	
-	my $path_select= $self->object_get_attribute("routing_auto",'PATH_SELECT');
-	my @acyclic_turns;	
-
-
-	if ($path_select ne "all-paths"){
-		 my $ref = $self->object_get_attribute('routing_auto','acyclic_turns_model'); 
-		 if(defined $ref) {
-		 	@acyclic_turns = @{$ref};
-		 }else{
-		 	add_colored_info($info,"Info:No acyclic route model is selected\n",'green');
-		 		 	
-		 }	
-	}
-		
-	foreach  my $src  (@all_endpoints ){	
-		foreach  my $dst  (@all_endpoints ){	
-			my $src_inst=$self->object_get_attribute("$src",'NAME');
-			my $dst_inst=$self->object_get_attribute("$dst",'NAME');
-		   	my $select = $self->object_get_attribute('Route',"${src}::$dst");
-		   	
-		   	my ($ref1,$ref2)= ($path_select eq "all-paths")? get_all_paths_between_two_endps($self,$src, $dst) : get_all_paths_between_two_endps_using_accyclic_turn($self,$src, $dst,\@acyclic_turns) ;
-			my @paths = @{$ref1};
-			if (defined $select){
-				#check if select exist in @paths
-				my $match=0;
-			
-				foreach  my $p (@paths ){
-					my @a1 = @{$p};
-					my @a2 = @{$select};
-					my $st1=join('->',@a1);
-					my $st2=join('->',@a2);
-					if($st1 eq $st2){
-						$match=1;
-					}
-				}#foreach
-				#remove it from the selected path
-				if ($match ==0){
-					my $selp;
-					foreach my $q ( @{$select}){
-						my $inst=$self->object_get_attribute("$q",'NAME');
-						$selp= (defined $selp)? $selp."->$inst" : $inst;
-					}
-					
-					add_info ($info,"$selp does not exist in path list anymore and it has been removed\n"); 
-					$self->object_add_attribute('Route',"${src}::$dst",undef);
-				}#if 
-			}#if 
-		}#foreach
-	}#foreach	   	
-		   	
-	
-	set_gui_status($self,"ref",1);
-	
-}		
-
+    my ($self,$info)=@_;
+    my @all_endpoints=get_list_of_all_endpoints($self);
+    my $path_select= $self->object_get_attribute("routing_auto",'PATH_SELECT');
+    my @acyclic_turns;
+    if ($path_select ne "all-paths"){
+        my $ref = $self->object_get_attribute('routing_auto','acyclic_turns_model');
+        if(defined $ref) {
+            @acyclic_turns = @{$ref};
+        }else{
+            add_colored_info($info,"Info:No acyclic route model is selected\n",'green');
+        }
+    }
+    foreach  my $src  (@all_endpoints ){
+        foreach  my $dst  (@all_endpoints ){
+            my $src_inst=$self->object_get_attribute("$src",'NAME');
+            my $dst_inst=$self->object_get_attribute("$dst",'NAME');
+            my $select = $self->object_get_attribute('Route',"${src}::$dst");
+            my ($ref1,$ref2)= ($path_select eq "all-paths")? get_all_paths_between_two_endps($self,$src, $dst) : get_all_paths_between_two_endps_using_accyclic_turn($self,$src, $dst,\@acyclic_turns) ;
+            my @paths = @{$ref1};
+            if (defined $select){
+                #check if select exist in @paths
+                my $match=0;
+                foreach  my $p (@paths ){
+                    my @a1 = @{$p};
+                    my @a2 = @{$select};
+                    my $st1=join('->',@a1);
+                    my $st2=join('->',@a2);
+                    if($st1 eq $st2){
+                        $match=1;
+                    }
+                }#foreach
+                #remove it from the selected path
+                if ($match ==0){
+                    my $selp;
+                    foreach my $q ( @{$select}){
+                        my $inst=$self->object_get_attribute("$q",'NAME');
+                        $selp= (defined $selp)? $selp."->$inst" : $inst;
+                    }
+                    add_info ($info,"$selp does not exist in path list anymore and it has been removed\n");
+                    $self->object_add_attribute('Route',"${src}::$dst",undef);
+                }#if
+            }#if
+        }#foreach
+    }#foreach
+    set_gui_status($self,"ref",1);
+}
 
 sub route_info_window{
-	my ($self,$info)= @_;	
-	my $w1 = show_paths_between_two_endps($self,$info);
-	my $w2 = routing_summary($self,$info);
-	my $h1=gen_hpaned($w1,.30,$w2);		
-	return $h1;	
+    my ($self,$info)= @_;
+    my $w1 = show_paths_between_two_endps($self,$info);
+    my $w2 = routing_summary($self,$info);
+    my $h1=gen_hpaned($w1,.30,$w2);
+    return $h1;
 }
 
-
-
 sub add_route_edge_to_graph{
-	my ($gref,$anodes_ref)=@_;
-	my %graph=%{$gref};
-	my @a_nodes= @{$anodes_ref};
-	
-	my $old_r;	
-	foreach my $r (@a_nodes){
-		
-		if(defined $old_r){
-			        push(@{$graph{$old_r}},$r);										
-		}
-		$old_r=$r;
-	}	
-	
-	return %graph;	
+    my ($gref,$anodes_ref)=@_;
+    my %graph=%{$gref};
+    my @a_nodes= @{$anodes_ref};
+    my $old_r;
+    foreach my $r (@a_nodes){
+        if(defined $old_r){
+            push(@{$graph{$old_r}},$r);
+        }
+        $old_r=$r;
+    }
+    return %graph;
 }
 
 sub get_adjacent_node_in_a_path{
-	my $ref=shift;
-	my @result;
-	my @path=@{$ref};
-	my $old_r;	
-	foreach my $r (@path){	
-		push (@result,"${old_r}::$r") if(defined $old_r);
-		$old_r=$r;
-	}	
-	return @result;
-	
+    my $ref=shift;
+    my @result;
+    my @path=@{$ref};
+    my $old_r;
+    foreach my $r (@path){
+        push (@result,"${old_r}::$r") if(defined $old_r);
+        $old_r=$r;
+    }
+    return @result;
 }
 
 sub get_adjacent_router_in_a_path{
-	
-	my $ref=shift;
-	my @result;
-	my @path=@{$ref};
-	shift @path; #remove source node from the path
-	pop @path; #remove the destination node from the path
-	
-	
-	my $old_r;	
-	foreach my $r (@path){	
-		push (@result,"${old_r}::$r") if(defined $old_r);
-		$old_r=$r;
-	}	
-	return @result;
-	
+    my $ref=shift;
+    my @result;
+    my @path=@{$ref};
+    shift @path; #remove source node from the path
+    pop @path; #remove the destination node from the path
+    my $old_r;
+    foreach my $r (@path){
+        push (@result,"${old_r}::$r") if(defined $old_r);
+        $old_r=$r;
+    }
+    return @result;
 }
 
-
 sub get_route_info{
-	my ($self)=@_;
-	my %R_num;
-	my %L_num;
-	my @all_endpoints=get_list_of_all_endpoints($self);
-	foreach  my $r  (@all_endpoints ){
-		#$R_num{$r} =0;
-	}
-	my @nodes=get_list_of_all_routers($self);
-	foreach my $p (@nodes){
-		$R_num{$p} =0;
-	}	
-	foreach  my $src  (@all_endpoints ){	
-		foreach  my $dst  (@all_endpoints ){	
-			my $path = $self->object_get_attribute('Route',"${src}::$dst");
-			if (defined $path){				
-				#router counting
-				my @p=@{$path};
-				shift @p; #remove source node from the path
-				pop @p; #remove the destination node from the path
-				foreach my $r (@p){				
-					$R_num{$r} ++;					
-				}
-				#path counting
-				@p= 	get_adjacent_router_in_a_path($path);
-				foreach my $r (@p){				
-					$L_num{$r} ++;	
-							
-				}
-			
-			
-			}			
-		}
-	}
-	
-	my @Rkeys = sort { $R_num{$a} <=> $R_num{$b} } keys(%R_num);
-	my @Lkeys = sort { $L_num{$a} <=> $L_num{$b} } keys(%L_num);
-	my $sample="sample0";
-	foreach  my $r  (@nodes ){
-		my $inst=$self->object_get_attribute("$r",'NAME');
-		update_result ($self,$sample,"router_all_paths_result",'-',$inst,$R_num{$r});
-	}
-	
-	my $max_r = (defined $Rkeys[-1]) ? $R_num{$Rkeys[-1]} : 0;
-	my $min_r = (defined $Rkeys[ 0]) ? $R_num{$Rkeys[ 0]} : 0;
-	my $max_l = (defined $Lkeys[-1]) ? $L_num{$Lkeys[-1]} : 0;
-	my $min_l = (defined $Lkeys[ 0]) ? $L_num{$Lkeys[ 0]} : 0;
-	my @l = sort  values (%L_num);
-	my $std_l=stdev(\@l);	
-	
-	$self->object_add_attribute ($sample,"link_all_paths_result",undef);
-	
-	my $nn=0;
-	my $min_l_name="-";
-	my $max_l_name="-";
-	my $siz = $#Lkeys;
-	foreach  my $r  (@Lkeys ){
-		my ($n1,$n2)=split(/::/,$r);
-		my $inst1=$self->object_get_attribute("$n1",'NAME');
-		my $inst2=$self->object_get_attribute("$n2",'NAME');
-		my $inst = "$inst1-$inst2"; 
-		update_result ($self,$sample,"link_all_paths_result",'-',$inst,$L_num{$r});
-		$min_l_name= $inst if($nn==0);
-		$max_l_name= $inst if($nn==$siz-1);
-		$nn++;
-	}
-	
-			
-		
-	my $max_r_name= (defined $Rkeys[-1])? $self->object_get_attribute("$Rkeys[-1]",'NAME') : "-";
-	my $min_r_name= (defined $Rkeys[0]) ? $self->object_get_attribute("$Rkeys[0]",'NAME') : "-";	
-	
-	$max_r_name= "-" if (!defined $max_r_name); 
-	$min_r_name= "-" if (!defined $min_r_name); 	
-    
-		   
-	return ($max_r,$min_r,$max_l,$min_l,$std_l,$max_r_name,$min_r_name,$max_l_name,$min_l_name);	
-}	
-
+    my ($self)=@_;
+    my %R_num;
+    my %L_num;
+    my @all_endpoints=get_list_of_all_endpoints($self);
+    foreach  my $r  (@all_endpoints ){
+        #$R_num{$r} =0;
+    }
+    my @nodes=get_list_of_all_routers($self);
+    foreach my $p (@nodes){
+        $R_num{$p} =0;
+    }
+    foreach  my $src  (@all_endpoints ){
+        foreach  my $dst  (@all_endpoints ){
+            my $path = $self->object_get_attribute('Route',"${src}::$dst");
+            if (defined $path){
+                #router counting
+                my @p=@{$path};
+                shift @p; #remove source node from the path
+                pop @p; #remove the destination node from the path
+                foreach my $r (@p){
+                    $R_num{$r} ++;
+                }
+                #path counting
+                @p=     get_adjacent_router_in_a_path($path);
+                foreach my $r (@p){
+                    $L_num{$r} ++;
+                }
+            }
+        }
+    }
+    my @Rkeys = sort { $R_num{$a} <=> $R_num{$b} } keys(%R_num);
+    my @Lkeys = sort { $L_num{$a} <=> $L_num{$b} } keys(%L_num);
+    my $sample="sample0";
+    foreach  my $r  (@nodes ){
+        my $inst=$self->object_get_attribute("$r",'NAME');
+        update_result ($self,$sample,"router_all_paths_result",'-',$inst,$R_num{$r});
+    }
+    my $max_r = (defined $Rkeys[-1]) ? $R_num{$Rkeys[-1]} : 0;
+    my $min_r = (defined $Rkeys[ 0]) ? $R_num{$Rkeys[ 0]} : 0;
+    my $max_l = (defined $Lkeys[-1]) ? $L_num{$Lkeys[-1]} : 0;
+    my $min_l = (defined $Lkeys[ 0]) ? $L_num{$Lkeys[ 0]} : 0;
+    my @l = sort  values (%L_num);
+    my $std_l=stdev(\@l);
+    $self->object_add_attribute ($sample,"link_all_paths_result",undef);
+    my $nn=0;
+    my $min_l_name="-";
+    my $max_l_name="-";
+    my $siz = $#Lkeys;
+    foreach  my $r  (@Lkeys ){
+        my ($n1,$n2)=split(/::/,$r);
+        my $inst1=$self->object_get_attribute("$n1",'NAME');
+        my $inst2=$self->object_get_attribute("$n2",'NAME');
+        my $inst = "$inst1-$inst2";
+        update_result ($self,$sample,"link_all_paths_result",'-',$inst,$L_num{$r});
+        $min_l_name= $inst if($nn==0);
+        $max_l_name= $inst if($nn==$siz-1);
+        $nn++;
+    }
+    my $max_r_name= (defined $Rkeys[-1])? $self->object_get_attribute("$Rkeys[-1]",'NAME') : "-";
+    my $min_r_name= (defined $Rkeys[0]) ? $self->object_get_attribute("$Rkeys[0]",'NAME') : "-";
+    $max_r_name= "-" if (!defined $max_r_name);
+    $min_r_name= "-" if (!defined $min_r_name);
+    return ($max_r,$min_r,$max_l,$min_l,$std_l,$max_r_name,$min_r_name,$max_l_name,$min_l_name);
+}
 
 sub routing_summary{
-	my ($self,$info)= @_;		
-	
-	my $sc_win = gen_scr_win_with_adjst($self,'map_info');
-	#my $table= def_table(10,10,FALSE);
-	
-	
-	my $row=0;
-	my $col=0;
-	my ($max_r,$min_r,$max_l,$min_l,$std_l,$max_r_name,$min_r_name,$max_l_name,$min_l_name)=get_route_info($self);
-	
-	
-	my @data = (
-   {0 => "The Maximum number that a router is used in routing",  1 =>"$max_r", 2 =>"$max_r_name"}, # The maximum number that a router is located in all paths between all source-destination pair in this routing algorithm.
-   {0 => "The Minimum number that a router is used in routing",  1 =>"$min_r", 2 =>"$min_r_name" },  
-   {0 => "The Maximum number that a link is used in routing ",  1 =>"$max_l", 2 =>"$max_l_name"}, # The maximum number that a node-2-node link is located in all paths between all source-destination pair in this routing algorithm.
-   {0 => "The Minimum number that a link is used in routing",  1=>"$min_l", 2 =>"$min_l_name" },  
-   {0 => "Link usage  standard deviation ",  1 =>"$std_l" } 
-  );
-	
-	  
- 
-	my @clmn_type = ('Glib::String',  # => G_TYPE_STRING
-                                    'Glib::String',
-                                    'Glib::String'); # you get the idea
-
-	my @clmns = ("Routing Summary", " ", " ");
-
-	my $list=	gen_list_store (\@data,\@clmn_type,\@clmns);
-
-
-	add_widget_to_scrolled_win($list,$sc_win);
-	
-	my $charts =  gen_routing_charts($self,$info);
-	
-	my $v1=gen_vpaned($sc_win,.25,$charts);
-	
-	$sc_win->show_all;
-	
-	return $v1;	
-	
+    my ($self,$info)= @_;
+    my $sc_win = gen_scr_win_with_adjst($self,'map_info');
+    #my $table= def_table(10,10,FALSE);
+    my $row=0;
+    my $col=0;
+    my ($max_r,$min_r,$max_l,$min_l,$std_l,$max_r_name,$min_r_name,$max_l_name,$min_l_name)=get_route_info($self);
+    my @data = (
+    {0 => "The Maximum number that a router is used in routing",  1 =>"$max_r", 2 =>"$max_r_name"}, # The maximum number that a router is located in all paths between all source-destination pair in this routing algorithm.
+    {0 => "The Minimum number that a router is used in routing",  1 =>"$min_r", 2 =>"$min_r_name" },
+    {0 => "The Maximum number that a link is used in routing ",  1 =>"$max_l", 2 =>"$max_l_name"}, # The maximum number that a node-2-node link is located in all paths between all source-destination pair in this routing algorithm.
+    {0 => "The Minimum number that a link is used in routing",  1=>"$min_l", 2 =>"$min_l_name" },
+    {0 => "Link usage  standard deviation ",  1 =>"$std_l" }
+    );
+    my @clmn_type =  (
+        'Glib::String',  # => G_TYPE_STRING
+        'Glib::String',
+        'Glib::String'
+    ); # you get the idea
+    my @clmns = ("Routing Summary", " ", " ");
+    my $list=    gen_list_store (\@data,\@clmn_type,\@clmns);
+    add_widget_to_scrolled_win($list,$sc_win);
+    my $charts =  gen_routing_charts($self,$info);
+    my $v1=gen_vpaned($sc_win,.25,$charts);
+    $sc_win->show_all;
+    return $v1;
 }
 
-
 sub gen_routing_charts{
-	
-	my ($self,$info)=@_;
-	
-	my @pages =(
-	{page_name=>" # Routers in all Paths", page_num=>0},
-	{page_name=>" # Links in all Paths ", page_num=>1}	
-);
-
-
-
-my @charts = (
-	{ type=>"3D_bar", page_num=>0, graph_name=> "# Router in all Paths", result_name => "router_all_paths_result", X_Title=> 'Router Name', Y_Title=>'The total number that a router is used in the routing', Z_Title=>undef},
-	{ type=>"3D_bar", page_num=>1, graph_name=> "# Links in all paths", result_name => "link_all_paths_result", X_Title=> 'Connection Link', Y_Title=>'The total number that a link is used in the routing', Z_Title=>undef},
-  	#{ type=>"2D_line", page_num=>0, graph_name=> "SD latency", result_name => "sd_latency_result", X_Title=> 'Desired Avg. Injected Load Per Router (flits/clock (%))', Y_Title=>'Latency Standard Deviation (clock)', Z_Title=>undef},
-	#{ type=>"3D_bar",  page_num=>1, graph_name=> "Received", result_name => "packet_rsvd_result", X_Title=>'Core ID' , Y_Title=>'Received Packets Per Router', Z_Title=>undef},
-	#{ type=>"3D_bar",  page_num=>1, graph_name=> "Sent", result_name => "packet_sent_result", X_Title=>'Core ID' , Y_Title=>'Sent Packets Per Router', Z_Title=>undef},
-	
-	);
-	
-	
-	my $chart   =gen_multiple_charts  ($self,\@pages,\@charts,.3);
+    my ($self,$info)=@_;
+    my @pages =(
+    {page_name=>" # Routers in all Paths", page_num=>0},
+    {page_name=>" # Links in all Paths ", page_num=>1}
+    );
+    my @charts = (
+    { type=>"3D_bar", page_num=>0, graph_name=> "# Router in all Paths", result_name => "router_all_paths_result", X_Title=> 'Router Name', Y_Title=>'The total number that a router is used in the routing', Z_Title=>undef},
+    { type=>"3D_bar", page_num=>1, graph_name=> "# Links in all paths", result_name => "link_all_paths_result", X_Title=> 'Connection Link', Y_Title=>'The total number that a link is used in the routing', Z_Title=>undef},
+    #{ type=>"2D_line", page_num=>0, graph_name=> "SD latency", result_name => "sd_latency_result", X_Title=> 'Desired Avg. Injected Load Per Router (flits/clock (%))', Y_Title=>'Latency Standard Deviation (clock)', Z_Title=>undef},
+    #{ type=>"3D_bar",  page_num=>1, graph_name=> "Received", result_name => "packet_rsvd_result", X_Title=>'Core ID' , Y_Title=>'Received Packets Per Router', Z_Title=>undef},
+    #{ type=>"3D_bar",  page_num=>1, graph_name=> "Sent", result_name => "packet_sent_result", X_Title=>'Core ID' , Y_Title=>'Sent Packets Per Router', Z_Title=>undef},
+    );
+    my $chart   =gen_multiple_charts  ($self,\@pages,\@charts,.3);
     return $chart;
-	
 }
 
-
-
-
 sub show_paths_between_two_endps{
-	my ($self,$info)= @_;
-	my $table=def_table(20,20,FALSE);
-		
-	my $row-=0;
-	my $col=0;
-	
-	my $src = $self->object_get_attribute("SELECT_PATH","src");
-	my $dst = $self->object_get_attribute("SELECT_PATH","dst");
-	
-	my @acyclic_turns;
-	my $path_select= $self->object_get_attribute("routing_auto",'PATH_SELECT');
-	if ($path_select ne "all-paths"){
-		 my $ref = $self->object_get_attribute('routing_auto','acyclic_turns_model'); 
-		 if(defined $ref) {
-		 	@acyclic_turns = @{$ref};
-		 }else{
-		 	add_colored_info($info,"Info:No acyclic route model is selected\n",'green');
-		 		 	
-		 }	
-	}
-	
-	
-	
-	
-	
-	if(defined $src && defined $dst ){
-		my $s= $self->object_get_attribute("$src","NAME");
-		my $d= $self->object_get_attribute("$dst","NAME");		
-		$table->attach (def_label("Select path between $s to $d" ),$col,$col+10,$row,$row+1,'fill','shrink',2,2);
-		add_info($info,"get list of all paths between $s to $d \n") if (defined $info);
-		$row=1;
-		my ($ref1,$ref2)= ($path_select eq "all-paths") ?  get_all_paths_between_two_endps($self,$src, $dst):
-		get_all_paths_between_two_endps_using_accyclic_turn($self,$src, $dst,\@acyclic_turns);
-		
-		
-		my @paths = @{$ref1};
-		my @ports= @{$ref2};
-		my $n=0;
-		my $select = $self->object_get_attribute('Route',"${src}::$dst");
-		foreach my $p (@paths){
-			my $scal;
-			my $selp;
-			my $path_num=$n;
-			my $path=$p;
-			foreach my $q ( @{$p}){
-				my $inst=$self->object_get_attribute("$q",'NAME');
-				$scal= (defined $scal)? $scal."->$inst" : $inst;
-			}
-			
-			foreach my $q ( @{$select}){
-				my $inst=$self->object_get_attribute("$q",'NAME');
-				$selp= (defined $selp)? $selp."->$inst" : $inst;
-			}
-			
-				
-			my $check= gen_checkbutton();
-			#print "if($select eq $path)";
-			if(defined $select && defined $scal && defined $selp) {if($selp eq $scal) {$check->set_active(TRUE);}}
-			else {$check->set_active(FALSE);}
-			
-			$check-> signal_connect("toggled" => sub{
-				if($check->get_active()) {
-					 
-					$self->object_add_attribute('Route',"${src}::$dst",$path);
-				}
-				else {
-					 
-					$self->object_add_attribute('Route',"${src}::$dst",undef);
-				}
-				set_gui_status($self,"ref",1);
-			});
-			
-			
-			my $label =gen_label_in_left("$scal");
-			$table->attach ($check ,  $col, $col+1,$row,$row+1,'shrink','shrink',2,2); $col++;
-			$table->attach ($label ,  $col, $col+1,$row,$row+1,'shrink','shrink',2,2); $row++;$col=0;
-			
-			$n++;	
-		}
-		
-		
-	}
-	
-	return add_widget_to_scrolled_win($table);
-	
+    my ($self,$info)= @_;
+    my $table=def_table(20,20,FALSE);
+    my $row-=0;
+    my $col=0;
+    my $src = $self->object_get_attribute("SELECT_PATH","src");
+    my $dst = $self->object_get_attribute("SELECT_PATH","dst");
+    my @acyclic_turns;
+    my $path_select= $self->object_get_attribute("routing_auto",'PATH_SELECT');
+    if ($path_select ne "all-paths"){
+        my $ref = $self->object_get_attribute('routing_auto','acyclic_turns_model');
+        if(defined $ref) {
+            @acyclic_turns = @{$ref};
+        }else{
+            add_colored_info($info,"Info:No acyclic route model is selected\n",'green');
+        }
+    }
+    if(defined $src && defined $dst ){
+        my $s= $self->object_get_attribute("$src","NAME");
+        my $d= $self->object_get_attribute("$dst","NAME");
+        $table->attach (def_label("Select path between $s to $d" ),$col,$col+10,$row,$row+1,'fill','shrink',2,2);
+        add_info($info,"get list of all paths between $s to $d \n") if (defined $info);
+        $row=1;
+        my ($ref1,$ref2)= ($path_select eq "all-paths") ?  get_all_paths_between_two_endps($self,$src, $dst):
+        get_all_paths_between_two_endps_using_accyclic_turn($self,$src, $dst,\@acyclic_turns);
+        my @paths = @{$ref1};
+        my @ports= @{$ref2};
+        my $n=0;
+        my $select = $self->object_get_attribute('Route',"${src}::$dst");
+        foreach my $p (@paths){
+            my $scal;
+            my $selp;
+            my $path_num=$n;
+            my $path=$p;
+            foreach my $q ( @{$p}){
+                my $inst=$self->object_get_attribute("$q",'NAME');
+                $scal= (defined $scal)? $scal."->$inst" : $inst;
+            }
+            foreach my $q ( @{$select}){
+                my $inst=$self->object_get_attribute("$q",'NAME');
+                $selp= (defined $selp)? $selp."->$inst" : $inst;
+            }
+            my $check= gen_checkbutton();
+            #print "if($select eq $path)";
+            if(defined $select && defined $scal && defined $selp) {if($selp eq $scal) {$check->set_active(TRUE);}}
+            else {$check->set_active(FALSE);}
+            $check-> signal_connect("toggled" => sub{
+                if($check->get_active()) {
+                    $self->object_add_attribute('Route',"${src}::$dst",$path);
+                }
+                else {
+                    $self->object_add_attribute('Route',"${src}::$dst",undef);
+                }
+                set_gui_status($self,"ref",1);
+            });
+            my $label =gen_label_in_left("$scal");
+            $table->attach ($check ,  $col, $col+1,$row,$row+1,'shrink','shrink',2,2); $col++;
+            $table->attach ($label ,  $col, $col+1,$row,$row+1,'shrink','shrink',2,2); $row++;$col=0;
+            $n++;
+        }
+    }
+    return add_widget_to_scrolled_win($table);
 }
-
-
-
 ##########
-#	save
+#    save
 ##########
 sub save_network {
-	my ($self)=@_;
-	# read topology  name
-	my $name=$self->object_get_attribute('save_as');	
-	#print $name;
-	my $s= (!defined $name)? 0 : (length($name)==0)? 0 :1;	
-	if ($s == 0){
-		message_dialog("Please set the topology name!");
-		return 0;
-	}
-	# Write object file
-	my $fname = "$name.NWM";
-	open(FILE,  ">lib/netwmaker/$fname") || die "Can not open: $!";
-	print FILE perl_file_header("$fname");
-	print FILE Data::Dumper->Dump([\%$self],["nwmaker"]);
-	close(FILE) || die "Error closing file: $!";
-	message_dialog("Current network maker state is saved as lib/netwmaker/$fname!");
-	return 1;
+    my ($self)=@_;
+    # read topology  name
+    my $name=$self->object_get_attribute('save_as');
+    #print $name;
+    my $s= (!defined $name)? 0 : (length($name)==0)? 0 :1;
+    if ($s == 0){
+        message_dialog("Please set the topology name!");
+        return 0;
+    }
+    # Write object file
+    my $fname = "$name.NWM";
+    open(FILE,  ">lib/netwmaker/$fname") || die "Can not open: $!";
+    print FILE perl_file_header("$fname");
+    print FILE Data::Dumper->Dump([\%$self],["nwmaker"]);
+    close(FILE) || die "Error closing file: $!";
+    message_dialog("Current network maker state is saved as lib/netwmaker/$fname!");
+    return 1;
 }
 
 sub get_all_endp_ids{
-	my $self=shift;
-	my %e=  $self->object_get_attribute("E");
-	my @list = sort keys %e;
-	return @list;
-	
+    my $self=shift;
+    my %e=  $self->object_get_attribute("E");
+    my @list = sort keys %e;
+    return @list;
 }
-
-
-
 #############
 #    load
 #############
-
 sub load_net_maker{
     my ($self,$info)=@_;
     my $file;
-	my $dialog =  gen_file_dialog (undef, 'NWM');
-   
-    
+    my $dialog =  gen_file_dialog (undef, 'NWM');
     my $dir = Cwd::getcwd();
     $dialog->set_current_folder ("$dir/lib/netwmaker")    ;
-   
     if ( "ok" eq $dialog->run ) {
         $file = $dialog->get_filename;
         my ($name,$path,$suffix) = fileparse("$file",qr"\..[^.]*$");
         if($suffix eq '.NWM'){
             my ($pp,$r,$err) = regen_object($file );
-            if ($r){        
+            if ($r){
                 add_info($info,"**Error: cannot open $file file: $err\n");
-                 $dialog->destroy;
+                $dialog->destroy;
                 return;
-            } 
-            
-
+            }
             clone_obj($self,$pp);
-
-                    
-        }                    
-     }
-     $dialog->destroy;
-     set_gui_status($self,"ref",1)
+        }
+    }
+    $dialog->destroy;
+    set_gui_status($self,"ref",1)
 }
 
-
-
-
-
-
-
 sub get_all_paths_between_two_endps{
-	my ($self,$src, $dst)=@_;
-	my @proceed_nodes;
-	my @head_nodes;
-	
-	my $offset = $self->object_get_attribute('routing_auto','OFFSET');
-	my $max_len = $self->object_get_attribute('routing_auto','MAX_LENGTH');	
-	
-	push (@head_nodes,$src);
-	push (@proceed_nodes,$src);
-	
-	my @paths;
-	my @ports;
-	my @paths_to_dst;
-	my @ports_to_dst;
-	
-	my @first_path=($src);
-	my @first_port=(0);
-	$paths[0]=\@first_path;
-	$ports[0]=\@first_port;
-	
-	# select one path
-	my $n=0;
-	my $min_dist=1000000;
-	do{	
-		my @current_path= @{$paths[$n]};
-		my @current_port= @{$ports[$n]};
-		# get head node
-		my $head_node = 	$current_path[-1];
-		if(defined $head_node){
-			# get connected nodes for all ports 
-			#print "hn=$head_node\n";
-			my $pnum =  $self->object_get_attribute($head_node,'PNUM');
-			
-			for (my $i=0;$i<$pnum; $i++){
-				my @new_path=@current_path;
-				my @new_ports=@current_port;
-				my $src_port = "Port[${i}]";
-		   	   	my $connect = $self->{$head_node}{'PCONNECT'}{$src_port};	
-				if(defined $connect){
-					my ($node,$pnode)=split(/\s*,\s*/,$connect);
-					#add connected nodes to head_nodes if they are not in path before
-					if(!defined get_scolar_pos($node,@new_path)){
-						my $size=scalar @new_path;
-						#if ($min_dist > $size){
-						if( ($min_dist+$offset) > $size &&   $max_len>=$size){
-							
-							
-							push (@new_path,$node);
-							push (@new_ports,$pnode);
-							push (@paths,\@new_path);
-							push (@ports,\@new_ports);						 
-							if($node eq $dst){
-								push(@paths_to_dst,\@new_path);
-								push(@ports_to_dst,\@new_ports); 
-								$min_dist=$size+1 if ($min_dist > $size);
-							} 
-						}
-					} #if
-				}
-			}#for
-		}	
-		$n++;
-	}while( defined $paths[$n]);
-	
-	#print "\@paths_to_dst". Dumper(@paths_to_dst). "\n \@ports_to_dst". Dumper(@ports_to_dst) . "\n" ;
-	
-	return (\@paths_to_dst,\@ports_to_dst);
-
+    my ($self,$src, $dst)=@_;
+    my @proceed_nodes;
+    my @head_nodes;
+    my $offset = $self->object_get_attribute('routing_auto','OFFSET');
+    my $max_len = $self->object_get_attribute('routing_auto','MAX_LENGTH');
+    push (@head_nodes,$src);
+    push (@proceed_nodes,$src);
+    my @paths;
+    my @ports;
+    my @paths_to_dst;
+    my @ports_to_dst;
+    my @first_path=($src);
+    my @first_port=(0);
+    $paths[0]=\@first_path;
+    $ports[0]=\@first_port;
+    # select one path
+    my $n=0;
+    my $min_dist=1000000;
+    do{
+        my @current_path= @{$paths[$n]};
+        my @current_port= @{$ports[$n]};
+        # get head node
+        my $head_node =     $current_path[-1];
+        if(defined $head_node){
+            # get connected nodes for all ports
+            #print "hn=$head_node\n";
+            my $pnum =  $self->object_get_attribute($head_node,'PNUM');
+            for (my $i=0;$i<$pnum; $i++){
+                my @new_path=@current_path;
+                my @new_ports=@current_port;
+                my $src_port = "Port[${i}]";
+                    my $connect = $self->{$head_node}{'PCONNECT'}{$src_port};
+                if(defined $connect){
+                    my ($node,$pnode)=split(/\s*,\s*/,$connect);
+                    #add connected nodes to head_nodes if they are not in path before
+                    if(!defined get_scolar_pos($node,@new_path)){
+                        my $size=scalar @new_path;
+                        #if ($min_dist > $size){
+                        if( ($min_dist+$offset) > $size &&   $max_len>=$size){
+                            push (@new_path,$node);
+                            push (@new_ports,$pnode);
+                            push (@paths,\@new_path);
+                            push (@ports,\@new_ports);
+                            if($node eq $dst){
+                                push(@paths_to_dst,\@new_path);
+                                push(@ports_to_dst,\@new_ports);
+                                $min_dist=$size+1 if ($min_dist > $size);
+                            }
+                        }
+                    } #if
+                }
+            }#for
+        }
+        $n++;
+    }while( defined $paths[$n]);
+    #print "\@paths_to_dst". Dumper(@paths_to_dst). "\n \@ports_to_dst". Dumper(@ports_to_dst) . "\n" ;
+    return (\@paths_to_dst,\@ports_to_dst);
 }
 
 sub get_path_from_turns {
-	my ($self,$ref)=@_;
-	my @new_turn = @{$ref} if(defined $ref);
-	my @path_nodes;
-	my @path_ports;
-	my $st2;
-	foreach my $code (@new_turn){
-		my $pn2  =  $code & 0xF;
-		$code >>=4;
-		my $rn2  = $code & 0xFFF;
-		$code >>=12;
-		my $pn1 =$code & 0xF;
-		$code >>=4;
-		my $rn1=$code;	
-		my $st1 = ($pn1==1)? "ENDP_${rn1}" : "ROUTER${pn1}_${rn1}";
-		$st2 = ($pn2==1)? "ENDP_${rn2}"    : "ROUTER${pn2}_${rn2}";
-		push(@path_nodes,$st1);		
-	}
-	push(@path_nodes,$st2);	
-	
-	@path_ports=(0);
-	for (my $i=0; $i<scalar @path_nodes-1; $i++){
-		my ($p1,$p2) =get_connection_port_num_between_two_nodes($self,$path_nodes[$i],$path_nodes[$i+1]);
-		push(@path_ports,"Port[$p2]");
-	}
-	
-	return (\@path_nodes,\@path_ports);
-		
+    my ($self,$ref)=@_;
+    my @new_turn = @{$ref} if(defined $ref);
+    my @path_nodes;
+    my @path_ports;
+    my $st2;
+    foreach my $code (@new_turn){
+        my $pn2  =  $code & 0xF;
+        $code >>=4;
+        my $rn2  = $code & 0xFFF;
+        $code >>=12;
+        my $pn1 =$code & 0xF;
+        $code >>=4;
+        my $rn1=$code;
+        my $st1 = ($pn1==1)? "ENDP_${rn1}" : "ROUTER${pn1}_${rn1}";
+        $st2 = ($pn2==1)? "ENDP_${rn2}"    : "ROUTER${pn2}_${rn2}";
+        push(@path_nodes,$st1);
+    }
+    push(@path_nodes,$st2);
+    @path_ports=(0);
+    for (my $i=0; $i<scalar @path_nodes-1; $i++){
+        my ($p1,$p2) =get_connection_port_num_between_two_nodes($self,$path_nodes[$i],$path_nodes[$i+1]);
+        push(@path_ports,"Port[$p2]");
+    }
+    return (\@path_nodes,\@path_ports);
 }
 
 sub get_all_paths_between_two_endps_using_accyclic_turn{
-	my ($self,$src, $dst,$ref)=@_;
-	my @proceed_turns;
-	my @head_turns;
-	my @accyclic_turn= @{$ref};
-	
-	my $offset = $self->object_get_attribute('routing_auto','OFFSET');
-	my $max_len = $self->object_get_attribute('routing_auto','MAX_LENGTH');	
-	
-	my @paths_to_dst;
-	my @ports_to_dst;
-	
-	my %graph;
-	
-	foreach my $str (@accyclic_turn){
-		my ($s1,$s2) = split /\s/, $str;
-		push(@{$graph{$s1}},$s2);			
-	}	
-
-	my $start_turns;
-	my $ended_turns;
-	my $src_port = "Port[0]";
-	my $connect = $self->{$src}{'PCONNECT'}{$src_port};	
-	if(defined $connect){
-		my ($node,$pnode)=split(/\s*,\s*/,$connect);
-		$start_turns = 	get_turn_code("${src}::${node}");
-	}
-	
-	$connect = $self->{$dst}{'PCONNECT'}{$src_port};	
-	if(defined $connect){
-		my ($node,$pnode)=split(/\s*,\s*/,$connect);
-		$ended_turns = 	get_turn_code("${node}::${dst}");
-	}
-	
-	push (@head_turns,$start_turns);
+    my ($self,$src, $dst,$ref)=@_;
+    my @proceed_turns;
+    my @head_turns;
+    my @accyclic_turn= @{$ref};
+    my $offset = $self->object_get_attribute('routing_auto','OFFSET');
+    my $max_len = $self->object_get_attribute('routing_auto','MAX_LENGTH');
+    my @paths_to_dst;
+    my @ports_to_dst;
+    my %graph;
+    foreach my $str (@accyclic_turn){
+        my ($s1,$s2) = split /\s/, $str;
+        push(@{$graph{$s1}},$s2);
+    }
+    my $start_turns;
+    my $ended_turns;
+    my $src_port = "Port[0]";
+    my $connect = $self->{$src}{'PCONNECT'}{$src_port};
+    if(defined $connect){
+        my ($node,$pnode)=split(/\s*,\s*/,$connect);
+        $start_turns =     get_turn_code("${src}::${node}");
+    }
+    $connect = $self->{$dst}{'PCONNECT'}{$src_port};
+    if(defined $connect){
+        my ($node,$pnode)=split(/\s*,\s*/,$connect);
+        $ended_turns =     get_turn_code("${node}::${dst}");
+    }
+    push (@head_turns,$start_turns);
     push (@proceed_turns,$start_turns);
-
-	
-	
-	
-	
-	my @turns;
-	my @ports;
-	my @turns_to_dst;
-	my @first_turn=($start_turns);
-	
-	$turns[0]=\@first_turn;
-	
-	
-	# select one path
-	my $n=0;
-	my $min_dist=1000000;
-	do{	
-		my @current_turn= @{$turns[$n]};
-		# get head node
-		my $head_turn = 	$current_turn[-1];
-		if(defined $head_turn){
-			#get all turns 
-			my @all_fwd_turns = @{$graph{$head_turn}} if (defined $graph{$head_turn});	
-					
-			foreach my $fwd_turn (@all_fwd_turns){
-				my @new_turn=@current_turn;
-				#add new turn to head_turns if they are not in turns before
-				if(!defined get_scolar_pos($fwd_turn,@new_turn)){	
-					my $size=scalar @new_turn;	
-					#if ($min_dist > $size){
-					if( ($min_dist+$offset) > $size &&   $max_len>=$size){
-						push (@new_turn,$fwd_turn);
-						push (@turns,\@new_turn);
-						if($fwd_turn eq $ended_turns){
-							push(@turns_to_dst,\@new_turn);	
-							my ($path_ref,$port_ref) = get_path_from_turns($self,\@new_turn); 				
-							push(@paths_to_dst,$path_ref);
-							push(@ports_to_dst,$port_ref);
-							$min_dist=$size+1 if ($min_dist > $size);
-						} #if
-						
-					}#if
-				}#if
-			}#foreach
-		}#if
-	$n++;
-	}while( defined $turns[$n]);			
-					
-		
-					
-	#print "\@paths_to_dst". Dumper(@paths_to_dst). "\n \@ports_to_dst". Dumper(@ports_to_dst) . "\n" ;
-	
-	
-	return (\@paths_to_dst,\@ports_to_dst);
-	
+    my @turns;
+    my @ports;
+    my @turns_to_dst;
+    my @first_turn=($start_turns);
+    $turns[0]=\@first_turn;
+    # select one path
+    my $n=0;
+    my $min_dist=1000000;
+    do{
+        my @current_turn= @{$turns[$n]};
+        # get head node
+        my $head_turn =     $current_turn[-1];
+        if(defined $head_turn){
+            #get all turns
+            my @all_fwd_turns = @{$graph{$head_turn}} if (defined $graph{$head_turn});
+            foreach my $fwd_turn (@all_fwd_turns){
+                my @new_turn=@current_turn;
+                #add new turn to head_turns if they are not in turns before
+                if(!defined get_scolar_pos($fwd_turn,@new_turn)){
+                    my $size=scalar @new_turn;
+                    #if ($min_dist > $size){
+                    if( ($min_dist+$offset) > $size &&   $max_len>=$size){
+                        push (@new_turn,$fwd_turn);
+                        push (@turns,\@new_turn);
+                        if($fwd_turn eq $ended_turns){
+                            push(@turns_to_dst,\@new_turn);
+                            my ($path_ref,$port_ref) = get_path_from_turns($self,\@new_turn);
+                            push(@paths_to_dst,$path_ref);
+                            push(@ports_to_dst,$port_ref);
+                            $min_dist=$size+1 if ($min_dist > $size);
+                        } #if
+                    }#if
+                }#if
+            }#foreach
+        }#if
+    $n++;
+    }while( defined $turns[$n]);
+    #print "\@paths_to_dst". Dumper(@paths_to_dst). "\n \@ports_to_dst". Dumper(@ports_to_dst) . "\n" ;
+    return (\@paths_to_dst,\@ports_to_dst);
 }
 
-
-
-
 sub get_turn_code {
-	my $turn =shift;
-	my ($pn1,$rn1,$pn2,$rn2)= sscanf( "ROUTER%u_%u::ROUTER%u_%u",$turn);
-	if(defined $rn1){
-		return ( ($rn1 << 20)+ ($pn1 << 16) +  ($rn2 << 4) +  $pn2);
-	}
-	($rn1,$pn2,$rn2)= sscanf( "ENDP_%u::ROUTER%u_%u",$turn);
-	if(defined $rn1){
-		return ( ($rn1 << 20)+ (1 << 16) +  ($rn2 << 4) +  $pn2);
-	}	
-	($pn1,$rn1,$rn2)= sscanf( "ROUTER%u_%u::ENDP_%u",$turn);
-	return ( ($rn1 << 20)+ ($pn1 << 16) +  ($rn2 << 4) +  1);
+    my $turn =shift;
+    my ($pn1,$rn1,$pn2,$rn2)= sscanf( "ROUTER%u_%u::ROUTER%u_%u",$turn);
+    if(defined $rn1){
+        return ( ($rn1 << 20)+ ($pn1 << 16) +  ($rn2 << 4) +  $pn2);
+    }
+    ($rn1,$pn2,$rn2)= sscanf( "ENDP_%u::ROUTER%u_%u",$turn);
+    if(defined $rn1){
+        return ( ($rn1 << 20)+ (1 << 16) +  ($rn2 << 4) +  $pn2);
+    }
+    ($pn1,$rn1,$rn2)= sscanf( "ROUTER%u_%u::ENDP_%u",$turn);
+    return ( ($rn1 << 20)+ ($pn1 << 16) +  ($rn2 << 4) +  1);
 }
 
 sub get_turn_str {
-	my $code =shift;
-	my $pn2  =  $code & 0xF;
-	$code >>=4;
-	my $rn2  = $code & 0xFFF;
-	$code >>=12;
-	my $pn1 =$code & 0xF;
-	$code >>=4;
-	my $rn1=$code;	
-	my $st1 = ($pn1==1)? "ENDP_${rn1}" : "ROUTER${pn1}_${rn1}";
-	my $st2 = ($pn2==1)? "ENDP_${rn2}" : "ROUTER${pn2}_${rn2}";
-	
-	return   "${st1}::${st2}";
+    my $code =shift;
+    my $pn2  =  $code & 0xF;
+    $code >>=4;
+    my $rn2  = $code & 0xFFF;
+    $code >>=12;
+    my $pn1 =$code & 0xF;
+    $code >>=4;
+    my $rn1=$code;
+    my $st1 = ($pn1==1)? "ENDP_${rn1}" : "ROUTER${pn1}_${rn1}";
+    my $st2 = ($pn2==1)? "ENDP_${rn2}" : "ROUTER${pn2}_${rn2}";
+    return   "${st1}::${st2}";
 }
 
 sub get_turn_involved_routrs{
-	my ($s1,$s2,$info)=@_;
-	my ($r1,$ra2) = split /::/, $s1;
-	my ($rb2,$r3) = split /::/, $s2;
-	add_colored_info($info,"Error in turn format. $s1 -> $s2 : $ra2 should be equal with $rb2 ",'red') if($ra2 ne $rb2);
-	return ($r1,$ra2,$r3);	
+    my ($s1,$s2,$info)=@_;
+    my ($r1,$ra2) = split /::/, $s1;
+    my ($rb2,$r3) = split /::/, $s2;
+    add_colored_info($info,"Error in turn format. $s1 -> $s2 : $ra2 should be equal with $rb2 ",'red') if($ra2 ne $rb2);
+    return ($r1,$ra2,$r3);
 }
 
 sub get_path_edges_graph_file{
-	my ($ref1,$ref2) = @_;	
-	my @a_nodes = @{$ref1};
-	my %graph   = %{$ref2};
-	
-	my $old_r;	
-	foreach my $r (@a_nodes){
-		
-		if(defined $old_r){
-			my $str1 = "$old_r $r";
-			my $n1  = get_turn_code($old_r);
-			my $n2  = get_turn_code($r); 
-			my $str2 = "$n1 $n2";
-			$graph{$str2}=$str1;			
-		}
-		$old_r=$r;
-	}
-	return %graph;
-}	
-
-
-
+    my ($ref1,$ref2) = @_;
+    my @a_nodes = @{$ref1};
+    my %graph   = %{$ref2};
+    my $old_r;
+    foreach my $r (@a_nodes){
+        if(defined $old_r){
+            my $str1 = "$old_r $r";
+            my $n1  = get_turn_code($old_r);
+            my $n2  = get_turn_code($r);
+            my $str2 = "$n1 $n2";
+            $graph{$str2}=$str1;
+        }
+        $old_r=$r;
+    }
+    return %graph;
+}
 
 sub get_forbiden_turns_old {
-#sub gen_aciclic_turn_graph {	
-	my ($self,$info)=@_;
-	my @forbiden_turn;
-	add_info($info,"Calculate forbidden turns to avoid deadlock \n");
-	#step 1: get the list of all  minimal paths between all source and destination pairs
-	my $graph='';
-	my $graph_coded='';
-	my @all_endpoints=get_list_of_all_endpoints($self);
-	
-	my %edge_graph;
-	foreach  my $src  (@all_endpoints ){	
-		foreach  my $dst  (@all_endpoints ){
-			if($src ne $dst){	
-				my ($paths_to_dst,$ports_to_dst) = get_all_paths_between_two_endps($self,$src, $dst);
-				foreach my $path (@{$paths_to_dst}) {
-					if (defined $path){
-						#path counting
-						my @a_nodes= 	get_adjacent_node_in_a_path($path);#get_adjacent_router_in_a_path($path);
-						print "@a_nodes = \@a_nodes \n";
-						%edge_graph = get_path_edges_graph_file (\@a_nodes,\%edge_graph);
-						#$graph  =$graph. $str1;
-						#$graph_coded = $graph_coded . $str2;
-					}#defined path	
-				}#foreach	
-			}#if			
-		}#froeach				
-			
-	}#froeach	
-	
-	foreach my $p (sort keys %edge_graph){
-		$graph_coded  .="$p\n";
-		$graph .= "$edge_graph{$p}\n";
-	}
-			
-	my $tmp_dir  = "$ENV{'PRONOC_WORK'}/tmp";
-	save_file ("$tmp_dir/paths_graph.edges",$graph);
-	save_file ("$tmp_dir/paths_graph_coded.edges",$graph_coded);
-	
-	
-	#remove old files 
-	my @files = File::Find::Rule->file()
+#sub gen_aciclic_turn_graph {
+    my ($self,$info)=@_;
+    my @forbiden_turn;
+    add_info($info,"Calculate forbidden turns to avoid deadlock \n");
+    #step 1: get the list of all  minimal paths between all source and destination pairs
+    my $graph='';
+    my $graph_coded='';
+    my @all_endpoints=get_list_of_all_endpoints($self);
+    my %edge_graph;
+    foreach  my $src  (@all_endpoints ){
+        foreach  my $dst  (@all_endpoints ){
+            if($src ne $dst){
+                my ($paths_to_dst,$ports_to_dst) = get_all_paths_between_two_endps($self,$src, $dst);
+                foreach my $path (@{$paths_to_dst}) {
+                    if (defined $path){
+                        #path counting
+                        my @a_nodes=     get_adjacent_node_in_a_path($path);#get_adjacent_router_in_a_path($path);
+                        #print "@a_nodes = \@a_nodes \n";
+                        %edge_graph = get_path_edges_graph_file (\@a_nodes,\%edge_graph);
+                        #$graph  =$graph. $str1;
+                        #$graph_coded = $graph_coded . $str2;
+                    }#defined path
+                }#foreach
+            }#if
+        }#froeach
+    }#froeach
+    foreach my $p (sort keys %edge_graph){
+        $graph_coded  .="$p\n";
+        $graph .= "$edge_graph{$p}\n";
+    }
+    my $tmp_dir  = "$ENV{'PRONOC_WORK'}/tmp";
+    save_file ("$tmp_dir/paths_graph.edges",$graph);
+    save_file ("$tmp_dir/paths_graph_coded.edges",$graph_coded);
+    #remove old files
+    my @files = File::Find::Rule->file()
                             ->name( 'paths_graph_coded_removed*.edges')
-                            ->in( "$tmp_dir" );	
-	foreach my $f (@files){
-		unlink  $f if (-f "$f");		
-	}			
-	
-	# run remove_cycle_edges_by_dfs on coded graph 
-	my $remover_dire = get_project_dir()."/mpsoc/remove_cycle/";
-	my $cmd  =  "cd $remover_dire; 
-	python  break_cycles.py  -g $tmp_dir/paths_graph_coded.edges;
-	python remove_cycle_edges_by_dfs.py -g $tmp_dir/paths_graph_coded.edges; 
-	python remove_cycle_edges_by_minimum_feedback_arc_set_greedy.py  -g $tmp_dir/paths_graph_coded.edges";	
-	#sort paths_graph_coded.edges | uniq > newfile.db
-	
-	my ($stdout,$exit,$stderr)=run_cmd_in_back_ground_get_stdout($cmd);
-	if(length $stderr>1){			
-		add_colored_info($info,"$stderr\n",'red');
-	}else {
-		add_info($info,"$stdout\n");
-	}	
-	# find the files with the list edges removal
-	@files = File::Find::Rule->file()
-                         ->name( 'paths_graph_coded_removed*.edges')
-                         ->in( "$tmp_dir" );	
-	
-	                       
-	my $line_num;
-	my $out;
-	foreach my $f (@files){
-		my $n =count_file_line_num ($f);
-		$line_num = $n if(! defined $line_num);
-		if($n <= $line_num){
-			$out = $f;
-			$line_num=$n; 
-		}		
-	}			
-		
-			
-	# check if the output file is generated 
-	if (-f $out ){
-		add_colored_info($info,"$out file has been selected as it has the minimum number of edge removal of $line_num \n",'blue');
-		
-	} else {
-		add_colored_info($info,"could not find a paths_graph_coded_removed*.edges file.  Please make sure $cmd has been run successfully\n",'red');
-		return;
-		
-	}
-	
-	
-	
-	
-	my $r;
-	open my $fh, "<", $out or $r = "$!\n";
+                            ->in( "$tmp_dir" );
+    foreach my $f (@files){
+        unlink  $f if (-f "$f");
+    }
+    # run remove_cycle_edges_by_dfs on coded graph
+    my $remover_dire = get_project_dir()."/mpsoc/remove_cycle/";
+    my $cmd  =  "cd $remover_dire;
+    python  break_cycles.py  -g $tmp_dir/paths_graph_coded.edges;
+    python remove_cycle_edges_by_dfs.py -g $tmp_dir/paths_graph_coded.edges;
+    python remove_cycle_edges_by_minimum_feedback_arc_set_greedy.py  -g $tmp_dir/paths_graph_coded.edges";
+    #sort paths_graph_coded.edges | uniq > newfile.db
+    my ($stdout,$exit,$stderr)=run_cmd_in_back_ground_get_stdout($cmd);
+    if(length $stderr>1){
+        add_colored_info($info,"$stderr\n",'red');
+    }else {
+        add_info($info,"$stdout\n");
+    }
+    # find the files with the list edges removal
+    @files = File::Find::Rule->file()
+        ->name( 'paths_graph_coded_removed*.edges')
+        ->in( "$tmp_dir" );
+    my $line_num;
+    my $out;
+    foreach my $f (@files){
+        my $n =count_file_line_num ($f);
+        $line_num = $n if(! defined $line_num);
+        if($n <= $line_num){
+            $out = $f;
+            $line_num=$n;
+        }
+    }
+    # check if the output file is generated
+    if (-f $out ){
+        add_colored_info($info,"$out file has been selected as it has the minimum number of edge removal of $line_num \n",'blue');
+    } else {
+        add_colored_info($info,"could not find a paths_graph_coded_removed*.edges file.  Please make sure $cmd has been run successfully\n",'red');
+        return;
+    }
+    my $r;
+    open my $fh, "<", $out or $r = "$!\n";
     if(defined $r) {
-    	add_colored_info($info,"Could not open $out: $r",'red');
-		return;
-    } 
-    
+        add_colored_info($info,"Could not open $out: $r",'red');
+        return;
+    }
     add_colored_info($info,"List of forbidden turns: \n",'blue');
-    
-	while (my $line = <$fh>) {
-    	chomp $line;
-    	$line=~ s/^\s+|\s+$//g; 
-    	my ($s1,$s2) = split /\s/, $line;
-        $s1  = get_turn_str($s1);  
-  		$s2  = get_turn_str($s2);
-  		my @turn = get_turn_involved_routrs($s1,$s2);
-  		my $str = get_path_instance_string($self,\@turn);
-  		my $string=join('->',@turn);
-  		push (@forbiden_turn, $string);
-  		add_info($info,"$str\n");  
-
-  }
-  return @forbiden_turn;
-  
+    while (my $line = <$fh>) {
+        chomp $line;
+        $line=~ s/^\s+|\s+$//g;
+        my ($s1,$s2) = split /\s/, $line;
+        $s1  = get_turn_str($s1);
+        $s2  = get_turn_str($s2);
+        my @turn = get_turn_involved_routrs($s1,$s2);
+        my $str = get_path_instance_string($self,\@turn);
+        my $string=join('->',@turn);
+        push (@forbiden_turn, $string);
+        add_info($info,"$str\n");
+    }
+    return @forbiden_turn;
 }
 
-
 sub gen_turn_graph{
-	my $self=shift;
-	my %edge_graph;
-	my @all_nodes=get_list_of_all_nodes($self);
-	foreach  my $node1  (@all_nodes ){	
-		my $pnum1=$self->object_get_attribute("$node1",'PNUM');
-		for (my $i=0;$i<$pnum1; $i++){ 
-   	   		my $port1 = "Port[${i}]";
-   	   		my $connect1 = $self->{$node1}{'PCONNECT'}{$port1};
-			if (defined $connect1) {
-				my ($node2,$Rport2)=split(/\s*,\s*/,$connect1);
-				my $pnum2=$self->object_get_attribute("$node2",'PNUM');
-				for (my $j=0;$j<$pnum2; $j++){ 
-					my $port2 = "Port[${j}]";
-					my $connect2 = $self->{$node2}{'PCONNECT'}{$port2};
-					if (defined $connect2) {
-						my ($node3,$Rport3)=split(/\s*,\s*/,$connect2);
-						if($node1 ne $node3){
-							my @a_nodes= 	("${node1}::${node2}","${node2}::${node3}");
-							%edge_graph = get_path_edges_graph_file (\@a_nodes,\%edge_graph);
-						}
-					
-					}#if	
-				}#for		
-			}#if
-		}#for	 
-	}	
-	return %edge_graph;
+    my $self=shift;
+    my %edge_graph;
+    my @all_nodes=get_list_of_all_nodes($self);
+    foreach  my $node1  (@all_nodes ){
+        my $pnum1=$self->object_get_attribute("$node1",'PNUM');
+        for (my $i=0;$i<$pnum1; $i++){
+            my $port1 = "Port[${i}]";
+            my $connect1 = $self->{$node1}{'PCONNECT'}{$port1};
+            if (defined $connect1) {
+                my ($node2,$Rport2)=split(/\s*,\s*/,$connect1);
+                my $pnum2=$self->object_get_attribute("$node2",'PNUM');
+                for (my $j=0;$j<$pnum2; $j++){
+                    my $port2 = "Port[${j}]";
+                    my $connect2 = $self->{$node2}{'PCONNECT'}{$port2};
+                    if (defined $connect2) {
+                        my ($node3,$Rport3)=split(/\s*,\s*/,$connect2);
+                        if($node1 ne $node3){
+                            my @a_nodes=     ("${node1}::${node2}","${node2}::${node3}");
+                            %edge_graph = get_path_edges_graph_file (\@a_nodes,\%edge_graph);
+                        }
+                    }#if
+                }#for
+            }#if
+        }#for
+    }
+    return %edge_graph;
 }
 
 sub gen_aciclic_turn_graph {
-	
-	my ($self,$info)=@_;
-	
-	#my @forbiden_turn;
-	
-	add_info($info,"Generate an acyclic turn graph to avoid deadlock \n");
-	#step 1: get the list of turn in topology. A turn is a path that include three nodes.
-	my $graph='';
-	my $graph_coded='';
-	
-	my %edge_graph =gen_turn_graph($self);
-	
-		
-	foreach my $p (sort keys %edge_graph){
-		$graph_coded  .="$p\n";
-		$graph .= "$edge_graph{$p}\n";
-	}
-			
-	my $tmp_dir  = "$ENV{'PRONOC_WORK'}/tmp";
-	save_file ("$tmp_dir/paths_graph.edges",$graph);
-	save_file ("$tmp_dir/paths_graph_coded.edges",$graph_coded);
-	
-	
-	#remove old files 
-	my @files = File::Find::Rule->file()
-                            ->name( 'paths_graph_coded_removed*.edges')
-                            ->in( "$tmp_dir" );	
-	foreach my $f (@files){
-		unlink  $f if (-f "$f");		
-	}			
-	
-	# run remove_cycle_edges_by_dfs on coded graph 
-	my $remover_dire = get_project_dir()."/mpsoc/remove_cycle/";
-	my $cmd  =  "cd $remover_dire; 
-	python  break_cycles.py  -g $tmp_dir/paths_graph_coded.edges;
-	python remove_cycle_edges_by_dfs.py -g $tmp_dir/paths_graph_coded.edges; 
-	python remove_cycle_edges_by_minimum_feedback_arc_set_greedy.py  -g $tmp_dir/paths_graph_coded.edges";	
-	#sort paths_graph_coded.edges | uniq > newfile.db
-	
-	my ($stdout,$exit,$stderr)=run_cmd_in_back_ground_get_stdout($cmd);
-	if(length $stderr>1){			
-		add_colored_info($info,"$stderr\n",'red');
-	}else {
-		add_info($info,"$stdout\n");
-	}	
-	# find the files with the list edges removal
-	@files = File::Find::Rule->file()
-                         ->name( 'paths_graph_coded_removed*.edges')
-                         ->in( "$tmp_dir" );		                       
-	my $line_num;
-	my $out;
-	my %all_outs;
-	foreach my $f (@files){
-		
-		my $n =count_file_line_num ($f);
-		$all_outs{$f}=$n;
-		
-	}			
-	
-	my @graph_array=sort keys %edge_graph;
-	my @acyclic_turns;
-	my @removed_edge;
-	my $result=0;
-	
-	my %algorithms;
-	
-	foreach my $file  (sort {$all_outs{$a} <=> $all_outs{$b}} keys %all_outs) {
-		$line_num = $all_outs{$file};
-		$out=$file;
-		add_info($info,"check if $file file $line_num edges removal results in a connected graph\n");
-		
-		@removed_edge=();			
-		open(FILE,$file);
-		if (tell FILE ){
-			add_colored_info($info,"Cannot open $file to read: $!\n",'red');
-			return;
-		}
-    	while (my $line = <FILE>) {
-    		chomp($line);
-    	   	$line=~ s/^\s+|\s+$//g; 
-	   		push(@removed_edge,$line);
-		}
-    	close FILE;
-		
-		@acyclic_turns = get_diff_array ( \@graph_array , \@removed_edge );
-		
-		
-				
-		$result = check_diff_graph_be_connected ($self,\@acyclic_turns,$info);
-		if($result == 1){			
-			my $alg = capture_string_between ('paths_graph_coded_removed_by_',$file,".edges");
-			$algorithms{$alg}=$line_num;
-			#save @acyclic_turns for this algorithm
-			open(F,  ">$tmp_dir/$alg.alg") || die "Can not creat: $!";
-    		print F perl_file_header("$alg.alg");
-    		print F Data::Dumper->Dump([\@acyclic_turns],['turn']);
-    		close(F ) || die "Error closing file: $!";			
-		}
-			
-		 
-	}
-
-	$self->object_add_attribute('routing_auto','acyclic_algorithms',\%algorithms);
-	
-
+    my ($self,$info)=@_;
+    #my @forbiden_turn;
+    add_info($info,"Generate an acyclic turn graph to avoid deadlock \n");
+    #step 1: get the list of turn in topology. A turn is a path that include three nodes.
+    my $graph='';
+    my $graph_coded='';
+    my %edge_graph =gen_turn_graph($self);
+    foreach my $p (sort keys %edge_graph){
+        $graph_coded  .="$p\n";
+        $graph .= "$edge_graph{$p}\n";
+    }
+    my $tmp_dir  = "$ENV{'PRONOC_WORK'}/tmp";
+    save_file ("$tmp_dir/paths_graph.edges",$graph);
+    save_file ("$tmp_dir/paths_graph_coded.edges",$graph_coded);
+    #remove old files
+    my @files = File::Find::Rule->file()
+        ->name( 'paths_graph_coded_removed*.edges')
+        ->in( "$tmp_dir" );
+    foreach my $f (@files){
+        unlink  $f if (-f "$f");
+    }
+    # run remove_cycle_edges_by_dfs on coded graph
+    my $remover_dire = get_project_dir()."/mpsoc/remove_cycle/";
+    my $cmd  =  "cd $remover_dire;
+    python  break_cycles.py  -g $tmp_dir/paths_graph_coded.edges;
+    python remove_cycle_edges_by_dfs.py -g $tmp_dir/paths_graph_coded.edges;
+    python remove_cycle_edges_by_minimum_feedback_arc_set_greedy.py  -g $tmp_dir/paths_graph_coded.edges";
+    #sort paths_graph_coded.edges | uniq > newfile.db
+    my ($stdout,$exit,$stderr)=run_cmd_in_back_ground_get_stdout($cmd);
+    if(length $stderr>1){
+        add_colored_info($info,"$stderr\n",'red');
+    }else {
+        add_info($info,"$stdout\n");
+    }
+    # find the files with the list edges removal
+    @files = File::Find::Rule->file()
+        ->name( 'paths_graph_coded_removed*.edges')
+        ->in( "$tmp_dir" );
+    my $line_num;
+    my $out;
+    my %all_outs;
+    foreach my $f (@files){
+        my $n =count_file_line_num ($f);
+        $all_outs{$f}=$n;
+    }
+    my @graph_array=sort keys %edge_graph;
+    my @acyclic_turns;
+    my @removed_edge;
+    my $result=0;
+    my %algorithms;
+    foreach my $file  (sort {$all_outs{$a} <=> $all_outs{$b}} keys %all_outs) {
+        $line_num = $all_outs{$file};
+        $out=$file;
+        add_info($info,"check if $file file $line_num edges removal results in a connected graph\n");
+        @removed_edge=();
+        open(FILE,$file);
+        if (tell FILE ){
+            add_colored_info($info,"Cannot open $file to read: $!\n",'red');
+            return;
+        }
+        while (my $line = <FILE>) {
+            chomp($line);
+            $line=~ s/^\s+|\s+$//g;
+            push(@removed_edge,$line);
+        }
+        close FILE;
+        @acyclic_turns = get_diff_array ( \@graph_array , \@removed_edge );
+        $result = check_diff_graph_be_connected ($self,\@acyclic_turns,$info);
+        if($result == 1){
+            my $alg = capture_string_between ('paths_graph_coded_removed_by_',$file,".edges");
+            $algorithms{$alg}=$line_num;
+            #save @acyclic_turns for this algorithm
+            open(F,  ">$tmp_dir/$alg.alg") || die "Can not creat: $!";
+            print F perl_file_header("$alg.alg");
+            print F Data::Dumper->Dump([\@acyclic_turns],['turn']);
+            close(F ) || die "Error closing file: $!";
+        }
+    }
+    $self->object_add_attribute('routing_auto','acyclic_algorithms',\%algorithms);
     if (scalar (keys %algorithms) == 0){
-		add_colored_info($info,"Unable to find any directed acyclic graph for routing\n",'red');
-		return;
-    }
-	
-	return;
-	#add_colored_info($info,"$out file has been selected as it has the minimum number of edge removal of $line_num and its connected\n",'blue');
-		
-	
-	    
+        add_colored_info($info,"Unable to find any directed acyclic graph for routing\n",'red');
+        return;
+    }
+    return;
+    #add_colored_info($info,"$out file has been selected as it has the minimum number of edge removal of $line_num and its connected\n",'blue');
     #add_colored_info($info,"List of forbidden turns: \n",'blue');
-    
-	foreach my $line (@removed_edge) {
-    	chomp $line;
-    	my ($s1,$s2) = split /\s/, $line;
-        $s1  = get_turn_str($s1);  
-  		$s2  = get_turn_str($s2);
-  		my @turn = get_turn_involved_routrs($s1,$s2);
-  		my $str = get_path_instance_string($self,\@turn);
-  		my $string=join('->',@turn);
-  #		push (@forbiden_turn, $string);
-  		add_info($info,"$str\n");  
-
-  	}
-  	
- # $self->object_add_attribute('routing_auto','acyclic_turns',\@acyclic_turns);
-  	
-#  return @forbiden_turn;
-  
+    foreach my $line (@removed_edge) {
+        chomp $line;
+        my ($s1,$s2) = split /\s/, $line;
+        $s1  = get_turn_str($s1);
+        $s2  = get_turn_str($s2);
+        my @turn = get_turn_involved_routrs($s1,$s2);
+        my $str = get_path_instance_string($self,\@turn);
+        my $string=join('->',@turn);
+    #   push (@forbiden_turn, $string);
+        add_info($info,"$str\n");
+    }
+    # $self->object_add_attribute('routing_auto','acyclic_turns',\@acyclic_turns);
+    #  return @forbiden_turn;
 }
 
-
-
 sub check_diff_graph_be_connected {
-	my ($self,$ref,$info)=@_;
-	my @diff = @{$ref};
-	my %all_turns;
-	my %graph;
-	
-	foreach my $str (@diff){
-		my ($s1,$s2) = split /\s/, $str;
-		$all_turns{$s1}=1;
-		$all_turns{$s2}=1;
-		push(@{$graph{$s1}},$s2);
-			
-	}
-	
-	my @all_endpoints=get_list_of_all_endpoints($self);
-	my @start_turns;
-	my @ended_turns;
-	foreach my $endp (@all_endpoints){
-				
-				my $src_port = "Port[0]";
-		   	   	my $connect = $self->{$endp}{'PCONNECT'}{$src_port};	
-				if(defined $connect){
-					my ($node,$pnode)=split(/\s*,\s*/,$connect);
-					push (@start_turns, 	get_turn_code("${endp}::${node}"));
-					push (@ended_turns, 	get_turn_code("${node}::${endp}"));
-				}
-	}
-	
-	my $k=0;
-	foreach my $s (@start_turns){# we should see all @ended_turns
-	
-		my @seen_turns=($s,$ended_turns[$k]);# put connect to itself connection as seen node.  
-		$k++;
-		my @next_turns =@{$graph{$s}};
-		
-		while (scalar @next_turns>0){
-		
-		
-			#print "\@next_nodes = @next_nodes\n";
-			#print "\@seen_nodes = @seen_nodes\n";
-			my $n = pop (@next_turns);
-			#print "\$n  = $n \n";
-			my @nn;
-			@nn = @{$graph{$n}} if (defined $graph{$n}); 		
-			#print "\@nn  = @nn \n";
-			push (@seen_turns, $n);
-			@diff = get_diff_array ( \@nn , \@seen_turns );
-			#print "\@diff  = @diff \n";
-			push (@next_turns,@diff);
-				
-		}
-		
-		my @sep = get_diff_array (\@ended_turns,\@seen_turns);
-		
-		if( scalar @sep > 0) {
-			my $s1  = get_turn_str($s);
-			my ($a1,$a2) = split ('::',$s1); 
-			my $n1=$self->object_get_attribute("$a1",'NAME');
-			
-			$s1  = get_turn_str($sep[0]);
-			my($a3,$a4) = split ('::',$s1); 
-			my $n2=$self->object_get_attribute("$a4",'NAME');
-				
-			add_info($info,"\t $n1 is not connected to $n2. \n");  
-			return 0;
-		}
-	
-			
-	}
-	
-		
-	add_info($info,"\t All endpoints are connected in chanel dpenedency graph. \n");  
-	return 1;
-
-}
-
-
-	
-sub get_path_instance_string {
-	my ($self,$path_ref)=@_;
-	my @path = @{$path_ref};
-	my @path_inst;
-	foreach my $p (@path){
-		push (@path_inst, $self->object_get_attribute("$p",'NAME'));	
-		
-	}
-	my $string=join('->',@path_inst);
-	return $string;
-}	
+    my ($self,$ref,$info)=@_;
+    my @diff = @{$ref};
+    my %all_turns;
+    my %graph;
+    foreach my $str (@diff){
+        my ($s1,$s2) = split /\s/, $str;
+        $all_turns{$s1}=1;
+        $all_turns{$s2}=1;
+        push(@{$graph{$s1}},$s2);
+    }
+    my @all_endpoints=get_list_of_all_endpoints($self);
+    my @start_turns;
+    my @ended_turns;
+    foreach my $endp (@all_endpoints){
+        my $src_port = "Port[0]";
+        my $connect = $self->{$endp}{'PCONNECT'}{$src_port};
+        if(defined $connect){
+            my ($node,$pnode)=split(/\s*,\s*/,$connect);
+            push (@start_turns,     get_turn_code("${endp}::${node}"));
+            push (@ended_turns,     get_turn_code("${node}::${endp}"));
+        }
+    }
+    my $k=0;
+    foreach my $s (@start_turns){# we should see all @ended_turns
+        my @seen_turns=($s,$ended_turns[$k]);# put connect to itself connection as seen node.
+        $k++;
+        my @next_turns =@{$graph{$s}};
+        while (scalar @next_turns>0){
+            #print "\@next_nodes = @next_nodes\n";
+            #print "\@seen_nodes = @seen_nodes\n";
+            my $n = pop (@next_turns);
+            #print "\$n  = $n \n";
+            my @nn;
+            @nn = @{$graph{$n}} if (defined $graph{$n});
+            #print "\@nn  = @nn \n";
+            push (@seen_turns, $n);
+            @diff = get_diff_array ( \@nn , \@seen_turns );
+            #print "\@diff  = @diff \n";
+            push (@next_turns,@diff);
+        }
+        my @sep = get_diff_array (\@ended_turns,\@seen_turns);
+        if( scalar @sep > 0) {
+            my $s1  = get_turn_str($s);
+            my ($a1,$a2) = split ('::',$s1);
+            my $n1=$self->object_get_attribute("$a1",'NAME');
+            $s1  = get_turn_str($sep[0]);
+            my($a3,$a4) = split ('::',$s1);
+            my $n2=$self->object_get_attribute("$a4",'NAME');
+            add_info($info,"\t $n1 is not connected to $n2. \n");
+            return 0;
+        }
+    }
+    add_info($info,"\t All endpoints are connected in chanel dpenedency graph. \n");
+    return 1;
+}
 
+sub get_path_instance_string {
+    my ($self,$path_ref)=@_;
+    my @path = @{$path_ref};
+    my @path_inst;
+    foreach my $p (@path){
+        push (@path_inst, $self->object_get_attribute("$p",'NAME'));
+    }
+    my $string=join('->',@path_inst);
+    return $string;
+}
 
 sub remove_cycle_paths {
-	my ($self,$info,$paths_ref, $fturn_ref)=@_;	
-	my @free_paths;
-	my @paths= @{$paths_ref};
-	my @fturns= @{$fturn_ref};
-	my $remove;
-	
-	
-	
-	foreach my $path (@paths) {
-		my @p = @$path;
-		my $turn;
-		my $string=join('->',@p);
-		#print "$string\n";	
-		$remove=0;
-		foreach my $t (@fturns){
-			 if ($string =~ /$t-/){
-			 	$remove=1;
-			 	$turn=$t;
-			 	last;
-			 }
-			 
-		}
-		push (@free_paths,$path) if($remove == 0);
-		if($remove == 1){
-			my @ft = split /->/, $turn; 
-			add_info($info,"path ".get_path_instance_string($self,$path)." is removed due to turn ".get_path_instance_string($self,\@ft)."\n") 
-		}
-	}	
-	return @free_paths;	
-}	
-	
-	
-	
-	
-	
-
-
+    my ($self,$info,$paths_ref, $fturn_ref)=@_;
+    my @free_paths;
+    my @paths= @{$paths_ref};
+    my @fturns= @{$fturn_ref};
+    my $remove;
+    foreach my $path (@paths) {
+        my @p = @$path;
+        my $turn;
+        my $string=join('->',@p);
+        #print "$string\n";
+        $remove=0;
+        foreach my $t (@fturns){
+            if ($string =~ /$t-/){
+                $remove=1;
+                $turn=$t;
+                last;
+            }
+        }
+        push (@free_paths,$path) if($remove == 0);
+        if($remove == 1){
+            my @ft = split /->/, $turn;
+            add_info($info,"path ".get_path_instance_string($self,$path)." is removed due to turn ".get_path_instance_string($self,\@ft)."\n")
+        }
+    }
+    return @free_paths;
+}
 
 sub auto_route {
-	my ($self,$info)=@_;
-	my %Psize;
-	my $alg = $self->object_get_attribute('routing_auto', 'CYCLE_FREE_ALG'); 	
-	my ($alg_name,$line) = split (/\s+--\s+/,$alg);
-	
-	if(!defined $line){
-		add_colored_info($info,"No acyclic turn model is selected. click on Generate Cycle-free and make sure it runs successfully!\n",'red');
-        return; 
-	}
-	my $tmp_dir  = "$ENV{'PRONOC_WORK'}/tmp";
-	my $model_file = "$tmp_dir/$alg_name.alg";	
-	my ($pp,$r,$err) = regen_object($model_file);
-    if ($r){        
-    	add_colored_info($info,"**Error: cannot open $model_file file: $err\n",'red');
-   		return;
+    my ($self,$info)=@_;
+    my %Psize;
+    my $alg = $self->object_get_attribute('routing_auto', 'CYCLE_FREE_ALG');
+    my ($alg_name,$line) = split (/\s+--\s+/,$alg);
+    if(!defined $line){
+        add_colored_info($info,"No acyclic turn model is selected. click on Generate Cycle-free and make sure it runs successfully!\n",'red');
+        return;
+    }
+    my $tmp_dir  = "$ENV{'PRONOC_WORK'}/tmp";
+    my $model_file = "$tmp_dir/$alg_name.alg";
+    my ($pp,$r,$err) = regen_object($model_file);
+    if ($r){
+        add_colored_info($info,"**Error: cannot open $model_file file: $err\n",'red');
+        return;
     } else {
-    	add_info($info,"Use $alg_name algorithm for obtaing acyclic paths\n");
-    }
-	
-	my @acyclic_turns = @{$pp};
-	my %rusage = get_router_usage ($self,\@acyclic_turns);
-	
-	
-	#step 1: calculate all minimal paths between all source and destination pairs
-	add_info($info,"Calculate all  paths between all source and destination pairs\n");
-	my @all_endpoints=get_list_of_all_endpoints($self);
-	foreach  my $src  (@all_endpoints ){	
-		foreach  my $dst  (@all_endpoints ){
-			if($src ne $dst){	
-				my ($paths_to_dst,$ports_to_dst) =  get_all_paths_between_two_endps_using_accyclic_turn($self,$src, $dst,\@acyclic_turns);
-				my @cyle_free_paths= @{$paths_to_dst} if (defined $paths_to_dst);
-				my $size = scalar  @cyle_free_paths;
-				$Psize{"${src}::$dst"} = $size;
-			}
-		}
-	}
-	#step 2: Remove cyclic paths between all source and destination pairs
-	
-	
-	
-	
-	
-	
-	#step 3 sort source destination based on the number of paths
-	my @keys = sort { $Psize{$a} <=> $Psize{$b} } keys(%Psize);
-	for my $key ( @keys) {
-		my $size=$Psize{$key};
-		#print "size = $size\n";
-		next if(defined $self->object_get_attribute('Route',$key));
-		
-       # print "($key)->($Psize{$key})\n";
+        add_info($info,"Use $alg_name algorithm for obtaing acyclic paths\n");
+    }
+    my @acyclic_turns = @{$pp};
+    my %rusage = get_router_usage ($self,\@acyclic_turns);
+    #step 1: calculate all minimal paths between all source and destination pairs
+    add_info($info,"Calculate all  paths between all source and destination pairs\n");
+    my @all_endpoints=get_list_of_all_endpoints($self);
+    foreach  my $src  (@all_endpoints ){
+        foreach  my $dst  (@all_endpoints ){
+            if($src ne $dst){
+                my ($paths_to_dst,$ports_to_dst) =  get_all_paths_between_two_endps_using_accyclic_turn($self,$src, $dst,\@acyclic_turns);
+                my @cyle_free_paths= @{$paths_to_dst} if (defined $paths_to_dst);
+                my $size = scalar  @cyle_free_paths;
+                $Psize{"${src}::$dst"} = $size;
+            }
+        }
+    }
+    #step 2: Remove cyclic paths between all source and destination pairs
+    #step 3 sort source destination based on the number of paths
+    my @keys = sort { $Psize{$a} <=> $Psize{$b} } keys(%Psize);
+    for my $key ( @keys) {
+        my $size=$Psize{$key};
+        #print "size = $size\n";
+        next if(defined $self->object_get_attribute('Route',$key));
+        # print "($key)->($Psize{$key})\n";
         my ($src , $dst)=split ('::',$key);
         my ($paths_to_dst,$ports_to_dst) = get_all_paths_between_two_endps_using_accyclic_turn($self,$src, $dst,\@acyclic_turns);
         #my @cyle_free_paths=remove_cycle_paths($self,$info,$paths_to_dst, \@forbiden_turn);
         my @cyle_free_paths= @{$paths_to_dst} if (defined $paths_to_dst);
         my @sort_paths=sort_paths_based_on_router_usage($self,\@cyle_free_paths,\%rusage);
-       
-      # my @sort_paths=sort_paths_based_on_link_usage($self,\@cyle_free_paths);
-      
-
-        
+        # my @sort_paths=sort_paths_based_on_link_usage($self,\@cyle_free_paths);
         my $path;
         my $n=0;
         foreach my $p (@sort_paths ){
-        	if(check_cyclick_loop($self,$p)==0){
-        		$path=$p;
-        		#my @rrr=($p);
-        		#remove_cycle_paths($self,$info,\@rrr, \@forbiden_turn);
-        		
-        		last;
-        	}  else {
-        		print "***Error  something goes wrong in acyclic turns model  ****************************\n";
-        	}
-        	$n++;      	
+            if(check_cyclick_loop($self,$p)==0){
+                $path=$p;
+                #my @rrr=($p);
+                #remove_cycle_paths($self,$info,\@rrr, \@forbiden_turn);
+                last;
+            }  else {
+                print "***Error  something goes wrong in acyclic turns model  ****************************\n";
+            }
+            $n++;
         }
         if(!defined $path){
-        	#extract path from acyclic turn graph. This graph is connected so there must be atleast a path between each endpoint pairs there. however this path does not match the offset or size lentgh
-        	
-        	
-        	set_gui_status($self,"ref",1);
-        	add_colored_info($info,"Failed to find an acyclic routing paths for $key nodes!\n",'red');
-        	return FALSE ;
-        	
+            #extract path from acyclic turn graph. This graph is connected so there must be atleast a path between each endpoint pairs there. however this path does not match the offset or size lentgh
+            set_gui_status($self,"ref",1);
+            add_colored_info($info,"Failed to find an acyclic routing paths for $key nodes!\n",'red');
+            return FALSE ;
         }
-        
         $self->object_add_attribute('Route',$key,$path);
-		
-	}
-	
-	set_gui_status($self,"ref",1);
-	add_colored_info($info,"The routeing function table is generated successfully!\n",'blue');
-	return TRUE;
-}	
-
+    }
+    set_gui_status($self,"ref",1);
+    add_colored_info($info,"The routeing function table is generated successfully!\n",'blue');
+    return TRUE;
+}
 
 sub clean_route {
-	my ($self,$info)=@_;
-	 
-	my @all_endpoints=get_list_of_all_endpoints($self);
-	foreach  my $src  (@all_endpoints ){	
-		foreach  my $dst  (@all_endpoints ){						
+    my ($self,$info)=@_;
+    my @all_endpoints=get_list_of_all_endpoints($self);
+    foreach  my $src  (@all_endpoints ){
+        foreach  my $dst  (@all_endpoints ){
         $self->object_add_attribute('Route',"${src}::$dst",undef);
-		
-	}}
-	
-	set_gui_status($self,"ref",1);
-	add_colored_info($info,"The Routing function table is cleared!\n",'blue');
-	return TRUE;
-}	
-
-
+    }}
+    set_gui_status($self,"ref",1);
+    add_colored_info($info,"The Routing function table is cleared!\n",'blue');
+    return TRUE;
+}
 
 sub average{
         my($data) = @_;
         if (not @$data) {
-               return 0;
+            return 0;
         }
         my $total = 0;
         foreach (@$data) {
-                $total += $_;
+            $total += $_;
         }
         my $average = $total / @$data;
         return $average;
 }
+
 sub stdev{
         my($data) = @_;
         if(@$data == 1){
@@ -2699,184 +2051,143 @@ sub stdev{
 }
 
 sub clone_hash{
-	my $ref=shift;
-	my %hash=%{$ref};
-	my %copy;
-	foreach my $p (keys %hash){
-		if (defined $hash{$p}){	$copy{$p} =  $hash{$p};}
-	}
-	return %copy;
+    my $ref=shift;
+    my %hash=%{$ref};
+    my %copy;
+    foreach my $p (keys %hash){
+        if (defined $hash{$p}){    $copy{$p} =  $hash{$p};}
+    }
+    return %copy;
 }
 
-
 sub sort_paths_based_on_router_usage{
-	my ($self,$paths_to_dst,$usage)=@_;
-	my %scored;
-	my %usage_r= %{$usage};
-	#get list of 30% high congested ruters 
-	my @A = sort { $usage_r{$b} <=> $usage_r{$a} } keys %usage_r;
-	#my $t = (scalar @A)*.3; # %30 
-	my %congested;
-	foreach my $a ( @A){		
-		$congested{$a}=$usage_r{$a};# if(scalar(keys %congested)<$t);
-	}
-	
-	my $i=0;
-	foreach my $path (@{$paths_to_dst}) {
-		my $val = 0;
-		my $num=0;			
-		for my $r (@{$path}){
-			if(defined $congested{$r}){
-				$val+=$congested{$r}**1.5;# pow of 3/2 to give higher weight to more congested routers
-				$num++;
-			}			
-		}
-		$scored{$i}=($num==0)? 0 : $val/$num;	#average weight of congested routers
-		$i++;
-	}
-	
-	my @order = sort { $scored{$a} <=> $scored{$b} } keys %scored;
-	my @sorted;
-	
-	
-	
-	$i=0;
-	foreach my $a ( @order){
-		$sorted[$i]=${$paths_to_dst}[$a];
-		$i++;
-		#print "\$max{$a}=$max{$a},"
-	}
-	
-	#print "\n";
-	
-	return @sorted;		
-}	
-
+    my ($self,$paths_to_dst,$usage)=@_;
+    my %scored;
+    my %usage_r= %{$usage};
+    #get list of 30% high congested ruters
+    my @A = sort { $usage_r{$b} <=> $usage_r{$a} } keys %usage_r;
+    #my $t = (scalar @A)*.3; # %30
+    my %congested;
+    foreach my $a ( @A){
+        $congested{$a}=$usage_r{$a};# if(scalar(keys %congested)<$t);
+    }
+    my $i=0;
+    foreach my $path (@{$paths_to_dst}) {
+        my $val = 0;
+        my $num=0;
+        for my $r (@{$path}){
+            if(defined $congested{$r}){
+                $val+=$congested{$r}**1.5;# pow of 3/2 to give higher weight to more congested routers
+                $num++;
+            }
+        }
+        $scored{$i}=($num==0)? 0 : $val/$num;    #average weight of congested routers
+        $i++;
+    }
+    my @order = sort { $scored{$a} <=> $scored{$b} } keys %scored;
+    my @sorted;
+    $i=0;
+    foreach my $a ( @order){
+        $sorted[$i]=${$paths_to_dst}[$a];
+        $i++;
+        #print "\$max{$a}=$max{$a},"
+    }
+    #print "\n";
+    return @sorted;
+}
 
 sub sort_paths_based_on_link_usage{
-	my ($self,$paths_to_dst)=@_;
-	
-	my %L_num;
-	my %max;
-	my @all_endpoints=get_list_of_all_endpoints($self);
-	#get link count
-	foreach  my $src  (@all_endpoints ){	
-		foreach  my $dst  (@all_endpoints ){	
-			my $path = $self->object_get_attribute('Route',"${src}::$dst");
-			if (defined $path){
-				#path counting
-				my @p= 	get_adjacent_router_in_a_path($path);
-				
-				foreach my $r (@p){				
-					$L_num{$r} ++;						
-				}	
-			
-			}			
-		}
-	}
-	#get std_devision of link  for each path if added   
-	my $i=0;
-	foreach my $path (@{$paths_to_dst}) {
-		my %copy = clone_hash(\%L_num);
-		my @p=get_adjacent_router_in_a_path($path);	
-		foreach my $r (@p){				
-					$copy{$r} ++;						
-		}				
-		my @l = sort  values (%copy);
-		my $std=stdev(\@l);		
-		$max{$i}=$std*100;
-		$i++;	
-	}
-	
-	
-	my @order = sort { $max{$a} <=> $max{$b} } keys(%max);
-	
-	#print "*********** @order ************"; 
-	my @sorted;
-	$i=0;
-	foreach my $a ( @order){
-		$sorted[$i]=${$paths_to_dst}[$a];
-		$i++;
-		#print "\$max{$a}=$max{$a},"
-	}
-	
-	#print "\n";
-	
-	return @sorted;
-	
-	
+    my ($self,$paths_to_dst)=@_;
+    my %L_num;
+    my %max;
+    my @all_endpoints=get_list_of_all_endpoints($self);
+    #get link count
+    foreach  my $src  (@all_endpoints ){
+        foreach  my $dst  (@all_endpoints ){
+            my $path = $self->object_get_attribute('Route',"${src}::$dst");
+            if (defined $path){
+                #path counting
+                my @p=     get_adjacent_router_in_a_path($path);
+                foreach my $r (@p){
+                    $L_num{$r} ++;
+                }
+            }
+        }
+    }
+    #get std_devision of link  for each path if added
+    my $i=0;
+    foreach my $path (@{$paths_to_dst}) {
+        my %copy = clone_hash(\%L_num);
+        my @p=get_adjacent_router_in_a_path($path);
+        foreach my $r (@p){
+            $copy{$r} ++;
+        }
+        my @l = sort  values (%copy);
+        my $std=stdev(\@l);
+        $max{$i}=$std*100;
+        $i++;
+    }
+    my @order = sort { $max{$a} <=> $max{$b} } keys(%max);
+    #print "*********** @order ************";
+    my @sorted;
+    $i=0;
+    foreach my $a ( @order){
+        $sorted[$i]=${$paths_to_dst}[$a];
+        $i++;
+        #print "\$max{$a}=$max{$a},"
+    }
+    #print "\n";
+    return @sorted;
 }
 
-
 sub get_router_usage{
-	my ($self,$acycle_turn_ref)=@_;
-	
-	my @all_endpoints=get_list_of_all_endpoints($self);
-	my %router_cnt;
-	#get router counts
-	foreach  my $src  (@all_endpoints ){	
-		foreach  my $dst  (@all_endpoints ){	
-			#get list of all path between a source and destination nodes
-			 my ($paths_to_dst,$ports_to_dst)= get_all_paths_between_two_endps_using_accyclic_turn($self,$src, $dst,$acycle_turn_ref);
-			
-			my @paths = @{$paths_to_dst};					
-			foreach my $path (@paths){
-				shift @{$path}; #remove source node from the path
-				pop @{$path}; #remove the destination node from the path	
-				foreach my $q ( @{$path}){
-				 	$router_cnt{"$q"} = ( defined $router_cnt{"$q"})? $router_cnt{"$q"}+1 : 1;
-				}
-			}		
-		}
-	}
-	
-	return %router_cnt;
-	
+    my ($self,$acycle_turn_ref)=@_;
+    my @all_endpoints=get_list_of_all_endpoints($self);
+    my %router_cnt;
+    #get router counts
+    foreach  my $src  (@all_endpoints ){
+        foreach  my $dst  (@all_endpoints ){
+            #get list of all path between a source and destination nodes
+            my ($paths_to_dst,$ports_to_dst)= get_all_paths_between_two_endps_using_accyclic_turn($self,$src, $dst,$acycle_turn_ref);
+            my @paths = @{$paths_to_dst};
+            foreach my $path (@paths){
+                shift @{$path}; #remove source node from the path
+                pop @{$path}; #remove the destination node from the path
+                foreach my $q ( @{$path}){
+                    $router_cnt{"$q"} = ( defined $router_cnt{"$q"})? $router_cnt{"$q"}+1 : 1;
+                }
+            }
+        }
+    }
+    return %router_cnt;
 }
 
-
 sub check_cyclick_loop{
-	my ($self,$paths_to_dst)=@_;
-	
-	
-	my %graph;
-	my @all_endpoints=get_list_of_all_endpoints($self);
-	# create routing dependency graph
-	
-	foreach  my $src  (@all_endpoints ){	
-		foreach  my $dst  (@all_endpoints ){	
-			my $path = $self->object_get_attribute('Route',"${src}::$dst");
-			if (defined $path){
-				#path counting
-				my @p= 	get_adjacent_node_in_a_path($path);
-				%graph=add_route_edge_to_graph(\%graph,\@p);
-			
-			}			
-		}
-	}
-	
-	my @p= 	get_adjacent_node_in_a_path($paths_to_dst);
-	%graph=add_route_edge_to_graph(\%graph,\@p);
-	
-	my $result = Algorithm::TSort::cicle_detect( Algorithm::TSort::Graph( ADJ => \%graph ), keys %graph ); 
-	
-	#print Data::Dumper->Dump([\%graph],["link"]);
-	#print "result=$result\n";
-	
-	
-	
-	
-	
-	
-	
-	return  $result;
-	
-	
+    my ($self,$paths_to_dst)=@_;
+    my %graph;
+    my @all_endpoints=get_list_of_all_endpoints($self);
+    # create routing dependency graph
+    foreach  my $src  (@all_endpoints ){
+        foreach  my $dst  (@all_endpoints ){
+            my $path = $self->object_get_attribute('Route',"${src}::$dst");
+            if (defined $path){
+                #path counting
+                my @p=     get_adjacent_node_in_a_path($path);
+                %graph=add_route_edge_to_graph(\%graph,\@p);
+            }
+        }
+    }
+    my @p=     get_adjacent_node_in_a_path($paths_to_dst);
+    %graph=add_route_edge_to_graph(\%graph,\@p);
+    my $result = Algorithm::TSort::cicle_detect( Algorithm::TSort::Graph( ADJ => \%graph ), keys %graph );
+    #print Data::Dumper->Dump([\%graph],["link"]);
+    #print "result=$result\n";
+    return  $result;
 }
 
 sub generate_topology{
-	my ($self,$info)=@_;
-	my $name=$self->object_get_attribute('save_as');
+    my ($self,$info)=@_;
+    my $name=$self->object_get_attribute('save_as');
     my $error = check_verilog_identifier_syntax($name);
     if ( defined $error ){
         #message_dialog("The \"$name\" is given with an unacceptable formatting. The mpsoc name will be used as top level verilog module name so it must follow Verilog identifier declaration formatting:\n $error");
@@ -2893,330 +2204,386 @@ sub generate_topology{
         add_colored_info($info, $message,'red' );
         return 0;
     }
-    
-    
-    
-    
-	#make destination dir
-	my $dir =get_project_dir()."/mpsoc/rtl/src_topology/$name";
-	mkpath("$dir",1,01777) unless (-d $dir) ;  
-    mkpath("$dir/../common",1,01777) unless (-d "$dir/../common") ;  
-    
-	#save topology image file
-	$self->object_add_attribute("graph_save","name","$dir/$name");
-	$self->object_add_attribute("graph_save","extension",'png');
-	$self->object_add_attribute("graph_save","enable",1);
-	
-	show_custom_topology_diagram ($self,undef,"topology_diagram");
-	
-	
-	
-	#generate topology top module verilog file
-	generate_topology_top_v($self,$info,$dir);
-	generate_topology_top_genvar_v($self,$info,$dir);
-	generate_routing_v($self,$info,$dir);
-	#generate_connection_v($self,$info,$dir);
-	add_routing_instance_v($self,$info,$dir);
-	add_noc_instance_v($self,$info,$dir);
-	add_noc_custom_h($self,$info,$dir);
-	save_topology_parameter_object_file($self,$info);	
-	
-	#create the file list
-	my $txt="+incdir+./\n";
-	my @files = File::Find::Rule->file()
-                            ->name( '*.v','*.sv')
-                            ->in( "$dir/../" );	
+    #make destination dir
+    my $dir =get_project_dir()."/mpsoc/rtl/src_topology/$name";
+    mkpath("$dir",1,01777) unless (-d $dir) ;
+    mkpath("$dir/../common",1,01777) unless (-d "$dir/../common") ;
+    #save topology image file
+    $self->object_add_attribute("graph_save","name","$dir/$name");
+    $self->object_add_attribute("graph_save","extension",'png');
+    $self->object_add_attribute("graph_save","enable",1);
+    show_custom_topology_diagram ($self,undef,"topology_diagram");
+    #generate topology top module verilog file
+    generate_topology_top_v($self,$info,$dir);
+    generate_topology_top_genvar_v($self,$info,$dir);
+    generate_routing_v($self,$info,$dir);
+    #generate_connection_v($self,$info,$dir);
+    add_routing_instance_v($self,$info,$dir);
+    add_noc_instance_v($self,$info,$dir);
+    add_noc_custom_h($self,$info,$dir);
+    save_topology_parameter_object_file($self,$info);
+    #create the file list
+    my $txt="+incdir+./\n";
+    my @files = File::Find::Rule->file()
+        ->name( '*.v','*.sv')
+        ->in( "$dir/../" );
     foreach my $f (@files){
-    	my $d = basename(dirname(abs_path($f)));
-    	my $n = basename($f);
-    	$txt.="./$d/$n\n";    	
+        my $d = basename(dirname(abs_path($f)));
+        my $n = basename($f);
+        $txt.="./$d/$n\n";
     }
-	save_file("$dir/../custom_flist.f",$txt);
-	
-	
+    save_file("$dir/../custom_flist.f",$txt);
+    message_dialog("Custom topology \"$name\" is generated in $dir!");
 }
 
-
 sub save_topology_parameter_object_file{
-	my ($self,$info)=@_;	
-	my $name=$self->object_get_attribute('save_as');
-	my $rname=$self->object_get_attribute('routing_name');
-	my $dir =get_project_dir()."/mpsoc/rtl/src_topology";
-	my $file="$dir/param.obj";
-	
-	my %param;
-	
-	if(-f $file){
-		 my ($pp,$r,$err) = regen_object($file );
-            if ($r){        
+    my ($self,$info)=@_;
+    my $name=$self->object_get_attribute('save_as');
+    my $rname=$self->object_get_attribute('routing_name');
+    my $dir =get_project_dir()."/mpsoc/rtl/src_topology";
+    my $file="$dir/param.obj";
+    my %param;
+    if(-f $file){
+        my ($pp,$r,$err) = regen_object($file );
+            if ($r){
                 add_info($info,"**Error: cannot open $file file: $err\n");
                 return;
-            } 
-		
-		%param=%{$pp};		
-	}
-	
-	
-	my @ends=get_list_of_all_endpoints($self);
+            }
+        %param=%{$pp};
+    }
+    my @ends=get_list_of_all_endpoints($self);
     my @routers=get_list_of_all_routers($self);
-    
     my $MAX_P=0;
     my %router_ps;
     foreach my $p (@routers){
-    	my $Pnum=$self->object_get_attribute("$p",'PNUM');
-    	$MAX_P =$Pnum  if($Pnum>$MAX_P ); 
-    	$router_ps{$Pnum}=(defined $router_ps{$Pnum})? $router_ps{$Pnum}+1 : '1';   	
-    }	
-
+        my $Pnum=$self->object_get_attribute("$p",'PNUM');
+        $MAX_P =$Pnum  if($Pnum>$MAX_P );
+        $router_ps{$Pnum}=(defined $router_ps{$Pnum})? $router_ps{$Pnum}+1 : '1';
+    }
     my $NE= scalar @ends;
     my $NR= scalar @routers;
-	
-	
-	$param{"\"$name\""}{'T1'}=$NE;
-	$param{"\"$name\""}{'T2'}=$NR;
-	$param{"\"$name\""}{'T3'}=$MAX_P;
-	my $routs = $param{"\"$name\""}{'ROUTE_NAME'};
-	my $new="\"$rname\"";
-	if(!defined $routs){
-		$param{"\"$name\""}{'ROUTE_NAME'}=$new;
-	}
-	else {	
-		my @r=split(/\s*,\s*/,$routs);
-		unless( grep (/^$new$/,@r)){
-			$param{"\"$name\""}{'ROUTE_NAME'}= $routs.",$new" ;
-		}
-	}
-	
-	$param{"\"$name\""}{'ROUTER_Ps'}= \%router_ps;
-	
-	
-	my @er_addr;
-	foreach my $end (@ends){
-		my $connect = $self->{$end}{'PCONNECT'}{'Port[0]'};
-		my ($Rname,$Rport)=split(/\s*,\s*/,$connect);
-		my $R = get_scolar_pos($Rname,@routers);
-		push(@er_addr,$R);			
-	}
-	$param{"\"$name\""}{'er_addr'}= \@er_addr;
-	
-	
-	
-	
+    $param{"\"$name\""}{'T1'}=$NE;
+    $param{"\"$name\""}{'T2'}=$NR;
+    $param{"\"$name\""}{'T3'}=$MAX_P;
+    my $routs = $param{"\"$name\""}{'ROUTE_NAME'};
+    my $new="\"$rname\"";
+    if(!defined $routs){
+        $param{"\"$name\""}{'ROUTE_NAME'}=$new;
+    }
+    else {
+        my @r=split(/\s*,\s*/,$routs);
+        unless( grep (/^$new$/,@r)){
+            $param{"\"$name\""}{'ROUTE_NAME'}= $routs.",$new" ;
+        }
+    }
+    $param{"\"$name\""}{'ROUTER_Ps'}= \%router_ps;
+    my @er_addr;
+    foreach my $end (@ends){
+        my $connect = $self->{$end}{'PCONNECT'}{'Port[0]'};
+        my ($Rname,$Rport)=split(/\s*,\s*/,$connect);
+        my $R = get_scolar_pos($Rname,@routers);
+        push(@er_addr,$R);
+    }
+    $param{"\"$name\""}{'er_addr'}= \@er_addr;
     open(FILE,  ">$file") || die "Can not open: $!";
     print FILE perl_file_header("$file");
     print FILE Data::Dumper->Dump([\%param],['Topology']);
     close(FILE) || die "Error closing file: $!";
-	
 }
 
-
 sub get_path_route_widgets {
-	my 	($self,$info)=@_;
-
-	my 		$w1 = show_paths_between_two_endps($self,$info);
-	my		$w2 = routing_summary($self,$info);
+    my     ($self,$info)=@_;
+    my         $w1 = show_paths_between_two_endps($self,$info);
+    my        $w2 = routing_summary($self,$info);
     my $h=gen_hpaned($w1,.15,$w2);
-    $h -> pack1($w1, TRUE, TRUE); 
-	$h -> pack2($w2, TRUE, TRUE); 
-	return $h;
+    $h -> pack1($w1, TRUE, TRUE);
+    $h -> pack2($w2, TRUE, TRUE);
+    return $h;
 }
 
-
 sub load_nwm{
-	my ($self,$info)=@_;
-	load_net_maker($self,$info);
-	my $n=0;
+    my ($self,$info)=@_;
+    load_net_maker($self,$info);
+    my $n=0;
     my $sample="sample$n";
-	$n++;
-	$self->object_add_attribute("id",undef,$n);
-	$self->object_add_attribute("active_setting",undef,undef);
-	$self->object_add_attribute_order("samples",$sample);
-	$self->object_add_attribute($sample,"color",1);
-	add_color_to_gd($self);	
+    $n++;
+    $self->object_add_attribute("id",undef,$n);
+    $self->object_add_attribute("active_setting",undef,undef);
+    $self->object_add_attribute_order("samples",$sample);
+    $self->object_add_attribute($sample,"color",1);
+    add_color_to_gd($self);
+}
+
+sub Get_yaml_noc_conf{
+    my ($self,$info)=@_;
+    my $file;
+    my $dialog =  gen_file_dialog (undef, 'yml');
+    my $dir = Cwd::getcwd();
+    $dialog->set_current_folder ("$dir/../script/noc_yml_gen")    ;
+    if ( "ok" eq $dialog->run ) {
+        $file = $dialog->get_filename;
+        my ($name,$path,$suffix) = fileparse("$file",qr"\..[^.]*$");
+        if($suffix eq '.yml'){
+            #Read yml file 
+            add_info($info,"Loading Custom NoC configuration from $file\n");
+            Read_yaml_noc_conf_file($self,$info,$file);
+        }
+    }
+    $dialog->destroy;
+    set_gui_status($self,"ref",1)
+}
+
+sub Read_yaml_noc_conf_file{
+    my ($self,$info,$file)=@_;
+    my $yp = YAML::PP->new(preserve => YAML::PP::Common->PRESERVE_ORDER);
+    my $data = $yp->load_file($file);
+    my %connections = map { $_->{source} => $_->{dest} } @{$data->{connections}};
+    my %endpoints = map { $_->{id} => $_->{endpoints} } @{$data->{nodes}};
+    my %port_count;
+    my %router_hash;
+    # Track per-port router counters
+    my %port_counters;
+    my $enps_count=0;
+    foreach my $router_id (sort { $a <=> $b } keys %connections) {
+        my $ports = scalar @{$connections{$router_id}};  # number of dest nodes = ports
+        my $eps   = scalar @{$endpoints{$router_id} // []};   # number of endpoints for this router
+        $ports+=$eps;
+        $port_count{$ports}++;
+        $enps_count+=$eps;
+        # assign router name router_${p}_${n}
+        my $n = $port_counters{$ports} // 0;
+        $router_hash{$router_id} = "ROUTER${ports}_${n}";
+        $port_counters{$ports} = $n + 1;
+    }
+    $self->object_add_attribute ("ENDP","NUM",$enps_count);
+    foreach my $p (sort { $a <=> $b } keys %port_count) {
+        add_info($info,"Add $p-Ports Router: $port_count{$p} number\n");
+        $self->object_add_attribute ("ROUTER${p}","NUM",$port_count{$p});
+    }
+    my %port_map;
+    # Track destination port counters (optional simple assumption: dest ports assigned sequentially)
+    my %dest_port_counter;
+    $enps_count=0;
+    # remembers port assignment between router pairs
+    my %link_ports;
+    # track used ports per router
+    my %router_used_ports;
+
+foreach my $src_id (sort { $a <=> $b } keys %connections) {
+
+    my $src_router = $router_hash{$src_id};
+    my @dst_ids    = @{$connections{$src_id}};
+    $port_map{$src_router} = [];
+
+    for my $src_port (0 .. $#dst_ids) {
+
+        my $dst_id     = $dst_ids[$src_port];
+        my $dst_router = $router_hash{$dst_id};
+
+        my ($assigned_src_port, $assigned_dst_port);
+
+        ############################################################
+        # CASE 1: Check if this src–dst link already has port numbers
+        ############################################################
+        if ( exists $link_ports{$src_router}{$dst_router} ) {
+
+            # retrieve the existing pair
+            ($assigned_src_port, $assigned_dst_port) =
+                @{ $link_ports{$src_router}{$dst_router} };
+
+        } else {
+
+            ############################################################
+            # CASE 2: New src/dst link → find free ports
+            ############################################################
+
+            # ---- find first free src port ----
+            my $src_port = 0;
+            $src_port++ while $router_used_ports{$src_router}{$src_port};
+            $assigned_src_port = $src_port;
+
+            # ---- find first free dst port ----
+            my $dst_port = 0;
+            $dst_port++ while $router_used_ports{$dst_router}{$dst_port};
+            $assigned_dst_port = $dst_port;
+
+            # Save symmetric mapping
+            $link_ports{$src_router}{$dst_router} =
+                [ $assigned_src_port, $assigned_dst_port ];
+
+            $link_ports{$dst_router}{$src_router} =
+                [ $assigned_dst_port, $assigned_src_port ];
+
+            # Mark ports as used
+            $router_used_ports{$src_router}{$assigned_src_port} = 1;
+            $router_used_ports{$dst_router}{$assigned_dst_port} = 1;
+        }
+
+        ############################################################
+        # Connect routers with the consistent port numbers
+        ############################################################
+
+        connect_nodes(
+            $self,
+            $src_router, "Port[$assigned_src_port]",
+            $dst_router, "Port[$assigned_dst_port]",
+            $info
+        );
+    }
+        my $eps   = scalar @{$endpoints{$src_id} // []};
+        
+        for (my $e= 0; $e<$eps;$e++ ){
+            my $src_port=$#dst_ids + $e +1;
+            connect_nodes ($self,$src_router,"Port[$src_port]","ENDP_$enps_count","Port[0]",$info);
+        }
+        $enps_count+=$eps;
+    }
+    #print "\nRouter hash mapping:\n";
+    #print Dumper(\%router_hash);
+    set_gui_status($self,"redraw",1)
 }
 
 sub build_network_maker_gui {
-	my ($self) = @_;
-	set_gui_status($self,"ideal",0);
-	$self->object_add_attribute ("process_notebook","currentpage",0);
-	my $main_table= def_table(2,10,FALSE);
-	
+    my ($self) = @_;
+    set_gui_status($self,"ideal",0);
+    $self->object_add_attribute ("process_notebook","currentpage",0);
+    my $main_table= def_table(2,10,FALSE);
     my ($infobox,$info)= create_txview();
-	
-	
-	my $notebook = gen_notebook();
-	$notebook->set_tab_pos ('left');
-	$notebook->set_scrollable(TRUE);
-	
-	
-	
-	my $page0=take_node_num_page($self);
-	my $page1=take_instance_page($self);
-	my $page2=connection_page_auto($self,$info);
-	my $page3=connection_page($self,$info);
-	my $page4=routing_page_manual($self,$info);
-	
-	my $page0_win = add_widget_to_scrolled_win($page0);
-	my $page1_win = add_widget_to_scrolled_win($page1);
-	my $page2_win = add_widget_to_scrolled_win($page2);
-	my $page3_win = add_widget_to_scrolled_win($page3);
-	my $page4_win = add_widget_to_scrolled_win($page4);
-
-	
-	$notebook->append_page ($page0_win,gen_label_in_center  (" Nodes #"));
-	$notebook->append_page ($page1_win,gen_label_in_center  ("Instance"));
-	$notebook->append_page ($page2_win,gen_label_in_center  ("Connection Auto"));
-	$notebook->append_page ($page3_win,gen_label_in_center  ("Connection Manual"));
-	$notebook->append_page ($page4_win,gen_label_in_center  ("Route Select"));
-
-	
-	$notebook->signal_connect( 'switch-page'=> sub{ # rebulid the current page		
-		$self->object_add_attribute ("process_notebook","currentpage",$_[2]);	#save the new pagenumber
-		set_gui_status($self,"ref",1);	
-	});	
-	
-		
-	my $draw=custom_topology_diagram($self);
-	my $h1=gen_hpaned($notebook,.35,$draw);
-	
-	
-	my $v2=gen_vpaned($h1,.65,$infobox);
-	my $pronoc_dir	  = get_project_dir(); #mpsoc dir addr
-	my $target_dir= "$pronoc_dir/mpsoc/rtl/src_topology/";
+    my $notebook = gen_notebook();
+    $notebook->set_tab_pos ('left');
+    $notebook->set_scrollable(TRUE);
+    my $page0=take_node_num_page($self);
+    my $page1=take_instance_page($self);
+    my $page2=connection_page_auto($self,$info);
+    my $page3=connection_page($self,$info);
+    my $page4=routing_page_manual($self,$info);
+    my $page0_win = add_widget_to_scrolled_win($page0);
+    my $page1_win = add_widget_to_scrolled_win($page1);
+    my $page2_win = add_widget_to_scrolled_win($page2);
+    my $page3_win = add_widget_to_scrolled_win($page3);
+    my $page4_win = add_widget_to_scrolled_win($page4);
+    $notebook->append_page ($page0_win,gen_label_in_center  (" Nodes #"));
+    $notebook->append_page ($page1_win,gen_label_in_center  ("Instance"));
+    $notebook->append_page ($page2_win,gen_label_in_center  ("Connection Auto"));
+    $notebook->append_page ($page3_win,gen_label_in_center  ("Connection Manual"));
+    $notebook->append_page ($page4_win,gen_label_in_center  ("Route Select"));
+    $notebook->signal_connect( 'switch-page'=> sub{ # rebulid the current page
+        $self->object_add_attribute ("process_notebook","currentpage",$_[2]);    #save the new pagenumber
+        set_gui_status($self,"ref",1);
+    });
+    my $draw=custom_topology_diagram($self);
+    my $h1=gen_hpaned($notebook,.35,$draw);
+    my $v2=gen_vpaned($h1,.65,$infobox);
+    my $pronoc_dir      = get_project_dir(); #mpsoc dir addr
+    my $target_dir= "$pronoc_dir/mpsoc/rtl/src_topology/";
+    my $yml = def_image_button('icons/yaml.png','Load YAML');
+    set_tip($yml, "Read Custom NoC configuration from yaml file.");
     my ($entrybox,$entry ) =gen_save_load_widget (
-        $self, #the object 
+        $self, #the object
         "Topology name",#the label shown for setting configuration
-        'save_as',#the key name for saveing the setting configuration in object 
+        'save_as',#the key name for saveing the setting configuration in object
         'Custom NoC Topology',#the label full name show in tool tips
         $target_dir,#Where the generted RTL files are loacted. Undef if not aplicaple
         'soc',#check the given name match the SoC or mpsoc name rules
         'lib/netwmaker',#where the current configuration seting file is saved
         'NWM',#the extenstion given for configuration seting file
-		\&load_nwm,#refrence to load function
-		$info
+        \&load_nwm,#refrence to load function
+        $info
         );
-
-
-	my $generate = def_image_button('icons/gen.png','Generate');
-	my ($entrybox2,$entry2) = def_h_labeled_entry('Routing Alg. name:',undef);
-	
-	$entry2->signal_connect( 'changed'=> sub{
-		my $name=$entry2->get_text();
-		$self->object_add_attribute ("routing_name",undef,$name);	
-	});	
-
-	$main_table->attach_defaults ($v2  , 0, 12, 0,24);	
-	$main_table->attach ($entrybox,2, 4, 24,25,'expand','shrink',2,2);
-	$main_table->attach ($entrybox2,4, 6, 24,25,'expand','shrink',2,2);	
-	$main_table->attach ($generate, 6, 9, 24,25,'expand','shrink',2,2);
-
-	my $sc_win = add_widget_to_scrolled_win($main_table);	
-	
-	#setting for graphs
-	my $n=0;
+    my $generate = def_image_button('icons/gen.png','Generate');
+    my ($entrybox2,$entry2) = def_h_labeled_entry('Routing Alg. name:',undef);
+    $entry2->signal_connect( 'changed'=> sub{
+        my $name=$entry2->get_text();
+        $self->object_add_attribute ("routing_name",undef,$name);
+    });
+    $main_table->attach_defaults ($v2  , 0, 12, 0,24);
+    $main_table->attach ($yml,0, 2, 24,25,'expand','shrink',2,2);
+    $main_table->attach ($entrybox,2, 4, 24,25,'expand','shrink',2,2);
+    $main_table->attach ($entrybox2,4, 6, 24,25,'expand','shrink',2,2);
+    $main_table->attach ($generate, 6, 9, 24,25,'expand','shrink',2,2);
+    my $sc_win = add_widget_to_scrolled_win($main_table);
+    #setting for graphs
+    my $n=0;
     my $sample="sample$n";
-	$n++;
-	$self->object_add_attribute("id",undef,$n);
-	$self->object_add_attribute("active_setting",undef,undef);
-	$self->object_add_attribute_order("samples",$sample);
-	$self->object_add_attribute($sample,"color",1);
-	add_color_to_gd($self);
-	
-	$generate->signal_connect("clicked" => sub{ 
-		generate_topology($self,$info);
-	
-	});	
-		
-	
-	
-	#check soc status every 0.5 second. refresh device table if there is any changes 
-	Glib::Timeout->add (100, sub{ 
-	   
-		my ($state,$timeout)= get_gui_status($self);
-		
-		if ($timeout>0){
-			$timeout--;
-			set_gui_status($self,$state,$timeout);	
-			return TRUE;
-			
-		}
-		if($state eq "ideal"){
-			return TRUE;
-			 
-		}
-		
-		if($state eq "ref" || $state eq "redraw"){
-			
-			my $page_num=$self->object_get_attribute ("process_notebook","currentpage");
-			if($state eq "ref"){
-				if($page_num==0){
-					$page0->destroy;
-					$page0=take_node_num_page($self);
-					add_widget_to_scrolled_win($page0,$page0_win);
-					$page0_win->show_all;
-					
-				}
-				if($page_num==1){
-					$page1->destroy;
-					$page1=take_instance_page($self);
-					add_widget_to_scrolled_win($page1,$page1_win);
-					$page1_win->show_all;
-				}
-				if($page_num==2){
-					$page2->destroy;
-					$page2=connection_page_auto($self,$info);
-					add_widget_to_scrolled_win($page2,$page2_win);
-					$page2_win->show_all;
-				}
-				if($page_num==3){
-					$page3->destroy;
-					$page3=connection_page($self,$info);
-					add_widget_to_scrolled_win($page3,$page3_win);
-					$page3_win->show_all;
-				}
-				if($page_num==4){
-					$page4->destroy;
-					$page4=routing_page_manual($self,$info);
-					add_widget_to_scrolled_win($page4,$page4_win);
-					$page4_win->show_all;
-				}
-						
-			}			
-			
-			if($page_num==4  ){
-				$draw->destroy;
-				$draw = get_path_route_widgets($self,$info);
-				$h1 -> pack2($draw, TRUE, TRUE);       	
-				
-				
-			}else{
-				
-				$draw->destroy;
-				$draw=custom_topology_diagram($self);
-				$h1 -> pack2($draw, TRUE, TRUE);    
-			}			
-			my $saved_name=$self->object_get_attribute('save_as');
-		    $entry->set_text($saved_name)if(defined $saved_name);
-		    
-		    $saved_name = $self->object_get_attribute('routing_name');
-		    $entry2->set_text($saved_name) if(defined $saved_name);
-		    
-			set_gui_status($self,"ideal",0);
-			$main_table->show_all();	
-			
-			return TRUE;
-			 
-		}	
-		
-		#refresh GUI
-			
-		
-		$main_table->show_all();			
-		set_gui_status($self,"ideal",0);
-		
-		return TRUE;
-		
-	} );
-
-	return $sc_win;	
+    $n++;
+    $self->object_add_attribute("id",undef,$n);
+    $self->object_add_attribute("active_setting",undef,undef);
+    $self->object_add_attribute_order("samples",$sample);
+    $self->object_add_attribute($sample,"color",1);
+    add_color_to_gd($self);
+    $generate->signal_connect("clicked" => sub{
+        generate_topology($self,$info);
+    });
+    $yml->signal_connect("clicked" => sub{
+        Get_yaml_noc_conf($self,$info);
+    });
+    #check soc status every 0.5 second. refresh device table if there is any changes
+    Glib::Timeout->add (100, sub{
+        my ($state,$timeout)= get_gui_status($self);
+        if ($timeout>0){
+            $timeout--;
+            set_gui_status($self,$state,$timeout);
+            return TRUE;
+        }
+        if($state eq "ideal"){
+            return TRUE;
+        }
+        if($state eq "ref" || $state eq "redraw"){
+            my $page_num=$self->object_get_attribute ("process_notebook","currentpage");
+            if($state eq "ref"){
+                if($page_num==0){
+                    $page0->destroy;
+                    $page0=take_node_num_page($self);
+                    add_widget_to_scrolled_win($page0,$page0_win);
+                    $page0_win->show_all;
+                }
+                if($page_num==1){
+                    $page1->destroy;
+                    $page1=take_instance_page($self);
+                    add_widget_to_scrolled_win($page1,$page1_win);
+                    $page1_win->show_all;
+                }
+                if($page_num==2){
+                    $page2->destroy;
+                    $page2=connection_page_auto($self,$info);
+                    add_widget_to_scrolled_win($page2,$page2_win);
+                    $page2_win->show_all;
+                }
+                if($page_num==3){
+                    $page3->destroy;
+                    $page3=connection_page($self,$info);
+                    add_widget_to_scrolled_win($page3,$page3_win);
+                    $page3_win->show_all;
+                }
+                if($page_num==4){
+                    $page4->destroy;
+                    $page4=routing_page_manual($self,$info);
+                    add_widget_to_scrolled_win($page4,$page4_win);
+                    $page4_win->show_all;
+                }
+            }
+            if($page_num==4  ){
+                $draw->destroy;
+                $draw = get_path_route_widgets($self,$info);
+                $h1 -> pack2($draw, TRUE, TRUE);
+            }else{
+                $draw->destroy;
+                $draw=custom_topology_diagram($self);
+                $h1 -> pack2($draw, TRUE, TRUE);
+            }
+            my $saved_name=$self->object_get_attribute('save_as');
+            $entry->set_text($saved_name)if(defined $saved_name);
+            $saved_name = $self->object_get_attribute('routing_name');
+            $entry2->set_text($saved_name) if(defined $saved_name);
+            set_gui_status($self,"ideal",0);
+            $main_table->show_all();
+            return TRUE;
+        }
+        #refresh GUI
+        $main_table->show_all();
+        set_gui_status($self,"ideal",0);
+        return TRUE;
+    } );
+    return $sc_win;
 }
+1;
diff --git a/mpsoc/perl_gui/lib/perl/orcc.pl b/mpsoc/perl_gui/lib/perl/orcc.pl
index 6e1aed1..80bde5c 100644
--- a/mpsoc/perl_gui/lib/perl/orcc.pl
+++ b/mpsoc/perl_gui/lib/perl/orcc.pl
@@ -2,771 +2,570 @@
 use constant::boolean;
 use strict;
 use warnings;
-
 use FindBin;
 use lib $FindBin::Bin;
-
-
 use String::Scanf; # imports sscanf()
 
-
 sub select_orcc_generated_srcs {
-	my ($self)=@_;
-	#my $window = def_popwin_size(80,80,"Generate software using ORCC compiler",'percent');	
-	#my $table = def_table(10, 10, FALSE);
-	#$table->attach_defaults($infobox,0,20,$row,$row+1);
-	
-	#pass noc parameter to trace generator
-	my %p;
-	my $params_ref=$self->object_get_attribute('noc_param');
-	if(defined $params_ref ){
-		
-		$p{'noc_param'}=$params_ref;	
-	}
-	#pass mpsoc name to trace genrator
-	my $mpsoc_name=$self->object_get_attribute('mpsoc_name');
-	$p{'mpsoc_name'}=$mpsoc_name;
-	
-	#pass soc names to trace genrator
-	my ($NE, $NR, $RAw, $EAw, $Fw)=get_topology_info($self);	
+    my ($self)=@_;
+    #my $window = def_popwin_size(80,80,"Generate software using ORCC compiler",'percent');
+    #my $table = def_table(10, 10, FALSE);
+    #$table->attach_defaults($infobox,0,20,$row,$row+1);
+    #pass noc parameter to trace generator
+    my %p;
+    my $params_ref=$self->object_get_attribute('noc_param');
+    if(defined $params_ref ){
+        $p{'noc_param'}=$params_ref;
+    }
+    #pass mpsoc name to trace genrator
+    my $mpsoc_name=$self->object_get_attribute('mpsoc_name');
+    $p{'mpsoc_name'}=$mpsoc_name;
+    #pass soc names to trace genrator
+    my ($NE, $NR, $RAw, $EAw, $Fw)=get_topology_info($self);
     for (my $tile_num=0;$tile_num<$NE;$tile_num++){
         my ($soc_name,$num)= $self->mpsoc_get_tile_soc_name($tile_num);
         my $top=$self->mpsoc_get_soc($soc_name);
         if(defined $top){
-        	my @nis=get_NI_instance_list($top);
-        	my $inst_name=$top->top_get_def_of_instance($nis[0],'instance');
-        	$p{'ni_name'}{$tile_num}=$inst_name; 
-			$p{'soc_name'}{$tile_num}=$soc_name;
+            my @nis=get_NI_instance_list($top);
+            my $inst_name=$top->top_get_def_of_instance($nis[0],'instance');
+            $p{'ni_name'}{$tile_num}=$inst_name;
+            $p{'soc_name'}{$tile_num}=$soc_name;
         }
     }
-    
-    
-    
-        
-    
-    			
-	my $trace_gen= trace_gen_main('orcc',\%p);#,$window);	
-
-	#$window->add ($trace_gen);
-	#$window->show_all();
-	
-	return $trace_gen;
-	my $table;
-	
-	
-	
-	
-	$self->object_add_attribute("file_id",undef,0);
-	$self->object_add_attribute("trace_id",undef,0);
-	
-	
-	
-	
-	
-	my $col=0;
-	my $row=0;
-	my $add = def_image_button('icons/import.png',"Load");
-	set_tip($add,'Select ORCC generated CSV file');
-	
-	
-	$table->attach($add,$col,$col+1,$row,$row+1,'shrink','shrink',2,2);$col++;
-    my ($infobox,$info)= create_txview();   
-    
-    
-    
+    my $trace_gen= trace_gen_main('orcc',\%p);#,$window);
+    #$window->add ($trace_gen);
+    #$window->show_all();
+    return $trace_gen;
+    my $table;
+    $self->object_add_attribute("file_id",undef,0);
+    $self->object_add_attribute("trace_id",undef,0);
+    my $col=0;
+    my $row=0;
+    my $add = def_image_button('icons/import.png',"Load");
+    set_tip($add,'Select ORCC generated CSV file');
+    $table->attach($add,$col,$col+1,$row,$row+1,'shrink','shrink',2,2);$col++;
+    my ($infobox,$info)= create_txview();
     my $draw = def_image_button('icons/diagram.png');
-	set_tip($draw,'View Actor Connection Graph');
-	$table->attach($draw,$col,$col+1,$row,$row+1,'shrink','shrink',2,2);$col++;
-	$draw->signal_connect ( 'clicked'=> sub{
-		show_trace_diagram($self,'trace');
-	});
+    set_tip($draw,'View Actor Connection Graph');
+    $table->attach($draw,$col,$col+1,$row,$row+1,'shrink','shrink',2,2);$col++;
+    $draw->signal_connect ( 'clicked'=> sub{
+        show_trace_diagram($self,'trace');
+    });
     $row++;
     $col=0;
     my $map=actor_map($self,$info);
-	$table->attach_defaults($map,0,5,$row,$row+1);
-	
-	
-	my $i;	
-	for ($i=$row; $i<5; $i++){
-		
-		my $temp=gen_label_in_center(" ");
-		$table->attach_defaults ($temp, 0, 6 , $i, $i+1);
-	}
-	$row=$i;	
-	
-	
-	$col=5;
-	my $next=def_image_button('icons/right.png','Next');
-	$table->attach($next,$col,$col+1,$row,$row+1,'shrink','shrink',2,2);$col++;
-	
-	
-	
-	$add->signal_connect ( 'clicked'=> sub{
-		
- 		my $file;
+    $table->attach_defaults($map,0,5,$row,$row+1);
+    my $i;
+    for ($i=$row; $i<5; $i++){
+        my $temp=gen_label_in_center(" ");
+        $table->attach_defaults ($temp, 0, 6 , $i, $i+1);
+    }
+    $row=$i;
+    $col=5;
+    my $next=def_image_button('icons/right.png','Next');
+    $table->attach($next,$col,$col+1,$row,$row+1,'shrink','shrink',2,2);$col++;
+    $add->signal_connect ( 'clicked'=> sub{
+        my $file;
         my $dialog = gen_file_dialog('Select the ORCC generated CSV File','csv');
-            	
-        	
-        
-        	
-		
-
-        	if ( "ok" eq $dialog->run ) {
-            		$file = $dialog->get_filename;
-					load_orcc_csv($self,$file,$info);
+            if ( "ok" eq $dialog->run ) {
+                    $file = $dialog->get_filename;
+                    load_orcc_csv($self,$file,$info);
             }
-       		$dialog->destroy;	
-	});
-	
-	
-
-
+            $dialog->destroy;
+    });
 }
 
-
-
-
-
 sub load_orcc_file{
-	my($self,$tview)=@_;
- 		my $file;
+    my($self,$tview)=@_;
+        my $file;
         my $dialog = gen_file_dialog( undef,"csv");
-			
-        	if ( "ok" eq $dialog->run ) {
-            		$file = $dialog->get_filename;
-					load_orcc_csv($self,$file,$tview);
+            if ( "ok" eq $dialog->run ) {
+                    $file = $dialog->get_filename;
+                    load_orcc_csv($self,$file,$tview);
             }
-       		$dialog->destroy;	
+            $dialog->destroy;
 }
 
-
-
-
-
 sub load_orcc_csv{
-	my ($self,$file,$info)=@_;		
-
-	add_info($info,"Use $file for generating actors network\n");
-	unless (-e $file){
-		add_colored_info($info,"Cannot find $file\n",'red');
-		return;
-	} 	
-	
-	my $f_id=$self->object_get_attribute("file_id",undef);
-	my $t_id=$self->object_get_attribute("trace_id",undef);
-		
-	open my $in, "<:encoding(utf8)", $file or die "$file: $!";
-	my $sect=0;
-	my $net;
-	my @actors;
-	
-	my %chanels;
-	
-	while (my $line = <$in>) {
-    	chomp $line;
-    	$line =~ s/[^\S\n]+//g; #remove space
-    	
-    	if ($line =~ /Name,Package,Actors,Connections/){
-    		$sect=1;
-    		next;	
-    	}
-    	if ($line =~ /Name,Incoming,Outgoing,Inputs,Outputs/){
-    		$sect=2;
-    		next;	
-    	}
-    	if ($line =~ /Source,SrcPort,Target,TgtPort/){
-    		$sect=3;
-    		next;	
-    	}
-    	if($sect==1){
-    		my @fileds=split(/\s*,\s*/,$line);
-    		if(defined $fileds[0]){$net=$fileds[0] if($fileds[0]=~/^\w/);}
-    	}
-    	if($sect==2){
-			my @fileds=split(/\s*,\s*/,$line);
-			if(defined $fileds[0]){ push(@actors,$fileds[0]) if($fileds[0]=~/^\w/);}
-    	}
-    	if($sect==3){
-    		my @fileds=split(/\s*,\s*/,$line);
-    		if(defined $fileds[0]){
-    			my $src=$fileds[0];
-    			my $src_port=$fileds[1];
-    			my $dest=$fileds[2];
-    			my $dst_port=$fileds[3];
-    			my $buff_Size=$fileds[4];   
-    			
-    			 			
-    			$chanels{"${src}:$src_port"}= (defined $chanels{"${src}:$src_port"})? $chanels{"${src}:$src_port"}+1 : 0;  
-    			my $cc=$chanels{"${src}:$src_port"};
-    			#print "find chanel for  ** ${src}_$src_port -> ${dest}_$dst_port**: $cc\n";
-    			  			
-    			add_trace($self, "${net}:${f_id}:","raw",$t_id, $src,$dest, 1,$file, $src_port,$dst_port,$buff_Size,$chanels{"${src}:$src_port"},0);	
-    			#print "add_trace($self, \"${net}:${f_id}:\",\"raw\",$t_id, $src,$dest, 1,$file, $src_port,$dst_port,$buff_Size,$chanels{\"${src}:$src_port\"});\n";	
-    			$t_id++;
-    		}
-    		
-    	}		
-    	$self->set_gui_status('ref',0);
-    	
-	}	
-	
-	my $num=scalar @actors;
-	if($num==0){
-		add_colored_info($info,"Could not find any actor in $file\n",'red');
-		return;
-	}
-	add_info($info,"total of $num actors have found:\n\t");
-	my $n=1;
-	foreach my $act (@actors){
-		add_colored_info($info,"$n-$act ",'blue');
-		$n++;
-	}
-	add_info($info,"\n");
-	
-	$f_id++;
-	$self->object_add_attribute("trace_id",undef,$t_id);
-	$self->object_add_attribute("file_id",undef,$f_id);
-	
-	
-	
+    my ($self,$file,$info)=@_;
+    add_info($info,"Use $file for generating actors network\n");
+    unless (-e $file){
+        add_colored_info($info,"Cannot find $file\n",'red');
+        return;
+    }
+    my $f_id=$self->object_get_attribute("file_id",undef);
+    my $t_id=$self->object_get_attribute("trace_id",undef);
+    open my $in, "<:encoding(utf8)", $file or die "$file: $!";
+    my $sect=0;
+    my $net;
+    my @actors;
+    my %chanels;
+    while (my $line = <$in>) {
+        chomp $line;
+        $line =~ s/[^\S\n]+//g; #remove space
+        if ($line =~ /Name,Package,Actors,Connections/){
+            $sect=1;
+            next;
+        }
+        if ($line =~ /Name,Incoming,Outgoing,Inputs,Outputs/){
+            $sect=2;
+            next;
+        }
+        if ($line =~ /Source,SrcPort,Target,TgtPort/){
+            $sect=3;
+            next;
+        }
+        if($sect==1){
+            my @fileds=split(/\s*,\s*/,$line);
+            if(defined $fileds[0]){$net=$fileds[0] if($fileds[0]=~/^\w/);}
+        }
+        if($sect==2){
+            my @fileds=split(/\s*,\s*/,$line);
+            if(defined $fileds[0]){ push(@actors,$fileds[0]) if($fileds[0]=~/^\w/);}
+        }
+        if($sect==3){
+            my @fileds=split(/\s*,\s*/,$line);
+            if(defined $fileds[0]){
+                my $src=$fileds[0];
+                my $src_port=$fileds[1];
+                my $dest=$fileds[2];
+                my $dst_port=$fileds[3];
+                my $buff_Size=$fileds[4];
+                $chanels{"${src}:$src_port"}= (defined $chanels{"${src}:$src_port"})? $chanels{"${src}:$src_port"}+1 : 0;
+                my $cc=$chanels{"${src}:$src_port"};
+                #print "find chanel for  ** ${src}_$src_port -> ${dest}_$dst_port**: $cc\n";
+                add_trace($self, "${net}:${f_id}:","raw",$t_id, $src,$dest, 1,$file, $src_port,$dst_port,$buff_Size,$chanels{"${src}:$src_port"},0);
+                #print "add_trace($self, \"${net}:${f_id}:\",\"raw\",$t_id, $src,$dest, 1,$file, $src_port,$dst_port,$buff_Size,$chanels{\"${src}:$src_port\"});\n";
+                $t_id++;
+            }
+        }
+        $self->set_gui_status('ref',0);
+    }
+    my $num=scalar @actors;
+    if($num==0){
+        add_colored_info($info,"Could not find any actor in $file\n",'red');
+        return;
+    }
+    add_info($info,"total of $num actors have found:\n\t");
+    my $n=1;
+    foreach my $act (@actors){
+        add_colored_info($info,"$n-$act ",'blue');
+        $n++;
+    }
+    add_info($info,"\n");
+    $f_id++;
+    $self->object_add_attribute("trace_id",undef,$t_id);
+    $self->object_add_attribute("file_id",undef,$f_id);
 }
 
-
 sub update_merge_actor_list{
-	my ($self,$tview)=@_;	
-	
-	#delete old merge objects
+    my ($self,$tview)=@_;
+    #delete old merge objects
     remove_all_traces ($self,'merge');
-	
-	#add not mereged traces 
-	my $t_id=0;
-	my $ungrouped_ref= $self->object_get_attribute("grouping",'ungrouped');
-	my @ungrouped = (defined $ungrouped_ref)? @{$ungrouped_ref}:[];		
-	foreach my $actor (@ungrouped){
-		my @injectors= get_all_source_traces_of_actr($self,$actor,'raw');
-		foreach my $inject (@injectors) {
-			my ($src,$dst, $Mbytes, $file_id, $file_name,$init_weight,$min_pck, $max_pck,  $burst, $injct_rate, $injct_rate_var,$src_port,$dst_port,$buff_size,$chanel,$vc,$class
-			)=get_trace($self,'raw',$inject);
-			my $tdst=$self->get_item_group_name('grouping',$dst);
-			$dst_port=0 if (!defined $dst_port);
-			if($tdst ne $dst){					
-					$dst_port="${dst}_$dst_port";
-			}
-								
-			add_trace($self, "$file_id",'merge',$t_id, $src,$tdst,$Mbytes,$file_name, $src_port,$dst_port,$buff_size,$chanel,$vc,$class);
-			if(defined $min_pck){
-				add_trace_extra($self, "$file_id",'merge',$t_id,$min_pck, $max_pck,  $burst, $injct_rate, $injct_rate_var );						
-			}
-			$t_id++;
-		}		
-		
-	}
-	
-	#update group  list
-	my $group_num=$self->object_get_attribute("grouping",'group_num');
-	my $gname=$self->object_get_attribute("grouping",'group_name_root');
-	for(my $i=0;$i<$group_num;$i=$i+1){
-		my $gref = $self->object_get_attribute("grouping","$gname($i)");
-		next if(! defined $gref);
-		my @grouped =  @{$gref};
-		next if (scalar @grouped == 0);
-			
-		
-		my $merged_actor =  $self->object_get_attribute('grouping',"group($i)"."_name");
-		$merged_actor = "group($i)" if(!defined $merged_actor);		
-		#my $tile =get_task_give_tile($self,$merged_actor);
-	#	print "my $tile =get_task_give_tile($self,$merged_actor);\n";
-		#my $tile_id=get_tile_id($self,$merged_actor);
-		#my $tile_id = tile_id_number($tile);
-		
-		#add_info($tview,"Generating $merged_actor.c grouped actor file from: @grouped  actors\n");
-	 
-	
-		my $mpsoc_name=$self->object_get_attribute('mpsoc_name');
-		$mpsoc_name = 'tmp' if (!defined $mpsoc_name);
-		my $target_dir  = "$ENV{'PRONOC_WORK'}/MPSOC/$mpsoc_name";
-		
-		#setp 1 : find local communication ports in merged actor
-		foreach my $actor (@grouped) {
-			my @injectors= get_all_source_traces_of_actr($self,$actor,'raw');
-			#Where does it transfer?
-			foreach my $inject (@injectors) {
-				my ($src,$dst, $Mbytes, $file_id, $file_name,$init_weight,$min_pck, $max_pck,  $burst, $injct_rate, $injct_rate_var,$src_port,$dst_port,$buff_size,$chanel,$vc,$class
-				)=get_trace($self,'raw',$inject);
-				$dst_port=0 if (!defined $dst_port);
-				$src_port=0 if (!defined $src_port);
-				my $dst_actor=$dst;
-				if (check_scolar_exist_in_array($dst,\@grouped)){
-					#print "$src $src_port is locally connected to $dst $dst_port\n";
-					 $self->object_add_attribute("locally_connected","${dst}_${dst_port}","${src}_${src_port}");
-				}
-				else
-				{
-					#my ($net,$num,$name)=split(':',$src);
-					my $merge_src="$merged_actor";
-					$src_port="${src}_$src_port";
-								
-					my $file="$target_dir/sw/$actor.c";
-										
-					my $tdst=$self->get_item_group_name('grouping',$dst);
-				#	($dnet,$dnum,$dname)=split(':',$tdst);
-					if($tdst ne $dst){
-							#my ($dnet,$dnum,$dname)=split(':',$dst);
-							$dst_port="${dst}_$dst_port";
-					}					
-					
-					add_trace($self, "$file_id",'merge',$t_id, $merge_src,$tdst, $Mbytes,$file, $src_port,$dst_port,$buff_size,$chanel,$vc,$class);
-					if(defined $min_pck){
-						add_trace_extra($self, "$file_id",'merge',$t_id,$min_pck, $max_pck,  $burst, $injct_rate, $injct_rate_var );						
-					}
-					$t_id++;	
-				}#else
-			}#$ink=ject
-		}#actor	
-	}		
+    #add not mereged traces
+    my $t_id=0;
+    my $ungrouped_ref= $self->object_get_attribute("grouping",'ungrouped');
+    my @ungrouped = (defined $ungrouped_ref)? @{$ungrouped_ref}:[];
+    foreach my $actor (@ungrouped){
+        my @injectors= get_all_source_traces_of_actr($self,$actor,'raw');
+        foreach my $inject (@injectors) {
+            my ($src,$dst, $Mbytes, $file_id, $file_name,$init_weight,$min_pck, $max_pck,  $burst, $injct_rate, $injct_rate_var,$src_port,$dst_port,$buff_size,$chanel,$vc,$class
+            )=get_trace($self,'raw',$inject);
+            my $tdst=$self->get_item_group_name('grouping',$dst);
+            $dst_port=0 if (!defined $dst_port);
+            if($tdst ne $dst){
+                    $dst_port="${dst}_$dst_port";
+            }
+            add_trace($self, "$file_id",'merge',$t_id, $src,$tdst,$Mbytes,$file_name, $src_port,$dst_port,$buff_size,$chanel,$vc,$class);
+            if(defined $min_pck){
+                add_trace_extra($self, "$file_id",'merge',$t_id,$min_pck, $max_pck,  $burst, $injct_rate, $injct_rate_var );
+            }
+            $t_id++;
+        }
+    }
+    #update group  list
+    my $group_num=$self->object_get_attribute("grouping",'group_num');
+    my $gname=$self->object_get_attribute("grouping",'group_name_root');
+    for(my $i=0;$i<$group_num;$i=$i+1){
+        my $gref = $self->object_get_attribute("grouping","$gname($i)");
+        next if(! defined $gref);
+        my @grouped =  @{$gref};
+        next if (scalar @grouped == 0);
+        my $merged_actor =  $self->object_get_attribute('grouping',"group($i)"."_name");
+        $merged_actor = "group($i)" if(!defined $merged_actor);
+        #my $tile =get_task_give_tile($self,$merged_actor);
+    #    print "my $tile =get_task_give_tile($self,$merged_actor);\n";
+        #my $tile_id=get_tile_id($self,$merged_actor);
+        #my $tile_id = tile_id_number($tile);
+        #add_info($tview,"Generating $merged_actor.c grouped actor file from: @grouped  actors\n");
+        my $mpsoc_name=$self->object_get_attribute('mpsoc_name');
+        $mpsoc_name = 'tmp' if (!defined $mpsoc_name);
+        my $target_dir  = "$ENV{'PRONOC_WORK'}/MPSOC/$mpsoc_name";
+        #setp 1 : find local communication ports in merged actor
+        foreach my $actor (@grouped) {
+            my @injectors= get_all_source_traces_of_actr($self,$actor,'raw');
+            #Where does it transfer?
+            foreach my $inject (@injectors) {
+                my ($src,$dst, $Mbytes, $file_id, $file_name,$init_weight,$min_pck, $max_pck,  $burst, $injct_rate, $injct_rate_var,$src_port,$dst_port,$buff_size,$chanel,$vc,$class
+                )=get_trace($self,'raw',$inject);
+                $dst_port=0 if (!defined $dst_port);
+                $src_port=0 if (!defined $src_port);
+                my $dst_actor=$dst;
+                if (check_scolar_exist_in_array($dst,\@grouped)){
+                    #print "$src $src_port is locally connected to $dst $dst_port\n";
+                    $self->object_add_attribute("locally_connected","${dst}_${dst_port}","${src}_${src_port}");
+                }
+                else
+                {
+                    #my ($net,$num,$name)=split(':',$src);
+                    my $merge_src="$merged_actor";
+                    $src_port="${src}_$src_port";
+                    my $file="$target_dir/sw/$actor.c";
+                    my $tdst=$self->get_item_group_name('grouping',$dst);
+                #    ($dnet,$dnum,$dname)=split(':',$tdst);
+                    if($tdst ne $dst){
+                            #my ($dnet,$dnum,$dname)=split(':',$dst);
+                            $dst_port="${dst}_$dst_port";
+                    }
+                    add_trace($self, "$file_id",'merge',$t_id, $merge_src,$tdst, $Mbytes,$file, $src_port,$dst_port,$buff_size,$chanel,$vc,$class);
+                    if(defined $min_pck){
+                        add_trace_extra($self, "$file_id",'merge',$t_id,$min_pck, $max_pck,  $burst, $injct_rate, $injct_rate_var );
+                    }
+                    $t_id++;
+                }#else
+            }#$ink=ject
+        }#actor
+    }
 }
 
-
-
 sub get_port_num{
-	my ($self,$hash_ref,$actor,$port_name,$chanel) =@_;
+    my ($self,$hash_ref,$actor,$port_name,$chanel) =@_;
     return undef if(!defined $hash_ref);
     my %hash = %{$hash_ref};
-    
-    my $port_num =(defined $chanel)?  $hash{$actor}{$port_name}{$chanel} :  $hash{$actor}{$port_name};			
-	if(!defined $port_num){
-		#its a merged actor
-		my $merge_actor=$self->get_item_group_name('grouping',$actor);
-		#my($net,$num,$name)=split(':',$merge_actor);
-		my $merge_port="${actor}_$port_name";
-		return $hash{$merge_actor}{$merge_port}{$chanel} if(defined  $chanel);
-		return $hash{$merge_actor}{$merge_port};		
-	}	  
-	return $port_num;  
+    my $port_num =(defined $chanel)?  $hash{$actor}{$port_name}{$chanel} :  $hash{$actor}{$port_name};
+    if(!defined $port_num){
+        #its a merged actor
+        my $merge_actor=$self->get_item_group_name('grouping',$actor);
+        #my($net,$num,$name)=split(':',$merge_actor);
+        my $merge_port="${actor}_$port_name";
+        return $hash{$merge_actor}{$merge_port}{$chanel} if(defined  $chanel);
+        return $hash{$merge_actor}{$merge_port};
+    }
+    return $port_num;
 }
 
-
-
-
-
-
-
 sub get_fifo_list{
-	my ($self)=@_;
-	my %fifos;	
-	
-	my ($NE, $NR, $RAw, $EAw, $Fw)=get_topology_info($self);	
-    for (my $tile_num=0;$tile_num<$NE;$tile_num++){	
-		my $actor=get_task_assigned_to_tile($self,$tile_num); 
-		next if(!defined $actor);
-		my $fifo_num=0;
-		my $ref = $self->get_items_in_a_group("grouping",$actor);
-		my @merge_actors = (defined $ref)? @{$ref} : ($actor);	
-		foreach my $actor (@merge_actors){
-			my @injectors= get_all_source_traces_of_actr($self,$actor,'raw');
-			foreach my $inject (@injectors) {
-				my ($src,$dst, $Mbytes, $file_id, $file_name,$init_weight,$min_pck, $max_pck,  $burst, $injct_rate, $injct_rate_var,$src_port,$dst_port,$buff_size,$chanel,$vc,$class
-				)=get_trace($self,'raw',$inject);				
-					
-				$fifos{"${actor}_${src_port}"}{'size'}=$buff_size;	
-				$fifos{"$actor"}{'file'}="$file_name";
-				$fifos{"${actor}_${src_port}"}{'fifo_num'}=$fifo_num;
-				$fifos{"${actor}_${src_port}"}{'chanel_num'}= 0 if(!defined $fifos{"${actor}_${src_port}"}{'chanel_num'});
-				$fifos{"${actor}_${src_port}"}{'chanel_num'}++;
-				$fifo_num++;
-				$fifos{"tile_$tile_num"}{'fifo_num'}=$fifo_num;
-			}
-		}
+    my ($self)=@_;
+    my %fifos;
+    my ($NE, $NR, $RAw, $EAw, $Fw)=get_topology_info($self);
+    for (my $tile_num=0;$tile_num<$NE;$tile_num++){
+        my $actor=get_task_assigned_to_tile($self,$tile_num);
+        next if(!defined $actor);
+        my $fifo_num=0;
+        my $ref = $self->get_items_in_a_group("grouping",$actor);
+        my @merge_actors = (defined $ref)? @{$ref} : ($actor);
+        foreach my $actor (@merge_actors){
+            my @injectors= get_all_source_traces_of_actr($self,$actor,'raw');
+            foreach my $inject (@injectors) {
+                my ($src,$dst, $Mbytes, $file_id, $file_name,$init_weight,$min_pck, $max_pck,  $burst, $injct_rate, $injct_rate_var,$src_port,$dst_port,$buff_size,$chanel,$vc,$class
+                )=get_trace($self,'raw',$inject);
+                $fifos{"${actor}_${src_port}"}{'size'}=$buff_size;
+                $fifos{"$actor"}{'file'}="$file_name";
+                $fifos{"${actor}_${src_port}"}{'fifo_num'}=$fifo_num;
+                $fifos{"${actor}_${src_port}"}{'chanel_num'}= 0 if(!defined $fifos{"${actor}_${src_port}"}{'chanel_num'});
+                $fifos{"${actor}_${src_port}"}{'chanel_num'}++;
+                $fifo_num++;
+                $fifos{"tile_$tile_num"}{'fifo_num'}=$fifo_num;
+            }
+        }
     }
-	
-	for (my $tile_num=0;$tile_num<$NE;$tile_num++){	
-		my $actor=get_task_assigned_to_tile($self,$tile_num); 
-		next if(!defined $actor);
-		my $fifo_num=$fifos{"tile_$tile_num"}{'fifo_num'};
-		$fifo_num= 0 if(!defined $fifo_num);
-		my $ref = $self->get_items_in_a_group("grouping",$actor);
-		my @merge_actors = (defined $ref)? @{$ref} : ($actor);
-		foreach my $actor (@merge_actors){		
-			my @sinkers =   get_all_dest_traces_of_actr ($self,$actor,'raw');
-				foreach my $sink (@sinkers){
-				my ($src,$dst, $Mbytes, $file_id, $file_name,$init_weight,$min_pck, $max_pck,  $burst, $injct_rate, $injct_rate_var,$src_port,$dst_port,$buff_size,$chanel,$vc,$class
-					)=get_trace($self,'raw',$sink);				    
-				
-					$fifos{"${actor}_${dst_port}"}{'size'}=$buff_size;	
-					$fifos{"$actor"}{'file'}="$file_name";
-					$fifos{"${actor}_${dst_port}"}{'chanel_num'}=$fifos{"${src}_${src_port}"}{'chanel_num'};
-					
-					my $src_fifo_name= $self->object_get_attribute("locally_connected","${actor}_${dst_port}");
-		    		if (defined $src_fifo_name){
-		    		#its localy connected.  src fifo num and dst fifo num are identical 
-		    			$fifos{"${actor}_${dst_port}"}{'fifo_num'}=$fifos{"$src_fifo_name"}{'fifo_num'};
-		    			#print "\$fifos{\"${actor}_${dst_port}\"}{'fifo_num'}=\$fifos{\"$src_fifo_name\"}{'fifo_num'}=$fifos{$src_fifo_name}{'fifo_num'};\n";
-		    		}else{
-		    			$fifos{"${actor}_${dst_port}"}{'fifo_num'}=$fifo_num;
-		    	 		$fifo_num++;
-		    	 		$fifos{"tile_$tile_num"}{'fifo_num'}=$fifo_num;
-		    		}			
-				
-				}
-			}	
+    for (my $tile_num=0;$tile_num<$NE;$tile_num++){
+        my $actor=get_task_assigned_to_tile($self,$tile_num);
+        next if(!defined $actor);
+        my $fifo_num=$fifos{"tile_$tile_num"}{'fifo_num'};
+        $fifo_num= 0 if(!defined $fifo_num);
+        my $ref = $self->get_items_in_a_group("grouping",$actor);
+        my @merge_actors = (defined $ref)? @{$ref} : ($actor);
+        foreach my $actor (@merge_actors){
+            my @sinkers =   get_all_dest_traces_of_actr ($self,$actor,'raw');
+                foreach my $sink (@sinkers){
+                my ($src,$dst, $Mbytes, $file_id, $file_name,$init_weight,$min_pck, $max_pck,  $burst, $injct_rate, $injct_rate_var,$src_port,$dst_port,$buff_size,$chanel,$vc,$class
+                    )=get_trace($self,'raw',$sink);
+                    $fifos{"${actor}_${dst_port}"}{'size'}=$buff_size;
+                    $fifos{"$actor"}{'file'}="$file_name";
+                    $fifos{"${actor}_${dst_port}"}{'chanel_num'}=$fifos{"${src}_${src_port}"}{'chanel_num'};
+                    my $src_fifo_name= $self->object_get_attribute("locally_connected","${actor}_${dst_port}");
+                    if (defined $src_fifo_name){
+                    #its localy connected.  src fifo num and dst fifo num are identical
+                        $fifos{"${actor}_${dst_port}"}{'fifo_num'}=$fifos{"$src_fifo_name"}{'fifo_num'};
+                        #print "\$fifos{\"${actor}_${dst_port}\"}{'fifo_num'}=\$fifos{\"$src_fifo_name\"}{'fifo_num'}=$fifos{$src_fifo_name}{'fifo_num'};\n";
+                    }else{
+                        $fifos{"${actor}_${dst_port}"}{'fifo_num'}=$fifo_num;
+                        $fifo_num++;
+                        $fifos{"tile_$tile_num"}{'fifo_num'}=$fifo_num;
+                    }
+                }
+            }
     }
-    
-  #  print Dumper (\%fifos);
-    
-    
-	return %fifos;
+    #  print Dumper (\%fifos);
+    return %fifos;
 }
 
-
 sub get_dest_chanel_from_orcc_file{
-	my ($actor_file,$actor,$dst_port)=@_;
-	#print ("-------------------\n");
-	my $str = "${actor}_${dst_port}->read_inds\\s*\\[";
-	my $txt = load_file($actor_file);
-	my $n = capture_number_after($str,$txt);
-	return $n;
+    my ($actor_file,$actor,$dst_port)=@_;
+    #print ("-------------------\n");
+    my $str = "${actor}_${dst_port}->read_inds\\s*\\[";
+    my $txt = load_file($actor_file);
+    my $n = capture_number_after($str,$txt);
+    return $n;
 }
 
-
 sub genereate_output_orcc{
-	my ($self,$tview,$window)=@_;
-	
-	# Code each actor destination port
-	
-
-	my %soc_names=%{$self->object_get_attribute('soc_name')};
+    my ($self,$tview,$window)=@_;
+    # Code each actor destination port
+    my %soc_names=%{$self->object_get_attribute('soc_name')};
     my %ni_names =%{$self->object_get_attribute('ni_name')};
-   
-	add_info($tview,"Generating grouped actor files\n");
-	my $group_num=$self->object_get_attribute("grouping",'group_num');
-	my $gname=$self->object_get_attribute("grouping",'group_name_root');
-	
-	
-	my $mpsoc_name=$self->object_get_attribute('mpsoc_name');
+    add_info($tview,"Generating grouped actor files\n");
+    my $group_num=$self->object_get_attribute("grouping",'group_num');
+    my $gname=$self->object_get_attribute("grouping",'group_name_root');
+    my $mpsoc_name=$self->object_get_attribute('mpsoc_name');
     my $target_dir  = "$ENV{'PRONOC_WORK'}/MPSOC/$mpsoc_name";
-	
     update_merge_actor_list ($self,$tview);
-	my %srcp_number=get_srcport_constant_list($self,'merge');
-	my %dstp_number=get_destport_constant_list($self,'merge');
-	
-	#print  "srcport:\n". Dumper(%srcp_number);
-	#print "dstport:\n".  Dumper(%dstp_number);
-	  
-	add_info($tview,"Generating source files\n");
-	
-	my $ungrouped_ref= $self->object_get_attribute("grouping",'ungrouped');
-	my @ungrouped = (defined $ungrouped_ref)? @{$ungrouped_ref}:[];		
-	
-	my %fifos=get_fifo_list($self);
-	
-	
-	my ($NE, $NR, $RAw, $EAw, $Fw)=get_topology_info($self);	
-    for (my $tile_num=0;$tile_num<$NE;$tile_num++){	
-		my $target_orccdir= "$target_dir/sw/tile${tile_num}/orcc";
-   		my $actor_tile ="tile($tile_num)";     			
-   		my $actor_tile_id=$tile_num;
-   		my $src_lib_file="$target_dir/sw/tile${actor_tile_id}/SOURCE_LIB"; 	
-   		my $actor=get_task_assigned_to_tile($self,$tile_num); 
+    my %srcp_number=get_srcport_constant_list($self,'merge');
+    my %dstp_number=get_destport_constant_list($self,'merge');
+    #print  "srcport:\n". Dumper(%srcp_number);
+    #print "dstport:\n".  Dumper(%dstp_number);
+    add_info($tview,"Generating source files\n");
+    my $ungrouped_ref= $self->object_get_attribute("grouping",'ungrouped');
+    my @ungrouped = (defined $ungrouped_ref)? @{$ungrouped_ref}:[];
+    my %fifos=get_fifo_list($self);
+    my ($NE, $NR, $RAw, $EAw, $Fw)=get_topology_info($self);
+    for (my $tile_num=0;$tile_num<$NE;$tile_num++){
+        my $target_orccdir= "$target_dir/sw/tile${tile_num}/orcc";
+        my $actor_tile ="tile($tile_num)";
+        my $actor_tile_id=$tile_num;
+        my $src_lib_file="$target_dir/sw/tile${actor_tile_id}/SOURCE_LIB";
+        my $actor=get_task_assigned_to_tile($self,$tile_num);
         my $soc_name=$soc_names{$actor_tile_id};
-		my $ni_name=$ni_names{$actor_tile_id};
+        my $ni_name=$ni_names{$actor_tile_id};
         my $max_dst_port_num=0;
-        
-        
-        
         #remove old orcc lib folder
-   		rmtree("$target_orccdir");
-              
-        #generate main.c  
-		my $r;
-		my @actors_file_names;
-   		my $main_c = "$target_dir/sw/tile${actor_tile_id}/main.c";
-   		unlink $main_c; #delete old main.c file 	
-		open my $fd, ">$main_c" or $r = "$!\n";
-   		if(defined $r) {
-    		add_colored_info($tview,"Could not open $main_c to write: $r",'red');
-			return;
-   		} 
-   		
-   		#generate source_lib file
-   		my $src_lib="SOURCE_LIB += $soc_name.c ";
-   		                  		
-   		
-   		if (!defined $actor){
-   			print $fd main_c_template($soc_name);   			
-   			close($fd);
-   			#write makefile source lib list file
-			save_file($src_lib_file,$src_lib);	
-   			next;
-   		}
-   	
-   	
-   		   		
-   		mkpath("$target_orccdir",1,0755);
-   	
-	   	print $fd autogen_warning();
-	   	print $fd get_license_header($main_c);  
-		
-		my $ref = $self->get_items_in_a_group("grouping",$actor);
-		my @merge_actors = (defined $ref)? @{$ref} : ($actor);
-		
-		my $main_include = "#include <stddef.h>
+        rmtree("$target_orccdir");
+        #generate main.c
+        my $r;
+        my @actors_file_names;
+        my $main_c = "$target_dir/sw/tile${actor_tile_id}/main.c";
+        unlink $main_c; #delete old main.c file
+        open my $fd, ">$main_c" or $r = "$!\n";
+        if(defined $r) {
+            add_colored_info($tview,"Could not open $main_c to write: $r",'red');
+            return;
+        }
+        #generate source_lib file
+        my $src_lib="SOURCE_LIB += $soc_name.c ";
+        if (!defined $actor){
+            print $fd main_c_template($soc_name);
+            close($fd);
+            #write makefile source lib list file
+            save_file($src_lib_file,$src_lib);
+            next;
+        }
+        mkpath("$target_orccdir",1,0755);
+        print $fd autogen_warning();
+        print $fd get_license_header($main_c);
+        my $ref = $self->get_items_in_a_group("grouping",$actor);
+        my @merge_actors = (defined $ref)? @{$ref} : ($actor);
+        my $main_include = "#include <stddef.h>
 #include \"$soc_name.h\"
 #include \"orcc/orcc_lib.h\"
 ";
-	
-		
-		
-		my $main_def=""; 
-		my $main_fifo_def="";
-		my $main_fifo_assign="";
-		my $main_fifo_rst_ptr="
+        my $main_def="";
+        my $main_fifo_def="";
+        my $main_fifo_assign="";
+        my $main_fifo_rst_ptr="
 volatile unsigned char iport_array[${ni_name}_NUM_VCs];
 volatile unsigned char oport_array[${ni_name}_NUM_VCs];
 unsigned int credit_buff[${ni_name}_NUM_VCs];
-
 void reset_all_fifo_ptr(void){\n";
-		
-		my $all_got_packet_function="";	
-		my $all_sent_packet_done_function="";	
-		my $all_check_packet_function="";
-		my $all_update_credit=""; 
-		my $all_init_actor="";
-		my $all_run_actor="";
-		my $actors_str='';
-	
-		
-		
-		#start generation
-		
-		
-		foreach my $actor (@merge_actors){
-			my $actor_file= get_actr_file_name($self,$actor,'raw');
-			my ($fname,$fpath,$fsuffix) = fileparse("$actor_file",qr"\..[^.]*$");
-   			my $target_actor_file="$target_orccdir/$fname.c";
-   			my $target_actor_header="$target_orccdir/$fname.h";
-			open my $fc, ">$target_actor_file" or $r = "$!\n";
-			if(defined $r) {
-		    	add_colored_info($tview,"Could not open $target_actor_file to write: $r",'red');
-				return;
-			} 
-		    
-		    my $LH=uc "${fname}";
-			my $actor_h="#ifndef\t ${LH}_H\n\t#define\t${LH}_H\n\n"; 
-			my $schedul='';
-			my $Hw_fifo_define='' ;
-			my $transfer_str='';
-			my $sink_str='';
-			my $crdit_update='';
-			
-		
-		
-	
-		
-			my $actor_got_pck_func= "
-char ${actor}_got_packet_function( unsigned char iport, unsigned int v){	
+        my $all_got_packet_function="";
+        my $all_sent_packet_done_function="";
+        my $all_check_packet_function="";
+        my $all_update_credit="";
+        my $all_init_actor="";
+        my $all_run_actor="";
+        my $actors_str='';
+        #start generation
+        foreach my $actor (@merge_actors){
+            my $actor_file= get_actr_file_name($self,$actor,'raw');
+            my ($fname,$fpath,$fsuffix) = fileparse("$actor_file",qr"\..[^.]*$");
+            my $target_actor_file="$target_orccdir/$fname.c";
+            my $target_actor_header="$target_orccdir/$fname.h";
+            open my $fc, ">$target_actor_file" or $r = "$!\n";
+            if(defined $r) {
+                add_colored_info($tview,"Could not open $target_actor_file to write: $r",'red');
+                return;
+            }
+            my $LH=uc "${fname}";
+            my $actor_h="#ifndef\t ${LH}_H\n\t#define\t${LH}_H\n\n";
+            my $schedul='';
+            my $Hw_fifo_define='' ;
+            my $transfer_str='';
+            my $sink_str='';
+            my $crdit_update='';
+            my $actor_got_pck_func= "
+char ${actor}_got_packet_function( unsigned char iport, unsigned int v){
 ";
-			my $actor_update_credit= "
+            my $actor_update_credit= "
 char ${actor}_update_credit (unsigned int credit_port,unsigned int credit_value){
 ";
-
-			my $actor_check_pck_func= "
+            my $actor_check_pck_func= "
 char ${actor}_check_packet_function (unsigned char iport,unsigned int size){
-";	
-
-			my $actor_sent_pck_done_func= "
+";
+            my $actor_sent_pck_done_func= "
 char ${actor}_sent_packet_done_function (unsigned char oport){
-";	
-
-			my $actor_init="
-void ${actor}_init_actor (schedinfo_t * si) { 	
 ";
-	
-			my $actor_local_connect;
-			
-			#schedular function 
-		
-	    	$schedul ="
-			${actor}_scheduler(si);"; 
-		
-			#For each actor which is mapped to this tile, we need to find all the traces going in and out to this tile 
-			#1- get the actor generated C file name:
-			
-			#push(@actors_file_names,      $actor_file);	   
-			#2- where it mapped?
-			#		my $actor_tile = $self->object_get_attribute("MAP_TILE",$actor);
-			#		my $actor_tile_id=get_tile_id($self,$actor);
-			#3- How many traces it transfers?
-		
-			my @injectors= get_all_source_traces_of_actr($self,$actor,'raw');
-		
-			#4- Where does it transffer?
-			foreach my $inject (@injectors) {
-				my ($src,$dst, $Mbytes, $file_id, $file_name,$init_weight,$min_pck, $max_pck,  $burst, $injct_rate, $injct_rate_var,$src_port,$dst_port,$buff_size,$chanel,$vc,$class
-				)=get_trace($self,'raw',$inject);				
-						
-				$vc= 0 if(!defined $vc);
-				$class= 0 if(!defined $class);
-				
-				#my $dst_tile = $self->object_get_attribute("MAP_TILE",$dst_actor);
-				my $dst_actor=$self->get_item_group_name('grouping',$dst);
-				my $dst_tile = get_task_give_tile($self,$dst_actor);
-				#my $dst_tile_id=get_tile_id($self,$dst_actor);				
-				my $dst_tile_id=tile_id_number($dst_tile);
-				
-				
-				if($dst_tile eq $actor_tile){
-					# this trace is connected locally in one tile
-					#my $rr="\t\t${dst}_$dst_port->read_inds[$chanel]= ${src}_${src_port}->write_ind;\n";
-					#$actor_local_connect=(defined $actor_local_connect)? $actor_local_connect.$rr:$rr;
-					next;					
-				}
-				
-				#5-Now generate all transfer functions (add inject ports) 	
-				#my ($net,$num,$name)=split(':',$actor);				
-				#print "dstp_number{$dst}{$dst_port}= $dstp_number{$dst}{$dst_port};\n";				
-				
-				my $srcportnum =  get_port_num($self,\%srcp_number,$src,$src_port,$chanel);
-				my $dstportnum =  get_port_num($self,\%dstp_number,$dst,$dst_port); 
-				
-		
-				if(!defined $dstportnum){				    
-				    print Dumper (\$self);
-					print Dumper (\%dstp_number);
-					print "my $dstportnum = get_port_num($self,\%dstp_number,$dst,$dst_port);\n"; 
-					print "***********************fix me**********\n";
-					exit();					
-				}
-		
-		
-	
-				if($chanel==0){			
-					$Hw_fifo_define=$Hw_fifo_define."	
-//	transfer ${src_port} port definitions:	
+            my $actor_init="
+void ${actor}_init_actor (schedinfo_t * si) {
+";
+            my $actor_local_connect;
+            #schedular function
+            $schedul ="
+            ${actor}_scheduler(si);";
+            #For each actor which is mapped to this tile, we need to find all the traces going in and out to this tile
+            #1- get the actor generated C file name:
+            #push(@actors_file_names,      $actor_file);
+            #2- where it mapped?
+            #        my $actor_tile = $self->object_get_attribute("MAP_TILE",$actor);
+            #        my $actor_tile_id=get_tile_id($self,$actor);
+            #3- How many traces it transfers?
+            my @injectors= get_all_source_traces_of_actr($self,$actor,'raw');
+            #4- Where does it transffer?
+            foreach my $inject (@injectors) {
+                my ($src,$dst, $Mbytes, $file_id, $file_name,$init_weight,$min_pck, $max_pck,  $burst, $injct_rate, $injct_rate_var,$src_port,$dst_port,$buff_size,$chanel,$vc,$class
+                )=get_trace($self,'raw',$inject);
+                $vc= 0 if(!defined $vc);
+                $class= 0 if(!defined $class);
+                #my $dst_tile = $self->object_get_attribute("MAP_TILE",$dst_actor);
+                my $dst_actor=$self->get_item_group_name('grouping',$dst);
+                my $dst_tile = get_task_give_tile($self,$dst_actor);
+                #my $dst_tile_id=get_tile_id($self,$dst_actor);
+                my $dst_tile_id=tile_id_number($dst_tile);
+                if($dst_tile eq $actor_tile){
+                    # this trace is connected locally in one tile
+                    #my $rr="\t\t${dst}_$dst_port->read_inds[$chanel]= ${src}_${src_port}->write_ind;\n";
+                    #$actor_local_connect=(defined $actor_local_connect)? $actor_local_connect.$rr:$rr;
+                    next;
+                }
+                #5-Now generate all transfer functions (add inject ports)
+                #my ($net,$num,$name)=split(':',$actor);
+                #print "dstp_number{$dst}{$dst_port}= $dstp_number{$dst}{$dst_port};\n";
+                my $srcportnum =  get_port_num($self,\%srcp_number,$src,$src_port,$chanel);
+                my $dstportnum =  get_port_num($self,\%dstp_number,$dst,$dst_port);
+                if(!defined $dstportnum){
+                    print Dumper (\$self);
+                    print Dumper (\%dstp_number);
+                    print "my $dstportnum = get_port_num($self,\%dstp_number,$dst,$dst_port);\n";
+                    print "***********************fix me**********\n";
+                    exit();
+                }
+                if($chanel==0){
+                    $Hw_fifo_define=$Hw_fifo_define."
+//    transfer ${src_port} port definitions:
 #define ${src_port}_w  $init_weight
-#define ${src_port}_v  $vc				
+#define ${src_port}_v  $vc
 #define ${src_port}_class_num  $class
 #define ${src_port}_queue_pointer (unsigned int)&tokens_${src_port}[0]
-#define ${src_port}_queue_size_in_byte  (SIZE_${src_port} << ${actor}_${src_port}_size_shift)	
-#define ${src_port}_end_index   index_${src_port} 
-
+#define ${src_port}_queue_size_in_byte  (SIZE_${src_port} << ${actor}_${src_port}_size_shift)
+#define ${src_port}_end_index   index_${src_port}
 ";
-
-					#$actor_init.="\t${actor}_${src_port}->write_ind=0;\n";
-
-				}
-	
-				$Hw_fifo_define=$Hw_fifo_define."
-// ${src_port} read chanel ${chanel}	definition
-#define ${src_port}_ch${chanel}_dest_port_num $dstportnum  
+                    #$actor_init.="\t${actor}_${src_port}->write_ind=0;\n";
+                }
+                $Hw_fifo_define=$Hw_fifo_define."
+// ${src_port} read chanel ${chanel}    definition
+#define ${src_port}_ch${chanel}_dest_port_num $dstportnum
 #define ${src_port}_ch${chanel}_dest_phy_addr PHY_ADDR_ENDP_${dst_tile_id}
 #define ${src_port}_ch${chanel}_src_port_num   $srcportnum
 #define ${src_port}_ch${chanel}_start_index ${actor}_${src_port}->read_inds[$chanel]
 #define ${src_port}_ch${chanel}_start_index_in_byte ((${src_port}_ch${chanel}_start_index % SIZE_${src_port}) << ${actor}_${src_port}_size_shift)
-#define ${src_port}_ch${chanel}_has_data_to_send    (${src_port}_end_index > ${src_port}_ch${chanel}_start_index)	
-#define ${src_port}_ch${chanel}_data_to_send_size   (${src_port}_end_index - ${src_port}_ch${chanel}_start_index)	
+#define ${src_port}_ch${chanel}_has_data_to_send    (${src_port}_end_index > ${src_port}_ch${chanel}_start_index)
+#define ${src_port}_ch${chanel}_data_to_send_size   (${src_port}_end_index - ${src_port}_ch${chanel}_start_index)
 #define ${src_port}_ch${chanel}_send_data_size_in_byte   (${src_port}_ch${chanel}_data_to_send_size << ${actor}_${src_port}_size_shift)
- 
-
-static unsigned int ${src_port}_ch${chanel}_credit =  ${src_port}_queue_size_in_byte;	
+static unsigned int ${src_port}_ch${chanel}_credit =  ${src_port}_queue_size_in_byte;
 static unsigned int ${src_port}_ch${chanel}_send_data;
 ";
 #$actor_init.="\t${src_port}_ch${chanel}_credit =  ${src_port}_queue_size_in_byte;\n";
-				
-				#$actor_init.="\t${actor}_${src_port}->read_inds[$chanel]=0;\n";
-				
-				$transfer_str=$transfer_str."		
-	if(${src_port}_ch${chanel}_has_data_to_send){
-		// if the sent vc is not busy and the sent_done_isr is not asserted sent a new packet
-		if(${ni_name}_send_is_free(${src_port}_v) &&     (oport_array[${src_port}_v]==255) ){  //(${ni_name}_packet_is_sent(${src_port}_v)==0))        {	
-		
-			//ask NI to transfer the data   
-			if(transfer_manage (${src_port}_w, ${src_port}_v, ${src_port}_class_num,${src_port}_ch${chanel}_dest_port_num , ${src_port}_queue_pointer , ${src_port}_queue_size_in_byte, 
-			${src_port}_ch${chanel}_start_index_in_byte, ${src_port}_ch${chanel}_send_data_size_in_byte, ${src_port}_ch${chanel}_dest_phy_addr, ${src_port}_ch${chanel}_credit,${src_port}_ch${chanel}_src_port_num, & ${src_port}_ch${chanel}_send_data, & ${src_port}_ch${chanel}_credit )){
-							
-			}				
-		}//has data					 
-	}//not busy
-	";
-	
-				$actor_sent_pck_done_func=$actor_sent_pck_done_func."
-	
-	if(oport == ${src_port}_ch${chanel}_src_port_num){ 
-		${src_port}_ch${chanel}_start_index= ${src_port}_ch${chanel}_start_index+ (${src_port}_ch${chanel}_send_data>>${actor}_${src_port}_size_shift);			
-		#ifdef ORCC_DEBUG_EN
-		if (${src_port}_ch${chanel}_data_to_send_size >  SIZE_${src_port}){
-			printf (\"Error the waiting data in ${actor} ${src_port} quque (\%u) is larger than the queue size (\%u)\\n\",${src_port}_ch${chanel}_data_to_send_size,SIZE_${src_port} );			  
-		}	
-		#endif
-		return 1;
-	}	
-	
-	";
-	
-				$actor_update_credit =$actor_update_credit."	
-	if( credit_port  == ${src_port}_ch${chanel}_src_port_num){
-		${src_port}_ch${chanel}_credit += (credit_value << ${actor}_${src_port}_size_shift); //credit value in byte
-		#ifdef ORCC_DEBUG_EN
-		if (${src_port}_ch${chanel}_credit >  (SIZE_${src_port}    << ${actor}_${src_port}_size_shift    )){
-			printf (\"Error the credit counter in ${actor} ${src_port}_ch${chanel} (\%u) is larger than the queue size (\%u)\\n\",${src_port}_ch${chanel}_credit,SIZE_${src_port} );			  
-		}	
-		#endif		
-		return 1;
-	}	
+                #$actor_init.="\t${actor}_${src_port}->read_inds[$chanel]=0;\n";
+                $transfer_str=$transfer_str."
+    if(${src_port}_ch${chanel}_has_data_to_send){
+        // if the sent vc is not busy and the sent_done_isr is not asserted sent a new packet
+        if(${ni_name}_send_is_free(${src_port}_v) &&     (oport_array[${src_port}_v]==255) ){  //(${ni_name}_packet_is_sent(${src_port}_v)==0))        {
+            //ask NI to transfer the data
+            if(transfer_manage (${src_port}_w, ${src_port}_v, ${src_port}_class_num,${src_port}_ch${chanel}_dest_port_num , ${src_port}_queue_pointer , ${src_port}_queue_size_in_byte,
+            ${src_port}_ch${chanel}_start_index_in_byte, ${src_port}_ch${chanel}_send_data_size_in_byte, ${src_port}_ch${chanel}_dest_phy_addr, ${src_port}_ch${chanel}_credit,${src_port}_ch${chanel}_src_port_num, & ${src_port}_ch${chanel}_send_data, & ${src_port}_ch${chanel}_credit )){
+            }
+        }//has data
+    }//not busy
+    ";
+                $actor_sent_pck_done_func=$actor_sent_pck_done_func."
+    if(oport == ${src_port}_ch${chanel}_src_port_num){
+        ${src_port}_ch${chanel}_start_index= ${src_port}_ch${chanel}_start_index+ (${src_port}_ch${chanel}_send_data>>${actor}_${src_port}_size_shift);
+        #ifdef ORCC_DEBUG_EN
+        if (${src_port}_ch${chanel}_data_to_send_size >  SIZE_${src_port}){
+            printf (\"Error the waiting data in ${actor} ${src_port} quque (\%u) is larger than the queue size (\%u)\\n\",${src_port}_ch${chanel}_data_to_send_size,SIZE_${src_port} );
+        }
+        #endif
+        return 1;
+    }
+    ";
+                $actor_update_credit =$actor_update_credit."
+    if( credit_port  == ${src_port}_ch${chanel}_src_port_num){
+        ${src_port}_ch${chanel}_credit += (credit_value << ${actor}_${src_port}_size_shift); //credit value in byte
+        #ifdef ORCC_DEBUG_EN
+        if (${src_port}_ch${chanel}_credit >  (SIZE_${src_port}    << ${actor}_${src_port}_size_shift    )){
+            printf (\"Error the credit counter in ${actor} ${src_port}_ch${chanel} (\%u) is larger than the queue size (\%u)\\n\",${src_port}_ch${chanel}_credit,SIZE_${src_port} );
+        }
+        #endif
+        return 1;
+    }
 ";
-
-			}# end inject
-		
-		
-		
-		
-		#6-Where the packet comes from? we need to update the sender with the remaining credit 
-		my @sinkers =   get_all_dest_traces_of_actr ($self,$actor,'raw');
-		foreach my $sink (@sinkers){
-			my ($src,$dst, $Mbytes, $file_id, $file_name,$init_weight,$min_pck, $max_pck,  $burst, $injct_rate, $injct_rate_var,$src_port,$dst_port,$buff_size,$chanel,$vc,$class
-				)=get_trace($self,'raw',$sink);
-						
-			my $dst_chnl =get_dest_chanel_from_orcc_file($actor_file,$actor,$dst_port);	
-					
-			my $srcportnum =  get_port_num($self,\%srcp_number,$src,$src_port,$chanel); 
-			my $src_actor=$self->get_item_group_name('grouping',$src);
-			my $src_tile = get_task_give_tile($self,$src_actor);
-		    #my $src_tile_id=get_tile_id($self,$src);
-		    my $src_tile_id=tile_id_number($src_tile);
-		    	
-		    #print "my $srcportnum = get_port_num($self,\%srcp_number,$src,$src_port,$chanel);\n";
-				
-				if($src_tile eq $actor_tile){
-				
-					next;					
-				}
-												
-			if(!defined $srcportnum){				    
-				    print Dumper (\$self);
-					print Dumper (\%srcp_number);
-					print "my $srcportnum = get_port_num($self,\%srcp_number,$src,$src_port,$chanel);\n";
-					print "***********************fix me**********\n";
-					exit();					
-			}
-								
-			#7 We need to add sink ports 				
-			#save the input  port index before running the credit	
-#$actor_init.=\t${actor}_${dst_port}->read_inds[0]=0;			
+            }# end inject
+        #6-Where the packet comes from? we need to update the sender with the remaining credit
+        my @sinkers =   get_all_dest_traces_of_actr ($self,$actor,'raw');
+        foreach my $sink (@sinkers){
+            my ($src,$dst, $Mbytes, $file_id, $file_name,$init_weight,$min_pck, $max_pck,  $burst, $injct_rate, $injct_rate_var,$src_port,$dst_port,$buff_size,$chanel,$vc,$class
+                )=get_trace($self,'raw',$sink);
+            my $dst_chnl =get_dest_chanel_from_orcc_file($actor_file,$actor,$dst_port);
+            my $srcportnum =  get_port_num($self,\%srcp_number,$src,$src_port,$chanel);
+            my $src_actor=$self->get_item_group_name('grouping',$src);
+            my $src_tile = get_task_give_tile($self,$src_actor);
+            #my $src_tile_id=get_tile_id($self,$src);
+            my $src_tile_id=tile_id_number($src_tile);
+            #print "my $srcportnum = get_port_num($self,\%srcp_number,$src,$src_port,$chanel);\n";
+                if($src_tile eq $actor_tile){
+                    next;
+                }
+            if(!defined $srcportnum){
+                    print Dumper (\$self);
+                    print Dumper (\%srcp_number);
+                    print "my $srcportnum = get_port_num($self,\%srcp_number,$src,$src_port,$chanel);\n";
+                    print "***********************fix me**********\n";
+                    exit();
+            }
+            #7 We need to add sink ports
+            #save the input  port index before running the credit
+#$actor_init.=\t${actor}_${dst_port}->read_inds[0]=0;
 #$actor_init.=\t${actor}_${dst_port}->write_ind=0;
-
-			$actor_init =$actor_init."
+            $actor_init =$actor_init."
 \tread_${dst_port}();
-\tindex_${dst_port}_sender=index_$dst_port;			
+\tindex_${dst_port}_sender=index_$dst_port;
 ";
-		
-	my $dstportnum = get_port_num($self,\%dstp_number,$dst,$dst_port); 
-	$max_dst_port_num=$dstportnum if($dstportnum > $max_dst_port_num );
-			
-	$Hw_fifo_define=$Hw_fifo_define."
-//	Receiver port  ${dst_port} port definitions:
-static unsigned int index_${dst_port}_sender; 
-
+    my $dstportnum = get_port_num($self,\%dstp_number,$dst,$dst_port);
+    $max_dst_port_num=$dstportnum if($dstportnum > $max_dst_port_num );
+    $Hw_fifo_define=$Hw_fifo_define."
+//    Receiver port  ${dst_port} port definitions:
+static unsigned int index_${dst_port}_sender;
 #define ${dst_port}_credit_w  1
-#define ${dst_port}_credit_v  0   //Alternatively it can be another VC				
+#define ${dst_port}_credit_v  0   //Alternatively it can be another VC
 #define ${dst_port}_credit_class_num  0 //Alternatively it can be another class
 #define ${dst_port}_credit_dest_port  0 //0 is reserved for credit
 #define ${dst_port}_credit_pointer (unsigned int)&credit_send_buff
@@ -778,854 +577,609 @@ sub genereate_output_orcc{
 #define ${dst_port}_src_port_num  $srcportnum
 #define ${dst_port}_dst_port_num  $dstportnum
 #define ${dst_port}_queu_pointer (unsigned int)&tokens_${dst_port}[0]
-#define ${dst_port}_queue_size_in_byte  (SIZE_${dst_port} << ${actor}_${dst_port}_size_shift)	
-#define ${dst_port}_start_index_in_byte	((${actor}_${dst_port}->write_ind % SIZE_${dst_port})<< ${actor}_${dst_port}_size_shift)
+#define ${dst_port}_queue_size_in_byte  (SIZE_${dst_port} << ${actor}_${dst_port}_size_shift)
+#define ${dst_port}_start_index_in_byte    ((${actor}_${dst_port}->write_ind % SIZE_${dst_port})<< ${actor}_${dst_port}_size_shift)
 #define ${dst_port}_read_indx    ${actor}_${dst_port}->read_inds[$dst_chnl]
-#define ${dst_port}_data_num_to_process (${actor}_${dst_port}->write_ind -${dst_port}_read_indx) 
+#define ${dst_port}_data_num_to_process (${actor}_${dst_port}->write_ind -${dst_port}_read_indx)
 ";
-			
-			
-	$crdit_update=$crdit_update."
-	if( ${dst_port}_has_credit_to_send){
-		if(${ni_name}_send_is_free(${dst_port}_credit_v) && (oport_array[${dst_port}_credit_v]==255) ){  // (${ni_name}_packet_is_sent(${dst_port}_credit_v)==0)){
-			//credit_num  = (SIZE_${dst_port} - ${dst_port}_data_num_to_process)& 0xFFFF;
-			credit_num  = (index_$dst_port - index_${dst_port}_sender)& 0xFFFF;				
-			credit_send_buff= ( (${dst_port}_src_port_num <<16) |  credit_num ); // most significant 16 bits indicates the port, list  significant 16 bits are credit in word 
-			#ifdef ORCC_DEBUG_EN
-				if(${dst_port}_data_num_to_process > SIZE_${dst_port}){
-					printf(\"Error ${dst_port}_data_num_to_process (\%u) is larger than SIZE_${dst_port} (\%u)\\n\",${dst_port}_data_num_to_process,SIZE_${dst_port});
-				}
-			#endif
-			if( transfer_manage (${dst_port}_credit_w, ${dst_port}_credit_v, ${dst_port}_credit_class_num, ${dst_port}_credit_dest_port, ${dst_port}_credit_pointer, ${dst_port}_credit_size_in_byte, ${dst_port}_credit_start_index, ${dst_port}_credit_send_data_size_in_byte, ${dst_port}_credit_dest_phy_addr, 5,${dst_port}_credit_dest_port, &tmp1,&tmp2 ) ){
-				index_${dst_port}_sender=index_${dst_port};					
-			}		 
-		} 
-	}			
-	";
-	
-	$actor_got_pck_func=$actor_got_pck_func."
-	if (iport == ${dst_port}_dst_port_num){	
-		${ni_name}_receive (v, ${dst_port}_queu_pointer , ${dst_port}_queue_size_in_byte, ${dst_port}_start_index_in_byte);	
-		return 1; 
-	}				
+    $crdit_update=$crdit_update."
+    if( ${dst_port}_has_credit_to_send){
+        if(${ni_name}_send_is_free(${dst_port}_credit_v) && (oport_array[${dst_port}_credit_v]==255) ){  // (${ni_name}_packet_is_sent(${dst_port}_credit_v)==0)){
+            //credit_num  = (SIZE_${dst_port} - ${dst_port}_data_num_to_process)& 0xFFFF;
+            credit_num  = (index_$dst_port - index_${dst_port}_sender)& 0xFFFF;
+            credit_send_buff= ( (${dst_port}_src_port_num <<16) |  credit_num ); // most significant 16 bits indicates the port, list  significant 16 bits are credit in word
+            #ifdef ORCC_DEBUG_EN
+                if(${dst_port}_data_num_to_process > SIZE_${dst_port}){
+                    printf(\"Error ${dst_port}_data_num_to_process (\%u) is larger than SIZE_${dst_port} (\%u)\\n\",${dst_port}_data_num_to_process,SIZE_${dst_port});
+                }
+            #endif
+            if( transfer_manage (${dst_port}_credit_w, ${dst_port}_credit_v, ${dst_port}_credit_class_num, ${dst_port}_credit_dest_port, ${dst_port}_credit_pointer, ${dst_port}_credit_size_in_byte, ${dst_port}_credit_start_index, ${dst_port}_credit_send_data_size_in_byte, ${dst_port}_credit_dest_phy_addr, 5,${dst_port}_credit_dest_port, &tmp1,&tmp2 ) ){
+                index_${dst_port}_sender=index_${dst_port};
+            }
+        }
+    }
+    ";
+    $actor_got_pck_func=$actor_got_pck_func."
+    if (iport == ${dst_port}_dst_port_num){
+        ${ni_name}_receive (v, ${dst_port}_queu_pointer , ${dst_port}_queue_size_in_byte, ${dst_port}_start_index_in_byte);
+        return 1;
+    }
 ";
-	
-	$actor_check_pck_func =$actor_check_pck_func."	
-	if(iport==${dst_port}_dst_port_num){
-		${actor}_${dst_port}->write_ind = ${actor}_${dst_port}->write_ind + (size >> ${actor}_${dst_port}_size_shift);								
-		#ifdef ORCC_DEBUG_EN
-		unsigned int diff = ${actor}_${dst_port}->write_ind - ${dst_port}_read_indx;
-		if(diff > SIZE_${dst_port})\{
-			printf (\"Error in ${actor}_${dst_port}: Write_index(\%u) - Read_index(\%u) is larger than queue size (\%u)\\n\",${actor}_${dst_port}->write_ind , ${dst_port}_read_indx,SIZE_${dst_port});     
-		}
-		#endif
-		return 1; 		
-	}						
-	";
-	
-	
-	
-	
-	
-	
-	#print  "\$fifos{\"$name\"}{'file'}=$file_name\n";
-	#print "\$fifos ${name}_${dst_port}'size'=$buff_size;\n";	
-	
-				
-			
-		} #sink
-		
-	
-	
-	
+    $actor_check_pck_func =$actor_check_pck_func."
+    if(iport==${dst_port}_dst_port_num){
+        ${actor}_${dst_port}->write_ind = ${actor}_${dst_port}->write_ind + (size >> ${actor}_${dst_port}_size_shift);
+        #ifdef ORCC_DEBUG_EN
+        unsigned int diff = ${actor}_${dst_port}->write_ind - ${dst_port}_read_indx;
+        if(diff > SIZE_${dst_port})\{
+            printf (\"Error in ${actor}_${dst_port}: Write_index(\%u) - Read_index(\%u) is larger than queue size (\%u)\\n\",${actor}_${dst_port}->write_ind , ${dst_port}_read_indx,SIZE_${dst_port});
+        }
+        #endif
+        return 1;
+    }
+    ";
+    #print  "\$fifos{\"$name\"}{'file'}=$file_name\n";
+    #print "\$fifos ${name}_${dst_port}'size'=$buff_size;\n";
+        } #sink
 $actor_h=$actor_h."void ${actor}_initialize(schedinfo_t *);\n";
-$actor_h=$actor_h."void ${actor}_scheduler(schedinfo_t *);\n";		
-		
-$actor_h=$actor_h."char ${actor}_got_packet_function(unsigned char , unsigned int);\n";		
-$all_got_packet_function=$all_got_packet_function."\t\t\t\t${actor}_got_packet_function(iport,i);\n";		
+$actor_h=$actor_h."void ${actor}_scheduler(schedinfo_t *);\n";
+$actor_h=$actor_h."char ${actor}_got_packet_function(unsigned char , unsigned int);\n";
+$all_got_packet_function=$all_got_packet_function."\t\t\t\t${actor}_got_packet_function(iport,i);\n";
 $actor_got_pck_func=$actor_got_pck_func."
-	#ifdef ORCC_DEBUG_EN
-	printf(\"Wrong got pck port \%u\\n\",iport);
-	#endif
-	return 0;
-}	
+    #ifdef ORCC_DEBUG_EN
+    printf(\"Wrong got pck port \%u\\n\",iport);
+    #endif
+    return 0;
+}
 ";
-
 $actor_h=$actor_h."char ${actor}_check_packet_function(unsigned char,unsigned int);\n";
 $all_check_packet_function = $all_check_packet_function."\t\t\t\t${actor}_check_packet_function(iport,size);\n";
 $actor_check_pck_func=$actor_check_pck_func."
-	#ifdef ORCC_DEBUG_EN
-	printf(\"Wrong check pck  port \%u\\n\",iport);
-	#endif
-	return 0;
-}	
+    #ifdef ORCC_DEBUG_EN
+    printf(\"Wrong check pck  port \%u\\n\",iport);
+    #endif
+    return 0;
+}
 ";
 $actor_h=$actor_h."char ${actor}_sent_packet_done_function(unsigned char);\n";
 $all_sent_packet_done_function = $all_sent_packet_done_function."\t\t\t\t${actor}_sent_packet_done_function(oport);\n";
 $actor_sent_pck_done_func=$actor_sent_pck_done_func."
-	#ifdef ORCC_DEBUG_EN
-	printf(\"Wrong sent done  port \%u\\n\",oport);
-	#endif
-	return 0;
+    #ifdef ORCC_DEBUG_EN
+    printf(\"Wrong sent done  port \%u\\n\",oport);
+    #endif
+    return 0;
 }
 ";
 $actor_h=$actor_h."char ${actor}_update_credit(unsigned int, unsigned int);\n";
 $all_update_credit=$all_update_credit."\t\t\t\t${actor}_update_credit(credit_port,credit_value);\n";
-$actor_update_credit =$actor_update_credit."	
-	#ifdef ORCC_DEBUG_EN
-	printf(\"Wrong ${actor} Credit port \%u\\n\",credit_port);
-	#endif
-	return 0;
+$actor_update_credit =$actor_update_credit."
+    #ifdef ORCC_DEBUG_EN
+    printf(\"Wrong ${actor} Credit port \%u\\n\",credit_port);
+    #endif
+    return 0;
 }
-";		
-$actor_h=$actor_h."void ${actor}_init_actor(schedinfo_t *);\n";	
-$all_init_actor=$all_init_actor."\t${actor}_init_actor(&si);\n";	
+";
+$actor_h=$actor_h."void ${actor}_init_actor(schedinfo_t *);\n";
+$all_init_actor=$all_init_actor."\t${actor}_init_actor(&si);\n";
 $actor_init=$actor_init."
-
-	${actor}_initialize(si);
-
+    ${actor}_initialize(si);
 }
-";	
-
-$actor_h=$actor_h."void ${actor}_run_actor(schedinfo_t *);\n";	
-$all_run_actor=$all_run_actor."\t\t${actor}_run_actor(&si);\n";	
+";
+$actor_h=$actor_h."void ${actor}_run_actor(schedinfo_t *);\n";
+$all_run_actor=$all_run_actor."\t\t${actor}_run_actor(&si);\n";
 #$all_run_actor=$all_run_actor.$actor_local_connect if(defined $actor_local_connect);
-
-my $t = (length  $crdit_update > 10  )? "unsigned int tmp1,tmp2,credit_num,credit_send_buff;" : ""; 
-
+my $t = (length  $crdit_update > 10  )? "unsigned int tmp1,tmp2,credit_num,credit_send_buff;" : "";
 my $actor_run="
-void ${actor}_run_actor (schedinfo_t * si) { 
-	
-	//unsigned int credit_send_buff;
-	
-	//run schedular
-	
-	
+void ${actor}_run_actor (schedinfo_t * si) {
+    //unsigned int credit_send_buff;
+    //run schedular
 $schedul
- 	
-	//check if input ports have credit update to send
-	$t
-	$crdit_update  
-		
-	//check if output port has data to send
-	$transfer_str 
-	
-	#if (ORCC_SENT_DONT_INT_EN == 0)  
-		if(${ni_name}_any_sent_done_isr_is_asserted()) sent_packet_done_function();	
-	#endif	
-	
-	#if (ORCC_SAVE_DONT_INT_EN == 0)			
-		if(${ni_name}_any_save_done_isr_is_asserted()) check_packet_function();
-	#endif
-	
-	#if (ORCC_GOT_PCK_INT_EN == 0)		
-		if(${ni_name}_any_got_pck_isr_is_asserted()) got_packet_function();		
-	#endif
-	
-	#if (ORCC_GOT_ERR_INT_EN == 0)
-	if(${ni_name}_any_err_isr_is_asserted()) error_handling_function();
-	#endif
-				
+    //check if input ports have credit update to send
+    $t
+    $crdit_update
+    //check if output port has data to send
+    $transfer_str
+    #if (ORCC_SENT_DONT_INT_EN == 0)
+        if(${ni_name}_any_sent_done_isr_is_asserted()) sent_packet_done_function();
+    #endif
+    #if (ORCC_SAVE_DONT_INT_EN == 0)
+        if(${ni_name}_any_save_done_isr_is_asserted()) check_packet_function();
+    #endif
+    #if (ORCC_GOT_PCK_INT_EN == 0)
+        if(${ni_name}_any_got_pck_isr_is_asserted()) got_packet_function();
+    #endif
+    #if (ORCC_GOT_ERR_INT_EN == 0)
+    if(${ni_name}_any_err_isr_is_asserted()) error_handling_function();
+    #endif
 }
 ";
-
-
-	
-	
-
-   my $r;
-  
-   add_colored_info($tview,"actor name: $actor\n",'green');
-   
-   
-  
-   #copy orcc lib files
-  
-   my $orcc_lib_dir = get_project_dir()."/mpsoc/src_c/orcc/lib";
-   opendir(DIR,"$orcc_lib_dir") or $r= "$!\n";
-   if(defined $r) {
-    	add_colored_info($tview,"cannot open directory: $r",'red');
-		return;
-   } 
-   foreach my $name (readdir(DIR))
-   {
-   	 # add_colored_info($tview,"copy ($orcc_lib_dir/$name,$target_dir/sw/tile${actor_tile_id}/);\n   ",'red');
-   	  copy ("$orcc_lib_dir/$name","$target_orccdir/");    
-   }
-   
-   
-   
-  
-   
-  
-   
-  #print $fe "orcc/$fname.c ";
-  #$main_include=$main_include."#include \"orcc/$fname.c\"\n";
-   $main_include=$main_include."#include \"orcc/$fname.h\"\n";
-  
-  $src_lib="$src_lib orcc/$fname.c";
-   
-   print $fc " // Generated from $actor_file\n";
-   my $defines="";
-   my $pval = 	$self->object_get_attribute("map_param","add_debug");
-   $defines .= ($pval eq '1\'b1')? "#define ORCC_DEBUG_EN\n" : "";
-   $pval = 	$self->object_get_attribute("map_param","sent_int");
-   $defines .= ($pval eq '1\'b1')? "#define ORCC_SENT_DONT_INT_EN  1\n" : "#define ORCC_SENT_DONT_INT_EN  0\n";
-   $pval = 	$self->object_get_attribute("map_param","receive_int");
-   $defines .= ($pval eq '1\'b1')? "#define ORCC_SAVE_DONT_INT_EN  1\n" : "#define ORCC_SAVE_DONT_INT_EN  0\n";
-   $pval = 	$self->object_get_attribute("map_param","receive_int"); 
-   $defines .= ($pval eq '1\'b1')? "#define ORCC_GOT_PCK_INT_EN  1\n" : "#define ORCC_GOT_PCK_INT_EN  0\n";
-   $pval = 	$self->object_get_attribute("map_param","got_err_int"); 
-   $defines .= ($pval eq '1\'b1')? "#define ORCC_GOT_ERR_INT_EN  1\n" : "#define ORCC_GOT_ERR_INT_EN  0\n";
-      
-   
-   
-   print $fc "  
-#include <stddef.h>    
-#include \"../$soc_name.h\" 
+    my $r;
+    add_colored_info($tview,"actor name: $actor\n",'green');
+    #copy orcc lib files
+    my $orcc_lib_dir = get_project_dir()."/mpsoc/src_c/orcc/lib";
+    opendir(DIR,"$orcc_lib_dir") or $r= "$!\n";
+    if(defined $r) {
+        add_colored_info($tview,"cannot open directory: $r",'red');
+        return;
+    }
+    foreach my $name (readdir(DIR))
+    {
+        # add_colored_info($tview,"copy ($orcc_lib_dir/$name,$target_dir/sw/tile${actor_tile_id}/);\n   ",'red');
+        copy ("$orcc_lib_dir/$name","$target_orccdir/");
+    }
+    #print $fe "orcc/$fname.c ";
+    #$main_include=$main_include."#include \"orcc/$fname.c\"\n";
+    $main_include=$main_include."#include \"orcc/$fname.h\"\n";
+    $src_lib="$src_lib orcc/$fname.c";
+    print $fc " // Generated from $actor_file\n";
+    my $defines="";
+    my $pval =     $self->object_get_attribute("map_param","add_debug");
+    $defines .= ($pval eq '1\'b1')? "#define ORCC_DEBUG_EN\n" : "";
+    $pval =     $self->object_get_attribute("map_param","sent_int");
+    $defines .= ($pval eq '1\'b1')? "#define ORCC_SENT_DONT_INT_EN  1\n" : "#define ORCC_SENT_DONT_INT_EN  0\n";
+    $pval =     $self->object_get_attribute("map_param","receive_int");
+    $defines .= ($pval eq '1\'b1')? "#define ORCC_SAVE_DONT_INT_EN  1\n" : "#define ORCC_SAVE_DONT_INT_EN  0\n";
+    $pval =     $self->object_get_attribute("map_param","receive_int");
+    $defines .= ($pval eq '1\'b1')? "#define ORCC_GOT_PCK_INT_EN  1\n" : "#define ORCC_GOT_PCK_INT_EN  0\n";
+    $pval =     $self->object_get_attribute("map_param","got_err_int");
+    $defines .= ($pval eq '1\'b1')? "#define ORCC_GOT_ERR_INT_EN  1\n" : "#define ORCC_GOT_ERR_INT_EN  0\n";
+    print $fc "
+#include <stddef.h>
+#include \"../$soc_name.h\"
 #include \"orcc_lib.h\"
 #include \"../../phy_addr.h\"
 #include \"$fname.h\"
-
-
 extern volatile unsigned char oport_array [${ni_name}_NUM_VCs];
-
 ";
-  
-
-   
-  my $origen_def="";
-  my $origen_fuctions=""; 
-  
-   
-	#read actor file name and remove unnecessarily codes. comment every files start with #include and extern
-	open my $fh, "<", $actor_file or $r = "$!\n";
+    my $origen_def="";
+    my $origen_fuctions="";
+    #read actor file name and remove unnecessarily codes. comment every files start with #include and extern
+    open my $fh, "<", $actor_file or $r = "$!\n";
     if(defined $r) {
-    	add_colored_info($tview,"Could not open $actor_file: $r",'red');
-		return;
-    } 
-	while (my $line = <$fh>) {
-	    chomp $line;
-	    #search for fifo size inside the file	    
-	    if( $line =~ /^\s*#define\s+SIZE_\w+/){
-	    	 #example: #define SIZE_operand_1 32
-	    	 my $text = $line;
-	    	 $text =~ s/\s+/ /g; # remove extra spaces
-	    	 $text =~ s/^\s+//; #ltrim
-	    	 my  ($fifo_name,$size) = sscanf("#define SIZE_%s %u",$text);
-	    	 $actor_h = $actor_h."#define SIZE_${actor}_$fifo_name $size\n";
-	    	 $fifos{"${actor}_$fifo_name"}{'size'}=$size;
-	    }	
-	    
-	    
-	    $line = '//'.$line if( $line =~ /^\s*#include/); # comment every line start with #include
-	    if( $line =~ /^\s*extern\s+/){
-	    	 my $extern=0;
-	    	 $line =~ s/\s+/ /g; # remove extra spaces
-	    	 $line =~ s/^\s+//; #ltrim
-	    	    	 
-	    	 #fifo
-	    	 my  ($type,$fifo_name) = sscanf("extern fifo_%s_t *%s;",$line);
-	    	 if(defined $type){
-	    	 	$extern=1;
-	    	 	if (defined $fifos{$fifo_name}){
-	    	 		#add fifo definition:
-	    	 		my $size = $fifos{$fifo_name}{'size'};
-	    	 		#if(!defined $size ){
-	    	 			$size = "$fifo_name";
-	    	 			#$size=~ s/^\s*${actor}_//g;
-	    	 			$size = "SIZE_$size";
-	    	 		#}
-	    	 		
-	    	 		my $fnum  = $fifos{"$fifo_name"}{'fifo_num'};
-	    	 		my $ch_num= $fifos{"$fifo_name"}{'chanel_num'};
-	    	 		$ch_num =1  if(!defined $ch_num);
-	    	 		
-	    	 		my $src_fifo_name= $self->object_get_attribute("locally_connected","$fifo_name");
-	    	 		#printf "$src_fifo_name locally connected $fifo_name\n";
-	    	 		
-	    	 		unless (defined $src_fifo_name){#check if destintion port is not localy connected 
-	    	 		   
-	    	 			$main_fifo_def=$main_fifo_def . "DECLARE_FIFO(${type}, $size, $fnum, $ch_num);\n";	    	 			
-	    	 		}
-	    	 		$main_fifo_assign=$main_fifo_assign . "fifo_${type}_t *$fifo_name = &fifo_$fnum;\n"; 
-	    	 		$main_fifo_rst_ptr.="\t${fifo_name}->write_ind=0;\n";
-	    	 		for (my $c=0; $c<$ch_num; $c++){
-	    	 			$main_fifo_rst_ptr.="\t${fifo_name}->read_inds[$c]=0;\n" 
-	    	 		}
-	    	 		
-	    	 		$origen_fuctions= $origen_fuctions . "$line \n";
-	    	 		
-	    	 		#$main_fifo_rst_ptr.="\t printf(\"${fifo_name}_addr=%u\\n\", &${fifo_name}->contents[0]);\n";  	 		
-	    	 		
-	    	 		my $shift =
-	    	 			($type eq "i8"  || $type eq "u8")  ? 0 :
-	    	 			($type eq "i16" || $type eq "u16") ? 1 :
-	    	 			($type eq "i32" || $type eq "u32") ? 2 :
-	    	 			($type eq "i64" || $type eq "u64") ? 3 : "undef_type check orcc.pl";
-	    	 			 
-	    	 		$origen_def=$origen_def. "#define ${fifo_name}_size_shift  $shift \n";
-	    	 		
-	    	 		
-	    	 		
-	    	 	}else{
-	    	 		print Dumper(\%fifos);
-	    	 		add_colored_info($tview,"Could not find $fifo_name in csv file\n",'red');	 	 		
-	    	 			return;
-	    	 	}		    	 	
-	    	 }
-	    	 
-	    	 #connection_t
-	    	 my  ($connect_name) = sscanf("extern connection_t %s;",$line);
-	    	 if(defined $connect_name ){
-	    	   $extern=1;
-	    	   $main_def=$main_def . " connection_t $connect_name = {0, 0, 0, 0};// We dont need connection as they are done in hardware. just define to prevent error\n";
-	    	   $origen_fuctions= $origen_fuctions . "$line \n";	
-	    	 }
-	    	 
-	    	 
-	    	 #actor_t
-	    	 my  ($actor_name) = sscanf("extern actor_t %s;",$line);
-	    	 if(defined $actor_name ){
-	    	 	$extern=1;
-	    	 	if (defined $fifos{"$actor_name"}{'file'}){
-	    	 	#	print "===============================================================\n";
-	    	 	#add actor definition
-	    	 	#search in network.c file for actor definition
-	    	 		my $csv=$fifos{"$actor_name"}{'file'};	
-	    	 		my ($fname,$path,$suffix) = fileparse("$csv",qr"\..[^.]*$");	
-	    	 		my $net= "$path/${fname}.c";
-	    	 		
-	    	 	    my @lines = get_line_have_string($net,"actor_t $actor_name",$tview);
-	    	 	    if(defined $lines[0]){
-	    	 	    	
-	    	 	    	#print $fd "void ${actor_name}_initialize(schedinfo_t *);\n";
-						#print $fd "void ${actor_name}_scheduler (schedinfo_t *);\n";	    	 	    	
-	    	 	    	#print $fd "$lines[0]\n";
-	    	 	    	$origen_fuctions= $origen_fuctions . "$line \n";	
-	    	 	    	$actors_str=$actors_str."$lines[0]\n"  if($actor_name eq $actor);
-	    	 	    }
-	    	 	     	
-	    	 	}
-	    	 	
-	    	 	
-	    	 }
-	    	 
-	    	 $line= "//$line\n" ; # comment every files start with extern
-	    	add_colored_info($tview,"The Auto generator does not know how to define this extern definition:\n $line \n",'red') if($extern == 0);
-	    	$origen_fuctions = $origen_fuctions.  "$line\n";
-	    }#extern
-	    elsif( $line =~ /^\s?#define\s+/){
-	    	$origen_def=$origen_def.  "$line\n";
-	    }else{	
-        	$origen_fuctions = $origen_fuctions.  "$line\n";
-	    }
-
-  }
-		
-
-
-print $fc "			
+        add_colored_info($tview,"Could not open $actor_file: $r",'red');
+        return;
+    }
+    while (my $line = <$fh>) {
+        chomp $line;
+        #search for fifo size inside the file
+        if( $line =~ /^\s*#define\s+SIZE_\w+/){
+            #example: #define SIZE_operand_1 32
+            my $text = $line;
+            $text =~ s/\s+/ /g; # remove extra spaces
+            $text =~ s/^\s+//; #ltrim
+            my  ($fifo_name,$size) = sscanf("#define SIZE_%s %u",$text);
+            $actor_h = $actor_h."#define SIZE_${actor}_$fifo_name $size\n";
+            $fifos{"${actor}_$fifo_name"}{'size'}=$size;
+        }
+        $line = '//'.$line if( $line =~ /^\s*#include/); # comment every line start with #include
+        if( $line =~ /^\s*extern\s+/){
+            my $extern=0;
+            $line =~ s/\s+/ /g; # remove extra spaces
+            $line =~ s/^\s+//; #ltrim
+            #fifo
+            my  ($type,$fifo_name) = sscanf("extern fifo_%s_t *%s;",$line);
+            if(defined $type){
+                $extern=1;
+                if (defined $fifos{$fifo_name}){
+                    #add fifo definition:
+                    my $size = $fifos{$fifo_name}{'size'};
+                    #if(!defined $size ){
+                        $size = "$fifo_name";
+                        #$size=~ s/^\s*${actor}_//g;
+                        $size = "SIZE_$size";
+                    #}
+                    my $fnum  = $fifos{"$fifo_name"}{'fifo_num'};
+                    my $ch_num= $fifos{"$fifo_name"}{'chanel_num'};
+                    $ch_num =1  if(!defined $ch_num);
+                    my $src_fifo_name= $self->object_get_attribute("locally_connected","$fifo_name");
+                    #printf "$src_fifo_name locally connected $fifo_name\n";
+                    unless (defined $src_fifo_name){#check if destintion port is not localy connected
+                        $main_fifo_def=$main_fifo_def . "DECLARE_FIFO(${type}, $size, $fnum, $ch_num);\n";
+                    }
+                    $main_fifo_assign=$main_fifo_assign . "fifo_${type}_t *$fifo_name = &fifo_$fnum;\n";
+                    $main_fifo_rst_ptr.="\t${fifo_name}->write_ind=0;\n";
+                    for (my $c=0; $c<$ch_num; $c++){
+                        $main_fifo_rst_ptr.="\t${fifo_name}->read_inds[$c]=0;\n"
+                    }
+                    $origen_fuctions= $origen_fuctions . "$line \n";
+                    #$main_fifo_rst_ptr.="\t printf(\"${fifo_name}_addr=%u\\n\", &${fifo_name}->contents[0]);\n";
+                    my $shift =
+                        ($type eq "i8"  || $type eq "u8")  ? 0 :
+                        ($type eq "i16" || $type eq "u16") ? 1 :
+                        ($type eq "i32" || $type eq "u32") ? 2 :
+                        ($type eq "i64" || $type eq "u64") ? 3 : "undef_type check orcc.pl";
+                    $origen_def=$origen_def. "#define ${fifo_name}_size_shift  $shift \n";
+                }else{
+                    print Dumper(\%fifos);
+                    add_colored_info($tview,"Could not find $fifo_name in csv file\n",'red');
+                        return;
+                }
+            }
+            #connection_t
+            my  ($connect_name) = sscanf("extern connection_t %s;",$line);
+            if(defined $connect_name ){
+                $extern=1;
+                $main_def=$main_def . " connection_t $connect_name = {0, 0, 0, 0};// We dont need connection as they are done in hardware. just define to prevent error\n";
+                $origen_fuctions= $origen_fuctions . "$line \n";
+            }
+            #actor_t
+            my  ($actor_name) = sscanf("extern actor_t %s;",$line);
+            if(defined $actor_name ){
+                $extern=1;
+                if (defined $fifos{"$actor_name"}{'file'}){
+                #    print "===============================================================\n";
+                #add actor definition
+                #search in network.c file for actor definition
+                    my $csv=$fifos{"$actor_name"}{'file'};
+                    my ($fname,$path,$suffix) = fileparse("$csv",qr"\..[^.]*$");
+                    my $net= "$path/${fname}.c";
+                    my @lines = get_line_have_string($net,"actor_t $actor_name",$tview);
+                    if(defined $lines[0]){
+                        #print $fd "void ${actor_name}_initialize(schedinfo_t *);\n";
+                        #print $fd "void ${actor_name}_scheduler (schedinfo_t *);\n";
+                        #print $fd "$lines[0]\n";
+                        $origen_fuctions= $origen_fuctions . "$line \n";
+                        $actors_str=$actors_str."$lines[0]\n"  if($actor_name eq $actor);
+                    }
+                }
+            }
+            $line= "//$line\n" ; # comment every files start with extern
+            add_colored_info($tview,"The Auto generator does not know how to define this extern definition:\n $line \n",'red') if($extern == 0);
+            $origen_fuctions = $origen_fuctions.  "$line\n";
+        }#extern
+        elsif( $line =~ /^\s?#define\s+/){
+            $origen_def=$origen_def.  "$line\n";
+        }else{
+            $origen_fuctions = $origen_fuctions.  "$line\n";
+        }
+    }
+print $fc "
 $origen_def
-
-$Hw_fifo_define 
-
-
-$origen_fuctions	
-
+$Hw_fifo_define
+$origen_fuctions
 $actor_got_pck_func
-
 $actor_update_credit
-
 $actor_check_pck_func
-
 $actor_sent_pck_done_func
-	
-
-
 $actor_run
-
-
-
 $actor_init
-
-";		
-		
-
-			close($fc);
-
-			$actor_h.="$defines
-	unsigned int  transfer_manage (unsigned int, unsigned int, unsigned int, unsigned char, unsigned int, unsigned int, unsigned int,  unsigned int, unsigned int, unsigned int, unsigned char, unsigned int *, unsigned int *);
-	void got_packet_function(void);
-	void check_packet_function (void);
-	void sent_packet_done_function (void);	
-	void error_handling_function (void);	
+";
+            close($fc);
+            $actor_h.="$defines
+    unsigned int  transfer_manage (unsigned int, unsigned int, unsigned int, unsigned char, unsigned int, unsigned int, unsigned int,  unsigned int, unsigned int, unsigned int, unsigned char, unsigned int *, unsigned int *);
+    void got_packet_function(void);
+    void check_packet_function (void);
+    void sent_packet_done_function (void);
+    void error_handling_function (void);
 #endif
 ";
-			open my $fp, ">$target_actor_header" or $r = "$!\n";
-			if(defined $r) {
-		    	add_colored_info($tview,"Could not open $target_actor_header to write: $r",'red');
-				return;
-			}
-			print $fp $actor_h;
-			close($fp);
-			 
-
-
-	}  
-	
-	
-	
-	
-	
-	my $got_pck_func= "	
+            open my $fp, ">$target_actor_header" or $r = "$!\n";
+            if(defined $r) {
+                add_colored_info($tview,"Could not open $target_actor_header to write: $r",'red');
+                return;
+            }
+            print $fp $actor_h;
+            close($fp);
+    }
+    my $got_pck_func= "
 void got_packet_function(void){
-	unsigned int i ;
-	unsigned char iport;
-	for (i=0;i<${ni_name}_NUM_VCs;i++){
-		if((${ni_name}_got_packet(i)) && (iport_array[i]==255) && ni_receive_is_free(i) ) {
-		
-			iport =${ni_name}_RECEIVE_PRECAP_DATA_REG(i); 
-			iport_array[i]=iport;	
-			if(iport==0){ //a credit update packet is recived;
-				${ni_name}_receive (i, (unsigned int)& credit_buff[i] , 4, 0);	
-			}else{
+    unsigned int i ;
+    unsigned char iport;
+    for (i=0;i<${ni_name}_NUM_VCs;i++){
+        if((${ni_name}_got_packet(i)) && (iport_array[i]==255) && ni_receive_is_free(i) ) {
+            iport =${ni_name}_RECEIVE_PRECAP_DATA_REG(i);
+            iport_array[i]=iport;
+            if(iport==0){ //a credit update packet is recived;
+                ${ni_name}_receive (i, (unsigned int)& credit_buff[i] , 4, 0);
+            }else{
 $all_got_packet_function
-			}			
-			${ni_name}_ack_got_pck_isr(i); 
-		}//If ${ni_name} got packet
-	}//for	
+            }
+            ${ni_name}_ack_got_pck_isr(i);
+        }//If ${ni_name} got packet
+    }//for
 }// got_packet_function
-
-";	
-		
-		
-
-
-	my $sent_packet_done_function = "
- 	
+";
+    my $sent_packet_done_function = "
 void sent_packet_done_function (void){
-	unsigned char oport;
-	unsigned int i;
-	for (i=0;i<${ni_name}_NUM_VCs;i++){
-		if(${ni_name}_packet_is_sent(i)) {
-			oport= oport_array[i];
-			if(oport==0){ // a credit update packet has sent out
-				
-			}else{	
+    unsigned char oport;
+    unsigned int i;
+    for (i=0;i<${ni_name}_NUM_VCs;i++){
+        if(${ni_name}_packet_is_sent(i)) {
+            oport= oport_array[i];
+            if(oport==0){ // a credit update packet has sent out
+            }else{
 $all_sent_packet_done_function
-			}
-			oport_array[i]=255;
-			${ni_name}_ack_send_done_isr(i); 			
-		}//If ${ni_name}_packet_is_sent
-	}//for		
-}//sent_packet_done_function	
-	
+            }
+            oport_array[i]=255;
+            ${ni_name}_ack_send_done_isr(i);
+        }//If ${ni_name}_packet_is_sent
+    }//for
+}//sent_packet_done_function
 ";
-
-
-	
-	my $check_pck_func ="	
-	
+    my $check_pck_func ="
 void check_packet_function (void){
-	unsigned char iport;
-	unsigned int i ,size ;
-	unsigned int credit_value,credit_port;
-	#ifdef ORCC_DEBUG_EN
-	struct SRC_INFOS  src_info;
-	#endif
-	for (i=0;i<${ni_name}_NUM_VCs;i++){
-		if(${ni_name}_packet_is_saved(i)) {
-			
-			size=${ni_name}_RECEIVE_DATA_SIZE_REG(i); //size in byte
-			iport= iport_array[i];
-			
-			#ifdef ORCC_DEBUG_EN
-			src_info=get_src_info(i);
-			if(iport != src_info.r) printf (\"Error: iport missmatch \%u != \%u \\n\",iport, src_info.r );			  
-			#endif
-			
-			iport_array[i]=255;
-			
-			if(iport==0){ // a credit update packet has been received
-				credit_port  = credit_buff[i] >> 16; //output port num
-				credit_value = (credit_buff[i] & 0xFFFF); // credit value in word
+    unsigned char iport;
+    unsigned int i ,size ;
+    unsigned int credit_value,credit_port;
+    #ifdef ORCC_DEBUG_EN
+    struct SRC_INFOS  src_info;
+    #endif
+    for (i=0;i<${ni_name}_NUM_VCs;i++){
+        if(${ni_name}_packet_is_saved(i)) {
+            size=${ni_name}_RECEIVE_DATA_SIZE_REG(i); //size in byte
+            iport= iport_array[i];
+            #ifdef ORCC_DEBUG_EN
+            src_info=get_src_info(i);
+            if(iport != src_info.r) printf (\"Error: iport missmatch \%u != \%u \\n\",iport, src_info.r );
+            #endif
+            iport_array[i]=255;
+            if(iport==0){ // a credit update packet has been received
+                credit_port  = credit_buff[i] >> 16; //output port num
+                credit_value = (credit_buff[i] & 0xFFFF); // credit value in word
 $all_update_credit
-			}else{	
+            }else{
 $all_check_packet_function
-			}
-			${ni_name}_ack_save_done_isr(i); 
-		}//If ${ni_name}_packet_is_saved
-	}//for	
+            }
+            ${ni_name}_ack_save_done_isr(i);
+        }//If ${ni_name}_packet_is_saved
+    }//for
 }// check_packet_function
-				
-";	
-	
+";
 my $ni_isr='
-	
 /*
 transfer_manage
-	w: initial weight
-	v: Virtual chanel number
-	class_num: message class number
-	dest_port: destination queue number
-	queue_pointer: address in byte
-	queue_size: queue size in byte
-	start_index: start index byte number
-	end_index:  end index byte number
-	dest_phy_addr
-	credit: Number of byte available in destination queue
+    w: initial weight
+    v: Virtual chanel number
+    class_num: message class number
+    dest_port: destination queue number
+    queue_pointer: address in byte
+    queue_size: queue size in byte
+    start_index: start index byte number
+    end_index:  end index byte number
+    dest_phy_addr
+    credit: Number of byte available in destination queue
 */
-
-
-
 unsigned int  transfer_manage (unsigned int w, unsigned int v, unsigned int class_num, unsigned char dest_port, unsigned int queue_pointer,unsigned int queue_size,
 unsigned int start_index,  unsigned int send_data_size_in_byte, unsigned int dest_phy_addr,unsigned int credit, unsigned char port_num, unsigned int * sent_dat_size, unsigned int * dest_credit_size){
-    
-
-	unsigned int start_addr_pointer;
-	unsigned int data_size=send_data_size_in_byte;
+    unsigned int start_addr_pointer;
+    unsigned int data_size=send_data_size_in_byte;
 ';
-	
 $ni_isr=$ni_isr."
     if (${ni_name}_send_is_busy(v)) return 0 ; // if VC is busy sending previous packet do nothing
-    
 ";
-
 $ni_isr=$ni_isr.'
-	if(credit==0) return 0;
+    if(credit==0) return 0;
     if(data_size==0) return 0;
     start_addr_pointer = queue_pointer + start_index;
     if(data_size > credit) data_size =  credit; // we dont want to send more data than the receiver credit
-    if((start_index + data_size) > queue_size) data_size =  queue_size-start_index; // we only send data until end of the queue. The rest will be sent in next round starting from beginning of the queue   
-	if(data_size==0) return 0;
+    if((start_index + data_size) > queue_size) data_size =  queue_size-start_index; // we only send data until end of the queue. The rest will be sent in next round starting from beginning of the queue
+    if(data_size==0) return 0;
 ';
-
-$ni_isr=$ni_isr."	
-	oport_array[v]=  port_num; // port_num and data size should be saved before calling transfer function.
-	* sent_dat_size =  data_size;
-	* dest_credit_size -= data_size;
-	${ni_name}_transfer (w, v, class_num, dest_port , start_addr_pointer, data_size, dest_phy_addr);
-    return 1;   
-}	
-	
-	
-	
-	
-
-	
-	
+$ni_isr=$ni_isr."
+    oport_array[v]=  port_num; // port_num and data size should be saved before calling transfer function.
+    * sent_dat_size =  data_size;
+    * dest_credit_size -= data_size;
+    ${ni_name}_transfer (w, v, class_num, dest_port , start_addr_pointer, data_size, dest_phy_addr);
+    return 1;
+}
 void error_handling_function(){
-	unsigned int i;
-	for (i=0;i<${ni_name}_NUM_VCs;i++){
-		if(${ni_name}_got_buff_ovf(i)) {
-			printf (\"VC%u:The receiver allocated buffer size is smaller than the received packet size in core\%u\\n\",i,COREID);
-			${ni_name}_ack_buff_ovf_isr(i);
-		}
-		if(${ni_name}_got_send_dsize_err(i)) {
-			 printf (\"VC%u:The send data size is not set in core\%u\\n\",i,COREID);
-			 ${ni_name}_ack_send_dsize_err_isr(i); 
-		}
-		if(${ni_name}_got_burst_size_err(i)){
- 			 printf (\"VC%u:The burst size is not set in core\%u\\n\",i,COREID);
-			 ${ni_name}_ack_burst_size_err_isr(i);
-		}
-		if(${ni_name}_got_invalid_send_req(i)){
-			 printf( \"VC%u:A new send request is received while the DMA is still busy sending previous packet in core\%u\\n\",i,COREID);
-			 ${ni_name}_ack_invalid_send_req_isr(i);
-		}
-		if(${ni_name}_got_crc_mismatch(i)){
-			printf( \"VC%u:CRC miss-matched in core\%u\\n\",i,COREID);
-			${ni_name}_ack_crc_mismatch_isr(i);
-		}		  
-	}//for
-}//error_handle		
-	
-
-         
-	
-	
+    unsigned int i;
+    for (i=0;i<${ni_name}_NUM_VCs;i++){
+        if(${ni_name}_got_buff_ovf(i)) {
+            printf (\"VC%u:The receiver allocated buffer size is smaller than the received packet size in core\%u\\n\",i,COREID);
+            ${ni_name}_ack_buff_ovf_isr(i);
+        }
+        if(${ni_name}_got_send_dsize_err(i)) {
+            printf (\"VC%u:The send data size is not set in core\%u\\n\",i,COREID);
+            ${ni_name}_ack_send_dsize_err_isr(i);
+        }
+        if(${ni_name}_got_burst_size_err(i)){
+            printf (\"VC%u:The burst size is not set in core\%u\\n\",i,COREID);
+            ${ni_name}_ack_burst_size_err_isr(i);
+        }
+        if(${ni_name}_got_invalid_send_req(i)){
+            printf( \"VC%u:A new send request is received while the DMA is still busy sending previous packet in core\%u\\n\",i,COREID);
+            ${ni_name}_ack_invalid_send_req_isr(i);
+        }
+        if(${ni_name}_got_crc_mismatch(i)){
+            printf( \"VC%u:CRC miss-matched in core\%u\\n\",i,COREID);
+            ${ni_name}_ack_crc_mismatch_isr(i);
+        }
+    }//for
+}//error_handle
 void ${ni_name}_isr(void){
-	//place your interrupt code here
-	#if (ORCC_GOT_ERR_INT_EN == 1)
-	if(${ni_name}_any_err_isr_is_asserted()  ){
-		// An error ocure 
-		error_handling_function();	
-	}
-	#endif
-	
-	#if (ORCC_SENT_DONT_INT_EN == 1) 
-	if( ${ni_name}_any_sent_done_isr_is_asserted()  ){
-		//check which VC has finished sending the packet. 
-		sent_packet_done_function();		
-	}
-	#endif
-	
-	#if (ORCC_GOT_PCK_INT_EN == 1 || ORCC_SAVE_DONT_INT_EN ==1)		
-	// regardless of ORCC_SAVE_DONT_INT_EN we need to check if the fifo pointer has been updated with last packet data size before sending save command for new packet to NI. 
-	if( ${ni_name}_any_save_done_isr_is_asserted()){
-		//check which VC has finished saving the packet. This function must be called before got_packet_function
-		check_packet_function();		
-	}	
-	#endif
-	
-	#if (ORCC_GOT_PCK_INT_EN == 1)		
-	if(${ni_name}_any_got_pck_isr_is_asserted() ){
-		//check which VC got packet
-		got_packet_function();		
-	}
-	#endif
-	
-	
-	
-	return;
+    //place your interrupt code here
+    #if (ORCC_GOT_ERR_INT_EN == 1)
+    if(${ni_name}_any_err_isr_is_asserted()  ){
+        // An error ocure
+        error_handling_function();
+    }
+    #endif
+    #if (ORCC_SENT_DONT_INT_EN == 1)
+    if( ${ni_name}_any_sent_done_isr_is_asserted()  ){
+        //check which VC has finished sending the packet.
+        sent_packet_done_function();
+    }
+    #endif
+    #if (ORCC_GOT_PCK_INT_EN == 1 || ORCC_SAVE_DONT_INT_EN ==1)
+    // regardless of ORCC_SAVE_DONT_INT_EN we need to check if the fifo pointer has been updated with last packet data size before sending save command for new packet to NI.
+    if( ${ni_name}_any_save_done_isr_is_asserted()){
+        //check which VC has finished saving the packet. This function must be called before got_packet_function
+        check_packet_function();
+    }
+    #endif
+    #if (ORCC_GOT_PCK_INT_EN == 1)
+    if(${ni_name}_any_got_pck_isr_is_asserted() ){
+        //check which VC got packet
+        got_packet_function();
+    }
+    #endif
+    return;
 }
-	
-	";	
-	
-	
-my $v_val= $self->object_get_attribute('noc_param','V');		
+    ";
+my $v_val= $self->object_get_attribute('noc_param','V');
 my $opr ='';
 for (my $i=0;$i<$v_val; $i++){
-	$opr = $opr."\toport_array[$i]=255;\n"; 
-	$opr = $opr."\tiport_array[$i]=255;\n"; 
-}	
-	
+    $opr = $opr."\toport_array[$i]=255;\n";
+    $opr = $opr."\tiport_array[$i]=255;\n";
+}
 $main_fifo_rst_ptr.=
 "$opr
-}\n";	
-	
-	
-my $main="	
+}\n";
+my $main="
 int main(){
-	schedinfo_t si;	
-	reset_all_fifo_ptr();	
-$all_init_actor	
-	general_int_init();
-	general_int_add(${ni_name}_INT_PIN, ${ni_name}_isr, 0); //${ni_name}_INT_PIN
-	// Enable ${ni_name} interrupt (its connected to interrupt pin 0)
-	general_int_enable(${ni_name}_INT_PIN);
-	general_cpu_int_en();
-	// hw interrupt enable function:
-	// ${ni_name}_initial (burst_size,  errors_int_en,  send_int_en,  save_int_en,  got_pck_int_en)
-	${ni_name}_initial (16,ORCC_GOT_ERR_INT_EN,ORCC_SENT_DONT_INT_EN,ORCC_SAVE_DONT_INT_EN,ORCC_GOT_PCK_INT_EN); 
-	
-	delay(100);
-	while(1){
+    schedinfo_t si;
+    reset_all_fifo_ptr();
+$all_init_actor
+    general_int_init();
+    general_int_add(${ni_name}_INT_PIN, ${ni_name}_isr, 0); //${ni_name}_INT_PIN
+    // Enable ${ni_name} interrupt (its connected to interrupt pin 0)
+    general_int_enable(${ni_name}_INT_PIN);
+    general_cpu_int_en();
+    // hw interrupt enable function:
+    // ${ni_name}_initial (burst_size,  errors_int_en,  send_int_en,  save_int_en,  got_pck_int_en)
+    ${ni_name}_initial (16,ORCC_GOT_ERR_INT_EN,ORCC_SENT_DONT_INT_EN,ORCC_SAVE_DONT_INT_EN,ORCC_GOT_PCK_INT_EN);
+    delay(100);
+    while(1){
 $all_run_actor
-	}	
-	return 0;
-}		
-			
-";		
-	
-my $log2=log2($max_dst_port_num +1);	
-	
-print $fd "	
+    }
+    return 0;
+}
+";
+my $log2=log2($max_dst_port_num +1);
+print $fd "
 $main_include
-
-#define MAX_DST_PORT_NUM  $max_dst_port_num 
-
-// make sure that the HDATA_PRECAPw widh is >= log2(MAX_DST_PORT_NUM) 	
+#define MAX_DST_PORT_NUM  $max_dst_port_num
+// make sure that the HDATA_PRECAPw widh is >= log2(MAX_DST_PORT_NUM)
 #if ( $log2 > ${ni_name}_HDATA_PRECAPw )
-	#error \" The value of HDATA_PRECAPw should be defined at least $log2. Open the processing tile generator and increase the NI HDATA_PRECAPw value >= $log2\"
+    #error \" The value of HDATA_PRECAPw should be defined at least $log2. Open the processing tile generator and increase the NI HDATA_PRECAPw value >= $log2\"
 #endif
-
-//make dure Byte_En is asserted in NI 
+//make dure Byte_En is asserted in NI
 #if (${ni_name}_BYTE_EN == 0)
-	#error \" The NI NI BYTE_EN parameter should be set as one for correct data comminication between cores. \"
+    #error \" The NI NI BYTE_EN parameter should be set as one for correct data comminication between cores. \"
 #endif
-
-
 // a simple delay function
-
 void delay ( unsigned int num ){
-	
-	while (num>0){ 
-		num--;
-		nop(); // asm volatile (\"nop\");
-	}
-	return;
-
+    while (num>0){
+        num--;
+        nop(); // asm volatile (\"nop\");
+    }
+    return;
 }
-
-
 $actors_str
-
 $main_fifo_def
-
 $main_fifo_assign
-
 $main_fifo_rst_ptr
-
 $main_def
-
-
-
-
-$got_pck_func 
-
-$check_pck_func  
-
-$sent_packet_done_function     
-
+$got_pck_func
+$check_pck_func
+$sent_packet_done_function
 $ni_isr
-
 $main
-
 ";
- 
-  
-  
-  
   close($fd);
-  
- 
-  
 save_file($src_lib_file,$src_lib);
-
-
-
-
- add_colored_info($tview,"$main_c file has been created successfully from @actors_file_names file \n",'blue');	
-		
-	}	#actor
-	
-	
-	#done 
-	message_dialog("The source files have been generated successfully");
-		#print Dumper (\$self);
+ add_colored_info($tview,"$main_c file has been created successfully from @actors_file_names file \n",'blue');
+    }    #actor
+    #done
+    message_dialog("The source files have been generated successfully");
+        #print Dumper (\$self);
 } #end sub
-
-
-
 sub get_line_have_string{
-	my ($file,$str,$tview)=@_;
-	my $r;
-	my @matches;
-	open my $fh, "<", $file or $r = "$!\n";
+    my ($file,$str,$tview)=@_;
+    my $r;
+    my @matches;
+    open my $fh, "<", $file or $r = "$!\n";
     if(defined $r) {
-    	add_colored_info($tview,"Could not open $file: $r",'red');
-		return;
-    } 
+        add_colored_info($tview,"Could not open $file: $r",'red');
+        return;
+    }
     while (my $line = <$fh>) {
-	    chomp $line;
-	    $line =~ s/\s+/ /g; # remove extra spaces
-	    $line =~ s/^\s+//; #ltrim
-	    if ($line =~ /$str/){
-	    	push(@matches,$line);
-	    }    
-    	
+        chomp $line;
+        $line =~ s/\s+/ /g; # remove extra spaces
+        $line =~ s/^\s+//; #ltrim
+        if ($line =~ /$str/){
+            push(@matches,$line);
+        }
     }
-	return @matches;
-}	
+    return @matches;
+}
 
 sub get_destport_constant_list{
-	my ($self,$category)=@_;
-	my %destport_const;
-	#1- Get list of all actors
-	my @actors= get_all_tasks($self,$category);
-	foreach my $actor (@actors){
-	
-		my $i=1;
-		#2- for each actor get the list of all input ports
-		my @sinkers= get_all_dest_traces_of_actr($self,$actor,$category);
-		#3- number each source port of this actor
-		foreach my $sink (@sinkers){
-			
-			my ($src,$dst, $Mbytes, $file_id, $file_name,$init_weight,$min_pck, $max_pck,  $burst, $injct_rate, $injct_rate_var,$src_port,$dst_port,$buff_size,$chanel,$vc,$class
-				)=get_trace($self,$category,$sink);
-			
-			$destport_const{$actor}{$dst_port}= $i;
-			#print "destport_const{$actor}{$dst_port}= $i;\n";
-			$i++;
-		}
-	}	
-	return %destport_const;
+    my ($self,$category)=@_;
+    my %destport_const;
+    #1- Get list of all actors
+    my @actors= get_all_tasks($self,$category);
+    foreach my $actor (@actors){
+        my $i=1;
+        #2- for each actor get the list of all input ports
+        my @sinkers= get_all_dest_traces_of_actr($self,$actor,$category);
+        #3- number each source port of this actor
+        foreach my $sink (@sinkers){
+            my ($src,$dst, $Mbytes, $file_id, $file_name,$init_weight,$min_pck, $max_pck,  $burst, $injct_rate, $injct_rate_var,$src_port,$dst_port,$buff_size,$chanel,$vc,$class
+                )=get_trace($self,$category,$sink);
+            $destport_const{$actor}{$dst_port}= $i;
+            #print "destport_const{$actor}{$dst_port}= $i;\n";
+            $i++;
+        }
+    }
+    return %destport_const;
 }
 
-
-
-
 sub get_srcport_constant_list{
-	my ($self,$category)=@_;
-	my %srcport_const;
-	#1- Get list of all actors
-	my @actors= get_all_tasks($self,$category);
-	#print "@actors\n**************************************************";
-	foreach my $actor (@actors){
-	
-		my $i=1;
-		#2- for each actor get the list of all output ports
-		my @injectors= get_all_source_traces_of_actr($self,$actor,$category);
-		#3- number each source port of this actor
-		foreach my $inject (@injectors){
-			
-			my ($src,$dst, $Mbytes, $file_id, $file_name,$init_weight,$min_pck, $max_pck,  $burst, $injct_rate, $injct_rate_var,$src_port,$dst_port,$buff_size,$chanel,$vc,$class
-				)=get_trace($self,$category,$inject);
-			
-			$srcport_const{$actor}{$src_port}{$chanel}= $i;					
-			$i++;
-		}
-	}	
-	return %srcport_const;
+    my ($self,$category)=@_;
+    my %srcport_const;
+    #1- Get list of all actors
+    my @actors= get_all_tasks($self,$category);
+    #print "@actors\n**************************************************";
+    foreach my $actor (@actors){
+        my $i=1;
+        #2- for each actor get the list of all output ports
+        my @injectors= get_all_source_traces_of_actr($self,$actor,$category);
+        #3- number each source port of this actor
+        foreach my $inject (@injectors){
+            my ($src,$dst, $Mbytes, $file_id, $file_name,$init_weight,$min_pck, $max_pck,  $burst, $injct_rate, $injct_rate_var,$src_port,$dst_port,$buff_size,$chanel,$vc,$class
+                )=get_trace($self,$category,$inject);
+            $srcport_const{$actor}{$src_port}{$chanel}= $i;
+            $i++;
+        }
+    }
+    return %srcport_const;
 }
 
-
-
-
-
 sub get_all_dest_traces_of_actr{
-	my ($self,$actor,$category)=@_;
-	my @traces =get_trace_list($self,$category);
-	my @sources;
-	foreach my $p (@traces){
-		my ($src,$dst, $Mbytes, $file_id, $file_name,$init_weight,$min_pck, $max_pck,  $burst, $injct_rate, $injct_rate_var)=get_trace($self,$category,$p);
-		push (@sources,$p) if($dst eq $actor);
-	}
-	return  @sources;	
+    my ($self,$actor,$category)=@_;
+    my @traces =get_trace_list($self,$category);
+    my @sources;
+    foreach my $p (@traces){
+        my ($src,$dst, $Mbytes, $file_id, $file_name,$init_weight,$min_pck, $max_pck,  $burst, $injct_rate, $injct_rate_var)=get_trace($self,$category,$p);
+        push (@sources,$p) if($dst eq $actor);
+    }
+    return  @sources;
 }
 
 sub get_all_source_traces_of_actr{
-	my ($self,$actor,$category)=@_;
-	my @traces =get_trace_list($self,$category);
-	my @dests;
-	foreach my $p (@traces){
-		my ($src,$dst, $Mbytes, $file_id, $file_name,$init_weight,$min_pck, $max_pck,  $burst, $injct_rate, $injct_rate_var)=get_trace($self,$category,$p);
-		push (@dests,$p) if($src eq $actor);
-	}
-	return  @dests;	
-}	
+    my ($self,$actor,$category)=@_;
+    my @traces =get_trace_list($self,$category);
+    my @dests;
+    foreach my $p (@traces){
+        my ($src,$dst, $Mbytes, $file_id, $file_name,$init_weight,$min_pck, $max_pck,  $burst, $injct_rate, $injct_rate_var)=get_trace($self,$category,$p);
+        push (@dests,$p) if($src eq $actor);
+    }
+    return  @dests;
+}
 
 sub get_actr_file_name {
-	my ($self,$actor,$category)=@_;
-	my @traces =get_trace_list($self,$category);
-	foreach my $p (@traces){
-		my ($src,$dst, $Mbytes, $file_id, $file_name,$init_weight,$min_pck, $max_pck,  $burst, $injct_rate, $injct_rate_var)=get_trace($self,$category,$p);
-		if($src eq $actor || $dst eq $actor){
-			#the actor supposed to be located next to CSV file and have the same file name as actor name
-			my ($fname,$path,$suffix) = fileparse("$file_name",qr"\..[^.]*$");	
-			#my ($net,$num,$name)=split(':',$actor);
-			return "$path/${actor}.c"; 
-		}
-	}
-	return undef;
+    my ($self,$actor,$category)=@_;
+    my @traces =get_trace_list($self,$category);
+    foreach my $p (@traces){
+        my ($src,$dst, $Mbytes, $file_id, $file_name,$init_weight,$min_pck, $max_pck,  $burst, $injct_rate, $injct_rate_var)=get_trace($self,$category,$p);
+        if($src eq $actor || $dst eq $actor){
+            #the actor supposed to be located next to CSV file and have the same file name as actor name
+            my ($fname,$path,$suffix) = fileparse("$file_name",qr"\..[^.]*$");
+            #my ($net,$num,$name)=split(':',$actor);
+            return "$path/${actor}.c";
+        }
+    }
+    return undef;
 }
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
 1;
diff --git a/mpsoc/perl_gui/lib/perl/phy_noc_gen.pl b/mpsoc/perl_gui/lib/perl/phy_noc_gen.pl
index de37a95..3bd370d 100644
--- a/mpsoc/perl_gui/lib/perl/phy_noc_gen.pl
+++ b/mpsoc/perl_gui/lib/perl/phy_noc_gen.pl
@@ -2,31 +2,26 @@
 use strict;
 use warnings;
 use constant::boolean;
-
 use Cwd 'abs_path';
 use base 'Class::Accessor::Fast';
-require "widget.pl"; 
+require "widget.pl";
 require "diagram.pl";
 require "topology_verilog_gen.pl";
-
 use String::Scanf; # imports sscanf()
-
 use FindBin;
 use lib $FindBin::Bin;
 use tsort;
-
 use File::Basename;
 use Cwd 'abs_path';
 
 __PACKAGE__->mk_accessors(qw{
     window
-    sourceview        
+    sourceview
 });
 
 my $NAME = 'phy_noc_maker';
 exit phy_noc_maker_main() unless caller;
 
-
 sub phy_noc_maker_main {
     my $app = __PACKAGE__->new();
     my $table=$app->build_phy_noc_gui();
@@ -39,11 +34,7 @@ sub get_noc_num_page {
     my $scrolled_win = gen_scr_win_with_adjst ($self,"noc${noc_num}_setting_gui");
     add_widget_to_scrolled_win($table,$scrolled_win);
     my $row=noc_config ($self,$table,$info,$noc_num);
-
-
     return $scrolled_win;
-
-
 }
 
 my @pages=();
@@ -54,73 +45,63 @@ sub gen_notebook_phy {
     my $notebook = gen_notebook();
     $notebook->set_tab_pos ('left');
     $notebook->set_scrollable(TRUE);
-    
     for (my $i=0;$i<$phys;$i++){
         $pages[$i]=get_noc_num_page($self,$i,$info);
         $page_wins[$i] = add_widget_to_scrolled_win($pages[$i]);
         $notebook->append_page ($page_wins[$i],gen_label_in_center  (" NoC $i"));
     }
-
-    $notebook->signal_connect( 'switch-page'=> sub{ # rebulid the current page        
+    $notebook->signal_connect( 'switch-page'=> sub{ # rebulid the current page
         $self->object_add_attribute ("process_notebook","currentpage",$_[2]);    #save the new pagenumber
-        set_gui_status($self,"ref",1);    
-    });    
-    
+        set_gui_status($self,"ref",1);
+    });
     return $notebook;
 }
 
-
 #############
 #    load_phy
 #############
-
 sub load_phy{
     my ($soc,$info,$ip)=@_;
     my $file;
-    my $dialog =  gen_file_dialog (undef, 'phy');    
+    my $dialog =  gen_file_dialog (undef, 'phy');
     my $dir = Cwd::getcwd();
-    $dialog->set_current_folder ("$dir/lib/multi_nocs");        
-
-
+    $dialog->set_current_folder ("$dir/lib/multi_nocs");
     if ( "ok" eq $dialog->run ) {
         $file = $dialog->get_filename;
         my ($name,$path,$suffix) = fileparse("$file",qr"\..[^.]*$");
         if($suffix eq '.phy'){
             my ($pp,$r,$err) = regen_object($file);
-            if ($r || !defined $pp){        
+            if ($r || !defined $pp){
                 show_info($info,"**Error reading  $file file: $err\n");
                 $dialog->destroy;
                 return;
-            } 
+            }
             clone_obj($soc,$pp);
-            set_gui_status($soc,"load_file",0);        
-        }                    
+            set_gui_status($soc,"load_file",0);
+        }
     }
     $dialog->destroy;
 }
 
-
 sub generate_phynocs{
-    my ($self,$info)=@_;    
+    my ($self,$info)=@_;
     my $name=$self->object_get_attribute('phy_name');
     return 0 if (check_mpsoc_name($name,$info,"Phy NoCs"));
     #make target dir
     my $pronoc_dir      = get_project_dir(); #mpsoc dir addr
     my $target_dir= "$ENV{PRONOC_WORK}/src_phy_nocs/$name";
     my $phys= $self->object_get_attribute('phy_num');
-
-
     my $ports1="";
     my $ports2="";
     my $imports="";
     my $nocs="";
     my $flist1=perl_file_header("phy_nocs.flist");
     my $flist2="";
-    #create a unique verilog modules for each NoC    
+    #create a unique verilog modules for each NoC
     for (my $i=0;$i<$phys;$i++){
         my $append="N$i";
         add_info($info,"Generating NoC$i Rtl code ...\n");
-        mkpath("$target_dir/noc$i",1,0755); 
+        mkpath("$target_dir/noc$i",1,0755);
         my $cmd = "perl $pronoc_dir/mpsoc/script/phy_noc_gen/phy_noc.pl $append $target_dir/noc$i";
         run_cmd_textview_errors ($cmd,$info);
         gen_noc_localparam_v_file($self,"$target_dir/noc$i",undef,$i);
@@ -135,65 +116,50 @@ sub generate_phynocs{
         $flist2.="-F  noc$i/noc_filelist_${append}.f\n";
         $nocs.="
     noc_top_${append} noc_${append} (
-	    .reset(reset),
-	    .clk(clk),    
-	    .chan_in_all(chan_in_$append),
-	    .chan_out_all(chan_out_$append),
-	    .router_event()
+        .reset(reset),
+        .clk(clk),
+        .chan_in_all(chan_in_$append),
+        .chan_out_all(chan_out_$append),
+        .router_event()
     );
 "
     }
     #copy common rtl modules
     my $cmd = "cp $pronoc_dir/mpsoc/rtl/*.v  $target_dir/";
     run_cmd_textview_errors ($cmd,$info);
-
-
     my $top=autogen_warning().get_license_header("${name}_top.v");
     $top.="module ${name}_top(
     reset,
-    clk,    
+    clk,
 $ports1
     );
-   
 $imports
-
     input reset,clk;
 $ports2
-
-$nocs    
+$nocs
 endmodule
     ";
-    
     save_file ("$target_dir/${name}_top.v",$top);
     save_file ("$target_dir/${name}.flist",$flist1.$flist2."./${name}_top.v");
-
-
     message_dialog("Multiple physical NoCs \"$name\" has been created successfully at $target_dir/ " );
     return 1;
 }
 
-
-
-
 sub build_phy_noc_gui {
     my ($self) = @_;
     set_gui_status($self,"ideal",0);
     $self->object_add_attribute ("process_notebook","currentpage",0);
     my $main_table= def_table(2,10,FALSE);
     add_param_widget ($self,"Phy NoCs #:" , undef, 3, 'Spin-button', "1,20,1","Specify the number of independent phisical NoCs. each NoC can have its unique set of parameter configuration.", $main_table,24,0,1, 'phy_num', 1,'ref_nocs','vertical');
-    
     my ($infobox,$info)= create_txview();
-    my $notebook = gen_notebook_phy($self,$info);        
+    my $notebook = gen_notebook_phy($self,$info);
     my $v2=gen_vpaned($notebook,.65,$infobox);
-    
-    
     my $pronoc_dir      = get_project_dir(); #mpsoc dir addr
     my $target_dir= "$ENV{PRONOC_WORK}/src_phy_nocs/";
-    
     my ($entrybox,$entry ) =gen_save_load_widget (
-        $self, #the object 
+        $self, #the object
         "Phy Name",#the label shown for setting configuration
-        'phy_name',#the key name for saveing the setting configuration in object 
+        'phy_name',#the key name for saveing the setting configuration in object
         'multiple physical NoCs',#the label full name show in tool tips
         $target_dir,#Where the generted RTL files are loacted. Undef if not aplicaple
         'soc',#check the given name match the SoC or mpsoc name rules
@@ -203,59 +169,46 @@ sub build_phy_noc_gui {
         $info
         );
     my $generate = def_image_button('icons/gen.png','Generate');
-
     $main_table->attach_defaults ($v2  , 0, 12, 0,24);
     $main_table->attach ($entrybox,3, 4, 24,25,'expand','shrink',2,2);
     $main_table->attach ($generate, 6, 9, 24,25,'expand','shrink',2,2);
     my $sc_win = add_widget_to_scrolled_win($main_table);
-        
-    $generate->signal_connect("clicked" => sub{ 
+    $generate->signal_connect("clicked" => sub{
         my $load= show_gif("icons/load.gif");
         $main_table->attach ($load, 9, 10, 24,25,'expand','shrink',2,2);
         $load->show_all;
-        generate_phynocs($self,$info);    
+        generate_phynocs($self,$info);
         $load->destroy;
-    });    
-
-    #check soc status every 0.5 second. refresh device table if there is any changes 
+    });
+    #check soc status every 0.5 second. refresh device table if there is any changes
     Glib::Timeout->add (100, sub{
         my ($state,$timeout)= get_gui_status($self);
-        
         if ($timeout>0){
             $timeout--;
-            set_gui_status($self,$state,$timeout);    
+            set_gui_status($self,$state,$timeout);
             return TRUE;
-            
         }
         if($state eq "ideal"){
             return TRUE;
-
         }
         if($state eq 'ref_nocs'){
             $notebook->destroy;
             $notebook = gen_notebook_phy($self,$info);
-            $v2 -> pack1($notebook, TRUE, TRUE);  
-            $v2 -> show_all; 
+            $v2 -> pack1($notebook, TRUE, TRUE);
+            $v2 -> show_all;
         } else { #only refresh current NoC setting
             my $page_num=$self->object_get_attribute ("process_notebook","currentpage");
             $pages[$page_num]->destroy;
             $pages[$page_num]=get_noc_num_page($self,$page_num,$info);
             add_widget_to_scrolled_win($pages[$page_num],$page_wins[$page_num]);
-            $page_wins[$page_num]->show_all;            
-        }  
-
+            $page_wins[$page_num]->show_all;
+        }
         my $saved_name=$self->object_get_attribute('save_as');
         $entry->set_text($saved_name)if(defined $saved_name);
-
         set_gui_status($self,"ideal",0);
-        $main_table->show_all();    
-
-
+        $main_table->show_all();
         return TRUE;
-    } );    
-
+    } );
     return $sc_win;
-
 }
-
-1;
+1;
\ No newline at end of file
diff --git a/mpsoc/perl_gui/lib/perl/readme_gen.pl b/mpsoc/perl_gui/lib/perl/readme_gen.pl
index b11d911..ad56f7b 100755
--- a/mpsoc/perl_gui/lib/perl/readme_gen.pl
+++ b/mpsoc/perl_gui/lib/perl/readme_gen.pl
@@ -3,70 +3,60 @@
 use Consts;
 
 sub get_license_header {
-	my $file_name=shift;
-	my $version = Consts::VERSION;
-	my $end  = Consts::END_YEAR;
-	my $head="
+    my $file_name=shift;
+    my $version = Consts::VERSION;
+    my $end  = Consts::END_YEAR;
+    my $head="
 /**********************************************************************
-**	File: $file_name
+**    File: $file_name
 **    
-**	Copyright (C) 2014-$end  Alireza Monemi
+**    Copyright (C) 2014-$end  Alireza Monemi
 **    
-**	This file is part of ProNoC $version 
+**    This file is part of ProNoC $version 
 **
-**	ProNoC ( stands for Prototype Network-on-chip)  is free software: 
-**	you can redistribute it and/or modify it under the terms of the GNU
-**	Lesser General Public License as published by the Free Software Foundation,
-**	either version 2 of the License, or (at your option) any later version.
+**    ProNoC ( stands for Prototype Network-on-chip)  is free software: 
+**    you can redistribute it and/or modify it under the terms of the GNU
+**    Lesser General Public License as published by the Free Software Foundation,
+**    either version 2 of the License, or (at your option) any later version.
 **
-** 	ProNoC is distributed in the hope that it will be useful, but WITHOUT
-** 	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
-** 	or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
-** 	Public License for more details.
+**     ProNoC is distributed in the hope that it will be useful, but WITHOUT
+**     ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+**     or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
+**     Public License for more details.
 **
-** 	You should have received a copy of the GNU Lesser General Public
-** 	License along with ProNoC. If not, see <http:**www.gnu.org/licenses/>.
+**     You should have received a copy of the GNU Lesser General Public
+**     License along with ProNoC. If not, see <http:**www.gnu.org/licenses/>.
 ******************************************************************************/ 
 ";
-
-
 return $head;
-
 }
 
 
 sub autogen_warning {
-
 my $string ="
 /**************************************************************************
-**	WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT ARE LIKELY TO BE
-**	OVERWRITTEN AND LOST. Rename this file if you wish to do any modification.
+**    WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT ARE LIKELY TO BE
+**    OVERWRITTEN AND LOST. Rename this file if you wish to do any modification.
 ****************************************************************************/\n\n";
-
 return $string;
-
-
 }
 
 
 sub perl_file_header {
-	my $file_name=shift;
-	my $version = Consts::VERSION;
-	my $end  = Consts::END_YEAR;
+    my $file_name=shift;
+    my $version = Consts::VERSION;
+    my $end  = Consts::END_YEAR;
 my $head="#######################################################################
-##	File: $file_name
+##    File: $file_name
 ##    
-##	Copyright (C) 2014-$end  Alireza Monemi
+##    Copyright (C) 2014-$end  Alireza Monemi
 ##    
-##	This file is part of ProNoC $version 
+##    This file is part of ProNoC $version 
 ##
-## 	WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT 
-##	MAY CAUSE UNEXPECTED BEHAVIOR.
+##     WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT 
+##    MAY CAUSE UNEXPECTED BEHAVIOR.
 ################################################################################
-
 ";
 return $head;
 }
-
-
-1;
+1;
\ No newline at end of file
diff --git a/mpsoc/perl_gui/lib/perl/run_time_jtag_debug.pl b/mpsoc/perl_gui/lib/perl/run_time_jtag_debug.pl
index be31727..d3c92a5 100644
--- a/mpsoc/perl_gui/lib/perl/run_time_jtag_debug.pl
+++ b/mpsoc/perl_gui/lib/perl/run_time_jtag_debug.pl
@@ -1,19 +1,15 @@
 #!/usr/bin/perl -w
 use strict;
 use warnings;
-
 use constant::boolean;
-
 use FindBin;
 use lib $FindBin::Bin;
-
 use Data::Dumper;
 use File::Which;
 use File::Basename;
-
 use IPC::Run qw( harness start pump finish timeout );
-
 use Consts;
+
 BEGIN {
     my $module = (Consts::GTK_VERSION==2) ? 'Gtk2' : 'Gtk3';
     my $file = $module;
@@ -23,928 +19,669 @@ BEGIN
     $module->import;
 }
 
-
-
 require "widget.pl";
 require "uart.pl";
 require "compile.pl";
-
-
 use String::Scanf; # imports sscanf()
-
-
 use constant JTAG_UPDATE_WB_ADDR => 7;
 use constant JTAG_UPDATE_WB_WR_DATA=>  6;
-use constant JTAG_UPDATE_WB_RD_DATA => 5;	
-
-
+use constant JTAG_UPDATE_WB_RD_DATA => 5;
 use base 'Class::Accessor::Fast';
+
 __PACKAGE__->mk_accessors(qw{
-	window
-	sourceview		
+    window
+    sourceview
 });
 
 my $NAME = 'Soure Probe';
-my 	$path = "";
-
-
-
+my     $path = "";
 my %memory;
 my %status;
 
-
 sub source_probe_stand_alone(){
-	$path = "../../";
-	set_path_env();
-	my $project_dir	  = get_project_dir(); #mpsoc dir addr
-	my $paths_file= "$project_dir/mpsoc/perl_gui/lib/Paths";
-	if (-f 	$paths_file){#} && defined $ENV{PRONOC_WORK} ) {
-		my $paths= do $paths_file;
-		set_gui_setting($paths);
-	}
-	
-	set_defualt_font_size();
-	my $window=source_probe_main();
-	$window->signal_connect (destroy => sub { gui_quite();});
+    $path = "../../";
+    set_path_env();
+    my $project_dir      = get_project_dir(); #mpsoc dir addr
+    my $paths_file= "$project_dir/mpsoc/perl_gui/lib/Paths";
+    if (-f     $paths_file){#} && defined $ENV{PRONOC_WORK} ) {
+        my $paths= do $paths_file;
+        set_gui_setting($paths);
+    }
+    set_defualt_font_size();
+    my $window=source_probe_main();
+    $window->signal_connect (destroy => sub { gui_quite();});
 }
 
 exit gtk_gui_run(\&source_probe_stand_alone) unless caller;
 
-
 sub get_jtag_intfc_rst_cmd {
-	my $self=shift;
-	
-	my $vendor = $self->object_get_attribute('CTRL','VENDOR');
-	my $board  = $self->object_get_attribute('CTRL','Board_Name');
-	my $chain  = $self->object_get_attribute('CTRL','RESET_CHAIN');
-	my $index  = 127;
-	my $pronoc = get_project_dir();
-	my $intfc = "$pronoc/mpsoc/boards/$vendor/$board/jtag_intfc.sh";
-	#my $script  = "$ENV{'PRONOC_WORK'}/tmp/script.bash";
-	
-	my $t = ($vendor eq 'Xilinx') ? "-t  $chain " : "";
-	
-	my $cmd = "bash -c \"source $intfc; \\\$JTAG_INTFC $t -n $index";
-	return $cmd;
-	
+    my $self=shift;
+    my $vendor = $self->object_get_attribute('CTRL','VENDOR');
+    my $board  = $self->object_get_attribute('CTRL','Board_Name');
+    my $chain  = $self->object_get_attribute('CTRL','RESET_CHAIN');
+    my $index  = 127;
+    my $pronoc = get_project_dir();
+    my $intfc = "$pronoc/mpsoc/boards/$vendor/$board/jtag_intfc.sh";
+    #my $script  = "$ENV{'PRONOC_WORK'}/tmp/script.bash";
+    my $t = ($vendor eq 'Xilinx') ? "-t  $chain " : "";
+    my $cmd = "bash -c \"source $intfc; \\\$JTAG_INTFC $t -n $index";
+    return $cmd;
 }
 
-
 sub jtag_enable_cpus_func{
-	my ($self,$new,$tview)=@_;
-	my $intfc = get_jtag_intfc_rst_cmd($self);
+    my ($self,$new,$tview)=@_;
+    my $intfc = get_jtag_intfc_rst_cmd($self);
     my $e = ($new eq 'Enabled')? 0 : 2;
-	my $cmd =	"$intfc  -d   I:1,D:2:$e,I:0\"";
-	add_info($tview,"$cmd\n");	
-	my $results =run_cmd_textview_errors($cmd,$tview);
-	return 1 if(!defined $results);
-
+    my $cmd =    "$intfc  -d   I:1,D:2:$e,I:0\"";
+    add_info($tview,"$cmd\n");
+    my $results =run_cmd_textview_errors($cmd,$tview);
+    return 1 if(!defined $results);
 }
 
 sub jtag_reset_cpus_func {
-	my ($self,$tview)=@_;
-	my $intfc = get_jtag_intfc_rst_cmd($self);
-
-	my $cmd =	"$intfc  -d   I:1,D:2:1,D:2:0,I:0\"";
-	add_info($tview,"$cmd\n");	
-	my $results =run_cmd_textview_errors($cmd,$tview);
-	return 1 if(!defined $results);
-			
-};	
-
-
-
-
-
+    my ($self,$tview)=@_;
+    my $intfc = get_jtag_intfc_rst_cmd($self);
+    my $cmd =    "$intfc  -d   I:1,D:2:1,D:2:0,I:0\"";
+    add_info($tview,"$cmd\n");
+    my $results =run_cmd_textview_errors($cmd,$tview);
+    return 1 if(!defined $results);
+};
 sub source_probe_ctrl {
-	my ($self,$tview)=@_;
-	my $table= def_table(2,10,FALSE);
-	
-	my $vendor= $self->object_get_attribute('CTRL','VENDOR');
-	$vendor= 'Xilinx' if(!defined $vendor);
-	
-	
-	#get the list of boards located in "boards/*" folder
-	my $pronoc = get_project_dir();
-
-	my @dirs = grep {-d} glob("$pronoc/mpsoc/boards/$vendor/*");
-	my ($fpgas,$init);
-	
-	
-	foreach my $dir (@dirs) {
-		my ($name,$path,$suffix) = fileparse("$dir",qr"\..[^.]*$");		
-		$fpgas= (defined $fpgas)? "$fpgas,$name" : "$name";	
-		$init="$name";	
-	}
-	
-	
-	my @info = (
-	{ label=>" FPGA Vendor name: ", param_name=>'VENDOR', type=>"Combo-box", default_val=>'Xilinx', content=>"Xilinx,Altera", info=>undef, param_parent=>'CTRL', ref_delay=> 1, new_status=>'ref_ctrl', loc=>'vertical'},
-	{ label=>" Board Name ", param_name=>'Board_Name', type=>"Combo-box", default_val=>$init, content=>$fpgas, info=>undef, param_parent=>'CTRL', ref_delay=> undef, new_status=>undef, loc=>'vertical'},
-	{ label=>" JTAG Index: ", param_name=>'JTAG_INDEX', type=>"Spin-button", default_val=>0, content=>"0,128,1", info=>undef, param_parent=>'CTRL', ref_delay=> undef, new_status=> undef, loc=>'vertical'}	
-	);	
-	
-	
-	
-	if ($vendor eq "Xilinx" ) {
-		push (@info,{ label=>" JTAG CHAIN ", param_name=>'JTAG_CHAIN', type=>"Combo-box", default_val=>4, content=>"1,2,3,4", info=>undef, param_parent=>'CTRL', ref_delay=> 0, new_status=>'ref_ctrl', loc=>'vertical'}) ;
-
-	}
-	
-		
-	my ($row,$col)=(0,6);
-	
-	foreach my $d (@info) {
-		my $wiget;		
-		($row,$col,$wiget)=add_param_widget  ($self, $d->{label}, $d->{param_name}, $d->{default_val}, $d->{type}, $d->{content}, $d->{info}, $table,$row,$col,1, $d->{param_parent}, $d->{ref_delay}, $d->{new_status}, $d->{loc});
-		my $sc=$col;
-		if($d->{param_name} eq 'Board_Name'){
-			my $add=def_image_button("icons/plus.png");
-			$table->attach ($add,  $sc+4, $sc+5,$row-1,$row,'shrink','shrink',2,2); 
-			set_tip($add, "Add new FPGA Board"); 
-			$add-> signal_connect("clicked" => sub{
-				add_new_fpga_board($self,undef,undef,undef,undef,$vendor);
-			}); 			
-			
-		}
-	
-	
-	}	
-	
-	 
-	 $table->attach (  gen_Vsep(), 5, 6 , 0, $row+1,'fill','fill',2,2);
-	
-	#Column 2
-	$row=0;$col=0;
-	my $d={ label=>" Number of Sources/Probes:", param_name=>'SP_NUM', type=>"Spin-button", default_val=>1, content=>"1,128,1", info=>undef, param_parent=>'CTRL', ref_delay=> 1, new_status=>'ref_all', loc=>'vertical'};		
-	($row,$col)=add_param_widget  ($self, $d->{label}, $d->{param_name}, $d->{default_val}, $d->{type}, $d->{content}, $d->{info}, $table,$row,$col,1, $d->{param_parent}, $d->{ref_delay}, $d->{new_status}, $d->{loc});
-	$d={ label=>" Address format: ", param_name=>'R_ADDR_FORMAT', type=>"Combo-box", default_val=>'Decimal', content=>"Decimal,Hexadecimal", info=>undef, param_parent=>'FILE_VIEW', ref_delay=> 1, new_status=>'ref_file_view', loc=>'vertical'},
-	($row,$col)=add_param_widget  ($self, $d->{label}, $d->{param_name}, $d->{default_val}, $d->{type}, $d->{content}, $d->{info}, $table,$row,$col,1, $d->{param_parent}, $d->{ref_delay}, $d->{new_status}, $d->{loc});
-	
-	
-	#enable
-	my $en_state=$self->object_get_attribute("CTRL","enable");
-	if (!defined $en_state){
-		$en_state='Enabled' ;
-		$self->object_add_attribute("CTRL","enable",$en_state);
-	}		
-	my $enable= ($en_state eq 'Enabled')? def_colored_button('Enabled',17): def_colored_button('Disabled',4);
-	
-	my $reset= def_button('Reset');
-	
-	if ($vendor eq "Xilinx" ) {
-	
-		my $w=gen_combobox_object ($self,'CTRL','RESET_CHAIN',"4,3,2,1","4",undef,undef);
-		my $h=gen_button_message ("The JTAG remote reset/enable is connected to the Jtag tab chain with the largest chain number in each tile.  ","icons/help.png");
-		my $b= def_pack_hbox(FALSE,0,(gen_label_in_center  ("CPU(s) Chain:"),$w,$h));
-		$table->attach ($b ,  $col, $col+1,$row,$row+1,'shrink','shrink',2,2); $col+=1;
-	
-	}else{	
-		$table->attach (gen_label_in_center  ("CPU(s)") ,  $col, $col+1,$row,$row+1,'shrink','shrink',2,2); $col+=1;
-	}
-	
-	$table->attach ($reset ,  $col, $col+1,$row,$row+1,'shrink','shrink',2,2); $col+=1;
-	$table->attach ($enable ,  $col, $col+1,$row,$row+1,'shrink','shrink',2,2); $row++;
-	
-	$enable -> signal_connect("clicked" => sub{ 
-			my $en_state=$self->object_get_attribute("CTRL","enable");			
-			my $new = ($en_state eq 'Enabled')? 'Disabled' : 'Enabled';
-			jtag_enable_cpus_func($self,$new,$tview);
-			$self->object_add_attribute("CTRL","enable",$new);	
-			set_gui_status($self,"ref",1);		
-	});	
-	
-	$reset -> signal_connect("clicked" => sub{ 
-			jtag_reset_cpus_func($self,$tview);		
-	});	
-	
-	
-	my $scrolled_win=gen_scr_win_with_adjst ($self,"receive_box");
-	add_widget_to_scrolled_win($table,$scrolled_win);
-	return $scrolled_win;		
+    my ($self,$tview)=@_;
+    my $table= def_table(2,10,FALSE);
+    my $vendor= $self->object_get_attribute('CTRL','VENDOR');
+    $vendor= 'Xilinx' if(!defined $vendor);
+    #get the list of boards located in "boards/*" folder
+    my $pronoc = get_project_dir();
+    my @dirs = grep {-d} glob("$pronoc/mpsoc/boards/$vendor/*");
+    my ($fpgas,$init);
+    foreach my $dir (@dirs) {
+        my ($name,$path,$suffix) = fileparse("$dir",qr"\..[^.]*$");
+        $fpgas= (defined $fpgas)? "$fpgas,$name" : "$name";
+        $init="$name";
+    }
+    my @info = (
+    { label=>" FPGA Vendor name: ", param_name=>'VENDOR', type=>"Combo-box", default_val=>'Xilinx', content=>"Xilinx,Altera", info=>undef, param_parent=>'CTRL', ref_delay=> 1, new_status=>'ref_ctrl', loc=>'vertical'},
+    { label=>" Board Name ", param_name=>'Board_Name', type=>"Combo-box", default_val=>$init, content=>$fpgas, info=>undef, param_parent=>'CTRL', ref_delay=> undef, new_status=>undef, loc=>'vertical'},
+    { label=>" JTAG Index: ", param_name=>'JTAG_INDEX', type=>"Spin-button", default_val=>0, content=>"0,128,1", info=>undef, param_parent=>'CTRL', ref_delay=> undef, new_status=> undef, loc=>'vertical'}
+    );
+    if ($vendor eq "Xilinx" ) {
+        push (@info,{ label=>" JTAG CHAIN ", param_name=>'JTAG_CHAIN', type=>"Combo-box", default_val=>4, content=>"1,2,3,4", info=>undef, param_parent=>'CTRL', ref_delay=> 0, new_status=>'ref_ctrl', loc=>'vertical'}) ;
+    }
+    my ($row,$col)=(0,6);
+    foreach my $d (@info) {
+        my $wiget;
+        ($row,$col,$wiget)=add_param_widget  ($self, $d->{label}, $d->{param_name}, $d->{default_val}, $d->{type}, $d->{content}, $d->{info}, $table,$row,$col,1, $d->{param_parent}, $d->{ref_delay}, $d->{new_status}, $d->{loc});
+        my $sc=$col;
+        if($d->{param_name} eq 'Board_Name'){
+            my $add=def_image_button("icons/plus.png");
+            $table->attach ($add,  $sc+4, $sc+5,$row-1,$row,'shrink','shrink',2,2);
+            set_tip($add, "Add new FPGA Board");
+            $add-> signal_connect("clicked" => sub{
+                add_new_fpga_board($self,undef,undef,undef,undef,$vendor);
+            });
+        }
+    }
+    $table->attach (  gen_Vsep(), 5, 6 , 0, $row+1,'fill','fill',2,2);
+    #Column 2
+    $row=0;$col=0;
+    my $d={ label=>" Number of Sources/Probes:", param_name=>'SP_NUM', type=>"Spin-button", default_val=>1, content=>"1,128,1", info=>undef, param_parent=>'CTRL', ref_delay=> 1, new_status=>'ref_all', loc=>'vertical'};
+    ($row,$col)=add_param_widget  ($self, $d->{label}, $d->{param_name}, $d->{default_val}, $d->{type}, $d->{content}, $d->{info}, $table,$row,$col,1, $d->{param_parent}, $d->{ref_delay}, $d->{new_status}, $d->{loc});
+    $d={ label=>" Address format: ", param_name=>'R_ADDR_FORMAT', type=>"Combo-box", default_val=>'Decimal', content=>"Decimal,Hexadecimal", info=>undef, param_parent=>'FILE_VIEW', ref_delay=> 1, new_status=>'ref_file_view', loc=>'vertical'},
+    ($row,$col)=add_param_widget  ($self, $d->{label}, $d->{param_name}, $d->{default_val}, $d->{type}, $d->{content}, $d->{info}, $table,$row,$col,1, $d->{param_parent}, $d->{ref_delay}, $d->{new_status}, $d->{loc});
+    #enable
+    my $en_state=$self->object_get_attribute("CTRL","enable");
+    if (!defined $en_state){
+        $en_state='Enabled' ;
+        $self->object_add_attribute("CTRL","enable",$en_state);
+    }
+    my $enable= ($en_state eq 'Enabled')? def_colored_button('Enabled',17): def_colored_button('Disabled',4);
+    my $reset= def_button('Reset');
+    if ($vendor eq "Xilinx" ) {
+        my $w=gen_combobox_object ($self,'CTRL','RESET_CHAIN',"4,3,2,1","4",undef,undef);
+        my $h=gen_button_message ("The JTAG remote reset/enable is connected to the Jtag tab chain with the largest chain number in each tile.  ","icons/help.png");
+        my $b= def_pack_hbox(FALSE,0,(gen_label_in_center  ("CPU(s) Chain:"),$w,$h));
+        $table->attach ($b ,  $col, $col+1,$row,$row+1,'shrink','shrink',2,2); $col+=1;
+    }else{
+        $table->attach (gen_label_in_center  ("CPU(s)") ,  $col, $col+1,$row,$row+1,'shrink','shrink',2,2); $col+=1;
+    }
+    $table->attach ($reset ,  $col, $col+1,$row,$row+1,'shrink','shrink',2,2); $col+=1;
+    $table->attach ($enable ,  $col, $col+1,$row,$row+1,'shrink','shrink',2,2); $row++;
+    $enable -> signal_connect("clicked" => sub{
+            my $en_state=$self->object_get_attribute("CTRL","enable");
+            my $new = ($en_state eq 'Enabled')? 'Disabled' : 'Enabled';
+            jtag_enable_cpus_func($self,$new,$tview);
+            $self->object_add_attribute("CTRL","enable",$new);
+            set_gui_status($self,"ref",1);
+    });
+    $reset -> signal_connect("clicked" => sub{
+            jtag_reset_cpus_func($self,$tview);
+    });
+    my $scrolled_win=gen_scr_win_with_adjst ($self,"receive_box");
+    add_widget_to_scrolled_win($table,$scrolled_win);
+    return $scrolled_win;
 }
 
-
-
-
-
-
-
-
 sub soure_probe_widgets_old {
-	my $self=shift;
-	my $table= def_table(2,10,FALSE);	
-	my $scrolled_win=gen_scr_win_with_adjst ($self,"receive_box");
-	add_widget_to_scrolled_win($table,$scrolled_win);
-	my $num = $self->object_get_attribute('CTRL','SP_NUM');
-	
-	my $y= 0;
-   	my $x= 0; 	
-	
-	$table->attach (gen_label_in_center(" Source "), 0, 3 , $y, $y+1,'shrink','shrink',2,2); 
-	$table->attach (gen_label_in_center(" Probe  "), 4, 7 , $y, $y+1,'shrink','shrink',2,2); 
-	$y++;
-	$table->attach ( gen_Hsep(), 0, 7 , $y, $y+1, 'fill','shrink',2,2); 
-	
-	$y++;
-	my @sources;
-	for (my $i=0; $i<$num; $i+=1){	
-			my $n=$i+1;
-			$table->attach (gen_label_in_left("  $n- "), $x, $x+1 , $y, $y+1,'shrink','shrink',2,2); $x++;
-			my $entry=gen_entry( );
-			$table->attach ($entry, $x, $x+1 , $y, $y+1,'shrink','shrink',2,2); $x++;			
-  			
-    		my $enter=def_image_button("icons/write.png","Write");   		
-
-	        $table->attach ($enter, $x, $x+1 , $y, $y+1,'shrink','shrink',2,2); $x++;
-	       
-	        $x++; #sep
-	       
-	        #probe 
-	        #$table->attach (gen_label_in_left(" Probe:  " )	, $x, $x+1 , $y, $y+1,'shrink','shrink',2,2); $x++; 
-	        my $probe_val = $self-> object_get_attribute('SP','PROBE_$n');
-	      
-	        my $probe_label= gen_label_in_left(" "); 
-	        
-	        ${probe_val}=25 if ($n ==1);
-	        
-	        $probe_label->set_markup("<span  foreground= 'red' ><b>XXXX</b></span>") if(!defined $probe_val );	
-	        $probe_label->set_markup("<span  foreground= 'blue' ><b></b>    ${probe_val}   </span>") unless(!defined $probe_val );	
-	        
-	        my $frame = gen_frame();
-			$frame->set_shadow_type ('in');
-			# Animation
-			$frame->add ($probe_label);
-	        
-	        
-	        $table->attach ($frame, $x, $x+1 , $y, $y+1,'shrink','shrink',2,2); $x++; 
-	        my $read=def_image_button("icons/simulator.png","Read"); 
-	        $table->attach ($read, $x, $x+1 , $y, $y+1,'shrink','shrink',2,2); $x++;
-	        
-	        $y++; $x=0; 
-	        $table->attach (gen_Hsep(), 0, 7 , $y, $y+1, 'fill','shrink',2,2); 
-	        $y++;	     
-	        
-	}	
-	
-	  $table->attach ( gen_Vsep(), 3, 4 , 0, $y+1,'fill','fill',2,2);
-	  $table->attach ( gen_Vsep(), 6, 7 , 0, $y+1,'fill','fill',2,2);
-	
-	return ($scrolled_win,\@sources);
+    my $self=shift;
+    my $table= def_table(2,10,FALSE);
+    my $scrolled_win=gen_scr_win_with_adjst ($self,"receive_box");
+    add_widget_to_scrolled_win($table,$scrolled_win);
+    my $num = $self->object_get_attribute('CTRL','SP_NUM');
+    my $y= 0;
+    my $x= 0;
+    $table->attach (gen_label_in_center(" Source "), 0, 3 , $y, $y+1,'shrink','shrink',2,2);
+    $table->attach (gen_label_in_center(" Probe  "), 4, 7 , $y, $y+1,'shrink','shrink',2,2);
+    $y++;
+    $table->attach ( gen_Hsep(), 0, 7 , $y, $y+1, 'fill','shrink',2,2);
+    $y++;
+    my @sources;
+    for (my $i=0; $i<$num; $i+=1){
+            my $n=$i+1;
+            $table->attach (gen_label_in_left("  $n- "), $x, $x+1 , $y, $y+1,'shrink','shrink',2,2); $x++;
+            my $entry=gen_entry( );
+            $table->attach ($entry, $x, $x+1 , $y, $y+1,'shrink','shrink',2,2); $x++;
+            my $enter=def_image_button("icons/write.png","Write");
+            $table->attach ($enter, $x, $x+1 , $y, $y+1,'shrink','shrink',2,2); $x++;
+            $x++; #sep
+            #probe
+            #$table->attach (gen_label_in_left(" Probe:  " )    , $x, $x+1 , $y, $y+1,'shrink','shrink',2,2); $x++;
+            my $probe_val = $self-> object_get_attribute('SP','PROBE_$n');
+            my $probe_label= gen_label_in_left(" ");
+            ${probe_val}=25 if ($n ==1);
+            $probe_label->set_markup("<span  foreground= 'red' ><b>XXXX</b></span>") if(!defined $probe_val );
+            $probe_label->set_markup("<span  foreground= 'blue' ><b></b>    ${probe_val}   </span>") unless(!defined $probe_val );
+            my $frame = gen_frame();
+            $frame->set_shadow_type ('in');
+            # Animation
+            $frame->add ($probe_label);
+            $table->attach ($frame, $x, $x+1 , $y, $y+1,'shrink','shrink',2,2); $x++;
+            my $read=def_image_button("icons/simulator.png","Read");
+            $table->attach ($read, $x, $x+1 , $y, $y+1,'shrink','shrink',2,2); $x++;
+            $y++; $x=0;
+            $table->attach (gen_Hsep(), 0, 7 , $y, $y+1, 'fill','shrink',2,2);
+            $y++;
+    }
+    $table->attach ( gen_Vsep(), 3, 4 , 0, $y+1,'fill','fill',2,2);
+    $table->attach ( gen_Vsep(), 6, 7 , 0, $y+1,'fill','fill',2,2);
+    return ($scrolled_win,\@sources);
 }
 
 sub read_mem_specefic_addr{
-	my ($self,$addr,$tview)=@_;
-	add_info($tview,"Read addr: $addr\n"); 	
-	my $intfc = get_jtag_intfc_cmd($self);
-	$addr=($addr>>2);
-	$addr=sprintf("%x",$addr);
-	my $cmd =	"$intfc -d  I:${\JTAG_UPDATE_WB_RD_DATA},R:32:$addr,I:0\"";
-	add_info($tview,"$cmd\n");	
-	my $results =run_cmd_textview_errors($cmd,$tview);
-	return 1 if(!defined $results);	
-	my ($hex)= sscanf("###read data#0x%s###read data#", $results);
-	###read data#0x18000000###read data#
-	#add_info($tview," $results \n"); 	
-	#add_info($tview," $hex \n"); 	
-	return $hex;
+    my ($self,$addr,$tview)=@_;
+    add_info($tview,"Read addr: $addr\n");
+    my $intfc = get_jtag_intfc_cmd($self);
+    $addr=($addr>>2);
+    $addr=sprintf("%x",$addr);
+    my $cmd =    "$intfc -d  I:${\JTAG_UPDATE_WB_RD_DATA},R:32:$addr,I:0\"";
+    add_info($tview,"$cmd\n");
+    my $results =run_cmd_textview_errors($cmd,$tview);
+    return 1 if(!defined $results);
+    my ($hex)= sscanf("###read data#0x%s###read data#", $results);
+    ###read data#0x18000000###read data#
+    #add_info($tview," $results \n");
+    #add_info($tview," $hex \n");
+    return $hex;
 }
 
-
 sub write_mem_specefic_addr {
-	my ($self,$addr,$value,$tview)=@_;
-	my $intfc = get_jtag_intfc_cmd($self);
-	$addr=($addr>>2);
-	$addr=sprintf("%x",$addr);
-	my $cmd =	"$intfc -d  I:${\JTAG_UPDATE_WB_ADDR},D:32:$addr,I:${\JTAG_UPDATE_WB_WR_DATA},D:32:$value,I:0\"";
-	add_info($tview,"$cmd\n");	
-	my $results =run_cmd_textview_errors($cmd,$tview);
-	return 1 if(!defined $results);
-}	
+    my ($self,$addr,$value,$tview)=@_;
+    my $intfc = get_jtag_intfc_cmd($self);
+    $addr=($addr>>2);
+    $addr=sprintf("%x",$addr);
+    my $cmd =    "$intfc -d  I:${\JTAG_UPDATE_WB_ADDR},D:32:$addr,I:${\JTAG_UPDATE_WB_WR_DATA},D:32:$value,I:0\"";
+    add_info($tview,"$cmd\n");
+    my $results =run_cmd_textview_errors($cmd,$tview);
+    return 1 if(!defined $results);
+}
 
 sub soure_probe_widgets {
-	my ($self,$tview)=@_;
-	my $table= def_table(2,10,FALSE);	
-	my $scrolled_win=gen_scr_win_with_adjst ($self,"receive_box");
-	add_widget_to_scrolled_win($table,$scrolled_win);
-	my $num = $self->object_get_attribute('CTRL','SP_NUM');
-	$num = 1 if (!defined $num);
-	my $y= 0;
-   	my $x= 0; 	
-	
-	
-
-
-	
-	$table->attach (gen_label_in_center(" Address (in byte)"), 0, 1 , $y, $y+1,'shrink','shrink',2,2); 
-	$table->attach (gen_label_in_center(" Memory Content  "), 2, 3 , $y, $y+1,'shrink','shrink',2,2); 
-	$table->attach (gen_label_in_center(" Action "), 4, 6 , $y, $y+1,'shrink','shrink',2,2); 
-	$y++;
-	
-	$table->attach ( gen_Hsep(), 0, 6 , $y, $y+1, 'fill','shrink',2,2); 
-	
-	$y++;
-	$x= 0; 	
-	
-	for (my $i=0; $i<$num; $i+=1){	
-			my $n=$i+1;
-			my $status=0;
-			#$table->attach (gen_label_in_left("  $n-address "), $x, $x+1 , $y, $y+1,'shrink','shrink',2,2); $x++;
-		#	($y,$x,$addr)=add_param_widget  ($self,"$n-", "$n-address", 0, "Spin-button", "0,99999999,1", undef, $table,$y,$x,1, "JTAG_WB", undef, undef, 'horizontal');
-		   # ($y,$x,$entry)=add_param_widget  ($self,undef, "$n-value", 0, "Entry", undef, undef, $table,$y,$x,1, "JTAG_WB", undef, undef, 'horizontal');
-		    
-		    my $addr = gen_entry(0);
-		    my $entry =gen_entry('xxxxxxxx');	   
-		    my $read=def_image_button($path."icons/simulator.png","Read"); 
-		    my $write=def_image_button($path."icons/write.png","Write"); 		    
-		   
-		    
-		    $entry->set_max_length (8);
-			$entry->set_width_chars(8);
-			
-			$table->attach ($addr, $x, $x+1 , $y, $y+1,'shrink','shrink',2,2); $x+=2;	
-		    $table->attach ($entry, $x, $x+1 , $y, $y+1,'shrink','shrink',2,2); $x+=2;		  
-	        $table->attach ($read, $x, $x+1 , $y, $y+1,'shrink','shrink',2,2);  $x++; 		   
-			$table->attach ($write, $x, $x+1 , $y, $y+1,'shrink','shrink',2,2); $x++;
-			my $sy= $y;
-			my $sx=7; 
-			        
-	        $y++; $x=0; 
-	        $table->attach ( gen_Hsep(), 0, $sx , $y, $y+1, 'fill','shrink',2,2); 
-	        $y++;
-	        
-	      
-	        
-	        $read-> signal_connect("clicked" => sub{
-	        	my $address=$addr->get_text();
-	        	my $format =$self->	object_get_attribute('FILE_VIEW','R_ADDR_FORMAT');
-				$format= 'Decimal' if (!defined $format);
-	        	$address = hex($address) unless($format eq 'Decimal');	        	
-	        	my $load= show_gif("icons/load.gif");
-				$table->attach ($load,$sx, $sx+1 , $sy, $sy+1,'shrink','shrink',0,0);
-				$table->show_all();
-	        	my $val =read_mem_specefic_addr($self,$address,$tview);
-	        	$entry->set_text($val) if (defined $val);
-	        	$status =1;
-	        	entry_set_text_color($entry,-1);
-	        	$load->destroy;
-	        });
-	        
-	        $write-> signal_connect("clicked" => sub{
-	        	my $value = $entry->get_text();
-	        	my $address=$addr->get_text();
-	        	my $format =$self->	object_get_attribute('FILE_VIEW','R_ADDR_FORMAT');
-				$format= 'Decimal' if (!defined $format);
-	        	$address = hex($address) unless($format eq 'Decimal');
-	        	my $load= show_gif("icons/load.gif");
-				$table->attach ($load,$sx, $sx+1 , $sy, $sy+1,'shrink','shrink',0,0);
-				$table->show_all();
-	        	write_mem_specefic_addr($self,$address,$value,$tview);
-	        	$status =1;
-	        	entry_set_text_color($entry,-1);
-	        	$load->destroy;
-	        	
-	        });
-	        
-	        $entry->signal_connect("changed" => sub{
-				if($status==0 || $status==1 ){
-					$status =2;#modified
-					#change color to red
-					entry_set_text_color($entry,11);
-					
-				}
-				my $in = $entry->get_text();
-				$entry->set_text(remove_not_hex($in));
-				
-			});	
-			
-			
-			$addr->signal_connect("changed" => sub{
-				my $format =$self->	object_get_attribute('FILE_VIEW','R_ADDR_FORMAT');
-				$format= 'Decimal' if (!defined $format);
-				my $in = $addr->get_text();
-				$addr->set_text(remove_not_hex($in)) if ($format ne 'Decimal' );
-				$addr->set_text(remove_not_number($in)) if ($format eq 'Decimal' );
-			});	
-	        
-	}	
-	
-	$table->attach ( gen_Vsep(), 1, 2 , 0, $y+1,'fill','fill',2,2);
-	$table->attach ( gen_Vsep(), 3, 4 , 0, $y+1,'fill','fill',2,2);
-	$table->attach ( gen_Vsep(), 6, 7 , 0, $y+1,'fill','fill',2,2);
-		
-	return $scrolled_win;
+    my ($self,$tview)=@_;
+    my $table= def_table(2,10,FALSE);
+    my $scrolled_win=gen_scr_win_with_adjst ($self,"receive_box");
+    add_widget_to_scrolled_win($table,$scrolled_win);
+    my $num = $self->object_get_attribute('CTRL','SP_NUM');
+    $num = 1 if (!defined $num);
+    my $y= 0;
+    my $x= 0;
+    $table->attach (gen_label_in_center(" Address (in byte)"), 0, 1 , $y, $y+1,'shrink','shrink',2,2);
+    $table->attach (gen_label_in_center(" Memory Content  "), 2, 3 , $y, $y+1,'shrink','shrink',2,2);
+    $table->attach (gen_label_in_center(" Action "), 4, 6 , $y, $y+1,'shrink','shrink',2,2);
+    $y++;
+    $table->attach ( gen_Hsep(), 0, 6 , $y, $y+1, 'fill','shrink',2,2);
+    $y++;
+    $x= 0;
+    for (my $i=0; $i<$num; $i+=1){
+            my $n=$i+1;
+            my $status=0;
+            #$table->attach (gen_label_in_left("  $n-address "), $x, $x+1 , $y, $y+1,'shrink','shrink',2,2); $x++;
+        #    ($y,$x,$addr)=add_param_widget  ($self,"$n-", "$n-address", 0, "Spin-button", "0,99999999,1", undef, $table,$y,$x,1, "JTAG_WB", undef, undef, 'horizontal');
+        # ($y,$x,$entry)=add_param_widget  ($self,undef, "$n-value", 0, "Entry", undef, undef, $table,$y,$x,1, "JTAG_WB", undef, undef, 'horizontal');
+            my $addr = gen_entry(0);
+            my $entry =gen_entry('xxxxxxxx');
+            my $read=def_image_button($path."icons/simulator.png","Read");
+            my $write=def_image_button($path."icons/write.png","Write");
+            $entry->set_max_length (8);
+            $entry->set_width_chars(8);
+            $table->attach ($addr, $x, $x+1 , $y, $y+1,'shrink','shrink',2,2); $x+=2;
+            $table->attach ($entry, $x, $x+1 , $y, $y+1,'shrink','shrink',2,2); $x+=2;
+            $table->attach ($read, $x, $x+1 , $y, $y+1,'shrink','shrink',2,2);  $x++;
+            $table->attach ($write, $x, $x+1 , $y, $y+1,'shrink','shrink',2,2); $x++;
+            my $sy= $y;
+            my $sx=7;
+            $y++; $x=0;
+            $table->attach ( gen_Hsep(), 0, $sx , $y, $y+1, 'fill','shrink',2,2);
+            $y++;
+            $read-> signal_connect("clicked" => sub{
+                my $address=$addr->get_text();
+                my $format =$self->    object_get_attribute('FILE_VIEW','R_ADDR_FORMAT');
+                $format= 'Decimal' if (!defined $format);
+                $address = hex($address) unless($format eq 'Decimal');
+                my $load= show_gif("icons/load.gif");
+                $table->attach ($load,$sx, $sx+1 , $sy, $sy+1,'shrink','shrink',0,0);
+                $table->show_all();
+                my $val =read_mem_specefic_addr($self,$address,$tview);
+                $entry->set_text($val) if (defined $val);
+                $status =1;
+                entry_set_text_color($entry,-1);
+                $load->destroy;
+            });
+            $write-> signal_connect("clicked" => sub{
+                my $value = $entry->get_text();
+                my $address=$addr->get_text();
+                my $format =$self->    object_get_attribute('FILE_VIEW','R_ADDR_FORMAT');
+                $format= 'Decimal' if (!defined $format);
+                $address = hex($address) unless($format eq 'Decimal');
+                my $load= show_gif("icons/load.gif");
+                $table->attach ($load,$sx, $sx+1 , $sy, $sy+1,'shrink','shrink',0,0);
+                $table->show_all();
+                write_mem_specefic_addr($self,$address,$value,$tview);
+                $status =1;
+                entry_set_text_color($entry,-1);
+                $load->destroy;
+            });
+            $entry->signal_connect("changed" => sub{
+                if($status==0 || $status==1 ){
+                    $status =2;#modified
+                    #change color to red
+                    entry_set_text_color($entry,11);
+                }
+                my $in = $entry->get_text();
+                $entry->set_text(remove_not_hex($in));
+            });
+            $addr->signal_connect("changed" => sub{
+                my $format =$self->    object_get_attribute('FILE_VIEW','R_ADDR_FORMAT');
+                $format= 'Decimal' if (!defined $format);
+                my $in = $addr->get_text();
+                $addr->set_text(remove_not_hex($in)) if ($format ne 'Decimal' );
+                $addr->set_text(remove_not_number($in)) if ($format eq 'Decimal' );
+            });
+    }
+    $table->attach ( gen_Vsep(), 1, 2 , 0, $y+1,'fill','fill',2,2);
+    $table->attach ( gen_Vsep(), 3, 4 , 0, $y+1,'fill','fill',2,2);
+    $table->attach ( gen_Vsep(), 6, 7 , 0, $y+1,'fill','fill',2,2);
+    return $scrolled_win;
 }
 
 sub get_file_b_setting{
-	my($self)=@_;
-	my $window = def_popwin_size (30,30,'Source Probe','percent');
-    my $table= def_table(2,10,FALSE);	
+    my($self)=@_;
+    my $window = def_popwin_size (30,30,'Source Probe','percent');
+    my $table= def_table(2,10,FALSE);
     my @info = (
-	#{ label=>" Address format: ", param_name=>'R_ADDR_FORMAT', type=>"Combo-box", default_val=>'Decimal', content=>"Decimal,Hexadecimal", info=>undef, param_parent=>'FILE_VIEW', ref_delay=> 1, new_status=>'ref_file_view', loc=>'vertical'},
-	{ label=>" Page row number: ", param_name=>'PAGE_MAX_X', type=>"Spin-button", default_val=>10, content=>"0,128,1", info=>undef, param_parent=>'FILE_VIEW', ref_delay=> 1, new_status=>'ref_file_view', loc=>'vertical'},
-	{ label=>" Page column number:", param_name=>'PAGE_MAX_Y', type=>"Spin-button", default_val=>10, content=>"1,128,1", info=>undef, param_parent=>'FILE_VIEW', ref_delay=> 1, new_status=>'ref_file_view', loc=>'vertical'}
-	);	
-	my $row=0;
-	my $col=0;
-	foreach my $d (@info) {
-		($row,$col)=add_param_widget  ($self, $d->{label}, $d->{param_name}, $d->{default_val}, $d->{type}, $d->{content}, $d->{info}, $table,$row,$col,1, $d->{param_parent}, $d->{ref_delay}, $d->{new_status}, $d->{loc});
-	}
-	$table->attach (gen_label_in_center(' '), 2, 3,$row,$row+1,'shrink','shrink',2,2); $row++; 
-	$table->attach (gen_label_in_center(' '), 2, 3,$row,$row+1,'shrink','shrink',2,2); $row++; 
-	$table->attach (gen_label_in_center(' '), 2, 3,$row,$row+1,'shrink','shrink',2,2); $row++; 
-	
-	
-	my $ok=def_image_button($path."icons/select.png",'OK');
-	$table->attach ($ok, 2, 3,$row,$row+1,'shrink','shrink',2,2); 
-	$ok-> signal_connect("clicked" => sub{
-		$window->destroy(); 
-	});
-	
-	$window->add(add_widget_to_scrolled_win($table));	
-	$window->show_all;
-
+    #{ label=>" Address format: ", param_name=>'R_ADDR_FORMAT', type=>"Combo-box", default_val=>'Decimal', content=>"Decimal,Hexadecimal", info=>undef, param_parent=>'FILE_VIEW', ref_delay=> 1, new_status=>'ref_file_view', loc=>'vertical'},
+    { label=>" Page row number: ", param_name=>'PAGE_MAX_X', type=>"Spin-button", default_val=>10, content=>"0,128,1", info=>undef, param_parent=>'FILE_VIEW', ref_delay=> 1, new_status=>'ref_file_view', loc=>'vertical'},
+    { label=>" Page column number:", param_name=>'PAGE_MAX_Y', type=>"Spin-button", default_val=>10, content=>"1,128,1", info=>undef, param_parent=>'FILE_VIEW', ref_delay=> 1, new_status=>'ref_file_view', loc=>'vertical'}
+    );
+    my $row=0;
+    my $col=0;
+    foreach my $d (@info) {
+        ($row,$col)=add_param_widget  ($self, $d->{label}, $d->{param_name}, $d->{default_val}, $d->{type}, $d->{content}, $d->{info}, $table,$row,$col,1, $d->{param_parent}, $d->{ref_delay}, $d->{new_status}, $d->{loc});
+    }
+    $table->attach (gen_label_in_center(' '), 2, 3,$row,$row+1,'shrink','shrink',2,2); $row++;
+    $table->attach (gen_label_in_center(' '), 2, 3,$row,$row+1,'shrink','shrink',2,2); $row++;
+    $table->attach (gen_label_in_center(' '), 2, 3,$row,$row+1,'shrink','shrink',2,2); $row++;
+    my $ok=def_image_button($path."icons/select.png",'OK');
+    $table->attach ($ok, 2, 3,$row,$row+1,'shrink','shrink',2,2);
+    $ok-> signal_connect("clicked" => sub{
+        $window->destroy();
+    });
+    $window->add(add_widget_to_scrolled_win($table));
+    $window->show_all;
 }
 
 sub fill_memory_array_from_file{
-	my  ($self,$fname,$tview)=@_;
-	
-	my $offset = $self->object_get_attribute('FILE_VIEW','IN_FILE_OFFSET');
-	my $BLOCK_SIZE =4;
-	
-	open(F,"<$fname") or die("Unable to open file $fname, $!");
-	binmode(F);
-	my $buf;
-	my $ct=($offset>>2);
-
-	my $start = ($offset>>2);
-	my $r=read(F,$buf,$BLOCK_SIZE);
-	while($r){
-		my $v='';
-		foreach(split(//, $buf)){
-			$v.=sprintf("%02x",ord($_));			
-		}
-		if($r!=4){
-			$v.='0'x(( 4 - $r)*2);
-		}
-		$memory{$ct}= $v;
-	    $status{$ct}=2;
-		$ct++;
-		$r=read(F,$buf,$BLOCK_SIZE);
-	}
-	close(F);
-	
-	add_info($tview,"Load $fname\n"); 
-	$ct=($ct << 2);
-	add_info($tview,"address $offset to $ct\n"); 
+    my  ($self,$fname,$tview)=@_;
+    my $offset = $self->object_get_attribute('FILE_VIEW','IN_FILE_OFFSET');
+    my $BLOCK_SIZE =4;
+    open(F,"<$fname") or die("Unable to open file $fname, $!");
+    binmode(F);
+    my $buf;
+    my $ct=($offset>>2);
+    my $start = ($offset>>2);
+    my $r=read(F,$buf,$BLOCK_SIZE);
+    while($r){
+        my $v='';
+        foreach(split(//, $buf)){
+            $v.=sprintf("%02x",ord($_));
+        }
+        if($r!=4){
+            $v.='0'x(( 4 - $r)*2);
+        }
+        $memory{$ct}= $v;
+        $status{$ct}=2;
+        $ct++;
+        $r=read(F,$buf,$BLOCK_SIZE);
+    }
+    close(F);
+    add_info($tview,"Load $fname\n");
+    $ct=($ct << 2);
+    add_info($tview,"address $offset to $ct\n");
 }
 
 sub get_file_in_name{
-	my ($self,$tview)=@_;
-	
-	my $file;
-	my $title ='select bin file';
-	my $dialog = gen_file_dialog ($title);
-		
-	if ( "ok" eq $dialog->run ) {
-	    	$file = $dialog->get_filename;
-			$dialog->destroy;
-			$self->object_add_attribute('FILE_VIEW','IN_FILE',$file);
-				
-			#get offset address;
-			my $window = def_popwin_size (30,20,'Get Offset Address','percent');
-			my $table= def_table(2,10,FALSE);	
-			my $d=
-			{ label=>" Offset address (in byte): ", param_name=>'IN_FILE_OFFSET', type=>"Spin-button", default_val=>0, content=>'0,9999999999,1', info=>'The Wishbone bus offset address where the beginning of the memory bin file is written there (It can be the base address of the peripheral device where the memory file is intended to be written to.)   ', param_parent=>'FILE_VIEW', ref_delay=> undef, new_status=>undef, loc=>'vertical'};
-			my $row=0;
-			my $col=0;
-			($row,$col)=add_param_widget  ($self, $d->{label}, $d->{param_name}, $d->{default_val}, $d->{type}, $d->{content}, $d->{info}, $table,$row,$col,1, $d->{param_parent}, $d->{ref_delay}, $d->{new_status}, $d->{loc});
-			my $ok=def_image_button($path."icons/select.png",'OK');
-			$table->attach ($ok, 2, 3,$row,$row+1,'shrink','shrink',2,2); 
-			$ok-> signal_connect("clicked" => sub{
-				fill_memory_array_from_file ($self,$file,$tview);
-				set_gui_status($self,'ref_file_view',1);
-				$window->destroy(); 
-			});
-			$window->add(add_widget_to_scrolled_win($table));	
-			$window->show_all;
-			
-			
-	} 
-	
-	
-	
+    my ($self,$tview)=@_;
+    my $file;
+    my $title ='select bin file';
+    my $dialog = gen_file_dialog ($title);
+    if ( "ok" eq $dialog->run ) {
+            $file = $dialog->get_filename;
+            $dialog->destroy;
+            $self->object_add_attribute('FILE_VIEW','IN_FILE',$file);
+            #get offset address;
+            my $window = def_popwin_size (30,20,'Get Offset Address','percent');
+            my $table= def_table(2,10,FALSE);
+            my $d=
+            { label=>" Offset address (in byte): ", param_name=>'IN_FILE_OFFSET', type=>"Spin-button", default_val=>0, content=>'0,9999999999,1', info=>'The Wishbone bus offset address where the beginning of the memory bin file is written there (It can be the base address of the peripheral device where the memory file is intended to be written to.)   ', param_parent=>'FILE_VIEW', ref_delay=> undef, new_status=>undef, loc=>'vertical'};
+            my $row=0;
+            my $col=0;
+            ($row,$col)=add_param_widget  ($self, $d->{label}, $d->{param_name}, $d->{default_val}, $d->{type}, $d->{content}, $d->{info}, $table,$row,$col,1, $d->{param_parent}, $d->{ref_delay}, $d->{new_status}, $d->{loc});
+            my $ok=def_image_button($path."icons/select.png",'OK');
+            $table->attach ($ok, 2, 3,$row,$row+1,'shrink','shrink',2,2);
+            $ok-> signal_connect("clicked" => sub{
+                fill_memory_array_from_file ($self,$file,$tview);
+                set_gui_status($self,'ref_file_view',1);
+                $window->destroy();
+            });
+            $window->add(add_widget_to_scrolled_win($table));
+            $window->show_all;
+    }
 }
 
-
-
-
 sub get_jtag_intfc_cmd {
-	my $self=shift;
-	
-	my $vendor = $self->object_get_attribute('CTRL','VENDOR');
-	my $board  = $self->object_get_attribute('CTRL','Board_Name');
-	my $chain  = $self->object_get_attribute('CTRL','JTAG_CHAIN');
-	my $index  = $self->object_get_attribute('CTRL','JTAG_INDEX');
-	my $pronoc = get_project_dir();
-	my $intfc = "$pronoc/mpsoc/boards/$vendor/$board/jtag_intfc.sh";
-	#my $script  = "$ENV{'PRONOC_WORK'}/tmp/script.bash";
-	
-	my $t = ($vendor eq 'Xilinx') ? "-t  $chain " : "";
-	
-	my $cmd = "bash -c \"source $intfc; \\\$JTAG_INTFC $t -n $index";
-	return $cmd;
-	
+    my $self=shift;
+    my $vendor = $self->object_get_attribute('CTRL','VENDOR');
+    my $board  = $self->object_get_attribute('CTRL','Board_Name');
+    my $chain  = $self->object_get_attribute('CTRL','JTAG_CHAIN');
+    my $index  = $self->object_get_attribute('CTRL','JTAG_INDEX');
+    my $pronoc = get_project_dir();
+    my $intfc = "$pronoc/mpsoc/boards/$vendor/$board/jtag_intfc.sh";
+    #my $script  = "$ENV{'PRONOC_WORK'}/tmp/script.bash";
+    my $t = ($vendor eq 'Xilinx') ? "-t  $chain " : "";
+    my $cmd = "bash -c \"source $intfc; \\\$JTAG_INTFC $t -n $index";
+    return $cmd;
 }
 
-
 sub read_memory_array_from_device {
-	my ($self,$tview)=@_;
-	my $lower  = $self->object_get_attribute('FILE_VIEW','READ_LBA');
-	my $upper  = $self->object_get_attribute('FILE_VIEW','READ_UBA');
-		
-	$lower= sprintf("0x%x",$lower);
-	$upper= sprintf("0x%x",$upper); 
-		
-	my $intfc = get_jtag_intfc_cmd($self);
-	#my $comand = "#!/bin/bash\n  source $intfc\n \$JTAG_INTFC $t -n $index -s \"$lower\" -e \"$upper\" -r";
-	my $cmd = "$intfc -s $lower -e $upper -r\"";
-	
-	#save_file ($script,$comand);
-	#chmod 0755, $script;
-		
-	#my $cmd = "bash -c \"  $script \"";	
-	add_info($tview,"$cmd\n");	
-	my $results =run_cmd_textview_errors($cmd,$tview);
-	return 1 if(!defined $results);	
-	
-	
-			
-	my @nn = split (/###read data#\n/,$results);	
-	if(!defined $nn[1]){
-		add_colored_info($tview,"Got an Error:$results!\n",'red');
-		return 1;
-	}
-	my @nums=split (/\n/,$nn[1]);
-	
-	$lower  = $self->object_get_attribute('FILE_VIEW','READ_LBA');
-	$lower>>=2; #change to word
-	foreach my $n ( @nums) {
-		$n='0'x( 8 - length $n).$n;
-		$memory{$lower }= $n;
-	    $status{$lower}=1; #valid
-	    $lower++;
-			
-	}	 
-}	 
-
+    my ($self,$tview)=@_;
+    my $lower  = $self->object_get_attribute('FILE_VIEW','READ_LBA');
+    my $upper  = $self->object_get_attribute('FILE_VIEW','READ_UBA');
+    $lower= sprintf("0x%x",$lower);
+    $upper= sprintf("0x%x",$upper);
+    my $intfc = get_jtag_intfc_cmd($self);
+    #my $comand = "#!/bin/bash\n  source $intfc\n \$JTAG_INTFC $t -n $index -s \"$lower\" -e \"$upper\" -r";
+    my $cmd = "$intfc -s $lower -e $upper -r\"";
+    #save_file ($script,$comand);
+    #chmod 0755, $script;
+    #my $cmd = "bash -c \"  $script \"";
+    add_info($tview,"$cmd\n");
+    my $results =run_cmd_textview_errors($cmd,$tview);
+    return 1 if(!defined $results);
+    my @nn = split (/###read data#\n/,$results);
+    if(!defined $nn[1]){
+        add_colored_info($tview,"Got an Error:$results!\n",'red');
+        return 1;
+    }
+    my @nums=split (/\n/,$nn[1]);
+    $lower  = $self->object_get_attribute('FILE_VIEW','READ_LBA');
+    $lower>>=2; #change to word
+    foreach my $n ( @nums) {
+        $n='0'x( 8 - length $n).$n;
+        $memory{$lower }= $n;
+        $status{$lower}=1; #valid
+        $lower++;
+    }
+}
 
 sub print_32_bit_val {
-	my ($file,$v)=@_;
-	for (my $i= 24; $i >=0 ; $i-=8) {
-		my $byte= ($v >> $i ) & 0xFF;
-		print $file pack('C*',$byte);
-		#printf ("%02x\t",$byte);
-	}
+    my ($file,$v)=@_;
+    for (my $i= 24; $i >=0 ; $i-=8) {
+        my $byte= ($v >> $i ) & 0xFF;
+        print $file pack('C*',$byte);
+        #printf ("%02x\t",$byte);
+    }
 }
 
-
 sub write_memory_array_from_device {
-	my ($self,$tview)=@_;
-	my $lower  = $self->object_get_attribute('FILE_VIEW','READ_LBA');
-	my $upper  = $self->object_get_attribute('FILE_VIEW','READ_UBA');
-	
-	my $tmp_bin= "$ENV{'PRONOC_WORK'}/tmp/tmp.bin";
-	
-		
-	#create binfile
-	unlink $tmp_bin;
-	open(my $F,">$tmp_bin") or die("Unable to open file $tmp_bin, $!");
-	#binmode($F);
-	my $warning;
-	my $n;
-	for (my $i=($lower>>2); $i< ($upper>>2); $i++){
-		 my $s =(defined $status{$i}) ? $status{$i} : 0; 
-		 if( $s==0) {
-		 	$n= 0;
-		 	$warning=$i;
-		 }
-		 else{
-		 	$n= $memory{$i};
-		 	$status{$i}=1;	
-		}
-		print_32_bit_val ($F, hex($n));
-	}
-	close ($F);
-	
-	
-	
-
-	$lower= sprintf("0x%x",$lower);
-	$upper= sprintf("0x%x",$upper); 
-		
-	
-	#my $comand = "#!/bin/bash\n  source $intfc\n \$JTAG_INTFC $t -n $index -s \"$lower\" -e \"$upper\"  -i  $tmp_bin -c";
-	
-	#save_file ($script,$comand);
-	#chmod 0755, $script;
-		
-	#my $cmd = "bash -c \"  $script \"";
-	my $intfc = get_jtag_intfc_cmd($self);
-	my $cmd = "$intfc -s $lower -e $upper  -i  $tmp_bin -c\"";
-		
-	add_info($tview,"$cmd\n");	
-	my $results =run_cmd_textview_errors($cmd,$tview);
-	return 1 if(!defined $results);	
-	
-	my @lines = split (/\n/, $results);
-	foreach my $line (@lines) {
-		add_colored_info($tview,"$line\n",'red') if	 ($line =~ /Error/);
-	}	 
-}	 
-
-
-
-
-
-
-
-	
+    my ($self,$tview)=@_;
+    my $lower  = $self->object_get_attribute('FILE_VIEW','READ_LBA');
+    my $upper  = $self->object_get_attribute('FILE_VIEW','READ_UBA');
+    my $tmp_bin= "$ENV{'PRONOC_WORK'}/tmp/tmp.bin";
+    #create binfile
+    unlink $tmp_bin;
+    open(my $F,">$tmp_bin") or die("Unable to open file $tmp_bin, $!");
+    #binmode($F);
+    my $warning;
+    my $n;
+    for (my $i=($lower>>2); $i< ($upper>>2); $i++){
+        my $s =(defined $status{$i}) ? $status{$i} : 0;
+        if( $s==0) {
+            $n= 0;
+            $warning=$i;
+        }
+        else{
+            $n= $memory{$i};
+            $status{$i}=1;
+        }
+        print_32_bit_val ($F, hex($n));
+    }
+    close ($F);
+    $lower= sprintf("0x%x",$lower);
+    $upper= sprintf("0x%x",$upper);
+    #my $comand = "#!/bin/bash\n  source $intfc\n \$JTAG_INTFC $t -n $index -s \"$lower\" -e \"$upper\"  -i  $tmp_bin -c";
+    #save_file ($script,$comand);
+    #chmod 0755, $script;
+    #my $cmd = "bash -c \"  $script \"";
+    my $intfc = get_jtag_intfc_cmd($self);
+    my $cmd = "$intfc -s $lower -e $upper  -i  $tmp_bin -c\"";
+    add_info($tview,"$cmd\n");
+    my $results =run_cmd_textview_errors($cmd,$tview);
+    return 1 if(!defined $results);
+    my @lines = split (/\n/, $results);
+    foreach my $line (@lines) {
+        add_colored_info($tview,"$line\n",'red') if     ($line =~ /Error/);
+    }
+}
 
 sub read_write_widget {
-	my ($self,$tview,$rw)=@_;
-	#get start & end addresses;
-	my $window = def_popwin_size (30,20,'Select Memory Boundary Addresses','percent');
-	my $table= def_table(2,10,FALSE);	
-	my $l ={ label=>" Lower-bound address (in byte): ", param_name=>'READ_LBA', type=>"Spin-button", default_val=>0, content=>'0,9999999999,1', info=>'The Wishbone bus offset address where the beginning of the memory bin file is written there (It can be the base address of the peripheral device where the memory file is intended to be written to.)   ', param_parent=>'FILE_VIEW', ref_delay=> undef, new_status=>undef, loc=>'vertical'};
-	my $u ={ label=>" Upper-bound address (in byte): ", param_name=>'READ_UBA', type=>"Spin-button", default_val=>0, content=>'0,9999999999,1', info=>'The Wishbone bus offset address where the end of the memory bin file is written there (It can be the base address of the peripheral device where the memory file is intended to be written to plus bin file size in byte.)   ', param_parent=>'FILE_VIEW', ref_delay=> undef, new_status=>undef, loc=>'vertical'};
-	my ($l_spin,$u_spin);
-	my $row=0;
-	my $col=0;
-	($row,$col,$l_spin)=add_param_widget  ($self, $l->{label}, $l->{param_name}, $l->{default_val}, $l->{type}, $l->{content}, $l->{info}, $table,$row,$col,1, $l->{param_parent}, $l->{ref_delay}, $l->{new_status}, $l->{loc});
-	($row,$col,$u_spin)=add_param_widget  ($self, $u->{label}, $u->{param_name}, $u->{default_val}, $u->{type}, $u->{content}, $u->{info}, $table,$row,$col,1, $u->{param_parent}, $u->{ref_delay}, $l->{new_status}, $u->{loc});
-	
-	$l_spin-> signal_connect("value_changed" => sub{
-		my $lower=$l_spin->get_value();
-		$u_spin->set_range ($lower, 9999999999);
-		
-	});
-	
-	$u_spin-> signal_connect("value_changed" => sub{
-		my $upper=$u_spin->get_value();
-		$l_spin->set_range (0,$upper);
-		
-	});		
-	
-	
-	
-	
-	my $ok=def_image_button($path."icons/select.png",'OK');
-	$table->attach ($ok, 2, 3,$row,$row+1,'shrink','shrink',2,2); 
-	$ok-> signal_connect("clicked" => sub{
-		my $vendor= $self->object_get_attribute('CTRL','VENDOR');
-		my $load= show_gif("icons/load.gif");
-		$table->attach ($load,1, 2, $row,$row+ 1,'shrink','shrink',0,0);
-		$table->show_all();
-		read_memory_array_from_device ($self,$tview)  if ($rw eq 'READ');	
-		write_memory_array_from_device ($self,$tview) if ($rw eq 'WRITE');	
-		set_gui_status($self,'ref_file_view',1);
-		$window->destroy(); 
-	});
-	$window->add(add_widget_to_scrolled_win($table));	
-	$window->show_all;	
-}	
-
-
-
-
-
-
+    my ($self,$tview,$rw)=@_;
+    #get start & end addresses;
+    my $window = def_popwin_size (30,20,'Select Memory Boundary Addresses','percent');
+    my $table= def_table(2,10,FALSE);
+    my $l ={ label=>" Lower-bound address (in byte): ", param_name=>'READ_LBA', type=>"Spin-button", default_val=>0, content=>'0,9999999999,1', info=>'The Wishbone bus offset address where the beginning of the memory bin file is written there (It can be the base address of the peripheral device where the memory file is intended to be written to.)   ', param_parent=>'FILE_VIEW', ref_delay=> undef, new_status=>undef, loc=>'vertical'};
+    my $u ={ label=>" Upper-bound address (in byte): ", param_name=>'READ_UBA', type=>"Spin-button", default_val=>0, content=>'0,9999999999,1', info=>'The Wishbone bus offset address where the end of the memory bin file is written there (It can be the base address of the peripheral device where the memory file is intended to be written to plus bin file size in byte.)   ', param_parent=>'FILE_VIEW', ref_delay=> undef, new_status=>undef, loc=>'vertical'};
+    my ($l_spin,$u_spin);
+    my $row=0;
+    my $col=0;
+    ($row,$col,$l_spin)=add_param_widget  ($self, $l->{label}, $l->{param_name}, $l->{default_val}, $l->{type}, $l->{content}, $l->{info}, $table,$row,$col,1, $l->{param_parent}, $l->{ref_delay}, $l->{new_status}, $l->{loc});
+    ($row,$col,$u_spin)=add_param_widget  ($self, $u->{label}, $u->{param_name}, $u->{default_val}, $u->{type}, $u->{content}, $u->{info}, $table,$row,$col,1, $u->{param_parent}, $u->{ref_delay}, $l->{new_status}, $u->{loc});
+    $l_spin-> signal_connect("value_changed" => sub{
+        my $lower=$l_spin->get_value();
+        $u_spin->set_range ($lower, 9999999999);
+    });
+    $u_spin-> signal_connect("value_changed" => sub{
+        my $upper=$u_spin->get_value();
+        $l_spin->set_range (0,$upper);
+    });
+    my $ok=def_image_button($path."icons/select.png",'OK');
+    $table->attach ($ok, 2, 3,$row,$row+1,'shrink','shrink',2,2);
+    $ok-> signal_connect("clicked" => sub{
+        my $vendor= $self->object_get_attribute('CTRL','VENDOR');
+        my $load= show_gif("icons/load.gif");
+        $table->attach ($load,1, 2, $row,$row+ 1,'shrink','shrink',0,0);
+        $table->show_all();
+        read_memory_array_from_device ($self,$tview)  if ($rw eq 'READ');
+        write_memory_array_from_device ($self,$tview) if ($rw eq 'WRITE');
+        set_gui_status($self,'ref_file_view',1);
+        $window->destroy();
+    });
+    $window->add(add_widget_to_scrolled_win($table));
+    $window->show_all;
+}
 
 sub read_write_bin_file {
-	my ($self,$tview)=@_;
-	my $table= def_table(2,10,FALSE);	
-	my $scrolled_win=gen_scr_win_with_adjst ($self,"receive_box");
-	add_widget_to_scrolled_win($table,$scrolled_win);
-	my @data;
-	
-	
-	my $MAX_X=$self->	object_get_attribute('FILE_VIEW','PAGE_MAX_X');
-	$MAX_X=10 if (!defined $MAX_X);
-	my $MAX_Y=$self->	object_get_attribute('FILE_VIEW','PAGE_MAX_Y');
-	$MAX_Y=10 if (!defined $MAX_Y);
-	my $format =$self->	object_get_attribute('FILE_VIEW','R_ADDR_FORMAT');
-	$format= 'Decimal' if (!defined $format);
-	
-	
-	my $OFFSET=0;
-	
-	my $table1= def_table(2,10,FALSE);
-	
-	#$page_num= 0 if(!defined $page_num);
-
-	
-	
-	
-	my $setting=def_image_button("icons/setting.png","setting");
-	my $load=def_image_button("icons/download.png","Load File");
-	my $read=def_image_button($path."icons/simulator.png","Read Memory");		
-	my $write=def_image_button($path."icons/write.png","Write Memory");   
-	my $clear=def_image_button($path."icons/clear.png");  
-	my $x=0;
-	
-	
-	$table->attach ($setting, $x, $x+1, 0, 1,'fill','fill',2,2);$x++; 
-	$table->attach ($load, $x, $x+1 , 0, 1,'fill','fill',2,2);$x++; 
-	$table->attach ($read, $x, $x+1 , 0, 1,'shrink','shrink',2,2); $x++; 
-	$table->attach ($write, $x, $x+1 , 0, 1,'shrink','shrink',2,2); $x++;
-	$table->attach ($clear, $x, $x+1 , 0, 1,'shrink','shrink',2,2); $x++;
-	
-	add_param_widget  ($self,"Page_num", 'FILE_VIEW',  0, "Spin-button", "0,999999,1", undef, $table,0, $x, 1, "R_PAGE_NUM",1,'ref_file_view');
-	
-	my $page_num =$self->object_get_attribute("R_PAGE_NUM",'FILE_VIEW'); 
-	
-	
-	
-	
-	$setting-> signal_connect("clicked" => sub{
-				get_file_b_setting($self);
-	}); 	
-	
-	$load-> signal_connect("clicked" => sub{
-				get_file_in_name($self,$tview);
-	}); 	
-	
-	$clear-> signal_connect("clicked" => sub{
-		undef %memory;
-		undef %status;
-		set_gui_status($self,'ref_file_view',1);
-	}); 	
-	
-	$read-> signal_connect("clicked" => sub{
-		read_write_widget($self,$tview,'READ');
-	}); 
-	
-	$write->signal_connect("clicked" => sub{
-		read_write_widget($self,$tview,'WRITE');
-	}); 
-	
-	my $base_addr=$page_num*$MAX_X*$MAX_Y+$OFFSET;	
-		
-	
-	#column address labels
-	for (my $y=1; $y<=$MAX_Y; $y++){
-		my $addr=(($y-1) << 2);
-		$addr =($format eq 'Hexadecimal')? sprintf("%x", $addr) : $addr;
-		
-		my $l=gen_label_in_center (" $addr ");
-		$table1->attach ( $l, $y, $y+1 , 0, 1,'fill','fill',2,2);
-	}	
-	
-	
-	#row address labels
-	for (my $x=1; $x<=$MAX_X; $x++){
-		my $addr=$base_addr+($x-1) * $MAX_Y;
-		
-		$addr = ($format eq 'Hexadecimal')? sprintf("%x",($addr << 2))   : ($addr << 2);
-		
-		
-		my $l=gen_label_in_left (" $addr ");
-		$table1->attach ( $l, 0, 1 , $x, $x+1,'fill','fill',2,2);
-	}	
-	
-	#entries	
-	for (my $x=1; $x<=$MAX_X; $x++){
-		for (my $y=1; $y<=$MAX_Y; $y++){
-			
-			
-			my $state=0;# not modified
-			
-			my $addr =$base_addr+ (($x-1) * $MAX_Y ) + $y-1;
-			my $addr_tip=($format eq 'Hexadecimal')? sprintf("0x%x",($addr << 2))   : ($addr << 2);
-			
-			my $v= $memory{$addr};
-			my $s = $status{$addr};
-			
-			$v= "xxxxxxxx" if (!defined $v);
-			$s = 0 if (!defined $s); #0 dontcare			
-			
-						
-			my $entry =gen_entry($v );
-			
-			$entry->set_max_length (8);
-			$entry->set_width_chars(8);
-			set_tip($entry,"$addr_tip");
-			$table1->attach ( $entry, $y, $y+1 , $x, $x+1,'fill','fill',2,2);
-			
-			if($s==2 ){
-				#change color to red
-				entry_set_text_color($entry,11);
-			}
-			
-			$entry->signal_connect("changed" => sub{
-				if($s==0 || $s==1 ){
-					$status{$addr} =2;#modified
-					#change color to red
-					entry_set_text_color($entry,11);
-					
-				}
-				my $in = $entry->get_text();
-				$memory{$addr}=$in;
-				$entry->set_text(remove_not_hex($in));
-				
-			});	
-		
-		}
-	}
- 		  
-  		  
-     
-	
-	$table->attach ( $table1, 0, 20 , 1, 10,'fill','fill',2,2);
-	
-	$scrolled_win->show_all;
-	return $scrolled_win;
-	
+    my ($self,$tview)=@_;
+    my $table= def_table(2,10,FALSE);
+    my $scrolled_win=gen_scr_win_with_adjst ($self,"receive_box");
+    add_widget_to_scrolled_win($table,$scrolled_win);
+    my @data;
+    my $MAX_X=$self->    object_get_attribute('FILE_VIEW','PAGE_MAX_X');
+    $MAX_X=10 if (!defined $MAX_X);
+    my $MAX_Y=$self->    object_get_attribute('FILE_VIEW','PAGE_MAX_Y');
+    $MAX_Y=10 if (!defined $MAX_Y);
+    my $format =$self->    object_get_attribute('FILE_VIEW','R_ADDR_FORMAT');
+    $format= 'Decimal' if (!defined $format);
+    my $OFFSET=0;
+    my $table1= def_table(2,10,FALSE);
+    #$page_num= 0 if(!defined $page_num);
+    my $setting=def_image_button("icons/setting.png","setting");
+    my $load=def_image_button("icons/download.png","Load File");
+    my $read=def_image_button($path."icons/simulator.png","Read Memory");
+    my $write=def_image_button($path."icons/write.png","Write Memory");
+    my $clear=def_image_button($path."icons/clear.png");
+    my $x=0;
+    $table->attach ($setting, $x, $x+1, 0, 1,'fill','fill',2,2);$x++;
+    $table->attach ($load, $x, $x+1 , 0, 1,'fill','fill',2,2);$x++;
+    $table->attach ($read, $x, $x+1 , 0, 1,'shrink','shrink',2,2); $x++;
+    $table->attach ($write, $x, $x+1 , 0, 1,'shrink','shrink',2,2); $x++;
+    $table->attach ($clear, $x, $x+1 , 0, 1,'shrink','shrink',2,2); $x++;
+    add_param_widget  ($self,"Page_num", 'FILE_VIEW',  0, "Spin-button", "0,999999,1", undef, $table,0, $x, 1, "R_PAGE_NUM",1,'ref_file_view');
+    my $page_num =$self->object_get_attribute("R_PAGE_NUM",'FILE_VIEW');
+    $setting-> signal_connect("clicked" => sub{
+                get_file_b_setting($self);
+    });
+    $load-> signal_connect("clicked" => sub{
+                get_file_in_name($self,$tview);
+    });
+    $clear-> signal_connect("clicked" => sub{
+        undef %memory;
+        undef %status;
+        set_gui_status($self,'ref_file_view',1);
+    });
+    $read-> signal_connect("clicked" => sub{
+        read_write_widget($self,$tview,'READ');
+    });
+    $write->signal_connect("clicked" => sub{
+        read_write_widget($self,$tview,'WRITE');
+    });
+    my $base_addr=$page_num*$MAX_X*$MAX_Y+$OFFSET;
+    #column address labels
+    for (my $y=1; $y<=$MAX_Y; $y++){
+        my $addr=(($y-1) << 2);
+        $addr =($format eq 'Hexadecimal')? sprintf("%x", $addr) : $addr;
+        my $l=gen_label_in_center (" $addr ");
+        $table1->attach ( $l, $y, $y+1 , 0, 1,'fill','fill',2,2);
+    }
+    #row address labels
+    for (my $x=1; $x<=$MAX_X; $x++){
+        my $addr=$base_addr+($x-1) * $MAX_Y;
+        $addr = ($format eq 'Hexadecimal')? sprintf("%x",($addr << 2))   : ($addr << 2);
+        my $l=gen_label_in_left (" $addr ");
+        $table1->attach ( $l, 0, 1 , $x, $x+1,'fill','fill',2,2);
+    }
+    #entries
+    for (my $x=1; $x<=$MAX_X; $x++){
+        for (my $y=1; $y<=$MAX_Y; $y++){
+            my $state=0;# not modified
+            my $addr =$base_addr+ (($x-1) * $MAX_Y ) + $y-1;
+            my $addr_tip=($format eq 'Hexadecimal')? sprintf("0x%x",($addr << 2))   : ($addr << 2);
+            my $v= $memory{$addr};
+            my $s = $status{$addr};
+            $v= "xxxxxxxx" if (!defined $v);
+            $s = 0 if (!defined $s); #0 dontcare
+            my $entry =gen_entry($v );
+            $entry->set_max_length (8);
+            $entry->set_width_chars(8);
+            set_tip($entry,"$addr_tip");
+            $table1->attach ( $entry, $y, $y+1 , $x, $x+1,'fill','fill',2,2);
+            if($s==2 ){
+                #change color to red
+                entry_set_text_color($entry,11);
+            }
+            $entry->signal_connect("changed" => sub{
+                if($s==0 || $s==1 ){
+                    $status{$addr} =2;#modified
+                    #change color to red
+                    entry_set_text_color($entry,11);
+                }
+                my $in = $entry->get_text();
+                $memory{$addr}=$in;
+                $entry->set_text(remove_not_hex($in));
+            });
+        }
+    }
+    $table->attach ( $table1, 0, 20 , 1, 10,'fill','fill',2,2);
+    $scrolled_win->show_all;
+    return $scrolled_win;
 }
 
-
-
 ############
-#	main
+#    main
 ############
-
-
-
 sub source_probe_main {
-	my $self = __PACKAGE__->new(); 
-	
-	
-	
-	set_gui_status($self,"ideal",0);
-	my $window = def_popwin_size (85,85,'Run time JTAG debug','percent');
-	my ($sw,$tview) =create_txview();# a textveiw for showing the info, erro messages etc
-	my $ctrl = source_probe_ctrl($self,$tview);
-	my $sp= soure_probe_widgets ($self,$tview);
-	my $bin_f = read_write_bin_file($self,$tview);
-	#my $bin_ctrl = file_bin_ctrl($self,$tview);
-	
-	
-	my $h1 = gen_hpaned ($sp,0.35,$ctrl);
-	#my $h2 = gen_hpaned ($bin_f,0.55,$bin_ctrl);
-	my $v1 = gen_vpaned ($h1,0.2,$bin_f);
-	my $v2 = gen_vpaned ($v1,0.65,$sw);
-	
-	
-	
-	
-		
-	#check soc status every ? second. referesh device table if there is any changes 
-    Glib::Timeout->add (100, sub{ 
+    my $self = __PACKAGE__->new();
+    set_gui_status($self,"ideal",0);
+    my $window = def_popwin_size (85,85,'Run time JTAG debug','percent');
+    my ($sw,$tview) =create_txview();# a textveiw for showing the info, erro messages etc
+    my $ctrl = source_probe_ctrl($self,$tview);
+    my $sp= soure_probe_widgets ($self,$tview);
+    my $bin_f = read_write_bin_file($self,$tview);
+    #my $bin_ctrl = file_bin_ctrl($self,$tview);
+    my $h1 = gen_hpaned ($sp,0.35,$ctrl);
+    #my $h2 = gen_hpaned ($bin_f,0.55,$bin_ctrl);
+    my $v1 = gen_vpaned ($h1,0.2,$bin_f);
+    my $v2 = gen_vpaned ($v1,0.65,$sw);
+    #check soc status every ? second. referesh device table if there is any changes
+    Glib::Timeout->add (100, sub{
         my ($state,$timeout)= get_gui_status($self);
-        
         if ($timeout>0){
             $timeout--;
-            set_gui_status($self,$state,$timeout);           
+            set_gui_status($self,$state,$timeout);
         }
-        elsif( $state ne "ideal" ){        	
+        elsif( $state ne "ideal" ){
             if($state eq 'ref_all') {
-            	$sp->destroy();
-            	$sp= soure_probe_widgets ($self,$tview);
-            	$bin_f->destroy(); 
-            	$bin_f = read_write_bin_file($self,$tview);
-            	$h1-> pack1($sp, TRUE, TRUE);
-            	$v1-> pack2($bin_f, TRUE, TRUE);
-            	$v2-> show_all(); 
+                $sp->destroy();
+                $sp= soure_probe_widgets ($self,$tview);
+                $bin_f->destroy();
+                $bin_f = read_write_bin_file($self,$tview);
+                $h1-> pack1($sp, TRUE, TRUE);
+                $v1-> pack2($bin_f, TRUE, TRUE);
+                $v2-> show_all();
             }
             elsif ($state eq  'ref_file_view'){
-            	$bin_f->destroy(); 
-            	$bin_f = read_write_bin_file($self,$tview);
-            	$v1-> pack2($bin_f, TRUE, TRUE);
-            	$v2-> show_all(); 
-            	
-            	
-            } 	  
-            
+                $bin_f->destroy();
+                $bin_f = read_write_bin_file($self,$tview);
+                $v1-> pack2($bin_f, TRUE, TRUE);
+                $v2-> show_all();
+            }
             $ctrl->destroy();
             $ctrl = source_probe_ctrl($self,$tview);
             $h1-> pack2($ctrl, TRUE, TRUE);
-            $v2-> show_all(); 
-            set_gui_status($self,"ideal",0);         
-               
-            
-       }
-             
-    	return TRUE;
-        
+            $v2-> show_all();
+            set_gui_status($self,"ideal",0);
+        }
+        return TRUE;
     } );
-	
-	
-	
-	$window->add($v2);
-	$window->show_all();
-	return $window;	
-}	
-
-
-
+    $window->add($v2);
+    $window->show_all();
+    return $window;
+}
\ No newline at end of file
diff --git a/mpsoc/perl_gui/lib/perl/simulator.pl b/mpsoc/perl_gui/lib/perl/simulator.pl
index d07d34c..0549fe5 100755
--- a/mpsoc/perl_gui/lib/perl/simulator.pl
+++ b/mpsoc/perl_gui/lib/perl/simulator.pl
@@ -5,8 +5,6 @@
 use FindBin;
 use lib $FindBin::Bin;
 
-
-
 use GD::Graph::Data;
 use emulator;
 use GD::Graph::colour qw/:colours/;
@@ -23,1208 +21,877 @@
 require "readme_gen.pl";
 require "graph.pl";
 
-
 use List::MoreUtils qw(uniq);
 
-
-
-
 sub generate_sim_bin_file {
-	my ($simulate,$info_text) =@_;
-	#check simulator envirement
-	my $simulator =$simulate->object_get_attribute("Simulator");
-	#TODO generate .sim file only for modelsim simulator
-		
-	$simulate->object_add_attribute('status',undef,'run');
-	set_gui_status($simulate,"ref",1);
-	
-	my ($nr,$ne,$router_p,$ref_tops,$includ_h)= get_noc_verilator_top_modules_info($simulate);
-	my %tops = %{$ref_tops};
-	
-	$tops{Vtraffic} = "--top-module traffic_gen_top";	
-	$tops{Vpck_inj} = "--top-module packet_injector_verilator";	
-	my $target_dir= "$ENV{PRONOC_WORK}/simulate";
-	
-	
-	my $project_dir	  = get_project_dir()."/mpsoc/";
-	my $src_verilator_dir="$project_dir/src_verilator";
-	my $src_c="$project_dir/src_c";
-	my $src_noc_dir="$project_dir/rtl/src_noc";	
-	my $script_dir="$project_dir/script";
-	my $testbench_file= "$src_verilator_dir/simulator.cpp";
-	
-	my $target_verilog_dr ="$target_dir/src_verilog";
-	my $obj_dir ="$target_dir/verilator/obj_dir/";
-	
-	rmtree("$target_dir/verilator");
-	rmtree("$target_verilog_dr");
-	mkpath("$target_verilog_dr/",1,01777);
-	
-	#copy src_verilator files
-	my @files_list = File::Find::Rule->file()
-                            ->name( '*.v','*.V','*.sv' )
-                            ->in( "$src_verilator_dir" );
-
-	#make sure source files have key word 'module' 
-	my @files;
-	foreach my $p (@files_list){
-		push (@files,$p)	if(check_file_has_string($p,'module')); 
-	}
-	push (@files,$src_noc_dir);
-	push (@files,"$project_dir/rtl/arbiter.v");
-	push (@files,"$project_dir/rtl/main_comp.v");
-	push (@files,"$project_dir/rtl/pronoc_def.v");
-	
-		
-	#my @files=(
-	#	$src_noc_dir,
-	#	"$src_verilator_dir/noc_connection.sv",
-	#	"$src_verilator_dir/mesh_torus_noc_connection.sv",			
-	#	"$src_verilator_dir/router_verilator.v",
-	#	"$src_verilator_dir/traffic_gen_verilator.v"		
-	#);
-	
-	copy_file_and_folders (\@files,$project_dir,$target_verilog_dr);
-	copy_file_and_folders (\@files,$project_dir,"$target_dir/modelsim/src_verilog/");
-	
-	my $target_modelsim_dr ="$target_dir/modelsim/src_modelsim";
-	my $src_modelsim_dir="$project_dir/rtl/src_modelsim";	
-	rmtree("$target_modelsim_dr");
-	mkpath("$target_modelsim_dr/",1,01777);
-	
-	#copy src_verilator files
-	@files_list = File::Find::Rule->file()
-                            ->name( '*.v','*.V','*.sv' )
-                            ->in( "$src_modelsim_dir" );
-
-	#make sure source files have key word 'module' 
-	@files=();
-	foreach my $p (@files_list){
-		push (@files,$p)	if(check_file_has_string($p,'module')); 
-	}
-	copy_file_and_folders (\@files,$project_dir,$target_modelsim_dr);
-	
-	
-		
-	
-	#check if we have a custom topology 
-	my $topology=$simulate->object_get_attribute('noc_param','TOPOLOGY');
-	if ($topology eq '"CUSTOM"'){ 
-		my $name=$simulate->object_get_attribute('noc_param','CUSTOM_TOPOLOGY_NAME');
-		$name=~s/["]//gs;     
-		my $dir1=  get_project_dir()."/mpsoc/rtl/src_topology/$name";
-		my $dir2=  get_project_dir()."/mpsoc/rtl/src_topology/common";
-		my @files = File::Find::Rule->file()
-                            ->name( '*.v','*.V','*.sv' )
-                            ->in( "$dir1" );
-		copy_file_and_folders (\@files,$project_dir,$target_verilog_dr);
-		copy_file_and_folders (\@files,$project_dir,"$target_dir/modelsim/src_verilog/");
-		
-		@files = File::Find::Rule->file()
-                            ->name( '*.v','*.V','*.sv' )
-                            ->in( "$dir2" );
-                         
-		copy_file_and_folders (\@files,$project_dir,$target_verilog_dr);
-		copy_file_and_folders (\@files,$project_dir,"$target_dir/modelsim/src_verilog/");
-		
-		
-	
-	}
-	# generate NoC parameter file	
-	my $fifow=$simulate->object_get_attribute('fpga_param','TIMSTMP_FIFO_NUM');
-	gen_noc_localparam_v_file($simulate,"$target_verilog_dr/src_noc");
-
-	#generate routers with different port num		
-	my $cpu_num = $simulate->object_get_attribute('compile', 'cpu_num');
-	my $result = verilator_compilation (\%tops,$target_dir,$info_text,$cpu_num);
-	
-	
-	if ($result){
-		add_colored_info($info_text,"Veriator model has been generated successfully!\n",'blue');
-	}else {
-		add_colored_info($info_text,"Verilator compilation failed!\n","red"); 
-		$simulate->object_add_attribute('status',undef,'programmer_failed');
-		set_gui_status($simulate,"ref",1);
-		print "gen-ended!\n";
-		return;
-	}
-	
-	my $r;	
-	#copy nettrace synful
-	dircopy("$src_c/netrace-1.0","$obj_dir/netrace-1.0") or $r=$!;
-	dircopy("$src_c/synfull","$obj_dir/synful") or $r=$!;
-	add_colored_info($info_text,"ERROR: $r\n","red") if(defined $r ) ; 	
-	
-	
-	#copy simulation c header files
-	@files = File::Find::Rule->file()
-                            ->name( '*.h')
-                            ->in( "$src_verilator_dir" );
-	
-	copy_file_and_folders (\@files,$project_dir,$obj_dir);
-	copy($testbench_file,"$obj_dir/testbench.cpp"); 
-		
-	
-		
-	#compile the testbench
-	my $param_h=gen_noc_param_h($simulate);
-	my $text = gen_sim_parameter_h($param_h,$includ_h,$ne,$nr,$router_p,$fifow);	
-	
-	
-	open(FILE,  ">$obj_dir/parameter.h") || die "Can not open: $!";
-	print FILE  "$text";
-	
-	close FILE;
-	
-	
-	
-	#$result = run_make_file("$obj_dir/",$info_text,'lib');	
-	my $lib_num=0;
-	add_colored_info($info_text,"Makefie will use the maximum number of $cpu_num core(s) in parallel for compilation\n",'green');
-	my $length=scalar (keys %tops);
-	my $cmd="";
-	foreach my $top (sort keys %tops) { 
-		$cmd.= "lib$lib_num & ";
-		$lib_num++;				
-		if( $lib_num % $cpu_num == 0 || $lib_num == $length){
-			$cmd.="wait\n";
-			$result = run_make_file("$obj_dir/",$info_text,$cmd);	
-			if ($result ==0){
-				$simulate->object_add_attribute('status',undef,'programmer_failed');
-				set_gui_status($simulate,"ref",1);
-				print "gen-ended!\n";
-				return;
-			}		
-			$cmd="";
-		}else {
-			$cmd.=" make ";
-		}	
-	}
-		
-		
-	
-	
-	run_make_file("$obj_dir/",$info_text);	
-	if ($result ==0){
-		$simulate->object_add_attribute('status',undef,'programmer_failed');
-		set_gui_status($simulate,"ref",1);
-		print "gen-ended!\n";
-		return;
-	}		
-	
-	
-	
-	
-	#my $end = localtime; 		
-	
-
-	
-	#save the binarry file
-	my $bin= "$obj_dir/testbench";
-	my $path=$simulate->object_get_attribute ('sim_param',"BIN_DIR");
-	my $name=$simulate->object_get_attribute ('sim_param',"SAVE_NAME");
-	
-	#create project directory if it does not exist
-	my	($stdout,$exit)=run_cmd_in_back_ground_get_stdout("mkdir -p $path" );
-	if($exit != 0 ){ 	print "$stdout\n";  print "gen-ended!\n";	message_dialog($stdout,'error'); return;}
-	
-
-	
-	#check if the verilation was successful
-	if ((-e $bin)==0) {#something goes wrong 		
-    	#message_dialog("Verilator compilation was unsuccessful please check the $path/$name.log files for more information",'error'); 
-    	add_colored_info($info_text,"Verilator compilation failed!\n","red"); 
-    	$simulate->object_add_attribute('status',undef,'programmer_failed');
-		set_gui_status($simulate,"ref",1);
-		print "gen-ended!\n";
-		return;
-	}
-	
-	
-	#copy ($bin,"$path/$name") or  die "Can not copy: $!";
-	($stdout,$exit)=run_cmd_in_back_ground_get_stdout("cp -f $bin $path/$name");
-	if($exit != 0 ){ 	print "$stdout\n";  print "gen-ended!\n";	message_dialog($stdout,'error'); return;}
-		
-	#save noc info
-	open(FILE,  ">$path/$name.inf") || die "Can not open: $!";
-	print FILE perl_file_header("$name.inf");
-	my %pp;
-	$pp{'noc_param'}= $simulate->{'noc_param'};
-	$pp{'sim_param'}= $simulate->{'sim_param'};
-	print FILE Data::Dumper->Dump([\%pp],["emulate_info"]);
-	close(FILE) || die "Error closing file: $!";		
-	
-	print "gen-ended successfully!\n";
-	message_dialog("The simulation binary file has been successfully generated in $path!"); 
-
-	$simulate->object_add_attribute('status',undef,'ideal');
-	set_gui_status($simulate,"ref",1);
-	
-	#make project dir
-	#my $dir= $simulate->object_get_attribute ("sim_param","BIN_DIR");
-	#my $name=$simulate->object_get_attribute ("sim_param","SAVE_NAME");	
-	#my $path= "$dir/$name";
-	#add_info($info_text, "$src_verilator_dir!\n");
-	#mkpath("$path",1,01777);
+    my ($simulate,$info_text) =@_;
+    #check simulator envirement
+    my $simulator =$simulate->object_get_attribute("Simulator");
+    $simulate->object_add_attribute('status',undef,'run');
+    set_gui_status($simulate,"ref",1);    
+    my ($nr,$ne,$router_p,$ref_tops,$includ_h)= get_noc_verilator_top_modules_info($simulate);
+    my %tops = %{$ref_tops};
+    
+    $tops{Vtraffic} = "--top-module traffic_gen_top";    
+    $tops{Vpck_inj} = "--top-module packet_injector_verilator";    
+    my $target_dir= "$ENV{PRONOC_WORK}/simulate";    
+    
+    my $project_dir      = get_project_dir()."/mpsoc/";
+    my $src_verilator_dir="$project_dir/src_verilator";
+    my $src_c="$project_dir/src_c";
+    my $src_noc_dir="$project_dir/rtl/src_noc";    
+    my $script_dir="$project_dir/script";
+    my $testbench_file= "$src_verilator_dir/simulator.cpp";
+    my $target_verilog_dr ="$target_dir/src_verilog";
+    my $obj_dir ="$target_dir/verilator/obj_dir/";
+    
+    rmtree("$target_dir/verilator") if($simulate eq 'Verilator');
+    rmtree("$target_verilog_dr");
+    mkpath("$target_verilog_dr/",1,01777);
+    
+    #copy src_verilator files
+    my @files_list = File::Find::Rule->file()
+        ->name( '*.v','*.V','*.sv' )
+        ->in( "$src_verilator_dir" );
+    #make sure source files have key word 'module' 
+    my @files;
+    foreach my $p (@files_list){
+        push (@files,$p)    if(check_file_has_string($p,'module')); 
+    }
+    push (@files,$src_noc_dir);
+    push (@files,"$project_dir/rtl/arbiter.v");
+    push (@files,"$project_dir/rtl/main_comp.v");
+    push (@files,"$project_dir/rtl/pronoc_def.v");   
+    
+    copy_file_and_folders (\@files,$project_dir,$target_verilog_dr);
+    copy_file_and_folders (\@files,$project_dir,"$target_dir/modelsim/src_verilog/");
+    my $target_modelsim_dr ="$target_dir/modelsim/src_modelsim";
+    my $src_modelsim_dir="$project_dir/rtl/src_modelsim";    
+    if($simulator ne 'Verilator'){
+        rmtree("$target_modelsim_dr");
+        mkpath("$target_modelsim_dr/",1,01777);
+        #copy src_verilator files
+        @files_list = File::Find::Rule->file()
+            ->name( '*.v','*.V','*.sv' )
+            ->in( "$src_modelsim_dir" );
+        #make sure source files have key word 'module' 
+        @files=();
+        foreach my $p (@files_list){
+            push (@files,$p)    if(check_file_has_string($p,'module')); 
+        }
+        copy_file_and_folders (\@files,$project_dir,$target_modelsim_dr);
+    }
+    
+    #check if we have a custom topology 
+    my $topology=$simulate->object_get_attribute('noc_param','TOPOLOGY');
+    if ($topology eq '"CUSTOM"'){ 
+        my $name=$simulate->object_get_attribute('noc_param','CUSTOM_TOPOLOGY_NAME');
+        $name=~s/["]//gs;     
+        my $dir1=  get_project_dir()."/mpsoc/rtl/src_topology/$name";
+        my $dir2=  get_project_dir()."/mpsoc/rtl/src_topology/common";
+        my @files = File::Find::Rule->file()
+            ->name( '*.v','*.V','*.sv' )
+            ->in( "$dir1" );
+        copy_file_and_folders (\@files,$project_dir,$target_verilog_dr);
+        copy_file_and_folders (\@files,$project_dir,"$target_dir/modelsim/src_verilog/") if($simulator ne 'Verilator');
+        
+        @files = File::Find::Rule->file()
+            ->name( '*.v','*.V','*.sv' )
+            ->in( "$dir2" );
+        copy_file_and_folders (\@files,$project_dir,$target_verilog_dr);
+        copy_file_and_folders (\@files,$project_dir,"$target_dir/modelsim/src_verilog/")if($simulator ne 'Verilator');
+    }
+    # generate NoC parameter file    
+    my $fifow=$simulate->object_get_attribute('fpga_param','TIMSTMP_FIFO_NUM');
+    gen_noc_localparam_v_file($simulate,"$target_verilog_dr/src_noc");
+    my $path=$simulate->object_get_attribute ('sim_param',"BIN_DIR");
+    my $name=$simulate->object_get_attribute ('sim_param',"SAVE_NAME");
+    
+    if($simulator eq 'Verilator'){
+        #generate routers with different port num        
+        my $cpu_num = $simulate->object_get_attribute('compile', 'cpu_num');
+        my $result = verilator_compilation (\%tops,$target_dir,$info_text,$cpu_num);
+        
+        if ($result){
+            add_colored_info($info_text,"Veriator model has been generated successfully!\n",'blue');
+        }else {
+            add_colored_info($info_text,"Verilator compilation failed!\n","red"); 
+            $simulate->object_add_attribute('status',undef,'programmer_failed');
+            set_gui_status($simulate,"ref",1);
+            print "gen-ended!\n";
+            return;
+        }
+        
+        my $r;
+        #copy nettrace synful
+        dircopy("$src_c/netrace-1.0","$obj_dir/netrace-1.0") or $r=$!;
+        dircopy("$src_c/synfull","$obj_dir/synful") or $r=$!;
+        add_colored_info($info_text,"ERROR: $r\n","red") if(defined $r ) ;     
+        
+        #copy simulation c header files
+        @files = File::Find::Rule->file()
+            ->name( '*.h')
+            ->in( "$src_verilator_dir" );
+        
+        copy_file_and_folders (\@files,$project_dir,$obj_dir);
+        copy($testbench_file,"$obj_dir/testbench.cpp"); 
+        
+        #compile the testbench
+        my $param_h=gen_noc_param_h($simulate);
+        my $text = gen_sim_parameter_h($param_h,$includ_h,$ne,$nr,$router_p,$fifow);    
+        open(FILE,  ">$obj_dir/parameter.h") || die "Can not open: $!";
+        print FILE  "$text";
+        close FILE;
+        
+        #$result = run_make_file("$obj_dir/",$info_text,'lib');    
+        my $lib_num=0;
+        add_colored_info($info_text,"Makefie will use the maximum number of $cpu_num core(s) in parallel for compilation\n",'green');
+        my $length=scalar (keys %tops);
+        my $cmd="";
+        foreach my $top (sort keys %tops) { 
+            $cmd.= "lib$lib_num & ";
+            $lib_num++;                
+            if( $lib_num % $cpu_num == 0 || $lib_num == $length){
+                $cmd.="wait\n";
+                $result = run_make_file("$obj_dir/",$info_text,$cmd);    
+                if ($result ==0){
+                    $simulate->object_add_attribute('status',undef,'programmer_failed');
+                    set_gui_status($simulate,"ref",1);
+                    return;
+                }        
+                $cmd="";
+            }else {
+                $cmd.=" make ";
+            }    
+        }
+        
+        run_make_file("$obj_dir/",$info_text);    
+        if ($result ==0){
+            $simulate->object_add_attribute('status',undef,'programmer_failed');
+            set_gui_status($simulate,"ref",1);
+            return;
+        }        
+        #my $end = localtime;         
+        #save the binarry file
+        my $bin= "$obj_dir/testbench";
+        
+        #create project directory if it does not exist
+        my    ($stdout,$exit)=run_cmd_in_back_ground_get_stdout("mkdir -p $path" );
+        if($exit != 0 ){     print "$stdout\n";  print "gen-ended!\n";    message_dialog($stdout,'error'); return;}
+        
+        #check if the verilation was successful
+        if ((-e $bin)==0) {#something goes wrong         
+            #message_dialog("Verilator compilation was unsuccessful please check the $path/$name.log files for more information",'error'); 
+            add_colored_info($info_text,"Verilator compilation failed!\n","red"); 
+            $simulate->object_add_attribute('status',undef,'programmer_failed');
+            set_gui_status($simulate,"ref",1);
+            return;
+        }
+        #copy ($bin,"$path/$name") or  die "Can not copy: $!";
+        ($stdout,$exit)=run_cmd_in_back_ground_get_stdout("cp -f $bin $path/$name");
+        if($exit != 0 ){     print "$stdout\n";  message_dialog($stdout,'error'); return;}
+    }
+    #save noc info
+    open(FILE,  ">$path/$name.inf") || die "Can not open: $!";
+    print FILE perl_file_header("$name.inf");
+    my %pp;
+    $pp{'noc_param'}= $simulate->{'noc_param'};
+    $pp{'sim_param'}= $simulate->{'sim_param'};
+    print FILE Data::Dumper->Dump([\%pp],["emulate_info"]);
+    close(FILE) || die "Error closing file: $!";        
+    message_dialog("The simulation binary file has been successfully generated in $path!"); 
+    $simulate->object_add_attribute('status',undef,'ideal');
+    set_gui_status($simulate,"ref",1);
 }
 
 
-
-
-
-
-##########
-#	save_simulation
-##########
-sub save_simulation {
-	my ($simulate)=@_;
-	# read emulation name
-	my $name=$simulate->object_get_attribute ("simulate_name",undef);	
-	my $s= (!defined $name)? 0 : (length($name)==0)? 0 :1;	
-	if ($s == 0){
-		message_dialog("Please set Simulation name!");
-		return 0;
-	}
-	# Write object file
-	open(FILE,  ">lib/simulate/$name.SIM") || die "Can not open: $!";
-	print FILE perl_file_header("$name.SIM");
-	print FILE Data::Dumper->Dump([\%$simulate],["simulate"]);
-	close(FILE) || die "Error closing file: $!";
-	message_dialog("Simulation has saved as lib/simulate/$name.SIM!");
-	return 1;
-}
-
 #############
-#	load_simulation
+#    load_simulation
 ############
-
 sub load_simulation {
-	my ($simulate,$info)=@_;
-	my $file;
-	my $dialog =  gen_file_dialog (undef, 'SIM');	
-	
-	my $dir = Cwd::getcwd();
-	$dialog->set_current_folder ("$dir/lib/simulate");		
-
-
-	if ( "ok" eq $dialog->run ) {
-		$file = $dialog->get_filename;
-		my ($name,$path,$suffix) = fileparse("$file",qr"\..[^.]*$");
-		if($suffix eq '.SIM'){
-			my ($pp,$r,$err) = regen_object($file);
-			if ($r){		
-				add_colored_info($info,"**Error reading $file file: $err\n",'red');
-				$dialog->destroy;
-				return;
-			} 
-			#deactivate running simulations
-			$pp->object_add_attribute('status',undef,'ideal');
-			my @samples =$pp->object_get_attribute_order("samples");
-			foreach my $sample (@samples){
-				my $st=$pp->object_get_attribute ($sample,"status");	
-				$pp->object_add_attribute ($sample,"status",'done');# if ($st eq "run");	
-			}
-			clone_obj($simulate,$pp);
-			#message_dialog("done!");				
-		}					
-     }
-     $dialog->destroy;
+    my ($simulate,$info)=@_;
+    my $file;
+    my $dialog =  gen_file_dialog (undef, 'SIM');
+    my $dir = Cwd::getcwd();
+    $dialog->set_current_folder ("$dir/lib/simulate");
+    if ( "ok" eq $dialog->run ) {
+        $file = $dialog->get_filename;
+        my ($name,$path,$suffix) = fileparse("$file",qr"\..[^.]*$");
+        if($suffix eq '.SIM'){
+            my ($pp,$r,$err) = regen_object($file);
+            if ($r){        
+                add_colored_info($info,"**Error reading $file file: $err\n",'red');
+                $dialog->destroy;
+                return;
+            } 
+            #deactivate running simulations
+            $pp->object_add_attribute('status',undef,'ideal');
+            my @samples =$pp->object_get_attribute_order("samples");
+            foreach my $sample (@samples){
+                my $st=$pp->object_get_attribute ($sample,"status");
+                $pp->object_add_attribute ($sample,"status",'done');# if ($st eq "run");
+            }
+            clone_obj($simulate,$pp);
+        }
+    }
+    $dialog->destroy;
 }
 
-
-
-
 sub check_hotspot_parameters{
-	my ($self,$sample)=@_;
-	my $num=$self->object_get_attribute($sample,"HOTSPOT_NUM");
-	my $result;
-	if (defined $num){
-		my @hotspots;	
-		my $acuum=0;	
-		for (my $i=0;$i<$num;$i++){
-			my $w1 = $self->object_get_attribute($sample,"HOTSPOT_CORE_$i");
-			if( grep (/^\Q$w1\E$/,@hotspots)){
-				$result="Error: Tile $w1 has been selected for Two or more than two hotspot nodes.\n";					
-			}
-			push( @hotspots,$w1);			
-			my $w2 = $self->object_get_attribute($sample,"HOTSPOT_PERCENT_$i");
-			$acuum+=$w2;
-					
-		}
-		if ($acuum > 100){
-			$result="Error: The traffic summation of all hotspot nodes is $acuum. The hotspot summation must be <=100";
-			
-		}
-	}
-	return $result;
+    my ($self,$sample)=@_;
+    my $num=$self->object_get_attribute($sample,"HOTSPOT_NUM");
+    my $result;
+    if (defined $num){
+        my @hotspots;    
+        my $acuum=0;    
+        for (my $i=0;$i<$num;$i++){
+            my $w1 = $self->object_get_attribute($sample,"HOTSPOT_CORE_$i");
+            if( grep (/^\Q$w1\E$/,@hotspots)){
+                $result="Error: Tile $w1 has been selected for Two or more than two hotspot nodes.\n";                    
+            }
+            push( @hotspots,$w1);            
+            my $w2 = $self->object_get_attribute($sample,"HOTSPOT_PERCENT_$i");
+            $acuum+=$w2;
+        }
+        if ($acuum > 100){
+            $result="Error: The traffic summation of all hotspot nodes is $acuum. The hotspot summation must be <=100";
+        }
+    }
+    return $result;
 }
 
 sub get_district_avg { 
-	my ($self,$sample)=@_;
-	my $vt=$self->object_get_attribute($sample,"DISCRETE_RANGE");
-	$vt =  "2,3,4,5" unless (defined $vt);
-	my $pt=$self->object_get_attribute($sample,"PROBEB_RANGE");
-	$pt= "25,25,25,25" unless (defined $pt);
-	
-	my $avg=0;
-	my @valus = split(',',$vt);
-	my @probs = split(',',$pt);
-	my $i=0;
-	my $sum=0;
-	my $min=10000000;
-	my $max=0;
-	foreach my $v (@valus) { 
-		return ("-","The $v is not numeric value") unless (is_integer($v));
-		$sum+=	$probs[$i];
-		$avg+=$v*$probs[$i];
-		$i++;	
-		$min=$v if($min>$v);
-		$max=$v if($max<$v);
-	}
-	return ("-","The summation of probebilities are $sum which is not equal 100.") if($sum!=100);
-	$avg/=100;
-	
-	$self->object_add_attribute ($sample,"MIN_PCK_SIZE",$min);
-	$self->object_add_attribute ($sample,"MAX_PCK_SIZE",$max);
-	return ($avg,undef); 
+    my ($self,$sample)=@_;
+    my $vt=$self->object_get_attribute($sample,"DISCRETE_RANGE");
+    $vt =  "2,3,4,5" unless (defined $vt);
+    my $pt=$self->object_get_attribute($sample,"PROBEB_RANGE");
+    $pt= "25,25,25,25" unless (defined $pt);
+    my $avg=0;
+    my @valus = split(',',$vt);
+    my @probs = split(',',$pt);
+    my $i=0;
+    my $sum=0;
+    my $min=10000000;
+    my $max=0;
+    foreach my $v (@valus) { 
+        return ("-","The $v is not numeric value") unless (is_integer($v));
+        $sum+=    $probs[$i];
+        $avg+=$v*$probs[$i];
+        $i++;    
+        $min=$v if($min>$v);
+        $max=$v if($max<$v);
+    }
+    return ("-","The summation of probebilities are $sum which is not equal 100.") if($sum!=100);
+    $avg/=100;
+    $self->object_add_attribute ($sample,"MIN_PCK_SIZE",$min);
+    $self->object_add_attribute ($sample,"MAX_PCK_SIZE",$max);
+    return ($avg,undef); 
 }
 
 sub get_simulator_noc_configuration{
-	my ($self,$mode,$sample,$set_win) =@_;	
-		
-	my $table=def_table(10,2,FALSE);	
-	my $row=0;
-	
-	
-	my $scrolled_win = add_widget_to_scrolled_win ($table,gen_scr_win_with_adjst($self,'noc_conf_scr_win'));
-		
-	my $ok = def_image_button('icons/select.png','_OK',FALSE,1);
-	my $import   = def_image_button('icons/import.png','I_mport',FALSE,1);
-	my $save   = def_image_button('icons/save.png','_Export',FALSE,1);
-	
-	$save ->signal_connect("clicked"=> sub{
-		my $dialog=save_file_dialog  ("Enter configuration file name",'conf');
-		#$dialog->set_current_folder ($open_in) if(defined  $open_in);
-		if ( "ok" eq $dialog->run ) {
-	   		my	$file = $dialog->get_filename;
-	   		my ($name,$path,$suffix) = fileparse("$file",qr"\..[^.]*$");
-			my $t=$self->object_get_attribute($sample);
-			open(FILE,  ">$path/${name}.conf") || die "Can not open: $!";
-			print FILE Data::Dumper->Dump([\$t],['config']);
-			close FILE;
-		}	
-		$dialog->destroy();			
-	});
-	
-	$import ->signal_connect("clicked"=> sub{
-		my $dialog=save_file_dialog  ("Enter configuration file name",'conf');
-		#$dialog->set_current_folder ($open_in) if(defined  $open_in);
-		if ( "ok" eq $dialog->run ) {
-	   		my	$file = $dialog->get_filename;
-	   		my $pp= do $file ;		
-		    my $status=1;
-		    $status=0 if $@;
-			message_dialog("Error reading: $@") if $@;
-			if ($status==1){
-				$self->object_add_attribute ("$sample",undef,$$pp);
-				set_gui_status($self,'ref_set_win',1);
-			}
-		}
-		$dialog->destroy();		
-	});
-	
-	
-	
-	my $mtable = def_table(10, 3, TRUE);
-
-	$mtable->attach_defaults($scrolled_win,0,3,0,9);
-	$mtable-> attach ($ok , 1, 2,  9, 10,'expand','shrink',2,2); 
-	$mtable-> attach ($import , 0, 1,  9, 10,'expand','shrink',2,2); 
-	$mtable-> attach ($save , 2, 3,  9, 10,'expand','shrink',2,2); 
-	
-	
-
-	$set_win ->signal_connect (destroy => sub{		
-		$self->object_add_attribute("active_setting",undef,undef);
-		
-	});	
-		
-	
-	my $dir = Cwd::getcwd();
-	my $open_in	  = abs_path("$ENV{PRONOC_WORK}/simulate");	
-	
-	
-	attach_widget_to_table ($table,$row,gen_label_in_left(" Search Path:"),gen_button_message ("Select the Path where the verilator simulation files are located. Different NoC verilated models can be generated using Generate NoC configuration tab.","icons/help.png"), 
-	get_dir_in_object ($self,$sample,"sof_path",undef,'ref_set_win',1,$open_in)); $row++;
-	
-	$open_in	= $self->object_get_attribute($sample,"sof_path");	
-	
-	
-	
-	my @files = glob "$open_in/*";
-	my $exe_files="";
-	foreach my $file (@files){
-		my ($name,$path,$suffix) = fileparse("$file",qr"\..[^.]*$");
-		if($suffix eq '.inf'){
-			$exe_files="$exe_files,$name";
-		}		
-	}
-	my $model_obj = gen_combobox_object ($self,$sample, "sof_file", $exe_files, undef,'ref_set_win',1);	
-	attach_widget_to_table ($table,$row,gen_label_in_left(" Verilated Model:"),gen_button_message ("Select the verilator simulation file. Different NoC simulators can be generated using Generate NoC configuration tab.","icons/help.png"), 
-	$model_obj); $row++;
-      
+    my ($self,$mode,$sample,$set_win) =@_;    
+    my $table=def_table(10,2,FALSE);    
+    my $row=0;
+    my $scrolled_win = add_widget_to_scrolled_win ($table,gen_scr_win_with_adjst($self,'noc_conf_scr_win'));
+    my $ok = def_image_button('icons/select.png','_OK',FALSE,1);
+    my $import   = def_image_button('icons/import.png','I_mport',FALSE,1);
+    my $save   = def_image_button('icons/save.png','_Export',FALSE,1);
+    $save ->signal_connect("clicked"=> sub{
+        my $dialog=save_file_dialog  ("Enter configuration file name",'conf');
+        #$dialog->set_current_folder ($open_in) if(defined  $open_in);
+        if ( "ok" eq $dialog->run ) {
+            my    $file = $dialog->get_filename;
+            my ($name,$path,$suffix) = fileparse("$file",qr"\..[^.]*$");
+            my $t=$self->object_get_attribute($sample);
+            open(FILE,  ">$path/${name}.conf") || die "Can not open: $!";
+            print FILE Data::Dumper->Dump([\$t],['config']);
+            close FILE;
+        }
+        $dialog->destroy();
+    });
+    
+    $import ->signal_connect("clicked"=> sub{
+        my $dialog=save_file_dialog  ("Enter configuration file name",'conf');
+        #$dialog->set_current_folder ($open_in) if(defined  $open_in);
+        if ( "ok" eq $dialog->run ) {
+            my    $file = $dialog->get_filename;
+            my $pp= do $file;
+            my $status=1;
+            $status=0 if $@;
+            message_dialog("Error reading: $@") if $@;
+            if ($status==1){
+                $self->object_add_attribute ("$sample",undef,$$pp);
+                set_gui_status($self,'ref_set_win',1);
+            }
+        }
+        $dialog->destroy();
+    });
+    my $mtable = def_table(10, 3, TRUE);
+    $mtable->attach_defaults($scrolled_win,0,3,0,9);
+    $mtable-> attach ($ok , 1, 2,  9, 10,'expand','shrink',2,2); 
+    $mtable-> attach ($import , 0, 1,  9, 10,'expand','shrink',2,2); 
+    $mtable-> attach ($save , 2, 3,  9, 10,'expand','shrink',2,2); 
+    $set_win ->signal_connect (destroy => sub{        
+        $self->object_add_attribute("active_setting",undef,undef);
+        
+    });
+    
+    my $dir = Cwd::getcwd();
+    my $open_in      = abs_path("$ENV{PRONOC_WORK}/simulate");    
+    
+    attach_widget_to_table ($table,$row,gen_label_in_left(" Search Path:"),gen_button_message ("Select the Path where the verilator simulation files are located. Different NoC verilated models can be generated using Generate NoC configuration tab.","icons/help.png"), 
+    get_dir_in_object ($self,$sample,"sof_path",undef,'ref_set_win',1,$open_in)); $row++;
+    $open_in  = $self->object_get_attribute($sample,"sof_path");    
+    
+    my @files = glob "$open_in/*";
+    my $exe_files="";
+    foreach my $file (@files){
+        my ($name,$path,$suffix) = fileparse("$file",qr"\..[^.]*$");
+        if($suffix eq '.inf'){
+            $exe_files="$exe_files,$name";
+        }
+    }
+    my $model_obj = gen_combobox_object ($self,$sample, "sof_file", $exe_files, undef,'ref_set_win',1);    
+    attach_widget_to_table ($table,$row,gen_label_in_left(" Verilated Model:"),gen_button_message ("Select the verilator simulation file. Different NoC simulators can be generated using Generate NoC configuration tab.","icons/help.png"), 
+    $model_obj); $row++;
     my $cast_type=  '"UNICAST"';
-      
     #get simulation parameters here                        
-  	my $s=$self->object_get_attribute($sample,"sof_file");
-  	if (defined $s){
-  		my ($infobox,$info)= create_txview();
-  		my $sof=get_sim_bin_path($self,$sample,$info);  		
-  		my ($name,$path,$suffix) = fileparse("$sof",qr"\..[^.]*$");
-		my $sof_info= "$path$name.inf";
-  		
-  		my $pp= do $sof_info ;
-		my $p=$pp->{'noc_param'};
-  		$cast_type = $p->{'CAST_TYPE'};  
-  		$cast_type=  '"UNICAST"' if (!defined $cast_type);
-  	}
-  
-   my $trf_info = "Select of the following traffic models:
-   1- Synthetic
-   2- Task-graph :  
-       The task graph traffic pattern can be generated
-       using ProNoC trace generator	
-   3- Netrace: 
-       Dependency-Tracking Trace-Based Network-on-Chip
-       Simulation. For downloading the trace files and more 
-       information refere to https://www.cs.utexas.edu/~netrace/
-   4- SynFull: 
-       Synthetic Traffic Models Capturing a Full Range
-       of Cache Coherent Behaviour
-       https://github.com/mariobadr/synfull-isca   
+    my $s=$self->object_get_attribute($sample,"sof_file");
+    if (defined $s){
+        my ($infobox,$info)= create_txview();
+        my $sof=get_sim_bin_path($self,$sample,$info);          
+        my ($name,$path,$suffix) = fileparse("$sof",qr"\..[^.]*$");
+        my $sof_info= "$path$name.inf";
+        my $pp= do $sof_info ;
+        my $p=$pp->{'noc_param'};
+        $cast_type = $p->{'CAST_TYPE'};  
+        $cast_type=  '"UNICAST"' if (!defined $cast_type);
+    }
+    my $trf_info = "Select of the following traffic models:
+    1- Synthetic
+    2- Task-graph :  
+        The task graph traffic pattern can be generated
+        using ProNoC trace generator    
+    3- Netrace: 
+        Dependency-Tracking Trace-Based Network-on-Chip
+        Simulation. For downloading the trace files and more 
+        information refere to https://www.cs.utexas.edu/~netrace/
+    4- SynFull: 
+        Synthetic Traffic Models Capturing a Full Range
+        of Cache Coherent Behaviour
+        https://github.com/mariobadr/synfull-isca   
 "; 
-   
     my $coltmp=0;
     ($row,$coltmp)=add_param_widget  ($self, "Traffic Type", "TRAFFIC_TYPE", "Synthetic", 'Combo-box', "Synthetic,Task-graph,SynFull,Netrace", $trf_info, $table,$row,undef,1, $sample, 1,'ref_set_win');
-    
     my $traffictype=$self->object_get_attribute($sample,"TRAFFIC_TYPE");
     my $MIN_PCK_SIZE=$self->object_get_attribute($sample,"MIN_PCK_SIZE");
+    my $max_pck_num = get_MAX_PCK_NUM();
+    my $max_sim_clk = get_MAX_SIM_CLKs();
+    my $pck_info = "Select how injected packet size are selected. 
+        random-range:    The injected packet size is randomly selected between given minimum and maximum packet size. 
+        random-discrete: The injected packet size is randomly selected among given district valuse.";
+    if($traffictype eq "Synthetic"){
+        my $min=$self->object_get_attribute($sample,'MIN_PCK_SIZE');
+        my $max=$self->object_get_attribute($sample,'MAX_PCK_SIZE');
+        $min=5 if(!defined $min);
+        $max=5 if(!defined $max);
+        $max= $min if($max< $min);
+        my $avg=floor(($min+$max)/2);
+        my $msg;
+        my $max_pck_size = get_MAX_PCK_SIZ();
+        my $NE;
+        my ($infobox,$info)= create_txview();
+        my $traffics="tornado,transposed 1,transposed 2,bit reverse,bit complement,random,hot spot,shuffle,bit rotation,neighbor,custom";     
+        my @synthinfo = (
+        { label=>'Configuration name:', param_name=>'line_name', type=>'Entry', default_val=>$sample, content=>undef, info=>"NoC configuration name. This name will be shown in load-latency graph for this configuration", param_parent=>$sample, ref_delay=> undef, new_status=>undef},
+        { label=>"Total packet number limit:", param_name=>'PCK_NUM_LIMIT', type=>'Spin-button', default_val=>200000, content=>"2,$max_pck_num,1", info=>"Simulation will stop when total number of sent packets by all nodes reaches packet number limit  or total simulation clock reach its limit", param_parent=>$sample, ref_delay=>undef, new_status=>undef},
+        { label=>"Simulator clocks limit:", param_name=>'SIM_CLOCK_LIMIT', type=>'Spin-button', default_val=>100000, content=>"2,$max_sim_clk,1", info=>"Each node stops sending packets when it reaches packet number limit  or simulation clock number limit", param_parent=>$sample, ref_delay=>undef,  new_status=>undef},
+        { label=>"Traffic name", param_name=>'traffic', type=>'Combo-box', default_val=>'random', content=>$traffics, info=>"Select traffic pattern", param_parent=>$sample, ref_delay=>1, new_status=>'ref_set_win'},
+        { label=>"Packet size (#flit)", param_name=>'PCK_SIZ_SEL', type=>'Combo-box', default_val=>'random-range', content=>"random-range,random-discrete", info=>$pck_info, param_parent=>$sample, ref_delay=>1, new_status=>'ref_set_win'},
+        );
+        my $coltmp=0;
+        foreach my $d (@synthinfo) {
+            ($row,$coltmp)=add_param_widget ($self, $d->{label}, $d->{param_name}, $d->{default_val}, $d->{type}, $d->{content}, $d->{info}, $table,$row,undef,1, $d->{param_parent}, $d->{ref_delay}, $d->{new_status});
+        }
+        
+        my $t=$self->object_get_attribute($sample,"PCK_SIZ_SEL");
+        if($t eq 'random-range' ){
+            @synthinfo = (    
+            { label=>"Min pck size :", param_name=>'MIN_PCK_SIZE', type=>'Spin-button', default_val=>5, content=>"1,$max,1", info=>"Minimum packet size in flit. The injected packet size is randomly selected between minimum and maximum packet size", param_parent=>$sample, ref_delay=>10, new_status=>'ref_set_win'},
+            { label=>"Max pck size :", param_name=>'MAX_PCK_SIZE', type=>'Spin-button', default_val=>5, content=>"$min,$max_pck_size,1", info=>"Maximum packet size in flit. The injected packet size is randomly selected between minimum and maximum packet size", param_parent=>$sample, ref_delay=>10, new_status=>'ref_set_win'},
+            { label=>"Avg. Packet size:", param_name=>'PCK_SIZE', type=>'Fixed', default_val=>$avg, content=>"$avg", info=>undef, param_parent=>$sample, ref_delay=>undef},
+            );
+        }else{
+            #$self->object_add_attribute ($sample,"MIN_PCK_SIZE",2);#will be updated by get_district_avg  
+            my $vt=$self->object_get_attribute($sample,"DISCRETE_RANGE");
+            $vt =  "2,3,4,5" unless (defined $vt);
+            my $pt=$self->object_get_attribute($sample,"PROBEB_RANGE");
+            $pt= "25,25,25,25" unless (defined $pt);
+            @synthinfo = (
+            { label=>"pck size discrete range: ", param_name=>'DISCRETE_RANGE', type=>'Entry', default_val=>$vt, content=>undef, info=>"Set discrete set of number as packet size separated by \",\" (v1,v2,v3 ..). The injected packet size is randomly selected among these discrete values", param_parent=>$sample, ref_delay=>10, new_status=>'ref_set_win'},
+            { label=>"pck size probebility(%): ", param_name=>'PROBEB_RANGE'  , type=>'Entry', default_val=>$pt, content=>undef, info=>"Set the probability  separated by \",\" (p1,p2,p3 ..). The probabilities pi must satisfy two requirements: every probability pi is a number between 0 and 100, and the sum of all the probabilities is 100.", param_parent=>$sample, ref_delay=>10, new_status=>'ref_set_win'},
+            # { label=>"Avg. Packet size:", param_name=>'PCK_SIZE', type=>'Fixed', default_val=>$avg, content=>"$avg", info=>undef, param_parent=>$sample, ref_delay=>undef}, 
+            );    
+        }
+        foreach my $d (@synthinfo){
+            ($row,$coltmp)=add_param_widget ($self, $d->{label}, $d->{param_name}, $d->{default_val}, $d->{type}, $d->{content}, $d->{info}, $table,$row,undef,1, $d->{param_parent}, $d->{ref_delay}, $d->{new_status});
+        }
+        if(defined $msg){
+            my $error= def_image_button("icons/cancel.png");
+            $table->attach  ($error , 6, 7,  $row-1,$row,'shrink','shrink',2,2); 
+        }
+        my $traffic=$self->object_get_attribute($sample,"traffic");
+        my $st =  check_sim_sample($self,$sample,$info);  
+        if ($st==0){
+                $NE=100;
+        }else{
+            my ($NEe, $NR, $RAw, $EAw, $Fw) = get_sample_topology_info($self,$sample);
+            $NE=$NEe;
+        }
+        if ($traffic eq 'custom'){
+            my $htable=def_table(10,2,FALSE);
+            my $d= { label=>'number of active nodes:', param_name=>'CUSTOM_SRC_NUM', type=>'Spin-button', default_val=>1,  content=>"1,$NE,1", info=>"Number of active nodes which injects packets to the NoC",              param_parent=>$sample, ref_delay=> 1, new_status=>'ref_set_win'};
+            ($row,$coltmp)=add_param_widget ($self, $d->{label}, $d->{param_name}, $d->{default_val}, $d->{type}, $d->{content}, $d->{info}, $table,$row,undef,1, $d->{param_parent}, $d->{ref_delay}, $d->{new_status});
+            my $num=$self->object_get_attribute($sample,"CUSTOM_SRC_NUM");
+            $htable->attach ( gen_label_in_left ("Source "), 0, 1,  $row,$row+1,'fill','shrink',2,2);
+            $htable->attach ( gen_label_in_left (" -> "), 1, 2,  $row,$row+1,'fill','shrink',2,2);
+            $htable->attach ( gen_label_in_left ("Destination"), 2, 3,  $row,$row+1,'fill','shrink',2,2);                        
+            $row++;
+            my $tiles="0";
+            for (my $i=1;$i<$NE;$i++){$tiles.=",$i";}
+            for (my $i=0;$i<$num;$i++){
+                my $w1 = gen_combobox_object ($self,$sample,"SRC_$i",$tiles, $i,undef,undef);
+                my $w2 = gen_combobox_object ($self,$sample,"DST_$i",$tiles, $i+1,undef,undef);
+                $htable->attach  ($w1 , 0, 1,  $row,$row+1,'shrink','shrink',2,2);
+                $htable->attach  ($w2 , 2, 3,  $row,$row+1,'shrink','shrink',2,2);
+                $row++;
+            }
+            $table->attach  ($htable , 0, 3,  $row,$row+1,'shrink','shrink',2,2); $row++;
+        }
+        if ($cast_type ne '"UNICAST"'){    
+            my $min=$self->object_get_attribute($sample,'MCAST_PCK_SIZ_MIN');
+            my $max=$self->object_get_attribute($sample,'MCAST_PCK_SIZ_MAX');
+            $min=5 if(!defined $min);
+            $max=5 if(!defined $max);
+            $max= $min if($max< $min);
+            my $s = ($cast_type eq '"BROADCAST_FULL"' || $cast_type eq '"BROADCAST_PARTIAL"')? "Broadcast" :  "Milticast";
+            my $info1= "Define the percentage ratio of $s traffic towards Unicast traffic";
+            my $info2= "Define how destinations is selected in Multicast packets";
+            ($row,$coltmp)=add_param_widget  ($self, "$s Node Select"  , "MCAST_TRAFFIC_TYPE" , "Uniform-Random",  'Combo-box', "Uniform-Random", $info1, $table,$row,undef,1, $sample);
+            ($row,$coltmp)=add_param_widget  ($self, "$s Traffic Ratio", "MCAST_TRAFFIC_RATIO", 5 , 'Spin-button',  "0,100,1"  , $info2, $table,$row,undef,1, $sample);    
+            ($row,$coltmp)=add_param_widget  ($self, "$s min pck size", "MCAST_PCK_SIZ_MIN", 5 , 'Spin-button',  "1,$max,1"  , $info2, $table,$row,undef,1, $sample,1,'ref_set_win');    
+            ($row,$coltmp)=add_param_widget  ($self, "$s max pck size", "MCAST_PCK_SIZ_MAX", 5 , 'Spin-button',  "$min,100,1"  , $info2, $table,$row,undef,1, $sample,1,'ref_set_win');    
+        }
+        my $d= { label=>'number of message class:', param_name=>'MESSAGE_CLASS', type=>'Spin-button', default_val=>0,  content=>"0,256,1", info=>"Number of packet message classes. Each message class can be configured to use specefic subset of avilable VCs",              param_parent=>$sample, ref_delay=> 1, new_status=>'ref_set_win'};
+        ($row,$coltmp)=add_param_widget ($self, $d->{label}, $d->{param_name}, $d->{default_val}, $d->{type}, $d->{content}, $d->{info}, $table,$row,undef,1, $d->{param_parent}, $d->{ref_delay}, $d->{new_status});
+        my $num=$self->object_get_attribute($sample,"MESSAGE_CLASS");
+        if($num>0){
+            my $htable=def_table(10,2,FALSE);
+            $htable->attach ( gen_label_in_left ("Class num "), 0, 1,  $row,$row+1,'fill','shrink',2,2);
+            $htable->attach ( gen_label_in_left (" - "), 1, 2,  $row,$row+1,'fill','shrink',2,2);
+            $htable->attach ( gen_label_in_left ("Traffic(%)"), 2, 3,  $row,$row+1,'fill','shrink',2,2);                        
+            $row++;
+            for (my $i=0;$i<$num;$i++){    
+                $htable->attach ( gen_label_in_left ("$i"), 0, 1,  $row,$row+1,'fill','shrink',2,2);
+                my $w1 = gen_spin_object ($self,$sample,"CLASS_$i","0,100,1", 100/$num,undef,undef);
+                $htable->attach ( $w1, 2, 3,  $row,$row+1,'fill','shrink',2,2);
+                $row++;
+            }
+            $table->attach  ($htable , 0, 3,  $row,$row+1,'shrink','shrink',2,2); $row++;
+        }
+        if ($traffic eq 'hot spot'){
+            my $htable=def_table(10,2,FALSE);
+            my $d= { label=>'number of Hot Spot nodes:', param_name=>'HOTSPOT_NUM', type=>'Spin-button', default_val=>1,  content=>"1,256,1", info=>"Number of hot spot nodes in the network",              param_parent=>$sample, ref_delay=> 1, new_status=>'ref_set_win'};
+            ($row,$coltmp)=add_param_widget ($self, $d->{label}, $d->{param_name}, $d->{default_val}, $d->{type}, $d->{content}, $d->{info}, $table,$row,undef,1, $d->{param_parent}, $d->{ref_delay}, $d->{new_status});
+                my $l1=gen_label_help("Define the tile number which is  hotspt. All other nodes will send [Hot Spot traffic percentage] of their traffic to this node","  Hot Spot tile number \%");
+                my $l2=gen_label_help("If it is set as \"n\" then each node sends n % of its traffic to each hotspot node","  Hot Spot traffic \%");
+                my $l3=gen_label_help("If it is checked then hot spot node also sends packets to other nodes otherwise it only receives packets from other nodes","  send enable");
+                $htable->attach  ($l1 , 0, 1,  $row,$row+1,'fill','shrink',2,2);
+                $htable->attach  ($l2 , 1, 2,  $row,$row+1,'fill','shrink',2,2);
+                $htable->attach  ($l3 , 2,3,  $row,$row+1,'fill','shrink',2,2);
+                $row++;
+                my $num=$self->object_get_attribute($sample,"HOTSPOT_NUM");
+                for (my $i=0;$i<$num;$i++){
+                    my $w1 = gen_spin_object ($self,$sample,"HOTSPOT_CORE_$i","0,256,1", $i,undef,undef);
+                    my $w2 = gen_spin_object ($self,$sample,"HOTSPOT_PERCENT_$i","0.1,100,0.1", 0.1,undef,undef);
+                    my $w3 = gen_check_box_object ($self,$sample,"HOTSPOT_SEND_EN_$i", 0,undef,undef);
+                    $htable->attach  ($w1 , 0, 1,  $row,$row+1,'fill','shrink',2,2);
+                    $htable->attach  ($w2 ,1, 2,  $row,$row+1,'fill','shrink',2,2);
+                    $htable->attach  ($w3 , 2,3,  $row,$row+1,'fill','shrink',2,2);
+                    $row++;
+                }
+                $table->attach  ($htable , 0, 3,  $row,$row+1,'shrink','shrink',2,2); $row++;
+        }
+        my $l= "Define injection ratios. You can define individual ratios separating by comma (\',\') or define a range of injection ratios with \$min:\$max:\$step format.
+            As an example defining 2,3,4:10:2 will result in (2,3,4,6,8,10) injection ratios." ;
+        my $u=get_injection_ratios ($self,$sample,"ratios");
+        attach_widget_to_table ($table,$row,gen_label_in_left(" Injection ratios:"),gen_button_message ($l,"icons/help.png") , $u); $row++;
+        $ok->signal_connect("clicked"=> sub{
+            #check if sof file has been selected
+            my $s=$self->object_get_attribute($sample,"sof_file");
+            #check if injection ratios are valid
+            my $r=$self->object_get_attribute($sample,"ratios");
+            my $h;
+            my $t=$self->object_get_attribute($sample,"PCK_SIZ_SEL");
+            unless ($t eq 'random-range' ){
+                ($avg,$msg) = get_district_avg($self,$sample);    
+                if(defined $msg){ 
+                    message_dialog($msg);  
+                    return;
+                }
+            }
+            if ($traffic eq 'hot spot'){
+                $h= check_hotspot_parameters($self,$sample);
+            }
+            my $v;
+            if(defined $r ){
+                    $v=check_inserted_ratios($r);
+            }
+            if(defined $s && defined $r && defined $v && !defined $h) {    
+                    #$set_win->destroy;
+                    $set_win->hide();
+                    $self->object_add_attribute("active_setting",undef,undef);
+                    set_gui_status($self,"ref",1);
+            } else {
+                if(!defined $s){
+                    my $m= "Please select NoC verilated file";
+                    message_dialog($m);  
+                } elsif (! defined $r) {
+                    message_dialog("Please define valid injection ratio(s)!");
+                } elsif (defined $h){
+                    message_dialog("$h");
+                }
+            }
+        });
+    }
+    if($traffictype eq "Task-graph"){
+        my @custominfo = (
+        #{ label=>"Verilated Model", param_name=>'sof_file', type=>'Combo-box', default_val=>undef, content=>$exe_files, info=>"Select the verilator simulation file. Different NoC simulators can be generated using Generate NoC configuration tab.", param_parent=>$sample, ref_delay=>undef, new_status=>undef},
+        { label=>'Configuration name:', param_name=>'line_name', type=>'Entry', default_val=>$sample, content=>undef, info=>"NoC configuration name. This name will be shown in load-latency graph for this configuration", param_parent=>$sample, ref_delay=> undef, new_status=>undef},
+        { label=>"Number of Files", param_name=>"TRAFFIC_FILE_NUM", type=>'Spin-button', default_val=>1, content=>"1,100,1", info=>"Select number of input files", param_parent=>$sample, ref_delay=>1, new_status=>'ref_set_win'},
+        { label=>"Simulator clocks limit:", param_name=>'SIM_CLOCK_LIMIT', type=>'Spin-button', default_val=>100000, content=>"2,$max_sim_clk,1", info=>"Each node stops sending packets when it reaches packet number limit  or simulation clock number limit", param_parent=>$sample, ref_delay=>undef,  new_status=>undef},
+        );
+        foreach my $d (@custominfo) {
+            ($row,$coltmp)=add_param_widget ($self, $d->{label}, $d->{param_name}, $d->{default_val}, $d->{type}, $d->{content}, $d->{info}, $table,$row,undef,1, $d->{param_parent}, $d->{ref_delay}, $d->{new_status});
+            
+        }
+        my $open_in  = "$ENV{'PRONOC_WORK'}/traffic_pattern";
+        my $num=$self->object_get_attribute($sample,"TRAFFIC_FILE_NUM");
+        for (my $i=0; $i<$num; $i++){
+            attach_widget_to_table ($table,$row,gen_label_in_left("traffic pattern file $i:"),gen_button_message ("Select the traffic pattern input file. Any custom traffic based on application task graphs can be generated using ProNoC Trace Generator tool.","icons/help.png"), get_file_name_object ($self,$sample,"traffic_file$i",undef,$open_in)); $row++;
+        }
+        $ok->signal_connect("clicked"=> sub{
+            #check if sof file has been selected
+            my $s=$self->object_get_attribute($sample,"sof_file");
+            if(!defined $s){
+                message_dialog("Please select NoC verilated file"); 
+                return;
+            }
+            #check if traffic files have been selected
+            for (my $i=0; $i<$num; $i++){
+                my $f=$self->object_get_attribute($sample,"traffic_file$i");
+                if(!defined $f){
+                    my $m= "Please select traffic_file$i";
+                    message_dialog($m); 
+                    return;
+                }
+            }
+            #$set_win->destroy;
+            $set_win->hide();
+            $self->object_add_attribute("active_setting",undef,undef);
+            set_gui_status($self,"ref",1);
+        });
+    }
+    if($traffictype eq "SynFull"){
+        #get the synful model names
+        my $models_dir  = get_project_dir()."/mpsoc/src_c/synfull/generated-models/";        
+        my ($flist)=get_file_list_by_extention ("$models_dir",".model");
+        my $model_obj = gen_combobox_object ($self,$sample, "MODEL_NAME", $flist, undef,undef,undef);    
+        attach_widget_to_table ($table,$row,gen_label_in_left(" Traffic Model name:"),gen_button_message ("Select an application traffic model.","icons/help.png"), 
+        $model_obj); $row++;
+        my @custominfo = (
+        { label=>"Synful Flit-size:(Bytes)", param_name=>'SYNFUL_FLITw', type=>'Spin-button', default_val=>4, content=>"4,72,4", info=>"The synful flit size in Byte. It defines the number of flits that should be set to ProNoC for each synful packets. The ProNoC packet size is : 
+        \t Ceil( synful packet size/synful flit size).  ", param_parent=>$sample, ref_delay=>undef,  new_status=>undef},
+        { label=>'Configuration name:', param_name=>'line_name', type=>'Entry', default_val=>$sample, content=>undef, info=>"NoC configuration name. This name will be shown in load-latency graph for this configuration", param_parent=>$sample, ref_delay=> undef, new_status=>undef},
+        { label=>"Total packet number limit:", param_name=>'PCK_NUM_LIMIT', type=>'Spin-button', default_val=>200000, content=>"2,$max_pck_num,1", info=>"Simulation will stop when total number of sent packets by all nodes reaches packet number limit  or total simulation clock reach its limit", param_parent=>$sample, ref_delay=>undef, new_status=>undef},
+        { label=>"Simulator clocks limit:", param_name=>'SIM_CLOCK_LIMIT', type=>'Spin-button', default_val=>100000, content=>"2,$max_sim_clk,1", info=>"Each node stops sending packets when it reaches packet number limit  or simulation clock number limit", param_parent=>$sample, ref_delay=>undef,  new_status=>undef},
+        { label=>"Markov Chain Random seed:", param_name=>'RND_SEED', type=>'Spin-button', default_val=>53432145, content=>"0,999999999,1", info=>"The seed valus is passe to synfull random number generator.", param_parent=>$sample, ref_delay=>undef,  new_status=>undef},
+        { label=>"Exit at steady state:", param_name=>'EXIT_STEADY', type=>'Check-box', default_val=>0, content=>"1", info=>"Exit the simulation when it reaches to a steady state.", param_parent=>$sample, ref_delay=>undef,  new_status=>undef},
+        );
+        foreach my $d (@custominfo) {
+            ($row,$coltmp)=add_param_widget ($self, $d->{label}, $d->{param_name}, $d->{default_val}, $d->{type}, $d->{content}, $d->{info}, $table,$row,undef,1, $d->{param_parent}, $d->{ref_delay}, $d->{new_status});
+            
+        }    
+        $ok->signal_connect("clicked"=> sub{
+            #check if sof file has been selected
+            my $s=$self->object_get_attribute($sample,"MODEL_NAME");
+            if(!defined $s){
+                    message_dialog("Please select a SynFull traffic model"); 
+                    return;
+            }
+            #$set_win->destroy;
+            $set_win->hide();
+            $self->object_add_attribute("active_setting",undef,undef);
+            set_gui_status($self,"ref",1);
+        });
+    }#SynFull
     
-   
-    
-   my $max_pck_num = get_MAX_PCK_NUM();
-   my $max_sim_clk = get_MAX_SIM_CLKs();
-   
-   my $pck_info = "Select how injected packet size are selected. 
-		random-range:    The injected packet size is randomly selected between given minimum and maximum packet size. 
-		random-discrete: The injected packet size is randomly selected among given district valuse.";
-	
-	if($traffictype eq "Synthetic"){
-		
-		my $min=$self->object_get_attribute($sample,'MIN_PCK_SIZE');
-		my $max=$self->object_get_attribute($sample,'MAX_PCK_SIZE');
-		$min=5 if(!defined $min);
-		$max=5 if(!defined $max);
-		$max= $min if($max< $min);
-		my $avg=floor(($min+$max)/2);	
-		my $msg;
-		my $max_pck_size =	 get_MAX_PCK_SIZ();
-		
-		my $NE;
-		my ($infobox,$info)= create_txview();
-		
-		
-		my $traffics="tornado,transposed 1,transposed 2,bit reverse,bit complement,random,hot spot,shuffle,bit rotation,neighbor,custom"; 	
-		my @synthinfo = (
-		
-		
-		{ label=>'Configuration name:', param_name=>'line_name', type=>'Entry', default_val=>$sample, content=>undef, info=>"NoC configuration name. This name will be shown in load-latency graph for this configuration", param_parent=>$sample, ref_delay=> undef, new_status=>undef},
-	
-		
-		
-		{ label=>"Total packet number limit:", param_name=>'PCK_NUM_LIMIT', type=>'Spin-button', default_val=>200000, content=>"2,$max_pck_num,1", info=>"Simulation will stop when total number of sent packets by all nodes reaches packet number limit  or total simulation clock reach its limit", param_parent=>$sample, ref_delay=>undef, new_status=>undef},
-	
-		{ label=>"Simulator clocks limit:", param_name=>'SIM_CLOCK_LIMIT', type=>'Spin-button', default_val=>100000, content=>"2,$max_sim_clk,1", info=>"Each node stops sending packets when it reaches packet number limit  or simulation clock number limit", param_parent=>$sample, ref_delay=>undef,  new_status=>undef},
-		
-		{ label=>"Traffic name", param_name=>'traffic', type=>'Combo-box', default_val=>'random', content=>$traffics, info=>"Select traffic pattern", param_parent=>$sample, ref_delay=>1, new_status=>'ref_set_win'},
-	
-		{ label=>"Packet size (#flit)", param_name=>'PCK_SIZ_SEL', type=>'Combo-box', default_val=>'random-range', content=>"random-range,random-discrete", info=>$pck_info, param_parent=>$sample, ref_delay=>1, new_status=>'ref_set_win'},
-	
-		);
-		my $coltmp=0;
-		
-		foreach my $d (@synthinfo) {
-			
-			($row,$coltmp)=add_param_widget ($self, $d->{label}, $d->{param_name}, $d->{default_val}, $d->{type}, $d->{content}, $d->{info}, $table,$row,undef,1, $d->{param_parent}, $d->{ref_delay}, $d->{new_status});
-			
-		}
-		
-		my $t=$self->object_get_attribute($sample,"PCK_SIZ_SEL");
-		if($t eq 'random-range' ){
-			
-			@synthinfo = (	
-			{ label=>"Min pck size :", param_name=>'MIN_PCK_SIZE', type=>'Spin-button', default_val=>5, content=>"1,$max,1", info=>"Minimum packet size in flit. The injected packet size is randomly selected between minimum and maximum packet size", param_parent=>$sample, ref_delay=>10, new_status=>'ref_set_win'},
-			{ label=>"Max pck size :", param_name=>'MAX_PCK_SIZE', type=>'Spin-button', default_val=>5, content=>"$min,$max_pck_size,1", info=>"Maximum packet size in flit. The injected packet size is randomly selected between minimum and maximum packet size", param_parent=>$sample, ref_delay=>10, new_status=>'ref_set_win'},
-			{ label=>"Avg. Packet size:", param_name=>'PCK_SIZE', type=>'Fixed', default_val=>$avg, content=>"$avg", info=>undef, param_parent=>$sample, ref_delay=>undef},
-			);
-			
-		}else{
-			#$self->object_add_attribute ($sample,"MIN_PCK_SIZE",2);#will be updated by get_district_avg  
-			my $vt=$self->object_get_attribute($sample,"DISCRETE_RANGE");
-			$vt =  "2,3,4,5" unless (defined $vt);
-			my $pt=$self->object_get_attribute($sample,"PROBEB_RANGE");
-			$pt= "25,25,25,25" unless (defined $pt);
-			
-			#($avg,$msg) = get_district_avg($self,$sample);
-			
-			 
-			@synthinfo = (	
-			{ label=>"pck size discrete range: ", param_name=>'DISCRETE_RANGE', type=>'Entry', default_val=>$vt, content=>undef, info=>"Set discrete set of number as packet size separated by \",\" (v1,v2,v3 ..). The injected packet size is randomly selected among these discrete values", param_parent=>$sample, ref_delay=>10, new_status=>'ref_set_win'},
-		    { label=>"pck size probebility(%): ", param_name=>'PROBEB_RANGE'  , type=>'Entry', default_val=>$pt, content=>undef, info=>"Set the probability  separated by \",\" (p1,p2,p3 ..). The probabilities pi must satisfy two requirements: every probability pi is a number between 0 and 100, and the sum of all the probabilities is 100.", param_parent=>$sample, ref_delay=>10, new_status=>'ref_set_win'},
-		   # { label=>"Avg. Packet size:", param_name=>'PCK_SIZE', type=>'Fixed', default_val=>$avg, content=>"$avg", info=>undef, param_parent=>$sample, ref_delay=>undef}, 
-			);	
-			
-			
-		}	
-		
-		foreach my $d (@synthinfo){
-		 	($row,$coltmp)=add_param_widget ($self, $d->{label}, $d->{param_name}, $d->{default_val}, $d->{type}, $d->{content}, $d->{info}, $table,$row,undef,1, $d->{param_parent}, $d->{ref_delay}, $d->{new_status});
-		}
-		if(defined $msg){
-				my $error= def_image_button("icons/cancel.png");
-				$table->attach  ($error , 6, 7,  $row-1,$row,'shrink','shrink',2,2); 
-		}	
-			
-	
-		my $traffic=$self->object_get_attribute($sample,"traffic");
-		
-		my $st =  check_sim_sample($self,$sample,$info);  
-		if ($st==0){
-				$NE=100;
-		}else{
-			my ($topology, $T1, $T2, $T3, $V, $Fpay) = get_sample_emulation_param($self,$sample);
-			my ($NEe, $NR, $RAw, $EAw, $Fw) = get_topology_info_sub ($topology, $T1, $T2, $T3, $V, $Fpay);
-			$NE=$NEe;				
-		}
-			
-		
-		if ($traffic eq 'custom'){
-						
-			
-			my $htable=def_table(10,2,FALSE);
-			
-			my $d= { label=>'number of active nodes:', param_name=>'CUSTOM_SRC_NUM', type=>'Spin-button', default_val=>1,  content=>"1,$NE,1", info=>"Number of active nodes which injects packets to the NoC",			  param_parent=>$sample, ref_delay=> 1, new_status=>'ref_set_win'};
-			($row,$coltmp)=add_param_widget ($self, $d->{label}, $d->{param_name}, $d->{default_val}, $d->{type}, $d->{content}, $d->{info}, $table,$row,undef,1, $d->{param_parent}, $d->{ref_delay}, $d->{new_status});
-			my $num=$self->object_get_attribute($sample,"CUSTOM_SRC_NUM");
-			$htable->attach ( gen_label_in_left ("Source "), 0, 1,  $row,$row+1,'fill','shrink',2,2);
-			$htable->attach ( gen_label_in_left (" -> "), 1, 2,  $row,$row+1,'fill','shrink',2,2);
-			$htable->attach ( gen_label_in_left ("Destination"), 2, 3,  $row,$row+1,'fill','shrink',2,2);						
-			
-			$row++;
-			
-			
-			my $tiles="0";
-			for (my $i=1;$i<$NE;$i++){$tiles.=",$i";}
-			
-						
-			for (my $i=0;$i<$num;$i++){
-				my $w1 = gen_combobox_object ($self,$sample,"SRC_$i",$tiles, $i,undef,undef);
-				my $w2 = gen_combobox_object ($self,$sample,"DST_$i",$tiles, $i+1,undef,undef);
-				$htable->attach  ($w1 , 0, 1,  $row,$row+1,'shrink','shrink',2,2);
-				$htable->attach  ($w2 , 2, 3,  $row,$row+1,'shrink','shrink',2,2);
-				$row++;
-					
-			}	
-			$table->attach  ($htable , 0, 3,  $row,$row+1,'shrink','shrink',2,2); $row++;
-				
-		}
-		
-		
-		if ($cast_type ne '"UNICAST"'){	
-			my $min=$self->object_get_attribute($sample,'MCAST_PCK_SIZ_MIN');
-			my $max=$self->object_get_attribute($sample,'MCAST_PCK_SIZ_MAX');
-			$min=5 if(!defined $min);
-			$max=5 if(!defined $max);
-			$max= $min if($max< $min);
-		
-				
-			my $s = ($cast_type eq '"BROADCAST_FULL"' || $cast_type eq '"BROADCAST_PARTIAL"')? "Broadcast" :  "Milticast";
-			my $info1= "Define the percentage ratio of $s traffic towards Unicast traffic";
-			my $info2= "Define how destinations is selected in Multicast packets";
-			($row,$coltmp)=add_param_widget  ($self, "$s Node Select"  , "MCAST_TRAFFIC_TYPE" , "Uniform-Random",  'Combo-box', "Uniform-Random", $info1, $table,$row,undef,1, $sample);
-			($row,$coltmp)=add_param_widget  ($self, "$s Traffic Ratio", "MCAST_TRAFFIC_RATIO", 5 , 'Spin-button',  "0,100,1"  , $info2, $table,$row,undef,1, $sample);	
-			
-			($row,$coltmp)=add_param_widget  ($self, "$s min pck size", "MCAST_PCK_SIZ_MIN", 5 , 'Spin-button',  "1,$max,1"  , $info2, $table,$row,undef,1, $sample,1,'ref_set_win');	
-			
-			($row,$coltmp)=add_param_widget  ($self, "$s max pck size", "MCAST_PCK_SIZ_MAX", 5 , 'Spin-button',  "$min,100,1"  , $info2, $table,$row,undef,1, $sample,1,'ref_set_win');	
-			
-			
-						
-		}
-		
-		
-		
-		
-		my $d= { label=>'number of message class:', param_name=>'MESSAGE_CLASS', type=>'Spin-button', default_val=>0,  content=>"0,256,1", info=>"Number of packet message classes. Each message class can be configured to use specefic subset of avilable VCs",			  param_parent=>$sample, ref_delay=> 1, new_status=>'ref_set_win'};
-		($row,$coltmp)=add_param_widget ($self, $d->{label}, $d->{param_name}, $d->{default_val}, $d->{type}, $d->{content}, $d->{info}, $table,$row,undef,1, $d->{param_parent}, $d->{ref_delay}, $d->{new_status});
-		my $num=$self->object_get_attribute($sample,"MESSAGE_CLASS");
-		if($num>0){
-			my $htable=def_table(10,2,FALSE);
-			$htable->attach ( gen_label_in_left ("Class num "), 0, 1,  $row,$row+1,'fill','shrink',2,2);
-			$htable->attach ( gen_label_in_left (" - "), 1, 2,  $row,$row+1,'fill','shrink',2,2);
-			$htable->attach ( gen_label_in_left ("Traffic(%)"), 2, 3,  $row,$row+1,'fill','shrink',2,2);						
-			$row++;
-			
-			for (my $i=0;$i<$num;$i++){	
-				$htable->attach ( gen_label_in_left ("$i"), 0, 1,  $row,$row+1,'fill','shrink',2,2);
-				my $w1 = gen_spin_object ($self,$sample,"CLASS_$i","0,100,1", 100/$num,undef,undef);
-				$htable->attach ( $w1, 2, 3,  $row,$row+1,'fill','shrink',2,2);
-				$row++;
-			}
-			$table->attach  ($htable , 0, 3,  $row,$row+1,'shrink','shrink',2,2); $row++;
-		}
-		
-		
-
-		if ($traffic eq 'hot spot'){
-			my $htable=def_table(10,2,FALSE);
-			
-			my $d= { label=>'number of Hot Spot nodes:', param_name=>'HOTSPOT_NUM', type=>'Spin-button', default_val=>1,  content=>"1,256,1", info=>"Number of hot spot nodes in the network",			  param_parent=>$sample, ref_delay=> 1, new_status=>'ref_set_win'};
-			($row,$coltmp)=add_param_widget ($self, $d->{label}, $d->{param_name}, $d->{default_val}, $d->{type}, $d->{content}, $d->{info}, $table,$row,undef,1, $d->{param_parent}, $d->{ref_delay}, $d->{new_status});
-				
-				my $l1=gen_label_help("Define the tile number which is  hotspt. All other nodes will send [Hot Spot traffic percentage] of their traffic to this node","  Hot Spot tile number \%");
-				my $l2=gen_label_help("If it is set as \"n\" then each node sends n % of its traffic to each hotspot node","  Hot Spot traffic \%");
-				my $l3=gen_label_help("If it is checked then hot spot node also sends packets to other nodes otherwise it only receives packets from other nodes","  send enable");
-				
-				$htable->attach  ($l1 , 0, 1,  $row,$row+1,'fill','shrink',2,2);
-				$htable->attach  ($l2 , 1, 2,  $row,$row+1,'fill','shrink',2,2);
-				$htable->attach  ($l3 , 2,3,  $row,$row+1,'fill','shrink',2,2);
-				$row++;
-						
-				my $num=$self->object_get_attribute($sample,"HOTSPOT_NUM");
-				for (my $i=0;$i<$num;$i++){
-					my $w1 = gen_spin_object ($self,$sample,"HOTSPOT_CORE_$i","0,256,1", $i,undef,undef);
-					my $w2 = gen_spin_object ($self,$sample,"HOTSPOT_PERCENT_$i","0.1,100,0.1", 0.1,undef,undef);
-					my $w3 = gen_check_box_object ($self,$sample,"HOTSPOT_SEND_EN_$i", 0,undef,undef);
-					$htable->attach  ($w1 , 0, 1,  $row,$row+1,'fill','shrink',2,2);
-					$htable->attach  ($w2 ,1, 2,  $row,$row+1,'fill','shrink',2,2);
-					$htable->attach  ($w3 , 2,3,  $row,$row+1,'fill','shrink',2,2);
-					$row++;
-				
-				}
-				
-				$table->attach  ($htable , 0, 3,  $row,$row+1,'shrink','shrink',2,2); $row++;
-			
-			
-			
-			
-			
-			
-		
-		}
-		my $l= "Define injection ratios. You can define individual ratios separating by comma (\',\') or define a range of injection ratios with \$min:\$max:\$step format.
-			As an example defining 2,3,4:10:2 will result in (2,3,4,6,8,10) injection ratios." ;
-		my $u=get_injection_ratios ($self,$sample,"ratios");
-		
-		attach_widget_to_table ($table,$row,gen_label_in_left(" Injection ratios:"),gen_button_message ($l,"icons/help.png") , $u); $row++;
-	
-		$ok->signal_connect("clicked"=> sub{
-			#check if sof file has been selected
-			my $s=$self->object_get_attribute($sample,"sof_file");
-			#check if injection ratios are valid
-			my $r=$self->object_get_attribute($sample,"ratios");
-			
-			my $h;
-			
-			my $t=$self->object_get_attribute($sample,"PCK_SIZ_SEL");
-			unless ($t eq 'random-range' ){
-				($avg,$msg) = get_district_avg($self,$sample);	
-				if(defined $msg){ 
-	 			message_dialog($msg);  
-	 			return;
-				}
-			}	
-			
-			if ($traffic eq 'hot spot'){
-				$h=	check_hotspot_parameters($self,$sample);
-			}
-			
-			my $v;
-			if(defined $r ){
-					$v=check_inserted_ratios($r);
-			}
-			
-			if(defined $s && defined $r && defined $v && !defined $h) {	
-					#$set_win->destroy;
-					$set_win->hide();
-					$self->object_add_attribute("active_setting",undef,undef);
-					set_gui_status($self,"ref",1);
-			} else {
-				
-				if(!defined $s){
-					my $m= "Please select NoC verilated file";
-					message_dialog($m);  
-				} elsif (! defined $r) {
-					 message_dialog("Please define valid injection ratio(s)!");
-				} elsif (defined $h){
-					 message_dialog("$h");					
-				}
-			}
-		});
-	
-	}	
-	
-	
-	if($traffictype eq "Task-graph"){
-		
-		my @custominfo = (
-		#{ label=>"Verilated Model", param_name=>'sof_file', type=>'Combo-box', default_val=>undef, content=>$exe_files, info=>"Select the verilator simulation file. Different NoC simulators can be generated using Generate NoC configuration tab.", param_parent=>$sample, ref_delay=>undef, new_status=>undef},
-		
-		{ label=>'Configuration name:', param_name=>'line_name', type=>'Entry', default_val=>$sample, content=>undef, info=>"NoC configuration name. This name will be shown in load-latency graph for this configuration", param_parent=>$sample, ref_delay=> undef, new_status=>undef},
-	
-	  	{ label=>"Number of Files", param_name=>"TRAFFIC_FILE_NUM", type=>'Spin-button', default_val=>1, content=>"1,100,1", info=>"Select number of input files", param_parent=>$sample, ref_delay=>1, new_status=>'ref_set_win'},
-		
-		{ label=>"Simulator clocks limit:", param_name=>'SIM_CLOCK_LIMIT', type=>'Spin-button', default_val=>100000, content=>"2,$max_sim_clk,1", info=>"Each node stops sending packets when it reaches packet number limit  or simulation clock number limit", param_parent=>$sample, ref_delay=>undef,  new_status=>undef},
-		);
-		
-		foreach my $d (@custominfo) {
-			($row,$coltmp)=add_param_widget ($self, $d->{label}, $d->{param_name}, $d->{default_val}, $d->{type}, $d->{content}, $d->{info}, $table,$row,undef,1, $d->{param_parent}, $d->{ref_delay}, $d->{new_status});
-			
-		}	
-		
-	
-		my $open_in  = "$ENV{'PRONOC_WORK'}/traffic_pattern";
-		
-		
-	
-		 my $num=$self->object_get_attribute($sample,"TRAFFIC_FILE_NUM");
-		 for (my $i=0; $i<$num; $i++){
-		 	attach_widget_to_table ($table,$row,gen_label_in_left("traffic pattern file $i:"),gen_button_message ("Select the traffic pattern input file. Any custom traffic based on application task graphs can be generated using ProNoC Trace Generator tool.","icons/help.png"), get_file_name_object ($self,$sample,"traffic_file$i",undef,$open_in)); $row++;
-		 }
-		 
-		
-		 
-		 
-		 
-		$ok->signal_connect("clicked"=> sub{
-			#check if sof file has been selected
-			my $s=$self->object_get_attribute($sample,"sof_file");
-			if(!defined $s){
-					message_dialog("Please select NoC verilated file"); 
-					return;
-			}
-						
-			#check if traffic files have been selected
-			for (my $i=0; $i<$num; $i++){
-				my $f=$self->object_get_attribute($sample,"traffic_file$i");
-				if(!defined $f){
-					my $m= "Please select traffic_file$i";
-					message_dialog($m); 
-					return;
-				}
-			 	
-			}
-			#$set_win->destroy;
-			$set_win->hide();
-			$self->object_add_attribute("active_setting",undef,undef);
-			set_gui_status($self,"ref",1);
-				
-		});
-		 
-		 
-	}
-	
-	
-	if($traffictype eq "SynFull"){
-		#get the synful model names
-		my $models_dir  = get_project_dir()."/mpsoc/src_c/synfull/generated-models/";		
-		my ($flist)=get_file_list_by_extention ("$models_dir",".model");
-	
-		
-		my $model_obj = gen_combobox_object ($self,$sample, "MODEL_NAME", $flist, undef,undef,undef);	
-		attach_widget_to_table ($table,$row,gen_label_in_left(" Traffic Model name:"),gen_button_message ("Select an application traffic model.","icons/help.png"), 
-		$model_obj); $row++;
-		
-		
-		
-		my @custominfo = (
-		{ label=>"Synful Flit-size:(Bytes)", param_name=>'SYNFUL_FLITw', type=>'Spin-button', default_val=>4, content=>"4,72,4", info=>"The synful flit size in Byte. It defines the number of flits that should be set to ProNoC for each synful packets. The ProNoC packet size is : 
-		\t Ceil( synful packet size/synful flit size).  ", param_parent=>$sample, ref_delay=>undef,  new_status=>undef},
-		{ label=>'Configuration name:', param_name=>'line_name', type=>'Entry', default_val=>$sample, content=>undef, info=>"NoC configuration name. This name will be shown in load-latency graph for this configuration", param_parent=>$sample, ref_delay=> undef, new_status=>undef},
-	    { label=>"Total packet number limit:", param_name=>'PCK_NUM_LIMIT', type=>'Spin-button', default_val=>200000, content=>"2,$max_pck_num,1", info=>"Simulation will stop when total number of sent packets by all nodes reaches packet number limit  or total simulation clock reach its limit", param_parent=>$sample, ref_delay=>undef, new_status=>undef},
-		{ label=>"Simulator clocks limit:", param_name=>'SIM_CLOCK_LIMIT', type=>'Spin-button', default_val=>100000, content=>"2,$max_sim_clk,1", info=>"Each node stops sending packets when it reaches packet number limit  or simulation clock number limit", param_parent=>$sample, ref_delay=>undef,  new_status=>undef},
-		{ label=>"Markov Chain Random seed:", param_name=>'RND_SEED', type=>'Spin-button', default_val=>53432145, content=>"0,999999999,1", info=>"The seed valus is passe to synfull random number generator.", param_parent=>$sample, ref_delay=>undef,  new_status=>undef},
-		{ label=>"Exit at steady state:", param_name=>'EXIT_STEADY', type=>'Check-box', default_val=>0, content=>"1", info=>"Exit the simulation when it reaches to a steady state.", param_parent=>$sample, ref_delay=>undef,  new_status=>undef},
-		
-	
-	
-		);
-		
-		
-		
-		foreach my $d (@custominfo) {
-			($row,$coltmp)=add_param_widget ($self, $d->{label}, $d->{param_name}, $d->{default_val}, $d->{type}, $d->{content}, $d->{info}, $table,$row,undef,1, $d->{param_parent}, $d->{ref_delay}, $d->{new_status});
-			
-		}	
-		
-		$ok->signal_connect("clicked"=> sub{
-			#check if sof file has been selected
-			my $s=$self->object_get_attribute($sample,"MODEL_NAME");
-			if(!defined $s){
-					message_dialog("Please select a SynFull traffic model"); 
-					return;
-			}
-						
-			
-			#$set_win->destroy;
-			$set_win->hide();
-			$self->object_add_attribute("active_setting",undef,undef);
-			set_gui_status($self,"ref",1);
-				
-		});
-		
-		
-		
-	}#SynFull
-	
-	
-	if($traffictype eq "Netrace"){
-		#get the synful model names
-		my $models_dir  = "$ENV{PRONOC_WORK}/simulate/netrace";		
-		my ($flist)=get_file_list_by_extention ("$models_dir",".bz2");
-	
-		my $model_obj = gen_combobox_object ($self,$sample, "MODEL_NAME", $flist, undef,undef,undef);	
-		my $download=def_image_button("icons/download.png",'Download');	
-		my $box =def_hbox(FALSE, 0);
-		$box->pack_start( $model_obj , 1,1, 0);
-		$box->pack_start( $download, 0, 1, 3);
-				
-		attach_widget_to_table ($table,$row,gen_label_in_left(" Trace name:"),gen_button_message ("Select a netrace trace file. You can download traces using download button.","icons/help.png"), 
-		$box); 
-		
-		
-		$row++;
-		
-		
-		
-		my @custominfo = (
-		{ label=>'Configuration name:', param_name=>'line_name', type=>'Entry', default_val=>$sample, content=>undef, info=>"NoC configuration name. This name will be shown in load-latency graph for this configuration", param_parent=>$sample, ref_delay=> undef, new_status=>undef},
-	    { label=>"Total packet number limit:", param_name=>'PCK_NUM_LIMIT', type=>'Spin-button', default_val=>200000, content=>"2,$max_pck_num,1", info=>"Simulation will stop when total number of sent packets by all nodes reaches packet number limit  or total simulation clock reach its limit", param_parent=>$sample, ref_delay=>undef, new_status=>undef},
-		#{ label=>"Simulator clocks limit:", param_name=>'SIM_CLOCK_LIMIT', type=>'Spin-button', default_val=>100000, content=>"2,$max_sim_clk,1", info=>"Each node stops sending packets when it reaches packet number limit  or simulation clock number limit", param_parent=>$sample, ref_delay=>undef,  new_status=>undef},
-		{ label=>"ignore dependencies:", param_name=>'IGNORE_DPNDCY', type=>'Check-box', default_val=>0, content=>"1", info=>"Ignore dependency between packets", param_parent=>$sample, ref_delay=>undef,  new_status=>undef},
-		{ label=>"Enable reader throttling:", param_name=>'READER_THRL', type=>'Check-box', default_val=>0, content=>"1", info=>"If Reader throttling is enabled, simulators offloads much of the work of reading and tracking packets to the Netrace reader,
+    if($traffictype eq "Netrace"){
+        #get the synful model names
+        my $models_dir  = "$ENV{PRONOC_WORK}/simulate/netrace";        
+        my ($flist)=get_file_list_by_extention ("$models_dir",".bz2");
+        my $model_obj = gen_combobox_object ($self,$sample, "MODEL_NAME", $flist, undef,undef,undef);    
+        my $download=def_image_button("icons/download.png",'Download');    
+        my $box =def_hbox(FALSE, 0);
+        $box->pack_start( $model_obj , 1,1, 0);
+        $box->pack_start( $download, 0, 1, 3);
+        attach_widget_to_table ($table,$row,gen_label_in_left(" Trace name:"),gen_button_message ("Select a netrace trace file. You can download traces using download button.","icons/help.png"), $box); 
+        $row++;
+        my @custominfo = (
+        { label=>'Configuration name:', param_name=>'line_name', type=>'Entry', default_val=>$sample, content=>undef, info=>"NoC configuration name. This name will be shown in load-latency graph for this configuration", param_parent=>$sample, ref_delay=> undef, new_status=>undef},
+        { label=>"Total packet number limit:", param_name=>'PCK_NUM_LIMIT', type=>'Spin-button', default_val=>200000, content=>"2,$max_pck_num,1", info=>"Simulation will stop when total number of sent packets by all nodes reaches packet number limit  or total simulation clock reach its limit", param_parent=>$sample, ref_delay=>undef, new_status=>undef},
+        #{ label=>"Simulator clocks limit:", param_name=>'SIM_CLOCK_LIMIT', type=>'Spin-button', default_val=>100000, content=>"2,$max_sim_clk,1", info=>"Each node stops sending packets when it reaches packet number limit  or simulation clock number limit", param_parent=>$sample, ref_delay=>undef,  new_status=>undef},
+        { label=>"ignore dependencies:", param_name=>'IGNORE_DPNDCY', type=>'Check-box', default_val=>0, content=>"1", info=>"Ignore dependency between packets", param_parent=>$sample, ref_delay=>undef,  new_status=>undef},
+        { label=>"Enable reader throttling:", param_name=>'READER_THRL', type=>'Check-box', default_val=>0, content=>"1", info=>"If Reader throttling is enabled, simulators offloads much of the work of reading and tracking packets to the Netrace reader,
 which simplifies the code in the network simulator.", param_parent=>$sample, ref_delay=>undef,  new_status=>undef},
-		{ label=>"trace file start region:", param_name=>'START_RGN', type=>'Spin-button', default_val=>0, content=>"0,10000,1", info=>undef, param_parent=>$sample, ref_delay=>undef,  new_status=>undef},
-		{ label=>"Netrace to Pronoc clk ratio:", param_name=>'SPEED_UP', type=>'Spin-button', default_val=>1, content=>"1,99,1", info=>"The ratio of netrace frequency to pronoc.The higher value results in higher injection ratio to the NoC. Default is one\n", param_parent=>$sample, ref_delay=>undef,  new_status=>undef},
-		
-		
-		
-		
-	
-	
-		);
-		
-		
-		
-		foreach my $d (@custominfo) {
-			($row,$coltmp)=add_param_widget ($self, $d->{label}, $d->{param_name}, $d->{default_val}, $d->{type}, $d->{content}, $d->{info}, $table,$row,undef,1, $d->{param_parent}, $d->{ref_delay}, $d->{new_status});
-			
-		}	
-		
-		$ok->signal_connect("clicked"=> sub{
-			#check if sof file has been selected
-			my $s=$self->object_get_attribute($sample,"MODEL_NAME");
-			if(!defined $s){
-					message_dialog("Please select a SynFull traffic model"); 
-					return;
-			}
-						
-			
-			#$set_win->destroy;
-			$set_win->hide();
-			$self->object_add_attribute("active_setting",undef,undef);
-			set_gui_status($self,"ref",1);
-				
-		});
-		
-		$download->signal_connect("clicked"=> sub{ download_netrace("$models_dir")	});
-
-
-		
-	}#netrace
-	
-	
-	
-	
-	
-	
-	add_widget_to_scrolled_win ($mtable,$set_win);
-	
-	$set_win->show_all();	
-	
-	
+        { label=>"trace file start region:", param_name=>'START_RGN', type=>'Spin-button', default_val=>0, content=>"0,10000,1", info=>undef, param_parent=>$sample, ref_delay=>undef,  new_status=>undef},
+        { label=>"Netrace to Pronoc clk ratio:", param_name=>'SPEED_UP', type=>'Spin-button', default_val=>1, content=>"1,99,1", info=>"The ratio of netrace frequency to pronoc.The higher value results in higher injection ratio to the NoC. Default is one\n", param_parent=>$sample, ref_delay=>undef,  new_status=>undef},
+        );
+        foreach my $d (@custominfo) {
+            ($row,$coltmp)=add_param_widget ($self, $d->{label}, $d->{param_name}, $d->{default_val}, $d->{type}, $d->{content}, $d->{info}, $table,$row,undef,1, $d->{param_parent}, $d->{ref_delay}, $d->{new_status});
+        }    
+        $ok->signal_connect("clicked"=> sub{
+            #check if sof file has been selected
+            my $s=$self->object_get_attribute($sample,"MODEL_NAME");
+            if(!defined $s){
+                message_dialog("Please select a SynFull traffic model"); 
+                return;
+            }
+            #$set_win->destroy;
+            $set_win->hide();
+            $self->object_add_attribute("active_setting",undef,undef);
+            set_gui_status($self,"ref",1);
+        });
+        $download->signal_connect("clicked"=> sub{ download_netrace("$models_dir")    });
+    }#netrace
+    add_widget_to_scrolled_win ($mtable,$set_win);
+    $set_win->show_all();    
 }
 
-
-
 ############
-#	run_simulator
+#    run_simulator
 ###########
-
 sub run_simulator {
-	my ($simulate,$info)=@_;
-	#return if(!check_samples($emulate,$info));
-	$simulate->object_add_attribute('status',undef,'run');
-	set_gui_status($simulate,"ref",1);
-	show_info($info, "Start Simulation\n");
-	my $name=$simulate->object_get_attribute ("simulate_name",undef);	
-	
-	#unlink $log; # remove old log file
-	
-	my @samples =$simulate->object_get_attribute_order("samples");
-	foreach my $sample (@samples){
-		my $status=$simulate->object_get_attribute ($sample,"status");	
-		next if($status ne "run");
-		next if(!check_sim_sample($simulate,$sample,$info));
-		my $traffictype=$simulate->object_get_attribute($sample,"TRAFFIC_TYPE");
-		if($traffictype eq "Synthetic") {run_synthetic_simulation($simulate,$info,$sample,$name);} 
-		elsif($traffictype eq "Task-graph"){run_task_simulation($simulate,$info,$sample,$name) ;}
-		else {run_trace_simulation($simulate,$info,$sample,$name);}
-    	
-	}
-	
-	add_info($info, "Simulation is done!\n");
-	printf "Simulation is done!\n";
-	$simulate->object_add_attribute('status',undef,'ideal');
-	set_gui_status($simulate,"ref",1);
-}	
+    my ($simulate,$info)=@_;
+    #return if(!check_samples($emulate,$info));
+    $simulate->object_add_attribute('status',undef,'run');
+    set_gui_status($simulate,"ref",1);
+    show_info($info, "Start Simulation\n");
+    my $name=$simulate->object_get_attribute ("simulate_name",undef);    
+    #unlink $log; # remove old log file
+    my @samples =$simulate->object_get_attribute_order("samples");
+    foreach my $sample (@samples){
+        my $status=$simulate->object_get_attribute ($sample,"status");    
+        next if($status ne "run");
+        next if(!check_sim_sample($simulate,$sample,$info));
+        my $traffictype=$simulate->object_get_attribute($sample,"TRAFFIC_TYPE");
+        if($traffictype eq "Synthetic") {run_synthetic_simulation($simulate,$info,$sample,$name);} 
+        elsif($traffictype eq "Task-graph"){run_task_simulation($simulate,$info,$sample,$name) ;}
+        else {run_trace_simulation($simulate,$info,$sample,$name);}
+    }
+    add_info($info, "Simulation is done!\n");
+    printf "Simulation is done!\n";
+    $simulate->object_add_attribute('status',undef,'ideal');
+    set_gui_status($simulate,"ref",1);
+}
 
 
 sub run_synthetic_simulation {
-	my ($simulate,$info,$sample,$name)=@_;
-	
-
-	my %traffic= (
-	'tornado' => 'TORNADO',
-	'transposed 1' => "TRANSPOSE1",
-	'transposed 2' => "TRANSPOSE2",
-	'bit reverse'  => "BIT_REVERSE",
-	'bit complement' => "BIT_COMPLEMENT",
-	'random' => "RANDOM",
-	'hot spot' => "HOTSPOT",
-	'shuffle' => "SHUFFLE",
-	'bit rotation' => "BIT_ROTATE",
-	'neighbor' => "NEIGHBOR",
-	'custom' => "CUSTOM"	 
-	);
-	
-	my $simulator =$simulate->object_get_attribute("Simulator");
-	my $log= (defined $name)? "$ENV{PRONOC_WORK}/simulate/$name.log": "$ENV{PRONOC_WORK}/simulate/sim.log";
-	my $out_path ="$ENV{PRONOC_WORK}/simulate/"; 
-	my $r= $simulate->object_get_attribute($sample,"ratios");
-	my @ratios=@{check_inserted_ratios($r)};
-	#$emulate->object_add_attribute ("sample$i","status","run");
-	my $bin=get_sim_bin_path($simulate,$sample,$info);
-	
-	#load traffic configuration
-	my $patern=$simulate->object_get_attribute ($sample,'traffic');	
-	my $PCK_NUM_LIMIT=$simulate->object_get_attribute ($sample,"PCK_NUM_LIMIT");
-	my $SIM_CLOCK_LIMIT=$simulate->object_get_attribute ($sample,"SIM_CLOCK_LIMIT");
-	my $MIN_PCK_SIZE=$simulate->object_get_attribute ($sample,"MIN_PCK_SIZE");
-	my $MAX_PCK_SIZE=$simulate->object_get_attribute ($sample,"MAX_PCK_SIZE");
-	
-	
-	#hotspot 
-	my $custom="";
-	my $custom_sv="";
-	if ($patern eq 'custom'){
-		$custom="";
-		my $num=$simulate->object_get_attribute($sample,"CUSTOM_SRC_NUM");
-		$custom_sv.="localparam CUSTOM_NODE_NUM=$num;\n\twire [NEw-1 : 0] custom_traffic_t   [NE-1 : 0];\n\twire [NE-1 : 0] custom_traffic_en;\n";
-			my @srcs;
-		for (my $i=0;$i<$num; $i++){
-			my $src = $simulate->object_get_attribute($sample,"SRC_$i");
-			my $dst = $simulate->object_get_attribute($sample,"DST_$i");
-			
-			$custom.=($i==0)? "-H \"$src,$dst" : ",$src,$dst";
-			
-		}
-		my ($topology, $T1, $T2, $T3, $V, $Fpay) = get_sample_emulation_param($simulate,$sample);
-		my ($NE, $NR, $RAw, $EAw, $Fw) = get_topology_info_sub ($topology, $T1, $T2, $T3, $V, $Fpay);
-			
-		for (my $i=0;$i<$NE; $i++){
-			my ($src,$dst) = custom_traffic_dest ($simulate,$sample,$i);
-			$custom_sv.="\tassign custom_traffic_t[$src]=$dst;\n";
-			$custom_sv.="\tassign custom_traffic_en[$src]=";
-			$custom_sv.=($dst==-1)? "1'b0;//off \n" : "1'b1;\n"
-		}	
-		$custom.="\"";	
-		
-	}
-	else{
-		$custom_sv.="localparam CUSTOM_NODE_NUM=0;\n\twire [NEw-1 : 0] custom_traffic_t   [NE-1 : 0];\n\twire [NE-1 : 0] custom_traffic_en;
-		";		
-	}
-	#multicast
-	my $mcast="";
-	my $mcast_sv="";
-	my $p= $simulate->object_get_attribute ($sample,"noc_info");    
+    my ($simulate,$info,$sample,$name)=@_;
+    my %traffic= (
+    'tornado' => 'TORNADO',
+    'transposed 1' => "TRANSPOSE1",
+    'transposed 2' => "TRANSPOSE2",
+    'bit reverse'  => "BIT_REVERSE",
+    'bit complement' => "BIT_COMPLEMENT",
+    'random' => "RANDOM",
+    'hot spot' => "HOTSPOT",
+    'shuffle' => "SHUFFLE",
+    'bit rotation' => "BIT_ROTATE",
+    'neighbor' => "NEIGHBOR",
+    'custom' => "CUSTOM"
+    );
+    
+    my $simulator =$simulate->object_get_attribute("Simulator");
+    my $log= (defined $name)? "$ENV{PRONOC_WORK}/simulate/$name.log": "$ENV{PRONOC_WORK}/simulate/sim.log";
+    my $out_path ="$ENV{PRONOC_WORK}/simulate/"; 
+    my $r= $simulate->object_get_attribute($sample,"ratios");
+    my @ratios=@{check_inserted_ratios($r)};
+    #$emulate->object_add_attribute ("sample$i","status","run");
+    my $bin=get_sim_bin_path($simulate,$sample,$info);
+    #load traffic configuration
+    my $patern=$simulate->object_get_attribute ($sample,'traffic');    
+    my $PCK_NUM_LIMIT=$simulate->object_get_attribute ($sample,"PCK_NUM_LIMIT");
+    my $SIM_CLOCK_LIMIT=$simulate->object_get_attribute ($sample,"SIM_CLOCK_LIMIT");
+    my $MIN_PCK_SIZE=$simulate->object_get_attribute ($sample,"MIN_PCK_SIZE");
+    my $MAX_PCK_SIZE=$simulate->object_get_attribute ($sample,"MAX_PCK_SIZE");
+    #hotspot 
+    my $custom="";
+    my $custom_sv="";
+    if ($patern eq 'custom'){
+        $custom="";
+        my $num=$simulate->object_get_attribute($sample,"CUSTOM_SRC_NUM");
+        $custom_sv.="localparam CUSTOM_NODE_NUM=$num;\n\twire [NEw-1 : 0] custom_traffic_t   [NE-1 : 0];\n\twire [NE-1 : 0] custom_traffic_en;\n";
+            my @srcs;
+        for (my $i=0;$i<$num; $i++){
+            my $src = $simulate->object_get_attribute($sample,"SRC_$i");
+            my $dst = $simulate->object_get_attribute($sample,"DST_$i");
+            $custom.=($i==0)? "-H \"$src,$dst" : ",$src,$dst";
+        }
+        my ($NE, $NR, $RAw, $EAw, $Fw) = get_sample_topology_info ($simulate,$sample);
+        for (my $i=0;$i<$NE; $i++){
+            my ($src,$dst) = custom_traffic_dest ($simulate,$sample,$i);
+            $custom_sv.="\tassign custom_traffic_t[$src]=$dst;\n";
+            $custom_sv.="\tassign custom_traffic_en[$src]=";
+            $custom_sv.=($dst==-1)? "1'b0;//off \n" : "1'b1;\n"
+        }    
+        $custom.="\"";    
+    }
+    else{
+        $custom_sv.="localparam CUSTOM_NODE_NUM=0;\n\twire [NEw-1 : 0] custom_traffic_t   [NE-1 : 0];\n\twire [NE-1 : 0] custom_traffic_en;
+        ";
+    }
+    #multicast
+    my $mcast="";
+    my $mcast_sv="";
+    my $p= $simulate->object_get_attribute ($sample,"noc_info");    
     my $cast_type=$p->{"CAST_TYPE"};
-	if ($cast_type ne '"UNICAST"'){	
-		#$self->object_get_attribute ($sample,  "MCAST_TRAFFIC_TYPE");
-		my $mr   = $simulate->object_get_attribute  ($sample,  "MCAST_TRAFFIC_RATIO");
-		my $mmax = $simulate->object_get_attribute  ($sample,  "MCAST_PCK_SIZ_MAX");
-		my $mmin = $simulate->object_get_attribute  ($sample,  "MCAST_PCK_SIZ_MIN");
-		
-		$mcast = "-u \"$mr,$mmin,$mmax\"";
-		$mcast_sv.= "localparam	MCAST_TRAFFIC_RATIO =	$mr;\n";
-		$mcast_sv.= "localparam	MCAST_PCK_SIZ_MAX =	$mmax;\n";
-		$mcast_sv.= "localparam	MCAST_PCK_SIZ_MIN =	$mmin;\n";	
-	}else {
-		$mcast_sv.= "localparam	MCAST_TRAFFIC_RATIO =	0;\n";	
-		$mcast_sv.= "localparam	MCAST_PCK_SIZ_MAX =	0;\n";
-		$mcast_sv.= "localparam	MCAST_PCK_SIZ_MIN =	0;\n";	
-	}
-	
-	
-	
-	
-	
-	my $classes;
-	my $num=$simulate->object_get_attribute($sample,"MESSAGE_CLASS");
-	$classes.="-p 100" if($num==0);
-	for (my $i=0;$i<$num;$i++){
-		my $w1 = $simulate->object_get_attribute($sample,"CLASS_$i");
-		$classes.= ($i==0)?  "-p $w1" : ",$w1" ;		
-	
-	}
-	
-	my $discrete_sv="";
-	my $hotspot="";
-	my $hotspot_sv="";
-	if($patern eq "hot spot"){
-		$hotspot="-h \" ";
-		my $num=$simulate->object_get_attribute($sample,"HOTSPOT_NUM");
-		if (defined $num){
-			$hotspot.=" $num";
-			
-			$hotspot_sv.="localparam HOTSPOT_NODE_NUM=$num;\n\thotspot_t  hotspot_info [HOTSPOT_NODE_NUM-1 : 0];\n";
-			my $acum=0;
-			
-			for (my $i=0;$i<$num;$i++){
-				my $w1 = $simulate->object_get_attribute($sample,"HOTSPOT_CORE_$i");
-				my $w2 = $simulate->object_get_attribute($sample,"HOTSPOT_PERCENT_$i");
-				$w2=$w2*10;
-				my $w3 = $simulate->object_get_attribute($sample,"HOTSPOT_SEND_EN_$i");
-				$hotspot.=",$w1,$w3,$w2";
-				$acum+=$w2;
-				
-				$hotspot_sv.="
-	assign  hotspot_info[$i].ip_num=$w1;
-	assign  hotspot_info[$i].send_enable=$w3;
-	assign  hotspot_info[$i].percentage=$acum;	// $w2
-";			}
-			
-		}
-		
-		$hotspot.=" \"";
-				
-	}
-	else{ $hotspot_sv.="localparam HOTSPOT_NODE_NUM = 0;\n\thotspot_t  hotspot_info [0:0];\n" }		
-	
-	my $pck_size;
-	my $t=$simulate->object_get_attribute($sample,"PCK_SIZ_SEL");
-	if($t eq 'random-range' ){
-		
-		$pck_size = "-m \"R,$MIN_PCK_SIZE,$MAX_PCK_SIZE\"";
-		$discrete_sv="\t localparam DISCRETE_PCK_SIZ_NUM=1;
+    if ($cast_type ne '"UNICAST"'){    
+        #$self->object_get_attribute ($sample,  "MCAST_TRAFFIC_TYPE");
+        my $mr   = $simulate->object_get_attribute  ($sample,  "MCAST_TRAFFIC_RATIO");
+        my $mmax = $simulate->object_get_attribute  ($sample,  "MCAST_PCK_SIZ_MAX");
+        my $mmin = $simulate->object_get_attribute  ($sample,  "MCAST_PCK_SIZ_MIN");
+        $mcast = "-u \"$mr,$mmin,$mmax\"";
+        $mcast_sv.= "localparam    MCAST_TRAFFIC_RATIO =    $mr;\n";
+        $mcast_sv.= "localparam    MCAST_PCK_SIZ_MAX =    $mmax;\n";
+        $mcast_sv.= "localparam    MCAST_PCK_SIZ_MIN =    $mmin;\n";    
+    }else {
+        $mcast_sv.= "localparam    MCAST_TRAFFIC_RATIO =    0;\n";    
+        $mcast_sv.= "localparam    MCAST_PCK_SIZ_MAX =    0;\n";
+        $mcast_sv.= "localparam    MCAST_PCK_SIZ_MIN =    0;\n";    
+    }
+    my $classes;
+    my $num=$simulate->object_get_attribute($sample,"MESSAGE_CLASS");
+    $classes.="-p 100" if($num==0);
+    for (my $i=0;$i<$num;$i++){
+        my $w1 = $simulate->object_get_attribute($sample,"CLASS_$i");
+        $classes.= ($i==0)?  "-p $w1" : ",$w1" ;        
+    }
+    my $discrete_sv="";
+    my $hotspot="";
+    my $hotspot_sv="";
+    if($patern eq "hot spot"){
+        $hotspot="-h \" ";
+        my $num=$simulate->object_get_attribute($sample,"HOTSPOT_NUM");
+        if (defined $num){
+            $hotspot.=" $num";
+            $hotspot_sv.="localparam HOTSPOT_NODE_NUM=$num;\n\thotspot_t  hotspot_info [HOTSPOT_NODE_NUM-1 : 0];\n";
+            my $acum=0;
+            for (my $i=0;$i<$num;$i++){
+                my $w1 = $simulate->object_get_attribute($sample,"HOTSPOT_CORE_$i");
+                my $w2 = $simulate->object_get_attribute($sample,"HOTSPOT_PERCENT_$i");
+                $w2=$w2*10;
+                my $w3 = $simulate->object_get_attribute($sample,"HOTSPOT_SEND_EN_$i");
+                $hotspot.=",$w1,$w3,$w2";
+                $acum+=$w2;
+                $hotspot_sv.="
+    assign  hotspot_info[$i].ip_num=$w1;
+    assign  hotspot_info[$i].send_enable=$w3;
+    assign  hotspot_info[$i].percentage=$acum;    // $w2\n";
+            }
+        }
+        $hotspot.=" \"";
+    }
+    else{ $hotspot_sv.="localparam HOTSPOT_NODE_NUM = 0;\n\thotspot_t  hotspot_info [0:0];\n" }        
+    my $pck_size;
+    my $t=$simulate->object_get_attribute($sample,"PCK_SIZ_SEL");
+    if($t eq 'random-range' ){
+        $pck_size = "-m \"R,$MIN_PCK_SIZE,$MAX_PCK_SIZE\"";
+        $discrete_sv="\t localparam DISCRETE_PCK_SIZ_NUM=1;
 \t rnd_discrete_t rnd_discrete [DISCRETE_PCK_SIZ_NUM-1:0];\n";
-	
-	}else{
-		my $vt=$simulate->object_get_attribute($sample,"DISCRETE_RANGE");
-		my $pt=$simulate->object_get_attribute($sample,"PROBEB_RANGE");
-		$pck_size = "-m \"D,$vt,P,$pt\"";		
-		my @injects = split(',',$vt);
-		my @probs = split(',',$pt);
-		my $i=0;
-		my $sum=0;
-		for my $v (@injects) {
-			$sum+=$probs[$i];
-			$discrete_sv.= "\t assign rnd_discrete[$i].value= $v;\n";
-			$discrete_sv.= "\t assign rnd_discrete[$i].percentage= $sum;\n";
-			$i++;
-		}
-		$discrete_sv="\t localparam DISCRETE_PCK_SIZ_NUM=$i;
+    }else{
+        my $vt=$simulate->object_get_attribute($sample,"DISCRETE_RANGE");
+        my $pt=$simulate->object_get_attribute($sample,"PROBEB_RANGE");
+        $pck_size = "-m \"D,$vt,P,$pt\"";        
+        my @injects = split(',',$vt);
+        my @probs = split(',',$pt);
+        my $i=0;
+        my $sum=0;
+        for my $v (@injects) {
+            $sum+=$probs[$i];
+            $discrete_sv.= "\t assign rnd_discrete[$i].value= $v;\n";
+            $discrete_sv.= "\t assign rnd_discrete[$i].percentage= $sum;\n";
+            $i++;
+        }
+        $discrete_sv="\t localparam DISCRETE_PCK_SIZ_NUM=$i;
 \t rnd_discrete_t rnd_discrete [DISCRETE_PCK_SIZ_NUM-1: 0];\n".$discrete_sv;
-	}
-	
-	my $modelsim_bin=  $ENV{MODELSIM_BIN};
-	my $vsim = (! defined $modelsim_bin)? "vsim" : "$modelsim_bin/vsim";
-	
-	
-			
-		
-	my $cpu_num = $simulate->object_get_attribute('compile', 'cpu_num');
-	$cpu_num = 1 if (!defined $cpu_num);
-	
-	my $thread_num = $simulate->object_get_attribute('compile', 'thread_num');
-	$thread_num = 1 if (!defined $thread_num);
-	
-	if ($simulator ne 'Verilator'){
-		for (my $i=0; $i<$cpu_num; $i++  ){
-			my $out="$out_path/modelsim/work$i";
-			rmtree("$out");
-			mkpath("$out",1,01777);
-	my $vsim = ($simulator eq 'Modelsim')? "vsim -c": "vsim";					
-			gen_noc_localparam_v_file($simulate,"$out",$sample);
-			my $param="
+    }
+    my $modelsim_bin=  $ENV{MODELSIM_BIN};
+    my $vsim = (! defined $modelsim_bin)? "vsim" : "$modelsim_bin/vsim";
+    my $cpu_num = $simulate->object_get_attribute('compile', 'cpu_num');
+    $cpu_num = 1 if (!defined $cpu_num);
+    my $thread_num = $simulate->object_get_attribute('compile', 'thread_num');
+    $thread_num = 1 if (!defined $thread_num);
+    if ($simulator ne 'Verilator'){
+        for (my $i=0; $i<$cpu_num; $i++  ){
+            my $out="$out_path/modelsim/work$i";
+            rmtree("$out");
+            mkpath("$out",1,01777);
+    my $vsim = ($simulator eq 'Modelsim')? "vsim -c": "vsim";                    
+            gen_noc_localparam_v_file($simulate,"$out",$sample);
+            my $param="
 // simulation parameter setting
 
 `ifdef INCLUDE_SIM_PARAM
-	localparam 
-		TRAFFIC=\"$traffic{$patern}\",
-		PCK_SIZ_SEL=\"$t\",	
-	  	AVG_LATENCY_METRIC= \"HEAD_2_TAIL\",
-		//simulation min and max packet size. The injected packet take a size randomly selected between min and max value
-		MIN_PACKET_SIZE=$MIN_PCK_SIZE,
-		MAX_PACKET_SIZE=$MAX_PCK_SIZE,
-		STOP_PCK_NUM=$PCK_NUM_LIMIT,
-		STOP_SIM_CLK=$SIM_CLOCK_LIMIT;
-	
-	    		
-	$hotspot_sv	
-		
-	$custom_sv
-	
-	$mcast_sv
-	
+    localparam 
+        TRAFFIC=\"$traffic{$patern}\",
+        PCK_SIZ_SEL=\"$t\",    
+        AVG_LATENCY_METRIC= \"HEAD_2_TAIL\",
+        //simulation min and max packet size. The injected packet take a size randomly selected between min and max value
+        MIN_PACKET_SIZE=$MIN_PCK_SIZE,
+        MAX_PACKET_SIZE=$MAX_PCK_SIZE,
+        STOP_PCK_NUM=$PCK_NUM_LIMIT,
+        STOP_SIM_CLK=$SIM_CLOCK_LIMIT;
+        
+    $hotspot_sv    
+        
+    $custom_sv
+    
+    $mcast_sv
+    
 $discrete_sv
-		
-		parameter INJRATIO=90; 
-`endif			
-			";
-			save_file("$out/sim_param.sv",$param);
-			
-			
-			#Get the list of  all verilog files in src_verilog folder
-			my @files = File::Find::Rule->file()
-			->name( '*.v','*.V','*.sv' )
-			->in( "$out_path/modelsim/src_verilog" );
-		
-			#get list of all verilog files in src_sim folder 
-    		my @sim_files = File::Find::Rule->file()
-			->name( '*.v','*.V','*.sv' )
-			->in( "$out_path/modelsim/src_modelsim" );		
-			push (@files, @sim_files);	
-			my $tt =create_file_list("$out_path/modelsim",\@files,'modelsim');
-			$tt="+incdir+./ \n$tt";	
-			save_file("$out/file_list.f",  "$tt");
-			my $tcl="#!/usr/bin/tclsh
-
+        
+        parameter INJRATIO=90; 
+`endif
+            ";
+            save_file("$out/sim_param.sv",$param);
+            #Get the list of  all verilog files in src_verilog folder
+            my @files = File::Find::Rule->file()
+            ->name( '*.v','*.V','*.sv' )
+            ->in( "$out_path/modelsim/src_verilog" );
+            #get list of all verilog files in src_sim folder 
+            my @sim_files = File::Find::Rule->file()
+            ->name( '*.v','*.V','*.sv' )
+            ->in( "$out_path/modelsim/src_modelsim" );        
+            push (@files, @sim_files);    
+            my $tt =create_file_list("$out_path/modelsim",\@files,'modelsim');
+            $tt="+incdir+./ \n$tt";    
+            save_file("$out/file_list.f",  "$tt");
+            my $tcl="#!/usr/bin/tclsh
 
 transcript on
 if {[file exists rtl_work]} {
-	vdel -lib rtl_work -all
+    vdel -lib rtl_work -all
 }
 vlib rtl_work
 vmap work rtl_work
@@ -1240,755 +907,538 @@ sub run_synthetic_simulation {
 run -all
 quit
 ";
-	
-			save_file ("$out/model.tcl",$tcl);
-			
-			my $cmd="cd $out; rm -Rf rtl_work; $vsim -do $out/model.tcl ";
-			save_file ("$out/run.sh",'#!/bin/bash'."			
-			sed -i \"s/ INJRATIO=\[\[:digit:\]\]\\+/ INJRATIO=\$1/\" $out/sim_param.sv
-			".$cmd);			
-			add_info($info, "model.tcl is created in $out\n");
-		}#for		
-	}
-	
-	
-	
-	my @paralel_ratio;
-	my $total=scalar @ratios;
-	my $jobs=0;	
-	my $c=0;
-	my $cmds="";
-	
-	
-	foreach  my $ratio_in (@ratios){						
-	    	#my $r= $ratio_in * MAX_RATIO/100;
-	    	my $cmd;
-	    	
-	    	if ($simulator eq 'Modelsim'){
-	    		add_info($info, "Run $bin with  injection ratio of $ratio_in \% \n");
-	    		my $out="$out_path/modelsim/work$c";
-	    		$cmd="	xterm -e bash -c '	cd $out; sed -i \"s/ INJRATIO=\[\[:digit:\]\]\\+/ INJRATIO=$ratio_in/\" $out/sim_param.sv; rm -Rf rtl_work; $vsim -c -do $out/model.tcl -l $out_path/sim_out$ratio_in;' &\n	";			
-	    	
-	    	}elsif ($simulator eq 'Modelsim gui'){
-	    		add_info($info, "Run $bin with  injection ratio of $ratio_in \% \n");
-	    		my $out="$out_path/modelsim/work$c";
-	    		$cmd="cd $out; sed -i \"s/ INJRATIO=\[\[:digit:\]\]\\+/ INJRATIO=$ratio_in/\" $out/sim_param.sv;  rm -Rf rtl_work; $vsim -do $out/model.tcl -l $out_path/sim_out$ratio_in;	";			
-	    	
-	    	}else{	
-	    		add_info($info, "Run $bin with  injection ratio of $ratio_in \% \n");
-		    	$cmd="$bin -t \"$patern\" $pck_size -T $thread_num -n $PCK_NUM_LIMIT -c $SIM_CLOCK_LIMIT -i $ratio_in $classes $hotspot $custom $mcast > $out_path/sim_out$ratio_in & ";
-							
-	    	}
-	    	$cmds .=$cmd;	
-			add_info($info, "$cmd \n");
-			
-			my $time_strg = localtime;
-			#append_text_to_file($log,"started at:$time_strg\n"); #save simulation output
-			$jobs++;
-			
-			push (@paralel_ratio,$ratio_in);
-			$c++;
-			if($jobs % $cpu_num ==0 || $jobs == $total){
-				
-				#run paralle simulation				
-					my ($stdout,$exit,$stderr)=run_cmd_in_back_ground_get_stdout("$cmds\n wait\n");
-					if($exit || (length $stderr >4)){
-							add_colored_info($info, "Error in running simulation: $stderr \n",'red');
-							$simulate->object_add_attribute ($sample,"status","failed");	
-							$simulate->object_add_attribute('status',undef,'ideal');
-							return;
-					 } 
-				
-				#save results
-				for (my $i=0; $i<$c; $i++){
-					my $r      = $paralel_ratio[$i];
-					
-					my @errors = unix_grep("$out_path/sim_out$r","ERROR:");
-					if (scalar @errors  ){
-						add_colored_info($info, "Error in running simulation: @errors \n",'red');
-						$simulate->object_add_attribute ($sample,"status","failed");	
-						$simulate->object_add_attribute('status',undef,'ideal');
-						return;						
-					}		
-					
-					
-					my $stdout = load_file("$out_path/sim_out$r");
-							
-					extract_and_update_noc_sim_statistic ($simulate,$sample,$r,$stdout);
-					    
-		   
-				} 
-				
-				$cmds="";
-				@paralel_ratio=();
-				$c=0;
-				
-				set_gui_status($simulate,"ref",2);
-			}  	
-	    		    	
-		}#@ratios	
-		
-		$simulate->object_add_attribute ($sample,"status","done");	
-	
+            save_file ("$out/model.tcl",$tcl);
+            my $cmd="cd $out; rm -Rf rtl_work; $vsim -do $out/model.tcl ";
+            save_file ("$out/run.sh",'#!/bin/bash'."            
+            sed -i \"s/ INJRATIO=\[\[:digit:\]\]\\+/ INJRATIO=\$1/\" $out/sim_param.sv
+            ".$cmd);            
+            add_info($info, "model.tcl is created in $out\n");
+        }#for        
+    }
+    my @paralel_ratio;
+    my $total=scalar @ratios;
+    my $jobs=0;    
+    my $c=0;
+    my $cmds="";
+    foreach  my $ratio_in (@ratios){                        
+        #my $r= $ratio_in * MAX_RATIO/100;
+        my $cmd;
+        if ($simulator eq 'Modelsim'){
+            add_info($info, "Run $bin with  injection ratio of $ratio_in \% \n");
+            my $out="$out_path/modelsim/work$c";
+            $cmd="    xterm -e bash -c '    cd $out; sed -i \"s/ INJRATIO=\[\[:digit:\]\]\\+/ INJRATIO=$ratio_in/\" $out/sim_param.sv; rm -Rf rtl_work; $vsim -c -do $out/model.tcl -l $out_path/sim_out$ratio_in;' &\n    ";            
+        }elsif ($simulator eq 'Modelsim gui'){
+            add_info($info, "Run $bin with  injection ratio of $ratio_in \% \n");
+            my $out="$out_path/modelsim/work$c";
+            $cmd="cd $out; sed -i \"s/ INJRATIO=\[\[:digit:\]\]\\+/ INJRATIO=$ratio_in/\" $out/sim_param.sv;  rm -Rf rtl_work; $vsim -do $out/model.tcl -l $out_path/sim_out$ratio_in;    ";            
+        }else{    
+            add_info($info, "Run $bin with  injection ratio of $ratio_in \% \n");
+            $cmd="$bin -t \"$patern\" $pck_size -T $thread_num -n $PCK_NUM_LIMIT -c $SIM_CLOCK_LIMIT -i $ratio_in $classes $hotspot $custom $mcast > $out_path/sim_out$ratio_in & ";
+        }
+        $cmds .=$cmd;    
+        add_info($info, "$cmd \n");
+        my $time_strg = localtime;
+        #append_text_to_file($log,"started at:$time_strg\n"); #save simulation output
+        $jobs++;
+        push (@paralel_ratio,$ratio_in);
+        $c++;
+        if($jobs % $cpu_num ==0 || $jobs == $total){
+            #run paralle simulation                
+                my ($stdout,$exit,$stderr)=run_cmd_in_back_ground_get_stdout("$cmds\n wait\n");
+                if($exit || (length $stderr >4)){
+                    add_colored_info($info, "Error in running simulation: $stderr \n",'red');
+                    $simulate->object_add_attribute ($sample,"status","failed");    
+                    $simulate->object_add_attribute('status',undef,'ideal');
+                    return;
+                } 
+            #save results
+            for (my $i=0; $i<$c; $i++){
+                my $r  = $paralel_ratio[$i];
+                my @errors = unix_grep("$out_path/sim_out$r","ERROR:");
+                if (scalar @errors  ){
+                    add_colored_info($info, "Error in running simulation:\n @errors \n",'red');
+                    $simulate->object_add_attribute ($sample,"status","failed");    
+                    $simulate->object_add_attribute('status',undef,'ideal');
+                    return;
+                }
+                my $stdout = load_file("$out_path/sim_out$r");
+                extract_and_update_noc_sim_statistic ($simulate,$sample,$r,$stdout);
+            } 
+            $cmds="";
+            @paralel_ratio=();
+            $c=0;
+            set_gui_status($simulate,"ref",2);
+        }
+    }#@ratios
+    $simulate->object_add_attribute ($sample,"status","done");    
 }
 
-
 sub extract_st_by_name{
-	my($st_name, $stdout)=@_;
-	
-	my @results = split($st_name,$stdout);
-	my %statistcs;
-	my @lines = split("\n",$results[1]);	
-	my @names;
-	my $i=0;
-	foreach my $line (@lines){
-		$line=remove_all_white_spaces($line);
-		$line =~ s/^#//g; #remove # from beginig of each line in modelsim 
-		if($i==0) {
-			$i++;
-			next;
-		}
-		elsif($i==1){
-			#first line is statsitic names
-			@names=split(",",$line);
-			$i++;
-			next;
-		}elsif(length($line)>1) {
-			my @fileds=split(",",$line);
-			my $j=0;
-			#print ("ff :@fileds\n");
-			foreach my $f (@fileds){				
-				unless($j==0){
-					$statistcs{$fileds[0]}{$names[$j]}=$f;	
-				}
-				$j++;
-			}
-			$i++;
-		}else{ #empty line end of endp statistic
-			last;
-		}
-		
-	}
-	#print Dumper(\%statistcs);
-	return  %statistcs;	
+    my($st_name, $stdout)=@_;    
+    my @results = split($st_name,$stdout);
+    my %statistcs;
+    if (!defined $results[1]){
+        print " Warning: was not able to capture $st_name results in simulation output\n";
+    }
+    my @lines = split("\n",$results[1]);    
+    my @names;
+    my $i=0;
+    foreach my $line (@lines){
+        $line=remove_all_white_spaces($line);
+        $line =~ s/^#//g; #remove # from beginig of each line in modelsim 
+        if($i==0) {
+            $i++;
+            next;
+        }
+        elsif($i==1){
+            #first line is statsitic names
+            @names=split(",",$line);
+            $i++;
+            next;
+        }elsif(length($line)>1) {
+            my @fileds=split(",",$line);
+            my $j=0;
+            #print ("ff :@fileds\n");
+            foreach my $f (@fileds){                
+                unless($j==0){
+                    $statistcs{$fileds[0]}{$names[$j]}=$f;    
+                }
+                $j++;
+            }
+            $i++;
+        }else{ #empty line end of endp statistic
+            last;
+        }
+        
+    }
+    #print Dumper(\%statistcs);
+    return  %statistcs;
 }
 
 
-
 sub extract_and_update_noc_sim_statistic {
-	my ($simulate,$sample,$ratio_in,$stdout)=@_;
-		
-	
-	
-	my $total_time =capture_number_after("Simulation clock cycles:",$stdout);
-
-	my %statistcs = extract_st_by_name("Endpoints Statistics:",$stdout);
-			
-	return if (!defined $statistcs{"total"}{'avg_latency_pck'});
-	update_result($simulate,$sample,"latency_result",$ratio_in,$statistcs{"total"}{'avg_latency_pck'});
-	update_result($simulate,$sample,"latency_flit_result",$ratio_in,$statistcs{"total"}{'avg_latency_flit'});
-	update_result($simulate,$sample,"sd_latency_result",$ratio_in,$statistcs{"total"}{'avg.std_dev'});
-	update_result($simulate,$sample,"throughput_result",$ratio_in,$statistcs{"total"}{'avg_throughput(%)'});
-	update_result($simulate,$sample,"exe_time_result",$ratio_in,$total_time);
-	update_result($simulate,$sample,"worst_latency_result",$ratio_in,$statistcs{"total"}{'sent_stat.worst_latency'});
-	update_result($simulate,$sample,"latency_perhop_result",$ratio_in,$statistcs{"total"}{'avg_latency_per_hop'});
-	update_result($simulate,$sample,"min_latency_result",,$ratio_in,$statistcs{"total"}{'sent_stat.min_latency'});
-	update_result($simulate,$sample,"injected_pck_total",,$ratio_in,$statistcs{"total"}{'sent_stat.pck_num'});
-	update_result($simulate,$sample,"injected_flit_total",,$ratio_in,$statistcs{"total"}{'sent_stat.flit_num'});
-	foreach my $p (sort keys %statistcs){
-		next unless (is_integer($p));
-		update_result($simulate,$sample,"packet_rsvd_result",$ratio_in,$p,$statistcs{$p}{'rsvd_stat.pck_num'});
-		update_result($simulate,$sample,"worst_delay_rsvd_result",$ratio_in,$p,$statistcs{$p}{'rsvd_stat.worst_latency'});
-		update_result($simulate,$sample,"packet_sent_result",$ratio_in,$p,$statistcs{$p}{'sent_stat.pck_num'} );
-		update_result($simulate,$sample,"worst_delay_sent_result",$ratio_in,$p,$statistcs{$p}{'sent_stat.worst_latency'});
-		update_result($simulate,$sample,"flit_rsvd_result",$ratio_in,$p,$statistcs{$p}{'rsvd_stat.flit_num'});
-		update_result($simulate,$sample,"flit_sent_result",$ratio_in,$p,$statistcs{$p}{'sent_stat.flit_num'});
-	}	
-	
-	my %st1 = extract_st_by_name("Endp_to_Endp flit_num:",$stdout);
-	update_result($simulate,$sample,"endp-endp-flit_result",$ratio_in,\%st1);
-	
-	my %st2 = extract_st_by_name("Endp_to_Endp pck_num:",$stdout);
-	update_result($simulate,$sample,"endp-endp-pck_result",$ratio_in,\%st2);
-	
-	my %st3 = extract_st_by_name("Routers' statistics:",$stdout);
-	foreach my $p (sort keys %st3){
-		update_result($simulate,$sample,"flit_per_router_result",$ratio_in,$p,$st3{$p}{'flit_in'});
-		update_result($simulate,$sample,"packet_per_router_result",$ratio_in,$p,$st3{$p}{'pck_in'});
-		my $tmp= ($st3{$p}{'flit_in'}==0)? 0 : ($st3{$p}{'flit_in_buffered'}*100) / $st3{$p}{'flit_in'};
-		#print " $tmp= ($st3{$p}{'flit_in_buffered'}*100) / $st3{$p}{'flit_in'};\n";
-		update_result($simulate,$sample,"flit_buffered_router_ratio",$ratio_in,$p,$tmp);
-		$tmp= ($st3{$p}{'flit_in'}==0)? 0 : ($st3{$p}{'flit_in_bypassed'}*100) / $st3{$p}{'flit_in'};
-		update_result($simulate,$sample,"flit_bypass_router_ratio",$ratio_in,$p,$tmp);
-		
-	}
-	
-	#my $p= $simulate->object_get_attribute ($sample,"noc_info");    
-   # my $TOPOLOGY=$p->{"TOPOLOGY"};
-	#print "$TOPOLOGY\n";
-	
-	
+    my ($simulate,$sample,$ratio_in,$stdout)=@_;    
+    my $total_time =capture_number_after("Simulation clock cycles:",$stdout);
+    my %statistcs = extract_st_by_name("Endpoints Statistics:",$stdout);
+    return if (!defined $statistcs{"total"}{'avg_latency_pck'});
+    update_result($simulate,$sample,"latency_result",$ratio_in,$statistcs{"total"}{'avg_latency_pck'});
+    update_result($simulate,$sample,"latency_flit_result",$ratio_in,$statistcs{"total"}{'avg_latency_flit'});
+    update_result($simulate,$sample,"sd_latency_result",$ratio_in,$statistcs{"total"}{'avg.std_dev'});
+    update_result($simulate,$sample,"throughput_result",$ratio_in,$statistcs{"total"}{'avg_throughput(%)'});
+    update_result($simulate,$sample,"exe_time_result",$ratio_in,$total_time);
+    update_result($simulate,$sample,"worst_latency_result",$ratio_in,$statistcs{"total"}{'sent_stat.worst_latency'});
+    update_result($simulate,$sample,"latency_perhop_result",$ratio_in,$statistcs{"total"}{'avg_latency_per_hop'});
+    update_result($simulate,$sample,"min_latency_result",,$ratio_in,$statistcs{"total"}{'sent_stat.min_latency'});
+    update_result($simulate,$sample,"injected_pck_total",,$ratio_in,$statistcs{"total"}{'sent_stat.pck_num'});
+    update_result($simulate,$sample,"injected_flit_total",,$ratio_in,$statistcs{"total"}{'sent_stat.flit_num'});
+    foreach my $p (sort keys %statistcs){
+        next unless (is_integer($p));
+        update_result($simulate,$sample,"packet_rsvd_result",$ratio_in,$p,$statistcs{$p}{'rsvd_stat.pck_num'});
+        update_result($simulate,$sample,"worst_delay_rsvd_result",$ratio_in,$p,$statistcs{$p}{'rsvd_stat.worst_latency'});
+        update_result($simulate,$sample,"packet_sent_result",$ratio_in,$p,$statistcs{$p}{'sent_stat.pck_num'} );
+        update_result($simulate,$sample,"worst_delay_sent_result",$ratio_in,$p,$statistcs{$p}{'sent_stat.worst_latency'});
+        update_result($simulate,$sample,"flit_rsvd_result",$ratio_in,$p,$statistcs{$p}{'rsvd_stat.flit_num'});
+        update_result($simulate,$sample,"flit_sent_result",$ratio_in,$p,$statistcs{$p}{'sent_stat.flit_num'});
+    }
+    my %st1 = extract_st_by_name("Endp_to_Endp flit_num:",$stdout);
+    update_result($simulate,$sample,"endp-endp-flit_result",$ratio_in,\%st1);
+    my %st2 = extract_st_by_name("Endp_to_Endp pck_num:",$stdout);
+    update_result($simulate,$sample,"endp-endp-pck_result",$ratio_in,\%st2);
+    my %st3 = extract_st_by_name("Routers Statistics:",$stdout);
+    foreach my $p (sort keys %st3){
+        update_result($simulate,$sample,"flit_per_router_result",$ratio_in,$p,$st3{$p}{'flit_in'});
+        update_result($simulate,$sample,"packet_per_router_result",$ratio_in,$p,$st3{$p}{'pck_in'});
+        my $tmp= ($st3{$p}{'flit_in'}==0)? 0 : ($st3{$p}{'flit_in_buffered'}*100) / $st3{$p}{'flit_in'};
+        #print " $tmp= ($st3{$p}{'flit_in_buffered'}*100) / $st3{$p}{'flit_in'};\n";
+        update_result($simulate,$sample,"flit_buffered_router_ratio",$ratio_in,$p,$tmp);
+        $tmp= ($st3{$p}{'flit_in'}==0)? 0 : ($st3{$p}{'flit_in_bypassed'}*100) / $st3{$p}{'flit_in'};
+        update_result($simulate,$sample,"flit_bypass_router_ratio",$ratio_in,$p,$tmp);
+    }
+    #my $p= $simulate->object_get_attribute ($sample,"noc_info");    
+    # my $TOPOLOGY=$p->{"TOPOLOGY"};
+    #print "$TOPOLOGY\n";
 }
 
 
 sub run_task_simulation{
-	my ($simulate,$info,$sample,$name)=@_;
-	my $log= (defined $name)? "$ENV{PRONOC_WORK}/simulate/$name.log": "$ENV{PRONOC_WORK}/simulate/sim.log";
-	my $SIM_CLOCK_LIMIT=$simulate->object_get_attribute ($sample,"SIM_CLOCK_LIMIT");
-	
-	my $bin=get_sim_bin_path($simulate,$sample,$info);
-	
-	my $dir = Cwd::getcwd();
-	my $project_dir	  = abs_path("$dir/../.."); #mpsoc directory address
-	$bin= "$project_dir/$bin"   if(!(-f $bin));
-	my $num=$simulate->object_get_attribute($sample,"TRAFFIC_FILE_NUM");
-	
-	my $cpu_num = $simulate->object_get_attribute('compile', 'cpu_num');
-	$cpu_num = 1 if (!defined $cpu_num);
-	
-	my @paralel_ratio;
-	my $total=$num;
-	my $jobs=0;	
-	my $c=0;
-	my $cmds="";
-	my $out_path ="$ENV{PRONOC_WORK}/simulate/"; 
-	
-	for (my $i=0; $i<$num; $i++){
-		 my $f=$simulate->object_get_attribute($sample,"traffic_file$i");
-		 add_info($info, "Run $bin for $f  file \n");	
-		 my $cmd="$bin -c $SIM_CLOCK_LIMIT -f  \"$f\" > $out_path/sim_out$i & ";
-		 $cmds .=$cmd;
-		 add_info($info, "$cmd \n");
-		 $jobs++;
-		 push (@paralel_ratio,$i);
-		 $c++;
-		 if($jobs % $cpu_num ==0 || $jobs == $total){
-			#run paralle simulation
-			my ($stdout,$exit,$stderr)=run_cmd_in_back_ground_get_stdout("$cmds\n wait\n");
-			#print "($stdout,$exit,$stderr)\n";
-			if($exit || (length $stderr >4)){
-				add_colored_info($info, "Error in running simulation: $stderr \n",'red');
-				$simulate->object_add_attribute ($sample,"status","failed");	
-				$simulate->object_add_attribute('status',undef,'ideal');
-				return;
-			 } 
-			 
-			
-			 
-			 
-			#save results
-			for (my $j=0; $j<$c; $j++){
-				my $r      = $paralel_ratio[$j];
-				my $stdout = load_file("$out_path/sim_out$r");
-				my @errors = unix_grep("$out_path/sim_out$r","ERROR:");
-				if (scalar @errors  ){
-						add_colored_info($info, "Error in running simulation: @errors \n",'red');
-						$simulate->object_add_attribute ($sample,"status","failed");	
-						$simulate->object_add_attribute('status',undef,'ideal');
-						return;						
-				}		
-			
-				extract_and_update_noc_sim_statistic ($simulate,$sample,$r,$stdout);
-			} 
-			
-			$cmds="";
-			@paralel_ratio=();
-			$c=0;
-			set_gui_status($simulate,"ref",2);	
-		} 		 
-		    	 
-	}#for i
-	
-	$simulate->object_add_attribute ($sample,"status","done");	
-}	
-
-
-
+    my ($simulate,$info,$sample,$name)=@_;
+    my $log= (defined $name)? "$ENV{PRONOC_WORK}/simulate/$name.log": "$ENV{PRONOC_WORK}/simulate/sim.log";
+    my $SIM_CLOCK_LIMIT=$simulate->object_get_attribute ($sample,"SIM_CLOCK_LIMIT");
+    my $bin=get_sim_bin_path($simulate,$sample,$info);
+    my $dir = Cwd::getcwd();
+    my $project_dir      = abs_path("$dir/../.."); #mpsoc directory address
+    $bin= "$project_dir/$bin"   if(!(-f $bin));
+    my $num=$simulate->object_get_attribute($sample,"TRAFFIC_FILE_NUM");
+    my $cpu_num = $simulate->object_get_attribute('compile', 'cpu_num');
+    $cpu_num = 1 if (!defined $cpu_num);
+    my @paralel_ratio;
+    my $total=$num;
+    my $jobs=0;    
+    my $c=0;
+    my $cmds="";
+    my $out_path ="$ENV{PRONOC_WORK}/simulate/"; 
+    for (my $i=0; $i<$num; $i++){
+        my $f=$simulate->object_get_attribute($sample,"traffic_file$i");
+        add_info($info, "Run $bin for $f  file \n");    
+        my $cmd="$bin -c $SIM_CLOCK_LIMIT -f  \"$f\" > $out_path/sim_out$i & ";
+        $cmds .=$cmd;
+        add_info($info, "$cmd \n");
+        $jobs++;
+        push (@paralel_ratio,$i);
+        $c++;
+        if($jobs % $cpu_num ==0 || $jobs == $total){
+            #run paralle simulation
+            my ($stdout,$exit,$stderr)=run_cmd_in_back_ground_get_stdout("$cmds\n wait\n");
+            #print "($stdout,$exit,$stderr)\n";
+            if($exit || (length $stderr >4)){
+                add_colored_info($info, "Error in running simulation: $stderr \n",'red');
+                $simulate->object_add_attribute ($sample,"status","failed");    
+                $simulate->object_add_attribute('status',undef,'ideal');
+                return;
+            } 
+            #save results
+            for (my $j=0; $j<$c; $j++){
+                my $r      = $paralel_ratio[$j];
+                my $stdout = load_file("$out_path/sim_out$r");
+                my @errors = unix_grep("$out_path/sim_out$r","ERROR:");
+                if (scalar @errors  ){
+                        add_colored_info($info, "Error in running simulation:\n @errors \n",'red');
+                        $simulate->object_add_attribute ($sample,"status","failed");    
+                        $simulate->object_add_attribute('status',undef,'ideal');
+                        return;
+                }
+                extract_and_update_noc_sim_statistic ($simulate,$sample,$r,$stdout);
+            } 
+            $cmds="";
+            @paralel_ratio=();
+            $c=0;
+            set_gui_status($simulate,"ref",2);    
+        }
+    }#for i
+    $simulate->object_add_attribute ($sample,"status","done");    
+}
 
 sub run_trace_simulation{
-	my ($simulate,$info,$sample,$name)=@_;
-	my $log= (defined $name)? "$ENV{PRONOC_WORK}/simulate/$name.log": "$ENV{PRONOC_WORK}/simulate/sim.log";
-	
-		
-	my $bin=get_sim_bin_path($simulate,$sample,$info);
-	
-	
-	my $project_dir	  = get_project_dir();
-	$bin= "$project_dir/$bin"   if(!(-f $bin));
-	
-	
-	my $cpu_num = $simulate->object_get_attribute('compile', 'cpu_num');
-	$cpu_num = 1 if (!defined $cpu_num);
-	
-	my @paralel_ratio;
-	
-	my $jobs=0;	
-	my $c=0;
-	my $cmds="";
-	my $out_path ="$ENV{PRONOC_WORK}/simulate/"; 
-	my $thread_num = $simulate->object_get_attribute('compile', 'thread_num');
-	$thread_num = 1 if (!defined $thread_num);
-	
-	my $model= $simulate->object_get_attribute($sample,'MODEL_NAME');
-	
-	add_info($info, "Run $bin for $model model \n");
-	
-	my $cmd="$bin -T $thread_num ";	
-	my $traffictype=$simulate->object_get_attribute($sample,"TRAFFIC_TYPE");
-	if($traffictype eq "Netrace"){
-		my $PCK_NUM_LIMIT=$simulate->object_get_attribute ($sample,"PCK_NUM_LIMIT");		
-		my $IGNORE_DPNDCY=$simulate->object_get_attribute ($sample,"IGNORE_DPNDCY");
-		my $READER_THRL=$simulate->object_get_attribute ($sample,"READER_THRL");
-		my $START_RGN=$simulate->object_get_attribute ($sample,"START_RGN");
-		my $SPEED_UP=$simulate->object_get_attribute ($sample,"SPEED_UP");
-	
-		my $models_dir  = "$ENV{PRONOC_WORK}/simulate/netrace";		
-		
-		$cmd .="-F $models_dir/$model.bz2 -n $PCK_NUM_LIMIT -r $START_RGN  -v 0 -s $SPEED_UP";
-		$cmd .=" -l " if ($READER_THRL eq "1\'b1" );
-		$cmd .=" -d " if ($IGNORE_DPNDCY eq "1\'b1");
-		
-		
-	
-		
-		
-	}else{#synful
-		my $SIM_CLOCK_LIMIT=$simulate->object_get_attribute ($sample,"SIM_CLOCK_LIMIT");
-		my $PCK_NUM_LIMIT=$simulate->object_get_attribute ($sample,"PCK_NUM_LIMIT");
-		my $RND_SEED=$simulate->object_get_attribute ($sample,"RND_SEED");
-		my $EXIT_STEADY=$simulate->object_get_attribute ($sample,"EXIT_STEADY");
-		my $FLITw=$simulate->object_get_attribute ($sample,"SYNFUL_FLITw");
-		
-		
-		my $models_dir  = get_project_dir()."/mpsoc/src_c/synfull/generated-models/";	
-		$cmd .=" -S $models_dir/$model.model -n $PCK_NUM_LIMIT -r $RND_SEED -c $SIM_CLOCK_LIMIT -v 0 -w $FLITw";
-		$cmd .=" -s " if ($EXIT_STEADY eq "1\'b1");
-
-		
-		
-	}
-	$cmd .=" > $out_path/sim_out";	
-	add_info($info, "$cmd \n");
-	
-	my ($stdout,$exit,$stderr)=run_cmd_in_back_ground_get_stdout("$cmd\n wait\n");
-	if($exit || (length $stderr >4)){
-		add_colored_info($info, "Error in running simulation: $stderr \n",'red');
-		$simulate->object_add_attribute ($sample,"status","failed");	
-		$simulate->object_add_attribute('status',undef,'ideal');
-		return;
-	 } 
-		
-	
-		 
-	$stdout = load_file("$out_path/sim_out");
-	my @errors = unix_grep("$out_path/sim_out","ERROR:");
-	if (scalar @errors  ){
-		add_colored_info($info, "Error in running simulation: @errors \n",'red');
-		$simulate->object_add_attribute ($sample,"status","failed");	
-		$simulate->object_add_attribute('status',undef,'ideal');
-		return;						
-	}		
-			
-	extract_and_update_noc_sim_statistic ($simulate,$sample,0,$stdout);
-	
-			
-	set_gui_status($simulate,"ref",2);	
-		
-	
-	$simulate->object_add_attribute ($sample,"status","done");	
-}	
-
-
+    my ($simulate,$info,$sample,$name)=@_;
+    my $log= (defined $name)? "$ENV{PRONOC_WORK}/simulate/$name.log": "$ENV{PRONOC_WORK}/simulate/sim.log";
+    my $bin=get_sim_bin_path($simulate,$sample,$info);
+    my $project_dir  = get_project_dir();
+    $bin= "$project_dir/$bin"   if(!(-f $bin));
+    my $cpu_num = $simulate->object_get_attribute('compile', 'cpu_num');
+    $cpu_num = 1 if (!defined $cpu_num);
+    my @paralel_ratio;
+    my $jobs=0;    
+    my $c=0;
+    my $cmds="";
+    my $out_path ="$ENV{PRONOC_WORK}/simulate/"; 
+    my $thread_num = $simulate->object_get_attribute('compile', 'thread_num');
+    $thread_num = 1 if (!defined $thread_num);
+    my $model= $simulate->object_get_attribute($sample,'MODEL_NAME');
+    add_info($info, "Run $bin for $model model \n");
+    my $cmd="$bin -T $thread_num ";    
+    my $traffictype=$simulate->object_get_attribute($sample,"TRAFFIC_TYPE");
+    if($traffictype eq "Netrace"){
+        my $PCK_NUM_LIMIT=$simulate->object_get_attribute ($sample,"PCK_NUM_LIMIT");        
+        my $IGNORE_DPNDCY=$simulate->object_get_attribute ($sample,"IGNORE_DPNDCY");
+        my $READER_THRL=$simulate->object_get_attribute ($sample,"READER_THRL");
+        my $START_RGN=$simulate->object_get_attribute ($sample,"START_RGN");
+        my $SPEED_UP=$simulate->object_get_attribute ($sample,"SPEED_UP");
+        my $models_dir  = "$ENV{PRONOC_WORK}/simulate/netrace";        
+        $cmd .="-F $models_dir/$model.bz2 -n $PCK_NUM_LIMIT -r $START_RGN  -v 0 -s $SPEED_UP";
+        $cmd .=" -l " if ($READER_THRL eq "1\'b1" );
+        $cmd .=" -d " if ($IGNORE_DPNDCY eq "1\'b1");
+    }else{#synful
+        my $SIM_CLOCK_LIMIT=$simulate->object_get_attribute ($sample,"SIM_CLOCK_LIMIT");
+        my $PCK_NUM_LIMIT=$simulate->object_get_attribute ($sample,"PCK_NUM_LIMIT");
+        my $RND_SEED=$simulate->object_get_attribute ($sample,"RND_SEED");
+        my $EXIT_STEADY=$simulate->object_get_attribute ($sample,"EXIT_STEADY");
+        my $FLITw=$simulate->object_get_attribute ($sample,"SYNFUL_FLITw");
+        my $models_dir  = get_project_dir()."/mpsoc/src_c/synfull/generated-models/";    
+        $cmd .=" -S $models_dir/$model.model -n $PCK_NUM_LIMIT -r $RND_SEED -c $SIM_CLOCK_LIMIT -v 0 -w $FLITw";
+        $cmd .=" -s " if ($EXIT_STEADY eq "1\'b1");
+    }
+    $cmd .=" > $out_path/sim_out";    
+    add_info($info, "$cmd \n");
+    my ($stdout,$exit,$stderr)=run_cmd_in_back_ground_get_stdout("$cmd\n wait\n");
+    if($exit || (length $stderr >4)){
+        add_colored_info($info, "Error in running simulation: $stderr \n",'red');
+        $simulate->object_add_attribute ($sample,"status","failed");    
+        $simulate->object_add_attribute('status',undef,'ideal');
+        return;
+    } 
+    
+    $stdout = load_file("$out_path/sim_out");
+    my @errors = unix_grep("$out_path/sim_out","ERROR:");
+    if (scalar @errors  ){
+        add_colored_info($info, "Error in running simulation:\n @errors \n",'red');
+        $simulate->object_add_attribute ($sample,"status","failed");    
+        $simulate->object_add_attribute('status',undef,'ideal');
+        return;
+    }
+    extract_and_update_noc_sim_statistic ($simulate,$sample,0,$stdout);
+    set_gui_status($simulate,"ref",2);    
+    $simulate->object_add_attribute ($sample,"status","done");    
+}
 
 
 ##########
 # check_sample
 ##########
-
 sub get_sim_bin_path {
-	my ($self,$sample,$info)=@_;
-	my $bin_path=$self->object_get_attribute ($sample,"sof_path");	
-	unless (-d $bin_path){
-		my $path= $self->object_get_attribute ("sim_param","BIN_DIR");
-		if(-d $path){
-			add_colored_info($info, "Warning: The given path ($bin_path) for searching $sample bin file does not exist. The system search in default $path instead.\n",'green');
-			$bin_path=$path;
-		}
-	}	
-	my $bin_file=$self->object_get_attribute ($sample,"sof_file");	
-	$bin_file = "-" if(!defined $bin_file);		
-	my $sof="$bin_path/$bin_file";
-	return $sof;
+    my ($self,$sample,$info)=@_;
+    my $bin_path=$self->object_get_attribute ($sample,"sof_path");    
+    unless (-d $bin_path){
+        my $path= $self->object_get_attribute ("sim_param","BIN_DIR");
+        if(-d $path){
+            add_colored_info($info, "Warning: The given path ($bin_path) for searching $sample bin file does not exist. The system search in default $path instead.\n",'green');
+            $bin_path=$path;
+        }
+    }    
+    my $bin_file=$self->object_get_attribute ($sample,"sof_file");    
+    $bin_file = "-" if(!defined $bin_file);        
+    my $sof="$bin_path/$bin_file";
+    return $sof;
 }
 
 sub check_sim_sample{
-	my ($self,$sample,$info)=@_;
-	my $status=1;
-	my $sof=get_sim_bin_path($self,$sample,$info);
-			
-	# ckeck if sample have sof file
-	if(!defined $sof){
-		add_colored_info($info, "Error: bin file has not set for $sample!\n",'red');
-		$self->object_add_attribute ($sample,"status","failed");	
-		$status=0;
-	} else {
-		# ckeck if bin file has info file 
-		my ($name,$path,$suffix) = fileparse("$sof",qr"\..[^.]*$");
-		my $sof_info= "$path$name.inf";
-		if(!(-f $sof_info)){
-			add_colored_info($info, "Could not find $name.inf file in $path. An information file is required for each sof file containing the device name and  NoC configuration. Press F3 for more help.\n",'red');
-			$self->object_add_attribute ($sample,"status","failed");	
-			$status=0;
-		}else { #add info
-			my $pp= do $sof_info ;
-
-			my $p=$pp->{'noc_param'};
-			
-			$status=0 if $@;
-			message_dialog("Error reading: $@") if $@;
-			if ($status==1){
-				$self->object_add_attribute ($sample,"noc_info",$p) ;
-					
-			
-			}			
-		}		
-	}
-	#check if sample min packet size matches in simulation 
-	
-	my $p= $self->object_get_attribute ($sample,"noc_info");    
+    my ($self,$sample,$info)=@_;
+    my $status=1;
+    my $sof=get_sim_bin_path($self,$sample,$info);
+    # ckeck if sample have sof file
+    if(!defined $sof){
+        add_colored_info($info, "Error: bin file has not set for $sample!\n",'red');
+        $self->object_add_attribute ($sample,"status","failed");    
+        $status=0;
+    } else {
+        # ckeck if bin file has info file 
+        my ($name,$path,$suffix) = fileparse("$sof",qr"\..[^.]*$");
+        my $sof_info= "$path$name.inf";
+        if(!(-f $sof_info)){
+            add_colored_info($info, "Could not find $name.inf file in $path. An information file is required for each sof file containing the device name and  NoC configuration. Press F3 for more help.\n",'red');
+            $self->object_add_attribute ($sample,"status","failed");    
+            $status=0;
+        }else { #add info
+            my $pp= do $sof_info ;
+            my $p=$pp->{'noc_param'};
+            $status=0 if $@;
+            message_dialog("Error reading: $@") if $@;
+            if ($status==1){
+                $self->object_add_attribute ($sample,"noc_info",$p) ;
+            }
+        }
+    }
+    #check if sample min packet size matches in simulation 
+    my $p= $self->object_get_attribute ($sample,"noc_info");    
     my $HW_MIN_PCK_SIZE=$p->{"MIN_PCK_SIZE"};
     my $HW_PCK_TYPE=$p->{"PCK_TYPE"};
     my $SIM_MIN_PCK_SIZE=$self->object_get_attribute ($sample,"MIN_PCK_SIZE");
     my $SIM_MAX_PCK_SIZE=$self->object_get_attribute ($sample,"MAX_PCK_SIZE");
-   if(!defined $HW_MIN_PCK_SIZE){
-    	$HW_MIN_PCK_SIZE= 2;   
-    	#print "undef\n"; 	
+    if(!defined $HW_MIN_PCK_SIZE){
+        $HW_MIN_PCK_SIZE= 2;   
+        #print "undef\n";     
     }
     $HW_PCK_TYPE = "MULTI_FLIT" if(~defined $HW_PCK_TYPE);
-	if($HW_MIN_PCK_SIZE>$SIM_MIN_PCK_SIZE){
-		add_colored_info($info, "Error: The minimum simulation packet size of $SIM_MIN_PCK_SIZE flit(s) is smaller than $HW_MIN_PCK_SIZE which is defined in generating verilog model of NoC!\n",'red');
-		$self->object_add_attribute ($sample,"status","failed");	
-		$status=0;
-	}
-	if( $HW_PCK_TYPE eq '"SINGLE_FLIT"' && $SIM_MAX_PCK_SIZE !=1){
-		#print "$HW_PCK_TYPE  \n"; 
-		add_colored_info($info, "Error: The maximum packet size is set as $SIM_MAX_PCK_SIZE however, the selected NoC model only support single-flit packet injection! Please redefine it to one\n",'red');
-		
-		$self->object_add_attribute ($sample,"status","failed");	
-		$status=0;
-	}
-			
-	return $status;
+    if($HW_MIN_PCK_SIZE>$SIM_MIN_PCK_SIZE){
+        add_colored_info($info, "Error: The minimum simulation packet size of $SIM_MIN_PCK_SIZE flit(s) is smaller than $HW_MIN_PCK_SIZE which is defined in generating verilog model of NoC!\n",'red');
+        $self->object_add_attribute ($sample,"status","failed");    
+        $status=0;
+    }
+    if( $HW_PCK_TYPE eq '"SINGLE_FLIT"' && $SIM_MAX_PCK_SIZE !=1){
+        #print "$HW_PCK_TYPE  \n"; 
+        add_colored_info($info, "Error: The maximum packet size is set as $SIM_MAX_PCK_SIZE however, the selected NoC model only support single-flit packet injection! Please redefine it to one\n",'red');
+        $self->object_add_attribute ($sample,"status","failed");    
+        $status=0;
+    }
+    return $status;
 }
 
 sub noc_sim_ctrl{
-	my ($simulate,$info)=@_;
-	
-	my $generate = def_image_button('icons/forward.png','R_un all',FALSE,1);
-	my $open = def_image_button('icons/browse.png',"_Load",FALSE,1);
-	my $save = def_image_button('icons/save.png','Sav_e',FALSE,1);
-	my $save_all_results = def_image_button('icons/copy.png',"E_xtract all results",FALSE,1);
-	my $cpus=select_parallel_process_num($simulate);
-	my ($object,$attribute1,$attribute2,$content,$default,$status,$timeout)=@_;
-	
-	my $compiler =def_pack_hbox('FALSE',0, gen_label_in_center('Simulator:'), gen_combobox_object($simulate,'Simulator',undef,"Modelsim gui,Modelsim,Verilator","Verilator",'ref',1));
-	
-	
-	my $entry = gen_entry_object($simulate,'simulate_name',undef,undef,undef,undef);
-	my $entrybox=gen_label_info(" Save as:",$entry);
-	$entrybox->pack_start( $save, FALSE, FALSE, 0);
-	
-	my $simulator =$simulate->object_get_attribute("Simulator");
-	
-	
-	my $thread=select_parallel_thread_num($simulate);
-	
-		
-	my $table = def_table (1, 12, FALSE);
-	$table->attach ($open,		0, 1, 0,1,'expand','shrink',2,2);
-	$table->attach ($compiler, 1, 2, 0,1,'expand','shrink',2,2);
-	
-	$table->attach ($cpus, 		2, 4, 0,1,'expand','shrink',2,2);
-	if($simulator eq "Verilator"){
-		$table->attach ($thread, 4, 5, 0,1,'expand','shrink',2,2);		
-	}
-	
-	$table->attach ($entrybox,	5, 7, 0,1,'expand','shrink',2,2);
-	$table->attach ($save_all_results, 7, 8, 0,1,'shrink','shrink',2,2);
-	$table->attach ($generate, 	8, 9, 0,1,'expand','shrink',2,2);
-	
-	$generate-> signal_connect("clicked" => sub{ 
-		my @samples =$simulate->object_get_attribute_order("samples");	
-		foreach my $sample (@samples){
-			$simulate->object_add_attribute ("$sample","status","run");	
-		}
-		run_simulator($simulate,$info);
-		#set_gui_status($emulate,"ideal",2);
-
-	});
-
-#	$wb-> signal_connect("clicked" => sub{ 
-#		wb_address_setting($mpsoc);
-#	
-#	});
-
-	$open-> signal_connect("clicked" => sub{ 
-		
-		load_simulation($simulate,$info);
-		#print Dumper($simulate);
-		set_gui_status($simulate,"ref",5);
-	
-	});	
-
-	$save-> signal_connect("clicked" => sub{ 
-		save_simulation($simulate);		
-		set_gui_status($simulate,"ref",5);
-		
-	
-	});	
-	
-	$save_all_results-> signal_connect("clicked" => sub{ 
-		#Get the path where to save all the simulation results
-		my $open_in = $simulate->object_get_attribute ('sim_param','BIN_DIR');
-     	get_dir_name($simulate,"Select the target directory","sim_param","ALL_RESULT_DIR",$open_in,'ref',1);
-		$simulate->object_add_attribute ("graph_save","save_all_result",1);
-		
-	});	
-	
-	
-	return add_widget_to_scrolled_win($table,gen_scr_win_with_adjst($simulate,"ctrl_sc_win"));
-	
+    my ($simulate,$info)=@_;
+    my $generate = def_image_button('icons/forward.png','R_un all',FALSE,1);
+    my ($entrybox,$entry ) =gen_save_load_widget (
+        $simulate, #the object 
+        "Name",#the label shown for setting configuration
+        "simulate_name",#the key name for saveing the setting configuration in object 
+        "Experiment name",#the label full name show in tool tips
+        undef,#Where the generted RTL files are loacted. Undef if not aplicaple
+        0,#check the given name match the SoC or mpsoc name rules
+        "lib/simulate",#where the current configuration seting file is saved
+        "SIM",#the extenstion given for configuration seting file
+        \&load_simulation,
+        $info);
+    my $save_all_results = def_image_button('icons/copy.png',"E_xtract all results",FALSE,1);
+    my $cpus=select_parallel_process_num($simulate);
+    my $compiler =def_pack_hbox('FALSE',0, gen_label_in_center('Simulator:'), gen_combobox_object($simulate,'Simulator',undef,"Modelsim gui,Modelsim,Verilator","Verilator",'ref',1));
+    my $simulator =$simulate->object_get_attribute("Simulator");
+    my $thread=select_parallel_thread_num($simulate);
+    my $table = def_table (1, 12, FALSE);
+    $table->attach ($compiler, 1, 2, 0,1,'expand','shrink',2,2);
+    $table->attach ($cpus, 2, 4, 0,1,'expand','shrink',2,2);
+    if($simulator eq "Verilator"){
+        $table->attach ($thread, 4, 5, 0,1,'expand','shrink',2,2);
+    }
+    $table->attach ($entrybox,    5, 7, 0,1,'expand','shrink',2,2);
+    $table->attach ($save_all_results, 7, 8, 0,1,'shrink','shrink',2,2);
+    $table->attach ($generate,     8, 9, 0,1,'expand','shrink',2,2);
+    $generate-> signal_connect("clicked" => sub{ 
+        my @samples =$simulate->object_get_attribute_order("samples");
+        foreach my $sample (@samples){
+            $simulate->object_add_attribute ("$sample","status","run");
+        }
+        run_simulator($simulate,$info);
+    });
+    $save_all_results-> signal_connect("clicked" => sub{ 
+        #Get the path where to save all the simulation results
+        my $open_in = $simulate->object_get_attribute ('sim_param','BIN_DIR');
+        get_dir_name($simulate,"Select the target directory","sim_param","ALL_RESULT_DIR",$open_in,'ref',1);
+        $simulate->object_add_attribute ("graph_save","save_all_result",1);
+    });
+    return add_widget_to_scrolled_win($table,gen_scr_win_with_adjst($simulate,"ctrl_sc_win"));
 }
 
-
 ############
 #    main
 ############
 sub simulator_main{
-	
-	add_color_to_gd();
-	my $simulate= emulator->emulator_new();
-	set_gui_status($simulate,"ideal",0);
-	
-
-	my $main_table = def_table (25, 12, FALSE);
-	$main_table->show_all;
-	my ($infobox,$info)= create_txview();	
-	
-	
-
-my @pages =(
-	{page_name=>" Average/Total ", page_num=>0},
-	{page_name=>" Per node ", page_num=>1},
-	#{page_name=>" Worst-Case Delay ",page_num=>2},
-	#{page_name=>" Execution Time ",page_num=>3},
-	{page_name=>" Heat-Map. ",page_num=>4},
-);
-
-
-
-my @charts = (
-	{ type=>"2D_line", page_num=>0, graph_name=> "Avg. packet Latency", result_name => "latency_result", X_Title=> 'Desired Avg. Injected Load Per Router (flits/clock (%))', Y_Title=>'Avg. Packet Latency (clock)', Z_Title=>undef, Y_Max=>100},
-  	{ type=>"2D_line", page_num=>0, graph_name=> "Avg. flit Latency", result_name => "latency_flit_result", X_Title=> 'Desired Avg. Injected Load Per Router (flits/clock (%))', Y_Title=>'Avg. Flit Latency (clock)', Z_Title=>undef, Y_Max=>100},
-  	{ type=>"2D_line", page_num=>0, graph_name=> "Avg. flit Latency per hop", result_name => "latency_perhop_result", X_Title=> 'Desired Avg. Injected Load Per Router (flits/clock (%))', Y_Title=>'Avg. Flit Latency per hop (clock)', Z_Title=>undef, Y_Max=>100},
-    { type=>"2D_line", page_num=>0, graph_name=> "Avg. throughput", result_name => "throughput_result", X_Title=> 'Desired Avg. Injected Load Per Router (flits/clock (%))', Y_Title=>'Avg. Throughput (flits/clock (%))', Z_Title=>undef,Y_Max=>100},
-  	{ type=>"2D_line", page_num=>0, graph_name=> "Avg. SD latency", result_name => "sd_latency_result", X_Title=> 'Desired Avg. Injected Load Per Router (flits/clock (%))', Y_Title=>'Latency Standard Deviation (clock)', Z_Title=>undef},
-	{ type=>"2D_line", page_num=>0, graph_name=> "Worst pck latency (clk)", result_name => "worst_latency_result", X_Title=> 'Desired Avg. Injected Load Per Router (flits/clock (%))', Y_Title=>'Worst Packet Latency (clock)', Z_Title=>undef},
-	{ type=>"2D_line", page_num=>0, graph_name=> "Min pck latency (clk)", result_name => "min_latency_result", X_Title=> 'Desired Avg. Injected Load Per Router (flits/clock (%))', Y_Title=>'Minimum Packet Latency (clock)', Z_Title=>undef},
-	{ type=>"2D_line", page_num=>0, graph_name=> "Total injected pck", result_name =>"injected_pck_total" , X_Title=> 'Desired Avg. Injected Load Per Router (flits/clock (%))', Y_Title=>'Total Injected packets', Z_Title=>undef},
-	{ type=>"2D_line", page_num=>0, graph_name=> "Total injected flit",result_name =>"injected_flit_total", X_Title=> 'Desired Avg. Injected Load Per Router (flits/clock (%))', Y_Title=>'Total Injected Fslits', Z_Title=>undef},
-	{ type=>"2D_line", page_num=>0, graph_name=> "Execuation Cycles", result_name => "exe_time_result",X_Title=>'Desired Avg. Injected Load Per Router (flits/clock (%))' , Y_Title=>'Total Simulation Time (clk)', Z_Title=>undef},
-	
-	
-
-	{ type=>"3D_bar",  page_num=>1, graph_name=> "Received packets per Endp", result_name => "packet_rsvd_result", X_Title=>'Endpoint ID' , Y_Title=>'Received Packets Per Endpoint', Z_Title=>undef},
-	{ type=>"3D_bar",  page_num=>1, graph_name=> "Sent packets per Endp", result_name => "packet_sent_result", X_Title=>'Endpoint ID' , Y_Title=>'Sent Packets Per Endpoint', Z_Title=>undef},
-	{ type=>"3D_bar",  page_num=>1, graph_name=> "Received flits per Endp", result_name => "flit_rsvd_result", X_Title=>'Endpoint ID' , Y_Title=>'Received Flits Per Endpoint', Z_Title=>undef},
-	{ type=>"3D_bar",  page_num=>1, graph_name=> "Sent flits per Endp", result_name => "flit_sent_result", X_Title=>'Endpoint ID' , Y_Title=>'Sent Packets Flits Endpoint', Z_Title=>undef},
-	{ type=>"3D_bar",  page_num=>1, graph_name=> "Flits per Router", result_name => "flit_per_router_result", X_Title=>'Router ID' , Y_Title=>'Received Flits Per Router', Z_Title=>undef},
-	{ type=>"3D_bar",  page_num=>1, graph_name=> "Packets per Router", result_name => "packet_per_router_result", X_Title=>'Router ID' , Y_Title=>'Received Packets Per Router', Z_Title=>undef},
-	{ type=>"3D_bar",  page_num=>1, graph_name=> "Worst Received pck latency per Endp", result_name => "worst_delay_rsvd_result",X_Title=>'Endpoint ID' , Y_Title=>'Worst-Case Delay (clk)', Z_Title=>undef},
-	{ type=>"3D_bar",  page_num=>1, graph_name=> "Worst Sent pck latency per Endp", result_name => "worst_delay_sent_result",X_Title=>'Endpoint ID' , Y_Title=>'Worst-Case Delay (clk)', Z_Title=>undef},
-	
-	{ type=>"3D_bar",  page_num=>1, graph_name=> "Buffered Flit in Ratio Per Router", result_name => "flit_buffered_router_ratio",X_Title=>'Router ID' , Y_Title=>'Flit in buffered in router/Flit in (%)', Z_Title=>undef},
-	{ type=>"3D_bar",  page_num=>1, graph_name=> "Bypassed Flit in Ratio Per Router", result_name => "flit_bypass_router_ratio",X_Title=>'Router ID' , Y_Title=>'Flit in bypassed in router/Flit in (%)', Z_Title=>undef},
-	
-	
-	
-	
-		
-	
-	
-	
-	
-	
-	
-	
-	{ type=>"Heat-map", page_num=>4, graph_name=> "Select", result_name => "undef",X_Title=>'-' , Y_Title=> undef, Z_Title=>undef},
-	{ type=>"Heat-map", page_num=>4, graph_name=> "Endp-2-Endp Flit-num", result_name => "endp-endp-flit_result",X_Title=>'total flit number sent from an endpoint to another' , Y_Title=> undef, Z_Title=>undef},
-	{ type=>"Heat-map", page_num=>4, graph_name=> "Endp-2-Endp Packet-num", result_name => "endp-endp-pck_result",X_Title=>'total packet number sent from an endpoint to another' , Y_Title=> undef, Z_Title=>undef},
-	
-	
-	);
-	
-	
-	my ($conf_box,$set_win)=process_notebook_gen($simulate,$info,"simulate",undef,@charts);
-	my $chart   =gen_multiple_charts  ($simulate,\@pages,\@charts,0.4);
-    
-
-
-	$main_table->set_row_spacings (4);
-	$main_table->set_col_spacings (1);
-	
-	
-	#my  $device_win=show_active_dev($soc,$soc,$infc,$soc_state,\$refresh,$info);
-	
-	
-	
-	
-	my $image = get_status_gif($simulate);
-	my $ctrl  = noc_sim_ctrl ($simulate,$info);
-	
-	my $v1=gen_vpaned($conf_box,.45,$image);
-	my $v2=gen_vpaned($infobox,.2,$chart);
-	my $h1=gen_hpaned($v1,.4,$v2);
-	
-	
-	
-	$main_table->attach_defaults ($h1  , 0, 12, 0,24);
-	$main_table->attach ($ctrl, 0,12, 24,25,'fill','fill',2,2);
-	
-	my $sc_win=add_widget_to_scrolled_win($main_table);
-
-
-	#check soc status every 0.5 second. refresh device table if there is any changes 
-	Glib::Timeout->add (100, sub{ 
-	 
-		my ($state,$timeout)= get_gui_status($simulate);
-		
-		if ($timeout>0){
-			$timeout--;
-			set_gui_status($simulate,$state,$timeout);	
-			return TRUE;
-			
-		}
-		if($state eq "ideal"){
-			return TRUE;
-			 
-		}
-		
-		
-		
-		#refresh GUI
-		
-		
-		$ctrl->destroy();							
-		$conf_box->destroy();
-		$chart->destroy();
-		$image->destroy(); 
-		$image = get_status_gif($simulate);
-		($conf_box,$set_win)=process_notebook_gen($simulate,$info,"simulate",$set_win,@charts);				
-		$chart = gen_multiple_charts  ($simulate,\@pages,\@charts,0.4);
-		$ctrl  = noc_sim_ctrl ($simulate,$info);
-		$main_table->attach ($ctrl,0, 12, 24,25,'fill','fill',2,2);
-		$v1 -> pack1($conf_box, TRUE, TRUE); 	
-		$v1 -> pack2($image, TRUE, TRUE); 		
-		$v2 -> pack2($chart, TRUE, TRUE); 	
-		
-		
-		
-		
-		$conf_box->show_all();
-		$main_table->show_all();			
-		set_gui_status($simulate,"ideal",0);
-		
-		
-		return TRUE;
-		
-	} );
-		
-		
-	
-		
-	
-
-	return $sc_win;
-
-		
-
+    add_color_to_gd();
+    my $simulate= emulator->emulator_new();
+    set_gui_status($simulate,"ideal",0);
+    my $main_table = def_table (25, 12, FALSE);
+    $main_table->show_all;
+    my ($infobox,$info)= create_txview();    
+    my @pages =(
+        {page_name=>" Average/Total ", page_num=>0},
+        {page_name=>" Per node ", page_num=>1},
+        #{page_name=>" Worst-Case Delay ",page_num=>2},
+        #{page_name=>" Execution Time ",page_num=>3},
+        {page_name=>" Heat-Map. ",page_num=>4},
+    );
+    my @charts = (
+        { type=>"2D_line", page_num=>0, graph_name=> "Avg. packet Latency", result_name => "latency_result", X_Title=> 'Desired Avg. Injected Load Per Router (flits/clock (%))', Y_Title=>'Avg. Packet Latency (clock)', Z_Title=>undef, Y_Max=>100},
+        { type=>"2D_line", page_num=>0, graph_name=> "Avg. flit Latency", result_name => "latency_flit_result", X_Title=> 'Desired Avg. Injected Load Per Router (flits/clock (%))', Y_Title=>'Avg. Flit Latency (clock)', Z_Title=>undef, Y_Max=>100},
+        { type=>"2D_line", page_num=>0, graph_name=> "Avg. flit Latency per hop", result_name => "latency_perhop_result", X_Title=> 'Desired Avg. Injected Load Per Router (flits/clock (%))', Y_Title=>'Avg. Flit Latency per hop (clock)', Z_Title=>undef, Y_Max=>100},
+        { type=>"2D_line", page_num=>0, graph_name=> "Avg. throughput", result_name => "throughput_result", X_Title=> 'Desired Avg. Injected Load Per Router (flits/clock (%))', Y_Title=>'Avg. Throughput (flits/clock (%))', Z_Title=>undef,Y_Max=>100},
+        { type=>"2D_line", page_num=>0, graph_name=> "Avg. SD latency", result_name => "sd_latency_result", X_Title=> 'Desired Avg. Injected Load Per Router (flits/clock (%))', Y_Title=>'Latency Standard Deviation (clock)', Z_Title=>undef},
+        { type=>"2D_line", page_num=>0, graph_name=> "Worst pck latency (clk)", result_name => "worst_latency_result", X_Title=> 'Desired Avg. Injected Load Per Router (flits/clock (%))', Y_Title=>'Worst Packet Latency (clock)', Z_Title=>undef},
+        { type=>"2D_line", page_num=>0, graph_name=> "Min pck latency (clk)", result_name => "min_latency_result", X_Title=> 'Desired Avg. Injected Load Per Router (flits/clock (%))', Y_Title=>'Minimum Packet Latency (clock)', Z_Title=>undef},
+        { type=>"2D_line", page_num=>0, graph_name=> "Total injected pck", result_name =>"injected_pck_total" , X_Title=> 'Desired Avg. Injected Load Per Router (flits/clock (%))', Y_Title=>'Total Injected packets', Z_Title=>undef},
+        { type=>"2D_line", page_num=>0, graph_name=> "Total injected flit",result_name =>"injected_flit_total", X_Title=> 'Desired Avg. Injected Load Per Router (flits/clock (%))', Y_Title=>'Total Injected Fslits', Z_Title=>undef},
+        { type=>"2D_line", page_num=>0, graph_name=> "Execuation Cycles", result_name => "exe_time_result",X_Title=>'Desired Avg. Injected Load Per Router (flits/clock (%))' , Y_Title=>'Total Simulation Time (clk)', Z_Title=>undef},
+        { type=>"3D_bar",  page_num=>1, graph_name=> "Received packets per Endp", result_name => "packet_rsvd_result", X_Title=>'Endpoint ID' , Y_Title=>'Received Packets Per Endpoint', Z_Title=>undef},
+        { type=>"3D_bar",  page_num=>1, graph_name=> "Sent packets per Endp", result_name => "packet_sent_result", X_Title=>'Endpoint ID' , Y_Title=>'Sent Packets Per Endpoint', Z_Title=>undef},
+        { type=>"3D_bar",  page_num=>1, graph_name=> "Received flits per Endp", result_name => "flit_rsvd_result", X_Title=>'Endpoint ID' , Y_Title=>'Received Flits Per Endpoint', Z_Title=>undef},
+        { type=>"3D_bar",  page_num=>1, graph_name=> "Sent flits per Endp", result_name => "flit_sent_result", X_Title=>'Endpoint ID' , Y_Title=>'Sent Packets Flits Endpoint', Z_Title=>undef},
+        { type=>"3D_bar",  page_num=>1, graph_name=> "Flits per Router", result_name => "flit_per_router_result", X_Title=>'Router ID' , Y_Title=>'Received Flits Per Router', Z_Title=>undef},
+        { type=>"3D_bar",  page_num=>1, graph_name=> "Packets per Router", result_name => "packet_per_router_result", X_Title=>'Router ID' , Y_Title=>'Received Packets Per Router', Z_Title=>undef},
+        { type=>"3D_bar",  page_num=>1, graph_name=> "Worst Received pck latency per Endp", result_name => "worst_delay_rsvd_result",X_Title=>'Endpoint ID' , Y_Title=>'Worst-Case Delay (clk)', Z_Title=>undef},
+        { type=>"3D_bar",  page_num=>1, graph_name=> "Worst Sent pck latency per Endp", result_name => "worst_delay_sent_result",X_Title=>'Endpoint ID' , Y_Title=>'Worst-Case Delay (clk)', Z_Title=>undef},
+        { type=>"3D_bar",  page_num=>1, graph_name=> "Buffered Flit in Ratio Per Router", result_name => "flit_buffered_router_ratio",X_Title=>'Router ID' , Y_Title=>'Flit in buffered in router/Flit in (%)', Z_Title=>undef},
+        { type=>"3D_bar",  page_num=>1, graph_name=> "Bypassed Flit in Ratio Per Router", result_name => "flit_bypass_router_ratio",X_Title=>'Router ID' , Y_Title=>'Flit in bypassed in router/Flit in (%)', Z_Title=>undef},
+        { type=>"Heat-map", page_num=>4, graph_name=> "Select", result_name => "undef",X_Title=>'-' , Y_Title=> undef, Z_Title=>undef},
+        { type=>"Heat-map", page_num=>4, graph_name=> "Endp-2-Endp Flit-num", result_name => "endp-endp-flit_result",X_Title=>'total flit number sent from an endpoint to another' , Y_Title=> undef, Z_Title=>undef},
+        { type=>"Heat-map", page_num=>4, graph_name=> "Endp-2-Endp Packet-num", result_name => "endp-endp-pck_result",X_Title=>'total packet number sent from an endpoint to another' , Y_Title=> undef, Z_Title=>undef},
+    );
+    my ($conf_box,$set_win)=process_notebook_gen($simulate,$info,"simulate",undef,@charts);
+    my $chart   =gen_multiple_charts  ($simulate,\@pages,\@charts,0.4);
+    $main_table->set_row_spacings (4);
+    $main_table->set_col_spacings (1);
+    my $image = get_status_gif($simulate);
+    my $ctrl  = noc_sim_ctrl ($simulate,$info);
+    my $v1=gen_vpaned($conf_box,.45,$image);
+    my $v2=gen_vpaned($infobox,.2,$chart);
+    my $h1=gen_hpaned($v1,.4,$v2);
+    $main_table->attach_defaults ($h1  , 0, 12, 0,24);
+    $main_table->attach ($ctrl, 0,12, 24,25,'fill','fill',2,2);
+    my $sc_win=add_widget_to_scrolled_win($main_table);
+    #check soc status every 0.5 second. refresh device table if there is any changes 
+    Glib::Timeout->add (100, sub{ 
+        my ($state,$timeout)= get_gui_status($simulate);
+        if ($timeout>0){
+            $timeout--;
+            set_gui_status($simulate,$state,$timeout);    
+            return TRUE;
+        }
+        if($state eq "ideal"){
+            return TRUE;
+        }
+        $ctrl->destroy();
+        $conf_box->destroy();
+        $chart->destroy();
+        $image->destroy(); 
+        $image = get_status_gif($simulate);
+        ($conf_box,$set_win)=process_notebook_gen($simulate,$info,"simulate",$set_win,@charts);                
+        $chart = gen_multiple_charts  ($simulate,\@pages,\@charts,0.4);
+        $ctrl  = noc_sim_ctrl ($simulate,$info);
+        $main_table->attach ($ctrl,0, 12, 24,25,'fill','fill',2,2);
+        $v1 -> pack1($conf_box, TRUE, TRUE);
+        $v1 -> pack2($image, TRUE, TRUE);
+        $v2 -> pack2($chart, TRUE, TRUE);
+        $conf_box->show_all();
+        $main_table->show_all();
+        set_gui_status($simulate,"ideal",0);
+        return TRUE;
+    } );
+    return $sc_win;
 }
 
 sub custom_traffic_dest{
-	my ($self,$sample,$core_num)	=@_;
-	
-	my $num=$self->object_get_attribute($sample,"CUSTOM_SRC_NUM");
+    my ($self,$sample,$core_num)    =@_;
+    my $num=$self->object_get_attribute($sample,"CUSTOM_SRC_NUM");
     for (my $i=0;$i<$num;$i++){
-			my $src = $self->object_get_attribute($sample,"SRC_$i");
-			my $dst = $self->object_get_attribute($sample,"DST_$i");
-			return  ($core_num,$dst) if($src == $core_num);
+            my $src = $self->object_get_attribute($sample,"SRC_$i");
+            my $dst = $self->object_get_attribute($sample,"DST_$i");
+            return  ($core_num,$dst) if($src == $core_num);
     }
-	return ($core_num, -1);#off	
+    return ($core_num, -1);#off
 }
 
 sub download_netrace{
-	my ($path) =@_;
-	#create path if it is not exist
-	unless (-d $path){
-		mkpath("$path",1,01777);
-	}
-	my $window = def_popwin_size(30,85,"Netrace download",'percent');
-	my $table = def_table(1, 1, FALSE);	
-	my $scrolled_win = add_widget_to_scrolled_win($table);
-	
-	
-my @links =(
-{ label=>"blackscholes simlarge (907M) ",name=>"blackscholes_64c_simlarge.tra.bz2" ,url=>"https://www.cs.utexas.edu/~netrace/download/blackscholes_64c_simlarge.tra.bz2"},
-{ label=>"blackscholes simmedium (182M)",name=>"blackscholes_64c_simmedium.tra.bz2",url=>"https://www.cs.utexas.edu/~netrace/download/blackscholes_64c_simmedium.tra.bz2"},
-{ label=>"blackscholes simsmall (55M)  ",name=>"blackscholes_64c_simsmall.tra.bz2" ,url=>"https://www.cs.utexas.edu/~netrace/download/blackscholes_64c_simsmall.tra.bz2"},
-{ label=>"bodytrack simlarge (3.5G)    ",name=>"bodytrack_64c_simlarge.tra.bz2"    ,url=>"https://www.cs.utexas.edu/~netrace/download/bodytrack_64c_simlarge.tra.bz2"},
-{ label=>"canneal simmedium (3.5G)     ",name=>"canneal_64c_simmedium.tra.bz2"     ,url=>"https://www.cs.utexas.edu/~netrace/download/canneal_64c_simmedium.tra.bz2"},
-{ label=>"dedup simmedium (4.1G)       ",name=>"dedup_64c_simmedium.tra.bz2"       ,url=>"https://www.cs.utexas.edu/~netrace/download/dedup_64c_simmedium.tra.bz2"},
-{ label=>"ferret simmedium (2.7G)      ",name=>"ferret_64c_simmedium.tra.bz2"      ,url=>"https://www.cs.utexas.edu/~netrace/download/ferret_64c_simmedium.tra.bz2"},
-{ label=>"fluidanimate simlarge (1.8G) ",name=>"fluidanimate_64c_simlarge.tra.bz2" ,url=>"https://www.cs.utexas.edu/~netrace/download/fluidanimate_64c_simlarge.tra.bz2"},
-{ label=>"fluidanimate simmedium (677M)",name=>"fluidanimate_64c_simmedium.tra.bz2",url=>"https://www.cs.utexas.edu/~netrace/download/fluidanimate_64c_simmedium.tra.bz2"},
-{ label=>"fluidanimate simsmall (317M) ",name=>"fluidanimate_64c_simsmall.tra.bz2" ,url=>"https://www.cs.utexas.edu/~netrace/download/fluidanimate_64c_simsmall.tra.bz2"},
-{ label=>"swaptions simlarge (3.0G)    ",name=>"swaptions_64c_simlarge.tra.bz2"    ,url=>"https://www.cs.utexas.edu/~netrace/download/swaptions_64c_simlarge.tra.bz2"},
-{ label=>"vips simmedium (3.1G)        ",name=>"vips_64c_simmedium.tra.bz2"        ,url=>"https://www.cs.utexas.edu/~netrace/download/vips_64c_simmedium.tra.bz2"},
-{ label=>"x264 simmedium (5.1G)        ",name=>"x264_64c_simmedium.tra.bz2"        ,url=>"https://www.cs.utexas.edu/~netrace/download/x264_64c_simmedium.tra.bz2"},
-{ label=>"x264 simsmall (1.2G)         ",name=>"x264_64c_simsmall.tra.bz2"         ,url=>"https://www.cs.utexas.edu/~netrace/download/x264_64c_simsmall.tra.bz2"},
-);
-
-	my $row=0;
-	
-
-	foreach my $d (@links){
-		my $srow=$row;
-		$table-> attach (gen_label_in_left($d->{label}) , 0, 1,  $row,$row+1,'expand','shrink',2,2); 
-		my $file="$path/$d->{name}";
-		if (-f $file){
-			
-		}else{
-			my $download=def_image_button("icons/download.png",'Download');	
-			$table-> attach ($download , 2, 3,  $row,$row+1,'expand','shrink',2,2);
-			$download->signal_connect("clicked"=> sub{
-					$download ->set_sensitive (FALSE);
-					my $load= show_gif("icons/load.gif");
-				    $table->attach ($load, 1, 2, $srow,$srow+ 1,'shrink','shrink',0,0); 
-				    $load->show_all;
-					my $o=$d->{name};					
-					download_from_google_drive("$d->{url}" ,"$path/$o"  );
-					$load->destroy;
-					$download->destroy if (-f $file);
-			});
-		}
-		$row++;
-	}
-
-
-
-
-
-$window ->add($scrolled_win);
-$window->show_all;
-
-}
+    my ($path) =@_;
+    #create path if it is not exist
+    unless (-d $path){
+        mkpath("$path",1,01777);
+    }
+    my $window = def_popwin_size(30,85,"Netrace download",'percent');
+    my $table = def_table(1, 1, FALSE);    
+    my $scrolled_win = add_widget_to_scrolled_win($table);
+    my @links =(
+    { label=>"blackscholes simlarge (907M) ",name=>"blackscholes_64c_simlarge.tra.bz2" ,url=>"https://www.cs.utexas.edu/~netrace/download/blackscholes_64c_simlarge.tra.bz2"},
+    { label=>"blackscholes simmedium (182M)",name=>"blackscholes_64c_simmedium.tra.bz2",url=>"https://www.cs.utexas.edu/~netrace/download/blackscholes_64c_simmedium.tra.bz2"},
+    { label=>"blackscholes simsmall (55M)  ",name=>"blackscholes_64c_simsmall.tra.bz2" ,url=>"https://www.cs.utexas.edu/~netrace/download/blackscholes_64c_simsmall.tra.bz2"},
+    { label=>"bodytrack simlarge (3.5G)    ",name=>"bodytrack_64c_simlarge.tra.bz2"    ,url=>"https://www.cs.utexas.edu/~netrace/download/bodytrack_64c_simlarge.tra.bz2"},
+    { label=>"canneal simmedium (3.5G)     ",name=>"canneal_64c_simmedium.tra.bz2"     ,url=>"https://www.cs.utexas.edu/~netrace/download/canneal_64c_simmedium.tra.bz2"},
+    { label=>"dedup simmedium (4.1G)       ",name=>"dedup_64c_simmedium.tra.bz2"       ,url=>"https://www.cs.utexas.edu/~netrace/download/dedup_64c_simmedium.tra.bz2"},
+    { label=>"ferret simmedium (2.7G)      ",name=>"ferret_64c_simmedium.tra.bz2"      ,url=>"https://www.cs.utexas.edu/~netrace/download/ferret_64c_simmedium.tra.bz2"},
+    { label=>"fluidanimate simlarge (1.8G) ",name=>"fluidanimate_64c_simlarge.tra.bz2" ,url=>"https://www.cs.utexas.edu/~netrace/download/fluidanimate_64c_simlarge.tra.bz2"},
+    { label=>"fluidanimate simmedium (677M)",name=>"fluidanimate_64c_simmedium.tra.bz2",url=>"https://www.cs.utexas.edu/~netrace/download/fluidanimate_64c_simmedium.tra.bz2"},
+    { label=>"fluidanimate simsmall (317M) ",name=>"fluidanimate_64c_simsmall.tra.bz2" ,url=>"https://www.cs.utexas.edu/~netrace/download/fluidanimate_64c_simsmall.tra.bz2"},
+    { label=>"swaptions simlarge (3.0G)    ",name=>"swaptions_64c_simlarge.tra.bz2"    ,url=>"https://www.cs.utexas.edu/~netrace/download/swaptions_64c_simlarge.tra.bz2"},
+    { label=>"vips simmedium (3.1G)        ",name=>"vips_64c_simmedium.tra.bz2"        ,url=>"https://www.cs.utexas.edu/~netrace/download/vips_64c_simmedium.tra.bz2"},
+    { label=>"x264 simmedium (5.1G)        ",name=>"x264_64c_simmedium.tra.bz2"        ,url=>"https://www.cs.utexas.edu/~netrace/download/x264_64c_simmedium.tra.bz2"},
+    { label=>"x264 simsmall (1.2G)         ",name=>"x264_64c_simsmall.tra.bz2"         ,url=>"https://www.cs.utexas.edu/~netrace/download/x264_64c_simsmall.tra.bz2"},
+    );
+    my $row=0;
+    foreach my $d (@links){
+        my $srow=$row;
+        $table-> attach (gen_label_in_left($d->{label}) , 0, 1,  $row,$row+1,'expand','shrink',2,2); 
+        my $file="$path/$d->{name}";
+        if (-f $file){
+        }else{
+            my $download=def_image_button("icons/download.png",'Download');    
+            $table-> attach ($download , 2, 3,  $row,$row+1,'expand','shrink',2,2);
+            $download->signal_connect("clicked"=> sub{
+                $download ->set_sensitive (FALSE);
+                my $load= show_gif("icons/load.gif");
+                $table->attach ($load, 1, 2, $srow,$srow+ 1,'shrink','shrink',0,0); 
+                $load->show_all;
+                my $o=$d->{name};                    
+                download_from_google_drive("$d->{url}" ,"$path/$o"  );
+                $load->destroy;
+                $download->destroy if (-f $file);
+            });
+        }
+        $row++;
+    }
+    $window ->add($scrolled_win);
+    $window->show_all;
+}
\ No newline at end of file
diff --git a/mpsoc/perl_gui/lib/perl/soc_gen.pl b/mpsoc/perl_gui/lib/perl/soc_gen.pl
index a89a0bc..f298e68 100755
--- a/mpsoc/perl_gui/lib/perl/soc_gen.pl
+++ b/mpsoc/perl_gui/lib/perl/soc_gen.pl
@@ -8,15 +8,12 @@
 use ip;
 use interface;
 use POSIX 'strtol';
-
 use File::Path;
 #use File::Find;
 use File::Copy;
 use File::Copy::Recursive qw(dircopy);
 use Cwd 'abs_path';
-
-
-require "widget.pl"; 
+require "widget.pl";
 require "verilog_gen.pl";
 require "readme_gen.pl";
 require "hdr_file_gen.pl";
@@ -24,1980 +21,1501 @@
 require "compile.pl";
 require "software_editor.pl";
 
- 
-
 sub is_hex {
     local $!;
     return ! (POSIX::strtol($_[0], 16))[1];
- }
-
+}
 ###############
 #   get_instance_id
-# return an instance id which is the module name with a unique number 
+# return an instance id which is the module name with a unique number
 #############
 sub get_instance_id{
-	my ($soc,$category,$module)=@_;
-	my @id_list= $soc->soc_get_all_instances_of_module($category,$module);
-	my $id=0;
-	my $instance_id="$module$id";
-	do {
-		$instance_id = "$module$id";
-		$id++;
-   	}while ((grep {$_ eq $instance_id} @id_list) ) ;
-	#print "$instance_id\n";
-	return ($instance_id,$id);
-
+    my ($soc,$category,$module)=@_;
+    my @id_list= $soc->soc_get_all_instances_of_module($category,$module);
+    my $id=0;
+    my $instance_id="$module$id";
+    do {
+        $instance_id = "$module$id";
+        $id++;
+    }while ((grep {$_ eq $instance_id} @id_list) ) ;
+    #print "$instance_id\n";
+    return ($instance_id,$id);
 }
 
-
-
 #################
 #  add_module_to_soc
 ###############
 sub add_module_to_soc{
-	my ($soc,$category,$module,$info)=@_;
-	my $ip = ip->lib_new ();
-	my ($instance_id,$id)= get_instance_id($soc,$category,$module);
-	
-	#add module instanance
-	my $result=$soc->soc_add_instance($instance_id,$category,$module,$ip);
-	
-	if($result == 0){
-		my $info_text= "Failed to add \"$instance_id\" to SoC. $instance_id is already exist.";	 
-		show_info($info,$info_text); 
-		return;
-	}
-	$soc->soc_add_instance_order($instance_id);
-	# Add IP version 
-	my $v=$ip->ip_get($category,$module,"version"); 
-	$v = 0 if(!defined $v);
-	#print "$v\n";
-	$soc->object_add_attribute($instance_id,"version",$v);
-	# Read default parameter from lib and add them to soc
-	my %param_default= $ip->get_param_default($category,$module);
-	
-	my $rr=$soc->soc_add_instance_param($instance_id,\%param_default);
-	if($rr == 0){
-		my $info_text= "Failed to add default parameter to \"$instance_id\".  $instance_id does not exist exist.";	 
-		show_info($info,$info_text); 
-		return;
-	}
-	my @r=$ip->ip_get_param_order($category,$module);
-	$soc->soc_add_instance_param_order($instance_id,\@r);
-	
-	get_module_parameter($soc,$ip,$instance_id);
-	undef $ip;
-	set_gui_status($soc,"refresh_soc",0);	
-} 
+    my ($soc,$category,$module,$info)=@_;
+    my $ip = ip->lib_new ();
+    my ($instance_id,$id)= get_instance_id($soc,$category,$module);
+    #add module instanance
+    my $result=$soc->soc_add_instance($instance_id,$category,$module,$ip);
+    if($result == 0){
+        my $info_text= "Failed to add \"$instance_id\" to SoC. $instance_id is already exist.";
+        show_info($info,$info_text);
+        return;
+    }
+    $soc->soc_add_instance_order($instance_id);
+    # Add IP version
+    my $v=$ip->ip_get($category,$module,"version");
+    $v = 0 if(!defined $v);
+    #print "$v\n";
+    $soc->object_add_attribute($instance_id,"version",$v);
+    # Read default parameter from lib and add them to soc
+    my %param_default= $ip->get_param_default($category,$module);
+    my $rr=$soc->soc_add_instance_param($instance_id,\%param_default);
+    if($rr == 0){
+        my $info_text= "Failed to add default parameter to \"$instance_id\".  $instance_id does not exist exist.";
+        show_info($info,$info_text);
+        return;
+    }
+    my @r=$ip->ip_get_param_order($category,$module);
+    $soc->soc_add_instance_param_order($instance_id,\@r);
+    get_module_parameter($soc,$ip,$instance_id);
+    undef $ip;
+    set_gui_status($soc,"refresh_soc",0);
+}
+
 ################
-#	remove_instance_from_soc
+#    remove_instance_from_soc
 ################
 sub remove_instance_from_soc{
-	my ($soc,$instance_id)=@_;
-	$soc->soc_remove_instance($instance_id);
-	$soc->soc_remove_from_instance_order($instance_id);
-	set_gui_status($soc,"refresh_soc",0);
-}	
-
-
+    my ($soc,$instance_id)=@_;
+    $soc->soc_remove_instance($instance_id);
+    $soc->soc_remove_from_instance_order($instance_id);
+    set_gui_status($soc,"refresh_soc",0);
+}
 
 ###############
 #   get module_parameter
 ##############
-
 sub get_module_parameter{
-	my ($soc,$ip,$instance_id)=@_;
-	
-	#read module parameters from lib
-	my $module=$soc->soc_get_module($instance_id);
-	my $category=$soc->soc_get_category($instance_id);
-	my @parameters=$ip->ip_get_param_order($category,$module);
-	my $param_num = @parameters;
-	
-	#read soc parameters
-	my %param_value= $soc->soc_get_module_param($instance_id);
-	my %param_type=  $soc->soc_get_module_param_type($instance_id);
-	my %new_param_value=%param_value;
-	
-	
-	
-	#gui
-	my $table_size = ($param_num<10) ? 10 : $param_num;
-	my $window =  def_popwin_size(40,60, "Parameter setting for $module ",'percent');
-	my $table = def_table($table_size, 7, FALSE);
-	
-	my $scrolled_win = add_widget_to_scrolled_win($table);
-
-	my $row=0;
-	my $column=0;
-	
-	my $ok = def_image_button('icons/select.png','OK');
-	
-	my $at0= 'shrink';
-	my $at1= 'shrink';
-	
-	$table->attach (gen_label_in_left("Parameter name"),0, 2, $row, $row+1,$at0,$at1,2,2);
-	$table->attach (gen_label_in_left("Value"),2, 3, $row, $row+1,$at0,$at1,2,2);
-	my $param_info='Define how parameter will be included in the SoC/Tile top module containing this IP core. If you define it as "Parameter", its value can be changed at SoC/tile  instantiation time. So multiple different instancitaions of single SoC/tile can be used in MPSoC where each has its own parameter value';
-	$table->attach (gen_label_help($param_info,"Type"),3, 4, $row, $row+1,$at0,$at1,2,2);
-    
-	$row++;
-	foreach my $p (@parameters){
-		my ($default,$type,$content,$info,$vfile_param_type)= $ip->ip_get_parameter($category,$module,$p);
-		my $show = ($type ne "Fixed");
-		if ($show){
-			my $default_type=  "Localparam";
-			$default_type=$param_type{$p} if(defined $param_type{$p});
-			my $combo = gen_combobox_object($soc,'current_module_param_type',$p,"Parameter,Localparam",$default_type,undef,undef);
-			$table->attach ($combo,3, 4, $row, $row+1,$at0,$at1,2,2) if($vfile_param_type ne 'Parameter' && $category ne 'NoC' && $p ne 'WB_Aw' );
-		}
-		$default= $param_value{$p} if(defined $param_value{$p});
-		($row,$column)=add_param_widget($soc,$p,$p, $default,$type,$content,$info, $table,$row,$column,$show,'current_module_param',undef,undef,'vertical');
-	   
-	}
-	
-	
-	
-	
-	my $mtable = def_table(10, 1, FALSE);
-
-	$mtable->attach_defaults($scrolled_win,0,1,0,9);
-	$mtable->attach($ok,0,1,9,10,'expand','fill',2,2);
-	
-	$window->add ($mtable);
-	$window->show_all();
-	
-	$ok-> signal_connect("clicked" => sub{ 
-		$window->destroy;
-		#save new values 
-		my $ref=$soc->object_get_attribute('current_module_param');
-		if(defined $ref){
-			%new_param_value=%{$ref} ;
-			$soc->soc_add_instance_param($instance_id,\%new_param_value);
-		}
-		$ref=$soc->object_get_attribute('current_module_param_type');
-		if(defined $ref){
-			%new_param_value=%{$ref} ;
-			$soc->soc_add_instance_param_type($instance_id,\%new_param_value);
-		}
-		
-		
-		
-		#check if wishbone address bus is parameterizable regenerate the addresses again 
-		my @plugs= $soc->soc_get_all_plugs_of_an_instance($instance_id);
-		foreach my $plug (@plugs){
-			if ($plug eq 'wb_slave'){
-				my @nums=$soc->soc_list_plug_nums($instance_id,$plug);
-				foreach my $plug_num (@nums){					
-					my ($addr_connect,$base,$end,$name,$connect_id,$connect_socket,$connect_socket_num)=$soc->soc_get_plug($instance_id,$plug,$plug_num);
-					if($connect_id ne 'IO' && $connect_id ne 'NC'){
-						#print "$connect_id : soc_get_plug_addr ($instance_id,$plug,$plug_num)\n";
-						#remove old wb addr
-						$soc->soc_add_plug_base_addr($instance_id,$plug,$plug_num,undef,undef);
-						#get base and address width
-						my ($addr , $width)=$soc->soc_get_plug_addr ($instance_id,$plug,$plug_num);
-						#check if width is a parameter
-						my $val= get_parameter_final_value($soc,$instance_id,$width);
-						$width= $val if(defined $val);
-						#allocate new address in $connect_id
-						my ($base,$end)=get_wb_address($soc,$connect_id,$addr,$width);
-						if(defined $base){#save it
-							$soc->soc_add_plug_base_addr($instance_id,$plug,$plug_num,$base,$end);
-						}
-					}
-				}#plug_num
-			}#if
-		}#plugs
-		$soc->object_add_attribute('current_module_param',undef,undef);
-		$soc->object_add_attribute('current_module_param_type',undef,undef);
-		set_gui_status($soc,"refresh_soc",0);
-		
-		});
+    my ($soc,$ip,$instance_id)=@_;
+    #read module parameters from lib
+    my $module=$soc->soc_get_module($instance_id);
+    my $category=$soc->soc_get_category($instance_id);
+    my @parameters=$ip->ip_get_param_order($category,$module);
+    my $param_num = @parameters;
+    #read soc parameters
+    my %param_value= $soc->soc_get_module_param($instance_id);
+    my %param_type=  $soc->soc_get_module_param_type($instance_id);
+    my %new_param_value=%param_value;
+    #gui
+    my $table_size = ($param_num<10) ? 10 : $param_num;
+    my $window =  def_popwin_size(40,60, "Parameter setting for $module ",'percent');
+    my $table = def_table($table_size, 7, FALSE);
+    my $scrolled_win = add_widget_to_scrolled_win($table);
+    my $row=0;
+    my $column=0;
+    my $ok = def_image_button('icons/select.png','OK');
+    my $at0= 'shrink';
+    my $at1= 'shrink';
+    $table->attach (gen_label_in_left("Parameter name"),0, 2, $row, $row+1,$at0,$at1,2,2);
+    $table->attach (gen_label_in_left("Value"),2, 3, $row, $row+1,$at0,$at1,2,2);
+    my $param_info='Define how parameter will be included in the SoC/Tile top module containing this IP core. If you define it as "Parameter", its value can be changed at SoC/tile  instantiation time. So multiple different instancitaions of single SoC/tile can be used in MPSoC where each has its own parameter value';
+    $table->attach (gen_label_help($param_info,"Type"),3, 4, $row, $row+1,$at0,$at1,2,2);
+    $row++;
+    foreach my $p (@parameters){
+        my ($default,$type,$content,$info,$vfile_param_type)= $ip->ip_get_parameter($category,$module,$p);
+        my $show = ($type ne "Fixed");
+        if ($show){
+            my $default_type=  "Localparam";
+            $default_type=$param_type{$p} if(defined $param_type{$p});
+            my $combo = gen_combobox_object($soc,'current_module_param_type',$p,"Parameter,Localparam",$default_type,undef,undef);
+            $table->attach ($combo,3, 4, $row, $row+1,$at0,$at1,2,2) if($vfile_param_type ne 'Parameter' && $category ne 'NoC' && $p ne 'WB_Aw' );
+        }
+        $default= $param_value{$p} if(defined $param_value{$p});
+        ($row,$column)=add_param_widget($soc,$p,$p, $default,$type,$content,$info, $table,$row,$column,$show,'current_module_param',undef,undef,'vertical');
+    }
+    my $mtable = def_table(10, 1, FALSE);
+    $mtable->attach_defaults($scrolled_win,0,1,0,9);
+    $mtable->attach($ok,0,1,9,10,'expand','fill',2,2);
+    $window->add ($mtable);
+    $window->show_all();
+    $ok-> signal_connect("clicked" => sub{
+        $window->destroy;
+        #save new values
+        my $ref=$soc->object_get_attribute('current_module_param');
+        if(defined $ref){
+            %new_param_value=%{$ref} ;
+            $soc->soc_add_instance_param($instance_id,\%new_param_value);
+        }
+        $ref=$soc->object_get_attribute('current_module_param_type');
+        if(defined $ref){
+            %new_param_value=%{$ref} ;
+            $soc->soc_add_instance_param_type($instance_id,\%new_param_value);
+        }
+        #check if wishbone address bus is parameterizable regenerate the addresses again
+        my @plugs= $soc->soc_get_all_plugs_of_an_instance($instance_id);
+        foreach my $plug (@plugs){
+            if ($plug eq 'wb_slave'){
+                my @nums=$soc->soc_list_plug_nums($instance_id,$plug);
+                foreach my $plug_num (@nums){
+                    my ($addr_connect,$base,$end,$name,$connect_id,$connect_socket,$connect_socket_num)=$soc->soc_get_plug($instance_id,$plug,$plug_num);
+                    if($connect_id ne 'IO' && $connect_id ne 'NC'){
+                        #print "$connect_id : soc_get_plug_addr ($instance_id,$plug,$plug_num)\n";
+                        #remove old wb addr
+                        $soc->soc_add_plug_base_addr($instance_id,$plug,$plug_num,undef,undef);
+                        #get base and address width
+                        my ($addr , $width)=$soc->soc_get_plug_addr ($instance_id,$plug,$plug_num);
+                        #check if width is a parameter
+                        my $val= get_parameter_final_value($soc,$instance_id,$width);
+                        $width= $val if(defined $val);
+                        #allocate new address in $connect_id
+                        my ($base,$end)=get_wb_address($soc,$connect_id,$addr,$width);
+                        if(defined $base){#save it
+                            $soc->soc_add_plug_base_addr($instance_id,$plug,$plug_num,$base,$end);
+                        }
+                    }
+                }#plug_num
+            }#if
+        }#plugs
+        $soc->object_add_attribute('current_module_param',undef,undef);
+        $soc->object_add_attribute('current_module_param_type',undef,undef);
+        set_gui_status($soc,"refresh_soc",0);
+        });
 }
 
-
-
 ############
 #  param_box
 #
 ############
-
-
- sub param_box{
-	 my ($param, $default,$type,$content,$info, $value)=@_;
-	 my $box=def_hbox(TRUE,0);
-	 my $label =gen_label_in_left($param);
-	 $box->pack_start($label,FALSE,FALSE,3);
-	 
-	 if ($type eq "Entry"){
-		my $entry=gen_entry($default);
-		$box->pack_start($entry,FALSE,FALSE,3);
-		
-	 }
-	 elsif ($type eq "Combo-box"){
-		 my @combo_list=split(/\s*,\s*/,$content);
-		 my $pos=get_item_pos($default, @combo_list);
-		 my $combo=gen_combo(\@combo_list, $pos);
-		 $box->pack_start($combo,FALSE,FALSE,3);
-	 }
-	 elsif 	($type eq "Spin-button"){ 
-		  my ($min,$max,$step)=split(/\s*,\s*/,$content);
-		  $default=~ s/\D//g;
-		  $min=~ s/\D//g;
-		  $max=~ s/\D//g;
-		  $step=~ s/\D//g;
-		  my $spin=gen_spin($min,$max,$step);
-		  $box->pack_start($spin,FALSE,FALSE,3);
-		 # $box=def_label_spin_help_box ($param,$info, $value,$min,$max,$step, 2);
-	 }	 
-	
-	 return $box;
+sub param_box{
+    my ($param, $default,$type,$content,$info, $value)=@_;
+    my $box=def_hbox(TRUE,0);
+    my $label =gen_label_in_left($param);
+    $box->pack_start($label,FALSE,FALSE,3);
+    if ($type eq "Entry"){
+        my $entry=gen_entry($default);
+        $box->pack_start($entry,FALSE,FALSE,3);
+    }
+    elsif ($type eq "Combo-box"){
+        my @combo_list=split(/\s*,\s*/,$content);
+        my $pos=get_item_pos($default, @combo_list);
+        my $combo=gen_combo(\@combo_list, $pos);
+        $box->pack_start($combo,FALSE,FALSE,3);
+    }
+    elsif     ($type eq "Spin-button"){
+        my ($min,$max,$step)=split(/\s*,\s*/,$content);
+        $default=~ s/\D//g;
+        $min=~ s/\D//g;
+        $max=~ s/\D//g;
+        $step=~ s/\D//g;
+        my $spin=gen_spin($min,$max,$step);
+        $box->pack_start($spin,FALSE,FALSE,3);
+        # $box=def_label_spin_help_box ($param,$info, $value,$min,$max,$step, 2);
+    }
+    return $box;
 }
 
-
 ###############
 #  get_mathced_socket_pos
 ###############
-
-
 sub  get_mathced_socket_pos{
-	my ($soc,$instance_id,$plug,$plug_num,@connettions)=@_;	
-	my ($id,$socket,$num)=$soc->soc_get_module_plug_conection($instance_id,$plug,$plug_num);
-	my $pos=($id eq "IO")? 0: (scalar @connettions)-1;	
-	if($id ne "IO" && $id ne 'NC'){
-		my $name= $soc->soc_get_instance_name($id);
-		if (defined $name){
-			my $connect="$name\:$socket\[$num]"; 
-			if( grep {$_ eq $connect} @connettions){$pos = get_scolar_pos($connect,@connettions);}
-		}
-		else {
-			$soc->soc_add_instance_plug_conection($instance_id,$plug,$plug_num,"IO");
-			
-		}
-	}
-	return $pos;	
+    my ($soc,$instance_id,$plug,$plug_num,@connettions)=@_;
+    my ($id,$socket,$num)=$soc->soc_get_module_plug_conection($instance_id,$plug,$plug_num);
+    my $pos=($id eq "IO")? 0: (scalar @connettions)-1;
+    if($id ne "IO" && $id ne 'NC'){
+        my $name= $soc->soc_get_instance_name($id);
+        if (defined $name){
+            my $connect="$name\:$socket\[$num]";
+            if( grep {$_ eq $connect} @connettions){$pos = get_scolar_pos($connect,@connettions);}
+        }
+        else {
+            $soc->soc_add_instance_plug_conection($instance_id,$plug,$plug_num,"IO");
+        }
+    }
+    return $pos;
 }
 
-
 ##############
-#	gen_dev_box
+#    gen_dev_box
 ##############
-
 sub gen_instance{
-	my ($soc,$ip,$infc,$instance_id,$info,$table,$offset)=@_;
-
-	
-	
-#	my $box= def_vbox (FALSE,0);
-	
-#	my $table = def_table(3,5,TRUE);
-	my $data_in;
-	
-#column 1	
-	#module name
-	my $module=$soc->soc_get_module($instance_id);
-	my $category=$soc->soc_get_category($instance_id);
-	my $module_name_label=box_label(FALSE,0,$module);
-	my $box0=def_hbox(FALSE,5);
-	$box0->pack_start( $module_name_label, FALSE, FALSE, 3);
-
-	#module pdf
-	my $pdf=$soc->soc_get_description_pdf($instance_id);
-	if(defined $pdf){
-		my $b=def_image_button('icons/evince-icon.png');
-		$box0->pack_start( $b, FALSE, FALSE, 3);
-		$b->signal_connect ("clicked"  => sub{
-			my $dir = Cwd::getcwd();
-			my $project_dir	  = abs_path("$dir/../../"); #mpsoc directory address
-			#print "path ${project_dir}$pdf\n";
-			if (-f "${project_dir}$pdf"){
-				system qq (xdg-open ${project_dir}$pdf);
-			}elsif (-f "$pdf"){
-				system qq (xdg-open $pdf);
-			}else{
-				message_dialog("Error! $pdf or ${project_dir}$pdf did not find!\n",'error');	
-			}
-
-		});
-
-	}
-	$table->attach  ($box0,0,1,$offset+0,$offset+1,'expand','shrink',2,2);
-
-	#parameter setting button
-	my $param_button = def_image_button('icons/setting.png','Setting');
-	my $box1=def_hbox(FALSE,5);
-	my $up=def_image_button("icons/up_sim.png");
-	$box1->pack_start( $up, FALSE, FALSE, 3);
-	$box1->pack_start($param_button,   FALSE, FALSE,3);
-	$table->attach  ($box1 ,0,1,$offset+1,$offset+2,'expand','shrink',2,2);
-	$param_button->signal_connect (clicked => sub{
-		get_module_parameter($soc,$ip,$instance_id);	
-		
-	});
-	$up->signal_connect (clicked => sub{
-		$soc->soc_decrease_instance_order($instance_id);
-		set_gui_status($soc,"refresh_soc",0);
-		
-	});
-	
-	#remove button
-	#my ($box2,$cancel_button) = button_box("Remove");
-	
-	my $cancel_button=def_image_button('icons/cancel.png','Remove');
-	my $box2=def_hbox(FALSE,5);
-	
-	my $dwn=def_image_button("icons/down_sim.png");
-	$box2->pack_start( $dwn, FALSE, FALSE, 3);
-	$box2->pack_start($cancel_button,   FALSE, FALSE,3) ;
-	$table->attach  ($box2,0,1,$offset+2,$offset+3,'expand','shrink',2,2); 
-	$cancel_button->signal_connect (clicked => sub{
-		remove_instance_from_soc($soc,$instance_id);				
-	});	
-	
-	$dwn->signal_connect (clicked => sub{
-		$soc->soc_increase_instance_order($instance_id);
-		set_gui_status($soc,"refresh_soc",0);
-		
-	});	
-	
-	#instance name
-	my $instance_name=$soc->soc_get_instance_name($instance_id);
-	my $instance_label=gen_label_in_left(" Instance name");
-	my $instance_entry = gen_entry($instance_name);	
-	
-	$table->attach  ($instance_label,1,2,$offset+0,$offset+1,'expand','shrink',2,2);
-	#$table->attach_defaults ($instance_entry,1,2,$offset+1,$offset+2);
-
-
-	my $enter= def_image_button("icons/enter.png");
-	
-	my $box=def_pack_hbox(FALSE,0,$instance_entry );
-	$table->attach  ($box,1,2,$offset+1,$offset+2,'expand','shrink',2,2);
-
-	my ($old_v,$new_v)=  get_old_new_ip_version ($soc,$ip,$instance_id);
-	if($old_v != $new_v){
-		my $warn=def_image_button("icons/warning.png");
-		$table->attach  ($warn,1,2,$offset+2,$offset+3,'expand','shrink',2,2);  #$box2->pack_start($warn, FALSE, FALSE, 3);  
-		$warn->signal_connect (clicked => sub{
-			message_dialog("Warning: ${module}'s version (V.$old_v) mismatches with the one existing in library (V.$new_v). The generated system may not work correctly.  Please remove and then add $module again to update it with current version")
-				
-		});	
-
-
-	}
-	
-
-	$instance_entry->signal_connect ("activate"  => sub{
-		#print "changed\n";
-		my $new_name=$instance_entry->get_text();
-		#check if instance name exist in soc
-		set_gui_status($soc,"refresh_soc",1) if($instance_name eq $new_name );
-		my @instance_names= $soc->soc_get_all_instance_name();
-		if( grep {$_ eq $new_name} @instance_names){
-			print "$new_name exist\n";
-		}
-		else {
-		#add instance name to soc
-			$soc->soc_set_instance_name($instance_id,$new_name);
-		
-			set_gui_status($soc,"refresh_soc",1);
-				
-		}	
-	});
-	my $change=0;
-	$instance_entry->signal_connect ("changed"  => sub{
-		if($change ==0){		
-			$box->pack_start( $enter, FALSE, FALSE, 0);
-			$box->show_all;
-			$change=1;
-		}
-
-	});
-	
-	$enter->signal_connect ("clicked"  => sub{
-		my $new_name=$instance_entry->get_text();
-		#check if instance name exist in soc
-		set_gui_status($soc,"refresh_soc",1) if($instance_name eq $new_name );
-		my @instance_names= $soc->soc_get_all_instance_name();
-		if( grep {$_ eq $new_name} @instance_names){
-			print "$new_name exist\n";
-		}
-		else {
-		#add instance name to soc
-			$soc->soc_set_instance_name($instance_id,$new_name);
-		
-			set_gui_status($soc,"refresh_soc",1);
-				
-		}	
-
-
-	});
-
-
-	
-	#interface_pluges
-	my %plugs = $ip->get_module_plugs_value($category,$module);
-	
-	##print "******* %plug=get_module_plugs_value($category,$module)*************\n";
-		#print Dumper (\%$ip);	
-	my $row=0;
-	foreach my $plug (sort keys %plugs) {
-		#print "******* $plug *************\n";
-		my $plug_num= $plugs{$plug};
-		for (my $k=0;$k<$plug_num;$k++){
-			
-			my @connettions=("IO");
-			my @connettions_name=("IO");
-			
-			my ($connection_num,$matched_soket)= $infc->get_plug($plug);
-					
-			
-			
-			my %connect_list= $soc->get_modules_have_this_socket($matched_soket);
-			foreach my $id(sort keys %connect_list ){
-				if($instance_id ne $id){ # assume its forbidden to connect the socket and plug of same ip to each other
-					#generate socket list
-					my $name=$soc->soc_get_instance_name($id);
-					#check if its a number or parameter
-					my $param=$connect_list{$id};
-					my $value=$soc->soc_get_module_param_value($id,$param);
-					my $array_name=0;
-					if ( !length( $value || '' )) {
-						$value=$param;
-						$array_name=1;					
-						
-						
-					};
-					for(my $i=0; $i<$value; $i++){
-						my $s= "$name\:$matched_soket\[$i]";
-						push (@connettions,$s);
-						
-						# show sockets with their connected plugs 
-						my ($type_t,$value_t,$connection_num_t)=$soc->soc_get_socket_of_instance($id,$matched_soket);
-							
-						my $cc=find_connection($soc,$id,$matched_soket,$i);
-						$cc= (!defined $cc )? '': 
-							 ($cc eq "$instance_id:$plug\[$k\]" || $connection_num_t eq 'multi connection')? '':  "->$cc";
-
-						if($array_name eq 0){
-							my $n= $soc->soc_get_socket_name($id,$matched_soket, 0);
-							
-							$n = (!defined $n)? $s:"$name\:$n\[$i]"; 
-							$n = "$n$cc";
-							push (@connettions_name,"$n");
-							
-						}else{
-							my $n= $soc->soc_get_socket_name($id,$matched_soket, $i);
-							
-							$n = (!defined $n)? $s:"$name\:$n"; 
-							$n = "$n$cc";
-							push (@connettions_name,"$n");
-							
-						}					
-						
-					}
-					
-				}	
-				
-			
-			}
-			push (@connettions,"NC");
-			push (@connettions_name,"NC");
-				
-			#print "connection is $connect for $p\n";
-			#my @socket_list= $soc_get_sockets();
-			
-			
-			my $pos= get_mathced_socket_pos($soc,$instance_id,$plug,$k,@connettions);
-			
-			#plug name
-			my $plug_name=	$soc->soc_get_plug_name($instance_id,$plug,$k);
-			if(! defined $plug_name ){$plug_name=($plug_num>1)?"$plug\[$k\]":$plug}
-			$plug_name="  $plug_name  ";
-			my($plug_box, $plug_combo)= def_h_labeled_combo_scaled($plug_name,\@connettions_name,$pos,1,2);
-			
-			#if($row>2){$table->resize ($row, 2);}
-			$table->attach ($plug_box,2,5,$row+$offset,$row+$offset+1,'fill','fill',2,2);	$row++;
-			
-			my $plug_num=$k;
-			my @ll=($soc,$instance_id,$plug,$info,$plug_num);
-			$plug_combo->signal_connect (changed => sub{
-				my $self=shift;
-				my $ref= shift;
-				my($soc,$instance_id,$plug,$info,$plug_num) = @{$ref};
-				my $connect_name=$plug_combo->get_active_text();
-				my $pos=get_item_pos($connect_name, @connettions_name);
-				my $connect=$connettions[$pos];
-				
-				
-				
-				my($intance_name,$socket,$num)= split("[:\[ \\]]", $connect);
-				my $id=$intance_name;# default IO or NC
-				if(($intance_name ne 'IO') && ($intance_name ne 'NC')){
-					
-					$id=$soc->soc_get_instance_id($intance_name);
-					my ($type,$value,$connection_num)=$soc->soc_get_socket_of_instance($id,$socket);
-					#print "\$$connection_num=$connection_num\n";
-					if($connection_num eq 'single connection'){# disconnect other plug from this soket
-						my ($ref1,$ref2)= $soc->soc_get_modules_plug_connected_to_socket($id,$socket,$num);
-						my %connected_plugs=%$ref1;
-						my %connected_plug_nums=%$ref2;
-						foreach my $p (sort keys %connected_plugs) {
-							#%pp{$instance_id}=$plug
-							$soc->soc_add_instance_plug_conection($p,$connected_plugs{$p},$connected_plug_nums{$p},'IO');
-							my $info_text="$id\:$socket\[$num\] support only single connection.  The previous connection to $p:$connected_plugs{$p}\[$connected_plug_nums{$p}] has been removed.";
-							show_info($info, $info_text);
-						}
-						
-					}
-				}
-				#print "$id \n $connect \n$num\n";
-				#my @rr=$soc->soc_get_all_plugs_of_an_instance($id);
-				
-				
-			
-				
-				$soc->soc_add_instance_plug_conection($instance_id,$plug,$plug_num,$id,$socket,$num);
-				
-				#get address for wishbone slave port
-				if ($plug eq 'wb_slave'){
-						#remove old wb addr
-						$soc->soc_add_plug_base_addr($instance_id,$plug,$plug_num,undef,undef);
-						
-						#get base and address width
-						my ($addr , $width)=$soc->soc_get_plug_addr ($instance_id,$plug,$plug_num);
-						
-						#check if width is a parameter
-						my $val= get_parameter_final_value($soc,$instance_id,$width);
-						#print "my $val= get_parameter_final_value($soc,$instance_id,$width);\n";
-						$width= $val if(defined $val);
-						
-							
-						#allocate new address in $id
-						my ($base,$end)=get_wb_address($soc,$id,$addr,$width);
-						if(defined $base){#save it
-							#print "($base,$end)\n";
-							$soc->soc_add_plug_base_addr($instance_id,$plug,$plug_num,$base,$end);
-						}
-						
-						
-						#$id
-				}	
-				# "$name\:$connect\[$i]";
-				
-			
-			
-				set_gui_status($soc,"refresh_soc",0);
-			},\@ll);
-			
-	
-	}#for $plug_num
-		
-	}#foreach plug
-	
-	
-	if($row<3) {$row=3;}
-	add_Hsep_to_table ($table,0,5,$row+$offset);$row++;
-
-	return ($offset+$row);
-}	
-
+    my ($soc,$ip,$infc,$instance_id,$info,$table,$offset)=@_;
+#    my $box= def_vbox (FALSE,0);
+#    my $table = def_table(3,5,TRUE);
+    my $data_in;
+#column 1
+    #module name
+    my $module=$soc->soc_get_module($instance_id);
+    my $category=$soc->soc_get_category($instance_id);
+    my $module_name_label=box_label(FALSE,0,$module);
+    my $box0=def_hbox(FALSE,5);
+    $box0->pack_start( $module_name_label, FALSE, FALSE, 3);
+    #module pdf
+    my $pdf=$soc->soc_get_description_pdf($instance_id);
+    if(defined $pdf){
+        my $b=def_image_button('icons/evince-icon.png');
+        $box0->pack_start( $b, FALSE, FALSE, 3);
+        $b->signal_connect ("clicked"  => sub{
+            my $dir = Cwd::getcwd();
+            my $project_dir      = abs_path("$dir/../../"); #mpsoc directory address
+            #print "path ${project_dir}$pdf\n";
+            if (-f "${project_dir}$pdf"){
+                system qq (xdg-open ${project_dir}$pdf);
+            }elsif (-f "$pdf"){
+                system qq (xdg-open $pdf);
+            }else{
+                message_dialog("Error! $pdf or ${project_dir}$pdf did not find!\n",'error');
+            }
+        });
+    }
+    $table->attach  ($box0,0,1,$offset+0,$offset+1,'expand','shrink',2,2);
+    #parameter setting button
+    my $param_button = def_image_button('icons/setting.png','Setting');
+    my $box1=def_hbox(FALSE,5);
+    my $up=def_image_button("icons/up_sim.png");
+    $box1->pack_start( $up, FALSE, FALSE, 3);
+    $box1->pack_start($param_button,   FALSE, FALSE,3);
+    $table->attach  ($box1 ,0,1,$offset+1,$offset+2,'expand','shrink',2,2);
+    $param_button->signal_connect (clicked => sub{
+        get_module_parameter($soc,$ip,$instance_id);
+    });
+    $up->signal_connect (clicked => sub{
+        $soc->soc_decrease_instance_order($instance_id);
+        set_gui_status($soc,"refresh_soc",0);
+    });
+    #remove button
+    #my ($box2,$cancel_button) = button_box("Remove");
+    my $cancel_button=def_image_button('icons/cancel.png','Remove');
+    my $box2=def_hbox(FALSE,5);
+    my $dwn=def_image_button("icons/down_sim.png");
+    $box2->pack_start( $dwn, FALSE, FALSE, 3);
+    $box2->pack_start($cancel_button,   FALSE, FALSE,3) ;
+    $table->attach  ($box2,0,1,$offset+2,$offset+3,'expand','shrink',2,2);
+    $cancel_button->signal_connect (clicked => sub{
+        remove_instance_from_soc($soc,$instance_id);
+    });
+    $dwn->signal_connect (clicked => sub{
+        $soc->soc_increase_instance_order($instance_id);
+        set_gui_status($soc,"refresh_soc",0);
+    });
+    #instance name
+    my $instance_name=$soc->soc_get_instance_name($instance_id);
+    my $instance_label=gen_label_in_left(" Instance name");
+    my $instance_entry = gen_entry($instance_name);
+    $table->attach  ($instance_label,1,2,$offset+0,$offset+1,'expand','shrink',2,2);
+    #$table->attach_defaults ($instance_entry,1,2,$offset+1,$offset+2);
+    my $enter= def_image_button("icons/enter.png");
+    my $box=def_pack_hbox(FALSE,0,$instance_entry );
+    $table->attach  ($box,1,2,$offset+1,$offset+2,'expand','shrink',2,2);
+    my ($old_v,$new_v)=  get_old_new_ip_version ($soc,$ip,$instance_id);
+    if($old_v != $new_v){
+        my $warn=def_image_button("icons/warning.png");
+        $table->attach  ($warn,1,2,$offset+2,$offset+3,'expand','shrink',2,2);  #$box2->pack_start($warn, FALSE, FALSE, 3);
+        $warn->signal_connect (clicked => sub{
+            message_dialog("Warning: ${module}'s version (V.$old_v) mismatches with the one existing in library (V.$new_v). The generated system may not work correctly.  Please remove and then add $module again to update it with current version")
+        });
+    }
+    $instance_entry->signal_connect ("activate"  => sub{
+        #print "changed\n";
+        my $new_name=$instance_entry->get_text();
+        #check if instance name exist in soc
+        set_gui_status($soc,"refresh_soc",1) if($instance_name eq $new_name );
+        my @instance_names= $soc->soc_get_all_instance_name();
+        if( grep {$_ eq $new_name} @instance_names){
+            print "$new_name exist\n";
+        }
+        else {
+        #add instance name to soc
+            $soc->soc_set_instance_name($instance_id,$new_name);
+            set_gui_status($soc,"refresh_soc",1);
+        }
+    });
+    my $change=0;
+    $instance_entry->signal_connect ("changed"  => sub{
+        if($change ==0){
+            $box->pack_start( $enter, FALSE, FALSE, 0);
+            $box->show_all;
+            $change=1;
+        }
+    });
+    $enter->signal_connect ("clicked"  => sub{
+        my $new_name=$instance_entry->get_text();
+        #check if instance name exist in soc
+        set_gui_status($soc,"refresh_soc",1) if($instance_name eq $new_name );
+        my @instance_names= $soc->soc_get_all_instance_name();
+        if( grep {$_ eq $new_name} @instance_names){
+            print "$new_name exist\n";
+        }
+        else {
+        #add instance name to soc
+            $soc->soc_set_instance_name($instance_id,$new_name);
+            set_gui_status($soc,"refresh_soc",1);
+        }
+    });
+    #interface_pluges
+    my %plugs = $ip->get_module_plugs_value($category,$module);
+    ##print "******* %plug=get_module_plugs_value($category,$module)*************\n";
+        #print Dumper (\%$ip);
+    my $row=0;
+    foreach my $plug (sort keys %plugs) {
+        #print "******* $plug *************\n";
+        my $plug_num= $plugs{$plug};
+        for (my $k=0;$k<$plug_num;$k++){
+            my @connettions=("IO");
+            my @connettions_name=("IO");
+            my ($connection_num,$matched_soket)= $infc->get_plug($plug);
+            my %connect_list= $soc->get_modules_have_this_socket($matched_soket);
+            foreach my $id(sort keys %connect_list ){
+                if($instance_id ne $id){ # assume its forbidden to connect the socket and plug of same ip to each other
+                    #generate socket list
+                    my $name=$soc->soc_get_instance_name($id);
+                    #check if its a number or parameter
+                    my $param=$connect_list{$id};
+                    my $value=$soc->soc_get_module_param_value($id,$param);
+                    my $array_name=0;
+                    if ( !length( $value || '' )) {
+                        $value=$param;
+                        $array_name=1;
+                    };
+                    for(my $i=0; $i<$value; $i++){
+                        my $s= "$name\:$matched_soket\[$i]";
+                        push (@connettions,$s);
+                        # show sockets with their connected plugs
+                        my ($type_t,$value_t,$connection_num_t)=$soc->soc_get_socket_of_instance($id,$matched_soket);
+                        my $cc=find_connection($soc,$id,$matched_soket,$i);
+                        $cc= (!defined $cc )? '':
+                            ($cc eq "$instance_id:$plug\[$k\]" || $connection_num_t eq 'multi connection')? '':  "->$cc";
+                        if($array_name eq 0){
+                            my $n= $soc->soc_get_socket_name($id,$matched_soket, 0);
+                            $n = (!defined $n)? $s:"$name\:$n\[$i]";
+                            $n = "$n$cc";
+                            push (@connettions_name,"$n");
+                        }else{
+                            my $n= $soc->soc_get_socket_name($id,$matched_soket, $i);
+                            $n = (!defined $n)? $s:"$name\:$n";
+                            $n = "$n$cc";
+                            push (@connettions_name,"$n");
+                        }
+                    }
+                }
+            }
+            push (@connettions,"NC");
+            push (@connettions_name,"NC");
+            #print "connection is $connect for $p\n";
+            #my @socket_list= $soc_get_sockets();
+            my $pos= get_mathced_socket_pos($soc,$instance_id,$plug,$k,@connettions);
+            #plug name
+            my $plug_name=    $soc->soc_get_plug_name($instance_id,$plug,$k);
+            if(! defined $plug_name ){$plug_name=($plug_num>1)?"$plug\[$k\]":$plug}
+            $plug_name="  $plug_name  ";
+            my($plug_box, $plug_combo)= def_h_labeled_combo_scaled($plug_name,\@connettions_name,$pos,1,2);
+            #if($row>2){$table->resize ($row, 2);}
+            $table->attach ($plug_box,2,5,$row+$offset,$row+$offset+1,'fill','fill',2,2);    $row++;
+            my $plug_num=$k;
+            my @ll=($soc,$instance_id,$plug,$info,$plug_num);
+            $plug_combo->signal_connect (changed => sub{
+                my $self=shift;
+                my $ref= shift;
+                my($soc,$instance_id,$plug,$info,$plug_num) = @{$ref};
+                my $connect_name=$plug_combo->get_active_text();
+                my $pos=get_item_pos($connect_name, @connettions_name);
+                my $connect=$connettions[$pos];
+                my($intance_name,$socket,$num)= split("[:\[ \\]]", $connect);
+                my $id=$intance_name;# default IO or NC
+                if(($intance_name ne 'IO') && ($intance_name ne 'NC')){
+                    $id=$soc->soc_get_instance_id($intance_name);
+                    my ($type,$value,$connection_num)=$soc->soc_get_socket_of_instance($id,$socket);
+                    #print "\$$connection_num=$connection_num\n";
+                    if($connection_num eq 'single connection'){# disconnect other plug from this soket
+                        my ($ref1,$ref2)= $soc->soc_get_modules_plug_connected_to_socket($id,$socket,$num);
+                        my %connected_plugs=%$ref1;
+                        my %connected_plug_nums=%$ref2;
+                        foreach my $p (sort keys %connected_plugs) {
+                            #%pp{$instance_id}=$plug
+                            $soc->soc_add_instance_plug_conection($p,$connected_plugs{$p},$connected_plug_nums{$p},'IO');
+                            my $info_text="$id\:$socket\[$num\] support only single connection.  The previous connection to $p:$connected_plugs{$p}\[$connected_plug_nums{$p}] has been removed.";
+                            show_info($info, $info_text);
+                        }
+                    }
+                }
+                #print "$id \n $connect \n$num\n";
+                #my @rr=$soc->soc_get_all_plugs_of_an_instance($id);
+                $soc->soc_add_instance_plug_conection($instance_id,$plug,$plug_num,$id,$socket,$num);
+                #get address for wishbone slave port
+                if ($plug eq 'wb_slave'){
+                        #remove old wb addr
+                        $soc->soc_add_plug_base_addr($instance_id,$plug,$plug_num,undef,undef);
+                        #get base and address width
+                        my ($addr , $width)=$soc->soc_get_plug_addr ($instance_id,$plug,$plug_num);
+                        #check if width is a parameter
+                        my $val= get_parameter_final_value($soc,$instance_id,$width);
+                        #print "my $val= get_parameter_final_value($soc,$instance_id,$width);\n";
+                        $width= $val if(defined $val);
+                        #allocate new address in $id
+                        my ($base,$end)=get_wb_address($soc,$id,$addr,$width);
+                        if(defined $base){#save it
+                            #print "($base,$end)\n";
+                            $soc->soc_add_plug_base_addr($instance_id,$plug,$plug_num,$base,$end);
+                        }
+                        #$id
+                }
+                # "$name\:$connect\[$i]";
+                set_gui_status($soc,"refresh_soc",0);
+            },\@ll);
+    }#for $plug_num
+    }#foreach plug
+    if($row<3) {$row=3;}
+    add_Hsep_to_table ($table,0,5,$row+$offset);$row++;
+    return ($offset+$row);
+}
 
 sub find_connection{
-	my ($soc,$id,$socket,$num)=@_;
-	my ($ref1,$ref2)= $soc->soc_get_modules_plug_connected_to_socket($id,$socket,$num);
-	my %connected_plugs=%$ref1;
-	my %connected_plug_nums=%$ref2;
-	my $c;
-	foreach my $p (sort keys %connected_plugs) {
-				$c="$p:$connected_plugs{$p}\[$connected_plug_nums{$p}]" ;
-				#print "($instance_id,$plug,$plug_num);($p:$connected_plugs{$p}\[$connected_plug_nums{$p})\n";
-	}
-	return $c;
-
+    my ($soc,$id,$socket,$num)=@_;
+    my ($ref1,$ref2)= $soc->soc_get_modules_plug_connected_to_socket($id,$socket,$num);
+    my %connected_plugs=%$ref1;
+    my %connected_plug_nums=%$ref2;
+    my $c;
+    foreach my $p (sort keys %connected_plugs) {
+                $c="$p:$connected_plugs{$p}\[$connected_plug_nums{$p}]" ;
+                #print "($instance_id,$plug,$plug_num);($p:$connected_plugs{$p}\[$connected_plug_nums{$p})\n";
+    }
+    return $c;
 }
 
-
-
 ###############
-#	generate_dev_table
+#    generate_dev_table
 ############
 sub generate_dev_table{
-	my($soc,$ip,$infc,$info)=@_;	
-
-  
-	my $table=def_table(3,25,FALSE);
-	my $row=0;
-	my @instance_list=$soc->soc_get_instance_order();
-	if (scalar @instance_list ==0 ){
-		@instance_list=$soc->soc_get_all_instances();
-	}
-	my $i=0;
-	
-
-	
-	foreach my $instanc(@instance_list){
-		$row=gen_instance($soc,$ip,$infc,$instanc,$info,$table,$row);		
-	}
-	if($row<20){for ($i=$row; $i<20; $i++){
-				
-	}}	
-	
+    my($soc,$ip,$infc,$info)=@_;
+    my $table=def_table(3,25,FALSE);
+    my $row=0;
+    my @instance_list=$soc->soc_get_instance_order();
+    if (scalar @instance_list ==0 ){
+        @instance_list=$soc->soc_get_all_instances();
+    }
+    my $i=0;
+    foreach my $instanc(@instance_list){
+        $row=gen_instance($soc,$ip,$infc,$instanc,$info,$table,$row);
+    }
+    if($row<20){for ($i=$row; $i<20; $i++){
+    }}
+    return $table;
+}
 
-	return $table;
-}	
-	 
-	 
 ####################
 #  show_active_dev
 #
-################ 
-
+################
 sub show_active_dev{
-	my($soc,$ip,$infc,$info)=@_;
-	my $dev_table = generate_dev_table($soc,$ip,$infc,$info);
-	my $scrolled_win = gen_scr_win_with_adjst($soc,'device_win_adj');
-	add_widget_to_scrolled_win($dev_table,$scrolled_win);
-	return $scrolled_win;
-}	
-
-
-
-
-
-
-
+    my($soc,$ip,$infc,$info)=@_;
+    my $dev_table = generate_dev_table($soc,$ip,$infc,$info);
+    my $scrolled_win = gen_scr_win_with_adjst($soc,'device_win_adj');
+    add_widget_to_scrolled_win($dev_table,$scrolled_win);
+    return $scrolled_win;
+}
 
 sub show_select_ip_description {
-	my ($soc,$category,$module,$info)=@_;
-	my $ip = ip->lib_new ();
-  	my $describ=$ip->ip_get($category,$module,"description");
-	if($describ){
-		show_info($info,$describ);
-		
-	}
-	undef $ip;
+    my ($soc,$category,$module,$info)=@_;
+    my $ip = ip->lib_new ();
+      my $describ=$ip->ip_get($category,$module,"description");
+    if($describ){
+        show_info($info,$describ);
+    }
+    undef $ip;
 }
 
-
-
-
-
-
 sub get_all_files_list {
-	my ($soc,$list_name)=@_;
-	my @instances=$soc->soc_get_all_instances();
-	my $ip = ip->lib_new ();
-	my @files;
-	my $dir = Cwd::getcwd();
-	my $warnings;
-	#make target dir
-	my $project_dir	  = abs_path("$dir/../..");
-		
-	foreach my $id (@instances){
-		my $module 		=$soc->soc_get_module($id);
-		my $module_name	=$soc->soc_get_module_name($id);
-		my $category 	=$soc->soc_get_category($id);
-		my $inst   		=$soc->soc_get_instance_name($id);
-			
-		my @new=$ip->ip_get_list( $category,$module,$list_name);
-		#print "@new\n";
-		foreach my $f(@new){
-    			my $n="$project_dir$f";
-    			 if (!(-f "$n") && !(-f "$f" ) && !(-d "$n") && !(-d "$f" )     ){
-    			 	$warnings=(defined $warnings)? "$warnings WARNING: Can not find  \"$f\" which is required for \"$inst\" \n":"WARNING: Can not find  \"$f\"  which is required for \"$inst\"\n ";   
-     			 }
-    		}
-		@files=(@files,@new);
-	}
-	return \@files,$warnings;
+    my ($soc,$list_name)=@_;
+    my @instances=$soc->soc_get_all_instances();
+    my $ip = ip->lib_new ();
+    my @files;
+    my $dir = Cwd::getcwd();
+    my $warnings;
+    #make target dir
+    my $project_dir      = abs_path("$dir/../..");
+    foreach my $id (@instances){
+        my $module         =$soc->soc_get_module($id);
+        my $module_name    =$soc->soc_get_module_name($id);
+        my $category     =$soc->soc_get_category($id);
+        my $inst           =$soc->soc_get_instance_name($id);
+        my @new=$ip->ip_get_list( $category,$module,$list_name);
+        #print "@new\n";
+        foreach my $f(@new){
+                my $n="$project_dir$f";
+                if (!(-f "$n") && !(-f "$f" ) && !(-d "$n") && !(-d "$f" )     ){
+                    $warnings=(defined $warnings)? "$warnings WARNING: Can not find  \"$f\" which is required for \"$inst\" \n":"WARNING: Can not find  \"$f\"  which is required for \"$inst\"\n ";
+                }
+            }
+        @files=(@files,@new);
+    }
+    return \@files,$warnings;
 }
 
-
 sub add_to_project_file_list{
-		my ($files_ref,$files_path,$list_path )=@_;
-			my @new_file_ref;
-			foreach my $f(@{$files_ref}){
-				my ($name,$path,$suffix) = fileparse("$f",qr"\..[^.]*$");
-				push(@new_file_ref,"$files_path/$name$suffix");
-			}
-			my ($old_file_ref,$r,$err) = regen_object("$list_path/file_list" );
-			
-			if (defined $old_file_ref){
-				foreach my $f(@{$old_file_ref}){
-					unless ( grep( /^$f$/, @new_file_ref ) ){
-						push(@new_file_ref,$f);
-					}
-
-				}
-			}			
-			open(FILE,  ">$list_path/file_list") || die "Can not open: $!";
-			print FILE Data::Dumper->Dump([\@new_file_ref],['files']);
-			close(FILE) || die "Error closing file: $!"; 
+        my ($files_ref,$files_path,$list_path )=@_;
+            my @new_file_ref;
+            foreach my $f(@{$files_ref}){
+                my ($name,$path,$suffix) = fileparse("$f",qr"\..[^.]*$");
+                push(@new_file_ref,"$files_path/$name$suffix");
+            }
+            my ($old_file_ref,$r,$err) = regen_object("$list_path/file_list" );
+            if (defined $old_file_ref){
+                foreach my $f(@{$old_file_ref}){
+                    unless ( grep( /^$f$/, @new_file_ref ) ){
+                        push(@new_file_ref,$f);
+                    }
+                }
+            }
+            open(FILE,  ">$list_path/file_list") || die "Can not open: $!";
+            print FILE Data::Dumper->Dump([\@new_file_ref],['files']);
+            close(FILE) || die "Error closing file: $!";
 }
 
-
-
 ################
-#	generate_soc
+#    generate_soc
 #################
-
 sub generate_soc{
-	my ($soc,$info,$target_dir,$hw_path,$sw_path,$gen_top,$gen_hw_lib,$oldfiles,$multi_core)=@_;
-		my $name=$soc->object_get_attribute('soc_name');
-	    $oldfiles = "remove" if(!defined $oldfiles);
-		$multi_core = 0 if(!defined $multi_core);
-		my ($file_v,$top_v,$readme,$prog)=soc_generate_verilog($soc,$sw_path,$info);
-			
-		# Write object file
-		open(FILE,  ">lib/soc/$name.SOC") || die "Can not open: $!";
-		print FILE perl_file_header("$name.SOC");
-		print FILE Data::Dumper->Dump([\%$soc],['soc']);
-		close(FILE) || die "Error closing file: $!";
-			
-		# Write verilog file
-		my $h=autogen_warning().get_license_header("${name}.sv")."\n";
-		open(FILE,  ">lib/verilog/$name.sv") || die "Can not open: $!";
-		print FILE $h.$file_v;
-		close(FILE) || die "Error closing file: $!";
-			
-		# Write Top module file
-		if($gen_top){
-			my $l=autogen_warning().get_license_header("${name}_top.sv")."\n`timescale 1ns / 1ps\n";
-			open(FILE,  ">lib/verilog/${name}_top.sv") || die "Can not open: $!";
-			print FILE "$l\n$top_v";
-			close(FILE) || die "Error closing file: $!";
-		}
-			
-		# Write readme file
-		open(FILE,  ">lib/verilog/README") || die "Can not open: $!";
-		print FILE $readme;
-		close(FILE) || die "Error closing file: $!";
-
-
-		# Write memory prog file
-		open(FILE,  ">lib/verilog/write_memory.sh") || die "Can not open: $!";
-		print FILE $prog;
-		close(FILE) || die "Error closing file: $!";
-
-
+    my ($soc,$info,$target_dir,$hw_path,$sw_path,$gen_top,$gen_hw_lib,$oldfiles,$multi_core)=@_;
+        my $name=$soc->object_get_attribute('soc_name');
+        $oldfiles = "remove" if(!defined $oldfiles);
+        $multi_core = 0 if(!defined $multi_core);
+        my ($file_v,$top_v,$readme,$prog)=soc_generate_verilog($soc,$sw_path,$info);
+        # Write object file
+        open(FILE,  ">lib/soc/$name.SOC") || die "Can not open: $!";
+        print FILE perl_file_header("$name.SOC");
+        print FILE Data::Dumper->Dump([\%$soc],['soc']);
+        close(FILE) || die "Error closing file: $!";
+        # Write verilog file
+        my $h=autogen_warning().get_license_header("${name}.sv")."\n";
+        open(FILE,  ">lib/verilog/$name.sv") || die "Can not open: $!";
+        print FILE $h.$file_v;
+        close(FILE) || die "Error closing file: $!";
+        # Write Top module file
+        if($gen_top){
+            my $l=autogen_warning().get_license_header("${name}_top.sv")."\n`timescale 1ns / 1ps\n";
+            open(FILE,  ">lib/verilog/${name}_top.sv") || die "Can not open: $!";
+            print FILE "$l\n$top_v";
+            close(FILE) || die "Error closing file: $!";
+        }
+        # Write readme file
+        open(FILE,  ">lib/verilog/README") || die "Can not open: $!";
+        print FILE $readme;
+        close(FILE) || die "Error closing file: $!";
+        # Write memory prog file
+        open(FILE,  ">lib/verilog/write_memory.sh") || die "Can not open: $!";
+        print FILE $prog;
+        close(FILE) || die "Error closing file: $!";
         my $m_chain = $soc->object_get_attribute('JTAG','M_CHAIN');
-
-		#generate prog_mem
-		open(FILE,  ">lib/verilog/program.sh") || die "Can not open: $!";
-		print FILE soc_mem_prog($m_chain) if (defined $m_chain);
-		close(FILE) || die "Error closing file: $!";
-
-
-		
-		my $dir = Cwd::getcwd();
-		my $project_dir	  = abs_path("$dir/../../"); 		
-		if($gen_hw_lib){
-
-			#make target dir
-			my $hw_lib="$hw_path/lib";
-			my $hw_sim="$hw_path/../src_sim";
-			mkpath("$hw_lib/",1,01777);
-			mkpath("$sw_path/",1,01777);
-			mkpath("$hw_sim/",1,01777);
-			
-			if ($oldfiles eq "remove"){
-				#remove old rtl files that were copied by ProNoC
-				my ($old_file_ref,$r,$err) = regen_object("$hw_path/file_list");
-				if (defined $old_file_ref){		
-					remove_file_and_folders($old_file_ref,$target_dir);
-				}				
-			}
-			
-			#copy hdl codes in src_verilog			
-			my ($file_ref,$warnings)= get_all_files_list($soc,"hdl_files");	
-			my ($sim_ref,$warnings2)= get_all_files_list($soc,"hdl_files_ticked");
-			#file_ref-sim_ref
-			my @n= get_diff_array($file_ref,$sim_ref);
-			$file_ref=\@n;
-					
-			copy_file_and_folders($file_ref,$project_dir,$hw_lib);
-			show_colored_info($info,$warnings,'green')     		if(defined $warnings);			
-			add_to_project_file_list($file_ref,$hw_lib,$hw_path);
-			
-			
-			copy_file_and_folders($sim_ref,$project_dir,$hw_sim  );
-			show_colored_info($info,$warnings2,'green')     if(defined $warnings2);			
-			add_to_project_file_list($sim_ref,$hw_sim,$hw_path);
-			    
-			  
-			    
-			    
-    		#copy clk setting hdl codes in src_verilog
-    		my $sc_soc =get_source_set_top($soc,'soc');  
-  			($file_ref,$warnings)= get_all_files_list($sc_soc,"hdl_files");	
-  			($sim_ref,$warnings2)= get_all_files_list($soc,"hdl_files_ticked");
-			#file_ref-sim_ref
-			my @m= get_diff_array($file_ref,$sim_ref);
-			$file_ref=\@m;
-  			
-  				
-			copy_file_and_folders($file_ref,$project_dir,$hw_lib);
-			show_colored_info($info,$warnings,'green')     		if(defined $warnings);			
-			add_to_project_file_list($file_ref,$hw_lib,$hw_path);
-			
-			copy_file_and_folders($sim_ref,$project_dir,$hw_sim  );
-			show_colored_info($info,$warnings2,'green')     if(defined $warnings2);			
-			add_to_project_file_list($sim_ref,$hw_sim,$hw_path);
-    		
-			#copy jtag control files 
-			my @jtags=(("/mpsoc/rtl/src_peripheral/jtag/jtag_wb"),("jtag"));
-			copy_file_and_folders(\@jtags,$project_dir,$hw_lib); 
-			add_to_project_file_list(\@jtags,$hw_lib,$hw_path);  
-			 		
-			move ("$dir/lib/verilog/$name.sv","$hw_path/"); 
-			move ("$dir/lib/verilog/${name}_top.sv","$hw_path/"); 		
-			move ("$dir/lib/verilog/README" ,"$sw_path/");
-			move ("$dir/lib/verilog/write_memory.sh" ,"$sw_path/");
-			move ("$dir/lib/verilog/program.sh" ,"$sw_path/");
-		}
-		
-		#remove old software files that were copied by ProNoC
-		
-		my ($old_file_ref,$r,$err) = regen_object("$sw_path/file_list" );
-		if (defined $old_file_ref){		
-			remove_file_and_folders($old_file_ref,$project_dir);
-		}
-		
-		# Copy Software files
-		my ($file_ref,$warnings)= get_all_files_list($soc,"sw_files");
-		copy_file_and_folders($file_ref,$project_dir,$sw_path);
-		show_colored_info($info,$warnings,'green')     		if(defined $warnings);	
-		
-		my @new_file_ref;
-		foreach my $f(@{$file_ref}){
-			my ($name,$path,$suffix) = fileparse("$f",qr"\..[^.]*$");
-			push(@new_file_ref,"$sw_path/$name$suffix");
-		}
-		
-		push(@new_file_ref,"$sw_path/$name.h");
-    	open(FILE,  ">$sw_path/file_list") || die "Can not open: $!";
-		print FILE Data::Dumper->Dump([\@new_file_ref],['files']);
-		close(FILE) || die "Error closing file: $!";
-		
-			
-		# Write system.h and Software gen files
-		generate_header_file($soc,$project_dir,$sw_path,$hw_path,$dir);   			
-
-
-		# Write main.c file if not exist
-		my $n="$sw_path/main.c";
-		if (!(-f "$n")) { 
-			# Write main.c
-			open(FILE,  ">$n") || die "Can not open: $!";
-			print FILE '#define MULTI_CORE' if($multi_core);
-			print FILE main_c_template($name);
-			close(FILE) || die "Error closing file: $!";
-			
-			#write makefile source lib list file
-			open(FILE,  ">$sw_path/SOURCE_LIB") || die "Can not open: $!";
-			print FILE "SOURCE_LIB += $name.c ";
-			close(FILE) || die "Error closing file: $!";		
-			
-			
-		}
-		
-		#regenerate linker var file
-    	create_linker_var_file($soc);
-		
-			
-		#write perl_object_file 
-		mkpath("$target_dir/perl_lib/",1,01777);
-		open(FILE,  ">$target_dir/perl_lib/$name.SOC") || die "Can not open: $!";
-		print FILE perl_file_header("$name.SOC");
-		print FILE Data::Dumper->Dump([\%$soc],['soc']);		
-			
-
-}	
-
+        #generate prog_mem
+        open(FILE,  ">lib/verilog/program.sh") || die "Can not open: $!";
+        print FILE soc_mem_prog($m_chain) if (defined $m_chain);
+        close(FILE) || die "Error closing file: $!";
+        my $dir = Cwd::getcwd();
+        my $project_dir      = abs_path("$dir/../../");
+        if($gen_hw_lib){
+            #make target dir
+            my $hw_lib="$hw_path/lib";
+            my $hw_sim="$hw_path/../src_sim";
+            mkpath("$hw_lib/",1,01777);
+            mkpath("$sw_path/",1,01777);
+            mkpath("$hw_sim/",1,01777);
+            if ($oldfiles eq "remove"){
+                #remove old rtl files that were copied by ProNoC
+                my ($old_file_ref,$r,$err) = regen_object("$hw_path/file_list");
+                if (defined $old_file_ref){
+                    remove_file_and_folders($old_file_ref,$target_dir);
+                }
+            }
+            #copy hdl codes in src_verilog
+            my ($file_ref,$warnings)= get_all_files_list($soc,"hdl_files");
+            my ($sim_ref,$warnings2)= get_all_files_list($soc,"hdl_files_ticked");
+            #file_ref-sim_ref
+            my @n= get_diff_array($file_ref,$sim_ref);
+            $file_ref=\@n;
+            copy_file_and_folders($file_ref,$project_dir,$hw_lib);
+            show_colored_info($info,$warnings,'green')             if(defined $warnings);
+            add_to_project_file_list($file_ref,$hw_lib,$hw_path);
+            copy_file_and_folders($sim_ref,$project_dir,$hw_sim  );
+            show_colored_info($info,$warnings2,'green')     if(defined $warnings2);
+            add_to_project_file_list($sim_ref,$hw_sim,$hw_path);
+            #copy clk setting hdl codes in src_verilog
+            my $sc_soc =get_source_set_top($soc,'soc');
+            ($file_ref,$warnings)= get_all_files_list($sc_soc,"hdl_files");
+            ($sim_ref,$warnings2)= get_all_files_list($soc,"hdl_files_ticked");
+            #file_ref-sim_ref
+            my @m= get_diff_array($file_ref,$sim_ref);
+            $file_ref=\@m;
+            copy_file_and_folders($file_ref,$project_dir,$hw_lib);
+            show_colored_info($info,$warnings,'green')             if(defined $warnings);
+            add_to_project_file_list($file_ref,$hw_lib,$hw_path);
+            copy_file_and_folders($sim_ref,$project_dir,$hw_sim  );
+            show_colored_info($info,$warnings2,'green')     if(defined $warnings2);
+            add_to_project_file_list($sim_ref,$hw_sim,$hw_path);
+            #copy jtag control files
+            my @jtags=(("/mpsoc/rtl/src_peripheral/jtag/jtag_wb"),("jtag"));
+            copy_file_and_folders(\@jtags,$project_dir,$hw_lib);
+            add_to_project_file_list(\@jtags,$hw_lib,$hw_path);
+            move ("$dir/lib/verilog/$name.sv","$hw_path/");
+            move ("$dir/lib/verilog/${name}_top.sv","$hw_path/");
+            move ("$dir/lib/verilog/README" ,"$sw_path/");
+            move ("$dir/lib/verilog/write_memory.sh" ,"$sw_path/");
+            move ("$dir/lib/verilog/program.sh" ,"$sw_path/");
+        }
+        #remove old software files that were copied by ProNoC
+        my ($old_file_ref,$r,$err) = regen_object("$sw_path/file_list" );
+        if (defined $old_file_ref){
+            remove_file_and_folders($old_file_ref,$project_dir);
+        }
+        # Copy Software files
+        my ($file_ref,$warnings)= get_all_files_list($soc,"sw_files");
+        copy_file_and_folders($file_ref,$project_dir,$sw_path);
+        show_colored_info($info,$warnings,'green')             if(defined $warnings);
+        my @new_file_ref;
+        foreach my $f(@{$file_ref}){
+            my ($name,$path,$suffix) = fileparse("$f",qr"\..[^.]*$");
+            push(@new_file_ref,"$sw_path/$name$suffix");
+        }
+        push(@new_file_ref,"$sw_path/$name.h");
+        open(FILE,  ">$sw_path/file_list") || die "Can not open: $!";
+        print FILE Data::Dumper->Dump([\@new_file_ref],['files']);
+        close(FILE) || die "Error closing file: $!";
+        # Write system.h and Software gen files
+        generate_header_file($soc,$project_dir,$sw_path,$hw_path,$dir);
+        # Write main.c file if not exist
+        my $n="$sw_path/main.c";
+        if (!(-f "$n")) {
+            # Write main.c
+            open(FILE,  ">$n") || die "Can not open: $!";
+            print FILE '#define MULTI_CORE' if($multi_core);
+            print FILE main_c_template($name);
+            close(FILE) || die "Error closing file: $!";
+            #write makefile source lib list file
+            open(FILE,  ">$sw_path/SOURCE_LIB") || die "Can not open: $!";
+            print FILE "SOURCE_LIB += $name.c ";
+            close(FILE) || die "Error closing file: $!";
+        }
+        #regenerate linker var file
+        create_linker_var_file($soc);
+        #write perl_object_file
+        mkpath("$target_dir/perl_lib/",1,01777);
+        open(FILE,  ">$target_dir/perl_lib/$name.SOC") || die "Can not open: $!";
+        print FILE perl_file_header("$name.SOC");
+        print FILE Data::Dumper->Dump([\%$soc],['soc']);
+}
 
 sub main_c_template{
-	my $hdr=shift;
-	my $text="
+    my $hdr=shift;
+    my $text="
 #include \"$hdr.h\"
-
-
 // a simple delay function
 void delay ( unsigned int num ){
-	
-	while (num>0){ 
-		num--;
-		nop(); // asm volatile (\"nop\");
-	}
-	return;
-
+    while (num>0){
+        num--;
+        nop(); // asm volatile (\"nop\");
+    }
+    return;
 }
-
 int main(){
-	while(1){
-		
-	
-
-	}
-
+    while(1){
+    }
 return 0;
 }
-
 ";
-
-return $text;
-
-
+    return $text;
 }
 
-
-
-
-sub get_wb_address	{
-	my ($soc,$instance_id,$addr,$width)=@_;
-	my ($base,$end);
-	my @list= split (" ",$addr);
-	$base= hex ($list[0]);
-	$end= $base+(1 << $width)-1;
-	#print "$addr:$base \& $end\n";
-	my %taken_bases= $soc->soc_list_base_addreses($instance_id);
-	
-	my $conflict=0;
-	do{
-		$conflict=0;
-		foreach my $taken_end (sort {$a<=>$b} keys %taken_bases){
-			my $taken_base=$taken_bases{$taken_end};
-			#print "taken:($taken_base,$taken_end)\n";
-			if (($base <= $taken_base && $end >= $taken_base ) || ($base <= $taken_end && $end >= $taken_end )){
-			#if (!(($base < $taken_base && $end < $taken_end ) || ($base > $taken_base && $end > $taken_end ))){
-				 $conflict=1;
-				 $base+=(1 << $width)while($base<$taken_end);
-				# $base=$taken_end+1;
-				 
-				 $end= $base+(1 << $width)-1;				 
-				 last;
-				 
-			}
-		}	
-		
-	}while($conflict==1 && $end<(1 << 32));
-	if($conflict==0){
-		#print"new ($base,$end);\n";
-		return ($base,$end);
-		
-	}	
-	
-	return ;
-
-}	
-
-
+sub get_wb_address    {
+    my ($soc,$instance_id,$addr,$width)=@_;
+    my ($base,$end);
+    my @list= split (" ",$addr);
+    $base= hex ($list[0]);
+    $end= $base+(1 << $width)-1;
+    #print "$addr:$base \& $end\n";
+    my %taken_bases= $soc->soc_list_base_addreses($instance_id);
+    my $conflict=0;
+    do{
+        $conflict=0;
+        foreach my $taken_end (sort {$a<=>$b} keys %taken_bases){
+            my $taken_base=$taken_bases{$taken_end};
+            #print "taken:($taken_base,$taken_end)\n";
+            if (($base <= $taken_base && $end >= $taken_base ) || ($base <= $taken_end && $end >= $taken_end )){
+            #if (!(($base < $taken_base && $end < $taken_end ) || ($base > $taken_base && $end > $taken_end ))){
+                $conflict=1;
+                $base+=(1 << $width)while($base<$taken_end);
+                # $base=$taken_end+1;
+                $end= $base+(1 << $width)-1;
+                last;
+            }
+        }
+    }while($conflict==1 && $end<(1 << 32));
+    if($conflict==0){
+        #print"new ($base,$end);\n";
+        return ($base,$end);
+    }
+    return ;
+}
 
 #############
 #  set_unset_infc
 #############
-
 sub set_unset_infc{
-	my $soc =shift;
-	my $window = def_popwin_size(40,60,"Unconnected Socket Interfaces",'percent');
-	my $table = def_table(10,4, FALSE);	
-	my $scrolled_win = add_widget_to_scrolled_win($table);
-	my $row=0;
-	my $column=0;
-	
-	my $ip = ip->lib_new ();
-	my @instances=$soc->soc_get_all_instances();
-	foreach my $id (@instances){
-		my $module 	=$soc->soc_get_module($id);
-		my $module_name	=$soc->soc_get_module_name($id);
-		my $category 	=$soc->soc_get_category($id);
-		my $inst   	= $soc->soc_get_instance_name($id);
-		my @ports=$ip->ip_list_ports($category,$module);
-		foreach my $port (@ports){
-			my ($type,$range,$intfc_name,$i_port)=$ip->ip_get_port($category,$module,$port);
-			my($i_type,$i_name,$i_num) =split("[:\[ \\]]", $intfc_name);
-			if($i_type eq 'socket' && $i_name ne'wb_addr_map' && $i_name ne'jtag_to_wb'){ 				
-				my ($ref1,$ref2)= $soc->soc_get_modules_plug_connected_to_socket($id,$i_name,$i_num);
-				my %connected_plugs=%$ref1;
-				my %connected_plug_nums=%$ref2;
-				if(!%connected_plugs ){ 
-					my  ($s_type,$s_value,$s_connection_num)=$soc->soc_get_socket_of_instance($id,$i_name);
-					my $v=$soc->soc_get_module_param_value($id,$s_value);
-					if ( length( $v || '' ) || $category eq 'NoC' ){ }
-					else {
-						($row,$column)=add_param_widget ($soc,"$inst->$port","$inst-$port", 'IO','Combo-box',"IO,NC",undef, $table,$row,$column,1,"Unset-intfc",undef,undef,"vertical");
-						if($column == 0){
-							$column = 4;
-														
-							$row= $row-1;
-						}else{
-							$column =  0;
-							
-							
-							
-						}
-						
-					}
-					
-				}
-			}
-		}
-	}
-	
-	my $box1=def_hbox(FALSE, 1);
-	$box1->pack_start( gen_Vsep(), FALSE, FALSE, 3);	
-	$table->attach($box1,3,4,0,$row+1,'expand','fill',2,2);
-	my $ok = def_image_button('icons/select.png','OK');
-	$ok->signal_connect	( 'clicked'=> sub {
-		$window->destroy;
-	});
-	
-	my $mtable = def_table(10, 1, FALSE);
-	$mtable->attach_defaults($scrolled_win,0,1,0,9);
-	$mtable->attach($ok,0,1,9,10,'expand','fill',2,2);
-	$window->add ($mtable);
-	$window->show_all;
-	
-	
+    my $soc =shift;
+    my $window = def_popwin_size(40,60,"Unconnected Socket Interfaces",'percent');
+    my $table = def_table(10,4, FALSE);
+    my $scrolled_win = add_widget_to_scrolled_win($table);
+    my $row=0;
+    my $column=0;
+    my $ip = ip->lib_new ();
+    my @instances=$soc->soc_get_all_instances();
+    foreach my $id (@instances){
+        my $module     =$soc->soc_get_module($id);
+        my $module_name    =$soc->soc_get_module_name($id);
+        my $category     =$soc->soc_get_category($id);
+        my $inst       = $soc->soc_get_instance_name($id);
+        my @ports=$ip->ip_list_ports($category,$module);
+        foreach my $port (@ports){
+            my ($type,$range,$intfc_name,$i_port)=$ip->ip_get_port($category,$module,$port);
+            my($i_type,$i_name,$i_num) =split("[:\[ \\]]", $intfc_name);
+            if($i_type eq 'socket' && $i_name ne'wb_addr_map' && $i_name ne'jtag_to_wb'){
+                my ($ref1,$ref2)= $soc->soc_get_modules_plug_connected_to_socket($id,$i_name,$i_num);
+                my %connected_plugs=%$ref1;
+                my %connected_plug_nums=%$ref2;
+                if(!%connected_plugs ){
+                    my  ($s_type,$s_value,$s_connection_num)=$soc->soc_get_socket_of_instance($id,$i_name);
+                    my $v=$soc->soc_get_module_param_value($id,$s_value);
+                    if ( length( $v || '' ) || $category eq 'NoC' ){ }
+                    else {
+                        ($row,$column)=add_param_widget ($soc,"$inst->$port","$inst-$port", 'IO','Combo-box',"IO,NC",undef, $table,$row,$column,1,"Unset-intfc",undef,undef,"vertical");
+                        if($column == 0){
+                            $column = 4;
+                            $row= $row-1;
+                        }else{
+                            $column =  0;
+                        }
+                    }
+                }
+            }
+        }
+    }
+    my $box1=def_hbox(FALSE, 1);
+    $box1->pack_start( gen_Vsep(), FALSE, FALSE, 3);
+    $table->attach($box1,3,4,0,$row+1,'expand','fill',2,2);
+    my $ok = def_image_button('icons/select.png','OK');
+    $ok->signal_connect    ( 'clicked'=> sub {
+        $window->destroy;
+    });
+    my $mtable = def_table(10, 1, FALSE);
+    $mtable->attach_defaults($scrolled_win,0,1,0,9);
+    $mtable->attach($ok,0,1,9,10,'expand','fill',2,2);
+    $window->add ($mtable);
+    $window->show_all;
 }
 
-
-
-
-
 ##########
-#	wb address setting
+#    wb address setting
 #########
-
 sub wb_address_setting {
-	my $soc=shift;
-		
-	
-	my $window = def_popwin_size(80,50,"Wishbone slave port address setting",'percent');
-	my $table = def_table(10, 6, FALSE);
-	
-	my $scrolled_win = add_widget_to_scrolled_win($table);
-	my $row=0;
-	
-	#title
-	$table->attach(gen_label_in_left  ("Instance name"),0,1,$row,$row+1,'expand','shrink',2,2);
-	$table->attach(gen_label_in_left  ("Interface name"),1,2,$row,$row+1,'expand','shrink',2,2);
-	$table->attach(gen_label_in_left  ("Bus name"),2,3,$row,$row+1,'expand','shrink',2,2);
-	$table->attach(gen_label_in_center("Base address"),3,4,$row,$row+1,'expand','shrink',2,2);
-	$table->attach(gen_label_in_center("End address"),4,5,$row,$row+1,'expand','shrink',2,2);
-	$table->attach(gen_label_in_center("Size (Bytes)"),5,6,$row,$row+1,'expand','shrink',2,2);
-	
-	my (@newbase,@newend,@connects);
-	
-	$row++;
-	my @all_instances=$soc->soc_get_all_instances();
-	foreach my $instance_id (@all_instances){
-		my @plugs= $soc->soc_get_all_plugs_of_an_instance($instance_id);
-		foreach my $plug (@plugs){
-			my @nums=$soc->soc_list_plug_nums($instance_id,$plug);
-			foreach my $num (@nums){
-				my ($addr,$base,$end,$name,$connect_id,$connect_socket,$connect_socket_num)=$soc->soc_get_plug($instance_id,$plug,$num);
-				if((defined $connect_socket) && ($connect_socket eq 'wb_slave')){
-					my $number=$row-1;
-					$newbase[$number]=$base;
-					$newend[$number]=$end;
-					$connects[$number]=$connect_id;	
-					$row++;	
-				}#if
-			}#foreach my $num
-		}#foreach my $plug
-	}#foreach my $instance_id
+    my $soc=shift;
+    my $window = def_popwin_size(80,50,"Wishbone slave port address setting",'percent');
+    my $table = def_table(10, 6, FALSE);
+    my $scrolled_win = add_widget_to_scrolled_win($table);
+    my $row=0;
+    #title
+    $table->attach(gen_label_in_left  ("Instance name"),0,1,$row,$row+1,'expand','shrink',2,2);
+    $table->attach(gen_label_in_left  ("Interface name"),1,2,$row,$row+1,'expand','shrink',2,2);
+    $table->attach(gen_label_in_left  ("Bus name"),2,3,$row,$row+1,'expand','shrink',2,2);
+    $table->attach(gen_label_in_center("Base address"),3,4,$row,$row+1,'expand','shrink',2,2);
+    $table->attach(gen_label_in_center("End address"),4,5,$row,$row+1,'expand','shrink',2,2);
+    $table->attach(gen_label_in_center("Size (Bytes)"),5,6,$row,$row+1,'expand','shrink',2,2);
+    my (@newbase,@newend,@connects);
+    $row++;
+    my @all_instances=$soc->soc_get_all_instances();
+    foreach my $instance_id (@all_instances){
+        my @plugs= $soc->soc_get_all_plugs_of_an_instance($instance_id);
+        foreach my $plug (@plugs){
+            my @nums=$soc->soc_list_plug_nums($instance_id,$plug);
+            foreach my $num (@nums){
+                my ($addr,$base,$end,$name,$connect_id,$connect_socket,$connect_socket_num)=$soc->soc_get_plug($instance_id,$plug,$num);
+                if((defined $connect_socket) && ($connect_socket eq 'wb_slave')){
+                    my $number=$row-1;
+                    $newbase[$number]=$base;
+                    $newend[$number]=$end;
+                    $connects[$number]=$connect_id;
+                    $row++;
+                }#if
+            }#foreach my $num
+        }#foreach my $plug
+    }#foreach my $instance_id
+    my @status_all;
+    $row=1;
+    foreach my $instance_id (@all_instances){
+        my @plugs= $soc->soc_get_all_plugs_of_an_instance($instance_id);
+        foreach my $plug (@plugs){
+            my @nums=$soc->soc_list_plug_nums($instance_id,$plug);
+            foreach my $num (@nums){
+                my ($addr,$base,$end,$name,$connect_id,$connect_socket,$connect_socket_num)=$soc->soc_get_plug($instance_id,$plug,$num);
+                if((defined $connect_socket) && ($connect_socket eq 'wb_slave')){
+                    my $instance_name=$soc->soc_get_instance_name($instance_id);
+                    my $plug_name=
+                        (defined $name ) ? gen_label_in_left($name):
+                        gen_label_in_left("$plug\[$num\]");
+                    my $connected_instance_name= $soc->soc_get_instance_name($connect_id);
+                    my $number=$row-1;
+                    my $label1= gen_label_in_left("$number: $instance_name");
+                    my $label2= gen_label_in_left($connected_instance_name);
+                    my $entry1= gen_entry_new_with_max_length (10,sprintf("0x%08x", $base));
+                    my $entry2= gen_entry_new_with_max_length (10,sprintf("0x%08x", $end));
+                    my ($box,$valid) =addr_box_gen(sprintf("0x%08x", $base), sprintf("0x%08x", $end),\@newbase,\@newend,\@connects,$number);
+                    $status_all[$number]=$valid;
+                    $table->attach($label1,0,1,$row,$row+1,'expand','shrink',2,2);
+                    $table->attach($plug_name,1,2,$row,$row+1,'expand','shrink',2,2);
+                    $table->attach($label2,2,3,$row,$row+1,'expand','shrink',2,2);
+                    $table->attach($entry1,3,4,$row,$row+1,'expand','shrink',2,2);
+                    $table->attach($entry2,4,5,$row,$row+1,'expand','shrink',2,2);
+                    $table->attach($box,5,7,$row,$row+1,'expand','shrink',2,2);
+                    $entry1->signal_connect('changed'=>sub{
+                        my $base_in=$entry1->get_text();
+                        if (length($base_in)<2){ $entry1->set_text('0x')};
+                        my $end_in=$entry2->get_text();
+                        my $valid;
+                        $box->destroy;
+                        ($box,$valid)=addr_box_gen($base_in, $end_in,\@newbase,\@newend,\@connects,$number);
+                        $status_all[$number]=$valid;
+                        $table->attach($box,5,7,$number+1,$number+2,'expand','shrink',2,2);
+                        $table->show_all;
+                    } );
+                    $entry2->signal_connect('changed'=>sub{
+                        my $base_in=$entry1->get_text();
+                        my $end_in=$entry2->get_text();
+                        if (length($end_in)<2){ $entry2->set_text('0x')};
+                        my $valid;
+                        $box->destroy;
+                        ($box,$valid)=addr_box_gen($base_in, $end_in,\@newbase,\@newend,\@connects,$number);
+                        $status_all[$number]=$valid;
+                        $table->attach($box,5,7,$number+1,$number+2,'expand','shrink',2,2);
+                        $table->show_all;
+                    } );
+                    $row++;
+                }#if
+            }#foreach my $num
+        }#foreach my $plug
+    }#foreach my $instance_id
+    my $ok = def_image_button('icons/select.png','OK');
+    my $refresh = def_image_button('icons/revert.png','Revert');
+    my $refbox=def_hbox(TRUE,0);
+    $refbox->pack_start($refresh, FALSE, FALSE,0);
+    $refresh->signal_connect( 'clicked'=> sub {
+        $window->destroy;
+        wb_address_setting($soc);
+        });
+    $ok->signal_connect    ( 'clicked'=> sub {
+        my $st=1;
+        foreach my $valid (@status_all){
+            if($valid==0){
+                $st=0;
+            }
+        }
+        if($st==1){
+            $row=1;
+            foreach my $instance_id (@all_instances){
+            my @plugs= $soc->soc_get_all_plugs_of_an_instance($instance_id);
+            foreach my $plug (@plugs){
+                my @nums=$soc->soc_list_plug_nums($instance_id,$plug);
+                foreach my $num (@nums){
+                    my ($addr,$base,$end,$name,$connect_id,$connect_socket,$connect_socket_num)=$soc->soc_get_plug($instance_id,$plug,$num);
+                    if(defined $connect_socket && ($connect_socket eq 'wb_slave')){
+                        my $number=$row-1;
+                        $soc->soc_add_plug_base_addr($instance_id,$plug,$num,$newbase[$number],$newend[$number]);
+                        $row++;
+                    }#if
+                }#foreach my $num
+            }#foreach my $plug
+        }#foreach my $instance_id
+            $window->destroy;
+        }else{
+            message_dialog("Invalid address!",'error');
+        }
+        });
+    my $mtable = def_table(10, 2, FALSE);
+    $mtable->attach_defaults($scrolled_win,0,2,0,9);
+    $mtable->attach ($refbox,0,1,9,10,'expand','shrink',2,2);
+    $mtable->attach($ok,1,2,9,10,'expand','fill',2,2);
+    $window->add ($mtable);
+    $window->show_all;
+}
 
-	my @status_all;
-	$row=1;
-	foreach my $instance_id (@all_instances){
-		my @plugs= $soc->soc_get_all_plugs_of_an_instance($instance_id);
-		foreach my $plug (@plugs){
-			my @nums=$soc->soc_list_plug_nums($instance_id,$plug);
-			foreach my $num (@nums){
-				my ($addr,$base,$end,$name,$connect_id,$connect_socket,$connect_socket_num)=$soc->soc_get_plug($instance_id,$plug,$num);
-				if((defined $connect_socket) && ($connect_socket eq 'wb_slave')){
-					my $instance_name=$soc->soc_get_instance_name($instance_id);
-					my $plug_name=(defined $name ) ? gen_label_in_left($name):
-													 gen_label_in_left("$plug\[$num\]");
-							
-					my $connected_instance_name= $soc->soc_get_instance_name($connect_id);
-					my $number=$row-1;
-					my $label1= gen_label_in_left("$number: $instance_name");
-					my $label2= gen_label_in_left($connected_instance_name);
-					my $entry1= gen_entry_new_with_max_length (10,sprintf("0x%08x", $base));						
-					my $entry2= gen_entry_new_with_max_length (10,sprintf("0x%08x", $end));
-												
-					my ($box,$valid) =addr_box_gen(sprintf("0x%08x", $base), sprintf("0x%08x", $end),\@newbase,\@newend,\@connects,$number);
-					$status_all[$number]=$valid;
-							
-							
-					$table->attach($label1,0,1,$row,$row+1,'expand','shrink',2,2);
-					$table->attach($plug_name,1,2,$row,$row+1,'expand','shrink',2,2);
-					$table->attach($label2,2,3,$row,$row+1,'expand','shrink',2,2);
-					$table->attach($entry1,3,4,$row,$row+1,'expand','shrink',2,2);
-					$table->attach($entry2,4,5,$row,$row+1,'expand','shrink',2,2);
-							
-							
-					$table->attach($box,5,7,$row,$row+1,'expand','shrink',2,2);
-							
-							
-					$entry1->signal_connect('changed'=>sub{
-						my $base_in=$entry1->get_text();
-						if (length($base_in)<2){ $entry1->set_text('0x')};
-						my $end_in=$entry2->get_text();
-						my $valid;
-						$box->destroy;
-						($box,$valid)=addr_box_gen($base_in, $end_in,\@newbase,\@newend,\@connects,$number);
-						$status_all[$number]=$valid;
-						$table->attach($box,5,7,$number+1,$number+2,'expand','shrink',2,2);
-						$table->show_all;
-						
-								
-					} );
-					$entry2->signal_connect('changed'=>sub{
-						my $base_in=$entry1->get_text();
-						my $end_in=$entry2->get_text();
-						if (length($end_in)<2){ $entry2->set_text('0x')};
-						my $valid;
-						$box->destroy;
-						($box,$valid)=addr_box_gen($base_in, $end_in,\@newbase,\@newend,\@connects,$number);
-						$status_all[$number]=$valid;
-						$table->attach($box,5,7,$number+1,$number+2,'expand','shrink',2,2);	
-						$table->show_all;				
-					} );
-														
-							
-							
-					$row++;		
-							
-						
-				}#if
-			}#foreach my $num
-		}#foreach my $plug
-	}#foreach my $instance_id
-		
-	
-	my $ok = def_image_button('icons/select.png','OK');
-	
-	
-	
-	my $refresh = def_image_button('icons/revert.png','Revert');
-	my $refbox=def_hbox(TRUE,0);
-	$refbox->pack_start($refresh, FALSE, FALSE,0);
-			
-	$refresh->signal_connect( 'clicked'=> sub {
-		$window->destroy;
-		wb_address_setting($soc);
-		
-		
-		});
-	$ok->signal_connect	( 'clicked'=> sub {
-		my $st=1;
-		foreach my $valid (@status_all){ 
-			if($valid==0){
-				$st=0;
-				
-			} 
-		}
-		
-		if($st==1){
-			$row=1;
-			foreach my $instance_id (@all_instances){
-			my @plugs= $soc->soc_get_all_plugs_of_an_instance($instance_id);
-			foreach my $plug (@plugs){
-				my @nums=$soc->soc_list_plug_nums($instance_id,$plug);
-				foreach my $num (@nums){
-					my ($addr,$base,$end,$name,$connect_id,$connect_socket,$connect_socket_num)=$soc->soc_get_plug($instance_id,$plug,$num);
-					if(defined $connect_socket && ($connect_socket eq 'wb_slave')){
-						my $number=$row-1;
-						$soc->soc_add_plug_base_addr($instance_id,$plug,$num,$newbase[$number],$newend[$number]);
-						$row++;
-					}#if
-				}#foreach my $num
-			}#foreach my $plug
-		}#foreach my $instance_id
-			
-			
-			
-			
-			
-			$window->destroy;
-		}else{
-			message_dialog("Invalid address!",'error');
-			
-		}	
-		
-		
-		});
-		
-	
-	my $mtable = def_table(10, 2, FALSE);
-	$mtable->attach_defaults($scrolled_win,0,2,0,9);
-	$mtable->attach ($refbox,0,1,9,10,'expand','shrink',2,2);
-	$mtable->attach($ok,1,2,9,10,'expand','fill',2,2);
-	$window->add ($mtable);
-	$window->show_all;
-		
-	
-	
-	
-}	
 ##############
-#	addr_box_gen
+#    addr_box_gen
 ##############
-
 sub addr_box_gen{
-	my ($base_in, $end_in,$newbase_ref,$newend_ref,$connects_ref,$number)=@_;
-	my $box= def_hbox(TRUE,0);
-	my $label;
-	my $valid=1;
-	my $info;
-	if(is_hex($base_in) && is_hex($end_in)){
-		my $size=(hex ($end_in) >= hex ($base_in))? hex ($end_in) - hex ($base_in) +1 : 0;
-		my $size_text=	metric_conversion($size);
-		$label= gen_label_in_center($size_text);
-		$$newbase_ref[$number]=hex($base_in);
-		$$newend_ref[$number]=hex($end_in);
-		$info=check_entered_address($newbase_ref,$newend_ref,$connects_ref,$number);
-		if(defined 	$info) {$valid=0;}
-		
-	}
-	else {
-		$label= gen_label_in_center("Invalid hex value!");
-		$info="Invalid hex value!";
-		$valid=0;
-	}
-	
-	
-	my $status=(defined $info)? gen_button_message ($info,'icons/warning.png'):
-								gen_button_message (undef,'icons/select.png');
-							
-	$box->pack_start($label,FALSE,FALSE,3);
-	$box->pack_start($status,FALSE,FALSE,3);
-	return ($box,$valid);
-	
-}	
-
-
-
+    my ($base_in, $end_in,$newbase_ref,$newend_ref,$connects_ref,$number)=@_;
+    my $box= def_hbox(TRUE,0);
+    my $label;
+    my $valid=1;
+    my $info;
+    if(is_hex($base_in) && is_hex($end_in)){
+        my $size=(hex ($end_in) >= hex ($base_in))? hex ($end_in) - hex ($base_in) +1 : 0;
+        my $size_text=    metric_conversion($size);
+        $label= gen_label_in_center($size_text);
+        $$newbase_ref[$number]=hex($base_in);
+        $$newend_ref[$number]=hex($end_in);
+        $info=check_entered_address($newbase_ref,$newend_ref,$connects_ref,$number);
+        if(defined     $info) {$valid=0;}
+    }
+    else {
+        $label= gen_label_in_center("Invalid hex value!");
+        $info="Invalid hex value!";
+        $valid=0;
+    }
+    my $status=(defined $info)? gen_button_message ($info,'icons/warning.png'):
+                                gen_button_message (undef,'icons/select.png');
+    $box->pack_start($label,FALSE,FALSE,3);
+    $box->pack_start($status,FALSE,FALSE,3);
+    return ($box,$valid);
+}
 
 ###########
-#	get_parameter_final_value
+#    get_parameter_final_value
 ############
 sub get_parameter_final_value{
-	my ($soc,$id,$param)=@_;
-	#get ordered param
-	my @ordered_param=$soc->soc_get_instance_param_order($id);
-	my %sim_params;
-	foreach my $p (@ordered_param){
-		my $value=$soc->soc_get_module_param_value($id,$p);
-		#print "\n$value=\$soc->soc_get_module_param_value($id,$p)\n";
-		foreach my $q (sort keys %sim_params){
-			
-			$value=replace_value($value,$q,$sim_params{$q}) if (defined $value);
-			
-			
-		}
-		$sim_params{$p}=$value;
-		#print "\$sim_params{$p}=$value;\n";
-	}
-	return $sim_params{$param};
-}	
-	
-	
-	
-	
-sub replace_value{
-	my ($string,$param,$value)=@_;
-
-	my $new_string=$string;
-	#print "$new_range\n";
-	my $new_param= $value;
-	($new_string=$new_string)=~ s/\b$param\b/$new_param/g;
-	my $new_val = eval $new_string;
-	return $new_val if (defined $new_val);
-	return $string;
-		
-}	
-
-
-
+    my ($soc,$id,$param)=@_;
+    #get ordered param
+    my @ordered_param=$soc->soc_get_instance_param_order($id);
+    my %sim_params;
+    foreach my $p (@ordered_param){
+        my $value=$soc->soc_get_module_param_value($id,$p);
+        #print "\n$value=\$soc->soc_get_module_param_value($id,$p)\n";
+        foreach my $q (sort keys %sim_params){
+            $value=replace_value($value,$q,$sim_params{$q}) if (defined $value);
+        }
+        $sim_params{$p}=$value;
+        #print "\$sim_params{$p}=$value;\n";
+    }
+    return $sim_params{$param};
+}
 
+sub replace_value{
+    my ($string,$param,$value)=@_;
+    my $new_string=$string;
+    #print "$new_range\n";
+    my $new_param= $value;
+    ($new_string=$new_string)=~ s/\b$param\b/$new_param/g;
+    my $new_val = eval $new_string;
+    return $new_val if (defined $new_val);
+    return $string;
+}
 
 sub check_entered_address{
-	my 	($base_ref,$end_ref,$connect_ref,$number)=@_;
-	my @bases=@{$base_ref};
-	my @ends=@{$end_ref};
-	my @connects=@{$connect_ref};
-
-	my $current_base=$bases[$number];
-	my $current_end=$ends[$number];
-
-	if($current_base>  $current_end) {
-			
-	return "Error: the given base address is bigger than the End address!";	
-		}
-
-	my $size= scalar @bases; 
-	my $conflicts;
-	foreach (my $i=0; $i<$size; $i++){
-		if($i != $number){ #if not same row
-			if	($connects[$i] eq $connects[$number]) {#same bus
-					my $ok=(($bases[$i]< $bases[$number] && $bases[$i] < $ends[$number])||($bases[$i]> $bases[$number] && $bases[$i] > $ends[$number]));
-					if($ok==0) {
-						$conflicts=(defined $conflicts )? "$conflicts,$i": $i;
-					}
-			}	
-		
-		
-		}
-		
-		
-	}	
-	if (defined $conflicts){ return " The given address range has conflict with rows:$conflicts"; }
-	return;
-	
-	
-}	
+    my     ($base_ref,$end_ref,$connect_ref,$number)=@_;
+    my @bases=@{$base_ref};
+    my @ends=@{$end_ref};
+    my @connects=@{$connect_ref};
+    my $current_base=$bases[$number];
+    my $current_end=$ends[$number];
+    if($current_base>  $current_end) {
+    return "Error: the given base address is bigger than the End address!";
+        }
+    my $size= scalar @bases;
+    my $conflicts;
+    foreach (my $i=0; $i<$size; $i++){
+        if($i != $number){ #if not same row
+            if    ($connects[$i] eq $connects[$number]) {#same bus
+                    my $ok=(($bases[$i]< $bases[$number] && $bases[$i] < $ends[$number])||($bases[$i]> $bases[$number] && $bases[$i] > $ends[$number]));
+                    if($ok==0) {
+                        $conflicts=(defined $conflicts )? "$conflicts,$i": $i;
+                    }
+            }
+        }
+    }
+    if (defined $conflicts){ return " The given address range has conflict with rows:$conflicts"; }
+    return;
+}
 
 #############
-#	load_soc
+#    load_soc
 #############
-
 sub load_soc{
-	my ($soc,$info)=@_;
-	my $ip = ip->lib_new ();
-	my $file;
-	my $dialog =  gen_file_dialog (undef, 'SOC');	
-	my $dir = Cwd::getcwd();
-	$dialog->set_current_folder ("$dir/lib/soc");		
-
-
-	if ( "ok" eq $dialog->run ) {
-		$file = $dialog->get_filename;
-		my ($name,$path,$suffix) = fileparse("$file",qr"\..[^.]*$");
-		if($suffix eq '.SOC'){
-			my ($pp,$r,$err) = regen_object($file);
-			if ($r || !defined $pp){		
-				show_info($info,"**Error reading  $file file: $err\n");
-				 $dialog->destroy;
-				return;
-			} 
-			clone_obj($soc,$pp);
-			check_instances_version($soc,$ip);
-			set_gui_status($soc,"load_file",0);		
-		}					
-     }
-     $dialog->destroy;
-
+    my ($soc,$info)=@_;
+    my $ip = ip->lib_new ();
+    my $file;
+    my $dialog =  gen_file_dialog (undef, 'SOC');
+    my $dir = Cwd::getcwd();
+    $dialog->set_current_folder ("$dir/lib/soc");
+    if ( "ok" eq $dialog->run ) {
+        $file = $dialog->get_filename;
+        my ($name,$path,$suffix) = fileparse("$file",qr"\..[^.]*$");
+        if($suffix eq '.SOC'){
+            my ($pp,$r,$err) = regen_object($file);
+            if ($r || !defined $pp){
+                show_info($info,"**Error reading  $file file: $err\n");
+                $dialog->destroy;
+                return;
+            }
+            clone_obj($soc,$pp);
+            check_instances_version($soc,$ip);
+            set_gui_status($soc,"load_file",0);
+        }
+    }
+    $dialog->destroy;
 }
 
-
-
-
 sub check_instances_version{
-	my ($soc,$ip)=@_;
-
- #check if the IP's version didnt increases 
+    my ($soc,$ip)=@_;
+    #check if the IP's version didnt increases
     my @all_instances=$soc->soc_get_all_instances();
     foreach my $instance_id (@all_instances){
-	my ($old_v,$new_v)=  get_old_new_ip_version ($soc,$ip,$instance_id);
-	my $differences='';
-	$differences="$differences \t The $instance_id version (V.$old_v) mismatches with the one existing in the library (V.$new_v).\n " if($old_v != $new_v);
-		
-	
-	message_dialog("Warning: The generated system may not work correctly: \n $differences Please remove and then add the aforementioned instance(s) to update them with current version(s)") if(length($differences)>1);
-
+    my ($old_v,$new_v)=  get_old_new_ip_version ($soc,$ip,$instance_id);
+    my $differences='';
+    $differences="$differences \t The $instance_id version (V.$old_v) mismatches with the one existing in the library (V.$new_v).\n " if($old_v != $new_v);
+    message_dialog("Warning: The generated system may not work correctly: \n $differences Please remove and then add the aforementioned instance(s) to update them with current version(s)") if(length($differences)>1);
     }
-
-
 }
 
 sub get_old_new_ip_version{
-	my ($soc,$ip,$instance_id)=@_;
-	my $old_v=$soc->object_get_attribute($instance_id,"version",undef);
-	$old_v=0 if(!defined $old_v);
-	my $module=$soc->soc_get_module($instance_id);
-	my $category=$soc->soc_get_category($instance_id);
-	my $new_v=$ip->ip_get($category,$module,"version");
-	$new_v=0 if(!defined $new_v);
-	return ($old_v,$new_v);
+    my ($soc,$ip,$instance_id)=@_;
+    my $old_v=$soc->object_get_attribute($instance_id,"version",undef);
+    $old_v=0 if(!defined $old_v);
+    my $module=$soc->soc_get_module($instance_id);
+    my $category=$soc->soc_get_category($instance_id);
+    my $new_v=$ip->ip_get($category,$module,"version");
+    $new_v=0 if(!defined $new_v);
+    return ($old_v,$new_v);
 }
 
 sub check_for_ni{
-	my $self=shift;
-	my $ckeck=0;
-	my @instances=$self->soc_get_all_instances();
-	foreach my $id (@instances){
-		my $category = $self->soc_get_category($id);
-		if ($category eq 'NoC') {
-		$ckeck=1;
-		}
-	}
-	return $ckeck;
-
+    my $self=shift;
+    my $ckeck=0;
+    my @instances=$self->soc_get_all_instances();
+    foreach my $id (@instances){
+        my $category = $self->soc_get_category($id);
+        if ($category eq 'NoC') {
+        $ckeck=1;
+        }
+    }
+    return $ckeck;
 }
 
-
 sub get_ram_init{
-	my $soc=shift;
-	my $window = def_popwin_size(80,50,"Memory initial file setting setting",'percent');
-	my $table = def_table(10, 6, FALSE);
-	
-	my $scrolled_win = add_widget_to_scrolled_win($table);
-	my $row=0;
-	my $col=0;
-	my @instances=$soc->soc_get_all_instances();
-	foreach my $id (@instances){
-		my $category = $soc->soc_get_category($id);
-		if ($category eq 'RAM') {
-			my $ram_name=  $soc->soc_get_instance_name($id);
-			$table->attach (gen_label_in_left("$ram_name"),$col,$col+1, $row, $row+1,'fill','shrink',2,2);$col++;
-			my $init_type=gen_combobox_object ($soc,'RAM_INIT','type',"Dont_Care,Fill_0,Fill_1,Search_in_sw,Fixed_file","Search_in_sw",undef);
-			my $init_inf= "Define how the memory must be initialized :
- Dont_Care: The memory wont be initialized
- Fill_0: All memory bits will fill with value zero
- Fill_1: All memory bits will fill with value one
- Search_in_sw: Each instance of this processing core 
-               use different initial file that is 
-               located in its SW folder. 
- Fixed_file: All instance of this processing core 
-             use the same initial file";
-			
-			$row++;
-		}
-	}
-	
-	
-	$window->add($scrolled_win);
-	$window->show_all;
+    my $soc=shift;
+    my $window = def_popwin_size(80,50,"Memory initial file setting setting",'percent');
+    my $table = def_table(10, 6, FALSE);
+    my $scrolled_win = add_widget_to_scrolled_win($table);
+    my $row=0;
+    my $col=0;
+    my @instances=$soc->soc_get_all_instances();
+    foreach my $id (@instances){
+        my $category = $soc->soc_get_category($id);
+        if ($category eq 'RAM') {
+            my $ram_name=  $soc->soc_get_instance_name($id);
+            $table->attach (gen_label_in_left("$ram_name"),$col,$col+1, $row, $row+1,'fill','shrink',2,2);$col++;
+            my $init_type=gen_combobox_object ($soc,'RAM_INIT','type',"Dont_Care,Fill_0,Fill_1,Search_in_sw,Fixed_file","Search_in_sw",undef);
+            my $init_inf= "Define how the memory must be initialized :
+    Dont_Care: The memory wont be initialized
+    Fill_0: All memory bits will fill with value zero
+    Fill_1: All memory bits will fill with value one
+    Search_in_sw: Each instance of this processing core
+        use different initial file that is
+        located in its SW folder.
+    Fixed_file: All instance of this processing core
+        use the same initial file";
+            $row++;
+        }
+    }
+    $window->add($scrolled_win);
+    $window->show_all;
 }
 
-
 sub software_edit_soc {
-	my $soc=shift;	
-	my $name=$soc->object_get_attribute('soc_name');
-	$name="" if (!defined $name);
-	if (length($name)==0){
-		message_dialog("Please define the Tile name!");
-		return ;
-	}
-	my $target_dir  = "$ENV{'PRONOC_WORK'}/SOC/$name";
-	my $sw 	= "$target_dir/sw";
-	my ($app,$table,$tview) = software_main($sw);
-
-	
-
+    my $soc=shift;
+    my $name=$soc->object_get_attribute('soc_name');
+    $name="" if (!defined $name);
+    if (length($name)==0){
+        message_dialog("Please define the Tile name!");
+        return ;
+    }
+    my $target_dir  = "$ENV{'PRONOC_WORK'}/SOC/$name";
+    my $sw     = "$target_dir/sw";
+    my ($app,$table,$tview) = software_main($sw);
     my $ram = def_image_button('icons/info.png',"Required BRAMs\' size",FALSE,1);
     my $linker = def_image_button('icons/setting.png','LD Linker',FALSE,1);
-	my $make = def_image_button('icons/gen.png','Compile');
-	my $regen= def_image_button('icons/refresh.png','Regenerate main.c');
-	my $prog= def_image_button('icons/write.png','Program the memory');
-
-	$table->attach ($ram,0, 1, 1,2,'shrink','shrink',0,0);	
-	$table->attach ($regen,1, 2, 1,2,'shrink','shrink',0,0);
-	$table->attach ($linker,4, 5, 1,2,'shrink','shrink',0,0);	
-	$table->attach ($make,5, 6, 1,2,'shrink','shrink',0,0);
-	$table->attach ($prog,9, 10, 1,2,'shrink','shrink',0,0); 
-	$regen -> signal_connect ("clicked" => sub{
-		my $response =  yes_no_dialog("Are you sure you want to regenerate the main.c file? Note that any changes you have made will be lost");
-		if ($response eq 'yes') {      			
-			save_file ("$sw/main.c",main_c_template($name));
-			$app->refresh_source("$sw/main.c");	
-  		}		
-	});
-    
+    my $make = def_image_button('icons/gen.png','Compile');
+    my $regen= def_image_button('icons/refresh.png','Regenerate main.c');
+    my $prog= def_image_button('icons/write.png','Program the memory');
+    $table->attach ($ram,0, 1, 1,2,'shrink','shrink',0,0);
+    $table->attach ($regen,1, 2, 1,2,'shrink','shrink',0,0);
+    $table->attach ($linker,4, 5, 1,2,'shrink','shrink',0,0);
+    $table->attach ($make,5, 6, 1,2,'shrink','shrink',0,0);
+    $table->attach ($prog,9, 10, 1,2,'shrink','shrink',0,0);
+    $regen -> signal_connect ("clicked" => sub{
+        my $response =  yes_no_dialog("Are you sure you want to regenerate the main.c file? Note that any changes you have made will be lost");
+        if ($response eq 'yes') {
+            save_file ("$sw/main.c",main_c_template($name));
+            $app->refresh_source("$sw/main.c");
+        }
+    });
     my $load;
-	$make -> signal_connect("clicked" => sub{
-		$load->destroy   if(defined $load);
-		$app->ask_to_save_changes();
-		$load= show_gif("icons/load.gif");
+    $make -> signal_connect("clicked" => sub{
+        $load->destroy   if(defined $load);
+        $app->ask_to_save_changes();
+        $load= show_gif("icons/load.gif");
         $table->attach ($load,7, 8, 1,2,'shrink','shrink',0,0);
-        $load->show_all; 
-		unless (run_make_file($sw,$tview,'clean')){
-        	$load->destroy;    
-        	$load=def_icon("icons/cancel.png");
-        	$table->attach ($load,7, 8, 1,2,'shrink','shrink',0,0); 
-        	$load->show_all; 
-        	return;
+        $load->show_all;
+        unless (run_make_file($sw,$tview,'clean')){
+            $load->destroy;
+            $load=def_icon("icons/cancel.png");
+            $table->attach ($load,7, 8, 1,2,'shrink','shrink',0,0);
+            $load->show_all;
+            return;
         };
-		unless (run_make_file($sw,$tview)){
-			$load->destroy;    
-        	$load=def_icon("icons/cancel.png");
-        	$table->attach ($load,7, 8, 1,2,'shrink','shrink',0,0); 
-        	$load->show_all; 
-        	return;			
-		}
-		$load->destroy;
-		$load=def_icon("icons/button_ok.png");
-        $table->attach ($load,7, 8, 1,2,'shrink','shrink',0,0); 
-        $load->show_all; 
-	});
-
-	#Programe the board 
-	$prog-> signal_connect("clicked" => sub{ 
-		my $error = 0;
-		my $bash_file="$target_dir/sw/program.sh";
-		my $jtag_intfc="$sw/jtag_intfc.sh";
-
-		add_info($tview,"Program the board using quartus_pgm and $bash_file file\n");
-		#check if the programming file exists
-		unless (-f $bash_file) {
-			add_colored_info($tview,"\tThe $bash_file does not exists! \n", 'red');
-			$error=1;
-		}
-		#check if the jtag_intfc.sh file exists
-		unless (-f $jtag_intfc) {
-			add_colored_info($tview,"\tThe $jtag_intfc does not exists!. Press the compile button and select your FPGA board first to generate $jtag_intfc file\n", 'red');
-			$error=1;
-		}
-		
-		return if($error);
-		my $command = "cd $target_dir/sw; bash program.sh";
-		add_info($tview,"$command\n");
-		my ($stdout,$exit,$stderr)=run_cmd_in_back_ground_get_stdout($command);
-		if(length $stderr>1){			
-			add_colored_info($tview,"$stderr\n",'red');
-			add_colored_info($tview,"Memory was not programmed successfully!\n",'red');
-		}else {
-
-			if($exit){
-				add_colored_info($tview,"$stdout\n",'red');
-				add_colored_info($tview,"Memory was not programmed successfully!\n",'red');
-			}else{
-				add_info($tview,"$stdout\n");
-				add_colored_info($tview,"Memory is programmed successfully!\n",'blue');
-
-			}
-			
-		}		
-	});
-	
-	$ram -> signal_connect("clicked" => sub{
-		show_reqired_brams($soc,$tview);
-	});
-	
-	$linker -> signal_connect("clicked" => sub{
-		linker_setting($soc,$tview);
-	});
-
+        unless (run_make_file($sw,$tview)){
+            $load->destroy;
+            $load=def_icon("icons/cancel.png");
+            $table->attach ($load,7, 8, 1,2,'shrink','shrink',0,0);
+            $load->show_all;
+            return;
+        }
+        $load->destroy;
+        $load=def_icon("icons/button_ok.png");
+        $table->attach ($load,7, 8, 1,2,'shrink','shrink',0,0);
+        $load->show_all;
+    });
+    #Programe the board
+    $prog-> signal_connect("clicked" => sub{
+        my $error = 0;
+        my $bash_file="$target_dir/sw/program.sh";
+        my $jtag_intfc="$sw/jtag_intfc.sh";
+        add_info($tview,"Program the board using quartus_pgm and $bash_file file\n");
+        #check if the programming file exists
+        unless (-f $bash_file) {
+            add_colored_info($tview,"\tThe $bash_file does not exists! \n", 'red');
+            $error=1;
+        }
+        #check if the jtag_intfc.sh file exists
+        unless (-f $jtag_intfc) {
+            add_colored_info($tview,"\tThe $jtag_intfc does not exists!. Press the compile button and select your FPGA board first to generate $jtag_intfc file\n", 'red');
+            $error=1;
+        }
+        return if($error);
+        my $command = "cd $target_dir/sw; bash program.sh";
+        add_info($tview,"$command\n");
+        my ($stdout,$exit,$stderr)=run_cmd_in_back_ground_get_stdout($command);
+        if(length $stderr>1){
+            add_colored_info($tview,"$stderr\n",'red');
+            add_colored_info($tview,"Memory was not programmed successfully!\n",'red');
+        }else {
+            if($exit){
+                add_colored_info($tview,"$stdout\n",'red');
+                add_colored_info($tview,"Memory was not programmed successfully!\n",'red');
+            }else{
+                add_info($tview,"$stdout\n");
+                add_colored_info($tview,"Memory is programmed successfully!\n",'blue');
+            }
+        }
+    });
+    $ram -> signal_connect("clicked" => sub{
+        show_reqired_brams($soc,$tview);
+    });
+    $linker -> signal_connect("clicked" => sub{
+        linker_setting($soc,$tview);
+    });
 }
 
-
 sub soc_mem_prog {
-	my $chain=shift;
-	my $string="#!/bin/bash
-
-
+    my $chain=shift;
+    my $string="#!/bin/bash
 #JTAG_INTFC=\"\$PRONOC_WORK/toolchain/bin/JTAG_INTFC\"
 source ./jtag_intfc.sh
-
 #reset and disable cpus, then release the reset but keep the cpus disabled
-
 \$JTAG_INTFC -t $chain -n 127  -d  \"I:1,D:2:3,D:2:2,I:0\"
-
-# jtag instruction 
-#	0: bypass
-#	1: getting data
+# jtag instruction
+#    0: bypass
+#    1: getting data
 # jtag data :
-# 	bit 0 is reset 
-#	bit 1 is disable
+#     bit 0 is reset
+#    bit 1 is disable
 # I:1  set jtag_enable  in active mode
 # D:2:3 load jtag_enable data register with 0x3 reset=1 disable=1
 # D:2:2 load jtag_enable data register with 0x2 reset=0 disable=1
 # I:0  set jtag_enable  in bypass mode
-
-
-
 #Program the memory
-
-	bash write_memory.sh 
-
- 
+    bash write_memory.sh
 #Enable the cpu
 \$JTAG_INTFC -t $chain -n 127  -d  \"I:1,D:2:0,I:0\"
 # I:1  set jtag_enable  in active mode
 # D:2:0 load jtag_enable data register with 0x0 reset=0 disable=0
 # I:0  set jtag_enable  in bypass mode
 ";
-return $string;
-	
+    return $string;
 }
 
-
 sub soc_gen_top_ip{
-	my $soc=shift;
-	my $top_ip=ip_gen->top_gen_new();
-	my $ip = ip->lib_new ();
-	my $intfc=interface->interface_new();
-	my @instances=$soc->soc_get_all_instances();
-	my $wires=soc->new_wires();
-	foreach my $id (@instances){
-		my ($param_v, $local_param_v, $wire_def_v, $inst_v, $plugs_assign_v, $sockets_assign_v,$io_full_v,$io_top_full_v,$io_sim_v,
-		$top_io_short,$param_as_in_v,$param_pass_v,$system_v,$assigned_ports,$top_io_pass,$src_io_short, $src_io_full)=gen_module_inst($id,$soc,$top_ip,$intfc,$wires);
-	}	#$id
-	return $top_ip;
+    my $soc=shift;
+    my $top_ip=ip_gen->top_gen_new();
+    my $ip = ip->lib_new ();
+    my $intfc=interface->interface_new();
+    my @instances=$soc->soc_get_all_instances();
+    my $wires=soc->new_wires();
+    foreach my $id (@instances){
+        my ($param_v, $local_param_v, $wire_def_v, $inst_v, $plugs_assign_v, $sockets_assign_v,$io_full_v,$io_top_full_v,$io_sim_v,
+        $top_io_short,$param_as_in_v,$param_pass_v,$system_v,$assigned_ports,$top_io_pass,$src_io_short, $src_io_full)=gen_module_inst($id,$soc,$top_ip,$intfc,$wires);
+    }    #$id
+    return $top_ip;
 }
 
-
-
-
 sub get_soc_clk_source_list{
-	my $soc=shift;
-    my %all_sources;    
+    my $soc=shift;
+    my %all_sources;
     my $top = soc_gen_top_ip($soc);
     my @intfcs=$top->top_get_intfc_list();
-	my @sources=('clk','reset');
-	foreach my $intfc (@intfcs){	
-			my($type,$name,$num)= split("[:\[ \\]]", $intfc);
-			foreach my $s (@sources){
-				if ($intfc =~ /plug:$s/){ 
-					my @ports=$top->top_get_intfc_ports_list($intfc);				
-					$all_sources{$s}=\@ports;
-				}	
-			}
-	}
-	return %all_sources;
-}	
+    my @sources=('clk','reset');
+    foreach my $intfc (@intfcs){
+            my($type,$name,$num)= split("[:\[ \\]]", $intfc);
+            foreach my $s (@sources){
+                if ($intfc =~ /plug:$s/){
+                    my @ports=$top->top_get_intfc_ports_list($intfc);
+                    $all_sources{$s}=\@ports;
+                }
+            }
+    }
+    return %all_sources;
+}
 
 sub check_soc_name{
-	my $name=shift;
-	$name="" if (!defined $name);
-	if (length($name)==0){
-		message_dialog("Please define the Tile name!");
-		return 1;
-	}	
-	
-	my @tmp=split('_',$name);
-	if ( $tmp[-1] =~ /^[0-9]+$/ ){
-		message_dialog("The soc name must not end with '_number'!");
-		return 1;
-	}
-	
-	my $error = check_verilog_identifier_syntax($name);
-	if ( defined $error ){
-		message_dialog("The \"$name\" is given with an unacceptable formatting. This name will be used as top level Verilog module name so it must follow Verilog identifier declaration formatting:\n $error");
-		return 1;
-	}
-	return 0;	
+    my $name=shift;
+    $name="" if (!defined $name);
+    if (length($name)==0){
+        message_dialog("Please define the Tile name!");
+        return 1;
+    }
+    my @tmp=split('_',$name);
+    if ( $tmp[-1] =~ /^[0-9]+$/ ){
+        message_dialog("The soc name must not end with '_number'!");
+        return 1;
+    }
+    my $error = check_verilog_identifier_syntax($name);
+    if ( defined $error ){
+        message_dialog("The \"$name\" is given with an unacceptable formatting. This name will be used as top level Verilog module name so it must follow Verilog identifier declaration formatting:\n $error");
+        return 1;
+    }
+    return 0;
 }
 
-
 ############
 #    main
 ############
-
-
-
-sub soc_clk_setting_win1 { 
-	my ($soc,$info)=@_;
-	my $window = def_popwin_size(80,80,"CLK setting",'percent');
-   
-    my $next=def_image_button('icons/right.png','Next'); 	
-	my $mtable = def_table(10, 1, FALSE);
-	#get the list of all tiles clk sources
-	
-	
-	
-	my $table = def_table(10, 7, FALSE);
-	my($row,$column)=(0,0);
-	
-	my %all = get_soc_clk_source_list($soc) ;
-	my @ports = @{$all{'clk'}} if defined $all{'clk'};
-	my $n=0;
-	foreach my $p (@ports){
-		my $r_lab=gen_label_in_center("$p:");
-		$table->attach  ($r_lab,$column,$column+1,$row,$row+1,'fill','shrink',2,2);$column+=1;
-		$soc->object_add_attribute('SOURCE_SET',"clk_${n}_name",$p);
-		($column,$row)=get_clk_constrain_widget($soc,$table,$column,$row,'clk',$n);	
-		$n++;
-	}
-
-	$mtable->attach_defaults($table,0,1,0,1);
-	$mtable->attach($next,0,1,20,21,'expand','fill',2,2);	
-	$window->add ($mtable);
-	$window->show_all();	
-	$next-> signal_connect("clicked" => sub{ 			
-		$window->destroy;		
-		clk_setting_win2($soc,$info,'soc');
-					
-	});	
-
-
- 	
-
+sub soc_clk_setting_win1 {
+    my ($soc,$info)=@_;
+    my $window = def_popwin_size(80,80,"CLK setting",'percent');
+    my $next=def_image_button('icons/right.png','Next');
+    my $mtable = def_table(10, 1, FALSE);
+    #get the list of all tiles clk sources
+    my $table = def_table(10, 7, FALSE);
+    my($row,$column)=(0,0);
+    my %all = get_soc_clk_source_list($soc) ;
+    my @ports = @{$all{'clk'}} if defined $all{'clk'};
+    my $n=0;
+    foreach my $p (@ports){
+        my $r_lab=gen_label_in_center("$p:");
+        $table->attach  ($r_lab,$column,$column+1,$row,$row+1,'fill','shrink',2,2);$column+=1;
+        $soc->object_add_attribute('SOURCE_SET',"clk_${n}_name",$p);
+        ($column,$row)=get_clk_constrain_widget($soc,$table,$column,$row,'clk',$n);
+        $n++;
+    }
+    $mtable->attach_defaults($table,0,1,0,1);
+    $mtable->attach($next,0,1,20,21,'expand','fill',2,2);
+    $window->add ($mtable);
+    $window->show_all();
+    $next-> signal_connect("clicked" => sub{
+        $window->destroy;
+        clk_setting_win2($soc,$info,'soc');
+    });
 }
 
-
 ######
 # ctrl
 ######
-
 sub soc_ctrl_tab {
-	my ($soc,$info,$ip)=@_;
-	
-	my $generate = def_image_button('icons/gen.png','_Generate RTL',FALSE,1);
-	my $compile  = def_image_button('icons/gate.png','Compile RTL');
-	my $software = def_image_button('icons/binary.png','Software');
-	my $diagram  = def_image_button('icons/diagram.png','Diagram');
-	my $clk=  def_image_button('icons/clk.png','CLK setting');
-	my $unset    = def_image_button('icons/intfc.png','Unset Intfc.');
-	
-	my $ram      = def_image_button('icons/RAM.png','Memory');	
-	my $wb = def_image_button('icons/setting.png','WB addr');	
-	#my $open = def_image_button('icons/browse.png',"_Load Tile",FALSE,1);
-	#my $entry=gen_entry_object($soc,'soc_name',undef,undef,undef,undef);
-	#my $entrybox=gen_label_info(" Tile name:",$entry);
-	#my $save      = def_image_button('icons/save.png');	
-	#my $open_dir  = def_image_button('icons/open-folder.png');
-	#set_tip($save, "Save current tile configuration setting");
-	#set_tip($open_dir, "Open target tile folder");
-		
-	#$entrybox->pack_start( $save, FALSE, FALSE, 0);
-	#$entrybox->pack_start( $open_dir, FALSE, FALSE, 0);
-	
-	my $main_table = def_table (1, 12, FALSE);
-
-
-    my $target_dir= "$ENV{'PRONOC_WORK'}/SOC";    
-	my ($entrybox,$entry ) =gen_save_load_widget (
-        $soc, #the object 
+    my ($soc,$info,$ip)=@_;
+    my $generate = def_image_button('icons/gen.png','_Generate RTL',FALSE,1);
+    my $compile  = def_image_button('icons/gate.png','Compile RTL');
+    my $software = def_image_button('icons/binary.png','Software');
+    my $diagram  = def_image_button('icons/diagram.png','Diagram');
+    my $clk=  def_image_button('icons/clk.png','CLK setting');
+    my $unset    = def_image_button('icons/intfc.png','Unset Intfc.');
+    my $ram      = def_image_button('icons/RAM.png','Memory');
+    my $wb = def_image_button('icons/setting.png','WB addr');
+    #my $open = def_image_button('icons/browse.png',"_Load Tile",FALSE,1);
+    #my $entry=gen_entry_object($soc,'soc_name',undef,undef,undef,undef);
+    #my $entrybox=gen_label_info(" Tile name:",$entry);
+    #my $save      = def_image_button('icons/save.png');
+    #my $open_dir  = def_image_button('icons/open-folder.png');
+    #set_tip($save, "Save current tile configuration setting");
+    #set_tip($open_dir, "Open target tile folder");
+    #$entrybox->pack_start( $save, FALSE, FALSE, 0);
+    #$entrybox->pack_start( $open_dir, FALSE, FALSE, 0);
+    my $main_table = def_table (1, 12, FALSE);
+    my $target_dir= "$ENV{'PRONOC_WORK'}/SOC";
+    my ($entrybox,$entry ) =gen_save_load_widget (
+        $soc, #the object
         "Tile name",#the label shown for setting configuration
-        'soc_name',#the key name for saveing the setting configuration in object 
+        'soc_name',#the key name for saveing the setting configuration in object
         'Tile',#the label full name show in tool tips
         $target_dir,#Where the generted RTL files are loacted. Undef if not aplicaple
         'soc',#check the given name match the SoC or mpsoc name rules
         'lib/soc',#where the current configuration seting file is saved
         'SOC',#the extenstion given for configuration seting file
-		\&load_soc,#refrence to load function
-		$info
+        \&load_soc,#refrence to load function
+        $info
         );
-
-
-
-
-	
-	#$main_table->attach ($open		, 0, 1, 0,1,'expand','shrink',2,2);
-	$main_table->attach ($entrybox	, 1, 3, 0,1,'expand','shrink',2,2);
-	$main_table->attach ($unset		, 3, 4, 0,1,'expand','shrink',2,2);
-	$main_table->attach ($wb		, 4, 5, 0,1,'expand','shrink',2,2);
-	$main_table->attach ($diagram	, 5, 6, 0,1,'expand','shrink',2,2);
-	$main_table->attach ($clk		, 6, 7, 0,1,'expand','shrink',2,2);
-	$main_table->attach ($generate	, 7, 8, 0,1,'expand','shrink',2,2);
-	$main_table->attach ($software	, 8, 9, 0,1,'expand','shrink',2,2);
-	$main_table->attach ($compile	,10,12, 0,1,'expand','shrink',2,2);
-	
-	
-	$clk-> signal_connect("clicked" => sub{ 
-			soc_clk_setting_win1($soc,$info);	
-	});
-
-	$diagram-> signal_connect("clicked" => sub{ 
-		show_tile_diagram ($soc);
-	});
-	
-
-	#$save-> signal_connect("clicked" => sub{ 
-	#	my $name=$soc->object_get_attribute('soc_name');		
-	#	return if(check_soc_name($name)) ;
-			
-	#	# Write object file
-	#	open(FILE,  ">lib/soc/$name.SOC") || die "Can not open: $!";
-	#	print FILE perl_file_header("$name.SOC");
-	#	print FILE Data::Dumper->Dump([\%$soc],['soc']);
-	#	close(FILE) || die "Error closing file: $!";
-	#	message_dialog("Processing Tile  \"$name\" is saved as lib/soc/$name.SOC.");		
-			
-	#});
-	
-	
-	$generate-> signal_connect("clicked" => sub{ 
-		my $name=$soc->object_get_attribute('soc_name');		
-		return if(check_soc_name($name)) ;
-
-		my $target_dir  = "$ENV{'PRONOC_WORK'}/SOC/$name";
-		my $hw_dir 	= "$target_dir/src_verilog";
-		my $sw_path 	= "$target_dir/sw";
-    		
-		$soc->object_add_attribute('global_param','CORE_ID',0);	
-		$soc->object_add_attribute('global_param','SW_LOC',$sw_path);	
-		
-		unlink  "$hw_dir/file_list";
-		generate_soc($soc,$info,$target_dir,$hw_dir,$sw_path,1,1);
-		
-		my $has_ni= check_for_ni($soc);
-		if($has_ni){
-			my $message = "Processing Tile  \"$name\" has been created successfully at $target_dir/.  In order to include this tile in MPSoC Generator you need to restart the ProNoC. Do you ant to reset the ProNoC now?";
-			my $response =  yes_no_dialog ($message);
-			if ($response eq 'yes') {
-	      			exec($^X, $0, @ARGV);# reset ProNoC to apply changes	
-	  		}
-	  		
-		} else {
-			message_dialog("Processing Tile  \"$name\" has been created successfully at $target_dir/.");
-
-		}
-	});
-
-	$software -> signal_connect("clicked" => sub{
-		software_edit_soc($soc);
-
-	});
-	
-	$unset-> signal_connect("clicked" => sub{
-		set_unset_infc($soc);
-	});
-
-	$ram-> signal_connect("clicked" => sub{
-		get_ram_init($soc);
-
-	});
-
-   
-	
-	$compile -> signal_connect("clicked" => sub{ 
-		$soc->object_add_attribute('compile','compilers',"QuartusII,Vivado,Verilator,Modelsim");
-		my $name=$soc->object_get_attribute('soc_name');
-		$name="" if (!defined $name);
-		if (length($name)==0){
-			message_dialog("Please define the Tile name!");
-			return ;
-		}
-		my $target_dir  = "$ENV{'PRONOC_WORK'}/SOC/$name";
-		my $hw_dir 	= "$target_dir/src_verilog";
-		my $sw_path 	= "$target_dir/sw";
-		my $top 	= "$target_dir/src_verilog/${name}_top.sv";
-		if (-f $top){
-			unlink  "$hw_dir/file_list";
-			generate_soc($soc,$info,$target_dir,$hw_dir,$sw_path,1,1);	
-			select_compiler($soc,$name,$top,$target_dir);
-		} else {
-			message_dialog("Cannot find $top file. Please run RTL Generator first!",'error');
-			return;
-		}
-	});
-
-	$wb-> signal_connect("clicked" => sub{ 
-		wb_address_setting($soc);
-	
-	});
-
-	#$open-> signal_connect("clicked" => sub{ 
-	#	load_soc($soc,$info);
-	
-	#});	
-	
-	#$open_dir-> signal_connect("clicked" => sub{ 
-	#	my $name=$soc->object_get_attribute('soc_name');
-	#	$name="" if (!defined $name);
-	#	if (length($name)==0){
-	#		message_dialog("Please define the Tile name!");
-	#		return ;
-	#	}
-	#	my $target_dir  = "$ENV{'PRONOC_WORK'}/SOC/$name";
-	#	unless (-d $target_dir){
-	#		message_dialog("Cannot find $target_dir.\n Please run RTL Generator first!",'error');
-	#		return;
-	#	}
-	#	system "xdg-open   $target_dir";
-		
-	#});	
-	
-	return $main_table;
-	
+    #$main_table->attach ($open        , 0, 1, 0,1,'expand','shrink',2,2);
+    $main_table->attach ($entrybox    , 1, 3, 0,1,'expand','shrink',2,2);
+    $main_table->attach ($unset        , 3, 4, 0,1,'expand','shrink',2,2);
+    $main_table->attach ($wb        , 4, 5, 0,1,'expand','shrink',2,2);
+    $main_table->attach ($diagram    , 5, 6, 0,1,'expand','shrink',2,2);
+    $main_table->attach ($clk        , 6, 7, 0,1,'expand','shrink',2,2);
+    $main_table->attach ($generate    , 7, 8, 0,1,'expand','shrink',2,2);
+    $main_table->attach ($software    , 8, 9, 0,1,'expand','shrink',2,2);
+    $main_table->attach ($compile    ,10,12, 0,1,'expand','shrink',2,2);
+    $clk-> signal_connect("clicked" => sub{
+            soc_clk_setting_win1($soc,$info);
+    });
+    $diagram-> signal_connect("clicked" => sub{
+        show_tile_diagram ($soc);
+    });
+    #$save-> signal_connect("clicked" => sub{
+    #    my $name=$soc->object_get_attribute('soc_name');
+    #    return if(check_soc_name($name)) ;
+    #    # Write object file
+    #    open(FILE,  ">lib/soc/$name.SOC") || die "Can not open: $!";
+    #    print FILE perl_file_header("$name.SOC");
+    #    print FILE Data::Dumper->Dump([\%$soc],['soc']);
+    #    close(FILE) || die "Error closing file: $!";
+    #    message_dialog("Processing Tile  \"$name\" is saved as lib/soc/$name.SOC.");
+    #});
+    $generate-> signal_connect("clicked" => sub{
+        my $name=$soc->object_get_attribute('soc_name');
+        return if(check_soc_name($name)) ;
+        my $target_dir  = "$ENV{'PRONOC_WORK'}/SOC/$name";
+        my $hw_dir     = "$target_dir/src_verilog";
+        my $sw_path     = "$target_dir/sw";
+        $soc->object_add_attribute('global_param','CORE_ID',0);
+        $soc->object_add_attribute('global_param','SW_LOC',$sw_path);
+        unlink  "$hw_dir/file_list";
+        generate_soc($soc,$info,$target_dir,$hw_dir,$sw_path,1,1);
+        my $has_ni= check_for_ni($soc);
+        if($has_ni){
+            my $message = "Processing Tile  \"$name\" has been created successfully at $target_dir/.  In order to include this tile in MPSoC Generator you need to restart the ProNoC. Do you ant to reset the ProNoC now?";
+            my $response =  yes_no_dialog ($message);
+            if ($response eq 'yes') {
+                exec($^X, $0, @ARGV);# reset ProNoC to apply changes
+            }
+        } else {
+            message_dialog("Processing Tile  \"$name\" has been created successfully at $target_dir/.");
+        }
+    });
+    $software -> signal_connect("clicked" => sub{
+        software_edit_soc($soc);
+    });
+    $unset-> signal_connect("clicked" => sub{
+        set_unset_infc($soc);
+    });
+    $ram-> signal_connect("clicked" => sub{
+        get_ram_init($soc);
+    });
+    $compile -> signal_connect("clicked" => sub{
+        $soc->object_add_attribute('compile','compilers',"QuartusII,Vivado,Verilator,Modelsim");
+        my $name=$soc->object_get_attribute('soc_name');
+        $name="" if (!defined $name);
+        if (length($name)==0){
+            message_dialog("Please define the Tile name!");
+            return ;
+        }
+        my $target_dir  = "$ENV{'PRONOC_WORK'}/SOC/$name";
+        my $hw_dir     = "$target_dir/src_verilog";
+        my $sw_path     = "$target_dir/sw";
+        my $top     = "$target_dir/src_verilog/${name}_top.sv";
+        if (-f $top){
+            unlink  "$hw_dir/file_list";
+            generate_soc($soc,$info,$target_dir,$hw_dir,$sw_path,1,1);
+            select_compiler($soc,$name,$top,$target_dir);
+        } else {
+            message_dialog("Cannot find $top file. Please run RTL Generator first!",'error');
+            return;
+        }
+    });
+    $wb-> signal_connect("clicked" => sub{
+        wb_address_setting($soc);
+    });
+    #$open-> signal_connect("clicked" => sub{
+    #    load_soc($soc,$info);
+    #});
+    #$open_dir-> signal_connect("clicked" => sub{
+    #    my $name=$soc->object_get_attribute('soc_name');
+    #    $name="" if (!defined $name);
+    #    if (length($name)==0){
+    #        message_dialog("Please define the Tile name!");
+    #        return ;
+    #    }
+    #    my $target_dir  = "$ENV{'PRONOC_WORK'}/SOC/$name";
+    #    unless (-d $target_dir){
+    #        message_dialog("Cannot find $target_dir.\n Please run RTL Generator first!",'error');
+    #        return;
+    #    }
+    #    system "xdg-open   $target_dir";
+    #});
+    return $main_table;
 }
 
-
 sub socgen_main{
-	 
-	my $infc = interface->interface_new(); 
-	my $ip = ip->lib_new ();
-	my $soc = soc->soc_new();
-	set_gui_status($soc,"ideal",0);
-		
-	#  The main table containing the lib tree, selected modules and info section 
-	my $main_table = def_table (20, 12, FALSE);
-	
-	# The box which holds the info, warning, error ...  messages
-	my ($infobox,$info)= create_txview();	
-		
-	
-	# A tree view for holding a library
-	my %tree_text;
-	my @categories= $ip->ip_get_categories();
+    my $infc = interface->interface_new();
+    my $ip = ip->lib_new ();
+    my $soc = soc->soc_new();
+    set_gui_status($soc,"ideal",0);
+    #  The main table containing the lib tree, selected modules and info section
+    my $main_table = def_table (20, 12, FALSE);
+    # The box which holds the info, warning, error ...  messages
+    my ($infobox,$info)= create_txview();
+    # A tree view for holding a library
+    my %tree_text;
+    my @categories= $ip->ip_get_categories();
     foreach my $p (@categories)
     {
-   		#next if ($p eq 'PLL');
-   		my @modules= $ip->get_modules($p);
-   		$tree_text{$p}=\@modules;	
+        #next if ($p eq 'PLL');
+        my @modules= $ip->get_modules($p);
+        $tree_text{$p}=\@modules;
     }
-	my $tree_box = create_tree ($soc,'IP list', $info,\%tree_text,\&show_select_ip_description,\&add_module_to_soc);
-
-	$main_table->set_row_spacings (4);
-	$main_table->set_col_spacings (1);
-	
-	my  $device_win=show_active_dev($soc,$ip,$infc,$info);
-	
-	
-	
-	
-		
-	my $h1=gen_hpaned($tree_box,.15,$device_win);
-	my $v2=gen_vpaned($h1,.55,$infobox);
-	$main_table->attach_defaults ($v2  , 0, 12, 0,19);
-	
-	my $ctrl = soc_ctrl_tab($soc,$info,$ip);
-	$main_table->attach ($ctrl  , 0, 12, 19,20,'fill','fill',2,2);
-
-	
-
-	my $sc_win = add_widget_to_scrolled_win($main_table);
-
-
-
-	#check soc status every 0.5 second. refresh device table if there is any changes 
-	Glib::Timeout->add (100, sub{ 
-	 	my ($state,$timeout)= get_gui_status($soc);
-		
-		if ($timeout>0){
-			$timeout--;
-			set_gui_status($soc,$state,$timeout);
-				
-		}elsif ($state eq 'save_project'){
-			# Write object file
-			my $name=$soc->object_get_attribute('soc_name',undef);
-			open(FILE,  ">lib/soc/$name.SOC") || die "Can not open: $!";
-			print FILE perl_file_header("$name.SOC");
-			print FILE Data::Dumper->Dump([\%$soc],['soc']);
-			close(FILE) || die "Error closing file: $!";			
-			set_gui_status($soc,"ideal",0);	
-		}
-		elsif( $state ne "ideal" ){
-			$device_win->destroy;
-			$device_win=show_active_dev($soc,$ip,$infc,$info);
-			$h1 -> pack2($device_win, TRUE, TRUE);  
-			$h1 -> show_all; 
-			$ctrl->destroy;
-			$ctrl= soc_ctrl_tab($soc,$info,$ip);
-			$main_table->attach ($ctrl  , 0, 12, 19,20,'fill','fill',2,2);
-			$main_table->show_all; 
-			set_gui_status($soc,"ideal",0);			
-		}	
-		return TRUE;
-		
-	} );
-
-	
-
-	return $sc_win;
-
-	
-
+    my $tree_box = create_tree ($soc,'IP list', $info,\%tree_text,\&show_select_ip_description,\&add_module_to_soc);
+    $main_table->set_row_spacings (4);
+    $main_table->set_col_spacings (1);
+    my  $device_win=show_active_dev($soc,$ip,$infc,$info);
+    my $h1=gen_hpaned($tree_box,.15,$device_win);
+    my $v2=gen_vpaned($h1,.55,$infobox);
+    $main_table->attach_defaults ($v2  , 0, 12, 0,19);
+    my $ctrl = soc_ctrl_tab($soc,$info,$ip);
+    $main_table->attach ($ctrl  , 0, 12, 19,20,'fill','fill',2,2);
+    my $sc_win = add_widget_to_scrolled_win($main_table);
+    #check soc status every 0.5 second. refresh device table if there is any changes
+    Glib::Timeout->add (100, sub{
+        my ($state,$timeout)= get_gui_status($soc);
+        if ($timeout>0){
+            $timeout--;
+            set_gui_status($soc,$state,$timeout);
+        }elsif ($state eq 'save_project'){
+            # Write object file
+            my $name=$soc->object_get_attribute('soc_name',undef);
+            open(FILE,  ">lib/soc/$name.SOC") || die "Can not open: $!";
+            print FILE perl_file_header("$name.SOC");
+            print FILE Data::Dumper->Dump([\%$soc],['soc']);
+            close(FILE) || die "Error closing file: $!";
+            set_gui_status($soc,"ideal",0);
+        }
+        elsif( $state ne "ideal" ){
+            $device_win->destroy;
+            $device_win=show_active_dev($soc,$ip,$infc,$info);
+            $h1 -> pack2($device_win, TRUE, TRUE);
+            $h1 -> show_all;
+            $ctrl->destroy;
+            $ctrl= soc_ctrl_tab($soc,$info,$ip);
+            $main_table->attach ($ctrl  , 0, 12, 19,20,'fill','fill',2,2);
+            $main_table->show_all;
+            set_gui_status($soc,"ideal",0);
+        }
+        return TRUE;
+    } );
+    return $sc_win;
 }
-
-
-
-
-
-
+1;
\ No newline at end of file
diff --git a/mpsoc/perl_gui/lib/perl/software_editor.pl b/mpsoc/perl_gui/lib/perl/software_editor.pl
index 5947671..dcec7a7 100644
--- a/mpsoc/perl_gui/lib/perl/software_editor.pl
+++ b/mpsoc/perl_gui/lib/perl/software_editor.pl
@@ -1,22 +1,16 @@
 #!/usr/bin/perl -w
-
 use strict;
 use warnings;
-
 use FindBin;
 use lib $FindBin::Bin;
 use Consts;
-
 use constant::boolean;
-
-
 use Data::Dumper;
 use File::Basename;
 use Cwd 'abs_path';
-
 use base 'Class::Accessor::Fast';
-
 use Consts;
+
 BEGIN {
     my $module = (Consts::GTK_VERSION==2) ? 'Gtk2' : 'Gtk3';
     my $file = $module;
@@ -26,963 +20,725 @@ BEGIN
     $module->import;
 }
 
-
-require "widget.pl"; 
-
+require "widget.pl";
 
 __PACKAGE__->mk_accessors(qw{
-	window
-	sourceview
-	buffer
-	filename
-	search_regexp
-	search_case
-	search_entry
-	regexp
-	highlighted
-	open_list_ref
-	source_view_notebook
-	menue
-	modified
-	label
-	ask_to_save
-	close_b
+    window
+    sourceview
+    buffer
+    filename
+    search_regexp
+    search_case
+    search_entry
+    regexp
+    highlighted
+    open_list_ref
+    source_view_notebook
+    menue
+    modified
+    label
+    ask_to_save
+    close_b
 });
 
-
-
-
-
 my $NAME = 'ProNoC';
-my 	$path = "";
-
-
-
+my     $path = "";
 exit gtk_gui_run(\&software_main_stand_alone) unless caller;
 
-
 sub software_main_stand_alone(){
-	$path = "../../";
-	
-	set_path_env();
-	my $project_dir	  = get_project_dir(); #mpsoc dir addr
-	my $paths_file= "$project_dir/mpsoc/perl_gui/lib/Paths";
-	if (-f 	$paths_file){#} && defined $ENV{PRONOC_WORK} ) {
-		my $paths= do $paths_file;
-		set_gui_setting($paths);
-	}
-	
-	set_defualt_font_size();
-	my ($app,$table,$tview,$window) = software_main("../../../../../back/tmp",undef,) ;
-	$window->signal_connect (destroy => sub { gui_quite();});	
+    $path = "../../";
+    set_path_env();
+    my $project_dir      = get_project_dir(); #mpsoc dir addr
+    my $paths_file= "$project_dir/mpsoc/perl_gui/lib/Paths";
+    if (-f     $paths_file){#} && defined $ENV{PRONOC_WORK} ) {
+        my $paths= do $paths_file;
+        set_gui_setting($paths);
+    }
+    set_defualt_font_size();
+    my ($app,$table,$tview,$window) = software_main("../../../../../back/tmp",undef,) ;
+    $window->signal_connect (destroy => sub { gui_quite();});
 }
-	
- 
-
-
 
 sub software_main {
-	my ($sw,$file,$pages_ref,$label_ref) = @_;
-
-	
-
-	my $app = __PACKAGE__->new();
-	my ($table,$tview,$widget)=$app->build_gui($sw,$pages_ref,$label_ref);
-	my $main_c=(defined $file)? "$sw/$file" : "$sw/main.c";
-	my @tmp;
-	$app->open_list_ref(\@tmp);
-	$app->ask_to_save(def_button());
-	$app->load_source($main_c) if (-f $main_c );
-	return ($app,$table,$tview,$widget);
+    my ($sw,$file,$pages_ref,$label_ref) = @_;
+    my $app = __PACKAGE__->new();
+    my ($table,$tview,$widget)=$app->build_gui($sw,$pages_ref,$label_ref);
+    my $main_c=(defined $file)? "$sw/$file" : "$sw/main.c";
+    my @tmp;
+    $app->open_list_ref(\@tmp);
+    $app->ask_to_save(def_button());
+    $app->load_source($main_c) if (-f $main_c );
+    return ($app,$table,$tview,$widget);
 }
 
-
-
-
 sub build_gui {
-	my ($app,$sw,$pages_ref,$label_ref) = @_;
-
-	
-	my $table= def_table(2,10,FALSE);	
-	
-	my $vbox = def_vbox(FALSE, 0);
-	my $scwin_text = add_widget_to_scrolled_win($vbox);
-
-	my ($scwin_info,$tview)= create_txview();
-	my ($tree_view,$tree_store) =$app->build_tree_view($sw);
-	my $scwin_dirs = add_widget_to_scrolled_win($tree_view);
-
-
-	my $hpaned = gen_hpaned($scwin_dirs,0.15,$scwin_text);
-	my $vpaned = gen_vpaned($hpaned,0.6,$scwin_info);
-
-	$table->attach_defaults ($vpaned,0, 10, 0,1);
-
-	my $window = def_popwin_size (84,84,'Source Editor','percent');
-		
-	my @menue_item=("$sw/",$window,$tree_view,$tree_store,$scwin_dirs);	
-	$app->menue(\@menue_item);	
-	if (defined $pages_ref){
-		#first page is software editor
-		my $notebook = gen_notebook();
-		
-		my $label1=def_image_label($path."icons/binary.png","Software Editor",1);
-		$notebook->append_page ($table,$label1);
-		$label1->show_all;
-		
-		
-		my @pages=@{$pages_ref};
-		my @labels=@{$label_ref};
-		my $i=0;
-		foreach my $page (@pages){
-			my $label=$labels[$i];
-			$notebook->append_page ($page,$label);
-			$label->show_all;
-			$i++;	
-		}
-		$notebook->show_all;
-		$notebook->set_current_page(0);
-		$window -> add ( $notebook);
-	}else {
-		$window -> add ( $table);
-	}
-	
-	$app->window($window);
-
-	
-	my $hbox = def_table(FALSE, 0);
-	my $source_view_notebook = gen_notebook();
-	$vbox->pack_start($hbox, FALSE, FALSE, 0);	
-	$vbox->pack_start($source_view_notebook, TRUE, TRUE, 0);
-	
-	
-	
-	
-	$app->source_view_notebook($source_view_notebook);
+    my ($app,$sw,$pages_ref,$label_ref) = @_;
+    my $table= def_table(2,10,FALSE);
+    my $vbox = def_vbox(FALSE, 0);
+    my $scwin_text = add_widget_to_scrolled_win($vbox);
+    my ($scwin_info,$tview)= create_txview();
+    my ($tree_view,$tree_store) =$app->build_tree_view($sw);
+    my $scwin_dirs = add_widget_to_scrolled_win($tree_view);
+    my $hpaned = gen_hpaned($scwin_dirs,0.15,$scwin_text);
+    my $vpaned = gen_vpaned($hpaned,0.6,$scwin_info);
+    $table->attach_defaults ($vpaned,0, 10, 0,1);
+    my $window = def_popwin_size (84,84,'Source Editor','percent');
+    my @menue_item=("$sw/",$window,$tree_view,$tree_store,$scwin_dirs);
+    $app->menue(\@menue_item);
+    if (defined $pages_ref){
+        #first page is software editor
+        my $notebook = gen_notebook();
+        my $label1=def_image_label($path."icons/binary.png","Software Editor",1);
+        $notebook->append_page ($table,$label1);
+        $label1->show_all;
+        my @pages=@{$pages_ref};
+        my @labels=@{$label_ref};
+        my $i=0;
+        foreach my $page (@pages){
+            my $label=$labels[$i];
+            $notebook->append_page ($page,$label);
+            $label->show_all;
+            $i++;
+        }
+        $notebook->show_all;
+        $notebook->set_current_page(0);
+        $window -> add ( $notebook);
+    }else {
+        $window -> add ( $table);
+    }
+    $app->window($window);
+    my $hbox = def_table(FALSE, 0);
+    my $source_view_notebook = gen_notebook();
+    $vbox->pack_start($hbox, FALSE, FALSE, 0);
+    $vbox->pack_start($source_view_notebook, TRUE, TRUE, 0);
+    $app->source_view_notebook($source_view_notebook);
     $window->show_all();
-	
-	$window->signal_connect ('delete_event'=> sub {
-		$app->ask_to_save_changes();		
-		return 0;
-		
-	}); 
-	
-	
-	
-	
-	
-	return ($table,$tview,$window);
+    $window->signal_connect ('delete_event'=> sub {
+        $app->ask_to_save_changes();
+        return 0;
+    });
+    return ($table,$tview,$window);
 }
 
 sub ask_to_save_changes{
-	my $app=shift;
-	my $save = $app->ask_to_save();
-	$save->clicked;	
+    my $app=shift;
+    my $save = $app->ask_to_save();
+    $save->clicked;
 }
 
 sub update_modified {
-	my $self=shift;
-	if($self->modified() ==2 ){
-		$self->set_source_label_modified(FALSE);
-		return;
-	}
-	elsif($self->modified() ==FALSE ){
-	   	#if ($buffer->get_modified()){
-	   		$self->set_source_label_modified(TRUE);
-	   	#}
-	}	
+    my $self=shift;
+    if($self->modified() ==2 ){
+        $self->set_source_label_modified(FALSE);
+        return;
+    }
+    elsif($self->modified() ==FALSE ){
+        #if ($buffer->get_modified()){
+            $self->set_source_label_modified(TRUE);
+        #}
+    }
 }
 
 sub new_source_view{
-	my ($app,$filename)=@_;
-	
+    my ($app,$filename)=@_;
     my $self = __PACKAGE__->new();
-    my ($name,$p,$suffix) = fileparse("$filename",qr"\..[^.]*$");	
-	my $label = gen_label_in_left ("${name}${suffix}");
-    $self->modified(2);#initial 
-	$self->label($label);
-	$self->filename($filename);
-	
-	my $hbox = def_table(FALSE, 0);
-	my $vbox = def_vbox(FALSE, 0);
-	my $ref =$app->menue();	
-	my ($sw,$window,$tree_view,$tree_store,$scwin_dirs) =@{$ref};	
+    my ($name,$p,$suffix) = fileparse("$filename",qr"\..[^.]*$");
+    my $label = gen_label_in_left ("${name}${suffix}");
+    $self->modified(2);#initial
+    $self->label($label);
+    $self->filename($filename);
+    my $hbox = def_table(FALSE, 0);
+    my $vbox = def_vbox(FALSE, 0);
+    my $ref =$app->menue();
+    my ($sw,$window,$tree_view,$tree_store,$scwin_dirs) =@{$ref};
     $hbox->attach($self->build_menu($sw,$window,$tree_view,$tree_store,$scwin_dirs,$app), 0, 1, 0,1,'shrink','shrink',2,2);
-  	
-	$hbox->attach_defaults($self->build_search_box, 1,2,0,1);
+    $hbox->attach_defaults($self->build_search_box, 1,2,0,1);
     $vbox->pack_start($hbox, FALSE, FALSE, 0);
-    
-	my $buffer = $self->create_SourceView_buffer();
-	my $sourceview = gen_SourceView_with_buffer($buffer);
-	$sourceview->signal_connect('key-press-event' => sub { handle_key( @_,$self ) } );
-	$sourceview->set_show_line_numbers(TRUE);
-	$sourceview->set_tab_width(2);
-	$sourceview->set_indent_on_tab(TRUE);
-	$sourceview->set_highlight_current_line(TRUE);
-	
-	
-    #	$sourceview->set_draw_spaces(['tab', 'newline']);
-	#
-	# Fix TextView's annoying paste behaviour when pasting with the mouse
-	# (middle button click). By default gtk will scroll the text view to the
-	# original place where the cursor is.
-	#
-	$sourceview->signal_connect(button_press_event => sub {
-		my ($view, $event) = @_;
-
-		# We're only interested on middle mouse clicks (mouse-paste)
-		return FALSE unless $event->button == 2;
-
-		# Remember the position of the paste
-		my (@coords) = $sourceview->window_to_buffer_coords('text', $event->x, $event->y);
-		my ($iter) = $sourceview->get_iter_at_position(@coords);
-		$self->{paste_mark} = $buffer->create_mark('paste', $iter, FALSE);
-
-		return FALSE;
-	});
-
-
-	#
-	# If a paste is done through the middle click then place the cursor at the end
-	# of the pasted text.
-	#
-	$buffer->signal_connect('paste-done' => sub {
-		my $mark = delete $self->{paste_mark} or return;
-
-		my $iter = $buffer->get_iter_at_mark($mark);
-		$buffer->place_cursor($iter);
-
-		$self->sourceview->scroll_to_mark(
-			$mark,
-			0.0,
-			FALSE,
-			0.0, 0.5
-		);
-		$buffer->delete_mark($mark);
-	});
-
-	$buffer->signal_connect('insert-text' => sub {
-		update_modified($self);		
-	});
-	$buffer->signal_connect('delete-range' => sub {
-		update_modified($self);		
-	});
-	
-
-
-	my $scroll = add_widget_to_scrolled_win($sourceview);
-	$vbox->pack_start($scroll, TRUE, TRUE, 0);
-	$self->sourceview($sourceview);
-	$self->buffer($sourceview->get_buffer);
-
-
-	my $notebook = $app->source_view_notebook();
-	my $close = def_button('x');
-	
-	my $box = def_hbox(FALSE,0);
-	$box->pack_start($label, TRUE, FALSE, 0);
-	$box->pack_start($close, TRUE, FALSE, 0);	
-	$notebook->append_page ($vbox,$box);
-	set_tip($box,"$filename");
-	$box->show_all;
-	$notebook->show_all();
-	my $n= $notebook->get_n_pages();
-	$notebook->set_current_page($n-1);
-	#save $sourceview ref in $app
-	my %srcviews;
-	my $ref2 = $app->sourceview();
-	if(defined $ref2){
-		%srcviews =%{$ref2};
-	}
-	$srcviews{$n-1}=$self;
-	$app->sourceview(\%srcviews);
-	
-	
-	$close->signal_connect("clicked" => sub {
-		#check if the file has been modified or not
-		if($self->modified()==TRUE){
-			my $r=create_dialog ("Save changes to documnet ${name}${suffix}?","If you do'nt save, changes will be permanently lost.",$path."icons/help.png","Save","Close without saving","Cancel");
-			return if ($r eq "Cancel");
-			if ($r eq "Save"){
-				$self->do_save();
-			}
-			
-		}
-		$vbox->destroy;
-		$box->destroy;
-		$self = undef;
-		my $ref =$app->open_list_ref();
-		my @new =remove_scolar_from_array($ref,$filename);
-		$app->open_list_ref(\@new);
-		
-	});
-	
-	my $save = $app->ask_to_save();
-    
+    my $buffer = $self->create_SourceView_buffer();
+    my $sourceview = gen_SourceView_with_buffer($buffer);
+    $sourceview->signal_connect('key-press-event' => sub { handle_key( @_,$self ) } );
+    $sourceview->set_show_line_numbers(TRUE);
+    $sourceview->set_tab_width(2);
+    $sourceview->set_indent_on_tab(TRUE);
+    $sourceview->set_highlight_current_line(TRUE);
+    #    $sourceview->set_draw_spaces(['tab', 'newline']);
+    #
+    # Fix TextView's annoying paste behaviour when pasting with the mouse
+    # (middle button click). By default gtk will scroll the text view to the
+    # original place where the cursor is.
+    #
+    $sourceview->signal_connect(button_press_event => sub {
+        my ($view, $event) = @_;
+        # We're only interested on middle mouse clicks (mouse-paste)
+        return FALSE unless $event->button == 2;
+        # Remember the position of the paste
+        my (@coords) = $sourceview->window_to_buffer_coords('text', $event->x, $event->y);
+        my ($iter) = $sourceview->get_iter_at_position(@coords);
+        $self->{paste_mark} = $buffer->create_mark('paste', $iter, FALSE);
+        return FALSE;
+    });
+    #
+    # If a paste is done through the middle click then place the cursor at the end
+    # of the pasted text.
+    #
+    $buffer->signal_connect('paste-done' => sub {
+        my $mark = delete $self->{paste_mark} or return;
+        my $iter = $buffer->get_iter_at_mark($mark);
+        $buffer->place_cursor($iter);
+        $self->sourceview->scroll_to_mark(
+            $mark,
+            0.0,
+            FALSE,
+            0.0, 0.5
+        );
+        $buffer->delete_mark($mark);
+    });
+    $buffer->signal_connect('insert-text' => sub {
+        update_modified($self);
+    });
+    $buffer->signal_connect('delete-range' => sub {
+        update_modified($self);
+    });
+    my $scroll = add_widget_to_scrolled_win($sourceview);
+    $vbox->pack_start($scroll, TRUE, TRUE, 0);
+    $self->sourceview($sourceview);
+    $self->buffer($sourceview->get_buffer);
+    my $notebook = $app->source_view_notebook();
+    my $close = def_button('x');
+    my $box = def_hbox(FALSE,0);
+    $box->pack_start($label, TRUE, FALSE, 0);
+    $box->pack_start($close, TRUE, FALSE, 0);
+    $notebook->append_page ($vbox,$box);
+    set_tip($box,"$filename");
+    $box->show_all;
+    $notebook->show_all();
+    my $n= $notebook->get_n_pages();
+    $notebook->set_current_page($n-1);
+    #save $sourceview ref in $app
+    my %srcviews;
+    my $ref2 = $app->sourceview();
+    if(defined $ref2){
+        %srcviews =%{$ref2};
+    }
+    $srcviews{$n-1}=$self;
+    $app->sourceview(\%srcviews);
+    $close->signal_connect("clicked" => sub {
+        #check if the file has been modified or not
+        if($self->modified()==TRUE){
+            my $r=create_dialog ("Save changes to documnet ${name}${suffix}?","If you do'nt save, changes will be permanently lost.",$path."icons/help.png","Save","Close without saving","Cancel");
+            return if ($r eq "Cancel");
+            if ($r eq "Save"){
+                $self->do_save();
+            }
+        }
+        $vbox->destroy;
+        $box->destroy;
+        $self = undef;
+        my $ref =$app->open_list_ref();
+        my @new =remove_scolar_from_array($ref,$filename);
+        $app->open_list_ref(\@new);
+    });
+    my $save = $app->ask_to_save();
     $save->signal_connect("clicked" => sub {
-		#check if the file has been modified or not
-		return if(!defined $self);
-		if($self->modified()==TRUE){
-			my $r=create_dialog ("Save changes to documnet ${name}${suffix}?"," ",$path."icons/help.png","Save","Continue without saving");
-			return if ($r eq "Continue without saving");
-			if ($r eq "Save"){
-				$self->do_save();
-			}
-			
-		}		
-	});    
-		
-	$self->close_b($close);	
-	return $self;	
+        #check if the file has been modified or not
+        return if(!defined $self);
+        if($self->modified()==TRUE){
+            my $r=create_dialog ("Save changes to documnet ${name}${suffix}?"," ",$path."icons/help.png","Save","Continue without saving");
+            return if ($r eq "Continue without saving");
+            if ($r eq "Save"){
+                $self->do_save();
+            }
+        }
+    });
+    $self->close_b($close);
+    return $self;
 }
 
-
-
 sub build_tree_view{
-	my ($app,$sw)=@_;
-
-	# Directory name, full path
-	my ($tree_store,$tree_view) =file_edit_tree();
-	
-#	$tree_view->signal_connect (button_release_event => sub{
-	$tree_view->signal_connect (row_activated  => sub{
-		my $tree_model = $tree_view->get_model();
-	 	my $selection = $tree_view->get_selection();
-	 	my $iter = $selection->get_selected();
-	 		
-	 	if(defined $iter){
-			my $path = $tree_model->get($iter, 1) ;
-			$path= substr $path, 0, -1;
-			#$self->do_save();
-			#print "open $path\n";
-			 $app->load_source($path) if(-f $path);
-		}
-		 return;
-	});
-
-
-	$tree_view->signal_connect ('row-expanded' => sub {
-		my ($tree_view, $iter, $tree_path) = @_;
-	 	my $tree_model = $tree_view->get_model();
-		my ($dir, $path) = $tree_model->get($iter);
-		
-		# for each of $iter's children add any subdirectories
-		my $child = $tree_model->iter_children ($iter);
-		
-		
-		my $r;
-		$r=$tree_model->iter_is_valid($child);
-		while ($child && $r ==1) {
-						
-	  		my ($dir, $path) = $tree_model->get($child, 0, 1);
-	  		add_to_tree($tree_view,$tree_store, $child, $dir, $path);
-	  		$child=treemodel_next_iter($child , $tree_model);
-	  		$r=$tree_model->iter_is_valid($child) if (defined $child);
-	  		
-	 	}
-		 return;
-});
-
-my $child = $tree_store->append(undef);
-	
-$tree_store->set($child, 0, $sw, 1, '/');
-add_to_tree($tree_view,$tree_store, $child, '/', "$sw/");
-return ($tree_view,$tree_store);
-
+    my ($app,$sw)=@_;
+    # Directory name, full path
+    my ($tree_store,$tree_view) =file_edit_tree();
+#    $tree_view->signal_connect (button_release_event => sub{
+    $tree_view->signal_connect (row_activated  => sub{
+        my $tree_model = $tree_view->get_model();
+        my $selection = $tree_view->get_selection();
+        my $iter = $selection->get_selected();
+        if(defined $iter){
+            my $path = $tree_model->get($iter, 1) ;
+            $path= substr $path, 0, -1;
+            #$self->do_save();
+            #print "open $path\n";
+            $app->load_source($path) if(-f $path);
+        }
+        return;
+    });
+    $tree_view->signal_connect ('row-expanded' => sub {
+        my ($tree_view, $iter, $tree_path) = @_;
+        my $tree_model = $tree_view->get_model();
+        my ($dir, $path) = $tree_model->get($iter);
+        # for each of $iter's children add any subdirectories
+        my $child = $tree_model->iter_children ($iter);
+        my $r;
+        $r=$tree_model->iter_is_valid($child);
+        while ($child && $r ==1) {
+            my ($dir, $path) = $tree_model->get($child, 0, 1);
+            add_to_tree($tree_view,$tree_store, $child, $dir, $path);
+            $child=treemodel_next_iter($child , $tree_model);
+            $r=$tree_model->iter_is_valid($child) if (defined $child);
+        }
+        return;
+    });
+    my $child = $tree_store->append(undef);
+    $tree_store->set($child, 0, $sw, 1, '/');
+    add_to_tree($tree_view,$tree_store, $child, '/', "$sw/");
+    return ($tree_view,$tree_store);
 }
 
-
-
 sub build_search_box {
-	my $self = shift;
-
-	# Elements of the search box
-	my $hbox = def_hbox(FALSE, 0);
-
-	my $search_entry = gen_entry();
-	$search_entry->signal_connect(activate => sub {$self->do_search()});
-	$search_entry->signal_connect(icon_release => sub {$self->do_search()});
-	$self->search_entry($search_entry);
-
-	my $search_regexp = gen_checkbutton('RegExp');
-	$search_regexp->signal_connect(toggled => sub {
-		$self->search_regexp($search_regexp->get_active);
-	});
-
-	my $search_case = gen_checkbutton('Case');
-	$search_case->signal_connect(toggled => sub {
-		$self->search_case($search_case->get_active);
-	});
-
-	
-	
-	my $search_icon = def_image_button($path."icons/browse.png");
-	$search_entry->set_icon_from_stock(primary => 'gtk-find');
-
-	
-	$hbox->pack_start($search_entry, TRUE, TRUE , 0);
-	$hbox->pack_start($search_regexp, FALSE, FALSE, 0);
-	$hbox->pack_start($search_case, FALSE, FALSE, 0);
-
-	return $hbox;
+    my $self = shift;
+    # Elements of the search box
+    my $hbox = def_hbox(FALSE, 0);
+    my $search_entry = gen_entry();
+    $search_entry->signal_connect(activate => sub {$self->do_search()});
+    $search_entry->signal_connect(icon_release => sub {$self->do_search()});
+    $self->search_entry($search_entry);
+    my $search_regexp = gen_checkbutton('RegExp');
+    $search_regexp->signal_connect(toggled => sub {
+        $self->search_regexp($search_regexp->get_active);
+    });
+    my $search_case = gen_checkbutton('Case');
+    $search_case->signal_connect(toggled => sub {
+        $self->search_case($search_case->get_active);
+    });
+    my $search_icon = def_image_button($path."icons/browse.png");
+    $search_entry->set_icon_from_stock(primary => 'gtk-find');
+    $hbox->pack_start($search_entry, TRUE, TRUE , 0);
+    $hbox->pack_start($search_regexp, FALSE, FALSE, 0);
+    $hbox->pack_start($search_case, FALSE, FALSE, 0);
+    return $hbox;
 }
 
 sub refresh_source {
-	my $app = shift;
-	my ($filename) = abs_path(@_);
-	
-	
-	my $ref =$app->open_list_ref();
-	my @open_list;
-	@open_list = @{$ref} if(defined $ref); 
-	#check if the file is opend before activate its notebook win, remove its content
-	my $pos=get_scolar_pos ($filename,@open_list);
-	my $self;
-	if (defined $pos){
-		my $notebook = $app->source_view_notebook();
-		$notebook->set_current_page($pos);
-		
-		my $ref = $app->sourceview();
-		if(defined $ref){
-			my %srcviews =%{$ref};
-			my $n = $notebook->get_current_page;
-			$self=$srcviews{$n};
-		}else {		
-			return;
-		}		
-	}
-	else {
-		$self=new_source_view($app,"$filename");
-		push(@open_list,$filename);
-		$app->open_list_ref(\@open_list);
-	
-	}
-	my $buffer = $self->buffer;
-
-	# Guess the programming language of the file
-	$self->detect_language($filename);
-
-	# Loading a file should not be undoable.
-	my $content;
-	do {
-		open my $handle, $filename or die "Can't read file $filename because $!";
-		local $/;
-		$content = <$handle>;
-		close $handle;
-	};
-	$buffer->begin_not_undoable_action();
-	$buffer->set_text($content);
-	$buffer->end_not_undoable_action();
-
-	#$buffer->set_modified(FALSE);
-	$buffer->place_cursor($buffer->get_start_iter);
-
-	
-		
-	my $notebook = $app->source_view_notebook();
-	$notebook->show_all();
-	
-	
-	#$self->window->set_title("$filename - $NAME");
+    my $app = shift;
+    my ($filename) = abs_path(@_);
+    my $ref =$app->open_list_ref();
+    my @open_list;
+    @open_list = @{$ref} if(defined $ref);
+    #check if the file is opend before activate its notebook win, remove its content
+    my $pos=get_scolar_pos ($filename,@open_list);
+    my $self;
+    if (defined $pos){
+        my $notebook = $app->source_view_notebook();
+        $notebook->set_current_page($pos);
+        my $ref = $app->sourceview();
+        if(defined $ref){
+            my %srcviews =%{$ref};
+            my $n = $notebook->get_current_page;
+            $self=$srcviews{$n};
+        }else {
+            return;
+        }
+    }
+    else {
+        $self=new_source_view($app,"$filename");
+        push(@open_list,$filename);
+        $app->open_list_ref(\@open_list);
+    }
+    my $buffer = $self->buffer;
+    # Guess the programming language of the file
+    $self->detect_language($filename);
+    # Loading a file should not be undoable.
+    my $content;
+    do {
+        open my $handle, $filename or die "Can't read file $filename because $!";
+        local $/;
+        $content = <$handle>;
+        close $handle;
+    };
+    $buffer->begin_not_undoable_action();
+    $buffer->set_text($content);
+    $buffer->end_not_undoable_action();
+    #$buffer->set_modified(FALSE);
+    $buffer->place_cursor($buffer->get_start_iter);
+    my $notebook = $app->source_view_notebook();
+    $notebook->show_all();
+    #$self->window->set_title("$filename - $NAME");
 }
-	
-	
-	
-	
-	
-	
-	
-
-
-
 
 sub load_source {
-	my $app = shift;
-	my ($filename) = abs_path(@_);
-	
-	
-	my $ref =$app->open_list_ref();
-	my @open_list;
-	@open_list = @{$ref} if(defined $ref); 
-	#check if the file is opend before activate its notebook win
-	my $pos=get_scolar_pos ($filename,@open_list);
-	
-	if (defined $pos){
-		my $notebook = $app->source_view_notebook();
-		$notebook->set_current_page($pos);
-		return;		
-	}
-	
-	
-	#create a new source view and load the file there
-	
-	my $self=new_source_view($app,"$filename");
-	
-	push(@open_list,$filename);
-	$app->open_list_ref(\@open_list);
-	
-	
-	
-	my $buffer = $self->buffer;
-
-	# Guess the programming language of the file
-	$self->detect_language($filename);
-
-	# Loading a file should not be undoable.
-	my $content;
-	do {
-		open my $handle, $filename or die "Can't read file $filename because $!";
-		local $/;
-		$content = <$handle>;
-		close $handle;
-	};
-	$buffer->begin_not_undoable_action();
-	$buffer->set_text($content);
-	$buffer->end_not_undoable_action();
-
-	#$buffer->set_modified(FALSE);
-	$buffer->place_cursor($buffer->get_start_iter);
-
-	
-		
-	my $notebook = $app->source_view_notebook();
-	$notebook->show_all();
-	
-	
-	#$self->window->set_title("$filename - $NAME");
+    my $app = shift;
+    my ($filename) = abs_path(@_);
+    my $ref =$app->open_list_ref();
+    my @open_list;
+    @open_list = @{$ref} if(defined $ref);
+    #check if the file is opend before activate its notebook win
+    my $pos=get_scolar_pos ($filename,@open_list);
+    if (defined $pos){
+        my $notebook = $app->source_view_notebook();
+        $notebook->set_current_page($pos);
+        return;
+    }
+    #create a new source view and load the file there
+    my $self=new_source_view($app,"$filename");
+    push(@open_list,$filename);
+    $app->open_list_ref(\@open_list);
+    my $buffer = $self->buffer;
+    # Guess the programming language of the file
+    $self->detect_language($filename);
+    # Loading a file should not be undoable.
+    my $content;
+    do {
+        open my $handle, $filename or die "Can't read file $filename because $!";
+        local $/;
+        $content = <$handle>;
+        close $handle;
+    };
+    $buffer->begin_not_undoable_action();
+    $buffer->set_text($content);
+    $buffer->end_not_undoable_action();
+    #$buffer->set_modified(FALSE);
+    $buffer->place_cursor($buffer->get_start_iter);
+    my $notebook = $app->source_view_notebook();
+    $notebook->show_all();
+    #$self->window->set_title("$filename - $NAME");
 }
 
-
 sub clear_highlighted {
-	my $self = shift;
-
-	my $highlighted = delete $self->{highlighted} or return;
-
-	my $buffer = $self->buffer;
-
-	my @iters;
-	foreach my $mark (@{ $highlighted->{marks} }) {
-		my $iter = $buffer->get_iter_at_mark($mark);
-		push @iters, $iter;
-		$buffer->delete_mark($mark);
-	}
-
-	$buffer->remove_tag_by_name($highlighted->{name}, @iters);
+    my $self = shift;
+    my $highlighted = delete $self->{highlighted} or return;
+    my $buffer = $self->buffer;
+    my @iters;
+    foreach my $mark (@{ $highlighted->{marks} }) {
+        my $iter = $buffer->get_iter_at_mark($mark);
+        push @iters, $iter;
+        $buffer->delete_mark($mark);
+    }
+    $buffer->remove_tag_by_name($highlighted->{name}, @iters);
 }
 
-
 sub get_text {
-	my $self = shift;
-	my $buffer = $self->buffer;
-	return $buffer->get_text($buffer->get_start_iter, $buffer->get_end_iter, FALSE);
+    my $self = shift;
+    my $buffer = $self->buffer;
+    return $buffer->get_text($buffer->get_start_iter, $buffer->get_end_iter, FALSE);
 }
 
-
 sub do_search {
-	my $self = shift;
-	my $criteria = $self->search_entry->get_text;
-	if ($criteria eq '') {return;}
-
-	my $case = $self->search_case;
-	my $buffer = $self->buffer;
-
-
-	# Start the search at the last search result or from the current cursor's
-	# position. As a fall back we also add the beginning of the document. Once we
-	# have the start position we can erase the previous search results.
-	my @start;
-	if (my $highlighted = $self->highlighted) {
-		# Search from the last match
-		push @start, $buffer->get_iter_at_mark($highlighted->{marks}[1]);
-		$self->clear_highlighted();
-	}
-	else {
-		# Search from the cursor
-		push @start, $buffer->get_iter_at_offset(
-			$buffer->get_property('cursor-position')
-		);
-	}
-	push @start, $buffer->get_start_iter;
-
-	my @iters;
-	#if ($self->search_regexp) {
-	if(1){	
-		# SourceView does not support regular expressions so we
-		# have to do the search by hand!
-
-		my $text = $self->get_text;
-		my $regexp;
-		if ($self->search_regexp){
-			$regexp = $case ? qr/$criteria/m : qr/$criteria/im;
-		}else {
-			$regexp = $case ? qr/\Q${criteria}\E/m : qr/\Q${criteria}\E/im;
-			
-		}
-
-		foreach my $iter (@start) {
-			# Tell Perl where to start the regexp lookup
-			pos($text) = $iter->get_offset;
-
-			if ($text =~ /($regexp)/g) {
-				my $word = $1;
-				my $pos = pos($text);
-				@iters = (
-					$buffer->get_iter_at_offset($pos - length($word)),
-					$buffer->get_iter_at_offset($pos),
-				);
-				last;
-			}
-		}
-	}
-	else {
-		# Use the builtin search mechanism
-		my $flags = $case ? [ ] : [ 'case-insensitive' ];
-		foreach my $iter (@start) {
-			#@iters = Gtk3::SourceView::Iter->forward_search($iter, $criteria, $flags);
-			last if @iters;
-		}
-	}
-
-	$self->show_highlighted(search => @iters) if @iters;
+    my $self = shift;
+    my $criteria = $self->search_entry->get_text;
+    if ($criteria eq '') {return;}
+    my $case = $self->search_case;
+    my $buffer = $self->buffer;
+    # Start the search at the last search result or from the current cursor's
+    # position. As a fall back we also add the beginning of the document. Once we
+    # have the start position we can erase the previous search results.
+    my @start;
+    if (my $highlighted = $self->highlighted) {
+        # Search from the last match
+        push @start, $buffer->get_iter_at_mark($highlighted->{marks}[1]);
+        $self->clear_highlighted();
+    }
+    else {
+        # Search from the cursor
+        push @start, $buffer->get_iter_at_offset(
+            $buffer->get_property('cursor-position')
+        );
+    }
+    push @start, $buffer->get_start_iter;
+    my @iters;
+    #if ($self->search_regexp) {
+    if(1){
+        # SourceView does not support regular expressions so we
+        # have to do the search by hand!
+        my $text = $self->get_text;
+        my $regexp;
+        if ($self->search_regexp){
+            $regexp = $case ? qr/$criteria/m : qr/$criteria/im;
+        }else {
+            $regexp = $case ? qr/\Q${criteria}\E/m : qr/\Q${criteria}\E/im;
+        }
+        foreach my $iter (@start) {
+            # Tell Perl where to start the regexp lookup
+            pos($text) = $iter->get_offset;
+            if ($text =~ /($regexp)/g) {
+                my $word = $1;
+                my $pos = pos($text);
+                @iters = (
+                    $buffer->get_iter_at_offset($pos - length($word)),
+                    $buffer->get_iter_at_offset($pos),
+                );
+                last;
+            }
+        }
+    }
+    else {
+        # Use the builtin search mechanism
+        my $flags = $case ? [ ] : [ 'case-insensitive' ];
+        foreach my $iter (@start) {
+            #@iters = Gtk3::SourceView::Iter->forward_search($iter, $criteria, $flags);
+            last if @iters;
+        }
+    }
+    $self->show_highlighted(search => @iters) if @iters;
 }
 
-
 sub show_highlighted {
-	my $self = shift;
-	my ($tag_name, $start, $end) = @_;
-	my $buffer = $self->buffer;
-
-	# Highlight the region, remember it and scroll to it
-	my $match_start = $buffer->create_mark('match-start', $start, TRUE);
-	my $match_end = $buffer->create_mark('match-end', $end, FALSE);
-
-	$buffer->apply_tag_by_name($tag_name, $start, $end);
-
-	# We have a callback that listens to when the cursor is placed and we don't
-	# want it to undo our work! So let's unhighlight the previous entry.
-	delete $self->{highlighted};
-	$buffer->place_cursor($end);
-
-	$self->sourceview->scroll_to_mark(
-		$match_start,
-		0.2,
-		FALSE,
-		0.0, 0.5
-	);
-
-	# Keep a reference to the markers once they have been added to the buffer.
-	# Using them before can be catastrophic (segmenation fault).
-	#
-	$self->highlighted({
-		name  => $tag_name,
-		marks => [$match_start, $match_end],
-	});
+    my $self = shift;
+    my ($tag_name, $start, $end) = @_;
+    my $buffer = $self->buffer;
+    # Highlight the region, remember it and scroll to it
+    my $match_start = $buffer->create_mark('match-start', $start, TRUE);
+    my $match_end = $buffer->create_mark('match-end', $end, FALSE);
+    $buffer->apply_tag_by_name($tag_name, $start, $end);
+    # We have a callback that listens to when the cursor is placed and we don't
+    # want it to undo our work! So let's unhighlight the previous entry.
+    delete $self->{highlighted};
+    $buffer->place_cursor($end);
+    $self->sourceview->scroll_to_mark(
+        $match_start,
+        0.2,
+        FALSE,
+        0.0, 0.5
+    );
+    # Keep a reference to the markers once they have been added to the buffer.
+    # Using them before can be catastrophic (segmenation fault).
+    #
+    $self->highlighted({
+        name  => $tag_name,
+        marks => [$match_start, $match_end],
+    });
 }
 
-
 sub do_file_new {
-	my ($self,$sw,$window,$tree_view,$tree_store,$scwin_dirs,$app) = @_;
-	
-	my $dialog = save_file_dialog('New file');
-	if(defined  $sw){
-		$dialog->set_current_folder ($sw); 
-		#print "open_in:$sw\n";
-		 
-	}
-
-	my $response = $dialog->run();
-	if ($response eq 'ok') {
-		my $file=$dialog->get_filename;
-		save_file($file,'');
-		$tree_view->destroy;
-		($tree_view,$tree_store) =$app->build_tree_view($sw);
-		add_widget_to_scrolled_win($tree_view,$scwin_dirs);
-		$scwin_dirs->show_all;
-		$app->load_source($file);	
-	}
-	$dialog->destroy();	
+    my ($self,$sw,$window,$tree_view,$tree_store,$scwin_dirs,$app) = @_;
+    my $dialog = save_file_dialog('New file');
+    if(defined  $sw){
+        $dialog->set_current_folder ($sw);
+        #print "open_in:$sw\n";
+    }
+    my $response = $dialog->run();
+    if ($response eq 'ok') {
+        my $file=$dialog->get_filename;
+        save_file($file,'');
+        $tree_view->destroy;
+        ($tree_view,$tree_store) =$app->build_tree_view($sw);
+        add_widget_to_scrolled_win($tree_view,$scwin_dirs);
+        $scwin_dirs->show_all;
+        $app->load_source($file);
+    }
+    $dialog->destroy();
 }
 
 sub do_remove{
-	my ($self,$sw,$window,$tree_view,$tree_store,$scwin_dirs,$app) = @_;
-	my $fname  = $self->filename;
-	my $r = yes_no_dialog ("Are you sure you want to permanently delete $fname file?");
-	return if $r eq 'no';
-	$self->close_b()->clicked;
-	unlink $fname;
-	$tree_view->destroy;
-	($tree_view,$tree_store) =$app->build_tree_view($sw);
-	add_widget_to_scrolled_win($tree_view,$scwin_dirs);
-	$scwin_dirs->show_all;
-	
-	
+    my ($self,$sw,$window,$tree_view,$tree_store,$scwin_dirs,$app) = @_;
+    my $fname  = $self->filename;
+    my $r = yes_no_dialog ("Are you sure you want to permanently delete $fname file?");
+    return if $r eq 'no';
+    $self->close_b()->clicked;
+    unlink $fname;
+    $tree_view->destroy;
+    ($tree_view,$tree_store) =$app->build_tree_view($sw);
+    add_widget_to_scrolled_win($tree_view,$scwin_dirs);
+    $scwin_dirs->show_all;
 }
 
-
 sub do_file_open {
-	my ($self,$sw,$window,$tree_view,$tree_store,$scwin_dirs,$app) = @_;
-
-	my $dialog = gen_file_dialog("Open file...");
-	$dialog->signal_connect(response => sub {
-		my ($dialog, $response) = @_;
-
-		if ($response eq 'ok') {
-			my $file = $dialog->get_filename;
-			return if -d $file;
-			$app->load_source($file);
-		}
-
-		$dialog->destroy();
-	});
-	$dialog->show();
+    my ($self,$sw,$window,$tree_view,$tree_store,$scwin_dirs,$app) = @_;
+    my $dialog = gen_file_dialog("Open file...");
+    $dialog->signal_connect(response => sub {
+        my ($dialog, $response) = @_;
+        if ($response eq 'ok') {
+            my $file = $dialog->get_filename;
+            return if -d $file;
+            $app->load_source($file);
+        }
+        $dialog->destroy();
+    });
+    $dialog->show();
 }
 
-
 sub do_show_about_dialog {
-	 about(Consts::VERSION);
+    about(Consts::VERSION);
 }
 
-
 sub do_ask_goto_line {
-	my $self = shift;
-	
-	my $dialog=new_dialog_with_buttons($self);
-	
-	my $hbox =def_hbox(FALSE, 0);
-	$hbox->pack_start(
-		gen_label_in_left("Line number: "),
-		FALSE, FALSE, 0
-	);
-	my $entry = gen_entry();
-	$hbox->pack_start($entry, TRUE, TRUE, 0);
-
-	$dialog->get_content_area->add($hbox);
-	$dialog->show_all();
-
-
-	# Signal handlers
-	$entry->signal_connect(activate => sub {
-		if ($entry->get_text =~ /(\d+)/) {
-			$dialog->response('ok');
-		}
-	});
-
-	# Run the dialog
-	my $response = $dialog->run();
-	
-	return unless $response eq 'ok';
-
-	return unless my ($line) = ($entry->get_text =~ /(\d+)/);
-	my $buffer = $self->buffer;
-	my $start = $buffer->get_iter_at_line($line - 1);
-	my $end = $start->copy;
-	$end->forward_to_line_end;
-
-	$self->clear_highlighted();
-	$self->show_highlighted(goto_line => $start, $end);
-	$dialog->destroy();
+    my $self = shift;
+    my $dialog=new_dialog_with_buttons($self);
+    my $hbox =def_hbox(FALSE, 0);
+    $hbox->pack_start(
+        gen_label_in_left("Line number: "),
+        FALSE, FALSE, 0
+    );
+    my $entry = gen_entry();
+    $hbox->pack_start($entry, TRUE, TRUE, 0);
+    $dialog->get_content_area->add($hbox);
+    $dialog->show_all();
+    # Signal handlers
+    $entry->signal_connect(activate => sub {
+        if ($entry->get_text =~ /(\d+)/) {
+            $dialog->response('ok');
+        }
+    });
+    # Run the dialog
+    my $response = $dialog->run();
+    return unless $response eq 'ok';
+    return unless my ($line) = ($entry->get_text =~ /(\d+)/);
+    my $buffer = $self->buffer;
+    my $start = $buffer->get_iter_at_line($line - 1);
+    my $end = $start->copy;
+    $end->forward_to_line_end;
+    $self->clear_highlighted();
+    $self->show_highlighted(goto_line => $start, $end);
+    $dialog->destroy();
 }
 
-
 sub do_quit {
-	my ($self,$window) = @_;
-	$window->destroy;
+    my ($self,$window) = @_;
+    $window->destroy;
 }
 
-
 sub do_save_as {
-	my ($self,$sw,$window,$tree_view,$tree_store,$scwin_dirs,$app) = @_;
-
-	# If no file is associated with the editor then ask the user for a file where
-	# to save the contents of the buffer.
-	my $dialog = save_file_dialog('Save file');
-	if(defined  $sw){
-		$dialog->set_current_folder ($sw); 
-		#print "open_in:$sw\n";
-		 
-	}
-
-	my $response = $dialog->run();
-	if ($response eq 'ok') {
-		my $file=$dialog->get_filename;
-		
-		my $buffer = $self->buffer;
-		open my $handle, '>:encoding(UTF-8)', $file or die "Can't write to $file: $!";
-		print $handle $self->get_text;
-		close $handle;
-		
-		$tree_view->destroy;
-		($tree_view,$tree_store) =$app->build_tree_view($sw);
-		add_widget_to_scrolled_win($tree_view,$scwin_dirs);
-		$scwin_dirs->show_all;
-		$app->load_source($file);
-		
-	
-	}
-	$dialog->destroy();
-	
-
+    my ($self,$sw,$window,$tree_view,$tree_store,$scwin_dirs,$app) = @_;
+    # If no file is associated with the editor then ask the user for a file where
+    # to save the contents of the buffer.
+    my $dialog = save_file_dialog('Save file');
+    if(defined  $sw){
+        $dialog->set_current_folder ($sw);
+        #print "open_in:$sw\n";
+    }
+    my $response = $dialog->run();
+    if ($response eq 'ok') {
+        my $file=$dialog->get_filename;
+        my $buffer = $self->buffer;
+        open my $handle, '>:encoding(UTF-8)', $file or die "Can't write to $file: $!";
+        print $handle $self->get_text;
+        close $handle;
+        $tree_view->destroy;
+        ($tree_view,$tree_store) =$app->build_tree_view($sw);
+        add_widget_to_scrolled_win($tree_view,$scwin_dirs);
+        $scwin_dirs->show_all;
+        $app->load_source($file);
+    }
+    $dialog->destroy();
 }
 
-
 sub do_save {
-	my $self = shift;
-
-	my $filename = $self->filename;
-
-	# If there's no file then do a save as...
-	if (! $filename) {
-		#$self->do_save_as();
-		return;
-	}
-
-	my $buffer = $self->buffer;
-	open my $handle, '>:encoding(UTF-8)', $filename or die "Can't write to $filename: $!";
-	print $handle $self->get_text;
-	close $handle;
-	$self->set_source_label_modified(FALSE);
-	if (! $buffer->get_language) {
-		$self->detect_language($filename);
-	}
+    my $self = shift;
+    my $filename = $self->filename;
+    # If there's no file then do a save as...
+    if (! $filename) {
+        #$self->do_save_as();
+        return;
+    }
+    my $buffer = $self->buffer;
+    open my $handle, '>:encoding(UTF-8)', $filename or die "Can't write to $filename: $!";
+    print $handle $self->get_text;
+    close $handle;
+    $self->set_source_label_modified(FALSE);
+    if (! $buffer->get_language) {
+        $self->detect_language($filename);
+    }
 }
 
-
 sub set_source_label_modified{
-	my ($self,$is_modified)=@_;
-	$self->modified($is_modified); 
-	my $buffer = $self->buffer;
-	$buffer->set_modified($is_modified); 
-	my $label=$self->label(); 
-    my $fname = $self->filename; 
-    my ($name,$p,$suffix) = fileparse("$fname",qr"\..[^.]*$");	
-   
+    my ($self,$is_modified)=@_;
+    $self->modified($is_modified);
+    my $buffer = $self->buffer;
+    $buffer->set_modified($is_modified);
+    my $label=$self->label();
+    my $fname = $self->filename;
+    my ($name,$p,$suffix) = fileparse("$fname",qr"\..[^.]*$");
     if ($is_modified ==TRUE){
-    	$label->set_markup("<span  foreground= 'black' ><b>*${name}${suffix}</b></span>");
-    }else{	   
-    	$label->set_markup("<span  foreground= 'black' >${name}${suffix}</span>");
-    	
-    }	    
-	$label->show_all;		  
+        $label->set_markup("<span  foreground= 'black' ><b>*${name}${suffix}</b></span>");
+    }else{
+        $label->set_markup("<span  foreground= 'black' >${name}${suffix}</span>");
+    }
+    $label->show_all;
 }
 
 sub build_menu {
-	my ($self,$sw,$window,$tree_view,$tree_store,$scwin_dirs,$app) = @_;
-
-
-
- my @menu_items = (
-  [ "/_File",            undef,        undef,          0, "<Branch>" ],
-  [ "/File/_New",       "<control>N", sub { $self->do_file_new($sw,$window,$tree_view,$tree_store,$scwin_dirs,$app); },  0,  undef ],
-  [ "/File/_Open",      "<control>O", sub { $self->do_file_open($sw,$window,$tree_view,$tree_store,$scwin_dirs,$app) },  0, undef  ],
-  [ "/File/_Save",      "<control>S", sub { $self->do_save($sw,$window,$tree_view,$tree_store,$scwin_dirs,$app)      },  0, undef  ],
-  [ "/File/_SaveAs",	"<control><shift>S", sub { $self->do_save_as($sw,$window,$tree_view,$tree_store,$scwin_dirs,$app)} , 0, undef],
-  [ "/File/_Delete",	"<control>D", sub { $self->do_remove($sw,$window,$tree_view,$tree_store,$scwin_dirs,$app)} , 0, undef],
-  [ "/File/_Quit",		"<control>Q", sub { $self->do_quit($window) },  0, undef  ],
-		
-  [ "/_Search",           undef,        undef,          0, "<Branch>" ],
-  [ "/Search/_Goto a Line",  "<control>L", 	sub { $self->do_ask_goto_line($sw,$window,$tree_view,$tree_store,$scwin_dirs,$app)},  0, undef  ],
-
-  [ "/_Help", 		undef,		undef,          0, 	"<Branch>" ],
-  [ "/_Help/_About",  	"F1", 		sub { $self->do_show_about_dialog($sw,$window,$tree_view,$tree_store,$scwin_dirs,$app) } ,	0,	undef ],
- 
-
-
-);
-	
-
-	return gen_MenuBar($window,@menu_items);    
-		
+    my ($self,$sw,$window,$tree_view,$tree_store,$scwin_dirs,$app) = @_;
+    my @menu_items = (
+    [ "/_File",            undef,        undef,          0, "<Branch>" ],
+    [ "/File/_New",       "<control>N", sub { $self->do_file_new($sw,$window,$tree_view,$tree_store,$scwin_dirs,$app); },  0,  undef ],
+    [ "/File/_Open",      "<control>O", sub { $self->do_file_open($sw,$window,$tree_view,$tree_store,$scwin_dirs,$app) },  0, undef  ],
+    [ "/File/_Save",      "<control>S", sub { $self->do_save($sw,$window,$tree_view,$tree_store,$scwin_dirs,$app)      },  0, undef  ],
+    [ "/File/_SaveAs",    "<control><shift>S", sub { $self->do_save_as($sw,$window,$tree_view,$tree_store,$scwin_dirs,$app)} , 0, undef],
+    [ "/File/_Delete",    "<control>D", sub { $self->do_remove($sw,$window,$tree_view,$tree_store,$scwin_dirs,$app)} , 0, undef],
+    [ "/File/_Quit",        "<control>Q", sub { $self->do_quit($window) },  0, undef  ],
+    [ "/_Search",           undef,        undef,          0, "<Branch>" ],
+    [ "/Search/_Goto a Line",  "<control>L",     sub { $self->do_ask_goto_line($sw,$window,$tree_view,$tree_store,$scwin_dirs,$app)},  0, undef  ],
+    [ "/_Help",         undef,        undef,          0,     "<Branch>" ],
+    [ "/_Help/_About",      "F1",         sub { $self->do_show_about_dialog($sw,$window,$tree_view,$tree_store,$scwin_dirs,$app) } ,    0,    undef ],
+    );
+    return gen_MenuBar($window,@menu_items);
 }
 
-
-
 sub add_to_tree {
- my ($tree_view,$tree_store, $parent, $dir, $path) = @_;
-my $tree_model = $tree_view->get_model();
-
-# If $parent already has children, then remove them first
- 
- my $child = $tree_model->iter_children ($parent);
- while ($child) {
-  
-  $tree_store->remove ($child);
-  $child = $tree_model->iter_children ($parent);
- }
-
-# Add children from directory listing
- opendir(DIRHANDLE, $path) || return ; #die "Cannot open directory:$path $!\n";
- foreach my $subdir (sort readdir(DIRHANDLE)) {
-  if ($subdir ne '.' and $subdir ne '..'
-                                   # and -d $path.$subdir and -r $path.$subdir
-) {
-   my $child = $tree_store->append($parent);
- 
-   
-   $tree_store->set($child, 0, $subdir, 1, "$path$subdir/") ;
-   
-  }
- }
- closedir(DIRHANDLE);
+    my ($tree_view,$tree_store, $parent, $dir, $path) = @_;
+    my $tree_model = $tree_view->get_model();
+    # If $parent already has children, then remove them first
+    my $child = $tree_model->iter_children ($parent);
+    while ($child) {
+        $tree_store->remove ($child);
+        $child = $tree_model->iter_children ($parent);
+    }
+    # Add children from directory listing
+    opendir(DIRHANDLE, $path) || return ; #die "Cannot open directory:$path $!\n";
+    foreach my $subdir (sort readdir(DIRHANDLE)) {
+        if ($subdir ne '.' and $subdir ne '..'
+        # and -d $path.$subdir and -r $path.$subdir
+        ) {
+            my $child = $tree_store->append($parent);
+        $tree_store->set($child, 0, $subdir, 1, "$path$subdir/") ;
+        }
+    }
+    closedir(DIRHANDLE);
 }
 
-
 # Directory expanded. Populate subdirectories in readiness.
-
 sub populate_treeo {
-
-# $iter has been expanded
- my ($tree_view,$tree_store, $iter, $tree_path) = @_;
- my $tree_model = $tree_view->get_model();
- my ($dir, $path) = $tree_model->get($iter);
-
-# for each of $iter's children add any subdirectories
- my $child = $tree_model->iter_children ($iter);
- while ($child) {
-  my ($dir, $path) = $tree_model->get($child, 0, 1);
-  add_to_tree($tree_view,$tree_store, $child, $dir, $path);
-  $child = $tree_model->iter_next ($child);
- }
- return;
+    # $iter has been expanded
+    my ($tree_view,$tree_store, $iter, $tree_path) = @_;
+    my $tree_model = $tree_view->get_model();
+    my ($dir, $path) = $tree_model->get($iter);
+    # for each of $iter's children add any subdirectories
+    my $child = $tree_model->iter_children ($iter);
+    while ($child) {
+        my ($dir, $path) = $tree_model->get($child, 0, 1);
+        add_to_tree($tree_view,$tree_store, $child, $dir, $path);
+        $child = $tree_model->iter_next ($child);
+    }
+    return;
 }
 
-
 sub run_make_file {
-	my ($dir,$outtext, $args)=@_;
-	my $cmd =	(defined $args) ? "cd \"$dir/\" \n  make $args" :  "cd \"$dir/\" \n  make ";
-	my $error=0;		
-	add_info($outtext,"$cmd\n");
-	
-	my ($stdout,$exit,$stderr)=run_cmd_in_back_ground_get_stdout( $cmd);
-	#($stdout,$exit,$stderr)=run_cmd_in_back_ground_get_stdout( $cmd);
-
-	
-	if($exit){
-		if($stderr){
-			$stderr=~ s/[‘,’]//g;
-			add_info($outtext,"$stdout\n"); 
-			add_colored_info($outtext,"$stderr\n","red"); 
-		}
-		add_colored_info($outtext,"Compilation failed.\n",'red');
-		print " failed!\n";   
-		return 0;
-
-	}else{
-		add_info($outtext,"$stdout\n"); 
-		if($stderr){ #probebly had warning
-			$stderr=~ s/[‘,’]//g;
-			#add_info($outtext,"$stdout\n"); 
-			add_colored_info($outtext,"$stderr\n","green"); 
-		}
-		
-		add_colored_info($outtext,"Compilation finished successfully.\n",'blue');
-		print " successful!\n";  
-		return 1;
-	}
-			
-	#add_info($outtext,"**********Quartus compilation is done successfully in $target_dir!*************\n") if($error==0);
-
-
-
+    my ($dir,$outtext, $args)=@_;
+    my $cmd =    (defined $args) ? "cd \"$dir/\" \n  make $args" :  "cd \"$dir/\" \n  make ";
+    my $error=0;
+    add_info($outtext,"$cmd\n");
+    my ($stdout,$exit,$stderr)=run_cmd_in_back_ground_get_stdout( $cmd);
+    #($stdout,$exit,$stderr)=run_cmd_in_back_ground_get_stdout( $cmd);
+    if($exit){
+        if($stderr){
+            $stderr=~ s/[‘,’]//g;
+            add_info($outtext,"$stdout\n");
+            add_colored_info($outtext,"$stderr\n","red");
+        }
+        add_colored_info($outtext,"Compilation failed.\n",'red');
+        print " failed!\n";
+        return 0;
+    }else{
+        add_info($outtext,"$stdout\n");
+        if($stderr){ #probebly had warning
+            $stderr=~ s/[‘,’]//g;
+            #add_info($outtext,"$stdout\n");
+            add_colored_info($outtext,"$stderr\n","green");
+        }
+        add_colored_info($outtext,"Compilation finished successfully.\n",'blue');
+        print " successful!\n";
+        return 1;
+    }
+    #add_info($outtext,"**********Quartus compilation is done successfully in $target_dir!*************\n") if($error==0);
 }
 
 sub handle_key {
@@ -990,26 +746,18 @@ sub handle_key {
     my $key = get_pressed_key ($event);
     my $buffer = $widget->get_buffer();
     if ( ($key eq 'f') && control_pressed( $event ) ) {
-    	
-    	
-    	my ($start, $end) = $buffer->get_selection_bounds;
-    	if (defined $start && defined $end){
-    		my $string = $buffer->get_text ($start, $end, 0);
-        	#print "CTRL+F copy $string to serach box\n";
-        	$self->search_entry->set_text($string);
-    	}
+        my ($start, $end) = $buffer->get_selection_bounds;
+        if (defined $start && defined $end){
+            my $string = $buffer->get_text ($start, $end, 0);
+            #print "CTRL+F copy $string to serach box\n";
+            $self->search_entry->set_text($string);
+        }
     }
-    
     return FALSE; # FALSE -> means propagate key further
 }
 
 sub control_pressed {
     my ( $event ) = @_;
-
     return $event->state & 'control-mask';
 }
-
-
-
-1;
-
+1;
\ No newline at end of file
diff --git a/mpsoc/perl_gui/lib/perl/sv_parser.pl b/mpsoc/perl_gui/lib/perl/sv_parser.pl
index 1156382..c736f54 100644
--- a/mpsoc/perl_gui/lib/perl/sv_parser.pl
+++ b/mpsoc/perl_gui/lib/perl/sv_parser.pl
@@ -2,28 +2,21 @@
 
 use strict;
 use warnings;
-
 use FindBin;
 use lib $FindBin::Bin;
-
-
 use Regexp::Common qw /comment/;
 require "common.pl";
 
-
 sub extract_sv_code {
-	my $file=shift;
-	my $text = load_file($file);
-	$text =~ s/($RE{comment}{'C++'})//g;
+    my $file=shift;
+    my $text = load_file($file);
+    $text =~ s/($RE{comment}{'C++'})//g;
     return $text;
-       
-
 }
 
-
 sub read_sv_file {
-	my $file=shift;
-	#read file and remove all comments
-	my $code = extract_sv_code($file); 
-	print $code;
-}
+    my $file=shift;
+    #read file and remove all comments
+    my $code = extract_sv_code($file); 
+    print $code;
+}
\ No newline at end of file
diff --git a/mpsoc/perl_gui/lib/perl/temp.pl b/mpsoc/perl_gui/lib/perl/temp.pl
index 5f2c8a8..1377263 100755
--- a/mpsoc/perl_gui/lib/perl/temp.pl
+++ b/mpsoc/perl_gui/lib/perl/temp.pl
@@ -1,38 +1,28 @@
 #!/usr/bin/perl -w
-
 use strict;
 use warnings;
 use IO::CaptureOutput qw(capture qxx qxy);
 use Gtk3;
-
-
-
 my ($screen_x,$screen_y);
 
 sub get_default_screen_size{
-	return  ($screen_x,$screen_y) if (defined $screen_x && defined $screen_y);
-	my $fh= 'xrandr --current | awk \'$2~/\*/{print $1}\'' ;
-	my ($stdout, $stderr, $success) = qxx( ($fh) );
-	my @a = split ("\n",$stdout);
-	my ($screen_x,$screen_y) = split ("x",$a[0]);
-	$screen_x = 600 if(!defined $screen_x);
-	$screen_y = 800 if(!defined $screen_y);
-	return  ($screen_x,$screen_y);
-} 
-
-
+    return  ($screen_x,$screen_y) if (defined $screen_x && defined $screen_y);
+    my $fh= 'xrandr --current | awk \'$2~/\*/{print $1}\'' ;
+    my ($stdout, $stderr, $success) = qxx( ($fh) );
+    my @a = split ("\n",$stdout);
+    my ($screen_x,$screen_y) = split ("x",$a[0]);
+    $screen_x = 600 if(!defined $screen_x);
+    $screen_y = 800 if(!defined $screen_y);
+    return  ($screen_x,$screen_y);
+}
 
 my ($x,$y)  =get_default_screen_size();
 print "$x,$y\n";
-
-
-
 sub get_screen_size{
     my $screen = Gtk3::Gdk::Screen::get_default;
-	my $hight = $screen->get_height(); 
-	my $width = $screen->get_width(); 
-	return ($width,$hight);
+    my $hight = $screen->get_height();
+    my $width = $screen->get_width();
+    return ($width,$hight);
 }
-
 ($x,$y)  =get_screen_size();
 print "$x,$y\n";
diff --git a/mpsoc/perl_gui/lib/perl/topology.pl b/mpsoc/perl_gui/lib/perl/topology.pl
index 69906ab..0ae06f0 100644
--- a/mpsoc/perl_gui/lib/perl/topology.pl
+++ b/mpsoc/perl_gui/lib/perl/topology.pl
@@ -10,49 +10,43 @@
 use lib $FindBin::Bin;
 
 sub get_topology_info {
-	my ($self,$noc_id) =@_;
-	$noc_id="" if (!defined $noc_id);
-	my $noc_param="noc_param$noc_id";
-	my $topology=$self->object_get_attribute($noc_param,'TOPOLOGY');
-	my $T1=$self->object_get_attribute($noc_param,'T1');
-	my $T2=$self->object_get_attribute($noc_param,'T2');
-	my $T3=$self->object_get_attribute($noc_param,'T3');
-	my $V = $self->object_get_attribute($noc_param,'V');
-	my $Fpay = $self->object_get_attribute($noc_param,'Fpay');
-	
-	return get_topology_info_sub($topology, $T1, $T2, $T3,$V, $Fpay);	
-}	
-
+    my ($self,$noc_id) =@_;
+    $noc_id="" if (!defined $noc_id);
+    my $noc_param="noc_param$noc_id";
+    my $topology=$self->object_get_attribute($noc_param,'TOPOLOGY');
+    my $T1=$self->object_get_attribute($noc_param,'T1');
+    my $T2=$self->object_get_attribute($noc_param,'T2');
+    my $T3=$self->object_get_attribute($noc_param,'T3');
+    my $T4=$self->object_get_attribute($noc_param,'T4');
+    my $V = $self->object_get_attribute($noc_param,'V');
+    my $Fpay = $self->object_get_attribute($noc_param,'Fpay');
+    return get_topology_info_sub($topology, $T1, $T2, $T3, $T4, $V, $Fpay);    
+}    
 
 sub get_topology_info_from_parameters {
-	my ($ref) =@_;
-	my %noc_info;
-	my %param= %$ref if(defined $ref );			
-	my $topology=$param{'TOPOLOGY'};
-	my $T1  =$param{'T1'};
-	my $T2  =$param{'T2'};
-	my $T3  =$param{'T3'};
-	my $V   =$param{'V'};
-	my $Fpay=$param{'Fpay'};	
-	print "lllllllllllllll\n";
-	return get_topology_info_sub($topology, $T1, $T2, $T3,$V, $Fpay);	
+    my ($ref) =@_;
+    my %noc_info;
+    my %param= %$ref if(defined $ref );            
+    my $topology=$param{'TOPOLOGY'};
+    my $T1  =$param{'T1'};
+    my $T2  =$param{'T2'};
+    my $T3  =$param{'T3'};
+    my $T4  =$param{'T4'};
+    my $V   =$param{'V'};
+    my $Fpay=$param{'Fpay'};   
+    return get_topology_info_sub($topology, $T1, $T2, $T3, $T4,$V, $Fpay);    
 }
 
-
-
 sub get_topology_info_sub {
-
-	my ($topology, $T1, $T2, $T3,$V, $Fpay)=@_;
-	
-	my $NE; # number of end points
-	my $NR; # number of routers
-	my $RAw; # routers address width
-	my $EAw; # Endpoints address width
-	
-	
-	my $Fw = 2+$V+$Fpay; 
-	if($topology eq '"TREE"') {
-		my $K =  $T1;
+    my ($topology, $T1, $T2, $T3, $T4, $V, $Fpay)=@_;
+    my $NE;    # Total number of end points (local ports) in the NoC
+    my $NR;    # Total number of routers in NoC
+    my $RAw;   # Routers address width
+    my $EAw;   # Endpoints address width
+    my $MAX_P; # Maximum number of ports in any router in the NoC
+    my $Fw = 2+$V+$Fpay; 
+    if($topology eq '"TREE"') {
+        my $K =  $T1;
         my $L =  $T2;
         $NE = powi( $K,$L );
         $NR = sum_powi ( $K,$L );
@@ -60,681 +54,664 @@ sub get_topology_info_sub {
         my $LKw=$L*$Kw;
         my $Lw=log2($L);  
         $RAw=$LKw + $Lw;   
-        $EAw = $LKw;          
-	
-	}elsif($topology eq '"FATTREE"') {
-		my $K =  $T1;
+        $EAw = $LKw;  
+        $MAX_P = $K + 1;       
+    }elsif($topology eq '"FATTREE"') {
+        my $K =  $T1;
         my $L =  $T2;
-		$NE = powi( $K,$L );
+        $NE = powi( $K,$L );
         $NR = $L * powi( $K , $L - 1 );
         my $Kw=log2($K);
         my $LKw=$L*$Kw;
         my $Lw=log2($L);  
         $RAw=$LKw + $Lw;   
         $EAw = $LKw;      
-		
-	}elsif ($topology eq '"RING"' || $topology eq '"LINE"'){
-		my $NX=$T1;
-		my $NY=1;
-		my $NL=$T3;
-		$NE = $NX*$NY*$NL;
+        $MAX_P = 2 * $K;
+    }elsif ($topology eq '"RING"' || $topology eq '"LINE"'){
+        my $NX=$T1;
+        my $NY=1;
+        my $NL=$T3;
+        $NE = $NX*$NY*$NL;
         $NR = $NX*$NY;    
         my $Xw=log2($NX);
         my $Yw=log2($NY); 
         my $Lw=log2($NL);               
         $RAw = $Xw; 
-        $EAw = ($NL==1) ? $RAw : $RAw + $Lw;		
-       
-	}elsif ($topology eq '"MESH"' || $topology eq '"TORUS"' ) {
-		my $NX=$T1;
-		my $NY=$T2;
-		my $NL=$T3;
-		$NE = $NX*$NY*$NL;
-		$NR = $NX*$NY;    
+        $EAw = ($NL==1) ? $RAw : $RAw + $Lw;    
+        $MAX_P =  2 + $NL;
+    }elsif ($topology eq '"MESH"' || $topology eq '"TORUS"' ) {
+        my $NX=$T1;
+        my $NY=$T2;
+        my $NL=$T3;
+        $NE = $NX*$NY*$NL;
+        $NR = $NX*$NY;    
         my $Xw=log2($NX);
         my $Yw=log2($NY); 
         my $Lw=log2($NL);         
         $RAw = $Xw + $Yw;
         $EAw = ($NL==1) ? $RAw : $RAw + $Lw;
-	}elsif ($topology eq '"FMESH"'){
-		my $NX=$T1;
-		my $NY=$T2;
-		my $NL=$T3;
-		$NE = $NX*$NY*$NL + 2*($NX + $NY);
-		$NR = $NX*$NY;    
+        $MAX_P =  4 + $NL;
+    }elsif ($topology eq '"MESH_3D"' ) {
+        my $NX=$T1;
+        my $NY=$T2;
+        my $NZ=$T3;
+        my $NL=$T4;
+        $NE = $NX*$NY*$NL*$NZ;
+        $NR = $NX*$NY*$NZ;    
+        my $Xw=log2($NX);
+        my $Yw=log2($NY); 
+        my $Lw=log2($NL);
+        my $Zw=log2($NZ);
+        $RAw = $Xw + $Yw + $Zw;
+        $EAw = ($NL==1) ? $RAw : $RAw + $Lw;
+        $MAX_P =  6 + $NL;
+    }elsif ($topology eq '"FMESH"'){
+        my $NX=$T1;
+        my $NY=$T2;
+        my $NL=$T3;
+        $NE = $NX*$NY*$NL + 2*($NX + $NY);
+        $NR = $NX*$NY;    
         my $Xw=log2($NX);
         my $Yw=log2($NY); 
         my $Lw=log2($NL);         
         $RAw = $Xw + $Yw;
-        $EAw = $RAw + log2(4+$NL);		
-		
-	}elsif ($topology eq '"STAR"' ) {	
-		$NE= $T1; 
-		$NR= 1;
-		$RAw=log2($NR);
-		$EAw=log2($NE);		
-	
-	}else{ #custom
-		$NE= $T1; 
-		$NR= $T2;
-		$RAw=log2($NR);
-		$EAw=log2($NE);		
-	}		
-	return ($NE, $NR, $RAw, $EAw, $Fw); 	
+        $EAw = $RAw + log2(4+$NL);    
+        $MAX_P =  4 + $NL;
+    }elsif ($topology eq '"STAR"' ) {    
+        $NE= $T1; 
+        $NR= 1;
+        $RAw=log2($NR);
+        $EAw=log2($NE);
+        $MAX_P = $NE;        
+    }else{ #custom
+        $NE= $T1; 
+        $NR= $T2;
+        $RAw=log2($NR);
+        $EAw=log2($NE);        
+        $MAX_P = $T3;        
+    }        
+    return ($NE, $NR, $RAw, $EAw, $Fw,$MAX_P);     
 }
 
 
 sub fattree_addrencode {
-	my ( $pos, $k, $l)=@_;
-	my  $pow; my $ tmp;
-	my $addrencode=0;
-	my $kw=log2($k);
-	$pow=1;
-	for (my $i = 0; $i <$l; $i=$i+1 ) {
-		$tmp=int($pos/$pow);
-		$tmp=$tmp % $k;
-		$tmp=$tmp << ($i)*$kw;
-		$addrencode=$addrencode | $tmp;
-		$pow=$pow * $k;
-	}
-	 return $addrencode;
+    my ( $pos, $k, $l)=@_;
+    my  $pow; my $ tmp;
+    my $addrencode=0;
+    my $kw=log2($k);
+    $pow=1;
+    for (my $i = 0; $i <$l; $i=$i+1 ) {
+        $tmp=int($pos/$pow);
+        $tmp=$tmp % $k;
+        $tmp=$tmp << ($i)*$kw;
+        $addrencode=$addrencode | $tmp;
+        $pow=$pow * $k;
+    }
+    return $addrencode;
 }
 
 sub fattree_addrdecode{
-	my ($addrencode, $k, $l)=@_;
-	my $kw=0;
-	my $mask=0;
-	my $pow; my $tmp;
-	my $pos=0;
-	while((0x1 << $kw) < $k){
-		$kw++;
-		$mask<<=1;
-		$mask|=0x1;
-	}
-	$pow=1;
-	for (my $i = 0; $i <$l; $i=$i+1 ) {
-		$tmp = $addrencode & $mask;
-		#printf("tmp1=%u\n",tmp);
-		$tmp=($tmp*$pow);
-		$pos= $pos + $tmp;
-		$pow=$pow * $k;
-		$addrencode>>=$kw;
-	}
-	return $pos;
+    my ($addrencode, $k, $l)=@_;
+    my $kw=0;
+    my $mask=0;
+    my $pow; my $tmp;
+    my $pos=0;
+    while((0x1 << $kw) < $k){
+        $kw++;
+        $mask<<=1;
+        $mask|=0x1;
+    }
+    $pow=1;
+    for (my $i = 0; $i <$l; $i=$i+1 ) {
+        $tmp = $addrencode & $mask;
+        #printf("tmp1=%u\n",tmp);
+        $tmp=($tmp*$pow);
+        $pos= $pos + $tmp;
+        $pow=$pow * $k;
+        $addrencode>>=$kw;
+    }
+    return $pos;
 }
 
-
-
-
-
-
-
-
-
 sub get_connected_router_id_to_endp{
-	my ($self,$endp_id)=@_;
-	my $topology=$self->object_get_attribute('noc_param','TOPOLOGY');
-	my $T1=$self->object_get_attribute('noc_param','T1');
-	my $T2=$self->object_get_attribute('noc_param','T2');
-	my $T3=$self->object_get_attribute('noc_param','T3');
-	if($topology eq '"FATTREE"' || $topology eq '"TREE"') {
-		return int($endp_id/$T1);
-	}elsif ($topology eq '"RING"' || $topology eq '"LINE"'  ||  $topology eq '"MESH"' || $topology eq '"TORUS"'){
-		 return int($endp_id/$T3);
-	}elsif ($topology eq '"STAR"' ) {	
-		 return 0;#there is only one routerin star topology
-	}elsif ($topology eq '"FMESH"'){
-		my $tmp = $T1*$T2*$T3;
-		return int($endp_id/$T3) if($endp_id<$tmp);
-		return $endp_id-$tmp if($endp_id<$tmp+$T1);
-		return ($endp_id-$tmp-$T1)+ $T1*($T2-1) if($endp_id<$tmp+2*$T1); 
-		return ($endp_id-$tmp-2*$T1)*$T1 if($endp_id<$tmp+2*$T1+$T2); 
-		return ($endp_id-$tmp-2*$T1-$T2+1)*$T1-1;
-		 
-	}else{#custom
-		my @er_addr = $self->object_get_attribute('noc_connection','er_addr');  
-		return $er_addr[$endp_id];		
-	}	
+    my ($self,$endp_id)=@_;
+    my $topology=$self->object_get_attribute('noc_param','TOPOLOGY');
+    my $T1=$self->object_get_attribute('noc_param','T1');
+    my $T2=$self->object_get_attribute('noc_param','T2');
+    my $T3=$self->object_get_attribute('noc_param','T3');
+    if($topology eq '"FATTREE"' || $topology eq '"TREE"') {
+        return int($endp_id/$T1);
+    }elsif ($topology eq '"RING"' || $topology eq '"LINE"'  ||  $topology eq '"MESH"' || $topology eq '"TORUS"'){
+        return int($endp_id/$T3);
+    }elsif ($topology eq '"STAR"' ) {    
+        return 0;#there is only one routerin star topology
+    }elsif ($topology eq '"FMESH"'){
+        my $tmp = $T1*$T2*$T3;
+        return int($endp_id/$T3) if($endp_id<$tmp);
+        return $endp_id-$tmp if($endp_id<$tmp+$T1);
+        return ($endp_id-$tmp-$T1)+ $T1*($T2-1) if($endp_id<$tmp+2*$T1); 
+        return ($endp_id-$tmp-2*$T1)*$T1 if($endp_id<$tmp+2*$T1+$T2); 
+        return ($endp_id-$tmp-2*$T1-$T2+1)*$T1-1;
+    }else{#custom
+        my @er_addr = $self->object_get_attribute('noc_connection','er_addr');  
+        return $er_addr[$endp_id];        
+    }    
 }
 
 
 sub fmesh_addrencode{ 
-	my($id,$T1,$T2,$T3)=@_;
-	my  ($y, $x, $l,$p, $diff,$mul);
-	$mul  = $T1*$T2*$T3; 
-	
-	my  $LOCAL   =   0;  
-	my	$EAST    =   1; 
-	my	$NORTH   =   2;  
-	my	$WEST    =   3;  
-	my	$SOUTH   =   4;  
-	           
-	if($id < $mul) { 
-		$y = (($id/$T3) / $T1 ); 
-		$x = (($id/$T3) % $T1 ); 
-		$l = ( $id %$T3); 
-		$p = ($l==0)? $LOCAL : 4+$l;		     
-	}else{       
-		$diff = $id -  $mul ;
-		if( $diff <  $T1){ #top mesh edge
-			$y = 0;
-			$x = $diff;
-			$p = $NORTH;			
-		}
-		elsif ( $diff < 2* $T1) { #bottom mesh edge 
-			$y = $T2-1;
-			$x = $diff-$T1;
-			$p = $SOUTH;			 
-		}
-	 	elsif ( $diff < (2* $T1)+$T2 ) { #left mesh edge 
-			$y = $diff - (2* $T1);
-			$x = 0;
-			$p = $WEST;			 
-		}
-		else {	#right mesh edge 
-			$y = $diff - (2* $T1) -$T2;
-			$x = $T1-1;
-			$p = $EAST; 
-		}
-	}
-	my $NXw=log2($T1);
-	my $NYw=log2($T2);
+    my($id,$T1,$T2,$T3)=@_;
+    my  ($y, $x, $l,$p, $diff,$mul);
+    $mul  = $T1*$T2*$T3; 
+    my  $LOCAL   =   0;  
+    my    $EAST    =   1; 
+    my    $NORTH   =   2;  
+    my    $WEST    =   3;  
+    my    $SOUTH   =   4;  
+    if($id < $mul) { 
+        $y = (($id/$T3) / $T1 ); 
+        $x = (($id/$T3) % $T1 ); 
+        $l = ( $id %$T3); 
+        $p = ($l==0)? $LOCAL : 4+$l;             
+    }else{       
+        $diff = $id -  $mul ;
+        if( $diff <  $T1){ #top mesh edge
+            $y = 0;
+            $x = $diff;
+            $p = $NORTH;            
+        }
+        elsif ( $diff < 2* $T1) { #bottom mesh edge 
+            $y = $T2-1;
+            $x = $diff-$T1;
+            $p = $SOUTH;             
+        }
+        elsif ( $diff < (2* $T1)+$T2 ) { #left mesh edge 
+            $y = $diff - (2* $T1);
+            $x = 0;
+            $p = $WEST;             
+        }
+        else {    #right mesh edge 
+            $y = $diff - (2* $T1) -$T2;
+            $x = $T1-1;
+            $p = $EAST; 
+        }
+    }
+    my $NXw=log2($T1);
+    my $NYw=log2($T2);
     my $addrencode=0;
     $addrencode = ($p << ($NXw+$NYw)|  ($y << $NXw) | $x);
-    return $addrencode;	
+    return $addrencode;    
 }   
 
 sub fmesh_endp_addr_decoder {
-	my ($code, $T1, $T2, $T3)=@_;
-	my ($x, $y, $p) =mesh_tori_addr_sep ($code, $T1, $T2, $T3);
-	my  $LOCAL   =   0;  
-	my	$EAST    =   1; 
-	my	$NORTH   =   2;  
-	my	$WEST    =   3;  
-	my	$SOUTH   =   4;  
-	return (($y*$T1)+$x)*$T3 if($p== $LOCAL);
-	return (($y*$T1)+$x)*$T3+($p-$SOUTH) if($p > $SOUTH);
-	return (($T1*$T2*$T3) + $x) if($p== $NORTH);
-	return (($T1*$T2*$T3) + $T1 + $x) if($p== $SOUTH);
-	return (($T1*$T2*$T3) + 2*$T1 + $y) if($p== $WEST );
-	return (($T1*$T2*$T3) + 2*$T1 + $T2 + $y) if($p== $EAST );
-	return 0; #should not reach here
+    my ($code, $T1, $T2, $T3)=@_;
+    my ($x, $y, $p) =mesh_tori_addr_sep ($code, $T1, $T2, $T3);
+    my  $LOCAL   =   0;  
+    my    $EAST    =   1; 
+    my    $NORTH   =   2;  
+    my    $WEST    =   3;  
+    my    $SOUTH   =   4;  
+    return (($y*$T1)+$x)*$T3 if($p== $LOCAL);
+    return (($y*$T1)+$x)*$T3+($p-$SOUTH) if($p > $SOUTH);
+    return (($T1*$T2*$T3) + $x) if($p== $NORTH);
+    return (($T1*$T2*$T3) + $T1 + $x) if($p== $SOUTH);
+    return (($T1*$T2*$T3) + 2*$T1 + $y) if($p== $WEST );
+    return (($T1*$T2*$T3) + 2*$T1 + $T2 + $y) if($p== $EAST );
+    return 0; #should not reach here
 }
-	
-	
-
-
 
 sub get_router_num {
-	my ($self,$x, $y)=@_;
-	my $topology=$self->object_get_attribute('noc_param','TOPOLOGY');
-	my $T1=$self->object_get_attribute('noc_param','T1');
-	my $T2=$self->object_get_attribute('noc_param','T2');
-	if($topology eq '"FATTREE"') {
-		return fattree_addrdecode($x, $T1, $T2);
-	}elsif ($topology eq '"RING"' || $topology eq '"LINE"' ||  $topology eq '"FMESH"'  ||  $topology eq '"MESH"' || $topology eq '"TORUS"'){
-		 return ($y*$T1)+$x;		
-	}else{#custom
-		#It is not used for custom & STAR topology 
-	}
+    my ($self,$x, $y)=@_;
+    my $topology=$self->object_get_attribute('noc_param','TOPOLOGY');
+    my $T1=$self->object_get_attribute('noc_param','T1');
+    my $T2=$self->object_get_attribute('noc_param','T2');
+    if($topology eq '"FATTREE"') {
+        return fattree_addrdecode($x, $T1, $T2);
+    }elsif ($topology eq '"RING"' || $topology eq '"LINE"' ||  $topology eq '"FMESH"'  ||  $topology eq '"MESH"' || $topology eq '"TORUS"'){
+        return ($y*$T1)+$x;        
+    }else{#custom
+        #It is not used for custom & STAR topology 
+    }
 }
 
 sub router_addr_encoder{
-	my ($self, $id)=@_;
-	my $topology=$self->object_get_attribute('noc_param','TOPOLOGY');
-	my $T1=$self->object_get_attribute('noc_param','T1');
-	my $T2=$self->object_get_attribute('noc_param','T2');
-	my $T3=$self->object_get_attribute('noc_param','T3');
-	if($topology eq '"FATTREE"' || $topology eq '"TREE"') {
-		return fattree_addrencode($id, $T1, $T2);
-	}elsif ($topology eq '"RING"' || $topology eq '"LINE"'  ||  $topology eq '"MESH"' || $topology eq '"FESH"' || $topology eq '"TORUS"'){
-		return mesh_tori_addrencode($id,$T1, $T2,1);
-	}else { #custom & STAR
-		return $id;		
-	}	
+    my ($self, $id)=@_;
+    my $topology=$self->object_get_attribute('noc_param','TOPOLOGY');
+    my $T1=$self->object_get_attribute('noc_param','T1');
+    my $T2=$self->object_get_attribute('noc_param','T2');
+    my $T3=$self->object_get_attribute('noc_param','T3');
+    if($topology eq '"FATTREE"' || $topology eq '"TREE"') {
+        return fattree_addrencode($id, $T1, $T2);
+    }elsif ($topology eq '"RING"' || $topology eq '"LINE"'  ||  $topology eq '"MESH"' || $topology eq '"FESH"' || $topology eq '"TORUS"'){
+        return mesh_tori_addrencode($id,$T1, $T2,1);
+    }else { #custom & STAR
+        return $id;        
+    }    
 }
 
 sub endp_addr_encoder{
-	my ($self, $id)=@_;
-	my $topology=$self->object_get_attribute('noc_param','TOPOLOGY');
-	my $T1=$self->object_get_attribute('noc_param','T1');
-	my $T2=$self->object_get_attribute('noc_param','T2');
-	my $T3=$self->object_get_attribute('noc_param','T3');
-	if($topology eq '"FATTREE"' || $topology eq '"TREE"') {
-		return fattree_addrencode($id, $T1, $T2);
-	}elsif ($topology eq '"MESH"' || $topology eq '"TORUS"'){
-		return mesh_tori_addrencode($id,$T1, $T2,$T3);
-	}elsif ($topology eq '"RING"' || $topology eq '"LINE"'){
-		return ring_line_addrencode($id,$T1, $T3);
-	}elsif ($topology eq '"FMESH"' ){
-		return 	fmesh_addrencode($id,$T1, $T2,$T3);
-	}else{#CUSTOM & STAR
-		return $id;
-	}
+    my ($self, $id)=@_;
+    my $topology=$self->object_get_attribute('noc_param','TOPOLOGY');
+    my $T1=$self->object_get_attribute('noc_param','T1');
+    my $T2=$self->object_get_attribute('noc_param','T2');
+    my $T3=$self->object_get_attribute('noc_param','T3');
+    if($topology eq '"FATTREE"' || $topology eq '"TREE"') {
+        return fattree_addrencode($id, $T1, $T2);
+    }elsif ($topology eq '"MESH"' || $topology eq '"TORUS"'){
+        return mesh_tori_addrencode($id,$T1, $T2,$T3);
+    }elsif ($topology eq '"RING"' || $topology eq '"LINE"'){
+        return ring_line_addrencode($id,$T1, $T3);
+    }elsif ($topology eq '"FMESH"' ){
+        return     fmesh_addrencode($id,$T1, $T2,$T3);
+    }else{#CUSTOM & STAR
+        return $id;
+    }
 }
 
 sub endp_addr_decoder {
-	my ($self,$code)=@_;
-	my $topology=$self->object_get_attribute('noc_param','TOPOLOGY');
-	my $T1=$self->object_get_attribute('noc_param','T1');
-	my $T2=$self->object_get_attribute('noc_param','T2');
-	my $T3=$self->object_get_attribute('noc_param','T3');
-	if($topology eq '"FATTREE"' || $topology eq '"TREE"') {
-		return fattree_addrdecode($code, $T1, $T2);
-	}
-	elsif ($topology eq '"RING"' || $topology eq '"LINE"'  ||  $topology eq '"MESH"' || $topology eq '"TORUS"'){
-		my ($x, $y, $l) = mesh_tori_addr_sep($code,$T1, $T2,$T3);
-		#print "my ($x, $y, $l) = mesh_tori_addr_sep($code,$T1, $T2,$T3);\n";
-		return (($y*$T1)+$x)*$T3+$l;
-	}elsif ($topology eq '"FMESH"' ){
-		return fmesh_endp_addr_decoder($code,$T1, $T2,$T3);
-	}else{#custom & STAR
-		return $code;
-	}
+    my ($self,$code)=@_;
+    my $topology=$self->object_get_attribute('noc_param','TOPOLOGY');
+    my $T1=$self->object_get_attribute('noc_param','T1');
+    my $T2=$self->object_get_attribute('noc_param','T2');
+    my $T3=$self->object_get_attribute('noc_param','T3');
+    if($topology eq '"FATTREE"' || $topology eq '"TREE"') {
+        return fattree_addrdecode($code, $T1, $T2);
+    }
+    elsif ($topology eq '"RING"' || $topology eq '"LINE"'  ||  $topology eq '"MESH"' || $topology eq '"TORUS"'){
+        my ($x, $y, $l) = mesh_tori_addr_sep($code,$T1, $T2,$T3);
+        #print "my ($x, $y, $l) = mesh_tori_addr_sep($code,$T1, $T2,$T3);\n";
+        return (($y*$T1)+$x)*$T3+$l;
+    }elsif ($topology eq '"FMESH"' ){
+        return fmesh_endp_addr_decoder($code,$T1, $T2,$T3);
+    }else{#custom & STAR
+        return $code;
+    }
 }
 
 sub mask_gen{
-	my $k=shift;
-	my $kw=0;
-	my $mask=0;
-	while((0x1 << $kw) < $k){
-		$kw++;
-		$mask<<=1;
-		$mask|=0x1;
-	}
-	return $mask;
+    my $k=shift;
+    my $kw=0;
+    my $mask=0;
+    while((0x1 << $kw) < $k){
+        $kw++;
+        $mask<<=1;
+        $mask|=0x1;
+    }
+    return $mask;
 }
 
 
 sub mesh_tori_addr_sep {
-	my ($code,$NX, $NY,$NL)=@_;
-	my ($x, $y, $l);
-	my $NXw=log2($NX);
-	my $NYw=log2($NY);
-	$x = $code &  mask_gen($NX);
-	$code>>=$NXw;
-	$y = $code &   mask_gen($NY);
-	$code>>=$NYw;
-	$l = $code;
-	return ($x, $y, $l);
+    my ($code,$NX, $NY,$NL)=@_;
+    my ($x, $y, $l);
+    my $NXw=log2($NX);
+    my $NYw=log2($NY);
+    $x = $code &  mask_gen($NX);
+    $code>>=$NXw;
+    $y = $code &   mask_gen($NY);
+    $code>>=$NYw;
+    $l = $code;
+    return ($x, $y, $l);
 }
 
 sub mesh_tori_addrencode{
-	my ($id,$T1, $T2,$T3)=@_;
-	my ($x,$y,$l)=mesh_tori_addrencod_sep($id,$T1,$T2,$T3);
+    my ($id,$T1, $T2,$T3)=@_;
+    my ($x,$y,$l)=mesh_tori_addrencod_sep($id,$T1,$T2,$T3);
     return mesh_tori_addr_join($x,$y,$l,$T1, $T2,$T3);
 }
 
 sub ring_line_addrencode {
-	my ($id,$T1, $T3)=@_;
-	my ($x,$y,$l)=mesh_tori_addrencod_sep($id,$T1,0,$T3);
-	return ring_line_addr_join($x,$y,$l,$T1, $T3);
+    my ($id,$T1, $T3)=@_;
+    my ($x,$y,$l)=mesh_tori_addrencod_sep($id,$T1,0,$T3);
+    return ring_line_addr_join($x,$y,$l,$T1, $T3);
 }
 
 sub  mesh_tori_addrencod_sep{
-	my ($id,$T1,$T2,$T3)=@_;
-	my ($x,$y,$l);
-	$l=$id % $T3; # id%NL
-	my $R= int($id / $T3);
-	$x= $R % $T1;# (id/NL)%NX
-	$y=int($R / $T1);# (id/NL)/NX
-	return ($x,$y,$l);	
+    my ($id,$T1,$T2,$T3)=@_;
+    my ($x,$y,$l);
+    $l=$id % $T3; # id%NL
+    my $R= int($id / $T3);
+    $x= $R % $T1;# (id/NL)%NX
+    $y=int($R / $T1);# (id/NL)/NX
+    return ($x,$y,$l);    
 }
 
 sub mesh_tori_addr_join {
-	my ($x, $y, $l,$T1, $T2,$T3)=@_;
-	my $NXw=log2($T1);
-	my $NYw=log2($T2);
+    my ($x, $y, $l,$T1, $T2,$T3)=@_;
+    my $NXw=log2($T1);
+    my $NYw=log2($T2);
     my $addrencode=0;
     $addrencode =($T3==1)?   ($y << $NXw | $x) : ($l << ($NXw+$NYw)|  ($y << $NXw) | $x);
     return $addrencode;
 }
 
 sub ring_line_addr_join {
-	my ($x, $y, $l,$T1, $T3)=@_;
-	my $NXw=log2($T1);
-	my $addrencode=0;
+    my ($x, $y, $l,$T1, $T3)=@_;
+    my $NXw=log2($T1);
+    my $addrencode=0;
     $addrencode =($T3==1)?  $x : ($l << $NXw) |  $x;
     return $addrencode;
 }
 
-
-
 sub mcast_partial_width {
         my ($p,$NE)=@_;
-		my @temp = split ("'h",$p);
-		if (defined $temp[1]){
-			#its hex format
-			my $m=0;
-			$p=remove_not_hex($temp[1]);
-			my @arr=split (//, $p);
-			foreach my $i (@arr) {        	
-				my $n=hex($i);
-				$m++ if($n & 0x1);
-				$m++ if($n & 0x2);
-				$m++ if($n & 0x4);
-				$m++ if($n & 0x8);
-			}
-		return $m;
-		}
-		#its bin format
-		@temp = split ("'b",$p);
-		if (defined $temp[1]){
-			my $m=0;
-			$p=remove_not_hex($temp[1]);
-			my @arr=split (//, $p);
-			foreach my $i (@arr) {        	
-				my $n=hex($i);
-				$m++ if($i);			
-			}
-		return $m;
-		}
-		return 0;#Error
-
+        my @temp = split ("'h",$p);
+        if (defined $temp[1]){
+            #its hex format
+            my $m=0;
+            $p=remove_not_hex($temp[1]);
+            my @arr=split (//, $p);
+            foreach my $i (@arr) {            
+                my $n=hex($i);
+                $m++ if($n & 0x1);
+                $m++ if($n & 0x2);
+                $m++ if($n & 0x4);
+                $m++ if($n & 0x8);
+            }
+        return $m;
+        }
+        #its bin format
+        @temp = split ("'b",$p);
+        if (defined $temp[1]){
+            my $m=0;
+            $p=remove_not_hex($temp[1]);
+            my @arr=split (//, $p);
+            foreach my $i (@arr) {            
+                my $n=hex($i);
+                $m++ if($i);            
+            }
+        return $m;
+        }
+        return 0;#Error
 }
 
-
-
 sub get_noc_verilator_top_modules_info {
-	my ($self) =@_;
-	
-	my $topology=$self->object_get_attribute('noc_param','TOPOLOGY');
-	my $T1=$self->object_get_attribute('noc_param','T1');
-	my $T2=$self->object_get_attribute('noc_param','T2');
-	my $T3=$self->object_get_attribute('noc_param','T3');
-	my $cast = $self->object_get_attribute('noc_param','MCAST_ENDP_LIST');		
-	my $CAST_TYPE= $self->object_get_attribute('noc_param','CAST_TYPE');	
-	my $DAw_OFFSETw  =  ($topology eq '"MESH"' || $topology eq '"TORUS"' || $topology eq '"FMESH"')?  $T1 : 0; 
-	
-	
-	my %tops;
-	my %nr_p; # number of routers have $p port num
-	my $router_p; #number of routers with different port number in topology 
-	
-	my ($ne, $nr, $RAw, $EAw)=get_topology_info($self); 
-
-	my $MCAST_PRTLw= mcast_partial_width($cast,$ne);
-	my $MCASTw =
+    my ($self) =@_;
+    my $topology=$self->object_get_attribute('noc_param','TOPOLOGY');
+    my $T1=$self->object_get_attribute('noc_param','T1');
+    my $T2=$self->object_get_attribute('noc_param','T2');
+    my $T3=$self->object_get_attribute('noc_param','T3');
+    my $T4=$self->object_get_attribute('noc_param','T4');
+    my $cast = $self->object_get_attribute('noc_param','MCAST_ENDP_LIST');
+    my $CAST_TYPE= $self->object_get_attribute('noc_param','CAST_TYPE');
+    my $DAw_OFFSETw  =  ($topology eq '"MESH"' || $topology eq '"TORUS"' || $topology eq '"FMESH"' ||  $topology eq '"MESH_3D"')?  $T1 : 0; 
+    my %tops;
+    my %nr_p; # number of routers have $p port num
+    my $router_p; #number of routers with different port number in topology 
+    my ($ne, $nr, $RAw, $EAw)=get_topology_info($self); 
+    my $MCAST_PRTLw= mcast_partial_width($cast,$ne);
+    my $MCASTw =
             ($CAST_TYPE eq '"MULTICAST_FULL"') ? $ne :
             ($CAST_TYPE eq '"MULTICAST_PARTIAL"' && $EAw >= $MCAST_PRTLw) ? $EAw +1 : 
             ($CAST_TYPE eq '"MULTICAST_PARTIAL"' && $EAw <  $MCAST_PRTLw) ? $MCAST_PRTLw +1 :
             $EAw +1; #broadcast
-	
-	my $DAw = ($CAST_TYPE eq '"UNICAST"') ?   $EAw: $MCASTw +  $DAw_OFFSETw;           
-	
-	my $custom_include="";
-	if($topology eq '"FATTREE"') {
-		my $K =  $T1;
-        my $L =  $T2;		
-        my $p2 = 2*$K;       
+    my $DAw = ($CAST_TYPE eq '"UNICAST"') ?   $EAw: $MCASTw +  $DAw_OFFSETw;           
+    my $custom_include="";
+    if($topology eq '"FATTREE"') {
+        my $K =  $T1;
+        my $L =  $T2;
+        my $p2 = 2*$K;
         $router_p=2;
         my $NRL= $ne/$K; #number of router in  each layer
         $nr_p{1}=$NRL;
         $nr_p{2}=$nr-$NRL;
         $nr_p{p1}=$K;
         $nr_p{p2}=2*$K;
-       
         %tops = (
-			#"Vrouter1" => "router_top_v_p${K}.v", 
-			#"Vrouter2" => "router_top_v_p${p2}.v", 
-			"Vrouter1" => "--top-module  router_top_v  -GP=${K}  ", 
-			"Vrouter2" => "--top-module  router_top_v  -GP=${p2} ", 
-	       # "Vnoc" => " --top-module noc_connection ",
-	 		
-    	);
-	}elsif ($topology eq '"TREE"'){
+            #"Vrouter1" => "router_top_v_p${K}.v", 
+            #"Vrouter2" => "router_top_v_p${p2}.v", 
+            "Vrouter1" => "--top-module  router_top_v  -GP=${K}  ", 
+            "Vrouter2" => "--top-module  router_top_v  -GP=${p2} ", 
+            # "Vnoc" => " --top-module noc_connection ",
+        );
+    }elsif ($topology eq '"TREE"'){
         my $K =  $T1;
-        my $L =  $T2;		
-        my $p2 = $K+1;       
+        my $L =  $T2;
+        my $p2 = $K+1;
         $router_p=2;# number of router with different port number                        
         $nr_p{1}=1;
         $nr_p{2}=$nr-1;
         $nr_p{p1}=$K;
         $nr_p{p2}=$K+1;
-       
         %tops = (
-			#"Vrouter1" => "router_top_v_p${K}.v", 
-			#"Vrouter2" => "router_top_v_p${p2}.v",
-			"Vrouter1" => "--top-module  router_top_v  -GP=${K}  ", 
-			"Vrouter2" => "--top-module  router_top_v  -GP=${p2} ",  
-	       # "Vnoc" => " --top-module noc_connection ", 		
-    	);
-		
-	}elsif ($topology eq '"RING"' || $topology eq '"LINE"'){
-		
-		$router_p=1;
-		$nr_p{1}=$nr;
-		my $ports= 3+$T3-1;
-		$nr_p{p1}=$ports;
-		%tops = (
-			#"Vrouter1" => "router_top_v_p${ports}.v", 
-	       "Vrouter1" => "--top-module  router_top_v  -GP=${ports}  ", 
-		  # "Vnoc" => " --top-module noc_connection ",
-	 		
-    	);
-				
-       
-	}elsif ($topology eq '"MESH"' || $topology eq '"TORUS"' || $topology eq '"FMESH"') {
-		
+            #"Vrouter1" => "router_top_v_p${K}.v", 
+            #"Vrouter2" => "router_top_v_p${p2}.v",
+            "Vrouter1" => "--top-module  router_top_v  -GP=${K}  ", 
+            "Vrouter2" => "--top-module  router_top_v  -GP=${p2} ",  
+            # "Vnoc" => " --top-module noc_connection ",         
+        );
+    }elsif ($topology eq '"RING"' || $topology eq '"LINE"'){
+        
+        $router_p=1;
+        $nr_p{1}=$nr;
+        my $ports= 3+$T3-1;
+        $nr_p{p1}=$ports;
+        %tops = (
+            #"Vrouter1" => "router_top_v_p${ports}.v", 
+            "Vrouter1" => "--top-module  router_top_v  -GP=${ports}  ", 
+            # "Vnoc" => " --top-module noc_connection ",
+        );
+    }elsif ($topology eq '"MESH"' || $topology eq '"TORUS"' || $topology eq '"FMESH"') {
         $router_p=1;
         $nr_p{1}=$nr;
         my $ports= 5+$T3-1;
-		$nr_p{p1}=$ports;
+        $nr_p{p1}=$ports;
         %tops = (
-        	#"Vrouter1" => "router_top_v_p${ports}.v",
-        	"Vrouter1" => "--top-module  router_top_v  -GP=${ports}  ",  
-	      #  "Vnoc" => " --top-module noc_connection",
-	 		
-    	);
-    }elsif ($topology eq '"STAR"') { 
-     	 $router_p=1;# number of router with different port number
-     	 my $ports= $T1;
-     	 $nr_p{p1}=$ports;
-     	 $nr_p{1}=1;
-     	  %tops = (
-        	#"Vrouter1" => "router_top_v_p${ports}.v",
-        	"Vrouter1" => "--top-module  router_top_v  -GP=${ports}  ",  
-	      #  "Vnoc" => " --top-module noc_connection",
-	 		
-    	);
-        
-	}else {#custom
-		
-		my $dir =get_project_dir()."/mpsoc/rtl/src_topology";
-		my $file="$dir/param.obj";	
-		my %param;
-		if(-f $file){
-			my ($pp,$r,$err) = regen_object($file );
-	        if ($r){        
-	        	print "**Error: cannot open $file file: $err\n";
-	            return;
-	         } 
-	         
-		 	%param=%{$pp};		
-		}else {
-			print "**Error: cannot find $file \n";
-			return;
-		}
-		 
-	    my $topology_name=$self->object_get_attribute('noc_param','CUSTOM_TOPOLOGY_NAME'); 
-		my $ref=$param{$topology_name}{'ROUTER_Ps'};
-		print $ref;
-		my %router_ps= %{$ref};
-		my $i=1;
-		#%tops = ("Vnoc" => " --top-module noc_connection");
-		
-		#should sort neumeric. The router with smaller port number should comes first
-		
-		foreach my $p (sort { $a <=> $b } keys  %router_ps){
-			$nr_p{$i}=$router_ps{$p};
+            #"Vrouter1" => "router_top_v_p${ports}.v",
+            "Vrouter1" => "--top-module  router_top_v  -GP=${ports}  ",  
+            #  "Vnoc" => " --top-module noc_connection",
+        );
+    } elsif ($topology eq '"MESH_3D"') {
+        $router_p=1;
+        $nr_p{1}=$nr;
+        my $ports= 7+$T4-1;
+        $nr_p{p1}=$ports;
+        %tops = (
+            #"Vrouter1" => "router_top_v_p${ports}.v",
+            "Vrouter1" => "--top-module  router_top_v  -GP=${ports} ",  
+            #  "Vnoc" => " --top-module noc_connection",
+        );
+    }
+    elsif ($topology eq '"STAR"') { 
+        $router_p=1;# number of router with different port number
+        my $ports= $T1;
+        $nr_p{p1}=$ports;
+        $nr_p{1}=1;
+        %tops = (
+            #"Vrouter1" => "router_top_v_p${ports}.v",
+            "Vrouter1" => "--top-module  router_top_v  -GP=${ports}  ",  
+            #  "Vnoc" => " --top-module noc_connection",
+        );
+    }else {#custom
+        my $dir =get_project_dir()."/mpsoc/rtl/src_topology";
+        my $file="$dir/param.obj";
+        my %param;
+        if(-f $file){
+            my ($pp,$r,$err) = regen_object($file );
+            if ($r){
+                print "**Error: cannot open $file file: $err\n";
+                return;
+            } 
+            %param=%{$pp};
+        }else {
+            print "**Error: cannot find $file \n";
+            return;
+        }
+        my $topology_name=$self->object_get_attribute('noc_param','CUSTOM_TOPOLOGY_NAME'); 
+        my $ref=$param{$topology_name}{'ROUTER_Ps'};
+        #print $ref;
+        my %router_ps= %{$ref};
+        my $i=1;
+        #%tops = ("Vnoc" => " --top-module noc_connection");
+        #should sort neumeric. The router with smaller port number should comes first
+        foreach my $p (sort { $a <=> $b } keys  %router_ps){
+            $nr_p{$i}=$router_ps{$p};
             $nr_p{"p$i"}=$p;
             #$tops{"Vrouter$i"}= "router_top_v_p${p}.v", 
             $tops{"Vrouter$i"}= "--top-module  router_top_v  -GP=${p}  ", 
-			$i++;
-			
-		}	
-		$router_p=$i-1;	
-		${topology_name} =~ s/\"+//g;
-		$custom_include="#define IS_${topology_name}_noc\n";
-	}#else
-	
-		
-	
-	my $includ_h="\n";
-	for (my $p=1; $p<=$router_p ; $p++){
-		 $includ_h=$includ_h."#include \"Vrouter$p.h\" \n";
-	}
-	my $rns_num = $router_p+1;
-	$includ_h.="int router_NRs[$rns_num];\n";
-	
-	my $max_p=0;
-	for (my $p=1; $p<=$router_p ; $p++){
-		  my $pnum= $nr_p{"p$p"};
-		 $includ_h=$includ_h."#define NR${p} $nr_p{$p}\n";
-	 	 $includ_h=$includ_h."#define NR${p}_PNUM $pnum\n";
-		
-		 $includ_h=$includ_h."Vrouter${p}		*router${p}[ $nr_p{$p} ];   // Instantiation of router with $pnum  port number\n";
-		 $max_p = $pnum if($max_p < $pnum);
-	}
-	$includ_h.="#define MAX_P  $max_p //The maximum number of ports available in a router in this topology\n";
-	
-	$includ_h.="#define DAw $DAw //The traffic generator's destination address width\n";
-	
-	
-	my $st1='';
-	my $st2='';
-	my $st3='';
-	my $st4='';
-	my $st5='';
-	my $st6='';
-	my $st7='';
-	my $st8='';
-		
-	my $i=1;
-	my $j=0;
-	my $accum=0;
-	for (my $p=1; $p<=$router_p ; $p++){
-		$includ_h=$includ_h."
-		
-		
+            $i++;
+            
+        }
+        $router_p=$i-1;
+        ${topology_name} =~ s/\"+//g;
+        $custom_include="#define IS_${topology_name}_noc\n";
+    }#else
+    
+    my $includ_h="
+extern void update_router_st (
+    unsigned int,
+    unsigned int, 
+    void * ,
+    size_t
+);
 
+#ifndef FLAT_MODE \n";
+    for (my $p=1; $p<=$router_p ; $p++){
+        $includ_h=$includ_h."#include \"Vrouter$p.h\" \n";
+    }
+    my $rns_num = $router_p+1;
+    $includ_h.="int router_NRs[$rns_num];\n";
+    
+    my $max_p=0;
+    for (my $p=1; $p<=$router_p ; $p++){
+        my $pnum= $nr_p{"p$p"};
+        $includ_h=$includ_h."#define NR${p} $nr_p{$p}\n";
+        $includ_h=$includ_h."#define NR${p}_PNUM $pnum\n";
+        $includ_h=$includ_h."Vrouter${p}        *router${p}[ $nr_p{$p} ];   // Instantiation of router with $pnum  port number\n";
+        $max_p = $pnum if($max_p < $pnum);
+    }
+    $includ_h.="#define MAX_P  $max_p //The maximum number of ports available in a router in this topology\n";
+    $includ_h.="#define DAw $DAw //The traffic generator's destination address width\n";
+    
+    my $st1='';
+    my $st2='';
+    my $st3='';
+    my $st4='';
+    my $st5='';
+    my $st6='';
+    my $st7='';
+    my $st8='';
+    my $i=1;
+    my $j=0;
+    my $accum=0;
+    for (my $p=1; $p<=$router_p ; $p++){
+        $includ_h=$includ_h."
+        
+        
 ";
-#if		ROUTER_P_NUM >$j
+#if        ROUTER_P_NUM >$j
 
 #endif
 
 $st2=$st2."
     router_NRs[$p] =$nr_p{$p};
-	for(i=0;i<NR${i};i++)	router${i}[i] 	= new Vrouter${i};            
+    for(i=0;i<NR${i};i++)    router${i}[i]     = new Vrouter${i};
 ";
 
 $st3=$st3."
-	for(i=0;i<NR${i};i++){
-		router${i}[i]->reset= reset;
-		router${i}[i]->clk= clk ;
-	}
+    for(i=0;i<NR${i};i++){
+        router${i}[i]->reset= reset;
+        router${i}[i]->clk= clk ;
+    }
 ";
 
 $st4=$st4."
-	for(i=0;i<NR${i};i++) router${i}[i]->eval();
+    for(i=0;i<NR${i};i++) router${i}[i]->eval();
 ";
 
-
 $st5=$st5."
-	for(i=0;i<NR${i};i++) router${i}[i]->final();
+    for(i=0;i<NR${i};i++) router${i}[i]->final();
 ";
 
-
 $st6=$st6."
-	if (i<NR${i}){ router${i}[i]->eval(); return;}
-	i-=	NR${i};
+    if (i<NR${i}){ router${i}[i]->eval(); return;}
+    i-=    NR${i};
 ";
 
-
-
-
-
 $st7.="
-	if (i<NR${i}){ 
-		update_router_st(
-			NR${i}_PNUM,
-			router${i}[i]->current_r_id,   
-			router${i}[i]->router_event,
-			sizeof(router${i}[i]->router_event[0])
-		); 
-		return;
-	}
-	i-=	NR${i};
+    if (i<NR${i}){ 
+        update_router_st(
+            NR${i}_PNUM,
+            router${i}[i]->current_r_id,   
+            router${i}[i]->router_event,
+            sizeof(router${i}[i]->router_event[0])
+        ); 
+        return;
+    }
+    i-=    NR${i};
 ";
 
 $st8=$st8."
-	if (i<NR${i}){ 
-		router${i}[i]->reset= reset;
-		router${i}[i]->clk= clk ;
-		return;
-	}
-	i-=	NR${i};
+    if (i<NR${i}){ 
+        router${i}[i]->reset= reset;
+        router${i}[i]->clk= clk ;
+        return;
+    }
+    i-=    NR${i};
 ";
 
+    $i++;
+    $j++;
+    $accum=$accum+$nr_p{$p};
+    
+    }
 
-
-	$i++;
-	$j++;
-	$accum=$accum+$nr_p{$p};
-	
-}
-	
-	
 $includ_h=$includ_h."
 
-
 void Vrouter_new(){
-	int i=0;
-	$st2	
+    int i=0;
+    $st2
 }
 
 $custom_include
 
 void inline connect_routers_reset_clk(){
-	int i;
-	$st3
+    int i;
+    $st3
 }
 
-
 void inline routers_eval(){
-	int i=0;
-	$st4
+    int i=0;
+    $st4
 }
 
 void inline routers_final(){
-	int i;
-	$st5
-}	
+    int i;
+    $st5
+}    
 
 void inline single_router_eval(int i){
-	$st6
+    $st6
 }
 
 #define SMART_NUM  ((SMART_MAX==0)? 1 : SMART_MAX)
 
 
-extern void update_router_st (
-  unsigned int,
-  unsigned int, 
-  void * ,
-  size_t
-);
- 
 void  single_router_st_update(int i){
-	$st7
+    $st7
 }
 
 void  inline single_router_reset_clk(int i){
-	$st8
-}
-
-	
-";	
+    $st8
+}
+#else
+    #define MAX_P  $max_p // The maximum number of ports available in a router in this topology
+    #define DAw $DAw // The traffic generator's destination address width
+    #define SMART_NUM  ((SMART_MAX==0)? 1 : SMART_MAX) 
+    extern Vnoc     *noc_top;
+
+    void  single_router_st_update(int i){
+        update_router_st(
+            MAX_P ,
+            i,   
+            noc_top->router_event[i],
+            sizeof(noc_top->router_event[0][0])
+        ); 
+        return;
+    }
+
+#endif //FLAT_MODE
+";
 
 #$includ_h.=" void connect_all_nodes(){\n";
 
@@ -743,139 +720,124 @@ sub get_noc_verilator_top_modules_info {
 #my @lines =split ("\n",$dot_file);
 #foreach my $l (@lines) {
 #    if ( $l =~  m{#*\"\s*R(\d+)\"\s*:\s*\"[pP](\d+)\"\s*->\s*\"R(\d+)\"\s*:\s*\"[pP](\d+)\"} ) {
-#		my ($R1, $P1, $R2,$P2) = ($1, $2,$3,$4);
-#		$includ_h.=connect_sim_nodes ($self,$topology,$R1, $P1, $R2, $P2);
-#		
+#        my ($R1, $P1, $R2,$P2) = ($1, $2,$3,$4);
+#        $includ_h.=connect_sim_nodes ($self,$topology,$R1, $P1, $R2, $P2);
+#        
 #   
-#	}
-#	if ( $l =~  m{#*\"\s*R(\d+)\"\s*:\s*\"[pP](\d+)\"\s*->\s*\"[Tt](\d+)\"} ) {
-#		my ($R1, $P1, $T) = ($1, $2,$3);
-#		$includ_h.=connect_sim_nodes($self,$topology,$R1, $P1, $T);
-#		
+#    }
+#    if ( $l =~  m{#*\"\s*R(\d+)\"\s*:\s*\"[pP](\d+)\"\s*->\s*\"[Tt](\d+)\"} ) {
+#        my ($R1, $P1, $T) = ($1, $2,$3);
+#        $includ_h.=connect_sim_nodes($self,$topology,$R1, $P1, $T);
+#        
 #   
-#	}
-#	if ( $l =~  m{#*\s*\"[Tt](\d+)\"\s*->\s*\"R(\d+)\"\s*:\s*\"[pP](\d+)\"} ) {
-#   		my ($T, $R1, $P1) = ($1, $2,$3);
-#		$includ_h.=connect_sim_nodes($self,$topology,$R1, $P1, $T);
-#	}
+#    }
+#    if ( $l =~  m{#*\s*\"[Tt](\d+)\"\s*->\s*\"R(\d+)\"\s*:\s*\"[pP](\d+)\"} ) {
+#           my ($T, $R1, $P1) = ($1, $2,$3);
+#        $includ_h.=connect_sim_nodes($self,$topology,$R1, $P1, $T);
+#    }
 #} 
 #$includ_h.="\n}\n";
-
-	 return ($nr,$ne,$router_p,\%tops,$includ_h);	
+    return ($nr,$ne,$router_p,\%tops,$includ_h);
 }
 
 sub connect_sim_nodes{
-	my ($self,$topology,$R1, $P1, $R2, $P2)=@_;
-	if(defined $P2){ #R2R
-		if($topology eq '"FATTREE"' || $topology eq '"TREE"'){
-			
-		}else{
-			return connect_r2r(1,$R1, $P1,1, $R2, $P2);
-			
-		}
-	}else {
-		my $T=$R2;
-		if($topology eq '"FATTREE"' || $topology eq '"TREE"'){
-			
-		}else{
-			return connect_r2t(1,$R1, $P1, $T);
-			
-		}
-		
-	}
-	
-	
+    my ($self,$topology,$R1, $P1, $R2, $P2)=@_;
+    if(defined $P2){ #R2R
+        if($topology eq '"FATTREE"' || $topology eq '"TREE"'){
+            
+        }else{
+            return connect_r2r(1,$R1, $P1,1, $R2, $P2);
+        }
+    }else {
+        my $T=$R2;
+        if($topology eq '"FATTREE"' || $topology eq '"TREE"'){
+            
+        }else{
+            return connect_r2t(1,$R1, $P1, $T);
+        }
+    }
 }
 
 sub connect_r2r{
-	my ($vrouter1_num,$r1,$p1,$vrouter2_num,$r2,$p2)=@_;
-return "	
-	memcpy(&router${vrouter1_num}[$r1]->chan_in[$p1], router${vrouter2_num}[$r2]->chan_out[$p2] , sizeof( router${vrouter1_num}[$r1]->chan_in[$p1] ) );
-	memcpy(&router${vrouter2_num}[$r2]->chan_in[$p2], router${vrouter1_num}[$r1]->chan_out[$p1] , sizeof( router${vrouter1_num}[$r1]->chan_in[$p1] ) );
-	";
+    my ($vrouter1_num,$r1,$p1,$vrouter2_num,$r2,$p2)=@_;
+    return "    
+    memcpy(&router${vrouter1_num}[$r1]->chan_in[$p1], router${vrouter2_num}[$r2]->chan_out[$p2] , sizeof( router${vrouter1_num}[$r1]->chan_in[$p1] ) );
+    memcpy(&router${vrouter2_num}[$r2]->chan_in[$p2], router${vrouter1_num}[$r1]->chan_out[$p1] , sizeof( router${vrouter1_num}[$r1]->chan_in[$p1] ) );
+    ";
 }
 
 sub connect_r2t{
 my ($vrouter1_num,$r1, $p1, $T)=@_;
-return "
-	memcpy(&router${vrouter1_num}[$r1]->chan_in[$p1], traffic[$T]->chan_out , sizeof( traffic[$T]->chan_in ) );
-	memcpy(&traffic[$T]->chan_in, router${vrouter1_num}[$r1]->chan_out[$p1] , sizeof( traffic[$T]->chan_in ) );	
-	";
+    return "
+    memcpy(&router${vrouter1_num}[$r1]->chan_in[$p1], traffic[$T]->chan_out , sizeof( traffic[$T]->chan_in ) );
+    memcpy(&traffic[$T]->chan_in, router${vrouter1_num}[$r1]->chan_out[$p1] , sizeof( traffic[$T]->chan_in ) );    
+    ";
 }
 
-
 sub gen_tiles_physical_addrsses_header_file{
-	my ($self,$file)=@_;
-	my $topology=$self->object_get_attribute('noc_param','TOPOLOGY');
-	my $txt = "#ifndef PHY_ADDR_H
-	#define PHY_ADDR_H\n\n";
-	
-	#add phy addresses
-	my ($NE, $NR, $RAw, $EAw,$Fw)=get_topology_info($self);
-	for (my $id=0; $id<$NE; $id++){
-		my $phy= endp_addr_encoder($self,$id);	
-		my $hex = sprintf("0x%x", $phy);
-		$txt=$txt."\t#define PHY_ADDR_ENDP_$id  $hex\n";	
-		
-	}	
-		
-	
-	$txt=$txt."#endif\n";
-	save_file($file,$txt);		
+    my ($self,$file)=@_;
+    my $topology=$self->object_get_attribute('noc_param','TOPOLOGY');
+    my $txt = "#ifndef PHY_ADDR_H
+    #define PHY_ADDR_H\n\n";
+    
+    #add phy addresses
+    my ($NE, $NR, $RAw, $EAw,$Fw)=get_topology_info($self);
+    for (my $id=0; $id<$NE; $id++){
+        my $phy= endp_addr_encoder($self,$id);    
+        my $hex = sprintf("0x%x", $phy);
+        $txt=$txt."\t#define PHY_ADDR_ENDP_$id  $hex\n";    
+    }    
+    $txt=$txt."#endif\n";
+    save_file($file,$txt);
 }
 
-
 sub get_endpoints_mah_distance {
-	my ($self,$endp1,$endp2)=@_;
-	
-	my $router1=get_connected_router_id_to_endp($self,$endp1);
-	my $router2=get_connected_router_id_to_endp($self,$endp2);
-	
-	my $topology=$self->object_get_attribute('noc_param','TOPOLOGY');
-	if($topology eq '"FATTREE"' || $topology eq '"TREE"') {
-		return fattree_mah_distance($self, $router1,$router2);
-	}elsif ($topology eq '"RING"' || $topology eq '"LINE"'  ||  $topology eq '"MESH"' || $topology eq '"TORUS"' || $topology eq '"FMESH"' ){
-		return mesh_tori_mah_distance($self, $router1,$router2);
-	}elsif ($topology eq '"STAR"'){
-		return 1;
-	}else { #custom
-		return undef;		
-	}	
-	
+    my ($self,$endp1,$endp2)=@_;
+    my $router1=get_connected_router_id_to_endp($self,$endp1);
+    my $router2=get_connected_router_id_to_endp($self,$endp2);
+    my $topology=$self->object_get_attribute('noc_param','TOPOLOGY');
+    if($topology eq '"FATTREE"' || $topology eq '"TREE"') {
+        return fattree_mah_distance($self, $router1,$router2);
+    }elsif ($topology eq '"RING"' || $topology eq '"LINE"'  ||  $topology eq '"MESH"' || $topology eq '"TORUS"' || $topology eq '"FMESH"' ){
+        return mesh_tori_mah_distance($self, $router1,$router2);
+    }elsif ($topology eq '"STAR"'){
+        return 1;
+    }else { #custom
+        return undef;
+    }    
 }
 
 sub mesh_tori_mah_distance {
-	my ($self, $router1,$router2)=@_;
-	my $T1=$self->object_get_attribute('noc_param','T1');
-	my $T2=$self->object_get_attribute('noc_param','T2');
-	my ($x1,$y1,$l1) = mesh_tori_addrencod_sep ($router1,$T1,$T2,1);
-	my ($x2,$y2,$l2) = mesh_tori_addrencod_sep ($router2,$T1,$T2,1);
-	my $x_diff = ($x1 > $x2) ? ($x1 - $x2) : ($x2 - $x1);
-	my $y_diff = ($y1 > $y2) ? ($y1 - $y2) : ($y2 - $y1);
-	my $mah_distance = $x_diff + $y_diff;
-	return $mah_distance;	
+    my ($self, $router1,$router2)=@_;
+    my $T1=$self->object_get_attribute('noc_param','T1');
+    my $T2=$self->object_get_attribute('noc_param','T2');
+    my ($x1,$y1,$l1) = mesh_tori_addrencod_sep ($router1,$T1,$T2,1);
+    my ($x2,$y2,$l2) = mesh_tori_addrencod_sep ($router2,$T1,$T2,1);
+    my $x_diff = ($x1 > $x2) ? ($x1 - $x2) : ($x2 - $x1);
+    my $y_diff = ($y1 > $y2) ? ($y1 - $y2) : ($y2 - $y1);
+    my $mah_distance = $x_diff + $y_diff;
+    return $mah_distance;    
 }
 
 sub fattree_mah_distance {
-	my ($self, $router1,$router2)=@_;
-	my $k =$self->object_get_attribute('noc_param','T1');
-	my $l =$self->object_get_attribute('noc_param','T2');
-	
-	my  $pow; 
-	my $tmp1;
-	my $tmp2;	
-	my $distance=0;
-	$pow=1;
-	for (my $i = 0; $i <$l; $i=$i+1 ) {
-		$tmp1=int($router1/$pow);
-		$tmp2=int($router2/$pow);		
-		$tmp1=$tmp1 % $k;
-		$tmp2=$tmp2 % $k;		
-		$pow=$pow * $k;		
-		$distance= ($i+1)*2-1 if($tmp1!=$tmp2); # distance obtained based on the highest level index which differ 
-		
-	}
-	 return $distance;	
-}	
-
+    my ($self, $router1,$router2)=@_;
+    my $k =$self->object_get_attribute('noc_param','T1');
+    my $l =$self->object_get_attribute('noc_param','T2');
+    
+    my  $pow; 
+    my $tmp1;
+    my $tmp2;    
+    my $distance=0;
+    $pow=1;
+    for (my $i = 0; $i <$l; $i=$i+1 ) {
+        $tmp1=int($router1/$pow);
+        $tmp2=int($router2/$pow);
+        $tmp1=$tmp1 % $k;
+        $tmp2=$tmp2 % $k;
+        $pow=$pow * $k;
+        $distance= ($i+1)*2-1 if($tmp1!=$tmp2); # distance obtained based on the highest level index which differ 
+        
+    }
+    return $distance;
+}    
 1
diff --git a/mpsoc/perl_gui/lib/perl/topology_verilog_gen.pl b/mpsoc/perl_gui/lib/perl/topology_verilog_gen.pl
index a47c226..af2f081 100755
--- a/mpsoc/perl_gui/lib/perl/topology_verilog_gen.pl
+++ b/mpsoc/perl_gui/lib/perl/topology_verilog_gen.pl
@@ -5,1731 +5,1371 @@
 use lib $FindBin::Bin;
 
 
-
-
 sub generate_topology_top_v {
-	my ($self,$info,$dir)=@_;
-	
-		
-	#create topology top file
-	my $name=$self->object_get_attribute('save_as');
-	
-	my $r; 
-	my $top="$dir/${name}_noc.sv";
+    my ($self,$info,$dir)=@_;
+    #create topology top file
+    my $name=$self->object_get_attribute('save_as');
+    my $r; 
+    my $top="$dir/${name}_noc.sv";
     open my $fd, ">$top" or $r = "$!\n";
     if(defined $r) {
-    	add_colored_info($info,"Error in creating $top: $r",'red');
-		return;
+        add_colored_info($info,"Error in creating $top: $r",'red');
+        return;
     } 
     print $fd autogen_warning();
     print $fd get_license_header($top);   
-	print $fd '
+    print $fd '
 `include "pronoc_def.v"
 ';
-   
-    my $param_str ="\tparameter TOPOLOGY = \"$name\",
-\tparameter ROUTE_NAME = \"${name}_DETERMINISTIC\"";
-
-   my @parameters=@{$self->object_get_attribute ('Verilog','Router_param')};
-   my @ports= @{$self->object_get_attribute('Verilog','Router_ports')}; 
-    
-#	foreach my $d (@parameters){
-#		$param_str = $param_str.",\n\tparameter $d->{param_name} = $d->{value}";
-#	}
- 
+    my $param_str ="    parameter TOPOLOGY = \"$name\",
+    parameter ROUTE_NAME = \"${name}_DETERMINISTIC\"";
+    my @parameters=@{$self->object_get_attribute ('Verilog','Router_param')};
+    my @ports= @{$self->object_get_attribute('Verilog','Router_ports')}; 
+#    foreach my $d (@parameters){
+#        $param_str = $param_str.",\n    parameter $d->{param_name} = $d->{value}";
+#    }
     my @ends=get_list_of_all_endpoints($self);
     my @routers=get_list_of_all_routers($self);
-    
     my $MAX_P=0;
     foreach my $p (@routers){
-    	my $Pnum=$self->object_get_attribute("$p",'PNUM');
-    	$MAX_P =$Pnum  if($Pnum>$MAX_P );    	
-    }	
-
+        my $Pnum=$self->object_get_attribute("$p",'PNUM');
+        $MAX_P =$Pnum  if($Pnum>$MAX_P );        
+    }    
     my $NE= scalar @ends;
     my $NR= scalar @routers;
-
-   
-
-	
-	
-	#step 2 	add routers
-	my @nodes=get_list_of_all_routers($self);
-	my $i=0;
-	
-	my $ports="\treset,
-\tclk";
-	my $wires='',
-	my $routers='';
-	
-	foreach my $p (@ends){
-		my $instance= $self->object_get_attribute("$p","NAME");	
-		$ports=$ports.",\n\t//$instance";
-		$wires=$wires."
-	/*******************
-	*		$instance
-	*******************/
+    #step 2     add routers
+    my @nodes=get_list_of_all_routers($self);
+    my $i=0;
+    my $ports="    reset,
+    clk";
+    my $wires='',
+    my $routers='';
+    foreach my $p (@ends){
+        my $instance= $self->object_get_attribute("$p","NAME");    
+        $ports=$ports.",\n    //$instance";
+        $wires=$wires."
+    /*******************
+    *        $instance
+    *******************/
 ";
-		
-		$wires=$wires."\tinput  smartflit_chanel_t ${instance}_chan_in;\n";
-		$wires=$wires."\toutput smartflit_chanel_t ${instance}_chan_out;\n";
-		$wires=$wires."\toutput router_event_t ${instance}_router_event;\n";		
-		$ports=$ports.",\n\t${instance}_chan_in,\n\t${instance}_chan_out,\n\t${instance}_router_event";
-		
-		foreach my $d (@ports){		
-				my $range = ($d->{pwidth} eq 1)? " " :  " [$d->{pwidth}-1 : 0]";
-				my $type=$d->{type};
-				my $ctype= ($type eq 'input')? 'output' : 'input';	
-				if( $d->{endp} eq "yes"){ 	    	 
-					#$wires=$wires."\t$type $range ${instance}_$d->{pname};\n";
-					#$wires=$wires."\t$ctype $range ${instance}_$d->{pconnect};\n";
-					#$ports=$ports.",\n\t${instance}_$d->{pname},\n\t${instance}_$d->{pconnect}";
-				}
-		}	
-	}
-	
-	
-	foreach my $p (@nodes){
-		
-		my ($wire,$router) = get_router_instance_v($self,$p,$i,$NE,$NR,$MAX_P);
-		$wires=$wires.$wire,
-		$routers=$routers.$router;
-		 
-		
-		$i++;
-	}
-	
-	my $assign="";
-	foreach my $p (@ends){
-		my $instance= $self->object_get_attribute("$p","NAME");	
-		my $pname= "Port[0]";
-		my $connect = $self->{$p}{'PCONNECT'}{$pname};
-		if(defined $connect){
-			my ($cname,$pnode)=split(/\s*,\s*/,$connect);
-			my $cinstance= $self->object_get_attribute("$cname","NAME");
-			my ($cp)= sscanf("Port[%u]","$pnode");
-			#$assign = $assign."//Connect $instance output ports 0 to  $cinstance input ports $cp\n";
-			my $cpplus=$cp+1;
-			
-		
-			foreach my $p (@ports){	
-				my $w=$p->{pwidth};
-				my $range = ($w eq 1)? 	" " : "[$w-1 : 		 0 ]";
-				my $crange = ($w eq 1)? "[$cp]"	: "[($cpplus*$w)-1 :	 $cp*$w ]";
-				my $cport =  "${cinstance}_$p->{connect}";
-				my $port ="${instance}_$p->{pconnect}";
-				if($p->{type} eq 'input' ){						
-					# $assign=  $assign."\t\tassign  $port $range = $cport $crange;\n" if($p->{endp} eq "yes");		
-				}else{
-					# $assign=  $assign."\t\tassign  $cport $crange= $port $range;\n" if($p->{endp} eq "yes");		
-				}	
-				
-			 }	#@port
-		}
+        $wires=$wires."    input  smartflit_chanel_t ${instance}_chan_in;\n";
+        $wires=$wires."    output smartflit_chanel_t ${instance}_chan_out;\n";
+        $wires=$wires."    output router_event_t ${instance}_router_event;\n";        
+        $ports=$ports.",\n    ${instance}_chan_in,\n    ${instance}_chan_out,\n    ${instance}_router_event";
+        foreach my $d (@ports){        
+                my $range = ($d->{pwidth} eq 1)? " " :  " [$d->{pwidth}-1 : 0]";
+                my $type=$d->{type};
+                my $ctype= ($type eq 'input')? 'output' : 'input';    
+                if( $d->{endp} eq "yes"){              
+                    #$wires=$wires."    $type $range ${instance}_$d->{pname};\n";
+                    #$wires=$wires."    $ctype $range ${instance}_$d->{pconnect};\n";
+                    #$ports=$ports.",\n    ${instance}_$d->{pname},\n    ${instance}_$d->{pconnect}";
+                }
+        }    
+    }
+    foreach my $p (@nodes){
+        my ($wire,$router) = get_router_instance_v($self,$p,$i,$NE,$NR,$MAX_P);
+        $wires=$wires.$wire,
+        $routers=$routers.$router;
+        $i++;
+    }
+    my $assign="";
+    foreach my $p (@ends){
+        my $instance= $self->object_get_attribute("$p","NAME");    
+        my $pname= "Port[0]";
+        my $connect = $self->{$p}{'PCONNECT'}{$pname};
+        if(defined $connect){
+            my ($cname,$pnode)=split(/\s*,\s*/,$connect);
+            my $cinstance= $self->object_get_attribute("$cname","NAME");
+            my ($cp)= sscanf("Port[%u]","$pnode");
+            #$assign = $assign."    //Connect $instance output ports 0 to  $cinstance input ports $cp\n";
+            my $cpplus=$cp+1;
+            foreach my $p (@ports){    
+                my $w=$p->{pwidth};
+                my $range = ($w eq 1)?     " " : "[$w-1 :          0 ]";
+                my $crange = ($w eq 1)? "[$cp]"    : "[($cpplus*$w)-1 :     $cp*$w ]";
+                my $cport =  "${cinstance}_$p->{connect}";
+                my $port ="${instance}_$p->{pconnect}";
+                if($p->{type} eq 'input' ){                        
+                    # $assign=  $assign."        assign  $port $range = $cport $crange;\n" if($p->{endp} eq "yes");        
+                }else{
+                    # $assign=  $assign."        assign  $cport $crange= $port $range;\n" if($p->{endp} eq "yes");        
+                }    
+            }    #@port
+        }
+    }
 
-	}
-	
-	
-	
-	
-	 print $fd "
+    print $fd "
 module   ${name}_noc
-#(
-	parameter NOC_ID=0
-)
 (
-	$ports
+    $ports
 );
-	
-	`NOC_CONF
-	 
-    input reset,clk;    
-       
+    import pronoc_pkg::*;
+    
+    input reset,clk;
+    
     $wires
     
     $routers
     
     $assign
-             
+    
 endmodule
 ";
-	add_info($info,"$top file is created\n  ");
-	close $fd;
-	
-	
+    add_info($info,"$top file is created\n  ");
+    close $fd;
 }
 
 
-
-
 sub get_router_instance_v {
-	my ($self,$rname,$current_r,$NE,$NR,$MAX_P)=@_;
-	
-	
-	my $instance= $self->object_get_attribute("$rname","NAME");		
-	my $Pnum=$self->object_get_attribute("$rname",'PNUM');
-	
-	#read ruter parameters and ports
-	 my @parameters=@{$self->object_get_attribute ('Verilog','Router_param')};
-     my @ports= @{$self->object_get_attribute('Verilog','Router_ports')}; 
-	
-	my $wires_v="
-	/*******************
-	*		$instance
-	*******************/
-\twire ${instance}_clk;
-\twire ${instance}_reset;
-
-\twire [RAw-1 :  0] ${instance}_current_r_addr;
-
-\tsmartflit_chanel_t    ${instance}_chan_in   [$Pnum-1 : 0];
-\tsmartflit_chanel_t    ${instance}_chan_out  [$Pnum-1 : 0]; 
-\trouter_event_t ${instance}_router_event [$Pnum-1 : 0]; 
-
+    my ($self,$rname,$current_r,$NE,$NR,$MAX_P)=@_;
+    my $instance= $self->object_get_attribute("$rname","NAME");        
+    my $Pnum=$self->object_get_attribute("$rname",'PNUM');
+    #read ruter parameters and ports
+    my @parameters=@{$self->object_get_attribute ('Verilog','Router_param')};
+    my @ports= @{$self->object_get_attribute('Verilog','Router_ports')}; 
+    my $wires_v="
+    /*******************
+    *        $instance
+    *******************/
+    wire ${instance}_clk;
+    wire ${instance}_reset;
+    smartflit_chanel_t    ${instance}_chan_in   [$Pnum-1 : 0];
+    smartflit_chanel_t    ${instance}_chan_out  [$Pnum-1 : 0]; 
+    router_event_t ${instance}_router_event [$Pnum-1 : 0]; 
 ";
-
-	
-
-	
-	my $router_v="	
-	/*******************
-	*		$instance
-	*******************/
-	router_top #(
-		.NOC_ID(NOC_ID),
-		.P($Pnum)		
-	)
-	$instance
-	(	
-		.clk(${instance}_clk), 
-		.reset(${instance}_reset),
-		.current_r_id($current_r),
-		.current_r_addr  (${instance}_current_r_addr), 
-		.chan_in   (${instance}_chan_in), 
-		.chan_out  (${instance}_chan_out),
-		.router_event (${instance}_router_event)
-	);
+    my $router_v="    
+    /*******************
+    *        $instance
+    *******************/
+    router_config_t ${instance}_router_config_in;
+    router_top #(
+        .ROUTER_ID($current_r),
+        .P($Pnum)
+    ) $instance (
+        .clk(${instance}_clk), 
+        .reset(${instance}_reset),
+        .router_config_in(${instance}_router_config_in),
+        .chan_in   (${instance}_chan_in), 
+        .chan_out  (${instance}_chan_out),
+        .router_event (${instance}_router_event)
+    );
 ";
-
-	
-$router_v= $router_v."
-\t\tassign ${instance}_clk = clk;
-\t\tassign ${instance}_reset = reset;
-\t\tassign ${instance}_current_r_addr = $current_r;
+    $router_v= $router_v."
+        assign ${instance}_clk = clk;
+        assign ${instance}_reset = reset;
+        assign ${instance}_router_config_in.router_addr = $current_r;
+        assign ${instance}_router_config_in.router_id = $current_r;
 "; 
 
-
-		
-
 for (my $i=0;$i<$Pnum; $i++){ 
-	my $pname= "Port[${i}]";
-	my $connect = $self->{$rname}{'PCONNECT'}{$pname};
-	my $iplus=$i+1;
-	if(defined $connect){
-		my ($cname,$pnode)=split(/\s*,\s*/,$connect);
-		my $cinstance= $self->object_get_attribute("$cname","NAME");
-		my $ctype = $self->object_get_attribute("$cname",'TYPE'); 		
-		my ($cp)= sscanf("Port[%u]","$pnode");
-		$router_v = $router_v."//Connect $instance port $i to  $cinstance port $cp\n";
-		if($ctype ne 'ENDP'){
-			$router_v.=" \t\tassign ${instance}_chan_in [$i]   = ${cinstance}_chan_out [$cp];\n";			
-		}else{
-			$router_v.=" \t\tassign ${instance}_chan_in [$i]  = ${cinstance}_chan_in;\n";
-			$router_v.=" \t\tassign ${cinstance}_chan_out = ${instance}_chan_out [$i];\n";
-			$router_v.=" \t\tassign ${cinstance}_router_event = ${instance}_router_event [$i];\n";
-			
-		}
-		my $cpplus=$cp+1;
-		    	
-		#{name=> "flit_in_all", type=>"input", width=>"PFw", connect=>"flit_out_all",  pwidth=>"Fw" },
-		
-		
-		
-		foreach my $p (@ports){	
-			my $w=$p->{pwidth};
-			my $range = ($w eq 1)? 	"[$i]" : "[($iplus*$w)-1 : 		 $i*$w ]";
-			my $crange = ($ctype eq 'ENDP') ? '' :
-			($w eq 1)? "[$cp]"	: "[($cpplus*$w)-1 :	 $cp*$w ]";
-			my $cport = ($ctype eq 'ENDP') ? "${cinstance}_$p->{pname}" : "${cinstance}_$p->{connect}";
-			my $port ="${instance}_$p->{name}";
-			if($ctype eq 'ENDP' && $p->{endp} eq "no" && $p->{type} eq 'input' ){						
-				# $router_v=  $router_v."\t\tassign  $port $range = 0;\n";		
-						
-			}else{
-				if($p->{type} eq 'input' ){						
-				# $router_v=  $router_v."\t\tassign  $port $range = $cport $crange;\n";		
-				}else{
-				# $router_v=  $router_v."\t\tassign  $cport $crange= $port $range;\n";	
-				}	
-			}
-		 }	#@port
-			
-	}else {
-			$router_v = $router_v."//Connect $instance port $i to  ground
-\t	assign  ${instance}_chan_in [$i]= {SMARTFLIT_CHANEL_w{1'b0}};\n";
-			
-			foreach my $p (@ports){	
-				my $w=$p->{pwidth};
-				my $range = ($w eq 1)? 	"[$i]" : "[($iplus*$w)-1 : 		 $i*$w ]";
-				if($p->{type} eq 'input' ){		
-			 	#	$router_v=  $router_v."\t\tassign  ${instance}_$p->{name} $range = \{$w\{1'b0\}\};\n";		
-				}
-			}	
-	}		
-			
-}	
-	
-	
-	return ($wires_v,$router_v);		
+    my $pname= "Port[${i}]";
+    my $connect = $self->{$rname}{'PCONNECT'}{$pname};
+    my $iplus=$i+1;
+    if(defined $connect){
+        my ($cname,$pnode)=split(/\s*,\s*/,$connect);
+        my $cinstance= $self->object_get_attribute("$cname","NAME");
+        my $ctype = $self->object_get_attribute("$cname",'TYPE');         
+        my ($cp)= sscanf("Port[%u]","$pnode");
+        $router_v = $router_v."    //Connect $instance port $i to  $cinstance port $cp\n";
+        if($ctype ne 'ENDP'){
+            $router_v.="    assign ${instance}_chan_in [$i]   = ${cinstance}_chan_out [$cp];\n";            
+        }else{
+            $router_v.="    assign ${instance}_chan_in [$i]  = ${cinstance}_chan_in;\n";
+            $router_v.="    assign ${cinstance}_chan_out = ${instance}_chan_out [$i];\n";
+            $router_v.="    assign ${cinstance}_router_event = ${instance}_router_event [$i];\n";
+            
+        }
+        my $cpplus=$cp+1;
+        #{name=> "flit_in_all", type=>"input", width=>"PFw", connect=>"flit_out_all",  pwidth=>"Fw" },
+        foreach my $p (@ports){    
+            my $w=$p->{pwidth};
+            my $range = ($w eq 1)?     "[$i]" : "[($iplus*$w)-1 :          $i*$w ]";
+            my $crange = ($ctype eq 'ENDP') ? '' :
+            ($w eq 1)? "[$cp]"    : "[($cpplus*$w)-1 :     $cp*$w ]";
+            my $cport = ($ctype eq 'ENDP') ? "${cinstance}_$p->{pname}" : "${cinstance}_$p->{connect}";
+            my $port ="${instance}_$p->{name}";
+            if($ctype eq 'ENDP' && $p->{endp} eq "no" && $p->{type} eq 'input' ){                        
+                # $router_v=  $router_v."        assign  $port $range = 0;\n";        
+            }else{
+                if($p->{type} eq 'input' ){                        
+                # $router_v=  $router_v."        assign  $port $range = $cport $crange;\n";        
+                }else{
+                # $router_v=  $router_v."        assign  $cport $crange= $port $range;\n";    
+                }    
+            }
+        }    #@port
+    }else {
+            $router_v = $router_v."    //Connect $instance port $i to  ground
+    assign  ${instance}_chan_in [$i]= {SMARTFLIT_CHANEL_w{1'b0}};\n";
+            foreach my $p (@ports){    
+                my $w=$p->{pwidth};
+                my $range = ($w eq 1)?     "[$i]" : "[($iplus*$w)-1 :          $i*$w ]";
+                if($p->{type} eq 'input' ){        
+                #    $router_v=  $router_v."        assign  ${instance}_$p->{name} $range = \{$w\{1'b0\}\};\n";        
+                }
+            }
+        }
+    }
+    return ($wires_v,$router_v);
 }
 
-
-
 #*******************
-#	generate_topology_top_genvar_v
+#    generate_topology_top_genvar_v
 #********************
-
-
 sub generate_topology_top_genvar_v{
-	my ($self,$info,$dir)=@_;
-	
-		
-	#create topology top file
-	my $name=$self->object_get_attribute('save_as');
-	my $r; 
-	my $top="$dir/${name}_noc_genvar.sv";
+    my ($self,$info,$dir)=@_;
+    #create topology top file
+    my $name=$self->object_get_attribute('save_as');
+    my $r; 
+    my $top="$dir/${name}_noc_genvar.sv";
     open my $fd, ">$top" or $r = "$!\n";
     if(defined $r) {
-    	add_colored_info($info,"Error in creating $top: $r",'red');
-		return;
+        add_colored_info($info,"Error in creating $top: $r",'red');
+        return;
     } 
     print $fd autogen_warning();
     print $fd get_license_header($top);   
-	print $fd '
+    print $fd '
 `include "pronoc_def.v"
 ';
-   
-    my $param_str ="\tparameter TOPOLOGY = \"$name\",
-\tparameter ROUTE_NAME = \"${name}_DETERMINISTIC\"";
+    my $param_str ="    parameter TOPOLOGY = \"$name\",
+    parameter ROUTE_NAME = \"${name}_DETERMINISTIC\"";
 
-   my @parameters=@{$self->object_get_attribute ('Verilog','Router_param')};
-   my @ports= @{$self->object_get_attribute('Verilog','Router_ports')}; 
-    
-	foreach my $d (@parameters){
-		$param_str = $param_str.",\n\tparameter $d->{param_name} = $d->{value}";
-	}
- 
+    my @parameters=@{$self->object_get_attribute ('Verilog','Router_param')};
+    my @ports= @{$self->object_get_attribute('Verilog','Router_ports')}; 
+    foreach my $d (@parameters){
+        $param_str = $param_str.",\n    parameter $d->{param_name} = $d->{value}";
+    }
     my @ends=get_list_of_all_endpoints($self);
     my @routers=get_list_of_all_routers($self);
-    
     my $MAX_P=0;
     foreach my $p (@routers){
-    	my $Pnum=$self->object_get_attribute("$p",'PNUM');
-    	$MAX_P =$Pnum  if($Pnum>$MAX_P );    	
-    }	
-
+        my $Pnum=$self->object_get_attribute("$p",'PNUM');
+        $MAX_P =$Pnum  if($Pnum>$MAX_P );        
+    }    
     my $NE= scalar @ends;
     my $NR= scalar @routers;
-
-   	
-	
-	my @nodes=get_list_of_all_routers($self);
-	my $i=0;
-	
-	my $ports="\treset,
-\tclk,
-\tchan_in_all,
-\tchan_out_all,
-\trouter_event  
+    my @nodes=get_list_of_all_routers($self);
+    my $i=0;
+    my $ports="    reset,
+    clk,
+    chan_in_all,
+    chan_out_all,
+    router_event  
 ";
     my $ports_def="
-\tinput  reset;
-\tinput  clk;
-\tinput  smartflit_chanel_t chan_in_all  [NE-1 : 0];
-\toutput smartflit_chanel_t chan_out_all [NE-1 : 0];
-
-//Events
-\toutput  router_event_t  router_event [NR-1 : 0][MAX_P-1 : 0];
-
-//all routers port 
-\tsmartflit_chanel_t    router_chan_in   [NR-1 :0][MAX_P-1 : 0];
-\tsmartflit_chanel_t    router_chan_out  [NR-1 :0][MAX_P-1 : 0];
-
-
-\twire [RAw-1 : 0] current_r_addr [NR-1 : 0];
-
-
-";
-
-	my $router_wires="";
-	my $endps_wires="";
-
-	
-	
-	
-	foreach my $d (@ports){		
-		my $range = ($d->{width} eq 1)? " " :  " [$d->{width}-1 : 0]";	
-		my $pdef_range = ($d->{pwidth} eq 1)? "[NE-1 : 0]" : "[(NE*$d->{pwidth})-1 : 0]";
-		my $endp_range = "[$d->{pwidth}-1 : 0]";
-		my $type=$d->{type};
-		my $ctype= ($type eq 'input')? 'output' : 'input';
-		if( $d->{endp} eq "yes"){ 	    	 
-			#$ports_def=$ports_def."\t$type $pdef_range $d->{name};\n";
-			#$ports_def=$ports_def."\t$ctype $pdef_range $d->{connect};\n";			
-			#$ports=$ports.",\n\t$d->{name},\n\t$d->{connect}";
-		}	
-			if($d->{width} eq 1){
-				#$router_wires=$router_wires. "\twire [NR-1 :0] router_$d->{name};\n";
-				#$router_wires=$router_wires. "\twire [NR-1 :0] router_$d->{connect};\n";
-			}else{	
-				#$router_wires=$router_wires. "\twire $range router_$d->{name} [NR-1 :0];\n";
-				#$router_wires=$router_wires. "\twire $range router_$d->{connect} [NR-1 :0];\n";
-			}
-		if( $d->{endp} eq "yes"){ 		
-		    if($d->{pwidth} eq 1){
-		    	#$endps_wires=$endps_wires. "\twire [NE-1 :0] ni_$d->{pname};\n";
-				#$endps_wires=$endps_wires. "\twire [NE-1 :0] ni_$d->{pconnect};\n";
-		    }else{	
-				#$endps_wires=$endps_wires. "\twire $endp_range ni_$d->{pname} [NE-1 :0];\n";
-				#$endps_wires=$endps_wires. "\twire $endp_range ni_$d->{pconnect} [NE-1 :0];\n";
-		    }
-			
-		}
-	}	
-		
-	
-	
-	
-	#step 2 	add routers
-	my $Tnum=1;
-	
-	my $routers='
-	genvar i;
-	generate	
-	';
-	my $offset=0;
-	my $assign="";
-	my $assign_r2r="";
-	my $assign_r2e="";
-	my $init_h="";
-	my $init_gnd_h="";
-	my %new_h;
-	my $addr=0;
-	for ( my $i=2;$i<=12; $i++){
-		my $n= $self->object_get_attribute("ROUTER${i}","NUM");
-		$n=0 if(!defined $n);
-		if($n>0){	
-						
-			for(my $rr=0; $rr<$n; $rr=$rr+1) {
-				my $pos= ($offset==0)? $rr : $rr+$offset;
-				$new_h{"TNUM_${pos}"}="$Tnum";
-				$new_h{"RNUM_${pos}"}="$rr";
-				
-				$init_h.="router${Tnum}[$rr]->current_r_addr=$addr;\n";
-				$init_h.="router${Tnum}[$rr]->current_r_id=$addr;\n";
-				$addr++;
-			}	
-			$offset+=	$n;
-			$Tnum++;		
-		}
-	}
-	
-	
-	
-	
-	
-	
-	
-	$offset=0;
-	my $R_num=0;
-	for ( my $i=2;$i<=12; $i++){
-		my $n= $self->object_get_attribute("ROUTER${i}","NUM");
-		$n=0 if(!defined $n);
-		if($n>0){	
-			my $router_pos= ($offset==0)? 'i' : "i+$offset";
-			#my $instant=get_router_genvar_instance_v($self,$i,$router_pos,$NE,$NR,$MAX_P);
-			my $p = $i-1;		
-			$routers=$routers."
-\tfor( i=0; i<$n; i=i+1) begin : router_${i}_port_lp
-	localparam RID = $router_pos;
-	assign current_r_addr [RID] = RID[RAw-1: 0]; 
-
-	router_top #(
-		.NOC_ID(NOC_ID),
-		.P($i)
-	)
-	router_${i}_port
-	(	
-		.clk(clk), 
-		.reset(reset),
-		.current_r_id(RID),
-		.current_r_addr(current_r_addr\[RID\]),	
-		.chan_in  (router_chan_in \[RID\] \[$p : 0\]), 
-		.chan_out (router_chan_out\[RID\] \[$p : 0\]),
-		.router_event(router_event\[RID\] \[$p : 0\])	
-	);
-    
-    
+    input  reset;
+    input  clk;
+    input  smartflit_chanel_t chan_in_all  [NE-1 : 0];
+    output smartflit_chanel_t chan_out_all [NE-1 : 0];
     
-\tend    
-			";
-	
-			for ( my $j=0;$j<$n; $j++){
-				my $rname ="ROUTER${i}_$j";
-				my ($ass_v,$r2r_h,$r2e_h, $int_h,$gnd_h);
-				($ass_v,$r2r_h,$r2e_h, $int_h,$gnd_h,$R_num) = get_wires_assignment_genvar_v($self,$rname,0,\%new_h,$R_num);
-				
-				$assign=$assign.$ass_v;
-				$assign_r2r.=$r2r_h;
-				$assign_r2e.=$r2e_h;
-				$init_h.=$int_h;
-				$init_gnd_h.=$gnd_h;
-			}
-			
-		$offset+=	$n;
-		
-		}	
-	}
-	
-	
-$routers.="endgenerate\n";	
-	
-	
-	
-	
-	
-	
-	 print $fd "
-module   ${name}_noc_genvar    
-#(
-	parameter NOC_ID=0
-)(
+    //Events
+    output  router_event_t  router_event [NR-1 : 0][MAX_P-1 : 0];
+    //all routers port 
+    smartflit_chanel_t    router_chan_in   [NR-1 :0][MAX_P-1 : 0];
+    smartflit_chanel_t    router_chan_out  [NR-1 :0][MAX_P-1 : 0];
+    router_config_t router_config [NR-1 : 0];
+";
 
+    my $router_wires="";
+    my $endps_wires="";
+    foreach my $d (@ports){        
+        my $range = ($d->{width} eq 1)? " " :  " [$d->{width}-1 : 0]";    
+        my $pdef_range = ($d->{pwidth} eq 1)? "[NE-1 : 0]" : "[(NE*$d->{pwidth})-1 : 0]";
+        my $endp_range = "[$d->{pwidth}-1 : 0]";
+        my $type=$d->{type};
+        my $ctype= ($type eq 'input')? 'output' : 'input';
+        if( $d->{endp} eq "yes"){              
+            #$ports_def=$ports_def."    $type $pdef_range $d->{name};\n";
+            #$ports_def=$ports_def."    $ctype $pdef_range $d->{connect};\n";            
+            #$ports=$ports.",\n    $d->{name},\n    $d->{connect}";
+        }    
+            if($d->{width} eq 1){
+                #$router_wires=$router_wires. "    wire [NR-1 :0] router_$d->{name};\n";
+                #$router_wires=$router_wires. "    wire [NR-1 :0] router_$d->{connect};\n";
+            }else{    
+                #$router_wires=$router_wires. "    wire $range router_$d->{name} [NR-1 :0];\n";
+                #$router_wires=$router_wires. "    wire $range router_$d->{connect} [NR-1 :0];\n";
+            }
+        if( $d->{endp} eq "yes"){         
+            if($d->{pwidth} eq 1){
+                #$endps_wires=$endps_wires. "    wire [NE-1 :0] ni_$d->{pname};\n";
+                #$endps_wires=$endps_wires. "    wire [NE-1 :0] ni_$d->{pconnect};\n";
+            }else{    
+                #$endps_wires=$endps_wires. "    wire $endp_range ni_$d->{pname} [NE-1 :0];\n";
+                #$endps_wires=$endps_wires. "    wire $endp_range ni_$d->{pconnect} [NE-1 :0];\n";
+            }
+            
+        }
+    }    
+    #step 2     add routers
+    my $Tnum=1;
+    my $routers="
+    genvar i;
+    generate   
+    if (TOPOLOGY == \"$name\" ) begin  
+    ";
+    my $offset=0;
+    my $assign="";
+    my $assign_r2r="";
+    my $assign_r2e="";
+    my $init_h="";
+    my $init_gnd_h="";
+    my %new_h;
+    my $addr=0;
+    for ( my $i=2;$i<=12; $i++){
+        my $n= $self->object_get_attribute("ROUTER${i}","NUM");
+        $n=0 if(!defined $n);
+        if($n>0){    
+                        
+            for(my $rr=0; $rr<$n; $rr=$rr+1) {
+                my $pos= ($offset==0)? $rr : $rr+$offset;
+                $new_h{"TNUM_${pos}"}="$Tnum";
+                $new_h{"RNUM_${pos}"}="$rr";
+                
+                $init_h.="router${Tnum}[$rr]->current_r_addr=$addr;\n";
+                $init_h.="router${Tnum}[$rr]->current_r_id=$addr;\n";
+                $addr++;
+            }    
+            $offset+=    $n;
+            $Tnum++;        
+        }
+    }
+    $offset=0;
+    my $R_num=0;
+    for ( my $i=2;$i<=12; $i++){
+        my $n= $self->object_get_attribute("ROUTER${i}","NUM");
+        $n=0 if(!defined $n);
+        if($n>0){    
+            my $router_pos= ($offset==0)? 'i' : "i+$offset";
+            #my $instant=get_router_genvar_instance_v($self,$i,$router_pos,$NE,$NR,$MAX_P);
+            my $p = $i-1;        
+            $routers=$routers."
+    for( i=0; i<$n; i=i+1) begin : router_${i}_port_lp
+        localparam RID = $router_pos;
+        assign router_config [RID].router_id = RID[RAw-1: 0];
+        assign router_config [RID].router_addr = RID[RAw-1: 0];
+        router_top #(
+            .ROUTER_ID(RID),
+            .P($i)
+        ) router_${i}_port (
+            .clk(clk), 
+            .reset(reset),
+            .router_config_in(router_config\[RID\]),
+            .chan_in  (router_chan_in \[RID\] \[$p : 0\]),
+            .chan_out (router_chan_out\[RID\] \[$p : 0\]),
+            .router_event(router_event\[RID\] \[$p : 0\])
+        );
+    end
+";
+            for ( my $j=0;$j<$n; $j++){
+                my $rname ="ROUTER${i}_$j";
+                my ($ass_v,$r2r_h,$r2e_h, $int_h,$gnd_h);
+                ($ass_v,$r2r_h,$r2e_h, $int_h,$gnd_h,$R_num) = get_wires_assignment_genvar_v($self,$rname,0,\%new_h,$R_num);
+                $assign=$assign.$ass_v;
+                $assign_r2r.=$r2r_h;
+                $assign_r2e.=$r2e_h;
+                $init_h.=$int_h;
+                $init_gnd_h.=$gnd_h;
+            }
+        $offset+=    $n;
+        }
+    }
+ #   $routers.="endgenerate\n";
+    print $fd "
+module   ${name}_noc_genvar
+(
     reset,
-    clk,    
+    clk,
     chan_in_all,
     chan_out_all,
-    router_event  
+    router_event
 );
-
-`NOC_CONF
-    
+import pronoc_pkg::*;
 $ports_def
-
 $router_wires
-
 $endps_wires
-   
 $routers
-
-$assign  
-
-  
-             
+$assign
+end // topology
+endgenerate
 endmodule
 ";
-	
-	close $fd;
-	add_info($info,"$top file is created\n  ");
-
-	my $project_dir	= get_project_dir();
-	$project_dir= "$project_dir/mpsoc";
-	my $src_verilator_dir="$project_dir/src_verilator/topology/custom";
-	mkpath("$src_verilator_dir",1,01777) unless -f $src_verilator_dir;
+    close $fd;
+    add_info($info,"$top file is created\n  ");
+    my $project_dir    = get_project_dir();
+    $project_dir= "$project_dir/mpsoc";
+    my $src_verilator_dir="$project_dir/src_verilator/topology/custom";
+    mkpath("$src_verilator_dir",1,01777) unless -f $src_verilator_dir;
     $top="$src_verilator_dir/${name}_noc.h";
     open $fd, ">$top" or $r = "$!\n";
     if(defined $r) {
-    	add_colored_info($info,"Error in creating $top: $r",'red');
-		return;
+        add_colored_info($info,"Error in creating $top: $r",'red');
+        return;
     } 
-    
-  my $fr2r="";
-  for (my $i=0;$i<$R_num ; $i++){ 
-  	$fr2r.="\n" if($i%10==0); 	
-  	$fr2r.=($i==0) ? "single_r2r$i" : ",single_r2r$i";
-  	
-  }  
-  
-  my $fr2e="";
-  for (my $i=0;$i<$NE ; $i++){ 
-  	$fr2e.="\n" if($i%10==0); 	
-  	$fr2e.=($i==0) ? "single_r2e$i" : ",single_r2e$i";  	
-  }   
-  
-    
+    my $fr2r="";
+    for (my $i=0;$i<$R_num ; $i++){ 
+        $fr2r.="\n" if($i%10==0);     
+        $fr2r.=($i==0) ? "single_r2r$i" : ",single_r2r$i";
+    }  
+    my $fr2e="";
+    for (my $i=0;$i<$NE ; $i++){ 
+        $fr2e.="\n" if($i%10==0);     
+        $fr2e.=($i==0) ? "single_r2e$i" : ",single_r2e$i";      
+    }   
     print $fd "
 
-
 $assign_r2r
 
 $assign_r2e
 
-
 void (*r2r_func_ptr[$R_num])() = {$fr2r};
 void (*r2e_func_ptr[$NE])() = {$fr2e};
 
 void topology_connect_r2r (int n){
-	 (*r2r_func_ptr[n])();
+        (*r2r_func_ptr[n])();
 }
 
 void topology_connect_r2e (int n){
-	 (*r2e_func_ptr[n])();
+        (*r2e_func_ptr[n])();
 }
 
-
-
 void topology_init(void){
-	$init_h
-	R2R_TABLE_SIZ=$R_num;
-	$init_gnd_h 	 
+    $init_h
+    R2R_TABLE_SIZ=$R_num;
+    $init_gnd_h      
 }
 ";
     close $fd;
-	add_info($info,"$top file is created\n  ");
-	
+    add_info($info,"$top file is created\n  ");
 }
 
-
-
-
 sub get_router_genvar_instance_v{
-	my ($self,$Pnum,$router_pos,$NE,$NR,$MAX_P)=@_;
-
-	#read ruter parameters and ports
-	my @parameters=@{$self->object_get_attribute ('Verilog','Router_param')};
+    my ($self,$Pnum,$router_pos,$NE,$NR,$MAX_P)=@_;
+    #read ruter parameters and ports
+    my @parameters=@{$self->object_get_attribute ('Verilog','Router_param')};
     my @ports= @{$self->object_get_attribute('Verilog','Router_ports')}; 
-	
-	
-	
-	my $router_v="	
-	
-	router_top #(
-		.NOC_ID(NOC_ID),
-		.P($Pnum)
-	)
-	router_${Pnum}_port
-	(	
-		.clk(clk), 
-		.reset(reset),
-		.current_r_addr($router_pos),
-		.current_r_id($router_pos),
-		.chan_in (router_chan_in\[$router_pos\]), 
-		.chan_out(router_chan_out\[$router_pos\]),
-		.router_event(router_event\[$router_pos\])	
-	);
-	
-	
-	
+    my $router_v="
+    assign router_config[$router_pos].router_id = $router_pos;
+    assign router_config[$router_pos].router_addr = $router_pos;
+    router_top #(
+        .ROUTER_ID($router_pos),
+        .P($Pnum)
+    ) router_${Pnum}_port (
+        .clk(clk), 
+        .reset(reset),
+        .router_config_in(router_config\[$router_pos\]),
+        .chan_in (router_chan_in\[$router_pos\]), 
+        .chan_out(router_chan_out\[$router_pos\]),
+        .router_event(router_event\[$router_pos\])    
+    );
 ";
 
 return $router_v;
-
-
 }
 
 
 sub get_wires_assignment_genvar_v{
-	my ($self,$rname,$reverse,$cref,$R_num)=@_;
+    my ($self,$rname,$reverse,$cref,$R_num)=@_;
     $reverse = 0 if(!defined $reverse);
-	my $instance= $self->object_get_attribute("$rname","NAME");		
-	my $Pnum=$self->object_get_attribute("$rname",'PNUM');
-	
-	#read ruter parameters and ports
-	 my @parameters=@{$self->object_get_attribute ('Verilog','Router_param')};
-     my @ports= @{$self->object_get_attribute('Verilog','Router_ports')}; 
-
-	my $assign="";
-	my $r2e_h="";
-	my $r2r_h="";
-	my $init_h="";
-	my $gnd_h="";
-	
-	
-
-	my @ends=get_list_of_all_endpoints($self);
+    my $instance= $self->object_get_attribute("$rname","NAME");        
+    my $Pnum=$self->object_get_attribute("$rname",'PNUM');
+    #read ruter parameters and ports
+    my @parameters=@{$self->object_get_attribute ('Verilog','Router_param')};
+    my @ports= @{$self->object_get_attribute('Verilog','Router_ports')}; 
+    my $assign="";
+    my $r2e_h="";
+    my $r2r_h="";
+    my $init_h="";
+    my $gnd_h="";
+    my @ends=get_list_of_all_endpoints($self);
     my @routers=get_list_of_all_routers($self);
-
-	my $pos = get_scolar_pos($rname,@routers);
-	my $type = "ROUTER";
-	if(!defined $pos){
-		$pos = get_scolar_pos($rname,@ends);
-		$type = "ENDP";
-	}
-	
-	my %rinfo = %{$cref} if (defined $cref);
-	
-for (my $i=0;$i<$Pnum; $i++){ 
-	my $pname= "Port[${i}]";
-	my $connect = $self->{$rname}{'PCONNECT'}{$pname};
-	my $iplus=$i+1;
-	if(defined $connect){
-		my ($cname,$pnode)=split(/\s*,\s*/,$connect);
-		my $cinstance= $self->object_get_attribute("$cname","NAME");
-		my $ctype = $self->object_get_attribute("$cname",'TYPE'); 		
-		my ($cp)= sscanf("Port[%u]","$pnode");
-		$assign.="//Connect $instance input ports $i to  $cinstance output ports $cp\n";
-		
-		
-		my $cpos =($ctype eq 'ENDP')?  get_scolar_pos($cname,@ends) :  get_scolar_pos($cname,@routers);
-		
-		my $cpplus=$cp+1;
-		my $cposplus = $cpos+1;
-		my $posplus=$pos+1;    	
-		#{name=> "flit_in_all", type=>"input", width=>"PFw", connect=>"flit_out_all",  pwidth=>"Fw" },
-		
-		my $TNUM_pos  = $rinfo{"TNUM_${pos}"};  
-		my $RNUM_pos  = $rinfo{"RNUM_${pos}"};  
-		my $TNUM_cpos = $rinfo{"TNUM_${cpos}"};
-		my $RNUM_cpos = $rinfo{"RNUM_${cpos}"};
-		
-		#$assign = $assign."//connet  $instance input port $i to  $cinstance output port $cp\n";
-		if($type  ne 'ENDP'  &&  $ctype eq 'ENDP'){
-			
-			$assign=  $assign."\t\tassign  router_chan_in \[$pos\]\[$i\] = chan_in_all \[$cpos\];\n" if($reverse==0);
-			$assign=  $assign."\t\tassign  chan_in_all \[$cpos\] = router_chan_in \[$pos\]\[$i\];\n" if($reverse==1);
-		
-			$assign=  $assign."\t\tassign  chan_out_all \[$cpos\] = router_chan_out \[$pos\]\[$i\];\n" if($reverse==0);
-			$assign=  $assign."\t\tassign  router_chan_out \[$pos\]\[$i\] = chan_out_all \[$cpos\];\n" if($reverse==1);
-			
-			$r2e_h.="//Connect $instance input ports $i to  $cinstance output ports $cp\n";			
-			$r2e_h.=  "void single_r2e$cpos(void) {connect_r2e($TNUM_pos,$RNUM_pos,$i,$cpos);}\n"	if (defined $TNUM_pos);	
-			
-		
-		}elsif ($type  ne 'ENDP'  &&  $ctype ne 'ENDP'){
-			$assign=  $assign."\t\tassign  router_chan_in \[$pos\]\[$i\] = router_chan_out \[$cpos\]\[$cp\];\n" if($reverse==0);
-			$assign=  $assign."\t\tassign  router_chan_out \[$cpos\]\[$cp\] = router_chan_in \[$pos\]\[$i\];\n" if($reverse==1);			
-			$r2r_h.="//Connect $instance input ports $i to  $cinstance output ports $cp\n";
-			$r2r_h.=  "void single_r2r$R_num(void){conect_r2r($TNUM_pos,$RNUM_pos,$i,$TNUM_cpos,$RNUM_cpos,$cp);}\n" if (defined $TNUM_pos);	
-			$init_h.="\tr2r_cnt_all[$R_num] =(r2r_cnt_table_t){.id1=$pos, .t1=$TNUM_pos, .r1=$RNUM_pos, .p1=$i,.id2=$cpos, .t2=$TNUM_cpos, .r2=$RNUM_cpos, .p2=$cp };\n";
-			$R_num++;
-		}
-				
-		
-		
-		
-			
-	}else {
-			my $TNUM_pos  = $rinfo{"TNUM_${pos}" };  
-			my $RNUM_pos  = $rinfo{"RNUM_${pos}" };  
-		
-			$assign = $assign."//Connect $instance port $i to  ground\n";		
-			$assign=  $assign."\t\tassign  router_chan_in  \[$pos\]\[$i\] ={SMARTFLIT_CHANEL_w{1'b0}};\n	" if($reverse==0);
-			$assign=  $assign."\t\tassign  router_chan_out \[$pos\]\[$i\] ={SMARTFLIT_CHANEL_w{1'b0}};\n	" if($reverse==1);	
-			
-			$gnd_h.="//Connect $instance port $i to  ground\n";
-			$gnd_h.=  "\tconnect_r2gnd($TNUM_pos,$RNUM_pos,$i);\n" if (defined $TNUM_pos);			
-	}		
-			
-}	
-
-	
-
-	return ($assign,$r2r_h,$r2e_h,$init_h,$gnd_h,$R_num);
+    my $pos = get_scolar_pos($rname,@routers);
+    my $type = "ROUTER";
+    if(!defined $pos){
+        $pos = get_scolar_pos($rname,@ends);
+        $type = "ENDP";
+    }
+    my %rinfo = %{$cref} if (defined $cref);
+    for (my $i=0;$i<$Pnum; $i++){ 
+        my $pname= "Port[${i}]";
+        my $connect = $self->{$rname}{'PCONNECT'}{$pname};
+        my $iplus=$i+1;
+        if(defined $connect){
+            my ($cname,$pnode)=split(/\s*,\s*/,$connect);
+            my $cinstance= $self->object_get_attribute("$cname","NAME");
+            my $ctype = $self->object_get_attribute("$cname",'TYPE');         
+            my ($cp)= sscanf("Port[%u]","$pnode");
+            $assign.="    //Connect $instance input ports $i to  $cinstance output ports $cp\n";
+            my $cpos =($ctype eq 'ENDP')?  get_scolar_pos($cname,@ends) :  get_scolar_pos($cname,@routers);
+            my $cpplus=$cp+1;
+            my $cposplus = $cpos+1;
+            my $posplus=$pos+1;        
+            #{name=> "flit_in_all", type=>"input", width=>"PFw", connect=>"flit_out_all",  pwidth=>"Fw" },
+            my $TNUM_pos  = $rinfo{"TNUM_${pos}"};  
+            my $RNUM_pos  = $rinfo{"RNUM_${pos}"};  
+            my $TNUM_cpos = $rinfo{"TNUM_${cpos}"};
+            my $RNUM_cpos = $rinfo{"RNUM_${cpos}"};
+            #$assign = $assign."//connet  $instance input port $i to  $cinstance output port $cp\n";
+            if($type  ne 'ENDP'  &&  $ctype eq 'ENDP'){
+                $assign=  $assign."    assign  router_chan_in \[$pos\]\[$i\] = chan_in_all \[$cpos\];\n" if($reverse==0);
+                $assign=  $assign."    assign  chan_in_all \[$cpos\] = router_chan_in \[$pos\]\[$i\];\n" if($reverse==1);
+                $assign=  $assign."    assign  chan_out_all \[$cpos\] = router_chan_out \[$pos\]\[$i\];\n" if($reverse==0);
+                $assign=  $assign."    assign  router_chan_out \[$pos\]\[$i\] = chan_out_all \[$cpos\];\n" if($reverse==1);
+                $r2e_h.="    //Connect $instance input ports $i to  $cinstance output ports $cp\n";            
+                $r2e_h.=  "void single_r2e$cpos(void) {connect_r2e($TNUM_pos,$RNUM_pos,$i,$cpos);}\n"    if (defined $TNUM_pos);    
+            }elsif ($type  ne 'ENDP'  &&  $ctype ne 'ENDP'){
+                $assign=  $assign."    assign  router_chan_in \[$pos\]\[$i\] = router_chan_out \[$cpos\]\[$cp\];\n" if($reverse==0);
+                $assign=  $assign."    assign  router_chan_out \[$cpos\]\[$cp\] = router_chan_in \[$pos\]\[$i\];\n" if($reverse==1);            
+                $r2r_h.="    //Connect $instance input ports $i to  $cinstance output ports $cp\n";
+                $r2r_h.=  "void single_r2r$R_num(void){conect_r2r($TNUM_pos,$RNUM_pos,$i,$TNUM_cpos,$RNUM_cpos,$cp);}\n" if (defined $TNUM_pos);    
+                $init_h.="    r2r_cnt_all[$R_num] =(r2r_cnt_table_t){.id1=$pos, .t1=$TNUM_pos, .r1=$RNUM_pos, .p1=$i,.id2=$cpos, .t2=$TNUM_cpos, .r2=$RNUM_cpos, .p2=$cp };\n";
+                $R_num++;
+            }
+        }else {
+                my $TNUM_pos  = $rinfo{"TNUM_${pos}" };  
+                my $RNUM_pos  = $rinfo{"RNUM_${pos}" };  
+                $assign = $assign."    //Connect $instance port $i to  ground\n";        
+                $assign=  $assign."    assign  router_chan_in  \[$pos\]\[$i\] ={SMARTFLIT_CHANEL_w{1'b0}};\n    " if($reverse==0);
+                $assign=  $assign."    assign  router_chan_out \[$pos\]\[$i\] ={SMARTFLIT_CHANEL_w{1'b0}};\n    " if($reverse==1);    
+                $gnd_h.="    //Connect $instance port $i to  ground\n";
+                $gnd_h.=  "    connect_r2gnd($TNUM_pos,$RNUM_pos,$i);\n" if (defined $TNUM_pos);            
+        }
+    }
+    return ($assign,$r2r_h,$r2e_h,$init_h,$gnd_h,$R_num);
 }
 
-
-
-
-
 sub generate_routing_v {
-	my ($self,$info,$dir)=@_;
-	
-	my @ends=get_list_of_all_endpoints($self);
-	my @routers=get_list_of_all_routers($self);
-	
-#########################	
-#  conventional_routing
-#########################
-
+    my ($self,$info,$dir)=@_;
+    my @ends=get_list_of_all_endpoints($self);
+    my @routers=get_list_of_all_routers($self);
+    #create routing file
+    my $name=$self->object_get_attribute('save_as');
+    my $rname=$self->object_get_attribute('routing_name');
+    my $Vname="T${name}R${rname}";
+    gen_ni_routing_file($self,$info,$dir,$Vname);
+    gen_ni_genvar_route($self,$info,$dir,$Vname);
+    gen_lkhead_genvar_routing_file ($self,$info,$dir,$Vname,'look_ahead');
+    gen_lkhead_conv_routing_file($self,$info,$dir,$Vname,'look_ahead');
+    gen_lkhead_conv_routing_file($self,$info,$dir,$Vname,'conv');
+}
 
-	#create routing file
-	my $name=$self->object_get_attribute('save_as');
-	my $rname=$self->object_get_attribute('routing_name');
-	my $Vname="T${name}R${rname}";
-	
-	my $r; 
-	my $top="$dir/${Vname}_conventional_routing.v";
+##########
+# ni_genvar_route
+#########
+sub gen_ni_genvar_route{
+    my ($self,$info,$dir,$Vname)=@_;
+    #create routing file
+    my $top="$dir/${Vname}_ni_routing_genvar.v";
+    my $r;
+    my @ends=get_list_of_all_endpoints($self);
+    my @routers=get_list_of_all_routers($self);
     open my $fd, ">$top" or $r = "$!\n";
     if(defined $r) {
-    	add_colored_info($info,"Error in creating $top: $r",'red');
-		return;
+        add_colored_info($info,"Error in creating $top: $r",'red');
+        return;
     } 
     print $fd autogen_warning();
     print $fd get_license_header($top);   
-	
-	
-	
-	
-	
-	my $route_str="\talways@(*)begin
-\t\tdestport=0;
-\t\tcase(src_e_addr) //source address of each individual NI is fixed. So this CASE will be optimized by the synthesizer for each endpoint. 
-";
-	
-	foreach my $src (@ends){
-		my $PNUM=$self->object_get_attribute($src,"PNUM");
-		my $src_num=get_scolar_pos($src,@ends);
-	    my %route;		
-		$route_str=$route_str."\t\t$src_num: begin
-\t\t\tcase(dest_e_addr)
-";
-		
-		foreach my $dst (@ends){
-			    my $dest_num = get_scolar_pos($dst,@ends);
-				my $ref = $self->object_get_attribute('Route',"${src}::$dst");
-				next if(!defined $ref);
-				my @path = @{$ref};
-				my ($p1,$p2)= get_connection_port_num_between_two_nodes($self,$path[1],$path[2] );
-				#print " ($p1,$p2)= get_connection_port_num_between_two_nodes($self,$path[1],$path[2] );\n";
-				$route{$p1} = (defined $route{$p1})? $route{$p1}.",$dest_num" : "$dest_num";						
-		}
-		foreach my $q (sort {$a <=> $b} keys %route){
-			$route_str=$route_str."\t\t\t$route{$q}: begin 
-\t\t\t\tdestport= $q; 
-\t\t\tend
-";
-		}
-		$route_str=$route_str."
-\t\t\tdefault: begin 
-\t\t\t\tdestport= {DSTPw{1\'bX}};
-\t\t\tend
-\t\t\tendcase\n\t\tend//$src_num\n";
-	}
-	$route_str=$route_str."
-\t\tdefault: begin 
-\t\t\tdestport= {DSTPw{1\'bX}};
-\t\tend
-\t\tendcase\n\tend\n";
-
-	
-	
-	 print $fd "module ${Vname}_conventional_routing  #(
-\tparameter RAw = 3,  
-\tparameter EAw = 3,   
-\tparameter DSTPw=4  
-)
-(
-\tdest_e_addr,
-\tsrc_e_addr,
-\tdestport        
-);
-    
-\tinput   [EAw-1   :0] dest_e_addr;
-\tinput   [EAw-1   :0] src_e_addr;
-\toutput reg [DSTPw-1 :0] destport;	
+    my $route_str="    generate\n";
+    foreach my $src (@ends){
+        my $PNUM=$self->object_get_attribute($src,"PNUM");
+        my $src_num=get_scolar_pos($src,@ends);
+        my %route;
+        $route_str=$route_str."    if(SRC_E_ADDR == $src_num) begin : SRC$src_num
+        always@(*)begin
+            destport= 0; 
+            case(dest_e_addr)\n";
         
+        foreach my $dst (@ends){
+            my $dest_num = get_scolar_pos($dst,@ends);
+            my $ref = $self->object_get_attribute('Route',"${src}::$dst");
+            next if(!defined $ref);
+            my @path = @{$ref};
+            my ($p1,$p2)= get_connection_port_num_between_two_nodes($self,$path[1],$path[2] );
+            #print " ($p1,$p2)= get_connection_port_num_between_two_nodes($self,$path[1],$path[2] );\n";
+            $route{$p1} = (defined $route{$p1})? $route{$p1}.",$dest_num" : "$dest_num";                        
+        }
+        foreach my $q (sort {$a <=> $b} keys %route){
+            $route_str=$route_str."            $route{$q}: begin 
+                destport= $q; 
+            end\n";
+        }
+        $route_str=$route_str."            default: begin 
+                destport= {DSTPw{1\'bX}};
+            end
+            endcase\n        end\n    end//SRC$src_num\n\n";
+    }
+    $route_str=$route_str."    endgenerate\n";
+    print $fd "module ${Vname}_ni_routing_genvar  #(
+    parameter RAw = 3,
+    parameter EAw = 3,
+    parameter DSTPw=4,
+    parameter SRC_E_ADDR=0  
+) (
+    dest_e_addr,
+    destport
+);
+    input   [EAw-1   :0] dest_e_addr;
+    output reg [DSTPw-1 :0] destport;
     
 $route_str
-		
-	
-endmodule  
     
+endmodule
 ";
-close($fd);
-add_info($info,"$top file is created\n  ");
-
-##################
-#   look_ahead_routing
-###################
+    close($fd);
+    add_info($info,"$top file is created\n  ");
+}
 
-#create routing file
-	$top="$dir/${Vname}_look_ahead_routing.v";
-    open  $fd, ">$top" or $r = "$!\n";
+################
+#   ni_route
+###############
+sub gen_ni_routing_file {
+    my ($self,$info,$dir,$Vname)=@_;
+    my @ends=get_list_of_all_endpoints($self);
+    my @routers=get_list_of_all_routers($self);
+    my $r; 
+    my $top="$dir/${Vname}_ni_routing.v";
+    open my $fd, ">$top" or $r = "$!\n";
     if(defined $r) {
-    	add_colored_info($info,"Error in creating $top: $r",'red');
-		return;
+        add_colored_info($info,"Error in creating $top: $r",'red');
+        return;
     } 
     print $fd autogen_warning();
     print $fd get_license_header($top);   
-
-
-	$route_str="\talways@(*)begin
-\t\tdestport=0;
-\t\tcase(current_r_addr) //current_r_addr of each individual router is fixed. So this CASE will be optimized by the synthesizer for each router. 
-";
-
-
-
-foreach my $router (@routers){
-		my $PNUM=$self->object_get_attribute($router,"PNUM");
-		my $router_num=get_scolar_pos($router,@routers);
-	    my %route;		
-		$route_str=$route_str."\t\t$router_num: begin
-\t\t\tcase({src_e_addr,dest_e_addr})
-";
-	# for each src-dest check if $router include in path 
-	foreach my $src (@ends){
-		foreach my $dst (@ends){
-			my $ref = $self->object_get_attribute('Route',"${src}::$dst");
-			next if(!defined $ref);
-			my @path = @{$ref};
-		    my $loc= get_scolar_pos($router,@path);
-		    next if(!defined $loc);# this router does not exist in path skip it
-		    my $next_router1=$path[$loc+1];
-		    my $next_router2=$path[$loc+2];
-		    next if(!defined $next_router2);
-		    my ($p1,$p2)= get_connection_port_num_between_two_nodes($self,$next_router1,$next_router2);		    
-		    next if(!defined $p1);
-		    my $src_num=get_scolar_pos($src,@ends);
-		    my $dest_num = get_scolar_pos($dst,@ends);
-			$route{$p1} = (defined $route{$p1})? $route{$p1}.",{E$src_num,E$dest_num}" : "{E$src_num,E$dest_num}";
-			
-			#print "@path\n";
-			#print "(current_router, next_router1, next_router2)=($router, $next_router1, $next_router2)\n";
-			#print "($p1,$p2)= get_connection_port_num_between_two_nodes(\$self,$next_router1,$next_router2)\n";	
-			#print "\$route{$p1} ={E$src_num,E$dest_num}\n";
-			#print"***************************\n"; 
-			
-		}
-	}
-	foreach my $q (sort {$a <=> $b} keys %route){
-			$route_str=$route_str."\t\t\t$route{$q}: begin 
-\t\t\t\tdestport= $q; 
-\t\t\tend
-";		
-					
-	}				
-		
-	$route_str.="\t\t\tdefault: begin 
-\t\t\t\tdestport= {DSTPw{1\'bX}};
-\t\t\tend
-\t\t\tendcase\n\t\tend//$router_num\n";
-	}
-$route_str.="\t\tdefault: begin 
-\t\t\tdestport= {DSTPw{1\'bX}};
-\t\tend
-\t\tendcase\n\tend\n";
-	
-
-
-my $localparam="";
-	my $i=0;
-	foreach my $src (@ends){
-		$localparam= $localparam."localparam [EAw-1 : 0]\tE$i=$i;\n";
-		$i++;
-	}	
-	
-
-
-
- print $fd "
- 
- `include \"pronoc_def.v\"
-/*******************
-*  ${Vname}_look_ahead_routing
-*******************/  
-module ${Vname}_look_ahead_routing  #(
-\tparameter RAw = 3,  
-\tparameter EAw = 3,   
-\tparameter DSTPw=4  
+    my $route_str="    always@(*)begin
+        destport=0;
+        case(src_e_addr) //source address of each individual NI is fixed. So this CASE will be optimized by the synthesizer for each endpoint.\n";
+    foreach my $src (@ends){
+        my $PNUM=$self->object_get_attribute($src,"PNUM");
+        my $src_num=get_scolar_pos($src,@ends);
+        my %route;        
+        $route_str=$route_str."        $src_num: begin
+            case(dest_e_addr)\n";
+        foreach my $dst (@ends){
+            my $dest_num = get_scolar_pos($dst,@ends);
+            my $ref = $self->object_get_attribute('Route',"${src}::$dst");
+            next if(!defined $ref);
+            my @path = @{$ref};
+            my ($p1,$p2)= get_connection_port_num_between_two_nodes($self,$path[1],$path[2] );
+            #print " ($p1,$p2)= get_connection_port_num_between_two_nodes($self,$path[1],$path[2] );\n";
+            $route{$p1} = (defined $route{$p1})? $route{$p1}.",$dest_num" : "$dest_num";
+        }
+        foreach my $q (sort {$a <=> $b} keys %route){
+            $route_str=$route_str."            $route{$q}: begin 
+                destport= $q; 
+            end\n";
+        }
+        $route_str=$route_str."
+            default: begin 
+                destport= {DSTPw{1\'bX}};
+            end
+            endcase\n        end//$src_num\n";
+    }
+    $route_str=$route_str."
+        default: begin 
+            destport= {DSTPw{1\'bX}};
+        end
+        endcase\n    end\n";
+    print $fd "module ${Vname}_ni_routing  #(
+    parameter RAw = 3,
+    parameter EAw = 3,
+    parameter DSTPw=4
 )
 (
-\treset,
-\tclk,
-\tcurrent_r_addr,
-\tdest_e_addr,
-\tsrc_e_addr,
-\tdestport        
+    dest_e_addr,
+    src_e_addr,
+    destport
 );
+    input   [EAw-1   :0] dest_e_addr;
+    input   [EAw-1   :0] src_e_addr;
+    output reg [DSTPw-1 :0] destport;
     
-\tinput   [RAw-1   :0] current_r_addr;
-\tinput   [EAw-1   :0] dest_e_addr;
-\tinput   [EAw-1   :0] src_e_addr;
-\toutput  [DSTPw-1 :0] destport;	
-\tinput reset,clk;
-
-	reg [EAw-1   :0] dest_e_addr_delay;
-	reg [EAw-1   :0] src_e_addr_delay;
-
-	always @ (`pronoc_clk_reset_edge )begin 
-        if(`pronoc_reset)begin 
-			dest_e_addr_delay<={EAw{1'b0}};
-			src_e_addr_delay<={EAw{1'b0}};			
-		end else begin 
-			dest_e_addr_delay<=dest_e_addr;
-			src_e_addr_delay<=src_e_addr;					
-		end 	
-	end
-
-	${Vname}_look_ahead_routing_comb  #(
-		.RAw(RAw),  
-		.EAw(EAw),   
-		.DSTPw(DSTPw)  
-	)
-	lkp_cmb
-	(
-		.current_r_addr(current_r_addr),
-		.dest_e_addr(dest_e_addr_delay),
-		.src_e_addr(src_e_addr_delay),
-		.destport(destport)        
-	);
-
-
-	
-endmodule  
- 
-/*******************
-*  ${Vname}_look_ahead_routing_comb
-*******************/ 
-  
- module ${Vname}_look_ahead_routing_comb  #(
-\tparameter RAw = 3,  
-\tparameter EAw = 3,   
-\tparameter DSTPw=4  
-)
-(
-\tcurrent_r_addr,
-\tdest_e_addr,
-\tsrc_e_addr,
-\tdestport        
-);
+$route_str
     
-\tinput   [RAw-1   :0] current_r_addr;
-\tinput   [EAw-1   :0] dest_e_addr;
-\tinput   [EAw-1   :0] src_e_addr;
-\toutput reg [DSTPw-1 :0] destport;	
-
-$localparam
-        
-$route_str  
-
-	
-endmodule  
-
-
+endmodule
 ";
-
-close($fd);
-add_info($info,"$top file is created\n  ");
-
-#########################	
-#  conventional_routing_genvar
-#########################
-
-
-	#create routing file
-	$top="$dir/${Vname}_conventional_routing_genvar.v";
-    open $fd, ">$top" or $r = "$!\n";
+    close($fd);
+    add_info($info,"$top file is created\n  ");
+}
+####################
+#   gen_lkhead_genvar_routing_file
+####################
+sub gen_lkhead_genvar_routing_file {
+    my ( $self,$info,$dir,$Vname,$mode)=@_; 
+    #conventional or look_ahead
+    my $top="$dir/${Vname}_${mode}_routing_genvar.v";
+    my $r;
+    my @ends=get_list_of_all_endpoints($self);
+    my @routers=get_list_of_all_routers($self);
+    my $localparam="";
+    my $i=0;
+    foreach my $src (@ends){
+        $localparam= $localparam."localparam [EAw-1 : 0]    E$i=$i;\n";
+        $i++;
+    }    
+    open  my $fd, ">$top" or $r = "$!\n";
     if(defined $r) {
-    	add_colored_info($info,"Error in creating $top: $r",'red');
-		return;
+        add_colored_info($info,"Error in creating $top: $r",'red');
+        return;
     } 
     print $fd autogen_warning();
-    print $fd get_license_header($top);   
-	
-	
-	
-	
-	
-	$route_str="\tgenerate
-
+    print $fd get_license_header($top);
+    my $route_str="    always@(*)begin
+        destport=0;
+        case(current_r_addr) //current_r_addr of each individual router is fixed. So this CASE will be optimized by the synthesizer for each router. 
 ";
-	
-	foreach my $src (@ends){
-		my $PNUM=$self->object_get_attribute($src,"PNUM");
-		my $src_num=get_scolar_pos($src,@ends);
-	    my %route;		
-		$route_str=$route_str."\tif(SRC_E_ADDR == $src_num) begin : SRC$src_num
-\t\talways@(*)begin	
-\t\t\tdestport= 0; 
-\t\t\tcase(dest_e_addr)
+    $route_str="    generate\n";
+    foreach my $router (@routers){
+        my $PNUM=$self->object_get_attribute($router,"PNUM");
+        my $router_num=get_scolar_pos($router,@routers);
+        my %route;
+        $route_str=$route_str."    if(CURRENT_R_ADDR == $router_num) begin :R$router_num
+        always@(*)begin
+            destport= 0;
+            case({src_e_addr,dest_e_addr})
 ";
-		
-		foreach my $dst (@ends){
-			    my $dest_num = get_scolar_pos($dst,@ends);
-				my $ref = $self->object_get_attribute('Route',"${src}::$dst");
-				next if(!defined $ref);
-				my @path = @{$ref};
-				my ($p1,$p2)= get_connection_port_num_between_two_nodes($self,$path[1],$path[2] );
-				#print " ($p1,$p2)= get_connection_port_num_between_two_nodes($self,$path[1],$path[2] );\n";
-				$route{$p1} = (defined $route{$p1})? $route{$p1}.",$dest_num" : "$dest_num";						
-		}
-		foreach my $q (sort {$a <=> $b} keys %route){
-			$route_str=$route_str."\t\t\t$route{$q}: begin 
-\t\t\t\tdestport= $q; 
-\t\t\tend
+    # for each src-dest check if $router include in path 
+    foreach my $src (@ends){
+        foreach my $dst (@ends){
+            my $ref = $self->object_get_attribute('Route',"${src}::$dst");
+            next if(!defined $ref);
+            my @path = @{$ref};
+            my $loc= get_scolar_pos($router,@path);
+            next if(!defined $loc);# this router does not exist in path skip it
+            my $next_router1=($mode eq 'look_ahead')? $path[$loc+1] : $path[$loc];
+            my $next_router2=($mode eq 'look_ahead')? $path[$loc+2] : $path[$loc+1];
+            next if(!defined $next_router2);
+            my ($p1,$p2)= get_connection_port_num_between_two_nodes($self,$next_router1,$next_router2);
+            next if(!defined $p1);
+            my $src_num=get_scolar_pos($src,@ends);
+            my $dest_num = get_scolar_pos($dst,@ends);
+            $route{$p1} = (defined $route{$p1})? $route{$p1}.",{E$src_num,E$dest_num}" : "{E$src_num,E$dest_num}";
+            #print "@path\n";
+            #print "(current_router, next_router1, next_router2)=($router, $next_router1, $next_router2)\n";
+            #print "($p1,$p2)= get_connection_port_num_between_two_nodes(\$self,$next_router1,$next_router2)\n";
+            #print "\$route{$p1} ={E$src_num,E$dest_num}\n";
+            #print"***************************\n"; 
+        }
+    }
+    foreach my $q (sort {$a <=> $b} keys %route){
+            $route_str=$route_str."            $route{$q}: begin 
+                destport= $q; 
+            end
 ";
-		}
-		$route_str=$route_str."\t\t\tdefault: begin 
-\t\t\t\tdestport= {DSTPw{1\'bX}};
-\t\t\tend
-
-\t\t\tendcase\n\t\tend\n\tend//SRC$src_num\n\n";
-	}
-	$route_str=$route_str."\tendgenerate\n";
-
-	
-	
-	 print $fd "module ${Vname}_conventional_routing_genvar  #(
-\tparameter RAw = 3,  
-\tparameter EAw = 3,   
-\tparameter DSTPw=4,
-\tparameter SRC_E_ADDR=0  
-)
-(
-\tdest_e_addr,
-\tdestport        
+    }
+    $route_str=$route_str."            endcase\n        end\n    end//R$router_num\n\n";
+    }
+    $route_str=$route_str."    endgenerate\n";
+    print $fd "
+`include \"pronoc_def.v\"
+/*****************************
+*    ${Vname}_${mode}_routing_genvar
+******************************/ 
+module ${Vname}_${mode}_routing_genvar  #(
+    parameter RAw = 3,  
+    parameter EAw = 3,   
+    parameter DSTPw=4,
+    parameter CURRENT_R_ADDR=0
+)(
+    dest_e_addr,
+    src_e_addr,
+    destport,
+    reset,
+    clk
 );
     
-\tinput   [EAw-1   :0] dest_e_addr;
-\toutput reg [DSTPw-1 :0] destport;	
-        
+    input   [EAw-1   :0] dest_e_addr;
+    input   [EAw-1   :0] src_e_addr;
+    output  [DSTPw-1 :0] destport;
+    input reset,clk;
     
-$route_str
-		
-	
-endmodule  
+    reg [EAw-1   :0] dest_e_addr_delay;
+    reg [EAw-1   :0] src_e_addr_delay;
     
+    always @ (`pronoc_clk_reset_edge )begin 
+        if(`pronoc_reset) begin 
+            dest_e_addr_delay<={EAw{1'b0}};
+            src_e_addr_delay<={EAw{1'b0}};
+        end else begin 
+            dest_e_addr_delay<=dest_e_addr;
+            src_e_addr_delay<=src_e_addr;
+        end
+    end
+    ${Vname}_${mode}_routing_genvar_comb  #(
+        .RAw(RAw),
+        .EAw(EAw),
+        .DSTPw(DSTPw),
+        .CURRENT_R_ADDR(CURRENT_R_ADDR)
+    ) lkp_cmb (
+        .dest_e_addr(dest_e_addr_delay),
+        .src_e_addr(src_e_addr_delay),
+        .destport(destport)
+    );
+endmodule
+
+/*******************
+* ${Vname}_${mode}_routing_genvar_comb
+********************/ 
+module ${Vname}_${mode}_routing_genvar_comb  #(
+    parameter RAw = 3,
+    parameter EAw = 3,
+    parameter DSTPw=4,
+    parameter CURRENT_R_ADDR=0
+) (
+    dest_e_addr,
+    src_e_addr,
+    destport
+);
+    input   [EAw-1   :0] dest_e_addr;
+    input   [EAw-1   :0] src_e_addr;
+    output  reg [DSTPw-1 :0] destport;
+$localparam
+
+$route_str
+
+endmodule
 ";
-close($fd);
-add_info($info,"$top file is created\n  ");
+    close($fd);
+    add_info($info,"$top file is created\n  ");
 
-##################
-#   look_ahead_routing_genvar
-###################
+}
 
-#create routing file
-	$top="$dir/${Vname}_look_ahead_routing_genvar.v";
-    open  $fd, ">$top" or $r = "$!\n";
+###########
+#   gen_lkhead_conv_routing_file
+##########
+sub gen_lkhead_conv_routing_file {
+    my ( $self,$info,$dir,$Vname,$mode)=@_; 
+    #conventional or look_ahead
+    my $r;
+    my @ends=get_list_of_all_endpoints($self);
+    my @routers=get_list_of_all_routers($self);
+
+    my $top="$dir/${Vname}_${mode}_routing.v";
+    open my $fd, ">$top" or $r = "$!\n";
     if(defined $r) {
-    	add_colored_info($info,"Error in creating $top: $r",'red');
-		return;
+        add_colored_info($info,"Error in creating $top: $r",'red');
+        return;
     } 
     print $fd autogen_warning();
-    print $fd get_license_header($top);   
-
-
-
-	$route_str="\talways@(*)begin
-\t\tdestport=0;
-\t\tcase(current_r_addr) //current_r_addr of each individual router is fixed. So this CASE will be optimized by the synthesizer for each router. 
+    print $fd get_license_header($top);
+    my $route_str="    always@(*)begin
+        destport=0;
+        case(current_r_addr) //current_r_addr of each individual router is fixed. So this CASE will be optimized by the synthesizer for each router. 
 ";
 
-$route_str="\tgenerate\n";
-
-
 foreach my $router (@routers){
-		my $PNUM=$self->object_get_attribute($router,"PNUM");
-		my $router_num=get_scolar_pos($router,@routers);
-	    my %route;		
-		$route_str=$route_str."\tif(CURRENT_R_ADDR == $router_num) begin :R$router_num
-\t\talways@(*)begin	
-\t\t\tdestport= 0; 
-\t\t\tcase({src_e_addr,dest_e_addr})
+    my $PNUM=$self->object_get_attribute($router,"PNUM");
+    my $router_num=get_scolar_pos($router,@routers);
+    my %route;        
+    $route_str=$route_str."        $router_num: begin
+            case({src_e_addr,dest_e_addr})
 ";
-	# for each src-dest check if $router include in path 
-	foreach my $src (@ends){
-		foreach my $dst (@ends){
-			my $ref = $self->object_get_attribute('Route',"${src}::$dst");
-			next if(!defined $ref);
-			my @path = @{$ref};
-		    my $loc= get_scolar_pos($router,@path);
-		    next if(!defined $loc);# this router does not exist in path skip it
-		    my $next_router1=$path[$loc+1];
-		    my $next_router2=$path[$loc+2];
-		    next if(!defined $next_router2);
-		    my ($p1,$p2)= get_connection_port_num_between_two_nodes($self,$next_router1,$next_router2);		    
-		    next if(!defined $p1);
-		    my $src_num=get_scolar_pos($src,@ends);
-		    my $dest_num = get_scolar_pos($dst,@ends);
-			$route{$p1} = (defined $route{$p1})? $route{$p1}.",{E$src_num,E$dest_num}" : "{E$src_num,E$dest_num}";
-			
-			#print "@path\n";
-			#print "(current_router, next_router1, next_router2)=($router, $next_router1, $next_router2)\n";
-			#print "($p1,$p2)= get_connection_port_num_between_two_nodes(\$self,$next_router1,$next_router2)\n";	
-			#print "\$route{$p1} ={E$src_num,E$dest_num}\n";
-			#print"***************************\n"; 
-			
-		}
-	}
-	foreach my $q (sort {$a <=> $b} keys %route){
-			$route_str=$route_str."\t\t\t$route{$q}: begin 
-\t\t\t\tdestport= $q; 
-\t\t\tend
-";		
-					
-	}				
-		
-	$route_str=$route_str."\t\t\tendcase\n\t\tend\n\tend//R$router_num\n\n";
-	}
-	$route_str=$route_str."\tendgenerate\n";
-	
-
-
- print $fd "
- `include \"pronoc_def.v\"
- 
-/*****************************
-*	${Vname}_look_ahead_routing_genvar
-******************************/ 
-module ${Vname}_look_ahead_routing_genvar  #(
-\tparameter RAw = 3,  
-\tparameter EAw = 3,   
-\tparameter DSTPw=4,
-\tparameter CURRENT_R_ADDR=0
-)
-(
-\tdest_e_addr,
-\tsrc_e_addr,
-\tdestport,
-\treset,
-\tclk        
+    # for each src-dest check if $router include in path 
+    foreach my $src (@ends){
+        foreach my $dst (@ends){
+            my $ref = $self->object_get_attribute('Route',"${src}::$dst");
+            next if(!defined $ref);
+            my @path = @{$ref};
+            my $loc= get_scolar_pos($router,@path);
+            next if(!defined $loc);# this router does not exist in path skip it
+            my $next_router1=($mode eq 'look_ahead')? $path[$loc+1] : $path[$loc];
+            my $next_router2=($mode eq 'look_ahead')? $path[$loc+2] : $path[$loc+1];
+            next if(!defined $next_router2);
+            my ($p1,$p2)= get_connection_port_num_between_two_nodes($self,$next_router1,$next_router2);
+            next if(!defined $p1);
+            my $src_num=get_scolar_pos($src,@ends);
+            my $dest_num = get_scolar_pos($dst,@ends);
+            $route{$p1} = (defined $route{$p1})? $route{$p1}.",{E$src_num,E$dest_num}" : "{E$src_num,E$dest_num}";
+            #print "@path\n";
+            #print "(current_router, next_router1, next_router2)=($router, $next_router1, $next_router2)\n";
+            #print "($p1,$p2)= get_connection_port_num_between_two_nodes(\$self,$next_router1,$next_router2)\n";
+            #print "\$route{$p1} ={E$src_num,E$dest_num}\n";
+            #print"***************************\n"; 
+        }
+    }
+    foreach my $q (sort {$a <=> $b} keys %route){
+            $route_str=$route_str."            $route{$q}: begin 
+                destport= $q; 
+            end
+";
+    }
+    $route_str.="            default: begin 
+                destport= {DSTPw{1\'bX}};
+            end
+            endcase\n        end//$router_num\n";
+    }
+    $route_str.="        default: begin 
+            destport= {DSTPw{1\'bX}};
+        end
+        endcase\n    end\n";
+    
+    my $localparam="";
+    my $i=0;
+    foreach my $src (@ends){
+        $localparam= $localparam."localparam [EAw-1 : 0]    E$i=$i;\n";
+        $i++;
+    }    
+    print $fd "
+    
+`include \"pronoc_def.v\"
+/*******************
+*  ${Vname}_${mode}_routing
+*******************/
+module ${Vname}_${mode}_routing  #(
+    parameter RAw = 3,
+    parameter EAw = 3,
+    parameter DSTPw=4
+)(
+    reset,
+    clk,
+    current_r_addr,
+    dest_e_addr,
+    src_e_addr,
+    destport
 );
+    input   [RAw-1   :0] current_r_addr;
+    input   [EAw-1   :0] dest_e_addr;
+    input   [EAw-1   :0] src_e_addr;
+    output  [DSTPw-1 :0] destport;
+    input reset,clk;
+    reg [EAw-1   :0] dest_e_addr_delay;
+    reg [EAw-1   :0] src_e_addr_delay;
+    
+    always @ (`pronoc_clk_reset_edge )begin 
+        if(`pronoc_reset)begin
+            dest_e_addr_delay<={EAw{1'b0}};
+            src_e_addr_delay<={EAw{1'b0}};
+        end else begin 
+            dest_e_addr_delay<=dest_e_addr;
+            src_e_addr_delay<=src_e_addr;
+        end
+    end
+    
+    ${Vname}_${mode}_routing_comb  #(
+        .RAw(RAw),
+        .EAw(EAw),
+        .DSTPw(DSTPw)
+    ) lkp_cmb  (
+        .current_r_addr(current_r_addr),
+        .dest_e_addr(dest_e_addr_delay),
+        .src_e_addr(src_e_addr_delay),
+        .destport(destport)
+    );
+endmodule
 
-\tinput   [EAw-1   :0] dest_e_addr;
-\tinput   [EAw-1   :0] src_e_addr;
-\toutput  [DSTPw-1 :0] destport;
-\tinput reset,clk;
-
-	reg [EAw-1   :0] dest_e_addr_delay;
-	reg [EAw-1   :0] src_e_addr_delay;
-
-	 always @ (`pronoc_clk_reset_edge )begin 
-        if(`pronoc_reset) begin 
-			dest_e_addr_delay<={EAw{1'b0}};
-			src_e_addr_delay<={EAw{1'b0}};			
-		end else begin 
-			dest_e_addr_delay<=dest_e_addr;
-			src_e_addr_delay<=src_e_addr;					
-		end 	
-	end
-
-	${name}_look_ahead_routing_genvar_comb  #(
-		.RAw(RAw),  
-		.EAw(EAw),   
-		.DSTPw(DSTPw),
-		.CURRENT_R_ADDR(CURRENT_R_ADDR)  
-	)
-	lkp_cmb
-	(
-		
-		.dest_e_addr(dest_e_addr_delay),
-		.src_e_addr(src_e_addr_delay),
-		.destport(destport)        
-	);
-
-
-	
-endmodule   
- 
 /*******************
-* ${Vname}_look_ahead_routing_genvar_comb
-********************/ 
-  
- 
- module ${Vname}_look_ahead_routing_genvar_comb  #(
-\tparameter RAw = 3,  
-\tparameter EAw = 3,   
-\tparameter DSTPw=4,
-\tparameter CURRENT_R_ADDR=0
-)
-(
-\tdest_e_addr,
-\tsrc_e_addr,
-\tdestport        
+*  ${Vname}_${mode}_routing_comb
+*******************/
+module ${Vname}_${mode}_routing_comb  #(
+    parameter RAw = 3,
+    parameter EAw = 3,
+    parameter DSTPw=4
+)(
+    current_r_addr,
+    dest_e_addr,
+    src_e_addr,
+    destport
 );
-
-\tinput   [EAw-1   :0] dest_e_addr;
-\tinput   [EAw-1   :0] src_e_addr;
-\toutput  reg [DSTPw-1 :0] destport;
+    input   [RAw-1   :0] current_r_addr;
+    input   [EAw-1   :0] dest_e_addr;
+    input   [EAw-1   :0] src_e_addr;
+    output reg [DSTPw-1 :0] destport;
 
 $localparam
-        
-$route_str  
-
-	
-endmodule  
 
+$route_str
 
+endmodule
 ";
 
-
 close($fd);
 add_info($info,"$top file is created\n  ");
-
 }
 
-
-
+##############
+#generate_connection_v
+##############
 sub generate_connection_v{
-	my($self,$info,$dir)=@_;
-	
-	#create connection top file
-	my $name=$self->object_get_attribute('save_as');
-
-	my $r; 
-	my $top="$dir/${name}_connection.sv";
+    my($self,$info,$dir)=@_;
+    #create connection top file
+    my $name=$self->object_get_attribute('save_as');
+    my $r; 
+    my $top="$dir/${name}_connection.sv";
     open my $fd, ">$top" or $r = "$!\n";
     if(defined $r) {
-    	add_colored_info($info,"Error in creating $top: $r",'red');
-		return;
+        add_colored_info($info,"Error in creating $top: $r",'red');
+        return;
     } 
     print $fd autogen_warning();
     print $fd get_license_header($top);   
-print $fd '
+    print $fd '
 `include "pronoc_def.v"
 ';
-
-
-
-   
-  
-
-   my @parameters=@{$self->object_get_attribute ('Verilog','Router_param')};
-   my @ports= @{$self->object_get_attribute('Verilog','Router_ports')}; 
-    
-	
- 
+    my @parameters=@{$self->object_get_attribute ('Verilog','Router_param')};
+    my @ports= @{$self->object_get_attribute('Verilog','Router_ports')}; 
     my @ends=get_list_of_all_endpoints($self);
     my @routers=get_list_of_all_routers($self);
-    
     my $MAX_P=0;
     foreach my $p (@routers){
-    	my $Pnum=$self->object_get_attribute("$p",'PNUM');
-    	$MAX_P =$Pnum  if($Pnum>$MAX_P );    	
-    }	
-
+        my $Pnum=$self->object_get_attribute("$p",'PNUM');
+        $MAX_P =$Pnum  if($Pnum>$MAX_P );
+    }    
     my $NE= scalar @ends;
     my $NR= scalar @routers;
-
-   	
-	
-	my @nodes=get_list_of_all_routers($self);
-	my $i=0;
-	
-	my $ports="\treset,
-\tclk,
-\tstart_i,
-\tstart_o,
-\ter_addr, 
-\tcurrent_r_addr,
-\tchan_in_all,
-\tchan_out_all, 
-\trouter_chan_in,
-\trouter_chan_out  
+    my @nodes=get_list_of_all_routers($self);
+    my $i=0;
+    my $ports="    reset,
+    clk,
+    start_i,
+    start_o,
+    er_addr, 
+    current_r_addr,
+    chan_in_all,
+    chan_out_all, 
+    router_chan_in,
+    router_chan_out  
 ";
 
-
     my $ports_def="
-\tinput reset;
-\tinput clk;
-\tinput start_i;
-\toutput [RAw-1 : 0] er_addr [NE-1 : 0]; // provide router address for each connected endpoint 
-\toutput [RAw-1 : 0] current_r_addr [NR-1 : 0]; // provide each router current address  ;
-\toutput [NE-1 : 0] start_o;
-\toutput smartflit_chanel_t chan_in_all [NE-1 : 0];
-\tinput  smartflit_chanel_t chan_out_all [NE-1 : 0]; 
-\tinput  smartflit_chanel_t    router_chan_in   [NR-1 :0][MAX_P-1 : 0];
-\toutput smartflit_chanel_t    router_chan_out  [NR-1 :0][MAX_P-1 : 0];
+    input reset;
+    input clk;
+    input start_i;
+    output [RAw-1 : 0] er_addr [NE-1 : 0]; // provide router address for each connected endpoint 
+    output [RAw-1 : 0] current_r_addr [NR-1 : 0]; // provide each router current address  ;
+    output [NE-1 : 0] start_o;
+    output smartflit_chanel_t chan_in_all [NE-1 : 0];
+    input  smartflit_chanel_t chan_out_all [NE-1 : 0]; 
+    input  smartflit_chanel_t    router_chan_in   [NR-1 :0][MAX_P-1 : 0];
+    output smartflit_chanel_t    router_chan_out  [NR-1 :0][MAX_P-1 : 0];
 
 ";
-
-	my $router_wires="";
-	my $endps_wires="";
-
-	
-	
-	
-	foreach my $d (@ports){		
-		my $range = ($d->{width} eq 1)? " " :  " [$d->{width}-1 : 0]";	
-		my $pdef_range = ($d->{pwidth} eq 1)? "[NE-1 : 0]" : "[$d->{pwidth}-1 : 0]";
-		my $pdef_range2 = ($d->{pwidth} eq 1)? "" : "[NE-1 : 0]";
-		#$ports=$ports.",\n\trouter_$d->{name},\n\trouter_$d->{connect}";
-		my $type=$d->{type};
-		my $ctype= ($type eq 'input')? 'output' : 'input';
-		if( $d->{endp} eq "yes"){ 	    	 
-			#$ports_def=$ports_def."\t$type\t$pdef_range ni_$d->{pname} $pdef_range2;\n";
-			#$ports_def=$ports_def."\t$ctype\t$pdef_range ni_$d->{pconnect} $pdef_range2;\n";			
-			#$ports=$ports.",\n\tni_$d->{pname},\n\tni_$d->{pconnect}";
-		}	
-		if($d->{width} eq 1){
-			#$ports_def=$ports_def. "\t$type\t[NR-1 :0] router_$d->{name};\n";
-			#$ports_def=$ports_def. "\t$ctype\t[NR-1 :0] router_$d->{connect};\n";
-		}else{	
-			#$ports_def=$ports_def. "\t$type\t$range router_$d->{name} [NR-1 :0];\n";
-			#$ports_def=$ports_def. "\t$ctype\t$range router_$d->{connect} [NR-1 :0];\n";
-		}
-					
-		
-	}	
-	
-	  
-	
-	
-	my $routers='
-	genvar i;
-	generate	
-	';
-	my $offset=0;
-	my $assign="";
-	my $R_num=0;
-	for ( my $i=2;$i<=12; $i++){
-		my $n= $self->object_get_attribute("ROUTER${i}","NUM");
-		$n=0 if(!defined $n);
-		if($n>0){	
-			my $router_pos= ($offset==0)? 'i' : "i+$offset";
-			my $instant=get_router_genvar_instance_v($self,$i,$router_pos,$NE,$NR,$MAX_P);
-					
-			$routers=$routers."
-\tfor( i=0; i<$n; i=i+1) begin : router_${i}_port_lp
-\t\t$instant
+    my $router_wires="";
+    my $endps_wires="";
+    foreach my $d (@ports){        
+        my $range = ($d->{width} eq 1)? " " :  " [$d->{width}-1 : 0]";    
+        my $pdef_range = ($d->{pwidth} eq 1)? "[NE-1 : 0]" : "[$d->{pwidth}-1 : 0]";
+        my $pdef_range2 = ($d->{pwidth} eq 1)? "" : "[NE-1 : 0]";
+        #$ports=$ports.",\n    router_$d->{name},\n    router_$d->{connect}";
+        my $type=$d->{type};
+        my $ctype= ($type eq 'input')? 'output' : 'input';
+        if( $d->{endp} eq "yes"){              
+            #$ports_def=$ports_def."    $type    $pdef_range ni_$d->{pname} $pdef_range2;\n";
+            #$ports_def=$ports_def."    $ctype    $pdef_range ni_$d->{pconnect} $pdef_range2;\n";            
+            #$ports=$ports.",\n    ni_$d->{pname},\n    ni_$d->{pconnect}";
+        }    
+        if($d->{width} eq 1){
+            #$ports_def=$ports_def. "    $type    [NR-1 :0] router_$d->{name};\n";
+            #$ports_def=$ports_def. "    $ctype    [NR-1 :0] router_$d->{connect};\n";
+        }else{    
+            #$ports_def=$ports_def. "    $type    $range router_$d->{name} [NR-1 :0];\n";
+            #$ports_def=$ports_def. "    $ctype    $range router_$d->{connect} [NR-1 :0];\n";
+        }
+    }
+    my $routers='
+    genvar i;
+    generate
+    ';
+    my $offset=0;
+    my $assign="";
+    my $R_num=0;
+    for ( my $i=2;$i<=12; $i++){
+        my $n= $self->object_get_attribute("ROUTER${i}","NUM");
+        $n=0 if(!defined $n);
+        if($n>0){    
+            my $router_pos= ($offset==0)? 'i' : "i+$offset";
+            my $instant=get_router_genvar_instance_v($self,$i,$router_pos,$NE,$NR,$MAX_P);
+            $routers=$routers."
+    for( i=0; i<$n; i=i+1) begin : router_${i}_port_lp
+        $instant
     
-\tend    
-			";
-			
-			for ( my $j=0;$j<$n; $j++){
-				my $rname ="ROUTER${i}_$j";		
-				my ($ass_v, $r2r_h,$r2e_h, $int_h,$gnd_h,$R_num)=	get_wires_assignment_genvar_v($self,$rname,1,undef,$R_num);
-				$assign=$assign.$ass_v;
-			}
-			
-		$offset+=	$n;
-			
-		}	
-	}
-	
-	
-	
-	foreach my $end (@ends){
-		#$assign=$assign.get_wires_assignment_genvar_v($self,$end,1);		
-	}
-	
-	$assign=$assign."\n";
-	
-	
-	my $pos=0;
-	$assign.="//The router address connected to each endpoint\n";
-	foreach my $end (@ends){
-		my $connect = $self->{$end}{'PCONNECT'}{'Port[0]'};
-		my ($Rname,$Rport)=split(/\s*,\s*/,$connect);
-		my $R = get_scolar_pos($Rname,@routers);
-		my $rname = $self->object_get_attribute("$Rname","NAME");
-		my $tname = $self->object_get_attribute("$end","NAME");
-		$assign=$assign."\tassign er_addr [$pos] = $R; //$tname -> $rname\n";  
-		$pos++;   		
-	}
-	
-	$assign=$assign."\n";
-	
-	$pos=0;
-	foreach my $router (@routers){
-		my $rname = $self->object_get_attribute("$router","NAME");
-		$assign=$assign."\tassign current_r_addr [$pos] = $pos; // $rname\n";  
-		$pos++;   		
-	}
-	
-	
-	
-	
-		 print $fd "
+    end    
+            ";
+            for ( my $j=0;$j<$n; $j++){
+                my $rname ="ROUTER${i}_$j";        
+                my ($ass_v, $r2r_h,$r2e_h, $int_h,$gnd_h,$R_num)=    get_wires_assignment_genvar_v($self,$rname,1,undef,$R_num);
+                $assign=$assign.$ass_v;
+            }
+        $offset+= $n;
+        }
+    }
+    foreach my $end (@ends){
+        #$assign=$assign.get_wires_assignment_genvar_v($self,$end,1);        
+    }
+    $assign=$assign."\n";
+    my $pos=0;
+    $assign.="//The router address connected to each endpoint\n";
+    foreach my $end (@ends){
+        my $connect = $self->{$end}{'PCONNECT'}{'Port[0]'};
+        my ($Rname,$Rport)=split(/\s*,\s*/,$connect);
+        my $R = get_scolar_pos($Rname,@routers);
+        my $rname = $self->object_get_attribute("$Rname","NAME");
+        my $tname = $self->object_get_attribute("$end","NAME");
+        $assign=$assign."    assign er_addr [$pos] = $R; //$tname -> $rname\n";  
+        $pos++;
+    }
+    $assign=$assign."\n";
+    $pos=0;
+    foreach my $router (@routers){
+        my $rname = $self->object_get_attribute("$router","NAME");
+        $assign=$assign."    assign current_r_addr [$pos] = $pos; // $rname\n";  
+        $pos++;
+    }
+        print $fd "
 module  ${name}_connection 
-#(
-	parameter NOC_ID=0
-)(
+(
     $ports
 );
-
-	`NOC_CONF
-
-	
-	localparam
-		P= MAX_P,
+    import pronoc_pkg::*;
+    
+    localparam
+        P= MAX_P,
         PV = V * P,
         PFw = P * Fw,
         CONG_ALw = CONGw * P,
         PRAw = P * RAw; 
     
 $ports_def
-
+    
 $router_wires
-
+    
 $endps_wires
-   
-
-$assign   
-
-
-	start_delay_gen #(
+    
+$assign
+    
+    start_delay_gen #(
         .NC(NE)
-    )
-    delay_gen
-    (
+    ) delay_gen (
         .clk(clk),
         .reset(reset),
         .start_i(start_i),
         .start_o(start_o)
     );
- 
-             
 endmodule
 ";
-	
-	add_info($info,"$top file is created\n  ");
-	close $fd;
-	
-				
-	
+    add_info($info,"$top file is created\n  ");
+    close $fd;
 }
 
+##############
+#
+##############
 sub add_noc_custom_h{
-	my ($self,$info,$dir)=@_;
-	my $name=$self->object_get_attribute('save_as');
-	my $str="
-		//do not modify this line ===${name}===
-		#ifdef IS_${name}_noc
-			#include \"${name}_noc.h\"
-		#endif
-	";
-	
-	
-	my $file = "$dir/../../../src_verilator/topology/custom/custom.h";	
-	#check if ***$name**** exist in the file
-	unless (-f $file){
-		add_colored_info($info,"$file dose not exist\n",'red');
-		return; 
-	}	
-	my $r = check_file_has_string($file, "===${name}==="); 
-	if ($r==1){
-		add_info($info,"The instance  ${name}_noc exists in $file. This file is not modified\n  ",'blue');
-	
-	}else{
-		my $text = read_file_cntent($file,' ');
+    my ($self,$info,$dir)=@_;
+    my $name=$self->object_get_attribute('save_as');
+    my $str="
+        //do not modify this line ===${name}===
+        #ifdef IS_${name}_noc
+            #include \"${name}_noc.h\"
+        #endif
+    ";
+    my $file = "$dir/../../../src_verilator/topology/custom/custom.h";    
+    #check if ***$name**** exist in the file
+    unless (-f $file){
+        add_colored_info($info,"$file dose not exist\n",'red');
+        return; 
+    }    
+    my $r = check_file_has_string($file, "===${name}==="); 
+    if ($r==1){
+        add_info($info,"The instance  ${name}_noc exists in $file. This file is not modified\n  ",'blue');
+    }else{
+        my $text = read_file_cntent($file,' ');
         my @a = split('endgenerate',$text);
         save_file($file,"$a[0] $str $a[1]");
         add_info($info,"$file has been modified. The  ${name}_noc has been added to the file\n  ",'blue');
-		
-	}
-	
+    }
 }
 
-
-
 sub add_routing_instance_v{
-	my ($self,$info,$dir)=@_;
-	my $name=$self->object_get_attribute('save_as');
-	my $rname=$self->object_get_attribute('routing_name');
-	my $Vname="T${name}R${rname}";
-	#####################################
-	#			custom_ni_routing
-	####################################
-	my $str="
-	//do not modify this line ===${Vname}===
+    my ($self,$info,$dir)=@_;
+    my $name=$self->object_get_attribute('save_as');
+    my $rname=$self->object_get_attribute('routing_name');
+    my $Vname="T${name}R${rname}";
+    #####################################
+    #            custom_ni_routing
+    ####################################
+    my $str="
+    //do not modify this line ===${Vname}===
+    /* verilator lint_off WIDTH */
     if(TOPOLOGY == \"$name\" && ROUTE_NAME== \"$rname\" ) begin : $Vname
-    
-        ${Vname}_conventional_routing  #(
-           	.RAw(RAw),  
+    /* verilator lint_on WIDTH */
+        ${Vname}_ni_routing  #(
+            .RAw(RAw),  
             .EAw(EAw),   
             .DSTPw(DSTPw)  
-        )
-        the_conventional_routing
-        (
+        )  the_ni_routing  (
             .dest_e_addr(dest_e_addr),
             .src_e_addr(src_e_addr),
-            .destport(destport)        
-        );    
-    
-    end	
-    
+            .destport(destport)
+        );
+    end
     endgenerate
-    	
 ";
-	
-	my $file = "$dir/../common/custom_ni_routing.v";	
-	#check if ***$name**** exist in the file
-	unless (-f $file){
-		add_colored_info($info,"$file dose not exist\n",'red');
-		return; 
-	}	
-	my $r = check_file_has_string($file, "===${Vname}==="); 
-	if ($r==1){
-		add_info($info,"The instance  ${Vname}_conventional_routing exists in $file. This file is not modified\n  ",'blue');
-	
-	}else{
-		my $text = read_file_cntent($file,' ');
+    
+    my $file = "$dir/../common/custom_ni_routing.v";
+    #check if ***$name**** exist in the file
+    unless (-f $file){
+        add_colored_info($info,"$file dose not exist\n",'red');
+        return; 
+    }    
+    my $r = check_file_has_string($file, "===${Vname}==="); 
+    if ($r==1){
+        add_info($info,"The instance  ${Vname}_ni_routing exists in $file. This file is not modified\n  ",'blue');
+    
+    }else{
+        my $text = read_file_cntent($file,' ');
         my @a = split('endgenerate',$text);
         save_file($file,"$a[0] $str $a[1]");
-        add_info($info,"$file has been modified. The  ${Vname}_conventional_routing has been added to the file\n  ",'blue');
-		
-	}
-	
-	
-	
-	#####################################
-	#			custom_lkh_routing
-	####################################
-	 $str="
-	//do not modify this line ===${Vname}===
+        add_info($info,"$file has been modified. The  ${Vname}_ni_routing has been added to the file\n  ",'blue');
+    }
+    #####################################
+    #            custom_lkh_routing
+    ####################################
+    $str="
+    //do not modify this line ===${Vname}===
+    /* verilator lint_off WIDTH */
     if(TOPOLOGY == \"$name\" && ROUTE_NAME== \"$rname\" ) begin : ${Vname}
-     
-	   ${Vname}_look_ahead_routing  #(
+    /* verilator lint_on WIDTH */
+        ${Vname}_look_ahead_routing  #(
             .RAw(RAw),  
             .EAw(EAw),   
             .DSTPw(DSTPw)  
-        )
-        the_lkh_routing
-        (
+        ) the_lkh_routing (
             .current_r_addr(current_r_addr),
             .dest_e_addr(dest_e_addr),
             .src_e_addr(src_e_addr),
             .destport(destport),
             .reset(reset),
-            .clk(clk)        
-        );    
-    
-    end	
-    
+            .clk(clk)
+        );
+    end
     endgenerate
-    	
 ";
-	
-	$file = "$dir/../common/custom_lkh_routing.v";	
-
-	unless (-f $file){
-		add_colored_info($info,"$file dose not exist\n",'red');
-		return; 
-	}	
-	$r = check_file_has_string($file, "===${Vname}==="); 
-	if ($r==1){
-		add_info($info,"The instance ${Vname}_look_ahead_routing exist in $file. This file is not modified\n  ",'blue');
-	
-	}else{
-		my $text = read_file_cntent($file,' ');
+    $file = "$dir/../common/custom_lkh_routing.v";    
+    unless (-f $file){
+        add_colored_info($info,"$file dose not exist\n",'red');
+        return; 
+    }    
+    $r = check_file_has_string($file, "===${Vname}==="); 
+    if ($r==1){
+        add_info($info,"The instance ${Vname}_look_ahead_routing exist in $file. This file is not modified\n  ",'blue');
+    
+    }else{
+        my $text = read_file_cntent($file,' ');
         my @a = split('endgenerate',$text);
-        save_file($file,"$a[0] $str $a[1]");	
+        save_file($file,"$a[0] $str $a[1]");    
         add_info($info,"$file has been modified. The  ${Vname}_look_ahead_routing has been added to the file\n  ",'blue');
-				
-	}
-	
-
+    }
+    #####################################
+    #            custom_conv_routing
+    ####################################
+    $str="
+    //do not modify this line ===${Vname}===
+    /* verilator lint_off WIDTH */
+    if(TOPOLOGY == \"$name\" && ROUTE_NAME== \"$rname\" ) begin : ${Vname}
+    /* verilator lint_on WIDTH */
+        ${Vname}_conv_routing_comb  #(
+            .RAw(RAw),
+            .EAw(EAw),
+            .DSTPw(DSTPw)
+        ) the_routing (
+            .current_r_addr(current_r_addr),
+            .dest_e_addr(dest_e_addr),
+            .src_e_addr(src_e_addr),
+            .destport(destport)
+        );
+    end
+    endgenerate
+";
+    $file = "$dir/../common/custom_conv_routing.v";
+    unless (-f $file){
+        add_colored_info($info,"$file dose not exist\n",'red');
+        return; 
+    }    
+    $r = check_file_has_string($file, "===${Vname}==="); 
+    if ($r==1){
+        add_info($info,"The instance ${Vname}_conv_routing exist in $file. This file is not modified\n  ",'blue');
+    
+    }else{
+        my $text = read_file_cntent($file,' ');
+        my @a = split('endgenerate',$text);
+        save_file($file,"$a[0] $str $a[1]");
+        add_info($info,"$file has been modified. The  ${Vname}_conv_routing has been added to the file\n  ",'blue');
+    }
 }
 
 sub add_noc_instance_v{
-	my ($self,$info,$dir)=@_;
-	my $name=$self->object_get_attribute('save_as');
-	
-	#####################################
-	#			add connection
-	####################################
-	
-	my $ports="\t\t.reset(reset),
-\t\t.clk(clk),
-\t\t.start_i(start_i),
-\t\t.start_o(start_o),
-\t\t.er_addr(er_addr), 
-\t\t.current_r_addr(current_r_addr),
-\t\t.chan_in_all(chan_in_all),
-\t\t.chan_out_all(chan_out_all), 
-\t\t.router_chan_in(router_chan_in),
-\t\t.router_chan_out(router_chan_out)  
-
-
+    my ($self,$info,$dir)=@_;
+    my $name=$self->object_get_attribute('save_as');
+    #####################################
+    #            add connection
+    ####################################
+    my $ports="        .reset(reset),
+        .clk(clk),
+        .start_i(start_i),
+        .start_o(start_o),
+        .er_addr(er_addr), 
+        .current_r_addr(current_r_addr),
+        .chan_in_all(chan_in_all),
+        .chan_out_all(chan_out_all), 
+        .router_chan_in(router_chan_in),
+        .router_chan_out(router_chan_out)
 ";
-	
-	
-
-	
-	my $str="
-	//do not modify this line ===${name}===
+    my $str="
+    //do not modify this line ===${name}===
+    /* verilator lint_off WIDTH */
     if(TOPOLOGY == \"$name\" ) begin : T$name
-    
-        ${name}_connection  #(
-			.NOC_ID(NOC_ID)
-		) connection (
-$ports     
-        );    
-    
-    end	
-    
+    /* verilator lint_on WIDTH */
+        ${name}_connection  connection (
+$ports
+        );
+    end
     endgenerate
-    	
 ";
-	
-	#my $file = "$dir/../common/custom_noc_connection.sv";	
-	#check if ***$name**** exist in the file
-	#unless (-f $file){
-	#	add_colored_info($info,"$file dose not exist\n",'red');
-	#	return; 
-	#}	
-	#my $r = check_file_has_string($file, "===${name}==="); 
-	#if ($r==1){
-		#add_info($info,"The instance  ${name}_connection exists in $file. This file is not modified\n  ",'blue');
-	
-	#}else{
-		#my $text = read_file_cntent($file,' ');
-       # my @a = split('endgenerate',$text);
-      #  save_file($file,"$a[0] $str $a[1]");
-       # add_info($info,"$file has been modified. The  ${name}_connection has been added to the file\n  ",'blue');
-			
-	#}
-	
-	
-	#####################################
-	#		add NoC 
-	####################################
-	
-	
-	 my $param_str ="\t\t.TOPOLOGY(TOPOLOGY),
-\t\t.ROUTE_NAME(ROUTE_NAME)";
-
-   my @parameters=@{$self->object_get_attribute ('Verilog','Router_param')};
-      
-	foreach my $d (@parameters){
-		$param_str = $param_str.",\n\t\t.$d->{param_name}($d->{param_name})";
-	}
-	
-	$ports="\t\t.reset(reset),
-\t\t.clk(clk)";
-		
-	
-	$str="
-	//do not modify this line ===${name}===
-    if(TOPOLOGY == \"$name\" ) begin : T$name
+    #####################################
+    #        add NoC 
+    ####################################
+    my $param_str ="        .TOPOLOGY(TOPOLOGY),
+        .ROUTE_NAME(ROUTE_NAME)";
+    my @parameters=@{$self->object_get_attribute ('Verilog','Router_param')};
+    foreach my $d (@parameters){
+        $param_str = $param_str.",\n        .$d->{param_name}($d->{param_name})";
+    }
+    $ports="        .reset(reset),
+        .clk(clk)";
     
-		${name}_noc_genvar #(
-			.NOC_ID(NOC_ID)
-		) the_noc (	
-		    .reset(reset),
-		    .clk(clk),    
-		    .chan_in_all(chan_in_all),
-		    .chan_out_all(chan_out_all),
-		    .router_event(router_event)  
-		);
+    $str="
+    //do not modify this line ===${name}===
+    /* verilator lint_off WIDTH */
+    if(TOPOLOGY == \"$name\" ) begin : T$name
+    /* verilator lint_on WIDTH */
+        ${name}_noc_genvar the_noc (
+            .reset(reset),
+            .clk(clk),
+            .chan_in_all(chan_in_all),
+            .chan_out_all(chan_out_all),
+            .router_event(router_event)
+        );
     end
-    
     endgenerate
-	
-	";
-	
-	
-	
-	my $file = "$dir/../common/custom_noc_top.sv";	
-	#check if ***$name**** exist in the file
-	unless (-f $file){
-		add_colored_info($info,"$file dose not exist\n",'red');
-		return; 
-	}	
-	my $r = check_file_has_string($file, "===${name}==="); 
-	if ($r==1){
-		add_info($info,"The instance  ${name}_noc exists in $file. This file is not modified\n  ",'blue');
-	
-	}else{
-		my $text = read_file_cntent($file,' ');
+";
+
+    my $file = "$dir/../common/custom_noc_top.sv";
+    #check if ***$name**** exist in the file
+    unless (-f $file){
+        add_colored_info($info,"$file dose not exist\n",'red');
+        return; 
+    }    
+    my $r = check_file_has_string($file, "===${name}==="); 
+    if ($r==1){
+        add_info($info,"The instance  ${name}_noc exists in $file. This file is not modified\n  ",'blue');
+    
+    }else{
+        my $text = read_file_cntent($file,' ');
         my @a = split('endgenerate',$text);
         save_file($file,"$a[0] $str $a[1]");
-        add_info($info,"$file has been modified. The  ${name}_noc has been added to the file\n  ",'blue');			
-	}
-	
-	
-	
-	
-	
-	
-	
-	
-	
-	
-		
+        add_info($info,"$file has been modified. The  ${name}_noc has been added to the file\n  ",'blue');            
+    }
 }
-
-
 1
diff --git a/mpsoc/perl_gui/lib/perl/trace_gen.pl b/mpsoc/perl_gui/lib/perl/trace_gen.pl
index e90f818..cd42698 100644
--- a/mpsoc/perl_gui/lib/perl/trace_gen.pl
+++ b/mpsoc/perl_gui/lib/perl/trace_gen.pl
@@ -21,16 +21,16 @@
 require "drag_drop.pl";
 
 __PACKAGE__->mk_accessors(qw{
-	window
-	sourceview
-	buffer
-	filename
-	search_regexp
-	search_case
-	search_entry
-	regexp
-	highlighted
-	
+    window
+    sourceview
+    buffer
+    filename
+    search_regexp
+    search_case
+    search_entry
+    regexp
+    highlighted
+    
 });
 
 my $NAME = 'Trace_gen';
@@ -38,2097 +38,1552 @@
 
 exit trace_gen_main() unless caller;
 
-
 sub trace_gen_main {
-	my ($mode,$ref,$w)=@_;
-	my $app = __PACKAGE__->new();
-	my $table=$app->build_trace_gui($mode,$ref,$w);
-		
-	return $table;
+    my ($mode,$ref,$w)=@_;
+    my $app = __PACKAGE__->new();
+    my $table=$app->build_trace_gui($mode,$ref,$w);
+    return $table;
 }
 
 
-
 ########
 #  trace_ctr
 ########
-
 sub trace_pad_ctrl{
-	my ($self,$tview,$mode)=@_;
-		
-	my $table= def_table(2,10,FALSE);
-	
-	my $row=0;
-	my $col=0;
-	#$table->attach ($separator , 0, 10 , $row, $row+1,'fill','fill',2,2);	$row++;	
-	
-	my $add = def_image_button('icons/import.png');
-	set_tip($add,'Load Task Graph') if($mode eq "task");
-	set_tip($add,'Load ORCC source files') if($mode eq "orcc");
-	my $remove = def_image_button('icons/cancel.png');
-	set_tip($remove,'Remove Selected Trace(s)');
-	my $draw = def_image_button('icons/diagram.png');
-	set_tip($draw,'View Task Graph');
-	my $auto = def_image_button('icons/refresh.png');
-	set_tip($auto,'Automatically calculate the traces burst size and injection ratio according to their bandwidth');
-	my $box=def_pack_hbox(FALSE,FALSE,$add,$draw,$remove,$auto);
-	
-	#my $auto = def_image_button('icons/setting.png');
-	#set_tip($auto,'Automatically set the burst size and injection ratio according to the packet size and bandwidth');
-	
-	
-	$col=0;
-	$table->attach ($box,$col, $col+1,  $row, $row+1,'shrink','shrink',2,2);$col++;
-	
-	$row++;	
-	$col=0;
-	my $info="Automatically set the burst size and injection ratio according to the packet size and bandwidth";
-	#add_param_widget($self,"Auto inject rate \& burst size",'Auto_inject', 0,"Check-box",1,$info, $table,$row,$col,1,'Auto',0,'ref',"vertical");
-	$row++;	
-	$col=0;	
-	my $info1="If hard-build QoS is enabled in NoC by using Weighted round robin arbiter (WRRA) instead of RRA, then the initial weights allow QoS support in NoC as in presence of contention, packets with higher initial weights receive higher bandwidth and lower worst case delay compared to others." ;
-	
-	#my $selects="tornado,transposed 1,transposed 2,bit reverse,bit complement,random,hot spot"; 
-	my $min=$self->object_get_attribute('select_multiple','min_pck_size');
-	my $max=$self->object_get_attribute('select_multiple','max_pck_size');	
-	$min=$max=5 if(!defined $min);
-	
-	my @selectedinfo;
-	$self->object_add_attribute('Auto','Auto_inject',"1\'b0" );
-	my $a= $self->object_get_attribute('Auto','Auto_inject');
-	
-	if ($a eq "1\'b0"){
-		@selectedinfo = (
-		{ label=>" Initial weight ", param_name=>'init_weight', type=>'Spin-button', default_val=>1, content=>"1,16,1", info=>$info1, param_parent=>'select_multiple', ref_delay=> undef, new_status=>undef},
-		{ label=>" Min pck size ", param_name=>'min_pck_size', type=>'Spin-button', default_val=>5, content=>"2,$max,1", info=>undef, param_parent=>'select_multiple', ref_delay=> 10, new_status=>'ref'},
-		{ label=>" Max pck size ",param_name=>'max_pck_size', type=>'Spin-button', default_val=>5, content=>"$min,1024,1", info=>undef, param_parent=>'select_multiple', ref_delay=> 10, new_status=>'ref'},
-		{ label=>" Burst_size ", param_name=>'burst_size', type=>'Spin-button', default_val=>1, content=>"1,1024,1", info=>undef, param_parent=>'select_multiple', ref_delay=> undef, new_status=>undef},
-		{ label=>" Inject rate(%) ", param_name=>'injct_rate', type=>'Spin-button', default_val=>10, content=>"1,100,1", info=>undef, param_parent=>'select_multiple', ref_delay=> undef, new_status=>undef},
-		{ label=>" Inject rate variation(%) ", param_name=>'injct_rate_var', type=>'Spin-button', default_val=>20, content=>"0,100,1", info=>undef, param_parent=>'select_multiple', ref_delay=> undef, new_status=>undef},
-
-	);
-		
-		
-	}else{
-		@selectedinfo = (
-		{ label=>" Initial weight ", param_name=>'init_weight', type=>'Spin-button', default_val=>1, content=>"1,16,1", info=>undef, param_parent=>'select_multiple', ref_delay=> undef, new_status=>undef},
-		{ label=>" Min pck size ", param_name=>'min_pck_size', type=>'Spin-button', default_val=>5, content=>"2,$max,1", info=>undef, param_parent=>'select_multiple', ref_delay=> 10, new_status=>'ref'},
-		{ label=>" Max pck size ",param_name=>'max_pck_size', type=>'Spin-button', default_val=>5, content=>"$min,1024,1", info=>undef, param_parent=>'select_multiple', ref_delay=> 10, new_status=>'ref'},
-		
-	);
-	}
-	if($mode eq "orcc"){
-		my $v_val= $self->object_get_attribute('noc_param','V');
-		my $v_max=$v_val-1;	
-		my $c_val= $self->object_get_attribute('noc_param','C');
-		my $c_max=($c_val==0)? 0 : $c_val-1;	
-	 
-	 	@selectedinfo = (
-	 	{ label=>" Initial weight ", param_name=>'init_weight', type=>'Spin-button', default_val=>1, content=>"1,16,1", info=>undef, param_parent=>'select_multiple', ref_delay=> undef, new_status=>undef},
-	 	{ label=>" Virtual chanel#", param_name=>'vc', type=>'Spin-button', default_val=>0, content=>"0,$v_max,1", info=>undef, param_parent=>'select_multiple', ref_delay=> undef, new_status=>undef},
-	 	{ label=>" Message class# ", param_name=>'class', type=>'Spin-button', default_val=>0, content=>"0,$c_max,1", info=>undef, param_parent=>'select_multiple', ref_delay=> undef, new_status=>undef}
-	 	);
-		
-	}
-	
-	
-	my @traces= get_trace_list($self,'raw');
-	my $any_selected=0;
-	foreach my $p (@traces) {	
-		my ($src,$dst, $Mbytes, $file_id, $file_name)=get_trace($self,'raw',$p);
-		$any_selected=1 if($self->object_get_attribute("raw_$p",'selected')==1); 
-	
-	}	
-	
-	if($any_selected){
+    my ($self,$tview,$mode)=@_;
+    my $table= def_table(2,10,FALSE);
+    my $row=0;
+    my $col=0;
+    #$table->attach ($separator , 0, 10 , $row, $row+1,'fill','fill',2,2);    $row++;    
+    my $add = def_image_button('icons/import.png');
+    set_tip($add,'Load Task Graph') if($mode eq "task");
+    set_tip($add,'Load ORCC source files') if($mode eq "orcc");
+    my $remove = def_image_button('icons/cancel.png');
+    set_tip($remove,'Remove Selected Trace(s)');
+    my $draw = def_image_button('icons/diagram.png');
+    set_tip($draw,'View Task Graph');
+    my $auto = def_image_button('icons/refresh.png');
+    set_tip($auto,'Automatically calculate the traces burst size and injection ratio according to their bandwidth');
+    my $box=def_pack_hbox(FALSE,FALSE,$add,$draw,$remove,$auto);
+    #my $auto = def_image_button('icons/setting.png');
+    #set_tip($auto,'Automatically set the burst size and injection ratio according to the packet size and bandwidth');
+    $col=0;
+    $table->attach ($box,$col, $col+1,  $row, $row+1,'shrink','shrink',2,2);$col++;
+    $row++;    
+    $col=0;
+    my $info="Automatically set the burst size and injection ratio according to the packet size and bandwidth";
+    #add_param_widget($self,"Auto inject rate \& burst size",'Auto_inject', 0,"Check-box",1,$info, $table,$row,$col,1,'Auto',0,'ref',"vertical");
+    $row++;    
+    $col=0;    
+    my $info1="If hard-build QoS is enabled in NoC by using Weighted round robin arbiter (WRRA) instead of RRA, then the initial weights allow QoS support in NoC as in presence of contention, packets with higher initial weights receive higher bandwidth and lower worst case delay compared to others." ;
+    #my $selects="tornado,transposed 1,transposed 2,bit reverse,bit complement,random,hot spot"; 
+    my $min=$self->object_get_attribute('select_multiple','min_pck_size');
+    my $max=$self->object_get_attribute('select_multiple','max_pck_size');    
+    $min=$max=5 if(!defined $min);
+    my @selectedinfo;
+    $self->object_add_attribute('Auto','Auto_inject',"1\'b0" );
+    my $a= $self->object_get_attribute('Auto','Auto_inject');
+    if ($a eq "1\'b0"){
+        @selectedinfo = (
+        { label=>" Initial weight ", param_name=>'init_weight', type=>'Spin-button', default_val=>1, content=>"1,16,1", info=>$info1, param_parent=>'select_multiple', ref_delay=> undef, new_status=>undef},
+        { label=>" Min pck size ", param_name=>'min_pck_size', type=>'Spin-button', default_val=>5, content=>"2,$max,1", info=>undef, param_parent=>'select_multiple', ref_delay=> 10, new_status=>'ref'},
+        { label=>" Max pck size ",param_name=>'max_pck_size', type=>'Spin-button', default_val=>5, content=>"$min,1024,1", info=>undef, param_parent=>'select_multiple', ref_delay=> 10, new_status=>'ref'},
+        { label=>" Burst_size ", param_name=>'burst_size', type=>'Spin-button', default_val=>1, content=>"1,1024,1", info=>undef, param_parent=>'select_multiple', ref_delay=> undef, new_status=>undef},
+        { label=>" Inject rate(%) ", param_name=>'injct_rate', type=>'Spin-button', default_val=>10, content=>"1,100,1", info=>undef, param_parent=>'select_multiple', ref_delay=> undef, new_status=>undef},
+        { label=>" Inject rate variation(%) ", param_name=>'injct_rate_var', type=>'Spin-button', default_val=>20, content=>"0,100,1", info=>undef, param_parent=>'select_multiple', ref_delay=> undef, new_status=>undef},
+    );
+    }else{
+        @selectedinfo = (
+        { label=>" Initial weight ", param_name=>'init_weight', type=>'Spin-button', default_val=>1, content=>"1,16,1", info=>undef, param_parent=>'select_multiple', ref_delay=> undef, new_status=>undef},
+        { label=>" Min pck size ", param_name=>'min_pck_size', type=>'Spin-button', default_val=>5, content=>"2,$max,1", info=>undef, param_parent=>'select_multiple', ref_delay=> 10, new_status=>'ref'},
+        { label=>" Max pck size ",param_name=>'max_pck_size', type=>'Spin-button', default_val=>5, content=>"$min,1024,1", info=>undef, param_parent=>'select_multiple', ref_delay=> 10, new_status=>'ref'},
+    );
+    }
+    if($mode eq "orcc"){
+        my $v_val= $self->object_get_attribute('noc_param','V');
+        my $v_max=$v_val-1;    
+        my $c_val= $self->object_get_attribute('noc_param','C');
+        my $c_max=($c_val==0)? 0 : $c_val-1;    
+        @selectedinfo = (
+        { label=>" Initial weight ", param_name=>'init_weight', type=>'Spin-button', default_val=>1, content=>"1,16,1", info=>undef, param_parent=>'select_multiple', ref_delay=> undef, new_status=>undef},
+        { label=>" Virtual chanel#", param_name=>'vc', type=>'Spin-button', default_val=>0, content=>"0,$v_max,1", info=>undef, param_parent=>'select_multiple', ref_delay=> undef, new_status=>undef},
+        { label=>" Message class# ", param_name=>'class', type=>'Spin-button', default_val=>0, content=>"0,$c_max,1", info=>undef, param_parent=>'select_multiple', ref_delay=> undef, new_status=>undef}
+        );
+    }
+    my @traces= get_trace_list($self,'raw');
+    my $any_selected=0;
+    foreach my $p (@traces) {    
+        my ($src,$dst, $Mbytes, $file_id, $file_name)=get_trace($self,'raw',$p);
+        $any_selected=1 if($self->object_get_attribute("raw_$p",'selected')==1); 
+    }    
+    
+    if($any_selected){
         add_Hsep_to_table($table,0, 10,  $row);$row++;
-		$table->attach (gen_label_in_center('Apply to all selected traces'),0, 10,  $row, $row+1,'fill','fill',2,2);$row++;	
-	}
-	
-	foreach my $d (@selectedinfo) {
-		my $apply= def_image_button("icons/enter.png",undef);
-		$apply->signal_connect( 'clicked'=> sub{
-			$self->object_add_attribute('select_multiple','action',$d->{param_name});
-			$self->set_gui_status('ref',0);
-		});
-		if($any_selected){
-			($row,$col)=add_param_widget ($self, $d->{label}, $d->{param_name}, $d->{default_val}, $d->{type}, $d->{content}, $d->{info}, $table,$row,$col,1, $d->{param_parent}, $d->{ref_delay},$d->{new_status},"horizontal");
-			$table->attach  ($apply , $col, $col+1,  $row,$row+1,'shrink','shrink',2,2);$row++;$col=0;
-		#	$row=noc_param_widget ($self, $d->{label}, $d->{param_name}, $d->{default_val}, $d->{type}, $d->{content}, $d->{info}, $table,$row,1, $d->{param_parent}, $d->{ref_delay}, $d->{new_status});
-		}
-		}
-	
-	
-	
-	
-			
-	
-	my $project_dir	  = get_project_dir()."/mpsoc/";
-	
-	
-	$add->signal_connect ( 'clicked'=> sub{
-		load_task_file($self,$project_dir,$tview) if($mode eq 'task');
- 		load_orcc_file($self,$tview) if($mode eq 'orcc');
-	});
-	
-	$draw->signal_connect ( 'clicked'=> sub{
-		show_trace_diagram($self,'trace');
-	});
-	
-	$remove->signal_connect ( 'clicked'=> sub{
-		$self->remove_selected_traces('raw');
-	});
-	
-	$auto->signal_connect ( 'clicked'=> sub{
-		$self->auto_generate_injtratio('raw');
-	});
-	
-	
-	my $sc_win = add_widget_to_scrolled_win($table);
-	
-	
-	return $sc_win;
-	
+        $table->attach (gen_label_in_center('Apply to all selected traces'),0, 10,  $row, $row+1,'fill','fill',2,2);$row++;    
+    }
+    
+    foreach my $d (@selectedinfo) {
+        my $apply= def_image_button("icons/enter.png",undef);
+        $apply->signal_connect( 'clicked'=> sub{
+            $self->object_add_attribute('select_multiple','action',$d->{param_name});
+            $self->set_gui_status('ref',0);
+        });
+        if($any_selected){
+            ($row,$col)=add_param_widget ($self, $d->{label}, $d->{param_name}, $d->{default_val}, $d->{type}, $d->{content}, $d->{info}, $table,$row,$col,1, $d->{param_parent}, $d->{ref_delay},$d->{new_status},"horizontal");
+            $table->attach  ($apply , $col, $col+1,  $row,$row+1,'shrink','shrink',2,2);$row++;$col=0;
+        #    $row=noc_param_widget ($self, $d->{label}, $d->{param_name}, $d->{default_val}, $d->{type}, $d->{content}, $d->{info}, $table,$row,1, $d->{param_parent}, $d->{ref_delay}, $d->{new_status});
+        }
+    }
+    
+    my $project_dir      = get_project_dir()."/mpsoc/";
+    $add->signal_connect ( 'clicked'=> sub{
+        load_task_file($self,$project_dir,$tview) if($mode eq 'task');
+        load_orcc_file($self,$tview) if($mode eq 'orcc');
+    });
+    
+    $draw->signal_connect ( 'clicked'=> sub{
+        show_trace_diagram($self,'trace');
+    });
+    
+    $remove->signal_connect ( 'clicked'=> sub{
+        $self->remove_selected_traces('raw');
+    });
+    
+    $auto->signal_connect ( 'clicked'=> sub{
+        $self->auto_generate_injtratio('raw');
+    });
+    my $sc_win = add_widget_to_scrolled_win($table);
+    return $sc_win;
 }
 
 sub load_task_file{
-	my($self,$project_dir,$tview)=@_;
-	my $file;
-	my $dialog = gen_file_dialog(undef,'app');
-	my $open_in	  = abs_path("${project_dir}/perl_gui/lib/simulate/embedded_app_graphs");
-	$dialog->set_current_folder ($open_in); 
-	if ( "ok" eq $dialog->run ) {
-		$file = $dialog->get_filename;
-		$self->load_tarce_file($file,$tview);
-	}
-	$dialog->destroy;	
+    my($self,$project_dir,$tview)=@_;
+    my $file;
+    my $dialog = gen_file_dialog(undef,'app');
+    my $open_in      = abs_path("${project_dir}/perl_gui/lib/simulate/embedded_app_graphs");
+    $dialog->set_current_folder ($open_in); 
+    if ( "ok" eq $dialog->run ) {
+        $file = $dialog->get_filename;
+        $self->load_tarce_file($file,$tview);
+    }
+    $dialog->destroy;    
 }
 
 ######
 # map_ctr
-######	
-	
+######    
 sub trace_map_ctrl{
-	
-	my ($self,$tview,$mode,$NE)=@_;
-	my $table= def_table(2,10,FALSE);
-	
-	my $run_map= def_image_button("icons/enter.png",undef);
-	my $drawmap = def_image_button('icons/trace.png');
-	my $diagram = def_image_button('icons/diagram.png');
-	set_tip($drawmap,'View actor Mapping Diagram') if($mode eq 'orcc');
-	set_tip($drawmap,'View Task Mapping Diagram') if($mode eq 'task');
-	set_tip($diagram,'View Topology Diagram') if($mode eq 'task');
-	set_tip($diagram,'View actor connection Diagram') if($mode eq 'orcc');
-	
-	my $auto = def_image_button('icons/refresh.png');
-	set_tip($auto,'Automatically set the network dimensions according to the task number');	
-	my $clean = def_image_button('icons/clear.png');
-	set_tip($clean,'Remove mapping');	
-	
-	my $box;
-	$box=def_pack_hbox(FALSE,FALSE,$drawmap,$diagram,$clean,$auto) if($mode eq 'task');
-	$box=def_pack_hbox(FALSE,FALSE,$drawmap,$diagram,$clean) if($mode eq 'orcc');	
-	
-	my $col=0;
-	my $row=0;
-	$table->attach ($box,$col, $col+1,  $row, $row+1,'shrink','shrink',2,2);$row++;	
-	
-	
-	if($mode eq 'task'){
-		($row,$col) =noc_topology_setting_gui($self,$table,$tview,$row,1,"");
-		
-		$diagram-> signal_connect("clicked" => sub{ 
-        	show_topology_diagram ($self) ;
-    	});
-		
-		
-	}
-	
-	if($mode eq 'orcc'){
-			
-		$diagram-> signal_connect("clicked" => sub{ 
-        	
-        	show_trace_diagram ($self,'merge-actor');
-    	});
-		
-		
-	}
-	
-	#my $credit =$self->object_get_attribute('map_param',"credit_en");
-	#if(defined $credit){
-	#	if($credit eq '1\'b0'){
-	#	$self->object_add_attribute('map_param',"receive_int",'1\'b0'); 
-	#}}
-	
-	
-	
-	my @info = ($mode eq 'task')? (
-  	{ label=>"Mapping Algorithm", param_name=>"Map_Algrm", type=>"Combo-box", default_val=>'Random', content=>"Nmap,Random,Reverse-NMAP,Direct", info=>undef, param_parent=>'map_param',ref_delay=>undef,placement=>'horizontal'},
-	) :
-	
-	(	
-	{ label=>"Mapping Algorithm", param_name=>"Map_Algrm", type=>"Combo-box", default_val=>'Random', content=>"Nmap,Random,Reverse-NMAP,Direct", info=>undef, param_parent=>'map_param',ref_delay=>undef,placement=>'horizontal'},
-	{ label=>"ORCC FIFO Debug", param_name=>"add_debug", type=>"Check-box", default_val=>'1\'b0', content=>1, info=>"Add Actor FIFO debugging code to generated C codes to make sure FIFOs handshakings signals are handeled correctly between the source and destination cores", param_parent=>'map_param',ref_delay=>undef,placement=>'vertical'},
-	{ label=>"Sent packet interrupt", param_name=>"sent_int", type=>"Check-box", default_val=>'1\'b1', content=>1, info=>"If the sent inttrupt is enabled, once a packet is completely sent out from the NI, the cpu is informed by intrrupt.", param_parent=>'map_param',ref_delay=>undef,placement=>'vertical'},
-	{ label=>"Receive packet interrupt", param_name=>"receive_int", type=>"Check-box", default_val=>'1\'b1', content=>1, info=>"This flag enables receive-interrupt. Hence, the CPU can collect the received packet immediately from the NI. This interrupt avoids the NoC to be blocked by long packets.", param_parent=>'map_param',ref_delay=>1,placement=>'vertical'},
-	{ label=>"Got NI error interrupt", param_name=>"got_err_int", type=>"Check-box", default_val=>'1\'b1', content=>1, info=>"Enable the inttrupt once any of NI error flags is asserted.", param_parent=>'map_param',ref_delay=>undef,placement=>'vertical'},
-	#{ label=>"ORCC FIFO Credit", param_name=>"credit_en", type=>"Check-box", default_val=>'1\'b1', content=>1, info=>"If this flag is enabled, the credit availbility of destination FIFOs are transfered to source FIFOs. The source FIFOs adapts the sent data size with the available space in destination FIFO. This makes sure the destination FIFO can collet whole of the packet and perevent the NoC resources to be blocked by long packets", param_parent=>'map_param',ref_delay=>1,placement=>'vertical'},
-	);
-	
-	#push(@info,{ label=>"Recieve FIFO extra space (%)", param_name=>"rsv_extra", type=>"Spin-button",content=>"1,100,1", default_val=>10, info=>"If ORCC FIFO Credit flag is not enabled, additional space is added to receive FIFOs to avoid FIFO overflow. The receiver FIFO only collects the NI's incoming packet if its occupied size is smaller than this additional space. This memory overhead could be avoided if the packet size is added to the header pre-captured data. However, it is not yet supported.", param_parent=>'map_param',ref_delay=>1,placement=>'vertical'},
-	#) if($credit eq '1\'b0');
-	
-	foreach my $d (@info) {
-		($row,$col)=add_param_widget ($self, $d->{label}, $d->{param_name}, $d->{default_val}, $d->{type}, $d->{content}, $d->{info}, $table,$row,$col,1, $d->{param_parent}, $d->{ref_delay},'ref',$d->{placement});
-		if($d->{param_name} eq "Map_Algrm"){
-			$table->attach  ($run_map , $col, $col+1,  $row,$row+1,'shrink','shrink',2,2);$row++;$col=0;
-			$table->attach  (gen_label_in_center  ("Enable/Disable flags:") , $col, $col+1,  $row,$row+1,'shrink','shrink',2,2);$row++;$col=0;
-		}
-	}
-
-	
-	
-	$run_map->signal_connect( 'clicked'=> sub{
-		my $alg=$self->object_get_attribute('map_param','Map_Algrm');
-		update_merge_actor_list($self,$tview);
-		$self->random_map() if ($alg eq 'Random');
-		$self->worst_map_algorithm() if ($alg eq 'Reverse-NMAP');		
-		$self->nmap_algorithm() if ($alg eq 'Nmap');
-		$self->direct_map() if ($alg eq 'Direct');
-		
-	
-	});
-	
-	$drawmap->signal_connect ( 'clicked'=> sub{
-		show_trace_diagram($self,'map');
-	});
-	
-	$auto->signal_connect ( 'clicked'=> sub{
-		my @tasks = $self->get_all_merged_tasks();
-		my $task_num= scalar @tasks;
-		return if($task_num ==0);
-		my $topology = $self->object_get_attribute('noc_param','TOPOLOGY');
-		if ($topology eq '"MESH"' || $topology eq '"TORUS"' ){
-			my ($nx,$ny) =network_dim_cal($task_num);
-			$self->object_add_attribute('noc_param','T1',$nx);
-			$self->object_add_attribute('noc_param','T2',$ny);	
-			$self->object_add_attribute('noc_param','T3',1);	
-			set_gui_status($self,"ref",1);
-		}elsif ($topology eq '"RING"' || $topology eq '"LINE"'){
-			$self->object_add_attribute('noc_param','T1',$task_num);
-			$self->object_add_attribute('noc_param','T2',1);
-			$self->object_add_attribute('noc_param','T3',1);
-			set_gui_status($self,"ref",1);			
-		}
-	});
-	
-	$clean->signal_connect ( 'clicked'=> sub{
-		remove_mapping($self);
-		set_gui_status($self,"ref",1);	
-	});
-	
-	return add_widget_to_scrolled_win($table);
-	
-	
+    my ($self,$tview,$mode,$NE)=@_;
+    my $table= def_table(2,10,FALSE);
+    my $run_map= def_image_button("icons/enter.png",undef);
+    my $drawmap = def_image_button('icons/trace.png');
+    my $diagram = def_image_button('icons/diagram.png');
+    set_tip($drawmap,'View actor Mapping Diagram') if($mode eq 'orcc');
+    set_tip($drawmap,'View Task Mapping Diagram') if($mode eq 'task');
+    set_tip($diagram,'View Topology Diagram') if($mode eq 'task');
+    set_tip($diagram,'View actor connection Diagram') if($mode eq 'orcc');
+    my $auto = def_image_button('icons/refresh.png');
+    set_tip($auto,'Automatically set the network dimensions according to the task number');    
+    my $clean = def_image_button('icons/clear.png');
+    set_tip($clean,'Remove mapping');    
+    my $box;
+    $box=def_pack_hbox(FALSE,FALSE,$drawmap,$diagram,$clean,$auto) if($mode eq 'task');
+    $box=def_pack_hbox(FALSE,FALSE,$drawmap,$diagram,$clean) if($mode eq 'orcc');    
+    my $col=0;
+    my $row=0;
+    $table->attach ($box,$col, $col+1,  $row, $row+1,'shrink','shrink',2,2);$row++;    
+    if($mode eq 'task'){
+        ($row,$col) =noc_topology_setting_gui($self,$table,$tview,$row,1,"");
+        $diagram-> signal_connect("clicked" => sub{ 
+            show_topology_diagram ($self) ;
+        });
+    }
+    
+    if($mode eq 'orcc'){
+        $diagram-> signal_connect("clicked" => sub{ 
+            show_trace_diagram ($self,'merge-actor');
+        });
+    }
+    
+    #my $credit =$self->object_get_attribute('map_param',"credit_en");
+    #if(defined $credit){
+    #    if($credit eq '1\'b0'){
+    #    $self->object_add_attribute('map_param',"receive_int",'1\'b0'); 
+    #}}
+    
+    my @info = ($mode eq 'task')? (
+    { label=>"Mapping Algorithm", param_name=>"Map_Algrm", type=>"Combo-box", default_val=>'Random', content=>"Nmap,Random,Reverse-NMAP,Direct", info=>undef, param_parent=>'map_param',ref_delay=>undef,placement=>'horizontal'},
+    ) :
+    
+    (    
+    { label=>"Mapping Algorithm", param_name=>"Map_Algrm", type=>"Combo-box", default_val=>'Random', content=>"Nmap,Random,Reverse-NMAP,Direct", info=>undef, param_parent=>'map_param',ref_delay=>undef,placement=>'horizontal'},
+    { label=>"ORCC FIFO Debug", param_name=>"add_debug", type=>"Check-box", default_val=>'1\'b0', content=>1, info=>"Add Actor FIFO debugging code to generated C codes to make sure FIFOs handshakings signals are handeled correctly between the source and destination cores", param_parent=>'map_param',ref_delay=>undef,placement=>'vertical'},
+    { label=>"Sent packet interrupt", param_name=>"sent_int", type=>"Check-box", default_val=>'1\'b1', content=>1, info=>"If the sent inttrupt is enabled, once a packet is completely sent out from the NI, the cpu is informed by intrrupt.", param_parent=>'map_param',ref_delay=>undef,placement=>'vertical'},
+    { label=>"Receive packet interrupt", param_name=>"receive_int", type=>"Check-box", default_val=>'1\'b1', content=>1, info=>"This flag enables receive-interrupt. Hence, the CPU can collect the received packet immediately from the NI. This interrupt avoids the NoC to be blocked by long packets.", param_parent=>'map_param',ref_delay=>1,placement=>'vertical'},
+    { label=>"Got NI error interrupt", param_name=>"got_err_int", type=>"Check-box", default_val=>'1\'b1', content=>1, info=>"Enable the inttrupt once any of NI error flags is asserted.", param_parent=>'map_param',ref_delay=>undef,placement=>'vertical'},
+    #{ label=>"ORCC FIFO Credit", param_name=>"credit_en", type=>"Check-box", default_val=>'1\'b1', content=>1, info=>"If this flag is enabled, the credit availbility of destination FIFOs are transfered to source FIFOs. The source FIFOs adapts the sent data size with the available space in destination FIFO. This makes sure the destination FIFO can collet whole of the packet and perevent the NoC resources to be blocked by long packets", param_parent=>'map_param',ref_delay=>1,placement=>'vertical'},
+    );
+    
+    #push(@info,{ label=>"Recieve FIFO extra space (%)", param_name=>"rsv_extra", type=>"Spin-button",content=>"1,100,1", default_val=>10, info=>"If ORCC FIFO Credit flag is not enabled, additional space is added to receive FIFOs to avoid FIFO overflow. The receiver FIFO only collects the NI's incoming packet if its occupied size is smaller than this additional space. This memory overhead could be avoided if the packet size is added to the header pre-captured data. However, it is not yet supported.", param_parent=>'map_param',ref_delay=>1,placement=>'vertical'},
+    #) if($credit eq '1\'b0');
+    foreach my $d (@info) {
+        ($row,$col)=add_param_widget ($self, $d->{label}, $d->{param_name}, $d->{default_val}, $d->{type}, $d->{content}, $d->{info}, $table,$row,$col,1, $d->{param_parent}, $d->{ref_delay},'ref',$d->{placement});
+        if($d->{param_name} eq "Map_Algrm"){
+            $table->attach  ($run_map , $col, $col+1,  $row,$row+1,'shrink','shrink',2,2);$row++;$col=0;
+            $table->attach  (gen_label_in_center  ("Enable/Disable flags:") , $col, $col+1,  $row,$row+1,'shrink','shrink',2,2);$row++;$col=0;
+        }
+    }
+    
+    $run_map->signal_connect( 'clicked'=> sub{
+        my $alg=$self->object_get_attribute('map_param','Map_Algrm');
+        update_merge_actor_list($self,$tview);
+        $self->random_map() if ($alg eq 'Random');
+        $self->worst_map_algorithm() if ($alg eq 'Reverse-NMAP');        
+        $self->nmap_algorithm() if ($alg eq 'Nmap');
+        $self->direct_map() if ($alg eq 'Direct');
+    });
+    
+    $drawmap->signal_connect ( 'clicked'=> sub{
+        show_trace_diagram($self,'map');
+    });
+    
+    $auto->signal_connect ( 'clicked'=> sub{
+        my @tasks = $self->get_all_merged_tasks();
+        my $task_num= scalar @tasks;
+        return if($task_num ==0);
+        my $topology = $self->object_get_attribute('noc_param','TOPOLOGY');
+        if ($topology eq '"MESH"' || $topology eq '"TORUS"' ){
+            my ($nx,$ny) =network_dim_cal($task_num);
+            $self->object_add_attribute('noc_param','T1',$nx);
+            $self->object_add_attribute('noc_param','T2',$ny);    
+            $self->object_add_attribute('noc_param','T3',1);    
+            set_gui_status($self,"ref",1);
+        }elsif ($topology eq '"RING"' || $topology eq '"LINE"'){
+            $self->object_add_attribute('noc_param','T1',$task_num);
+            $self->object_add_attribute('noc_param','T2',1);
+            $self->object_add_attribute('noc_param','T3',1);
+            set_gui_status($self,"ref",1);            
+        }
+    });
+    
+    $clean->signal_connect ( 'clicked'=> sub{
+        remove_mapping($self);
+        set_gui_status($self,"ref",1);    
+    });
+    return add_widget_to_scrolled_win($table);
 }
 
 
 ######
 # map_ctr
-######		
+######        
 sub trace_group_ctrl{
-	
-	my ($self,$tview,$mode,$NE)=@_;
-	my $table= def_table(2,10,FALSE);
-	
-	
-	
-		
-	my $clean = def_image_button('icons/clear.png');
-	set_tip($clean,'Ungroup all actors');	
-	
-	my $box;
-	$box=def_pack_hbox(FALSE,FALSE,$clean);	
-	
-	my $col=0;
-	my $row=0;
-	
-	
-	
-	
-	$table->attach ($box,$col, $col+1,  $row, $row+1,'shrink','shrink',2,2);$row++;	
-	
-	#$self->object_add_attribute('grouping','map_limit',$NE);
-	#add_param_widget ($self,'Max actors in a group:','map_limit', 4,"Spin-button","1,1024,1","The maximum number of actors that can be grouped to be run in one tile", $table,$row,$col,1,'grouping',undef,undef);
-	
-	
-	
-	$clean->signal_connect ( 'clicked'=> sub{
-		my $group_num=$self->object_get_attribute('grouping','group_num');
-		my $gname=$self->object_get_attribute('grouping','group_name_root');
-		for(my $i=0;$i<$group_num;$i=$i+1){
-			$self->object_add_attribute('grouping',"$gname($i)",\());		
-		}			
-		set_gui_status($self,"ref",1);	
-	});
-	
-	
-	return add_widget_to_scrolled_win($table);
-	
-	
-	
+    my ($self,$tview,$mode,$NE)=@_;
+    my $table= def_table(2,10,FALSE);
+    my $clean = def_image_button('icons/clear.png');
+    set_tip($clean,'Ungroup all actors');    
+    my $box;
+    $box=def_pack_hbox(FALSE,FALSE,$clean);    
+    my $col=0;
+    my $row=0;
+    $table->attach ($box,$col, $col+1,  $row, $row+1,'shrink','shrink',2,2);$row++;    
+    #$self->object_add_attribute('grouping','map_limit',$NE);
+    #add_param_widget ($self,'Max actors in a group:','map_limit', 4,"Spin-button","1,1024,1","The maximum number of actors that can be grouped to be run in one tile", $table,$row,$col,1,'grouping',undef,undef);
+    $clean->signal_connect ( 'clicked'=> sub{
+        my $group_num=$self->object_get_attribute('grouping','group_num');
+        my $gname=$self->object_get_attribute('grouping','group_name_root');
+        for(my $i=0;$i<$group_num;$i=$i+1){
+            $self->object_add_attribute('grouping',"$gname($i)",\());        
+        }            
+        set_gui_status($self,"ref",1);    
+    });
+    return add_widget_to_scrolled_win($table);
 }
 
 
 
-
-
-
-
-
-	
 #########
 # trace
 #########
-
 sub trace_pad{
-	my ($self,$tview,$mode)=@_;
-	my $table= def_table(10,10,FALSE);
-	
-	my $row=0;
-	my $col=0;
-		
-	
-	my @selectedinfo = (
-		{ label=>" Initial weight ", param_name=>'init_weight', type=>'Spin-button', default_val=>1, content=>"1,16,1", info=>undef, param_parent=>'select_multiple', ref_delay=> undef, new_status=>undef},
-		{ label=>" Min pck size ", param_name=>'min_pck_size', type=>'Spin-button', default_val=>5, content=>"2,1024,1", info=>undef, param_parent=>'select_multiple', ref_delay=> 10, new_status=>'ref'},
-		{ label=>" Max pck size ",param_name=>'max_pck_size', type=>'Spin-button', default_val=>5, content=>"2,1024,1", info=>undef, param_parent=>'select_multiple', ref_delay=> 10, new_status=>'ref'},
-		{ label=>" Burst_size ", param_name=>'burst_size', type=>'Spin-button', default_val=>1, content=>"1,1024,1", info=>undef, param_parent=>'select_multiple', ref_delay=> undef, new_status=>undef},
-		{ label=>" Inject rate(%) ", param_name=>'injct_rate', type=>'Spin-button', default_val=>10, content=>"1,100,1", info=>undef, param_parent=>'select_multiple', ref_delay=> undef, new_status=>undef},
-	    { label=>" Inject rate variation (%) ", param_name=>'injct_rate_var', type=>'Spin-button', default_val=>20, content=>"0,100,1", info=>undef, param_parent=>'select_multiple', ref_delay=> undef, new_status=>undef},
-	);
-	
-	my $v_val= $self->object_get_attribute('noc_param','V');
-	my $v_max=$v_val-1;	
-	
-	my $c_val= $self->object_get_attribute('noc_param','C');
-	my $c_max=($c_val==0)? 0 : $c_val-1;
-	
-	
-	if($mode eq "orcc"){
-		
-		@selectedinfo = (
-			{ label=>" Initial weight ", param_name=>'init_weight', type=>'Spin-button', default_val=>1, content=>"1,16,1", info=>undef, param_parent=>'select_multiple', ref_delay=> undef, new_status=>undef},
-			{ label=>" Virtual chanel# ", param_name=>'vc', type=>'Spin-button', default_val=>0, content=>"0,$v_max,1", info=>undef, param_parent=>'select_multiple', ref_delay=> undef, new_status=>undef},
-			{ label=>" Message class# ", param_name=>'class', type=>'Spin-button', default_val=>0, content=>"0,$c_max,1", info=>undef, param_parent=>'select_multiple', ref_delay=> undef, new_status=>undef}
-		);
-	}
-	
-	
-	my @traces= get_trace_list($self,'raw');
-	my %f;
-	
-	
-	my $sel=$self->object_get_attribute('select_multiple','action');
-	
-	foreach my $p (@traces) {	
-		my ($src,$dst, $Mbytes, $file_id, $file_name)=get_trace($self,'raw',$p);
-		$f{$file_id}=$file_id.'*';
-		$self->object_add_attribute("raw_$p",'selected', 1 ) if ($sel eq  'All');
-		$self->object_add_attribute("raw_$p",'selected', 0 ) if ($sel eq  'None');
-		$self->object_add_attribute("raw_$p",'selected', 1 ) if ($sel eq  "All-$file_id*");
-		$self->object_add_attribute("raw_$p",'selected', 0 ) if ($sel eq  "None-$file_id*");
-		
-		my $seleceted =$self->object_get_attribute("raw_$p",'selected');
-		foreach my $d (@selectedinfo) {
-			my $val=$self->object_get_attribute($d->{param_parent},$d->{param_name}) if ($sel eq  $d->{param_name} && $seleceted);	
-			$self->object_add_attribute("raw_$p",$d->{param_name}, $val ) if ($sel eq  $d->{param_name}&& $seleceted);	
-			
-		}
-	}	
-	my $sel_options= "Select,All,None";
-	if( keys %f > 1){
-		foreach my $p (sort keys %f) {
-			$sel_options="$sel_options,All-$f{$p}";
-			$sel_options="$sel_options,None-$f{$p}";
-		}
-	}	
-	$self->object_add_attribute('select_multiple','action',"Select");
-	my $selcombo = $self-> gen_combobox_object ('select_multiple',"action", $sel_options,'-','ref',1);
-	
-	
-	if(scalar @traces ){$table-> attach  ($selcombo, $col, $col+1,  $row, $row+1,'shrink','shrink',2,2);  $col++;}
-	
-	
-	my @titles;
-	#print "******************$mode*******************\n";
-	if($mode eq 'task'){
-		@titles = (scalar @traces ) ? (" # "," Source "," Destination "," Bandwidth(MB) ", " Initial weight ", " Min pck size ",  " Max pck size "):
-	("Load a task graph");
-	}
-	else{
-		@titles = (scalar @traces ) ? (" # "," Source "," Destination "," Bandwidth(MB) ", " Initial weight#", "Virtual chanel#", "Message class#"):
-	("Load an ORCC file");
-	}
-	
-	my $auto=$self->object_get_attribute('Auto','Auto_inject');
-	
-	push (@titles, (" Burst_size ", " Inject rate(%) ", " Inject rate variation(%) ")) if ($auto eq "1\'b0" && $mode eq 'task');
-	foreach my $p (@titles){
-		$table-> attach  (gen_label_in_left($p), $col, $col+1,  $row, $row+1,'shrink','shrink',2,2);  
-		$col++;
-	}
-		$row++;	
-				
-	my $i=0;
-	#my @t=sort { $a cmp $b } @traces;
-	
-	foreach my $p (@traces) {	
-		$col=0;	
-		my ($src,$dst, $Mbytes, $file_id, $file_name)=get_trace($self,'raw',$p);
-		
-				
-		my $check = gen_check_box_object ($self,"raw_$p",'selected',0,'ref',0);
-		my $weight= gen_spin_object ($self,"raw_$p",'init_weight',"1,16,1", 1,undef,undef);
-		my $vc= gen_spin_object ($self,"raw_$p",'vc',"0,$v_max,1", 0,undef,undef);
-		my $class= gen_spin_object ($self,"raw_$p",'class',"0,$c_max,1", 0,undef,undef);
-		
-		my $min=$self->object_get_attribute("raw_$p",'min_pck_size');
-		my $max=$self->object_get_attribute("raw_$p",'max_pck_size');
-		$min=$max=5 if(!defined $min);
-		my $min_pck_size= gen_spin_object ($self,"raw_$p",'min_pck_size',"2,$max,1", 5,'ref',10);
-		my $max_pck_size= gen_spin_object ($self,"raw_$p",'max_pck_size',"$min,1024,1", 5,'ref',10);
-		
-		my $burst_size	= gen_spin_object ($self,"raw_$p",'burst_size',"1,1024,1", 1,undef,undef);
-		my $injct_rate  = gen_spin_object ($self,"raw_$p",'injct_rate',"1,100,1", 10,undef,undef);
-		my $injct_rate_var  = gen_spin_object ($self,"raw_$p",'injct_rate_var',"0,100,1", 20,undef,undef);
-		
-		#my $weight=  trace_$trace_id",'init_weight'
-		
-		$table-> attach  ($check, $col, $col+1,  $row, $row+1,'shrink','shrink',2,2);  $col++;
-		
-		$table-> attach (gen_label_in_left($i), $col, $col+1,  $row, $row+1,'shrink','shrink',2,2);  $col++; 
-		$table-> attach (gen_label_in_left("$src") ,$col, $col+1,  $row, $row+1,'shrink','shrink',2,2);  $col++;
-		$table-> attach (gen_label_in_left("$dst") , $col, $col+1,  $row, $row+1,'shrink','shrink',2,2);  $col++;
-		$table-> attach (gen_label_in_left("$Mbytes") ,$col, $col+1,  $row, $row+1,'shrink','shrink',2,2);  $col++;
-		$table-> attach ($weight ,$col, $col+1,  $row, $row+1,'shrink','shrink',2,2);  $col++;
-		if($mode eq 'task'){			
-			$table-> attach ($min_pck_size, $col, $col+1,  $row, $row+1,'shrink','shrink',2,2);  $col++;
-		    $table-> attach ($max_pck_size, $col, $col+1,  $row, $row+1,'shrink','shrink',2,2);  $col++;
-		    if ($auto eq "1\'b0"){
-				$table-> attach ($burst_size ,$col, $col+1,  $row, $row+1,'shrink','shrink',2,2);  $col++;
-				$table-> attach ($injct_rate ,$col, $col+1,  $row, $row+1,'shrink','shrink',2,2);  $col++;
-				$table-> attach ($injct_rate_var ,$col, $col+1,  $row, $row+1,'shrink','shrink',2,2);  $col++;		
-		    }
-		}else{
-			$table-> attach ($vc ,$col, $col+1,  $row, $row+1,'shrink','shrink',2,2);  $col++;
-			$table-> attach ($class ,$col, $col+1,  $row, $row+1,'shrink','shrink',2,2);  $col++;
-		}
-		
-		$row++;	
-		
-	}
-	
-	my $sc_win = gen_scr_win_with_adjst($self,'trace_pad');
-	$sc_win=add_widget_to_scrolled_win($table,$sc_win);
-	
-	return $sc_win;
+    my ($self,$tview,$mode)=@_;
+    my $table= def_table(10,10,FALSE);
+    my $row=0;
+    my $col=0;
+    my @selectedinfo = (
+        { label=>" Initial weight ", param_name=>'init_weight', type=>'Spin-button', default_val=>1, content=>"1,16,1", info=>undef, param_parent=>'select_multiple', ref_delay=> undef, new_status=>undef},
+        { label=>" Min pck size ", param_name=>'min_pck_size', type=>'Spin-button', default_val=>5, content=>"2,1024,1", info=>undef, param_parent=>'select_multiple', ref_delay=> 10, new_status=>'ref'},
+        { label=>" Max pck size ",param_name=>'max_pck_size', type=>'Spin-button', default_val=>5, content=>"2,1024,1", info=>undef, param_parent=>'select_multiple', ref_delay=> 10, new_status=>'ref'},
+        { label=>" Burst_size ", param_name=>'burst_size', type=>'Spin-button', default_val=>1, content=>"1,1024,1", info=>undef, param_parent=>'select_multiple', ref_delay=> undef, new_status=>undef},
+        { label=>" Inject rate(%) ", param_name=>'injct_rate', type=>'Spin-button', default_val=>10, content=>"1,100,1", info=>undef, param_parent=>'select_multiple', ref_delay=> undef, new_status=>undef},
+        { label=>" Inject rate variation (%) ", param_name=>'injct_rate_var', type=>'Spin-button', default_val=>20, content=>"0,100,1", info=>undef, param_parent=>'select_multiple', ref_delay=> undef, new_status=>undef},
+    );
+    
+    my $v_val= $self->object_get_attribute('noc_param','V');
+    my $v_max=$v_val-1;    
+    my $c_val= $self->object_get_attribute('noc_param','C');
+    my $c_max=($c_val==0)? 0 : $c_val-1;
+    if($mode eq "orcc"){
+        @selectedinfo = (
+            { label=>" Initial weight ", param_name=>'init_weight', type=>'Spin-button', default_val=>1, content=>"1,16,1", info=>undef, param_parent=>'select_multiple', ref_delay=> undef, new_status=>undef},
+            { label=>" Virtual chanel# ", param_name=>'vc', type=>'Spin-button', default_val=>0, content=>"0,$v_max,1", info=>undef, param_parent=>'select_multiple', ref_delay=> undef, new_status=>undef},
+            { label=>" Message class# ", param_name=>'class', type=>'Spin-button', default_val=>0, content=>"0,$c_max,1", info=>undef, param_parent=>'select_multiple', ref_delay=> undef, new_status=>undef}
+        );
+    }
+    
+    my @traces= get_trace_list($self,'raw');
+    my %f;
+    my $sel=$self->object_get_attribute('select_multiple','action');
+    foreach my $p (@traces) {    
+        my ($src,$dst, $Mbytes, $file_id, $file_name)=get_trace($self,'raw',$p);
+        $f{$file_id}=$file_id.'*';
+        $self->object_add_attribute("raw_$p",'selected', 1 ) if ($sel eq  'All');
+        $self->object_add_attribute("raw_$p",'selected', 0 ) if ($sel eq  'None');
+        $self->object_add_attribute("raw_$p",'selected', 1 ) if ($sel eq  "All-$file_id*");
+        $self->object_add_attribute("raw_$p",'selected', 0 ) if ($sel eq  "None-$file_id*");
+        my $seleceted =$self->object_get_attribute("raw_$p",'selected');
+        foreach my $d (@selectedinfo) {
+            my $val=$self->object_get_attribute($d->{param_parent},$d->{param_name}) if ($sel eq  $d->{param_name} && $seleceted);    
+            $self->object_add_attribute("raw_$p",$d->{param_name}, $val ) if ($sel eq  $d->{param_name}&& $seleceted);    
+            
+        }
+    }    
+    my $sel_options= "Select,All,None";
+    if( keys %f > 1){
+        foreach my $p (sort keys %f) {
+            $sel_options="$sel_options,All-$f{$p}";
+            $sel_options="$sel_options,None-$f{$p}";
+        }
+    }    
+    $self->object_add_attribute('select_multiple','action',"Select");
+    my $selcombo = $self-> gen_combobox_object ('select_multiple',"action", $sel_options,'-','ref',1);
+    if(scalar @traces ){$table-> attach  ($selcombo, $col, $col+1,  $row, $row+1,'shrink','shrink',2,2);  $col++;}
+    my @titles;
+    #print "******************$mode*******************\n";
+    if($mode eq 'task'){
+        @titles = (scalar @traces ) ? (" # "," Source "," Destination "," Bandwidth(MB) ", " Initial weight ", " Min pck size ",  " Max pck size "):
+    ("Load a task graph");
+    }
+    else{
+        @titles = (scalar @traces ) ? (" # "," Source "," Destination "," Bandwidth(MB) ", " Initial weight#", "Virtual chanel#", "Message class#"):
+    ("Load an ORCC file");
+    }
+    my $auto=$self->object_get_attribute('Auto','Auto_inject');
+    push (@titles, (" Burst_size ", " Inject rate(%) ", " Inject rate variation(%) ")) if ($auto eq "1\'b0" && $mode eq 'task');
+    foreach my $p (@titles){
+        $table-> attach  (gen_label_in_left($p), $col, $col+1,  $row, $row+1,'shrink','shrink',2,2);  
+        $col++;
+    }
+        $row++;    
+    my $i=0;
+    #my @t=sort { $a cmp $b } @traces;
+    foreach my $p (@traces) {    
+        $col=0;    
+        my ($src,$dst, $Mbytes, $file_id, $file_name)=get_trace($self,'raw',$p);
+        my $check = gen_check_box_object ($self,"raw_$p",'selected',0,'ref',0);
+        my $weight= gen_spin_object ($self,"raw_$p",'init_weight',"1,16,1", 1,undef,undef);
+        my $vc= gen_spin_object ($self,"raw_$p",'vc',"0,$v_max,1", 0,undef,undef);
+        my $class= gen_spin_object ($self,"raw_$p",'class',"0,$c_max,1", 0,undef,undef);
+        my $min=$self->object_get_attribute("raw_$p",'min_pck_size');
+        my $max=$self->object_get_attribute("raw_$p",'max_pck_size');
+        $min=$max=5 if(!defined $min);
+        my $min_pck_size= gen_spin_object ($self,"raw_$p",'min_pck_size',"2,$max,1", 5,'ref',10);
+        my $max_pck_size= gen_spin_object ($self,"raw_$p",'max_pck_size',"$min,1024,1", 5,'ref',10);
+        my $burst_size    = gen_spin_object ($self,"raw_$p",'burst_size',"1,1024,1", 1,undef,undef);
+        my $injct_rate  = gen_spin_object ($self,"raw_$p",'injct_rate',"1,100,1", 10,undef,undef);
+        my $injct_rate_var  = gen_spin_object ($self,"raw_$p",'injct_rate_var',"0,100,1", 20,undef,undef);
+        #my $weight=  trace_$trace_id",'init_weight'
+        $table-> attach  ($check, $col, $col+1,  $row, $row+1,'shrink','shrink',2,2);  $col++;
+        $table-> attach (gen_label_in_left($i), $col, $col+1,  $row, $row+1,'shrink','shrink',2,2);  $col++; 
+        $table-> attach (gen_label_in_left("$src") ,$col, $col+1,  $row, $row+1,'shrink','shrink',2,2);  $col++;
+        $table-> attach (gen_label_in_left("$dst") , $col, $col+1,  $row, $row+1,'shrink','shrink',2,2);  $col++;
+        $table-> attach (gen_label_in_left("$Mbytes") ,$col, $col+1,  $row, $row+1,'shrink','shrink',2,2);  $col++;
+        $table-> attach ($weight ,$col, $col+1,  $row, $row+1,'shrink','shrink',2,2);  $col++;
+        if($mode eq 'task'){            
+            $table-> attach ($min_pck_size, $col, $col+1,  $row, $row+1,'shrink','shrink',2,2);  $col++;
+            $table-> attach ($max_pck_size, $col, $col+1,  $row, $row+1,'shrink','shrink',2,2);  $col++;
+            if ($auto eq "1\'b0"){
+                $table-> attach ($burst_size ,$col, $col+1,  $row, $row+1,'shrink','shrink',2,2);  $col++;
+                $table-> attach ($injct_rate ,$col, $col+1,  $row, $row+1,'shrink','shrink',2,2);  $col++;
+                $table-> attach ($injct_rate_var ,$col, $col+1,  $row, $row+1,'shrink','shrink',2,2);  $col++;        
+            }
+        }else{
+            $table-> attach ($vc ,$col, $col+1,  $row, $row+1,'shrink','shrink',2,2);  $col++;
+            $table-> attach ($class ,$col, $col+1,  $row, $row+1,'shrink','shrink',2,2);  $col++;
+        }
+        $row++;    
+    }
+    my $sc_win = gen_scr_win_with_adjst($self,'trace_pad');
+    $sc_win=add_widget_to_scrolled_win($table,$sc_win);
+    return $sc_win;
 }
 
 
-
 sub load_tarce_file{
-	my ($self,$file,$tview)=@_;
-	#open file
-	my @x;
-	my %traces;
-	if (!defined $file) {return; }
-	if (-e $file) { 
-		my $f_id=$self->object_get_attribute("file_id",undef);
-		my $t_id=$self->object_get_attribute("trace_id",undef);
-		open(my $fh, '<:encoding(UTF-8)', $file) or die "Could not open file '$file' $!";
-		while (my $row = <$fh>) {
-			chomp $row;
-			my @data = 	split (/\s/,$row);
-			
-			next if (! defined $data[0]);
-			next if ($data[0] eq '#' || scalar @data < 3);
-			
-			$self->add_trace($f_id,'raw',$t_id,$data[0],$data[1],$data[2],$file);
-			$t_id++;			
-		}
-		$f_id++;
-		$self->object_add_attribute("trace_id",undef,$t_id);
-		$self->object_add_attribute("file_id",undef,$f_id);
-	}
-	set_gui_status($self,"ref",1);
-	
+    my ($self,$file,$tview)=@_;
+    #open file
+    my @x;
+    my %traces;
+    if (!defined $file) {return; }
+    if (-e $file) { 
+        my $f_id=$self->object_get_attribute("file_id",undef);
+        my $t_id=$self->object_get_attribute("trace_id",undef);
+        open(my $fh, '<:encoding(UTF-8)', $file) or die "Could not open file '$file' $!";
+        while (my $row = <$fh>) {
+            chomp $row;
+            my @data =     split (/\s/,$row);
+            next if (! defined $data[0]);
+            next if ($data[0] eq '#' || scalar @data < 3);
+            $self->add_trace($f_id,'raw',$t_id,$data[0],$data[1],$data[2],$file);
+            $t_id++;            
+        }
+        $f_id++;
+        $self->object_add_attribute("trace_id",undef,$t_id);
+        $self->object_add_attribute("file_id",undef,$f_id);
+    }
+    set_gui_status($self,"ref",1);
 }
 
-
-
-
 ########
 # map
 #######
-
-
 sub group_info {
-	my ($self,$tview,$mode)=@_;
-	my $table= def_table(10,10,FALSE);
-	
-	
-	my $sc_win = gen_scr_win_with_adjst($self,'trace_map');
-	$sc_win=add_widget_to_scrolled_win($table,$sc_win);
-	
-	my $row=0;
-	my $col=0;
-	
-	my $lab= ($mode eq 'task')? "Task-name" :"Actor-name";
-	
-	my @titles = (" # "," $lab ", " Internal" , " Sent ", " Resvd ", " Sent+Resvd ");
-	foreach my $p (@titles){
-		$table-> attach  (gen_label_in_left($p), $col, $col+1,  $row, $row+1,'shrink','shrink',2,2); $col++;
-	}
-	$col=0;
-	$row++;	
-	
-	
-	
-	my $i=0;
-	my @tasks=get_all_merged_tasks($self);
-	
-	
-	
-	
-	#print "tils=@tiles \nass=@assigned  \nlist=@list\n";
-	my %com_tasks= $self->get_communication_task('merge');
-	#print Dumper(\%com_tasks);
-	foreach my $p (@tasks){
-		
-			
-		$table-> attach  (gen_label_in_left($i), $col, $col+1,  $row, $row+1,'shrink','shrink',2,2); $col++; 
-		$table-> attach  (gen_label_in_left($p), $col, $col+1,  $row, $row+1,'shrink','shrink',2,2); $col++; 
-	    
-		my @a=('internal' , 'sent','rsv','total');
-		foreach my $q (@a){
-			my $s = (defined $com_tasks{$p}{$q}) ? $com_tasks{$p}{$q} : '-';
-			$table-> attach  (gen_label_in_left($s), $col, $col+1,  $row, $row+1,'shrink','shrink',2,2); $col++; 
-		
-		}
-		
-		
-		
-		
-	
-		$i++;
-		$col=0;
-		$row++;						
-	}
-		
-   
-   		
-			
-	
-	return $sc_win;
-	
+    my ($self,$tview,$mode)=@_;
+    my $table= def_table(10,10,FALSE);
+    my $sc_win = gen_scr_win_with_adjst($self,'trace_map');
+    $sc_win=add_widget_to_scrolled_win($table,$sc_win);
+    my $row=0;
+    my $col=0;
+    my $lab= ($mode eq 'task')? "Task-name" :"Actor-name";
+    my @titles = (" # "," $lab ", " Internal" , " Sent ", " Resvd ", " Sent+Resvd ");
+    foreach my $p (@titles){
+        $table-> attach  (gen_label_in_left($p), $col, $col+1,  $row, $row+1,'shrink','shrink',2,2); $col++;
+    }
+    $col=0;
+    $row++;    
+    my $i=0;
+    my @tasks=get_all_merged_tasks($self);
+    #print "tils=@tiles \nass=@assigned  \nlist=@list\n";
+    my %com_tasks= $self->get_communication_task('merge');
+    #print Dumper(\%com_tasks);
+    foreach my $p (@tasks){
+        $table-> attach  (gen_label_in_left($i), $col, $col+1,  $row, $row+1,'shrink','shrink',2,2); $col++; 
+        $table-> attach  (gen_label_in_left($p), $col, $col+1,  $row, $row+1,'shrink','shrink',2,2); $col++; 
+        my @a=('internal' , 'sent','rsv','total');
+        foreach my $q (@a){
+            my $s = (defined $com_tasks{$p}{$q}) ? $com_tasks{$p}{$q} : '-';
+            $table-> attach  (gen_label_in_left($s), $col, $col+1,  $row, $row+1,'shrink','shrink',2,2); $col++; 
+        }
+        $i++;
+        $col=0;
+        $row++;                        
+    }
+    return $sc_win;
 }
 
-
-
-
-
-
-
-
-########
-# map_info
-#######
-
-
-
 ########
 # map_info
 #######
-
-
 sub map_info {
-	my ($self)=@_;
-	my $sc_win = gen_scr_win_with_adjst($self,'map_info');
-	my $table= def_table(10,10,FALSE);
-	
-	
-	my $row=0;
-	my $col=0;
-	my ($avg,$max,$min,$norm)=get_map_info($self);
-	
-	
-	my @data = (
-  {0 => "Average distance", 1 =>"$avg"}, 
-  {0 => "Max distance"    , 1 =>"$max" },  
-  {0 => "Min distance"    , 1 => "$min"},    
-  {0 => "Normalized data per hop", 1 =>"$norm" }
-  );
-	
-	
-	
-	# create list store
-	my @clmn_type =  ('Glib::String',  'Glib::String'); 
-	my @clmns = ("Mapping Summary", " ");
-	add_widget_to_scrolled_win(gen_list_store (\@data,\@clmn_type,\@clmns),$sc_win);
-	$sc_win->show_all;
-	return $sc_win;
-
+    my ($self)=@_;
+    my $sc_win = gen_scr_win_with_adjst($self,'map_info');
+    my $table= def_table(10,10,FALSE);
+    my $row=0;
+    my $col=0;
+    my ($avg,$max,$min,$norm)=get_map_info($self);
+    my @data = (
+    {0 => "Average distance", 1 =>"$avg"}, 
+    {0 => "Max distance"    , 1 =>"$max" },  
+    {0 => "Min distance"    , 1 => "$min"},    
+    {0 => "Normalized data per hop", 1 =>"$norm" }
+    );
+    # create list store
+    my @clmn_type =  ('Glib::String',  'Glib::String'); 
+    my @clmns = ("Mapping Summary", " ");
+    add_widget_to_scrolled_win(gen_list_store (\@data,\@clmn_type,\@clmns),$sc_win);
+    $sc_win->show_all;
+    return $sc_win;
 }
 
 
-
-
-
 sub get_map_info {
-	my $self=shift;
-	my ($avg,$max,$min,$norm)=(0,0,999999,0);
-	my $sum=0;	
-	my $num=0;	
-	
-	my $data=0;	
-	my $comtotal=0;	
-	
-	my @traces= get_trace_list($self,'merge');
-	
-	foreach my $p (@traces) {	
-		my ($src, $dst, $Mbytes, $file_id, $file_name)=get_trace($self,'merge',$p);
-		#my $src_tile = $self->object_get_attribute('MAP_TILE',"$src");
-		my  $src_tile = get_task_give_tile($self,"$src");
-		#my $dst_tile = $self->object_get_attribute('MAP_TILE',"$dst");
-		my $dst_tile  = get_task_give_tile($self,"$dst");
-		next if(!defined $src_tile || !defined  $dst_tile );
-		next if($src_tile eq '-' || $dst_tile eq "-" );
-		#my ($src_x,$src_y)= tile_id_to_loc($src_tile);
-		
-		#my ($dst_x,$dst_y)= tile_id_to_loc($dst_tile);		
-		#print" ($dst_x,$dst_y)= tile_id_to_loc($dst_tile)\n";
-		
-		my $mah_distance=get_endpoints_mah_distance($self,tile_id_number($src_tile),tile_id_number($dst_tile));
-		#print "$mah_distance=get_mah_distance($src_x,$src_y,$dst_x,$dst_y);\n";
-		$min = $mah_distance if($min> $mah_distance);
-		$max = $mah_distance if($max< $mah_distance);
-		$sum+=$mah_distance;	
-		$num++;	
-		
-		$data+=($Mbytes*$mah_distance);	
-	    $comtotal+=$Mbytes;	
-		
-	}
-	
-	$avg=$sum/$num if($num!=0);
-	$min = 0 if $min == 999999;
-	$norm = $data/$comtotal if ($comtotal !=0);
-	return ($avg,$max,$min,$norm);
-	
-}	
-
-
-
-
+    my $self=shift;
+    my ($avg,$max,$min,$norm)=(0,0,999999,0);
+    my $sum=0;    
+    my $num=0;    
+    my $data=0;    
+    my $comtotal=0;    
+    my @traces= get_trace_list($self,'merge');
+    foreach my $p (@traces) {    
+        my ($src, $dst, $Mbytes, $file_id, $file_name)=get_trace($self,'merge',$p);
+        #my $src_tile = $self->object_get_attribute('MAP_TILE',"$src");
+        my  $src_tile = get_task_give_tile($self,"$src");
+        #my $dst_tile = $self->object_get_attribute('MAP_TILE',"$dst");
+        my $dst_tile  = get_task_give_tile($self,"$dst");
+        next if(!defined $src_tile || !defined  $dst_tile );
+        next if($src_tile eq '-' || $dst_tile eq "-" );
+        #my ($src_x,$src_y)= tile_id_to_loc($src_tile);
+        #my ($dst_x,$dst_y)= tile_id_to_loc($dst_tile);        
+        #print" ($dst_x,$dst_y)= tile_id_to_loc($dst_tile)\n";
+        my $mah_distance=get_endpoints_mah_distance($self,tile_id_number($src_tile),tile_id_number($dst_tile));
+        #print "$mah_distance=get_mah_distance($src_x,$src_y,$dst_x,$dst_y);\n";
+        $min = $mah_distance if($min> $mah_distance);
+        $max = $mah_distance if($max< $mah_distance);
+        $sum+=$mah_distance;    
+        $num++;    
+        $data+=($Mbytes*$mah_distance);    
+        $comtotal+=$Mbytes;    
+    }
+    $avg=$sum/$num if($num!=0);
+    $min = 0 if $min == 999999;
+    $norm = $data/$comtotal if ($comtotal !=0);
+    return ($avg,$max,$min,$norm);
+}    
 
 sub map_combobox {
- 	my ($object,$task_name,$content,$default)=@_;
-	my @combo_list=@{$content};
-	#my $value=$object->object_get_attribute("MAP_TILE",$task_name);
-	my $value=get_task_give_tile($object,$task_name);
-	my $pos;
-	$pos=get_pos($value, @combo_list) if (defined $value);
-	if(!defined $pos && defined $default){
-		#$object->object_add_attribute("MAP_TILE",$task_name,$default);	
-	 	$pos=get_item_pos($default, @combo_list);
-	}
-	#print " my $pos=get_item_pos($value, @combo_list);\n";
-	my $widget=gen_combo(\@combo_list, $pos);
-	$widget-> signal_connect("changed" => sub{
-		my $new_tile=$widget->get_active_text();
-		$object->map_task($task_name,$new_tile);
-				
-		set_gui_status($object,'ref',1);
-	 });
-	return $widget;	
+    my ($object,$task_name,$content,$default)=@_;
+    my @combo_list=@{$content};
+    #my $value=$object->object_get_attribute("MAP_TILE",$task_name);
+    my $value=get_task_give_tile($object,$task_name);
+    my $pos;
+    $pos=get_pos($value, @combo_list) if (defined $value);
+    if(!defined $pos && defined $default){
+        #$object->object_add_attribute("MAP_TILE",$task_name,$default);    
+        $pos=get_item_pos($default, @combo_list);
+    }
+    #print " my $pos=get_item_pos($value, @combo_list);\n";
+    my $widget=gen_combo(\@combo_list, $pos);
+    $widget-> signal_connect("changed" => sub{
+        my $new_tile=$widget->get_active_text();
+        $object->map_task($task_name,$new_tile);
+                
+        set_gui_status($object,'ref',1);
+    });
+    return $widget;    
 }
 
 
 ##########
-#	save_as
+#    save_as
 ##########
 sub save_as{
-	my ($self)=@_;
-	# read emulation name
-	my $name=$self->object_get_attribute ("save_as",undef);	
-	my $s= (!defined $name)? 0 : (length($name)==0)? 0 :1;	
-	if ($s == 0){
-		message_dialog("Please define file name!");
-		return 0;
-	}
-	# Write object file
-	open(FILE,  ">lib/simulate/$name.TRC") || die "Can not open: $!";
-	print FILE perl_file_header("$name.TRC");
-	print FILE Data::Dumper->Dump([\%$self],['Trace']);
-	close(FILE) || die "Error closing file: $!";
-	message_dialog("workspace has been saved as lib/simulate/$name.TRC!");
-	return 1;
+    my ($self)=@_;
+    # read emulation name
+    my $name=$self->object_get_attribute ("save_as",undef);    
+    my $s= (!defined $name)? 0 : (length($name)==0)? 0 :1;    
+    if ($s == 0){
+        message_dialog("Please define file name!");
+        return 0;
+    }
+    # Write object file
+    open(FILE,  ">lib/simulate/$name.TRC") || die "Can not open: $!";
+    print FILE perl_file_header("$name.TRC");
+    print FILE Data::Dumper->Dump([\%$self],['Trace']);
+    close(FILE) || die "Error closing file: $!";
+    message_dialog("workspace has been saved as lib/simulate/$name.TRC!");
+    return 1;
 }
 
 
-
-
 #############
-#	load_workspace
+#    load_workspace
 ############
-
 sub load_workspace {
-	my $self=shift;
-	my $mpsoc_name=$self->object_get_attribute('mpsoc_name');
-	
-	my $file;
-	my $dialog = gen_file_dialog(undef,'TRC');
-	my $dir = Cwd::getcwd();
-	$dialog->set_current_folder ("$dir/lib/simulate");		
-	
-	if ( "ok" eq $dialog->run ) {
-		$file = $dialog->get_filename;
-		my ($name,$path,$suffix) = fileparse("$file",qr"\..[^.]*$");
-		if($suffix eq '.TRC'){		
-							
-			my ($pp,$r,$err) = regen_object($file);
-			if ($r){		
-				message_dialog("Error reading  $file file: $err\n",'error');
-				 $dialog->destroy;
-				return;
-			} 
-			
-			my ($tmp,$r1,$err1) = regen_object($file);
-			
-			
-			clone_obj($tmp,$self);
-			
-								
-			clone_obj($self,$pp);
-			
-			#update current parameter 
-			my @pnames=('soc_name','ni_name','noc_param');
-			foreach my $n (@pnames){
-				my $param=$tmp->object_get_attribute($n);
-				if( defined $param){
-					my %params=%{$param};
-					foreach my $p (sort keys %params){
-						$self->{$n}{$p}=$params{$p};			 
-					}
-				}
-			}
-			
-			#update mpsocname
-			$self->object_add_attribute('mpsoc_name',undef,$mpsoc_name) if (defined $mpsoc_name);
-			
-			
-			
-			
-			
-			
-			#print Dumper($self);
-			
-			#message_dialog("done!");				
-		}					
-     }
-     $dialog->destroy;
+    my $self=shift;
+    my $mpsoc_name=$self->object_get_attribute('mpsoc_name');
+    my $file;
+    my $dialog = gen_file_dialog(undef,'TRC');
+    my $dir = Cwd::getcwd();
+    $dialog->set_current_folder ("$dir/lib/simulate");        
+    if ( "ok" eq $dialog->run ) {
+        $file = $dialog->get_filename;
+        my ($name,$path,$suffix) = fileparse("$file",qr"\..[^.]*$");
+        if($suffix eq '.TRC'){        
+                            
+            my ($pp,$r,$err) = regen_object($file);
+            if ($r){        
+                message_dialog("Error reading  $file file: $err\n",'error');
+                $dialog->destroy;
+                return;
+            } 
+            my ($tmp,$r1,$err1) = regen_object($file);
+            clone_obj($tmp,$self);
+            clone_obj($self,$pp);
+            #update current parameter 
+            my @pnames=('soc_name','ni_name','noc_param');
+            foreach my $n (@pnames){
+                my $param=$tmp->object_get_attribute($n);
+                if( defined $param){
+                    my %params=%{$param};
+                    foreach my $p (sort keys %params){
+                        $self->{$n}{$p}=$params{$p};             
+                    }
+                }
+            }
+            #update mpsocname
+            $self->object_add_attribute('mpsoc_name',undef,$mpsoc_name) if (defined $mpsoc_name);
+            #print Dumper($self);
+            #message_dialog("done!");                
+        }                    
+    }
+    $dialog->destroy;
 }
 
 
 ########
 # genereate_output_tasks
 ########
-
 sub genereate_output_tasks{
-	my $self=shift;
-	my $name= $self->object_get_attribute('out_name');
-	my $size= (defined $name)? length($name) :0;
-	if ($size ==0) {
-		message_dialog("Please define the output file name!");
-		return 0;
-	}
-	
-	
-	
-	# make target dir
-	my $dir = Cwd::getcwd();
-	my $target_dir  = "$ENV{'PRONOC_WORK'}/traffic_pattern";
-	mkpath("$target_dir",1,0755);
-	
-	my @tasks=get_all_merged_tasks($self);
-	foreach my $p (@tasks) {	
-		#my $tile=$self->object_get_attribute("MAP_TILE",$p);
-		my $tile= get_task_give_tile($self,$p);
-		if ( $tile eq "-" ){
-			message_dialog("Error: unmapped task. Please map task $p to a tile", 'error' );
-			return;
-		}
-	
-	}
-	#creat output file
+    my $self=shift;
+    my $name= $self->object_get_attribute('out_name');
+    my $size= (defined $name)? length($name) :0;
+    if ($size ==0) {
+        message_dialog("Please define the output file name!");
+        return 0;
+    }
+    # make target dir
+    my $dir = Cwd::getcwd();
+    my $target_dir  = "$ENV{'PRONOC_WORK'}/traffic_pattern";
+    mkpath("$target_dir",1,0755);
+    my @tasks=get_all_merged_tasks($self);
+    foreach my $p (@tasks) {    
+        #my $tile=$self->object_get_attribute("MAP_TILE",$p);
+        my $tile= get_task_give_tile($self,$p);
+        if ( $tile eq "-" ){
+            message_dialog("Error: unmapped task. Please map task $p to a tile", 'error' );
+            return;
+        }
+    }
+    #creat output file
     open(FILE,  ">$target_dir/$name.cfg") || die "Can not open: $!";
-	print FILE get_cfg_content($self);
-	close(FILE) || die "Error closing file: $!";
-	message_dialog("The traffic pattern is saved as $target_dir/$name.cfg" );
-	
+    print FILE get_cfg_content($self);
+    close(FILE) || die "Error closing file: $!";
+    message_dialog("The traffic pattern is saved as $target_dir/$name.cfg" );
 }
 
 sub get_cfg_content{
-	my $self=shift;
-	my $file="% source tile, destination tile, bytes, initial_weight, min_pck_size, max_pck_size, burst_size, injection_rate(%), injection_rate variation(%)\n";
-	
-
-	
-	my @tasks= get_trace_list($self,'merge');
-	my @traces= get_trace_list($self,'raw');
-	
-	foreach my $p (@traces){
-		my ($src_r,$dst_r, $Mbytes_r, $file_id_r, $file_name_r,$init_weight_r,$min_pck_r, $max_pck_r,  $burst_r, $injct_rate_r, $injct_rate_var_r)=get_trace($self,'raw',$p);
-				
-		
-		my $src =$self->get_item_group_name('grouping',$src_r);
-		my $dst =$self->get_item_group_name('grouping',$dst_r);
-	    if	($src eq  $dst){
-	    	# source-destination is merged to one tile so ommit it
-	    	next;
-	    	
-	    }else{	
-		
-			my $minpck = $self->object_get_attribute("raw_$p",'min_pck_size');
-			my $maxpck = $self->object_get_attribute("raw_$p",'max_pck_size');
-			my $avg_pck_size =($minpck+ $maxpck)/2;
-			my $pck_num = ($Mbytes_r*8) /($avg_pck_size*64);
-			$pck_num= 1 if($pck_num==0);
-			
-			my  $src_tile = tile_id_number(get_task_give_tile($self,"$src"));
-			my  $dst_tile = tile_id_number(get_task_give_tile($self,"$dst"));
-		
-			my $auto=$self->object_get_attribute('Auto','Auto_inject');
-		
-			my $bytes = $Mbytes_r * 1000000;
-		
-			$file=$file."$src_tile, $dst_tile, $bytes, $init_weight_r, $min_pck_r, $max_pck_r";
-			$file=$file.", $burst_r, $injct_rate_r, $injct_rate_var_r \n" if ($auto eq "1\'b0");
-			$file=$file." \n" if ($auto eq "1\'b1");
-			 		
-			
-	    }
-	}	
-	
-	
-	
-	return $file;
+    my $self=shift;
+    my $file="% source tile, destination tile, bytes, initial_weight, min_pck_size, max_pck_size, burst_size, injection_rate(%), injection_rate variation(%)\n";
+    my @tasks= get_trace_list($self,'merge');
+    my @traces= get_trace_list($self,'raw');
+    foreach my $p (@traces){
+        my ($src_r,$dst_r, $Mbytes_r, $file_id_r, $file_name_r,$init_weight_r,$min_pck_r, $max_pck_r,  $burst_r, $injct_rate_r, $injct_rate_var_r)=get_trace($self,'raw',$p);
+        my $src =$self->get_item_group_name('grouping',$src_r);
+        my $dst =$self->get_item_group_name('grouping',$dst_r);
+        if    ($src eq  $dst){
+            # source-destination is merged to one tile so ommit it
+            next;
+        }else{    
+            my $minpck = $self->object_get_attribute("raw_$p",'min_pck_size');
+            my $maxpck = $self->object_get_attribute("raw_$p",'max_pck_size');
+            my $avg_pck_size =($minpck+ $maxpck)/2;
+            my $pck_num = ($Mbytes_r*8) /($avg_pck_size*64);
+            $pck_num= 1 if($pck_num==0);
+            my  $src_tile = tile_id_number(get_task_give_tile($self,"$src"));
+            my  $dst_tile = tile_id_number(get_task_give_tile($self,"$dst"));
+            my $auto=$self->object_get_attribute('Auto','Auto_inject');
+            my $bytes = $Mbytes_r * 1000000;
+            $file=$file."$src_tile, $dst_tile, $bytes, $init_weight_r, $min_pck_r, $max_pck_r";
+            $file=$file.", $burst_r, $injct_rate_r, $injct_rate_var_r \n" if ($auto eq "1\'b0");
+            $file=$file." \n" if ($auto eq "1\'b1");
+        }
+    }    
+    return $file;
 }
 
 
 
 sub add_trace{
-	my ($self, $file_id,$category,$trace_id, $source,$dest, $Mbytes, $file_name,$src_port,$dst_port,$buff_size,$chanel,$vc,$class)=@_;	
-	$self->object_add_attribute("${category}_$trace_id",'file',$file_id);
-	$self->object_add_attribute("${category}_$trace_id",'source',"${source}");
-	$self->object_add_attribute("${category}_$trace_id",'destination',"${dest}");
-	$self->object_add_attribute("${category}_$trace_id",'Mbytes', $Mbytes);
-	$self->object_add_attribute("${category}_$trace_id",'file_name', $file_name);  
-	$self->object_add_attribute("${category}_$trace_id",'selected', 0); 
-	$self->object_add_attribute("${category}_$trace_id",'init_weight', 1); 
-	$self->object_add_attribute("${category}_$trace_id",'scr_port',$src_port);
-	$self->object_add_attribute("${category}_$trace_id",'dst_port',$dst_port);	
-	$self->object_add_attribute("${category}_$trace_id",'buff_size',$buff_size);	
-	$self->object_add_attribute("${category}_$trace_id",'chanel',$chanel);
-	$self->object_add_attribute("${category}_$trace_id",'vc',$vc);
-	$self->object_add_attribute("${category}_$trace_id",'class',$class);					
-	$self->{"${category}_traces"}{$trace_id}=1;
-	
+    my ($self, $file_id,$category,$trace_id, $source,$dest, $Mbytes, $file_name,$src_port,$dst_port,$buff_size,$chanel,$vc,$class)=@_;    
+    $self->object_add_attribute("${category}_$trace_id",'file',$file_id);
+    $self->object_add_attribute("${category}_$trace_id",'source',"${source}");
+    $self->object_add_attribute("${category}_$trace_id",'destination',"${dest}");
+    $self->object_add_attribute("${category}_$trace_id",'Mbytes', $Mbytes);
+    $self->object_add_attribute("${category}_$trace_id",'file_name', $file_name);  
+    $self->object_add_attribute("${category}_$trace_id",'selected', 0); 
+    $self->object_add_attribute("${category}_$trace_id",'init_weight', 1); 
+    $self->object_add_attribute("${category}_$trace_id",'scr_port',$src_port);
+    $self->object_add_attribute("${category}_$trace_id",'dst_port',$dst_port);    
+    $self->object_add_attribute("${category}_$trace_id",'buff_size',$buff_size);    
+    $self->object_add_attribute("${category}_$trace_id",'chanel',$chanel);
+    $self->object_add_attribute("${category}_$trace_id",'vc',$vc);
+    $self->object_add_attribute("${category}_$trace_id",'class',$class);                    
+    $self->{"${category}_traces"}{$trace_id}=1;
 }
 
 sub add_trace_extra {
-	my ($self, $file_id,$category,$trace_id,$min_pck, $max_pck,$burst, $injct_rate, $injct_rate_var)=@_;
-	$self->object_add_attribute("${category}_$trace_id",'min_pck_size',$min_pck);
-	$self->object_add_attribute("${category}_$trace_id",'max_pck_size',$max_pck);
-	$self->object_add_attribute("${category}_$trace_id",'burst_size',$burst); 
-	$self->object_add_attribute("${category}_$trace_id",'injct_rate',$injct_rate);	
-	$self->object_add_attribute("${category}_$trace_id",'injct_rate_var',$injct_rate_var);	
-}	
-
+    my ($self, $file_id,$category,$trace_id,$min_pck, $max_pck,$burst, $injct_rate, $injct_rate_var)=@_;
+    $self->object_add_attribute("${category}_$trace_id",'min_pck_size',$min_pck);
+    $self->object_add_attribute("${category}_$trace_id",'max_pck_size',$max_pck);
+    $self->object_add_attribute("${category}_$trace_id",'burst_size',$burst); 
+    $self->object_add_attribute("${category}_$trace_id",'injct_rate',$injct_rate);    
+    $self->object_add_attribute("${category}_$trace_id",'injct_rate_var',$injct_rate_var);    
+}    
 
 sub remove_trace{
-	my ($self,$category, $trace_id)=@_;
-	delete $self->{"${category}_$trace_id"};	
-	delete $self->{"${category}_traces"}{$trace_id};
+    my ($self,$category, $trace_id)=@_;
+    delete $self->{"${category}_$trace_id"};    
+    delete $self->{"${category}_traces"}{$trace_id};
 }
 
 sub get_trace_list{
-	my ($self,$category)=@_;
-	#print "($self,$category)\n";
-	return sort (keys %{$self->{"${category}_traces"}});	
+    my ($self,$category)=@_;
+    #print "($self,$category)\n";
+    return sort (keys %{$self->{"${category}_traces"}});    
 }
 
 sub remove_all_traces{
-	my ($self,$category)=@_;
-	my @all =get_trace_list($self,$category);
-	foreach my $trace_id (@all ){
-		remove_trace ($self,$category, $trace_id);
-	}
+    my ($self,$category)=@_;
+    my @all =get_trace_list($self,$category);
+    foreach my $trace_id (@all ){
+        remove_trace ($self,$category, $trace_id);
+    }
 }
 
-
 sub get_trace{
-	my ($self,$category,$trace_id)=@_;	
-	my $file_id		= $self->object_get_attribute("${category}_$trace_id",'file');
-	my $source 		= $self->object_get_attribute("${category}_$trace_id",'source');
-	my $dest		= $self->object_get_attribute("${category}_$trace_id",'destination');
-	my $Mbytes  	= $self->object_get_attribute("${category}_$trace_id",'Mbytes');
-	my $file_name	= $self->object_get_attribute("${category}_$trace_id",'file_name');	
-	my $init_weight = $self->object_get_attribute("${category}_$trace_id",'init_weight'); 
-	my $min_pck_size= $self->object_get_attribute("${category}_$trace_id",'min_pck_size');
-	my $max_pck_size= $self->object_get_attribute("${category}_$trace_id",'max_pck_size');
-	my $burst_size	= $self->object_get_attribute("${category}_$trace_id",'burst_size'); 
-	my $injct_rate  = $self->object_get_attribute("${category}_$trace_id",'injct_rate');	
-	my $injct_rate_var = $self->object_get_attribute("${category}_$trace_id",'injct_rate_var');	
-	my $src_port = $self->object_get_attribute("${category}_$trace_id",'scr_port');
-	my $dst_port = $self->object_get_attribute("${category}_$trace_id",'dst_port');
-	my $buff_size= $self->object_get_attribute("${category}_$trace_id",'buff_size');
-	my $chanel = $self->object_get_attribute("${category}_$trace_id",'chanel');
-	my $vc= $self->object_get_attribute("${category}_$trace_id",'vc');	
-	my $class= $self->object_get_attribute("${category}_$trace_id",'class');	  
-	return ($source,$dest, $Mbytes, $file_id,$file_name,$init_weight,$min_pck_size, $max_pck_size, $burst_size, $injct_rate, $injct_rate_var, $src_port,$dst_port,$buff_size,$chanel,$vc,$class);	
+    my ($self,$category,$trace_id)=@_;    
+    my $file_id  = $self->object_get_attribute("${category}_$trace_id",'file');
+    my $source   = $self->object_get_attribute("${category}_$trace_id",'source');
+    my $dest     = $self->object_get_attribute("${category}_$trace_id",'destination');
+    my $Mbytes   = $self->object_get_attribute("${category}_$trace_id",'Mbytes');
+    my $file_name  = $self->object_get_attribute("${category}_$trace_id",'file_name');    
+    my $init_weight = $self->object_get_attribute("${category}_$trace_id",'init_weight'); 
+    my $min_pck_size = $self->object_get_attribute("${category}_$trace_id",'min_pck_size');
+    my $max_pck_size = $self->object_get_attribute("${category}_$trace_id",'max_pck_size');
+    my $burst_size  = $self->object_get_attribute("${category}_$trace_id",'burst_size'); 
+    my $injct_rate  = $self->object_get_attribute("${category}_$trace_id",'injct_rate');    
+    my $injct_rate_var = $self->object_get_attribute("${category}_$trace_id",'injct_rate_var');    
+    my $src_port = $self->object_get_attribute("${category}_$trace_id",'scr_port');
+    my $dst_port = $self->object_get_attribute("${category}_$trace_id",'dst_port');
+    my $buff_size= $self->object_get_attribute("${category}_$trace_id",'buff_size');
+    my $chanel = $self->object_get_attribute("${category}_$trace_id",'chanel');
+    my $vc= $self->object_get_attribute("${category}_$trace_id",'vc');    
+    my $class= $self->object_get_attribute("${category}_$trace_id",'class');      
+    return ($source,$dest, $Mbytes, $file_id,$file_name,$init_weight,$min_pck_size, $max_pck_size, $burst_size, $injct_rate, $injct_rate_var, $src_port,$dst_port,$buff_size,$chanel,$vc,$class);    
 }
 
 sub get_all_tasks{
-	my ($self,$category)=@_;
-	my @traces= get_trace_list($self,$category);
-	my @x;
-	foreach my $p (@traces){
-		my ($src,$dst, $Mbytes, $file_id, $file_name)=get_trace($self,$category,$p);
-		push(@x,$src);
-		push(@x,$dst);		
-	}
-	my @x2 =  uniq(sort  @x) if (scalar @x);
-	return @x2;	
+    my ($self,$category)=@_;
+    my @traces= get_trace_list($self,$category);
+    my @x;
+    foreach my $p (@traces){
+        my ($src,$dst, $Mbytes, $file_id, $file_name)=get_trace($self,$category,$p);
+        push(@x,$src);
+        push(@x,$dst);        
+    }
+    my @x2 =  uniq(sort  @x) if (scalar @x);
+    return @x2;    
 }
 
-
 sub remove_mapping{
-	my $self=shift;
-	$self->object_add_attribute('MAP_TASK',undef,undef);
-	$self->object_add_attribute('mapping',undef,undef); 
-	#$self->object_add_attribute('MAP_TILE',undef,undef);
+    my $self=shift;
+    $self->object_add_attribute('MAP_TASK',undef,undef);
+    $self->object_add_attribute('mapping',undef,undef); 
+    #$self->object_add_attribute('MAP_TILE',undef,undef);
 }
 
-
-
 sub remove_nlock_mapping{
-	my $self=shift;
-	my @tasks=get_all_merged_tasks($self);
-	
-	foreach my $p (@tasks){
-		my $lock=$self->object_get_attribute("MAP_LOCK",$p);
-		$lock = 0 if (!defined $lock);
-		if($lock == 0){
-			#my $tile=$self->object_get_attribute("MAP_TILE",$p);
-			my $tile=get_task_give_tile($self,$p);
-			#$self->object_add_attribute("MAP_TILE",$p,undef);
-			$self->object_add_attribute("MAP_TASK",$tile,undef);
-			$self->object_add_attribute("mapping",$tile,undef);
-			
-			
-		}		
-	}	
+    my $self=shift;
+    my @tasks=get_all_merged_tasks($self);
+    foreach my $p (@tasks){
+        my $lock=$self->object_get_attribute("MAP_LOCK",$p);
+        $lock = 0 if (!defined $lock);
+        if($lock == 0){
+            #my $tile=$self->object_get_attribute("MAP_TILE",$p);
+            my $tile=get_task_give_tile($self,$p);
+            #$self->object_add_attribute("MAP_TILE",$p,undef);
+            $self->object_add_attribute("MAP_TASK",$tile,undef);
+            $self->object_add_attribute("mapping",$tile,undef);
+        }        
+    }    
 }
 
 
 sub get_nlock_tasks {
-	#my ($self,$taskref,$tileref)=shift;
-	my $self=shift;
-	my @unluck_tasks;
-	my @tasks=get_all_merged_tasks($self);
-	
-	foreach my $p (@tasks){
-		my $lock=$self->object_get_attribute("MAP_LOCK",$p);
-		$lock = 0 if (!defined $lock);
-		if($lock == 0){
-			push(@unluck_tasks,$p);
-		}
-	
-	}
-	return  @unluck_tasks;	
+    #my ($self,$taskref,$tileref)=shift;
+    my $self=shift;
+    my @unluck_tasks;
+    my @tasks=get_all_merged_tasks($self);
+    foreach my $p (@tasks){
+        my $lock=$self->object_get_attribute("MAP_LOCK",$p);
+        $lock = 0 if (!defined $lock);
+        if($lock == 0){
+            push(@unluck_tasks,$p);
+        }
+    }
+    return  @unluck_tasks;    
 }
 
 sub get_nlock_tiles {
-	#my ($self,$taskref,$tileref)=shift;
-	my $self=shift;
-	my @luck_tiles;
-	my @tasks=get_all_merged_tasks($self);
-	
-	foreach my $task (@tasks){
-		my $lock=$self->object_get_attribute("MAP_LOCK",$task);
-		$lock = 0 if (!defined $lock);
-		if($lock == 1){
-			#my $tile=$self->object_get_attribute('MAP_TILE',"$task");
-			my $tile=get_task_give_tile($self,"$task");
-			push(@luck_tiles,$tile);
-		}
-	
-	}
-	my @tiles=get_tiles_name($self);
-	
-	#a-b
-	return get_diff_array(\@tiles,\@luck_tiles);	
+    #my ($self,$taskref,$tileref)=shift;
+    my $self=shift;
+    my @luck_tiles;
+    my @tasks=get_all_merged_tasks($self);
+    foreach my $task (@tasks){
+        my $lock=$self->object_get_attribute("MAP_LOCK",$task);
+        $lock = 0 if (!defined $lock);
+        if($lock == 1){
+            #my $tile=$self->object_get_attribute('MAP_TILE',"$task");
+            my $tile=get_task_give_tile($self,"$task");
+            push(@luck_tiles,$tile);
+        }
+    }
+    my @tiles=get_tiles_name($self);
+    #a-b
+    return get_diff_array(\@tiles,\@luck_tiles);    
 }
 
 
 sub get_locked_map {
-	my $self=shift;
-	my %map; 
-	my @tasks=get_all_merged_tasks($self);
-	
-	foreach my $task (@tasks){
-		my $lock=$self->object_get_attribute("MAP_LOCK",$task);
-		
-		$lock = 0 if (!defined $lock);
-		if($lock == 1){
-			#my $tile=$self->object_get_attribute('MAP_TILE',"$task");
-			my $tile=get_task_give_tile($self,"$task");
-			$map{$task}=$tile;
-		}
-	
-	}
-	return  %map;	
+    my $self=shift;
+    my %map; 
+    my @tasks=get_all_merged_tasks($self);
+    foreach my $task (@tasks){
+        my $lock=$self->object_get_attribute("MAP_LOCK",$task);
+        $lock = 0 if (!defined $lock);
+        if($lock == 1){
+            #my $tile=$self->object_get_attribute('MAP_TILE',"$task");
+            my $tile=get_task_give_tile($self,"$task");
+            $map{$task}=$tile;
+        }
+    }
+    return  %map;    
 }
 
 
 #########
-#	Mapping algorithm
+#    Mapping algorithm
 #########
 sub random_map{
-	my $self=shift;
-		
-	
-	
-	my $nx=$self->object_get_attribute('noc_param','T1');
-	my $ny=$self->object_get_attribute('noc_param','T2');
-	my $nc= $nx * $ny;
-	
-	
-	
-	my @tasks=get_nlock_tasks($self);	
-	my @tiles=get_nlock_tiles($self);	
-	$self->remove_nlock_mapping() ;
-	
-	
-	my @rnd= shuffle @tiles;
-	
-	my $i=0;
-	foreach my $task (@tasks){
-		if($i>=scalar @rnd){
-			last;
-		};
-		my $tile=$rnd[$i];
-		#$self->object_add_attribute('MAP_TILE',"$task",$tile);
-		$self->object_add_attribute('MAP_TASK',"$tile",$task);
-		my @l=($task);
-		$self->object_add_attribute("mapping","$tile",\@l); 
-		
-		$i++;	
-		
-	}
-	
-	set_gui_status($self,"ref",1);
-	
+    my $self=shift;
+    my $nx=$self->object_get_attribute('noc_param','T1');
+    my $ny=$self->object_get_attribute('noc_param','T2');
+    my $nc= $nx * $ny;
+    my @tasks=get_nlock_tasks($self);    
+    my @tiles=get_nlock_tiles($self);    
+    $self->remove_nlock_mapping() ;
+    my @rnd= shuffle @tiles;
+    my $i=0;
+    foreach my $task (@tasks){
+        if($i>=scalar @rnd){
+            last;
+        };
+        my $tile=$rnd[$i];
+        #$self->object_add_attribute('MAP_TILE',"$task",$tile);
+        $self->object_add_attribute('MAP_TASK',"$tile",$task);
+        my @l=($task);
+        $self->object_add_attribute("mapping","$tile",\@l); 
+        $i++;    
+    }
+    set_gui_status($self,"ref",1);
 }
 
 sub direct_map {
-	my $self=shift;
-	
-	
-	my @tasks=get_nlock_tasks($self);	
-	my @tiles=get_nlock_tiles($self);	
-	$self->remove_nlock_mapping() ;
-	
-	my @sort_tiles;
-	my %tilenum;
-	foreach my $tile (@tiles){
-		#my ($x,$y)=tile_id_to_loc($tile);
-		#my $id= $y*$nx+$x;
-		my $id=tile_id_number($tile);
-		$tilenum{$id}=$tile;
-	}
-	
-	foreach my $id  (sort  {$a <=> $b} keys %tilenum){
-		
-		push(@sort_tiles, $tilenum{$id});
-	}
-	
-	
-	my @sort_tasks = sort @tasks;
-	
-	
-	my $i=0;
-	foreach my $task (@sort_tasks){
-		if($i>=scalar @sort_tiles){
-			last;
-		};
-		my $tile=$sort_tiles[$i];
-		#$self->object_add_attribute('MAP_TILE',"$task",$tile);
-		$self->object_add_attribute('MAP_TASK',"$tile",$task);
-		my @l = ($task);
-		$self->object_add_attribute("mapping","$tile",\@l); 
-	
-		$i++;	
-		
-	}
-	
-	set_gui_status($self,"ref",1);
-	
-	
+    my $self=shift;
+    my @tasks=get_nlock_tasks($self);    
+    my @tiles=get_nlock_tiles($self);    
+    $self->remove_nlock_mapping() ;
+    my @sort_tiles;
+    my %tilenum;
+    foreach my $tile (@tiles){
+        #my ($x,$y)=tile_id_to_loc($tile);
+        #my $id= $y*$nx+$x;
+        my $id=tile_id_number($tile);
+        $tilenum{$id}=$tile;
+    }
+    
+    foreach my $id  (sort  {$a <=> $b} keys %tilenum){
+        
+        push(@sort_tiles, $tilenum{$id});
+    }
+    
+    my @sort_tasks = sort @tasks;
+    my $i=0;
+    foreach my $task (@sort_tasks){
+        if($i>=scalar @sort_tiles){
+            last;
+        };
+        my $tile=$sort_tiles[$i];
+        #$self->object_add_attribute('MAP_TILE',"$task",$tile);
+        $self->object_add_attribute('MAP_TASK',"$tile",$task);
+        my @l = ($task);
+        $self->object_add_attribute("mapping","$tile",\@l); 
+        $i++;    
+    }
+    set_gui_status($self,"ref",1);
 }
 
 
 sub get_task_give_tile{
-	my ($self,$task)=@_;
-	my @tiles=get_tiles_name($self);
-	foreach my $p (@tiles){
-		my $r=$self->object_get_attribute("mapping","$p");
-		
-		my @l=@{$r} if(defined $r); 		
-		if(defined $l[0] ){
-			return $p	if($l[0] eq $task );
-		}		
-	}	
-	return undef;
+    my ($self,$task)=@_;
+    my @tiles=get_tiles_name($self);
+    foreach my $p (@tiles){
+        my $r=$self->object_get_attribute("mapping","$p");
+        my @l=@{$r} if(defined $r);         
+        if(defined $l[0] ){
+            return $p    if($l[0] eq $task );
+        }        
+    }    
+    return undef;
 }
 
-	
 sub network_3dim_cal{
-	my $n_tasks= shift;
-	
-	my $dim_x = floor($n_tasks**(1/3));
-	
-	my ($dim_y,$dim_z)=network_dim_cal(ceil($n_tasks/$dim_x));
-	 
-	
-	
-	return ($dim_x,$dim_y,$dim_z);
-
-	
-}	
-	
-
-
-
+    my $n_tasks= shift;
+    my $dim_x = floor($n_tasks**(1/3));
+    my ($dim_y,$dim_z)=network_dim_cal(ceil($n_tasks/$dim_x));
+    return ($dim_x,$dim_y,$dim_z);
+}    
 
 sub network_dim_cal{
-	my $n_tasks= shift;
-	 
-	my $dim_y = floor(sqrt($n_tasks));
-
-	my $dim_x = ceil($n_tasks/$dim_y);
-	
-	return ($dim_x,$dim_y);
-
-	#cout << "dim_x = " << dim_x << "; dim_y = " << dim_y << endl;
+    my $n_tasks= shift;
+    my $dim_y = floor(sqrt($n_tasks));
+    my $dim_x = ceil($n_tasks/$dim_y);
+    return ($dim_x,$dim_y);
+    #cout << "dim_x = " << dim_x << "; dim_y = " << dim_y << endl;
 }
 
-
 sub get_tiles_name{
-	my $self=shift;
-	my @tiles;
+    my $self=shift;
+    my @tiles;
     my ($NE, $NR, $RAw, $EAw, $Fw)=get_topology_info($self);
     #print " my ($NE, $NR, $RAw, $EAw, $Fw)=get_topology_info($self)\n";
-	for (my $tile_num=0;$tile_num<$NE;$tile_num++){
-		push(@tiles,"tile($tile_num)");	
-	}	
-	
-	return @tiles;	
+    for (my $tile_num=0;$tile_num<$NE;$tile_num++){
+        push(@tiles,"tile($tile_num)");    
+    }    
+    return @tiles;    
 }
 
-
 sub tile_id_number{
-	my $tile=shift;
-	my ($x) =  $tile =~ /(\d+)/g;  
-	return $x;
+    my $tile=shift;
+    my ($x) =  $tile =~ /(\d+)/g;  
+    return $x;
 }
 
-
-
 sub get_communication_task{
-	my ($self,$category)=@_;
-	my %com_tasks;
-	my @tasks=get_all_merged_tasks($self);
-	my @traces= get_trace_list($self,'raw');
-	
-
-	
-	foreach my $p (@tasks){
-		$com_tasks{$p}{'total'}= 0;
-	
-		foreach my $q (@tasks){
-			$com_tasks{$p}{$q}= 0;
-		
-		}
-	}
-	
-	foreach my $p (@traces){
-		my ($src,$dst, $Mbytes, $file_id, $file_name)=get_trace($self,'raw',$p);
-		$src =$self->get_item_group_name('grouping',$src);
-		$dst =$self->get_item_group_name('grouping',$dst);
-	    if	($src eq  $dst){
-	    	$com_tasks{$src}{'internal'} += $Mbytes;
-	    	
-	    }else{	
-		
-			$com_tasks{$src}{'sent'} += $Mbytes;
-			$com_tasks{$dst}{'rsv'} += $Mbytes;
-			
-			$com_tasks{$src}{'total'} += $Mbytes;
-			$com_tasks{$dst}{'total'} += $Mbytes;
-			$com_tasks{$src}{$dst} += $Mbytes;
-			$com_tasks{$file_id}{'maxsent'} = $com_tasks{$src}{'sent'} if(!defined $com_tasks{$file_id}{'maxsent'});
-			$com_tasks{$file_id}{'maxsent'} = $com_tasks{$src}{'sent'} if( $com_tasks{$file_id}{'maxsent'}<$com_tasks{$src}{'sent'});
-			
-			
-			
-			my $minpck = $self->object_get_attribute("raw_$p",'min_pck_size');
-			my $maxpck = $self->object_get_attribute("raw_$p",'max_pck_size');
-			my $avg_pck_size =($minpck+ $maxpck)/2;
-			my $pck_num = ($Mbytes*8) /($avg_pck_size*64);
-			$pck_num= 1 if($pck_num==0); 		
-			$com_tasks{$src}{'min_pck_num'} =$pck_num if(!defined $com_tasks{$src}{'min_pck_num'}); 
-			$com_tasks{$src}{'min_pck_num'} =$pck_num if( $com_tasks{$src}{'min_pck_num'} > $pck_num); 
-	    }
-		
-	}
-	return %com_tasks;
-}	
+    my ($self,$category)=@_;
+    my %com_tasks;
+    my @tasks=get_all_merged_tasks($self);
+    my @traces= get_trace_list($self,'raw');
+    foreach my $p (@tasks){
+        $com_tasks{$p}{'total'}= 0;
+        foreach my $q (@tasks){
+            $com_tasks{$p}{$q}= 0;
+        }
+    }
+    
+    foreach my $p (@traces){
+        my ($src,$dst, $Mbytes, $file_id, $file_name)=get_trace($self,'raw',$p);
+        $src =$self->get_item_group_name('grouping',$src);
+        $dst =$self->get_item_group_name('grouping',$dst);
+        if    ($src eq  $dst){
+            $com_tasks{$src}{'internal'} += $Mbytes;
+        }else{    
+            $com_tasks{$src}{'sent'} += $Mbytes;
+            $com_tasks{$dst}{'rsv'} += $Mbytes;
+            $com_tasks{$src}{'total'} += $Mbytes;
+            $com_tasks{$dst}{'total'} += $Mbytes;
+            $com_tasks{$src}{$dst} += $Mbytes;
+            $com_tasks{$file_id}{'maxsent'} = $com_tasks{$src}{'sent'} if(!defined $com_tasks{$file_id}{'maxsent'});
+            $com_tasks{$file_id}{'maxsent'} = $com_tasks{$src}{'sent'} if( $com_tasks{$file_id}{'maxsent'}<$com_tasks{$src}{'sent'});
+            my $minpck = $self->object_get_attribute("raw_$p",'min_pck_size');
+            my $maxpck = $self->object_get_attribute("raw_$p",'max_pck_size');
+            my $avg_pck_size =($minpck+ $maxpck)/2;
+            my $pck_num = ($Mbytes*8) /($avg_pck_size*64);
+            $pck_num= 1 if($pck_num==0);         
+            $com_tasks{$src}{'min_pck_num'} =$pck_num if(!defined $com_tasks{$src}{'min_pck_num'}); 
+            $com_tasks{$src}{'min_pck_num'} =$pck_num if( $com_tasks{$src}{'min_pck_num'} > $pck_num); 
+        }
+    }
+    return %com_tasks;
+}    
 
 
 sub find_max_neighbor_tile_old{
-	my $self=shift;
-	#Select the tile located in center as the max-neighbor if its not locked for any other task
-	my ($NE,$NR) = get_topology_info($self);
-	
-	my $ne_mid = floor($NE/2);
-	print "$ne_mid = $ne_mid\n";
-	
-	
-	#my $centered_tile= get_tile_name($self,$x_mid ,$y_mid);
-	#Select the tile located in center as the max-neighbor if its not locked for any other task
-	#therwise select the tile with the min manhatan distance to center tile
-	my @tiles=get_nlock_tiles($self);
-	my $min=1000000;
-	my $max_neighbors_tile_id;
-	foreach my $tile (@tiles){
-		#my ($x,$y)=tile_id_to_loc($tile);
-		my $tile_num = tile_id_number($tile);
-		my $mah_distance=get_endpoints_mah_distance($self,$ne_mid,$tile_num);
-		
-		if($min > $mah_distance ){
-			$min = $mah_distance;
-			$max_neighbors_tile_id=$tile;
-		}
-		
-	} 	
-
-	return $max_neighbors_tile_id;
-}	
-	
-	
-sub find_max_neighbor_tile{
-	my $self=shift;
-	#Select the tile with the list manhatan distance from all endpoints
-	my ($NE,$NR) = get_topology_info($self);
-	my $min_manth_dist_acum;
-	my $max_neighbors_tile_id;
-	
-	for (my $i=0; $i<$NE; $i++){
-		my $c=0;
-		for (my $j=0; $j<$NE; $j++){
-			next if($i==$j);
-			my $d=get_endpoints_mah_distance($self,$i,$j);
-			$c+=$d*$d;			
-		}
-		$min_manth_dist_acum=$c if(!defined $min_manth_dist_acum);
-		if($c <= $min_manth_dist_acum){
-			$min_manth_dist_acum=$c;
-			$max_neighbors_tile_id="tile($i)";
-		}
-		
-	}
-	
-
-	return $max_neighbors_tile_id;
-}		
-	
-	
-	
-sub find_min_neighbor_tile	{
-	my $self=shift;
-
-	my $ne_mid = 0;
-
-	#my $centered_tile= get_tile_name($self,$x_mid ,$y_mid);
-	#Select the tile located in center as the max-neighbor if its not locked for any other task
-	#otherwise select the tile with the min Manhattan distance to center tile
-	my @tiles=get_nlock_tiles($self);
-	my $min=1000000;
-	my $min_neighbors_tile_id;
-	foreach my $tile (@tiles){
-		#my ($x,$y)=tile_id_to_loc($tile);
-		my $tile_num = tile_id_number($tile);
-		my $mah_distance=get_endpoints_mah_distance($self,$ne_mid,$tile_num );
-		if($min > $mah_distance ){
-			$min = $mah_distance;
-			$min_neighbors_tile_id=$tile;
-		}
-		
-	} 	
-
-	return $min_neighbors_tile_id;
-}	
-	
+    my $self=shift;
+    #Select the tile located in center as the max-neighbor if its not locked for any other task
+    my ($NE,$NR) = get_topology_info($self);
+    my $ne_mid = floor($NE/2);
+    print "$ne_mid = $ne_mid\n";
+    #my $centered_tile= get_tile_name($self,$x_mid ,$y_mid);
+    #Select the tile located in center as the max-neighbor if its not locked for any other task
+    #therwise select the tile with the min manhatan distance to center tile
+    my @tiles=get_nlock_tiles($self);
+    my $min=1000000;
+    my $max_neighbors_tile_id;
+    foreach my $tile (@tiles){
+        #my ($x,$y)=tile_id_to_loc($tile);
+        my $tile_num = tile_id_number($tile);
+        my $mah_distance=get_endpoints_mah_distance($self,$ne_mid,$tile_num);
+        if($min > $mah_distance ){
+            $min = $mah_distance;
+            $max_neighbors_tile_id=$tile;
+        }
+    }     
+    return $max_neighbors_tile_id;
+}    
 
+sub find_max_neighbor_tile{
+    my $self=shift;
+    #Select the tile with the list manhatan distance from all endpoints
+    my ($NE,$NR) = get_topology_info($self);
+    my $min_manth_dist_acum;
+    my $max_neighbors_tile_id;
+    for (my $i=0; $i<$NE; $i++){
+        my $c=0;
+        for (my $j=0; $j<$NE; $j++){
+            next if($i==$j);
+            my $d=get_endpoints_mah_distance($self,$i,$j);
+            $c+=$d*$d;            
+        }
+        $min_manth_dist_acum=$c if(!defined $min_manth_dist_acum);
+        if($c <= $min_manth_dist_acum){
+            $min_manth_dist_acum=$c;
+            $max_neighbors_tile_id="tile($i)";
+        }
+        
+    }
+    return $max_neighbors_tile_id;
+}        
+
+sub find_min_neighbor_tile    {
+    my $self=shift;
+    my $ne_mid = 0;
+    #my $centered_tile= get_tile_name($self,$x_mid ,$y_mid);
+    #Select the tile located in center as the max-neighbor if its not locked for any other task
+    #otherwise select the tile with the min Manhattan distance to center tile
+    my @tiles=get_nlock_tiles($self);
+    my $min=1000000;
+    my $min_neighbors_tile_id;
+    foreach my $tile (@tiles){
+        #my ($x,$y)=tile_id_to_loc($tile);
+        my $tile_num = tile_id_number($tile);
+        my $mah_distance=get_endpoints_mah_distance($self,$ne_mid,$tile_num );
+        if($min > $mah_distance ){
+            $min = $mah_distance;
+            $min_neighbors_tile_id=$tile;
+        }
+    }     
+    return $min_neighbors_tile_id;
+}
 
 sub nmap_algorithm{
-	my $self=shift;	
-	my $nx=$self->object_get_attribute('noc_param','T1');
-	my $ny=$self->object_get_attribute('noc_param','T2');
-	my $nc= $nx * $ny;
-	
-	my @tasks=get_all_merged_tasks($self);
-	my @tiles= get_tiles_name($self);	
-	my $n_tasks = scalar  @tasks;
-	
-	
-	my @unmapped_tasks_set=@tasks; # unmapped set of tasks
-	my @unallocated_tiles_set=@tiles;	# tile ids which are not allocated yet
-	
-#	print "@unmapped_tasks_set *** @unallocated_tiles_set\n";
-	
-	
-	#------ step 1: find the task with highest weighted communication volume
-	# find the max of com_vol
-	# consider all incoming and outgoing connections of each tasks
-	
-	my %com_tasks= $self->get_communication_task('merge');
-	#print  Data::Dumper->Dump([\%com_tasks],['mpsoc']);	
-	
-	my $max_com_task;
-	my $max_com =0;
-	foreach my $p (sort keys %com_tasks){
-		#print "**$p\n";
-		if(defined $com_tasks{$p}{'total'}){
-		if ($com_tasks{$p}{'total'} >$max_com){
-			$max_com = $com_tasks{$p}{'total'};
-			$max_com_task = $p;
-		}}
-	}
-	
-	#print "m=$max_com 	t=$max_com_task\n";
-	
-	
-	#------ step 2: find the tile with max number of neighbors
-	# normally, this tile is in the middle of the array
-	my $max_neighbors_tile_id = find_max_neighbor_tile($self);
-	
-	print "\$max_neighbors_tile_id = $max_neighbors_tile_id\n";
-	
-	
-	
-	my %map=get_locked_map ($self);	
-	$self->remove_nlock_mapping();
-	foreach my $mapped_task (sort keys %map){
-			my $mapped_tile=$map{$mapped_task};
-			@unmapped_tasks_set=remove_scolar_from_array(\@unmapped_tasks_set,$mapped_task);
-			@unallocated_tiles_set=remove_scolar_from_array(\@unallocated_tiles_set,$mapped_tile);
-	}
-		
-	
-	
-	
-	# add this task with highest weighted communication volume to the mapped task set
-	#push(@mapped_tasks_set,$max_com_task);
-	#task_mapping[max_com_task] = max_neighbors_tile_id;
-	
-	if(!defined $map{$max_com_task}){
-		$map{$max_com_task}=$max_neighbors_tile_id;
-		@unmapped_tasks_set=remove_scolar_from_array(\@unmapped_tasks_set,$max_com_task);
-		@unallocated_tiles_set=remove_scolar_from_array(\@unallocated_tiles_set,$max_neighbors_tile_id);
-	}
-
-
-
-	#------ step 3: map all unmapped tasks
-	while(scalar @unmapped_tasks_set){
-		$max_com =0;
-		my $max_com_unmapped_task;
-		my $max_overall_com=0;
-		#--------- step 3.1:
-		# find the unmapped task which communicates most with mapped_tasks_set
-		# among many tasks which have the same communication volume with mapped_tasks,
-		# choose the task with highest communication volume with others
-		
-		foreach my $unmapped_task (@unmapped_tasks_set){
-			
-			my $com_vol=0;
-			foreach my $mapped_task (sort keys %map){
-				$com_vol += $com_tasks{$unmapped_task}{$mapped_task};
-				$com_vol += $com_tasks{$mapped_task}{$unmapped_task};
-			}
-			
-			my $overall_com_vol = 0;
-			foreach my $p (@tasks){
-				$overall_com_vol += $com_tasks{$unmapped_task}{$p};
-				$overall_com_vol += $com_tasks{$p}{$unmapped_task};
-			}
-			
-			
-			if ($com_vol > $max_com){
-				$max_com = $com_vol;
-				$max_com_unmapped_task = $unmapped_task;
-				$max_overall_com = $overall_com_vol;
-			}
-			elsif ($com_vol == $max_com){ # choose if it have higher comm volume
-				if ($overall_com_vol > $max_overall_com){
-					$max_com_unmapped_task = $unmapped_task;
-					$max_overall_com = $overall_com_vol;
-				}
-			}
-		}#foreach my $unmapped_task (@unmapped_tasks_set)
-
-		#--------- step 3.2, find the unallocated tile with lowest communication cost to/from allocated_tile_set
-		my $min_com_cost;
-		my $min_com_cost_tile_id;
-		
-		
-		foreach my $unallocated_tile(@unallocated_tiles_set){
-			my $com_cost = 0;
-			#my ($unallocated_x,$unallocated_y)=tile_id_to_loc($unallocated_tile);
-			my $unallocated_tile_num = tile_id_number($unallocated_tile);
-			# scan all mapped tasks
-			foreach my $mapped_task (sort keys %map){
-				# get location of this mapped task
-				my $mapped_tile=$map{$mapped_task};
-				#my ($allocated_x,$allocated_y)=tile_id_to_loc($mapped_tile);
-				my $mapped_tile_num = tile_id_number($mapped_tile);				
-				# mahattan distance of 2 tiles
-				my $mah_distance=get_endpoints_mah_distance($self,$unallocated_tile_num,$mapped_tile_num);
-				
-
-				$com_cost += $com_tasks{$max_com_unmapped_task}{$mapped_task} * $mah_distance;
-				$com_cost += $com_tasks{$mapped_task}{$max_com_unmapped_task} * $mah_distance;
-					
-			}
-			$min_com_cost = $com_cost+1 if(!defined $min_com_cost);
-			if ($com_cost < $min_com_cost){
-				$min_com_cost = $com_cost;
-				$min_com_cost_tile_id = $unallocated_tile;
-			}
-		}
-		
-		# add max_com_unmapped_task to the mapped_tasks_set set
-		#task_mapping[max_com_unmapped_task] = min_com_cost_tile_id;
-		$map{$max_com_unmapped_task}=$min_com_cost_tile_id;
-		@unmapped_tasks_set=remove_scolar_from_array(\@unmapped_tasks_set,$max_com_unmapped_task);
-		@unallocated_tiles_set=remove_scolar_from_array(\@unallocated_tiles_set,$min_com_cost_tile_id);
-		
-	}
-	
-	
-	foreach my $mapped_task (sort keys %map){
-			my $mapped_tile=$map{$mapped_task};
-			#print "$mapped_tile=\$map{$mapped_task};\n";
-			#$self->object_add_attribute('MAP_TILE',"$mapped_task", $mapped_tile) if(defined $mapped_tile);
-			$self->object_add_attribute('MAP_TASK',"$mapped_tile",$mapped_task) if(defined $mapped_tile);
-			my @l = ($mapped_task);
-			$self->object_add_attribute('mapping',"$mapped_tile",\@l) if(defined $mapped_tile);		
-			#print "\$self->object_add_attribute('mapping',$mapped_tile,@l) if(defined $mapped_tile);\n";
-	}
-	set_gui_status($self,"ref",1);
-		
-}	
-		
-		
-
-
-
-
-
+    my $self=shift;    
+    my $nx=$self->object_get_attribute('noc_param','T1');
+    my $ny=$self->object_get_attribute('noc_param','T2');
+    my $nc= $nx * $ny;
+    my @tasks=get_all_merged_tasks($self);
+    my @tiles= get_tiles_name($self);    
+    my $n_tasks = scalar  @tasks;
+    my @unmapped_tasks_set=@tasks; # unmapped set of tasks
+    my @unallocated_tiles_set=@tiles;    # tile ids which are not allocated yet
+    #    print "@unmapped_tasks_set *** @unallocated_tiles_set\n";
+    #------ step 1: find the task with highest weighted communication volume
+    # find the max of com_vol
+    # consider all incoming and outgoing connections of each tasks
+    my %com_tasks= $self->get_communication_task('merge');
+    #print  Data::Dumper->Dump([\%com_tasks],['mpsoc']);    
+    my $max_com_task;
+    my $max_com =0;
+    foreach my $p (sort keys %com_tasks){
+        #print "**$p\n";
+        if(defined $com_tasks{$p}{'total'}){
+        if ($com_tasks{$p}{'total'} >$max_com){
+            $max_com = $com_tasks{$p}{'total'};
+            $max_com_task = $p;
+        }}
+    }
+    #print "m=$max_com     t=$max_com_task\n";
+    #------ step 2: find the tile with max number of neighbors
+    # normally, this tile is in the middle of the array
+    my $max_neighbors_tile_id = find_max_neighbor_tile($self);
+    print "\$max_neighbors_tile_id = $max_neighbors_tile_id\n";
+    my %map=get_locked_map ($self);    
+    $self->remove_nlock_mapping();
+    foreach my $mapped_task (sort keys %map){
+            my $mapped_tile=$map{$mapped_task};
+            @unmapped_tasks_set=remove_scolar_from_array(\@unmapped_tasks_set,$mapped_task);
+            @unallocated_tiles_set=remove_scolar_from_array(\@unallocated_tiles_set,$mapped_tile);
+    }
+    # add this task with highest weighted communication volume to the mapped task set
+    #push(@mapped_tasks_set,$max_com_task);
+    #task_mapping[max_com_task] = max_neighbors_tile_id;
+    if(!defined $map{$max_com_task}){
+        $map{$max_com_task}=$max_neighbors_tile_id;
+        @unmapped_tasks_set=remove_scolar_from_array(\@unmapped_tasks_set,$max_com_task);
+        @unallocated_tiles_set=remove_scolar_from_array(\@unallocated_tiles_set,$max_neighbors_tile_id);
+    }
+    #------ step 3: map all unmapped tasks
+    while(scalar @unmapped_tasks_set){
+        $max_com =0;
+        my $max_com_unmapped_task;
+        my $max_overall_com=0;
+        #--------- step 3.1:
+        # find the unmapped task which communicates most with mapped_tasks_set
+        # among many tasks which have the same communication volume with mapped_tasks,
+        # choose the task with highest communication volume with others
+        foreach my $unmapped_task (@unmapped_tasks_set){
+            my $com_vol=0;
+            foreach my $mapped_task (sort keys %map){
+                $com_vol += $com_tasks{$unmapped_task}{$mapped_task};
+                $com_vol += $com_tasks{$mapped_task}{$unmapped_task};
+            }
+            my $overall_com_vol = 0;
+            foreach my $p (@tasks){
+                $overall_com_vol += $com_tasks{$unmapped_task}{$p};
+                $overall_com_vol += $com_tasks{$p}{$unmapped_task};
+            }
+            if ($com_vol > $max_com){
+                $max_com = $com_vol;
+                $max_com_unmapped_task = $unmapped_task;
+                $max_overall_com = $overall_com_vol;
+            }
+            elsif ($com_vol == $max_com){ # choose if it have higher comm volume
+                if ($overall_com_vol > $max_overall_com){
+                    $max_com_unmapped_task = $unmapped_task;
+                    $max_overall_com = $overall_com_vol;
+                }
+            }
+        }#foreach my $unmapped_task (@unmapped_tasks_set)
+        #--------- step 3.2, find the unallocated tile with lowest communication cost to/from allocated_tile_set
+        my $min_com_cost;
+        my $min_com_cost_tile_id;
+        foreach my $unallocated_tile(@unallocated_tiles_set){
+            my $com_cost = 0;
+            #my ($unallocated_x,$unallocated_y)=tile_id_to_loc($unallocated_tile);
+            my $unallocated_tile_num = tile_id_number($unallocated_tile);
+            # scan all mapped tasks
+            foreach my $mapped_task (sort keys %map){
+                # get location of this mapped task
+                my $mapped_tile=$map{$mapped_task};
+                #my ($allocated_x,$allocated_y)=tile_id_to_loc($mapped_tile);
+                my $mapped_tile_num = tile_id_number($mapped_tile);                
+                # mahattan distance of 2 tiles
+                my $mah_distance=get_endpoints_mah_distance($self,$unallocated_tile_num,$mapped_tile_num);
+                $com_cost += $com_tasks{$max_com_unmapped_task}{$mapped_task} * $mah_distance;
+                $com_cost += $com_tasks{$mapped_task}{$max_com_unmapped_task} * $mah_distance;
+                    
+            }
+            $min_com_cost = $com_cost+1 if(!defined $min_com_cost);
+            if ($com_cost < $min_com_cost){
+                $min_com_cost = $com_cost;
+                $min_com_cost_tile_id = $unallocated_tile;
+            }
+        }
+        # add max_com_unmapped_task to the mapped_tasks_set set
+        #task_mapping[max_com_unmapped_task] = min_com_cost_tile_id;
+        $map{$max_com_unmapped_task}=$min_com_cost_tile_id;
+        @unmapped_tasks_set=remove_scolar_from_array(\@unmapped_tasks_set,$max_com_unmapped_task);
+        @unallocated_tiles_set=remove_scolar_from_array(\@unallocated_tiles_set,$min_com_cost_tile_id);
+    }
+    foreach my $mapped_task (sort keys %map){
+            my $mapped_tile=$map{$mapped_task};
+            #print "$mapped_tile=\$map{$mapped_task};\n";
+            #$self->object_add_attribute('MAP_TILE',"$mapped_task", $mapped_tile) if(defined $mapped_tile);
+            $self->object_add_attribute('MAP_TASK',"$mapped_tile",$mapped_task) if(defined $mapped_tile);
+            my @l = ($mapped_task);
+            $self->object_add_attribute('mapping',"$mapped_tile",\@l) if(defined $mapped_tile);        
+            #print "\$self->object_add_attribute('mapping',$mapped_tile,@l) if(defined $mapped_tile);\n";
+    }
+    set_gui_status($self,"ref",1);
+}    
 
 sub worst_map_algorithm{
-
-	my $self=shift;
-	
-	
-	my $nx=$self->object_get_attribute('noc_param','T1');
-	my $ny=$self->object_get_attribute('noc_param','T2');
-	my $nc= $nx * $ny;
-	
-	my @tasks=get_all_merged_tasks($self);
-	my @tiles= get_tiles_name($self);
-	
-	my $n_tasks = scalar  @tasks;
-	
-	
-	
-	
-	my @unmapped_tasks_set=@tasks; # unmapped set of tasks
-	my @unallocated_tiles_set=@tiles;	# tile ids which are not allocated yet
-	
-	
-	
-	
-	#------ step 1: find the task with highest weighted communication volume
-	# find the max of com_vol
-	# consider all incoming and outgoing connections of each tasks
-	
-	my %com_tasks= $self->get_communication_task('merge');
-	#print  Data::Dumper->Dump([\%com_tasks],['mpsoc']);	
-	
-	my $max_com_task;
-	my $max_com =0;
-	foreach my $p (sort keys %com_tasks){
-		#print "$p\n";
-		if(defined $com_tasks{$p}{'total'}){
-		if ($com_tasks{$p}{'total'} >$max_com){
-			$max_com = $com_tasks{$p}{'total'};
-			$max_com_task = $p;
-		}}
-	}
-	
-	
-	
-	
-	#------ step 2: find the tile with min number of neighbors
-	# normally, this tile is in the corners 
-	my $min_neighbors_tile_id = find_min_neighbor_tile($self);
-	
-	
-	
-	
-	my %map=get_locked_map ($self);	
-	$self->remove_nlock_mapping();
-	foreach my $mapped_task (sort keys %map){
-			my $mapped_tile=$map{$mapped_task};
-			@unmapped_tasks_set=remove_scolar_from_array(\@unmapped_tasks_set,$mapped_task);
-			@unallocated_tiles_set=remove_scolar_from_array(\@unallocated_tiles_set,$mapped_tile);
-	}
-		
-	
-	
-	
-	# add this task with highest weighted communication volume to the mapped task set
-	#push(@mapped_tasks_set,$max_com_task);
-	#task_mapping[max_com_task] = max_neighbors_tile_id;
-	
-	if(!defined $map{$max_com_task}){
-		$map{$max_com_task}=$min_neighbors_tile_id;
-		@unmapped_tasks_set=remove_scolar_from_array(\@unmapped_tasks_set,$max_com_task);
-		@unallocated_tiles_set=remove_scolar_from_array(\@unallocated_tiles_set,$min_neighbors_tile_id);
-	}
-
-
-
-
-
-
-
-	#------ step 3: map all unmapped tasks
-	while(scalar @unmapped_tasks_set){
-		$max_com =0;
-		my $max_com_unmapped_task;
-		my $max_overall_com=0;
-		#--------- step 3.1:
-		# find the unmapped task which communicates most with mapped_tasks_set
-		# among many tasks which have the same communication volume with mapped_tasks,
-		# choose the task with highest communication volume with others
-		
-		foreach my $unmapped_task (@unmapped_tasks_set){
-			
-			my $com_vol=0;
-			foreach my $mapped_task (sort keys %map){
-				$com_vol += $com_tasks{$unmapped_task}{$mapped_task};
-				$com_vol += $com_tasks{$mapped_task}{$unmapped_task};
-			}
-			
-			my $overall_com_vol = 0;
-			foreach my $p (@tasks){
-				$overall_com_vol += $com_tasks{$unmapped_task}{$p};
-				$overall_com_vol += $com_tasks{$p}{$unmapped_task};
-			}
-			
-			
-			if ($com_vol > $max_com){
-				$max_com = $com_vol;
-				$max_com_unmapped_task = $unmapped_task;
-				$max_overall_com = $overall_com_vol;
-			}
-			elsif ($com_vol == $max_com){ # choose if it have higher comm volume
-				if ($overall_com_vol > $max_overall_com){
-					$max_com_unmapped_task = $unmapped_task;
-					$max_overall_com = $overall_com_vol;
-				}
-			}
-		}#foreach my $unmapped_task (@unmapped_tasks_set)
-
-		#--------- step 3.2, find the unallocated tile with highest communication cost to/from allocated_tile_set
-		my $max_com_cost;
-		my $max_com_cost_tile_id;
-		
-		
-		foreach my $unallocated_tile(@unallocated_tiles_set){
-			my $com_cost = 0;
-			#my ($unallocated_x,$unallocated_y)=tile_id_to_loc($unallocated_tile);
-			my $unallocated_tile_num = tile_id_number($unallocated_tile);
-			# scan all mapped tasks
-			foreach my $mapped_task (sort keys %map){
-				# get location of this mapped task
-				my $mapped_tile=$map{$mapped_task};
-				#my ($allocated_x,$allocated_y)=tile_id_to_loc($mapped_tile);
-				my $mapped_tile_num = tile_id_number($mapped_tile);				
-				# mahattan distance of 2 tiles				
-				my $mah_distance=get_endpoints_mah_distance($self,$unallocated_tile_num,$mapped_tile_num);
-				
-				$com_cost += $com_tasks{$max_com_unmapped_task}{$mapped_task} * $mah_distance;
-				$com_cost += $com_tasks{$mapped_task}{$max_com_unmapped_task} * $mah_distance;
-					
-			}
-			$max_com_cost = $com_cost-1 if(!defined $max_com_cost);
-			if ($com_cost > $max_com_cost){
-				$max_com_cost = $com_cost;
-				$max_com_cost_tile_id = $unallocated_tile;
-			}
-		}
-		
-		# add max_com_unmapped_task to the mapped_tasks_set set
-		#task_mapping[max_com_unmapped_task] = min_com_cost_tile_id;
-		$map{$max_com_unmapped_task}=$max_com_cost_tile_id;
-		@unmapped_tasks_set=remove_scolar_from_array(\@unmapped_tasks_set,$max_com_unmapped_task);
-		@unallocated_tiles_set=remove_scolar_from_array(\@unallocated_tiles_set,$max_com_cost_tile_id);
-		
-	}
-	
-	
-	foreach my $mapped_task (sort keys %map){
-			my $mapped_tile=$map{$mapped_task};
-			#print "$mapped_tile=\$map{$mapped_task};\n";
-			#$self->object_add_attribute('MAP_TILE',"$mapped_task", $mapped_tile) if(defined $mapped_tile);
-			 	
-			$self->object_add_attribute('MAP_TASK',"$mapped_tile",$mapped_task) if(defined $mapped_tile);
-			my @l=($mapped_task);
-			$self->object_add_attribute("mapping","$mapped_tile",\@l) if(defined $mapped_tile); 
-			#print "$self->object_add_attribute(\"mapping\",\"$mapped_tile\",$mapped_task);\n"; 
-	}
-	set_gui_status($self,"ref",1);
-		
-}	
-
-
-
-
+    my $self=shift;
+    my $nx=$self->object_get_attribute('noc_param','T1');
+    my $ny=$self->object_get_attribute('noc_param','T2');
+    my $nc= $nx * $ny;
+    my @tasks=get_all_merged_tasks($self);
+    my @tiles= get_tiles_name($self);
+    my $n_tasks = scalar  @tasks;
+    my @unmapped_tasks_set=@tasks; # unmapped set of tasks
+    my @unallocated_tiles_set=@tiles;    # tile ids which are not allocated yet
+    #------ step 1: find the task with highest weighted communication volume
+    # find the max of com_vol
+    # consider all incoming and outgoing connections of each tasks
+    my %com_tasks= $self->get_communication_task('merge');
+    #print  Data::Dumper->Dump([\%com_tasks],['mpsoc']);    
+    my $max_com_task;
+    my $max_com =0;
+    foreach my $p (sort keys %com_tasks){
+        #print "$p\n";
+        if(defined $com_tasks{$p}{'total'}){
+        if ($com_tasks{$p}{'total'} >$max_com){
+            $max_com = $com_tasks{$p}{'total'};
+            $max_com_task = $p;
+        }}
+    }
+    #------ step 2: find the tile with min number of neighbors
+    # normally, this tile is in the corners 
+    my $min_neighbors_tile_id = find_min_neighbor_tile($self);
+    my %map=get_locked_map ($self);    
+    $self->remove_nlock_mapping();
+    foreach my $mapped_task (sort keys %map){
+            my $mapped_tile=$map{$mapped_task};
+            @unmapped_tasks_set=remove_scolar_from_array(\@unmapped_tasks_set,$mapped_task);
+            @unallocated_tiles_set=remove_scolar_from_array(\@unallocated_tiles_set,$mapped_tile);
+    }
+    # add this task with highest weighted communication volume to the mapped task set
+    #push(@mapped_tasks_set,$max_com_task);
+    #task_mapping[max_com_task] = max_neighbors_tile_id;
+    if(!defined $map{$max_com_task}){
+        $map{$max_com_task}=$min_neighbors_tile_id;
+        @unmapped_tasks_set=remove_scolar_from_array(\@unmapped_tasks_set,$max_com_task);
+        @unallocated_tiles_set=remove_scolar_from_array(\@unallocated_tiles_set,$min_neighbors_tile_id);
+    }
+    #------ step 3: map all unmapped tasks
+    while(scalar @unmapped_tasks_set){
+        $max_com =0;
+        my $max_com_unmapped_task;
+        my $max_overall_com=0;
+        #--------- step 3.1:
+        # find the unmapped task which communicates most with mapped_tasks_set
+        # among many tasks which have the same communication volume with mapped_tasks,
+        # choose the task with highest communication volume with others
+        foreach my $unmapped_task (@unmapped_tasks_set){
+            my $com_vol=0;
+            foreach my $mapped_task (sort keys %map){
+                $com_vol += $com_tasks{$unmapped_task}{$mapped_task};
+                $com_vol += $com_tasks{$mapped_task}{$unmapped_task};
+            }
+            my $overall_com_vol = 0;
+            foreach my $p (@tasks){
+                $overall_com_vol += $com_tasks{$unmapped_task}{$p};
+                $overall_com_vol += $com_tasks{$p}{$unmapped_task};
+            }
+            if ($com_vol > $max_com){
+                $max_com = $com_vol;
+                $max_com_unmapped_task = $unmapped_task;
+                $max_overall_com = $overall_com_vol;
+            }
+            elsif ($com_vol == $max_com){ # choose if it have higher comm volume
+                if ($overall_com_vol > $max_overall_com){
+                    $max_com_unmapped_task = $unmapped_task;
+                    $max_overall_com = $overall_com_vol;
+                }
+            }
+        }#foreach my $unmapped_task (@unmapped_tasks_set)
+        #--------- step 3.2, find the unallocated tile with highest communication cost to/from allocated_tile_set
+        my $max_com_cost;
+        my $max_com_cost_tile_id;
+        foreach my $unallocated_tile(@unallocated_tiles_set){
+            my $com_cost = 0;
+            #my ($unallocated_x,$unallocated_y)=tile_id_to_loc($unallocated_tile);
+            my $unallocated_tile_num = tile_id_number($unallocated_tile);
+            # scan all mapped tasks
+            foreach my $mapped_task (sort keys %map){
+                # get location of this mapped task
+                my $mapped_tile=$map{$mapped_task};
+                #my ($allocated_x,$allocated_y)=tile_id_to_loc($mapped_tile);
+                my $mapped_tile_num = tile_id_number($mapped_tile);                
+                # mahattan distance of 2 tiles                
+                my $mah_distance=get_endpoints_mah_distance($self,$unallocated_tile_num,$mapped_tile_num);
+                $com_cost += $com_tasks{$max_com_unmapped_task}{$mapped_task} * $mah_distance;
+                $com_cost += $com_tasks{$mapped_task}{$max_com_unmapped_task} * $mah_distance;
+            }
+            $max_com_cost = $com_cost-1 if(!defined $max_com_cost);
+            if ($com_cost > $max_com_cost){
+                $max_com_cost = $com_cost;
+                $max_com_cost_tile_id = $unallocated_tile;
+            }
+        }
+        # add max_com_unmapped_task to the mapped_tasks_set set
+        #task_mapping[max_com_unmapped_task] = min_com_cost_tile_id;
+        $map{$max_com_unmapped_task}=$max_com_cost_tile_id;
+        @unmapped_tasks_set=remove_scolar_from_array(\@unmapped_tasks_set,$max_com_unmapped_task);
+        @unallocated_tiles_set=remove_scolar_from_array(\@unallocated_tiles_set,$max_com_cost_tile_id);
+    }
+    foreach my $mapped_task (sort keys %map){
+            my $mapped_tile=$map{$mapped_task};
+            #print "$mapped_tile=\$map{$mapped_task};\n";
+            #$self->object_add_attribute('MAP_TILE',"$mapped_task", $mapped_tile) if(defined $mapped_tile);
+            $self->object_add_attribute('MAP_TASK',"$mapped_tile",$mapped_task) if(defined $mapped_tile);
+            my @l=($mapped_task);
+            $self->object_add_attribute("mapping","$mapped_tile",\@l) if(defined $mapped_tile); 
+            #print "$self->object_add_attribute(\"mapping\",\"$mapped_tile\",$mapped_task);\n"; 
+    }
+    set_gui_status($self,"ref",1);
+}    
 
 sub get_task_assigned_to_tile {
-	my ($self,$i)=@_;
-	#my $p= $self->object_get_attribute("MAP_TASK","tile($i)");
-	my $r=$self->object_get_attribute("mapping","tile($i)");
-	return undef if(!defined $r);
-	my @l=@{$r}; 
-	return $l[0]; 	
+    my ($self,$i)=@_;
+    #my $p= $self->object_get_attribute("MAP_TASK","tile($i)");
+    my $r=$self->object_get_attribute("mapping","tile($i)");
+    return undef if(!defined $r);
+    my @l=@{$r}; 
+    return $l[0];     
 }
 
-
-
 sub get_assigned_tiles{
-	my $self=shift;
-	my @assigned_tiles;
-	my @tiles=get_tiles_name($self);
-	foreach my $p (@tiles){
-		my @l=@{$self->object_get_attribute("mapping","$p")}; 
-		push(@assigned_tiles,$p)if(defined $l[0] );		
-	}	
-	#my @assigned_tiles = sort keys %{$self->{'MAP_TASK'}};
-	return @assigned_tiles;		
+    my $self=shift;
+    my @assigned_tiles;
+    my @tiles=get_tiles_name($self);
+    foreach my $p (@tiles){
+        my @l=@{$self->object_get_attribute("mapping","$p")}; 
+        push(@assigned_tiles,$p)if(defined $l[0] );        
+    }    
+    #my @assigned_tiles = sort keys %{$self->{'MAP_TASK'}};
+    return @assigned_tiles;        
 }
 
 sub map_task {
-	my ($self,$task,$tile)=@_;
-	#my $oldtile= $self->{"MAP_TILE"}{$task};
-	my $oldtile=get_task_give_tile($self,$task);
-	if($tile eq "-"){		
-	 	#delete $self->{"MAP_TILE"}{$task};	 	
-	}else{
-		#$self->{"MAP_TILE"}{$task}= $tile;
-		$self->{'MAP_TASK'}{$tile}= $task;
-		my @l=($task);
-		$self->object_add_attribute("mapping","$tile",\@l); 
-	}	
-	delete $self->{"MAP_TASK"}{$oldtile} if(defined $oldtile);	
-	$self->object_add_attribute("mapping",$oldtile,undef) if(defined $oldtile);	
+    my ($self,$task,$tile)=@_;
+    #my $oldtile= $self->{"MAP_TILE"}{$task};
+    my $oldtile=get_task_give_tile($self,$task);
+    if($tile eq "-"){        
+        #delete $self->{"MAP_TILE"}{$task};         
+    }else{
+        #$self->{"MAP_TILE"}{$task}= $tile;
+        $self->{'MAP_TASK'}{$tile}= $task;
+        my @l=($task);
+        $self->object_add_attribute("mapping","$tile",\@l); 
+    }    
+    delete $self->{"MAP_TASK"}{$oldtile} if(defined $oldtile);    
+    $self->object_add_attribute("mapping",$oldtile,undef) if(defined $oldtile);    
 }
 
 sub remove_selected_traces{
-	my ($self,$category)=@_;
-	my @traces= get_trace_list($self,$category);
-	foreach my $p (@traces) {	
-		my $select=$self->object_get_attribute("${category}_$p",'selected', 0); 
-		
-		if($select){
-			$self->remove_trace($category,"$p");
-			
-		}
-	}
-	set_gui_status($self,"ref",1);
+    my ($self,$category)=@_;
+    my @traces= get_trace_list($self,$category);
+    foreach my $p (@traces) {    
+        my $select=$self->object_get_attribute("${category}_$p",'selected', 0); 
+        if($select){
+            $self->remove_trace($category,"$p");
+        }
+    }
+    set_gui_status($self,"ref",1);
 }
 
-
-
 sub auto_generate_injtratio{
-	my ($self,$category)=@_;
-	my %com_tasks= $self->get_communication_task($category);
-	my @traces= get_trace_list($self,'raw');
-	foreach my $p (@traces) {	
-		my ($src,$dst, $Mbytes, $file_id, $file_name)=get_trace($self,$category,$p);
-		my $max= $com_tasks{$file_id}{'maxsent'};
-		my $sent= $com_tasks{$src}{'sent'};
-		my $ratio = ($sent*100)/$max;
-		$self->object_add_attribute("raw_$p",'injct_rate',$ratio);
-		
-		my $minpck = $self->object_get_attribute("raw_$p",'min_pck_size');
-		my $maxpck = $self->object_get_attribute("raw_$p",'max_pck_size' );
-		my $avg_pck_size =($minpck+ $maxpck)/2;
-		my $pck_num = ($Mbytes*8) /($avg_pck_size*64);
-		
-				
-		my $burst =$pck_num/ $com_tasks{$src}{'min_pck_num'} ;
-		$self->object_add_attribute("raw_$p",'burst_size',ceil($burst));
-		
-		#my $burst_size	= gen_spin_object ($self,"raw_$p",'burst_size',"1,1024,1", 1,undef,undef);
-		
-		
-		
-	}
-	set_gui_status($self,"ref",1);
-	
-	
+    my ($self,$category)=@_;
+    my %com_tasks= $self->get_communication_task($category);
+    my @traces= get_trace_list($self,'raw');
+    foreach my $p (@traces) {    
+        my ($src,$dst, $Mbytes, $file_id, $file_name)=get_trace($self,$category,$p);
+        my $max= $com_tasks{$file_id}{'maxsent'};
+        my $sent= $com_tasks{$src}{'sent'};
+        my $ratio = ($sent*100)/$max;
+        $self->object_add_attribute("raw_$p",'injct_rate',$ratio);
+        my $minpck = $self->object_get_attribute("raw_$p",'min_pck_size');
+        my $maxpck = $self->object_get_attribute("raw_$p",'max_pck_size' );
+        my $avg_pck_size =($minpck+ $maxpck)/2;
+        my $pck_num = ($Mbytes*8) /($avg_pck_size*64);
+        my $burst =$pck_num/ $com_tasks{$src}{'min_pck_num'} ;
+        $self->object_add_attribute("raw_$p",'burst_size',ceil($burst));
+        #my $burst_size    = gen_spin_object ($self,"raw_$p",'burst_size',"1,1024,1", 1,undef,undef);
+    }
+    set_gui_status($self,"ref",1);
 }
 
 
 sub trace_merger{
-	my ($self,$tview,$mode)=@_;	
-	my $table= def_table(2,10,FALSE);
-	my $row=0;
-	my $col=0;
-	
-	my $m= ($mode eq 'task')? "Task" :"Actor";
-	
-	
-	my $label = gen_label_in_center(' ');
-    $label->set_markup ("<u>Group ${m}s</u>      ");	
-	$table->attach ($label,$col, $col+5,  $row, $row+1,'shrink','shrink',2,2);$col+=5;	
-	my ($Ebox,$entry)=def_h_labeled_entry ("New group name:",undef);
-	$table->attach ($Ebox,$col, $col+4,  $row, $row+1,'shrink','shrink',2,2);$col+=5;
-	my $add=def_image_button('icons/plus.png');
-	$table->attach ($add,$col, $col+1,  $row, $row+1,'shrink','shrink',2,2);$col+=1;
-	
-	$row++;
-	$col=0;
-	
-	#my @info =  (
-  	#{ label=>'Number of Group', param_name=>'GROUP_NUM', type=>"Spin-button", default_val=>1, content=>"1,1000,1", info=>"Several  ${m}s can be grouped and mapped on the same tile. Define the number of groups which ${m} can be categorized to.", param_parent=>'noc_param', ref_delay=>1,placement=>'vertical'}
-	#);
-	
-	#foreach my $d (@info) {
-	#	($row,$col)=add_param_widget ($self, $d->{label}, $d->{param_name}, $d->{default_val}, $d->{type}, $d->{content}, $d->{info}, $table,$row,$col,1, $d->{param_parent}, $d->{ref_delay},'ref',$d->{placement});
-	#}
-	
-	
-	return add_widget_to_scrolled_win($table);
-	
+    my ($self,$tview,$mode)=@_;    
+    my $table= def_table(2,10,FALSE);
+    my $row=0;
+    my $col=0;
+    my $m= ($mode eq 'task')? "Task" :"Actor";
+    my $label = gen_label_in_center(' ');
+    $label->set_markup ("<u>Group ${m}s</u>      ");    
+    $table->attach ($label,$col, $col+5,  $row, $row+1,'shrink','shrink',2,2);$col+=5;    
+    my ($Ebox,$entry)=def_h_labeled_entry ("New group name:",undef);
+    $table->attach ($Ebox,$col, $col+4,  $row, $row+1,'shrink','shrink',2,2);$col+=5;
+    my $add=def_image_button('icons/plus.png');
+    $table->attach ($add,$col, $col+1,  $row, $row+1,'shrink','shrink',2,2);$col+=1;
+    $row++;
+    $col=0;
+    #my @info =  (
+    #{ label=>'Number of Group', param_name=>'GROUP_NUM', type=>"Spin-button", default_val=>1, content=>"1,1000,1", info=>"Several  ${m}s can be grouped and mapped on the same tile. Define the number of groups which ${m} can be categorized to.", param_parent=>'noc_param', ref_delay=>1,placement=>'vertical'}
+    #);
+    #foreach my $d (@info) {
+    #    ($row,$col)=add_param_widget ($self, $d->{label}, $d->{param_name}, $d->{default_val}, $d->{type}, $d->{content}, $d->{info}, $table,$row,$col,1, $d->{param_parent}, $d->{ref_delay},'ref',$d->{placement});
+    #}
+    return add_widget_to_scrolled_win($table);
 }
 
-
-
-
 sub select_trace_file {
-	my ($self,$tview,$mode)=@_;
-	my $traces=trace_pad($self,$tview,$mode);
-	my $traces_ctrl=trace_pad_ctrl($self,$tview,$mode);
-	my $h=gen_hpaned_adj($self,$traces_ctrl,.20,$traces,'trace-hpan');
-	return $h;
+    my ($self,$tview,$mode)=@_;
+    my $traces=trace_pad($self,$tview,$mode);
+    my $traces_ctrl=trace_pad_ctrl($self,$tview,$mode);
+    my $h=gen_hpaned_adj($self,$traces_ctrl,.20,$traces,'trace-hpan');
+    return $h;
 }
 
-
 sub trace_maker_notebook{
-	my ($self,$mode,$tview)=@_;		
-	my $notebook = gen_notebook();
-	my $lb= ($mode eq 'orcc')?  'Actor' : 'Trace';
-	my $group_num=16;
-	
-	
-	$notebook->set_tab_pos ('left');
-	$notebook->set_scrollable(TRUE);
-	
-	my $page1=select_trace_file($self,$tview,$mode);
-	$notebook->append_page ($page1,gen_label_in_center  ("1-Select $mode file"));
-	
-	my ($NE, $NR, $RAw, $EAw, $Fw)=get_topology_info($self);
-	
-	#group tasks
-	$self->object_add_attribute('grouping','group_name_root','group');	
-	$self->object_add_attribute('grouping','group_name_editble','YES');	
-	$self->object_add_attribute('grouping','trace_icon','icons/cd.png');
-	$self->object_add_attribute('grouping','group_num',$NE);
-	$self->object_add_attribute('grouping','map_limit',1024);
-	$self->object_add_attribute('grouping','lable',"${lb}s: Drag and drop ${lb}s to bottom group list");	
-	my $group_ctrl =gen_group_ctrl_box($self,$tview,$mode);
-		
-	my @tasks=get_all_tasks($self,'raw');
-	my $page2=drag_and_drop_page($self,$tview,'grouping',\@tasks,$group_ctrl);
-	$notebook->append_page ($page2,gen_label_in_center  ("2-Group ${lb}s   "));
-	
-	#map tasks	
-	$self->object_add_attribute('mapping','group_name_root','tile');	
-	$self->object_add_attribute('mapping','group_name_editble','NO');
-	$self->object_add_attribute('mapping','trace_icon','icons/cd2.png');	
-	$self->object_add_attribute('mapping','lable',"${lb}s: Drag and drop ${lb}s/grouped ${lb}s to bottom tile list");
-	$self->object_add_attribute('mapping','map_limit',1);
-	$self->object_add_attribute('mapping','group_num',$NE);
-	
-	#get list of non-empty groups	
-	my @merged_tasks=get_all_merged_tasks($self);
-	my $map_ctrl =gen_mapping_ctrl_box($self,$tview,$mode);
-	
-	# check task names to be uniq 
-	my @r= return_not_unique_names_in_array(@merged_tasks);
+    my ($self,$mode,$tview)=@_;        
+    my $notebook = gen_notebook();
+    my $lb= ($mode eq 'orcc')?  'Actor' : 'Trace';
+    my $group_num=16;
+    $notebook->set_tab_pos ('left');
+    $notebook->set_scrollable(TRUE);
+    my $page1=select_trace_file($self,$tview,$mode);
+    $notebook->append_page ($page1,gen_label_in_center  ("1-Select $mode file"));
+    my ($NE, $NR, $RAw, $EAw, $Fw)=get_topology_info($self);
+    #group tasks
+    $self->object_add_attribute('grouping','group_name_root','group');    
+    $self->object_add_attribute('grouping','group_name_editble','YES');    
+    $self->object_add_attribute('grouping','trace_icon','icons/cd.png');
+    $self->object_add_attribute('grouping','group_num',$NE);
+    $self->object_add_attribute('grouping','map_limit',1024);
+    $self->object_add_attribute('grouping','lable',"${lb}s: Drag and drop ${lb}s to bottom group list");    
+    my $group_ctrl =gen_group_ctrl_box($self,$tview,$mode);
+    my @tasks=get_all_tasks($self,'raw');
+    my $page2=drag_and_drop_page($self,$tview,'grouping',\@tasks,$group_ctrl);
+    $notebook->append_page ($page2,gen_label_in_center  ("2-Group ${lb}s   "));
+    #map tasks    
+    $self->object_add_attribute('mapping','group_name_root','tile');    
+    $self->object_add_attribute('mapping','group_name_editble','NO');
+    $self->object_add_attribute('mapping','trace_icon','icons/cd2.png');    
+    $self->object_add_attribute('mapping','lable',"${lb}s: Drag and drop ${lb}s/grouped ${lb}s to bottom tile list");
+    $self->object_add_attribute('mapping','map_limit',1);
+    $self->object_add_attribute('mapping','group_num',$NE);
+    #get list of non-empty groups    
+    my @merged_tasks=get_all_merged_tasks($self);
+    my $map_ctrl =gen_mapping_ctrl_box($self,$tview,$mode);
+    # check task names to be uniq 
+    my @r= return_not_unique_names_in_array(@merged_tasks);
     foreach my $p (@r){
-    	add_colored_info($tview,"$lb name $p is not unique!\n",'red');
+        add_colored_info($tview,"$lb name $p is not unique!\n",'red');
     }
-	
-	
-	my $page3=drag_and_drop_page($self,$tview,'mapping',\@merged_tasks,$map_ctrl);
-	$notebook->append_page ($page3,gen_label_in_center  ("3-Map ${lb}s"));
-	
-	
-	
-	
-	#my $page4=routing_page($self,$tview);
-	#$notebook->append_page ($page4,gen_label_in_center ("Route Selection"));
-	
-	
-	
-	$notebook->show_all;
-		
-	my $first=1;
-	my $page_num=$self->object_get_attribute ("process_notebook","currentpage");		
-	$notebook->set_current_page ($page_num) if(defined $page_num);
-	$notebook->signal_connect( 'switch-page'=> sub{			
-		$self->object_add_attribute ("process_notebook","currentpage",$_[2]);	#save the new pagenumber
-	});	
-	$notebook->signal_connect("switch-page" => sub{ 		
-		if(!$first){
-			
-			set_gui_status($self,"ref",1);
-		}else {
-			set_gui_status($self,"ref",1);
-		}
-		$first=0;		
-	});
-	
-	return $notebook;
-	
+    my $page3=drag_and_drop_page($self,$tview,'mapping',\@merged_tasks,$map_ctrl);
+    $notebook->append_page ($page3,gen_label_in_center  ("3-Map ${lb}s"));
+    #my $page4=routing_page($self,$tview);
+    #$notebook->append_page ($page4,gen_label_in_center ("Route Selection"));
+    $notebook->show_all;
+    my $first=1;
+    my $page_num=$self->object_get_attribute ("process_notebook","currentpage");        
+    $notebook->set_current_page ($page_num) if(defined $page_num);
+    $notebook->signal_connect( 'switch-page'=> sub{            
+        $self->object_add_attribute ("process_notebook","currentpage",$_[2]);    #save the new pagenumber
+    });    
+    $notebook->signal_connect("switch-page" => sub{         
+        if(!$first){
+            set_gui_status($self,"ref",1);
+        }else {
+            set_gui_status($self,"ref",1);
+        }
+        $first=0;        
+    });
+    return $notebook;
 }
 
 sub get_all_merged_tasks {
-	my($self)=@_;
-	my @merged;
-	my $group_num=$self->object_get_attribute('mapping','group_num');	
-	$group_num = 0 if(!defined $group_num);
-	for(my $i=0;$i<$group_num;$i=$i+1){
-		my $gref = $self->object_get_attribute('grouping',"group($i)");
-		next if(! defined $gref);
-		next if (scalar @{$gref} == 0);
-		
-		my $label =  $self->object_get_attribute('grouping',"group($i)"."_name");
-		$label = "group($i)" if(!defined $label);		
-		push (@merged,"$label");
-	}
-	my $uref= $self->object_get_attribute('grouping','ungrouped');	
-	push (@merged, @{$uref}) if(defined  $uref);	
-	return @merged;
+    my($self)=@_;
+    my @merged;
+    my $group_num=$self->object_get_attribute('mapping','group_num');    
+    $group_num = 0 if(!defined $group_num);
+    for(my $i=0;$i<$group_num;$i=$i+1){
+        my $gref = $self->object_get_attribute('grouping',"group($i)");
+        next if(! defined $gref);
+        next if (scalar @{$gref} == 0);
+        
+        my $label =  $self->object_get_attribute('grouping',"group($i)"."_name");
+        $label = "group($i)" if(!defined $label);        
+        push (@merged,"$label");
+    }
+    my $uref= $self->object_get_attribute('grouping','ungrouped');    
+    push (@merged, @{$uref}) if(defined  $uref);    
+    return @merged;
 }
 
-
-
 sub gen_mapping_ctrl_box{
-	my ($self,$tview,$mode)=@_;
-	my $map_ctrl= trace_map_ctrl($self,$tview,$mode);
-	my $map_info=map_info($self);
-	my $v_paned=gen_vpaned($map_ctrl,.4,$map_info);
-	return $v_paned; 
+    my ($self,$tview,$mode)=@_;
+    my $map_ctrl= trace_map_ctrl($self,$tview,$mode);
+    my $map_info=map_info($self);
+    my $v_paned=gen_vpaned($map_ctrl,.4,$map_info);
+    return $v_paned; 
 }
 
 sub gen_group_ctrl_box{
-	my ($self,$tview,$mode)=@_;
-	my $group_ctrl= trace_group_ctrl($self,$tview,$mode);
-	#my $map_info=map_info($self);
-	#my $v_paned=gen_vpaned($map_ctrl,.5,$map_info);
-	#return $v_paned; 
-	
-	my $group_info = group_info ($self,$tview,$mode);
-	my $v_paned=gen_vpaned($group_ctrl,0.2,$group_info);
-	return $v_paned; 
-	
-	#return $group_ctrl;
+    my ($self,$tview,$mode)=@_;
+    my $group_ctrl= trace_group_ctrl($self,$tview,$mode);
+    #my $map_info=map_info($self);
+    #my $v_paned=gen_vpaned($map_ctrl,.5,$map_info);
+    #return $v_paned; 
+    my $group_info = group_info ($self,$tview,$mode);
+    my $v_paned=gen_vpaned($group_ctrl,0.2,$group_info);
+    return $v_paned; 
+    #return $group_ctrl;
 }
 
-
-
-
-
 sub build_trace_gui {
-	my ($self,$mode,$ref,$w) = @_;
-	set_gui_status($self,"ideal",0);
-	$self->object_add_attribute ("process_notebook","currentpage",0);
-	if($mode eq 'task'){
-		$self->object_add_attribute('noc_param','T1',2);
-		$self->object_add_attribute('noc_param','T2',2);
-		$self->object_add_attribute('noc_param','T3',1);
-		$self->object_add_attribute('noc_param','Fpay',32);
-		$self->object_add_attribute('noc_param','V',1);	
-		$self->object_add_attribute('noc_param','C',1);		
-		$self->object_add_attribute('noc_param','TOPOLOGY','"MESH"');		
-	}
-	
-	$self->object_add_attribute("file_id",undef,'a');
-	$self->object_add_attribute("trace_id",undef,0);
-	$self->object_add_attribute('select_multiple','action',"_");
-	$self->object_add_attribute('Auto','Auto_inject',"1\'b1");
-	if(defined $ref){
-	   # add noc parameters
-		my %params=%{$ref};
-		foreach my $p (sort keys %params){
-			$self->{$p}=$params{$p};
-			 
-		}
-		
-	}
-	
-	
-	my ($scwin_info,$tview)= create_txview();	
-	my $notebook = trace_maker_notebook($self,$mode,$tview);
-	my $tt = ($mode eq 'task') ? 0.65 : 0.55;
-		
-	my $v2=gen_vpaned($notebook,$tt,$scwin_info);
-	
-	
-	
-	
-	
-	
-	
-	
-	set_gui_status($self,"ideal",0);
-
-	my $main_table= def_table(2,10,FALSE);
-	
-	
-
-	
-	my $generate = def_image_button('icons/gen.png','Generate');
-	my $open = def_image_button('icons/browse.png','Load');	
-	my ($entrybox,$entry) = def_h_labeled_entry('Save as:',undef);
-	$entry->signal_connect( 'changed'=> sub{
-		my $name=$entry->get_text();
-		$self->object_add_attribute ("save_as",undef,$name);	
-	});	
-	
-	my $entry2=gen_entry_object($self,'out_name',undef,undef,undef,undef);
-	my $entrybox2=gen_label_info(" Output file name:",$entry2);
-	
-	my $save = def_image_button('icons/save.png','Save');
-	$entrybox->pack_end($save,   FALSE, FALSE,0);
-
-	$main_table->attach_defaults ($v2  , 0, 12, 0,24);
-	$main_table->attach ($open,0, 3, 24,25,'expand','shrink',2,2);
-	$main_table->attach ($entrybox,3, 5, 24,25,'expand','shrink',2,2);
-	$main_table->attach ($entrybox2,5,6 , 24,25,'expand','shrink',2,2) if ($mode eq 'task');
-	$main_table->attach ($generate, 6, 9, 24,25,'expand','shrink',2,2);
-	
-
-	my $sc_win =add_widget_to_scrolled_win($main_table);
-	
-	
-	
-	$open-> signal_connect("clicked" => sub{ 
-		
-		load_workspace($self);
-		set_gui_status($self,"ref",5);
-	
-	});	
-
-	$save-> signal_connect("clicked" => sub{ 
-		save_as($self);		
-		set_gui_status($self,"ref",5);
-		
-	
-	});	
-	
-	$generate->signal_connect("clicked" => sub{ 
-		genereate_output_tasks($self) if ($mode eq 'task');
-		genereate_output_orcc ($self,$tview,$w) if ($mode eq 'orcc');
-	
-	});	
-	
-	
-	
-	
-	
-	
-	#check soc status every 0.5 second. refresh device table if there is any changes 
-	Glib::Timeout->add (100, sub{ 
-	   
-		my ($state,$timeout)= get_gui_status($self);
-		
-		if ($timeout>0){
-			$timeout--;
-			set_gui_status($self,$state,$timeout);	
-			return TRUE;
-			
-		}
-		if($state eq "ideal"){
-			return TRUE;
-			 
-		}
-		
-		
-		
-		#refresh GUI
-		my $saved_name=$self->object_get_attribute('save_as');
-		if(defined $saved_name) {$entry->set_text($saved_name);}
-		
-		$saved_name=$self->object_get_attribute('out_name');
-		if(defined $saved_name) {$entry2->set_text($saved_name);}
-		
-		
-		$notebook->destroy;
-		$notebook = trace_maker_notebook($self,$mode,$tview);
-		$v2 -> pack1($notebook, TRUE, TRUE); 							
-		
-		set_gui_status($self,"ideal",0);
-		
-		return TRUE;
-		
-	} );	
-
-	return $sc_win;
-	
-}
-
-
-	
+    my ($self,$mode,$ref,$w) = @_;
+    set_gui_status($self,"ideal",0);
+    $self->object_add_attribute ("process_notebook","currentpage",0);
+    if($mode eq 'task'){
+        $self->object_add_attribute('noc_param','T1',2);
+        $self->object_add_attribute('noc_param','T2',2);
+        $self->object_add_attribute('noc_param','T3',1);
+        $self->object_add_attribute('noc_param','Fpay',32);
+        $self->object_add_attribute('noc_param','V',1);    
+        $self->object_add_attribute('noc_param','C',1);        
+        $self->object_add_attribute('noc_param','TOPOLOGY','"MESH"');        
+    }
+    $self->object_add_attribute("file_id",undef,'a');
+    $self->object_add_attribute("trace_id",undef,0);
+    $self->object_add_attribute('select_multiple','action',"_");
+    $self->object_add_attribute('Auto','Auto_inject',"1\'b1");
+    if(defined $ref){
+        # add noc parameters
+        my %params=%{$ref};
+        foreach my $p (sort keys %params){
+            $self->{$p}=$params{$p};
+        }
+    }
+    my ($scwin_info,$tview)= create_txview();    
+    my $notebook = trace_maker_notebook($self,$mode,$tview);
+    my $tt = ($mode eq 'task') ? 0.65 : 0.55;
+    my $v2=gen_vpaned($notebook,$tt,$scwin_info);
+    set_gui_status($self,"ideal",0);
+    my $main_table= def_table(2,10,FALSE);
+    my $generate = def_image_button('icons/gen.png','Generate');
+    my $open = def_image_button('icons/browse.png','Load');    
+    my ($entrybox,$entry) = def_h_labeled_entry('Save as:',undef);
+    $entry->signal_connect( 'changed'=> sub{
+        my $name=$entry->get_text();
+        $self->object_add_attribute ("save_as",undef,$name);    
+    });    
+    my $entry2=gen_entry_object($self,'out_name',undef,undef,undef,undef);
+    my $entrybox2=gen_label_info(" Output file name:",$entry2);
+    my $save = def_image_button('icons/save.png','Save');
+    $entrybox->pack_end($save,   FALSE, FALSE,0);
+    $main_table->attach_defaults ($v2  , 0, 12, 0,24);
+    $main_table->attach ($open,0, 3, 24,25,'expand','shrink',2,2);
+    $main_table->attach ($entrybox,3, 5, 24,25,'expand','shrink',2,2);
+    $main_table->attach ($entrybox2,5,6 , 24,25,'expand','shrink',2,2) if ($mode eq 'task');
+    $main_table->attach ($generate, 6, 9, 24,25,'expand','shrink',2,2);
+    my $sc_win =add_widget_to_scrolled_win($main_table);
+    $open-> signal_connect("clicked" => sub{ 
+        load_workspace($self);
+        set_gui_status($self,"ref",5);
+    });    
+    $save-> signal_connect("clicked" => sub{ 
+        save_as($self);        
+        set_gui_status($self,"ref",5);
+    });    
+    $generate->signal_connect("clicked" => sub{ 
+        genereate_output_tasks($self) if ($mode eq 'task');
+        genereate_output_orcc ($self,$tview,$w) if ($mode eq 'orcc');
+    });    
+    #check soc status every 0.5 second. refresh device table if there is any changes 
+    Glib::Timeout->add (100, sub{ 
+        my ($state,$timeout)= get_gui_status($self);
+        if ($timeout>0){
+            $timeout--;
+            set_gui_status($self,$state,$timeout);    
+            return TRUE;
+        }
+        if($state eq "ideal"){
+            return TRUE;
+        }
+        #refresh GUI
+        my $saved_name=$self->object_get_attribute('save_as');
+        if(defined $saved_name) {$entry->set_text($saved_name);}
+        $saved_name=$self->object_get_attribute('out_name');
+        if(defined $saved_name) {$entry2->set_text($saved_name);}
+        $notebook->destroy;
+        $notebook = trace_maker_notebook($self,$mode,$tview);
+        $v2 -> pack1($notebook, TRUE, TRUE);                             
+        set_gui_status($self,"ideal",0);
+        return TRUE;
+    } );    
+    return $sc_win;
+}
\ No newline at end of file
diff --git a/mpsoc/perl_gui/lib/perl/traffic_pattern.pl b/mpsoc/perl_gui/lib/perl/traffic_pattern.pl
index 0cc4d67..b440818 100644
--- a/mpsoc/perl_gui/lib/perl/traffic_pattern.pl
+++ b/mpsoc/perl_gui/lib/perl/traffic_pattern.pl
@@ -5,223 +5,197 @@
 
 use FindBin;
 use lib $FindBin::Bin;
-		
 sub get_sample_emulation_param {
-	my ($emulate,$sample)=@_;
-	my $ref=$emulate->object_get_attribute($sample,"noc_info"); 
-	my %noc_info= %$ref;
-	my $topology=$noc_info{'TOPOLOGY'};
-	my $C=$noc_info{C};
-	my $T1=$noc_info{'T1'};
-	my $T2=$noc_info{'T2'};
-	my $T3=$noc_info{'T3'};
-	my $V =$noc_info{'V'};
-	my $Fpay = $noc_info{'Fpay'};	
-	return ($topology, $T1, $T2, $T3, $V, $Fpay);		
+    my ($emulate,$sample)=@_;
+    my $ref=$emulate->object_get_attribute($sample,"noc_info"); 
+    my %noc_info= %$ref;
+    my $topology=$noc_info{'TOPOLOGY'};
+    my $C=$noc_info{C};
+    my $T1=$noc_info{'T1'};
+    my $T2=$noc_info{'T2'};
+    my $T3=$noc_info{'T3'};
+    my $T4=$noc_info{'T4'};
+    my $V =$noc_info{'V'};
+    my $Fpay = $noc_info{'Fpay'};    
+    return ($topology, $T1, $T2, $T3, $T4, $V, $Fpay);        
 }
 
-
+sub get_sample_topology_info{
+    my ($self,$sample)= @_;
+    my ($topology, $T1, $T2, $T3, $T4, $V, $Fpay) = get_sample_emulation_param($self,$sample);
+    my ($NE, $NR, $RAw, $EAw, $Fw) = get_topology_info_sub ($topology, $T1, $T2, $T3, $T4, $V, $Fpay);
+    return ($NE, $NR, $RAw, $EAw, $Fw);
+}
 
 sub getBit{
-	my ($num, $b, $W)=@_;
-	while($b<0) {$b=$b+$W; }
-	$b=$b % $W;
-	return ($num >> $b) & 1;
+    my ($num, $b, $W)=@_;
+    while($b<0) {$b=$b+$W; }
+    $b=$b % $W;
+    return ($num >> $b) & 1;
 }
 
 # number; b:bit location;  W: number width log2(num); v: 1 assert the bit, 0 de-assert the bit; 
 sub setBit{
-	my ($num ,$b,$W,$v)=@_;
-	while($b<0) {$b=$b+$W;}
-	$b=$b % $W;
-		
+    my ($num ,$b,$W,$v)=@_;
+    while($b<0) {$b=$b+$W;}
+    $b=$b % $W;
     my $mask = 1 << $b;
     if ($v == 0) {$$num  = $$num & ~$mask;} # assert bit
     else {$$num = $$num | $mask;} #de-assert bit      
 }
 
 sub pck_dst_gen_2D {
-	my ($self,$sample,$traffic,$core_num,$line_num,$rnd)=@_;
-	my ($topology, $T1, $T2, $T3, $V, $Fpay) = get_sample_emulation_param($self,$sample);
-	my ($NE, $NR, $RAw, $EAw, $Fw) = get_topology_info_sub ($topology, $T1, $T2, $T3, $V, $Fpay);
-	
-	my $NEw=log2($NE);      
-	#for mesh-tori
-	my  ($current_l,$current_x, $current_y);
-	my  ($dest_l,$dest_x,$dest_y);
-	
-	($current_x,$current_y,$current_l)=mesh_tori_addrencod_sep($core_num,$T1, $T2,$T3);
-
-	if( $traffic eq "random") {				
-		my @randoms=@{$rnd};		
-		my $tmp = @{$randoms[$core_num]}[$line_num-1];
-		return endp_addr_encoder($self,$tmp);			
-	}
-	
-	if( $traffic eq "transposed 1"){
-		 $dest_x = $T1-$current_y-1;
-		 $dest_y = $T2-$current_x-1;
-		 $dest_l = $T3-$current_l-1;
-		 return mesh_tori_addr_join($dest_x,$dest_y,$dest_l,$T1, $T2,$T3);
-	}
-
-	if( $traffic eq "transposed 2"){
-		$dest_x = $current_y;
-		$dest_y = $current_x;
-		$dest_l = $current_l;
-		return mesh_tori_addr_join($dest_x,$dest_y,$dest_l,$T1, $T2,$T3);
-	}
-
-	if( $traffic eq "bit reverse"){
-		#di = sb−i−1
-		my $tmp=0;
-		for(my $i=0; $i< $NEw; $i++) {setBit(\$tmp, $i, $NEw, getBit($core_num, $NEw-$i-1, $NEw));}
-		return endp_addr_encoder($self,$tmp);		
-	}
-
-	if( $traffic  eq "bit complement") {
-		my $tmp=0;
-		for(my $i=0; $i< $NEw; $i++) {  setBit(\$tmp, $i, $NEw, getBit($core_num, $i, $NEw)==0)};
-		return endp_addr_encoder($self,$tmp);
-	}
-
-	if( $traffic eq "tornado") {
-		#[(x+(k/2-1)) mod k, (y+(k/2-1)) mod k],
-			$dest_x = (($current_x + (int($T1/2)-1)) % $T1);
-			$dest_y = (($current_y + (int($T2/2)-1)) % $T2);
-			$dest_l = $current_l;
-			return mesh_tori_addr_join($dest_x,$dest_y,$dest_l,$T1, $T2,$T3);
-     }
-
+    my ($self,$sample,$traffic,$core_num,$line_num,$rnd)=@_;
+    my ($topology, $T1, $T2, $T3, $T4, $V, $Fpay) = get_sample_emulation_param($self,$sample);
+    my ($NE, $NR, $RAw, $EAw, $Fw) = get_topology_info_sub ($topology, $T1, $T2, $T3, $T4, $V, $Fpay);
+    my $NEw=log2($NE);      
+    #for mesh-tori
+    my  ($current_l,$current_x, $current_y);
+    my  ($dest_l,$dest_x,$dest_y);
+    ($current_x,$current_y,$current_l)=mesh_tori_addrencod_sep($core_num,$T1, $T2,$T3);
+    if( $traffic eq "random") {                
+        my @randoms=@{$rnd};        
+        my $tmp = @{$randoms[$core_num]}[$line_num-1];
+        return endp_addr_encoder($self,$tmp);            
+    }
+    if( $traffic eq "transposed 1"){
+        $dest_x = $T1-$current_y-1;
+        $dest_y = $T2-$current_x-1;
+        $dest_l = $T3-$current_l-1;
+        return mesh_tori_addr_join($dest_x,$dest_y,$dest_l,$T1, $T2,$T3);
+    }
+    if( $traffic eq "transposed 2"){
+        $dest_x = $current_y;
+        $dest_y = $current_x;
+        $dest_l = $current_l;
+        return mesh_tori_addr_join($dest_x,$dest_y,$dest_l,$T1, $T2,$T3);
+    }
+    if( $traffic eq "bit reverse"){
+        #di = sb−i−1
+        my $tmp=0;
+        for(my $i=0; $i< $NEw; $i++) {setBit(\$tmp, $i, $NEw, getBit($core_num, $NEw-$i-1, $NEw));}
+        return endp_addr_encoder($self,$tmp);        
+    }
+    if( $traffic  eq "bit complement") {
+        my $tmp=0;
+        for(my $i=0; $i< $NEw; $i++) {  setBit(\$tmp, $i, $NEw, getBit($core_num, $i, $NEw)==0)};
+        return endp_addr_encoder($self,$tmp);
+    }
+    if( $traffic eq "tornado") {
+        #[(x+(k/2-1)) mod k, (y+(k/2-1)) mod k],
+            $dest_x = (($current_x + (int($T1/2)-1)) % $T1);
+            $dest_y = (($current_y + (int($T2/2)-1)) % $T2);
+            $dest_l = $current_l;
+            return mesh_tori_addr_join($dest_x,$dest_y,$dest_l,$T1, $T2,$T3);
+    }
     if($traffic eq "shuffle"){
-		#di = si−1 mod b
-		my $tmp=0;
-		for(my $i=0; $i< $NEw; $i++) { setBit(\$tmp, $i, $NEw, getBit($core_num, $i-1, $NEw));}
-		return endp_addr_encoder($self,$tmp);
-     }
-
+        #di = si−1 mod b
+        my $tmp=0;
+        for(my $i=0; $i< $NEw; $i++) { setBit(\$tmp, $i, $NEw, getBit($core_num, $i-1, $NEw));}
+        return endp_addr_encoder($self,$tmp);
+    }
     if($traffic eq "bit rotation"){
-		#di = si+1 mod b
-		my $tmp=0;
-		for(my $i=0; $i< $NEw; $i++) { setBit(\$tmp, $i, $NEw, getBit($core_num, $i+1, $NEw));}
-		return endp_addr_encoder($self,$tmp);
-     }
-
-     if($traffic eq "neighbor"){
-		#dx = sx + 1 mod k
-		#if ($current_x==0 && $current_y==0 && $current_l ==0) {
-	    #	$dest_x = 2;
-		# 	$dest_y = 2;
-		# 	$dest_l = 0;		
-		#}else {
-		#	$dest_x = $current_x;
-		# 	$dest_y = $current_y;
-		# 	$dest_l = $current_l;			
-		#}
-		#return mesh_tori_addr_join($dest_x,$dest_y,$dest_l,$T1, $T2,$T3);
-		
-		 $dest_x = ($current_x + 1) % $T1;
-		 $dest_y = ($current_y + 1) % $T2;
-		 $dest_l = $current_l;
-		 return mesh_tori_addr_join($dest_x,$dest_y,$dest_l,$T1, $T2,$T3);
-     } 
-     if($traffic eq "custom"){
-     	my $num=$self->object_get_attribute($sample,"CUSTOM_SRC_NUM");
-     	for (my $i=0;$i<$num;$i++){
-				my $src = $self->object_get_attribute($sample,"SRC_$i");
-				my $dst = $self->object_get_attribute($sample,"DST_$i");
-				return endp_addr_encoder($self,$dst) if($src == $core_num);
-     	}
-      	return endp_addr_encoder($self,$core_num);#off     
-     }       
-    
-		 print ("ERROR: $traffic is an unsupported traffic pattern\n");
-		 $dest_x = $current_x;
-		 $dest_y = $current_y;
-		 $dest_l = $current_l;
-		 return mesh_tori_addr_join($dest_x,$dest_y,$dest_l,$T1, $T2,$T3);
+        #di = si+1 mod b
+        my $tmp=0;
+        for(my $i=0; $i< $NEw; $i++) { setBit(\$tmp, $i, $NEw, getBit($core_num, $i+1, $NEw));}
+        return endp_addr_encoder($self,$tmp);
+    }
+    if($traffic eq "neighbor"){
+        #dx = sx + 1 mod k
+        #if ($current_x==0 && $current_y==0 && $current_l ==0) {
+        #    $dest_x = 2;
+        #     $dest_y = 2;
+        #     $dest_l = 0;        
+        #}else {
+        #    $dest_x = $current_x;
+        #     $dest_y = $current_y;
+        #     $dest_l = $current_l;            
+        #}
+        #return mesh_tori_addr_join($dest_x,$dest_y,$dest_l,$T1, $T2,$T3);
+        $dest_x = ($current_x + 1) % $T1;
+        $dest_y = ($current_y + 1) % $T2;
+        $dest_l = $current_l;
+        return mesh_tori_addr_join($dest_x,$dest_y,$dest_l,$T1, $T2,$T3);
+    } 
+    if($traffic eq "custom"){
+        my $num=$self->object_get_attribute($sample,"CUSTOM_SRC_NUM");
+        for (my $i=0;$i<$num;$i++){
+            my $src = $self->object_get_attribute($sample,"SRC_$i");
+            my $dst = $self->object_get_attribute($sample,"DST_$i");
+            return endp_addr_encoder($self,$dst) if($src == $core_num);
+        }
+        return endp_addr_encoder($self,$core_num);#off     
+    }       
+    print ("ERROR: $traffic is an unsupported traffic pattern\n");
+    $dest_x = $current_x;
+    $dest_y = $current_y;
+    $dest_l = $current_l;
+    return mesh_tori_addr_join($dest_x,$dest_y,$dest_l,$T1, $T2,$T3);
 }
 
-
-
-
 sub pck_dst_gen_1D {
-	my ($self,$sample,$traffic,$core_num,$line_num,$rnd)=@_;
-	my ($topology, $T1, $T2, $T3, $V, $Fpay) = get_sample_emulation_param($self,$sample);
-	my ($NE, $NR, $RAw, $EAw, $Fw) = get_topology_info_sub ($topology, $T1, $T2, $T3, $V, $Fpay);
-	my $NEw=log2($NE);      
-	    
-	if( $traffic eq "random") {				
-		my @randoms=@{$rnd};		
-		my $tmp = @{$randoms[$core_num]}[$line_num-1];
-		return endp_addr_encoder($self,$tmp);			
-	}		
-	
-	if( $traffic eq "transposed 1"){
-		  return endp_addr_encoder($self,$NE-$core_num-1);
-	} 
-	
-	if( $traffic eq "transposed 2"){
-		  return endp_addr_encoder($self,$NE-$core_num-1);
-	} 	
-	
-	if( $traffic eq "bit reverse"){
-		my $tmp=0;
-		for(my $i=0; $i< $NEw; $i++) {setBit(\$tmp, $i, $NEw, getBit($core_num, $NEw-$i-1, $NEw));}
-		return endp_addr_encoder($self,$tmp);		
-	 } 
-	 
-	 if( $traffic  eq "bit complement") {
-		my $tmp=0;
-		for(my $i=0; $i< $NEw; $i++) {  setBit(\$tmp, $i, $NEw, getBit($core_num, $i, $NEw)==0)};
-		return endp_addr_encoder($self,$tmp);
-	}
-	 
-	if( $traffic eq "tornado") {
-		#[(x+(k/2-1)) mod k, (y+(k/2-1)) mod k],
-		 return endp_addr_encoder($self, ($core_num + (int($NE/2)-1)) % $NE);
-     }
-
-      if($traffic eq "shuffle"){
-		#di = si−1 mod b
-		my $tmp=0;
-		for(my $i=0; $i< $NEw; $i++) { setBit(\$tmp, $i, $NEw, getBit($core_num, $i-1, $NEw));}
-		return endp_addr_encoder($self,$tmp);
-     }
-
+    my ($self,$sample,$traffic,$core_num,$line_num,$rnd)=@_;
+    my ($topology, $T1, $T2, $T3, $T4, $V, $Fpay) = get_sample_emulation_param($self,$sample);
+    my ($NE, $NR, $RAw, $EAw, $Fw) = get_topology_info_sub ($topology, $T1, $T2, $T3, $T4, $V, $Fpay);
+    my $NEw=log2($NE);      
+    if( $traffic eq "random") {                
+        my @randoms=@{$rnd};        
+        my $tmp = @{$randoms[$core_num]}[$line_num-1];
+        return endp_addr_encoder($self,$tmp);            
+    }        
+    if( $traffic eq "transposed 1"){
+        return endp_addr_encoder($self,$NE-$core_num-1);
+    } 
+    if( $traffic eq "transposed 2"){
+        return endp_addr_encoder($self,$NE-$core_num-1);
+    }     
+    if( $traffic eq "bit reverse"){
+        my $tmp=0;
+        for(my $i=0; $i< $NEw; $i++) {setBit(\$tmp, $i, $NEw, getBit($core_num, $NEw-$i-1, $NEw));}
+        return endp_addr_encoder($self,$tmp);        
+    } 
+    if( $traffic  eq "bit complement") {
+        my $tmp=0;
+        for(my $i=0; $i< $NEw; $i++) {  setBit(\$tmp, $i, $NEw, getBit($core_num, $i, $NEw)==0)};
+        return endp_addr_encoder($self,$tmp);
+    }
+    if( $traffic eq "tornado") {
+        #[(x+(k/2-1)) mod k, (y+(k/2-1)) mod k],
+        return endp_addr_encoder($self, ($core_num + (int($NE/2)-1)) % $NE);
+    }
+    if($traffic eq "shuffle"){
+        #di = si−1 mod b
+        my $tmp=0;
+        for(my $i=0; $i< $NEw; $i++) { setBit(\$tmp, $i, $NEw, getBit($core_num, $i-1, $NEw));}
+        return endp_addr_encoder($self,$tmp);
+    }
     if($traffic eq "bit rotation"){
-		#di = si+1 mod b
-		my $tmp=0;
-		for(my $i=0; $i< $NEw; $i++) { setBit(\$tmp, $i, $NEw, getBit($core_num, $i+1, $NEw));}
-		return endp_addr_encoder($self,$tmp);
-     }
-
-     if($traffic eq "neighbor"){
-		#dx = sx + 1 mod k
-		 return endp_addr_encoder($self,($core_num + 1) % $NE);
-	 } 
-	 
-	 if($traffic eq "custom"){
-     	my $num=$self->object_get_attribute($sample,"CUSTOM_SRC_NUM");
-     	for (my $i=0;$i<$num;$i++){
-				my $src = $self->object_get_attribute($sample,"SRC_$i");
-				my $dst = $self->object_get_attribute($sample,"DST_$i");
-				return endp_addr_encoder($self,$dst) if($src == $core_num);
-     	}
-      	return endp_addr_encoder($self,$core_num);#off     
-     }          
-     
-	 printf ("ERROR: $traffic is an unsupported traffic pattern\n");
-	 return  endp_addr_encoder($self,$core_num);
+        #di = si+1 mod b
+        my $tmp=0;
+        for(my $i=0; $i< $NEw; $i++) { setBit(\$tmp, $i, $NEw, getBit($core_num, $i+1, $NEw));}
+        return endp_addr_encoder($self,$tmp);
+    }
+    if($traffic eq "neighbor"){
+        #dx = sx + 1 mod k
+        return endp_addr_encoder($self,($core_num + 1) % $NE);
+    } 
+    if($traffic eq "custom"){
+        my $num=$self->object_get_attribute($sample,"CUSTOM_SRC_NUM");
+        for (my $i=0;$i<$num;$i++){
+            my $src = $self->object_get_attribute($sample,"SRC_$i");
+            my $dst = $self->object_get_attribute($sample,"DST_$i");
+            return endp_addr_encoder($self,$dst) if($src == $core_num);
+        }
+        return endp_addr_encoder($self,$core_num);#off     
+    }          
+    printf ("ERROR: $traffic is an unsupported traffic pattern\n");
+    return  endp_addr_encoder($self,$core_num);
 }
 
-
 sub pck_dst_gen{ 
-	my ($self,$sample,$traffic,$core_num,$line_num,$rnd)=@_;
-	my ($topology, $T1, $T2, $T3, $V, $Fpay) = get_sample_emulation_param($self,$sample);
-	return  pck_dst_gen_2D ($self,$sample,$traffic,$core_num,$line_num,$rnd) if(( $topology eq '"MESH"') ||( $topology eq '"TORUS"'));
-	return  pck_dst_gen_1D ($self,$sample,$traffic,$core_num,$line_num,$rnd);
+    my ($self,$sample,$traffic,$core_num,$line_num,$rnd)=@_;
+    my ($topology, $T1, $T2, $T3, $T4, $V, $Fpay) = get_sample_emulation_param($self,$sample);
+    return  pck_dst_gen_2D ($self,$sample,$traffic,$core_num,$line_num,$rnd) if(( $topology eq '"MESH"') ||( $topology eq '"TORUS"'));
+    return  pck_dst_gen_1D ($self,$sample,$traffic,$core_num,$line_num,$rnd);
 }
-
- 1;       
-    
+1;
\ No newline at end of file
diff --git a/mpsoc/perl_gui/lib/perl/tsort.pm b/mpsoc/perl_gui/lib/perl/tsort.pm
index cdaa055..2592202 100644
--- a/mpsoc/perl_gui/lib/perl/tsort.pm
+++ b/mpsoc/perl_gui/lib/perl/tsort.pm
@@ -1,30 +1,23 @@
 #!/usr/bin/perl
- 
- 
-
 package Algorithm::TSort;
 use 5.007003;
 use strict;
 use warnings;
 require Exporter;
 our @ISA = qw(Exporter);
-
 # Items to export into callers namespace by default. Note: do not export
 # names by default without a very good reason. Use EXPORT_OK instead.
 # Do not simply export all your public functions/methods/constants.
-
-# This allows declaration	use Algorithm::TSort ':all';
+# This allows declaration    use Algorithm::TSort ':all';
 # If you do not need this, moving things directly into @EXPORT or @EXPORT_OK
 # will save memory.
 our %EXPORT_TAGS = ( 'all' => [ qw(
-	tsort
-	Graph	
+    tsort
+    Graph    
 ) ] );
 
 our @EXPORT_OK = ( @{ $EXPORT_TAGS{'all'} } );
-
 our @EXPORT = qw( tsort );
-
 our $VERSION = '0.05';
 {
     package Algorithm::TSort::ADJ;
@@ -36,7 +29,6 @@ our $VERSION = '0.05';
         }
         return ();
     }
-
     sub nodes {
         return keys %{ $_[0] };
     }
@@ -48,12 +40,12 @@ our $VERSION = '0.05';
     }
     package Algorithm::TSort::ADJSUB_ARRAYREF;
     sub adj_nodes {
-	my $array = $_[0]->( $_[1] );
-	return $array ? @$array : ();
+    my $array = $_[0]->( $_[1] );
+    return $array ? @$array : ();
     }
     package Algorithm::TSort::Guard;
     sub new{
-	return bless $_[1], $_[0];
+    return bless $_[1], $_[0];
     }
     sub DESTROY { $_[0]->() };
 }
@@ -116,10 +108,8 @@ sub tsort($;@) {
         }
     }
     $guard = Algorithm::TSort::Guard->new(sub {
-	$req_sub = undef; # remove circular dependency;
+    $req_sub = undef; # remove circular dependency;
     });
-
-
     $req_sub = sub {
         my $node = shift;
         if ( $seen{$node} ) {
@@ -133,7 +123,6 @@ sub tsort($;@) {
         $seen{$node} = 2;
         push @sorted, $node;
     };
-
     for (@nodes) {
         next if $seen{$_};
         $req_sub->($_);
@@ -141,9 +130,6 @@ sub tsort($;@) {
     return reverse @sorted;
 }
 
-
-
-
 sub  cicle_detect($;@) {
     my $object = shift;
     my @nodes  = @_;
@@ -162,16 +148,14 @@ sub  cicle_detect($;@) {
         }
     }
     $guard = Algorithm::TSort::Guard->new(sub {
-	$req_sub = undef; # remove circular dependency;
+    $req_sub = undef; # remove circular dependency;
     });
-
-
     $req_sub = sub {
         my $node = shift;
         if ( $seen{$node} ) {
             #die "Algorithm::TSort - can't tsort cicle detected" if ( $seen{$node} == 1 );
-	     $cyclic=1 if ( $seen{$node} == 1 );          
-		return;
+        $cyclic=1 if ( $seen{$node} == 1 );          
+        return;
         }
         $seen{$node} = 1;
         for ( $object->adj_nodes($node) ) {
@@ -180,7 +164,6 @@ sub  cicle_detect($;@) {
         $seen{$node} = 2;
         push @sorted, $node;
     };
-
     for (@nodes) {
         next if $seen{$_};
         $req_sub->($_);
@@ -188,18 +171,6 @@ sub  cicle_detect($;@) {
     return $cyclic;
 }
 
-
-
-
-
-
-
-
-
-
-
-
-
 1;
 __END__
 # Below is stub documentation for your module. You'd better edit it!
@@ -218,12 +189,12 @@ Algorithm::TSort - Perl extension for topological sort
   say for @sorted; 
 
   # -- OR --
-	
+    
   # $adj_sub = sub { return unless $adj->{ $_[0] } ; return @{$adj->{$_[0]}}; };
   my (@sorted) = tsort( Graph( ADJSUB => $adj_sub ), @nodes_for_sort );
 
   # -- OR --
-	
+    
   # $sub_arrayref = sub { $adj->{ $_[0] } };
   my (@sorted) = tsort( Graph( ADJSUB_ARRAYREF => $adj_sub ), @nodes_for_sort );
 
diff --git a/mpsoc/perl_gui/lib/perl/uart.pl b/mpsoc/perl_gui/lib/perl/uart.pl
index 547c1d1..3d72e2a 100644
--- a/mpsoc/perl_gui/lib/perl/uart.pl
+++ b/mpsoc/perl_gui/lib/perl/uart.pl
@@ -1,27 +1,18 @@
 #!/usr/bin/perl -w
-
 use strict;
 use warnings;
-
 use FindBin;
 use lib $FindBin::Bin;
-
 require "widget.pl";
-
-
 use constant::boolean;
-
-
 use Data::Dumper;
 use File::Which;
 use File::Basename;
-
 use IPC::Run qw( harness start pump finish timeout );
 use String::Scanf; # imports sscanf()
 use base 'Class::Accessor::Fast';
-
-
 use Consts;
+
 BEGIN {
     my $module = (Consts::GTK_VERSION==2) ? 'Gtk2' : 'Gtk3';
     my $file = $module;
@@ -31,261 +22,204 @@ BEGIN
     $module->import;
 }
 
-
-
 __PACKAGE__->mk_accessors(qw{
-	window
-	sourceview		
+    window
+    sourceview
 });
 
 my $NAME = 'Uart Terminal';
-my 	$path = "";
+my     $path = "";
 our $FONT_SIZE='default';
 our $ICON_SIZE='default';
-
-
-
 sub uart_stand_alone(){
-	$path = "../../";
-	set_path_env();
-	my $project_dir	  = get_project_dir(); #mpsoc dir addr
-	my $paths_file= "$project_dir/mpsoc/perl_gui/lib/Paths";
-	if (-f 	$paths_file){#} && defined $ENV{PRONOC_WORK} ) {
-		my $paths= do $paths_file;
-		my %p=%{$paths};
-		$FONT_SIZE= $p{'GUI_SETTING'}{'FONT_SIZE'} if (defined $p{'GUI_SETTING'}{'FONT_SIZE'});
-		$ICON_SIZE= $p{'GUI_SETTING'}{'ICON_SIZE'} if (defined $p{'GUI_SETTING'}{'ICON_SIZE'});
-	}
-	
-	set_defualt_font_size();
-	my $window=uart_main();
-	$window->signal_connect (destroy => sub { gui_quite();});	
+    $path = "../../";
+    set_path_env();
+    my $project_dir      = get_project_dir(); #mpsoc dir addr
+    my $paths_file= "$project_dir/mpsoc/perl_gui/lib/Paths";
+    if (-f     $paths_file){#} && defined $ENV{PRONOC_WORK} ) {
+        my $paths= do $paths_file;
+        my %p=%{$paths};
+        $FONT_SIZE= $p{'GUI_SETTING'}{'FONT_SIZE'} if (defined $p{'GUI_SETTING'}{'FONT_SIZE'});
+        $ICON_SIZE= $p{'GUI_SETTING'}{'ICON_SIZE'} if (defined $p{'GUI_SETTING'}{'ICON_SIZE'});
+    }
+    set_defualt_font_size();
+    my $window=uart_main();
+    $window->signal_connect (destroy => sub { gui_quite();});
 }
 
 exit gtk_gui_run(\&uart_stand_alone) unless caller;
 
-
-
-
 sub create_rsv_box {
-	my ($self,$num)=@_;
-	my ($sw,$tview) =create_txview(); 
+    my ($self,$num)=@_;
+    my ($sw,$tview) =create_txview();
     $sw->set_policy('never','automatic');
     $sw->set_border_width(3);
     my($width,$hight)=max_win_size();
-	$sw->set_size_request($width/10,$hight/10);
+    $sw->set_size_request($width/10,$hight/10);
     my $frame = gen_frame();
-	$frame->set_shadow_type ('in');
-	$frame->add ($sw);
-	my $def = 126-$num;
-	my $spin=gen_spin_object($self,'CTRL',"INDEX_$num",'0,128,1',$def,undef,undef);	
-	my $label=gen_label_in_center("INDEX#");
-	my $box=def_pack_hbox( FALSE, 0 , $label,$spin);	
-	$frame->set_label_widget ($box);        
-    return ($frame,$tview);	
+    $frame->set_shadow_type ('in');
+    $frame->add ($sw);
+    my $def = 126-$num;
+    my $spin=gen_spin_object($self,'CTRL',"INDEX_$num",'0,128,1',$def,undef,undef);
+    my $label=gen_label_in_center("INDEX#");
+    my $box=def_pack_hbox( FALSE, 0 , $label,$spin);
+    $frame->set_label_widget ($box);
+    return ($frame,$tview);
 }
 
-
-
 sub receive_boxes{
-	my $self=shift;
-	my $table= def_table(2,10,FALSE);	
-	my $scrolled_win=gen_scr_win_with_adjst ($self,"receive_box");
-	add_widget_to_scrolled_win($table,$scrolled_win);
-	my $num = $self->object_get_attribute('CTRL','UART_NUM');
-	my $dim_y = floor(sqrt($num));
-	my @tviews;
-	for (my $i=0; $i<$num; $i+=1){	
-			my ($box,$tview) = create_rsv_box($self,$i);
-			$tviews[$i]=$tview;  			
-  			my $y= int($i/$dim_y);
-    		my $x= $i % $dim_y;    		
-	        $table->attach_defaults ($box, $x, $x+1 , $y, $y+1);	
-	}	
-	return ($scrolled_win,\@tviews);
+    my $self=shift;
+    my $table= def_table(2,10,FALSE);
+    my $scrolled_win=gen_scr_win_with_adjst ($self,"receive_box");
+    add_widget_to_scrolled_win($table,$scrolled_win);
+    my $num = $self->object_get_attribute('CTRL','UART_NUM');
+    my $dim_y = floor(sqrt($num));
+    my @tviews;
+    for (my $i=0; $i<$num; $i+=1){
+            my ($box,$tview) = create_rsv_box($self,$i);
+            $tviews[$i]=$tview;
+            my $y= int($i/$dim_y);
+            my $x= $i % $dim_y;
+            $table->attach_defaults ($box, $x, $x+1 , $y, $y+1);
+    }
+    return ($scrolled_win,\@tviews);
 }
 
 sub ctrl_boxes{
-	my ($self,$main_tview)=@_;
-	
-	my $state=$self->object_get_attribute("CTRL","RUN");
-	if (!defined $state){
-		$state='OFF' ;
-		$self->object_add_attribute("CTRL","RUN",$state);
-	}		
-	
-	
-	my $table= def_table(2,10,FALSE);	
-	my $scrolled_win=add_widget_to_scrolled_win ($table);
-	my ($row,$col)=(0,0);
-	my @info = (
-	#TODO add Altera_Qsys_UART
-		{ label=>" UART name ", param_name=>'UART_NAME', type=>"Combo-box", default_val=>'ProNoC_XILINX_UART', content=>"ProNoC_XILINX_UART,ProNoC_ALTERA_UART", info=>undef, param_parent=>'CTRL', ref_delay=> 1, new_status=>'ref_ctrl', loc=>'vertical'},
-		{ label=>" Number of UART", param_name=>'UART_NUM', type=>"Spin-button", default_val=>1, content=>"1,128,1", info=>undef, param_parent=>'CTRL', ref_delay=> 1, new_status=>'ref_all', loc=>'vertical'}		
-		
-	);	
-	
-	
-	my $uname= $self->object_get_attribute('CTRL','UART_NAME');
-	$uname = 'ProNoC_XILINX_UART' if(!defined $uname);
-	if ($uname eq "ProNoC_XILINX_UART" ) {
-		push (@info,{ label=>" JTAG CHAIN ", param_name=>'JTAG_CHAIN', type=>"Combo-box", default_val=>3, content=>"1,2,3,4", info=>undef, param_parent=>'CTRL', ref_delay=> 1, new_status=>'ref_ctrl', loc=>'vertical'}) ;
-		push (@info,{ label=>" JTAG TARGET ", param_name=>'JTAG_TARGET', type=>"Spin-button", default_val=>3, content=>"1,128,1", info=>"The FPGA device target number in the Jtag chain. Click on the front magnifier Icon to see the list of devices in your board JTAG chain.", param_parent=>'CTRL', ref_delay=> 1, new_status=>'ref_ctrl', loc=>'vertical'}) ;
-	}elsif ($uname eq "ProNoC_ALTERA_UART" ) {
-		my $list= $self->object_get_attribute('CTRL','quartus_device_list');
-		push (@info,{ label=>" Hardware Name", param_name=>'quartus_hardware', type=>"Entry", default_val=>undef, content=>undef, info=>undef, param_parent=>'CTRL', ref_delay=> 1, new_status=>undef, loc=>'vertical'}) ;
-		push (@info,{ label=>" Device Number",   param_name=>'quartus_device',   type=>"EntryCombo", default_val=>undef,  content=>$list, info=>undef,param_parent=>'CTRL', ref_delay=> 1, new_status=>undef, loc=>'vertical'}) ;
-	}
-	
-	
-	my @restricted_params= ('UART_NAME','JTAG_TARGET','quartus_hardware','quartus_device');
-	
-	foreach my $d (@info) {
-		my $wiget;		
-		($row,$col,$wiget)=add_param_widget  ($self, $d->{label}, $d->{param_name}, $d->{default_val}, $d->{type}, $d->{content}, $d->{info}, $table,$row,$col,1, $d->{param_parent}, $d->{ref_delay}, $d->{new_status}, $d->{loc});
-		
-		#the following parameter should not be changed while the jtag connection is stablished
-		if($state eq "ON"){
-			$wiget->set_sensitive (FALSE) if (check_scolar_exist_in_array($d->{param_name},\@restricted_params )); 
-		}
-		
-		
-		if($d->{param_name} eq 'JTAG_TARGET' || $d->{param_name} eq "quartus_hardware"){
-			my $search=def_image_button($path."icons/browse.png");
-			$table->attach ($search,  4, 5,$row-1,$row,'shrink','shrink',2,2); 
-			set_tip($search, "Display all Jtag targets. You need to connect your FPGA device to your PC first."); 
-			$search-> signal_connect("clicked" => sub{
-				show_all_xilinx_targets ($self,$main_tview) if($uname eq "ProNoC_XILINX_UART");
-				capture_altera_jtag_info($self,$main_tview) if($uname eq "ProNoC_ALTERA_UART");
-			}); 			
-			
-		}
-	} 
-	
-	
-	
-	$col=0;
-	my $label=gen_label_in_left(" JTAG Connect ");
-	my $run= ($state eq 'ON')? def_colored_button('ON',17): def_colored_button('OFF',4); 
-	$table->attach ($label,  $col, $col+1,$row,$row+1,'fill','shrink',2,2); $col+=1; 
-	$table->attach ($run,  $col, $col+1,$row,$row+1,'shrink','shrink',2,2); $row++;$col=0;
-	$run -> signal_connect("clicked" => sub{ 
-			my $state=$self->object_get_attribute("CTRL","RUN");			
-			my $new = ($state eq "ON")? "OFF" : "ON";
-			$self->object_add_attribute("CTRL","CONNECT",1) if($new eq 'ON');
-			$self->object_add_attribute("CTRL","DISCONNECT",1) if($new eq 'OFF');
-			set_gui_status($self,"ON-OFF",1);		
-	});		
-	
-	return $scrolled_win;
+    my ($self,$main_tview)=@_;
+    my $state=$self->object_get_attribute("CTRL","RUN");
+    if (!defined $state){
+        $state='OFF' ;
+        $self->object_add_attribute("CTRL","RUN",$state);
+    }
+    my $table= def_table(2,10,FALSE);
+    my $scrolled_win=add_widget_to_scrolled_win ($table);
+    my ($row,$col)=(0,0);
+    my @info = (
+    #TODO add Altera_Qsys_UART
+        { label=>" UART name ", param_name=>'UART_NAME', type=>"Combo-box", default_val=>'ProNoC_XILINX_UART', content=>"ProNoC_XILINX_UART,ProNoC_ALTERA_UART", info=>undef, param_parent=>'CTRL', ref_delay=> 1, new_status=>'ref_ctrl', loc=>'vertical'},
+        { label=>" Number of UART", param_name=>'UART_NUM', type=>"Spin-button", default_val=>1, content=>"1,128,1", info=>undef, param_parent=>'CTRL', ref_delay=> 1, new_status=>'ref_all', loc=>'vertical'}
+    );
+    my $uname= $self->object_get_attribute('CTRL','UART_NAME');
+    $uname = 'ProNoC_XILINX_UART' if(!defined $uname);
+    if ($uname eq "ProNoC_XILINX_UART" ) {
+        push (@info,{ label=>" JTAG CHAIN ", param_name=>'JTAG_CHAIN', type=>"Combo-box", default_val=>3, content=>"1,2,3,4", info=>undef, param_parent=>'CTRL', ref_delay=> 1, new_status=>'ref_ctrl', loc=>'vertical'}) ;
+        push (@info,{ label=>" JTAG TARGET ", param_name=>'JTAG_TARGET', type=>"Spin-button", default_val=>3, content=>"1,128,1", info=>"The FPGA device target number in the Jtag chain. Click on the front magnifier Icon to see the list of devices in your board JTAG chain.", param_parent=>'CTRL', ref_delay=> 1, new_status=>'ref_ctrl', loc=>'vertical'}) ;
+    }elsif ($uname eq "ProNoC_ALTERA_UART" ) {
+        my $list= $self->object_get_attribute('CTRL','quartus_device_list');
+        push (@info,{ label=>" Hardware Name", param_name=>'quartus_hardware', type=>"Entry", default_val=>undef, content=>undef, info=>undef, param_parent=>'CTRL', ref_delay=> 1, new_status=>undef, loc=>'vertical'}) ;
+        push (@info,{ label=>" Device Number",   param_name=>'quartus_device',   type=>"EntryCombo", default_val=>undef,  content=>$list, info=>undef,param_parent=>'CTRL', ref_delay=> 1, new_status=>undef, loc=>'vertical'}) ;
+    }
+    my @restricted_params= ('UART_NAME','JTAG_TARGET','quartus_hardware','quartus_device');
+    foreach my $d (@info) {
+        my $wiget;
+        ($row,$col,$wiget)=add_param_widget  ($self, $d->{label}, $d->{param_name}, $d->{default_val}, $d->{type}, $d->{content}, $d->{info}, $table,$row,$col,1, $d->{param_parent}, $d->{ref_delay}, $d->{new_status}, $d->{loc});
+        #the following parameter should not be changed while the jtag connection is stablished
+        if($state eq "ON"){
+            $wiget->set_sensitive (FALSE) if (check_scolar_exist_in_array($d->{param_name},\@restricted_params ));
+        }
+        if($d->{param_name} eq 'JTAG_TARGET' || $d->{param_name} eq "quartus_hardware"){
+            my $search=def_image_button($path."icons/browse.png");
+            $table->attach ($search,  4, 5,$row-1,$row,'shrink','shrink',2,2);
+            set_tip($search, "Display all Jtag targets. You need to connect your FPGA device to your PC first.");
+            $search-> signal_connect("clicked" => sub{
+                show_all_xilinx_targets ($self,$main_tview) if($uname eq "ProNoC_XILINX_UART");
+                capture_altera_jtag_info($self,$main_tview) if($uname eq "ProNoC_ALTERA_UART");
+            });
+        }
+    }
+    $col=0;
+    my $label=gen_label_in_left(" JTAG Connect ");
+    my $run= ($state eq 'ON')? def_colored_button('ON',17): def_colored_button('OFF',4);
+    $table->attach ($label,  $col, $col+1,$row,$row+1,'fill','shrink',2,2); $col+=1;
+    $table->attach ($run,  $col, $col+1,$row,$row+1,'shrink','shrink',2,2); $row++;$col=0;
+    $run -> signal_connect("clicked" => sub{
+            my $state=$self->object_get_attribute("CTRL","RUN");
+            my $new = ($state eq "ON")? "OFF" : "ON";
+            $self->object_add_attribute("CTRL","CONNECT",1) if($new eq 'ON');
+            $self->object_add_attribute("CTRL","DISCONNECT",1) if($new eq 'OFF');
+            set_gui_status($self,"ON-OFF",1);
+    });
+    return $scrolled_win;
 }
 
-
-
 sub select_uart_board {
-	my ($self,$table,$vendor,$row,$col)=@_;
-	
-	#get the list of boards located in "boards/*" folder
-	my @dirs = grep {-d} glob("$path/../boards/$vendor/*");
-	my ($fpgas,$init);
-	$fpgas="";
-	
-	foreach my $dir (@dirs) {
-		my ($name,$fpath,$suffix) = fileparse("$dir",qr"\..[^.]*$");
-		
-		$fpgas= (defined $fpgas)? "$fpgas,$name" : "$name";	
-		$init="$name";	
-	}
-	my $button=def_image_button("$path/icons/help.png");
-	my $help1= "The list of supported boards are obtained from \"mpsoc/boards/$vendor\" path. You can add your boards by adding its required files in aforementioned path";
-	$button->signal_connect("clicked" => sub {message_dialog($help1);});	
-	my $combo=gen_combobox_object ($self,'compile','board',$fpgas,$init,undef,undef);	
-	$table->attach(gen_label_in_left('Targeted Board:'),$col,$col+1,$row,$row+1,'fill','shrink',2,2);$col++;
-	$table->attach($button,$col,$col+1,$row,$row+1,'fill','shrink',2,2);$col++;
-	$table->attach($combo, $col,$col+1,$row,$row+1,'fill','shrink',2,2);$row++;
-		
-	#do not change the board when the connection is ON
-	my $state=$self->object_get_attribute("CTRL","RUN");
-	$combo->set_sensitive (FALSE) if($state eq "ON" );	
-		
-	
+    my ($self,$table,$vendor,$row,$col)=@_;
+    #get the list of boards located in "boards/*" folder
+    my @dirs = grep {-d} glob("$path/../boards/$vendor/*");
+    my ($fpgas,$init);
+    $fpgas="";
+    foreach my $dir (@dirs) {
+        my ($name,$fpath,$suffix) = fileparse("$dir",qr"\..[^.]*$");
+        $fpgas= (defined $fpgas)? "$fpgas,$name" : "$name";
+        $init="$name";
+    }
+    my $button=def_image_button("$path/icons/help.png");
+    my $help1= "The list of supported boards are obtained from \"mpsoc/boards/$vendor\" path. You can add your boards by adding its required files in aforementioned path";
+    $button->signal_connect("clicked" => sub {message_dialog($help1);});
+    my $combo=gen_combobox_object ($self,'compile','board',$fpgas,$init,undef,undef);
+    $table->attach(gen_label_in_left('Targeted Board:'),$col,$col+1,$row,$row+1,'fill','shrink',2,2);$col++;
+    $table->attach($button,$col,$col+1,$row,$row+1,'fill','shrink',2,2);$col++;
+    $table->attach($combo, $col,$col+1,$row,$row+1,'fill','shrink',2,2);$row++;
+    #do not change the board when the connection is ON
+    my $state=$self->object_get_attribute("CTRL","RUN");
+    $combo->set_sensitive (FALSE) if($state eq "ON" );
 }
 
-
-
 sub capture_altera_jtag_info {
-	my ($self,$tview) = @_;
-	my $command=  "$ENV{QUARTUS_BIN}/jtagconfig";
-	#add_info($tview,"$command\n");
-	my $stdout= run_cmd_textview_errors($command,$tview);
-	if(!defined $stdout){
-		add_colored_info($tview,"No JTAG Hardware is detected\n",'red');
-		return 1; 
-	}
-	#add_info($tview,"$stdout\n");
-	my @a=split /1\)\s+/, $stdout; 
-	if(!defined $a[1]){
-		add_colored_info($tview,"No JTAG Hardware is detected\n",'red');
-		return 1;
-	}
-	my @b=split /\s+/, $a[1]; 
-	my $hw=$b[0];
-	
-	
-	
-	
-	my @devs=split /\n/, $stdout; 
-	
-	$self->object_add_attribute('CTRL','quartus_hardware',$hw);
-	add_colored_info($tview,"Detected Hardware: $hw\n",'blue');
-	
-	#capture device name in JTAG chain
-		
-	my $i=0;
-	my $info="";
-	my $list;
-	foreach my $p (@devs){
-		next if ($p =~/^\s*1\)/); 
-		$i++;
-		$info .= "\t $i : $p\n"; 
-		$list= (defined $list) ? "$list,$i" : $i;
-		
-	}
-	
-	$info = "There are total of $i devices in JTAG chain:\n $info. Select the corresponding Jtag device number which the serial port is connected to\n";
-		
-	
-	my $names = join (',',@devs);
-	add_colored_info($tview,"$info",'blue');
-	$self->object_add_attribute('CTRL','quartus_device_list',$list);
-	$self->object_add_attribute('CTRL','quartus_device',$i);
-	set_gui_status($self,'ref_ctrl',1);	   
-	return 0;		
+    my ($self,$tview) = @_;
+    my $command=  "$ENV{QUARTUS_BIN}/jtagconfig";
+    #add_info($tview,"$command\n");
+    my $stdout= run_cmd_textview_errors($command,$tview);
+    if(!defined $stdout){
+        add_colored_info($tview,"No JTAG Hardware is detected\n",'red');
+        return 1;
+    }
+    #add_info($tview,"$stdout\n");
+    my @a=split /1\)\s+/, $stdout;
+    if(!defined $a[1]){
+        add_colored_info($tview,"No JTAG Hardware is detected\n",'red');
+        return 1;
+    }
+    my @b=split /\s+/, $a[1];
+    my $hw=$b[0];
+    my @devs=split /\n/, $stdout;
+    $self->object_add_attribute('CTRL','quartus_hardware',$hw);
+    add_colored_info($tview,"Detected Hardware: $hw\n",'blue');
+    #capture device name in JTAG chain
+    my $i=0;
+    my $info="";
+    my $list;
+    foreach my $p (@devs){
+        next if ($p =~/^\s*1\)/);
+        $i++;
+        $info .= "\t $i : $p\n";
+        $list= (defined $list) ? "$list,$i" : $i;
+    }
+    $info = "There are total of $i devices in JTAG chain:\n $info. Select the corresponding Jtag device number which the serial port is connected to\n";
+    my $names = join (',',@devs);
+    add_colored_info($tview,"$info",'blue');
+    $self->object_add_attribute('CTRL','quartus_device_list',$list);
+    $self->object_add_attribute('CTRL','quartus_device',$i);
+    set_gui_status($self,'ref_ctrl',1);
+    return 0;
 }
 
-
-
-
-
-
-
 sub show_all_xilinx_targets{
-	my ($self,$tview) =@_;
-	my ($pipe,$in, $out, $err,$r);
-	my $xsct = which('xsct');	
-	
-	#check if $xsct exits
-	unless(-f $xsct){
-		add_colored_info($tview,"Error xsct not found. Please add the path to xilinx/SDK/bin to your \$PATH environment\n",'red');
-		return 0;	
-	}	
-	my @cat = ( $xsct );
-	$pipe =start \@cat, \$in, \$out, \$err or $r=$?;
-	if(defined $r){
-		add_colored_info($tview," quartus_stp got an Error: $r\n",'red');
-		return 0;		
-	}
-
+    my ($self,$tview) =@_;
+    my ($pipe,$in, $out, $err,$r);
+    my $xsct = which('xsct');
+    #check if $xsct exits
+    unless(-f $xsct){
+        add_colored_info($tview,"Error xsct not found. Please add the path to xilinx/SDK/bin to your \$PATH environment\n",'red');
+        return 0;
+    }
+    my @cat = ( $xsct );
+    $pipe =start \@cat, \$in, \$out, \$err or $r=$?;
+    if(defined $r){
+        add_colored_info($tview," quartus_stp got an Error: $r\n",'red');
+        return 0;
+    }
     $in = "";
     return 0 unless run_xsct_pipe($self,\$pipe,\$in,\$out,\$err,$tview);
     $in = "set jseq [jtag sequence]\n connect\n";
@@ -293,404 +227,325 @@ sub show_all_xilinx_targets{
     $in = "set R [jtag targets]\n puts \$R \n";
     return 0 unless run_xsct_pipe($self,\$pipe,\$in,\$out,\$err,$tview);
     if (length ($out)> 10){
-    	add_colored_info($tview,"targets are:\n $out .\n",'blue');    	
+        add_colored_info($tview,"targets are:\n $out .\n",'blue');
     }else {
-    	add_colored_info($tview,"No Jtag target is detected. Make sure your FPGA board is connected to the PC and it is powered on.\n",'red');
-    } 
-	close_xsct($self,\$pipe,$tview,\$in, \$out, \$err);
-	return $out;
+        add_colored_info($tview,"No Jtag target is detected. Make sure your FPGA board is connected to the PC and it is powered on.\n",'red');
+    }
+    close_xsct($self,\$pipe,$tview,\$in, \$out, \$err);
+    return $out;
 }
 
-
-
 sub sender_box{
-	my ($self,$main_tview)=@_;
-	my $table= def_table(2,10,FALSE);	
-	my $scrolled_win=add_widget_to_scrolled_win ($table);
-	my ($sw,$tview) =create_txview(); 
+    my ($self,$main_tview)=@_;
+    my $table= def_table(2,10,FALSE);
+    my $scrolled_win=add_widget_to_scrolled_win ($table);
+    my ($sw,$tview) =create_txview();
     $sw->set_policy('never','automatic');
     $sw->set_border_width(3);
     my($width,$hight)=max_win_size();
-	$sw->set_size_request($width/10,$hight/10);
+    $sw->set_size_request($width/10,$hight/10);
     my $frame = gen_frame();
-	$frame->set_shadow_type ('in');
-	$frame->add ($sw);
-	my $num = $self->object_get_attribute('CTRL','UART_NUM');
-	my @indexs;
-	my $def;
-	for (my $i=0; $i<$num; $i+=1){	
-		my $index= $self->object_get_attribute("CTRL","INDEX_$i");	
-		$def= $index if(!defined $def);
-		$indexs[$i]=$index;
-	}
-	my $indexs = join(',',@indexs);
-	my $comb=gen_combobox_object($self,'CTRL',"SEND_TO_INDEX",$indexs,$def,undef,undef);	
-	my $label=gen_label_in_center("SEND_TO INDEX#");
-	my $send = def_image_button($path.'icons/run.png');	
-	my $box=def_pack_hbox( FALSE, 0 , $label,$comb,$send);	
-	$frame->set_label_widget ($box);   		
-	$table->attach_defaults ($frame, 0, 1 , 0,1);
-	$send-> signal_connect("clicked" => sub{ 
-			my $st =$self->object_get_attribute("CTRL","RUN");
-			my $index =$self->object_get_attribute("CTRL","SEND_TO_INDEX");
-			if ($st eq 'OFF'){
-				add_colored_info($main_tview,"Error: Cannot send the data. Jtag connection is not established yet.\n",'red');
-				return;
-			}
-			my $text_buffer = $tview->get_buffer;
-	        my $txt=$text_buffer->get_text($text_buffer->get_bounds, TRUE);
-			if(length ($txt) >0 ){	
-				my $buf=$self->object_get_attribute("SEND","TXT_$index");
-				$txt=	$buf.$txt if(length $buf);		
-				$self->object_add_attribute("SEND","TXT_$index",$txt);
-				set_gui_status($self,"REF_SEND",1);	   
-				
-			}			
-	});		
-	
-		
-	return ($scrolled_win,$tview);	
+    $frame->set_shadow_type ('in');
+    $frame->add ($sw);
+    my $num = $self->object_get_attribute('CTRL','UART_NUM');
+    my @indexs;
+    my $def;
+    for (my $i=0; $i<$num; $i+=1){
+        my $index= $self->object_get_attribute("CTRL","INDEX_$i");
+        $def= $index if(!defined $def);
+        $indexs[$i]=$index;
+    }
+    my $indexs = join(',',@indexs);
+    my $comb=gen_combobox_object($self,'CTRL',"SEND_TO_INDEX",$indexs,$def,undef,undef);
+    my $label=gen_label_in_center("SEND_TO INDEX#");
+    my $send = def_image_button($path.'icons/run.png');
+    my $box=def_pack_hbox( FALSE, 0 , $label,$comb,$send);
+    $frame->set_label_widget ($box);
+    $table->attach_defaults ($frame, 0, 1 , 0,1);
+    $send-> signal_connect("clicked" => sub{
+            my $st =$self->object_get_attribute("CTRL","RUN");
+            my $index =$self->object_get_attribute("CTRL","SEND_TO_INDEX");
+            if ($st eq 'OFF'){
+                add_colored_info($main_tview,"Error: Cannot send the data. Jtag connection is not established yet.\n",'red');
+                return;
+            }
+            my $text_buffer = $tview->get_buffer;
+            my $txt=$text_buffer->get_text($text_buffer->get_bounds, TRUE);
+            if(length ($txt) >0 ){
+                my $buf=$self->object_get_attribute("SEND","TXT_$index");
+                $txt=    $buf.$txt if(length $buf);
+                $self->object_add_attribute("SEND","TXT_$index",$txt);
+                set_gui_status($self,"REF_SEND",1);
+            }
+    });
+    return ($scrolled_win,$tview);
 }
 
-
-
 sub check_jtag_connect {
-	my ($self,$pipe,$tview,$in, $out, $err,$pipe_name)=@_;
-	my $run =$self->object_get_attribute("CTRL","RUN");
-	my $connect = $self->object_get_attribute("CTRL","CONNECT");
-	my $disconnect = $self->object_get_attribute("CTRL","DISCONNECT");
-	
-	
-	
-	my $r;
-	if($connect){
-		
-       	$r=start_xsct($self,$pipe,$tview,$in, $out, $err) if($pipe_name eq 'xsct' );
-       	$r=start_stp ($self,$pipe,$tview,$in, $out, $err) if($pipe_name eq 'stp'  );
-       	if($r){
-       		$self->object_add_attribute("CTRL","RUN",'ON');
-       		add_info($tview,"Connected!\n");
-       		set_gui_status($self,"ref",1); 
-       		
-          		
-       	}else{
-       		$self->object_add_attribute("CTRL","RUN",'OFF');
-       		add_colored_info($tview,"failed to connect!\n",'red');
-      		set_gui_status($self,"ref",1); 
-      		
-       	}            					
-		$self->object_add_attribute("CTRL","CONNECT",0);
-	}if($disconnect){
-		close_xsct($self,$pipe,$tview,$in, $out, $err) if($pipe_name eq 'xsct' );
-		close_stp ($self,$pipe,$tview,$in, $out, $err) if($pipe_name eq 'stp'  );
-		$self->object_add_attribute("CTRL","RUN",'OFF');
-		$self->object_add_attribute("CTRL","DISCONNECT",0);	
-		add_info($tview,"disconnected!\n");
-		set_gui_status($self,"ref",1); 			
-	}	
-}	
-
-
+    my ($self,$pipe,$tview,$in, $out, $err,$pipe_name)=@_;
+    my $run =$self->object_get_attribute("CTRL","RUN");
+    my $connect = $self->object_get_attribute("CTRL","CONNECT");
+    my $disconnect = $self->object_get_attribute("CTRL","DISCONNECT");
+    my $r;
+    if($connect){
+        $r=start_xsct($self,$pipe,$tview,$in, $out, $err) if($pipe_name eq 'xsct' );
+        $r=start_stp ($self,$pipe,$tview,$in, $out, $err) if($pipe_name eq 'stp'  );
+        if($r){
+            $self->object_add_attribute("CTRL","RUN",'ON');
+            add_info($tview,"Connected!\n");
+            set_gui_status($self,"ref",1);
+        }else{
+            $self->object_add_attribute("CTRL","RUN",'OFF');
+            add_colored_info($tview,"failed to connect!\n",'red');
+            set_gui_status($self,"ref",1);
+        }
+        $self->object_add_attribute("CTRL","CONNECT",0);
+    }if($disconnect){
+        close_xsct($self,$pipe,$tview,$in, $out, $err) if($pipe_name eq 'xsct' );
+        close_stp ($self,$pipe,$tview,$in, $out, $err) if($pipe_name eq 'stp'  );
+        $self->object_add_attribute("CTRL","RUN",'OFF');
+        $self->object_add_attribute("CTRL","DISCONNECT",0);
+        add_info($tview,"disconnected!\n");
+        set_gui_status($self,"ref",1);
+    }
+}
 use constant UART_UPDATE_WB_ADDR => 7;
 use constant UART_UPDATE_WB_WR_DATA=>  6;
-use constant UART_UPDATE_WB_RD_DATA => 5;	
-
+use constant UART_UPDATE_WB_RD_DATA => 5;
 # Converts pairs of hex digits to asci
 sub hex_to_ascii { # $ascii ($hex)
-  my $s = shift;
- 
-  return pack 'H*', $s;
+    my $s = shift;
+    return pack 'H*', $s;
 }
-	
-
 
 sub nop{
-	#no oprtstion
-	return
+    #no oprtstion
+    return
 }
 ##########
-#	Quartus stp
+#    Quartus stp
 ##########
-
-
 sub run_stp_pipe{
-	my ($self,$pipe,$in,$out,$err,$tview)=@_;
-	$$out='';	
-	$$in .= "puts done\n";
-	
-	#print $$in;
-	
-	pump $$pipe while (length $$in);
+    my ($self,$pipe,$in,$out,$err,$tview)=@_;
+    $$out='';
+    $$in .= "puts done\n";
+    #print $$in;
+    pump $$pipe while (length $$in);
     until ($$out =~ /done/ || (length $$err)){
-    
-    	pump $$pipe; 
-    	refresh_gui();    	
-    }	 
+        pump $$pipe;
+        refresh_gui();
+    }
     if(length $$err){
-    	add_colored_info($tview,"Got an Error: $$err\n",'red');
-    	$self->object_add_attribute("CTRL","DISCONNECT",1);	
-    	set_gui_status($self,"ON-OFF",0);	    	
-    	return 0;    	
+        add_colored_info($tview,"Got an Error: $$err\n",'red');
+        $self->object_add_attribute("CTRL","DISCONNECT",1);
+        set_gui_status($self,"ON-OFF",0);
+        return 0;
     }
-    # stp does not print on stderr. we need to check stdout manually for error 
+    # stp does not print on stderr. we need to check stdout manually for error
     my @error_list=("ERROR:","can't read");
     foreach my $err (@error_list) {
-    	if( $$out =~ /$err/){
-    		add_colored_info($tview,"Got an Error: $$out\n",'red');
-    		$self->object_add_attribute("CTRL","DISCONNECT",1);	
-    		set_gui_status($self,"ON-OFF",0);	    	
-    		return 0;    		
-    	}	
-    	
+        if( $$out =~ /$err/){
+            add_colored_info($tview,"Got an Error: $$out\n",'red');
+            $self->object_add_attribute("CTRL","DISCONNECT",1);
+            set_gui_status($self,"ON-OFF",0);
+            return 0;
+        }
     }
-     
     refresh_gui();
     #print $$out;
-	return 1;	
+    return 1;
 }
 
 sub start_stp{
-	my ($self,$pipe,$tview,$in, $out, $err)=@_;
-	
-	
-	my $stp = which('quartus_stp');	
-	
-	#check if $xsct exits
-	unless(-f $stp){
-		add_colored_info($tview,"Error quartus_stp not found. Please add the path to QuartusII/bin to your \$PATH environment\n",'red');
-		return 0;	
-	}	
-	my @run = ( "$stp" );
-	my @run_args = ( "-s" );
-	
-	my $r;
-	
-	$$pipe =start [@run, @run_args], $in, $out, $err or $r=$?;
-	if(defined $r){
-		add_colored_info($tview," quartus_stp got an Error: $r\n",'red');
-		return 0;		
-	}
-	
-	my $hdw= $self->object_get_attribute('CTRL','quartus_hardware');
-	my $dev= $self->object_get_attribute('CTRL','quartus_device');
-
-	$hdw="" if(!defined $hdw);	
-	$dev="" if(!defined $dev);
-	
-	
-	if(length ($hdw) ==0){
-		add_colored_info($tview,"Error: Cannot initial the quartus_stp. the hardware name is not defined!\n",'red');
-		return 0;		
-	}
-	
-	if(length ($dev)==0) {
-		add_colored_info($tview,"Error: Cannot initial the quartus_stp. the device number is not defined!\n",'red');		
-		return 0;
-	}
-	
-	my $HARDWARE_NAME="$hdw *";
-	my $DEVICE_NAME="\@$dev*"; 
-		
-	
-	$$in = " ";	
-	
+    my ($self,$pipe,$tview,$in, $out, $err)=@_;
+    my $stp = which('quartus_stp');
+    #check if $xsct exits
+    unless(-f $stp){
+        add_colored_info($tview,"Error quartus_stp not found. Please add the path to QuartusII/bin to your \$PATH environment\n",'red');
+        return 0;
+    }
+    my @run = ( "$stp" );
+    my @run_args = ( "-s" );
+    my $r;
+    $$pipe =start [@run, @run_args], $in, $out, $err or $r=$?;
+    if(defined $r){
+        add_colored_info($tview," quartus_stp got an Error: $r\n",'red');
+        return 0;
+    }
+    my $hdw= $self->object_get_attribute('CTRL','quartus_hardware');
+    my $dev= $self->object_get_attribute('CTRL','quartus_device');
+    $hdw="" if(!defined $hdw);
+    $dev="" if(!defined $dev);
+    if(length ($hdw) ==0){
+        add_colored_info($tview,"Error: Cannot initial the quartus_stp. the hardware name is not defined!\n",'red');
+        return 0;
+    }
+    if(length ($dev)==0) {
+        add_colored_info($tview,"Error: Cannot initial the quartus_stp. the device number is not defined!\n",'red');
+        return 0;
+    }
+    my $HARDWARE_NAME="$hdw *";
+    my $DEVICE_NAME="\@$dev*";
+    $$in = " ";
     return 0 unless run_stp_pipe($self,$pipe,$in,$out,$err,$tview);
     $$in = "  foreach name [get_hardware_names] {
-   if { [string match \"*${HARDWARE_NAME}*\" \$name] } {
-       set hardware_name \$name\n
-     }
-   }
-   puts \"\\nhardware_name is \$hardware_name\"
-   foreach name [get_device_names -hardware_name \$hardware_name] {
-     if { [string match \"*$DEVICE_NAME*\" \$name] } {
-       set chip_name \$name
-     }
-   }
-   puts \"device_name is \$chip_name\\n\";
-   open_device -hardware_name \$hardware_name -device_name \$chip_name\n";
-   return 0 unless run_stp_pipe($self,$pipe,$in,$out,$err,$tview);
-         
+        if { [string match \"*${HARDWARE_NAME}*\" \$name] } {
+            set hardware_name \$name\n
+        }
+    }
+    puts \"\\nhardware_name is \$hardware_name\"
+    foreach name [get_device_names -hardware_name \$hardware_name] {
+        if { [string match \"*$DEVICE_NAME*\" \$name] } {
+            set chip_name \$name
+        }
+    }
+    puts \"device_name is \$chip_name\\n\";
+    open_device -hardware_name \$hardware_name -device_name \$chip_name\n";
+    return 0 unless run_stp_pipe($self,$pipe,$in,$out,$err,$tview);
     return 1;
 }
 
 sub close_stp{
-	my ($self,$pipe,$tview,$in, $out, $err)=@_;
-	$$in = 
+    my ($self,$pipe,$tview,$in, $out, $err)=@_;
+    $$in =
 "device_unlock
 close_device
 exit
 ";
-  	pump $$pipe while (length $$in);
-   	finish $$pipe;
+    pump $$pipe while (length $$in);
+    finish $$pipe;
 }
 
-
 sub stp_jtag_vir {
-	my ($index,$ir)=@_;	
-	my $hex = sprintf("%X", $ir);
-	my $in = 
+    my ($index,$ir)=@_;
+    my $hex = sprintf("%X", $ir);
+    my $in =
 "device_lock -timeout 10000
 device_virtual_ir_shift -instance_index $index -ir_value $hex -no_captured_ir_value
 catch {device_unlock}
 ";
-return $in;	
+return $in;
 }
 
-
 sub stp_jtag_vdr{
-	my ($index,$dat,$width)=@_;
-	my $digits= $width>>2;	
-	my $hex = sprintf("%0${digits}X", $dat);
-	my $in=
+    my ($index,$dat,$width)=@_;
+    my $digits= $width>>2;
+    my $hex = sprintf("%0${digits}X", $dat);
+    my $in=
 "device_lock -timeout 10000
 set data [device_virtual_dr_shift -dr_value $hex -instance_index $index  -length $width  -value_in_hex]
 catch {device_unlock}
 puts R:\$data:R
 ";
-	return $in;	
+    return $in;
 }
 
-
 sub run_stp_jtag_scaner{
-	my ($self,$tview,$tv_ref,$pipe,$in, $out, $err)=@_; 
-		
-	my $num = $self->object_get_attribute('CTRL','UART_NUM');
-		
-	
-	my @tviews=@{$tv_ref};
-	
-	for (my $i=0; $i<$num; $i+=1){	
-		my $index= $self->object_get_attribute("CTRL","INDEX_$i");	
-		next if (!defined $index);
-		
-		
-		
-		my $txt= $self->object_get_attribute("SEND","TXT_$index");
-		my $send_char =0;
-		my $l=length $txt;
-		if ($l){
-			$send_char = substr $txt, 0,1;
-			$send_char = ord($send_char); #convert a character to a number
-			$txt =  substr $txt, 1,$l;
-			$self->object_add_attribute("SEND","TXT_$index",$txt );
-		}
-		
-			
-		
-		#select instruction
-		$$in=stp_jtag_vir ($index,UART_UPDATE_WB_RD_DATA);	
-		return  unless run_stp_pipe($self,$pipe,$in,$out,$err,$tview);
-				
-		
-		#read uart reg 0 
-		my $str=stp_jtag_vdr ($index,$send_char,32);	
-		$$in=$str;
-		nop();
-		return  unless run_stp_pipe($self,$pipe,$in,$out,$err,$tview);
-		nop();
-		my ($tmp,$hex)= sscanf("%sR:%s:R",$$out);
-		#print "capture $hex\n";
-		my $char= substr($hex, -2);
-		#print "char = $char\n";
-		if($char ne '00'){	
-			$char =hex_to_ascii($char);	
-			add_info($tviews[$i],$char) if(defined $tviews[$i]);
-		}
-	}
+    my ($self,$tview,$tv_ref,$pipe,$in, $out, $err)=@_;
+    my $num = $self->object_get_attribute('CTRL','UART_NUM');
+    my @tviews=@{$tv_ref};
+    for (my $i=0; $i<$num; $i+=1){
+        my $index= $self->object_get_attribute("CTRL","INDEX_$i");
+        next if (!defined $index);
+        my $txt= $self->object_get_attribute("SEND","TXT_$index");
+        my $send_char =0;
+        my $l=length $txt;
+        if ($l){
+            $send_char = substr $txt, 0,1;
+            $send_char = ord($send_char); #convert a character to a number
+            $txt =  substr $txt, 1,$l;
+            $self->object_add_attribute("SEND","TXT_$index",$txt );
+        }
+        #select instruction
+        $$in=stp_jtag_vir ($index,UART_UPDATE_WB_RD_DATA);
+        return  unless run_stp_pipe($self,$pipe,$in,$out,$err,$tview);
+        #read uart reg 0
+        my $str=stp_jtag_vdr ($index,$send_char,32);
+        $$in=$str;
+        nop();
+        return  unless run_stp_pipe($self,$pipe,$in,$out,$err,$tview);
+        nop();
+        my ($tmp,$hex)= sscanf("%sR:%s:R",$$out);
+        #print "capture $hex\n";
+        my $char= substr($hex, -2);
+        #print "char = $char\n";
+        if($char ne '00'){
+            $char =hex_to_ascii($char);
+            add_info($tviews[$i],$char) if(defined $tviews[$i]);
+        }
+    }
 }
 
-
 ###############
-#	xsct 
+#    xsct
 ##############
-
 use constant UPDATE_INDEX => "01";
 use constant UPDATE_IR    => "02";
 use constant UPDATE_DAT   => "04";
-
 #USER1 000010 Access user-defined register 1.
 #USER2 000011 Access user-defined register 2.
 #USER3 100010 Access user-defined register 3.
 #USER4 100011 Access user-defined register 4
-
 sub run_xsct_pipe{
-	my ($self,$pipe,$in,$out,$err,$tview)=@_;
-	$$out='';	
-	$$in .= "puts done\n";
-	
-	pump $$pipe while (length $$in);
+    my ($self,$pipe,$in,$out,$err,$tview)=@_;
+    $$out='';
+    $$in .= "puts done\n";
+    pump $$pipe while (length $$in);
     until ($$out =~ /done/ || (length $$err)){
-    
-    	pump $$pipe; 
-    	refresh_gui();    	
-    }	 
+        pump $$pipe;
+        refresh_gui();
+    }
     if(length $$err){
-    	add_colored_info($tview,"Got an Error: $$err\n",'red');
-    	$self->object_add_attribute("CTRL","DISCONNECT",1);	
-    	set_gui_status($self,"ON-OFF",0);	    	
-    	return 0;    	
+        add_colored_info($tview,"Got an Error: $$err\n",'red');
+        $self->object_add_attribute("CTRL","DISCONNECT",1);
+        set_gui_status($self,"ON-OFF",0);
+        return 0;
     }
     refresh_gui();
-  
-	return 1;	
+    return 1;
 }
 
-
 sub start_xsct{
-	my ($self,$pipe,$tview,$in, $out, $err)=@_;
-	
-	
-	my $xsct = which('xsct');	
-	
-	#check if $xsct exits
-	unless(-f $xsct){
-		add_colored_info($tview,"Error xsct not found. Please add the path to xilinx/SDK/bin to your \$PATH environment\n",'red');
-		return 0;	
-	}	
-	my @cat = ( $xsct );
-	my $r;
-	
-	$$pipe =start \@cat, $in, $out, $err or $r=$?;
-	if(defined $r){
-		add_colored_info($tview,"XSCT got an Error: $r\n",'red');
-		return 0;		
-	}
-	
-	
-	my $target= $self->object_get_attribute('CTRL','JTAG_TARGET');
-	
-	$$in = "";
+    my ($self,$pipe,$tview,$in, $out, $err)=@_;
+    my $xsct = which('xsct');
+    #check if $xsct exits
+    unless(-f $xsct){
+        add_colored_info($tview,"Error xsct not found. Please add the path to xilinx/SDK/bin to your \$PATH environment\n",'red');
+        return 0;
+    }
+    my @cat = ( $xsct );
+    my $r;
+    $$pipe =start \@cat, $in, $out, $err or $r=$?;
+    if(defined $r){
+        add_colored_info($tview,"XSCT got an Error: $r\n",'red');
+        return 0;
+    }
+    my $target= $self->object_get_attribute('CTRL','JTAG_TARGET');
+    $$in = "";
     return 0 unless run_xsct_pipe($self,$pipe,$in,$out,$err,$tview);
     $$in = "set jseq [jtag sequence]\n connect\n jtag targets $target\n";
     return 0 unless run_xsct_pipe($self,$pipe,$in,$out,$err,$tview);
-         
     return 1;
 }
 
-
-
-
 sub close_xsct{
-	my ($self,$pipe,$tview,$in, $out, $err)=@_;
-	$$in = "exit\n";
-  	pump $$pipe while (length $$in);
-   	finish $$pipe;
+    my ($self,$pipe,$tview,$in, $out, $err)=@_;
+    $$in = "exit\n";
+    pump $$pipe while (length $$in);
+    finish $$pipe;
 }
 
-
 sub jtag_reorder{
-  my ( $string_in ) =@_;
-  my @chars =( $string_in =~ m/../g );#split a string into chunks of two characters
-  return join("", reverse @chars);  
+    my ( $string_in ) =@_;
+    my @chars =( $string_in =~ m/../g );#split a string into chunks of two characters
+    return join("", reverse @chars);
 }
 
-
-
 sub xsct_send_to_jtag{
-	my ($hex,$width,$chain) =@_;
-	my $siz = $width+4;
-	#print "$chain\n";
-	my $str="\$jseq clear
+    my ($hex,$width,$chain) =@_;
+    my $siz = $width+4;
+    #print "$chain\n";
+    my $str="\$jseq clear
 \$jseq irshift -state IDLE -hex 6 $chain
 \$jseq drshift -state IDLE -hex $siz $hex
 \$jseq run
@@ -698,186 +553,146 @@ sub xsct_send_to_jtag{
 return $str;
 }
 
-
 sub xsct_send_capture_jtag {
-	my ($hex,$width,$chain) =@_;
-	my $siz = $width+4;
-	my $str="\$jseq clear                                                      
-\$jseq irshift -state IDLE -hex 6 $chain                 
-\$jseq drshift -state IDLE -capture -hex $siz $hex  
+    my ($hex,$width,$chain) =@_;
+    my $siz = $width+4;
+    my $str="\$jseq clear
+\$jseq irshift -state IDLE -hex 6 $chain
+\$jseq drshift -state IDLE -capture -hex $siz $hex
 set data [\$jseq run]
 puts R:\$data:R
-"; 
-return $str;	
+";
+return $str;
 }
 
-
 sub xsct_jtag_vdr{
-	my ($dat,$width,$chain)=@_;
-	my $digits= $width>>2;	
-	my $hex = UPDATE_DAT.sprintf("%0${digits}X", $dat);
-	$hex=jtag_reorder($hex);	
-	return xsct_send_capture_jtag($hex,$width,$chain);
+    my ($dat,$width,$chain)=@_;
+    my $digits= $width>>2;
+    my $hex = UPDATE_DAT.sprintf("%0${digits}X", $dat);
+    $hex=jtag_reorder($hex);
+    return xsct_send_capture_jtag($hex,$width,$chain);
 }
 
-
 sub xsct_jtag_vir {
-	my ($ir,$width,$chain)=@_;	
-	my $digits= $width>>2;	
-	my $hex = UPDATE_IR.sprintf("%0${digits}X", $ir);
-	$hex=jtag_reorder($hex);
-	return xsct_send_to_jtag($hex,$width,$chain);
+    my ($ir,$width,$chain)=@_;
+    my $digits= $width>>2;
+    my $hex = UPDATE_IR.sprintf("%0${digits}X", $ir);
+    $hex=jtag_reorder($hex);
+    return xsct_send_to_jtag($hex,$width,$chain);
 }
 
 sub xsct_jtag_vindex {
-	my ($index,$width,$chain)=@_;	
-	my $digits= $width>>2;	
-	my $hex = UPDATE_INDEX.sprintf("%0${digits}X", $index);
-	$hex=jtag_reorder($hex);
-	return xsct_send_to_jtag($hex,$width,$chain);
+    my ($index,$width,$chain)=@_;
+    my $digits= $width>>2;
+    my $hex = UPDATE_INDEX.sprintf("%0${digits}X", $index);
+    $hex=jtag_reorder($hex);
+    return xsct_send_to_jtag($hex,$width,$chain);
 }
 
 sub run_xsct_jtag_scaner{
-	my ($self,$tview,$tv_ref,$pipe,$in, $out, $err)=@_; 
-		
-	my $num = $self->object_get_attribute('CTRL','UART_NUM');
-	my $chain= $self->object_get_attribute('CTRL','JTAG_CHAIN');
-	my $chain_code=
-		($chain==1)? '02':
-		($chain==2)? '03':
-		($chain==3)? '22':
-		'23';
-	
-	my @tviews=@{$tv_ref};
-	
-	for (my $i=0; $i<$num; $i+=1){	
-		my $index= $self->object_get_attribute("CTRL","INDEX_$i");	
-		next if (!defined $index);
-		my $txt= $self->object_get_attribute("SEND","TXT_$index");
-		my $send_char =0;
-		my $l=length $txt;
-		if ($l){
-			$send_char = substr $txt, 0,1;
-			$send_char = ord($send_char); #convert a character to a number
-			$txt =  substr $txt, 1,$l;
-			$self->object_add_attribute("SEND","TXT_$index",$txt );
-		}
-		
-	
-		#select index		
-		#print"select index\n";
-		$$in=xsct_jtag_vindex ($index,32,$chain_code);
-		return  unless run_xsct_pipe($self,$pipe,$in,$out,$err,$tview);
-			
-		
-		#select instruction
-		#print"select instruction\n";
-		$$in=xsct_jtag_vir (UART_UPDATE_WB_RD_DATA,32,$chain_code);	
-		return  unless run_xsct_pipe($self,$pipe,$in,$out,$err,$tview);
-				
-		
-		#read uart reg 0 
-		#print"read reg 0\n";
-		my $str=xsct_jtag_vdr   ($send_char,32,$chain_code);	
-		$$in=$str;
-		nop();
-		return  unless run_xsct_pipe($self,$pipe,$in,$out,$err,$tview);
-		nop();
-		my ($hex)= sscanf("R:%s:R",$$out);
-		my $char= substr $hex, 0, 2;
-		if($char ne '00'){	
-			$char =hex_to_ascii(substr $hex, 0, 2);	
-			add_info($tviews[$i],$char) if(defined $tviews[$i]);
-		}
-		
-		
-		
-	}
+    my ($self,$tview,$tv_ref,$pipe,$in, $out, $err)=@_;
+    my $num = $self->object_get_attribute('CTRL','UART_NUM');
+    my $chain= $self->object_get_attribute('CTRL','JTAG_CHAIN');
+    my $chain_code=
+        ($chain==1)? '02':
+        ($chain==2)? '03':
+        ($chain==3)? '22':
+        '23';
+    my @tviews=@{$tv_ref};
+    for (my $i=0; $i<$num; $i+=1){
+        my $index= $self->object_get_attribute("CTRL","INDEX_$i");
+        next if (!defined $index);
+        my $txt= $self->object_get_attribute("SEND","TXT_$index");
+        my $send_char =0;
+        my $l=length $txt;
+        if ($l){
+            $send_char = substr $txt, 0,1;
+            $send_char = ord($send_char); #convert a character to a number
+            $txt =  substr $txt, 1,$l;
+            $self->object_add_attribute("SEND","TXT_$index",$txt );
+        }
+        #select index
+        #print"select index\n";
+        $$in=xsct_jtag_vindex ($index,32,$chain_code);
+        return  unless run_xsct_pipe($self,$pipe,$in,$out,$err,$tview);
+        #select instruction
+        #print"select instruction\n";
+        $$in=xsct_jtag_vir (UART_UPDATE_WB_RD_DATA,32,$chain_code);
+        return  unless run_xsct_pipe($self,$pipe,$in,$out,$err,$tview);
+        #read uart reg 0
+        #print"read reg 0\n";
+        my $str=xsct_jtag_vdr   ($send_char,32,$chain_code);
+        $$in=$str;
+        nop();
+        return  unless run_xsct_pipe($self,$pipe,$in,$out,$err,$tview);
+        nop();
+        my ($hex)= sscanf("R:%s:R",$$out);
+        my $char= substr $hex, 0, 2;
+        if($char ne '00'){
+            $char =hex_to_ascii(substr $hex, 0, 2);
+            add_info($tviews[$i],$char) if(defined $tviews[$i]);
+        }
+    }
 }
 
-
-
-
 ############
-#	main
+#    main
 ############
-
-
-
 sub uart_main {
-	my $self = __PACKAGE__->new(); 
-	set_gui_status($self,"ideal",0);
-	my $window = def_popwin_size (85,85,'UART Terminal','percent');
-	my ($sw,$tview) =create_txview();# a textveiw for showing the info, erro messages etc
-	my $ctrl= ctrl_boxes($self,$tview);
-	my ($rsv,$tv_ref) = receive_boxes($self);
-	my ($send,$send_tv) =	sender_box($self,$tview);
-	 
-	my $v1 = gen_vpaned ($ctrl,0.3,$send);	
-	my $v2 = gen_vpaned ($v1,0.5,$sw);
-	my $h1 = gen_hpaned ($rsv,0.55,$v2);
-	
-	my ($pipe,$in, $out, $err);
-	my $counter=5;
-	#check soc status every 0.5 second. referesh device table if there is any changes 
-    Glib::Timeout->add (10, sub{ 
+    my $self = __PACKAGE__->new();
+    set_gui_status($self,"ideal",0);
+    my $window = def_popwin_size (85,85,'UART Terminal','percent');
+    my ($sw,$tview) =create_txview();# a textveiw for showing the info, erro messages etc
+    my $ctrl= ctrl_boxes($self,$tview);
+    my ($rsv,$tv_ref) = receive_boxes($self);
+    my ($send,$send_tv) =    sender_box($self,$tview);
+    my $v1 = gen_vpaned ($ctrl,0.3,$send);
+    my $v2 = gen_vpaned ($v1,0.5,$sw);
+    my $h1 = gen_hpaned ($rsv,0.55,$v2);
+    my ($pipe,$in, $out, $err);
+    my $counter=5;
+    #check soc status every 0.5 second. referesh device table if there is any changes
+    Glib::Timeout->add (10, sub{
         my ($state,$timeout)= get_gui_status($self);
-        
         if ($timeout>0){
             $timeout--;
-            set_gui_status($self,$state,$timeout);           
+            set_gui_status($self,$state,$timeout);
         }
-        elsif( $state ne "ideal" ){        	
+        elsif( $state ne "ideal" ){
             if($state eq 'ref_all') {
-            	 $rsv->destroy();
-            	 ($rsv,$tv_ref) = receive_boxes($self);
-            	 $h1-> pack1($rsv, TRUE, TRUE);
-            }	  
-            
-            
-           
+                $rsv->destroy();
+                ($rsv,$tv_ref) = receive_boxes($self);
+                $h1-> pack1($rsv, TRUE, TRUE);
+            }
             $ctrl->destroy();
             $send->destroy();
-           
-            ($send,$send_tv) =	sender_box($self,$tview);
+            ($send,$send_tv) =    sender_box($self,$tview);
             $ctrl= ctrl_boxes($self,$tview);
-           
             $v1-> pack1($ctrl, TRUE, TRUE);
             $v1-> pack2($send, TRUE, TRUE);
             $h1->show_all();
-            set_gui_status($self,"ideal",0);     
-            if($state eq 'ON-OFF') {  
-            	my $uname= $self->object_get_attribute('CTRL','UART_NAME');
-            	my $pipe_name = ($uname eq 'ProNoC_XILINX_UART') ? 'xsct' : 'stp';            	
-            	check_jtag_connect ($self,\$pipe,$tview,\$in, \$out, \$err,$pipe_name);
-            	my $st =$self->object_get_attribute("CTRL","RUN");
-            	$counter=5 if ($st eq 'OFF');
-            	#print "ON-OFF\n";
+            set_gui_status($self,"ideal",0);
+            if($state eq 'ON-OFF') {
+                my $uname= $self->object_get_attribute('CTRL','UART_NAME');
+                my $pipe_name = ($uname eq 'ProNoC_XILINX_UART') ? 'xsct' : 'stp';
+                check_jtag_connect ($self,\$pipe,$tview,\$in, \$out, \$err,$pipe_name);
+                my $st =$self->object_get_attribute("CTRL","RUN");
+                $counter=5 if ($st eq 'OFF');
+                #print "ON-OFF\n";
             }
-           # print "ref\n";
-               
-            
-       }
+            # print "ref\n";
+        }
         my $st =$self->object_get_attribute("CTRL","RUN");
         $counter-- if ($st eq 'ON' && $counter>0);
         if($counter ==0 ){
-        	my $uname= $self->object_get_attribute('CTRL','UART_NAME');
-			run_xsct_jtag_scaner($self,$tview,$tv_ref,\$pipe,\$in, \$out, \$err) if($uname eq 'ProNoC_XILINX_UART' ); 
-			run_stp_jtag_scaner($self,$tview,$tv_ref,\$pipe,\$in, \$out, \$err) if($uname eq 'ProNoC_ALTERA_UART' ); 
+            my $uname= $self->object_get_attribute('CTRL','UART_NAME');
+            run_xsct_jtag_scaner($self,$tview,$tv_ref,\$pipe,\$in, \$out, \$err) if($uname eq 'ProNoC_XILINX_UART' );
+            run_stp_jtag_scaner($self,$tview,$tv_ref,\$pipe,\$in, \$out, \$err) if($uname eq 'ProNoC_ALTERA_UART' );
         }
-    	return TRUE;
-        
+        return TRUE;
     } );
-	
-	
-	$window->add($h1);
-	$window->show_all();
-	return $window;	
-}	
-
-
- 	
-
-
-
-1;
+    $window->add($h1);
+    $window->show_all();
+    return $window;
+}
+1;
\ No newline at end of file
diff --git a/mpsoc/perl_gui/lib/perl/verilog_gen.pl b/mpsoc/perl_gui/lib/perl/verilog_gen.pl
index d6c506a..3cdeeb3 100755
--- a/mpsoc/perl_gui/lib/perl/verilog_gen.pl
+++ b/mpsoc/perl_gui/lib/perl/verilog_gen.pl
@@ -1,101 +1,77 @@
 use constant::boolean;
-
 use lib 'lib/perl';
-
 use strict;
 use warnings;
-
-
 use FindBin;
 use lib $FindBin::Bin;
-
 use soc;
 use ip;
 use ip_gen;
 use Cwd;
 
-
-
-
-
 ######################
 #   soc_generate_verilog
 #####################
-
-sub soc_generate_verilog{ 
-	my ($soc,$sw_path,$txview)= @_;
-	my $soc_name=$soc->object_get_attribute('soc_name');
-	#my $top_ip=ip_gen->ip_gen_new();
-	my $top_ip=ip_gen->top_gen_new();
-	if(!defined $soc_name){$soc_name='soc'};
-	
-	my @instances=$soc->soc_get_all_instances();
-	my $io_sim_v;
-	my $top_io_short;
-	my $core_id= $soc->object_get_attribute('global_param','CORE_ID');
-	$core_id= 0 if(!defined $core_id);
-	my $param_as_in_v_all="\tparameter\tCORE_ID=$core_id,
+sub soc_generate_verilog{
+    my ($soc,$sw_path,$txview)= @_;
+    my $soc_name=$soc->object_get_attribute('soc_name');
+    #my $top_ip=ip_gen->ip_gen_new();
+    my $top_ip=ip_gen->top_gen_new();
+    if(!defined $soc_name){$soc_name='soc'};
+    my @instances=$soc->soc_get_all_instances();
+    my $io_sim_v;
+    my $top_io_short;
+    my $core_id= $soc->object_get_attribute('global_param','CORE_ID');
+    $core_id= 0 if(!defined $core_id);
+    my $param_as_in_v_all="\tparameter\tCORE_ID=$core_id,
 \tparameter\tSW_LOC=\"$sw_path\"";
-
-
-
     my $system_v_all="";
-	my $param_pass_v_all="\t\t.CORE_ID(CORE_ID),\n\t\t.SW_LOC(SW_LOC)";
-	my $body_v;
-	
-	my ($param_v_all, $local_param_v_all, $wire_def_v_all, $inst_v_all, $plugs_assign_v_all, $sockets_assign_v_all,$io_full_v_all,$top_io_pass_all,$io_sim_v_all);
-	my $top_io_short_all="\tjtag_debug_reset_in";  
-	my $top_io_full_all="\tinput \tjtag_debug_reset_in;\n";
-	my $wires=soc->new_wires();
-	my $intfc=interface->interface_new();
-	 
-	 
-	foreach my $id (@instances){
-		my ($param_v, $local_param_v, $wire_def_v, $inst_v, $plugs_assign_v, $sockets_assign_v,$io_full_v,$io_top_full_v,$io_sim_v,
-		$top_io_short,$param_as_in_v,$param_pass_v,$system_v,$assigned_ports,$top_io_pass,$src_io_short, $src_io_full)=gen_module_inst($id,$soc,$top_ip,$intfc,$wires);
-		my $inst   	= $soc->soc_get_instance_name($id);
-		add_text_to_string(\$body_v,"/*******************\n*\n*\t$inst\n*\n*\n*********************/\n");
-		add_text_to_string(\$param_as_in_v_all,",\n$param_as_in_v")   	if(defined($param_as_in_v)); 
-		add_text_to_string(\$local_param_v_all,"$local_param_v\n")   	if(defined($local_param_v)); 
-		add_text_to_string(\$param_pass_v_all,",\n$param_pass_v")       if(defined($param_pass_v));
-		add_text_to_string(\$system_v_all,"$system_v\n")   				if(defined($system_v)); 
-		add_text_to_string(\$wire_def_v_all,"$wire_def_v\n")		 	if(defined($wire_def_v));
-		add_text_to_string(\$inst_v_all,$inst_v)					 	if(defined($inst_v));
-		add_text_to_string(\$plugs_assign_v_all,"$plugs_assign_v\n") 	if(defined($plugs_assign_v));
-		add_text_to_string(\$sockets_assign_v_all,"$sockets_assign_v\n")if(defined($sockets_assign_v));
-		add_text_to_string(\$io_full_v_all,"$io_full_v\n")				if(length($io_full_v)>3);
-		add_text_to_string(\$top_io_full_all,"$io_top_full_v\n")		if(length($io_top_full_v)>3);
-		$top_io_pass_all  = (defined $top_io_pass_all )? "$top_io_pass_all,\n$top_io_pass"   : $top_io_pass         if(defined($top_io_pass));
-		$io_sim_v_all     = (defined $io_sim_v_all    )? "$io_sim_v_all,\n$io_sim_v"         : $io_sim_v  	    	if(defined($io_sim_v));
-		$top_io_short_all = (defined $top_io_short_all)? "$top_io_short_all,\n$top_io_short" : $top_io_short 		if(defined($top_io_short));
-		
-		
-		#print  "$param_v $local_param_v $wire_def_v $inst_v $plugs_assign_v $sockets_assign_v $io_full_v";
-			
-	}	
-	my ($addr_map,$addr_localparam,$module_addr_localparam)= generate_address_cmp($soc,$wires);
-
-	#add functions
-	my $dir = Cwd::getcwd();
-	open my $file1, "<", "$dir/lib/verilog/functions.v" or die;
-	my $functions_all='';
-	while (my $f1 = readline ($file1)) {	
-		 $functions_all="$functions_all $f1 ";
-	}
-	close($file1);
-	my $unused_wiers_v=assign_unconnected_wires($wires,$intfc);
-	
-	$unused_wiers_v="" if(!defined $unused_wiers_v);
-	$sockets_assign_v_all=""  if(!defined $sockets_assign_v_all);
-
-my $has_ni =check_for_ni($soc);
-my $import = ($has_ni)? "\n\t`NOC_CONF\n" : ""; 
-my $tscale = ($has_ni)? "`include \"pronoc_def.v\"\n" : "`timescale 1ns / 1ps\n"; 
-
-my $global_localparam=get_golal_param_v();	
-	my $soc_v = (defined $param_as_in_v_all )? "$tscale module $soc_name  #(\n $param_as_in_v_all\n)(\n$io_sim_v_all\n);\n$import\n": "$tscale module $soc_name (\n$io_sim_v_all\n);\n $import\n";
-	$soc_v = $soc_v."
-$functions_all	
+    my $param_pass_v_all="\t\t.CORE_ID(CORE_ID),\n\t\t.SW_LOC(SW_LOC)";
+    my $body_v;
+    my ($param_v_all, $local_param_v_all, $wire_def_v_all, $inst_v_all, $plugs_assign_v_all, $sockets_assign_v_all,$io_full_v_all,$top_io_pass_all,$io_sim_v_all);
+    my $top_io_short_all="\tjtag_debug_reset_in";
+    my $top_io_full_all="\tinput \tjtag_debug_reset_in;\n";
+    my $wires=soc->new_wires();
+    my $intfc=interface->interface_new();
+    foreach my $id (@instances){
+        my ($param_v, $local_param_v, $wire_def_v, $inst_v, $plugs_assign_v, $sockets_assign_v,$io_full_v,$io_top_full_v,$io_sim_v,
+        $top_io_short,$param_as_in_v,$param_pass_v,$system_v,$assigned_ports,$top_io_pass,$src_io_short, $src_io_full)=gen_module_inst($id,$soc,$top_ip,$intfc,$wires);
+        my $inst       = $soc->soc_get_instance_name($id);
+        add_text_to_string(\$body_v,"/*******************\n*\n*\t$inst\n*\n*\n*********************/\n");
+        add_text_to_string(\$param_as_in_v_all,",\n$param_as_in_v")       if(defined($param_as_in_v));
+        add_text_to_string(\$local_param_v_all,"$local_param_v\n")       if(defined($local_param_v));
+        add_text_to_string(\$param_pass_v_all,",\n$param_pass_v")       if(defined($param_pass_v));
+        add_text_to_string(\$system_v_all,"$system_v\n")                   if(defined($system_v));
+        add_text_to_string(\$wire_def_v_all,"$wire_def_v\n")             if(defined($wire_def_v));
+        add_text_to_string(\$inst_v_all,$inst_v)                         if(defined($inst_v));
+        add_text_to_string(\$plugs_assign_v_all,"$plugs_assign_v\n")     if(defined($plugs_assign_v));
+        add_text_to_string(\$sockets_assign_v_all,"$sockets_assign_v\n")if(defined($sockets_assign_v));
+        add_text_to_string(\$io_full_v_all,"$io_full_v\n")                if(length($io_full_v)>3);
+        add_text_to_string(\$top_io_full_all,"$io_top_full_v\n")        if(length($io_top_full_v)>3);
+        $top_io_pass_all  = (defined $top_io_pass_all )? "$top_io_pass_all,\n$top_io_pass"   : $top_io_pass         if(defined($top_io_pass));
+        $io_sim_v_all     = (defined $io_sim_v_all    )? "$io_sim_v_all,\n$io_sim_v"         : $io_sim_v              if(defined($io_sim_v));
+        $top_io_short_all = (defined $top_io_short_all)? "$top_io_short_all,\n$top_io_short" : $top_io_short         if(defined($top_io_short));
+        #print  "$param_v $local_param_v $wire_def_v $inst_v $plugs_assign_v $sockets_assign_v $io_full_v";
+    }
+    my ($addr_map,$addr_localparam,$module_addr_localparam)= generate_address_cmp($soc,$wires);
+    #add functions
+    my $dir = Cwd::getcwd();
+    open my $file1, "<", "$dir/lib/verilog/functions.v" or die;
+    my $functions_all='';
+    while (my $f1 = readline ($file1)) {
+        $functions_all="$functions_all $f1 ";
+    }
+    close($file1);
+    my $unused_wiers_v=assign_unconnected_wires($wires,$intfc);
+    $unused_wiers_v="" if(!defined $unused_wiers_v);
+    $sockets_assign_v_all=""  if(!defined $sockets_assign_v_all);
+    my $has_ni =check_for_ni($soc);
+    my $import = ($has_ni)? "\n\timport pronoc_pkg::*;\n" : "";
+    my $tscale = ($has_ni)? "`include \"pronoc_def.v\"\n" : "`timescale 1ns / 1ps\n";
+    my $global_localparam=get_golal_param_v();
+    my $soc_v = (defined $param_as_in_v_all )? "$tscale module $soc_name  #(\n $param_as_in_v_all\n)(\n$io_sim_v_all\n);\n$import\n": "$tscale module $soc_name (\n$io_sim_v_all\n);\n $import\n";
+    $soc_v = $soc_v."
+$functions_all
 $system_v_all
 $global_localparam
 $local_param_v_all
@@ -109,1234 +85,913 @@ sub soc_generate_verilog{
 $sockets_assign_v_all
 $addr_map
 endmodule
-
 ";
-	
-	
-	$soc->object_add_attribute('top_ip',undef,$top_ip);
-	#print @assigned_wires;
-
-	#generate top module
-	my ($clk_set, $clk_io_sim,$clk_io_full, $clk_assigned_port)= get_top_clk_setting($soc);
-	$top_io_short_all=(defined $top_io_short_all)? "$top_io_short_all,\n$clk_io_sim" : $clk_io_sim;
-	$top_io_full_all=$top_io_full_all."\n$clk_io_full";            
+    $soc->object_add_attribute('top_ip',undef,$top_ip);
+    #print @assigned_wires;
+    #generate top module
+    my ($clk_set, $clk_io_sim,$clk_io_full, $clk_assigned_port)= get_top_clk_setting($soc);
+    $top_io_short_all=(defined $top_io_short_all)? "$top_io_short_all,\n$clk_io_sim" : $clk_io_sim;
+    $top_io_full_all=$top_io_full_all."\n$clk_io_full";
     $top_io_pass_all=$top_io_pass_all.",\n$clk_assigned_port";
     my %jtag_info= get_soc_jtag_v($soc,$soc_name,$txview);
-	my $jtag_v=add_jtag_ctrl (\%jtag_info,$txview);
+    my $jtag_v=add_jtag_ctrl (\%jtag_info,$txview);
     my @chains = (sort { $b <=> $a } keys  %jtag_info);
-	$soc->object_add_attribute('JTAG','M_CHAIN',$chains[0]);
-    
-	my $top_v = (defined $param_as_in_v_all )? "module ${soc_name}_top  #(\n $param_as_in_v_all\n)(\n$top_io_short_all\n);\n": "module ${soc_name}_top (\n $top_io_short_all\n);\n $import ";
-	
-	
-	#my $ins= gen_soc_instance_v($soc,$soc_name,$param_pass_v,$txview);
-	
-	my $pass =  (defined $param_pass_v_all )? "#(\n$param_pass_v_all\n\t)\n": ""; 
-	
-	
-	$top_v=$top_v."
-$functions_all	
+    $soc->object_add_attribute('JTAG','M_CHAIN',$chains[0]);
+    my $top_v = (defined $param_as_in_v_all )? "module ${soc_name}_top  #(\n $param_as_in_v_all\n)(\n$top_io_short_all\n);\n": "module ${soc_name}_top (\n $top_io_short_all\n);\n $import ";
+    #my $ins= gen_soc_instance_v($soc,$soc_name,$param_pass_v,$txview);
+    my $pass =  (defined $param_pass_v_all )? "#(\n$param_pass_v_all\n\t)\n": "";
+    $top_v=$top_v."
+$functions_all
 $global_localparam
 $local_param_v_all
 $top_io_full_all
 $clk_set
-$jtag_v	
-\t${soc_name}${pass}\tthe_${soc_name} 
+$jtag_v
+\t${soc_name}${pass}\tthe_${soc_name}
 \t(
 $top_io_pass_all
 \t);
 endmodule
 ";
-	
-	my ($readme,$prog)=gen_system_info($soc,$param_as_in_v_all); 
-	return ("$soc_v",$top_v,$readme,$prog);
-
-
-}	
-
-
-
+    my ($readme,$prog)=gen_system_info($soc,$param_as_in_v_all);
+    return ("$soc_v",$top_v,$readme,$prog);
+}
 
 sub append_to_hash {
-	my ($ref,$att1,$att2,$data)=@_;
-	my %hash= %{$ref};
-	my $r = $hash{$att1}{$att2};
-	my @array= (defined  $r)? @{$r} : ();
-	push (@array,$data);
-	$hash{$att1}{$att2} = \@array;
-	return %hash;	
+    my ($ref,$att1,$att2,$data)=@_;
+    my %hash= %{$ref};
+    my $r = $hash{$att1}{$att2};
+    my @array= (defined  $r)? @{$r} : ();
+    push (@array,$data);
+    $hash{$att1}{$att2} = \@array;
+    return %hash;
 }
 
-
 sub get_soc_jtag_v{
-	my ($soc,$soc_name,$txview)=@_;
-	
-	my $processor_en=0;
-	#my $jtag_insts="";
-	#my $altera_jtag_ctrl=0;
-	#my $xilinx_jtag_ctrl=0;
-	#my $xilinx_jtag_ctrl_in;
-	#my $xilinx_jtag_ctrl_out;
-	my $jtag_inst_name="";
-	
-		
-	my $top=$soc->soc_get_top();
-	my @intfcs=$top->top_get_intfc_list();
-
-	my %jtag_info;
-	
-	foreach my $intfc (@intfcs){			
-		if( $intfc =~ /socket:jtag_to_wb\[/){ #check JTAG connect parameter. if it is XILINX then connect it to jtag tap
-			my @ports=$top->top_get_intfc_ports_list($intfc);
-			foreach my $p (@ports){
-				my($id,$range,$type,$intfc_name,$intfc_port)= $top->top_get_port($p);				
-				my $JTAG_CONNECT=$soc->soc_get_module_param_value ($id,'JTAG_CONNECT');						
-				$JTAG_CONNECT=remove_all_white_spaces($JTAG_CONNECT);
-				if($JTAG_CONNECT  =~ /XILINX_JTAG_WB/){
-					my $chain=$soc->soc_get_module_param_value ($id,'JTAG_CHAIN');		
-					my $index=$soc->soc_get_module_param_value ($id,'JTAG_INDEX');	
-					$jtag_inst_name= $soc->soc_get_instance_name($id);					
-					my %params	= $soc->soc_get_module_param($id);
-					my $new_range = add_instantc_name_to_parameters(\%params,$id,$range);
-					%jtag_info=append_to_hash (\%jtag_info,$chain,'wire',"\twire [ $new_range ] ${p};");
-		#			$jtag_def=$jtag_def."\twire [ $new_range ] ${p};\n";				
-					if($type eq 'input'){
-		#				$jtag_insts=$jtag_insts."$id XILINX JTAG,";
-						%jtag_info=append_to_hash (\%jtag_info,0,'inst',"$id XILINX JTAG");
-		#				$xilinx_jtag_ctrl++;
-						%jtag_info=append_to_hash (\%jtag_info,$chain,'xilinx_num',1);
-		#				$xilinx_jtag_ctrl_in=(defined $xilinx_jtag_ctrl_in)? "$xilinx_jtag_ctrl_in,$p" : "$p";
-						%jtag_info=append_to_hash (\%jtag_info,$chain,'input',$p);
-						%jtag_info=check_jtag_indexs(\%jtag_info,$chain,$index,$txview,$jtag_inst_name,0);
-						#print "\%jtag_info=check_jtag_indexs(\%jtag_info,$chain,$index,$txview,$jtag_inst_name);\n"
-						
-					}else {
-		#				$xilinx_jtag_ctrl_out=(defined $xilinx_jtag_ctrl_out)? "$xilinx_jtag_ctrl_out,$p" : "$p";
-						%jtag_info=append_to_hash (\%jtag_info,$chain,'output',$p);
-					}				
-				}#'"XILINX_JTAG_WB"'
-			
-				elsif($JTAG_CONNECT eq '"ALTERA_JTAG_WB"'){
-					my $index=$soc->soc_get_module_param_value ($id,'JTAG_INDEX');	
-					if($type eq 'input'){
-		#				$jtag_insts=$jtag_insts."$id ALTERA JTAG,";
-						%jtag_info=append_to_hash (\%jtag_info,0,'inst',"$id ALTERA JTAG");
-						%jtag_info=append_to_hash (\%jtag_info,0,'altera_num',1);
-						%jtag_info=check_jtag_indexs(\%jtag_info,0,$index,$txview,$jtag_inst_name,0);
-		#				$altera_jtag_ctrl++;
-										
-					}
-				}#'"ALTERA_JTAG_WB"'	
-
-			}	#$p	
-		}#if
-	
-	}
-	#print Dumper \%jtag_info;	
-	return %jtag_info;
+    my ($soc,$soc_name,$txview)=@_;
+    my $processor_en=0;
+    #my $jtag_insts="";
+    #my $altera_jtag_ctrl=0;
+    #my $xilinx_jtag_ctrl=0;
+    #my $xilinx_jtag_ctrl_in;
+    #my $xilinx_jtag_ctrl_out;
+    my $jtag_inst_name="";
+    my $top=$soc->soc_get_top();
+    my @intfcs=$top->top_get_intfc_list();
+    my %jtag_info;
+    foreach my $intfc (@intfcs){
+        if( $intfc =~ /socket:jtag_to_wb\[/){ #check JTAG connect parameter. if it is XILINX then connect it to jtag tap
+            my @ports=$top->top_get_intfc_ports_list($intfc);
+            foreach my $p (@ports){
+                my($id,$range,$type,$intfc_name,$intfc_port)= $top->top_get_port($p);
+                my $JTAG_CONNECT=$soc->soc_get_module_param_value ($id,'JTAG_CONNECT');
+                $JTAG_CONNECT=remove_all_white_spaces($JTAG_CONNECT);
+                if($JTAG_CONNECT  =~ /XILINX_JTAG_WB/){
+                    my $chain=$soc->soc_get_module_param_value ($id,'JTAG_CHAIN');
+                    my $index=$soc->soc_get_module_param_value ($id,'JTAG_INDEX');
+                    $jtag_inst_name= $soc->soc_get_instance_name($id);
+                    my %params    = $soc->soc_get_module_param($id);
+                    my $new_range = add_instantc_name_to_parameters(\%params,$id,$range);
+                    %jtag_info=append_to_hash (\%jtag_info,$chain,'wire',"\twire [ $new_range ] ${p};");
+        #            $jtag_def=$jtag_def."\twire [ $new_range ] ${p};\n";
+                    if($type eq 'input'){
+        #                $jtag_insts=$jtag_insts."$id XILINX JTAG,";
+                        %jtag_info=append_to_hash (\%jtag_info,0,'inst',"$id XILINX JTAG");
+        #                $xilinx_jtag_ctrl++;
+                        %jtag_info=append_to_hash (\%jtag_info,$chain,'xilinx_num',1);
+        #                $xilinx_jtag_ctrl_in=(defined $xilinx_jtag_ctrl_in)? "$xilinx_jtag_ctrl_in,$p" : "$p";
+                        %jtag_info=append_to_hash (\%jtag_info,$chain,'input',$p);
+                        %jtag_info=check_jtag_indexs(\%jtag_info,$chain,$index,$txview,$jtag_inst_name,0);
+                        #print "\%jtag_info=check_jtag_indexs(\%jtag_info,$chain,$index,$txview,$jtag_inst_name);\n"
+                    }else {
+        #                $xilinx_jtag_ctrl_out=(defined $xilinx_jtag_ctrl_out)? "$xilinx_jtag_ctrl_out,$p" : "$p";
+                        %jtag_info=append_to_hash (\%jtag_info,$chain,'output',$p);
+                    }
+                }#'"XILINX_JTAG_WB"'
+                elsif($JTAG_CONNECT eq '"ALTERA_JTAG_WB"'){
+                    my $index=$soc->soc_get_module_param_value ($id,'JTAG_INDEX');
+                    if($type eq 'input'){
+        #                $jtag_insts=$jtag_insts."$id ALTERA JTAG,";
+                        %jtag_info=append_to_hash (\%jtag_info,0,'inst',"$id ALTERA JTAG");
+                        %jtag_info=append_to_hash (\%jtag_info,0,'altera_num',1);
+                        %jtag_info=check_jtag_indexs(\%jtag_info,0,$index,$txview,$jtag_inst_name,0);
+        #                $altera_jtag_ctrl++;
+                    }
+                }#'"ALTERA_JTAG_WB"'
+            }    #$p
+        }#if
+    }
+    #print Dumper \%jtag_info;
+    return %jtag_info;
 }
 
-
 #################
-#	gen_module_inst
+#    gen_module_inst
 ###############
-
 sub get_io_nc_info  {
-	my($soc,$port,$inst,$intfc_name,$id)=@_;
-	my $IO='no';
-	my $NC='no';
-	my($i_type,$i_name,$i_num) =split("[:\[ \\]]", $intfc_name);		
-	if($i_type eq 'plug'){
-		my ($addr,$base,$end,$name,$connect_id,$connect_socket,$connect_socket_num)=$soc->soc_get_plug($id,$i_name,$i_num);
-			if($connect_id eq 'IO'){ $IO='yes';}
-			if($connect_id eq 'NC'){ $NC='yes';}
-	}		
-	if($i_type eq 'socket' && $i_name ne'wb_addr_map'){  
-			
-		my ($ref1,$ref2)= $soc->soc_get_modules_plug_connected_to_socket($id,$i_name,$i_num);
-		my %connected_plugs=%$ref1;
-		my %connected_plug_nums=%$ref2;
-		if(!%connected_plugs ){ 
-			my  ($s_type,$s_value,$s_connection_num)=$soc->soc_get_socket_of_instance($id,$i_name);
-			my $v=$soc->soc_get_module_param_value($id,$s_value);
-				if ( length( $v || '' )){ $IO='no';} else {
-					my $con= $soc->object_get_attribute("Unset-intfc" ,"$inst-$port");
-					if(!defined $con){ $IO='yes';}
-					else{
-						$IO='yes' if $con eq 'IO'; 
-					}
-				}
-			}
-		}
-		
-		
-	
-	return ($IO ,$NC);
+    my($soc,$port,$inst,$intfc_name,$id)=@_;
+    my $IO='no';
+    my $NC='no';
+    my($i_type,$i_name,$i_num) =split("[:\[ \\]]", $intfc_name);
+    if($i_type eq 'plug'){
+        my ($addr,$base,$end,$name,$connect_id,$connect_socket,$connect_socket_num)=$soc->soc_get_plug($id,$i_name,$i_num);
+            if($connect_id eq 'IO'){ $IO='yes';}
+            if($connect_id eq 'NC'){ $NC='yes';}
+    }
+    if($i_type eq 'socket' && $i_name ne'wb_addr_map'){
+        my ($ref1,$ref2)= $soc->soc_get_modules_plug_connected_to_socket($id,$i_name,$i_num);
+        my %connected_plugs=%$ref1;
+        my %connected_plug_nums=%$ref2;
+        if(!%connected_plugs ){
+            my  ($s_type,$s_value,$s_connection_num)=$soc->soc_get_socket_of_instance($id,$i_name);
+            my $v=$soc->soc_get_module_param_value($id,$s_value);
+                if ( length( $v || '' )){ $IO='no';} else {
+                    my $con= $soc->object_get_attribute("Unset-intfc" ,"$inst-$port");
+                    if(!defined $con){ $IO='yes';}
+                    else{
+                        $IO='yes' if $con eq 'IO';
+                    }
+                }
+            }
+        }
+    return ($IO ,$NC);
 }
 
-
-
 sub gen_module_inst {
-	my ($id,$soc,$top_ip,$intfc,$wires, $sim_only)=@_;
-	$sim_only = 0 if (!defined $sim_only);
-	my ($io_sim_v,$top_io_short,$param_as_in_v,$param_pass_v,$system_v);
-	my $top_io_pass;
-	my $src_io_short;
-	my $src_io_full="";
-	my $module 	=$soc->soc_get_module($id);
-	my $module_name	=$soc->soc_get_module_name($id);
-	my $category 	=$soc->soc_get_category($id);
-	
-	
-	my $inst   	= $soc->soc_get_instance_name($id);
-	my %params	= $soc->soc_get_module_param($id);
-	my %params_type	= $soc->soc_get_module_param_type($id);
-	
-	
-	
-	my $src_ip=$soc ->object_get_attribute('SOURCE_SET',"IP");
-	my $ip = ip->lib_new ();
-	$ip->add_ip($src_ip) if defined $src_ip;	
-	
-	
-	my @ports=$ip->ip_list_ports($category,$module);
-	my ($inst_v,$intfc_v,$plugs_assign_v,$sockets_assign_v);
-	my $wire_def_v="";
-	my $io_full_v="";
-	my $io_top_full_v="";
-	$plugs_assign_v="\n";
-	
-	
-	my $counter=0;
-	my @param_order=$soc->soc_get_instance_param_order($id);
-	
-	my ($param_v,$local_param_v,$instance_param_v)= gen_parameter_v(\%params,$id,$inst,$category,$module,$ip,\$param_as_in_v,\@param_order,$top_ip,\$param_pass_v,\%params_type);
-	
-	
-	
-	$top_ip->top_add_def_to_instance($id,'module',$module);
-	$top_ip->top_add_def_to_instance($id,'module_name',$module_name);
-	$top_ip->top_add_def_to_instance($id,'category',$category);
-	$top_ip->top_add_def_to_instance($id,'instance',$inst);
-	
-	#
-	my $assigned_ports="";
-	
-	#module name	
-	$inst_v=( defined $instance_param_v )? "$module_name #(\n": $module_name ; 
-	#module parameters
-	$inst_v=( defined $instance_param_v)? "$inst_v $instance_param_v\n\t)": $inst_v;
-	#module instance name 
-	$inst_v="$inst_v  $inst \t(\n";	
-	#module ports
-	$counter=0;
-	foreach my $port (@ports){
-		my ($type,$range,$intfc_name,$i_port)=$ip->ip_get_port($category,$module,$port);
-		my $assigned_port;
-		my($i_type,$i_name,$i_num) =split("[:\[ \\]]", $intfc_name);
-		
-		my ($IO ,$NC) =get_io_nc_info($soc,$port,$inst,$intfc_name,$id);
-		
-		
-		
-		if($NC eq 'yes'){
-			
-			
-		}
-		elsif($IO eq 'yes' || !defined $i_type || !defined $i_name || !defined $i_num){ #its an IO port
-			if($i_port eq 'NC' ){
-				$NC='yes';
-			}else {
-				 $i_name ='IO' if( !defined $i_name);
-				 
-								 
-				 $assigned_port="$inst\_$port";
-				 $io_sim_v= (!defined $io_sim_v)? "\t$assigned_port" : "$io_sim_v,\n\t$assigned_port";
-				 my $new_range = add_instantc_name_to_parameters(\%params,$inst,$range);
-				 my $r = (!defined $new_range)? 0 : (length ($new_range)>1 )?  1 : 0;
-				 
-				my $str = (!defined $new_range) ? "\t\t\t" : 
-				 			  ($new_range =~ /:/  ) ? "\t[ $new_range ]\t" : "\t$new_range\t";
-				 
-				
-				 my $port_def=  	"\t$type $str $assigned_port;\n";
-				 $io_full_v=$io_full_v.$port_def;
-				 
-				 if ($i_name eq 'RxD_sim' && $sim_only == 0){
-				 	#do notthing 
-				 }
-				 elsif($i_name eq 'enable'){
-				 	$top_io_pass = (!defined $top_io_pass )? "\t\t.$assigned_port($assigned_port & jtag_cpu_en)" : "$top_io_pass,\n\t\t.$assigned_port($assigned_port & jtag_cpu_en)"; 				 	
-				 	$top_io_short= (!defined $top_io_short)? "\t$assigned_port" : "$top_io_short, \n\t$assigned_port";
-				 	$io_top_full_v= $io_top_full_v.$port_def;				 	
-				 } elsif($i_name eq 'reset' || $i_name eq 'clk'){
-					#connection done using  get_top_clk_setting 
-				 	 $src_io_short= (!defined $src_io_short)? "\t$assigned_port" : "$src_io_short, \n\t$assigned_port"; 
-					 $src_io_full= $src_io_full.$port_def;
-				 } elsif( $i_name eq 'jtag_to_wb' ){
-				 	 $top_io_pass = (!defined $top_io_pass )? "\t\t.$assigned_port($assigned_port)" : "$top_io_pass,\n\t\t.$assigned_port($assigned_port)";
-				 
-				 }else{	
-					 $top_io_short= (!defined $top_io_short)? "\t$assigned_port" : "$top_io_short, \n\t$assigned_port"; 
-					 $top_io_pass = (!defined $top_io_pass )? "\t\t.$assigned_port($assigned_port)" : "$top_io_pass,\n\t\t.$assigned_port($assigned_port)";
-					 $io_top_full_v= $io_top_full_v.$port_def;
-				 }
-						 
-				 
-				 
-				# $top_ip->ipgen_add_port($assigned_port, $new_range, $type ,$intfc_name,$i_port);
-				$top_ip->top_add_port($id,$assigned_port, $new_range, $type ,$intfc_name,$i_port);
-			}
-			 
-			 
-		}
-		else{ # port connected internally using interface 
-			 $assigned_port="$inst\_$i_type\_$i_name\_$i_num\_$i_port";
-			 
-			 #create plug wires
-			 my ($wire_string,$port_name)=generate_wire ($range,$assigned_port,$inst,\%params,$i_type,$i_name,$i_num,$i_port, $wires);
-			 #add wire def if it is not defined before
-			
-			 add_text_to_string(\$wire_def_v,$wire_string)  if ($wire_def_v !~ /[\s\]]$port_name;/);
-				
-			 
-			 
-			if($i_type eq 'plug'){
-				#read socket port name
-				my ($addr,$base,$end,$name,$connect_id,$connect_socket,$connect_socket_num)=$soc->soc_get_plug($id,$i_name,$i_num);
-				my ($i_range,$t,$i_connect)=$intfc->get_port_info_of_plug($i_name,$i_port);
-				#my $connect_port= "socket_$i_name\_$i_num\_$i_connect";
-				if(defined $connect_socket_num){
-					my $connect_n=$soc->soc_get_instance_name($connect_id);
-					my $connect_port= "$connect_n\_socket_$i_name\_$connect_socket_num\_$i_connect";
-					#connect plug port to socket port
-					my $new_range = add_instantc_name_to_parameters(\%params,$inst,$range);
-					my $r= (!defined $range)? 0 : (length ($range)>1 )? 1 :0; 
-					
-					my $connect_port_range=($r==1)?"$connect_port\[$new_range\]":$connect_port;					
-					
-					if($type eq 'input' ){
-						$plugs_assign_v= "$plugs_assign_v \tassign  $assigned_port = $connect_port_range;\n";
-						$wires->wire_add($assigned_port,"connected",1);
-						
-					}else{
-						$plugs_assign_v= "$plugs_assign_v \tassign  $connect_port  = $assigned_port;\n";
-						$wires->wire_add($connect_port,"connected",1);						
-					}
-
-
-				}
-			}#plug
-			else{ #socket
-				my  ($s_type,$s_value,$s_connection_num)=$soc->soc_get_socket_of_instance($id,$i_name);
-				my $v=$soc->soc_get_module_param_value($id,$s_value);
-				my ($i_range,$t,$i_connect)=$intfc->get_port_info_of_socket($i_name,$i_port);
-				if ( length( $v || '' )) {
-						$v--;
-						my $name= $soc->soc_get_instance_name($id);
-						my $joint= "$name\_$i_type\_$i_name\_$v\_$i_port";
-						
-						my ($wire_string,$port_name)=generate_wire ($i_range,"$name\_$i_type\_$i_name\_$v\_$i_port",$inst,\%params,$i_type,$i_name,$i_num,$i_port, $wires);
-						add_text_to_string(\$wire_def_v,$wire_string) if ($wire_def_v !~ /[\s\]]$port_name;/);
-						
-						for(my $i=$v-1; $i>=0; $i--) {
-							$joint= "$joint ,$name\_$i_type\_$i_name\_$i\_$i_port";
-							#create socket wires
-							 #create plug wires
-							my ($wire_string,$port_name)=generate_wire ($i_range,"$name\_$i_type\_$i_name\_$i\_$i_port",$inst,\%params,$i_type,$i_name,$i_num,$i_port, $wires);
-							add_text_to_string(\$wire_def_v,$wire_string) if ($wire_def_v !~ /[\s\]]$port_name;/);
-				
-							
-							
-							
-							
-							
-						}
-						$wires->wire_add($assigned_port,"connected",1)  if($type eq 'input');
-						if($type ne 'input' ){
-							my @w=split('\s*,\s*',$joint);
-							foreach my $q (@w) {
-								$wires->wire_add($q,"connected",1);
-							}
-							
-						}
-						$joint=($v>0)? "\{ $joint\ }" : "$joint";
-						my $text=($type eq 'input' )? "\tassign $assigned_port = $joint;\n": "\tassign $joint = $assigned_port;\n";
-						
-						add_text_to_string(\$sockets_assign_v,$text);
-				}
-				
-				
-				
-			}#socket	
-			 
-			
-		}		
-		
-		$i_name ='IO' if (!defined $i_name);
-		my $reset_jtag_ored = ($i_name eq 'reset')? '| jtag_system_reset' : '';	
-		my $reset_jtag_nc = ($i_name eq 'reset')? 'jtag_system_reset' : '';		
-		
-		
-		if (++$counter == scalar(@ports)){#last port def
-			
-			$inst_v=($NC eq 'yes')? "$inst_v\t\t.$port()\n": "$inst_v\t\t.$port($assigned_port)\n";
-			$assigned_ports=($NC eq 'yes')? "$assigned_ports\t\t.$port($reset_jtag_nc)\n": "$assigned_ports\t\t.$port($assigned_port $reset_jtag_ored)\n";
-			
-		}
-		else {
-			$inst_v=($NC eq 'yes')? "$inst_v\t\t.$port(),\n":"$inst_v\t\t.$port($assigned_port),\n";
-			$assigned_ports=($NC eq 'yes')? "$assigned_ports\t\t.$port($reset_jtag_nc),\n":"$assigned_ports\t\t.$port($assigned_port $reset_jtag_ored),\n";
-		}
-		
-		if($type ne 'input' && $NC ne 'yes' ){
-			$wires->wire_add($assigned_port,"connected",1);
-			
-		}
-		
-		
-		
-	}	
-	$inst_v="$inst_v\t);\n";
-	
-	
-	
-	my $hdr =$ip->ip_get($category,$module,'system_v');
-	if(defined $hdr){
-			$hdr=replace_golb_var($hdr,\%params);
-	    	$system_v= "$system_v $hdr\n";
-	}
-	
-	return ($param_v, $local_param_v, $wire_def_v, $inst_v, $plugs_assign_v, $sockets_assign_v,	$io_full_v,
-	$io_top_full_v,$io_sim_v,$top_io_short,$param_as_in_v,$param_pass_v,$system_v,$assigned_ports,$top_io_pass,
-	$src_io_short, $src_io_full);
-	#return ($param_v, $local_param_v, $wire_def_v, $inst_v, $plugs_assign_v, $sockets_assign_v,$io_full_v,$io_top_full_v,$param_pass_v,$assigned_ports);
-	
-	
-}	
-
+    my ($id,$soc,$top_ip,$intfc,$wires, $sim_only)=@_;
+    $sim_only = 0 if (!defined $sim_only);
+    my ($io_sim_v,$top_io_short,$param_as_in_v,$param_pass_v,$system_v);
+    my $top_io_pass;
+    my $src_io_short;
+    my $src_io_full="";
+    my $module     =$soc->soc_get_module($id);
+    my $module_name    =$soc->soc_get_module_name($id);
+    my $category     =$soc->soc_get_category($id);
+    my $inst       = $soc->soc_get_instance_name($id);
+    my %params    = $soc->soc_get_module_param($id);
+    my %params_type    = $soc->soc_get_module_param_type($id);
+    my $src_ip=$soc ->object_get_attribute('SOURCE_SET',"IP");
+    my $ip = ip->lib_new ();
+    $ip->add_ip($src_ip) if defined $src_ip;
+    my @ports=$ip->ip_list_ports($category,$module);
+    my ($inst_v,$intfc_v,$plugs_assign_v,$sockets_assign_v);
+    my $wire_def_v="";
+    my $io_full_v="";
+    my $io_top_full_v="";
+    $plugs_assign_v="\n";
+    my $counter=0;
+    my @param_order=$soc->soc_get_instance_param_order($id);
+    my ($param_v,$local_param_v,$instance_param_v)= gen_parameter_v(\%params,$id,$inst,$category,$module,$ip,\$param_as_in_v,\@param_order,$top_ip,\$param_pass_v,\%params_type);
+    $top_ip->top_add_def_to_instance($id,'module',$module);
+    $top_ip->top_add_def_to_instance($id,'module_name',$module_name);
+    $top_ip->top_add_def_to_instance($id,'category',$category);
+    $top_ip->top_add_def_to_instance($id,'instance',$inst);
+    #
+    my $assigned_ports="";
+    #module name
+    $inst_v=( defined $instance_param_v )? "$module_name #(\n": $module_name ;
+    #module parameters
+    $inst_v=( defined $instance_param_v)? "$inst_v $instance_param_v\n\t)": $inst_v;
+    #module instance name
+    $inst_v="$inst_v  $inst \t(\n";
+    #module ports
+    $counter=0;
+    foreach my $port (@ports){
+        my ($type,$range,$intfc_name,$i_port)=$ip->ip_get_port($category,$module,$port);
+        my $assigned_port;
+        my($i_type,$i_name,$i_num) =split("[:\[ \\]]", $intfc_name);
+        my ($IO ,$NC) =get_io_nc_info($soc,$port,$inst,$intfc_name,$id);
+        if($NC eq 'yes'){
+        }
+        elsif($IO eq 'yes' || !defined $i_type || !defined $i_name || !defined $i_num){ #its an IO port
+            if($i_port eq 'NC' ){
+                $NC='yes';
+            }else {
+                $i_name ='IO' if( !defined $i_name);
+                $assigned_port="$inst\_$port";
+                $io_sim_v= (!defined $io_sim_v)? "\t$assigned_port" : "$io_sim_v,\n\t$assigned_port";
+                my $new_range = add_instantc_name_to_parameters(\%params,$inst,$range);
+                my $r = (!defined $new_range)? 0 : (length ($new_range)>1 )?  1 : 0;
+                my $str = (!defined $new_range) ? "\t\t\t" :
+                            ($new_range =~ /:/  ) ? "\t[ $new_range ]\t" : "\t$new_range\t";
+                my $port_def=      "\t$type $str $assigned_port;\n";
+                $io_full_v=$io_full_v.$port_def;
+                if ($i_name eq 'RxD_sim' && $sim_only == 0){
+                    #do notthing
+                }
+                elsif($i_name eq 'enable'){
+                    $top_io_pass = (!defined $top_io_pass )? "\t\t.$assigned_port($assigned_port & jtag_cpu_en)" : "$top_io_pass,\n\t\t.$assigned_port($assigned_port & jtag_cpu_en)";
+                    $top_io_short= (!defined $top_io_short)? "\t$assigned_port" : "$top_io_short, \n\t$assigned_port";
+                    $io_top_full_v= $io_top_full_v.$port_def;
+                } elsif($i_name eq 'reset' || $i_name eq 'clk'){
+                    #connection done using  get_top_clk_setting
+                    $src_io_short= (!defined $src_io_short)? "\t$assigned_port" : "$src_io_short, \n\t$assigned_port";
+                    $src_io_full= $src_io_full.$port_def;
+                } elsif( $i_name eq 'jtag_to_wb' ){
+                    $top_io_pass = (!defined $top_io_pass )? "\t\t.$assigned_port($assigned_port)" : "$top_io_pass,\n\t\t.$assigned_port($assigned_port)";
+                }else{
+                    $top_io_short= (!defined $top_io_short)? "\t$assigned_port" : "$top_io_short, \n\t$assigned_port";
+                    $top_io_pass = (!defined $top_io_pass )? "\t\t.$assigned_port($assigned_port)" : "$top_io_pass,\n\t\t.$assigned_port($assigned_port)";
+                    $io_top_full_v= $io_top_full_v.$port_def;
+                }
+                # $top_ip->ipgen_add_port($assigned_port, $new_range, $type ,$intfc_name,$i_port);
+                $top_ip->top_add_port($id,$assigned_port, $new_range, $type ,$intfc_name,$i_port);
+            }
+        }
+        else{ # port connected internally using interface
+            $assigned_port="$inst\_$i_type\_$i_name\_$i_num\_$i_port";
+            #create plug wires
+            my ($wire_string,$port_name)=generate_wire ($range,$assigned_port,$inst,\%params,$i_type,$i_name,$i_num,$i_port, $wires);
+            #add wire def if it is not defined before
+            add_text_to_string(\$wire_def_v,$wire_string)  if ($wire_def_v !~ /[\s\]]$port_name;/);
+            if($i_type eq 'plug'){
+                #read socket port name
+                my ($addr,$base,$end,$name,$connect_id,$connect_socket,$connect_socket_num)=$soc->soc_get_plug($id,$i_name,$i_num);
+                my ($i_range,$t,$i_connect)=$intfc->get_port_info_of_plug($i_name,$i_port);
+                #my $connect_port= "socket_$i_name\_$i_num\_$i_connect";
+                if(defined $connect_socket_num){
+                    my $connect_n=$soc->soc_get_instance_name($connect_id);
+                    my $connect_port= "$connect_n\_socket_$i_name\_$connect_socket_num\_$i_connect";
+                    #connect plug port to socket port
+                    my $new_range = add_instantc_name_to_parameters(\%params,$inst,$range);
+                    my $r= (!defined $range)? 0 : (length ($range)>1 )? 1 :0;
+                    my $connect_port_range=($r==1)?"$connect_port\[$new_range\]":$connect_port;
+                    if($type eq 'input' ){
+                        $plugs_assign_v= "$plugs_assign_v \tassign  $assigned_port = $connect_port_range;\n";
+                        $wires->wire_add($assigned_port,"connected",1);
+                    }else{
+                        $plugs_assign_v= "$plugs_assign_v \tassign  $connect_port  = $assigned_port;\n";
+                        $wires->wire_add($connect_port,"connected",1);
+                    }
+                }
+            }#plug
+            else{ #socket
+                my  ($s_type,$s_value,$s_connection_num)=$soc->soc_get_socket_of_instance($id,$i_name);
+                my $v=$soc->soc_get_module_param_value($id,$s_value);
+                my ($i_range,$t,$i_connect)=$intfc->get_port_info_of_socket($i_name,$i_port);
+                if ( length( $v || '' )) {
+                        $v--;
+                        my $name= $soc->soc_get_instance_name($id);
+                        my $joint= "$name\_$i_type\_$i_name\_$v\_$i_port";
+                        my ($wire_string,$port_name)=generate_wire ($i_range,"$name\_$i_type\_$i_name\_$v\_$i_port",$inst,\%params,$i_type,$i_name,$i_num,$i_port, $wires);
+                        add_text_to_string(\$wire_def_v,$wire_string) if ($wire_def_v !~ /[\s\]]$port_name;/);
+                        for(my $i=$v-1; $i>=0; $i--) {
+                            $joint= "$joint ,$name\_$i_type\_$i_name\_$i\_$i_port";
+                            #create socket wires
+                            #create plug wires
+                            my ($wire_string,$port_name)=generate_wire ($i_range,"$name\_$i_type\_$i_name\_$i\_$i_port",$inst,\%params,$i_type,$i_name,$i_num,$i_port, $wires);
+                            add_text_to_string(\$wire_def_v,$wire_string) if ($wire_def_v !~ /[\s\]]$port_name;/);
+                        }
+                        $wires->wire_add($assigned_port,"connected",1)  if($type eq 'input');
+                        if($type ne 'input' ){
+                            my @w=split('\s*,\s*',$joint);
+                            foreach my $q (@w) {
+                                $wires->wire_add($q,"connected",1);
+                            }
+                        }
+                        $joint=($v>0)? "\{ $joint\ }" : "$joint";
+                        my $text=($type eq 'input' )? "\tassign $assigned_port = $joint;\n": "\tassign $joint = $assigned_port;\n";
+                        add_text_to_string(\$sockets_assign_v,$text);
+                }
+            }#socket
+        }
+        $i_name ='IO' if (!defined $i_name);
+        my $reset_jtag_ored = ($i_name eq 'reset')? '| jtag_system_reset' : '';
+        my $reset_jtag_nc = ($i_name eq 'reset')? 'jtag_system_reset' : '';
+        if (++$counter == scalar(@ports)){#last port def
+            $inst_v=($NC eq 'yes')? "$inst_v\t\t.$port()\n": "$inst_v\t\t.$port($assigned_port)\n";
+            $assigned_ports=($NC eq 'yes')? "$assigned_ports\t\t.$port($reset_jtag_nc)\n": "$assigned_ports\t\t.$port($assigned_port $reset_jtag_ored)\n";
+        }
+        else {
+            $inst_v=($NC eq 'yes')? "$inst_v\t\t.$port(),\n":"$inst_v\t\t.$port($assigned_port),\n";
+            $assigned_ports=($NC eq 'yes')? "$assigned_ports\t\t.$port($reset_jtag_nc),\n":"$assigned_ports\t\t.$port($assigned_port $reset_jtag_ored),\n";
+        }
+        if($type ne 'input' && $NC ne 'yes' ){
+            $wires->wire_add($assigned_port,"connected",1);
+        }
+    }
+    $inst_v="$inst_v\t);\n";
+    my $hdr =$ip->ip_get($category,$module,'system_v');
+    if(defined $hdr){
+            $hdr=replace_golb_var($hdr,\%params);
+            $system_v= "$system_v $hdr\n";
+    }
+    return ($param_v, $local_param_v, $wire_def_v, $inst_v, $plugs_assign_v, $sockets_assign_v,    $io_full_v,
+    $io_top_full_v,$io_sim_v,$top_io_short,$param_as_in_v,$param_pass_v,$system_v,$assigned_ports,$top_io_pass,
+    $src_io_short, $src_io_full);
+    #return ($param_v, $local_param_v, $wire_def_v, $inst_v, $plugs_assign_v, $sockets_assign_v,$io_full_v,$io_top_full_v,$param_pass_v,$assigned_ports);
+}
 
 sub add_instantc_name_to_parameters{
-	my ($params_ref,$inst,$range)=@_;
-	my $new_range=$range;
-	#print "$new_range\n";
-	return $new_range if(!defined $range);
-	my @list=sort keys%{$params_ref};
-	foreach my $param (@list){
-		my $new_param= "$inst\_$param";
-		($new_range=$new_range)=~ s/\b$param\b/$new_param/g;
-		#print "$new_range= s/\b$param\b/$new_param/g\n";
-	}
-		return $new_range;
-}			
-
+    my ($params_ref,$inst,$range)=@_;
+    my $new_range=$range;
+    #print "$new_range\n";
+    return $new_range if(!defined $range);
+    my @list=sort keys%{$params_ref};
+    foreach my $param (@list){
+        my $new_param= "$inst\_$param";
+        ($new_range=$new_range)=~ s/\b$param\b/$new_param/g;
+        #print "$new_range= s/\b$param\b/$new_param/g\n";
+    }
+        return $new_range;
+}
 
 sub gen_parameter_v{
-	my ($param_ref,$id,$inst,$category,$module,$ip,$param_as_in_v,$ref_ordered,$top_ip,$param_pass_v,$param_type_ref)=@_;
-	my %params=%{$param_ref};
-	my %params_type=%{$param_type_ref};
-	my @param_order;
-	@param_order=@{$ref_ordered} if(defined $ref_ordered);
-	
-	my ($param_v,$local_param_v,$instance_param_v);	
-	my @list;
-	@list= (@param_order)? @param_order : 	sort keys%params;
-	my $first_param=1;
-	
-	$local_param_v="";
-	$param_v="";
-	
-	#add instance name to parameter value
-	foreach my $param (@list){
-		$params{$param}=add_instantc_name_to_parameters(\%params,$inst,$params{$param});
-		#%params_type{$param}=add_instantc_name_to_parameters(\%params_type,$inst,$params_type{$param});
-	}
-
-
-	#print parameters
-	foreach my $param (@list){
-		my $inst_param= "$inst\_$param";
-		my ($default,$type,$content,$info,$vfile_param_type,$redefine_param)= $ip->ip_get_parameter($category,$module,$param);
-		$vfile_param_type= "Don't include" if (!defined $vfile_param_type );
-		if ($vfile_param_type eq "Localparam"){
-			my $type = $params_type{$param};
-			$type = "Localparam" if (! defined $type);	
-			$vfile_param_type = ($type eq 'Parameter')?  "Parameter" : "Localparam";			
-		}
-			
-		
-		
-		#$vfile_param_type= "Parameter"  if ($vfile_param_type eq 1);
-		#$vfile_param_type= "Localparam" if ($vfile_param_type eq 0);		
-		$redefine_param=1 if (! defined $redefine_param);
-		$redefine_param=0 if ($vfile_param_type eq "Don't include");
-		if($redefine_param eq 1){				
-			$instance_param_v=($first_param eq 1)? "\t\t.$param($inst_param)" : "$instance_param_v,\n\t\t.$param($inst_param)";
-			$first_param=0;		
-
-		}
-		
-		
-		
-		if($vfile_param_type eq "Localparam"){
-			$local_param_v="$local_param_v\tlocalparam\t$inst_param=$params{$param};\n"; 
-			$top_ip->top_add_localparam($id,$inst_param,$params{$param},$type,$content,$info,$vfile_param_type,$redefine_param);
-		}
-		elsif($vfile_param_type eq "Parameter"){
-			#print "$inst_param($inst_param)\n";
-			$param_v="$param_v\tparameter\t$inst_param=$params{$param};\n"; 
-			$$param_pass_v =(defined ($$param_pass_v ))? "$$param_pass_v,\n\t\t.$inst_param($inst_param)": "\t\t.$inst_param($inst_param)";
-			$$param_as_in_v=(defined ($$param_as_in_v))? "$$param_as_in_v ,\n\tparameter\t$inst_param=$params{$param}":
-														 "   \tparameter\t$inst_param=$params{$param}";
-			#add parameter to top 
-			#$top_ip  $inst_param			
-			$top_ip->top_add_parameter($id,$inst_param,$params{$param},$type,$content,$info,$vfile_param_type,$redefine_param);
-			
-		}
-		
-		
-		
-	}
-	
-	return ($param_v,$local_param_v,$instance_param_v);	
-	
-	
-}	
+    my ($param_ref,$id,$inst,$category,$module,$ip,$param_as_in_v,$ref_ordered,$top_ip,$param_pass_v,$param_type_ref)=@_;
+    my %params=%{$param_ref};
+    my %params_type=%{$param_type_ref};
+    my @param_order;
+    @param_order=@{$ref_ordered} if(defined $ref_ordered);
+    my ($param_v,$local_param_v,$instance_param_v);
+    my @list;
+    @list= (@param_order)? @param_order :     sort keys%params;
+    my $first_param=1;
+    $local_param_v="";
+    $param_v="";
+    #add instance name to parameter value
+    foreach my $param (@list){
+        $params{$param}=add_instantc_name_to_parameters(\%params,$inst,$params{$param});
+        #%params_type{$param}=add_instantc_name_to_parameters(\%params_type,$inst,$params_type{$param});
+    }
+    #print parameters
+    foreach my $param (@list){
+        my $inst_param= "$inst\_$param";
+        my ($default,$type,$content,$info,$vfile_param_type,$redefine_param)= $ip->ip_get_parameter($category,$module,$param);
+        $vfile_param_type= "Don't include" if (!defined $vfile_param_type );
+        if ($vfile_param_type eq "Localparam"){
+            my $type = $params_type{$param};
+            $type = "Localparam" if (! defined $type);
+            $vfile_param_type = ($type eq 'Parameter')?  "Parameter" : "Localparam";
+        }
+        #$vfile_param_type= "Parameter"  if ($vfile_param_type eq 1);
+        #$vfile_param_type= "Localparam" if ($vfile_param_type eq 0);
+        $redefine_param=1 if (! defined $redefine_param);
+        $redefine_param=0 if ($vfile_param_type eq "Don't include");
+        if($redefine_param eq 1){
+            $instance_param_v=($first_param eq 1)? "\t\t.$param($inst_param)" : "$instance_param_v,\n\t\t.$param($inst_param)";
+            $first_param=0;
+        }
+        if($vfile_param_type eq "Localparam"){
+            $local_param_v="$local_param_v\tlocalparam\t$inst_param=$params{$param};\n";
+            $top_ip->top_add_localparam($id,$inst_param,$params{$param},$type,$content,$info,$vfile_param_type,$redefine_param);
+        }
+        elsif($vfile_param_type eq "Parameter"){
+            #print "$inst_param($inst_param)\n";
+            $param_v="$param_v\tparameter\t$inst_param=$params{$param};\n";
+            $$param_pass_v =(defined ($$param_pass_v ))? "$$param_pass_v,\n\t\t.$inst_param($inst_param)": "\t\t.$inst_param($inst_param)";
+            $$param_as_in_v=(defined ($$param_as_in_v))? "$$param_as_in_v ,\n\tparameter\t$inst_param=$params{$param}":
+                                                        "   \tparameter\t$inst_param=$params{$param}";
+            #add parameter to top
+            #$top_ip  $inst_param
+            $top_ip->top_add_parameter($id,$inst_param,$params{$param},$type,$content,$info,$vfile_param_type,$redefine_param);
+        }
+    }
+    return ($param_v,$local_param_v,$instance_param_v);
+}
 
 ###############
-#	generate_address_cmp
+#    generate_address_cmp
 ##############
-
 sub generate_address_cmp{
-	my ($soc,$wires)=@_;
-	my $number=0;
-	my $addr_mp_v="\n//Wishbone slave address match\n";
-	my $instance_addr_localparam="\n//Wishbone slave base address based on instance name\n";
-	my $module_addr_localparam="\n//Wishbone slave base address based on module name. \n";
-	
-	my @all_instances=$soc->soc_get_all_instances();
-	foreach my $instance_id (@all_instances){
-		my $instance_name=$soc->soc_get_instance_name($instance_id);
-			my @plugs= $soc->soc_get_all_plugs_of_an_instance($instance_id);
-			foreach my $plug (@plugs){
-				my @nums=$soc->soc_list_plug_nums($instance_id,$plug);				
-				foreach my $num (@nums){
-					my ($addr,$base,$end,$name,$connect_id,$connect_socket,$connect_socket_num)=$soc->soc_get_plug($instance_id,$plug,$num);
-					if((defined $connect_socket) && ($connect_socket eq 'wb_slave')){
-						#read wishbone bus address and data width size						
-						my $Aw=$soc->soc_get_module_param_value ($connect_id,'Aw');
-						my $Dw=$soc->soc_get_module_param_value ($connect_id,'Dw');
-						$Aw=32 if (!defined $Aw); 
-						$Dw=32 if (!defined $Dw); 
-						add_text_to_string(\$addr_mp_v,"/* $instance_name wb_slave $num */\n");
-						#count how many nibbles we have in address size 
-						my $hh= ($Aw % 4)? ($Aw >> 2)+1 : ($Aw >> 2);
-						$hh= "'h%0${hh}x";#hex address nibble num
-						#change addresses to word as the assign addresses by ProNoC GUI are in bytes  
-						my $bytenum=($Dw/8);
-						my $base_hex=$Aw.sprintf($hh, ($base/$bytenum));
-						my $end_hex=$Aw.sprintf($hh, ($end/$bytenum));
-						#my $base_hex=sprintf("32'h%08x", ($base>>2));
-						#my $end_hex=sprintf("32'h%08x", ($end>>2));
-						add_text_to_string(\$instance_addr_localparam,"\tlocalparam \t$instance_name\_WB$num\_BASE_ADDR\t=\t$base_hex;\n");
-						add_text_to_string(\$instance_addr_localparam,"\tlocalparam \t$instance_name\_WB$num\_END_ADDR\t=\t$end_hex;\n");
-						if($instance_name ne $instance_id){
-							add_text_to_string(\$module_addr_localparam,"\tlocalparam \t$instance_id\_WB$num\_BASE_ADDR\t=\t$base_hex;\n");
-							add_text_to_string(\$module_addr_localparam,"\tlocalparam \t$instance_id\_WB$num\_END_ADDR\t=\t$end_hex;\n");
-						}
-						
-						my $connect_name=$soc->soc_get_instance_name($connect_id);
-						$wires->wire_add("$connect_name\_socket_wb_addr_map_0_sel_one_hot","connected",1);
-						$addr_mp_v="$addr_mp_v \tassign $connect_name\_socket_wb_addr_map_0_sel_one_hot[$connect_socket_num\] = (($connect_name\_socket_wb_addr_map_0_grant_addr >= $instance_name\_WB$num\_BASE_ADDR)   & ($connect_name\_socket_wb_addr_map_0_grant_addr <= $instance_name\_WB$num\_END_ADDR));\n";
-						
-						$number++;
-					}#if
-				}#foreach my $num
-			}#foreach my $plug
-		}#foreach my $instance_id
-		
-		add_text_to_string(\$instance_addr_localparam,"\n");
-		add_text_to_string(\$module_addr_localparam,"\n");
-		return ($addr_mp_v,$instance_addr_localparam,$module_addr_localparam);	
-}	
-
+    my ($soc,$wires)=@_;
+    my $number=0;
+    my $addr_mp_v="\n//Wishbone slave address match\n";
+    my $instance_addr_localparam="\n//Wishbone slave base address based on instance name\n";
+    my $module_addr_localparam="\n//Wishbone slave base address based on module name. \n";
+    my @all_instances=$soc->soc_get_all_instances();
+    foreach my $instance_id (@all_instances){
+        my $instance_name=$soc->soc_get_instance_name($instance_id);
+            my @plugs= $soc->soc_get_all_plugs_of_an_instance($instance_id);
+            foreach my $plug (@plugs){
+                my @nums=$soc->soc_list_plug_nums($instance_id,$plug);
+                foreach my $num (@nums){
+                    my ($addr,$base,$end,$name,$connect_id,$connect_socket,$connect_socket_num)=$soc->soc_get_plug($instance_id,$plug,$num);
+                    if((defined $connect_socket) && ($connect_socket eq 'wb_slave')){
+                        #read wishbone bus address and data width size
+                        my $Aw=$soc->soc_get_module_param_value ($connect_id,'Aw');
+                        my $Dw=$soc->soc_get_module_param_value ($connect_id,'Dw');
+                        $Aw=32 if (!defined $Aw);
+                        $Dw=32 if (!defined $Dw);
+                        add_text_to_string(\$addr_mp_v,"/* $instance_name wb_slave $num */\n");
+                        #count how many nibbles we have in address size
+                        my $hh= ($Aw % 4)? ($Aw >> 2)+1 : ($Aw >> 2);
+                        $hh= "'h%0${hh}x";#hex address nibble num
+                        #change addresses to word as the assign addresses by ProNoC GUI are in bytes
+                        my $bytenum=($Dw/8);
+                        my $base_hex=$Aw.sprintf($hh, ($base/$bytenum));
+                        my $end_hex=$Aw.sprintf($hh, ($end/$bytenum));
+                        #my $base_hex=sprintf("32'h%08x", ($base>>2));
+                        #my $end_hex=sprintf("32'h%08x", ($end>>2));
+                        add_text_to_string(\$instance_addr_localparam,"\tlocalparam \t$instance_name\_WB$num\_BASE_ADDR\t=\t$base_hex;\n");
+                        add_text_to_string(\$instance_addr_localparam,"\tlocalparam \t$instance_name\_WB$num\_END_ADDR\t=\t$end_hex;\n");
+                        if($instance_name ne $instance_id){
+                            add_text_to_string(\$module_addr_localparam,"\tlocalparam \t$instance_id\_WB$num\_BASE_ADDR\t=\t$base_hex;\n");
+                            add_text_to_string(\$module_addr_localparam,"\tlocalparam \t$instance_id\_WB$num\_END_ADDR\t=\t$end_hex;\n");
+                        }
+                        my $connect_name=$soc->soc_get_instance_name($connect_id);
+                        $wires->wire_add("$connect_name\_socket_wb_addr_map_0_sel_one_hot","connected",1);
+                        $addr_mp_v="$addr_mp_v \tassign $connect_name\_socket_wb_addr_map_0_sel_one_hot[$connect_socket_num\] = (($connect_name\_socket_wb_addr_map_0_grant_addr >= $instance_name\_WB$num\_BASE_ADDR)   & ($connect_name\_socket_wb_addr_map_0_grant_addr <= $instance_name\_WB$num\_END_ADDR));\n";
+                        $number++;
+                    }#if
+                }#foreach my $num
+            }#foreach my $plug
+        }#foreach my $instance_id
+        add_text_to_string(\$instance_addr_localparam,"\n");
+        add_text_to_string(\$module_addr_localparam,"\n");
+        return ($addr_mp_v,$instance_addr_localparam,$module_addr_localparam);
+}
 
 sub add_text_to_string{
-		my ($string,$text)=@_;
-		if(defined $text){
-			$$string=(defined ($$string))? "$$string $text" : $text;	
-		}
-}	
-
-
+        my ($string,$text)=@_;
+        if(defined $text){
+            $$string=(defined ($$string))? "$$string $text" : $text;
+        }
+}
 
 sub generate_wire {
-	my($range,$port_name,$inst_name,$params_ref,$i_type,$i_name,$i_num,$i_port, $wires)=@_;
-	my $wire_string;
-	my $new_range;
-	my $r= (!defined $range)? 0 : (length ($range)>1 )? 1 :0; 
-	
-	if($r ==1 ){
-		#replace parameter in range
-		$new_range = add_instantc_name_to_parameters($params_ref,$inst_name,$range);
-		$wire_string= "\twire\t[ $new_range ] $port_name;\n";				
-	}
-	else{
-		$wire_string="\twire\t\t\t $port_name;\n";
-	}
-	$wires->wire_add("$port_name","range",$new_range);
-	$wires->wire_add("$port_name","inst_name",$inst_name);
-	$wires->wire_add("$port_name","i_type",$i_type);
-	$wires->wire_add("$port_name","i_name",$i_name);
-	$wires->wire_add("$port_name","i_num",$i_num);
-	$wires->wire_add("$port_name","i_port",$i_port);
-		
-	return ($wire_string,$port_name);	
-}	
+    my($range,$port_name,$inst_name,$params_ref,$i_type,$i_name,$i_num,$i_port, $wires)=@_;
+    my $wire_string;
+    my $new_range;
+    my $r= (!defined $range)? 0 : (length ($range)>1 )? 1 :0;
+    if($r ==1 ){
+        #replace parameter in range
+        $new_range = add_instantc_name_to_parameters($params_ref,$inst_name,$range);
+        $wire_string= "\twire\t[ $new_range ] $port_name;\n";
+    }
+    else{
+        $wire_string="\twire\t\t\t $port_name;\n";
+    }
+    $wires->wire_add("$port_name","range",$new_range);
+    $wires->wire_add("$port_name","inst_name",$inst_name);
+    $wires->wire_add("$port_name","i_type",$i_type);
+    $wires->wire_add("$port_name","i_name",$i_name);
+    $wires->wire_add("$port_name","i_num",$i_num);
+    $wires->wire_add("$port_name","i_port",$i_port);
+    return ($wire_string,$port_name);
+}
 
 sub port_width_repeat{
-	my ($range,$value)=@_;
-	return "$value" if (!defined $range);
-	$range= remove_all_white_spaces($range);
-	my ($h,$l)=split(':',$range);
-	return "$value" if(!defined $h ) ; # port width is 1
-	return "$value" if($h eq "0" && "$l" eq "0"); # port width is 1
-	$h=$l if($h eq "0" && "$l" ne "0"); 
-	if($h =~ /-1$/){ # the address ranged is endup with -1 
-		$h =~ s/-1$//; # remove -1
-		return "\{$h\{$value\}\}"  if($h =~ /\)$/);
-		return "\{($h)\{$value\}\}" if($h =~ /[\*\.\+\-\^\%\&]/);
-		return "\{$h\{$value\}\}";
-	}
-	return "\{($h+1){$value}}";	
+    my ($range,$value)=@_;
+    return "$value" if (!defined $range);
+    $range= remove_all_white_spaces($range);
+    my ($h,$l)=split(':',$range);
+    return "$value" if(!defined $h ) ; # port width is 1
+    return "$value" if($h eq "0" && "$l" eq "0"); # port width is 1
+    $h=$l if($h eq "0" && "$l" ne "0");
+    if($h =~ /-1$/){ # the address ranged is endup with -1
+        $h =~ s/-1$//; # remove -1
+        return "\{$h\{$value\}\}"  if($h =~ /\)$/);
+        return "\{($h)\{$value\}\}" if($h =~ /[\*\.\+\-\^\%\&]/);
+        return "\{$h\{$value\}\}";
+    }
+    return "\{($h+1){$value}}";
 }
 
 sub assign_unconnected_wires{
-	my($wires,$intfc)=@_;
-	my $unused_wire_v=undef;
-	
-	my @all_wires=$wires->wires_list();
-	foreach my $p (@all_wires ){
-		if(!defined $wires->wire_get($p,"connected")){ # unconnected wires
-			# Take default value from interface definition 
-			#$wires->wire_get("$p","inst_name");
-			my $i_type=$wires->wire_get($p,"i_type");
-			my $i_name= $wires->wire_get($p,"i_name");
-			my $i_num=$wires->wire_get($p,"i_num");
-			my $i_port=$wires->wire_get($p,"i_port");
-			my $new_range=$wires->wire_get($p,"range");
-			my ($range,$type,$connect,$default_out) = ($i_type eq "socket" )? $intfc->get_port_info_of_socket($i_name,$i_port):
-																			  $intfc->get_port_info_of_plug($i_name,$i_port);
-			#""Active high","Don't care"
-			
-			my $default=(!defined $default_out		  )? port_width_repeat($new_range,"1\'bx"):
-						($default_out eq 'Active low' )? port_width_repeat($new_range,"1\'b0"):
-					    ($default_out eq 'Active high')? port_width_repeat($new_range,"1\'b1"):
- 						($default_out eq 'Don\'t care')? port_width_repeat($new_range,"1\'bx"): $default_out;
-					    
-			
-			$unused_wire_v= (defined $unused_wire_v)? "$unused_wire_v \tassign ${p} = $default;\n" : "\tassign ${p} = $default;\n";
-		
-		}
-		
-	}
-	$unused_wire_v="\n//Take the default value for ports that defined by interfaces but did not assigned to any wires.\n $unused_wire_v\n\n" if(defined $unused_wire_v); 
-	return $unused_wire_v;
-
-	
+    my($wires,$intfc)=@_;
+    my $unused_wire_v=undef;
+    my @all_wires=$wires->wires_list();
+    foreach my $p (@all_wires ){
+        if(!defined $wires->wire_get($p,"connected")){ # unconnected wires
+            # Take default value from interface definition
+            #$wires->wire_get("$p","inst_name");
+            my $i_type=$wires->wire_get($p,"i_type");
+            my $i_name= $wires->wire_get($p,"i_name");
+            my $i_num=$wires->wire_get($p,"i_num");
+            my $i_port=$wires->wire_get($p,"i_port");
+            my $new_range=$wires->wire_get($p,"range");
+            my ($range,$type,$connect,$default_out) = 
+                ($i_type eq "socket" )? $intfc->get_port_info_of_socket($i_name,$i_port):
+                $intfc->get_port_info_of_plug($i_name,$i_port);
+            #""Active high","Don't care"
+            my $default=(!defined $default_out          )? port_width_repeat($new_range,"1\'bx"):
+                        ($default_out eq 'Active low' )? port_width_repeat($new_range,"1\'b0"):
+                        ($default_out eq 'Active high')? port_width_repeat($new_range,"1\'b1"):
+                        ($default_out eq 'Don\'t care')? port_width_repeat($new_range,"1\'bx"): $default_out;
+            $unused_wire_v= (defined $unused_wire_v)? "$unused_wire_v \tassign ${p} = $default;\n" : "\tassign ${p} = $default;\n";
+        }
+    }
+    $unused_wire_v="\n//Take the default value for ports that defined by interfaces but did not assigned to any wires.\n $unused_wire_v\n\n" if(defined $unused_wire_v);
+    return $unused_wire_v;
 }
 
-
-
-
 sub gen_soc_instance_v{
-	my ($soc,$soc_name,$param_pass_v,$txview)=@_;
-	
-	my $processor_en=0;
-	my $altera_jtag_ctrl=0;
-	my $xilinx_jtag_ctrl=0; #if it becomes larger than 0 then add jtag to wb module 
-	my $jtag_insts="";
-	my $xilinx_jtag_ctrl_in;
-	my $xilinx_jtag_ctrl_out;
-	my $rpin = "1\'b0";
-	my $clkpin;
-	my $soc_v="
-	// Allow software to remote reset/enable the cpu via jtag
-	wire jtag_cpu_en, jtag_system_reset;
+    my ($soc,$soc_name,$param_pass_v,$txview)=@_;
+    my $processor_en=0;
+    my $altera_jtag_ctrl=0;
+    my $xilinx_jtag_ctrl=0; #if it becomes larger than 0 then add jtag to wb module
+    my $jtag_insts="";
+    my $xilinx_jtag_ctrl_in;
+    my $xilinx_jtag_ctrl_out;
+    my $rpin = "1\'b0";
+    my $clkpin;
+    my $soc_v="
+    // Allow software to remote reset/enable the cpu via jtag
+    wire jtag_cpu_en, jtag_system_reset;
 ";
-
-	my $mm="$soc_name #(\n $param_pass_v \n\t)the_${soc_name}(\n";
-	my $top=$soc->soc_get_top();
-	my @intfcs=$top->top_get_intfc_list();
-	my $i=0;	
-	my $ss="";
-	my $ww="";
-	
-	my $jtag_inst_name="";
-	
-	foreach my $intfc (@intfcs){	
-		
-		#reset
-		if( $intfc eq 'plug:reset[0]'){
-			my @ports=$top->top_get_intfc_ports_list($intfc);
-			foreach my $p (@ports){
-				my($id,$range,$type,$intfc_name,$intfc_port)= $top->top_get_port($p);
-				$mm="$mm," if ($i);	
-				$mm="$mm\n\t\t.$p(${p}_ored_jtag)";
-				$ss="$ss\tassign ${p}_ored_jtag = (jtag_system_reset | $p);\n";
-				$ww="$ww\twire ${p}_ored_jtag;\n";
-				$rpin = $p;
-				$i=1;		
-				
-			}			
-		}
-		
-		#enable
-		elsif( $intfc eq 'plug:enable[0]'){
-			my @ports=$top->top_get_intfc_ports_list($intfc);
-			foreach my $p (@ports){
-				my($id,$range,$type,$intfc_name,$intfc_port)= $top->top_get_port($p);
-				$mm="$mm," if ($i);		
-				$mm="$mm\n\t\t.$p(${p}_anded_jtag)";
-				$ss="$ss\tassign ${p}_anded_jtag= (jtag_cpu_en & $p);\n";
-				$ww="$ww\twire ${p}_anded_jtag;\n";
-				$processor_en=1;
-				$i=1;		
-				
-			}		
-		}
-		
-		#RxD_sim
-		elsif( $intfc eq 'socket:RxD_sim[0]'){
-			#This interface is for simulation only donot include it in top module			
-			my @ports=$top->top_get_intfc_ports_list($intfc);
-			foreach my $p (@ports){
-				$mm="$mm," if ($i);		
-				$mm="$mm\n\t\t.$p( )";
-				$i=1;
-			}			
-		}
-		
-		
-		#jtag_to_wb	
-		elsif( $intfc =~ /socket:jtag_to_wb\[/){ #check JTAG connect parameter. if it is XILINX then connect it to jtag tap
-			my @ports=$top->top_get_intfc_ports_list($intfc);
-			foreach my $p (@ports){
-				my($id,$range,$type,$intfc_name,$intfc_port)= $top->top_get_port($p);
-				
-				
-				my $JTAG_CONNECT=remove_all_white_spaces($soc->soc_get_module_param_value ($id,'JTAG_CONNECT'));
-				
-				#print "$inst,$range,$type,$intfc_name,$intfc_port-> $JTAG_CONNECT;";
-				if($JTAG_CONNECT eq '"XILINX_JTAG_WB"'){
-					$jtag_inst_name= $soc->soc_get_instance_name($id);
-				
-					
-					my %params	= $soc->soc_get_module_param($id);
-					my $new_range = add_instantc_name_to_parameters(\%params,$id,$range);
-					$ww="$ww\twire [ $new_range ] ${p};\n";
-					
-					$mm="$mm," if ($i);		
-					$mm="$mm\n\t\t.$p($p)";	
-					if($type eq 'input'){
-						$jtag_insts=$jtag_insts."$id XILINX JTAG,";
-						$xilinx_jtag_ctrl++;
-						$xilinx_jtag_ctrl_in=(defined $xilinx_jtag_ctrl_in)? "$xilinx_jtag_ctrl_in,$p" : "$p";
-					}else {
-						$xilinx_jtag_ctrl_out=(defined $xilinx_jtag_ctrl_out)? "$xilinx_jtag_ctrl_out,$p" : "$p";
-					}
-					
-					
-				}else{#Dont not connect 
-					$mm="$mm," if ($i);		
-					$mm="$mm\n\t\t.$p( )";
-				}
-			
-				if($JTAG_CONNECT =~ /ALTERA_JTAG_WB/){
-					
-					if($type eq 'input'){
-						$jtag_insts=$jtag_insts."$id ALTERA JTAG,";
-						$altera_jtag_ctrl++;
-										
-					}
-				}	
-				$i=1;	
-			}		
-		
-		}
-		
-		
-		
-		else {
-		#other interface
-			my @ports=$top->top_get_intfc_ports_list($intfc);
-			foreach my $p (@ports){
-			my($inst,$range,$type,$intfc_name,$intfc_port)= $top->top_get_port($p);	
-			$clkpin=$p if( $intfc eq 'plug:clk[0]');		
-			$mm="$mm," if ($i);		
-			$mm="$mm\n\t\t.$p($p)";	
-			$i=1;	
-				
-			}				
-		}			
-		
-	}
-	$mm="$mm\n\t);";
-	add_text_to_string(\$soc_v,"$ww\n");
-	add_text_to_string(\$soc_v,"$mm\n");
-	add_text_to_string(\$soc_v,"$ss\n");
-
-	
-	if($altera_jtag_ctrl>0 && $xilinx_jtag_ctrl>0 ){
-		add_colored_info($txview,"Found JTAG comminication ports from differnt FPGA vendors:$jtag_insts. ",'red');			
-		
-	}elsif ($xilinx_jtag_ctrl>0){
-		$xilinx_jtag_ctrl_in  ="{$xilinx_jtag_ctrl_in}"  if($xilinx_jtag_ctrl != 1); 
-		$xilinx_jtag_ctrl_out ="{$xilinx_jtag_ctrl_out}" if($xilinx_jtag_ctrl != 1); 
-		
-		$soc_v = $soc_v."
-	xilinx_jtag_wb  #(
-		.JWB_NUM($xilinx_jtag_ctrl),
-		.JDw(${jtag_inst_name}_JDw),
-    	.JAw(${jtag_inst_name}_JAw)		
-	)jwb(
-		
-		.reset($rpin),
-		.cpu_en(jtag_cpu_en),
-		.system_reset(jtag_system_reset),
-		.wb_to_jtag_all($xilinx_jtag_ctrl_out),
-		.jtag_to_wb_all($xilinx_jtag_ctrl_in)
-	);		
-		
+    my $mm="$soc_name #(\n $param_pass_v \n\t)the_${soc_name}(\n";
+    my $top=$soc->soc_get_top();
+    my @intfcs=$top->top_get_intfc_list();
+    my $i=0;
+    my $ss="";
+    my $ww="";
+    my $jtag_inst_name="";
+    foreach my $intfc (@intfcs){
+        #reset
+        if( $intfc eq 'plug:reset[0]'){
+            my @ports=$top->top_get_intfc_ports_list($intfc);
+            foreach my $p (@ports){
+                my($id,$range,$type,$intfc_name,$intfc_port)= $top->top_get_port($p);
+                $mm="$mm," if ($i);
+                $mm="$mm\n\t\t.$p(${p}_ored_jtag)";
+                $ss="$ss\tassign ${p}_ored_jtag = (jtag_system_reset | $p);\n";
+                $ww="$ww\twire ${p}_ored_jtag;\n";
+                $rpin = $p;
+                $i=1;
+            }
+        }
+        #enable
+        elsif( $intfc eq 'plug:enable[0]'){
+            my @ports=$top->top_get_intfc_ports_list($intfc);
+            foreach my $p (@ports){
+                my($id,$range,$type,$intfc_name,$intfc_port)= $top->top_get_port($p);
+                $mm="$mm," if ($i);
+                $mm="$mm\n\t\t.$p(${p}_anded_jtag)";
+                $ss="$ss\tassign ${p}_anded_jtag= (jtag_cpu_en & $p);\n";
+                $ww="$ww\twire ${p}_anded_jtag;\n";
+                $processor_en=1;
+                $i=1;
+            }
+        }
+        #RxD_sim
+        elsif( $intfc eq 'socket:RxD_sim[0]'){
+            #This interface is for simulation only donot include it in top module
+            my @ports=$top->top_get_intfc_ports_list($intfc);
+            foreach my $p (@ports){
+                $mm="$mm," if ($i);
+                $mm="$mm\n\t\t.$p( )";
+                $i=1;
+            }
+        }
+        #jtag_to_wb
+        elsif( $intfc =~ /socket:jtag_to_wb\[/){ #check JTAG connect parameter. if it is XILINX then connect it to jtag tap
+            my @ports=$top->top_get_intfc_ports_list($intfc);
+            foreach my $p (@ports){
+                my($id,$range,$type,$intfc_name,$intfc_port)= $top->top_get_port($p);
+                my $JTAG_CONNECT=remove_all_white_spaces($soc->soc_get_module_param_value ($id,'JTAG_CONNECT'));
+                #print "$inst,$range,$type,$intfc_name,$intfc_port-> $JTAG_CONNECT;";
+                if($JTAG_CONNECT eq '"XILINX_JTAG_WB"'){
+                    $jtag_inst_name= $soc->soc_get_instance_name($id);
+                    my %params    = $soc->soc_get_module_param($id);
+                    my $new_range = add_instantc_name_to_parameters(\%params,$id,$range);
+                    $ww="$ww\twire [ $new_range ] ${p};\n";
+                    $mm="$mm," if ($i);
+                    $mm="$mm\n\t\t.$p($p)";
+                    if($type eq 'input'){
+                        $jtag_insts=$jtag_insts."$id XILINX JTAG,";
+                        $xilinx_jtag_ctrl++;
+                        $xilinx_jtag_ctrl_in=(defined $xilinx_jtag_ctrl_in)? "$xilinx_jtag_ctrl_in,$p" : "$p";
+                    }else {
+                        $xilinx_jtag_ctrl_out=(defined $xilinx_jtag_ctrl_out)? "$xilinx_jtag_ctrl_out,$p" : "$p";
+                    }
+                }else{#Dont not connect
+                    $mm="$mm," if ($i);
+                    $mm="$mm\n\t\t.$p( )";
+                }
+                if($JTAG_CONNECT =~ /ALTERA_JTAG_WB/){
+                    if($type eq 'input'){
+                        $jtag_insts=$jtag_insts."$id ALTERA JTAG,";
+                        $altera_jtag_ctrl++;
+                    }
+                }
+                $i=1;
+            }
+        }
+        else {
+        #other interface
+            my @ports=$top->top_get_intfc_ports_list($intfc);
+            foreach my $p (@ports){
+            my($inst,$range,$type,$intfc_name,$intfc_port)= $top->top_get_port($p);
+            $clkpin=$p if( $intfc eq 'plug:clk[0]');
+            $mm="$mm," if ($i);
+            $mm="$mm\n\t\t.$p($p)";
+            $i=1;
+            }
+        }
+    }
+    $mm="$mm\n\t);";
+    add_text_to_string(\$soc_v,"$ww\n");
+    add_text_to_string(\$soc_v,"$mm\n");
+    add_text_to_string(\$soc_v,"$ss\n");
+    if($altera_jtag_ctrl>0 && $xilinx_jtag_ctrl>0 ){
+        add_colored_info($txview,"Found JTAG comminication ports from differnt FPGA vendors:$jtag_insts. ",'red');
+    }elsif ($xilinx_jtag_ctrl>0){
+        $xilinx_jtag_ctrl_in  ="{$xilinx_jtag_ctrl_in}"  if($xilinx_jtag_ctrl != 1);
+        $xilinx_jtag_ctrl_out ="{$xilinx_jtag_ctrl_out}" if($xilinx_jtag_ctrl != 1);
+        $soc_v = $soc_v."
+    xilinx_jtag_wb  #(
+        .JWB_NUM($xilinx_jtag_ctrl),
+        .JDw(${jtag_inst_name}_JDw),
+        .JAw(${jtag_inst_name}_JAw)
+    )jwb(
+        .reset($rpin),
+        .cpu_en(jtag_cpu_en),
+        .system_reset(jtag_system_reset),
+        .wb_to_jtag_all($xilinx_jtag_ctrl_out),
+        .jtag_to_wb_all($xilinx_jtag_ctrl_in)
+    );
 ";
-		
-	}elsif($altera_jtag_ctrl>0) {
-$soc_v = $soc_v."		
-	jtag_system_en jtag_en (
-		.cpu_en(jtag_cpu_en),
-		.system_reset(jtag_system_reset)
-	
-	);	
-";		
-		
-	}else{
+    }elsif($altera_jtag_ctrl>0) {
 $soc_v = $soc_v."
-    //No jtag connection has found in the design	
-	assign jtag_cpu_en=1\'b0;
-	assign jtag_system_reset=1'b0;	
+    jtag_system_en jtag_en (
+        .cpu_en(jtag_cpu_en),
+        .system_reset(jtag_system_reset)
+    );
 ";
-	}
-		
-	$soc_v=$soc_v."\n endmodule\n";	
-	return $soc_v;
-
+    }else{
+$soc_v = $soc_v."
+    //No jtag connection has found in the design
+    assign jtag_cpu_en=1\'b0;
+    assign jtag_system_reset=1'b0;
+";
+    }
+    $soc_v=$soc_v."\n endmodule\n";
+    return $soc_v;
 }
 
-
-
-
-
 sub gen_soc_instance_v_no_modfy{
-	my ($soc,$soc_name,$param_pass_v)=@_;
-	my $soc_v;
-	my $processor_en=0;
-	
-
-	my $mm="$soc_name #(\n $param_pass_v \n\t)the_${soc_name}(\n";
-
-	my $top=$soc->soc_get_top();
-	my @intfcs=$top->top_get_intfc_list();
-	
-	my $i=0;
-
-	
-	
-	
-	my $ss="";
-	my $ww="";
-	
-	foreach my $intfc (@intfcs){
-	
-		
-		
-	
-		
-			my @ports=$top->top_get_intfc_ports_list($intfc);
-			foreach my $p (@ports){
-			my($inst,$range,$type,$intfc_name,$intfc_port)= $top->top_get_port($p);			
-			$mm="$mm," if ($i);	
-			if( $intfc =~ /socket:jtag_to_wb\[/){#dont include jtag connection
-				$mm="$mm\n\t\t.$p( )";
-			}else{	
-				$mm="$mm\n\t\t.$p($p)";
-			}	
-			$i=1;	
-				
-			
-		}	
-		
-		
-	}
-	$mm="$mm\n\t);";
-	add_text_to_string(\$soc_v,"$ww\n");
-	add_text_to_string(\$soc_v,"$mm\n");
-	add_text_to_string(\$soc_v,"$ss\n");
-	add_text_to_string(\$soc_v,"\n endmodule\n");	
-	
-	
-	
-	return $soc_v;
-
+    my ($soc,$soc_name,$param_pass_v)=@_;
+    my $soc_v;
+    my $processor_en=0;
+    my $mm="$soc_name #(\n $param_pass_v \n\t)the_${soc_name}(\n";
+    my $top=$soc->soc_get_top();
+    my @intfcs=$top->top_get_intfc_list();
+    my $i=0;
+    my $ss="";
+    my $ww="";
+    foreach my $intfc (@intfcs){
+            my @ports=$top->top_get_intfc_ports_list($intfc);
+            foreach my $p (@ports){
+            my($inst,$range,$type,$intfc_name,$intfc_port)= $top->top_get_port($p);
+            $mm="$mm," if ($i);
+            if( $intfc =~ /socket:jtag_to_wb\[/){#dont include jtag connection
+                $mm="$mm\n\t\t.$p( )";
+            }else{
+                $mm="$mm\n\t\t.$p($p)";
+            }
+            $i=1;
+        }
+    }
+    $mm="$mm\n\t);";
+    add_text_to_string(\$soc_v,"$ww\n");
+    add_text_to_string(\$soc_v,"$mm\n");
+    add_text_to_string(\$soc_v,"$ss\n");
+    add_text_to_string(\$soc_v,"\n endmodule\n");
+    return $soc_v;
 }
 
-
-
-
-
-
-
-
 sub gen_system_info {
-	my ($soc,$param)=@_;
-	my ($wb_slaves,$wb_masters,$other,$jtag);	
-	#my (@newbase,@newend,@connects);
-	
-
-   $jtag='';
-
-	my @all_instances=$soc->soc_get_all_instances();
-
-my %jtagwb; my %ram;
-	
-	
-	foreach my $instance_id (@all_instances){
-		my $category=$soc->soc_get_category($instance_id);
-		
-		my @plugs= $soc->soc_get_all_plugs_of_an_instance($instance_id);
-		foreach my $plug (@plugs){
-			my @nums=$soc->soc_list_plug_nums($instance_id,$plug);
-			foreach my $num (@nums){
-				my ($addr,$base,$end,$name,$connect_id,$connect_socket,$connect_socket_num)=$soc->soc_get_plug($instance_id,$plug,$num);
-									
-				my $instance_name=$soc->soc_get_instance_name($instance_id);
-				my $connect_name=$soc->soc_get_instance_name($connect_id);
-				#get interfaces
-				if((defined $connect_socket) && ($connect_socket eq 'wb_slave')){	
-					
-					$base=sprintf("0x%08x", $base);
-					$end=sprintf("0x%08x", $end);					
-					add_text_to_string(\$wb_slaves, "\t$instance_name, $name, $connect_name, $base, $end\n");	
-					if ($category eq 'RAM') {
-						$ram{$instance_id}{'base'}=$base;
-						$ram{$instance_id}{'end'}=$end;
-						$ram{$instance_id}{'connect'}=$connect_id;
-					}			
-					
-				}#if
-				elsif((defined $connect_socket) && ($connect_socket eq 'wb_master')){
-					add_text_to_string(\$wb_masters,"\t$instance_name, $name, $connect_name\n");
-				}
-				elsif(defined $connect_socket) {
-					add_text_to_string(\$other,"\t$instance_name, $name, $connect_name\n");
-
-				}
-				# get jtag_wbs
-				if((defined $connect_socket) && ($connect_socket eq 'wb_master') && ($instance_id =~ /jtag_wb/)){						
-					my $index=$soc->soc_get_module_param_value($instance_id,'JTAG_INDEX');
-					my $chain=$soc->soc_get_module_param_value($instance_id,'JTAG_CHAIN');
-					my $vendor_connect =$soc->soc_get_module_param_value($instance_id,'JTAG_CONNECT');
-					add_text_to_string(\$jtag, "\t$instance_name,  $connect_name, $index\n");
-					
-					$jtagwb{$connect_id}{'index'}=$index;	
-					$jtagwb{$connect_id}{'chain'}=$chain;	
-					$jtagwb{$connect_id}{'vendor_connect'}=$vendor_connect;
-				}
-
-
-			}#foreach my $num
-		}#foreach my $plug
-	}#foreach my $instance_id
-
-	#Generate memory programming command
+    my ($soc,$param)=@_;
+    my ($wb_slaves,$wb_masters,$other,$jtag);
+    #my (@newbase,@newend,@connects);
+    $jtag='';
+    my @all_instances=$soc->soc_get_all_instances();
+    my %jtagwb; my %ram;
+    foreach my $instance_id (@all_instances){
+        my $category=$soc->soc_get_category($instance_id);
+        my @plugs= $soc->soc_get_all_plugs_of_an_instance($instance_id);
+        foreach my $plug (@plugs){
+            my @nums=$soc->soc_list_plug_nums($instance_id,$plug);
+            foreach my $num (@nums){
+                my ($addr,$base,$end,$name,$connect_id,$connect_socket,$connect_socket_num)=$soc->soc_get_plug($instance_id,$plug,$num);
+                my $instance_name=$soc->soc_get_instance_name($instance_id);
+                my $connect_name=$soc->soc_get_instance_name($connect_id);
+                #get interfaces
+                if((defined $connect_socket) && ($connect_socket eq 'wb_slave')){
+                    $base=sprintf("0x%08x", $base);
+                    $end=sprintf("0x%08x", $end);
+                    add_text_to_string(\$wb_slaves, "\t$instance_name, $name, $connect_name, $base, $end\n");
+                    if ($category eq 'RAM') {
+                        $ram{$instance_id}{'base'}=$base;
+                        $ram{$instance_id}{'end'}=$end;
+                        $ram{$instance_id}{'connect'}=$connect_id;
+                    }
+                }#if
+                elsif((defined $connect_socket) && ($connect_socket eq 'wb_master')){
+                    add_text_to_string(\$wb_masters,"\t$instance_name, $name, $connect_name\n");
+                }
+                elsif(defined $connect_socket) {
+                    add_text_to_string(\$other,"\t$instance_name, $name, $connect_name\n");
+                }
+                # get jtag_wbs
+                if((defined $connect_socket) && ($connect_socket eq 'wb_master') && ($instance_id =~ /jtag_wb/)){
+                    my $index=$soc->soc_get_module_param_value($instance_id,'JTAG_INDEX');
+                    my $chain=$soc->soc_get_module_param_value($instance_id,'JTAG_CHAIN');
+                    my $vendor_connect =$soc->soc_get_module_param_value($instance_id,'JTAG_CONNECT');
+                    add_text_to_string(\$jtag, "\t$instance_name,  $connect_name, $index\n");
+                    $jtagwb{$connect_id}{'index'}=$index;
+                    $jtagwb{$connect_id}{'chain'}=$chain;
+                    $jtagwb{$connect_id}{'vendor_connect'}=$vendor_connect;
+                }
+            }#foreach my $num
+        }#foreach my $plug
+    }#foreach my $instance_id
+    #Generate memory programming command
 my $prog='#!/bin/bash
-
 #JTAG_INTFC="$PRONOC_WORK/toolchain/bin/JTAG_INTFC"
 source ./jtag_intfc.sh
-
 ';
-
-
-	foreach my $instance_id (@all_instances){
-		my $category=$soc->soc_get_category($instance_id);
-		if ($category eq 'RAM') {
-		
-			my $jtag_connect=$soc->soc_get_module_param_value($instance_id,'JTAG_CONNECT');
-			$jtag_connect=remove_all_white_spaces($jtag_connect);
-			my $aw=$soc->soc_get_module_param_value($instance_id,'Aw');
-			my $dw=$soc->soc_get_module_param_value($instance_id,'Dw');
-			my $JTAG_INDEX=$soc->soc_get_module_param_value($instance_id,'JTAG_INDEX');
-			my $JTAG_CHAIN=$soc->soc_get_module_param_value($instance_id,'JTAG_CHAIN');
-			
-			#check if jtag_index is a parameter
-			my $v=$soc->soc_get_module_param_value($instance_id,$JTAG_INDEX);
-			$JTAG_INDEX = $v if (defined $v);
-			$v= $soc->object_get_attribute('global_param',$JTAG_INDEX);
-			$JTAG_INDEX = $v if (defined $v);
-			
-			my $BINFILE=$soc->soc_get_module_param_value($instance_id,'JTAG_MEM_FILE');
-			($BINFILE)=$BINFILE=~ /"([^"]*)"/ if(defined $BINFILE);
-			$BINFILE=(defined $BINFILE) ? "./RAM/".$BINFILE.'.bin' : './RAM/ram0.bin';
-			
-			my $OFSSET="0x00000000";
-			my $end=((1 << $aw)*($dw/8))-1;
-			my $BOUNDRY=sprintf("0x%08x", $end);			
-			if($jtag_connect =~ /ALTERA_JTAG_WB/ ) {
-				$prog= "$prog \$JTAG_INTFC -n $JTAG_INDEX -s \"$OFSSET\" -e \"$BOUNDRY\" -i  \"$BINFILE\" -c";
-				#print "prog= $prog\n";
-				
-			} elsif ($jtag_connect =~ /XILINX_JTAG_WB/){
-				$prog= "$prog \$JTAG_INTFC -t $JTAG_CHAIN -n $JTAG_INDEX -s \"$OFSSET\" -e \"$BOUNDRY\" -i  \"$BINFILE\" -c";
-				
-			}
-			
-			elsif ($jtag_connect eq 'ALTERA_IMCE'){
-				#TODO add later
-				$prog= "$prog ".'>&2 echo'." \"ALTERA_IMCE runtime programming is not supported yet for programming  $instance_id\"\n";	
-				
-			} else{
-				#check if its connected to jtag_wb via the bus
-				my 	$connect_id = $ram{$instance_id}{'connect'};
-				my $OFSSET = $ram{$instance_id}{'base'};
-				my $BOUNDRY = $ram{$instance_id}{'end'};
-				if(defined $connect_id){
-					#print "id=$connect_id\n";
-					my $JTAG_INDEX= $jtagwb{$connect_id}{'index'};
-					my $JTAG_CHAIN= $jtagwb{$connect_id}{'chain'};
-					my $JTAG_VENDOR= $jtagwb{$connect_id}{'vendor_connect'}; 
-					
-					my $t="";
-					$t="-t $JTAG_CHAIN"if($JTAG_VENDOR =~ /XILINX_JTAG_WB/);
-					
-					if(defined $JTAG_INDEX){
-							$v= $soc->object_get_attribute('global_param',$JTAG_INDEX);
-							$JTAG_INDEX = $v if (defined $v);
-							$prog= "$prog  \$JTAG_INTFC $t -n $JTAG_INDEX -s \"$OFSSET\" -e \"$BOUNDRY\" -i  \"$BINFILE\" -c";
-							#print "prog= $prog\n";
-							
-					}else{
-						$prog= "$prog".'>&2 echo'." \"JTAG runtime programming is not enabled in  $instance_id\"\n";	
-					
-					}
-					
-				}else{
-					$prog= "$prog".'>&2 echo'."\"JTAG runtime programming is not enabled in  $instance_id\"\n";	
-					
-				}
-			}
-			
-			
-		}	
-	
-		
-	}
-
-
-my $lisence= get_license_header("readme"); 
-my $warning=autogen_warning();
-
-
-$wb_slaves = " \t\t NOTE: No wishbone slaves interface has been found in the design " if (!defined $wb_slaves);
-$wb_masters= " \t\t NOTE: No wishbone master interface has been found in the design " if (!defined $wb_masters);
-
-my $readme="
+    foreach my $instance_id (@all_instances){
+        my $category=$soc->soc_get_category($instance_id);
+        if ($category eq 'RAM') {
+            my $jtag_connect=$soc->soc_get_module_param_value($instance_id,'JTAG_CONNECT');
+            $jtag_connect=remove_all_white_spaces($jtag_connect);
+            my $aw=$soc->soc_get_module_param_value($instance_id,'Aw');
+            my $dw=$soc->soc_get_module_param_value($instance_id,'Dw');
+            my $JTAG_INDEX=$soc->soc_get_module_param_value($instance_id,'JTAG_INDEX');
+            my $JTAG_CHAIN=$soc->soc_get_module_param_value($instance_id,'JTAG_CHAIN');
+            #check if jtag_index is a parameter
+            my $v=$soc->soc_get_module_param_value($instance_id,$JTAG_INDEX);
+            $JTAG_INDEX = $v if (defined $v);
+            $v= $soc->object_get_attribute('global_param',$JTAG_INDEX);
+            $JTAG_INDEX = $v if (defined $v);
+            my $BINFILE=$soc->soc_get_module_param_value($instance_id,'JTAG_MEM_FILE');
+            ($BINFILE)=$BINFILE=~ /"([^"]*)"/ if(defined $BINFILE);
+            $BINFILE=(defined $BINFILE) ? "./RAM/".$BINFILE.'.bin' : './RAM/ram0.bin';
+            my $OFSSET="0x00000000";
+            my $end=((1 << $aw)*($dw/8))-1;
+            my $BOUNDRY=sprintf("0x%08x", $end);
+            if($jtag_connect =~ /ALTERA_JTAG_WB/ ) {
+                $prog= "$prog \$JTAG_INTFC -n $JTAG_INDEX -s \"$OFSSET\" -e \"$BOUNDRY\" -i  \"$BINFILE\" -c";
+                #print "prog= $prog\n";
+            } elsif ($jtag_connect =~ /XILINX_JTAG_WB/){
+                $prog= "$prog \$JTAG_INTFC -t $JTAG_CHAIN -n $JTAG_INDEX -s \"$OFSSET\" -e \"$BOUNDRY\" -i  \"$BINFILE\" -c";
+            }
+            elsif ($jtag_connect eq 'ALTERA_IMCE'){
+                #TODO add later
+                $prog= "$prog ".'>&2 echo'." \"ALTERA_IMCE runtime programming is not supported yet for programming  $instance_id\"\n";
+            } else{
+                #check if its connected to jtag_wb via the bus
+                my     $connect_id = $ram{$instance_id}{'connect'};
+                my $OFSSET = $ram{$instance_id}{'base'};
+                my $BOUNDRY = $ram{$instance_id}{'end'};
+                if(defined $connect_id){
+                    #print "id=$connect_id\n";
+                    my $JTAG_INDEX= $jtagwb{$connect_id}{'index'};
+                    my $JTAG_CHAIN= $jtagwb{$connect_id}{'chain'};
+                    my $JTAG_VENDOR= $jtagwb{$connect_id}{'vendor_connect'};
+                    my $t="";
+                    $t="-t $JTAG_CHAIN"if($JTAG_VENDOR =~ /XILINX_JTAG_WB/);
+                    if(defined $JTAG_INDEX){
+                            $v= $soc->object_get_attribute('global_param',$JTAG_INDEX);
+                            $JTAG_INDEX = $v if (defined $v);
+                            $prog= "$prog  \$JTAG_INTFC $t -n $JTAG_INDEX -s \"$OFSSET\" -e \"$BOUNDRY\" -i  \"$BINFILE\" -c";
+                            #print "prog= $prog\n";
+                    }else{
+                        $prog= "$prog".'>&2 echo'." \"JTAG runtime programming is not enabled in  $instance_id\"\n";
+                    }
+                }else{
+                    $prog= "$prog".'>&2 echo'."\"JTAG runtime programming is not enabled in  $instance_id\"\n";
+                }
+            }
+        }
+    }
+    my $lisence= get_license_header("readme");
+    my $warning=autogen_warning();
+    $wb_slaves = " \t\t NOTE: No wishbone slaves interface has been found in the design " if (!defined $wb_slaves);
+    $wb_masters= " \t\t NOTE: No wishbone master interface has been found in the design " if (!defined $wb_masters);
+    my $readme="
 $warning
 $lisence
-
 ***********************
-**	Program the memories
+**    Program the memories
 ***********************
-
-If the memory core and jtag_wb are connected to the same wishbone bus, you can program the memory using 
-
-	bash program.sh  
-
-
-
+If the memory core and jtag_wb are connected to the same wishbone bus, you can program the memory using
+    bash program.sh
 ***************************
-**	soc parameters
+**    soc parameters
 ***************************
-
 $param
-
 ****************************
-**	wishbone bus(es)  info
+**    wishbone bus(es)  info
 ****************************
-	#slave interfaces:
-	#instance name,  interface name, connected to, base address, boundary address 	
+    #slave interfaces:
+    #instance name,  interface name, connected to, base address, boundary address
 $wb_slaves
-
-	#master interfaces:
-	#instance name,  interface name, connected to
+    #master interfaces:
+    #instance name,  interface name, connected to
 $wb_masters
-
 ****************************
-**	Jtag to wishbone interface (jtag_wb) info:
+**    Jtag to wishbone interface (jtag_wb) info:
 ****************************
-
-	#instance name, instance name,  JTAG_INDEX
+    #instance name, instance name,  JTAG_INDEX
 $jtag
-
-
 ";
-
-
-
-
-	return ($readme,$prog);
-	
-	
-	
-}	
-
-
+    return ($readme,$prog);
+}
 
 ######################
 #   soc_generate_verilog
 #####################
-
-sub soc_generate_verilator{ 
-	my ($soc,$sw_path,$name,$params_ref)= @_;
-	my $soc_name=$soc->object_get_attribute('soc_name');
-	my $top_ip=ip_gen->top_gen_new();
-	if(!defined $soc_name){$soc_name='soc'};
-	
-	my @instances=$soc->soc_get_all_instances();
-	my $io_sim_v;
-	my $top_io_short_all;
-	my $core_id= $soc->object_get_attribute('global_param','CORE_ID');
-	$core_id= 0 if(!defined $core_id);
-	my $param_as_in_v_all="\tparameter\tCORE_ID=$core_id,
+sub soc_generate_verilator{
+    my ($soc,$sw_path,$name,$params_ref)= @_;
+    my $soc_name=$soc->object_get_attribute('soc_name');
+    my $top_ip=ip_gen->top_gen_new();
+    if(!defined $soc_name){$soc_name='soc'};
+    my @instances=$soc->soc_get_all_instances();
+    my $io_sim_v;
+    my $top_io_short_all;
+    my $core_id= $soc->object_get_attribute('global_param','CORE_ID');
+    $core_id= 0 if(!defined $core_id);
+    my $param_as_in_v_all="\tparameter\tCORE_ID=$core_id,
 \tparameter\tSW_LOC=\"$sw_path\"\n,";
-
-	my $param_pass_v_all="\t\t.CORE_ID(CORE_ID),\n\t\t.SW_LOC(SW_LOC)";
-	my $body_v;
-	
-	my ($param_v_all, $local_param_v_all, $wire_def_v_all, $inst_v_all, $plugs_assign_v_all, $sockets_assign_v_all,$io_full_v_all,$top_io_full_all,$system_v_all);
-	my ($src_io_full_all,$src_io_short_all);
-	my $wires=soc->new_wires();
-	my $intfc=interface->interface_new();
-	
-	
-	foreach my $id (@instances){
-		my ($param_v, $local_param_v, $wire_def_v, $inst_v, $plugs_assign_v, $sockets_assign_v,$io_full_v,$io_top_full_v,$io_sim_v,
-		$top_io_short,$param_as_in_v,$param_pass_v,$system_v,$assigned_ports,$top_io_pass,$src_io_short, $src_io_full)=gen_module_inst($id,$soc,$top_ip,$intfc,$wires,1);
-		my $inst   	= $soc->soc_get_instance_name($id);
-		add_text_to_string(\$body_v,"/*******************\n*\n*\t$inst\n*\n*\n*********************/\n");
-		add_text_to_string(\$param_as_in_v_all,",\n$param_as_in_v")   	if(defined ($param_as_in_v)); 
-		add_text_to_string(\$local_param_v_all,"$local_param_v\n")   	if(defined($local_param_v)); 
-		add_text_to_string(\$param_pass_v_all,",\n$param_pass_v")       if(defined($param_pass_v));
-		add_text_to_string(\$wire_def_v_all,"$wire_def_v\n")		 	if(defined($wire_def_v));
-		add_text_to_string(\$inst_v_all,$inst_v)					 	if(defined($inst_v));
-		add_text_to_string(\$plugs_assign_v_all,"$plugs_assign_v\n") 	if(defined($plugs_assign_v));
-		add_text_to_string(\$sockets_assign_v_all,"$sockets_assign_v\n")if(defined($sockets_assign_v));
-		add_text_to_string(\$io_full_v_all,"$io_full_v\n")				if(length($io_full_v)>3);
-		add_text_to_string(\$top_io_full_all,"$io_top_full_v\n")		if(length($io_top_full_v)>3);
-		add_text_to_string(\$src_io_full_all,"$src_io_full\n")			if(length($src_io_full)>3);
-	
-		$top_io_short_all = (defined $top_io_short_all)? "$top_io_short_all,\n$top_io_short" : $top_io_short 		if(defined($top_io_short));		
-		$src_io_short_all = (defined $src_io_short_all)? "$src_io_short_all,\n$src_io_short" : $src_io_short 		if(defined($src_io_short));		
-		#print  "$param_v $local_param_v $wire_def_v $inst_v $plugs_assign_v $sockets_assign_v $io_full_v";
-			
-	}	
-	
-	
-		
-	my ($addr_map,$addr_localparam,$module_addr_localparam)= generate_address_cmp($soc,$wires);
-
-	#add functions
-	my $dir = Cwd::getcwd();
-	open my $file1, "<", "$dir/lib/verilog/functions.v" or die;
-	my $functions_all='';
-	while (my $f1 = readline ($file1)) {	
-		 $functions_all="$functions_all $f1 ";
-	}
-	close($file1);
-	my $unused_wiers_v=assign_unconnected_wires($wires,$intfc);
-		
-	
-	$soc->object_add_attribute('top_ip',undef,$top_ip);
-	#print @assigned_wires;
-
-	#generate topmodule
-	my $params_v="
+    my $param_pass_v_all="\t\t.CORE_ID(CORE_ID),\n\t\t.SW_LOC(SW_LOC)";
+    my $body_v;
+    my ($param_v_all, $local_param_v_all, $wire_def_v_all, $inst_v_all, $plugs_assign_v_all, $sockets_assign_v_all,$io_full_v_all,$top_io_full_all,$system_v_all);
+    my ($src_io_full_all,$src_io_short_all);
+    my $wires=soc->new_wires();
+    my $intfc=interface->interface_new();
+    foreach my $id (@instances){
+        my ($param_v, $local_param_v, $wire_def_v, $inst_v, $plugs_assign_v, $sockets_assign_v,$io_full_v,$io_top_full_v,$io_sim_v,
+        $top_io_short,$param_as_in_v,$param_pass_v,$system_v,$assigned_ports,$top_io_pass,$src_io_short, $src_io_full)=gen_module_inst($id,$soc,$top_ip,$intfc,$wires,1);
+        my $inst       = $soc->soc_get_instance_name($id);
+        add_text_to_string(\$body_v,"/*******************\n*\n*\t$inst\n*\n*\n*********************/\n");
+        add_text_to_string(\$param_as_in_v_all,",\n$param_as_in_v")       if(defined ($param_as_in_v));
+        add_text_to_string(\$local_param_v_all,"$local_param_v\n")       if(defined($local_param_v));
+        add_text_to_string(\$param_pass_v_all,",\n$param_pass_v")       if(defined($param_pass_v));
+        add_text_to_string(\$wire_def_v_all,"$wire_def_v\n")             if(defined($wire_def_v));
+        add_text_to_string(\$inst_v_all,$inst_v)                         if(defined($inst_v));
+        add_text_to_string(\$plugs_assign_v_all,"$plugs_assign_v\n")     if(defined($plugs_assign_v));
+        add_text_to_string(\$sockets_assign_v_all,"$sockets_assign_v\n")if(defined($sockets_assign_v));
+        add_text_to_string(\$io_full_v_all,"$io_full_v\n")                if(length($io_full_v)>3);
+        add_text_to_string(\$top_io_full_all,"$io_top_full_v\n")        if(length($io_top_full_v)>3);
+        add_text_to_string(\$src_io_full_all,"$src_io_full\n")            if(length($src_io_full)>3);
+        $top_io_short_all = (defined $top_io_short_all)? "$top_io_short_all,\n$top_io_short" : $top_io_short         if(defined($top_io_short));
+        $src_io_short_all = (defined $src_io_short_all)? "$src_io_short_all,\n$src_io_short" : $src_io_short         if(defined($src_io_short));
+        #print  "$param_v $local_param_v $wire_def_v $inst_v $plugs_assign_v $sockets_assign_v $io_full_v";
+    }
+    my ($addr_map,$addr_localparam,$module_addr_localparam)= generate_address_cmp($soc,$wires);
+    #add functions
+    my $dir = Cwd::getcwd();
+    open my $file1, "<", "$dir/lib/verilog/functions.v" or die;
+    my $functions_all='';
+    while (my $f1 = readline ($file1)) {
+        $functions_all="$functions_all $f1 ";
+    }
+    close($file1);
+    my $unused_wiers_v=assign_unconnected_wires($wires,$intfc);
+    $soc->object_add_attribute('top_ip',undef,$top_ip);
+    #print @assigned_wires;
+    #generate topmodule
+    my $params_v="
 \tparameter\tCORE_ID=$core_id;
 \tparameter\tSW_LOC=\"$sw_path\";\n";
-	
-	
-	my %all_param=soc_get_all_parameters($soc);
-	my @order= soc_get_all_parameters_order($soc);		
-	
-	
-	
-	#replace global parameters
-	my @list=sort keys%{$params_ref};
-	foreach my $p (@list){
-		 my %hash=%{$params_ref}; 
-		 $all_param{$p}= $hash{$p};
-	}
-	
-	foreach my $p (@order){
-		add_text_to_string(\$params_v,"\tlocalparam  $p = $all_param{$p};\n") if(defined $all_param{$p} );			
-	}
-	
-  
-	$top_io_short_all=(defined $top_io_short_all)? "$top_io_short_all,\n$src_io_short_all" : $src_io_short_all;
-	$top_io_full_all=$top_io_full_all."\n$src_io_full_all";            
-  #  $top_io_pass_all=$top_io_pass_all.",\n$clk_assigned_port";	
-	
-	my $has_ni =check_for_ni($soc);
-    my $import = ($has_ni)? "\n\t`NOC_CONF\n" : ""; 
-	
-	my $verilator_v =  "
+    my %all_param=soc_get_all_parameters($soc);
+    my @order= soc_get_all_parameters_order($soc);
+    #replace global parameters
+    my @list=sort keys%{$params_ref};
+    foreach my $p (@list){
+        my %hash=%{$params_ref};
+        $all_param{$p}= $hash{$p};
+    }
+    foreach my $p (@order){
+        add_text_to_string(\$params_v,"\tlocalparam  $p = $all_param{$p};\n") if(defined $all_param{$p} );
+    }
+    $top_io_short_all=(defined $top_io_short_all)? "$top_io_short_all,\n$src_io_short_all" : $src_io_short_all;
+    $top_io_full_all=$top_io_full_all."\n$src_io_full_all";
+    #  $top_io_pass_all=$top_io_pass_all.",\n$clk_assigned_port";
+    my $has_ni =check_for_ni($soc);
+    my $import = ($has_ni)? "\n\timport pronoc_pkg::*;\n" : "";
+    my $verilator_v =  "
 /*********************
-		${name}
+        ${name}
 *********************/
-	
 module ${name}  (\n $top_io_short_all\n);\n  $import \n";
-	my $ins= gen_soc_instance_v_no_modfy($soc,$soc_name,$param_pass_v_all);
+    my $ins= gen_soc_instance_v_no_modfy($soc,$soc_name,$param_pass_v_all);
 $verilator_v.="
-$functions_all	
+$functions_all
 /* verilator lint_off WIDTH */
 $params_v
 /* verilator lint_on WIDTH */
 $top_io_full_all
 $ins
 ";
-	my ($readme,$prog)=gen_system_info($soc,$param_as_in_v_all); 
-	return ($verilator_v);
-
-
-}	
-
+    my ($readme,$prog)=gen_system_info($soc,$param_as_in_v_all);
+    return ($verilator_v);
+}
 
 sub get_golal_param_v{
-	my $project_dir	  = get_project_dir(); #mpsoc dir addr
-	my $paths_file= "$project_dir/mpsoc/perl_gui/lib/glob_params";
-	my $paramv='';
-	if (-f 	$paths_file ){
-		my $self= do $paths_file;
-		my @parameters = object_get_attribute_order($self,'Parameters');
-		foreach my $p (@parameters) {
-			my $v =object_get_attribute($self,'Parameters',$p);
-			$paramv.="\t localparam  $p = $v;\n" if(defined $v);	
-		}
-	}
-	return $paramv;
+    my $project_dir      = get_project_dir(); #mpsoc dir addr
+    my $paths_file= "$project_dir/mpsoc/perl_gui/lib/glob_params";
+    my $paramv='';
+    if (-f     $paths_file ){
+        my $self= do $paths_file;
+        my @parameters = object_get_attribute_order($self,'Parameters');
+        foreach my $p (@parameters) {
+            my $v =object_get_attribute($self,'Parameters',$p);
+            $paramv.="\t localparam  $p = $v;\n" if(defined $v);
+        }
+    }
+    return $paramv;
 }
-
-
-
-
-1;
-
-
+1;
\ No newline at end of file
diff --git a/mpsoc/perl_gui/lib/perl/widget.pl b/mpsoc/perl_gui/lib/perl/widget.pl
index 7201cdc..89c7992 100755
--- a/mpsoc/perl_gui/lib/perl/widget.pl
+++ b/mpsoc/perl_gui/lib/perl/widget.pl
@@ -12,17 +12,9 @@ BEGIN
     $module->import;
 }
 
-
-
 if(Consts::GTK_VERSION==2){
-	require "widget2.pl"; 
+    require "widget2.pl"; 
 }else{
-	require "widget3.pl";
+    require "widget3.pl";
 }
-
-
-
-
-
-
 1;
diff --git a/mpsoc/perl_gui/lib/perl/widget2.pl b/mpsoc/perl_gui/lib/perl/widget2.pl
index ce90f2b..fb8c72f 100755
--- a/mpsoc/perl_gui/lib/perl/widget2.pl
+++ b/mpsoc/perl_gui/lib/perl/widget2.pl
@@ -2,418 +2,355 @@
 #use Gtk2 '-init';
 use strict;
 use warnings;
-
 use Data::Dumper;
 use Gtk2::SourceView2;
 use Consts;
-
-require "common.pl"; 
-
+require "common.pl";
 use FindBin;
 use lib $FindBin::Bin;
 use IO::CaptureOutput qw(capture qxx qxy);
-
 use ColorButton;
 use HexSpin2;
-
-
 use Gtk2::Pango;
-#use Tk::Animation;
 
+#use Tk::Animation;
 our %glob_setting;
 
-
 ##############
 # combo box
 #############
 sub gen_combo{
-	my ($combo_list, $combo_active_pos)= @_;
-	my $combo = Gtk2::ComboBox->new_text;
-	
-	combo_set_names($combo,$combo_list);
-	$combo->set_active($combo_active_pos) if(defined $combo_active_pos);
-	
-	#my $font = Gtk2::Pango::FontDescription->from_string('Tahoma 5');
-	#$combo->modify_font($font);
-
-	
-	return $combo;	
+    my ($combo_list, $combo_active_pos)= @_;
+    my $combo = Gtk2::ComboBox->new_text;
+    combo_set_names($combo,$combo_list);
+    $combo->set_active($combo_active_pos) if(defined $combo_active_pos);
+    #my $font = Gtk2::Pango::FontDescription->from_string('Tahoma 5');
+    #$combo->modify_font($font);
+    return $combo;
 }
 
-
 sub combo_set_names {
-	my ( $combo, $list_ref ) = @_;
-	my @list=@{$list_ref};
-	#print "$list[0]\n";
-	for my $item (@list){$combo->append_text($item);}
+    my ( $combo, $list_ref ) = @_;
+    my @list=@{$list_ref};
+    #print "$list[0]\n";
+    for my $item (@list){$combo->append_text($item);}
 }
 
-
 sub gen_combo_help {
-	my ($help, @combo_list, $pos)= @_;
-	my $box = def_hbox(FALSE, 0);
-	my $combo= gen_combo(@combo_list, $pos);
-	my $button=def_image_button("icons/help.png");
-		
-	$button->signal_connect("clicked" => sub {message_dialog($help);});
-			
-	$box->pack_start( $combo, FALSE, FALSE, 3);
-	$box->pack_start( $button, FALSE, FALSE, 3);
-	$box->show_all;
-	
-	return ($box,$combo);
-}
-
-	
+    my ($help, @combo_list, $pos)= @_;
+    my $box = def_hbox(FALSE, 0);
+    my $combo= gen_combo(@combo_list, $pos);
+    my $button=def_image_button("icons/help.png");
+    $button->signal_connect("clicked" => sub {message_dialog($help);});
+    $box->pack_start( $combo, FALSE, FALSE, 3);
+    $box->pack_start( $button, FALSE, FALSE, 3);
+    $box->show_all;
+    return ($box,$combo);
+}
+
 sub def_h_labeled_combo{
-		my ($label_name,$combo_list,$combo_active_pos)=@_;
-		my $box = def_hbox(TRUE,0);
-		my $label= gen_label_in_left($label_name);	
-		my $combo= gen_combo($combo_list, $combo_active_pos);
-		$box->pack_start( $label, FALSE, FALSE, 3);
-		$box->pack_start( $combo, FALSE, TRUE, 3);
-		return ($box,$combo);
-}	
+        my ($label_name,$combo_list,$combo_active_pos)=@_;
+        my $box = def_hbox(TRUE,0);
+        my $label= gen_label_in_left($label_name);
+        my $combo= gen_combo($combo_list, $combo_active_pos);
+        $box->pack_start( $label, FALSE, FALSE, 3);
+        $box->pack_start( $combo, FALSE, TRUE, 3);
+        return ($box,$combo);
+}
 
 sub def_h_labeled_combo_scaled{
-		my ($label_name,$combo_list,$combo_active_pos,$label_w,$comb_w)=@_;
-		my $table= def_table(1,3,TRUE);
-		my $label= gen_label_in_left($label_name);	
-		my $combo= gen_combo($combo_list, $combo_active_pos);
-		$table->attach_defaults ($label, 0, $label_w, 0, 1);
-		$table->attach_defaults ($combo, 1, $label_w+$comb_w, 0, 1);
-		return ($table,$combo);
-}	
-
+        my ($label_name,$combo_list,$combo_active_pos,$label_w,$comb_w)=@_;
+        my $table= def_table(1,3,TRUE);
+        my $label= gen_label_in_left($label_name);
+        my $combo= gen_combo($combo_list, $combo_active_pos);
+        $table->attach_defaults ($label, 0, $label_w, 0, 1);
+        $table->attach_defaults ($combo, 1, $label_w+$comb_w, 0, 1);
+        return ($table,$combo);
+}
 
 sub gen_combo_model{
-	my $ref=shift;
-	my %inputs=%{$ref};
-	my $store = Gtk2::TreeStore->new('Glib::String');
-  	 for my $i (sort { $a cmp $b} keys %inputs ) {
-    	 	my $iter = $store->append(undef);
-		
-    	 	$store->set($iter, 0, $i);
-    		for my $capital (sort { $a cmp $b} keys %{$inputs{$i}}) {
-      			my $iter2 = $store->append($iter);
-       			$store->set($iter2, 0, $capital);
-    		}
- 	}
-	return $store;
-
+    my $ref=shift;
+    my %inputs=%{$ref};
+    my $store = Gtk2::TreeStore->new('Glib::String');
+        for my $i (sort { $a cmp $b} keys %inputs ) {
+            my $iter = $store->append(undef);
+            $store->set($iter, 0, $i);
+            for my $capital (sort { $a cmp $b} keys %{$inputs{$i}}) {
+                my $iter2 = $store->append($iter);
+                $store->set($iter2, 0, $capital);
+            }
+    }
+    return $store;
 }
 
 sub gen_tree_combo{
-	my $model=shift;
-	my $combo = Gtk2::ComboBox->new_with_model($model);
-   	my $renderer = Gtk2::CellRendererText->new();
-    	$combo->pack_start($renderer, TRUE);
-    	$combo->set_attributes($renderer, "text", 0);
-    	$combo->set_cell_data_func($renderer, \&is_capital_sensitive);
-	return $combo;
-
+    my $model=shift;
+    my $combo = Gtk2::ComboBox->new_with_model($model);
+    my $renderer = Gtk2::CellRendererText->new();
+    $combo->pack_start($renderer, TRUE);
+    $combo->set_attributes($renderer, "text", 0);
+    $combo->set_cell_data_func($renderer, \&is_capital_sensitive);
+    return $combo;
 }
 
-
 sub TreePath_new_from_indices {
-	 my @indices =@_;
-	 my $path = Gtk2::TreePath->new_from_indices(@indices);
-	 return $path;
-
+    my @indices =@_;
+    my $path = Gtk2::TreePath->new_from_indices(@indices);
+    return $path;
 }
 
-
 ##############
 # spin button
 #############
 sub gen_spin{
-	my ($min,$max,$step,$digit)= @_;
-	
-	return Gtk2::SpinButton->new_with_range ($min, $max, $step);
-	 if(!defined $digit){
-		my $d1 = get_float_precision($min);
-		my $d2 = get_float_precision($max);
-		my $d3 = get_float_precision($step);
-		$digit = ($d1 >$d2)? $d1 : $d2;
-		$digit = $d3 if($d3>$digit);				
-	}
-	print "($min,$max,$step,$digit)\n";	
-	return Gtk2::SpinButton->new_with_range ($min, $max, $step) if($digit ==0);
-    return gen_spin_float($min,$max,$step,$digit);	
+    my ($min,$max,$step,$digit)= @_;
+    return Gtk2::SpinButton->new_with_range ($min, $max, $step);
+     if(!defined $digit){
+        my $d1 = get_float_precision($min);
+        my $d2 = get_float_precision($max);
+        my $d3 = get_float_precision($step);
+        $digit = ($d1 >$d2)? $d1 : $d2;
+        $digit = $d3 if($d3>$digit);
+    }
+    print "($min,$max,$step,$digit)\n";
+    return Gtk2::SpinButton->new_with_range ($min, $max, $step) if($digit ==0);
+    return gen_spin_float($min,$max,$step,$digit);
 }
 
 sub get_float_precision{
-	my $num=shift; 
-	my $digit = length(($num =~ /\.(.*)/)[0]);
-	$digit=0 if(!defined $digit);
-	return $digit;
+    my $num=shift;
+    my $digit = length(($num =~ /\.(.*)/)[0]);
+    $digit=0 if(!defined $digit);
+    return $digit;
 }
 
 sub gen_spin_float{
-	my ($min,$max,$step,$digit)= @_;
-	#$page_inc = ($max - $min)/ 
-	my $adj = Gtk2::Adjustment->new (0, $min, $max, $step,3.1, 0);	
-	my $spinner = Gtk2::SpinButton->new ($adj, 1.0,$digit);
-	return $spinner; 
+    my ($min,$max,$step,$digit)= @_;
+    #$page_inc = ($max - $min)/
+    my $adj = Gtk2::Adjustment->new (0, $min, $max, $step,3.1, 0);
+    my $spinner = Gtk2::SpinButton->new ($adj, 1.0,$digit);
+    return $spinner;
 }
 
-
 sub gen_spin_help {
-	my ($help, $min,$max,$step,$digit)= @_;
-	my $box = def_hbox(FALSE, 0);
-	my $spin= gen_spin($min,$max,$step,$digit);
-	my $button=def_image_button("icons/help.png");
-		
-	$button->signal_connect("clicked" => sub {message_dialog($help);});
-			
-	$box->pack_start( $spin, FALSE, FALSE, 3);
-	$box->pack_start( $button, FALSE, FALSE, 3);
-	$box->show_all;
-	
-	return ($box,$spin);
+    my ($help, $min,$max,$step,$digit)= @_;
+    my $box = def_hbox(FALSE, 0);
+    my $spin= gen_spin($min,$max,$step,$digit);
+    my $button=def_image_button("icons/help.png");
+    $button->signal_connect("clicked" => sub {message_dialog($help);});
+    $box->pack_start( $spin, FALSE, FALSE, 3);
+    $box->pack_start( $button, FALSE, FALSE, 3);
+    $box->show_all;
+    return ($box,$spin);
 }
 
-
 #############
 #  entry
 #############
 sub gen_entry{
-	my ($initial) = @_;
-	my $entry = Gtk2::Entry->new;
-	if(defined $initial){ $entry->set_text($initial)};
-	return $entry;
+    my ($initial) = @_;
+    my $entry = Gtk2::Entry->new;
+    if(defined $initial){ $entry->set_text($initial)};
+    return $entry;
 }
 
-
 sub gen_entry_new_with_max_length{
-	my ($n,$initial) = @_;
-	my $entry = Gtk2::Entry->new_with_max_length ($n);
-	if(defined $initial){ $entry->set_text($initial)};
-	return $entry;
+    my ($n,$initial) = @_;
+    my $entry = Gtk2::Entry->new_with_max_length ($n);
+    if(defined $initial){ $entry->set_text($initial)};
+    return $entry;
 }
 
-
-
 sub gen_entry_help{
-	my ($help, $init)= @_;
-	my $box = def_hbox(FALSE, 0);
-	my $entry= gen_entry ($init);
-	my $button=def_image_button("icons/help.png");
-		
-	$button->signal_connect("clicked" => sub {message_dialog($help);});
-			
-	$box->pack_start( $entry, FALSE, FALSE, 3);
-	$box->pack_start( $button, FALSE, FALSE, 3);
-	$box->show_all;
-	
-	return ($box,$entry);
+    my ($help, $init)= @_;
+    my $box = def_hbox(FALSE, 0);
+    my $entry= gen_entry ($init);
+    my $button=def_image_button("icons/help.png");
+    $button->signal_connect("clicked" => sub {message_dialog($help);});
+    $box->pack_start( $entry, FALSE, FALSE, 3);
+    $box->pack_start( $button, FALSE, FALSE, 3);
+    $box->show_all;
+    return ($box,$entry);
 }
 
 sub def_h_labeled_entry{
-	my ($label_name,$initial)=@_;
-	my $box = def_hbox(TRUE,0);
-	my $label= gen_label_in_left($label_name);	
-	my $entry =gen_entry($initial);
-	$box->pack_start( $label, FALSE, FALSE, 3);
-	$box->pack_start( $entry, FALSE, FALSE, 3);
-	return ($box,$entry);
-	
+    my ($label_name,$initial)=@_;
+    my $box = def_hbox(TRUE,0);
+    my $label= gen_label_in_left($label_name);
+    my $entry =gen_entry($initial);
+    $box->pack_start( $label, FALSE, FALSE, 3);
+    $box->pack_start( $entry, FALSE, FALSE, 3);
+    return ($box,$entry);
 }
 
 sub def_h_labeled_entry_help{
-	my ($help,$label_name,$initial)=@_;
-	my $box = def_hbox(TRUE,0);
-	my $label= gen_label_in_left($label_name);	
-	my ($b,$entry) =gen_entry_help($help,$initial);
-	$box->pack_start( $label, FALSE, FALSE, 3);
-	$box->pack_start( $b, FALSE, FALSE, 3);
-	return ($box,$entry);
-	
-}			
-
+    my ($help,$label_name,$initial)=@_;
+    my $box = def_hbox(TRUE,0);
+    my $label= gen_label_in_left($label_name);
+    my ($b,$entry) =gen_entry_help($help,$initial);
+    $box->pack_start( $label, FALSE, FALSE, 3);
+    $box->pack_start( $b, FALSE, FALSE, 3);
+    return ($box,$entry);
+}
 
 ##############
 # ComboBoxEntry
 ##############
-
 sub gen_combo_entry{
-	my ($list_ref,$pos)=@_;
-	my @list=@{$list_ref};	
-
-	my $combo_box_entry = Gtk2::ComboBoxEntry->new_text;
-	foreach my $p (@list){
-		$combo_box_entry->append_text($p);
-	}
-	$pos=0 if(! defined $pos ); 
-	$combo_box_entry->set_active($pos);
-	return $combo_box_entry;
+    my ($list_ref,$pos)=@_;
+    my @list=@{$list_ref};
+    my $combo_box_entry = Gtk2::ComboBoxEntry->new_text;
+    foreach my $p (@list){
+        $combo_box_entry->append_text($p);
+    }
+    $pos=0 if(! defined $pos );
+    $combo_box_entry->set_active($pos);
+    return $combo_box_entry;
 }
 
-
 sub combo_entry_get_chiled{
-	my $combentry =shift;
-    	return 	$combentry->child;
+    my $combentry =shift;
+        return     $combentry->child;
 }
 
-
-
-
 sub update_combo_entry_content {
-	my ($self,$content,$pos)=@_;
-	my @combo_list=split(/\s*,\s*/,$content) if(defined $content);
-	foreach my $p (@combo_list){
-		$self->append_text($p);
-	}
-	$pos=0 if(! defined $pos ); 
-	$self->set_active($pos);	
+    my ($self,$content,$pos)=@_;
+    my @combo_list=split(/\s*,\s*/,$content) if(defined $content);
+    foreach my $p (@combo_list){
+        $self->append_text($p);
+    }
+    $pos=0 if(! defined $pos );
+    $self->set_active($pos);
 }
 
 ###########
 # checkbutton
 ###########
-
 sub def_h_labeled_checkbutton{
-	my ($label_name)=@_;
-	my $box = def_hbox(TRUE,0);
-	my $label= gen_label_in_left($label_name) if (defined $label_name);	
-	my $check= Gtk2::CheckButton->new;
-	#if($status==1) $check->
-	$box->pack_start( $label, FALSE, FALSE, 3) if (defined $label_name);	
-	$box->pack_start( $check, FALSE, FALSE, 3);
-	return ($box,$check);
-	
-}	
+    my ($label_name)=@_;
+    my $box = def_hbox(TRUE,0);
+    my $label= gen_label_in_left($label_name) if (defined $label_name);
+    my $check= Gtk2::CheckButton->new;
+    #if($status==1) $check->
+    $box->pack_start( $label, FALSE, FALSE, 3) if (defined $label_name);
+    $box->pack_start( $check, FALSE, FALSE, 3);
+    return ($box,$check);
+}
 
 sub gen_checkbutton{
-	my $label=shift;
-	return Gtk2::CheckButton->new($label) if (defined $label);
-	return Gtk2::CheckButton->new;
+    my $label=shift;
+    return Gtk2::CheckButton->new($label) if (defined $label);
+    return Gtk2::CheckButton->new;
 }
 
-
 #############
 #  label
 ############
-
 sub gen_label_in_left{
-	my ($data)=@_;
-	my $label   = Gtk2::Label->new($data);
-	$label->set_alignment( 0, 0.5 );
-	#my $font = Gtk2::Pango::FontDescription->from_string('Tahoma 5');
-	#$label->modify_font($font);
-	return $label;
+    my ($data)=@_;
+    my $label   = Gtk2::Label->new($data);
+    $label->set_alignment( 0, 0.5 );
+    #my $font = Gtk2::Pango::FontDescription->from_string('Tahoma 5');
+    #$label->modify_font($font);
+    return $label;
 }
 
-
 sub gen_label_in_center{
-	my ($data)=@_;
-	my $label   = Gtk2::Label->new($data);
-	return $label;
+    my ($data)=@_;
+    my $label   = Gtk2::Label->new($data);
+    return $label;
 }
 
 sub def_label{
-	my @data=@_;
-	my $label   = Gtk2::Label->new(@data);
-	$label->set_alignment( 0, 0.5 );
-	return $label;
-
+    my @data=@_;
+    my $label   = Gtk2::Label->new(@data);
+    $label->set_alignment( 0, 0.5 );
+    return $label;
 }
 
-
 sub box_label{
-	my( $homogeneous, $spacing, $name)=@_;
-	my $box=def_hbox($homogeneous, $spacing);
-	my $label= def_label($name);	
-	$box->pack_start( $label, FALSE, FALSE, 3);
-	return $box;
+    my( $homogeneous, $spacing, $name)=@_;
+    my $box=def_hbox($homogeneous, $spacing);
+    my $label= def_label($name);
+    $box->pack_start( $label, FALSE, FALSE, 3);
+    return $box;
 }
 
-
 sub def_title_box{
-	my( $homogeneous, $spacing, @labels)=@_;
-	my $box=def_hbox($homogeneous, $spacing);
-	foreach my $label (@labels){
-		my $labelbox=box_label($homogeneous, $spacing, $label);
-		$box->pack_start( $labelbox, FALSE, FALSE, 3);
-	}
-	return $box;
-}	
-
-
-sub gen_label_help {	
-	my ($help, $label_name)= @_;
-	my $box = def_hbox(FALSE, 0);
-	my $label= gen_label_in_left($label_name);
-	my $button=def_image_button("icons/help.png");
-	$button->signal_connect("clicked" => sub {message_dialog($help);});
-	$box->pack_start( $label, FALSE, FALSE, 0);
-	$box->pack_start( $button, FALSE, FALSE, 0);
-	$box->set_spacing (0);
-	$box->show_all;
-	return $box;
+    my( $homogeneous, $spacing, @labels)=@_;
+    my $box=def_hbox($homogeneous, $spacing);
+    foreach my $label (@labels){
+        my $labelbox=box_label($homogeneous, $spacing, $label);
+        $box->pack_start( $labelbox, FALSE, FALSE, 3);
+    }
+    return $box;
 }
 
-sub gen_label_with_mnemonic {
-	my $name=shift;
-	Gtk2::Label->new_with_mnemonic($name);
+sub gen_label_help {
+    my ($help, $label_name)= @_;
+    my $box = def_hbox(FALSE, 0);
+    my $label= gen_label_in_left($label_name);
+    my $button=def_image_button("icons/help.png");
+    $button->signal_connect("clicked" => sub {message_dialog($help);});
+    $box->pack_start( $label, FALSE, FALSE, 0);
+    $box->pack_start( $button, FALSE, FALSE, 0);
+    $box->set_spacing (0);
+    $box->show_all;
+    return $box;
+}
 
+sub gen_label_with_mnemonic {
+    my $name=shift;
+    Gtk2::Label->new_with_mnemonic($name);
 }
-	
+
 ##############
 # button
 #############
-
 sub button_box{
 # create a new button
-	my $label=@_;
-	my $button = Gtk2::Button->new_from_stock($label);
-	my $box=def_hbox(TRUE,5);
-	$box->pack_start($button,   FALSE, FALSE,0);
-	
-	return ($box,$button);
-
+    my $label=@_;
+    my $button = Gtk2::Button->new_from_stock($label);
+    my $box=def_hbox(TRUE,5);
+    $box->pack_start($button,   FALSE, FALSE,0);
+    return ($box,$button);
 }
 
-
 sub get_icon_pixbuff{
     my $icon_file=shift;
-	my $size;
+    my $size;
     if ($glob_setting{'ICON_SIZE'} eq 'default'){
-   		my $font_size=get_defualt_font_size();
-		$size=($font_size *2.5);
+        my $font_size=get_defualt_font_size();
+        $size=($font_size *2.5);
     }else{
-    	$size = int ($glob_setting{'ICON_SIZE'});
+        $size = int ($glob_setting{'ICON_SIZE'});
     }
-	my $pixbuf = Gtk2::Gdk::Pixbuf->new_from_file_at_scale($icon_file,$size,$size,FALSE);
-	return $pixbuf;
+    my $pixbuf = Gtk2::Gdk::Pixbuf->new_from_file_at_scale($icon_file,$size,$size,FALSE);
+    return $pixbuf;
 }
 
-
- 
 sub def_icon{
-	my $icon_file=shift;
-	return Gtk2::Image->new_from_pixbuf(get_icon_pixbuff($icon_file));
+    my $icon_file=shift;
+    return Gtk2::Image->new_from_pixbuf(get_icon_pixbuff($icon_file));
 }
 
 sub call_gtk_drag_finish{
-	my ($context,$a,$b,$time)=@_;
-	$context->finish (0, 0, $time);	
+    my ($context,$a,$b,$time)=@_;
+    $context->finish (0, 0, $time);
 }
 
-
-
 sub add_drag_dest_set{
-	my ($widget,$a,$b,$c) = @_;
-	#Create a target table to receive drops
-	my @target_table = (
+    my ($widget,$a,$b,$c) = @_;
+    #Create a target table to receive drops
+    my @target_table = (
         {'target' => $a,       'flags' => $b, 'info' => $c  },
-	);
-	$widget->drag_dest_set('all', ['copy'], @target_table);
+    );
+    $widget->drag_dest_set('all', ['copy'], @target_table);
 }
 
 sub add_drag_source {
-	my ($widget,$a,$b,$c) = @_;
-	$widget->drag_source_set (
+    my ($widget,$a,$b,$c) = @_;
+    $widget->drag_source_set (
                                 ['button1_mask', 'button3_mask'],
                                 ['copy'],
                                 {
@@ -425,1254 +362,1050 @@ sub add_drag_source {
 }
 
 sub drag_set_icon_pixbuf {
-	my ($icon_view,$icon_pixbuf)=@_;	
-	$icon_view->drag_source_set_icon_pixbuf ($icon_pixbuf);
+    my ($icon_view,$icon_pixbuf)=@_;
+    $icon_view->drag_source_set_icon_pixbuf ($icon_pixbuf);
 }
 
 sub gen_iconview {
-	my ($tree_model,$marc_col,$pix_con)=@_;
-	my $icon_view = Gtk2::IconView->new_with_model($tree_model);
+    my ($tree_model,$marc_col,$pix_con)=@_;
+    my $icon_view = Gtk2::IconView->new_with_model($tree_model);
     $icon_view->set_markup_column($marc_col);
     $icon_view->set_pixbuf_column($pix_con);
-	return $icon_view;
+    return $icon_view;
 }
 
-
 sub add_frame_to_image{
-	my $image=shift;
-	my $align = Gtk2::Alignment->new (0.5, 0.5, 0, 0);
-   	my $frame = Gtk2::Frame->new;
-	$frame->set_shadow_type ('in');
-	# Animation
-	$frame->add ($image);
-	$align->add ($frame);
-	return $align;
+    my $image=shift;
+    my $align = Gtk2::Alignment->new (0.5, 0.5, 0, 0);
+    my $frame = Gtk2::Frame->new;
+    $frame->set_shadow_type ('in');
+    # Animation
+    $frame->add ($image);
+    $align->add ($frame);
+    return $align;
 }
 
 sub gen_frame {
-	return  Gtk2::Frame->new;
+    return  Gtk2::Frame->new;
 }
 
-
-
 sub new_image_from_file{
-	return  Gtk2::Image->new_from_file (@_);
+    return  Gtk2::Image->new_from_file (@_);
 }
 
-
 sub gen_pixbuf{
-	my $file=shift;
-	return Gtk2::Gdk::Pixbuf->new_from_file($file);	
+    my $file=shift;
+    return Gtk2::Gdk::Pixbuf->new_from_file($file);
 }
 
 sub open_image{
-	my ($image_file,$x,$y,$unit)=@_;
-	if(defined $unit){
-		my($width,$hight)=max_win_size();
-		if($unit eq 'percent'){
-			$x= ($x * $width)/100;
-			$y= ($y * $hight)/100;
-		} # else its pixels
-			
-	}
-	$image_file ="icons/blank.png"  unless(-f $image_file);
-	my $pixbuf = Gtk2::Gdk::Pixbuf->new_from_file_at_scale($image_file,$x,$y,TRUE);
- 	my $image = Gtk2::Image->new_from_pixbuf($pixbuf);
-	return $image;
+    my ($image_file,$x,$y,$unit)=@_;
+    if(defined $unit){
+        my($width,$hight)=max_win_size();
+        if($unit eq 'percent'){
+            $x= ($x * $width)/100;
+            $y= ($y * $hight)/100;
+        } # else its pixels
+    }
+    $image_file ="icons/blank.png"  unless(-f $image_file);
+    my $pixbuf = Gtk2::Gdk::Pixbuf->new_from_file_at_scale($image_file,$x,$y,TRUE);
+    my $image = Gtk2::Image->new_from_pixbuf($pixbuf);
+    return $image;
 }
 
 sub open_inline_image{
-	my ($image_string,$x,$y,$unit)=@_;
-	if(defined $unit){
-		my($width,$hight)=max_win_size();
-		if($unit eq 'percent'){
-			$x= ($x * $width)/100;
-			$y= ($y * $hight)/100;
-		} # else its pixels
-			
-	}
-	my $pixbuf = do {
+    my ($image_string,$x,$y,$unit)=@_;
+    if(defined $unit){
+        my($width,$hight)=max_win_size();
+        if($unit eq 'percent'){
+            $x= ($x * $width)/100;
+            $y= ($y * $hight)/100;
+        } # else its pixels
+    }
+    my $pixbuf = do {
         my $loader = Gtk2::Gdk::PixbufLoader->new();
         $loader->set_size(  $x,$y ) if (defined $y);
-        $loader->write(  $image_string );        
+        $loader->write(  $image_string );
         $loader->close();
         $loader->get_pixbuf();
     };
-	
-
- 	my $image = Gtk2::Image->new_from_pixbuf($pixbuf);
- 	 
-	return $image;
+    my $image = Gtk2::Image->new_from_pixbuf($pixbuf);
+    return $image;
 }
 
 sub find_icon{
-	my $file =shift;
-	return $file if(-f $file); #called from perl_gui
-	return "../../$file"; #called from lib/perl 		
+    my $file =shift;
+    return $file if(-f $file); #called from perl_gui
+    return "../../$file"; #called from lib/perl
 }
 
 sub def_image_button{
-	my ($image_file, $label_text, $homogeneous, $mnemonic)=@_;
-	# create box for image and label 
-	$homogeneous = FALSE if(!defined $homogeneous);
-	my $box = def_hbox($homogeneous,0);
-	my $image; 
-	$image_file = find_icon( $image_file);
-	$image = def_icon($image_file) if(-f $image_file); 
-	
-	# now on to the image stuff
-	#my $image = Gtk2::Image->new_from_file($image_file);
-	$box->pack_start($image, FALSE, FALSE, 0) if(defined  $image);
-	$box->set_border_width(0);
-	$box->set_spacing (0);
-	# Create a label for the button
-	if(defined $label_text ) {
-		my $label;
-		$label = Gtk2::Label->new("  $label_text") unless (defined $mnemonic);
-		$label = Gtk2::Label->new_with_mnemonic (" $label_text") if (defined $mnemonic);
-		$box->pack_start($label, FALSE, FALSE, 0);
-	}	
-	
-	my $button = Gtk2::Button->new();
-	$button->add($box);
-	$button->set_border_width(0);
-	$button->show_all;
-	return $button;
+    my ($image_file, $label_text, $homogeneous, $mnemonic)=@_;
+    # create box for image and label
+    $homogeneous = FALSE if(!defined $homogeneous);
+    my $box = def_hbox($homogeneous,0);
+    my $image;
+    $image_file = find_icon( $image_file);
+    $image = def_icon($image_file) if(-f $image_file);
+    # now on to the image stuff
+    #my $image = Gtk2::Image->new_from_file($image_file);
+    $box->pack_start($image, FALSE, FALSE, 0) if(defined  $image);
+    $box->set_border_width(0);
+    $box->set_spacing (0);
+    # Create a label for the button
+    if(defined $label_text ) {
+        my $label;
+        $label = Gtk2::Label->new("  $label_text") unless (defined $mnemonic);
+        $label = Gtk2::Label->new_with_mnemonic (" $label_text") if (defined $mnemonic);
+        $box->pack_start($label, FALSE, FALSE, 0);
+    }
+    my $button = Gtk2::Button->new();
+    $button->add($box);
+    $button->set_border_width(0);
+    $button->show_all;
+    return $button;
 }
 
 sub def_button{
-	my ($label_text)=@_;
-	my $label = Gtk2::Label->new("$label_text") if (defined $label_text);
-	my $button= Gtk2::Button->new();
-	$button->add($label) if (defined $label_text);
-	return $button;
-}	
-
+    my ($label_text)=@_;
+    my $label = Gtk2::Label->new("$label_text") if (defined $label_text);
+    my $button= Gtk2::Button->new();
+    $button->add($label) if (defined $label_text);
+    return $button;
+}
 
 sub def_image_label{
-	my ($image_file, $label_text,$mnemonic)=@_;
-	# create box for image and label 
-	my $box = def_hbox(FALSE,1);
-	# now on to the image stuff
-	my $image = def_icon($image_file);
-	$box->pack_start($image, TRUE, FALSE, 0);
-	# Create a label for the button
-	if(defined $label_text ) {
-		my $label; 
-		$label = Gtk2::Label->new("  $label_text") unless (defined $mnemonic);
-		$label = Gtk2::Label->new_with_mnemonic (" $label_text") if (defined $mnemonic);
-		$box->pack_start($label, TRUE, FALSE, 0);
-	}	
-		
-	return $box;
-
+    my ($image_file, $label_text,$mnemonic)=@_;
+    # create box for image and label
+    my $box = def_hbox(FALSE,1);
+    # now on to the image stuff
+    my $image = def_icon($image_file);
+    $box->pack_start($image, TRUE, FALSE, 0);
+    # Create a label for the button
+    if(defined $label_text ) {
+        my $label;
+        $label = Gtk2::Label->new("  $label_text") unless (defined $mnemonic);
+        $label = Gtk2::Label->new_with_mnemonic (" $label_text") if (defined $mnemonic);
+        $box->pack_start($label, TRUE, FALSE, 0);
+    }
+    return $box;
 }
 
-
-sub gen_button_message {	
-	my ($help, $image_file,$label_name)= @_;
-	my $box = def_hbox(FALSE, 0);
-	my $label= gen_label_in_center($label_name) if(defined $label_name);
-	my $button=def_image_button($image_file);
-		
-	if(defined $help ){$button->signal_connect("clicked" => sub {message_dialog($help);});}
-			
-	$box->pack_start( $label, FALSE, FALSE, 0) if(defined $label_name);
-	$box->pack_start( $button, FALSE, FALSE, 0);
-	$box->set_border_width(0);
-	$box->set_spacing (0);
-	$box->show_all;
-	
-	return $box;
-
-
+sub gen_button_message {
+    my ($help, $image_file,$label_name)= @_;
+    my $box = def_hbox(FALSE, 0);
+    my $label= gen_label_in_center($label_name) if(defined $label_name);
+    my $button=def_image_button($image_file);
+    if(defined $help ){$button->signal_connect("clicked" => sub {message_dialog($help);});}
+    $box->pack_start( $label, FALSE, FALSE, 0) if(defined $label_name);
+    $box->pack_start( $button, FALSE, FALSE, 0);
+    $box->set_border_width(0);
+    $box->set_spacing (0);
+    $box->show_all;
+    return $box;
 }
 
-
 sub def_colored_button{
-	my ($label_text,$color_num)=@_;
-	# create box for image and label 
-	my $box = def_hbox(FALSE,0);
-	my $font_size=get_defualt_font_size();
-	
-	my ($red,$green,$blue) = get_color($color_num);
-	my $button = ColorButton->new (red => $red, green => $green, blue => $blue, label=>"$label_text");
-	
-	$button->set_border_width(0);
-	$button->show_all;
-	return $button;
+    my ($label_text,$color_num)=@_;
+    # create box for image and label
+    my $box = def_hbox(FALSE,0);
+    my $font_size=get_defualt_font_size();
+    my ($red,$green,$blue) = get_color($color_num);
+    my $button = ColorButton->new (red => $red, green => $green, blue => $blue, label=>"$label_text");
+    $button->set_border_width(0);
+    $button->show_all;
+    return $button;
 }
 
-
-
-
-
 sub entry_set_text_color {
-	my ($entry,$color_num)=@_;
-	my ($red,$green,$blue) = get_color($color_num);
-	my $color = Gtk2::Gdk::Color->new ($red,$green,$blue);
-	$entry->modify_text('normal' , $color); 
+    my ($entry,$color_num)=@_;
+    my ($red,$green,$blue) = get_color($color_num);
+    my $color = Gtk2::Gdk::Color->new ($red,$green,$blue);
+    $entry->modify_text('normal' , $color);
 }
 
-
-
-
-
-
-
-
 sub show_gif{
-	my $gif = shift;
-	$gif=find_icon( $gif);
-	my $vbox = Gtk2::HBox->new (TRUE, 8);
+    my $gif = shift;
+    $gif=find_icon( $gif);
+    my $vbox = Gtk2::HBox->new (TRUE, 8);
     my $filename;
-      eval {
-          $filename = main::demo_find_file ($gif);
-      };
+    eval {
+        $filename = main::demo_find_file ($gif);
+    };
     my $image = Gtk2::Image->new_from_file ($gif);
     $vbox->set_border_width (4);
     my   $align = Gtk2::Alignment->new (0.5, 0.5, 0, 0);
-	my $frame = Gtk2::Frame->new;
-	$frame->set_shadow_type ('in');
+    my $frame = Gtk2::Frame->new;
+    $frame->set_shadow_type ('in');
     # Animation
     $frame->add ($image);
     $align->add ($frame);
-	$vbox->pack_start ($align, FALSE, FALSE, 0);
-  	return $vbox;
+    $vbox->pack_start ($align, FALSE, FALSE, 0);
+    return $vbox;
 }
 
 sub gen_radiobutton {
-	my ($from,$label,$icon,$tip) =@_;
-	my $rbtn = (defined $from )? Gtk2::RadioToolButton->new_from_widget($from) : Gtk2::RadioToolButton->new (undef);
-	$rbtn->set_label ($label) if(defined $label);
-	$rbtn->set_icon_widget (def_icon($icon)) if(defined $icon);
-	set_tip($rbtn, $tip) if(defined $tip);
-	return $rbtn;
+    my ($from,$label,$icon,$tip) =@_;
+    my $rbtn = (defined $from )? Gtk2::RadioToolButton->new_from_widget($from) : Gtk2::RadioToolButton->new (undef);
+    $rbtn->set_label ($label) if(defined $label);
+    $rbtn->set_icon_widget (def_icon($icon)) if(defined $icon);
+    set_tip($rbtn, $tip) if(defined $tip);
+    return $rbtn;
 }
 
 sub gen_colored_label{
-	my ($label_text, $color_num)=@_;
-
-	my $color_hex = get_color_hex_string($color_num);
-	my $label   = Gtk2::Label->new($label_text);
-	$label->set_markup("<span 
+    my ($label_text, $color_num)=@_;
+    my $color_hex = get_color_hex_string($color_num);
+    my $label   = Gtk2::Label->new($label_text);
+    $label->set_markup("<span
  background= '#$color_hex'
  foreground= 'black' ><b>$label_text</b></span>");
-	
-	return $label;
+    return $label;
 }
 
-
 ############
-#	message_dialog
+#    message_dialog
 ############
-
 sub message_dialog {
-  my ($message,$type)=@_;
-  $type = 'info' if (!defined $type);
-  my $window;
-  my $dialog = Gtk2::MessageDialog->new ($window,
-				   [qw/modal destroy-with-parent/],
-				   $type,
-				   'ok',
-				    $message);
-  $dialog->run;
-  $dialog->destroy;
- 
+    my ($message,$type)=@_;
+    $type = 'info' if (!defined $type);
+    my $window;
+    my $dialog = Gtk2::MessageDialog->new ($window,
+        [qw/modal destroy-with-parent/],
+        $type,
+        'ok',
+        $message);
+    $dialog->run;
+    $dialog->destroy;
 }
 
-
-
 sub set_tip{
-	my ($widget,$tip)=@_;
-	my $tooltips = Gtk2::Tooltips->new;
-	$tooltips->set_tip($widget,$tip);
-	
-	
+    my ($widget,$tip)=@_;
+    my $tooltips = Gtk2::Tooltips->new;
+    $tooltips->set_tip($widget,$tip);
 }
 
-
 sub yes_no_dialog {
-	my ($message)=@_;
-	my $dialog = Gtk2::MessageDialog->new (my $window,
-			'destroy-with-parent',
-			'question', # message type
-			'yes-no', # which set of buttons?
-			"$message");
-	my $response = $dialog->run;
-	$dialog->destroy;
-	return $response;
+    my ($message)=@_;
+    my $dialog = Gtk2::MessageDialog->new (my $window,
+            'destroy-with-parent',
+            'question', # message type
+            'yes-no', # which set of buttons?
+            "$message");
+    my $response = $dialog->run;
+    $dialog->destroy;
+    return $response;
 }
 
 sub create_dialog {
-	my ($message_head,$message_body,$icon,@buttons)=@_;
-	# create a new dialog with some buttons - one stock, one not.
-	my %hash1;
-	my %hash2;
-	my $i=0;
-	foreach my $b (@buttons){
-		$hash1{$b}=$i;
-		$hash2{$i}=$b;
-		$i++;
-	}
-	
-  	my $dialog = Gtk2::Dialog->new (
-  		" ", 
-  		Gtk2::Window->new('toplevel'),
-  		[qw/modal destroy-with-parent/],
+    my ($message_head,$message_body,$icon,@buttons)=@_;
+    # create a new dialog with some buttons - one stock, one not.
+    my %hash1;
+    my %hash2;
+    my $i=0;
+    foreach my $b (@buttons){
+        $hash1{$b}=$i;
+        $hash2{$i}=$b;
+        $i++;
+    }
+    my $dialog = Gtk2::Dialog->new (
+        " ",
+        Gtk2::Window->new('toplevel'),
+        [qw/modal destroy-with-parent/],
         %hash1
     );
-	my $content = $dialog->get_content_area ();
-	
-	my $table = def_table(1,3,TRUE);
-	$table->attach  (def_icon($icon) , 0, 1,  0, 2,'expand','expand',2,2) if(defined $icon);
-	if(defined $message_head){
-		my $hd=gen_label_in_left($message_head);
-		$hd->set_markup("<span  foreground= 'black' ><b>$message_head</b></span>");
-		$table->attach  ($hd , 1, 10,  0, 1,'fill','shrink',2,2);
-	}
-	if(defined $message_head){
-		$table->attach  (gen_label_in_left($message_body) , 2, 10,  1, 2,'fill','shrink',2,2);
-	}
-	
-	$content->add ($table);
-	$content->show_all;
-			
-	$dialog->set_transient_for (Gtk2::Window->new('toplevel'));#just to get rid of transient warning		
-	my $response = $dialog->run;
-	
-	$dialog->destroy;
-	return $hash2{$response};
-}
-
 
+    my $content = $dialog->get_content_area ();
+    my $table = def_table(1,3,TRUE);
+    $table->attach  (def_icon($icon) , 0, 1,  0, 2,'expand','expand',2,2) if(defined $icon);
+    if(defined $message_head){
+        my $hd=gen_label_in_left($message_head);
+        $hd->set_markup("<span  foreground= 'black' ><b>$message_head</b></span>");
+        $table->attach  ($hd , 1, 10,  0, 1,'fill','shrink',2,2);
+    }
+    if(defined $message_head){
+        $table->attach  (gen_label_in_left($message_body) , 2, 10,  1, 2,'fill','shrink',2,2);
+    }
+    $content->add ($table);
+    $content->show_all;
+    $dialog->set_transient_for (Gtk2::Window->new('toplevel'));#just to get rid of transient warning
+    my $response = $dialog->run;
+    $dialog->destroy;
+    return $hash2{$response};
+}
 
 ############
 # window
 ###########
-
 sub def_win {
-	my @titel=shift;
-	my $window = Gtk2::Window->new('toplevel');
-	$window->set_title(@titel);
-	$window->set_position("center");
-	$window->set_default_size(100, 100);
-	$window->set_border_width(20);
-	$window->signal_connect (delete_event => sub { Gtk2->main_quit });
-	return $window;
-	
-}	
-
+    my @titel=shift;
+    my $window = Gtk2::Window->new('toplevel');
+    $window->set_title(@titel);
+    $window->set_position("center");
+    $window->set_default_size(100, 100);
+    $window->set_border_width(20);
+    $window->signal_connect (delete_event => sub { Gtk2->main_quit });
+    return $window;
+}
 
 sub def_win_size {
-	my $x=shift;
-	my $y=shift;
-	my @titel=shift;
-	my $window = Gtk2::Window->new('toplevel');
-	$window->set_title(@titel);
-	$window->set_position("center");
-	$window->set_default_size($x, $y);
-	$window->set_border_width(20);
-	$window->signal_connect (delete_event => sub { Gtk2->main_quit });
-	return $window;
-	
-}	
-
+    my $x=shift;
+    my $y=shift;
+    my @titel=shift;
+    my $window = Gtk2::Window->new('toplevel');
+    $window->set_title(@titel);
+    $window->set_position("center");
+    $window->set_default_size($x, $y);
+    $window->set_border_width(20);
+    $window->signal_connect (delete_event => sub { Gtk2->main_quit });
+    return $window;
+}
 
 sub def_popwin_size {
-	my ($x,$y,$titel,$unit)=@_;
-	if(defined $unit){
-		my($width,$hight)=max_win_size();
-		if($unit eq 'percent'){
-			$x= ($x * $width)/100;
-			$y= ($y * $hight)/100;
-		} # else its pixels
-			
-	}
-	#my $window = Gtk2::Window->new('popup');
-	my $window = Gtk2::Window->new('toplevel');
-	$window->set_title($titel);
-	$window->set_position("center");
-	$window->set_default_size($x, $y);
-	$window->set_border_width(20);
-	#$window->signal_connect (delete_event => sub { $window->destroy });
-	return $window;
-	
-}	
-
-
-
-
+    my ($x,$y,$titel,$unit)=@_;
+    if(defined $unit){
+        my($width,$hight)=max_win_size();
+        if($unit eq 'percent'){
+            $x= ($x * $width)/100;
+            $y= ($y * $hight)/100;
+        } # else its pixels
+    }
+    #my $window = Gtk2::Window->new('popup');
+    my $window = Gtk2::Window->new('toplevel');
+    $window->set_title($titel);
+    $window->set_position("center");
+    $window->set_default_size($x, $y);
+    $window->set_border_width(20);
+    #$window->signal_connect (delete_event => sub { $window->destroy });
+    return $window;
+}
 
 sub def_scrolled_window_box{
-			
-	my $window =  def_popwin_size(@_);
-	my $box=def_vbox(TRUE,5);
-	my $scrolled_window = new Gtk2::ScrolledWindow (undef, undef);
-	$scrolled_window->set_policy( "automatic", "automatic" );
-	$scrolled_window->add_with_viewport($box);
-	$window->add($scrolled_window);
-	$window->show_all;
-	$box->show_all;
-	return ($box,$window);
-
+    my $window =  def_popwin_size(@_);
+    my $box=def_vbox(TRUE,5);
+    my $scrolled_window = new Gtk2::ScrolledWindow (undef, undef);
+    $scrolled_window->set_policy( "automatic", "automatic" );
+    $scrolled_window->add_with_viewport($box);
+    $window->add($scrolled_window);
+    $window->show_all;
+    $box->show_all;
+    return ($box,$window);
 }
 
-
 sub get_default_screen {
-  return Gtk2::Gdk::Screen->get_default();
+    return Gtk2::Gdk::Screen->get_default();
 }
 
-
-
 sub get_defualt_font_size{
-	return int($glob_setting{'FONT_SIZE'}) if ($glob_setting{'FONT_SIZE'} ne 'default');
-	
-	my($width,$hight)=max_win_size();
-	#print "($width,$hight)\n";
-	my $font_size=($width>=1600)? 10:
-			      ($width>=1400)? 9:
-				  ($width>=1200)? 9:
-				  ($width>=1000)? 8:7;
-	#print "$font_size\n";	
-	return $font_size;
+    return int($glob_setting{'FONT_SIZE'}) if ($glob_setting{'FONT_SIZE'} ne 'default');
+    my($width,$hight)=max_win_size();
+    #print "($width,$hight)\n";
+    my $font_size=
+        ($width>=1600)? 10:
+        ($width>=1400)? 9:
+        ($width>=1200)? 9:
+        ($width>=1000)? 8:7;
+    #print "$font_size\n";
+    return $font_size;
 }
 
-
 sub set_defualt_font_size{
-	my $font_size=get_defualt_font_size();
-	   #$font_size= int (1.5*$font_size);
-		Gtk2::Rc->parse_string(<<__);
-			style "normal" { 
-				font_name ="Verdana $font_size" 
-			}
-			widget "*" style "normal"
+    my $font_size=get_defualt_font_size();
+    #$font_size= int (1.5*$font_size);
+    Gtk2::Rc->parse_string(<<__);
+        style "normal" {
+        font_name ="Verdana $font_size"
+        }
+        widget "*" style "normal"
 __
-
 }
 
-
-
 sub add_widget_to_scrolled_win{
-	my ($widget,$scrolled_win) =@_;
-	if(! defined $scrolled_win){
-		$scrolled_win = new Gtk2::ScrolledWindow (undef, undef);
-		$scrolled_win->set_policy( "automatic", "automatic" );			
-	}	
-	$scrolled_win->add_with_viewport($widget) if(defined $widget);	
-	#$scrolled_win->set_shadow_type('in');
-	#$scrolled_win->show_all;	
-	return $scrolled_win;
+    my ($widget,$scrolled_win) =@_;
+    if(! defined $scrolled_win){
+        $scrolled_win = new Gtk2::ScrolledWindow (undef, undef);
+        $scrolled_win->set_policy( "automatic", "automatic" );
+    }
+    $scrolled_win->add_with_viewport($widget) if(defined $widget);
+    #$scrolled_win->set_shadow_type('in');
+    #$scrolled_win->show_all;
+    return $scrolled_win;
 }
 
 sub gen_scr_win_with_adjst {
-	my ($self,$name)=@_;
-	my $scrolled_win = new Gtk2::ScrolledWindow (undef, undef);	
-	$scrolled_win->set_policy( "automatic", "automatic" );	
-	$scrolled_win->signal_connect("destroy"=> sub{
-	 	save_scrolled_win_adj($self,$scrolled_win, $name);
-	 	
-	 });
-	 my $adjast=0;
-	 $scrolled_win->signal_connect("size-allocate"=> sub{
-	 	if($adjast==0){
-	 		load_scrolled_win_adj($self,$scrolled_win, $name);
-	 		$adjast=1;
-	 	}
-	 	
-	 });	
-	return $scrolled_win;
+    my ($self,$name)=@_;
+    my $scrolled_win = new Gtk2::ScrolledWindow (undef, undef);
+    $scrolled_win->set_policy( "automatic", "automatic" );
+    $scrolled_win->signal_connect("destroy"=> sub{
+        save_scrolled_win_adj($self,$scrolled_win, $name);
+    });
+    my $adjast=0;
+    $scrolled_win->signal_connect("size-allocate"=> sub{
+        if($adjast==0){
+            load_scrolled_win_adj($self,$scrolled_win, $name);
+            $adjast=1;
+        }
+    });
+    return $scrolled_win;
 }
 
-
 sub save_scrolled_win_adj {
-	my ($self,$scrolled_win,$name)=@_;  	
-	my $ha= $scrolled_win->get_hadjustment();
+    my ($self,$scrolled_win,$name)=@_;
+    my $ha= $scrolled_win->get_hadjustment();
     my $va =$scrolled_win->get_vadjustment();
     return if(!defined $ha);
     return if(!defined $va);
-    save_adj ($self,$ha,$name,"ha"); 
-	save_adj ($self,$va,$name,"va"); 
+    save_adj ($self,$ha,$name,"ha");
+    save_adj ($self,$va,$name,"va");
 }
 
-
 sub load_scrolled_win_adj {
-	my ($self,$scrolled_win,$name)=@_;  
-	my $ha= $scrolled_win->get_hadjustment();
+    my ($self,$scrolled_win,$name)=@_;
+    my $ha= $scrolled_win->get_hadjustment();
     my $va =$scrolled_win->get_vadjustment();
-	my $h=load_adj ($self,$ha,$name,"ha"); 
-	my $v=load_adj ($self,$va,$name,"va"); 
-	#$ha->set_value($h) if(defined $h);
-    #$va->set_value($v) if(defined $v);    
-}
-  
-    
-    
-    
-sub save_adj {
-	my ($self,$adjustment,$at1,$at2)=@_;  	
-	my $value = $adjustment->value;
-	$self->object_add_attribute($at1,$at2,$value);
+    my $h=load_adj ($self,$ha,$name,"ha");
+    my $v=load_adj ($self,$va,$name,"va");
+    #$ha->set_value($h) if(defined $h);
+    #$va->set_value($v) if(defined $v);
 }
 
+sub save_adj {
+    my ($self,$adjustment,$at1,$at2)=@_;
+    my $value = $adjustment->value;
+    $self->object_add_attribute($at1,$at2,$value);
+}
 
 sub load_adj {
-	my ($self,$adjustment,$at1,$at2)=@_;
-	return if(!defined $at1);
+    my ($self,$adjustment,$at1,$at2)=@_;
+    return if(!defined $at1);
     my $value=  $self->object_get_attribute($at1,$at2);
     return if(!defined $value);
     my $lower =  $adjustment->lower;
     my $upper = $adjustment->upper - $adjustment->page_size;
-    $value=  ($value < $lower || $value > $upper ) ? 0 : $value; 
-    
-    $adjustment->set_value($value);   
+    $value=  ($value < $lower || $value > $upper ) ? 0 : $value;
+    $adjustment->set_value($value);
 }
 
 sub set_pronoc_icon{
-	my $window=shift;
-    my $navIco = gen_pixbuf("./icons/ProNoC.png");        
-	$window->set_default_icon($navIco); 
+    my $window=shift;
+    my $navIco = gen_pixbuf("./icons/ProNoC.png");
+    $window->set_default_icon($navIco);
 }
 
 ##############
-#	box
+#    box
 #############
-
 sub def_hbox {
-	my( $homogeneous, $spacing)=@_;
-	my $box = Gtk2::HBox->new($homogeneous, $spacing);
-	$box->set_border_width(2);
-	return $box;
+    my( $homogeneous, $spacing)=@_;
+    my $box = Gtk2::HBox->new($homogeneous, $spacing);
+    $box->set_border_width(2);
+    return $box;
 }
 
 sub def_vbox {
-	my $box = Gtk2::VBox->new(FALSE, 0);
-	$box->set_border_width(2);
-	return $box;
+    my $box = Gtk2::VBox->new(FALSE, 0);
+    $box->set_border_width(2);
+    return $box;
 }
 
 sub def_pack_hbox{
-	my( $homogeneous, $spacing , @box_list)=@_;
-	my $box=def_hbox($homogeneous, $spacing); 
-	foreach my $subbox (@box_list){
-		$box->pack_start( $subbox, FALSE, FALSE, 3);
-	}
-	return $box;	
-
-
+    my( $homogeneous, $spacing , @box_list)=@_;
+    my $box=def_hbox($homogeneous, $spacing);
+    foreach my $subbox (@box_list){
+        $box->pack_start( $subbox, FALSE, FALSE, 3);
+    }
+    return $box;
 }
 
 sub def_pack_vbox{
-	my( $homogeneous, $spacing , @box_list)=@_;
-	my $box=def_vbox($homogeneous, $spacing); 
-	foreach my $subbox (@box_list){
-		$box->pack_start( $subbox, FALSE, FALSE, 3);
-	}
-	return $box;	
-
+    my( $homogeneous, $spacing , @box_list)=@_;
+    my $box=def_vbox($homogeneous, $spacing);
+    foreach my $subbox (@box_list){
+        $box->pack_start( $subbox, FALSE, FALSE, 3);
+    }
+    return $box;
 }
 
-
 ##########
 # Paned
 #########
-
-
 sub gen_vpaned {
-	my ($w1,$loc,$w2) = @_;
-	my $vpaned = Gtk2::VPaned -> new;
-	my($width,$hight)=max_win_size();
-		
-	$vpaned -> pack1($w1, TRUE, TRUE); 	
-	$vpaned -> set_position ($hight*$loc);	
-	$vpaned -> pack2($w2, TRUE, TRUE); 
-	
-	return $vpaned;
+    my ($w1,$loc,$w2) = @_;
+    my $vpaned = Gtk2::VPaned -> new;
+    my($width,$hight)=max_win_size();
+    $vpaned -> pack1($w1, TRUE, TRUE);
+    $vpaned -> set_position ($hight*$loc);
+    $vpaned -> pack2($w2, TRUE, TRUE);
+    return $vpaned;
 }
 
-
 sub gen_hpaned {
-	my ($w1,$loc,$w2) = @_;
-	my $hpaned = Gtk2::HPaned -> new;
-	my($width,$hight)=max_win_size();
-
-	
-	$hpaned -> pack1($w1, TRUE, TRUE); 	
-	$hpaned -> set_position ($width*$loc);	
-	$hpaned -> pack2($w2, TRUE, TRUE); 
-	
-	return $hpaned;
+    my ($w1,$loc,$w2) = @_;
+    my $hpaned = Gtk2::HPaned -> new;
+    my($width,$hight)=max_win_size();
+    $hpaned -> pack1($w1, TRUE, TRUE);
+    $hpaned -> set_position ($width*$loc);
+    $hpaned -> pack2($w2, TRUE, TRUE);
+    return $hpaned;
 }
 
 sub gen_hpaned_adj {
-	my ($self,$w1,$loc,$w2,$name) = @_;
-	my $hpaned = Gtk2::HPaned -> new;
-	$hpaned -> pack1($w1, TRUE, TRUE); 
-	$hpaned -> pack2($w2, TRUE, TRUE); 	
-	
-	$hpaned->signal_connect("destroy"=> sub{
-	 	my $adj = $hpaned->get_position ();
-	 	$self->object_add_attribute("adj",$name,$adj);
-	 });	
-	
-	my $val =$self->object_get_attribute("adj",$name);
-	if(defined $val){
-		$hpaned -> set_position ($val);
-	} else{
-		my($width,$hight)=max_win_size();
-		$hpaned -> set_position ($width*$loc);		
-	}	
-	
-	return $hpaned;
+    my ($self,$w1,$loc,$w2,$name) = @_;
+    my $hpaned = Gtk2::HPaned -> new;
+    $hpaned -> pack1($w1, TRUE, TRUE);
+    $hpaned -> pack2($w2, TRUE, TRUE);
+    $hpaned->signal_connect("destroy"=> sub{
+        my $adj = $hpaned->get_position ();
+        $self->object_add_attribute("adj",$name,$adj);
+    });
+    my $val =$self->object_get_attribute("adj",$name);
+    if(defined $val){
+        $hpaned -> set_position ($val);
+    } else{
+        my($width,$hight)=max_win_size();
+        $hpaned -> set_position ($width*$loc);
+    }
+    return $hpaned;
 }
 
-
 #############
-# text_view 
+# text_view
 ############
-
 sub create_txview {
-  my $scrolled_window = Gtk2::ScrolledWindow->new;
-  $scrolled_window->set_policy ('automatic', 'automatic');
-  $scrolled_window->set_shadow_type ('in');
-  my $tview = Gtk2::TextView->new();
-  $scrolled_window->add ($tview);
-  $tview->show_all;
-  # Make it a bit nicer for text.
-  $tview->set_wrap_mode ('word');
-  $tview->set_pixels_above_lines (2);
-  $tview->set_pixels_below_lines (2);
-  # $scrolled_window->set_placement('bottom_left' );
-  add_colors_to_textview($tview);
- 	
-  return ($scrolled_window,$tview);
+    my $scrolled_window = Gtk2::ScrolledWindow->new;
+    $scrolled_window->set_policy ('automatic', 'automatic');
+    $scrolled_window->set_shadow_type ('in');
+    my $tview = Gtk2::TextView->new();
+    $scrolled_window->add ($tview);
+    $tview->show_all;
+    # Make it a bit nicer for text.
+    $tview->set_wrap_mode ('word');
+    $tview->set_pixels_above_lines (2);
+    $tview->set_pixels_below_lines (2);
+    # $scrolled_window->set_placement('bottom_left' );
+    add_colors_to_textview($tview);
+    return ($scrolled_window,$tview);
 }
 
-
 sub txview_scrol_to_end {
-  my $tview =shift;
-  my $buffer =  $tview->get_buffer;
-  my $end_mark = $buffer->create_mark( 'end', $buffer->get_end_iter, 0 );
-  $tview->scroll_to_mark( $end_mark, 0.0,0, 0.0, 1.0 );	
+    my $tview =shift;
+    my $buffer =  $tview->get_buffer;
+    my $end_mark = $buffer->create_mark( 'end', $buffer->get_end_iter, 0 );
+    $tview->scroll_to_mark( $end_mark, 0.0,0, 0.0, 1.0 );
 }
 
-
-
 #################
-#	table
+#    table
 ################
-
 sub def_table{
-	my ($row,$col,$homogeneous)=@_;
-	my $table = Gtk2::Table->new ($row, $col, $homogeneous);
-	$table->set_row_spacings (0);
-	$table->set_col_spacings (0);
-	return $table;
-
+    my ($row,$col,$homogeneous)=@_;
+    my $table = Gtk2::Table->new ($row, $col, $homogeneous);
+    $table->set_row_spacings (0);
+    $table->set_col_spacings (0);
+    return $table;
 }
 
 sub attach_widget_to_table {
-	my ($table,$row,$label,$inf_bt,$widget,$column)=@_;
-	$column = 0 if(!defined $column);
-	#$column *=4;
-	#my $tmp=gen_label_in_left(" "); 
-	if(defined $label)  {$table->attach  ($label , $column, $column+1,  $row,$row+1,'fill','shrink',2,2);$column++;}
-	if(defined $inf_bt) {$table->attach  ($inf_bt , $column, $column+1, $row,$row+1,'fill','shrink',2,2);$column++;}
-	if(defined $widget) {$table->attach  ($widget , $column, $column+1, $row,$row+1,'fill','shrink',2,2);$column++;}
-	#$table->attach  ($tmp , $column+3, $column+4, $row,$row+1,'fill','shrink',2,2);
+    my ($table,$row,$label,$inf_bt,$widget,$column)=@_;
+    $column = 0 if(!defined $column);
+    #$column *=4;
+    #my $tmp=gen_label_in_left(" ");
+    if(defined $label)  {$table->attach  ($label , $column, $column+1,  $row,$row+1,'fill','shrink',2,2);$column++;}
+    if(defined $inf_bt) {$table->attach  ($inf_bt , $column, $column+1, $row,$row+1,'fill','shrink',2,2);$column++;}
+    if(defined $widget) {$table->attach  ($widget , $column, $column+1, $row,$row+1,'fill','shrink',2,2);$column++;}
+    #$table->attach  ($tmp , $column+3, $column+4, $row,$row+1,'fill','shrink',2,2);
 }
 
-sub gen_Hsep { 
-	return Gtk2::HSeparator->new;
+sub gen_Hsep {
+    return Gtk2::HSeparator->new;
 }
 
-sub gen_Vsep { 
-	return Gtk2::VSeparator->new;
+sub gen_Vsep {
+    return Gtk2::VSeparator->new;
 }
 
-
 sub add_Hsep_to_table {
-	my($table,$col0,$col1,$row)=@_;
-	my $separator = gen_Hsep();	
-	$table->attach ($separator ,$col0,$col1 , $row, $row+1,'fill','fill',2,2);	
+    my($table,$col0,$col1,$row)=@_;
+    my $separator = gen_Hsep();
+    $table->attach ($separator ,$col0,$col1 , $row, $row+1,'fill','fill',2,2);
 }
 
 sub add_Vsep_to_table {
-	my($table,$col,$row1,$row2)=@_;
-	my $separator = gen_Vsep();	
-	$table->attach ($separator ,$col,$col+1 , $row1, $row2,'fill','fill',2,2);	
+    my($table,$col,$row1,$row2)=@_;
+    my $separator = gen_Vsep();
+    $table->attach ($separator ,$col,$col+1 , $row1, $row2,'fill','fill',2,2);
 }
 
-
 ##################
-#	show_info
+#    show_info
 ##################
 sub show_info{
-	my ($textview,$info)=@_;
-	#return;# if(!defined $textview_ref);
-	#print "$textview_ref\n";
-	my $buffer = $textview->get_buffer();
-  	$buffer->set_text($info);
-  	txview_scrol_to_end($textview);
+    my ($textview,$info)=@_;
+    #return;# if(!defined $textview_ref);
+    #print "$textview_ref\n";
+    my $buffer = $textview->get_buffer();
+    $buffer->set_text($info);
+    txview_scrol_to_end($textview);
 }
 
 sub add_info{
-	my ($textview,$info)=@_;
-	my $buffer = $textview->get_buffer();
-	my $textiter = $buffer->get_end_iter();
-	#Insert some text into the buffer
-	$buffer->insert($textiter,$info);
-	txview_scrol_to_end($textview);
-	
+    my ($textview,$info)=@_;
+    my $buffer = $textview->get_buffer();
+    my $textiter = $buffer->get_end_iter();
+    #Insert some text into the buffer
+    $buffer->insert($textiter,$info);
+    txview_scrol_to_end($textview);
 }
 
-
 sub show_colored_info{
-	my ($textview,$info,$color)=@_;
-	my $buffer = $textview->get_buffer();
-  	#$buffer->set_text($info);
-	my $textiter = $buffer->get_start_iter();
-	$buffer->insert_with_tags_by_name ($textiter, "$info", "${color}_tag");
-	txview_scrol_to_end($textview);
+    my ($textview,$info,$color)=@_;
+    my $buffer = $textview->get_buffer();
+    #$buffer->set_text($info);
+    my $textiter = $buffer->get_start_iter();
+    $buffer->insert_with_tags_by_name ($textiter, "$info", "${color}_tag");
+    txview_scrol_to_end($textview);
 }
 
 sub add_colored_info{
-	my ($textview,$info,$color)=@_;
-	my $buffer = $textview->get_buffer();
-	my $textiter = $buffer->get_end_iter();
-	$buffer->insert_with_tags_by_name ($textiter, "$info", "${color}_tag");
-	txview_scrol_to_end($textview);
-	
+    my ($textview,$info,$color)=@_;
+    my $buffer = $textview->get_buffer();
+    my $textiter = $buffer->get_end_iter();
+    $buffer->insert_with_tags_by_name ($textiter, "$info", "${color}_tag");
+    txview_scrol_to_end($textview);
 }
 
 sub add_colors_to_textview{
-	my $tview= shift;
-	add_colored_tag($tview,'red');
-	add_colored_tag($tview,'blue');
-	add_colored_tag($tview,'brown');
-	add_colored_tag($tview,'green');
+    my $tview= shift;
+    add_colored_tag($tview,'red');
+    add_colored_tag($tview,'blue');
+    add_colored_tag($tview,'brown');
+    add_colored_tag($tview,'green');
 }
 
-
 sub add_colored_tag{
-	my ($textview_ref,$color)=@_;
-	my $buffer = $textview_ref->get_buffer();
-  	$buffer->create_tag ("${color}_tag", foreground => $color);  
+    my ($textview_ref,$color)=@_;
+    my $buffer = $textview_ref->get_buffer();
+    $buffer->create_tag ("${color}_tag", foreground => $color);
 }
 
 sub add_color_to_gd{
-	foreach (my $i=0;$i<32;$i++ ) {
-		my ($red,$green,$blue)=get_color($i);	    
-		add_colour("my_color$i"=>[$red>>8,$green>>8,$blue>>8]);
-		
-	}	
+    foreach (my $i=0;$i<32;$i++ ) {
+        my ($red,$green,$blue)=get_color($i);
+        add_colour("my_color$i"=>[$red>>8,$green>>8,$blue>>8]);
+    }
 }
 
-
-
 ############
-#	get file folder list
+#    get file folder list
 ###########
-
 sub get_directory_name_widget {
-	my ($object,$title,$entry,$attribute1,$attribute2,$status,$timeout)= @_;
-	my $browse= def_image_button("icons/browse.png");
-
-	$browse->signal_connect("clicked"=> sub{
-		my $entry_ref=$_[1];
- 		my $file;
-		$title ='select directory' if(!defined $title);
-		my $dialog = Gtk2::FileChooserDialog->new(
-		    	$title, undef,
-			#       	'open',
-			'select-folder',
-		    	'gtk-cancel' => 'cancel',
-		    	'gtk-ok'     => 'ok',
-			);
-	       
-			
-			if ( "ok" eq $dialog->run ) {
-		    	$file = $dialog->get_filename;
-				$$entry_ref->set_text($file);
-				$object->object_add_attribute($attribute1,$attribute2,$file);
-				set_gui_status($object,$status,$timeout) if(defined $status);			
-				#check_input_file($file,$socgen,$soc_state,$info);
-		    		#print "file = $file\n";
-	       		 }
-	       		$dialog->destroy;
-	       		
-
-
-		} , \$entry);
-	
-	return $browse;
-
+    my ($object,$title,$entry,$attribute1,$attribute2,$status,$timeout)= @_;
+    my $browse= def_image_button("icons/browse.png");
+    $browse->signal_connect("clicked"=> sub{
+        my $entry_ref=$_[1];
+        my $file;
+        $title ='select directory' if(!defined $title);
+        my $dialog = Gtk2::FileChooserDialog->new(
+                $title, undef,
+            #           'open',
+            'select-folder',
+                'gtk-cancel' => 'cancel',
+                'gtk-ok'     => 'ok',
+            );
+            if ( "ok" eq $dialog->run ) {
+                $file = $dialog->get_filename;
+                $$entry_ref->set_text($file);
+                $object->object_add_attribute($attribute1,$attribute2,$file);
+                set_gui_status($object,$status,$timeout) if(defined $status);
+                #check_input_file($file,$socgen,$soc_state,$info);
+                    #print "file = $file\n";
+                    }
+                $dialog->destroy;
+        } , \$entry);
+    return $browse;
 }
 
-
 sub get_dir_name {
-	my ($object,$title,$attribute1,$attribute2,$open_in,$status,$timeout)= @_;
-	my $dir;
-	$title ='select directory' if(!defined $title);
-	my $dialog = Gtk2::FileChooserDialog->new(
-	  	$title, undef,
-		#       	'open',
-		'select-folder',
-	   	'gtk-cancel' => 'cancel',
-	   	'gtk-ok'     => 'ok',
-	);
-	if(defined  $open_in){
-		$dialog->set_current_folder ($open_in); 
-	}
-	       			
-	if ( "ok" eq $dialog->run ) {
-		    	$dir = $dialog->get_filename;
-				$object->object_add_attribute($attribute1,$attribute2,$dir);
-				set_gui_status($object,$status,$timeout) if(defined $status);	
-				$dialog->destroy;
-	}
+    my ($object,$title,$attribute1,$attribute2,$open_in,$status,$timeout)= @_;
+    my $dir;
+    $title ='select directory' if(!defined $title);
+    my $dialog = Gtk2::FileChooserDialog->new(
+        $title, undef,
+        #           'open',
+        'select-folder',
+        'gtk-cancel' => 'cancel',
+        'gtk-ok'     => 'ok',
+    );
+    if(defined  $open_in){
+        $dialog->set_current_folder ($open_in);
+    }
+    if ( "ok" eq $dialog->run ) {
+                $dir = $dialog->get_filename;
+                $object->object_add_attribute($attribute1,$attribute2,$dir);
+                set_gui_status($object,$status,$timeout) if(defined $status);
+                $dialog->destroy;
+    }
 }
 
-
-
 sub get_file_name {
-	my ($object,$title,$entry,$attribute1,$attribute2,$extension,$label,$open_in)= @_;
-	my $browse= def_image_button("icons/browse.png");
-	
-	$browse->signal_connect("clicked"=> sub{
-		my $entry_ref=$_[1];
- 		my $file;
-		$title ='select a file' if(!defined $title);
-		my $dialog = Gtk2::FileChooserDialog->new(
-            	'Select a File', undef,
-            	'open',
-            	'gtk-cancel' => 'cancel',
-            	'gtk-ok'     => 'ok',
-        	);
-	 if(defined $extension){
-		my $filter = Gtk2::FileFilter->new();
-		$filter->set_name($extension);
-		$filter->add_pattern("*.$extension");
-		$dialog->add_filter ($filter);
-	 }
-	  if(defined  $open_in){
-		$dialog->set_current_folder ($open_in); 
-		# print "$open_in\n";
-		 
-	}
-		
-			if ( "ok" eq $dialog->run ) {
-		    	$file = $dialog->get_filename;
-				#remove $project_dir form beginig of each file
-            	$file =remove_project_dir_from_addr($file); 
-				$$entry_ref->set_text($file);
-				$object->object_add_attribute($attribute1,$attribute2,$file) if(defined $object);
-				my ($name,$path,$suffix) = fileparse("$file",qr"\..[^.]*$");
-				if(defined $label){
-					$label->set_markup("<span  foreground= 'black' ><b>$name$suffix</b></span>");
-					$label->show;
-				}
-						
-				#check_input_file($file,$socgen,$soc_state,$info);
-		    		#print "file = $file\n";
-	       		 }
-	       		$dialog->destroy;
-	       		
-
-
-		} , \$entry);
-	
-	return $browse;
-
+    my ($object,$title,$entry,$attribute1,$attribute2,$extension,$label,$open_in)= @_;
+    my $browse= def_image_button("icons/browse.png");
+    $browse->signal_connect("clicked"=> sub{
+        my $entry_ref=$_[1];
+        my $file;
+        $title ='select a file' if(!defined $title);
+        my $dialog = Gtk2::FileChooserDialog->new(
+                'Select a File', undef,
+                'open',
+                'gtk-cancel' => 'cancel',
+                'gtk-ok'     => 'ok',
+            );
+    if(defined $extension){
+        my $filter = Gtk2::FileFilter->new();
+        $filter->set_name($extension);
+        $filter->add_pattern("*.$extension");
+        $dialog->add_filter ($filter);
+    }
+    if(defined  $open_in){
+        $dialog->set_current_folder ($open_in);
+        # print "$open_in\n";
+    }
+            if ( "ok" eq $dialog->run ) {
+                $file = $dialog->get_filename;
+                #remove $project_dir form beginig of each file
+                $file =remove_project_dir_from_addr($file);
+                $$entry_ref->set_text($file);
+                $object->object_add_attribute($attribute1,$attribute2,$file) if(defined $object);
+                my ($name,$path,$suffix) = fileparse("$file",qr"\..[^.]*$");
+                if(defined $label){
+                    $label->set_markup("<span  foreground= 'black' ><b>$name$suffix</b></span>");
+                    $label->show;
+                }
+                #check_input_file($file,$socgen,$soc_state,$info);
+                    #print "file = $file\n";
+                    }
+                $dialog->destroy;
+        } , \$entry);
+    return $browse;
 }
 
 sub gen_file_dialog  {
-	my ($title, @extension)=@_;
-	$title = 'Select a File' if (!defined $title);
-
-	my $dialog = Gtk2::FileChooserDialog->new(
-            	$title, undef,
-            	'open',
-            	'gtk-cancel' => 'cancel',
-            	'gtk-ok'     => 'ok',
-     );
-
-	foreach my $ext (@extension){
-		my $filter = Gtk2::FileFilter->new();
-		$filter->set_name("$ext");
-		$filter->add_pattern("*.$ext");
-		$dialog->add_filter ($filter);
-	}	
-
-	return $dialog;
+    my ($title, @extension)=@_;
+    $title = 'Select a File' if (!defined $title);
+    my $dialog = Gtk2::FileChooserDialog->new(
+                $title, undef,
+                'open',
+                'gtk-cancel' => 'cancel',
+                'gtk-ok'     => 'ok',
+    );
+    foreach my $ext (@extension){
+        my $filter = Gtk2::FileFilter->new();
+        $filter->set_name("$ext");
+        $filter->add_pattern("*.$ext");
+        $dialog->add_filter ($filter);
+    }
+    return $dialog;
 }
 
-
 sub save_file_dialog  {
-	my ($title, @extension)=@_;
-	$title = 'Select a File' if (!defined $title);
-
-	my $dialog = Gtk2::FileChooserDialog->new(
-            	$title, 
-				undef,
-            	'save',
-            	'gtk-cancel' => 'cancel',
-            	'gtk-ok'     => 'ok',
-     );
-
-	$dialog->set_modal(TRUE);
-	$dialog->set_transient_for (Gtk2::Window->new('toplevel'));#just to get rid of transient warning
-
-	foreach my $ext (@extension){
-		my $filter = Gtk2::FileFilter->new();
-		$filter->set_name("$ext");
-		$filter->add_pattern("*.$ext");
-		$dialog->add_filter ($filter);
-	}	
-
-	return $dialog;
-
+    my ($title, @extension)=@_;
+    $title = 'Select a File' if (!defined $title);
+    my $dialog = Gtk2::FileChooserDialog->new(
+                $title,
+                undef,
+                'save',
+                'gtk-cancel' => 'cancel',
+                'gtk-ok'     => 'ok',
+    );
+    $dialog->set_modal(TRUE);
+    $dialog->set_transient_for (Gtk2::Window->new('toplevel'));#just to get rid of transient warning
+    foreach my $ext (@extension){
+        my $filter = Gtk2::FileFilter->new();
+        $filter->set_name("$ext");
+        $filter->add_pattern("*.$ext");
+        $dialog->add_filter ($filter);
+    }
+    return $dialog;
 }
 
-
-
-
 sub gen_folder_dialog  {
-	my ($title)=@_;
-	$title = 'Select Folder' if (!defined $title);
-	
-	
-
-	my $dialog = Gtk2::FileChooserDialog->new(
-		$title, 
-		undef,
-		'select-folder',
-	   	'gtk-cancel' => 'cancel',
-	   	'gtk-ok'     => 'ok',
-     );
-	$dialog->set_modal(TRUE);
-	
-	return $dialog;
-
+    my ($title)=@_;
+    $title = 'Select Folder' if (!defined $title);
+    my $dialog = Gtk2::FileChooserDialog->new(
+        $title,
+        undef,
+        'select-folder',
+        'gtk-cancel' => 'cancel',
+        'gtk-ok'     => 'ok',
+    );
+    $dialog->set_modal(TRUE);
+    return $dialog;
 }
 
-
 sub get_filenames_from_dialog{
-	my $dialog=shift;
-	my @files = $dialog->get_filenames;
-	return @files;
+    my $dialog=shift;
+    my @files = $dialog->get_filenames;
+    return @files;
 }
 
-
 sub new_dialog_with_buttons {
-	my $self =shift;
-	return Gtk2::Dialog->new_with_buttons(
-		"Goto to line",
-		$self->window,
-		[ 'modal' ],
-		'gtk-cancel' => 'cancel',
-		'gtk-ok'     => 'ok',
-	);
-
+    my $self =shift;
+    return Gtk2::Dialog->new_with_buttons(
+        "Goto to line",
+        $self->window,
+        [ 'modal' ],
+        'gtk-cancel' => 'cancel',
+        'gtk-ok'     => 'ok',
+    );
 }
 
-
 #################
-#	widget update object
+#    widget update object
 #################
-
 sub gen_entry_object {
-	my ($object,$attribute1,$attribute2,$default,$status,$timeout)=@_;
-	my $old=$object->object_get_attribute($attribute1,$attribute2);
-	my $widget;
-	if(defined $old ){
-		$widget=gen_entry($old);
-	}
-	else
-	{
-		$widget=gen_entry($default);
-		$object->object_add_attribute($attribute1,$attribute2,$default);		
-	}	
-	$widget-> signal_connect("changed" => sub{
-		my $new_param_value=$widget->get_text();
-		$object->object_add_attribute($attribute1,$attribute2,$new_param_value);
-		set_gui_status($object,$status,$timeout) if (defined $status);
-	});
-	return $widget;
+    my ($object,$attribute1,$attribute2,$default,$status,$timeout)=@_;
+    my $old=$object->object_get_attribute($attribute1,$attribute2);
+    my $widget;
+    if(defined $old ){
+        $widget=gen_entry($old);
+    }
+    else
+    {
+        $widget=gen_entry($default);
+        $object->object_add_attribute($attribute1,$attribute2,$default);
+    }
+    $widget-> signal_connect("changed" => sub{
+        my $new_param_value=$widget->get_text();
+        $object->object_add_attribute($attribute1,$attribute2,$new_param_value);
+        set_gui_status($object,$status,$timeout) if (defined $status);
+    });
+    return $widget;
 }
 
-
 sub gen_combobox_object {
- 	my ($object,$attribute1,$attribute2,$content,$default,$status,$timeout)=@_;
-	my @combo_list=split(/\s*,\s*/,$content);
-	my $value=$object->object_get_attribute($attribute1,$attribute2);
-	my $pos;
-	$pos=get_pos($value, @combo_list) if (defined $value);
-	if(!defined $pos && defined $default){
-		$object->object_add_attribute($attribute1,$attribute2,$default);	
-	 	$pos=get_item_pos($default, @combo_list);
-	}
-	#print " my $pos=get_item_pos($value, @combo_list);\n";
-	my $widget=gen_combo(\@combo_list, $pos);
-	$widget-> signal_connect("changed" => sub{
-		my $new_param_value=$widget->get_active_text();
-		$object->object_add_attribute($attribute1,$attribute2,$new_param_value);
-		set_gui_status($object,$status,$timeout) if (defined $status);
-	 });
-	return $widget;		 
-	
-
+    my ($object,$attribute1,$attribute2,$content,$default,$status,$timeout)=@_;
+    my @combo_list=split(/\s*,\s*/,$content);
+    my $value=$object->object_get_attribute($attribute1,$attribute2);
+    my $pos;
+    $pos=get_pos($value, @combo_list) if (defined $value);
+    if(!defined $pos && defined $default){
+        $object->object_add_attribute($attribute1,$attribute2,$default);
+        $pos=get_item_pos($default, @combo_list);
+    }
+    #print " my $pos=get_item_pos($value, @combo_list);\n";
+    my $widget=gen_combo(\@combo_list, $pos);
+    $widget-> signal_connect("changed" => sub{
+        my $new_param_value=$widget->get_active_text();
+        $object->object_add_attribute($attribute1,$attribute2,$new_param_value);
+        set_gui_status($object,$status,$timeout) if (defined $status);
+    });
+    return $widget;
 }
 
-
 sub gen_comboentry_object {
- 	my ($object,$attribute1,$attribute2,$content,$default,$status,$timeout)=@_;
-	my @combo_list;
-	@combo_list=split(/\s*,\s*/,$content) if(defined $content );
-	my $value=$object->object_get_attribute($attribute1,$attribute2);
-	my $pos;
-	$pos=get_pos($value, @combo_list) if (defined $value);
-	if(!defined $pos && defined $default){
-		$object->object_add_attribute($attribute1,$attribute2,$default);	
-	 	$pos=get_item_pos($default, @combo_list);
-	}
-	#print " my $pos=get_item_pos($value, @combo_list);\n";
-	
-	my $widget=gen_combo_entry(\@combo_list, $pos);
-	($widget->child)->signal_connect('changed' => sub {
-		my ($entry) = @_;
-		my $new_param_value=$entry->get_text();
-		$object->object_add_attribute($attribute1,$attribute2,$new_param_value);
-		set_gui_status($object,$status,$timeout) if (defined $status);
-	 });
-	return $widget;	
-
+    my ($object,$attribute1,$attribute2,$content,$default,$status,$timeout)=@_;
+    my @combo_list;
+    @combo_list=split(/\s*,\s*/,$content) if(defined $content );
+    my $value=$object->object_get_attribute($attribute1,$attribute2);
+    my $pos;
+    $pos=get_pos($value, @combo_list) if (defined $value);
+    if(!defined $pos && defined $default){
+        $object->object_add_attribute($attribute1,$attribute2,$default);
+        $pos=get_item_pos($default, @combo_list);
+    }
+    #print " my $pos=get_item_pos($value, @combo_list);\n";
+    my $widget=gen_combo_entry(\@combo_list, $pos);
+    ($widget->child)->signal_connect('changed' => sub {
+        my ($entry) = @_;
+        my $new_param_value=$entry->get_text();
+        $object->object_add_attribute($attribute1,$attribute2,$new_param_value);
+        set_gui_status($object,$status,$timeout) if (defined $status);
+    });
+    return $widget;
 }
 
-
-
 sub gen_spin_object {
-	my ($object,$attribute1,$attribute2,$content, $default,$status,$timeout)=@_;
-	my $value=$object->object_get_attribute($attribute1,$attribute2);
-	my ($min,$max,$step,$digit)=split(/\s*,\s*/,$content);
-	if(!defined $value){
-		$value=$default;
-		$object->object_add_attribute($attribute1,$attribute2,$value);
-	}
-	
-	$value=~ s/[^0-9.\-]//g;
-	$min=~   s/[^0-9.\-]//g;
-	$max=~   s/[^0-9.\-]//g;
-	$step=~  s/[^0-9.\-]//g;
-	$digit=~ s/[^0-9.\-]//g if (defined $digit);
-	
-	my $widget=gen_spin($min,$max,$step,$digit);
-	$widget->set_value($value);
-	$widget-> signal_connect("value_changed" => sub{
-		my $new_param_value=$widget->get_value();
-		$object->object_add_attribute($attribute1,$attribute2,$new_param_value);
-		set_gui_status($object,$status,$timeout) if (defined $status);
-	});
-	return $widget;		
+    my ($object,$attribute1,$attribute2,$content, $default,$status,$timeout)=@_;
+    my $value=$object->object_get_attribute($attribute1,$attribute2);
+    my ($min,$max,$step,$digit)=split(/\s*,\s*/,$content);
+    if(!defined $value){
+        $value=$default;
+        $object->object_add_attribute($attribute1,$attribute2,$value);
+    }
+    $value=~ s/[^0-9.\-]//g;
+    $min=~   s/[^0-9.\-]//g;
+    $max=~   s/[^0-9.\-]//g;
+    $step=~  s/[^0-9.\-]//g;
+    $digit=~ s/[^0-9.\-]//g if (defined $digit);
+    my $widget=gen_spin($min,$max,$step,$digit);
+    $widget->set_value($value);
+    $widget-> signal_connect("value_changed" => sub{
+        my $new_param_value=$widget->get_value();
+        $object->object_add_attribute($attribute1,$attribute2,$new_param_value);
+        set_gui_status($object,$status,$timeout) if (defined $status);
+    });
+    return $widget;
 }
 
-
 sub gen_check_box_object_array {
-		my ($object,$attribute1,$attribute2,$content,$default,$status,$timeout)=@_;
-    		my $value=$object->object_get_attribute($attribute1,$attribute2);
-		$value = $default if (!defined $value);
-		my $widget = def_hbox(FALSE,0);
-		my @check;
-		for (my $i=0;$i<$content;$i++){
-			$check[$i]= Gtk2::CheckButton->new;
-		}
-		for (my $i=0;$i<$content;$i++){
-			$widget->pack_end(  $check[$i], FALSE, FALSE, 0);
-			
-			my @chars = split("",$value);
-			#check if saved value match the size of check box
-			if($chars[0] ne $content ) {
-				$object->object_add_attribute($attribute1,$attribute2,$default);
-				$value=$default;
-				@chars = split("",$value);
-			}
-			#set initial value
-			
-			#print "\@chars=@chars\n";
-			for (my $i=0;$i<$content;$i++){
-				my $loc= (scalar @chars) -($i+1);
-					if( $chars[$loc] eq '1') {$check[$i]->set_active(TRUE);}
-					else {$check[$i]->set_active(FALSE);}
-			}
-
-
-			#get new value
-			$check[$i]-> signal_connect("toggled" => sub{
-				my $new_val="$content\'b";			
- 				
-				for (my $i=$content-1; $i >= 0; $i--){
-					if($check[$i]->get_active()) {$new_val="${new_val}1" ;}
-					else {$new_val="${new_val}0" ;}
-				}
-				$object->object_add_attribute($attribute1,$attribute2,$new_val);
-				#print "\$new_val=$new_val\n";
-				set_gui_status($object,$status,$timeout) if (defined $status);
-			});
-	}
-	return $widget;
-
+        my ($object,$attribute1,$attribute2,$content,$default,$status,$timeout)=@_;
+            my $value=$object->object_get_attribute($attribute1,$attribute2);
+        $value = $default if (!defined $value);
+        my $widget = def_hbox(FALSE,0);
+        my @check;
+        for (my $i=0;$i<$content;$i++){
+            $check[$i]= Gtk2::CheckButton->new;
+        }
+        for (my $i=0;$i<$content;$i++){
+            $widget->pack_end(  $check[$i], FALSE, FALSE, 0);
+            my @chars = split("",$value);
+            #check if saved value match the size of check box
+            if($chars[0] ne $content ) {
+                $object->object_add_attribute($attribute1,$attribute2,$default);
+                $value=$default;
+                @chars = split("",$value);
+            }
+            #set initial value
+            #print "\@chars=@chars\n";
+            for (my $i=0;$i<$content;$i++){
+                my $loc= (scalar @chars) -($i+1);
+                    if( $chars[$loc] eq '1') {$check[$i]->set_active(TRUE);}
+                    else {$check[$i]->set_active(FALSE);}
+            }
+            #get new value
+            $check[$i]-> signal_connect("toggled" => sub{
+                my $new_val="$content\'b";
+                for (my $i=$content-1; $i >= 0; $i--){
+                    if($check[$i]->get_active()) {$new_val="${new_val}1" ;}
+                    else {$new_val="${new_val}0" ;}
+                }
+                $object->object_add_attribute($attribute1,$attribute2,$new_val);
+                #print "\$new_val=$new_val\n";
+                set_gui_status($object,$status,$timeout) if (defined $status);
+            });
+    }
+    return $widget;
 }
 
-
-
-
-
 sub gen_check_box_object {
-		my ($object,$attribute1,$attribute2,$default,$status,$timeout)=@_;
-    		my $value=$object->object_get_attribute($attribute1,$attribute2);
-		if (!defined $value){
-			#set initial value
-			$object->object_add_attribute($attribute1,$attribute2,$default);
-			$value = $default 
-		}
-		my $widget = Gtk2::CheckButton->new;
-		if($value == 1) {$widget->set_active(TRUE);}
-		else {$widget->set_active(FALSE);}
-		
-		#get new value
-		$widget-> signal_connect("toggled" => sub{
-			my $new_val;
-			if($widget->get_active()) {$new_val=1;}
-			else {$new_val=0;}
-			$object->object_add_attribute($attribute1,$attribute2,$new_val);
-			#print "\$new_val=$new_val\n";
-			set_gui_status($object,$status,$timeout) if (defined $status);
-		});
-	
-	return $widget;
-
+        my ($object,$attribute1,$attribute2,$default,$status,$timeout)=@_;
+            my $value=$object->object_get_attribute($attribute1,$attribute2);
+        if (!defined $value){
+            #set initial value
+            $object->object_add_attribute($attribute1,$attribute2,$default);
+            $value = $default
+        }
+        my $widget = Gtk2::CheckButton->new;
+        if($value == 1) {$widget->set_active(TRUE);}
+        else {$widget->set_active(FALSE);}
+        #get new value
+        $widget-> signal_connect("toggled" => sub{
+            my $new_val;
+            if($widget->get_active()) {$new_val=1;}
+            else {$new_val=0;}
+            $object->object_add_attribute($attribute1,$attribute2,$new_val);
+            #print "\$new_val=$new_val\n";
+            set_gui_status($object,$status,$timeout) if (defined $status);
+        });
+    return $widget;
 }
 
-
-
-
-
-
 sub get_dir_in_object {
-	my ($object,$attribute1,$attribute2,$content,$status,$timeout,$default)=@_;
-	my $widget = def_hbox(FALSE,0);
-	my $value=$object->object_get_attribute($attribute1,$attribute2);
-	$object->object_add_attribute($attribute1,$attribute2,  $default) if (!defined $value );
-	$value = $default if (!defined $value );
-	if (defined $default){
-		$object->object_add_attribute($attribute1,$attribute2,  $default) if  !(-d $value );
-		$value = $default  if !(-d $value );
-	};
-	
-	my $warning;
-	
-	my $entry=gen_entry($value);
-	$entry-> signal_connect("changed" => sub{
-		my $new_param_value=$entry->get_text();
-		$object->object_add_attribute($attribute1,$attribute2,$new_param_value);
-		set_gui_status($object,$status,$timeout) if (defined $status);
-		unless (-d $new_param_value ){
-			if (!defined $warning){
-				$warning = def_icon("icons/warning.png");
-				$widget->pack_start( $warning, FALSE, FALSE, 0);
-				set_tip($warning,"$new_param_value is not a valid directory");
-				$widget->show_all;
-			}
-			
-		}else{
-			$warning->destroy if (defined $warning); 
-			undef $warning;
-			
-		}
-	
-	});
-	my $browse= get_directory_name_widget($object,undef,$entry,$attribute1,$attribute2,$status,$timeout);
-	
-	$widget->pack_start( $entry, FALSE, FALSE, 0);
-	$widget->pack_start( $browse, FALSE, FALSE, 0);
-	
-	 if(defined $value){
-		unless (-d $value ){
-		 	$warning= def_icon("icons/warning.png");	
-			$widget->pack_start( $warning, FALSE, FALSE, 0); 
-			set_tip($warning,"$value is not a valid directory path");
-		}
-	}
-	return $widget;
+    my ($object,$attribute1,$attribute2,$content,$status,$timeout,$default)=@_;
+    my $widget = def_hbox(FALSE,0);
+    my $value=$object->object_get_attribute($attribute1,$attribute2);
+    $object->object_add_attribute($attribute1,$attribute2,  $default) if (!defined $value );
+    $value = $default if (!defined $value );
+    if (defined $default){
+        $object->object_add_attribute($attribute1,$attribute2,  $default) if  !(-d $value );
+        $value = $default  if !(-d $value );
+    };
+    my $warning;
+    my $entry=gen_entry($value);
+    $entry-> signal_connect("changed" => sub{
+        my $new_param_value=$entry->get_text();
+        $object->object_add_attribute($attribute1,$attribute2,$new_param_value);
+        set_gui_status($object,$status,$timeout) if (defined $status);
+        unless (-d $new_param_value ){
+            if (!defined $warning){
+                $warning = def_icon("icons/warning.png");
+                $widget->pack_start( $warning, FALSE, FALSE, 0);
+                set_tip($warning,"$new_param_value is not a valid directory");
+                $widget->show_all;
+            }
+        }else{
+            $warning->destroy if (defined $warning);
+            undef $warning;
+        }
+    });
+    my $browse= get_directory_name_widget($object,undef,$entry,$attribute1,$attribute2,$status,$timeout);
+    $widget->pack_start( $entry, FALSE, FALSE, 0);
+    $widget->pack_start( $browse, FALSE, FALSE, 0);
+    if(defined $value){
+        unless (-d $value ){
+            $warning= def_icon("icons/warning.png");
+            $widget->pack_start( $warning, FALSE, FALSE, 0);
+            set_tip($warning,"$value is not a valid directory path");
+        }
+    }
+    return $widget;
 }
 
-
-
-
 sub get_file_name_object {
-	my ($object,$attribute1,$attribute2,$extension,$open_in)=@_;
-	my $widget = def_hbox(FALSE,0);
-	my $value=$object->object_get_attribute($attribute1,$attribute2);
-	my $label;
-	if(defined $value){
-		my ($name,$path,$suffix) = fileparse("$value",qr"\..[^.]*$");
-		$label=gen_label_in_center($name.$suffix);
-		
-	} else {
-			$label=gen_label_in_center("Selecet a file");
-			$label->set_markup("<span  foreground= 'red' ><b>No file has been selected yet</b></span>");
-	}
-	my $entry=gen_entry();
-	my $browse= get_file_name($object,undef,$entry,$attribute1,$attribute2,$extension,$label,$open_in);
-	$widget->pack_start( $label, FALSE, FALSE, 0);
-	$widget->pack_start( $browse, FALSE, FALSE, 0);
-	return $widget;
+    my ($object,$attribute1,$attribute2,$extension,$open_in)=@_;
+    my $widget = def_hbox(FALSE,0);
+    my $value=$object->object_get_attribute($attribute1,$attribute2);
+    my $label;
+    if(defined $value){
+        my ($name,$path,$suffix) = fileparse("$value",qr"\..[^.]*$");
+        $label=gen_label_in_center($name.$suffix);
+    } else {
+            $label=gen_label_in_center("Selecet a file");
+            $label->set_markup("<span  foreground= 'red' ><b>No file has been selected yet</b></span>");
+    }
+    my $entry=gen_entry();
+    my $browse= get_file_name($object,undef,$entry,$attribute1,$attribute2,$extension,$label,$open_in);
+    $widget->pack_start( $label, FALSE, FALSE, 0);
+    $widget->pack_start( $browse, FALSE, FALSE, 0);
+    return $widget;
 }
 
-
-
-
-
 sub gen_notebook {
-	my $notebook = Gtk2::Notebook->new;
-	$notebook->can_focus(FALSE);
-
-	return $notebook;
+    my $notebook = Gtk2::Notebook->new;
+    $notebook->can_focus(FALSE);
+    return $notebook;
 }
+
 ################
 # ADD info and label to widget
 ################
-
-
 sub gen_label_info{
-	my ($label_name,$widget,$info)=@_;
-	my $box = def_hbox(FALSE,0);
-	#label
-	if(defined $label_name){
-		my $label= gen_label_in_left($label_name);	
-		$box->pack_start( $label, FALSE, FALSE, 3);
-	}
-	$box->pack_start( $widget, FALSE, FALSE, 3);
-	#info	
-	if(defined $info){
-		my $button=def_image_button("icons/help.png");
-		$button->signal_connect("clicked" => sub {message_dialog($info);});	
-		$box->pack_start( $button, FALSE, FALSE, 3);
-	}
-	$box->show_all;	
-	return $box;
-}	
-
+    my ($label_name,$widget,$info)=@_;
+    my $box = def_hbox(FALSE,0);
+    #label
+    if(defined $label_name){
+        my $label= gen_label_in_left($label_name);
+        $box->pack_start( $label, FALSE, FALSE, 3);
+    }
+    $box->pack_start( $widget, FALSE, FALSE, 3);
+    #info
+    if(defined $info){
+        my $button=def_image_button("icons/help.png");
+        $button->signal_connect("clicked" => sub {message_dialog($info);});
+        $box->pack_start( $button, FALSE, FALSE, 3);
+    }
+    $box->show_all;
+    return $box;
+}
 
 ############
 #
 ###########
-
 sub gen_MenuBar{
-	my ($window,@menu_items)=@_;
- 	my $accel_group = Gtk2::AccelGroup->new;
+    my ($window,@menu_items)=@_;
+    my $accel_group = Gtk2::AccelGroup->new;
     my $item_factory = Gtk2::ItemFactory->new ("Gtk2::MenuBar", "<main>",$accel_group);
-	$window->add_accel_group ($accel_group);   
+    $window->add_accel_group ($accel_group);
     # Set up item factory to go away with the window
     $window->{'<main>'} = $item_factory;
     # create menu items
@@ -1681,43 +1414,39 @@ sub gen_MenuBar{
 }
 
 sub creating_detachable_toolbar{
-	my @attachments=@_;
-	
-	#The handle box helps in creating a detachable toolbar 
-	my $hb = Gtk2::HandleBox->new;
-	#create a toolbar, and do some initial settings
-	my $toolbar = Gtk2::Toolbar->new;
-	$toolbar->set_icon_size ('small-toolbar');	
-	$toolbar->set_show_arrow (FALSE);
-	foreach my $p (@attachments){
-		$toolbar->insert($p,-1);
-		
-	}
-	$hb->add($toolbar);	
-	return $hb;
+    my @attachments=@_;
+    #The handle box helps in creating a detachable toolbar
+    my $hb = Gtk2::HandleBox->new;
+    #create a toolbar, and do some initial settings
+    my $toolbar = Gtk2::Toolbar->new;
+    $toolbar->set_icon_size ('small-toolbar');
+    $toolbar->set_show_arrow (FALSE);
+    foreach my $p (@attachments){
+        $toolbar->insert($p,-1);
+    }
+    $hb->add($toolbar);
+    return $hb;
 }
 
 sub gui_quite{
-	Gtk2->main_quit;
+    Gtk2->main_quit;
 }
 
 sub gtk_gui_run{
-	my ($main)=@_;
-	Gtk2->init;
-	&$main;
-	Gtk2->main();
-	return 1;
+    my ($main)=@_;
+    Gtk2->init;
+    &$main;
+    Gtk2->main();
+    return 1;
 }
 
-
 sub refresh_gui{
-	while (Gtk2->events_pending) {
-      Gtk2->main_iteration;
+    while (Gtk2->events_pending) {
+    Gtk2->main_iteration;
     }
     Gtk2::Gdk->flush;
 }
 
-
 sub about {
     my $version=shift;
     my $about = Gtk2::AboutDialog->new;
@@ -1728,358 +1457,269 @@ sub about {
     $about->set_program_name('ProNoC');
     my $pixbuf = Gtk2::Gdk::Pixbuf->new_from_file_at_scale("icons/ProNoC.png",50,50,FALSE);
     $about->set_logo($pixbuf);
-
     $about->set_license(
-                 "This program is free software; you can redistribute it\n"
+                "This program is free software; you can redistribute it\n"
                 . "and/or modify it under the terms of the GNU General \n"
-		. "Public License as published by the Free Software \n"
-		. "Foundation; either version 1, or (at your option)\n"
-		. "any later version.\n\n"
-                 
+        . "Public License as published by the Free Software \n"
+        . "Foundation; either version 1, or (at your option)\n"
+        . "any later version.\n\n"
         );
-	# Add the Hide action to the 'Close' button in the AboutDialog():
+    # Add the Hide action to the 'Close' button in the AboutDialog():
     $about->signal_connect('response' => sub { $about->hide; });
-
-
     $about->run;
     $about->destroy;
     return;
 }
 
-
-
 ############
 #  list_store
 ###########
-
 sub gen_list_store {
-	my ($dref,$clmn_type_ref, $clmn_lables_ref)=@_;
-	
-	
-#		my @data = (
-#  {0 => "Average distance",  1 =>"$avg"}, 
-#  {0 => "Max distance",  1 =>"$max" },  
-#  {0 => "Min distance",1 => "$min"},    
+    my ($dref,$clmn_type_ref, $clmn_lables_ref)=@_;
+#        my @data = (
+#  {0 => "Average distance",  1 =>"$avg"},
+#  {0 => "Max distance",  1 =>"$max" },
+#  {0 => "Min distance",1 => "$min"},
 #  {0 => "Normlized data per hop", 1 =>"$norm" }
 #  );
-
 # my @clmn_type = (#'Glib::Boolean', # => G_TYPE_BOOLEAN
 #                                    #'Glib::Uint',    # => G_TYPE_UINT
 #                                    'Glib::String',  # => G_TYPE_STRING
 #                                  'Glib::String'); # you get the idea
-
-	
-	my @data = @{$dref};	
-	my @clmn_type = @{$clmn_type_ref}; 	
-	my @clmn_lables= @{$clmn_lables_ref};
-	
-   
+    my @data = @{$dref};
+    my @clmn_type = @{$clmn_type_ref};
+    my @clmn_lables= @{$clmn_lables_ref};
     # create list store
     my $store = Gtk2::ListStore->new ( @clmn_type);
-   
-
-	# add data to the list store
-	foreach my $d (@data) {
-		my $iter = $store->append;
-		my @clmns = sort keys %{$d};
-		my @a=($iter);
-	  	foreach my $c (@clmns){
-	  		push (@a,($c,$d->{$c}));
-			
-	  	}
-     	$store->set (@a);   
-     	
- 	}
-  
-
+    # add data to the list store
+    foreach my $d (@data) {
+        my $iter = $store->append;
+        my @clmns = sort keys %{$d};
+        my @a=($iter);
+        foreach my $c (@clmns){
+            push (@a,($c,$d->{$c}));
+        }
+        $store->set (@a);
+    }
     my $treeview = Gtk2::TreeView->new ($store);
     $treeview->set_rules_hint (TRUE);
-	$treeview->set_search_column (1);
+    $treeview->set_search_column (1);
     my $renderer = Gtk2::CellRendererToggle->new;
     $renderer->signal_connect (toggled => \&fixed_toggled, $store);
-
-
-	# column for severities
-	my $c=0;
-	foreach my $l (@clmn_lables){
-		$renderer = Gtk2::CellRendererText->new;
-		my $column = Gtk2::TreeViewColumn->new_with_attributes ("$l",
-							       $renderer,
-							       text => $c );
-		$column->set_sort_column_id ($c );
-		$treeview->append_column ($column);
-		$c++;
-	}
- 
-	
-	return $treeview;
+    # column for severities
+    my $c=0;
+    foreach my $l (@clmn_lables){
+        $renderer = Gtk2::CellRendererText->new;
+        my $column = Gtk2::TreeViewColumn->new_with_attributes (
+            "$l",
+            $renderer,
+            text => $c );
+        $column->set_sort_column_id ($c );
+        $treeview->append_column ($column);
+        $c++;
+    }
+    return $treeview;
 }
 
-
-
-
-
 ##############
-#	create tree
+#    create tree
 ##############
-
-
 sub create_tree_model_network_maker{
-	my $model = Gtk2::TreeStore->new ('Glib::String', 'Glib::String', 'Glib::Scalar', 'Glib::Boolean');
-	my $tree_view = Gtk2::TreeView->new;
-	$tree_view->set_model ($model);
-	my $selection = $tree_view->get_selection;
-	$selection->set_mode ("single");
-	my $cell = Gtk2::CellRendererText->new;
-	$cell->set ('style' => 'italic');
-	my $column = Gtk2::TreeViewColumn->new_with_attributes ("select", $cell, 'text' => 0, 'style_set' => 3);
-	return ($model,$tree_view,$column);
+    my $model = Gtk2::TreeStore->new ('Glib::String', 'Glib::String', 'Glib::Scalar', 'Glib::Boolean');
+    my $tree_view = Gtk2::TreeView->new;
+    $tree_view->set_model ($model);
+    my $selection = $tree_view->get_selection;
+    $selection->set_mode ("single");
+    my $cell = Gtk2::CellRendererText->new;
+    $cell->set ('style' => 'italic');
+    my $column = Gtk2::TreeViewColumn->new_with_attributes ("select", $cell, 'text' => 0, 'style_set' => 3);
+    return ($model,$tree_view,$column);
 }
 
-
 sub treemodel_next_iter{
-	my 	($child , $tree_model)=@_;
-	return $tree_model->iter_next ($child);
+    my     ($child , $tree_model)=@_;
+    return $tree_model->iter_next ($child);
 }
-
-
-
-
-
-
-
-
-
-
-
-
-
 # clean names for column numbers.
 use constant DISPLAY_COLUMN    => 0;
 use constant CATRGORY_COLUMN    => 1;
 use constant MODULE_COLUMN     => 2;
 use constant ITALIC_COLUMN   => 3;
 use constant NUM_COLUMNS     => 4;
-
 sub create_tree {
-   my ($self,$label,$info,$tree_ref,$row_selected_func,$row_activated_func)=@_;
-   my %tree_in = %{$tree_ref};
-   my $model = Gtk2::TreeStore->new ('Glib::String', 'Glib::String', 'Glib::Scalar', 'Glib::Boolean');
-   my $tree_view = Gtk2::TreeView->new;
-   $tree_view->set_model ($model);
-   my $selection = $tree_view->get_selection;
-   $selection->set_mode ('browse');   
- 
-   
-
-   foreach my $p (sort keys %tree_in)
-   {
-  
-	my @modules= @{$tree_in{$p}};
-	#my @dev_entry=  @{$tree_entry{$p}}; 	
-	my $iter = $model->append (undef);
-	$model->set ($iter,
-                   DISPLAY_COLUMN,    $p,
-                   CATRGORY_COLUMN, $p || '',
-                   MODULE_COLUMN,     0     || '',
-                   ITALIC_COLUMN,   FALSE);
-
-	next unless  @modules;
-	
-	foreach my $v ( @modules){
-		 my $child_iter = $model->append ($iter);
-		 my $entry= '';
-		
-         	$model->set ($child_iter,
-			DISPLAY_COLUMN,    $v,
-                   	CATRGORY_COLUMN, $p|| '',
-                   	MODULE_COLUMN,     $v     || '',
-                   	ITALIC_COLUMN,   FALSE);
-      	}	
-	
-
-
-   }
-	
-   my $cell = Gtk2::CellRendererText->new;
-   $cell->set ('style' => 'italic');
-   my $column = Gtk2::TreeViewColumn->new_with_attributes
- 					("$label",
-                                        $cell,
-                                        'text' => DISPLAY_COLUMN,
-                                        'style_set' => ITALIC_COLUMN);
-
-	$tree_view->append_column ($column);
-	my @ll=($model,$info);
-   #row selected
-	$selection->signal_connect (changed =>sub {
-	my ($selection, $ref) = @_;
-	my ($model,$info)=@{$ref};
-	my $iter = $selection->get_selected;
-  	return unless defined $iter;
-
-  	my ($category) = $model->get ($iter, CATRGORY_COLUMN);
-  	my ($module) = $model->get ($iter,MODULE_COLUMN );
-  	$row_selected_func->($self,$category,$module,$info) if(defined $row_selected_func);
-  
-
-
-}, \@ll);
-
-#  row_activated 
-  $tree_view->signal_connect (row_activated => sub{
-
-	my ($tree_view, $path, $column) = @_;
-	my $model = $tree_view->get_model;
-	my $iter = $model->get_iter ($path);
-	my ($category) = $model->get ($iter, CATRGORY_COLUMN);
-  	my ($module) = $model->get ($iter,MODULE_COLUMN );
-	
-
-	if($module){ 
-		#print "$module  is selected via row activaton!\n";
-		$row_activated_func->($self,$category,$module,$info) if(defined $row_activated_func);
-		#add_module_to_soc($soc,$ip,$category,$module,$info);
-			
-	}
-
-}, \@ll);
-
-  #$tree_view->expand_all;
-
-  my $scrolled_window = Gtk2::ScrolledWindow->new;
-  $scrolled_window->set_policy ('automatic', 'automatic');
-  $scrolled_window->set_shadow_type ('in');
-  $scrolled_window->add($tree_view);
-
-  my $hbox = Gtk2::HBox->new (FALSE, 0);
-  $hbox->pack_start ( $scrolled_window, TRUE, TRUE, 0); 
-
-  return $hbox;
+    my ($self,$label,$info,$tree_ref,$row_selected_func,$row_activated_func)=@_;
+    my %tree_in = %{$tree_ref};
+    my $model = Gtk2::TreeStore->new ('Glib::String', 'Glib::String', 'Glib::Scalar', 'Glib::Boolean');
+    my $tree_view = Gtk2::TreeView->new;
+    $tree_view->set_model ($model);
+    my $selection = $tree_view->get_selection;
+    $selection->set_mode ('browse');
+    foreach my $p (sort keys %tree_in)
+    {
+    my @modules= @{$tree_in{$p}};
+    #my @dev_entry=  @{$tree_entry{$p}};
+    my $iter = $model->append (undef);
+    $model->set (
+        $iter,
+        DISPLAY_COLUMN,    $p,
+        CATRGORY_COLUMN, $p || '',
+        MODULE_COLUMN,     0     || '',
+        ITALIC_COLUMN,   FALSE);
+    next unless  @modules;
+    foreach my $v ( @modules){
+        my $child_iter = $model->append ($iter);
+        my $entry= '';
+            $model->set ($child_iter,
+            DISPLAY_COLUMN,    $v,
+            CATRGORY_COLUMN, $p|| '',
+            MODULE_COLUMN,     $v     || '',
+            ITALIC_COLUMN,   FALSE);
+        }
+    }
+    my $cell = Gtk2::CellRendererText->new;
+    $cell->set ('style' => 'italic');
+    my $column = Gtk2::TreeViewColumn->new_with_attributes (
+        "$label",
+        $cell,
+        'text' => DISPLAY_COLUMN,
+        'style_set' => ITALIC_COLUMN);
+    $tree_view->append_column ($column);
+    my @ll=($model,$info);
+    #row selected
+    $selection->signal_connect (changed =>sub {
+        my ($selection, $ref) = @_;
+        my ($model,$info)=@{$ref};
+        my $iter = $selection->get_selected;
+        return unless defined $iter;
+        my ($category) = $model->get ($iter, CATRGORY_COLUMN);
+        my ($module) = $model->get ($iter,MODULE_COLUMN );
+        $row_selected_func->($self,$category,$module,$info) if(defined $row_selected_func);
+    }, \@ll);
+    #  row_activated
+    $tree_view->signal_connect (row_activated => sub{
+        my ($tree_view, $path, $column) = @_;
+        my $model = $tree_view->get_model;
+        my $iter = $model->get_iter ($path);
+        my ($category) = $model->get ($iter, CATRGORY_COLUMN);
+        my ($module) = $model->get ($iter,MODULE_COLUMN );
+        if($module){
+            #print "$module  is selected via row activaton!\n";
+            $row_activated_func->($self,$category,$module,$info) if(defined $row_activated_func);
+            #add_module_to_soc($soc,$ip,$category,$module,$info);
+        }
+    }, \@ll);
+    #$tree_view->expand_all;
+    my $scrolled_window = Gtk2::ScrolledWindow->new;
+    $scrolled_window->set_policy ('automatic', 'automatic');
+    $scrolled_window->set_shadow_type ('in');
+    $scrolled_window->add($tree_view);
+    my $hbox = Gtk2::HBox->new (FALSE, 0);
+    $hbox->pack_start ( $scrolled_window, TRUE, TRUE, 0);
+    return $hbox;
 }
 
-
 sub row_activated_cb{
-	 my ($tree_view, $path, $column) = @_;
-	 my $model = $tree_view->get_model;
-	 my $iter = $model->get_iter ($path);
-	 my ($category) = $model->get ($iter, DISPLAY_COLUMN);
-  	 my ($module) = $model->get ($iter, CATRGORY_COLUMN);
-
+    my ($tree_view, $path, $column) = @_;
+    my $model = $tree_view->get_model;
+    my $iter = $model->get_iter ($path);
+    my ($category) = $model->get ($iter, DISPLAY_COLUMN);
+    my ($module) = $model->get ($iter, CATRGORY_COLUMN);
 }
 
-
-
 sub file_edit_tree {
-	my $tree_store = Gtk2::TreeStore->new('Glib::String', 'Glib::String');
-	my $tree_view = Gtk2::TreeView->new($tree_store);
-	my $column = Gtk2::TreeViewColumn->new_with_attributes('Double-click to open', Gtk2::CellRendererText->new(), text => "0");
-	$tree_view->append_column($column);
-	$tree_view->set_headers_visible(TRUE);
-	return ($tree_store,$tree_view);
+    my $tree_store = Gtk2::TreeStore->new('Glib::String', 'Glib::String');
+    my $tree_view = Gtk2::TreeView->new($tree_store);
+    my $column = Gtk2::TreeViewColumn->new_with_attributes('Double-click to open', Gtk2::CellRendererText->new(), text => "0");
+    $tree_view->append_column($column);
+    $tree_view->set_headers_visible(TRUE);
+    return ($tree_store,$tree_view);
 }
 
 ##########
 #  run external commands
 ##########
-
-
-
 sub run_cmd_in_back_ground
 {
-  my $command = shift;
-  #print "\t$command\n";
- 
-  ### Start running the Background Job:
+    my $command = shift;
+    #print "\t$command\n";
+    ### Start running the Background Job:
     my $proc = Proc::Background->new($command);
     my $PID = $proc->pid;
     my $start_time = $proc->start_time;
     my $alive = $proc->alive;
-
-  ### While $alive is NOT '0', then keep checking till it is...
-  #  *When $alive is '0', it has finished executing.
-  while($alive ne 0)
-  {
-    $alive = $proc->alive;
-
-    # This while loop will cause Gtk2 to continue processing events, if
-    # there are events pending... *which there are...
-    while (Gtk2->events_pending) {
-      Gtk2->main_iteration;
-    }
+    ### While $alive is NOT '0', then keep checking till it is...
+    #  *When $alive is '0', it has finished executing.
+    while($alive ne 0)
+    {
+        $alive = $proc->alive;
+        # This while loop will cause Gtk2 to continue processing events, if
+        # there are events pending... *which there are...
+        while (Gtk2->events_pending) {
+            Gtk2->main_iteration;
+        }
     Gtk2::Gdk->flush;
-
     usleep(1000);
-  }
-  
-  my $end_time = $proc->end_time;
- # print "*Command Completed at $end_time, with PID = $PID\n\n";
-
-  # Since the while loop has exited, the BG job has finished running:
-  # so close the pop-up window...
- # $popup_window->hide;
-
-  # Get the RETCODE from the Background Job using the 'wait' method
-  my $retcode = $proc->wait;
-  $retcode /= 256;
-
-  #print "\t*RETCODE == $retcode\n\n";
-  Gtk2::Gdk->flush;
-  ### Check if the RETCODE returned with an Error:
-  if ($retcode ne 0) {
+    }
+    my $end_time = $proc->end_time;
+    # print "*Command Completed at $end_time, with PID = $PID\n\n";
+    # Since the while loop has exited, the BG job has finished running:
+    # so close the pop-up window...
+    # $popup_window->hide;
+    # Get the RETCODE from the Background Job using the 'wait' method
+    my $retcode = $proc->wait;
+    $retcode /= 256;
+    #print "\t*RETCODE == $retcode\n\n";
+    Gtk2::Gdk->flush;
+    ### Check if the RETCODE returned with an Error:
+    if ($retcode ne 0) {
     print "Error: The Background Job ($command) returned with an Error...!\n";
     return 1;
-  } else {
+    } else {
     #print "Success: The Background Job Completed Successfully...!\n";
     return 0;
-  }
-	
+    }
 }
 
 sub run_cmd_in_back_ground_get_stdout
 {
-	my $cmd=shift;
-	my $exit;
-	my ($stdout, $stderr);
-	STDOUT->flush();
-	STDERR->flush();
-	capture { $exit=run_cmd_in_back_ground($cmd) } \$stdout, \$stderr;
-	return ($stdout,$exit,$stderr);
-	
-}		
-	
-sub run_cmd_message_dialog_errors{
-	my ($cmd)=@_;
-	my ($stdout,$exit,$stderr)=run_cmd_in_back_ground_get_stdout($cmd);
-	if(length $stderr>1){			
-		message_dialog("$stderr\n",'error');
-		return 1;
-	}if($exit){
-		message_dialog("Error $cmd failed: $stdout\n",'error');
-		return 1;		
-	}
-	return 0;
-	
+    my $cmd=shift;
+    my $exit;
+    my ($stdout, $stderr);
+    STDOUT->flush();
+    STDERR->flush();
+    capture { $exit=run_cmd_in_back_ground($cmd) } \$stdout, \$stderr;
+    return ($stdout,$exit,$stderr);
 }
 
+sub run_cmd_message_dialog_errors{
+    my ($cmd)=@_;
+    my ($stdout,$exit,$stderr)=run_cmd_in_back_ground_get_stdout($cmd);
+    if(length $stderr>1){
+        message_dialog("$stderr\n",'error');
+        return 1;
+    }if($exit){
+        message_dialog("Error $cmd failed: $stdout\n",'error');
+        return 1;
+    }
+    return 0;
+}
 
 sub run_cmd_textview_errors{
-	my ($cmd,$tview)=@_;
-	my ($stdout,$exit,$stderr)=run_cmd_in_back_ground_get_stdout($cmd);
-	if(length $stderr>1){			
-		add_colored_info($tview,"Error: $stderr\n",'red');
-		add_colored_info($tview,"$cmd did not run successfully!\n",'red');
-		return undef;
-	}
-	if($exit){
-		add_colored_info($tview,"Error:$stdout\n",'red');
-		add_colored_info($tview,"$cmd did not run successfully!\n",'red');
-		return undef;
-	}
-	$stdout = "" if (!defined $stdout);
-	return 	$stdout
-}	
-
+    my ($cmd,$tview)=@_;
+    my ($stdout,$exit,$stderr)=run_cmd_in_back_ground_get_stdout($cmd);
+    if(length $stderr>1){
+        add_colored_info($tview,"Error: $stderr\n",'red');
+        add_colored_info($tview,"$cmd did not run successfully!\n",'red');
+        return undef;
+    }
+    if($exit){
+        add_colored_info($tview,"Error:$stdout\n",'red');
+        add_colored_info($tview,"$cmd did not run successfully!\n",'red');
+        return undef;
+    }
+    $stdout = "" if (!defined $stdout);
+    return     $stdout
+}
 
 sub create_iconview_model {
 #----------------------------------------------------
@@ -2089,90 +1729,63 @@ sub create_iconview_model {
 #text of the icon, and the last for the icon self----
 #Gtk2::ListStore is ideal for this ------------------
 #----------------------------------------------------
-	my ($self,$name,$ref)=@_;
-	my @sources= (defined $ref)? @{$ref}:(); 
+    my ($self,$name,$ref)=@_;
+    my @sources= (defined $ref)? @{$ref}:();
     my $list_store = Gtk2::ListStore->new(qw/Glib::String Gtk2::Gdk::Pixbuf Glib::String/);
-
     #******************************************************
     #we populate the Gtk2::ListStore with Gtk2::Stock icons
     #******************************************************
-
- 
-
     foreach my $val(@sources){
         #get the iconset from the icon_factory
         #my $iconset = $icon_factory->lookup_default($val);
         #try and extract the icon from it
         add_icon_to_tree($self,$name,$list_store,$val);
     }
-
     return $list_store;
 }
 
 ####################
-#	SourceView
+#    SourceView
 ####################
-
-sub	gen_SourceView_with_buffer{
-	return Gtk2::SourceView2::View->new_with_buffer(@_);
+sub    gen_SourceView_with_buffer{
+    return Gtk2::SourceView2::View->new_with_buffer(@_);
 }
 
-
-
-
-
 sub create_SourceView_buffer {
-	my $self = shift;
-	my $tags = Gtk2::TextTagTable->new();
-
-	add_tag_to_SourceView($tags, search => {
-			background => 'yellow',
-	});
-	add_tag_to_SourceView($tags, goto_line => {
-			'paragraph-background' => 'orange',
-	});
-
-	my $buffer = Gtk2::SourceView2::Buffer->new($tags);
-	$buffer->signal_connect('notify::cursor-position' => sub {
-		$self->clear_highlighted();
-	});
-
-	return $buffer;
+    my $self = shift;
+    my $tags = Gtk2::TextTagTable->new();
+    add_tag_to_SourceView($tags, search => {
+            background => 'yellow',
+    });
+    add_tag_to_SourceView($tags, goto_line => {
+            'paragraph-background' => 'orange',
+    });
+    my $buffer = Gtk2::SourceView2::Buffer->new($tags);
+    $buffer->signal_connect('notify::cursor-position' => sub {
+        $self->clear_highlighted();
+    });
+    return $buffer;
 }
 
-
 sub add_tag_to_SourceView {
-	my ($tags, $name, $properties) = @_;
-
-	my $tag = Gtk2::TextTag->new($name);
-	$tag->set(%{ $properties });
-	$tags->add($tag);
+    my ($tags, $name, $properties) = @_;
+    my $tag = Gtk2::TextTag->new($name);
+    $tag->set(%{ $properties });
+    $tags->add($tag);
 }
 
-
 sub detect_language {
-	my $self = shift;
-	my ($filename) = @_;
-
-	# Guess the programming language of the file
-	my $manager = Gtk2::SourceView2::LanguageManager->get_default;
-	my $language = $manager->guess_language($filename);
-	$self->buffer->set_language($language);
+    my $self = shift;
+    my ($filename) = @_;
+    # Guess the programming language of the file
+    my $manager = Gtk2::SourceView2::LanguageManager->get_default;
+    my $language = $manager->guess_language($filename);
+    $self->buffer->set_language($language);
 }
 
-
-
-sub get_pressed_key{ 
-	my $event=shift;
-	
-	my $key = Gtk2::Gdk->keyval_name( $event->keyval );
-	return $key;
+sub get_pressed_key{
+    my $event=shift;
+    my $key = Gtk2::Gdk->keyval_name( $event->keyval );
+    return $key;
 }
-
-
-
-
-
-
-
-1
+1;
\ No newline at end of file
diff --git a/mpsoc/perl_gui/lib/perl/widget3.pl b/mpsoc/perl_gui/lib/perl/widget3.pl
index 5792501..03a7b79 100755
--- a/mpsoc/perl_gui/lib/perl/widget3.pl
+++ b/mpsoc/perl_gui/lib/perl/widget3.pl
@@ -2,1872 +2,1551 @@
 use Gtk3;
 use strict;
 use warnings;
-
 use FindBin;
 use lib $FindBin::Bin;
-
 use Data::Dumper;
 use Gtk3::SourceView;
 use Consts;
-
-require "common.pl"; 
-
-
+require "common.pl";
 use IO::CaptureOutput qw(capture qxx qxy);
-
+use File::Temp qw/tempfile/;
 #use ColorButton;
 use HexSpin3;
-
 #use Tk::Animation;
-
 our %glob_setting;
 
 ##############
 # combo box
 #############
 sub gen_combo{
-	my ($combo_list, $combo_active_pos)= @_;
-	my $combo = Gtk3::ComboBoxText->new();
-	
-	combo_set_names($combo,$combo_list);
-	$combo->set_active($combo_active_pos) if(defined $combo_active_pos);
-	
-	#my $font = Gtk3::Pango::FontDescription->from_string('Tahoma 5');
-	#$combo->modify_font($font);
-
-	
-	return $combo;	
+    my ($combo_list, $combo_active_pos)= @_;
+    my $combo = Gtk3::ComboBoxText->new();
+    combo_set_names($combo,$combo_list);
+    $combo->set_active($combo_active_pos) if(defined $combo_active_pos);
+    #my $font = Gtk3::Pango::FontDescription->from_string('Tahoma 5');
+    #$combo->modify_font($font);
+    return $combo;
 }
 
-
 sub combo_set_names {
-	my ( $combo, $list_ref ) = @_;
-	my @list=@{$list_ref};
-	#print "$list[0]\n";
-	for my $item (@list){$combo->append_text($item);}
+    my ( $combo, $list_ref ) = @_;
+    my @list=@{$list_ref};
+    #print "$list[0]\n";
+    for my $item (@list){$combo->append_text($item);}
 }
 
-
 sub gen_combo_help {
-	my ($help, @combo_list, $pos)= @_;
-	my $box = def_hbox(FALSE, 0);
-	my $combo= gen_combo(@combo_list, $pos);
-	my $button=def_image_button("icons/help.png");
-		
-	$button->signal_connect("clicked" => sub {message_dialog($help);});
-			
-	$box->pack_start( $combo, FALSE, FALSE, 3);
-	$box->pack_start( $button, FALSE, FALSE, 3);
-	$box->show_all;
-	
-	return ($box,$combo);
-}
-
-	
+    my ($help, @combo_list, $pos)= @_;
+    my $box = def_hbox(FALSE, 0);
+    my $combo= gen_combo(@combo_list, $pos);
+    my $button=def_image_button("icons/help.png");
+    $button->signal_connect("clicked" => sub {message_dialog($help);});
+    $box->pack_start( $combo, FALSE, FALSE, 3);
+    $box->pack_start( $button, FALSE, FALSE, 3);
+    $box->show_all;
+    return ($box,$combo);
+}
+
 sub def_h_labeled_combo{
-		my ($label_name,$combo_list,$combo_active_pos)=@_;
-		my $box = def_hbox(TRUE,0);
-		my $label= gen_label_in_left($label_name);	
-		my $combo= gen_combo($combo_list, $combo_active_pos);
-		$box->pack_start( $label, FALSE, FALSE, 3);
-		$box->pack_start( $combo, FALSE, TRUE, 3);
-		return ($box,$combo);
-}	
+        my ($label_name,$combo_list,$combo_active_pos)=@_;
+        my $box = def_hbox(TRUE,0);
+        my $label= gen_label_in_left($label_name);
+        my $combo= gen_combo($combo_list, $combo_active_pos);
+        $box->pack_start( $label, FALSE, FALSE, 3);
+        $box->pack_start( $combo, FALSE, TRUE, 3);
+        return ($box,$combo);
+}
 
 sub def_h_labeled_combo_scaled{
-		my ($label_name,$combo_list,$combo_active_pos,$label_w,$comb_w)=@_;
-		my $table= def_table(1,3,TRUE);
-		my $label= gen_label_in_left($label_name);	
-		my $combo= gen_combo($combo_list, $combo_active_pos);
-		$table->attach_defaults ($label, 0, $label_w, 0, 1);
-		$table->attach_defaults ($combo, 1, $label_w+$comb_w, 0, 1);
-		return ($table,$combo);
-}	
-
+        my ($label_name,$combo_list,$combo_active_pos,$label_w,$comb_w)=@_;
+        my $table= def_table(1,3,TRUE);
+        my $label= gen_label_in_left($label_name);
+        my $combo= gen_combo($combo_list, $combo_active_pos);
+        $table->attach_defaults ($label, 0, $label_w, 0, 1);
+        $table->attach_defaults ($combo, 1, $label_w+$comb_w, 0, 1);
+        return ($table,$combo);
+}
 
 sub gen_combo_model{
-	my $ref=shift;
-	my %inputs=%{$ref};
-	my $store = Gtk3::TreeStore->new('Glib::String');
-  	 for my $i (sort { $a cmp $b} keys %inputs ) {
-    	 	my $iter = $store->append(undef);
-		
-    	 	$store->set($iter, 0, $i);
-    		for my $capital (sort { $a cmp $b} keys %{$inputs{$i}}) {
-      			my $iter2 = $store->append($iter);
-       			$store->set($iter2, 0, $capital);
-    		}
- 	}
-	return $store;
-
+    my $ref=shift;
+    my %inputs=%{$ref};
+    my $store = Gtk3::TreeStore->new('Glib::String');
+    for my $i (sort { $a cmp $b} keys %inputs ) {
+        my $iter = $store->append(undef);
+        $store->set($iter, 0, $i);
+        for my $capital (sort { $a cmp $b} keys %{$inputs{$i}}) {
+            my $iter2 = $store->append($iter);
+            $store->set($iter2, 0, $capital);
+        }
+    }
+    return $store;
 }
 
 sub gen_tree_combo{
-	my $model=shift;
-	my $combo = Gtk3::ComboBox->new_with_model($model);
-   	my $renderer = Gtk3::CellRendererText->new();
-    	$combo->pack_start($renderer, TRUE);
-    	$combo->set_attributes($renderer, "text", 0);
-    	$combo->set_cell_data_func($renderer, \&is_capital_sensitive);
-	return $combo;
-
+    my $model=shift;
+    my $combo = Gtk3::ComboBox->new_with_model($model);
+    my $renderer = Gtk3::CellRendererText->new();
+    $combo->pack_start($renderer, TRUE);
+    $combo->set_attributes($renderer, "text", 0);
+    $combo->set_cell_data_func($renderer, \&is_capital_sensitive);
+    return $combo;
 }
 
-
 sub TreePath_new_from_indices {
-	 my @indices =@_;
-	 my $path = Gtk3::TreePath->new_from_indices(@indices);
-	 return $path;
-
+    my @indices =@_;
+    my $path = Gtk3::TreePath->new_from_indices(@indices);
+    return $path;
 }
 
-
 ##############
 # spin button
 #############
 sub gen_spin{
-	my ($min,$max,$step,$digit)= @_;
-	
-	return Gtk3::SpinButton->new_with_range ($min, $max, $step);
-	 if(!defined $digit){
-		my $d1 = get_float_precision($min);
-		my $d2 = get_float_precision($max);
-		my $d3 = get_float_precision($step);
-		$digit = ($d1 >$d2)? $d1 : $d2;
-		$digit = $d3 if($d3>$digit);				
-	}
-	print "($min,$max,$step,$digit)\n";	
-	return Gtk3::SpinButton->new_with_range ($min, $max, $step) if($digit ==0);
-    return gen_spin_float($min,$max,$step,$digit);	
+    my ($min,$max,$step,$digit)= @_;
+    return Gtk3::SpinButton->new_with_range ($min, $max, $step);
+    if(!defined $digit){
+        my $d1 = get_float_precision($min);
+        my $d2 = get_float_precision($max);
+        my $d3 = get_float_precision($step);
+        $digit = ($d1 >$d2)? $d1 : $d2;
+        $digit = $d3 if($d3>$digit);
+    }
+    print "($min,$max,$step,$digit)\n";
+    return Gtk3::SpinButton->new_with_range ($min, $max, $step) if($digit ==0);
+    return gen_spin_float($min,$max,$step,$digit);
 }
 
 sub get_float_precision{
-	my $num=shift; 
-	my $digit = length(($num =~ /\.(.*)/)[0]);
-	$digit=0 if(!defined $digit);
-	return $digit;
+    my $num=shift;
+    my $digit = length(($num =~ /\.(.*)/)[0]);
+    $digit=0 if(!defined $digit);
+    return $digit;
 }
 
 sub gen_spin_float{
-	my ($min,$max,$step,$digit)= @_;
-	#$page_inc = ($max - $min)/ 
-	my $adj = Gtk3::Adjustment->new (0, $min, $max, $step,3.1, 0);	
-	my $spinner = Gtk3::SpinButton->new ($adj, 1.0,$digit);
-	return $spinner; 
+    my ($min,$max,$step,$digit)= @_;
+    #$page_inc = ($max - $min)/
+    my $adj = Gtk3::Adjustment->new (0, $min, $max, $step,3.1, 0);
+    my $spinner = Gtk3::SpinButton->new ($adj, 1.0,$digit);
+    return $spinner;
 }
 
-
 sub gen_spin_help {
-	my ($help, $min,$max,$step,$digit)= @_;
-	my $box = def_hbox(FALSE, 0);
-	my $spin= gen_spin($min,$max,$step,$digit);
-	my $button=def_image_button("icons/help.png");
-		
-	$button->signal_connect("clicked" => sub {message_dialog($help);});
-			
-	$box->pack_start( $spin, FALSE, FALSE, 3);
-	$box->pack_start( $button, FALSE, FALSE, 3);
-	$box->show_all;
-	
-	return ($box,$spin);
+    my ($help, $min,$max,$step,$digit)= @_;
+    my $box = def_hbox(FALSE, 0);
+    my $spin= gen_spin($min,$max,$step,$digit);
+    my $button=def_image_button("icons/help.png");
+    $button->signal_connect("clicked" => sub {message_dialog($help);});
+    $box->pack_start( $spin, FALSE, FALSE, 3);
+    $box->pack_start( $button, FALSE, FALSE, 3);
+    $box->show_all;
+    return ($box,$spin);
 }
 
-
 #############
 #  entry
 #############
 sub gen_entry{
-	my ($initial) = @_;
-	my $entry = Gtk3::Entry->new;
-	if(defined $initial){ $entry->set_text($initial)};
-	return $entry;
+    my ($initial) = @_;
+    my $entry = Gtk3::Entry->new;
+    if(defined $initial){ $entry->set_text($initial)};
+    return $entry;
 }
 
-
 sub gen_entry_new_with_max_length{
-	my ($n,$initial) = @_;
-	my $entry = Gtk3::Entry->new ();
-	$entry->set_max_length($n);
-	if(defined $initial){ $entry->set_text($initial)};
-	return $entry;
+    my ($n,$initial) = @_;
+    my $entry = Gtk3::Entry->new ();
+    $entry->set_max_length($n);
+    if(defined $initial){ $entry->set_text($initial)};
+    return $entry;
 }
 
-
-
 sub gen_entry_help{
-	my ($help, $init)= @_;
-	my $box = def_hbox(FALSE, 0);
-	my $entry= gen_entry ($init);
-	my $button=def_image_button("icons/help.png");
-		
-	$button->signal_connect("clicked" => sub {message_dialog($help);});
-			
-	$box->pack_start( $entry, FALSE, FALSE, 3);
-	$box->pack_start( $button, FALSE, FALSE, 3);
-	$box->show_all;
-	
-	return ($box,$entry);
+    my ($help, $init)= @_;
+    my $box = def_hbox(FALSE, 0);
+    my $entry= gen_entry ($init);
+    my $button=def_image_button("icons/help.png");
+    $button->signal_connect("clicked" => sub {message_dialog($help);});
+    $box->pack_start( $entry, FALSE, FALSE, 3);
+    $box->pack_start( $button, FALSE, FALSE, 3);
+    $box->show_all;
+    return ($box,$entry);
 }
 
 sub def_h_labeled_entry{
-	my ($label_name,$initial)=@_;
-	my $box = def_hbox(TRUE,0);
-	my $label= gen_label_in_left($label_name);	
-	my $entry =gen_entry($initial);
-	$box->pack_start( $label, FALSE, FALSE, 3);
-	$box->pack_start( $entry, FALSE, FALSE, 3);
-	return ($box,$entry);
-	
+    my ($label_name,$initial)=@_;
+    my $box = def_hbox(TRUE,0);
+    my $label= gen_label_in_left($label_name);
+    my $entry =gen_entry($initial);
+    $box->pack_start( $label, FALSE, FALSE, 3);
+    $box->pack_start( $entry, FALSE, FALSE, 3);
+    return ($box,$entry);
 }
 
 sub def_h_labeled_entry_help{
-	my ($help,$label_name,$initial)=@_;
-	my $box = def_hbox(TRUE,0);
-	my $label= gen_label_in_left($label_name);	
-	my ($b,$entry) =gen_entry_help($help,$initial);
-	$box->pack_start( $label, FALSE, FALSE, 3);
-	$box->pack_start( $b, FALSE, FALSE, 3);
-	return ($box,$entry);
-	
-}			
-
+    my ($help,$label_name,$initial)=@_;
+    my $box = def_hbox(TRUE,0);
+    my $label= gen_label_in_left($label_name);
+    my ($b,$entry) =gen_entry_help($help,$initial);
+    $box->pack_start( $label, FALSE, FALSE, 3);
+    $box->pack_start( $b, FALSE, FALSE, 3);
+    return ($box,$entry);
+}
 
 ##############
 # ComboBoxEntry
 ##############
-
 sub gen_combo_entry{
-	my ($list_ref,$pos)=@_;
-	my @list=@{$list_ref};	
-
-	#my $combo_box_entry = Gtk3::ComboBoxEntry->new_text;
-
+    my ($list_ref,$pos)=@_;
+    my @list=@{$list_ref};
+    #my $combo_box_entry = Gtk3::ComboBoxEntry->new_text;
     my $lstore =
     Gtk3::ListStore->new('Glib::String');
-
     foreach my $p (@list){
         my $iter = $lstore->append();
         $lstore->set( $iter,  0, $p );
     }
-    
-
-
-	$pos=0 if(! defined $pos || scalar @list < $pos ); 
-	my $combo_box_entry = Gtk3::ComboBox->new_with_model_and_entry($lstore);
-	$combo_box_entry->set_entry_text_column(0);
-	$combo_box_entry->set_active($pos);
-
-	return $combo_box_entry;
-	
+    $pos=0 if(! defined $pos || scalar @list < $pos );
+    my $combo_box_entry = Gtk3::ComboBox->new_with_model_and_entry($lstore);
+    $combo_box_entry->set_entry_text_column(0);
+    $combo_box_entry->set_active($pos);
+    return $combo_box_entry;
 }
 
 sub combo_entry_get_chiled{
-	my $combentry =shift;
-    return 	Gtk3::Bin::get_child($combentry);
+    my $combentry =shift;
+    return     Gtk3::Bin::get_child($combentry);
 }
 
-
-
-
 sub update_combo_entry_content {
-	my ($self,$content,$pos)=@_;
-	my @combo_list=split(/\s*,\s*/,$content) if(defined $content);
-	foreach my $p (@combo_list){
-		$self->append_text($p);
-	}
-	$pos=0 if(! defined $pos ); 
-	$self->set_active($pos);	
+    my ($self,$content,$pos)=@_;
+    my @combo_list=split(/\s*,\s*/,$content) if(defined $content);
+    foreach my $p (@combo_list){
+        $self->append_text($p);
+    }
+    $pos=0 if(! defined $pos );
+    $self->set_active($pos);
 }
 
 ###########
 # checkbutton
 ###########
-
 sub def_h_labeled_checkbutton{
-	my ($label_name)=@_;
-	my $box = def_hbox(TRUE,0);
-	my $label= gen_label_in_left($label_name) if (defined $label_name);	
-	my $check= Gtk3::CheckButton->new;
-	#if($status==1) $check->
-	$box->pack_start( $label, FALSE, FALSE, 3) if (defined $label_name);	
-	$box->pack_start( $check, FALSE, FALSE, 3);
-	return ($box,$check);
-	
-}	
+    my ($label_name)=@_;
+    my $box = def_hbox(TRUE,0);
+    my $label= gen_label_in_left($label_name) if (defined $label_name);
+    my $check= Gtk3::CheckButton->new;
+    #if($status==1) $check->
+    $box->pack_start( $label, FALSE, FALSE, 3) if (defined $label_name);
+    $box->pack_start( $check, FALSE, FALSE, 3);
+    return ($box,$check);
+}
 
 sub gen_checkbutton{
-	my $label=shift;
-	return Gtk3::CheckButton->new_with_label($label) if (defined $label);
-	return Gtk3::CheckButton->new;
+    my $label=shift;
+    return Gtk3::CheckButton->new_with_label($label) if (defined $label);
+    return Gtk3::CheckButton->new;
 }
 
-
 #############
 #  label
 ############
-
 sub gen_label_in_left{
-	my ($data)=@_;
-	my $label   = Gtk3::Label->new($data);
-	$label->set_alignment( 0, 0.5 );
-	#my $font = Gtk3::Pango::FontDescription->from_string('Tahoma 5');
-	#$label->modify_font($font);
-	return $label;
+    my ($data)=@_;
+    my $label   = Gtk3::Label->new($data);
+    $label->set_alignment( 0, 0.5 );
+    #my $font = Gtk3::Pango::FontDescription->from_string('Tahoma 5');
+    #$label->modify_font($font);
+    return $label;
 }
 
-
 sub gen_label_in_center{
-	my ($data)=@_;
-	my $label   = Gtk3::Label->new($data);
-	return $label;
+    my ($data)=@_;
+    my $label   = Gtk3::Label->new($data);
+    return $label;
 }
 
 sub def_label{
-	my @data=@_;
-	my $label   = Gtk3::Label->new(@data);
-	$label->set_alignment( 0, 0.5 );
-	return $label;
-
+    my @data=@_;
+    my $label   = Gtk3::Label->new(@data);
+    $label->set_alignment( 0, 0.5 );
+    return $label;
 }
 
-
 sub box_label{
-	my( $homogeneous, $spacing, $name)=@_;
-	my $box=def_hbox($homogeneous, $spacing);
-	my $label= def_label($name);	
-	$box->pack_start( $label, FALSE, FALSE, 3);
-	return $box;
+    my( $homogeneous, $spacing, $name)=@_;
+    my $box=def_hbox($homogeneous, $spacing);
+    my $label= def_label($name);
+    $box->pack_start( $label, FALSE, FALSE, 3);
+    return $box;
 }
 
-
 sub def_title_box{
-	my( $homogeneous, $spacing, @labels)=@_;
-	my $box=def_hbox($homogeneous, $spacing);
-	foreach my $label (@labels){
-		my $labelbox=box_label($homogeneous, $spacing, $label);
-		$box->pack_start( $labelbox, FALSE, FALSE, 3);
-	}
-	return $box;
-}	
-
-
-sub gen_label_help {	
-	my ($help, $label_name)= @_;
-	my $box = def_hbox(FALSE, 0);
-	my $label= gen_label_in_left($label_name);
-	my $button=def_image_button("icons/help.png");
-	$button->signal_connect("clicked" => sub {message_dialog($help);});
-	$box->pack_start( $label, FALSE, FALSE, 0);
-	$box->pack_start( $button, FALSE, FALSE, 0);
-	$box->set_spacing (0);
-	$box->show_all;
-	return $box;
+    my( $homogeneous, $spacing, @labels)=@_;
+    my $box=def_hbox($homogeneous, $spacing);
+    foreach my $label (@labels){
+        my $labelbox=box_label($homogeneous, $spacing, $label);
+        $box->pack_start( $labelbox, FALSE, FALSE, 3);
+    }
+    return $box;
 }
 
-sub gen_label_with_mnemonic {
-	my $name=shift;
-	Gtk3::Label->new_with_mnemonic($name);
+sub gen_label_help {
+    my ($help, $label_name)= @_;
+    my $box = def_hbox(FALSE, 0);
+    my $label= gen_label_in_left($label_name);
+    my $button=def_image_button("icons/help.png");
+    $button->signal_connect("clicked" => sub {message_dialog($help);});
+    $box->pack_start( $label, FALSE, FALSE, 0);
+    $box->pack_start( $button, FALSE, FALSE, 0);
+    $box->set_spacing (0);
+    $box->show_all;
+    return $box;
+}
 
+sub gen_label_with_mnemonic {
+    my $name=shift;
+    Gtk3::Label->new_with_mnemonic($name);
 }
-	
+
 ##############
 # button
 #############
-
 sub button_box{
 # create a new button
-	my $label=@_;
-	my $button = Gtk3::Button->new_from_stock($label);
-	my $box=def_hbox(TRUE,5);
-	$box->pack_start($button,   FALSE, FALSE,0);
-	
-	return ($box,$button);
-
+    my $label=@_;
+    my $button = Gtk3::Button->new_from_stock($label);
+    my $box=def_hbox(TRUE,5);
+    $box->pack_start($button,   FALSE, FALSE,0);
+    return ($box,$button);
 }
-	
 
 sub get_icon_pixbuff{
     my $icon_file=shift;
     my $size;
     if ($glob_setting{'ICON_SIZE'} eq 'default'){
-   		my $font_size=get_defualt_font_size();
-		$size=($font_size *2.5);
+        my $font_size=get_defualt_font_size();
+        $size=($font_size *2.5);
     }else{
-    	$size = int ($glob_setting{'ICON_SIZE'});
+        $size = int ($glob_setting{'ICON_SIZE'});
     }
-	my $pixbuf = Gtk3::Gdk::Pixbuf->new_from_file_at_scale($icon_file,$size,$size,FALSE);
-	return $pixbuf;
+    my $pixbuf = Gtk3::Gdk::Pixbuf->new_from_file_at_scale($icon_file,$size,$size,FALSE);
+    return $pixbuf;
 }
 
-
 sub def_icon{
-	my $icon_file=shift;
-	return Gtk3::Image->new_from_pixbuf(get_icon_pixbuff($icon_file));
+    my $icon_file=shift;
+    return Gtk3::Image->new_from_pixbuf(get_icon_pixbuff($icon_file));
 }
 
 sub call_gtk_drag_finish{
-	Gtk3::drag_finish(@_);
+    Gtk3::drag_finish(@_);
 }
 
-
-
 sub add_drag_dest_set{
-	my ($widget,$a,$b,$c) = @_;
-	$widget->drag_dest_set(['all'],[def_gtk_target_entry($a,$b,$c)], ['copy']);
+    my ($widget,$a,$b,$c) = @_;
+    $widget->drag_dest_set(['all'],[def_gtk_target_entry($a,$b,$c)], ['copy']);
 }
 
 sub def_gtk_target_entry{
-	return Gtk3::TargetEntry->new(@_);
+    return Gtk3::TargetEntry->new(@_);
 }
 
-
 sub add_drag_source {
-	my ($widget,$a,$b,$c) = @_;
-	$widget->drag_source_set (
-                                ['button1_mask', 'button3_mask'],
-								[def_gtk_target_entry($a,$b,$c)],
-                                ['copy']
-                        );
+    my ($widget,$a,$b,$c) = @_;
+    $widget->drag_source_set (
+        ['button1_mask', 'button3_mask'],
+        [def_gtk_target_entry($a,$b,$c)],
+        ['copy']
+    );
 }
 
 sub drag_set_icon_pixbuf {
-	my ($icon_view,$icon_pixbuf)=@_;	
-	#$icon_view->drag_source_set_icon_pixbuf ($icon_pixbuf);
+    my ($icon_view,$icon_pixbuf)=@_;
+    #$icon_view->drag_source_set_icon_pixbuf ($icon_pixbuf);
 }
 
 sub gen_iconview {
-	my ($tree_model,$marc_col,$pix_con)=@_;
-	my $icon_view = Gtk3::IconView->new_with_model($tree_model);
+    my ($tree_model,$marc_col,$pix_con)=@_;
+    my $icon_view = Gtk3::IconView->new_with_model($tree_model);
     $icon_view->set_markup_column($marc_col);
     $icon_view->set_pixbuf_column($pix_con);
-	return $icon_view;
+    return $icon_view;
 }
 
-
 sub add_frame_to_image{
-	my $image=shift;
-	my $align = Gtk3::Alignment->new (0.5, 0.5, 0, 0);
-   	my $frame = Gtk3::Frame->new;
-	$frame->set_shadow_type ('in');
-	# Animation
-	$frame->add ($image);
-	$align->add ($frame);
-	return $align;
+    my $image=shift;
+    my $align = Gtk3::Alignment->new (0.5, 0.5, 0, 0);
+    my $frame = Gtk3::Frame->new;
+    $frame->set_shadow_type ('in');
+    # Animation
+    $frame->add ($image);
+    $align->add ($frame);
+    return $align;
 }
 
 sub gen_frame {
-	return  Gtk3::Frame->new;
+    return  Gtk3::Frame->new;
 }
 
-
-
 sub new_image_from_file{
-	return  Gtk3::Image->new_from_file (@_);
+    return  Gtk3::Image->new_from_file (@_);
 }
 
-
 sub gen_pixbuf{
-	my $file=shift;
-	return Gtk3::Gdk::Pixbuf->new_from_file($file);	
+    my $file=shift;
+    return Gtk3::Gdk::Pixbuf->new_from_file($file);
 }
 
 sub open_image{
-	my ($image_file,$x,$y,$unit)=@_;
-	if(defined $unit){
-		my($width,$hight)=max_win_size();
-		if($unit eq 'percent'){
-			$x= ($x * $width)/100;
-			$y= ($y * $hight)/100;
-		} # else its pixels
-			
-	}
-	$image_file ="icons/blank.png"  unless(-f $image_file);
-	my $pixbuf = Gtk3::Gdk::Pixbuf->new_from_file_at_scale($image_file,$x,$y,TRUE);
- 	my $image = Gtk3::Image->new_from_pixbuf($pixbuf);
-	return $image;
+    my ($image_file,$x,$y,$unit)=@_;
+    if(defined $unit){
+        my($width,$hight)=max_win_size();
+        if($unit eq 'percent'){
+            $x= ($x * $width)/100;
+            $y= ($y * $hight)/100;
+        } # else its pixels
+    }
+    $image_file ="icons/blank.png"  unless(-f $image_file);
+    my $pixbuf = Gtk3::Gdk::Pixbuf->new_from_file_at_scale($image_file,$x,$y,TRUE);
+    my $image = Gtk3::Image->new_from_pixbuf($pixbuf);
+    return $image;
 }
 
 sub open_inline_image{
-	my ($image_string,$x,$y,$unit)=@_;
-	if(defined $unit){
-		my($width,$hight)=max_win_size();
-		if($unit eq 'percent'){
-			$x= ($x * $width)/100;
-			$y= ($y * $hight)/100;
-		} # else its pixels
-			
-	}
-	my $pixbuf = do {
+    my ($image_string,$x,$y,$unit)=@_;
+    if(defined $unit){
+        my($width,$hight)=max_win_size();
+        if($unit eq 'percent'){
+            $x= ($x * $width)/100;
+            $y= ($y * $hight)/100;
+        } # else its pixels
+    }
+    my $pixbuf = do {
         my $loader = Gtk3::Gdk::PixbufLoader->new();
         $loader->set_size(  $x,$y ) if (defined $y);
-        $loader->write( [unpack 'C*', $image_string] );        
+        $loader->write( [unpack 'C*', $image_string] );
         $loader->close();
         $loader->get_pixbuf();
     };
-	
-
- 	my $image = Gtk3::Image->new_from_pixbuf($pixbuf);
- 	 
-	return $image;
+    my $image = Gtk3::Image->new_from_pixbuf($pixbuf);
+    return $image;
 }
 
 sub find_icon{
-	my $file =shift;
-	return $file if(-f $file); #called from perl_gui
-	return "../../$file"; #called from lib/perl 		
+    my $file =shift;
+    return $file if(-f $file); #called from perl_gui
+    return "../../$file"; #called from lib/perl
 }
 
 sub def_image_button{
-	my ($image_file, $label_text, $homogeneous, $mnemonic)=@_;
-	# create box for image and label 
-	$homogeneous = FALSE if(!defined $homogeneous);
-	my $box = def_hbox($homogeneous,0);
-	my $image; 
-	$image_file = find_icon( $image_file);
-	$image = def_icon($image_file) if(-f $image_file); 
-	
-	# now on to the image stuff
-	#my $image = Gtk3::Image->new_from_file($image_file);
-	$box->pack_start($image, FALSE, FALSE, 0) if(defined  $image);
-	$box->set_border_width(0);
-	$box->set_spacing (0);
-	# Create a label for the button
-	if(defined $label_text ) {
-		my $label;
-		$label = Gtk3::Label->new("  $label_text") unless (defined $mnemonic);
-		$label = Gtk3::Label->new_with_mnemonic (" $label_text") if (defined $mnemonic);
-		$box->pack_start($label, FALSE, FALSE, 0);
-	}	
-	
-	my $button = Gtk3::Button->new();
-	$button->add($box);
-	$button->set_border_width(0);
-	$button->show_all;
-	return $button;
+    my ($image_file, $label_text, $homogeneous, $mnemonic)=@_;
+    # create box for image and label
+    $homogeneous = FALSE if(!defined $homogeneous);
+    my $box = def_hbox($homogeneous,0);
+    my $image;
+    $image_file = find_icon( $image_file);
+    $image = def_icon($image_file) if(-f $image_file);
+    # now on to the image stuff
+    #my $image = Gtk3::Image->new_from_file($image_file);
+    $box->pack_start($image, FALSE, FALSE, 0) if(defined  $image);
+    $box->set_border_width(0);
+    $box->set_spacing (0);
+    # Create a label for the button
+    if(defined $label_text ) {
+        my $label;
+        $label = Gtk3::Label->new("  $label_text") unless (defined $mnemonic);
+        $label = Gtk3::Label->new_with_mnemonic (" $label_text") if (defined $mnemonic);
+        $box->pack_start($label, FALSE, FALSE, 0);
+    }
+    my $button = Gtk3::Button->new();
+    $button->add($box);
+    $button->set_border_width(0);
+    $button->show_all;
+    return $button;
 }
 
 sub def_button{
-	my ($label_text)=@_;
-	my $label = Gtk3::Label->new("$label_text") if(defined $label_text);
-	my $button= Gtk3::Button->new();
-	$button->add($label) if(defined $label_text);
-	return $button;
-}	
-
+    my ($label_text)=@_;
+    my $label = Gtk3::Label->new("$label_text") if(defined $label_text);
+    my $button= Gtk3::Button->new();
+    $button->add($label) if(defined $label_text);
+    return $button;
+}
 
 sub def_image_label{
-	my ($image_file, $label_text,$mnemonic)=@_;
-	# create box for image and label 
-	my $box = def_hbox(FALSE,1);
-	# now on to the image stuff
-	my $image = def_icon($image_file);
-	$box->pack_start($image, TRUE, FALSE, 0);
-	# Create a label for the button
-	if(defined $label_text ) {
-		my $label; 
-		$label = Gtk3::Label->new("  $label_text") unless (defined $mnemonic);
-		$label = Gtk3::Label->new_with_mnemonic (" $label_text") if (defined $mnemonic);
-		$box->pack_start($label, TRUE, FALSE, 0);
-	}	
-		
-	return $box;
-
+    my ($image_file, $label_text,$mnemonic)=@_;
+    # create box for image and label
+    my $box = def_hbox(FALSE,1);
+    # now on to the image stuff
+    my $image = def_icon($image_file);
+    $box->pack_start($image, TRUE, FALSE, 0);
+    # Create a label for the button
+    if(defined $label_text ) {
+        my $label;
+        $label = Gtk3::Label->new("  $label_text") unless (defined $mnemonic);
+        $label = Gtk3::Label->new_with_mnemonic (" $label_text") if (defined $mnemonic);
+        $box->pack_start($label, TRUE, FALSE, 0);
+    }
+    return $box;
 }
 
-
-sub gen_button_message {	
-	my ($help, $image_file,$label_name)= @_;
-	my $box = def_hbox(FALSE, 0);
-	my $label= gen_label_in_center($label_name) if(defined $label_name);
-	my $button=def_image_button($image_file);
-		
-	if(defined $help ){$button->signal_connect("clicked" => sub {message_dialog($help);});}
-			
-	$box->pack_start( $label, FALSE, FALSE, 0) if(defined $label_name);
-	$box->pack_start( $button, FALSE, FALSE, 0);
-	$box->set_border_width(0);
-	$box->set_spacing (0);
-	$box->show_all;
-	
-	return $box;
-
-
+sub gen_button_message {
+    my ($help, $image_file,$label_name)= @_;
+    my $box = def_hbox(FALSE, 0);
+    my $label= gen_label_in_center($label_name) if(defined $label_name);
+    my $button=def_image_button($image_file);
+    if(defined $help ){$button->signal_connect("clicked" => sub {message_dialog($help);});}
+    $box->pack_start( $label, FALSE, FALSE, 0) if(defined $label_name);
+    $box->pack_start( $button, FALSE, FALSE, 0);
+    $box->set_border_width(0);
+    $box->set_spacing (0);
+    $box->show_all;
+    return $box;
 }
 
-
 sub def_colored_button{
-	my ($label_text,$color_num)=@_;
-	# create box for image and label 
-	my $box = def_hbox(FALSE,0);
-	my $font_size=get_defualt_font_size();
-	
-	
-	my $button= Gtk3::Button->new();
-	my $label = gen_label_in_center($label_text) if(defined $label_text);
-		
-
-	# do custom css #####################################################
-	my $css_provider = Gtk3::CssProvider->new;
-
-	my ($red,$green,$blue) = get_color($color_num);
-	my $r =int ($red*100/65535);
-	my $g =int ($green*100/65535);
-	my $b =int ($blue*100/65535);
-
-	
-	#select lable color based on backgorund 
-	my $lc = (($r*0.299 + $g*0.587 + $b*0.114) > 50)? 0 : 1; # use #000000 else use #ffffff
-	
-	$label->set_markup("<span  foreground= 'white' >$label_text</span>")  if(defined $label_text && $lc==1);	
-	
-	
-
-	$css_provider->load_from_data ([map ord, split //, "
-	
+    my ($label_text,$color_num)=@_;
+    # create box for image and label
+    my $box = def_hbox(FALSE,0);
+    my $font_size=get_defualt_font_size();
+    my $button= Gtk3::Button->new();
+    my $label = gen_label_in_center($label_text) if(defined $label_text);
+    # do custom css #####################################################
+    my $css_provider = Gtk3::CssProvider->new;
+    my ($red,$green,$blue) = get_color($color_num);
+    my $r =int ($red*100/65535);
+    my $g =int ($green*100/65535);
+    my $b =int ($blue*100/65535);
+    #select lable color based on backgorund
+    my $lc = (($r*0.299 + $g*0.587 + $b*0.114) > 50)? 0 : 1; # use #000000 else use #ffffff
+    $label->set_markup("<span  foreground= 'white' >$label_text</span>")  if(defined $label_text && $lc==1);
+    $css_provider->load_from_data ([map ord, split //, "
 button {
-	background-image: none; 
-	background-color: rgba($r%,$g%,$b%,100);
+    background-image: none;
+    background-color: rgba($r%,$g%,$b%,100);
 }"
 ]);
-
-	
-	my $style_context = $button->get_style_context;
-	$style_context->add_provider ( $css_provider, Gtk3::STYLE_PROVIDER_PRIORITY_USER);
-
-	$button->add($label)  if(defined $label_text);
-	
-	$button->show_all;
-	return $button;
+    my $style_context = $button->get_style_context;
+    $style_context->add_provider ( $css_provider, Gtk3::STYLE_PROVIDER_PRIORITY_USER);
+    $button->add($label)  if(defined $label_text);
+    $button->show_all;
+    return $button;
 }
 
-
-
-
-
 sub entry_set_text_color {
-	my ($entry,$color_num)=@_;
-	my $color_hex = get_color_hex_string($color_num);
-	
-	my $css_provider = Gtk3::CssProvider->new;
-	$css_provider->load_from_data ([map ord, split //, "
+    my ($entry,$color_num)=@_;
+    my $color_hex = get_color_hex_string($color_num);
+    my $css_provider = Gtk3::CssProvider->new;
+    $css_provider->load_from_data ([map ord, split //, "
 entry {
-  color: #$color_hex;
+    color: #$color_hex;
 }"
-	]);
-
-	my $style_context = $entry->get_style_context;
-	$style_context->add_provider ( $css_provider, Gtk3::STYLE_PROVIDER_PRIORITY_USER);
-	
+    ]);
+    my $style_context = $entry->get_style_context;
+    $style_context->add_provider ( $css_provider, Gtk3::STYLE_PROVIDER_PRIORITY_USER);
 }
 
-
-
-
-
-
-
-
 sub show_gif{
-	my $gif = shift;
-	$gif=find_icon( $gif);
-	my $vbox = Gtk3::HBox->new (TRUE, 8);
+    my $gif = shift;
+    $gif=find_icon( $gif);
+    my $vbox = Gtk3::HBox->new (TRUE, 8);
     my $filename;
-      eval {
-          $filename = main::demo_find_file ($gif);
-      };
+    eval {
+        $filename = main::demo_find_file ($gif);
+    };
     my $image = Gtk3::Image->new_from_file ($gif);
     $vbox->set_border_width (4);
     my   $align = Gtk3::Alignment->new (0.5, 0.5, 0, 0);
-	my $frame = Gtk3::Frame->new;
-	$frame->set_shadow_type ('in');
+    my $frame = Gtk3::Frame->new;
+    $frame->set_shadow_type ('in');
     # Animation
     $frame->add ($image);
     $align->add ($frame);
-	$vbox->pack_start ($align, FALSE, FALSE, 0);
-  	return $vbox;
+    $vbox->pack_start ($align, FALSE, FALSE, 0);
+    return $vbox;
 }
 
 sub gen_radiobutton {
-	my ($from,$label,$icon,$tip) =@_;
-	my $rbtn = (defined $from )? Gtk3::RadioToolButton->new_from_widget($from) : Gtk3::RadioToolButton->new (undef);
-	$rbtn->set_label ($label) if(defined $label);
-	$rbtn->set_icon_widget (def_icon($icon)) if(defined $icon);
-	set_tip($rbtn, $tip) if(defined $tip);
-	return $rbtn;
+    my ($from,$label,$icon,$tip) =@_;
+    my $rbtn = (defined $from )? Gtk3::RadioToolButton->new_from_widget($from) : Gtk3::RadioToolButton->new (undef);
+    $rbtn->set_label ($label) if(defined $label);
+    $rbtn->set_icon_widget (def_icon($icon)) if(defined $icon);
+    set_tip($rbtn, $tip) if(defined $tip);
+    return $rbtn;
 }
 
 sub gen_colored_label{
-	my ($label_text, $color_num)=@_;
-
-	my $color_hex = get_color_hex_string($color_num);
+    my ($label_text, $color_num)=@_;
+    my $color_hex = get_color_hex_string($color_num);
     my $label   = Gtk3::Label->new($label_text);
-	$label->set_markup("<span 
- background= '#$color_hex'
- foreground= 'black' ><b>$label_text</b></span>");
-	
-	return $label;
+    $label->set_markup("<span
+    background= '#$color_hex'
+    foreground= 'black' ><b>$label_text</b></span>");
+    return $label;
 }
 
-
 ############
-#	message_dialog
+#    message_dialog
 ############
-
 sub message_dialog {
-  my ($message,$type)=@_;
-  $type = 'info' if (!defined $type);
-  my $window;
-  my $dialog = Gtk3::MessageDialog->new ($window,
-				   [qw( modal destroy-with-parent )],
-				   $type,
-				   'ok',
-				    $message);
-  
-  $dialog->set_transient_for (Gtk3::Window->new('toplevel'));#just to get rid of transient warning
-  $dialog->run;
-  $dialog->destroy;
- 
+    my ($message,$type)=@_;
+    $type = 'info' if (!defined $type);
+    my $window;
+    my $dialog = Gtk3::MessageDialog->new ($window,
+        [qw( modal destroy-with-parent )],
+        $type,
+        'ok',
+        $message);
+    $dialog->set_transient_for (Gtk3::Window->new('toplevel'));#just to get rid of transient warning
+    $dialog->run;
+    $dialog->destroy;
 }
 
-
-
 sub set_tip{
-	my ($widget,$tip)=@_;
-	#my $tooltips = Gtk3::Tooltips->new;
-	#$tooltips->set_tip($widget,$tip);
-	$widget->set_tooltip_text($tip); 
-	
-	
+    my ($widget,$tip)=@_;
+    #my $tooltips = Gtk3::Tooltips->new;
+    #$tooltips->set_tip($widget,$tip);
+    $widget->set_tooltip_text($tip);
 }
 
-
 sub yes_no_dialog {
-	my ($message)=@_;
-	my $dialog = Gtk3::MessageDialog->new (my $window,
-			'destroy-with-parent',
-			'question', # message type
-			'yes-no', # which set of buttons?
-			"$message");
-			
-	$dialog->set_transient_for (Gtk3::Window->new('toplevel'));#just to get rid of transient warning		
-	my $response = $dialog->run;
-	
-	$dialog->destroy;
-	return $response;
+    my ($message)=@_;
+    my $dialog = Gtk3::MessageDialog->new (my $window,
+            'destroy-with-parent',
+            'question', # message type
+            'yes-no', # which set of buttons?
+            "$message");
+    $dialog->set_transient_for (Gtk3::Window->new('toplevel'));#just to get rid of transient warning
+    my $response = $dialog->run;
+    $dialog->destroy;
+    return $response;
 }
 
 sub create_dialog {
-	my ($message_head,$message_body,$icon,@buttons)=@_;
-	# create a new dialog with some buttons 
-	my %hash1;
-	my %hash2;
-	my $i=0;
-	foreach my $b (@buttons){
-		$hash1{$b}=$i;
-		$hash2{$i}=$b;
-		$i++;
-	}
-	
-  	my $dialog = Gtk3::Dialog->new (
-  		" ", 
-  		Gtk3::Window->new('toplevel'),
-  		[qw/modal destroy-with-parent/],
+    my ($message_head,$message_body,$icon,@buttons)=@_;
+    # create a new dialog with some buttons
+    my %hash1;
+    my %hash2;
+    my $i=0;
+    foreach my $b (@buttons){
+        $hash1{$b}=$i;
+        $hash2{$i}=$b;
+        $i++;
+    }
+    my $dialog = Gtk3::Dialog->new (
+        " ",
+        Gtk3::Window->new('toplevel'),
+        [qw/modal destroy-with-parent/],
         %hash1
     );
-	my $content = $dialog->get_content_area ();
-	
-	my $table = def_table(1,3,TRUE);
-	$table->attach  (def_icon($icon) , 0, 1,  0, 2,'expand','expand',2,2) if(defined $icon);
-	if(defined $message_head){
-		my $hd=gen_label_in_left($message_head);
-		$hd->set_markup("<span  foreground= 'black' ><b>$message_head</b></span>");
-		$table->attach  ($hd , 1, 10,  0, 1,'fill','shrink',2,2);
-	}
-	if(defined $message_head){
-		$table->attach  (gen_label_in_left($message_body) , 2, 10,  1, 2,'fill','shrink',2,2);
-	}
-	
-	$content->add ($table);
-	$content->show_all;
-			
-	$dialog->set_transient_for (Gtk3::Window->new('toplevel'));#just to get rid of transient warning		
-	my $response = $dialog->run;
-	
-	$dialog->destroy;
-	return $hash2{$response};
+    my $content = $dialog->get_content_area ();
+    my $table = def_table(1,3,TRUE);
+    $table->attach  (def_icon($icon) , 0, 1,  0, 2,'expand','expand',2,2) if(defined $icon);
+    if(defined $message_head){
+        my $hd=gen_label_in_left($message_head);
+        $hd->set_markup("<span  foreground= 'black' ><b>$message_head</b></span>");
+        $table->attach  ($hd , 1, 10,  0, 1,'fill','shrink',2,2);
+    }
+    if(defined $message_head){
+        $table->attach  (gen_label_in_left($message_body) , 2, 10,  1, 2,'fill','shrink',2,2);
+    }
+    $content->add ($table);
+    $content->show_all;
+    $dialog->set_transient_for (Gtk3::Window->new('toplevel'));#just to get rid of transient warning
+    my $response = $dialog->run;
+    $dialog->destroy;
+    return $hash2{$response};
 }
 
 ############
 # window
 ###########
-
 sub def_win {
-	my @titel=shift;
-	my $window = Gtk3::Window->new('toplevel');
-	$window->set_title(@titel);
-	$window->set_position("center");
-	$window->set_default_size(100, 100);
-	$window->set_border_width(20);
-	$window->signal_connect (delete_event => sub { Gtk3->main_quit });
-	return $window;
-	
-}	
-
+    my @titel=shift;
+    my $window = Gtk3::Window->new('toplevel');
+    $window->set_title(@titel);
+    $window->set_position("center");
+    $window->set_default_size(100, 100);
+    $window->set_border_width(20);
+    $window->signal_connect (delete_event => sub { Gtk3->main_quit });
+    return $window;
+}
 
 sub def_win_size {
-	my $x=shift;
-	my $y=shift;
-	my @titel=shift;
-	my $window = Gtk3::Window->new('toplevel');
-	$window->set_title(@titel);
-	$window->set_position("center");
-	$window->set_default_size($x, $y);
-	$window->set_border_width(20);
-	$window->signal_connect (delete_event => sub { Gtk3->main_quit });
-	return $window;
-	
-}	
-
+    my $x=shift;
+    my $y=shift;
+    my @titel=shift;
+    my $window = Gtk3::Window->new('toplevel');
+    $window->set_title(@titel);
+    $window->set_position("center");
+    $window->set_default_size($x, $y);
+    $window->set_border_width(20);
+    $window->signal_connect (delete_event => sub { Gtk3->main_quit });
+    return $window;
+}
 
 sub def_popwin_size {
-	my ($x,$y,$titel,$unit)=@_;
-	if(defined $unit){
-		my($width,$hight)=max_win_size();
-		if($unit eq 'percent'){
-			$x= ($x * $width)/100;
-			$y= ($y * $hight)/100;
-		} # else its pixels
-			
-	}
-	#my $window = Gtk3::Window->new('popup');
-	my $window = Gtk3::Window->new('toplevel');
-	$window->set_title($titel);
-	$window->set_position("center");
-	$window->set_default_size($x, $y);
-	$window->set_border_width(20);
-	#$window->signal_connect (delete_event => sub { $window->destroy });
-	return $window;
-	
-}	
-
-
-
-
+    my ($x,$y,$titel,$unit)=@_;
+    if(defined $unit){
+        my($width,$hight)=max_win_size();
+        if($unit eq 'percent'){
+            $x= ($x * $width)/100;
+            $y= ($y * $hight)/100;
+        } # else its pixels
+    }
+    #my $window = Gtk3::Window->new('popup');
+    my $window = Gtk3::Window->new('toplevel');
+    $window->set_title($titel);
+    $window->set_position("center");
+    $window->set_default_size($x, $y);
+    $window->set_border_width(20);
+    #$window->signal_connect (delete_event => sub { $window->destroy });
+    return $window;
+}
 
 sub def_scrolled_window_box{
-			
-	my $window =  def_popwin_size(@_);
-	my $box=def_vbox(TRUE,5);
-	my $scrolled_window = new Gtk3::ScrolledWindow (undef, undef);
-	$scrolled_window->set_policy( "automatic", "automatic" );
-	$scrolled_window->add($box);
-	$window->add($scrolled_window);
-	$window->show_all;
-	$box->show_all;
-	return ($box,$window);
-
+    my $window =  def_popwin_size(@_);
+    my $box=def_vbox(TRUE,5);
+    my $scrolled_window = new Gtk3::ScrolledWindow (undef, undef);
+    $scrolled_window->set_policy( "automatic", "automatic" );
+    $scrolled_window->add($box);
+    $window->add($scrolled_window);
+    $window->show_all;
+    $box->show_all;
+    return ($box,$window);
 }
 
-
 sub get_default_screen {
-  return Gtk3::Gdk::Screen::get_default;
+    return Gtk3::Gdk::Screen::get_default;
 }
 
 sub get_defualt_font_size{
-	return int($glob_setting{'FONT_SIZE'}) if ($glob_setting{'FONT_SIZE'} ne 'default');	
-	
-	my($width,$hight)=max_win_size();
-	#print "($width,$hight)\n";
-	my $font_size=($width>=1600)? 10:
-			      ($width>=1400)? 9:
-				  ($width>=1200)? 9:
-				  ($width>=1000)? 7:6;
-	#print "$font_size\n";	
-	return $font_size;
+    return int($glob_setting{'FONT_SIZE'}) if ($glob_setting{'FONT_SIZE'} ne 'default');
+    my($width,$hight)=max_win_size();
+    #print "($width,$hight)\n";
+    my $font_size=
+        ($width>=1600)? 10:
+        ($width>=1400)? 9:
+        ($width>=1200)? 9:
+        ($width>=1000)? 7:6;
+    #print "$font_size\n";
+    return $font_size;
 }
 
-
 sub set_defualt_font_size{
-	my $font_size=get_defualt_font_size();
-	$font_size= int (1.35*$font_size);
+    my $font_size=get_defualt_font_size();
+    $font_size= int (1.35*$font_size);
 # do custom css #####################################################
-	my $css_provider = Gtk3::CssProvider->new;
-	$css_provider->load_from_data ([map ord, split //, "
-	*{
-                           
+    my $css_provider = Gtk3::CssProvider->new;
+    $css_provider->load_from_data ([map ord, split //, "
+    *{
                             font-family:Verdana;
                             font-size:${font_size}px;
-                                  }"
-	
+                                }"
 ]);
-
 #font_name = Verdana $font_size"
-
-
-	#print  $css_provider->to_string,"\n";
-
-	my $d = Gtk3::Gdk::Display::get_default ();
-	my $s = $d->get_default_screen;
-	
-	Gtk3::StyleContext::add_provider_for_screen ( $s, $css_provider, Gtk3::STYLE_PROVIDER_PRIORITY_USER);
-
-
-	   
-		#Gtk3::Rc->parse_string(<<__);
-		#	style "normal" { 
-		#		font_name ="Verdana $font_size" 
-		#	}
-		#	widget "*" style "normal"
+    #print  $css_provider->to_string,"\n";
+    my $d = Gtk3::Gdk::Display::get_default ();
+    my $s = $d->get_default_screen;
+    Gtk3::StyleContext::add_provider_for_screen ( $s, $css_provider, Gtk3::STYLE_PROVIDER_PRIORITY_USER);
+        #Gtk3::Rc->parse_string(<<__);
+        #    style "normal" {
+        #        font_name ="Verdana $font_size"
+        #    }
+        #    widget "*" style "normal"
 #__
-
 }
 
 sub add_widget_to_scrolled_win{
-	my ($widget,$scrolled_win) =@_;
-	if(! defined $scrolled_win){
-		$scrolled_win = new Gtk3::ScrolledWindow (undef, undef);
-		$scrolled_win->set_policy( "automatic", "automatic" );
-		$scrolled_win->set_shadow_type('in');
-	}else {
-		my @list = $scrolled_win->get_children ();
-		foreach my $c( @list){ $scrolled_win->remove($c);}
-	}		
-	#$scrolled_win->add_with_viewport($widget) if(defined $widget);
-	$scrolled_win->add($widget) if(defined $widget);	
-	$scrolled_win->show_all;	
-	return $scrolled_win ;
+    my ($widget,$scrolled_win) =@_;
+    if(! defined $scrolled_win){
+        $scrolled_win = new Gtk3::ScrolledWindow (undef, undef);
+        $scrolled_win->set_policy( "automatic", "automatic" );
+        $scrolled_win->set_shadow_type('in');
+    }else {
+        my @list = $scrolled_win->get_children ();
+        foreach my $c( @list){ $scrolled_win->remove($c);}
+    }
+    #$scrolled_win->add_with_viewport($widget) if(defined $widget);
+    $scrolled_win->add($widget) if(defined $widget);
+    $scrolled_win->show_all;
+    return $scrolled_win ;
 }
 
 sub gen_scr_win_with_adjst {
-	my ($self,$name)=@_;
-	my $scrolled_win = new Gtk3::ScrolledWindow (undef, undef);	
-	$scrolled_win->set_policy( "automatic", "automatic" );	
-	$scrolled_win->signal_connect("destroy"=> sub{
-	 	save_scrolled_win_adj($self,$scrolled_win, $name);
-	 	
-	 });
-	 my $adjast=0;
-	 $scrolled_win->signal_connect("size-allocate"=> sub{
-	 	if($adjast==0){
-	 		load_scrolled_win_adj($self,$scrolled_win, $name);
-	 		$adjast=1;
-	 	}
-	 	
-	 });	
-	return $scrolled_win;
+    my ($self,$name)=@_;
+    my $scrolled_win = new Gtk3::ScrolledWindow (undef, undef);
+    $scrolled_win->set_policy( "automatic", "automatic" );
+    $scrolled_win->signal_connect("destroy"=> sub{
+        save_scrolled_win_adj($self,$scrolled_win, $name);
+    });
+    my $adjast=0;
+    $scrolled_win->signal_connect("size-allocate"=> sub{
+        if($adjast==0){
+            load_scrolled_win_adj($self,$scrolled_win, $name);
+            $adjast=1;
+        }
+    });
+    return $scrolled_win;
 }
 
-
 sub save_scrolled_win_adj {
-	my ($self,$scrolled_win,$name)=@_;  	
-	return if (!defined $scrolled_win);
-	my $ha= $scrolled_win->get_hadjustment();
+    my ($self,$scrolled_win,$name)=@_;
+    return if (!defined $scrolled_win);
+    my $ha= $scrolled_win->get_hadjustment();
     my $va =$scrolled_win->get_vadjustment();
     return if(!defined $ha);
     return if(!defined $va);
-    save_adj ($self,$ha,$name,"ha"); 
-	save_adj ($self,$va,$name,"va"); 
+    save_adj ($self,$ha,$name,"ha");
+    save_adj ($self,$va,$name,"va");
 }
 
-
 sub load_scrolled_win_adj {
-	my ($self,$scrolled_win,$name)=@_;  
-	my $ha= $scrolled_win->get_hadjustment();
+    my ($self,$scrolled_win,$name)=@_;
+    my $ha= $scrolled_win->get_hadjustment();
     my $va =$scrolled_win->get_vadjustment();
-	my $h=load_adj ($self,$ha,$name,"ha"); 
-	my $v=load_adj ($self,$va,$name,"va"); 
-	#$ha->set_value($h) if(defined $h);
-    #$va->set_value($v) if(defined $v);    
+    my $h=load_adj ($self,$ha,$name,"ha");
+    my $v=load_adj ($self,$va,$name,"va");
+    #$ha->set_value($h) if(defined $h);
+    #$va->set_value($v) if(defined $v);
 }
-  
-    
-    
-    
+
 sub save_adj {
-	my ($self,$adjustment,$at1,$at2)=@_;  	
-	my $value = $adjustment->get_value;
-	$self->object_add_attribute($at1,$at2,$value) if (defined $self);
+    my ($self,$adjustment,$at1,$at2)=@_;
+    my $value = $adjustment->get_value;
+    $self->object_add_attribute($at1,$at2,$value) if (defined $self);
 }
 
-
 sub load_adj {
-	my ($self,$adjustment,$at1,$at2)=@_;
-	return if(!defined $at1);
+    my ($self,$adjustment,$at1,$at2)=@_;
+    return if(!defined $at1);
     my $value=  $self->object_get_attribute($at1,$at2);
     return if(!defined $value);
     my $lower =  $adjustment->get_lower;
     my $upper = $adjustment->get_upper - $adjustment->get_page_size;
-    $value=  ($value < $lower || $value > $upper ) ? 0 : $value; 
-    
-    $adjustment->set_value($value);   
+    $value=  ($value < $lower || $value > $upper ) ? 0 : $value;
+    $adjustment->set_value($value);
 }
 
 sub set_pronoc_icon{
-	my $window=shift;
-    my $navIco = gen_pixbuf("./icons/ProNoC.png");        
-	$window->set_icon($navIco); 
+    my $window=shift;
+    my $navIco = gen_pixbuf("./icons/ProNoC.png");
+    $window->set_icon($navIco);
 }
 
 ##############
-#	box
+#    box
 #############
-
 sub def_hbox {
-	my( $homogeneous, $spacing)=@_;
-	my $box = Gtk3::HBox->new($homogeneous, $spacing);
-	$box->set_border_width(2);
-	return $box;
+    my( $homogeneous, $spacing)=@_;
+    my $box = Gtk3::HBox->new($homogeneous, $spacing);
+    $box->set_border_width(2);
+    return $box;
 }
 
 sub def_vbox {
-	my $box = Gtk3::VBox->new(FALSE, 0);
-	$box->set_border_width(2);
-	return $box;
+    my $box = Gtk3::VBox->new(FALSE, 0);
+    $box->set_border_width(2);
+    return $box;
 }
 
 sub def_pack_hbox{
-	my( $homogeneous, $spacing , @box_list)=@_;
-	my $box=def_hbox($homogeneous, $spacing); 
-	foreach my $subbox (@box_list){
-		$box->pack_start( $subbox, FALSE, FALSE, 3);
-	}
-	return $box;	
-
-
+    my( $homogeneous, $spacing , @box_list)=@_;
+    my $box=def_hbox($homogeneous, $spacing);
+    foreach my $subbox (@box_list){
+        $box->pack_start( $subbox, FALSE, FALSE, 3);
+    }
+    return $box;
 }
 
 sub def_pack_vbox{
-	my( $homogeneous, $spacing , @box_list)=@_;
-	my $box=def_vbox($homogeneous, $spacing); 
-	foreach my $subbox (@box_list){
-		$box->pack_start( $subbox, FALSE, FALSE, 3);
-	}
-	return $box;	
-
+    my( $homogeneous, $spacing , @box_list)=@_;
+    my $box=def_vbox($homogeneous, $spacing);
+    foreach my $subbox (@box_list){
+        $box->pack_start( $subbox, FALSE, FALSE, 3);
+    }
+    return $box;
 }
 
-
 ##########
 # Paned
 #########
-
-
 sub gen_vpaned {
-	my ($w1,$loc,$w2) = @_;
-	my $vpaned = Gtk3::VPaned -> new;
-	my($width,$hight)=max_win_size();
-
-	
-	$vpaned -> pack1($w1, TRUE, TRUE); 	
-	$vpaned -> set_position ($hight*$loc);	
-	$vpaned -> pack2($w2, TRUE, TRUE); 
-	
-	return $vpaned;
+    my ($w1,$loc,$w2) = @_;
+    my $vpaned = Gtk3::VPaned -> new;
+    my($width,$hight)=max_win_size();
+    $vpaned -> pack1($w1, TRUE, TRUE);
+    $vpaned -> set_position ($hight*$loc);
+    $vpaned -> pack2($w2, TRUE, TRUE);
+    return $vpaned;
 }
 
-
 sub gen_hpaned {
-	my ($w1,$loc,$w2) = @_;
-	my $hpaned = Gtk3::HPaned -> new;
-	my($width,$hight)=max_win_size();
-	
-	$hpaned -> pack1($w1, TRUE, TRUE); 	
-	$hpaned -> set_position ($width*$loc);	
-	$hpaned -> pack2($w2, TRUE, TRUE); 
-	
-	return $hpaned;
+    my ($w1,$loc,$w2) = @_;
+    my $hpaned = Gtk3::HPaned -> new;
+    my($width,$hight)=max_win_size();
+    $hpaned -> pack1($w1, TRUE, TRUE);
+    $hpaned -> set_position ($width*$loc);
+    $hpaned -> pack2($w2, TRUE, TRUE);
+    return $hpaned;
 }
 
-
 sub gen_hpaned_adj {
-	my ($self,$w1,$loc,$w2,$name) = @_;
-	my $hpaned = Gtk3::HPaned -> new;
-	$hpaned -> pack1($w1, TRUE, TRUE); 
-	$hpaned -> pack2($w2, TRUE, TRUE); 	
-	
-	$hpaned->signal_connect("destroy"=> sub{
-	 	my $adj = $hpaned->get_position ();
-	 	$self->object_add_attribute("adj",$name,$adj);
-	 });	
-	
-	my $val =$self->object_get_attribute("adj",$name);
-	if(defined $val){
-		$hpaned -> set_position ($val);
-	} else{
-		my($width,$hight)=max_win_size();
-		$hpaned -> set_position ($width*$loc);		
-	}	
-	
-	return $hpaned;
+    my ($self,$w1,$loc,$w2,$name) = @_;
+    my $hpaned = Gtk3::HPaned -> new;
+    $hpaned -> pack1($w1, TRUE, TRUE);
+    $hpaned -> pack2($w2, TRUE, TRUE);
+    $hpaned->signal_connect("destroy"=> sub{
+        my $adj = $hpaned->get_position ();
+        $self->object_add_attribute("adj",$name,$adj);
+    });
+    my $val =$self->object_get_attribute("adj",$name);
+    if(defined $val){
+        $hpaned -> set_position ($val);
+    } else{
+        my($width,$hight)=max_win_size();
+        $hpaned -> set_position ($width*$loc);
+    }
+    return $hpaned;
 }
 
-
 #############
-# text_view 
+# text_view
 ############
-
 sub create_txview {
-  my $scrolled_window = Gtk3::ScrolledWindow->new;
-  $scrolled_window->set_policy ('automatic', 'automatic');
-  $scrolled_window->set_shadow_type ('in');
-  my $tview = Gtk3::TextView->new();
-  $scrolled_window->add ($tview);
-  
-  # Make it a bit nicer for text.
-  $tview->set_wrap_mode ('word');
-  $tview->set_pixels_above_lines (2);
-  $tview->set_pixels_below_lines (2);
-  # $scrolled_window->set_placement('bottom_left' );
-  add_colors_to_textview($tview);
-  
-  
-  $scrolled_window->show_all;
-  	
-  return ($scrolled_window,$tview);
+    my $scrolled_window = Gtk3::ScrolledWindow->new;
+    $scrolled_window->set_policy ('automatic', 'automatic');
+    $scrolled_window->set_shadow_type ('in');
+    my $tview = Gtk3::TextView->new();
+    $scrolled_window->add ($tview);
+    # Make it a bit nicer for text.
+    $tview->set_wrap_mode ('word');
+    $tview->set_pixels_above_lines (2);
+    $tview->set_pixels_below_lines (2);
+    # $scrolled_window->set_placement('bottom_left' );
+    add_colors_to_textview($tview);
+    $scrolled_window->show_all;
+    return ($scrolled_window,$tview);
 }
 
-
 sub txview_scrol_to_end {
-  my $tview =shift;
-  my $buffer =  $tview->get_buffer;
-  my $end_mark = $buffer->create_mark( 'end', $buffer->get_end_iter, 0 );
-  $tview->scroll_to_mark( $end_mark, 0.0,0, 0.0, 1.0 );	
+    my $tview =shift;
+    my $buffer =  $tview->get_buffer;
+    my $end_mark = $buffer->create_mark( 'end', $buffer->get_end_iter, 0 );
+    $tview->scroll_to_mark( $end_mark, 0.0,0, 0.0, 1.0 );
 }
 
-
 #################
-#	table
+#    table
 ################
-
 sub def_table{
-	my ($row,$col,$homogeneous)=@_;
-	my $table = Gtk3::Table->new ($row, $col, $homogeneous);
-	$table->set_row_spacings (0);
-	$table->set_col_spacings (0);
-	return $table;
-
+    my ($row,$col,$homogeneous)=@_;
+    my $table = Gtk3::Table->new ($row, $col, $homogeneous);
+    $table->set_row_spacings (0);
+    $table->set_col_spacings (0);
+    return $table;
 }
 
 sub attach_widget_to_table {
-	my ($table,$row,$label,$inf_bt,$widget,$column)=@_;
-	$column = 0 if(!defined $column);
-	#$column *=4;
-	#my $tmp=gen_label_in_left(" "); 
-	if(defined $label)  {$table->attach  ($label , $column, $column+1,  $row,$row+1,'fill','shrink',2,2);$column++;}
-	if(defined $inf_bt) {$table->attach  ($inf_bt , $column, $column+1, $row,$row+1,'fill','shrink',2,2);$column++;}
-	if(defined $widget) {$table->attach  ($widget , $column, $column+1, $row,$row+1,'fill','shrink',2,2);$column++;}
-	#$table->attach  ($tmp , $column+3, $column+4, $row,$row+1,'fill','shrink',2,2);
+    my ($table,$row,$label,$inf_bt,$widget,$column)=@_;
+    $column = 0 if(!defined $column);
+    #$column *=4;
+    #my $tmp=gen_label_in_left(" ");
+    if(defined $label)  {$table->attach  ($label , $column, $column+1,  $row,$row+1,'fill','shrink',2,2);$column++;}
+    if(defined $inf_bt) {$table->attach  ($inf_bt , $column, $column+1, $row,$row+1,'fill','shrink',2,2);$column++;}
+    if(defined $widget) {$table->attach  ($widget , $column, $column+1, $row,$row+1,'fill','shrink',2,2);$column++;}
+    #$table->attach  ($tmp , $column+3, $column+4, $row,$row+1,'fill','shrink',2,2);
 }
 
-sub gen_Hsep { 
-	return Gtk3::HSeparator->new;
+sub gen_Hsep {
+    return Gtk3::HSeparator->new;
 }
 
-sub gen_Vsep { 
-	return Gtk3::VSeparator->new;
+sub gen_Vsep {
+    return Gtk3::VSeparator->new;
 }
 
-
 sub add_Hsep_to_table {
-	my($table,$col0,$col1,$row)=@_;
-	my $separator = gen_Hsep();	
-	$table->attach ($separator ,$col0,$col1 , $row, $row+1,'fill','fill',2,2);	
+    my($table,$col0,$col1,$row)=@_;
+    my $separator = gen_Hsep();
+    $table->attach ($separator ,$col0,$col1 , $row, $row+1,'fill','fill',2,2);
 }
 
 sub add_Vsep_to_table {
-	my($table,$col,$row1,$row2)=@_;
-	my $separator = gen_Vsep();	
-	$table->attach ($separator ,$col,$col+1 , $row1, $row2,'fill','fill',2,2);	
+    my($table,$col,$row1,$row2)=@_;
+    my $separator = gen_Vsep();
+    $table->attach ($separator ,$col,$col+1 , $row1, $row2,'fill','fill',2,2);
 }
 
-
 ##################
-#	show_info
+#    show_info
 ##################
 sub show_info{
-	my ($textview,$info)=@_;
-	#return;# if(!defined $textview_ref);
-	#print "$textview_ref\n";
-	my $buffer = $textview->get_buffer();
-  	$buffer->set_text($info);
-  	txview_scrol_to_end($textview);
+    my ($textview,$info)=@_;
+    #return;# if(!defined $textview_ref);
+    #print "$textview_ref\n";
+    my $buffer = $textview->get_buffer();
+    $buffer->set_text($info);
+    txview_scrol_to_end($textview);
 }
 
 sub add_info{
-	my ($textview,$info)=@_;
-	my $buffer = $textview->get_buffer();
-	my $textiter = $buffer->get_end_iter();
-	#Insert some text into the buffer
-	$buffer->insert($textiter,$info);
-	txview_scrol_to_end($textview);
-	
+    my ($textview,$info)=@_;
+    my $buffer = $textview->get_buffer();
+    my $textiter = $buffer->get_end_iter();
+    #Insert some text into the buffer
+    $buffer->insert($textiter,$info);
+    txview_scrol_to_end($textview);
 }
 
-
-
-
 sub show_colored_info{
-	my ($textview,$info,$color)=@_;
-	my $buffer = $textview->get_buffer();
-  	#$buffer->set_text($info);
-	my $textiter = $buffer->get_start_iter();
-	$buffer->insert_with_tags_by_name ($textiter, "$info", "${color}_tag");
-	txview_scrol_to_end($textview);
+    my ($textview,$info,$color)=@_;
+    my $buffer = $textview->get_buffer();
+    #$buffer->set_text($info);
+    my $textiter = $buffer->get_start_iter();
+    $buffer->insert_with_tags_by_name ($textiter, "$info", "${color}_tag");
+    txview_scrol_to_end($textview);
 }
 
 sub add_colored_info{
-	my ($textview,$info,$color)=@_;
-	my $buffer = $textview->get_buffer();
-	my $textiter = $buffer->get_end_iter();
-	#Insert some text into the buffer
-	#$buffer->insert($textiter,$info);
-	$buffer->insert_with_tags_by_name ($textiter, "$info", "${color}_tag");
-	txview_scrol_to_end($textview);	
+    my ($textview,$info,$color)=@_;
+    my $buffer = $textview->get_buffer();
+    my $textiter = $buffer->get_end_iter();
+    #Insert some text into the buffer
+    #$buffer->insert($textiter,$info);
+    $buffer->insert_with_tags_by_name ($textiter, "$info", "${color}_tag");
+    txview_scrol_to_end($textview);
 }
 
 sub add_colors_to_textview{
-	my $tview= shift;
-	add_colored_tag($tview,'red');
-	add_colored_tag($tview,'blue');
-	add_colored_tag($tview,'brown');
-	add_colored_tag($tview,'green');
+    my $tview= shift;
+    add_colored_tag($tview,'red');
+    add_colored_tag($tview,'blue');
+    add_colored_tag($tview,'brown');
+    add_colored_tag($tview,'green');
 }
 
-
 sub add_colored_tag{
-	my ($textview_ref,$color)=@_;
-	my $buffer = $textview_ref->get_buffer();
-  	$buffer->create_tag ("${color}_tag", foreground => $color);  
+    my ($textview_ref,$color)=@_;
+    my $buffer = $textview_ref->get_buffer();
+    $buffer->create_tag ("${color}_tag", foreground => $color);
 }
 
 sub add_color_to_gd{
-	foreach (my $i=0;$i<32;$i++ ) {
-		my ($red,$green,$blue)=get_color($i);	    
-		add_colour("my_color$i"=>[$red>>8,$green>>8,$blue>>8]);
-		
-	}	
+    foreach (my $i=0;$i<32;$i++ ) {
+        my ($red,$green,$blue)=get_color($i);
+        add_colour("my_color$i"=>[$red>>8,$green>>8,$blue>>8]);
+    }
 }
 
-
-
 ############
-#	get file folder list
+#    get file folder list
 ###########
-
 sub get_directory_name_widget {
-	my ($object,$title,$entry,$attribute1,$attribute2,$status,$timeout)= @_;
-	my $browse= def_image_button("icons/browse.png");
-
-	$browse->signal_connect("clicked"=> sub{
-		my $entry_ref=$_[1];
- 		my $file;
-		$title ='select directory' if(!defined $title);
-		my $dialog = Gtk3::FileChooserDialog->new(
-		    	$title, undef,
-			#       	'open',
-			'select-folder',
-		    	'gtk-cancel' => 'cancel',
-		    	'gtk-ok'     => 'ok',
-			);
-	       
-			
-			if ( "ok" eq $dialog->run ) {
-		    	$file = $dialog->get_filename;
-				$$entry_ref->set_text($file);
-				$object->object_add_attribute($attribute1,$attribute2,$file);
-				set_gui_status($object,$status,$timeout) if(defined $status);			
-				#check_input_file($file,$socgen,$soc_state,$info);
-		    		#print "file = $file\n";
-	       		 }
-				$dialog->set_transient_for (Gtk3::Window->new('toplevel'));#just to get rid of transient warning
-	       		$dialog->destroy;
-	       		
-
-
-		} , \$entry);
-	
-	return $browse;
-
+    my ($object,$title,$entry,$attribute1,$attribute2,$status,$timeout)= @_;
+    my $browse= def_image_button("icons/browse.png");
+    $browse->signal_connect("clicked"=> sub{
+        my $entry_ref=$_[1];
+        my $file;
+        $title ='select directory' if(!defined $title);
+        my $dialog = Gtk3::FileChooserDialog->new(
+                $title, undef,
+            #           'open',
+            'select-folder',
+                'gtk-cancel' => 'cancel',
+                'gtk-ok'     => 'ok',
+            );
+            if ( "ok" eq $dialog->run ) {
+                $file = $dialog->get_filename;
+                $$entry_ref->set_text($file);
+                $object->object_add_attribute($attribute1,$attribute2,$file);
+                set_gui_status($object,$status,$timeout) if(defined $status);
+                #check_input_file($file,$socgen,$soc_state,$info);
+                    #print "file = $file\n";
+                    }
+                $dialog->set_transient_for (Gtk3::Window->new('toplevel'));#just to get rid of transient warning
+                $dialog->destroy;
+        } , \$entry);
+    return $browse;
 }
 
-
 sub get_dir_name {
-	my ($object,$title,$attribute1,$attribute2,$open_in,$status,$timeout)= @_;
-	my $dir;
-	$title ='select directory' if(!defined $title);
-	my $dialog = Gtk3::FileChooserDialog->new(
-	  	$title, undef,
-		#       	'open',
-		'select-folder',
-	   	'gtk-cancel' => 'cancel',
-	   	'gtk-ok'     => 'ok',
-	);
-
-	$dialog->set_transient_for (Gtk3::Window->new('toplevel'));#just to get rid of transient warning
-
-	if(defined  $open_in){
-		$dialog->set_current_folder ($open_in); 
-	}
-	       			
-	if ( "ok" eq $dialog->run ) {
-		    	$dir = $dialog->get_filename;
-				$object->object_add_attribute($attribute1,$attribute2,$dir);
-				set_gui_status($object,$status,$timeout) if(defined $status);	
-				$dialog->destroy;
-	}
+    my ($object,$title,$attribute1,$attribute2,$open_in,$status,$timeout)= @_;
+    my $dir;
+    $title ='select directory' if(!defined $title);
+    my $dialog = Gtk3::FileChooserDialog->new(
+        $title, undef,
+        #           'open',
+        'select-folder',
+        'gtk-cancel' => 'cancel',
+        'gtk-ok'     => 'ok',
+    );
+    $dialog->set_transient_for (Gtk3::Window->new('toplevel'));#just to get rid of transient warning
+    if(defined  $open_in){
+        $dialog->set_current_folder ($open_in);
+    }
+    if ( "ok" eq $dialog->run ) {
+                $dir = $dialog->get_filename;
+                $object->object_add_attribute($attribute1,$attribute2,$dir);
+                set_gui_status($object,$status,$timeout) if(defined $status);
+                $dialog->destroy;
+    }
 }
 
-
-
 sub get_file_name {
-	my ($object,$title,$entry,$attribute1,$attribute2,$extension,$label,$open_in,$new_status,$ref_delay)= @_;
-	my $browse= def_image_button("icons/browse.png");
-	
-	$browse->signal_connect("clicked"=> sub{
-		my $entry_ref=$_[1];
- 		my $file;
-		$title ='select a file' if(!defined $title);
-		my $dialog = Gtk3::FileChooserDialog->new(
-            	'Select a File', undef,
-            	'open',
-            	'gtk-cancel' => 'cancel',
-            	'gtk-ok'     => 'ok',
-        	);
-
-	$dialog->set_transient_for (Gtk3::Window->new('toplevel'));#just to get rid of transient warning
-
-	 if(defined $extension){
-		my $filter = Gtk3::FileFilter->new();
-		$filter->set_name($extension);
-		$filter->add_pattern("*.$extension");
-		$dialog->add_filter ($filter);
-	 }
-	  if(defined  $open_in){
-		$dialog->set_current_folder ($open_in); 
-		# print "$open_in\n";
-		 
-	}
-		
-			if ( "ok" eq $dialog->run ) {
-		    	$file = $dialog->get_filename;
-				#remove $project_dir form beginig of each file
-            	$file =remove_project_dir_from_addr($file); 
-				$$entry_ref->set_text($file);
-				$object->object_add_attribute($attribute1,$attribute2,$file) if(defined $object);
-				set_gui_status($object,$new_status,$ref_delay) if(defined $ref_delay);
-				my ($name,$path,$suffix) = fileparse("$file",qr"\..[^.]*$");
-				if(defined $label){
-					$label->set_markup("<span  foreground= 'black' ><b>$name$suffix</b></span>");
-					$label->show;
-				}
-						
-				#check_input_file($file,$socgen,$soc_state,$info);
-		    		#print "file = $file\n";
-	       		 }
-	       		$dialog->destroy;
-	       		
-
-
-		} , \$entry);
-	
-	return $browse;
-
+    my ($object,$title,$entry,$attribute1,$attribute2,$extension,$label,$open_in,$new_status,$ref_delay)= @_;
+    my $browse= def_image_button("icons/browse.png");
+    $browse->signal_connect("clicked"=> sub{
+        my $entry_ref=$_[1];
+        my $file;
+        $title ='select a file' if(!defined $title);
+        my $dialog = Gtk3::FileChooserDialog->new(
+                'Select a File', undef,
+                'open',
+                'gtk-cancel' => 'cancel',
+                'gtk-ok'     => 'ok',
+            );
+    $dialog->set_transient_for (Gtk3::Window->new('toplevel'));#just to get rid of transient warning
+    if(defined $extension){
+        my $filter = Gtk3::FileFilter->new();
+        $filter->set_name($extension);
+        $filter->add_pattern("*.$extension");
+        $dialog->add_filter ($filter);
+    }
+    if(defined  $open_in){
+        $dialog->set_current_folder ($open_in);
+        # print "$open_in\n";
+    }
+    if ( "ok" eq $dialog->run ) {
+        $file = $dialog->get_filename;
+        #remove $project_dir form beginig of each file
+        $file =remove_project_dir_from_addr($file);
+        $$entry_ref->set_text($file);
+        $object->object_add_attribute($attribute1,$attribute2,$file) if(defined $object);
+        set_gui_status($object,$new_status,$ref_delay) if(defined $ref_delay);
+        my ($name,$path,$suffix) = fileparse("$file",qr"\..[^.]*$");
+        if(defined $label){
+            $label->set_markup("<span  foreground= 'black' ><b>$name$suffix</b></span>");
+            $label->show;
+        }
+        #check_input_file($file,$socgen,$soc_state,$info);
+        #print "file = $file\n";
+    }
+    $dialog->destroy;
+    } , \$entry);
+    return $browse;
 }
 
 sub gen_file_dialog  {
-	my ($title, @extension)=@_;
-	$title = 'Select a File' if (!defined $title);
-
-	my $dialog = Gtk3::FileChooserDialog->new(
-            	$title, 
-				undef,
-            	'open',
-            	'gtk-cancel' => 'cancel',
-            	'gtk-ok'     => 'ok',
-     );
-
-	$dialog->set_modal(TRUE);
-	$dialog->set_transient_for (Gtk3::Window->new('toplevel'));#just to get rid of transient warning
-
-	foreach my $ext (@extension){
-		my $filter = Gtk3::FileFilter->new();
-		$filter->set_name("$ext");
-		$filter->add_pattern("*.$ext");
-		$dialog->add_filter ($filter);
-	}	
-
-	return $dialog;
-
+    my ($title, @extension)=@_;
+    $title = 'Select a File' if (!defined $title);
+    my $dialog = Gtk3::FileChooserDialog->new(
+                $title,
+                undef,
+                'open',
+                'gtk-cancel' => 'cancel',
+                'gtk-ok'     => 'ok',
+    );
+    $dialog->set_modal(TRUE);
+    $dialog->set_transient_for (Gtk3::Window->new('toplevel'));#just to get rid of transient warning
+    foreach my $ext (@extension){
+        my $filter = Gtk3::FileFilter->new();
+        $filter->set_name("$ext");
+        $filter->add_pattern("*.$ext");
+        $dialog->add_filter ($filter);
+    }
+    return $dialog;
 }
 
-
 sub save_file_dialog  {
-	my ($title, @extension)=@_;
-	$title = 'Select a File' if (!defined $title);
-
-	my $dialog = Gtk3::FileChooserDialog->new(
-            	$title, 
-				undef,
-            	'save',
-            	'gtk-cancel' => 'cancel',
-            	'gtk-ok'     => 'ok',
-     );
-
-	$dialog->set_modal(TRUE);
-	$dialog->set_transient_for (Gtk3::Window->new('toplevel'));#just to get rid of transient warning
-
-	foreach my $ext (@extension){
-		my $filter = Gtk3::FileFilter->new();
-		$filter->set_name("$ext");
-		$filter->add_pattern("*.$ext");
-		$dialog->add_filter ($filter);
-	}	
-
-	return $dialog;
-
+    my ($title, @extension)=@_;
+    $title = 'Select a File' if (!defined $title);
+    my $dialog = Gtk3::FileChooserDialog->new(
+                $title,
+                undef,
+                'save',
+                'gtk-cancel' => 'cancel',
+                'gtk-ok'     => 'ok',
+    );
+    $dialog->set_modal(TRUE);
+    $dialog->set_transient_for (Gtk3::Window->new('toplevel'));#just to get rid of transient warning
+    foreach my $ext (@extension){
+        my $filter = Gtk3::FileFilter->new();
+        $filter->set_name("$ext");
+        $filter->add_pattern("*.$ext");
+        $dialog->add_filter ($filter);
+    }
+    return $dialog;
 }
 
-
-
-
 sub gen_folder_dialog  {
-	my ($title)=@_;
-	$title = 'Select Folder' if (!defined $title);
-	
-	
-
-	my $dialog = Gtk3::FileChooserDialog->new(
-		$title, 
-		undef,
-		'select-folder',
-	   	'gtk-cancel' => 'cancel',
-	   	'gtk-ok'     => 'ok',
-     );
-	$dialog->set_modal(TRUE);
-	$dialog->set_transient_for (Gtk3::Window->new('toplevel'));#just to get rid of transient warning
-	
-	return $dialog;
-
+    my ($title)=@_;
+    $title = 'Select Folder' if (!defined $title);
+    my $dialog = Gtk3::FileChooserDialog->new(
+        $title,
+        undef,
+        'select-folder',
+        'gtk-cancel' => 'cancel',
+        'gtk-ok'     => 'ok',
+    );
+    $dialog->set_modal(TRUE);
+    $dialog->set_transient_for (Gtk3::Window->new('toplevel'));#just to get rid of transient warning
+    return $dialog;
 }
 
-
 sub get_filenames_from_dialog{
-	my $dialog=shift;
-	my $ref = $dialog->get_filenames;
-	my @files;
-	@files = @{$ref} if (defined $ref); 
-	return @files;
+    my $dialog=shift;
+    my $ref = $dialog->get_filenames;
+    my @files;
+    @files = @{$ref} if (defined $ref);
+    return @files;
 }
 
-
 sub new_dialog_with_buttons {
-	my $self =shift;
-	return Gtk3::Dialog->new_with_buttons(
-		"Goto to line",
-		$self->window,
-		[ 'modal' ],
-		'gtk-cancel' => 'cancel',
-		'gtk-ok'     => 'ok',
-	);
-
+    my $self =shift;
+    return Gtk3::Dialog->new_with_buttons(
+        "Goto to line",
+        $self->window,
+        [ 'modal' ],
+        'gtk-cancel' => 'cancel',
+        'gtk-ok'     => 'ok',
+    );
 }
 
-
 #################
-#	widget update object
+#    widget update object
 #################
-
 sub gen_entry_object {
-	my ($object,$attribute1,$attribute2,$default,$status,$timeout)=@_;
-	my $old=$object->object_get_attribute($attribute1,$attribute2);
-	my $widget;
-	if(defined $old ){
-		$widget=gen_entry($old);
-	}
-	else
-	{
-		$widget=gen_entry($default);
-		$object->object_add_attribute($attribute1,$attribute2,$default);		
-	}	
-	$widget-> signal_connect("changed" => sub{
-		my $new_param_value=$widget->get_text();
-		$object->object_add_attribute($attribute1,$attribute2,$new_param_value);
-		set_gui_status($object,$status,$timeout) if (defined $status);
-	});
-	return $widget;
+    my ($object,$attribute1,$attribute2,$default,$status,$timeout)=@_;
+    my $old=$object->object_get_attribute($attribute1,$attribute2);
+    my $widget;
+    if(defined $old ){
+        $widget=gen_entry($old);
+    }
+    else
+    {
+        $widget=gen_entry($default);
+        $object->object_add_attribute($attribute1,$attribute2,$default);
+    }
+    $widget-> signal_connect("changed" => sub{
+        my $new_param_value=$widget->get_text();
+        $object->object_add_attribute($attribute1,$attribute2,$new_param_value);
+        set_gui_status($object,$status,$timeout) if (defined $status);
+    });
+    return $widget;
 }
 
-
 sub gen_combobox_object {
- 	my ($object,$attribute1,$attribute2,$content,$default,$status,$timeout)=@_;
-	my @combo_list=split(/\s*,\s*/,$content);
-	my $value=$object->object_get_attribute($attribute1,$attribute2);
-	my $pos;
-	$pos=get_pos($value, @combo_list) if (defined $value);
-	if(!defined $pos && defined $default){
-		$object->object_add_attribute($attribute1,$attribute2,$default);	
-	 	$pos=get_item_pos($default, @combo_list);
-	}
-	#print " my $pos=get_item_pos($value, @combo_list);\n";
-	my $widget=gen_combo(\@combo_list, $pos);
-	$widget-> signal_connect("changed" => sub{
-		my $new_param_value=$widget->get_active_text();
-		$object->object_add_attribute($attribute1,$attribute2,$new_param_value);
-		set_gui_status($object,$status,$timeout) if (defined $status);
-	 });
-	return $widget;
+    my ($object,$attribute1,$attribute2,$content,$default,$status,$timeout)=@_;
+    my @combo_list=split(/\s*,\s*/,$content);
+    my $value=$object->object_get_attribute($attribute1,$attribute2);
+    my $pos;
+    $pos=get_pos($value, @combo_list) if (defined $value);
+    if(!defined $pos && defined $default){
+        $object->object_add_attribute($attribute1,$attribute2,$default);
+        $pos=get_item_pos($default, @combo_list);
+    }
+    #print " my $pos=get_item_pos($value, @combo_list);\n";
+    my $widget=gen_combo(\@combo_list, $pos);
+    $widget-> signal_connect("changed" => sub{
+        my $new_param_value=$widget->get_active_text();
+        $object->object_add_attribute($attribute1,$attribute2,$new_param_value);
+        set_gui_status($object,$status,$timeout) if (defined $status);
+    });
+    return $widget;
 }
 
-
 sub gen_comboentry_object {
- 	my ($object,$attribute1,$attribute2,$content,$default,$status,$timeout)=@_;
-	my @combo_list;
-	@combo_list=split(/\s*,\s*/,$content) if(defined $content );
-	my $value=$object->object_get_attribute($attribute1,$attribute2);
-	my $pos;
-	$pos=get_pos($value, @combo_list) if (defined $value);
-	if(!defined $pos && defined $default){
-		$object->object_add_attribute($attribute1,$attribute2,$default);	
-	 	$pos=get_item_pos($default, @combo_list);
-	}
-	#print " my $pos=get_item_pos($value, @combo_list);\n";
-	
-	my $widget=gen_combo_entry(\@combo_list, $pos);
-	my $child = combo_entry_get_chiled($widget);
-	$child->signal_connect('changed' => sub {
-		my ($entry) = @_;
-		my $new_param_value=$entry->get_text();
-		$object->object_add_attribute($attribute1,$attribute2,$new_param_value);
-		set_gui_status($object,$status,$timeout) if (defined $status);
-	 });
-	return $widget;	
-
+    my ($object,$attribute1,$attribute2,$content,$default,$status,$timeout)=@_;
+    my @combo_list;
+    @combo_list=split(/\s*,\s*/,$content) if(defined $content );
+    my $value=$object->object_get_attribute($attribute1,$attribute2);
+    my $pos;
+    $pos=get_pos($value, @combo_list) if (defined $value);
+    if(!defined $pos && defined $default){
+        $object->object_add_attribute($attribute1,$attribute2,$default);
+        $pos=get_item_pos($default, @combo_list);
+    }
+    #print " my $pos=get_item_pos($value, @combo_list);\n";
+    my $widget=gen_combo_entry(\@combo_list, $pos);
+    my $child = combo_entry_get_chiled($widget);
+    $child->signal_connect('changed' => sub {
+        my ($entry) = @_;
+        my $new_param_value=$entry->get_text();
+        $object->object_add_attribute($attribute1,$attribute2,$new_param_value);
+        set_gui_status($object,$status,$timeout) if (defined $status);
+    });
+    return $widget;
 }
 
-
-
 sub gen_spin_object {
-	my ($object,$attribute1,$attribute2,$content, $default,$status,$timeout)=@_;
-	my $value=$object->object_get_attribute($attribute1,$attribute2);
-	my ($min,$max,$step,$digit)=split(/\s*,\s*/,$content);
-	if(!defined $value){
-		$value=$default;
-		$object->object_add_attribute($attribute1,$attribute2,$value);
-	}
-	
-	$value=~ s/[^0-9.\-]//g;
-	$min=~   s/[^0-9.\-]//g;
-	$max=~   s/[^0-9.\-]//g;
-	$step=~  s/[^0-9.\-]//g;
-	$digit=~ s/[^0-9.\-]//g if (defined $digit);
-	
-	my $widget=gen_spin($min,$max,$step,$digit);
-	$widget->set_value($value);
-	$widget-> signal_connect("value_changed" => sub{
-		my $new_param_value=$widget->get_value();
-		$object->object_add_attribute($attribute1,$attribute2,$new_param_value);
-		set_gui_status($object,$status,$timeout) if (defined $status);
-	});
-	return $widget;		
+    my ($object,$attribute1,$attribute2,$content, $default,$status,$timeout)=@_;
+    my $value=$object->object_get_attribute($attribute1,$attribute2);
+    my ($min,$max,$step,$digit)=split(/\s*,\s*/,$content);
+    if(!defined $value){
+        $value=$default;
+        $object->object_add_attribute($attribute1,$attribute2,$value);
+    }
+    $value=~ s/[^0-9.\-]//g;
+    $min=~   s/[^0-9.\-]//g;
+    $max=~   s/[^0-9.\-]//g;
+    $step=~  s/[^0-9.\-]//g;
+    $digit=~ s/[^0-9.\-]//g if (defined $digit);
+    my $widget=gen_spin($min,$max,$step,$digit);
+    $widget->set_value($value);
+    $widget-> signal_connect("value_changed" => sub{
+        my $new_param_value=$widget->get_value();
+        $object->object_add_attribute($attribute1,$attribute2,$new_param_value);
+        set_gui_status($object,$status,$timeout) if (defined $status);
+    });
+    return $widget;
 }
 
-
 sub gen_check_box_object_array {
-		my ($object,$attribute1,$attribute2,$content,$default,$status,$timeout)=@_;
-    		my $value=$object->object_get_attribute($attribute1,$attribute2);
-		$value = $default if (!defined $value);
-		my $widget = def_hbox(FALSE,0);
-		my @check;
-		for (my $i=0;$i<$content;$i++){
-			$check[$i]= gen_checkbutton();
-		}
-		for (my $i=0;$i<$content;$i++){
-			$widget->pack_end(  $check[$i], FALSE, FALSE, 0);
-			
-			my @chars = split("",$value);
-			#check if saved value match the size of check box
-			if($chars[0] ne $content ) {
-				$object->object_add_attribute($attribute1,$attribute2,$default);
-				$value=$default;
-				@chars = split("",$value);
-			}
-			#set initial value
-			
-			#print "\@chars=@chars\n";
-			for (my $i=0;$i<$content;$i++){
-				my $loc= (scalar @chars) -($i+1);
-					if( $chars[$loc] eq '1') {$check[$i]->set_active(TRUE);}
-					else {$check[$i]->set_active(FALSE);}
-			}
-
-
-			#get new value
-			$check[$i]-> signal_connect("toggled" => sub{
-				my $new_val="$content\'b";			
- 				
-				for (my $i=$content-1; $i >= 0; $i--){
-					if($check[$i]->get_active()) {$new_val="${new_val}1" ;}
-					else {$new_val="${new_val}0" ;}
-				}
-				$object->object_add_attribute($attribute1,$attribute2,$new_val);
-				#print "\$new_val=$new_val\n";
-				set_gui_status($object,$status,$timeout) if (defined $status);
-			});
-	}
-	return $widget;
-
+        my ($object,$attribute1,$attribute2,$content,$default,$status,$timeout)=@_;
+            my $value=$object->object_get_attribute($attribute1,$attribute2);
+        $value = $default if (!defined $value);
+        my $widget = def_hbox(FALSE,0);
+        my @check;
+        for (my $i=0;$i<$content;$i++){
+            $check[$i]= gen_checkbutton();
+        }
+        for (my $i=0;$i<$content;$i++){
+            $widget->pack_end(  $check[$i], FALSE, FALSE, 0);
+            my @chars = split("",$value);
+            #check if saved value match the size of check box
+            if($chars[0] ne $content ) {
+                $object->object_add_attribute($attribute1,$attribute2,$default);
+                $value=$default;
+                @chars = split("",$value);
+            }
+            #set initial value
+            #print "\@chars=@chars\n";
+            for (my $i=0;$i<$content;$i++){
+                my $loc= (scalar @chars) -($i+1);
+                    if( $chars[$loc] eq '1') {$check[$i]->set_active(TRUE);}
+                    else {$check[$i]->set_active(FALSE);}
+            }
+            #get new value
+            $check[$i]-> signal_connect("toggled" => sub{
+                my $new_val="$content\'b";
+                for (my $i=$content-1; $i >= 0; $i--){
+                    if($check[$i]->get_active()) {$new_val="${new_val}1" ;}
+                    else {$new_val="${new_val}0" ;}
+                }
+                $object->object_add_attribute($attribute1,$attribute2,$new_val);
+                #print "\$new_val=$new_val\n";
+                set_gui_status($object,$status,$timeout) if (defined $status);
+            });
+    }
+    return $widget;
 }
 
-
-
-
-
 sub gen_check_box_object {
-		my ($object,$attribute1,$attribute2,$default,$status,$timeout)=@_;
-    		my $value=$object->object_get_attribute($attribute1,$attribute2);
-		if (!defined $value){
-			#set initial value
-			$object->object_add_attribute($attribute1,$attribute2,$default);
-			$value = $default 
-		}
-		my $widget = Gtk3::CheckButton->new;
-		if($value == 1) {$widget->set_active(TRUE);}
-		else {$widget->set_active(FALSE);}
-		
-		#get new value
-		$widget-> signal_connect("toggled" => sub{
-			my $new_val;
-			if($widget->get_active()) {$new_val=1;}
-			else {$new_val=0;}
-			$object->object_add_attribute($attribute1,$attribute2,$new_val);
-			#print "\$new_val=$new_val\n";
-			set_gui_status($object,$status,$timeout) if (defined $status);
-		});
-	
-	return $widget;
-
+        my ($object,$attribute1,$attribute2,$default,$status,$timeout)=@_;
+            my $value=$object->object_get_attribute($attribute1,$attribute2);
+        if (!defined $value){
+            #set initial value
+            $object->object_add_attribute($attribute1,$attribute2,$default);
+            $value = $default
+        }
+        my $widget = Gtk3::CheckButton->new;
+        if($value == 1) {$widget->set_active(TRUE);}
+        else {$widget->set_active(FALSE);}
+        #get new value
+        $widget-> signal_connect("toggled" => sub{
+            my $new_val;
+            if($widget->get_active()) {$new_val=1;}
+            else {$new_val=0;}
+            $object->object_add_attribute($attribute1,$attribute2,$new_val);
+            #print "\$new_val=$new_val\n";
+            set_gui_status($object,$status,$timeout) if (defined $status);
+        });
+    return $widget;
 }
 
-
-
-
-
-
 sub get_dir_in_object {
-	my ($object,$attribute1,$attribute2,$content,$status,$timeout,$default)=@_;
-	my $widget = def_hbox(FALSE,0);
-	my $value=$object->object_get_attribute($attribute1,$attribute2);
-	$object->object_add_attribute($attribute1,$attribute2,  $default) if (!defined $value );
-	$value = $default if (!defined $value );
-	if (defined $default){
-		$object->object_add_attribute($attribute1,$attribute2,  $default) if  !(-d $value );
-		$value = $default  if !(-d $value );
-	};
-	
-	my $warning;
-	
-	my $entry=gen_entry($value);
-	$entry-> signal_connect("changed" => sub{
-		my $new_param_value=$entry->get_text();
-		$object->object_add_attribute($attribute1,$attribute2,$new_param_value);
-		set_gui_status($object,$status,$timeout) if (defined $status);
-		unless (-d $new_param_value ){
-			if (!defined $warning){
-				$warning = def_icon("icons/warning.png");
-				$widget->pack_start( $warning, FALSE, FALSE, 0);
-				set_tip($warning,"$new_param_value is not a valid directory");
-				$widget->show_all;
-			}
-			
-		}else{
-			$warning->destroy if (defined $warning); 
-			undef $warning;
-			
-		}
-	
-	});
-	my $browse= get_directory_name_widget($object,undef,$entry,$attribute1,$attribute2,$status,$timeout);
-	
-	$widget->pack_start( $entry, FALSE, FALSE, 0);
-	$widget->pack_start( $browse, FALSE, FALSE, 0);
-	
-	 if(defined $value){
-		unless (-d $value ){
-		 	$warning= def_icon("icons/warning.png");	
-			$widget->pack_start( $warning, FALSE, FALSE, 0); 
-			set_tip($warning,"$value is not a valid directory path");
-		}
-	}
-	return $widget;
+    my ($object,$attribute1,$attribute2,$content,$status,$timeout,$default)=@_;
+    my $widget = def_hbox(FALSE,0);
+    my $value=$object->object_get_attribute($attribute1,$attribute2);
+    $object->object_add_attribute($attribute1,$attribute2,  $default) if (!defined $value );
+    $value = $default if (!defined $value );
+    if (defined $default){
+        $object->object_add_attribute($attribute1,$attribute2,  $default) if  !(-d $value );
+        $value = $default  if !(-d $value );
+    };
+    my $warning;
+    my $entry=gen_entry($value);
+    $entry-> signal_connect("changed" => sub{
+        my $new_param_value=$entry->get_text();
+        $object->object_add_attribute($attribute1,$attribute2,$new_param_value);
+        set_gui_status($object,$status,$timeout) if (defined $status);
+        unless (-d $new_param_value ){
+            if (!defined $warning){
+                $warning = def_icon("icons/warning.png");
+                $widget->pack_start( $warning, FALSE, FALSE, 0);
+                set_tip($warning,"$new_param_value is not a valid directory");
+                $widget->show_all;
+            }
+        }else{
+            $warning->destroy if (defined $warning);
+            undef $warning;
+        }
+    });
+    my $browse= get_directory_name_widget($object,undef,$entry,$attribute1,$attribute2,$status,$timeout);
+    $widget->pack_start( $entry, FALSE, FALSE, 0);
+    $widget->pack_start( $browse, FALSE, FALSE, 0);
+    if(defined $value){
+        unless (-d $value ){
+            $warning= def_icon("icons/warning.png");
+            $widget->pack_start( $warning, FALSE, FALSE, 0);
+            set_tip($warning,"$value is not a valid directory path");
+        }
+    }
+    return $widget;
 }
 
-
-
-
 sub get_file_name_object {
-	my ($object,$attribute1,$attribute2,$extension,$open_in,$new_status,$ref_delay)=@_;
-	my $widget = def_hbox(FALSE,0);
-	my $value=$object->object_get_attribute($attribute1,$attribute2);
-	my $label;
-	if(defined $value){
-		my ($name,$path,$suffix) = fileparse("$value",qr"\..[^.]*$");
-		$label=gen_label_in_center($name.$suffix);
-		
-	} else {
-			$label=gen_label_in_center("Selecet a file");
-			$label->set_markup("<span  foreground= 'red' ><b>No file has been selected yet</b></span>");
-	}
-	my $entry=gen_entry();
-	my $browse= get_file_name($object,undef,$entry,$attribute1,$attribute2,$extension,$label,$open_in,$new_status,$ref_delay);
-	$widget->pack_start( $label, FALSE, FALSE, 0);
-	$widget->pack_start( $browse, FALSE, FALSE, 0);
-	return $widget;
+    my ($object,$attribute1,$attribute2,$extension,$open_in,$new_status,$ref_delay)=@_;
+    my $widget = def_hbox(FALSE,0);
+    my $value=$object->object_get_attribute($attribute1,$attribute2);
+    my $label;
+    if(defined $value){
+        my ($name,$path,$suffix) = fileparse("$value",qr"\..[^.]*$");
+        $label=gen_label_in_center($name.$suffix);
+    } else {
+            $label=gen_label_in_center("Selecet a file");
+            $label->set_markup("<span  foreground= 'red' ><b>No file has been selected yet</b></span>");
+    }
+    my $entry=gen_entry();
+    my $browse= get_file_name($object,undef,$entry,$attribute1,$attribute2,$extension,$label,$open_in,$new_status,$ref_delay);
+    $widget->pack_start( $label, FALSE, FALSE, 0);
+    $widget->pack_start( $browse, FALSE, FALSE, 0);
+    return $widget;
 }
 
-
-
-
-
 sub gen_notebook {
-	my $notebook = Gtk3::Notebook->new;
-	return $notebook;
+    my $notebook = Gtk3::Notebook->new;
+    return $notebook;
 }
+
 ################
 # ADD info and label to widget
 ################
-
-
 sub gen_label_info{
-	my ($label_name,$widget,$info)=@_;
-	my $box = def_hbox(FALSE,0);
-	#label
-	if(defined $label_name){
-		my $label= gen_label_in_left($label_name);	
-		$box->pack_start( $label, FALSE, FALSE, 3);
-	}
-	$box->pack_start( $widget, FALSE, FALSE, 3);
-	#info	
-	if(defined $info){
-		my $button=def_image_button("icons/help.png");
-		$button->signal_connect("clicked" => sub {message_dialog($info);});	
-		$box->pack_start( $button, FALSE, FALSE, 3);
-	}
-	$box->show_all;	
-	return $box;
-}	
-
+    my ($label_name,$widget,$info)=@_;
+    my $box = def_hbox(FALSE,0);
+    #label
+    if(defined $label_name){
+        my $label= gen_label_in_left($label_name);
+        $box->pack_start( $label, FALSE, FALSE, 3);
+    }
+    $box->pack_start( $widget, FALSE, FALSE, 3);
+    #info
+    if(defined $info){
+        my $button=def_image_button("icons/help.png");
+        $button->signal_connect("clicked" => sub {message_dialog($info);});
+        $box->pack_start( $button, FALSE, FALSE, 3);
+    }
+    $box->show_all;
+    return $box;
+}
 
 ############
 #
 ###########
-
 sub gen_MenuBar{
-	my ($window,@menu_items)=@_;
- 	
- 	my $accel_group = Gtk3::AccelGroup->new;
-   	$window->add_accel_group ($accel_group);   
-	my $menubar = Gtk3::MenuBar->new;
-	my $menu  = Gtk3::Menu->new;
+    my ($window,@menu_items)=@_;
+    my $accel_group = Gtk3::AccelGroup->new;
+    $window->add_accel_group ($accel_group);
+    my $menubar = Gtk3::MenuBar->new;
+    my $menu  = Gtk3::Menu->new;
     $menu->set_accel_group ($accel_group);
-	
-	my %all_menus;
-	foreach my $p (@menu_items){
-		my ($name,$key,$func,$u,$type)=@{$p};
-		$name =~ s/_//;	
-		my @l =split ('/',$name);
-		
-		my $m= pop @l;
-		$m =~ s/_//;	
-		my $parent = join('/',@l);
-		$parent =~ s/_//;	
-
-
-	#	print "\$parent= $parent **   \$m=$m\n";
-	#    print "   all_menus{$parent}  = $all_menus{$parent}\n";
-		my $menuitem = Gtk3::MenuItem->new_with_label($m);
-		
-		if(!defined $all_menus{$parent}){
-			my $menu  = Gtk3::Menu->new;
-		    $menu->set_accel_group ($accel_group);
-			$menuitem->set_submenu($menu);
-			$all_menus{$name}{'menu'}=$menu;
-			$all_menus{$name}{'num'}=0;
-			$menubar->append($menuitem) 
-		}else {
-			my $menu = $all_menus{$parent}{'menu'};
-			my $pos = $all_menus{$parent}{'num'};
-			$menu->insert($menuitem,$pos);
-			$all_menus{$parent}{'num'}= $pos+1;
-			if(defined $type){
-			if($type eq "<Branch>"){
-				$all_menus{$name}{'menu'}=$menu;				
-				$all_menus{$name}{'num'}=0;
-			}}
-			
-		}
-		if(defined $key){
-			$menuitem->add_accelerator('activate',$accel_group,Gtk3::accelerator_parse($key),'visible');
-		}
-		if(defined $func){
-			$menuitem->signal_connect('activate' => \&$func);
-		}
-		#print "$name,$key,$func,$u,$type\n";
-		$menuitem->show();
-	}
-
-	my $box = Gtk3::Box->new( 'vertical', 0 );
-	$box->pack_start( $menubar, FALSE, TRUE, 0 );
-	$menubar->show();
-
-	return $box;
+    my %all_menus;
+    foreach my $p (@menu_items){
+        my ($name,$key,$func,$u,$type)=@{$p};
+        $name =~ s/_//;
+        my @l =split ('/',$name);
+        my $m= pop @l;
+        $m =~ s/_//;
+        my $parent = join('/',@l);
+        $parent =~ s/_//;
+    #    print "\$parent= $parent **   \$m=$m\n";
+    #    print "   all_menus{$parent}  = $all_menus{$parent}\n";
+        my $menuitem = Gtk3::MenuItem->new_with_label($m);
+        if(!defined $all_menus{$parent}){
+            my $menu  = Gtk3::Menu->new;
+            $menu->set_accel_group ($accel_group);
+            $menuitem->set_submenu($menu);
+            $all_menus{$name}{'menu'}=$menu;
+            $all_menus{$name}{'num'}=0;
+            $menubar->append($menuitem)
+        }else {
+            my $menu = $all_menus{$parent}{'menu'};
+            my $pos = $all_menus{$parent}{'num'};
+            $menu->insert($menuitem,$pos);
+            $all_menus{$parent}{'num'}= $pos+1;
+            if(defined $type){
+            if($type eq "<Branch>"){
+                $all_menus{$name}{'menu'}=$menu;
+                $all_menus{$name}{'num'}=0;
+            }}
+        }
+        if(defined $key){
+            $menuitem->add_accelerator('activate',$accel_group,Gtk3::accelerator_parse($key),'visible');
+        }
+        if(defined $func){
+            $menuitem->signal_connect('activate' => \&$func);
+        }
+        #print "$name,$key,$func,$u,$type\n";
+        $menuitem->show();
+    }
+    my $box = Gtk3::Box->new( 'vertical', 0 );
+    $box->pack_start( $menubar, FALSE, TRUE, 0 );
+    $menubar->show();
+    return $box;
 }
 
-
-
 sub creating_detachable_toolbar{
-	my @attachments=@_;
-	return def_pack_hbox('FALSE', 0, @_);
-	#The handle box helps in creating a detachable toolbar 
-	my $hb = Gtk3::HandleBox->new;
-	#create a toolbar, and do some initial settings
-	my $toolbar = Gtk3::Toolbar->new;
-	$toolbar->set_icon_size ('small-toolbar');	
-	$toolbar->set_show_arrow (FALSE);
-	foreach my $p (@attachments){
-		$toolbar->insert($p,-1);
-		
-	}
-	$hb->add($toolbar);	
-	return $hb;
+    my @attachments=@_;
+    return def_pack_hbox('FALSE', 0, @_);
+    #The handle box helps in creating a detachable toolbar
+    my $hb = Gtk3::HandleBox->new;
+    #create a toolbar, and do some initial settings
+    my $toolbar = Gtk3::Toolbar->new;
+    $toolbar->set_icon_size ('small-toolbar');
+    $toolbar->set_show_arrow (FALSE);
+    foreach my $p (@attachments){
+        $toolbar->insert($p,-1);
+    }
+    $hb->add($toolbar);
+    return $hb;
 }
 
 sub gui_quite{
-	Gtk3->main_quit;
+    Gtk3->main_quit;
 }
 
 sub gtk_gui_run{
-	my ($main)=@_;
-	Gtk3->init;
-	&$main;
-	Gtk3->main();
-	return 1;
+    my ($main)=@_;
+    Gtk3->init;
+    &$main;
+    Gtk3->main();
+    return 1;
 }
 
-
-
-
 sub refresh_gui{
-	while (Gtk3::events_pending) {
-     Gtk3::main_iteration;
+    while (Gtk3::events_pending) {
+    Gtk3::main_iteration;
     }
-    Gtk3::Gdk::flush;  
+    Gtk3::Gdk::flush;
 }
 
-
 sub about {
     my $version=shift;
     my $about = Gtk3::AboutDialog->new;
-	my @authors=("Alireza Monemi", "Email: alirezamonemi\@opencores.org");
+    my @authors=("Alireza Monemi", "Email: alirezamonemi\@opencores.org");
     $about->set_authors(\@authors);
     $about->set_version( $version );
     $about->set_website('http://opencores.org/project,an-fpga-implementation-of-low-latency-noc-based-mpsoc');
@@ -1875,135 +1554,93 @@ sub about {
     $about->set_program_name('ProNoC');
     my $pixbuf = Gtk3::Gdk::Pixbuf->new_from_file_at_scale("icons/ProNoC.png",50,50,FALSE);
     $about->set_logo($pixbuf);
-
     $about->set_license(
-                 "This program is free software; you can redistribute it\n"
+                "This program is free software; you can redistribute it\n"
                 . "and/or modify it under the terms of the GNU General \n"
-		. "Public License as published by the Free Software \n"
-		. "Foundation; either version 1, or (at your option)\n"
-		. "any later version.\n\n"
-                 
+        . "Public License as published by the Free Software \n"
+        . "Foundation; either version 1, or (at your option)\n"
+        . "any later version.\n\n"
         );
-	# Add the Hide action to the 'Close' button in the AboutDialog():
+    # Add the Hide action to the 'Close' button in the AboutDialog():
     $about->signal_connect('response' => sub { $about->hide; });
-	
-	$about->set_transient_for (Gtk3::Window->new('toplevel'));#just to get rid of transient warning
-
+    $about->set_transient_for (Gtk3::Window->new('toplevel'));#just to get rid of transient warning
     $about->run;
     $about->destroy;
     return;
 }
 
-
-
 ############
 #  list_store
 ###########
-
 sub gen_list_store {
-	my ($dref,$clmn_type_ref, $clmn_lables_ref)=@_;
-	
-	
-#		my @data = (
-#  {0 => "Average distance",  1 =>"$avg"}, 
-#  {0 => "Max distance",  1 =>"$max" },  
-#  {0 => "Min distance",1 => "$min"},    
-#  {0 => "Normlized data per hop", 1 =>"$norm" }
-#  );
-
-# my @clmn_type = (#'Glib::Boolean', # => G_TYPE_BOOLEAN
-#                                    #'Glib::Uint',    # => G_TYPE_UINT
-#                                    'Glib::String',  # => G_TYPE_STRING
-#                                  'Glib::String'); # you get the idea
-
-	
-	my @data = @{$dref};	
-	my @clmn_type = @{$clmn_type_ref}; 	
-	my @clmn_lables= @{$clmn_lables_ref};
-	
-   
+    my ($dref,$clmn_type_ref, $clmn_lables_ref)=@_;
+    #        my @data = (
+    #  {0 => "Average distance",  1 =>"$avg"},
+    #  {0 => "Max distance",  1 =>"$max" },
+    #  {0 => "Min distance",1 => "$min"},
+    #  {0 => "Normlized data per hop", 1 =>"$norm" }
+    #  );
+    # my @clmn_type = (#'Glib::Boolean', # => G_TYPE_BOOLEAN
+    #                                    #'Glib::Uint',    # => G_TYPE_UINT
+    #                                    'Glib::String',  # => G_TYPE_STRING
+    #                                  'Glib::String'); # you get the idea
+    my @data = @{$dref};
+    my @clmn_type = @{$clmn_type_ref};
+    my @clmn_lables= @{$clmn_lables_ref};
     # create list store
     my $store = Gtk3::ListStore->new ( @clmn_type);
-   
-
-	# add data to the list store
-	foreach my $d (@data) {
-		my $iter = $store->append;
-		my @clmns = sort keys %{$d};
-		my @a=($iter);
-	  	foreach my $c (@clmns){
-	  		push (@a,($c,$d->{$c}));
-				
-	  	}
-     	$store->set (@a);   
-     	
- 	}
-  
-
+    # add data to the list store
+    foreach my $d (@data) {
+        my $iter = $store->append;
+        my @clmns = sort keys %{$d};
+        my @a=($iter);
+        foreach my $c (@clmns){
+            push (@a,($c,$d->{$c}));
+        }
+        $store->set (@a);
+    }
     my $treeview = Gtk3::TreeView->new ($store);
     $treeview->set_rules_hint (TRUE);
-	$treeview->set_search_column (1);
+    $treeview->set_search_column (1);
     #my $renderer = Gtk3::CellRendererToggle->new;
     #$renderer->signal_connect (toggled => \&fixed_toggled, $store);
-
-
-	# column for severities
-	my $c=0;
-	foreach my $l (@clmn_lables){
-		my $renderer = Gtk3::CellRendererText->new;
-		my $column = Gtk3::TreeViewColumn->new_with_attributes ("$l",
-							       $renderer,
-							       text => $c
-							       );
-		$column->set_sort_column_id ($c );
-		$treeview->append_column ($column);
-		$c++;
-	}
- 
-	
-	return $treeview;
+    # column for severities
+    my $c=0;
+    foreach my $l (@clmn_lables){
+        my $renderer = Gtk3::CellRendererText->new;
+        my $column = Gtk3::TreeViewColumn->new_with_attributes (
+            "$l",
+            $renderer,
+            text => $c
+        );
+        $column->set_sort_column_id ($c );
+        $treeview->append_column ($column);
+        $c++;
+    }
+    return $treeview;
 }
 
-
-
-
-
 ##############
-#	create tree
+#    create tree
 ##############
-
-
 sub create_tree_model_network_maker{
-	my $model = Gtk3::TreeStore->new ('Glib::String', 'Glib::String', 'Glib::Scalar', 'Glib::Boolean');
-	my $tree_view = Gtk3::TreeView->new;
-	$tree_view->set_model ($model);
-	my $selection = $tree_view->get_selection;
-	$selection->set_mode ("single");
-	my $cell = Gtk3::CellRendererText->new;
-	$cell->set ('style' => 'italic');
-	my $column = Gtk3::TreeViewColumn->new_with_attributes ("select", $cell, 'text' => 0, 'style_set' => 3);
-	return ($model,$tree_view,$column);
+    my $model = Gtk3::TreeStore->new ('Glib::String', 'Glib::String', 'Glib::Scalar', 'Glib::Boolean');
+    my $tree_view = Gtk3::TreeView->new;
+    $tree_view->set_model ($model);
+    my $selection = $tree_view->get_selection;
+    $selection->set_mode ("single");
+    my $cell = Gtk3::CellRendererText->new;
+    $cell->set ('style' => 'italic');
+    my $column = Gtk3::TreeViewColumn->new_with_attributes ("select", $cell, 'text' => 0, 'style_set' => 3);
+    return ($model,$tree_view,$column);
 }
 
-
 sub treemodel_next_iter{
-	my 	($child , $tree_model)=@_;
-	$tree_model->iter_next ($child);
-	return $child;
+    my     ($child , $tree_model)=@_;
+    $tree_model->iter_next ($child);
+    return $child;
 }
 
-
-
-
-
-
-
-
-
-
-
-
-
 # clean names for column numbers.
 use constant DISPLAY_COLUMN    => 0;
 use constant CATRGORY_COLUMN    => 1;
@@ -2012,239 +1649,167 @@ sub treemodel_next_iter{
 use constant NUM_COLUMNS     => 4;
 
 sub create_tree {
-   my ($self,$label,$info,$tree_ref,$row_selected_func,$row_activated_func)=@_;
-   my %tree_in = %{$tree_ref};
-   my $model = Gtk3::TreeStore->new ('Glib::String', 'Glib::String', 'Glib::Scalar', 'Glib::Boolean');
-   my $tree_view = Gtk3::TreeView->new;
-   $tree_view->set_model ($model);
-   my $selection = $tree_view->get_selection;
-   $selection->set_mode ('browse');   
- 
-   
-
-   foreach my $p (sort keys %tree_in)
-   {
-  
-	my @modules= @{$tree_in{$p}};
-	#my @dev_entry=  @{$tree_entry{$p}}; 	
-	my $iter = $model->append (undef);
-	$model->set ($iter,
-                   DISPLAY_COLUMN,    $p,
-                   CATRGORY_COLUMN, $p || '',
-                   MODULE_COLUMN,     0     || '',
-                   ITALIC_COLUMN,   FALSE);
-
-	next unless  @modules;
-	
-	foreach my $v ( @modules){
-		 my $child_iter = $model->append ($iter);
-		 my $entry= '';
-		
-         	$model->set ($child_iter,
-			DISPLAY_COLUMN,    $v,
-                   	CATRGORY_COLUMN, $p|| '',
-                   	MODULE_COLUMN,     $v     || '',
-                   	ITALIC_COLUMN,   FALSE);
-      	}	
-	
-
-
-   }
-	
-   my $cell = Gtk3::CellRendererText->new;
-   $cell->set ('style' => 'italic');
-   my $column = Gtk3::TreeViewColumn->new_with_attributes
- 					("$label",
-                                        $cell,
-                                        'text' => DISPLAY_COLUMN,
-                                        'style_set' => ITALIC_COLUMN);
-
-	$tree_view->append_column ($column);
-	my @ll=($model,$info);
-   #row selected
-	$selection->signal_connect (changed =>sub {
-	my ($selection, $ref) = @_;
-	my ($model,$info)=@{$ref};
-	my $iter = $selection->get_selected;
-  	return unless defined $iter;
-
-  	my ($category) = $model->get ($iter, CATRGORY_COLUMN);
-  	my ($module) = $model->get ($iter,MODULE_COLUMN );
-  	$row_selected_func->($self,$category,$module,$info) if(defined $row_selected_func);
-  
-
-
+    my ($self,$label,$info,$tree_ref,$row_selected_func,$row_activated_func)=@_;
+    my %tree_in = %{$tree_ref};
+    my $model = Gtk3::TreeStore->new ('Glib::String', 'Glib::String', 'Glib::Scalar', 'Glib::Boolean');
+    my $tree_view = Gtk3::TreeView->new;
+    $tree_view->set_model ($model);
+    my $selection = $tree_view->get_selection;
+    $selection->set_mode ('browse');
+    foreach my $p (sort keys %tree_in)
+    {
+    my @modules= @{$tree_in{$p}};
+    #my @dev_entry=  @{$tree_entry{$p}};
+    my $iter = $model->append (undef);
+    $model->set (
+        $iter,
+        DISPLAY_COLUMN,    $p,
+        CATRGORY_COLUMN, $p || '',
+        MODULE_COLUMN,     0     || '',
+        ITALIC_COLUMN,   FALSE);
+    next unless  @modules;
+    foreach my $v ( @modules){
+        my $child_iter = $model->append ($iter);
+        my $entry= '';
+            $model->set ($child_iter,
+            DISPLAY_COLUMN,    $v,
+            CATRGORY_COLUMN, $p|| '',
+            MODULE_COLUMN,     $v     || '',
+            ITALIC_COLUMN,   FALSE);
+        }
+    }
+    my $cell = Gtk3::CellRendererText->new;
+    $cell->set ('style' => 'italic');
+    my $column = Gtk3::TreeViewColumn->new_with_attributes  (
+        "$label",
+        $cell,
+        'text' => DISPLAY_COLUMN,
+        'style_set' => ITALIC_COLUMN);
+    $tree_view->append_column ($column);
+    my @ll=($model,$info);
+    #row selected
+    $selection->signal_connect (changed =>sub {
+    my ($selection, $ref) = @_;
+    my ($model,$info)=@{$ref};
+    my $iter = $selection->get_selected;
+    return unless defined $iter;
+    my ($category) = $model->get ($iter, CATRGORY_COLUMN);
+    my ($module) = $model->get ($iter,MODULE_COLUMN );
+    $row_selected_func->($self,$category,$module,$info) if(defined $row_selected_func);
 }, \@ll);
-
-#  row_activated 
-  $tree_view->signal_connect (row_activated => sub{
-
-	my ($tree_view, $path, $column) = @_;
-	my $model = $tree_view->get_model;
-	my $iter = $model->get_iter ($path);
-	my ($category) = $model->get ($iter, CATRGORY_COLUMN);
-  	my ($module) = $model->get ($iter,MODULE_COLUMN );
-	
-
-	if($module){ 
-		#print "$module  is selected via row activaton!\n";
-		$row_activated_func->($self,$category,$module,$info) if(defined $row_activated_func);
-		#add_module_to_soc($soc,$ip,$category,$module,$info);
-			
-	}
-
+#  row_activated
+    $tree_view->signal_connect (row_activated => sub{
+    my ($tree_view, $path, $column) = @_;
+    my $model = $tree_view->get_model;
+    my $iter = $model->get_iter ($path);
+    my ($category) = $model->get ($iter, CATRGORY_COLUMN);
+    my ($module) = $model->get ($iter,MODULE_COLUMN );
+    if($module){
+        #print "$module  is selected via row activaton!\n";
+        $row_activated_func->($self,$category,$module,$info) if(defined $row_activated_func);
+        #add_module_to_soc($soc,$ip,$category,$module,$info);
+    }
 }, \@ll);
-
-  #$tree_view->expand_all;
-
-  my $scrolled_window = Gtk3::ScrolledWindow->new;
-  $scrolled_window->set_policy ('automatic', 'automatic');
-  $scrolled_window->set_shadow_type ('in');
-  $scrolled_window->add($tree_view);
-
-  my $hbox = Gtk3::HBox->new (FALSE, 0);
-  $hbox->pack_start ( $scrolled_window, TRUE, TRUE, 0); 
-
-  return $hbox;
+    #$tree_view->expand_all;
+    my $scrolled_window = Gtk3::ScrolledWindow->new;
+    $scrolled_window->set_policy ('automatic', 'automatic');
+    $scrolled_window->set_shadow_type ('in');
+    $scrolled_window->add($tree_view);
+    my $hbox = Gtk3::HBox->new (FALSE, 0);
+    $hbox->pack_start ( $scrolled_window, TRUE, TRUE, 0);
+    return $hbox;
 }
 
-
 sub row_activated_cb{
-	 my ($tree_view, $path, $column) = @_;
-	 my $model = $tree_view->get_model;
-	 my $iter = $model->get_iter ($path);
-	 my ($category) = $model->get ($iter, DISPLAY_COLUMN);
-  	 my ($module) = $model->get ($iter, CATRGORY_COLUMN);
-
+    my ($tree_view, $path, $column) = @_;
+    my $model = $tree_view->get_model;
+    my $iter = $model->get_iter ($path);
+    my ($category) = $model->get ($iter, DISPLAY_COLUMN);
+    my ($module) = $model->get ($iter, CATRGORY_COLUMN);
 }
 
-
-
 sub file_edit_tree {
-	my $model = Gtk3::TreeStore->new('Glib::String', 'Glib::String');
-	my $tree_view = Gtk3::TreeView->new;
-	$tree_view->set_model ($model);
-	my $selection = $tree_view->get_selection;
-	$selection->set_mode ("single");	
-	my $cell = Gtk3::CellRendererText->new;
-	$cell->set ('style' => 'italic');
-	my $column = Gtk3::TreeViewColumn->new_with_attributes('Double-click to open',$cell, text => "0");
-	$tree_view->append_column($column);
-	$tree_view->set_headers_visible(TRUE);
-	return ($model,$tree_view);
-}
-
-
-#	my $column = Gtk3::TreeViewColumn->new_with_attributes ("select", $cell, 'text' => 0, 'style_set' => 3);
-
-
-
-
-
+    my $model = Gtk3::TreeStore->new('Glib::String', 'Glib::String');
+    my $tree_view = Gtk3::TreeView->new;
+    $tree_view->set_model ($model);
+    my $selection = $tree_view->get_selection;
+    $selection->set_mode ("single");
+    my $cell = Gtk3::CellRendererText->new;
+    $cell->set ('style' => 'italic');
+    my $column = Gtk3::TreeViewColumn->new_with_attributes('Double-click to open',$cell, text => "0");
+    $tree_view->append_column($column);
+    $tree_view->set_headers_visible(TRUE);
+    return ($model,$tree_view);
+}
+#    my $column = Gtk3::TreeViewColumn->new_with_attributes ("select", $cell, 'text' => 0, 'style_set' => 3);
 ##########
 #  run external commands
 ##########
+sub run_cmd_in_back_ground {
+    my ($command, $stdout_file, $stderr_file) = @_;
+    chomp $command; #remove newline 
+    
+    my $proc = (defined $stdout_file)? 
+    Proc::Background->new({
+        stdout => $stdout_file,  
+        stderr => $stderr_file,  
+    },$command) : Proc::Background->new($command);
 
-
-
-sub run_cmd_in_back_ground
-{
-  my $command = shift;
-  #print "\t$command\n";
- 
-  ### Start running the Background Job:
-    my $proc = Proc::Background->new($command);
-    my $PID = $proc->pid;
-    my $start_time = $proc->start_time;
-    my $alive = $proc->alive;
-
-  ### While $alive is NOT '0', then keep checking till it is...
-  #  *When $alive is '0', it has finished executing.
-  while($alive ne 0)
-  {
-    $alive = $proc->alive;
-
-    # This while loop will cause Gtk3 to continue processing events, if
-    # there are events pending... *which there are...
+    while ($proc->alive) {
     while (Gtk3::events_pending) {
-     
-      Gtk3::main_iteration;
+        Gtk3::main_iteration;
     }
     Gtk3::Gdk::flush;
-
     usleep(1000);
-  }
-  
-  my $end_time = $proc->end_time;
- # print "*Command Completed at $end_time, with PID = $PID\n\n";
-
-  # Since the while loop has exited, the BG job has finished running:
-  # so close the pop-up window...
- # $popup_window->hide;
-
-  # Get the RETCODE from the Background Job using the 'wait' method
-  my $retcode = $proc->wait;
-  $retcode /= 256;
-
-  #print "\t*RETCODE == $retcode\n\n";
-  Gtk3::Gdk::flush;
-  ### Check if the RETCODE returned with an Error:
-  if ($retcode ne 0) {
-    print "Error: The Background Job ($command) returned with an Error...!\n";
-    return 1;
-  } else {
-    #print "Success: The Background Job Completed Successfully...!\n";
-    return 0;
-  }
-	
+    }
+    my $ret = $proc->wait / 256;
+    return $ret;
 }
 
 sub run_cmd_in_back_ground_get_stdout
 {
-	my $cmd=shift;
-	my $exit;
-	my ($stdout, $stderr);	
-	STDOUT->flush();
-	STDERR->flush();
-	
-	capture { $exit=run_cmd_in_back_ground($cmd) } \$stdout, \$stderr;
-	
-	return ($stdout,$exit,$stderr);
-	
-}		
-	
-sub run_cmd_message_dialog_errors{
-	my ($cmd)=@_;
-	my ($stdout,$exit,$stderr)=run_cmd_in_back_ground_get_stdout($cmd);
-	if(length $stderr>1){			
-		message_dialog("$stderr\n",'error');
-		return 1;
-	}if($exit){
-		message_dialog("Error $cmd failed: $stdout\n",'error');
-		return 1;		
-	}
-	return 0;
-	
+    my $cmd=shift;
+    my $exit;
+    # Create temp files in /dev/shm (RAM)
+    my ($stderr_fh, $stderr_file) = tempfile(DIR => "/dev/shm", UNLINK => 1);
+    my ($stdout_fh, $stdout_file) = tempfile(DIR => "/dev/shm", UNLINK => 1);
+    close $stderr_fh;
+    close $stdout_fh;
+    $exit=run_cmd_in_back_ground($cmd, $stdout_file, $stderr_file) ;
+    my $stderr = do { local (@ARGV, $/) = ($stderr_file); <> };
+    my $stdout = do { local (@ARGV, $/) = ($stdout_file); <> };
+    return ($stdout,$exit,$stderr);
 }
 
+sub run_cmd_message_dialog_errors{
+    my ($cmd)=@_;
+    my ($stdout,$exit,$stderr)=run_cmd_in_back_ground_get_stdout($cmd);
+    if(length $stderr>1){
+        message_dialog("$stderr\n",'error');
+        return 1;
+    }if($exit){
+        message_dialog("Error $cmd failed: $stdout\n",'error');
+        return 1;
+    }
+    return 0;
+}
 
 sub run_cmd_textview_errors{
-	my ($cmd,$tview)=@_;
-	my ($stdout,$exit,$stderr)=run_cmd_in_back_ground_get_stdout($cmd);
-	if(length $stderr>1){			
-		add_colored_info($tview,"Error: $stderr\n",'red');
-		add_colored_info($tview,"$cmd did not run successfully!\n",'red');
-		return undef;
-	}
-	if($exit){
-		add_colored_info($tview,"Error:$stdout\n",'red');
-		add_colored_info($tview,"$cmd did not run successfully!\n",'red');
-		return undef;
-	}
-	$stdout = "" if (!defined $stdout);
-	return 	$stdout
-}	
-
+    my ($cmd,$tview)=@_;
+    my ($stdout,$exit,$stderr)=run_cmd_in_back_ground_get_stdout($cmd);
+    if(length $stderr>1){
+        add_colored_info($tview,"Error: $stderr\n",'red');
+        add_colored_info($tview,"$cmd did not run successfully!\n",'red');
+        return undef;
+    }
+    if($exit){
+        add_colored_info($tview,"Error:$stdout\n",'red');
+        add_colored_info($tview,"$cmd did not run successfully!\n",'red');
+        return undef;
+    }
+    $stdout = "" if (!defined $stdout);
+    return     $stdout
+}
 
 sub create_iconview_model {
 #----------------------------------------------------
@@ -2254,90 +1819,63 @@ sub create_iconview_model {
 #text of the icon, and the last for the icon self----
 #Gtk3::ListStore is ideal for this ------------------
 #----------------------------------------------------
-	my ($self,$name,$ref)=@_;
-	my @sources= (defined $ref)? @{$ref}:(); 
+    my ($self,$name,$ref)=@_;
+    my @sources= (defined $ref)? @{$ref}:();
     my $list_store = Gtk3::ListStore->new(qw/Glib::String Gtk3::Gdk::Pixbuf Glib::String/);
-
     #******************************************************
     #we populate the Gtk3::ListStore with Gtk3::Stock icons
     #******************************************************
-
- 
-
     foreach my $val(@sources){
         #get the iconset from the icon_factory
         #my $iconset = $icon_factory->lookup_default($val);
         #try and extract the icon from it
         add_icon_to_tree($self,$name,$list_store,$val);
     }
-
     return $list_store;
 }
 
 ####################
-#	SourceView
+#    SourceView
 ####################
-
-sub	gen_SourceView_with_buffer{
-	return Gtk3::SourceView::View->new_with_buffer(@_);
+sub    gen_SourceView_with_buffer{
+    return Gtk3::SourceView::View->new_with_buffer(@_);
 }
 
-
-
-
-
 sub create_SourceView_buffer {
-	my $self = shift;
-	my $tags = Gtk3::TextTagTable->new();
-
-	add_tag_to_SourceView($tags, search => {
-			background => 'yellow',
-	});
-	add_tag_to_SourceView($tags, goto_line => {
-			'paragraph-background' => 'orange',
-	});
-
-	my $buffer = Gtk3::SourceView::Buffer->new($tags);
-	$buffer->signal_connect('notify::cursor-position' => sub {
-		$self->clear_highlighted();
-	});
-
-	return $buffer;
+    my $self = shift;
+    my $tags = Gtk3::TextTagTable->new();
+    add_tag_to_SourceView($tags, search => {
+            background => 'yellow',
+    });
+    add_tag_to_SourceView($tags, goto_line => {
+            'paragraph-background' => 'orange',
+    });
+    my $buffer = Gtk3::SourceView::Buffer->new($tags);
+    $buffer->signal_connect('notify::cursor-position' => sub {
+        $self->clear_highlighted();
+    });
+    return $buffer;
 }
 
-
 sub add_tag_to_SourceView {
-	my ($tags, $name, $properties) = @_;
-
-	my $tag = Gtk3::TextTag->new($name);
-	$tag->set(%{ $properties });
-	$tags->add($tag);
+    my ($tags, $name, $properties) = @_;
+    my $tag = Gtk3::TextTag->new($name);
+    $tag->set(%{ $properties });
+    $tags->add($tag);
 }
 
-
 sub detect_language {
-	my $self = shift;
-	my ($filename) = @_;
-
-	# Guess the programming language of the file
-	my $manager = Gtk3::SourceView::LanguageManager->get_default;
-	my $language = $manager->guess_language($filename);
-	$self->buffer->set_language($language);
+    my $self = shift;
+    my ($filename) = @_;
+    # Guess the programming language of the file
+    my $manager = Gtk3::SourceView::LanguageManager->get_default;
+    my $language = $manager->guess_language($filename);
+    $self->buffer->set_language($language);
 }
 
-
-sub get_pressed_key{ 
-	my $event=shift;
-	my $key = Gtk3::Gdk::keyval_name( $event->keyval );
-	return $key;
+sub get_pressed_key{
+    my $event=shift;
+    my $key = Gtk3::Gdk::keyval_name( $event->keyval );
+    return $key;
 }
-
-
-
-
-
-
-
-
-
-1
+1;
diff --git a/mpsoc/perl_gui/lib/soc/mor1k_tile.SOC b/mpsoc/perl_gui/lib/soc/mor1k_tile.SOC
index d2cc171..d758604 100644
--- a/mpsoc/perl_gui/lib/soc/mor1k_tile.SOC
+++ b/mpsoc/perl_gui/lib/soc/mor1k_tile.SOC
@@ -1517,10 +1517,10 @@ For XILINX FPGAs define it as "XILINX_JTAG_WB". In this case, the UART uses BSCA
                                                                                'value' => '4'
                                                                              },
                                                                      'ROUTE_NAME' => {
-                                                                                       'value' => '"XY"'
+                                                                                       'value' => '"DOR"'
                                                                                      },
                                                                      'SELF_LOOP_EN' => {
-                                                                                         'value' => '"NO"'
+                                                                                         'value' => '0'
                                                                                        },
                                                                      'RAw' => {
                                                                                 'value' => '16'
@@ -1574,7 +1574,7 @@ For XILINX FPGAs define it as "XILINX_JTAG_WB". In this case, the UART uses BSCA
                                                                                  'value' => '32'
                                                                                },
                                                                      'SSA_EN' => {
-                                                                                   'value' => '"NO"'
+                                                                                   'value' => '0'
                                                                                  },
                                                                      'WEIGHTw' => {
                                                                                     'value' => '4'
diff --git a/mpsoc/perl_gui/test.conf b/mpsoc/perl_gui/test.conf
deleted file mode 100644
index d1c6189..0000000
--- a/mpsoc/perl_gui/test.conf
+++ /dev/null
@@ -1,107 +0,0 @@
-$config = \{
-              'CLASS_6' => '1.81818181818182',
-              'CLASS_0' => '1.81818181818182',
-              'CLASS_17' => '1.81818181818182',
-              'CLASS_7' => '1.81818181818182',
-              'ratios' => '55',
-              'CLASS_46' => '1.81818181818182',
-              'CLASS_41' => '1.81818181818182',
-              'CLASS_4' => '1.81818181818182',
-              'CLASS_5' => '1.81818181818182',
-              'CLASS_51' => '1.81818181818182',
-              'CLASS_22' => '1.81818181818182',
-              'sof_path' => '/home/alireza/work/git/hca_git/git-hub/ProNoC/mpsoc_work/simulate',
-              'CLASS_19' => '1.81818181818182',
-              'CLASS_3' => '1.81818181818182',
-              'CLASS_36' => '1.81818181818182',
-              'CLASS_31' => '1.81818181818182',
-              'CLASS_24' => '1.81818181818182',
-              'MCAST_PCK_SIZ_MIN' => '2',
-              'PCK_NUM_LIMIT' => '20000',
-              'color' => 2,
-              'CLASS_18' => '1.81818181818182',
-              'CLASS_34' => '1.81818181818182',
-              'TRAFFIC_TYPE' => 'Synthetic',
-              'CLASS_26' => '1.81818181818182',
-              'CLASS_21' => '1.81818181818182',
-              'CLASS_2' => '1.81818181818182',
-              'CLASS_10' => '1.81818181818182',
-              'CLASS_32' => '1.81818181818182',
-              'CLASS_13' => '1.81818181818182',
-              'CLASS_54' => '1.81818181818182',
-              'sof_file' => 'simulate1',
-              'SIM_CLOCK_LIMIT' => '10000',
-              'CLASS_52' => '1.81818181818182',
-              'CLASS_44' => '1.81818181818182',
-              'CLASS_15' => '1.81818181818182',
-              'PCK_SIZ_SEL' => 'random-range',
-              'CLASS_42' => '1.81818181818182',
-              'CLASS_25' => '1.81818181818182',
-              'CLASS_49' => '1.81818181818182',
-              'CLASS_37' => '1.81818181818182',
-              'CLASS_23' => '1.81818181818182',
-              'line_name' => 'sample0',
-              'CLASS_11' => '1.81818181818182',
-              'CLASS_16' => '1.81818181818182',
-              'MCAST_TRAFFIC_TYPE' => 'Uniform-Random',
-              'CLASS_1' => '1.81818181818182',
-              'MCAST_TRAFFIC_RATIO' => '50',
-              'CLASS_8' => '1.81818181818182',
-              'CLASS_47' => '1.81818181818182',
-              'MCAST_PCK_SIZ_MAX' => '4',
-              'CLASS_39' => '1.81818181818182',
-              'CLASS_20' => '1.81818181818182',
-              'MIN_PCK_SIZE' => '2',
-              'noc_info' => {
-                              'MIN_PCK_SIZE' => '2',
-                              'CAST_TYPE' => '"MULTICAST_PARTIAL"',
-                              'BYTE_EN' => 0,
-                              'PCK_TYPE' => '"MULTI_FLIT"',
-                              'B' => '4',
-                              'Fpay' => '32',
-                              'TOPOLOGY' => '"STAR"',
-                              'MUX_TYPE' => '"BINARY"',
-                              'LB' => 'B',
-                              'SWA_ARBITER_TYPE' => '"RRA"',
-                              'T1' => '6',
-                              'T3' => '1',
-                              'AVC_ATOMIC_EN' => 0,
-                              'WEIGHTw' => '4',
-                              'SSA_EN' => '"NO"',
-                              'SELF_LOOP_EN' => '"YES"',
-                              'ADD_PIPREG_AFTER_CROSSBAR' => '1\'b0',
-                              'ESCAP_VC_MASK' => '2\'b01',
-                              'VC_REALLOCATION_TYPE' => '"NONATOMIC"',
-                              'CONGESTION_INDEX' => 3,
-                              'ROUTE_NAME' => '"UNKNOWN"',
-                              'FIRST_ARBITER_EXT_P_EN' => 1,
-                              'DEBUG_EN' => '1',
-                              'V' => '2',
-                              'SMART_MAX' => '0',
-                              'C' => 0,
-                              'MCAST_ENDP_LIST' => '\'h0b',
-                              'T2' => 1,
-                              'COMBINATION_TYPE' => '"COMB_NONSPEC"'
-                            },
-              'PCK_SIZE' => '6',
-              'status' => 'failed',
-              'CLASS_28' => '1.81818181818182',
-              'CLASS_9' => '1.81818181818182',
-              'CLASS_38' => '1.81818181818182',
-              'CLASS_43' => '1.81818181818182',
-              'CLASS_12' => '1.81818181818182',
-              'CLASS_30' => '1.81818181818182',
-              'CLASS_29' => '1.81818181818182',
-              'CLASS_14' => '1.81818181818182',
-              'CLASS_45' => '1.81818181818182',
-              'CLASS_53' => '1.81818181818182',
-              'CLASS_50' => '1.81818181818182',
-              'CLASS_48' => '1.81818181818182',
-              'MAX_PCK_SIZE' => '10',
-              'CLASS_33' => '1.81818181818182',
-              'MESSAGE_CLASS' => '0',
-              'CLASS_27' => '1.81818181818182',
-              'traffic' => 'random',
-              'CLASS_40' => '1.81818181818182',
-              'CLASS_35' => '1.81818181818182'
-            };
diff --git a/mpsoc/rtl/arbiter.v b/mpsoc/rtl/arbiter.v
index c2caeb2..40cf26a 100755
--- a/mpsoc/rtl/arbiter.v
+++ b/mpsoc/rtl/arbiter.v
@@ -1,68 +1,54 @@
- `timescale     1ns/1ps
+`include "pronoc_def.v"
 /**********************************************************************
-**	File: arbiter.v
+**    File: arbiter.v
 **    
-**	Copyright (C) 2014-2017  Alireza Monemi
+**    Copyright (C) 2014-2017  Alireza Monemi
 **    
-**	This file is part of ProNoC 
+**    This file is part of ProNoC 
 **
-**	ProNoC ( stands for Prototype Network-on-chip)  is free software: 
-**	you can redistribute it and/or modify it under the terms of the GNU
-**	Lesser General Public License as published by the Free Software Foundation,
-**	either version 2 of the License, or (at your option) any later version.
+**    ProNoC ( stands for Prototype Network-on-chip)  is free software: 
+**    you can redistribute it and/or modify it under the terms of the GNU
+**    Lesser General Public License as published by the Free Software Foundation,
+**    either version 2 of the License, or (at your option) any later version.
 **
-** 	ProNoC is distributed in the hope that it will be useful, but WITHOUT
-** 	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
-** 	or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
-** 	Public License for more details.
+**     ProNoC is distributed in the hope that it will be useful, but WITHOUT
+**     ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+**     or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
+**     Public License for more details.
 **
-** 	You should have received a copy of the GNU Lesser General Public
-** 	License along with ProNoC. If not, see <http:**www.gnu.org/licenses/>.
+**     You should have received a copy of the GNU Lesser General Public
+**     License along with ProNoC. If not, see <http:**www.gnu.org/licenses/>.
 **
 **
 **
-**	Description: 
-**	This file contains several Fixed prority and round robin 
-**	arbiters 
+**    Description: 
+**    This file contains several Fixed prority and round robin 
+**    arbiters 
 **
 ******************************************************************************/ 
 
 
 /*****************************************
-*        
 * general round robin arbiter
-* 
-*
 ******************************************/
-
 `ifndef PRONOC_ARBITER
 `define PRONOC_ARBITER
 
-`include "pronoc_def.v"
-
-
-
 module arbiter #(
     parameter    ARBITER_WIDTH    =8
-        
-)
-(    
-   clk, 
-   reset, 
-   request, 
-   grant,
-   any_grant
+)(    
+    clk, 
+    reset, 
+    request, 
+    grant,
+    any_grant
 );
-
+    input [ARBITER_WIDTH-1 : 0] request;
+    output [ARBITER_WIDTH-1 : 0] grant;
+    output any_grant;
+    input clk;
+    input reset;
     
-    input    [ARBITER_WIDTH-1             :    0]    request;
-    output    [ARBITER_WIDTH-1            :    0]    grant;
-    output                                        any_grant;
-    input                                        clk;
-    input                                        reset;
-
-
-
     generate 
     if(ARBITER_WIDTH==1)  begin: w1
         assign grant= request;
@@ -71,23 +57,18 @@ module arbiter #(
         //my own arbiter 
         my_one_hot_arbiter #(
             .ARBITER_WIDTH    (ARBITER_WIDTH)
-        )
-        one_hot_arb
-        (    
+        ) one_hot_arb (    
             .clk            (clk), 
             .reset         (reset), 
             .request        (request), 
             .grant        (grant),
             .any_grant    (any_grant)
         );
-    
     end else begin : wb4
         
         thermo_arbiter #(
             .ARBITER_WIDTH    (ARBITER_WIDTH)
-        )
-        one_hot_arb
-        (    
+        )  one_hot_arb   (    
             .clk            (clk), 
             .reset         (reset), 
             .request        (request), 
@@ -104,30 +85,22 @@ endmodule
 * RRA with external priority enable signal
 *
 ******************************************/
-
 module arbiter_priority_en #(
-        parameter    ARBITER_WIDTH    =8
-        
-)
-(    
-   clk, 
-   reset, 
-   request, 
-   grant,
-   any_grant,
-   priority_en
+    parameter    ARBITER_WIDTH    =8
+)(    
+    clk, 
+    reset, 
+    request, 
+    grant,
+    any_grant,
+    priority_en
 );
-
-  
-
-
-    input        [ARBITER_WIDTH-1             :    0]    request;
-    output    [ARBITER_WIDTH-1            :    0]    grant;
-    output                                            any_grant;
-    input                                                clk;
-    input                                                reset;
-    input                                              priority_en;
-    
+    input [ARBITER_WIDTH-1 : 0] request;
+    output [ARBITER_WIDTH-1 : 0] grant;
+    output any_grant;
+    input clk;
+    input reset;
+    input priority_en;
     
     generate 
     if(ARBITER_WIDTH==1)  begin: w1
@@ -137,25 +110,19 @@ module arbiter_priority_en #(
         //my own arbiter 
         my_one_hot_arbiter_priority_en #(
             .ARBITER_WIDTH    (ARBITER_WIDTH)
-        )
-        one_hot_arb
-        (    
+        )  one_hot_arb  (    
             .clk            (clk), 
             .reset         (reset), 
             .request        (request), 
             .grant        (grant),
             .any_grant    (any_grant),
             .priority_en (priority_en)
-            
         );
-    
     end else begin :wb4
         
         thermo_arbiter_priority_en #(
             .ARBITER_WIDTH    (ARBITER_WIDTH)
-        )
-        one_hot_arb
-        (    
+        )  one_hot_arb  (    
             .clk            (clk), 
             .reset         (reset), 
             .request        (request), 
@@ -168,287 +135,238 @@ endgenerate
 endmodule
 
 
-
 /******************************************************
-*	my_one_hot_arbiter
+*    my_one_hot_arbiter
 * RRA with binary-coded priority register. Binary-coded 
 * Priority results in less area cost and CPD for arbire 
 * width of 4 and smaller only. 
 *
 ******************************************************/
-      
-    
-
 module my_one_hot_arbiter #(
     parameter ARBITER_WIDTH    =4
-    
-    
-)
-(
-    input        [ARBITER_WIDTH-1             :    0]    request,
-    output    [ARBITER_WIDTH-1            :    0]    grant,
-    output                                            any_grant,
-    input                                                clk,
-    input                                                reset
+)(
+    input [ARBITER_WIDTH-1 : 0] request,
+    output [ARBITER_WIDTH-1 : 0] grant,
+    output any_grant,
+    input clk,
+    input reset
 );
-   
+
     function integer log2;
-      input integer number; begin   
-         log2=(number <=1) ? 1: 0;    
-         while(2**log2<number) begin    
-            log2=log2+1;    
-         end 	   
-      end   
+    input integer number; begin
+        log2=(number <=1) ? 1: 0;
+        while(2**log2<number) begin
+            log2=log2+1;
+        end 
+    end   
     endfunction // log2 
     
     localparam ARBITER_BIN_WIDTH= log2(ARBITER_WIDTH);
-    reg     [ARBITER_BIN_WIDTH-1        :    0]     low_pr;
-    wire     [ARBITER_BIN_WIDTH-1        :    0]     grant_bcd;
-    
-    one_hot_to_bin #(
-        .ONE_HOT_WIDTH    (ARBITER_WIDTH)
-    )conv
-    (
-    .one_hot_code(grant),
-    .bin_code(grant_bcd)
-
-    );
+    reg [ARBITER_BIN_WIDTH-1 : 0] low_pr;
+    reg [ARBITER_BIN_WIDTH-1 : 0] grant_bin;
+    
+    integer i;
+    always @(*) begin
+        grant_bin = '0;
+        for (i = 0; i < ARBITER_WIDTH; i=i+1) begin
+            if (grant[i]) begin
+                grant_bin = ARBITER_BIN_WIDTH'(i); // casting i to BIN_WIDTH
+            end
+        end
+    end
     
     always @ (`pronoc_clk_reset_edge )begin 
         if(`pronoc_reset) begin
-            low_pr    <=    {ARBITER_BIN_WIDTH{1'b0}};
+            low_pr <= {ARBITER_BIN_WIDTH{1'b0}};
         end else begin
-            if(any_grant) low_pr <= grant_bcd;
+            if(any_grant) low_pr <= grant_bin;
         end
     end
-    
-
     assign any_grant = | request;
-
     generate 
-        if(ARBITER_WIDTH    ==2) begin: w2        arbiter_2_one_hot arb( .in(request) , .out(grant), .low_pr(low_pr)); end
-        if(ARBITER_WIDTH    ==3) begin: w3        arbiter_3_one_hot arb( .in(request) , .out(grant), .low_pr(low_pr)); end
-        if(ARBITER_WIDTH    ==4) begin: w4        arbiter_4_one_hot arb( .in(request) , .out(grant), .low_pr(low_pr)); end
+        if(ARBITER_WIDTH    ==2) begin: w2  arbiter_2_one_hot arb( .D_in(request) , .Q_out(grant), .low_pr(low_pr)); end
+        if(ARBITER_WIDTH    ==3) begin: w3  arbiter_3_one_hot arb( .D_in(request) , .Q_out(grant), .low_pr(low_pr)); end
+        if(ARBITER_WIDTH    ==4) begin: w4  arbiter_4_one_hot arb( .D_in(request) , .Q_out(grant), .low_pr(low_pr)); end
     endgenerate
-
 endmodule
 
 
 module arbiter_2_one_hot(
-     input      [1             :    0]    in,
-     output    reg[1                :    0]    out,
-     input                                low_pr
+    input [1 : 0] D_in,
+    output reg[1 : 0] Q_out,
+    input low_pr
 );
-always @(*) begin
-     out=2'b00;
-      case(low_pr)
-         1'd0:
-             if(in[1])                 out=2'b10;
-             else if(in[0])         out=2'b01;
-         1'd1:
-             if(in[0])                 out=2'b01;
-             else if(in[1])         out=2'b10;
-          default: out=2'b00;
-     endcase 
-  end
- endmodule 
-
-
+    always @(*) begin
+        Q_out=2'b00;
+        case(low_pr)
+            1'd0:
+                if(D_in[1])              Q_out=2'b10;
+                else if(D_in[0])         Q_out=2'b01;
+            1'd1:
+                if(D_in[0])              Q_out=2'b01;
+                else if(D_in[1])         Q_out=2'b10;
+            default: Q_out=2'b00;
+        endcase 
+    end
+endmodule 
 
 
 module arbiter_3_one_hot(
-     input      [2             :    0]    in,
-     output    reg[2                :    0]    out,
-     input        [1                :    0]    low_pr
+    input [2 : 0] D_in,
+    output reg[2 : 0] Q_out,
+    input [1 : 0] low_pr
 );
-always @(*) begin
-  out=3'b000;
-      case(low_pr)
-         2'd0:
-             if(in[1])                 out=3'b010;
-             else if(in[2])         out=3'b100;
-             else if(in[0])         out=3'b001;
-         2'd1:
-             if(in[2])                 out=3'b100;
-             else if(in[0])         out=3'b001;
-             else if(in[1])         out=3'b010;
-         2'd2:
-             if(in[0])                 out=3'b001;
-             else if(in[1])         out=3'b010;
-             else if(in[2])         out=3'b100;
-         default: out=3'b000;
-     endcase 
-  end
- endmodule 
-
-
- module arbiter_4_one_hot(
-     input      [3             :    0]    in,
-     output    reg[3                :    0]    out,
-     input        [1                :    0]    low_pr
+    always @(*) begin
+        Q_out=3'b000;
+        case(low_pr)
+            2'd0:
+                if(D_in[1])              Q_out=3'b010;
+                else if(D_in[2])         Q_out=3'b100;
+                else if(D_in[0])         Q_out=3'b001;
+            2'd1:
+                if(D_in[2])              Q_out=3'b100;
+                else if(D_in[0])         Q_out=3'b001;
+                else if(D_in[1])         Q_out=3'b010;
+            2'd2:
+                if(D_in[0])              Q_out=3'b001;
+                else if(D_in[1])         Q_out=3'b010;
+                else if(D_in[2])         Q_out=3'b100;
+            default: Q_out=3'b000;
+        endcase 
+    end
+endmodule 
+
+
+module arbiter_4_one_hot(
+    input [3 : 0] D_in,
+    output reg[3 : 0] Q_out,
+    input [1 : 0] low_pr
 );
-always @(*) begin
-  out=4'b0000;
-      case(low_pr)
-         2'd0:
-             if(in[1])                 out=4'b0010;
-             else if(in[2])         out=4'b0100;
-             else if(in[3])         out=4'b1000;
-             else if(in[0])         out=4'b0001;
-         2'd1:
-             if(in[2])                 out=4'b0100;
-             else if(in[3])         out=4'b1000;
-             else if(in[0])         out=4'b0001;
-             else if(in[1])         out=4'b0010;
-         2'd2:
-             if(in[3])                 out=4'b1000;
-             else if(in[0])         out=4'b0001;
-             else if(in[1])         out=4'b0010;
-             else if(in[2])         out=4'b0100;
-         2'd3:
-             if(in[0])                 out=4'b0001;
-             else if(in[1])         out=4'b0010;
-             else if(in[2])         out=4'b0100;
-             else if(in[3])         out=4'b1000;
-         default: out=4'b0000;
-     endcase 
-  end
- endmodule 
+    always @(*) begin
+        Q_out=4'b0000;
+        case(low_pr)
+            2'd0:
+                if(D_in[1])              Q_out=4'b0010;
+                else if(D_in[2])         Q_out=4'b0100;
+                else if(D_in[3])         Q_out=4'b1000;
+                else if(D_in[0])         Q_out=4'b0001;
+            2'd1:
+                if(D_in[2])              Q_out=4'b0100;
+                else if(D_in[3])         Q_out=4'b1000;
+                else if(D_in[0])         Q_out=4'b0001;
+                else if(D_in[1])         Q_out=4'b0010;
+            2'd2:
+                if(D_in[3])              Q_out=4'b1000;
+                else if(D_in[0])         Q_out=4'b0001;
+                else if(D_in[1])         Q_out=4'b0010;
+                else if(D_in[2])         Q_out=4'b0100;
+            2'd3:
+                if(D_in[0])              Q_out=4'b0001;
+                else if(D_in[1])         Q_out=4'b0010;
+                else if(D_in[2])         Q_out=4'b0100;
+                else if(D_in[3])         Q_out=4'b1000;
+            default: Q_out=4'b0000;
+        endcase 
+    end
+endmodule 
 
 
 /******************************************************
-*	my_one_hot_arbiter_priority_en
+*    my_one_hot_arbiter_priority_en
 * 
 ******************************************************/
-
-
-
 module my_one_hot_arbiter_priority_en #(
     parameter ARBITER_WIDTH    =4
-    
-    
-)
-(
-    input        [ARBITER_WIDTH-1             :    0]    request,
-    output    [ARBITER_WIDTH-1            :    0]    grant,
-    output                                            any_grant,
-    input                                                clk,
-    input                                                reset,
-    input                                                priority_en
+)(
+    input [ARBITER_WIDTH-1 : 0] request,
+    output [ARBITER_WIDTH-1 : 0] grant,
+    output any_grant,
+    input clk,
+    input reset,
+    input priority_en
 );
-   
     function integer log2;
-      input integer number; begin   
-         log2=(number <=1) ? 1: 0;    
-         while(2**log2<number) begin    
-            log2=log2+1;    
-         end 	   
-      end   
+    input integer number; begin
+        log2=(number <=1) ? 1: 0;
+        while(2**log2<number) begin
+            log2=log2+1;
+        end
+    end
     endfunction // log2 
     
-    localparam ARBITER_BIN_WIDTH= log2(ARBITER_WIDTH);
-    reg     [ARBITER_BIN_WIDTH-1        :    0]     low_pr;
-    wire     [ARBITER_BIN_WIDTH-1        :    0]     grant_bcd;
+    localparam ARBITER_BIN_WIDTH = log2(ARBITER_WIDTH);
+    reg [ARBITER_BIN_WIDTH-1 : 0] low_pr;
+    reg [ARBITER_BIN_WIDTH-1 : 0] grant_bin;
+    
+    integer i;
+    always @(*) begin
+        grant_bin = '0;
+        for (i = 0; i < ARBITER_WIDTH; i=i+1) begin
+            if (grant[i]) begin
+                grant_bin = ARBITER_BIN_WIDTH'(i); // casting i to BIN_WIDTH
+            end
+        end
+    end
     
-    one_hot_to_bin #(
-        .ONE_HOT_WIDTH    (ARBITER_WIDTH)
-    )conv 
-    (
-        .one_hot_code(grant),
-        .bin_code(grant_bcd)
-    );
-
     always @ (`pronoc_clk_reset_edge )begin 
         if(`pronoc_reset) begin
             low_pr    <=    {ARBITER_BIN_WIDTH{1'b0}};
         end else begin
-            if(priority_en) low_pr <= grant_bcd;
+            if(priority_en) low_pr <= grant_bin;
         end
     end
     
-
     assign any_grant = | request;
-
     generate 
-        if(ARBITER_WIDTH    ==2) begin :w2        arbiter_2_one_hot arb( .in(request) , .out(grant), .low_pr(low_pr)); end
-        if(ARBITER_WIDTH    ==3) begin :w3        arbiter_3_one_hot arb( .in(request) , .out(grant), .low_pr(low_pr)); end
-        if(ARBITER_WIDTH    ==4) begin :w4        arbiter_4_one_hot arb( .in(request) , .out(grant), .low_pr(low_pr)); end
+        if(ARBITER_WIDTH    ==2) begin : w2 arbiter_2_one_hot arb( .D_in(request) , .Q_out(grant), .low_pr(low_pr)); end
+        if(ARBITER_WIDTH    ==3) begin : w3 arbiter_3_one_hot arb( .D_in(request) , .Q_out(grant), .low_pr(low_pr)); end
+        if(ARBITER_WIDTH    ==4) begin : w4 arbiter_4_one_hot arb( .D_in(request) , .Q_out(grant), .low_pr(low_pr)); end
     endgenerate
-
-endmodule   
+endmodule
 
 
 
 /*******************
-*
 *    thermo_arbiter RRA
-*
 ********************/
-
 module thermo_gen #(
     parameter WIDTH=16
-
-
 )(
-    input  [WIDTH-1    :    0]in,
-    output [WIDTH-1    :    0]out
+    input [WIDTH-1 : 0]D_in,
+    output [WIDTH-1 : 0]Q_out
 );
     genvar i;
     generate
     for(i=0;i<WIDTH;i=i+1)begin :lp
-        assign out[i]= | in[i    :0];    
+        assign Q_out[i]= | D_in[i :0];    
     end
     endgenerate
-
 endmodule
- 
- 
- 
- 
-module thermo_arbiter #(
- parameter    ARBITER_WIDTH    =4
-        
-)
-(    
-   clk, 
-   reset, 
-   request, 
-   grant,
-   any_grant
-);
-
-        
-
-    
-    input        [ARBITER_WIDTH-1             :    0]    request;
-    output    [ARBITER_WIDTH-1            :    0]    grant;
-    output                                            any_grant;
-    input                                                reset,clk;
-    
-    
-    wire        [ARBITER_WIDTH-1             :    0]    termo1,termo2,mux_out,masked_request,edge_mask;
-    reg        [ARBITER_WIDTH-1             :    0]    pr;
-
-
-    thermo_gen #(
-        .WIDTH(ARBITER_WIDTH)
-    ) tm1
-    (
-        .in(request),
-        .out(termo1)
-    );
-
-
 
 
-    thermo_gen #(
-        .WIDTH(ARBITER_WIDTH)
-    ) tm2
-    (
-        .in(masked_request),
-        .out(termo2)
-    );
-
+module thermo_arbiter #(
+    parameter    ARBITER_WIDTH    =4
+)(    
+    clk, 
+    reset, 
+    request, 
+    grant,
+    any_grant
+);
+    input [ARBITER_WIDTH-1 : 0] request;
+    output [ARBITER_WIDTH-1 : 0] grant;
+    output any_grant;
+    input reset,clk;
+    wire [ARBITER_WIDTH-1 : 0] mux_out,masked_request,edge_mask;
+    reg       [ARBITER_WIDTH-1 : 0] pr;
+    reg       [ARBITER_WIDTH-1 : 0] termo1,termo2;
+    integer i;
+    always @(*) begin 
+        for(i=0;i<ARBITER_WIDTH; i=i+1) begin 
+            termo1[i] = |(request << (ARBITER_WIDTH - 1 - i));
+            termo2[i] = |(masked_request << (ARBITER_WIDTH - 1 - i));
+        end
+    end
     
     assign mux_out=(termo2[ARBITER_WIDTH-1])? termo2 : termo1;
     assign masked_request= request & pr;
@@ -459,346 +377,225 @@ module thermo_arbiter #(
         else begin 
             if(any_grant) pr<= edge_mask;
         end
-    
     end
     
     assign edge_mask= {mux_out[ARBITER_WIDTH-2:0],1'b0};
     assign grant= mux_out ^ edge_mask;
+endmodule
 
 
 
-endmodule
-    
-    
-
- 
- 
 module thermo_arbiter_priority_en #(
- parameter    ARBITER_WIDTH    =4
-        
-)
-(    
-   clk, 
-   reset, 
-   request, 
-   grant,
-   any_grant,
-   priority_en
+    parameter    ARBITER_WIDTH    =4
+)(    
+    clk, 
+    reset, 
+    request, 
+    grant,
+    any_grant,
+    priority_en
 );
-
-        
-
-    
-    input        [ARBITER_WIDTH-1             :    0]    request;
-    output    [ARBITER_WIDTH-1            :    0]    grant;
-    output                                            any_grant;
-    input                                                reset,clk;
+    input [ARBITER_WIDTH-1 : 0] request;
+    output [ARBITER_WIDTH-1 : 0] grant;
+    output any_grant;
+    input reset,clk;
     input priority_en;
     
-    wire        [ARBITER_WIDTH-1             :    0]    termo1,termo2,mux_out,masked_request,edge_mask;
-    reg        [ARBITER_WIDTH-1             :    0]    pr;
-
-
-    thermo_gen #(
-        .WIDTH(ARBITER_WIDTH)
-    ) tm1
-    (
-        .in(request),
-        .out(termo1)
-    );
-
-
-
-
-    thermo_gen #(
-        .WIDTH(ARBITER_WIDTH)
-    ) tm2
-    (
-        .in(masked_request),
-        .out(termo2)
-    );
+    wire [ARBITER_WIDTH-1 : 0] mux_out,masked_request,edge_mask;
+    reg   [ARBITER_WIDTH-1 : 0] pr;
+    reg   [ARBITER_WIDTH-1 : 0] termo1,termo2;
+    integer i;
+    always @(*) begin 
+        for(i=0;i<ARBITER_WIDTH; i=i+1) begin 
+            termo1[i] = |(request << (ARBITER_WIDTH - 1 - i));
+            termo2[i] = |(masked_request << (ARBITER_WIDTH - 1 - i));
+        end
+    end
 
-    
     assign mux_out=(termo2[ARBITER_WIDTH-1])? termo2 : termo1;
     assign masked_request= request & pr;
     assign any_grant=termo1[ARBITER_WIDTH-1];
-
     always @ (`pronoc_clk_reset_edge )begin 
             if(`pronoc_reset) pr<= {ARBITER_WIDTH{1'b1}};
         else begin 
             if(priority_en) pr<= edge_mask;
         end
-    
     end
     
     assign edge_mask= {mux_out[ARBITER_WIDTH-2:0],1'b0};
     assign grant= mux_out ^ edge_mask;
-
-
-
 endmodule
-    
 
 
-
-
-
-
- 
 module thermo_arbiter_ext_priority #(
- parameter    ARBITER_WIDTH    =4
-        
-)
-(    
-   
-   request, 
-   grant,
-   any_grant,
-   priority_in
-  
+    parameter    ARBITER_WIDTH    =4
+)(
+    request, 
+    grant,
+    any_grant,
+    priority_in
 );
-
-        
-
-    
-    input        [ARBITER_WIDTH-1             :    0]    request;
-    output    [ARBITER_WIDTH-1            :    0]    grant;
-    output                                            any_grant;
-    input   [ARBITER_WIDTH-1            :   0]  priority_in;
-
-    wire        [ARBITER_WIDTH-1             :    0]    termo1,termo2,mux_out,masked_request,edge_mask;
-    wire        [ARBITER_WIDTH-1             :    0]    pr;
-
-
-    thermo_gen #(
-        .WIDTH(ARBITER_WIDTH)
-    ) tm1
-    (
-        .in(request),
-        .out(termo1)
-    );
-
-
-
-
-    thermo_gen #(
-        .WIDTH(ARBITER_WIDTH)
-    ) tm2
-    (
-        .in(masked_request),
-        .out(termo2)
-    );
-
-
-    thermo_gen #(
-        .WIDTH(ARBITER_WIDTH)
-    ) tm3
-    (
-        .in(priority_in),
-        .out(pr)
-    );
-
+    input [ARBITER_WIDTH-1 : 0] request;
+    output [ARBITER_WIDTH-1 : 0] grant;
+    output any_grant;
+    input [ARBITER_WIDTH-1 : 0] priority_in;
+    
+    wire [ARBITER_WIDTH-1 : 0] mux_out,masked_request,edge_mask;
+    reg [ARBITER_WIDTH-1 : 0] termo1,termo2,pr;
+    
+    integer i;
+    always @(*) begin 
+        for(i=0;i<ARBITER_WIDTH; i=i+1) begin 
+            termo1[i] = |(request << (ARBITER_WIDTH - 1 - i));
+            termo2[i] = |(masked_request << (ARBITER_WIDTH - 1 - i));
+            pr[i] = |(priority_in << (ARBITER_WIDTH - 1 - i));
+        end
+    end
     
-assign mux_out=(termo2[ARBITER_WIDTH-1])? termo2 : termo1;
-assign masked_request= request & pr;
-assign any_grant=termo1[ARBITER_WIDTH-1];
-
-
-assign edge_mask= {mux_out[ARBITER_WIDTH-2:0],1'b0};
-assign grant= mux_out ^ edge_mask;
-
-
-
+    assign mux_out=(termo2[ARBITER_WIDTH-1])? termo2 : termo1;
+    assign masked_request= request & pr;
+    assign any_grant=termo1[ARBITER_WIDTH-1];
+    assign edge_mask= {mux_out[ARBITER_WIDTH-2:0],1'b0};
+    assign grant= mux_out ^ edge_mask;
 endmodule
-    
-
 
 /********************************
-*    
 *   Tree arbiter
-* 
-*******************************/
-
+******************************/
 module tree_arbiter #(
-        parameter    GROUP_NUM        =4,
-        parameter    ARBITER_WIDTH    =16
-)
-(    
-   clk, 
-   reset, 
-   request, 
-   grant,
-   any_grant
+    parameter    GROUP_NUM        =4,
+    parameter    ARBITER_WIDTH    =16
+)(
+    clk, 
+    reset, 
+    request, 
+    grant,
+    any_grant
 );
-
- 
     function integer log2;
-      input integer number; begin   
-         log2=(number <=1) ? 1: 0;    
-         while(2**log2<number) begin    
-            log2=log2+1;    
-         end 	   
-      end   
+    input integer number; begin
+        log2=(number <=1) ? 1: 0;
+        while(2**log2<number) begin
+            log2=log2+1;
+        end
+    end
     endfunction // log2 
-
-  localparam N = ARBITER_WIDTH;
-  localparam S = log2(ARBITER_WIDTH); // ceil of log_2 of N - put manually
-  
-
-  // I/O interface
-  input           clk;
-  input           reset;
-  input  [N-1:0]  request;
-  output [N-1:0]  grant;
-  output          any_grant;
-
-
+    
+    localparam N = ARBITER_WIDTH;
+    localparam S = log2(ARBITER_WIDTH); // ceil of log_2 of N - put manually
+    // I/O interface
+    input clk;
+    input reset;
+    input [N-1:0] request;
+    output [N-1:0] grant;
+    output any_grant;
+    
     localparam GROUP_WIDTH    =    ARBITER_WIDTH/GROUP_NUM;
-  
-  wire [GROUP_WIDTH-1        :    0]    group_req    [GROUP_NUM-1        :    0];
-  wire [GROUP_WIDTH-1        :    0]    group_grant [GROUP_NUM-1        :    0];
-  wire [GROUP_WIDTH-1        :    0]    grant_masked[GROUP_NUM-1        :    0];
-  
-  wire [GROUP_NUM-1            :    0] any_group_member_req;
-  wire [GROUP_NUM-1            :    0] any_group_member_grant;
- 
+    wire [GROUP_WIDTH-1 : 0] group_req    [GROUP_NUM-1 : 0];
+    wire [GROUP_WIDTH-1 : 0] group_grant [GROUP_NUM-1 : 0];
+    wire [GROUP_WIDTH-1 : 0] grant_masked[GROUP_NUM-1 : 0];
+    wire [GROUP_NUM-1 : 0] any_group_member_req;
+    wire [GROUP_NUM-1 : 0] any_group_member_grant;
     
     genvar i;
     generate
     for (i=0;i<GROUP_NUM;i=i+1) begin :group_lp
-        
         //seprate inputs in group
-        assign group_req[i]    =    request[(i+1)*GROUP_WIDTH-1        :    i*GROUP_WIDTH];
-        
+        assign group_req[i] =    request[(i+1)*GROUP_WIDTH-1 : i*GROUP_WIDTH];
         //check if any member of qrup has request
-        assign any_group_member_req[i]    =    | group_req[i];
-        
+        assign any_group_member_req[i] =    | group_req[i];
         //arbiterate one request from each group
         arbiter #(
             .ARBITER_WIDTH    (GROUP_WIDTH)
-        )group_member_arbiter
-        (    
+        )group_member_arbiter   (    
             .clk            (clk), 
             .reset        (reset), 
             .request        (group_req[i]), 
             .grant        (group_grant[i]),
             .any_grant    ()
         );
-        
-    // mask the non selected groups        
+        // mask the non selected groups        
         assign grant_masked [i] = (any_group_member_grant[i])?    group_grant[i]: {GROUP_WIDTH{1'b0}};
-    
-    //assemble the grants
-        assign grant [(i+1)*GROUP_WIDTH-1        :    i*GROUP_WIDTH] = grant_masked [i];
-    
-    
+        //assemble the grants
+        assign grant [(i+1)*GROUP_WIDTH-1 : i*GROUP_WIDTH] = grant_masked [i];
     end
     endgenerate
     
     //select one group which has atleast one active request
-    
     //arbiterate one request from each group
-        arbiter #(
-            .ARBITER_WIDTH    (GROUP_NUM)
-        )second_arbiter
-        (    
-            .clk        (clk), 
-            .reset        (reset), 
-            .request    (any_group_member_req), 
-            .grant        (any_group_member_grant),
-            .any_grant    (any_grant)
-        );
-                
-    
- 
- endmodule 
- 
-
+    arbiter #(
+        .ARBITER_WIDTH    (GROUP_NUM)
+    )second_arbiter (    
+        .clk        (clk), 
+        .reset        (reset), 
+        .request    (any_group_member_req), 
+        .grant        (any_group_member_grant),
+        .any_grant    (any_grant)
+    );
+endmodule 
 
 
- 
- 
 /*******************************
-
-    my_one_hot_arbiter_ext_priority
-
+*    my_one_hot_arbiter_ext_priority
 *******************************/
-
 module my_one_hot_arbiter_ext_priority #(
     parameter ARBITER_WIDTH =4
-    
-    
-)
-(
-    input   [ARBITER_WIDTH-1            :   0]  request,
-    input   [ARBITER_WIDTH-1            :   0]  priority_in,
-    output  [ARBITER_WIDTH-1            :   0]  grant,
-    output                                      any_grant
+)(
+    input [ARBITER_WIDTH-1 : 0] request,
+    input [ARBITER_WIDTH-1 : 0] priority_in,
+    output [ARBITER_WIDTH-1 : 0] grant,
+    output any_grant
 );
- 
+    
     function integer log2;
-      input integer number; begin   
-         log2=(number <=1) ? 1: 0;    
-         while(2**log2<number) begin    
-            log2=log2+1;    
-         end 	   
-      end   
+    input integer number; begin
+        log2=(number <=1) ? 1: 0;
+        while(2**log2<number) begin
+            log2=log2+1;
+        end
+    end
     endfunction // log2 
-
+    
     localparam ARBITER_BIN_WIDTH= log2(ARBITER_WIDTH);
-    wire    [ARBITER_BIN_WIDTH-1        :   0]  low_pr;
-      
-   
-    wire [ARBITER_WIDTH-1            :   0] low_pr_one_hot = {priority_in[0],priority_in[ARBITER_BIN_WIDTH-1:1]};
+    reg [ARBITER_BIN_WIDTH-1 : 0] low_pr;
+    wire [ARBITER_WIDTH-1 : 0] low_pr_one_hot = {priority_in[0],priority_in[ARBITER_BIN_WIDTH-1:1]};
+    //onehot to bin
+    integer i;
+    always @(*) begin
+        low_pr = '0;
+        for (i = 0; i < ARBITER_WIDTH; i=i+1) begin
+            if (low_pr_one_hot[i]) begin
+                low_pr = ARBITER_BIN_WIDTH'(i); // casting i to BIN_WIDTH
+            end
+        end
+    end
     
-    one_hot_to_bin #(
-        .ONE_HOT_WIDTH    (ARBITER_WIDTH)
-    )conv 
-    (
-        .one_hot_code(low_pr_one_hot),
-        .bin_code(low_pr)
-    );
-      
-
     assign any_grant = | request;
-
     generate 
-        if(ARBITER_WIDTH    ==2) begin: w2       arbiter_2_one_hot arb( .in(request) , .out(grant), .low_pr(low_pr)); end
-        if(ARBITER_WIDTH    ==3) begin: w3       arbiter_3_one_hot arb( .in(request) , .out(grant), .low_pr(low_pr)); end
-        if(ARBITER_WIDTH    ==4) begin: w4       arbiter_4_one_hot arb( .in(request) , .out(grant), .low_pr(low_pr)); end
+        if(ARBITER_WIDTH    ==2) begin: w2       arbiter_2_one_hot arb( .D_in(request) , .Q_out(grant), .low_pr(low_pr)); end
+        if(ARBITER_WIDTH    ==3) begin: w3       arbiter_3_one_hot arb( .D_in(request) , .Q_out(grant), .low_pr(low_pr)); end
+        if(ARBITER_WIDTH    ==4) begin: w4       arbiter_4_one_hot arb( .D_in(request) , .Q_out(grant), .low_pr(low_pr)); end
     endgenerate
-
 endmodule
 
 
 /*********************************
-*
 *       arbiter_ext_priority
-*
 **********************************/
-
-
- module arbiter_ext_priority  #(
-        parameter   ARBITER_WIDTH   =8
-        
-)
-(   
-  
-   request, 
-   grant,
-   priority_in,
-   any_grant
+module arbiter_ext_priority  #(
+    parameter   ARBITER_WIDTH   =8
+)(   
+    request, 
+    grant,
+    priority_in,
+    any_grant
 );
-
-    
-    input   [ARBITER_WIDTH-1            :   0]  request;
-    input   [ARBITER_WIDTH-1            :   0]  priority_in;
-    output  [ARBITER_WIDTH-1            :   0]  grant;
-    output                                      any_grant;
- 
-   /*
+    input [ARBITER_WIDTH-1 : 0] request;
+    input [ARBITER_WIDTH-1 : 0] priority_in;
+    output [ARBITER_WIDTH-1 : 0] grant;
+    output any_grant;
+    /*
     generate 
-  
     if(ARBITER_WIDTH<=4) begin :ws4
         //my own arbiter 
         my_one_hot_arbiter_ext_priority #(
@@ -806,22 +603,16 @@ endmodule
         )
         one_hot_arb
         (   
-           
             .request    (request),
             .priority_in(priority_in), 
             .grant      (grant),
             .any_grant  (any_grant)
         );
-    
     end else begin :wb4
     */
-        
         thermo_arbiter_ext_priority #(
             .ARBITER_WIDTH  (ARBITER_WIDTH)
-        )
-        one_hot_arb
-        (   
-            
+        ) one_hot_arb  (   
             .request    (request), 
             .priority_in(priority_in), 
             .grant      (grant),
@@ -829,78 +620,50 @@ endmodule
         );
    // end
    // endgenerate
- 
- 
- 
- 
 endmodule 
- 
-
-
-
 
 
 
-    
-
- 
- module fixed_priority_arbiter #(
-     parameter   ARBITER_WIDTH   =8,
-     parameter   HIGH_PRORITY_BIT = "HSB"
- )
- (   
-  
-   request, 
-   grant,
-   any_grant
+module fixed_priority_arbiter #(
+    parameter   ARBITER_WIDTH   =8,
+    parameter   HIGH_PRORITY_BIT = "HSB"
+) (   
+    request, 
+    grant,
+    any_grant
 );
-
-    
-    input   [ARBITER_WIDTH-1            :   0]  request;
-    output  [ARBITER_WIDTH-1            :   0]  grant;
-    output                                      any_grant;
-   /*
-    wire    [ARBITER_WIDTH-1            :   0]  cout;
-    reg     [ARBITER_WIDTH-1            :   0]  cin;
-    
-    
-  
-    
+    input [ARBITER_WIDTH-1 : 0] request;
+    output [ARBITER_WIDTH-1 : 0] grant;
+    output any_grant;
+    /*
+    wire [ARBITER_WIDTH-1 : 0] cout;
+    reg     [ARBITER_WIDTH-1 : 0] cin;
     assign grant    = cin & request;
     assign cout     = cin & ~request; 
-    
-     always @(*) begin 
+    always @(*) begin 
         if( HIGH_PRORITY_BIT == "HSB")  cin      = {1'b1, cout[ARBITER_WIDTH-1 :1]}; // hsb has highest priority
         else                            cin      = {cout[ARBITER_WIDTH-2 :0] ,1'b1}; // lsb has highest priority
     end//always
-    
     */
     
     assign  any_grant= | request;
-    wire  [ARBITER_WIDTH-1            :   0] termo_code, edge_mask;
+    wire [ARBITER_WIDTH-1 : 0] termo_code, edge_mask;
     
-     
     genvar i;
     generate
     if( HIGH_PRORITY_BIT == "LSB") begin :hsb
         for(i=0;i<ARBITER_WIDTH;i=i+1)begin :lp
-            assign termo_code[i]= | request[i    :0];    
+            assign termo_code[i]= | request[i :0];    
         end
         assign edge_mask=  {termo_code[ARBITER_WIDTH-2:0],1'b0};
-        
     end else begin :hsb
         for(i=0;i<ARBITER_WIDTH;i=i+1)begin :lp
-            assign termo_code[i]= | request[ARBITER_WIDTH-1    :i];    
+            assign termo_code[i]= | request[ARBITER_WIDTH-1 :i];    
         end
         assign edge_mask=  {1'b0, termo_code[ARBITER_WIDTH-1:1]};
-        
     end
     endgenerate
     
     assign grant= termo_code ^ edge_mask;
-    
-    
-    
 endmodule
-
-`endif
+`endif
\ No newline at end of file
diff --git a/mpsoc/rtl/arch/baseline.v b/mpsoc/rtl/arch/baseline.v
index ab55b93..6ae0b7b 100755
--- a/mpsoc/rtl/arch/baseline.v
+++ b/mpsoc/rtl/arch/baseline.v
@@ -35,7 +35,7 @@ module baseline_allocator #(
     parameter TREE_ARBITER_EN = 0,
     parameter DEBUG_EN = 1,
     parameter SWA_ARBITER_TYPE = "WRRA",
-    parameter SELF_LOOP_EN= "NO"
+    parameter SELF_LOOP_EN= 0
 )
 (
     dest_port_all,
@@ -62,11 +62,11 @@ module baseline_allocator #(
     localparam 
         PV = V * P,
         PVV = PV * V,   
-        P_1 = (SELF_LOOP_EN == "NO") ? P-1 : P,
+        P_1 = (SELF_LOOP_EN) ? P : P-1, 
         PP_1 = P_1 * P,
-        PVP_1 = PV * P_1;                   
-                    
-    input  [PVP_1-1:   0]    dest_port_all;    
+        PVP_1 = PV * P_1;
+        
+    input  [PVP_1-1:   0]    dest_port_all;
     input  [PV-1:   0]    ovc_is_assigned_all;
     input  [PV-1:   0]  ivc_request_all;
     input  [PV-1:   0]  assigned_ovc_not_full_all;
@@ -302,7 +302,7 @@ module canonical_vc_alloc #(
         );
        end
        
-       custom_or #(
+       reduction_or #(
         .IN_NUM (P_1),
         .OUT_WIDTH (V)
         
diff --git a/mpsoc/rtl/arch/flit_buffer_reg_bas.v b/mpsoc/rtl/arch/flit_buffer_reg_bas.v
index 65d9323..9afca74 100644
--- a/mpsoc/rtl/arch/flit_buffer_reg_bas.v
+++ b/mpsoc/rtl/arch/flit_buffer_reg_bas.v
@@ -8,7 +8,6 @@
 `timescale 1ns / 1ps
 
 module  flit_buffer_reg_base #(
-    parameter NOC_ID = 0,
     parameter V        =   4,
     parameter B        =   4,   // buffer space :flit per VC 
     parameter Fpay     =   32,
@@ -16,9 +15,8 @@ module  flit_buffer_reg_base #(
     parameter DEBUG_EN =   1,
     parameter C=1,
     parameter DSTPw=4,
-    parameter SSA_EN="YES", // "YES" , "NO"  
+    parameter SSA_EN=1, // 1,0
     parameter CAST_TYPE="UNI_CAST"
-         
 )(
     din,
     vc_num_wr,
@@ -138,7 +136,7 @@ module  flit_buffer_reg_base #(
     flit_buffer #(
 		.V(V),
         .B(B),
-        .SSA_EN("NO"),// should be "NO" even if SSA is enabled
+        .SSA_EN(0),// should be 0 even if SSA is enabled
         .Fw(Fw),
 		.PCK_TYPE(PCK_TYPE),
 		.CAST_TYPE(CAST_TYPE),
@@ -184,7 +182,6 @@ module  flit_buffer_reg_base #(
         
         
      extract_header_flit_info #(
-        .NOC_ID(NOC_ID),
         .DATA_w(0)
      ) header_extractor (
          .flit_in({flit_reg_mux_out[REGFw-1:REGFw-2],flit_reg_wr_en,flit_reg_mux_out[Fpay-1 : 0]}),
@@ -214,20 +211,20 @@ module  flit_buffer_reg_base #(
       pronoc_register #(
            .W(REGFw)          
       ) reg1 ( 
-           .in(flit_regs_next[i]),
+           .D_in(flit_regs_next[i]),
            .reset(reset),    
            .clk(clk),      
-           .out(flit_regs[i])
+           .Q_out(flit_regs[i])
       );
       
       
        pronoc_register #(
            .W(Cw)           
       ) reg2 ( 
-           .in(class_vc_next[i]),
+           .D_in(class_vc_next[i]),
            .reset(reset),    
            .clk(clk),      
-           .out(class_vc[i])
+           .Q_out(class_vc[i])
       );
         
         
diff --git a/mpsoc/rtl/arch/iport_reg_base.sv b/mpsoc/rtl/arch/iport_reg_base.sv
index 591b718..fdfa09f 100644
--- a/mpsoc/rtl/arch/iport_reg_base.sv
+++ b/mpsoc/rtl/arch/iport_reg_base.sv
@@ -36,7 +36,6 @@
 **************************/
 
 module iport_reg_base  #(
-    parameter NOC_ID=0,
     parameter PCK_TYPE = "MULTI_FLIT",
     parameter V = 4,     // vc_num_per_port
     parameter P = 5,     // router port num
@@ -53,7 +52,7 @@ module iport_reg_base  #(
     parameter VC_REALLOCATION_TYPE =  "ATOMIC",
     parameter COMBINATION_TYPE= "BASELINE",// "BASELINE", "COMB_SPEC1", "COMB_SPEC2", "COMB_NONSPEC"
     parameter TOPOLOGY =  "MESH",//"MESH","TORUS"
-    parameter ROUTE_NAME="XY",// "XY", "TRANC_XY"
+    parameter ROUTE_NAME="DOR",// "DOR", "TRANC_DOR"
     parameter ROUTE_TYPE="DETERMINISTIC",// "DETERMINISTIC", "FULL_ADAPTIVE", "PAR_ADAPTIVE"
     parameter DEBUG_EN =1,
     parameter AVC_ATOMIC_EN= 0,
@@ -61,7 +60,7 @@ module iport_reg_base  #(
     parameter [CVw-1: 0] CLASS_SETTING = {CVw{1'b1}}, // shows how each class can use VCs   
     parameter [V-1  : 0] ESCAP_VC_MASK = 4'b1000,  // mask scape vc, valid only for full adaptive
     parameter DSTPw = P-1,
-    parameter SSA_EN="YES", // "YES" , "NO"      
+    parameter SSA_EN=1, // 1: enable SSA, 0: disable SSA 
     parameter SWA_ARBITER_TYPE ="RRA",// "RRA","WRRA"
     parameter WEIGHTw=4,
     parameter WRRA_CONFIG_INDEX=0,
@@ -187,7 +186,6 @@ module iport_reg_base  #(
 
     //extract header flit info
     extract_header_flit_info #(
-        .NOC_ID(NOC_ID),
         .DATA_w(0)
     ) header_extractor (
         .flit_in(flit_in),
@@ -232,13 +230,13 @@ module iport_reg_base  #(
      
 
     pronoc_register #(.W(WEIGHTw), .RESET_TO(1)) reg5(
-    		.in		(iport_weight_next ), 
+    		.D_in(iport_weight_next ), 
     		.reset  (reset ), 
     		.clk    (clk   ), 
-    		.out    (iport_weight  ));
+    		.Q_out(iport_weight  ));
 	
 	
-    always @ (*)begin 
+    always_comb begin 
     	iport_weight_next = iport_weight;
     	if(hdr_flit_wr != {V{1'b0}})  iport_weight_next = (weight_in=={WEIGHTw{1'b0}})? 1 : weight_in; // the minimum weight is 1
     end
@@ -247,10 +245,10 @@ module iport_reg_base  #(
 // genrate write enable for lk_routing result with one clock cycle latency after reciveing the flit
     
     pronoc_register #(.W(V)) reg1(
-    		.in		(hdr_flit_wr ), 
+    		.D_in(hdr_flit_wr ), 
     		.reset  (reset ), 
     		.clk    (clk   ), 
-    		.out    (hdr_flit_wr_delayed  ));
+    		.Q_out(hdr_flit_wr_delayed  ));
 
 
 
@@ -260,14 +258,7 @@ generate
     /* verilator lint_off WIDTH */  
     if (( TOPOLOGY == "RING" || TOPOLOGY == "LINE" || TOPOLOGY == "MESH" || TOPOLOGY == "TORUS") && (T3>1)) begin : multi_local
     /* verilator lint_on WIDTH */  
-        mesh_tori_endp_addr_decode #(
-            .TOPOLOGY("MESH"),
-            .T1(T1),
-            .T2(T2),
-            .T3(T3),
-            .EAw(EAw)
-        )
-        endp_addr_decode
+        regular_topo_endp_addr_decode endp_addr_decode
         (
             .e_addr(dest_e_addr_in),
             .ex( ),
@@ -275,7 +266,7 @@ generate
             .el(endp_l_in),
             .valid( )
         );
-   end
+    end
 
     /* verilator lint_off WIDTH */  
     if(TOPOLOGY=="FATTREE" && ROUTE_NAME == "NCA_STRAIGHT_UP") begin : fat
@@ -324,10 +315,7 @@ generate
             .wr_en (flit_wr[i]),   // Write enable
             .rd_en (ivc_num_getting_sw_grant[i]),   // Read the next word
             .dout (flit_is_tail[i]),    // Data out
-            .full ( ),
-            .nearly_full ( ),
-            .recieve_more_than_0 ( ),
-            .recieve_more_than_1 ( ),
+            .status_o(),
             .reset (reset),
             .clk (clk)            
         );
@@ -344,10 +332,7 @@ generate
                 .wr_en (hdr_flit_wr[i]),   // Write enable
                 .rd_en (class_rd_fifo[i]),   // Read the next word
                 .dout (class_out[i]),    // Data out
-                .full ( ),
-                .nearly_full ( ),
-                .recieve_more_than_0 ( ),
-                .recieve_more_than_1 ( ),
+                .status_o(),
                 .reset (reset),
                 .clk (clk)
             
@@ -367,10 +352,7 @@ generate
              .wr_en (hdr_flit_wr_delayed [i]),   // Write enable
              .rd_en (lk_dst_rd_fifo [i]),   // Read the next word
              .dout (lk_destination_encoded  [(i+1)*DSTPw-1 : i*DSTPw]),    // Data out
-             .full (),
-             .nearly_full (),
-             .recieve_more_than_0 (),
-             .recieve_more_than_1 (),
+             .status_o(),
              .reset (reset),
              .clk (clk)
              
@@ -390,10 +372,7 @@ generate
                  .wr_en(hdr_flit_wr[i]),   // Write enable
                  .rd_en(dst_rd_fifo[i]),   // Read the next word
                  .dout(dest_port_encoded[(i+1)*DSTPw-1 : i*DSTPw]),    // Data out
-                 .full(),
-                 .nearly_full(),
-                 .recieve_more_than_0(),
-                 .recieve_more_than_1(),
+                 .status_o(),
                  .reset(reset),
                  .clk(clk) 
             );               
@@ -410,10 +389,7 @@ generate
                 .wr_en(hdr_flit_wr[i]),   // Write enable
                 .rd_en(dst_rd_fifo[i]),   // Read the next word
                 .dout(dest_port_encoded[(i+1)*DSTPw-1 : i*DSTPw]),    // Data out
-                .full(),
-                .nearly_full(),
-                .recieve_more_than_0(),
-                .recieve_more_than_1(),
+                .status_o(),
                 .reset(reset),
                 .clk(clk),
                 .clear(destport_clear[(i+1)*DSTPw-1 : i*DSTPw])   // clear other destination ports once one of them is selected
@@ -464,10 +440,7 @@ generate
                  .wr_en(hdr_flit_wr[i]),   // Write enable
                  .rd_en(dst_rd_fifo[i]),   // Read the next word
                  .dout(endp_localp_num[(i+1)*ELw-1 : i*ELw]),    // Data out
-                 .full( ),
-                 .nearly_full( ),
-                 .recieve_more_than_0(),
-                 .recieve_more_than_1(),
+                 .status_o(),
                  .reset(reset),
                  .clk(clk) 
             );       
@@ -511,8 +484,8 @@ generate
         	.N(V)
         )
         onehot_mux(
-        	.in(flit_is_tail),
-        	.out(granted_flit_is_tail),
+        	.D_in(flit_is_tail),
+        	.Q_out(granted_flit_is_tail),
         	.sel(ivc_num_getting_sw_grant)
         );
     
@@ -582,7 +555,6 @@ generate
         
         
         flit_buffer_reg_base #(           
-            .NOC_ID(NOC_ID),
             .V(V),
             .B(B),
             .SSA_EN(SSA_EN),
@@ -667,18 +639,9 @@ generate
 endgenerate    
 
     look_ahead_routing #(
-    	.T1(T1),
-        .T2(T2),
-        .T3(T3),
-        .T4(T4), 
-        .P(P),       
-        .RAw(RAw),  
-        .EAw(EAw), 
-    	.DSTPw(DSTPw),
-    	.SW_LOC(SW_LOC),
-    	.TOPOLOGY(TOPOLOGY),
-    	.ROUTE_NAME(ROUTE_NAME),
-    	.ROUTE_TYPE(ROUTE_TYPE)
+        .P(P),
+    	.SW_LOC(SW_LOC)
+    	
     ) lk_routing (
         .current_r_addr(current_r_addr),
         .neighbors_r_addr(neighbors_r_addr),
@@ -691,7 +654,6 @@ endgenerate
      );
 
     header_flit_update_lk_route_ovc #(
-        .NOC_ID(NOC_ID),
         .P(P)   
     ) the_flit_update (
         .flit_in (buffer_out),
@@ -710,10 +672,10 @@ endgenerate
         
     
     pronoc_register #(.W(V)) reg2(
-    		.in		(dst_rd_fifo ), 
+    		.D_in(dst_rd_fifo ), 
     		.reset  (reset ), 
     		.clk    (clk   ), 
-    		.out    (lk_dst_rd_fifo  ));
+    		.Q_out(lk_dst_rd_fifo  ));
 
    
     assign    dst_rd_fifo = reset_ivc;
@@ -746,7 +708,7 @@ if(DEBUG_EN) begin :dbg
      if (( TOPOLOGY == "RING" || TOPOLOGY == "LINE" || TOPOLOGY == "MESH" || TOPOLOGY == "TORUS")) begin : mesh_based
      /* verilator lint_on WIDTH */  
 
-        debug_mesh_tori_route_ckeck #(
+        debug_regular_topo_route_ckeck #(
             .T1(T1),
             .T2(T2),
             .T3(T3),
diff --git a/mpsoc/rtl/main_comp.v b/mpsoc/rtl/main_comp.v
index b53fc6b..fde6876 100755
--- a/mpsoc/rtl/main_comp.v
+++ b/mpsoc/rtl/main_comp.v
@@ -1,274 +1,121 @@
- `timescale  1ns/1ps
-
-
+`include "pronoc_def.v"
 /**********************************************************************
-**	File:  main_comp.v
+**    File: main_comp.v
 **    
-**	Copyright (C) 2014-2017  Alireza Monemi
+**    Copyright (C) 2014-2017  Alireza Monemi
 **    
-**	This file is part of ProNoC 
+**    This file is part of ProNoC 
 **
-**	ProNoC ( stands for Prototype Network-on-chip)  is free software: 
-**	you can redistribute it and/or modify it under the terms of the GNU
-**	Lesser General Public License as published by the Free Software Foundation,
-**	either version 2 of the License, or (at your option) any later version.
+**    ProNoC ( stands for Prototype Network-on-chip)  is free software: 
+**    you can redistribute it and/or modify it under the terms of the GNU
+**    Lesser General Public License as published by the Free Software Foundation,
+**    either version 2 of the License, or (at your option) any later version.
 **
-** 	ProNoC is distributed in the hope that it will be useful, but WITHOUT
-** 	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
-** 	or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
-** 	Public License for more details.
+**     ProNoC is distributed in the hope that it will be useful, but WITHOUT
+**     ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+**     or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
+**     Public License for more details.
 **
-** 	You should have received a copy of the GNU Lesser General Public
-** 	License along with ProNoC. If not, see <http:**www.gnu.org/licenses/>.
+**     You should have received a copy of the GNU Lesser General Public
+**     License along with ProNoC. If not, see <http:**www.gnu.org/licenses/>.
 **
 **
-**	Description: 
-**	This file contains several general RTL modules such as 
-**	different types of multiplexors, converters and counters ...
+**    Description: 
+**    This file contains several general RTL modules such as 
+**    different types of multiplexors, converters and counters ...
 **
 **************************************************************/
 `ifndef PRONOC_COMMON
 `define PRONOC_COMMON
-`include "pronoc_def.v"
-
-module pronoc_register 
-       #(
-        parameter W=1,
-        parameter  RESET_TO={W{1'b0}}
-        
-        )( 
-            input [W-1:0] in,
-            input reset,    
-            input clk,      
-            output [W-1:0] out
-        );
-
-    pronoc_register_reset_init #(
-        .W(W)           
-    )reg1( 
-        .in(in),
-        .reset(reset),  
-        .clk(clk),      
-        .out(out),
-        .reset_to(RESET_TO[W-1 : 0])
-    );
-endmodule
-
-
-
-module pronoc_register_reset_init 
-        #(
-        parameter W=1       
-        )( 
-        input [W-1:0] in,
-        input reset,    
-        input clk,      
-        output reg [W-1:0] out,
-        input [W-1 : 0] reset_to
-        );
-    
-    
-        always @ (`pronoc_clk_reset_edge )begin 
-            if(`pronoc_reset)   out<=reset_to;
-            else        out<=in;
-        end   
-        
-endmodule
-
-
-module pronoc_register_reset_init_ld_en 
-        #(
-        parameter W=1       
-        )( 
-        input [W-1:0] in,
-        input reset,    
-        input clk, 
-        input ld,
-        output reg [W-1:0] out,
-        input [W-1 : 0] reset_to
-        );    
-    
-        always @ (`pronoc_clk_reset_edge )begin 
-            if(`pronoc_reset)   out<=reset_to;
-            else  if(ld)      out<=in;
-        end        
-endmodule
-
-
-module pronoc_register_ld_en 
-       #(
-        parameter W=1,
-        parameter  RESET_TO={W{1'b0}}
-        
-        )( 
-            input [W-1:0] in,
-            input reset,    
-            input clk,  
-            input ld,
-            output [W-1:0] out 
-        );
 
-    pronoc_register_reset_init_ld_en  #(
-        .W(W)           
-    )reg1( 
-        .in(in),
-        .reset(reset),  
-        .clk(clk),  
-        .ld(ld),
-        .out(out),
-        .reset_to(RESET_TO[W-1 : 0])
-    );
+module pronoc_register #(
+    parameter W=1,
+    parameter RESET_TO={W{1'b0}}
+)( 
+    input [W-1: 0] D_in,
+    input reset,    
+    input clk,      
+    output reg [W-1: 0] Q_out
+);
+    always @ (`pronoc_clk_reset_edge )begin 
+        if(`pronoc_reset)   Q_out <= W'(RESET_TO);
+        else  Q_out <= D_in;
+    end
 endmodule
 
 
-
 /*********************************
-
-
-
-    multiplexer
-
-    
-    
+*   multiplexer
 ********************************/
-
 module one_hot_mux #(
-        parameter   IN_WIDTH      = 20,
-        parameter   SEL_WIDTH =   5, 
-        parameter   OUT_WIDTH = IN_WIDTH/SEL_WIDTH
-
-    )
-    (
-        input [IN_WIDTH-1       :0] mux_in,
-        output[OUT_WIDTH-1  :0] mux_out,
-        input[SEL_WIDTH-1   :0] sel
-
-    );
-
-    wire [IN_WIDTH-1    :0] mask;
-    wire [IN_WIDTH-1    :0] masked_mux_in;
-    wire [SEL_WIDTH-1:0]    mux_out_gen [OUT_WIDTH-1:0]; 
+    parameter   IN_WIDTH = 20,
+    parameter   SEL_WIDTH = 5, 
+    parameter   OUT_WIDTH = IN_WIDTH/SEL_WIDTH
+)(
+    input [IN_WIDTH-1 : 0] mux_in,
+    output[OUT_WIDTH-1 : 0] mux_out,
+    input[SEL_WIDTH-1 : 0] sel
+);
+    wire [IN_WIDTH-1 : 0] mask;
+    wire [IN_WIDTH-1 : 0] masked_mux_in;
+    wire [SEL_WIDTH-1: 0]    mux_out_gen [OUT_WIDTH-1: 0]; 
     
     genvar i,j;
-    
     //first selector masking
     generate    // first_mask = {sel[0],sel[0],sel[0],....,sel[n],sel[n],sel[n]}
         for(i=0; i<SEL_WIDTH; i=i+1) begin : mask_loop
-            assign mask[(i+1)*OUT_WIDTH-1 : (i)*OUT_WIDTH]  =   {OUT_WIDTH{sel[i]} };
+            assign mask[(i+1)*OUT_WIDTH-1 : (i)*OUT_WIDTH] = {OUT_WIDTH{sel[i]} };
         end
-        
-        assign masked_mux_in    = mux_in & mask;
-        
+        assign masked_mux_in = mux_in & mask;
         for(i=0; i<OUT_WIDTH; i=i+1) begin : lp1
             for(j=0; j<SEL_WIDTH; j=j+1) begin : lp2
-                assign mux_out_gen [i][j]   =   masked_mux_in[i+OUT_WIDTH*j];
+                assign mux_out_gen [i][j] = masked_mux_in[i+OUT_WIDTH*j];
             end
             assign mux_out[i] = | mux_out_gen [i];
         end
     endgenerate
-    
 endmodule
 
 
-
-
-
-    
 /******************************
-
-    One hot demultiplexer
-
+*    One hot demultiplexer
 ****************************/   
-    
-
 module one_hot_demux    #(
-        parameter IN_WIDTH=5,
-        parameter SEL_WIDTH=4,
-        parameter OUT_WIDTH=IN_WIDTH*SEL_WIDTH
-    )
-    (
-        input   [SEL_WIDTH-1        :   0] demux_sel,//selectore
-        input   [IN_WIDTH-1         :   0] demux_in,//repeated
-        output  [OUT_WIDTH-1        :   0]  demux_out
-    );
-
-    genvar i,j;
-    generate 
-    for(i=0;i<SEL_WIDTH;i=i+1)begin :loop1
-        for(j=0;j<IN_WIDTH;j=j+1)begin :loop2
-                assign demux_out[i*IN_WIDTH+j] =     demux_sel[i]   &   demux_in[j];
-        end//for j
-    end//for i
-    endgenerate
-
-    
-
-endmodule
-
-/**************************
-
-
-    custom_or
-
-    
-***************************/
-
-
-module custom_or #(
-    parameter IN_NUM        =   4,
-    parameter OUT_WIDTH =   5
+    parameter IN_WIDTH=5,
+    parameter SEL_WIDTH=4,
+    parameter OUT_WIDTH=IN_WIDTH*SEL_WIDTH
 )(
-    or_in,
-    or_out
+    input   [SEL_WIDTH-1 : 0] demux_sel,//selectore
+    input   [IN_WIDTH-1 : 0] demux_in,//repeated
+    output  [OUT_WIDTH-1 : 0]  demux_out
 );
-    
-    localparam IN_WIDTH  = IN_NUM*OUT_WIDTH;
-    
-    input [IN_WIDTH-1       :   0]  or_in;
-    output[OUT_WIDTH-1      :   0]  or_out;
-
-    wire        [IN_NUM-1       :   0] in_sep   [OUT_WIDTH-1        :   0];
-    genvar i,j;
-    generate
-    for (i=0;i<OUT_WIDTH;i=i+1) begin: sep_loop
-        for (j=0;j<IN_NUM;j=j+1) begin: sep_loop
-            assign in_sep[i][j]= or_in [j*OUT_WIDTH+i];
-        end
-        assign or_out[i]= |in_sep[i];
-    end
-    endgenerate
-    
-    
+    genvar i;
+    generate for (i = 0; i < SEL_WIDTH; i=i+1) begin : D_
+        assign demux_out[i*IN_WIDTH +: IN_WIDTH] = (demux_sel[i]==1'b1) ? demux_in : {IN_WIDTH{1'b0}};
+    end endgenerate
 endmodule
 
-
 /*****************************************
-
-sum the output of all ports except the output of  port itself
-
-
+* sum the output of all ports 
+* except the output of  port itself
 ****************************************/
-
-
 module outport_sum #(
     parameter IN_ARRAY_WIDTH =10,
-    parameter IN_NUM     =5,
-    parameter IN_WIDTH  =   IN_ARRAY_WIDTH/IN_NUM,
-    parameter CMP_VAL   =   IN_WIDTH/(IN_NUM-1),
+    parameter IN_NUM =5,
+    parameter IN_WIDTH = IN_ARRAY_WIDTH/IN_NUM,
+    parameter CMP_VAL = IN_WIDTH/(IN_NUM-1),
     parameter OUT_WIDTH = (IN_ARRAY_WIDTH/IN_NUM)+CMP_VAL
-    
-    )
-    (
-    input   [IN_ARRAY_WIDTH-1       :   0]  in,
-    output  [OUT_WIDTH-1                :   0]  out
+)(
+    input   [IN_ARRAY_WIDTH-1 : 0]  D_in,
+    output  [OUT_WIDTH-1 : 0]  Q_out
 );
     
     genvar i,j;
-    wire [IN_WIDTH-1        :   0]      in_sep  [IN_NUM-1       :   0];
-    wire [IN_NUM-2          :   0]      gen         [OUT_WIDTH-1    :   0];
+    wire [IN_WIDTH-1 : 0] in_sep  [IN_NUM-1 : 0];
+    wire [IN_NUM-2 : 0] gen [OUT_WIDTH-1 : 0];
     generate 
-        for(i=0;i<IN_NUM; i=i+1      ) begin : lp
-            assign in_sep[i]  = in[(IN_WIDTH*(i+1))-1   : IN_WIDTH*i];
+        for(i=0;i<IN_NUM; i=i+1 ) begin : L_
+            assign in_sep[i] = D_in[(IN_WIDTH*(i+1))-1 : IN_WIDTH*i];
         end
         for (j=0;j<IN_NUM-1;j=j+1)begin : loop1
                 for(i=0;i<OUT_WIDTH; i=i+1  )begin : loop2
@@ -283,749 +130,250 @@ module outport_sum #(
                     end
                 end// for i
             end// for j
-        for(i=0;i<OUT_WIDTH; i=i+1       ) begin : lp2
-            assign out[i]               = |  gen[i];
+        for(i=0;i<OUT_WIDTH; i=i+1 ) begin : lp2
+            assign Q_out[i] = |  gen[i];
         end
     endgenerate
 endmodule
 
-/***********************************
-
-        module bin_to_one_hot 
-        
 
+/***********************************
+*   module bin_to_one_hot 
 ************************************/
-
-
 module bin_to_one_hot #(
-    parameter BIN_WIDTH     =   2,
-    parameter ONE_HOT_WIDTH =   2**BIN_WIDTH
+    parameter BIN_WIDTH = 2,
+    parameter ONE_HOT_WIDTH = 2**BIN_WIDTH
     
-)
-(
-    input   [BIN_WIDTH-1            :   0]  bin_code,
-    output  [ONE_HOT_WIDTH-1        :   0] one_hot_code
- );
-
-    genvar i;
-    generate 
-        for(i=0; i<ONE_HOT_WIDTH; i=i+1) begin :one_hot_gen_loop
-                assign one_hot_code[i] = (bin_code == i[BIN_WIDTH-1         :   0]);
-        end
-    endgenerate
- 
+)(
+    input   [BIN_WIDTH-1 : 0]  bin_code,
+    output reg [ONE_HOT_WIDTH-1 : 0] one_hot_code
+);
+    always @(*) begin
+        one_hot_code = {ONE_HOT_WIDTH{1'b0}};
+        one_hot_code[bin_code] = 1'b1;
+    end
 endmodule
 
 /***********************************
-
-        one_hot_to_binary
-
+*        one_hot_to_binary
 ************************************/
-
-
-
 module one_hot_to_bin #(
-    parameter ONE_HOT_WIDTH =   4,
-    parameter BIN_WIDTH     =  (ONE_HOT_WIDTH>1)? log2(ONE_HOT_WIDTH):1
-)
-(
-    input   [ONE_HOT_WIDTH-1        :   0] one_hot_code,
-    output  [BIN_WIDTH-1            :   0]  bin_code
-
+    parameter ONE_HOT_WIDTH = 4,
+    parameter BIN_WIDTH = (ONE_HOT_WIDTH > 1) ? $clog2(ONE_HOT_WIDTH) : 1
+)(
+    input   [ONE_HOT_WIDTH-1 : 0] one_hot_code,
+    output reg [BIN_WIDTH-1 : 0]  bin_code
 );
-
-  
-    function integer log2;
-      input integer number; begin   
-         log2=(number <=1) ? 1: 0;    
-         while(2**log2<number) begin    
-            log2=log2+1;    
-         end 	   
-      end   
-    endfunction // log2 
-
-localparam MUX_IN_WIDTH =   BIN_WIDTH* ONE_HOT_WIDTH;
-
-wire [MUX_IN_WIDTH-1        :   0]  bin_temp ;
-
-genvar i;
-generate 
-    if(ONE_HOT_WIDTH>1)begin :if1
-        for(i=0; i<ONE_HOT_WIDTH; i=i+1) begin :mux_in_gen_loop
-            assign bin_temp[(i+1)*BIN_WIDTH-1 : i*BIN_WIDTH] =  i[BIN_WIDTH-1:0];
+    integer i;
+    always @(*) begin
+        bin_code = '0;
+        for (i = 0; i < ONE_HOT_WIDTH; i=i+1) begin
+            if (one_hot_code[i]) begin
+                bin_code = BIN_WIDTH'(i); // casting i to BIN_WIDTH
+            end
         end
-
-
-        one_hot_mux #(
-            .IN_WIDTH   (MUX_IN_WIDTH),
-            .SEL_WIDTH  (ONE_HOT_WIDTH)
-            
-        )
-        one_hot_to_bcd_mux
-        (
-            .mux_in     (bin_temp),
-            .mux_out        (bin_code),
-            .sel            (one_hot_code)
-    
-        );
-     end else begin :els
-       // assign  bin_code = one_hot_code;
-       assign  bin_code = 1'b0;
-     end
-
-endgenerate
-
+    end
 endmodule
 
 
-
 /****************************************
-
-            binary_mux
-
+*     binary_mux
 ***************************************/
-
 module binary_mux #(
-        parameter   IN_WIDTH         =   20,
-        parameter   OUT_WIDTH       =   5
-    )
-    (
-        mux_in,
-        mux_out,
-        sel
-
-    );
-    
-  
-    function integer log2;
-      input integer number; begin   
-         log2=(number <=1) ? 1: 0;    
-         while(2**log2<number) begin    
-            log2=log2+1;    
-         end 	   
-      end   
-    endfunction // log2 
-
-     localparam  IN_NUM          =   IN_WIDTH/OUT_WIDTH,
-                 SEL_WIDTH_BIN   = (IN_NUM>1)?  log2(IN_NUM): 1; 
-                 
-                 
-    input   [IN_WIDTH-1         :0] mux_in;
-    output  [OUT_WIDTH-1        :0] mux_out;
-    input   [SEL_WIDTH_BIN-1    :0] sel;                 
+    parameter IN_WIDTH = 20,
+    parameter OUT_WIDTH = 5
+)(
+    mux_in,
+    mux_out,
+    sel
+);
+    localparam  
+        IN_NUM = IN_WIDTH / OUT_WIDTH,
+        SEL_WIDTH_BIN = (IN_NUM > 1) ? $clog2(IN_NUM) : 1; 
+    input   [IN_WIDTH-1 : 0] mux_in;
+    output  [OUT_WIDTH-1 : 0] mux_out;
+    input   [SEL_WIDTH_BIN-1 : 0] sel;                 
     genvar i;
-     
-    
-	generate 
-		if(IN_NUM>1) begin :if1
-			wire [OUT_WIDTH-1       :0] mux_in_2d [IN_NUM -1    :0];
-			for (i=0; i< IN_NUM; i=i+1) begin : loop
-				assign mux_in_2d[i] =mux_in[((i+1)*OUT_WIDTH)-1 :   i*OUT_WIDTH];   
-			end
-			assign mux_out = mux_in_2d[sel];		
-		end else  begin :els
-			assign mux_out = mux_in;			
-		end
-	endgenerate
-    
+    generate 
+        if(IN_NUM > 1) begin 
+            wire [OUT_WIDTH-1 : 0] mux_in_2d [IN_NUM -1 : 0];
+            for (i=0; i< IN_NUM; i=i+1) begin : loop
+                assign mux_in_2d[i] = mux_in[((i+1)*OUT_WIDTH)-1 : i*OUT_WIDTH];   
+            end
+            assign mux_out = mux_in_2d[sel];        
+        end else  begin 
+            assign mux_out = mux_in;            
+        end
+    endgenerate
 endmodule
 
 
-
 module  accumulator #(
     parameter INw= 20,
     parameter OUTw=4,
     parameter NUM =5
-)
-(
+)(
     in_all,
-    out         
+    sum_o         
 );
-
     function integer log2;
-      input integer number; begin   
-         log2=(number <=1) ? 1: 0;    
-         while(2**log2<number) begin    
+    input integer number; begin   
+        log2=(number <=1) ? 1: 0;    
+        while(2**log2<number) begin    
             log2=log2+1;    
-         end       
-      end   
+        end       
+    end   
     endfunction // log2 
     
-    localparam N= INw/NUM,
-               SUMw= log2(NUM)+N; 
-    input [INw-1  :   0] in_all;
-    output[OUTw-1 :   0] out;
-    
-    wire [N-1   :   0] in [NUM-1    :   0];
-    reg [SUMw-1 :   0] sum;
-  
-  
+    localparam 
+        N = INw/NUM,
+        SUMw = log2(NUM)+N; 
+    input [INw-1 : 0] in_all;
+    output[OUTw-1 : 0] sum_o;
+
+    wire [N-1 : 0] D_in [NUM-1 : 0];
+    reg [SUMw-1 : 0] sum;
     genvar i;
     generate 
     for (i=0; i<NUM; i=i+1)begin : lp
-        assign in[i] = in_all[(i+1)*N-1 : i*N];    
+        assign D_in[i] = in_all[(i+1)*N-1 : i*N];
     end
     
-    if(  SUMw ==  OUTw) begin :  equal
-        assign out = sum;
+    if(  SUMw == OUTw) begin : equal
+        assign sum_o = sum;
     end else if(SUMw >  OUTw) begin : bigger
-        assign out = (sum[SUMw-1 : OUTw] > 0 ) ? {OUTw{1'b1}} : sum[OUTw-1  :   0] ;
+        assign sum_o = (sum[SUMw-1 : OUTw] > 0 ) ? {OUTw{1'b1}} : sum[OUTw-1 : 0] ;
     end else begin : less
-          assign out = {{(OUTw-SUMw){1'b0}},  sum} ;
+        assign sum_o = {{(OUTw-SUMw){1'b0}},  sum} ;
     end
-    
-  
-    
     endgenerate
-  
-  // This is supposed to be synyhesized as "sum=in[0]+in[1]+...in[Num-1]"; 
-  // It works with Quartus, Verilator and Modelsim compilers  
+    // This is supposed to be synyhesized as "sum=in[0]+in[1]+...in[Num-1]"; 
+    // It works with Quartus, Verilator and Modelsim compilers  
     integer k; 
     always @(*)begin 
-        sum=0;
+        sum = {SUMw{1'b0}};
         for (k=0;k<NUM;k=k+1)begin 
-             sum= sum + {{(SUMw-N){1'b0}},in[k]};        
-        end   
+            sum= sum + {{(SUMw-N){1'b0}},D_in[k]};
+        end
     end
     //In case your compiler could not synthesize or wrongly synthesizes it try this
     //assumming the maximum NUM as parameter can be 20:
     /*
     generate 
-     wire [N-1   :   0] tmp [19    :   0];
-     for (i=0; i<NUM; i=i+1)begin : lp
+    wire [N-1 : 0] tmp [19 : 0];
+    for (i=0; i<NUM; i=i+1)begin : lp
         assign tmp[i] = in_all[(i+1)*N-1 : i*N];    
-     end
-     for (i=NUM; i<20; i=i+1)begin : lp2
+    end
+    for (i=NUM; i<20; i=i+1)begin : lp2
         assign tmp[i] = {N{1'b0}};    
-     end
+    end
     
     always @(*)begin 
-              sum= tmp[0] + tmp[1]+ tmp[2] + ...+ tmp[19];        
+            sum= tmp[0] + tmp[1]+ tmp[2] + ...+ tmp[19];        
     end
     endgenerate     
     */
-
-endmodule
-
-
-
-/******************************
-
-    set_bits_counter 
-
-*******************************/
-
-
-module set_bits_counter #(
-    parameter IN_WIDTH =120,
-    parameter OUT_WIDTH = log2(IN_WIDTH+1)
-    )
-    (
-    input   [IN_WIDTH-1         :   0]  in,
-    output  [OUT_WIDTH-1        :   0]  out
-    
-);
-  
-    function integer log2;
-      input integer number; begin   
-         log2=(number <=1) ? 1: 0;    
-         while(2**log2<number) begin    
-            log2=log2+1;    
-         end 	   
-      end   
-    endfunction // log2 
-
-    
-    wire    [IN_WIDTH-2     :   0]  addrin2;
-    wire    [OUT_WIDTH-1    :   0]  addrout [IN_WIDTH-2         :   0];
-    wire    [OUT_WIDTH-1    :   0]  addrin1 [IN_WIDTH-1         :   0];
-    
-    
-    assign out          = addrin1 [IN_WIDTH-1];
-    
-    genvar i;
-    //always @(*)begin
-    assign  addrin1[0] = {{(OUT_WIDTH-1){1'b0}},in[0]};
-    generate        
-        for (i=0; i<IN_WIDTH-1; i=i+1) begin : loop
-                assign  addrin1[i+1]  = addrout[i];
-                assign  addrin2[i]    = in[i+1];
-                assign  addrout[i]    = addrin1[i] + addrin2 [i];
-        end
-    endgenerate
-
 endmodule
 
-
-
-
-
-
 /******************************
-
-    check_single_bit_assertation
-
+*    check_single_bit_assertation
 *******************************/
-
-
 module is_onehot0 #(
     parameter IN_WIDTH =2
-    
-    )
-    (
-    input   [IN_WIDTH-1         :   0]  in,
+)(
+    input   [IN_WIDTH-1 : 0]  D_in,
     output  result
-    
-    );
-  
+);
     function integer log2;
-      input integer number; begin   
-         log2=(number <=1) ? 1: 0;    
-         while(2**log2<number) begin    
+    input integer number; begin   
+        log2=(number <=1) ? 1: 0;    
+        while(2**log2<number) begin    
             log2=log2+1;    
-         end 	   
-      end   
+        end        
+    end   
     endfunction // log2 
-
-
     
     localparam OUT_WIDTH = log2(IN_WIDTH+1);
-    
-    wire [OUT_WIDTH-1   :   0]  sum;
-    
+    wire [OUT_WIDTH-1 : 0]  sum;
     
     accumulator #(
         .INw(IN_WIDTH),
         .OUTw(OUT_WIDTH),
         .NUM(IN_WIDTH)
-    )
-    accum
-    (
-        .in_all(in),
-        .out(sum)         
+    ) accum (
+        .in_all(D_in),
+        .sum_o(sum)         
     );
-    
-    
-    /*
-    parallel_counter #(
-        .IN_WIDTH (IN_WIDTH)
-    )counter
-    (
-        .in(in),
-        .out(sum)
-    );
-    */
-    
     assign result = (sum <=1)? 1'b1: 1'b0;
-    
-    
 endmodule
 
 /**********************************
-
-fast_minimum_number
-
+*fast_minimum_number
 ***********************************/
-
-
 module fast_minimum_number#(
-    parameter NUM_OF_INPUTS     =   8,
-    parameter DATA_WIDTH            =   5,
-    parameter IN_ARRAY_WIDTH    =   NUM_OF_INPUTS   * DATA_WIDTH
-)
-(
-    input  [IN_ARRAY_WIDTH-1            :   0] in_array,
-    output [NUM_OF_INPUTS-1             :   0]  min_out
+    parameter NUM_OF_INPUTS = 8,
+    parameter DATA_WIDTH = 5,
+    parameter IN_ARRAY_WIDTH = NUM_OF_INPUTS   * DATA_WIDTH
+)(
+    input  [IN_ARRAY_WIDTH-1 : 0] in_array,
+    output [NUM_OF_INPUTS-1 : 0]  min_out
 );
 
     genvar i,j;
-    wire [DATA_WIDTH-1                  :   0]  numbers             [NUM_OF_INPUTS-1            :0];    
-    wire [NUM_OF_INPUTS-2               :   0]  comp_array          [NUM_OF_INPUTS-1            :0];    
-        
+    wire [DATA_WIDTH-1 : 0]  numbers             [NUM_OF_INPUTS-1 : 0];    
+    wire [NUM_OF_INPUTS-2 : 0]  comp_array          [NUM_OF_INPUTS-1 : 0];    
+    
     generate
     if(NUM_OF_INPUTS==1)begin:if1
         assign min_out = 1'b1;
     end
     else begin : els//(vc num >1)
         for(i=0; i<NUM_OF_INPUTS;  i=i+1) begin : loop_i
-                assign numbers[i]   = in_array  [(i+1)* DATA_WIDTH-1: i*DATA_WIDTH];
+                assign numbers[i] = in_array  [(i+1)* DATA_WIDTH-1: i*DATA_WIDTH];
                 for(j=0; j<NUM_OF_INPUTS-1;  j=j+1) begin : loop_j
                             if(i>j) begin :if1 assign comp_array [i][j] = ~ comp_array [j][i-1]; end
                             else   begin :els     assign comp_array [i]   [j] = numbers[i]<= numbers[j+1]; end
                 end//for j
-                assign min_out[i]=  & comp_array[i];
+                assign min_out[i]= & comp_array[i];
         end//for i
     end//else
     endgenerate
-    
-endmodule
-
-
-
-
-
-/********************************************
-
-        Carry-based reduction parallel counter
-
-
-********************************************/
-module parallel_counter  #(
-    parameter IN_WIDTH =120 // max 127
-)
-(
-    in,
-    out    
-);
-    
-    
-   
-    function integer log2;
-      input integer number; begin   
-         log2=(number <=1) ? 1: 0;    
-         while(2**log2<number) begin    
-            log2=log2+1;    
-         end 	   
-      end   
-    endfunction // log2 
-    
-  localparam OUT_WIDTH = log2(IN_WIDTH+1);
-  localparam PCIw      = (IN_WIDTH < 8   )? 7    :
-                         (IN_WIDTH < 16  )? 15   :
-                         (IN_WIDTH < 31  )? 31   :
-                         (IN_WIDTH < 36  )? 63   :   127;
-                         
-                         
-   localparam PCOw      = (IN_WIDTH < 8  )? 3   :
-                         (IN_WIDTH < 16  )? 4   :
-                         (IN_WIDTH < 31  )? 5   :
-                         (IN_WIDTH < 36  )? 6   :   7;                         
-  
-input   [IN_WIDTH-1         :   0]  in;
-output  [OUT_WIDTH-1        :   0]  out;
-     
-wire [PCIw-1    :   0]  pc_in;
-wire [PCOw-1    :   0]  pc_out;
-
-generate 
-    if(PCIw > IN_WIDTH ) begin :w1
-        assign   pc_in = {{(PCIw-IN_WIDTH){1'b0}},in};
-    end else begin:els
-         assign   pc_in=in;
-    end // if 
-    
-    if(PCIw == 7) begin :w7
-       
-        PC_7_3   pc (
-            .in(pc_in),
-            .out(pc_out)
-        );
-    
-    end else if(PCIw == 15) begin :w15
-          PC_15_4   pc (
-            .in(pc_in),
-            .out(pc_out)
-           );
-    
-    end else if(PCIw == 31) begin :w31
-        PC_31_5   pc (
-            .in(pc_in),
-            .out(pc_out)
-        );   
-    end else if(PCIw == 63) begin :w63
-         PC_63_6   pc (
-            .in(pc_in),
-            .out(pc_out)
-        );   
-    
-    end else  begin :w127
-         PC_127_7 pc (
-            .in(pc_in),
-            .out(pc_out)
-        );   
-    end
-    
- endgenerate
- 
- assign out = pc_out[OUT_WIDTH-1    :   0];
- 
-endmodule
-
-
-
-//carry-sum generation blocks
-module CS_GEN (
-    in,
-    abc,
-    s
-);
-    input   [6  :   0] in;
-    output  s;
-    output  [2  :   0] abc;
-    
-    wire      a,b,c,s;
-    wire    [3  :   0] in1;
-    wire    [2  :   0] in2;
-    wire    [2  :   0] j1;
-    wire    [1  :   0] j2;
-    
-    assign {in2,in1} =  in;
-/* verilator lint_off WIDTH */
-    assign j1= in1[3]+in1[2]+in1[1]+in1[0];
-    assign j2= in2[2]+in2[1]+in2[0];
-/* verilator lint_on WIDTH */
-    
-    //s is asserted when both in1 and in2 have odd number of ones.
-    assign s    = j1[0] ^ j2[0];
-    // a is asserted when there are at least two ones in in1 (i.e., j1 >= 2);
-    assign  a   =   (j1 >   3'd1);
-    
-    //b is asserted when there are at least two ones in in2 (i.e., j2 >= 2);
-    assign  b   =   (j2 >   2'd1);
-    
-    // C is asserted when when j1 equals 4 or when  s is asserted
-    assign c    =   (j1==4) | (j1[0] & j2[0]);
-
-    assign abc = {a,b,c};
-endmodule
-
-/*************************
- 
- (7,3) parallel counter
- 
-*************************/
-
-module PC_7_3 (
-    in,
-    out
-
-);
-    input   [6    : 0]  in;
-    output  [2    : 0]  out;
-    
-    wire    [2    : 0] abc;
-   
-    CS_GEN cs(
-        .in(in),
-        .abc(abc),
-        .s(out[0])
-    );
-   
-    assign out[2:1] = abc[2]+abc[1]+abc[0];  
-    
-  
-
-
 endmodule
 
-/*************************
-
-    (15,4) parallel counter
-    
-*************************/
-
-module PC_15_4 (
-    in,
-    out
-
-);
-    input   [14   : 0]  in;
-    output  [3    : 0]  out;
-    
-    wire    [2:0]   abc0,abc1;
-    wire            s0,s1,b2;
-   
-    CS_GEN cs0(
-        .in     (in  [6  :   0]),
-        .abc    (abc0),
-        .s      (s0)
-    );
-    
-     CS_GEN cs1(
-        .in     (in  [13  :   7]),
-        .abc    (abc1),
-        .s      (s1)
-    );
-    
-    assign {b2,out[0]}  =in  [14] + s0 +s1;
-    
-    PC_7_3 pc_sub(
-        .in({abc0,abc1,b2}),
-        .out(out[3:1])
-    );  
-    
-  
-
-
-endmodule
-
-
-// (31,5) parallel counter
-module PC_31_5 (
-    in,
-    out
-
-);
-    localparam CS_NUM   =   5;
-    
-    input   [30         : 0]  in;
-    output  [4          : 0]  out;
-    
-   
-    wire    [CS_NUM-1   : 0]   s;
-    wire    [(CS_NUM*7)-1   :   0]  cs_in;
-    wire    [14         :   0]  pc_15_in;
-    
-    assign cs_in ={s[3:0] ,in };
-    
-    genvar i;
-    generate 
-    for (i=0;i<CS_NUM;i=i+1) begin: lp    
-        CS_GEN cs(
-            .in     (cs_in     [(i+1)*7-1  :  i*7]),
-            .abc    (pc_15_in  [(i+1)*3-1  :  i*3]),
-            .s      (s      [i])
-        );
-        
-    end//for
-    endgenerate
-    
-    PC_15_4 pc_15(
-        .in    (pc_15_in ),
-        .out   (out[4:1])
-    );
-    
-    assign out[0] = s[4];
-    
- endmodule
-
-/*************************
- 
- (63,6) parallel counter
- 
-**************************/
-
-module PC_63_6 (
-    in,
-    out
-
-);
-    localparam CS_NUM   =   10;
-    
-    input   [62         : 0]  in;
-    output  [5          : 0]  out;
-    
-   
-    wire    [CS_NUM-1   : 0]   s;
-    wire    [(CS_NUM*7)-1   :   0]  cs_in;
-    wire    [30         : 0]  pc_31_in;
-    
-    assign cs_in ={s[7:0] ,in };
-    
-    genvar i;
-    generate 
-    for (i=0;i<CS_NUM;i=i+1) begin:lp    
-        CS_GEN cs(
-            .in     (cs_in     [(i+1)*7-1  :  i*7]),
-            .abc    (pc_31_in  [(i+1)*3-1  :  i*3]),
-            .s      (s      [i])
-        );
-        
-    end//for
-    endgenerate
-    
-    assign {pc_31_in[30],out[0]}    =   s[7]+s[8]+s[9];
-         
-    PC_31_5 pc_31(
-        .in(pc_31_in ),
-        .out(out[5:1])
-    );
- endmodule
-
-/*************************
-
- (127,7) parallel counter
-
-*************************/
-
-module PC_127_7 (
-    in,
-    out
-
-);
-    localparam CS_NUM   =   21;
-    
-    input   [126        : 0]  in;
-    output  [6          : 0]  out;
-    
-   
-    wire    [CS_NUM-1       : 0]   s;
-    wire    [(CS_NUM*7)-1   : 0]  cs_in;//147
-    wire    [62             : 0]  pc_63_in;
-    
-    assign cs_in ={s[19:0] ,in };
-    
-    genvar i;
-    generate 
-    for (i=0;i<CS_NUM;i=i+1) begin :lp   
-        CS_GEN cs(
-            .in     (cs_in     [(i+1)*7-1  :  i*7]),
-            .abc    (pc_63_in  [(i+1)*3-1  :  i*3]),
-            .s      (s      [i])
-        );
-        
-    end//for
-    endgenerate
-    
-    assign {out[0]}    =   s[20];
-         
-    PC_63_6 pc63(
-        .in(pc_63_in),
-        .out(out[6:1])
-    );
-   
-    
- endmodule
 
 
 module start_delay_gen #(
-    parameter NC     =    64 //number of cores
-
+    parameter NC = 64 //number of cores
 )(
     clk,
     reset,
     start_i,
     start_o
 );
-
     input reset,clk,start_i;
-    output [NC-1    :    0] start_o;
+    output [NC-1 : 0] start_o;
     reg start_i_reg;
     wire start;
     wire cnt_increase;
-    reg  [NC-1    :    0] start_o_next;
-    reg [NC-1    :    0] start_o_reg;
+    reg [NC-1 : 0] start_o_next;
+    reg [NC-1 : 0] start_o_reg;
     
     assign start= start_i_reg|start_i;
-
-generate 
-if(NC > 2) begin :l1
-    always @(*)begin 
-        if(NC[0]==1'b0)begin // odd
-            start_o_next={start_o[NC-3:0],start_o[NC-2],start};
-        end else begin //even
-            start_o_next={start_o[NC-3:0],start_o[NC-1],start};
-        
-        end    
+    generate 
+    if(NC > 2) begin :l1
+        always @(*)begin 
+            if(NC[0]==1'b0)begin // odd
+                start_o_next={start_o[NC-3: 0],start_o[NC-2],start};
+            end else begin //even
+                start_o_next={start_o[NC-3: 0],start_o[NC-1],start};
+            end    
+        end
+    end else begin :l2
+        always @(*) start_o_next = {NC{start}}; 
     end
- end
-else begin :l2
-	 always @(*) start_o_next = {NC{start}}; 
-end
-
-endgenerate
-   
-    reg [2:0] counter;
+    endgenerate
+    
+    reg [2: 0] counter;
     assign cnt_increase=(counter==3'd0);
     always @ (`pronoc_clk_reset_edge )begin 
         if(`pronoc_reset)  begin             
@@ -1037,12 +385,8 @@ endgenerate
             start_i_reg <= start_i;
             if(cnt_increase | start) start_o_reg <= start_o_next;
             
-
         end//reset
     end //always
-
     assign start_o=(cnt_increase | start)? start_o_reg : {NC{1'b0}};
-
 endmodule
-
-`endif
+`endif
\ No newline at end of file
diff --git a/mpsoc/rtl/pronoc_def.v b/mpsoc/rtl/pronoc_def.v
index 0b344ff..35b8817 100644
--- a/mpsoc/rtl/pronoc_def.v
+++ b/mpsoc/rtl/pronoc_def.v
@@ -1,74 +1,80 @@
 `ifndef PRONOC_DEF
 `define PRONOC_DEF
-
-    `timescale      1ns/1ps
-
-   //`define SYNC_RESET_MODE       /* Reset is asynchronous by default. Uncomment this line for having synchronous reset*/
-   //`define ACTIVE_LOW_RESET_MODE /* Reset is active high by deafult. Uncomment this line for having active low reset*/
-
-    
-  `define IMPORT_PRONOC_PCK   
-  								 /* pronoc.sv is imported by default. Inorder to support Multiple physical NoCs with different 
-                                  you need to compile each NoC as a separate library (passing USE_LIB in compilationtime).
-                                  Comment IMPORT_PRONOC_PCK macro to include pronoc_pck.sv as a file instead of importing.
-                                  Including pronoc.sv allows having Multiple physical NoCs with different configurations 
-                                  where configuration can be set via parameter redefinition at NoC_Top module  */
-   
-   
-
-   `ifdef SYNC_RESET_MODE 
-         `define pronoc_clk_reset_edge  posedge clk
-   `else 
-      `ifdef ACTIVE_LOW_RESET_MODE 
-             `define pronoc_clk_reset_edge  posedge clk or negedge reset
-      `else 
-         `define pronoc_clk_reset_edge  posedge clk or posedge reset      
-      `endif  
-   `endif   
-      
-
-
-
-   `ifdef ACTIVE_LOW_RESET_MODE 
-             `define pronoc_reset !reset
-      `else 
-         `define pronoc_reset  reset
-   `endif  
-
-
-
+    
+    // Reset Configurations
+    `define SYNC_RESET_MODE
+    /*
+     *  Reset is synchronous by default.
+     *  comment this line to enable synchronous reset.
+     */
+    
+    // `define ACTIVE_LOW_RESET_MODE
+    /*
+     *  Reset is active-high by default.
+     *  Uncomment this line to enable an active-low reset.
+     */
+    
+    /******************
+     * Define SIMULATION for supported RTL simulators
+     *******************/
+    
+    `ifdef VERILATOR
+        `define SIMULATION
+    `endif
+    
+    `ifdef MODEL_TECH  // ModelSim/Questa
+        `define SIMULATION  
+    `endif  
+    
+    `ifdef VCS  // Synopsys VCS
+        `define SIMULATION
+    `endif  
+    
+    `ifdef XCELIUM  // Cadence Xcelium
+        `define SIMULATION
+    `endif
+    
+    `ifdef RIVIERA  // Aldec Riviera-PRO
+        `define SIMULATION
+    `endif
+    
+    `ifdef SIMULATION
+        `timescale 1ns/1ps
+    `endif
+    
+    /****************
+     * Enable TRACE Dump
+     ****************/
+    
+    `ifdef SIMULATION
+        // Uncomment the following defines to enable TRACE dumping  
+        // `define TRACE_DUMP_PER_NoC        // Dump all in/out traces of the NoC into a single file  
+        // `define TRACE_DUMP_PER_ROUTER     // Dump in/out traces of each router into a separate file  
+        // `define TRACE_DUMP_PER_PORT       // Dump in/out traces of each router port into a separate file  
+    `endif
+    
+    // Clock and Reset Edge Definitions
+    `ifdef SYNC_RESET_MODE
+        `define pronoc_clk_reset_edge posedge clk
+    `else
+        `ifdef ACTIVE_LOW_RESET_MODE
+            `define pronoc_clk_reset_edge posedge clk or negedge reset
+        `else
+            `define pronoc_clk_reset_edge posedge clk or posedge reset
+        `endif
+    `endif
+    
+    // Reset Signal Definition
+    `ifdef ACTIVE_LOW_RESET_MODE
+        `define pronoc_reset !reset
+    `else
+        `define pronoc_reset reset
+    `endif
+    
+    // Library Usage
     `ifdef USE_LIB
-         `uselib lib=`USE_LIB    
+        `uselib lib=`USE_LIB
     `endif
     
-
-   
-   `ifdef IMPORT_PRONOC_PCK
-      `define NOC_CONF  import pronoc_pkg::*;  
-      `define PRONOC_PKG  
-   `else
-      `define NOC_CONF  `define PRONOC_PKG \
-                        `include "pronoc_pkg.sv" 
-   `endif
-   
-   
-   
-   
-
-
-/****************
-   TRACE dump 
-*****************/    
-   //uncomment following define to enable TRACE dumping
-   
-   
-   // `define TRACE_DUMP_PER_NoC       // dump all in/out traces to the NoC in single file
-   // `define TRACE_DUMP_PER_ROUTER       // dump each router in/out traces in a seprate file
-  // `define TRACE_DUMP_PER_PORT       // dump each router port in/out in a single file
- 
-
-
-
-
-`endif
-
+    
+`endif // PRONOC_DEF
diff --git a/mpsoc/rtl/src_ambachi/chi_wrapper.sv b/mpsoc/rtl/src_ambachi/chi_wrapper.sv
new file mode 100644
index 0000000..085a4ac
--- /dev/null
+++ b/mpsoc/rtl/src_ambachi/chi_wrapper.sv
@@ -0,0 +1,354 @@
+`include "pronoc_def.v"
+
+/**************************************
+* Module: chi_wrapper
+* Date:2019-05-03
+* Author: alireza
+*
+* Description: 
+***************************************/
+
+
+module chi_to_pronoc_wrapper (
+    chi_flit_i,
+    chi_flitpend_i,
+    chi_flitv_i,
+    chi_lcrdv_i,
+    current_r_addr_i,
+    pronoc_chan_out,
+    clk,
+    reset
+);
+    import pronoc_pkg::*;
+    import amba_5_chi_pkg::*;
+    
+    input chi_flitpend_i, chi_flitv_i, chi_lcrdv_i, clk,reset;  
+    input [Fpay-1 : 0]  chi_flit_i;
+    input [RAw-1 : 0] current_r_addr_i;
+    output smartflit_chanel_t pronoc_chan_out;
+    
+    wire [QOS_REQ-1 : 0] qos;
+    wire [TGTID_REQ-1 : 0] target_id;
+    wire [SRCID_REQ-1 : 0] src_id;
+    wire [Fpay-QOS_REQ-TGTID_REQ-SRCID_REQ-1 : 0] rest_flit;
+    assign {qos,target_id,src_id,rest_flit} = chi_flit_i;    
+    
+    wire [ EAw-1 : 0] dest_e_addr;// = target_id[ EAw-1 : 0];//TODO need to check how they code the destiation adreeses
+    wire [ EAw-1 : 0] src_e_addr;// = src_id[ EAw-1 : 0];//TODO need to check how they code the source adreeses
+    wire [DSTPw-1: 0] destport;   
+    wire [Fw-1 : 0] pronoc_hdr_flit;
+    
+    endp_addr_encoder des_addr_encoder (
+        .id_in(target_id[NEw-1:0]),
+        .code_out(dest_e_addr)
+    );
+    
+    endp_addr_encoder src_addr_encoder (
+        .id_in(src_id[NEw-1:0]),
+        .code_out(src_e_addr)
+    );
+    
+    generate 
+    if((CAST_TYPE == "UNICAST") && (IS_LOOKAHEAD==1'b1)) begin : uni
+    //The router is configured with lookaheadrouting. 
+    //The header flit is supposed to carry the destinaion output port
+        conventional_routing #(
+            .LOCATED_IN_NI(1)
+        ) route_compute (
+            .reset(1'b0), //only needed for fattree
+            .clk(1'b0), // only needed for fattree
+            .current_r_addr(current_r_addr_i),
+            .dest_e_addr(dest_e_addr),
+            .src_e_addr(src_e_addr),
+            .destport(destport)
+        );
+    end
+    endgenerate 
+    localparam [WEIGHTw-1 : 0] WINIT = 1;
+    
+    header_flit_generator #(
+        .DATA_w(Fpay)
+    ) hdr_flit_gen (
+        .flit_out(pronoc_hdr_flit),
+        .class_in(1'b0),
+        .dest_e_addr_in(dest_e_addr),
+        .src_e_addr_in(src_e_addr),
+        .destport_in(destport),
+        .vc_num_in(1'b0),
+        .weight_in(WINIT),
+        .data_in(chi_flit_i),
+        .be_in(1'b0)
+    );
+    
+    assign  pronoc_chan_out.flit_chanel.flit_wr = chi_flitv_i;
+    assign  pronoc_chan_out.flit_chanel.credit = chi_lcrdv_i;
+    assign  pronoc_chan_out.flit_chanel.flit.hdr_flag = 1'b1;
+    assign  pronoc_chan_out.flit_chanel.flit.tail_flag = 1'b1;
+    assign  pronoc_chan_out.flit_chanel.flit.vc = 1'b1;
+    assign  pronoc_chan_out.flit_chanel.flit.payload = pronoc_hdr_flit[FPAYw-1 : 0];
+    //credit release should be asserted externaly via register. For simulation we just use a counter to set it few cycles after reset
+    reg [3:0] counter;
+    always @(posedge clk or posedge reset)begin 
+        if(reset)  counter<=0;
+        else if(counter<4) counter<=counter+1'b1;
+    end
+    
+    wire credit_release = counter==4;
+    genvar i;
+    generate
+    for (i=0; i<V;i++) begin :V_
+        assign pronoc_chan_out.ctrl_chanel.credit_init_val[i]= 0;
+        assign pronoc_chan_out.ctrl_chanel.credit_release_en[i]= credit_release;
+    end
+    endgenerate
+    
+    `ifdef SIMULATION
+    always @(posedge clk) begin 
+        if((dest_e_addr == src_e_addr ) & chi_flitv_i ) begin 
+            $display("%t:Error: The src and destination address of injected packet is the same in core (%d) %m",$time,src_id);
+            $stop;
+        end
+    end
+    `endif
+endmodule
+
+
+//snoop chanel doesnot have target id. our home node does not support broad casting so we need to add target id from home node  
+module  snp_chi_to_pronoc_wrapper (
+    chi_flit_i,
+    chi_flitpend_i,
+    chi_flitv_i,
+    chi_lcrdv_i,
+    snp_target_id,
+    current_r_addr_i,
+    pronoc_chan_out,
+    clk,
+    reset
+);
+    import pronoc_pkg::*;
+    import amba_5_chi_pkg::*;
+    
+    input chi_flitpend_i, chi_flitv_i, chi_lcrdv_i, clk, reset;  
+    input [Fpay-1 : 0]  chi_flit_i;
+    input [RAw-1 : 0] current_r_addr_i;
+    input [TGTID_DAT-1 : 0] snp_target_id;
+    output smartflit_chanel_t pronoc_chan_out;
+    
+    wire [QOS_SNP-1 : 0] qos;
+    wire [TGTID_REQ-1 : 0] target_id =  snp_target_id;
+    wire [SRCID_SNP-1 : 0] src_id;
+    wire [Fpay-QOS_SNP-SRCID_SNP-1 : 0] rest_flit;
+    assign {qos,src_id,rest_flit} = chi_flit_i;
+    
+    wire [ EAw-1 : 0] dest_e_addr;
+    wire [ EAw-1 : 0] src_e_addr;// = src_id[ EAw-1 : 0];//TODO need to check how they code the source adreeses
+    wire [DSTPw-1: 0] destport;
+    wire [Fw-1 : 0] pronoc_hdr_flit;
+    
+    endp_addr_encoder  des_addr_encoder  (
+        .id_in(target_id[NEw-1:0]),
+        .code_out(dest_e_addr)
+    );
+    
+    endp_addr_encoder src_addr_encoder (
+        .id_in(src_id[NEw-1:0]),
+        .code_out(src_e_addr)
+    );
+    generate 
+    if((CAST_TYPE == "UNICAST") && (IS_LOOKAHEAD==1'b1)) begin : uni
+    //The router is configured with lookaheadrouting. 
+    //The header flit is supposed to carry the destinaion output port
+        conventional_routing #(
+            .LOCATED_IN_NI(1)
+        ) route_compute (
+            .reset(1'b0), //only needed for fattree
+            .clk(1'b0), // only needed for fattree
+            .current_r_addr(current_r_addr_i),
+            .dest_e_addr(dest_e_addr),
+            .src_e_addr(src_e_addr),
+            .destport(destport)
+        );
+    end
+    endgenerate
+    localparam [WEIGHTw-1 : 0] WINIT = 1;
+    
+    header_flit_generator #(
+        .DATA_w(Fpay)
+    ) hdr_flit_gen (
+        .flit_out(pronoc_hdr_flit),
+        .class_in(1'b0),
+        .dest_e_addr_in(dest_e_addr),
+        .src_e_addr_in(src_e_addr),
+        .destport_in(destport),
+        .vc_num_in(1'b0),
+        .weight_in(WINIT),
+        .data_in(chi_flit_i),
+        .be_in(1'b0)
+    );
+    
+    assign  pronoc_chan_out.flit_chanel.flit_wr  = chi_flitv_i;
+    assign  pronoc_chan_out.flit_chanel.credit   = chi_lcrdv_i;
+    assign  pronoc_chan_out.flit_chanel.flit.hdr_flag = 1'b1;
+    assign  pronoc_chan_out.flit_chanel.flit.tail_flag= 1'b1;
+    assign  pronoc_chan_out.flit_chanel.flit.vc= 1'b1;
+    assign  pronoc_chan_out.flit_chanel.flit.payload= pronoc_hdr_flit[FPAYw-1 : 0];    
+    //credit release should be asserted externaly via register. For simulation we just use a counter to set it few cycles after reset
+    reg [3:0] counter;
+    always @(posedge clk or posedge reset)begin 
+        if(reset)  counter<=0;
+        else if(counter<4) counter<=counter+1'b1;
+    end
+    wire credit_release = counter==4;
+    
+    genvar i;
+    generate
+    for (i=0; i<V;i++) begin :V_
+        assign pronoc_chan_out.ctrl_chanel.credit_init_val[i]= 0;
+        assign pronoc_chan_out.ctrl_chanel.credit_release_en[i]= credit_release;
+    end
+    endgenerate
+    
+    `ifdef SIMULATION
+    always @(posedge clk) begin 
+        if((dest_e_addr == src_e_addr ) & chi_flitv_i ) begin 
+            $display("%t:Error: The src and destination address of injected packet is the same in core (%d) %m",$time,src_id);
+            $stop;
+        end
+    end
+    `endif
+endmodule
+
+
+module pronoc_to_chi_wrapper (
+    pronoc_chan_in,
+    chi_flit_o,
+    chi_flitpend_o,
+    chi_flitv_o,
+    chi_lcrdv_o
+);
+    import pronoc_pkg::*; 
+    input smartflit_chanel_t pronoc_chan_in;
+    output [Fpay-1 : 0]  chi_flit_o;
+    output  chi_flitpend_o,   chi_flitv_o, chi_lcrdv_o;
+    
+    assign chi_flitv_o = pronoc_chan_in.flit_chanel.flit_wr;
+    assign chi_lcrdv_o = pronoc_chan_in.flit_chanel.credit; 
+    assign chi_flitpend_o = 1'b1;
+    
+    header_flit_info #(
+        .DATA_w(Fpay)
+    )extr(
+        .flit(pronoc_chan_in.flit_chanel.flit),
+        .hdr_flit(),
+        .data_o(chi_flit_o)
+    );
+endmodule
+
+
+
+module  chi_noc (
+    reset,
+    clk,
+    /*--------- Interface with NoC ---------------------------------*/    
+    //TX // snoop tx home node
+    // wire   [TGTID_REQ-1 : 0] chi_noc_tx__target_id_all ; // we are not supporting braod casting on snoop chanel so need target ID
+    chi_noc_txflitpend_all, 
+    chi_noc_txflitv_all,
+    chi_noc_txflit_all,
+    noc_chi_txlcrdv_all,
+    
+    // /RX
+    noc_chi_rxflitpend_all,
+    noc_chi_rxflitv_all,
+    noc_chi_rxflit_all,
+    chi_noc_rxlcrdv_all,
+    
+    snp_target_id_all //only needed for snp
+    );
+    
+    import pronoc_pkg::*;
+    import amba_5_chi_pkg::*;
+    
+    // Clock and Reset
+    input clk,reset;
+    input [TGTID_DAT * NE-1 : 0]  snp_target_id_all;
+    
+    
+    /*--------- Interface with NoC ---------------------------------*/
+    // RX
+    output   [NE-1 : 0] noc_chi_rxflitpend_all ;
+    output   [NE-1 : 0] noc_chi_rxflitv_all ;
+    output   [Fpay*NE-1:0]  noc_chi_rxflit_all ;
+    input  [NE-1 : 0] chi_noc_rxlcrdv_all ;
+    
+    //TX 
+    input   [NE-1 : 0] chi_noc_txflitpend_all ;
+    input   [NE-1 : 0] chi_noc_txflitv_all ;
+    input   [Fpay*NE-1:0]    chi_noc_txflit_all ;
+    output  [NE-1 : 0] noc_chi_txlcrdv_all ;
+    
+    wire  [Fpay-1:0]    noc_chi_rxflit [NE-1 : 0];
+    wire  [Fpay-1:0]    chi_noc_txflit [NE-1 : 0]; 
+    wire  [TGTID_DAT-1  :0]   snp_target_id [NE-1 : 0];
+
+    /*----------------------------------------------------------------------------*/
+    /*ProNoC interface */
+    /*----------------------------------------------------------------------------*/
+    //local ports 
+    smartflit_chanel_t pronoc_chan_in  [NE-1 : 0];
+    smartflit_chanel_t pronoc_chan_out [NE-1 : 0];
+    noc_top the_noc (
+        .reset(reset),
+        .clk(clk),
+        .chan_in_all (pronoc_chan_in),
+        .chan_out_all(pronoc_chan_out)
+    );
+    
+    genvar i;
+    generate 
+    for(i=0;i<NE;i=i+1)begin :ne
+     //connected router encoded address
+        localparam CURRENTR=  i/T3;
+        localparam CURRENTX=  CURRENTR%T1;
+        localparam CURRENTY=  CURRENTR/T1;
+        localparam [RAw-1 : 0] CURRENT_ADDR =  (CURRENTY<<NXw) + CURRENTX; 
+        
+        assign snp_target_id [i] = snp_target_id_all[(i+1)* TGTID_DAT-1 : i* TGTID_DAT];
+        assign chi_noc_txflit[i] = chi_noc_txflit_all[(i+1)*Fpay-1 : i*Fpay];
+        assign noc_chi_rxflit_all [(i+1)*Fpay-1 : i*Fpay] = noc_chi_rxflit[i];  
+        
+        if(NOC_ID == "snp") begin : _snp
+            snp_chi_to_pronoc_wrapper chi_to_pronoc (
+                .chi_flitpend_i(chi_noc_txflitpend_all[i]),
+                .chi_flitv_i(chi_noc_txflitv_all[i]),
+                .chi_lcrdv_i(chi_noc_rxlcrdv_all[i]),
+                .chi_flit_i(chi_noc_txflit[i]),
+                .snp_target_id(snp_target_id[i]),//comes from home nodes
+                .current_r_addr_i(CURRENT_ADDR),
+                .pronoc_chan_out(pronoc_chan_in[i]),
+                .clk(clk),
+                .reset(reset)
+            );
+        end else begin 
+            chi_to_pronoc_wrapper chi_to_pronoc (
+                .chi_flitpend_i(chi_noc_txflitpend_all[i]),
+                .chi_flitv_i(chi_noc_txflitv_all[i]),
+                .chi_lcrdv_i(chi_noc_rxlcrdv_all[i]),
+                .chi_flit_i(chi_noc_txflit[i]),
+                .current_r_addr_i(CURRENT_ADDR),
+                .pronoc_chan_out(pronoc_chan_in[i]),
+                .clk(clk),
+                .reset(reset)
+            );
+        end
+        pronoc_to_chi_wrapper pronoc_to_chi (
+            .chi_flit_o(noc_chi_rxflit[i]),
+            .chi_flitpend_o(noc_chi_rxflitpend_all[i]),
+            .chi_flitv_o(noc_chi_rxflitv_all[i]),
+            .chi_lcrdv_o(noc_chi_txlcrdv_all[i]),
+            .pronoc_chan_in(pronoc_chan_out[i])
+        );
+    end
+    endgenerate
+endmodule
+
diff --git a/mpsoc/rtl/src_ambachi/noc_localparam.v b/mpsoc/rtl/src_ambachi/noc_localparam.v
new file mode 100644
index 0000000..0a413eb
--- /dev/null
+++ b/mpsoc/rtl/src_ambachi/noc_localparam.v
@@ -0,0 +1,79 @@
+
+/**************************************************************************
+**    WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT ARE LIKELY TO BE
+**    OVERWRITTEN AND LOST. Rename this file if you wish to do any modification.
+****************************************************************************/
+
+
+/**********************************************************************
+**    File: noc_localparam.v
+**    
+**    Copyright (C) 2014-2019  Alireza Monemi
+**    
+**    This file is part of ProNoC 1.9.1 
+**
+**    ProNoC ( stands for Prototype Network-on-chip)  is free software: 
+**    you can redistribute it and/or modify it under the terms of the GNU
+**    Lesser General Public License as published by the Free Software Foundation,
+**    either version 2 of the License, or (at your option) any later version.
+**
+**     ProNoC is distributed in the hope that it will be useful, but WITHOUT
+**     ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+**     or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
+**     Public License for more details.
+**
+**     You should have received a copy of the GNU Lesser General Public
+**     License along with ProNoC. If not, see <http:**www.gnu.org/licenses/>.
+******************************************************************************/ 
+
+`ifdef   NOC_LOCAL_PARAM 
+//TODO: replace it with package
+    
+    import amba_5_chi_pkg::*;
+    `include "pronoc_conf.svh"
+    
+    
+    //NoC parameters
+    localparam NOC_ID=0;
+    localparam V=1;
+    localparam LB=B;
+    localparam ROUTE_MODE="LOOKAHEAD";
+    localparam PCK_TYPE="SINGLE_FLIT";
+    localparam MIN_PCK_SIZE=1;
+    localparam BYTE_EN=0;
+    localparam SSA_EN="NO";
+    localparam SMART_MAX=0;
+    localparam CONGESTION_INDEX=3;
+    localparam ESCAP_VC_MASK=1;
+    localparam VC_REALLOCATION_TYPE="NONATOMIC";
+    localparam COMBINATION_TYPE="COMB_NONSPEC";
+    localparam MUX_TYPE="BINARY";
+    localparam C=1;
+    localparam ADD_PIPREG_AFTER_CROSSBAR=1'b0;
+    localparam FIRST_ARBITER_EXT_P_EN=1;
+    localparam SWA_ARBITER_TYPE="RRA";
+    localparam WEIGHTw=4;
+    localparam SELF_LOOP_EN="NO";
+    localparam AVC_ATOMIC_EN=0;
+    localparam CVw=(C==0)? V : C * V;
+    localparam CLASS_SETTING={CVw{1'b1}};
+    localparam CAST_TYPE = "UNICAST";
+    localparam MCAST_ENDP_LIST = 'b11110011;
+    localparam HETERO_VC=0;
+    localparam DEBUG_EN=1;
+    
+    //simulation parameter
+    //localparam MAX_RATIO = 1000;
+    localparam MAX_PCK_NUM = 1000000000;
+    localparam MAX_PCK_SIZ = 16383; 
+    localparam MAX_SIM_CLKs=  1000000000;
+    localparam TIMSTMP_FIFO_NUM = 16;
+    localparam MAX_ROUTER=1;
+    localparam MAX_PORT=1;
+    localparam int VC_CONFIG_TABLE [MAX_ROUTER][MAX_PORT]='{'{0}};
+    
+    localparam Fpay =
+        (NOC_ID =="dat")? DAT_FLIT_SIZE :
+        (NOC_ID =="req")? REQ_FLIT_SIZE :
+        (NOC_ID =="rsp")? RSP_FLIT_SIZE : SNP_FLIT_SIZE;
+`endif
diff --git a/mpsoc/rtl/src_emulate/rtl/noc_emulator.sv b/mpsoc/rtl/src_emulate/rtl/noc_emulator.sv
index 133583e..3a295ed 100644
--- a/mpsoc/rtl/src_emulate/rtl/noc_emulator.sv
+++ b/mpsoc/rtl/src_emulate/rtl/noc_emulator.sv
@@ -1,18 +1,18 @@
+`include "pronoc_def.v"
 /**************************************
 * Module: emulator
-* Date:2017-01-20  
-* Author: alireza     
+* Date:2017-01-20
+* Author: alireza
 *
-* Description: 
+* Description:
 ***************************************/
-`include "pronoc_def.v"
 
-module  noc_emulator	
+
+module  noc_emulator
  #(
-    parameter NOC_ID=0,   
     // simulation
     parameter PATTERN_VJTAG_INDEX=125,
-    parameter STATISTIC_VJTAG_INDEX=124    
+    parameter STATISTIC_VJTAG_INDEX=124
 )(
     jtag_ctrl_reset,
     start_o,
@@ -20,352 +20,257 @@ module  noc_emulator
     clk,
     done
 );
-
-    `NOC_CONF
-
-	parameter MAX_RATIO = 100;
+    import pronoc_pkg::*;
+    parameter MAX_RATIO = 100;
     parameter RAM_Aw=7;
-    parameter STATISTIC_NUM=8;  
-   
-
+    parameter STATISTIC_NUM=8;
     input reset,jtag_ctrl_reset,clk;
     output done;
-    output start_o;     
-
+    output start_o;
     localparam
         PCK_CNTw =30,  // 1 G packets
-        MAX_EAw  =8,  
-        MAX_Cw   =4;   // 16 message classes                 
-               
-   //localparam  MAX_SIM_CLKs  = 1_000_000_000;
-    
+        MAX_EAw  =8,
+        MAX_Cw   =4;   // 16 message classes
+    //localparam  MAX_SIM_CLKs  = 1_000_000_000;
     reg start_i;
     reg [10:0] cnt;
-    
     assign start_o=start_i;
-   
-   
     //noc connection channels
     smartflit_chanel_t chan_in_all  [NE-1 : 0];
-	smartflit_chanel_t chan_out_all [NE-1 : 0];
+    smartflit_chanel_t chan_out_all [NE-1 : 0];
+    noc_top  the_top (
+        .reset(reset),
+        .clk(clk),
+        .chan_in_all(chan_in_all),
+        .chan_out_all(chan_out_all),
+        .router_event()
+    );
 
-	noc_top  # ( 
-		.NOC_ID(NOC_ID)
-	) the_top (
-		.reset(reset),
-		.clk(clk),    
-		.chan_in_all(chan_in_all),
-		.chan_out_all(chan_out_all),
-		.router_event()
-	);
- 
-   Jtag_traffic_gen #(
-        .NOC_ID(NOC_ID),
+    Jtag_traffic_gen #(
         .PATTERN_VJTAG_INDEX(PATTERN_VJTAG_INDEX),
         .STATISTIC_VJTAG_INDEX(STATISTIC_VJTAG_INDEX),
-		.MAX_RATIO(MAX_RATIO),
+        .MAX_RATIO(MAX_RATIO),
         .RAM_Aw(RAM_Aw),
         .STATISTIC_NUM(STATISTIC_NUM),  // the last 8 rows of RAM is reserved for collecting statistic values;
         .PCK_CNTw(PCK_CNTw),  // 1 G packets
         .PCK_SIZw(PCK_SIZw),   // 16 K flit
         .MAX_EAw(MAX_EAw),   // 16 nodes in x dimension
-        .MAX_Cw(MAX_Cw)   // 16 message class            
-    )
-    the_traffic_gen
-    (
-          
-        .start_i(start_i),   
-        .jtag_ctrl_reset(jtag_ctrl_reset),           
+        .MAX_Cw(MAX_Cw)   // 16 message class
+    ) the_traffic_gen (
+        .start_i(start_i),
+        .jtag_ctrl_reset(jtag_ctrl_reset),
         .reset(reset),
         .clk(clk),
-        .done(done),                  
-   		//noc            
+        .done(done),
+        //noc
         .chan_in_all(chan_out_all),
-		.chan_out_all(chan_in_all)       
+        .chan_out_all(chan_in_all)
     );
- 
-  
-  always @(posedge clk or posedge reset) begin 
-        if(reset) begin 
+
+    always @(posedge clk or posedge reset) begin
+        if(reset) begin
             cnt     <=0;
             start_i   <=0;
-       end else begin 
-             if(cnt < 1020) cnt<=  cnt+1'b1;            
-             if(cnt== 1000)begin 
+        end else begin
+            if(cnt < 1020) cnt<=  cnt+1'b1;
+            if(cnt== 1000)begin
                     start_i<=1'b1;
-             end else if(cnt== 1010)begin 
+            end else if(cnt== 1010)begin
                     start_i<=1'b0;
-             end        
-        end    
+            end
+        end
     end
 endmodule
 
 
-
 /***************
     Jtag_traffic_gen:
-    A traffic generator which can be programed using JTAG port    
-
+    A traffic generator which can be programed using JTAG port
 ****************/
-
-module  Jtag_traffic_gen 
+module  Jtag_traffic_gen
 #(
-    parameter NOC_ID = 0,
     parameter PATTERN_VJTAG_INDEX=125,
-    parameter STATISTIC_VJTAG_INDEX=124, 
+    parameter STATISTIC_VJTAG_INDEX=124,
     parameter RAM_Aw=7,
-    parameter STATISTIC_NUM=8, 
+    parameter STATISTIC_NUM=8,
     parameter MAX_RATIO = 100,
     parameter PCK_CNTw =30,  // 1 G packets
     parameter PCK_SIZw =14,   // 16 K flit
-    parameter MAX_EAw    =8,   
+    parameter MAX_EAw    =8,
     parameter MAX_Cw    =4   // 16 message class
-)
-(
+) (
     chan_in_all,
-	chan_out_all,
-
-    done,       
-    start_i,   
+    chan_out_all,
+    done,
+    start_i,
     jtag_ctrl_reset,
     reset,
     clk
 );
-
-`NOC_CONF
-
-    
-    
-    input  reset,jtag_ctrl_reset, clk;   
+    import pronoc_pkg::*;
+    input  reset,jtag_ctrl_reset, clk;
     input  start_i;
     output done;
-   
     // NOC interfaces
     input  smartflit_chanel_t chan_in_all  [NE-1 : 0];
-	output smartflit_chanel_t chan_out_all [NE-1 : 0];
-   
-     
- 
+    output smartflit_chanel_t chan_out_all [NE-1 : 0];
     wire [NE-1 :   0]  start;
-    wire [NE-1      :   0]  done_sep; 
-    assign done = &done_sep; 
-   
+    wire [NE-1      :   0]  done_sep;
+    assign done = &done_sep;
+    
     start_delay_gen #(
         .NC(NE) //number of cores
-
-    )
-    st_gen
-    (
+    ) st_gen (
         .clk(clk),
         .reset(reset),
         .start_i(start_i),
         .start_o(start)
     );
-        
-    //jtag pattern controller  
-
-    localparam   
-		NEw=$clog2(NE),		
-		Dw=64,  
-        Aw =RAM_Aw;   
-
-    wire [Dw-1 :   0] jtag_data ; 
-    wire [Aw-1 :   0] jtag_addr ; 
-    wire              jtag_we; 
+    //jtag pattern controller
+    localparam
+        NEw=$clog2(NE),
+        Dw=64,
+        Aw =RAM_Aw;
+    wire [Dw-1 :   0] jtag_data ;
+    wire [Aw-1 :   0] jtag_addr ;
+    wire              jtag_we;
     wire [Dw-1 :   0] jtag_q ;
     wire [NEw-1:   0] jtag_RAM_select;
     wire [NE-1 :   0] jtag_we_sep;
     wire [Dw-1 :   0] jtag_q_sep   [NE-1  :   0];
-
     assign jtag_q = jtag_q_sep[jtag_RAM_select];
-   
-
     jtag_emulator_controller #(
         .VJTAG_INDEX(PATTERN_VJTAG_INDEX),
         .Dw(Dw),
-        .Aw(Aw+NEw)        
-    )
-    pttern_jtag_controller
-    (
+        .Aw(Aw+NEw)
+    ) pttern_jtag_controller (
         .dat_o(jtag_data),
         .addr_o({jtag_RAM_select,jtag_addr}),
         .we_o(jtag_we),
         .q_i(jtag_q),
         .clk(clk),
-        .reset(jtag_ctrl_reset)       
+        .reset(jtag_ctrl_reset)
     );
-    
-    
-    
-    //jtag statistic reader 
-    
-     
+
+    //jtag statistic reader
     localparam
-		STATISw=log2(STATISTIC_NUM);     
-   
-    
-    wire [STATISw-1 :   0] statis_jtag_addr ; 
+        STATISw=log2(STATISTIC_NUM);
+    wire [STATISw-1 :   0] statis_jtag_addr ;
     wire [Dw-1 :   0] statis_jtag_data_i;
     wire [NEw-1:   0] statis_jtag_select;
     wire [Dw-1 :   0] statis_jtag_q_sep   [NE-1  :   0];
-    
     assign statis_jtag_data_i = statis_jtag_q_sep[statis_jtag_select];
-         
-   jtag_emulator_controller #(
+    
+    jtag_emulator_controller #(
         .VJTAG_INDEX(STATISTIC_VJTAG_INDEX),
         .Dw(Dw),
         .Aw(STATISw+NEw)
-        
-   )
-   jtag_statistic_reader
-   (
+    ) jtag_statistic_reader (
         .dat_o(),
         .addr_o({statis_jtag_select,statis_jtag_addr}),
         .we_o( ),
         .q_i(statis_jtag_data_i),
         .clk(clk),
-        .reset(jtag_ctrl_reset)       
-   );
-  
-   function integer addrencode;
+        .reset(jtag_ctrl_reset)
+    );
+
+    function integer addrencode;
         input integer pos,k,n,kw;
         integer pow,i,tmp;begin
         addrencode=0;
         pow=1;
-        for (i = 0; i <n; i=i+1 ) begin 
+        for (i = 0; i <n; i=i+1 ) begin
             tmp=(pos/pow);
             tmp=tmp%k;
             tmp=tmp<<i*kw;
             addrencode=addrencode | tmp;
             pow=pow * k;
         end
-        end   
-    endfunction 
-  
-    
+        end
+    endfunction
+
     genvar i;
-    generate 
+    generate
     for (i=0;   i<NE;   i=i+1) begin: endp
-    	     
-    	wire [EAw-1 : 0] current_e_addr [NE-1 : 0];
-			
-    	endp_addr_encoder #(
-    		.TOPOLOGY(TOPOLOGY),
-    		.T1(T1),
-    		.T2(T2),
-    		.T3(T3),
-    		.EAw(EAw),
-    		.NE(NE)
-    	)
-    	encoder
-    	(
-    		.id(i[NEw-1 : 0]),
-    		.code(current_e_addr[i])
-    	);     
-                
-                
-        // seperate interfaces per router             
+        wire [EAw-1 : 0] current_e_addr [NE-1 : 0];
+        endp_addr_encoder encoder (
+            .id_in(i[NEw-1 : 0]),
+            .code_out(current_e_addr[i])
+        );
+        // seperate interfaces per router
         assign jtag_we_sep[i] = (jtag_RAM_select == i) ? jtag_we :1'b0;
-            
+        
         traffic_gen_ram #(
-            .NOC_ID(NOC_ID),
-          	.RAM_Aw(RAM_Aw),
-            .STATISTIC_NUM(STATISTIC_NUM), 
-          	.MAX_RATIO(MAX_RATIO),
-          	.PCK_CNTw(PCK_CNTw),  // 1 G packets
+            .RAM_Aw(RAM_Aw),
+            .STATISTIC_NUM(STATISTIC_NUM),
+            .MAX_RATIO(MAX_RATIO),
+            .PCK_CNTw(PCK_CNTw),  // 1 G packets
             .PCK_SIZw(PCK_SIZw),   // 16 K flit
-            .MAX_EAw(MAX_EAw),  
+            .MAX_EAw(MAX_EAw),
             .MAX_Cw(MAX_Cw)   // 16 message cla
-          )
-          traffic_gen_ram_inst
-          (
-          	.reset(reset),
-          	.clk(clk),
-          	.current_r_addr(chan_in_all[i].ctrl_chanel.neighbors_r_addr),
+        ) traffic_gen_ram_inst (
+            .reset(reset),
+            .clk(clk),
+            .current_r_addr(chan_in_all[i].ctrl_chanel.router_addr),
             .current_e_addr(current_e_addr[i]),
-          	.start(start[i]),
-          	.done(done_sep[i]),
-          	//pattern updater
-          	.jtag_data_b(jtag_data),
-          	.jtag_addr_b(jtag_addr),
-          	.jtag_we_b( jtag_we_sep[i]),
-          	.jtag_q_b(  jtag_q_sep[i]),          	
-          	//statistic reader
-          	.statistic_jtag_addr_b(statis_jtag_addr),
-            .statistic_jtag_q_b( statis_jtag_q_sep[i]),       
-          	//noc interface
-			.chan_in (chan_in_all[i]),
-			.chan_out(chan_out_all[i])
-          	
-          );        
+            .start(start[i]),
+            .done(done_sep[i]),
+            //pattern updater
+            .jtag_data_b(jtag_data),
+            .jtag_addr_b(jtag_addr),
+            .jtag_we_b( jtag_we_sep[i]),
+            .jtag_q_b(  jtag_q_sep[i]),
+            //statistic reader
+            .statistic_jtag_addr_b(statis_jtag_addr),
+            .statistic_jtag_q_b( statis_jtag_q_sep[i]),
+            //noc interface
+            .chan_in (chan_in_all[i]),
+            .chan_out(chan_out_all[i])
+        );
     end
     endgenerate
-     
 endmodule
 
 
-
 /********************
-*
 *   traffic_gen_ram
-*
 *********************/
-
-module  traffic_gen_ram 
+module  traffic_gen_ram
 #(
-    parameter NOC_ID=0,
     parameter RAM_Aw=7,
-    parameter STATISTIC_NUM=8,  // the last 8 rows of RAM is reserved for collecting statistic values;   
+    parameter STATISTIC_NUM=8,  // the last 8 rows of RAM is reserved for collecting statistic values;
     parameter MAX_RATIO=100,
     parameter PCK_CNTw =30,  // 1 G packets
     parameter PCK_SIZw =14,   // 16 K flit
-    parameter MAX_EAw    =8,   
+    parameter MAX_EAw    =8,
     parameter MAX_Cw    =4  // 16 message class
-  
-)
-(
-       
-    done,    
+)(
+    done,
     current_r_addr,
     current_e_addr,
     start,
-   
-   //noc port
+    //noc port
     chan_in,
-	chan_out, 
-    
-    //Pattern RAM to jtag interface   
-    jtag_data_b, 
-    jtag_addr_b, 
-    jtag_we_b, 
-    jtag_q_b, 
-    
+    chan_out,
+    //Pattern RAM to jtag interface
+    jtag_data_b,
+    jtag_addr_b,
+    jtag_we_b,
+    jtag_q_b,
     // Statistic to jtag interface
     statistic_jtag_addr_b,
-    statistic_jtag_q_b,    
-   
+    statistic_jtag_q_b,
     reset,
     clk
 );
-
-    `NOC_CONF
-   
-
-  
-  //  localparam   MAX_PATTERN =  (2**RAM_Aw)-1;   // support up to MAX_PATTERN different injections pattern
-    
-   
-                 
-     
-      //define maximum width for each parameter of packet injector
-
-    localparam    RATIOw   =7;   // log2(100)  
-
-    localparam  Dw=PCK_CNTw+ RATIOw + PCK_SIZw + MAX_EAw + MAX_Cw  +1;//=64  
+    import pronoc_pkg::*;
+    // localparam   MAX_PATTERN =  (2**RAM_Aw)-1;   // support up to MAX_PATTERN different injections pattern
+    // define maximum width for each parameter of packet injector
+    localparam    RATIOw   =7;   // log2(100)
+    localparam  Dw=PCK_CNTw+ RATIOw + PCK_SIZw + MAX_EAw + MAX_Cw  +1;//=64
     localparam  Aw=RAM_Aw;
-    localparam  STATISw=log2(STATISTIC_NUM);      
-   
-    localparam 
+    localparam  STATISw=log2(STATISTIC_NUM);
+    localparam
         STATE_NUM=5,
         IDEAL =1,
         WAIT1 = 2,
@@ -378,276 +283,214 @@ module  traffic_gen_ram
         SAVE_WORST_LATENCY_NUM=32,
         */
         ASSET_DONE=16;
-
     localparam
         CLK_CNTw = log2(MAX_SIM_CLKs+1),
         MAX_PCK_NUM   = (2**PCK_CNTw)-1,
         MAX_PCK_SIZ   = (2**PCK_SIZw)-1;  // max packet size
-    
     localparam [Aw-1    :   0]
         RAM_CNT_ADDR = 0,
-        PATTERN_START_ADDR=1,        
- //       PATTERN_END_ADDR=  MAX_PATTERN,
+        PATTERN_START_ADDR=1,
+    //  PATTERN_END_ADDR=  MAX_PATTERN,
         SENT_PCK_ADDR = 0,
         RSVD_PCK_ADDR = 1,
         TOTAL_LATENCY_ADDR  = 2,
         WORST_LATENCY_ADDR  = 3;
-        
-
-    input                               reset, clk;   
+    input                               reset, clk;
     // the connected router address
     input  [RAw-1                   :0] current_r_addr;
     // the current endpoint address
     input  [EAw-1                   :0] current_e_addr;
-
-   
-   
     input                               start;
-   
     output  reg done;
     reg done_next;
-    
-    input [Dw-1 :   0]  jtag_data_b; 
-    input [Aw-1 :   0]  jtag_addr_b; 
-    input jtag_we_b; 
+    input [Dw-1 :   0]  jtag_data_b;
+    input [Aw-1 :   0]  jtag_addr_b;
+    input jtag_we_b;
     output [Dw-1 :   0] jtag_q_b;
-     
     input [STATISw-1    :   0] statistic_jtag_addr_b;
-    output reg [Dw-1 :   0] statistic_jtag_q_b;    
-    
-    
-    
+    output reg [Dw-1 :   0] statistic_jtag_q_b;
     // NOC interfaces
-    input   smartflit_chanel_t 	chan_in;
-	output  smartflit_chanel_t 	chan_out;  
-     
-  
-   
+    input   smartflit_chanel_t     chan_in;
+    output  smartflit_chanel_t     chan_out;
     wire [Dw-1  :   0] q_a;
     reg  [Aw-1  :   0] addr_a,addr_a_next;
     reg                we_a;
-    reg  [Dw-1  :   0] data_a; 
-  
-  
+    reg  [Dw-1  :   0] data_a;
     wire  [PCK_CNTw-1 :0] pck_num_to_send_in;
-    wire  [RATIOw-1 :0] ratio,ratio_in;   
+    wire  [RATIOw-1 :0] ratio,ratio_in;
     wire  [PCK_SIZw-1 :0] pck_size_in;
     wire  [MAX_EAw-1  :0] dest_e_in;
     wire  [MAX_Cw-1   :0] pck_class_in;
     wire  last_adr_in;
-           
     assign {pck_num_to_send_in,ratio_in, pck_size_in,dest_e_in, pck_class_in, last_adr_in}= q_a;
-    
     wire  [EAw-1                    :0] dest_e_addr = dest_e_in [EAw-1                    :0];
     wire  [Cw-1                    :0] pck_class= pck_class_in[Cw-1                :0];
-   
-
     wire [CLK_CNTw-1              :0] time_stamp_h2t;
     wire sent_done, update;
-    reg  [ STATE_NUM-1 :   0]  ps,ns;   
+    reg  [ STATE_NUM-1 :   0]  ps,ns;
     reg  [63    :   0] total_pck_recieved,total_pck_recieved_next,total_pck_sent,total_pck_sent_next;
     reg  [63    :   0] total_latency_cnt,total_latency_cnt_next;
     reg  [31    :   0] ram_counter,ram_counter_next;
     reg  [PCK_CNTw-1 : 0] pck_number_sent,pck_number_sent_next;
     reg  [CLK_CNTw-1 : 0] worst_latency,worst_latency_next;
-      
     reg nvalid_dest,reset_pck_number_sent_old;
-    wire nvalid_dest_next= (current_e_addr==dest_e_addr && ps!=IDEAL && ps!=WAIT1);         
-    wire reset_pck_number_sent= ((pck_number_sent==pck_num_to_send_in) | nvalid_dest) & ~reset_pck_number_sent_old;  
+    wire nvalid_dest_next= (current_e_addr==dest_e_addr && ps!=IDEAL && ps!=WAIT1);
+    wire reset_pck_number_sent= ((pck_number_sent==pck_num_to_send_in) | nvalid_dest) & ~reset_pck_number_sent_old;
     reg stop;
-	assign ratio=(ps==SEND_PCK)?  ratio_in : {RATIOw{1'b0}};
-  
-    dual_port_ram #( 
+    assign ratio=(ps==SEND_PCK)?  ratio_in : {RATIOw{1'b0}};
+    dual_port_ram #(
         .Dw (Dw),
         .Aw (Aw)
-    )
-    the_ram
-    (    
+    ) the_ram  (
         .clk        (clk),
-         //port a 
-        .data_a     (data_a), 
-        .addr_a     (addr_a),       
+         //port a
+        .data_a     (data_a),
+        .addr_a     (addr_a),
         .we_a       (we_a),
         .q_a        (q_a),
-               
         //port b connected to the jtag
         .data_b     (jtag_data_b),
         .addr_b     (jtag_addr_b),
         .we_b       (jtag_we_b),
-        .q_b        (jtag_q_b)        
+        .q_b        (jtag_q_b)
     );
- 
- wire start_traffic;    
- reg [3:0] counter;
- 
- always @(posedge clk or posedge reset) begin 
-    if(reset)  counter <=4'd0;
-    else begin 
-        if(start)  counter <=4'd1;
-        else if(counter> 4'd0 &&  counter<=4'b1111) counter <=counter+1'b1; 
+    wire start_traffic;
+    reg [3:0] counter;
+    always @(posedge clk or posedge reset) begin
+        if(reset)  counter <=4'd0;
+        else begin
+            if(start)  counter <=4'd1;
+            else if(counter> 4'd0 &&  counter<=4'b1111) counter <=counter+1'b1;
+        end
     end
- end
-            
- assign start_traffic = counter == 4'b1100; // delaied for 12 clock cycles
+    assign start_traffic = counter == 4'b1100; // delaied for 12 clock cycles
     
-       
-  traffic_gen_top #(
-        .NOC_ID(NOC_ID),
+    traffic_gen_top #(
         .MAX_RATIO(MAX_RATIO)
-    )
-    the_traffic_gen
-    (
-    
+    )  the_traffic_gen   (
         .reset(reset),
         .clk(clk),
-        //input 
+        //input
         .ratio (ratio),
         .start(start_traffic),
         .stop(stop),
-        .pck_size_in(pck_size_in), 
+        .pck_size_in(pck_size_in),
         .current_e_addr(current_e_addr),
-        .dest_e_addr(dest_e_addr),        
-        .pck_class_in(pck_class),         
+        .dest_e_addr(dest_e_addr),
+        .pck_class_in(pck_class),
         .init_weight({WEIGHTw{1'b0}}),
         .report ( ),
-        
         //output
         .update(update), // update the noc_analayzer
-        .src_e_addr( ),      
+        .src_e_addr( ),
         .pck_number( ),
         .sent_done(sent_done), // tail flit has been sent
         .hdr_flit_sent( ),
         .distance( ),
-        .pck_class_out( ),   
+        .pck_class_out( ),
         .time_stamp_h2h( ),
         .time_stamp_h2t(time_stamp_h2t),
         .flit_out_class(),
-         //noc
-         .chan_in(chan_in),
-		 .chan_out(chan_out),  
-		 .mcast_dst_num_o()
-			
-               
+        //noc
+        .chan_in(chan_in),
+        .chan_out(chan_out),
+        .mcast_dst_num_o()
     );
-      
-    always @ (*)begin 
+
+    always_comb begin
         case (statistic_jtag_addr_b)
             SENT_PCK_ADDR: statistic_jtag_q_b=  total_pck_sent;
             RSVD_PCK_ADDR: statistic_jtag_q_b=  total_pck_recieved;
             TOTAL_LATENCY_ADDR: statistic_jtag_q_b= total_latency_cnt;
             WORST_LATENCY_ADDR: statistic_jtag_q_b= worst_latency;
-            default: statistic_jtag_q_b= worst_latency; 
-         endcase
+            default: statistic_jtag_q_b= worst_latency;
+        endcase
     end
-        
-           
-          
-              
-     always @ (*)begin
-         ns=ps;
-         addr_a_next =  addr_a;
-         pck_number_sent_next = pck_number_sent;
-         done_next =done;
-         total_latency_cnt_next = total_latency_cnt;
-         worst_latency_next = worst_latency;
-         total_pck_recieved_next = total_pck_recieved;
-         total_pck_sent_next = total_pck_sent;
-         ram_counter_next = ram_counter;
-         data_a = total_pck_sent;
-         we_a = 0;
-         stop=1'b0;
-
-         if(update)begin
-                total_latency_cnt_next = total_latency_cnt + time_stamp_h2t;
-                if(time_stamp_h2t >worst_latency ) worst_latency_next=time_stamp_h2t;  
-                total_pck_recieved_next =total_pck_recieved+1'b1;
-         end 
-         
-         if(sent_done)begin 
-                 pck_number_sent_next =pck_number_sent+1'b1;
-                 total_pck_sent_next  =total_pck_sent+1'b1;
-         end              
-
-     
-         case(ps)
-         IDEAL : begin 
-              done_next =1'b0;
-              addr_a_next =RAM_CNT_ADDR;
-              ram_counter_next = q_a[31:0];  // first ram data shows how many times the RAM is needed to ne read
-              if( start) begin 
-                    addr_a_next=PATTERN_START_ADDR;
-                    ns= WAIT1;              
-              end
-         
-         end//IDEAL
-         WAIT1 : begin 
-            ns= WAIT2;            
-         
-         end 
-         WAIT2 : begin 
-            ns= SEND_PCK;            
-         
-         end        
-         SEND_PCK: begin 
-            if (reset_pck_number_sent) begin 
-                 pck_number_sent_next={PCK_CNTw{1'b0}};
-                 if(last_adr_in)begin
-                     if(ram_counter==0)begin
-                       ns = ASSET_DONE;// SAVE_SENT_PCK_NUM;
-                       //addr_a_next = SENT_PCK_ADDR;
-                     end else addr_a_next = 1;
-                     ram_counter_next=ram_counter-1'b1; 
-               end else begin
+    
+    always_comb begin
+        ns=ps;
+        addr_a_next =  addr_a;
+        pck_number_sent_next = pck_number_sent;
+        done_next =done;
+        total_latency_cnt_next = total_latency_cnt;
+        worst_latency_next = worst_latency;
+        total_pck_recieved_next = total_pck_recieved;
+        total_pck_sent_next = total_pck_sent;
+        ram_counter_next = ram_counter;
+        data_a = total_pck_sent;
+        we_a = 0;
+        stop=1'b0;
+        if(update)begin
+            total_latency_cnt_next = total_latency_cnt + time_stamp_h2t;
+            if(time_stamp_h2t >worst_latency ) worst_latency_next=time_stamp_h2t;
+            total_pck_recieved_next =total_pck_recieved+1'b1;
+        end
+        if(sent_done)begin
+            pck_number_sent_next =pck_number_sent+1'b1;
+            total_pck_sent_next  =total_pck_sent+1'b1;
+        end
+        case(ps)
+        IDEAL : begin
+            done_next =1'b0;
+            addr_a_next =RAM_CNT_ADDR;
+            ram_counter_next = q_a[31:0];  // first ram data shows how many times the RAM is needed to ne read
+            if( start) begin
+                addr_a_next=PATTERN_START_ADDR;
+                    ns= WAIT1;
+            end
+        end//IDEAL
+        WAIT1 : begin
+            ns= WAIT2;
+        end
+        WAIT2 : begin
+            ns= SEND_PCK;
+        end
+        SEND_PCK: begin
+            if (reset_pck_number_sent) begin
+                pck_number_sent_next={PCK_CNTw{1'b0}};
+                if(last_adr_in)begin
+                    if(ram_counter==0)begin
+                        ns = ASSET_DONE;// SAVE_SENT_PCK_NUM;
+                        //addr_a_next = SENT_PCK_ADDR;
+                    end else addr_a_next = 1;
+                    ram_counter_next=ram_counter-1'b1;
+                end else begin
                     addr_a_next=addr_a+1'b1;
-                                  
-               end
-            
+                end
             end
-                
-               
-                  
-         
-         
-         end//SEND_PCk
-         /*
-         SAVE_SENT_PCK_NUM: begin 
+        end//SEND_PCk
+        /*
+        SAVE_SENT_PCK_NUM: begin
             data_a = total_pck_sent;
             we_a   = 1;
             addr_a_next =RSVD_PCK_ADDR ;
-            ns= SAVE_RSVD_PCK_NUM;       
-         
-         end
-         SAVE_RSVD_PCK_NUM: begin 
+            ns= SAVE_RSVD_PCK_NUM;
+        end
+        SAVE_RSVD_PCK_NUM: begin
             data_a = total_pck_recieved;
             addr_a_next =TOTAL_LATENCY_ADDR;
             we_a   = 1;
-            ns= SAVE_TOTAL_LATENCY_NUM;       
-         
-         
-         end        
-         SAVE_TOTAL_LATENCY_NUM:  begin 
+            ns= SAVE_TOTAL_LATENCY_NUM;
+        end
+        SAVE_TOTAL_LATENCY_NUM:  begin
             data_a = total_latency_cnt;
             addr_a_next =WORST_LATENCY_ADDR;
-            we_a   = 1; 
+            we_a   = 1;
             ns=SAVE_WORST_LATENCY_NUM;
-           
-         
-         end   
-         SAVE_WORST_LATENCY_NUM:begin 
+        end
+        SAVE_WORST_LATENCY_NUM:begin
             data_a = worst_latency;
-            we_a   = 1; 
-            ns= ASSET_DONE;     
-         end  
-         */    
-         ASSET_DONE: begin 
-              done_next =1'b1;
-              stop=1'b1;
-         end
-         endcase
-      end//always
-   
-   
-   
+            we_a   = 1;
+            ns= ASSET_DONE;
+        end
+        */
+        ASSET_DONE: begin
+            done_next =1'b1;
+            stop=1'b1;
+        end
+        endcase
+    end//always
+    
     always @(posedge clk) begin
         if(reset)begin
             ps      <=  IDEAL;
@@ -661,7 +504,7 @@ module  traffic_gen_ram
             nvalid_dest<=1'b0;
             reset_pck_number_sent_old<=1'b0;
             worst_latency<={CLK_CNTw{1'b0}};
-        end else begin 
+        end else begin
             ps      <=  ns;
             addr_a<= addr_a_next;
             pck_number_sent<= pck_number_sent_next;
@@ -673,87 +516,60 @@ module  traffic_gen_ram
             nvalid_dest<=nvalid_dest_next;
             reset_pck_number_sent_old<=reset_pck_number_sent;
             worst_latency<=worst_latency_next;
-        end   
-     end
- 
-
-
+        end
+    end
 endmodule
 
 
-
-
-
 /***********************
 *
 *   jtag_emulator_controller
 *
 ***********************/
-
-
-
 module jtag_emulator_controller #(
     parameter VJTAG_INDEX=125,
     parameter Dw=32,
-    parameter Aw=32 
-
+    parameter Aw=32
 )(
     clk,
-    reset,    
+    reset,
     //wishbone master interface signals
-    
     dat_o,
     addr_o,
     we_o,
-    q_i    
+    q_i
 );
-
     //IO declaration
     input reset,clk;
-         
-    
     //wishbone master interface signals
-     
     output  [Dw-1            :   0] dat_o;
     output  [Aw-1          :   0] addr_o;
-    output  we_o; 
+    output  we_o;
     input   [Dw-1           :  0]   q_i;
-     
-   
-    
-    localparam STATE_NUM=3,
-                  IDEAL =1,
-                  WB_WR_DATA=2,
-                  WB_RD_DATA=4;
     
+    localparam 
+        STATE_NUM=3,
+        IDEAL =1,
+        WB_WR_DATA=2,
+        WB_RD_DATA=4;
+
     reg [STATE_NUM-1    :   0] ps,ns;
-    
     wire [Dw-1  :0] data_out,  data_in;
     wire  wb_wr_addr_en,  wb_wr_data_en,    wb_rd_data_en;
     reg wr_mem_en,    wb_cap_rd;
-    
     reg [Aw-1   :   0]  wb_addr,wb_addr_next;
     reg [Dw-1   :   0]  wb_wr_data,wb_rd_data;
     reg wb_addr_inc;
-    
-    
-     
     assign  we_o                = wr_mem_en;
     assign  dat_o           = wb_wr_data;
     assign  addr_o          = wb_addr;
     assign  data_in             = wb_rd_data;
-//vjtag vjtag signals declaration
-    
-
-localparam VJ_DW= (Dw > Aw)? Dw : Aw;   
-    
-    
+    //vjtag vjtag signals declaration
+    localparam VJ_DW= (Dw > Aw)? Dw : Aw;
     vjtag_ctrl #(
         .DW(VJ_DW),
         .VJTAG_INDEX(VJTAG_INDEX)
-    )
-    vjtag_ctrl_inst
-    (
+    ) vjtag_ctrl_inst  (
         .clk(clk),
         .reset(reset),
         .data_out(data_out),
@@ -764,61 +580,46 @@ localparam VJ_DW= (Dw > Aw)? Dw : Aw;
         .status_i( )
     );
     
-    
-    
-    always @(posedge clk or posedge reset) begin 
-        if(reset) begin 
+    always @(posedge clk or posedge reset) begin
+        if(reset) begin
             wb_addr <= {Aw{1'b0}};
-            wb_wr_data  <= {Dw{1'b0}};  
+            wb_wr_data  <= {Dw{1'b0}};
             ps <= IDEAL;
         end else begin
             wb_addr <= wb_addr_next;
             ps <= ns;
-            if(wb_wr_data_en) wb_wr_data  <= data_out;  
+            if(wb_wr_data_en) wb_wr_data  <= data_out;
             if(wb_cap_rd) wb_rd_data <= q_i;
         end
     end
-       
     
-    always @(*)begin 
+    always_comb begin
         wb_addr_next= wb_addr;
         if(wb_wr_addr_en) wb_addr_next = data_out [Aw-1 :   0];
-        else if (wb_addr_inc)  wb_addr_next =   wb_addr + 1'b1;    
+        else if (wb_addr_inc)  wb_addr_next =   wb_addr + 1'b1;
     end
     
-    
-    
-    always @(*)begin 
+    always_comb begin
         ns=ps;
         wr_mem_en =1'b0;
-         
         wb_addr_inc=1'b0;
         wb_cap_rd=1'b0;
         case(ps)
-        IDEAL : begin 
-            if(wb_wr_data_en) ns= WB_WR_DATA;   
-            if(wb_rd_data_en) ns= WB_RD_DATA;   
-        end 
-        WB_WR_DATA: begin 
+        IDEAL : begin
+            if(wb_wr_data_en) ns= WB_WR_DATA;
+            if(wb_rd_data_en) ns= WB_RD_DATA;
+        end
+        WB_WR_DATA: begin
             wr_mem_en =1'b1;
             ns=IDEAL;
-            wb_addr_inc=1'b1;           
-            
-        end 
-        WB_RD_DATA: begin 
-          
+            wb_addr_inc=1'b1;
+        end
+        WB_RD_DATA: begin
             wb_cap_rd=1'b1;
             ns=IDEAL;
-                //wb_addr_inc=1'b1;         
-            
-        end     
-        endcase 
-    end 
-    
+                //wb_addr_inc=1'b1;
+        end
+        endcase
+    end
     //assign led={wb_addr[7:0], wb_wr_data[7:0]};
-
-endmodule
-
-
-
-
+endmodule
\ No newline at end of file
diff --git a/mpsoc/rtl/src_emulate/rtl/noc_emulator.vold b/mpsoc/rtl/src_emulate/rtl/noc_emulator.vold
index 446c68f..b23be17 100755
--- a/mpsoc/rtl/src_emulate/rtl/noc_emulator.vold
+++ b/mpsoc/rtl/src_emulate/rtl/noc_emulator.vold
@@ -9,14 +9,14 @@
 
 module  noc_emulator #(
     //NoC parameters
-    parameter V    = 1,    
-    parameter B    = 4,     
+    parameter V    = 1,
+    parameter B    = 4,
     parameter T1   = 4, 
     parameter T2   = 4, 
     parameter T3   = 1,
     parameter TOPOLOGY = "MESH",
-    parameter ROUTE_NAME  =   "XY",
-    parameter C    = 4,  
+    parameter ROUTE_NAME  =   "DOR",
+    parameter C    = 4,
     parameter Fpay = 32,
     parameter MUX_TYPE  = "BINARY", 
     parameter VC_REALLOCATION_TYPE  =  "NONATOMIC",
@@ -27,13 +27,13 @@ module  noc_emulator #(
     parameter AVC_ATOMIC_EN = 1,
     parameter ADD_PIPREG_AFTER_CROSSBAR = 0,
     parameter CVw=(C==0)? V : C * V,
-    parameter [CVw-1:   0] CLASS_SETTING = {CVw{1'b1}},    
-    parameter [V-1  :   0] ESCAP_VC_MASK = 4'b1000,  
-    parameter SSA_EN = "NO",        
+    parameter [CVw-1:   0] CLASS_SETTING = {CVw{1'b1}},
+    parameter [V-1  :   0] ESCAP_VC_MASK = 4'b1000,
+    parameter SSA_EN = 0,
     parameter SWA_ARBITER_TYPE = "RRA", 
     parameter WEIGHTw = 4, 
     parameter MIN_PCK_SIZE = 2, 
-    parameter BYTE_EN=0,    
+    parameter BYTE_EN=0,
     
     
     // simulation
@@ -215,7 +215,7 @@ module  Jtag_traffic_gen #(
     parameter Fpay = 32,
     parameter VC_REALLOCATION_TYPE  = "NONATOMIC",// "ATOMIC" , "NONATOMIC"
     parameter TOPOLOGY  = "MESH",
-    parameter ROUTE_NAME    = "XY",
+    parameter ROUTE_NAME    = "DOR",
     parameter C = 4 ,   //  number of flit class
     parameter MIN_PCK_SIZE = 2,
     parameter BYTE_EN=0,    
@@ -475,7 +475,7 @@ module  traffic_gen_ram #(
     parameter Fpay = 32,
     parameter VC_REALLOCATION_TYPE  = "NONATOMIC",// "ATOMIC" , "NONATOMIC"
     parameter TOPOLOGY  = "MESH",
-    parameter ROUTE_NAME    = "XY",
+    parameter ROUTE_NAME    = "DOR",
     parameter C = 4,    //  number of flit class
     parameter RAM_Aw=7,
     parameter STATISTIC_NUM=8,  // the last 8 rows of RAM is reserved for collecting statistic values;   
diff --git a/mpsoc/rtl/src_modelsim/multicast_injector.sv b/mpsoc/rtl/src_modelsim/multicast_injector.sv
index bce9d4f..942f5a5 100644
--- a/mpsoc/rtl/src_modelsim/multicast_injector.sv
+++ b/mpsoc/rtl/src_modelsim/multicast_injector.sv
@@ -1,497 +1,364 @@
 `include "pronoc_def.v"
-
 /****************************
  * This module can inject and eject packets from the NoC.
- * It can be used in simulation for injecting real application traces to the NoC 
+ * It can be used in simulation for injecting real application traces to the NoC
  * *************************/
-
-
-module multicast_injector #(
-	parameter NOC_ID=0
-)(
-	//general
-	current_e_addr,
-	reset,
-	clk,		
-	//noc port
-	chan_in,
-	chan_out,  
-	//control interafce
-	pck_injct_in,
-	pck_injct_out		
+module multicast_injector (
+    //general
+    current_e_addr,
+    reset,
+    clk,
+    //noc port
+    chan_in,
+    chan_out,
+    //control interafce
+    pck_injct_in,
+    pck_injct_out
 );
-	
-	`NOC_CONF
-	
-	//general
-	input reset,clk;
-	input [EAw-1 :0 ] current_e_addr;
-	
-	// the destination endpoint address
-	//NoC interface
-	input   smartflit_chanel_t 	chan_in;
-	output  smartflit_chanel_t 	chan_out;	
-	//control interafce
-	
-	input   pck_injct_t pck_injct_in;
-	output  pck_injct_t pck_injct_out;
-	
-	
-	wire  [RAw-1 :0 ] current_r_addr;    
-	
-	wire  [DSTPw-1 : 0 ] destport;   
-	reg flit_wr;	
-	
-	assign current_r_addr = chan_in.ctrl_chanel.neighbors_r_addr;
-		
-	/*
-	conventional_routing #(
-		.NOC_ID(NOC_ID),
-		.TOPOLOGY(TOPOLOGY),
-		.ROUTE_NAME(ROUTE_NAME),
-		.ROUTE_TYPE(ROUTE_TYPE),
-		.T1(T1),
-		.T2(T2),
-		.T3(T3),
-		.RAw(RAw),
-		.EAw(EAw),
-		.DSTPw(DSTPw),
-		.LOCATED_IN_NI(1)
-	)
-	routing_module
-	(
-		.reset(reset),
-		.clk(clk),
-		.current_r_addr(current_r_addr),
-		.dest_e_addr(pck_injct_in.endp_addr),
-		.src_e_addr(current_e_addr),
-		.destport(destport)
-	);
-	
-*/
-
-	assign destport = 7;
-
-	localparam 
-		HDR_BYTE_NUM =	HDR_MAX_DATw / 8, // = HDR_MAX_DATw / (8 - HDR_MAX_DATw %8)
-		HDR_DATA_w_tmp   =  HDR_BYTE_NUM * 8,
-		HDR_DATA_w = (PCK_INJ_Dw < HDR_DATA_w_tmp)? PCK_INJ_Dw : HDR_DATA_w_tmp;
-
-	wire [HDR_DATA_w-1 : 0]	hdr_data_in = pck_injct_in.data [HDR_DATA_w-1 : 0];
-	wire [Fw-1 : 0] hdr_flit_out;
-	
-	header_flit_generator #(
-		.NOC_ID(NOC_ID),
-		.DATA_w(HDR_DATA_w)				
-	) the_header_flit_generator (
-		.flit_out			(hdr_flit_out),
-		.vc_num_in			(pck_injct_in.vc),
-		.class_in			(pck_injct_in.class_num),
-		.dest_e_addr_in		(pck_injct_in.endp_addr),
-		.src_e_addr_in		(current_e_addr),
-		.weight_in			(pck_injct_in.init_weight),
-		.destport_in		(destport),
-		.data_in			(hdr_data_in),
-		.be_in({BEw{1'b1}} )// Be is not used in simulation as we dont sent real data
-	);
-	
-	
-	localparam 
-		REMAIN_DATw =  PCK_INJ_Dw - HDR_DATA_w,
-		REMAIN_DAT_FLIT_I = (REMAIN_DATw / Fpay),
-		REMAIN_DAT_FLIT_F = (REMAIN_DATw % Fpay == 0)? 0 : 1,
-		REMAIN_DAT_FLIT   = REMAIN_DAT_FLIT_I + REMAIN_DAT_FLIT_F,
-		CNTw = log2(REMAIN_DAT_FLIT),
-		MIN_PCK_SIZ = REMAIN_DAT_FLIT +1;
-		
-	
-	reg [PCK_SIZw-1             :   0]  counter, counter_next;
-	reg [CNTw-1                 :   0]  counter2,counter2_next;
-	reg tail,head;	
-		
-	wire [Fpay -1 : 0]  remain_dat [REMAIN_DAT_FLIT -1 : 0];
-	wire [Fpay-1 : 0] dataIn =  remain_dat[counter2];
-	enum {HEADER, BODY,TAIL} flit_type,flit_type_next;
-		
-	
-	
-	wire [V-1 : 0]   wr_vc_send = (flit_wr)?   pck_injct_in.vc : {V{1'b0}};
-	wire [V-1 : 0]   vc_fifo_full;
-		
-	
-	wire noc_ready;
-		
-	localparam 
-		LAST_TMP =PCK_INJ_Dw -  (Fpay*REMAIN_DAT_FLIT_I)-HDR_DATA_w,
-		LASTw=(LAST_TMP==0)? Fpay : LAST_TMP;
-	genvar i;
-	generate 
-		for(i=0; i<REMAIN_DAT_FLIT_I; i++) begin 
-			assign remain_dat [i] = pck_injct_in.data [Fpay*(i+1)+HDR_DATA_w-1   : (Fpay*i)+HDR_DATA_w];				
-		end
-		if(REMAIN_DAT_FLIT_F ) begin 
-
-			assign remain_dat [REMAIN_DAT_FLIT_I][LASTw-1 : 0] = pck_injct_in.data [PCK_INJ_Dw-1   : (Fpay*REMAIN_DAT_FLIT_I)+HDR_DATA_w];				
-		end
-	endgenerate
-	
-		
-	
-		
-		
-		one_hot_mux #(
-			.IN_WIDTH   (V ), 
-			.SEL_WIDTH  (V ), 
-			.OUT_WIDTH  (1 )
-			) one_hot_mux1 (
-			.mux_in     (~ vc_fifo_full    ), 
-			.mux_out    (noc_ready   ), 
-			.sel        (pck_injct_in.vc       ));
-		
-		
-		
-		
-		always @ (*) begin 
-			counter_next = counter;
-			counter2_next =counter2;
-			flit_type_next =flit_type;
-			tail=1'b0;
-			head=1'b0;
-			flit_wr=0;
-			if(noc_ready)begin 
-				case(flit_type) 
-					HEADER:begin 
-						if(pck_injct_in.pck_wr)begin 
-							flit_wr=1;
-							counter_next = pck_injct_in.size-1;
-							counter2_next=0;
-							head=1'b1;
-							if(pck_injct_in.size == 1)begin
-								tail=1'b1;
-							end else if (pck_injct_in.size == 2) begin 
-								flit_type_next = TAIL;
-							end else begin 
-								flit_type_next = BODY;
-							end 
-						end
-					end
-					BODY: begin 
-						flit_wr=1;
-						counter_next = counter -1'b1;
-						counter2_next =counter2 +1'b1;
-						if(counter == 2) begin 							
-							flit_type_next = TAIL;
-						end
-					end
-					TAIL: begin						
-						flit_type_next = HEADER;
-						flit_wr=1;
-						tail=1'b1;
-					end
-				endcase
-				
-			end
-		end
-		reg [V-1 : 0] credit_o;
-		
-		always @ (posedge clk) begin 
-			if(`pronoc_reset) begin 
-				flit_type<=HEADER;
-				counter<=0;
-				counter2<=0;
-				credit_o<={V{1'b0}};				
-			end else begin 
-				flit_type<=flit_type_next;
-				counter<=counter_next;
-				counter2<=counter2_next;
-				if (chan_in.flit_chanel.flit_wr) credit_o<=  chan_in.flit_chanel.flit.vc;
-				else credit_o<={V{1'b0}};		
-			end
-		end	
-		
-		
-	
-	
-		
-	multi_cast_injector_ovc_status #(
-		.V(V),
-		.B(LB),
-		.CRDTw(CRDTw)    
-	)
-	the_ovc_status
-	(
-		.credit_init_val_in ( chan_in.ctrl_chanel.credit_init_val),
-		.wr_in(wr_vc_send),
-		.credit_in(chan_in.flit_chanel.credit),
-		.full_vc(vc_fifo_full),
-		.nearly_full_vc( ),
-		.empty_vc( ),
-		.clk(clk),
-		.reset(reset)
-	); 
-		
-	
-	wire [HDR_DATA_w-1 : 0]	hdr_data_o;
-	hdr_flit_t hdr_flit_i;
-	
-	header_flit_info
-	#(
-		.NOC_ID (NOC_ID),	
-		.DATA_w (HDR_DATA_w)
-	) extractor (
-		.flit(chan_in.flit_chanel.flit),
-		.hdr_flit(hdr_flit_i),		
-		.data_o(hdr_data_o)    
-	);
-		
-	wire [PCK_INJ_Dw-1 : 0]  pck_data_o [V-1 : 0];
-	reg  [Fpay-1 : 0] pck_data_o_gen [V-1 : 0][REMAIN_DAT_FLIT : 0];
-	
-	genvar k;
-	
-	reg [PCK_SIZw-1 : 0] rsv_counter [V-1 : 0];
-	reg [EAw-1 : 0] sender_endp_addr_reg [V-1 : 0];
-	logic [15:0] h2t_counter [V-1 : 0];
-	logic [15:0] h2t_counter_next [V-1 : 0];
-	
-	
-	
-	//synthesis translate_off
-	wire [NEw-1 : 0] current_id; 
-	wire [NEw-1 : 0] sendor_id; 
-	endp_addr_decoder #( .TOPOLOGY(TOPOLOGY), .T1(T1), .T2(T2), .T3(T3), .EAw(EAw),  .NE(NE)) encode1 ( .id(current_id), .code(current_e_addr));
-	endp_addr_decoder #( .TOPOLOGY(TOPOLOGY), .T1(T1), .T2(T2), .T3(T3), .EAw(EAw),  .NE(NE)) encode2 ( .id(sendor_id), .code(pck_injct_out.endp_addr[EAw-1 : 0]));
-	//synthesis translate_on
-	
-	
-	generate 
-		for(i=0; i<V; i++) begin: V_ 
-			always@(*) begin
-				h2t_counter_next[i]=h2t_counter[i]+1'b1;
-				if(chan_in.flit_chanel.flit.vc[i] & chan_in.flit_chanel.flit_wr & chan_in.flit_chanel.flit.hdr_flag)begin 
-							h2t_counter_next[i]= 16'd0; // reset once header flit is received
-				end//hdr flit wr
-			end//always
-			
-			
-			
-			
-			always_ff @(`pronoc_clk_reset_edge) begin
-				if (`pronoc_reset)  begin
-					rsv_counter[i]<= {PCK_SIZw{1'b0}};
-					h2t_counter[i]<= 16'd0;
-					sender_endp_addr_reg [i]<= {EAw{1'b0}};
-				end else begin 
-					h2t_counter[i]<=h2t_counter_next[i];
-					if(chan_in.flit_chanel.flit.vc[i] & chan_in.flit_chanel.flit_wr ) begin 
-						if(chan_in.flit_chanel.flit.hdr_flag)begin						
-							rsv_counter[i]<= {{(PCK_SIZw-1){1'b0}}, 1'b1};
-							sender_endp_addr_reg [i]<= hdr_flit_i.src_e_addr; 
-							//synthesis translate_off
-							if(hdr_flit_i.dest_e_addr != current_e_addr) begin 
-								$display("%t: ERROR: packet destination address %d does not match reciver endp address %d. %m",$time,hdr_flit_i.dest_e_addr , current_e_addr );
-								$finish;
-							end//if hdr_flit_i
-							//synthesis translate_on	
-						end //if hdr_flag
-						else rsv_counter[i]<= rsv_counter[i]+1'b1;						
-					end//flit wr					
-				end//reset
-			end//always
-			
-			
-				
-
-			for (k=0;k< REMAIN_DAT_FLIT+1;k++)begin : K_
-			
-				always_ff @(`pronoc_clk_reset_edge) begin
-					if (`pronoc_reset)  begin
-						pck_data_o_gen [i][k] <= {Fpay{1'b0}};
-						
-					end else begin
-						if(chan_in.flit_chanel.flit.vc[i] & chan_in.flit_chanel.flit_wr ) begin 
-							if (chan_in.flit_chanel.flit.hdr_flag )begin 
-								if ( k ==0 ) pck_data_o_gen [i][k][HDR_DATA_w-1 : 0] <= hdr_data_o;														
-							end
-							else begin 
-								if (rsv_counter[i] == k ) pck_data_o_gen [i][k] <= chan_in.flit_chanel.flit.payload;
-								
-							end // else
-						end //if
-					end //else
-				end// always
-					
-                                        if   (k == 0 ) assign pck_data_o [i][HDR_DATA_w-1 : 0] = pck_data_o_gen [i][0][HDR_DATA_w-1 : 0];
-					else if (k == REMAIN_DAT_FLIT) assign pck_data_o [i][PCK_INJ_Dw-1 :    (k-1)*Fpay+ HDR_DATA_w] = pck_data_o_gen [i][k][LASTw-1: 0];	
-					else assign pck_data_o [i][(k)*Fpay+HDR_DATA_w -1 : (k-1)*Fpay+ HDR_DATA_w] = pck_data_o_gen [i][k];	
-					
-			end //for k
-			
-			
-			//synthesis translate_off
-			always @(posedge clk) begin 
-				if((pck_injct_out.ready[i] == 1'b0 ) & pck_injct_in.vc[i] & pck_injct_in.pck_wr )begin 
-					$display("%t: ERROR: a packet injection request is recived in core(%d), vc (%d) while packet injectore was not ready. %m",$time,current_id,i);
-					$finish;
-				end
-		
-			end	
-			//synthesis translate_on
-	
-	
-			
-					
-		end//for i			
-	endgenerate
-	
-	wire [V-1 : 0] vc_reg;
-	wire tail_flag_reg, hdr_flag_reg;
-	
-	
-	pronoc_register #(.W(V))   register1 (.in(chan_in.flit_chanel.flit.vc),        .reset  (reset ), .clk (clk),.out(vc_reg));
-	pronoc_register #(.W(1))   register2 (.in(chan_in.flit_chanel.flit.hdr_flag),	.reset  (reset ), .clk (clk),.out(hdr_flag_reg));
-	pronoc_register #(.W(1))   register3 (.in(chan_in.flit_chanel.flit.tail_flag & chan_in.flit_chanel.flit_wr ),.reset  (reset ), .clk (clk),.out(tail_flag_reg));
-	
-	wire [Vw-1 : 0] vc_bin;
-	
-	one_hot_to_bin #(
-		.ONE_HOT_WIDTH  (V), 
-		.BIN_WIDTH      (Vw )
-	) one_hot_to_bin (
-		.one_hot_code   (vc_reg  ), 
-		.bin_code       (vc_bin      )
-	);
-
-	
-	assign pck_injct_out.data  =  pck_data_o[vc_bin];
-	assign pck_injct_out.size  =  rsv_counter[vc_bin];
-	assign pck_injct_out.h2t_delay = h2t_counter[vc_bin];
-	assign pck_injct_out.ready = (flit_type == HEADER)?  ~vc_fifo_full : {V{1'b0}};	
-	assign pck_injct_out.endp_addr =  sender_endp_addr_reg[vc_bin];
-	assign pck_injct_out.vc = vc_reg;
-	assign pck_injct_out.pck_wr = tail_flag_reg;  	
-	
-	assign chan_out.flit_chanel.flit.hdr_flag =head;
-	assign chan_out.flit_chanel.flit.tail_flag=tail;
-	assign chan_out.flit_chanel.flit.vc=pck_injct_in.vc;
-	assign chan_out.flit_chanel.flit_wr=flit_wr;
-
-	assign chan_out.flit_chanel.flit.payload = (flit_type==	HEADER)? hdr_flit_out[Fpay-1 : 0] : dataIn;
-	assign chan_out.smart_chanel = {SMART_CHANEL_w{1'b0}};
-	assign chan_out.flit_chanel.congestion = {CONGw{1'b0}};
-	assign chan_out.flit_chanel.credit= credit_o;	
-	assign chan_out.ctrl_chanel.credit_init_val= LB;	
-	assign chan_out.ctrl_chanel.endp_port =1'b1;
-	
-	
-	distance_gen #(
-			.TOPOLOGY(TOPOLOGY),
-			.T1(T1),
-			.T2(T2),
-			.T3(T3),
-			.EAw(EAw),
-			.DISTw(DISTw)
-		)
-		the_distance_gen
-		(
-			.src_e_addr(sender_endp_addr_reg[vc_bin]),
-			.dest_e_addr(current_e_addr),
-			.distance(pck_injct_out.distance)
-		);
-	
-	
-	
-	
-	
-	
-	//synthesis translate_off
-	//`define MONITOR_RSV_DAT
-	
-
-	
-	always @(posedge clk) begin 
-		if((pck_injct_in.vc == {V{1'b0}} ) & pck_injct_in.pck_wr )begin 
-			$display("%t: ERROR: a packet injection request is recived while vc is not set. %m",$time);
-			$finish;
-		end
-		if(pck_injct_in.pck_wr && (pck_injct_in.size<MIN_PCK_SIZ[PCK_SIZw-1 : 0])) begin 
-			$display("%t: ERROR: requested %d flit packet size is smaller than minimum %d flits to send %d bits of data. %m",$time,pck_injct_in.size,MIN_PCK_SIZ, PCK_INJ_Dw );
-			$finish;
-		end
-		
-		`ifdef MONITOR_RSV_DAT
-		
-			
-		if(pck_injct_in.pck_wr) begin 
-			$display ("pck_inj(%d) send a packet:  size=%d, data=%h, v=%h",current_id,
-					pck_injct_in.size, pck_injct_in.data,pck_injct_in.vc);
-		end	
-			
-		if(pck_injct_out.pck_wr) begin 
-			$display ("pck_inj(%d) got a packet: source=%d, size=%d, data=%h",current_id,
-					sendor_id,pck_injct_out.size,pck_injct_out.data);
-		end	
-		
-		
-		`endif
-		
-	end	
-	
-	
-	//synthesis translate_on
-	
-	
-	
-	
-	
+    import pronoc_pkg::*;
+    //general
+    input reset,clk;
+    input [EAw-1 :0 ] current_e_addr;
+    // the destination endpoint address
+    //NoC interface
+    input   smartflit_chanel_t     chan_in;
+    output  smartflit_chanel_t     chan_out;
+    //control interafce
+    input   pck_injct_t pck_injct_in;
+    output  pck_injct_t pck_injct_out;
+    wire  [RAw-1 :0 ] current_r_addr;
+    wire  [DSTPw-1 : 0 ] destport;
+    reg flit_wr;
+    assign current_r_addr = chan_in.ctrl_chanel.router_addr;
+    
+    assign destport = 7;
+    localparam
+        HDR_BYTE_NUM =    HDR_MAX_DATw / 8, // = HDR_MAX_DATw / (8 - HDR_MAX_DATw %8)
+        HDR_DATA_w_tmp   =  HDR_BYTE_NUM * 8,
+        HDR_DATA_w = (PCK_INJ_Dw < HDR_DATA_w_tmp)? PCK_INJ_Dw : HDR_DATA_w_tmp;
+    wire [HDR_DATA_w-1 : 0]    hdr_data_in = pck_injct_in.data [HDR_DATA_w-1 : 0];
+    wire [Fw-1 : 0] hdr_flit_out;
+    header_flit_generator #(
+        .DATA_w(HDR_DATA_w)
+    ) the_header_flit_generator (
+        .flit_out (hdr_flit_out),
+        .vc_num_in (pck_injct_in.vc),
+        .class_in (pck_injct_in.class_num),
+        .dest_e_addr_in (pck_injct_in.endp_addr),
+        .src_e_addr_in (current_e_addr),
+        .weight_in (pck_injct_in.init_weight),
+        .destport_in (destport),
+        .data_in (hdr_data_in),
+        .be_in({BEw{1'b1}} )// Be is not used in simulation as we dont sent real data
+    );
+    localparam
+        REMAIN_DATw =  PCK_INJ_Dw - HDR_DATA_w,
+        REMAIN_DAT_FLIT_I = (REMAIN_DATw / Fpay),
+        REMAIN_DAT_FLIT_F = (REMAIN_DATw % Fpay == 0)? 0 : 1,
+        REMAIN_DAT_FLIT   = REMAIN_DAT_FLIT_I + REMAIN_DAT_FLIT_F,
+        CNTw = log2(REMAIN_DAT_FLIT),
+        MIN_PCK_SIZ = REMAIN_DAT_FLIT +1;
+    reg [PCK_SIZw-1 : 0]  counter, counter_next;
+    reg [CNTw-1 : 0]  counter2,counter2_next;
+    reg tail,head;
+    wire [Fpay -1 : 0]  remain_dat [REMAIN_DAT_FLIT -1 : 0];
+    wire [Fpay-1 : 0] dataIn =  remain_dat[counter2];
+    enum {HEADER, BODY,TAIL} flit_type,flit_type_next;
+    wire [V-1 : 0] wr_vc_send = (flit_wr)?   pck_injct_in.vc : {V{1'b0}};
+    wire [V-1 : 0] vc_fifo_full;
+    wire noc_ready;
+    localparam
+        LAST_TMP =PCK_INJ_Dw - (Fpay*REMAIN_DAT_FLIT_I)-HDR_DATA_w,
+        LASTw=(LAST_TMP==0)? Fpay : LAST_TMP;
+    genvar i;
+    generate
+    for(i=0; i<REMAIN_DAT_FLIT_I; i++) begin :F_
+        assign remain_dat [i] = pck_injct_in.data [Fpay*(i+1)+HDR_DATA_w-1   : (Fpay*i)+HDR_DATA_w];
+    end
+    if(REMAIN_DAT_FLIT_F ) begin
+        assign remain_dat [REMAIN_DAT_FLIT_I][LASTw-1 : 0] = pck_injct_in.data [PCK_INJ_Dw-1   : (Fpay*REMAIN_DAT_FLIT_I)+HDR_DATA_w];
+    end
+    endgenerate
+    
+    one_hot_mux #(
+        .IN_WIDTH (V ),
+        .SEL_WIDTH (V ),
+        .OUT_WIDTH (1 )
+    ) one_hot_mux1 (
+        .mux_in (~ vc_fifo_full),
+        .mux_out (noc_ready),
+        .sel (pck_injct_in.vc)
+    );
+    
+    always_comb begin
+        counter_next = counter;
+        counter2_next =counter2;
+        flit_type_next =flit_type;
+        tail=1'b0;
+        head=1'b0;
+        flit_wr=0;
+        if(noc_ready)begin
+            case(flit_type)
+                HEADER:begin
+                    if(pck_injct_in.pck_wr)begin
+                        flit_wr=1;
+                        counter_next = pck_injct_in.size-1;
+                        counter2_next=0;
+                        head=1'b1;
+                        if(pck_injct_in.size == 1)begin
+                            tail=1'b1;
+                        end else if (pck_injct_in.size == 2) begin
+                            flit_type_next = TAIL;
+                        end else begin
+                            flit_type_next = BODY;
+                        end
+                    end
+                end
+                BODY: begin
+                    flit_wr=1;
+                    counter_next = counter -1'b1;
+                    counter2_next =counter2 +1'b1;
+                    if(counter == 2) begin
+                        flit_type_next = TAIL;
+                    end
+                end
+                TAIL: begin
+                    flit_type_next = HEADER;
+                    flit_wr=1;
+                    tail=1'b1;
+                end
+            endcase
+        end
+    end
+    reg [V-1 : 0] credit_o;
+    
+    always @ (posedge clk) begin
+        if(`pronoc_reset) begin
+            flit_type<=HEADER;
+            counter<=0;
+            counter2<=0;
+            credit_o<={V{1'b0}};
+        end else begin
+            flit_type<=flit_type_next;
+            counter<=counter_next;
+            counter2<=counter2_next;
+            if (chan_in.flit_chanel.flit_wr) credit_o<=  chan_in.flit_chanel.flit.vc;
+            else credit_o<={V{1'b0}};
+        end
+    end
+    
+    multi_cast_injector_ovc_status #(
+        .V(V),
+        .B(LB),
+        .CRDTw(CRDTw)
+    ) the_ovc_status (
+        .credit_init_val_in ( chan_in.ctrl_chanel.credit_init_val),
+        .wr_in(wr_vc_send),
+        .credit_in(chan_in.flit_chanel.credit),
+        .full_vc(vc_fifo_full),
+        .nearly_full_vc( ),
+        .empty_vc( ),
+        .clk(clk),
+        .reset(reset)
+    );
+    wire [HDR_DATA_w-1 : 0]    hdr_data_o;
+    hdr_flit_t hdr_flit_i;
+    header_flit_info #(
+        .DATA_w (HDR_DATA_w)
+    ) extractor (
+        .flit(chan_in.flit_chanel.flit),
+        .hdr_flit(hdr_flit_i),
+        .data_o(hdr_data_o)
+    );
+    wire [PCK_INJ_Dw-1 : 0]  pck_data_o [V-1 : 0];
+    reg  [Fpay-1 : 0] pck_data_o_gen [V-1 : 0][REMAIN_DAT_FLIT : 0];
+    genvar k;
+    reg [PCK_SIZw-1 : 0] rsv_counter [V-1 : 0];
+    reg [EAw-1 : 0] sender_endp_addr_reg [V-1 : 0];
+    logic [Cw-1 : 0] sender_class_reg [V-1 : 0];
+    logic [15:0] h2t_counter [V-1 : 0];
+    logic [15:0] h2t_counter_next [V-1 : 0];
+    
+    `ifdef SIMULATION
+    wire [NEw-1 : 0] current_id;
+    wire [NEw-1 : 0] sendor_id;
+    endp_addr_decoder  encode1 ( .id_out(current_id), .code_in(current_e_addr));
+    endp_addr_decoder  encode2 ( .id_out(sendor_id), .code_in(pck_injct_out.endp_addr[EAw-1 : 0]));
+    `endif
+    
+    generate
+    for(i=0; i<V; i++) begin: V_
+        always@(*) begin
+            h2t_counter_next[i]=h2t_counter[i]+1'b1;
+            if(chan_in.flit_chanel.flit.vc[i] & chan_in.flit_chanel.flit_wr & chan_in.flit_chanel.flit.hdr_flag)begin
+                h2t_counter_next[i]= 16'd0; // reset once header flit is received
+            end//hdr flit wr
+        end//always
+        always_ff @ (`pronoc_clk_reset_edge) begin
+            if (`pronoc_reset)  begin
+                rsv_counter[i]<= {PCK_SIZw{1'b0}};
+                h2t_counter[i]<= 16'd0;
+                sender_endp_addr_reg [i]<= {EAw{1'b0}};
+                sender_class_reg [i]<= {Cw{1'b0}};
+            end else begin
+                h2t_counter[i]<=h2t_counter_next[i];
+                if(chan_in.flit_chanel.flit.vc[i] & chan_in.flit_chanel.flit_wr ) begin
+                    if(chan_in.flit_chanel.flit.hdr_flag)begin
+                        rsv_counter[i]<= {{(PCK_SIZw-1){1'b0}}, 1'b1};
+                        sender_endp_addr_reg [i]<= hdr_flit_i.src_e_addr;
+                        sender_class_reg [i]<= hdr_flit_i.message_class;
+                        `ifdef SIMULATION
+                        if(hdr_flit_i.dest_e_addr != current_e_addr) begin
+                            $display("%t: ERROR: packet destination address %d does not match reciver endp address %d. %m",$time,hdr_flit_i.dest_e_addr , current_e_addr );
+                            $finish;
+                        end//if hdr_flit_i
+                        `endif //SIMULATION
+                    end //if hdr_flag
+                    else rsv_counter[i]<= rsv_counter[i]+1'b1;
+                end//flit wr
+            end//reset
+        end//always
+        for (k=0;k< REMAIN_DAT_FLIT+1;k++)begin : K_
+            always_ff @ (`pronoc_clk_reset_edge) begin
+                if (`pronoc_reset)  begin
+                    pck_data_o_gen [i][k] <= {Fpay{1'b0}};
+                end else begin
+                    if(chan_in.flit_chanel.flit.vc[i] & chan_in.flit_chanel.flit_wr ) begin
+                        if (chan_in.flit_chanel.flit.hdr_flag )begin
+                            if ( k ==0 ) pck_data_o_gen [i][k][HDR_DATA_w-1 : 0] <= hdr_data_o;
+                        end
+                        else begin
+                            if (rsv_counter[i] == k ) pck_data_o_gen [i][k] <= chan_in.flit_chanel.flit.payload;
+                        end // else
+                    end //if
+                end //else
+            end// always
+            if (k == 0 ) assign pck_data_o [i][HDR_DATA_w-1 : 0] = pck_data_o_gen [i][0][HDR_DATA_w-1 : 0];
+            else if (k == REMAIN_DAT_FLIT) assign pck_data_o [i][PCK_INJ_Dw-1 : (k-1)*Fpay+ HDR_DATA_w] = pck_data_o_gen [i][k][LASTw-1: 0];
+            else assign pck_data_o [i][(k)*Fpay+HDR_DATA_w -1 : (k-1)*Fpay+ HDR_DATA_w] = pck_data_o_gen [i][k];
+        end //for k
+        `ifdef SIMULATION
+        always @(posedge clk) begin
+            if((pck_injct_out.ready[i] == 1'b0 ) & pck_injct_in.vc[i] & pck_injct_in.pck_wr )begin
+                $display("%t: ERROR: a packet injection request is recived in core(%d), vc (%d) while packet injectore was not ready. %m",$time,current_id,i);
+                $finish;
+            end
+        end
+        `endif
+    end//for i
+    endgenerate
+    
+    logic [V-1 : 0] vc_reg;
+    logic tail_flag_reg, hdr_flag_reg;
+    logic [DISTw-1:   0] distance;
+    
+    always_ff @ (`pronoc_clk_reset_edge )begin 
+        if(`pronoc_reset) begin 
+            vc_reg <= {V{1'b0}};
+            hdr_flag_reg  <= 1'b0;
+            tail_flag_reg <= 1'b0;
+        end else begin
+            vc_reg <= chan_in.flit_chanel.flit.vc;
+            hdr_flag_reg <= chan_in.flit_chanel.flit.hdr_flag;
+            tail_flag_reg <= chan_in.flit_chanel.flit.tail_flag & chan_in.flit_chanel.flit_wr;
+        end
+    end
+    
+    wire [Vw-1 : 0] vc_bin;
+    one_hot_to_bin #(
+        .ONE_HOT_WIDTH (V),
+        .BIN_WIDTH (Vw )
+    ) one_hot_to_bin (
+        .one_hot_code (vc_reg  ),
+        .bin_code (vc_bin  )
+    );
+    always_comb begin 
+        pck_injct_out.data  =  pck_data_o[vc_bin];
+        pck_injct_out.size  =  rsv_counter[vc_bin];
+        pck_injct_out.h2t_delay = h2t_counter[vc_bin];
+        pck_injct_out.ready = (flit_type == HEADER)?  ~vc_fifo_full : {V{1'b0}};
+        pck_injct_out.endp_addr =  sender_endp_addr_reg[vc_bin];
+        pck_injct_out.class_num = sender_class_reg[vc_bin];
+        pck_injct_out.init_weight = WEIGHT_INIT;
+        pck_injct_out.vc = vc_reg;
+        pck_injct_out.pck_wr = tail_flag_reg;
+        pck_injct_out.distance = distance;
+        
+        chan_out.flit_chanel.flit.hdr_flag =head;
+        chan_out.flit_chanel.flit.tail_flag=tail;
+        chan_out.flit_chanel.flit.vc=pck_injct_in.vc;
+        chan_out.flit_chanel.flit_wr=flit_wr;
+        chan_out.flit_chanel.flit.payload = (flit_type == HEADER)? hdr_flit_out[Fpay-1 : 0] : dataIn;
+        chan_out.flit_chanel.congestion = {CONGw{1'b0}};
+        chan_out.flit_chanel.credit= credit_o;
+        chan_out.smart_chanel = {SMART_CHANEL_w{1'b0}};
+        for(int i=0;i<V;i++) chan_out.ctrl_chanel.credit_init_val[i]= LB [CRDTw-1: 0];
+        chan_out.ctrl_chanel.endp_port =1'b1;
+        chan_out.ctrl_chanel.hetero_ovc_presence ={V{1'b1}};
+    end
+    
+    distance_gen the_distance_gen (
+        .src_e_addr(sender_endp_addr_reg[vc_bin]),
+        .dest_e_addr(current_e_addr),
+        .distance(distance)
+    );
+    `ifdef SIMULATION
+    //`define MONITOR_RSV_DAT
+    always @(posedge clk) begin
+        if((pck_injct_in.vc == {V{1'b0}} ) & pck_injct_in.pck_wr )begin
+            $display("%t: ERROR: a packet injection request is recived while vc is not set. %m",$time);
+            $finish;
+        end
+        if(pck_injct_in.pck_wr && (pck_injct_in.size<MIN_PCK_SIZ[PCK_SIZw-1 : 0])) begin
+            $display("%t: ERROR: requested %d flit packet size is smaller than minimum %d flits to send %d bits of data. %m",$time,pck_injct_in.size,MIN_PCK_SIZ, PCK_INJ_Dw );
+            $finish;
+        end
+        `ifdef MONITOR_RSV_DAT
+        if(pck_injct_in.pck_wr) begin
+            $display ("pck_inj(%d) send a packet:  size=%d, data=%h, v=%h",current_id,
+                    pck_injct_in.size, pck_injct_in.data,pck_injct_in.vc);
+        end
+        if(pck_injct_out.pck_wr) begin
+            $display ("pck_inj(%d) got a packet: source=%d, size=%d, data=%h",current_id,
+                    sendor_id,pck_injct_out.size,pck_injct_out.data);
+        end
+        `endif
+    end
+    `endif //SIMULATION
 endmodule
 
-
-
-
 /******************
  *   ovc_status
  *******************/
- 
 module multi_cast_injector_ovc_status #(
-		parameter V     =   4,
-		parameter B =   16,
-		parameter CRDTw =4
-		)
-		(
-   
-		input   [V-1 : 0] [CRDTw-1 : 0 ] credit_init_val_in,
-		input   [V-1            :0] wr_in,
-		input   [V-1            :0] credit_in,
-		output  [V-1            :0] full_vc,
-		output  [V-1            :0] nearly_full_vc,
-		output  [V-1            :0] empty_vc,		
-		input                       clk,
-		input                       reset
-		);
-
- 
-	function integer log2;
-		input integer number; begin   
-			log2=(number <=1) ? 1: 0;    
-			while(2**log2<number) begin    
-				log2=log2+1;    
-			end 	   
-		end   
-	endfunction // log2 
-    
-  
-	localparam  DEPTH_WIDTH =   log2(B+1);
- 
-    
-	reg  [DEPTH_WIDTH-1 : 0] credit    [V-1 : 0];
-	wire  [V-1 : 0] cand_vc_next;
-	
-    
-	genvar i;
-	generate
+    parameter V = 4,
+    parameter B = 16,
+    parameter CRDTw = 4
+    ) (
+    input   [V-1 : 0] [CRDTw-1 : 0 ] credit_init_val_in,
+    input   [V-1 :0] wr_in,
+    input   [V-1 :0] credit_in,
+    output  [V-1 :0] full_vc,
+    output  [V-1 :0] nearly_full_vc,
+    output  [V-1 :0] empty_vc,
+    input clk,
+    input reset
+    );
+    function integer log2;
+        input integer number; begin
+            log2=(number <=1) ? 1: 0;
+            while(2**log2<number) begin
+                log2=log2+1;
+            end
+        end
+    endfunction // log2
+    localparam  DEPTH_WIDTH =   log2(B+1);
+    reg  [DEPTH_WIDTH-1 : 0] credit    [V-1 : 0];
+    wire  [V-1 : 0] cand_vc_next;
+    genvar i;
+    generate
     for(i=0;i<V;i=i+1) begin : vc_loop
-        always @ (`pronoc_clk_reset_edge)begin 
+        always @ (`pronoc_clk_reset_edge)begin
             if(`pronoc_reset)begin
                 credit[i]<= credit_init_val_in[i][DEPTH_WIDTH-1:0];
             end else begin
@@ -499,9 +366,8 @@ module multi_cast_injector_ovc_status #(
                 if( ~wr_in[i]  &&  credit_in[i])   credit[i] <= credit[i]+1'b1;
             end //reset
         end//always
-
         assign  full_vc[i]   = (credit[i] == {DEPTH_WIDTH{1'b0}});
-        assign  nearly_full_vc[i]=  (credit[i] == 1) |  full_vc[i];
+        assign  nearly_full_vc[i]= (credit[i] == 1) | full_vc[i];
         assign  empty_vc[i]  = (credit[i] == credit_init_val_in[i][DEPTH_WIDTH-1:0]);
     end//for
     endgenerate
diff --git a/mpsoc/rtl/src_modelsim/multicast_test.sv b/mpsoc/rtl/src_modelsim/multicast_test.sv
index 61727e1..11c9f1f 100755
--- a/mpsoc/rtl/src_modelsim/multicast_test.sv
+++ b/mpsoc/rtl/src_modelsim/multicast_test.sv
@@ -1,135 +1,102 @@
 // synthesis translate_off
 `include "pronoc_def.v"
 
-
 module multicast_test;
-	
-	parameter NOC_ID=0;
-
-	`NOC_CONF
-	
-	reg     reset ,clk;
-	
-	initial begin 
-		clk = 1'b0;
-		forever clk = #10 ~clk;
-	end 
-	
-	
-	smartflit_chanel_t chan_in_all  [NE-1 : 0];
-	smartflit_chanel_t chan_out_all [NE-1 : 0];
-	
-	pck_injct_t pck_injct_in [NE-1 : 0];
-	pck_injct_t pck_injct_out[NE-1 : 0];
-	
-	
-	noc_top  # ( 
-		.NOC_ID(NOC_ID)
-	) the_noc (
-		.reset(reset),
-		.clk(clk),    
-		.chan_in_all(chan_in_all),
-		.chan_out_all(chan_out_all),
-		.router_event( )
-	);
-		
-	reg [NEw-1 : 0] dest_id [NE-1 : 0];
-	wire [NEw-1: 0] current_e_addr [NE-1 : 0];
-		
-	genvar i;
-	generate 
-	for(i=0; i< NE; i=i+1) begin : endpoints
-		
-		endp_addr_encoder #( .TOPOLOGY(TOPOLOGY), .T1(T1), .T2(T2), .T3(T3), .EAw(EAw),  .NE(NE)) encode1 ( .id(i[NEw-1 :0]), .code(current_e_addr[i]));
-		
-		multicast_injector #(
-			.NOC_ID(NOC_ID)
-		) pck_inj(
-			//general
-			.current_e_addr(current_e_addr[i]),
-			.reset(reset),
-			.clk(clk),		
-   			//noc port
-			.chan_in(chan_out_all[i]),
-			.chan_out(chan_in_all[i]),  
-			//control interafce
-			.pck_injct_in(pck_injct_in[i]),
-			.pck_injct_out(pck_injct_out[i])		
-		);			
-	
-
-		endp_addr_encoder #( .TOPOLOGY(TOPOLOGY), .T1(T1), .T2(T2), .T3(T3), .EAw(EAw),  .NE(NE)) encode2 ( .id(dest_id[i]), .code(pck_injct_in[i].endp_addr[EAw-1 : 0]));
-		
-		
-	   reg [31:0]k;
-
+    
+    import pronoc_pkg::*;
+    
+    reg  reset ,clk;
+    
     initial begin 
+        clk = 1'b0;
+        forever clk = #10 ~clk;
+    end 
+    
+    
+    smartflit_chanel_t chan_in_all  [NE-1 : 0];
+    smartflit_chanel_t chan_out_all [NE-1 : 0];
+    
+    pck_injct_t pck_injct_in [NE-1 : 0];
+    pck_injct_t pck_injct_out[NE-1 : 0];
+    
+    
+    noc_top  the_noc (
+        .reset(reset),
+        .clk(clk),    
+        .chan_in_all(chan_in_all),
+        .chan_out_all(chan_out_all),
+        .router_event( )
+    );
+    
+    reg [NEw-1 : 0] dest_id [NE-1 : 0];
+    wire [NEw-1: 0] current_e_addr [NE-1 : 0];
+    
+    genvar i;
+    generate 
+    for(i=0; i< NE; i=i+1) begin : endpoints
+        
+        endp_addr_encoder encode1 ( .id_in(i[NEw-1 :0]), .code_out(current_e_addr[i]));
+        
+        multicast_injector  pck_inj(
+            //general
+            .current_e_addr(current_e_addr[i]),
+            .reset(reset),
+            .clk(clk),
+               //noc port
+            .chan_in(chan_out_all[i]),
+            .chan_out(chan_in_all[i]),  
+            //control interafce
+            .pck_injct_in(pck_injct_in[i]),
+            .pck_injct_out(pck_injct_out[i])
+        );
+        
+        endp_addr_encoder encode2 ( .id_in(dest_id[i]), .code_out(pck_injct_in[i].endp_addr[EAw-1 : 0]));
+        
+        reg [31:0]k;
+
+        initial begin 
 `ifdef ACTIVE_LOW_RESET_MODE 
         reset = 1'b0;
  `else 
         reset = 1'b1;
 `endif  
-			k=0;
-			pck_injct_in[i].data =0;
-			#10
-			pck_injct_in[i].class_num=0; 
-			pck_injct_in[i].init_weight=1;
-			pck_injct_in[i].vc=1;
-			pck_injct_in[i].pck_wr=1'b0; 
-			#100
-			@(posedge clk) #1;
-			reset=~reset;
-			#100
-			@(posedge clk) #1;
-			//if(i==1) begin 
-			//	repeat(10) begin 
-					while (pck_injct_out[i].ready[0] == 1'b0) @(posedge clk)   #1;
-						
-					pck_injct_in[i].data='h123456789ABCDEFEDCBA987654321+k;
-					pck_injct_in[i].size=3+(k%18);
-					dest_id[i]=0;				
-					pck_injct_in[i].pck_wr=1'b1;  	
-					@(posedge clk)	#1 k++;
-					pck_injct_in[i].pck_wr=1'b0;
-					@(posedge clk)	#1 k++;
-
-			//	end
-
-				#10000
-			@(posedge clk) $stop;
-
-			//end
-			
-			
-			
-			
-			
-			
-		end
-		
-		always @(posedge clk) begin
-			if(pck_injct_out[i].pck_wr) begin 
-				$display ("%t:pck_inj(%d) got a packet: source=%d, size=%d, data=%h",$time,i,
-						pck_injct_out[i].endp_addr,pck_injct_out[i].size,pck_injct_out[i].data);
-			end		
-			
-		end
-		
-	
-	  
-	end//for
-	endgenerate
-       
-	
-
-
-
-	
-	
-
-	
-	
-
+            k=0;
+            pck_injct_in[i].data =0;
+            #10
+            pck_injct_in[i].class_num=0; 
+            pck_injct_in[i].init_weight=1;
+            pck_injct_in[i].vc=1;
+            pck_injct_in[i].pck_wr=1'b0; 
+            #100
+            @(posedge clk) #1;
+            reset=~reset;
+            #100
+            @(posedge clk) #1;
+            //if(i==1) begin 
+            //    repeat(10) begin 
+                    while (pck_injct_out[i].ready[0] == 1'b0) @(posedge clk)   #1;
+                        
+                    pck_injct_in[i].data='h123456789ABCDEFEDCBA987654321+k;
+                    pck_injct_in[i].size=3+(k%18);
+                    dest_id[i]=0;
+                    pck_injct_in[i].pck_wr=1'b1;
+                    @(posedge clk)    #1 k++;
+                    pck_injct_in[i].pck_wr=1'b0;
+                    @(posedge clk)    #1 k++;
+            //    end
+                #10000
+            @(posedge clk) $stop;
+            //end
+        end
+        
+        always @(posedge clk) begin
+            if(pck_injct_out[i].pck_wr) begin 
+                $display ("%t:pck_inj(%d) got a packet: source=%d, size=%d, data=%h",$time,i,
+                        pck_injct_out[i].endp_addr,pck_injct_out[i].size,pck_injct_out[i].data);
+            end
+        end
+    end//for
+    endgenerate
 endmodule
 // synthesis translate_on
 
diff --git a/mpsoc/rtl/src_modelsim/noc_sim_statistic.sv b/mpsoc/rtl/src_modelsim/noc_sim_statistic.sv
index ba2ede4..005b25c 100755
--- a/mpsoc/rtl/src_modelsim/noc_sim_statistic.sv
+++ b/mpsoc/rtl/src_modelsim/noc_sim_statistic.sv
@@ -1,129 +1,114 @@
-// synthesis translate_off
-`timescale   1ns/1ns
 `include "pronoc_def.v"
-module routers_statistic_collector #(
-	parameter NOC_ID=0
-)(
-	reset,
-	clk,		
-	router_event,
-	print
-);
-  
-	`NOC_CONF
-  	
-	input   clk,reset;
-	input   router_event_t  router_event [NR-1 : 0][MAX_P-1 : 0];
-	input   print;
- 	
-	typedef struct   {
-		integer pck_num_in;
-		integer flit_num_in;
-		integer pck_num_out;
-		integer flit_num_out;
-		integer flit_num_in_bypassed;
-		integer flit_num_in_buffered;
-		integer bypass_counter [SMART_NUM : 0];
-	} router_stat_t;
-	
-	
-	
-	task  reset_router_stat;
-		output  router_stat_t stat_in;
-		integer k;
-		begin
-			stat_in.pck_num_in=0;
-			stat_in.flit_num_in=0;
-			stat_in.pck_num_out=0;
-			stat_in.flit_num_out=0;
-			stat_in.flit_num_in_bypassed=0;
-			stat_in.flit_num_in_buffered=0;
-			for (k=0;k<SMART_NUM+1;k++) stat_in.bypass_counter[k]=0;
-		end
-	endtask
-	
-	task print_router_st;
-		input router_stat_t stat_in;
-		integer k;
-		begin 
-			$write("%0d,", stat_in.flit_num_in);
-			$write("%0d,", stat_in.pck_num_in);
-			$write("%0d,", stat_in.flit_num_out);
-			$write("%0d,", stat_in.pck_num_out);
-			$write("%0d,", stat_in.flit_num_in_buffered);
-			$write("%0d,", stat_in.flit_num_in_bypassed);	
-			if(SMART_MAX>0) for (k=0;k<SMART_MAX+1;k++) $write("%0d,",stat_in.bypass_counter[k]);
-			$write("\n");
-		end
-	endtask
-
-	router_stat_t router_stat [NR][MAX_P];
-	router_stat_t router_stat_accum [NR];	
-	
-	integer r,p;
-	initial begin 
-		for(r=0;r<NR;r++) begin
-			reset_router_stat(router_stat_accum[r]);	
-			for (p=0;p<MAX_P;p++)begin			
-				reset_router_stat(router_stat[r][p]);						
-			end//p	
-		end//r
-	end//init
+`ifdef SIMULATION
 
-	
-	
-	always @ (posedge clk) begin 
-		for(r=0;r<NR;r++) begin			
-			for (p=0;p<MAX_P;p++)begin
-				if( router_event[r][p].flit_wr_i ) 	router_stat[r][p].flit_num_in++;			
-				if( router_event[r][p].pck_wr_i  ) router_stat[r][p].pck_num_in++;
-				if( router_event[r][p].flit_wr_o ) router_stat[r][p].flit_num_out++;
-				if( router_event[r][p].pck_wr_o  ) router_stat[r][p].pck_num_out++;
-				if(	router_event[r][p].flit_in_bypassed) router_stat[r][p].flit_num_in_bypassed++;
-				else if( router_event[r][p].flit_wr_i) begin 
-					router_stat [r][p].flit_num_in_buffered++;
-					router_stat[r][p].bypass_counter[router_event[r][p].bypassed_num]++;
-				end
-				     
-			end//p	
-		end//r		
-	end//always
-	
-	
-	
-	integer k;
-	
-	always @(posedge print) begin 
-		for(r=0;r<NR;r++) begin		
-			for (p=0;p<MAX_P;p++)begin
-				router_stat_accum[r].pck_num_in+=		   router_stat[r][p].pck_num_in;                  
-				router_stat_accum[r].flit_num_in+=         router_stat[r][p].flit_num_in;                 
-				router_stat_accum[r].pck_num_out+=         router_stat[r][p].pck_num_out;                 
-				router_stat_accum[r].flit_num_out+=        router_stat[r][p].flit_num_out;                
-				router_stat_accum[r].flit_num_in_bypassed+=router_stat[r][p].flit_num_in_bypassed;        
-				router_stat_accum[r].flit_num_in_buffered+=router_stat[r][p].flit_num_in_buffered;        	
-				for (k=0;k<SMART_MAX+1;k++) router_stat_accum[r].bypass_counter[k]+=router_stat[r][p].bypass_counter[k];   
-				
-			end//p
-		end//r
-		
-		
-		//report router statistic
-		$display("\n\tRouters' statistics");
-		$write("\t#RID, #Port,flit_in,pck_in,flit_out,pck_out,flit_in_buffered,flit_in_bypassed,");
-		if(SMART_MAX>0) for (k=0;k<SMART_MAX+1;k++) $write("bypsd_%0d_times,",k);
-		$write("\n");		
-		for(r=0;r<NR;r++) begin	
-			for (p=0;p<MAX_P;p++)begin
-				$write("\t%0d,%0d,",r,p);
-				print_router_st(router_stat [r][p]);
-			end//p
-			$write("\t%0d,total,",r);
-			print_router_st(router_stat_accum [r]);
-		end	//r	
-	end//always
-	
-	
-	
+module routers_statistic_collector (
+    reset,
+    clk,
+    router_event,
+    print
+);
+    import pronoc_pkg::*;
+    
+    input   clk,reset;
+    input   router_event_t  router_event [NR-1 : 0][MAX_P-1 : 0];
+    input   print;
+    
+    typedef struct   {
+        integer pck_num_in;
+        integer flit_num_in;
+        integer pck_num_out;
+        integer flit_num_out;
+        integer flit_num_in_bypassed;
+        integer flit_num_in_buffered;
+        integer bypass_counter [SMART_NUM : 0];
+    } router_stat_t;
+    
+    task  reset_router_stat;
+        output  router_stat_t stat_in;
+        integer k;
+        begin
+            stat_in.pck_num_in=0;
+            stat_in.flit_num_in=0;
+            stat_in.pck_num_out=0;
+            stat_in.flit_num_out=0;
+            stat_in.flit_num_in_bypassed=0;
+            stat_in.flit_num_in_buffered=0;
+            for (k=0;k<SMART_NUM+1;k++) stat_in.bypass_counter[k]=0;
+        end
+    endtask
+    
+    task print_router_st;
+        input router_stat_t stat_in;
+        integer k;
+        begin 
+            $write("%0d,", stat_in.flit_num_in);
+            $write("%0d,", stat_in.pck_num_in);
+            $write("%0d,", stat_in.flit_num_out);
+            $write("%0d,", stat_in.pck_num_out);
+            $write("%0d,", stat_in.flit_num_in_buffered);
+            $write("%0d,", stat_in.flit_num_in_bypassed);    
+            if(SMART_MAX>0) for (k=0;k<SMART_MAX+1;k++) $write("%0d,",stat_in.bypass_counter[k]);
+            $write("\n");
+        end
+    endtask
+    
+    router_stat_t router_stat [NR][MAX_P];
+    router_stat_t router_stat_accum [NR];    
+    
+    integer r,p;
+    initial begin 
+        for(r=0;r<NR;r++) begin
+            reset_router_stat(router_stat_accum[r]);    
+            for (p=0;p<MAX_P;p++)begin            
+                reset_router_stat(router_stat[r][p]);                        
+            end//p    
+        end//r
+    end//init
+    
+    always @ (posedge clk) begin 
+        for(r=0;r<NR;r++) begin            
+            for (p=0;p<MAX_P;p++)begin
+                if( router_event[r][p].flit_wr_i )     router_stat[r][p].flit_num_in++;            
+                if( router_event[r][p].pck_wr_i  ) router_stat[r][p].pck_num_in++;
+                if( router_event[r][p].flit_wr_o ) router_stat[r][p].flit_num_out++;
+                if( router_event[r][p].pck_wr_o  ) router_stat[r][p].pck_num_out++;
+                if(    router_event[r][p].flit_in_bypassed) router_stat[r][p].flit_num_in_bypassed++;
+                else if( router_event[r][p].flit_wr_i) begin 
+                    router_stat [r][p].flit_num_in_buffered++;
+                    router_stat[r][p].bypass_counter[router_event[r][p].bypassed_num]++;
+                end
+            end//p    
+        end//r        
+    end//always   
+    
+    integer k;
+    always @(posedge print) begin 
+        for(r=0;r<NR;r++) begin        
+            for (p=0;p<MAX_P;p++)begin
+                router_stat_accum[r].pck_num_in+=           router_stat[r][p].pck_num_in;                  
+                router_stat_accum[r].flit_num_in+=         router_stat[r][p].flit_num_in;                 
+                router_stat_accum[r].pck_num_out+=         router_stat[r][p].pck_num_out;                 
+                router_stat_accum[r].flit_num_out+=        router_stat[r][p].flit_num_out;                
+                router_stat_accum[r].flit_num_in_bypassed+=router_stat[r][p].flit_num_in_bypassed;        
+                router_stat_accum[r].flit_num_in_buffered+=router_stat[r][p].flit_num_in_buffered;            
+                for (k=0;k<SMART_MAX+1;k++) router_stat_accum[r].bypass_counter[k]+=router_stat[r][p].bypass_counter[k];   
+                
+            end//p
+        end//r
+        //report router statistic
+        $write("\n"); 
+        $display("\n\tRouters Statistics:");
+        $write("\t#RID, #Port,flit_in,pck_in,flit_out,pck_out,flit_in_buffered,flit_in_bypassed,");
+        if(SMART_MAX>0) for (k=0;k<SMART_MAX+1;k++) $write("bypsd_%0d_times,",k);
+        $write("\n");        
+        for(r=0;r<NR;r++) begin    
+            for (p=0;p<MAX_P;p++)begin
+                $write("\t%0d,%0d,",r,p);
+                print_router_st(router_stat [r][p]);
+            end//p
+            $write("\t%0d,total,",r);
+            print_router_st(router_stat_accum [r]);
+        end    //r    
+    end//always
 endmodule
-// synthesis translate_on
+`endif
\ No newline at end of file
diff --git a/mpsoc/rtl/src_modelsim/pck_injector_test.sv b/mpsoc/rtl/src_modelsim/pck_injector_test.sv
index 2a2461e..74b8d84 100755
--- a/mpsoc/rtl/src_modelsim/pck_injector_test.sv
+++ b/mpsoc/rtl/src_modelsim/pck_injector_test.sv
@@ -2,137 +2,101 @@
 `include "pronoc_def.v"
 
 module pck_injector_test;
-	parameter NOC_ID=0;
-    `NOC_CONF
-	
-	reg     reset ,clk;
-	
-	initial begin 
-		clk = 1'b0;
-		forever clk = #10 ~clk;
-	end 
-
-	initial begin 
+    import pronoc_pkg::*;
+    reg  reset ,clk;
+    
+    initial begin 
+        clk = 1'b0;
+        forever clk = #10 ~clk;
+    end 
+    
+    initial begin 
 `ifdef ACTIVE_LOW_RESET_MODE 
-        	reset = 1'b0;
- `else 
-        	reset = 1'b1;
+            reset = 1'b0;
+`else 
+            reset = 1'b1;
 `endif  
-		#110;
-        	@(posedge clk) #1;
-		reset=~reset;
-	end
-	
-	
-       smartflit_chanel_t chan_in_all  [NE-1 : 0];
-	smartflit_chanel_t chan_out_all [NE-1 : 0];
-	
-	pck_injct_t pck_injct_in [NE-1 : 0];
-	pck_injct_t pck_injct_out[NE-1 : 0];	
-	noc_top  # ( 
-		.NOC_ID(NOC_ID)
-	) the_noc (
-		.reset(reset),
-		.clk(clk),    
-		.chan_in_all(chan_in_all),
-		.chan_out_all(chan_out_all),
-		.router_event( )
-	);
-		
-	reg  [NEw-1 : 0] dest_id [NE-1 : 0];
-	wire [NEw-1 : 0] src_id  [NE-1 : 0];
-	wire [NEw-1: 0] current_e_addr [NE-1 : 0];
-		
-	genvar i;
-	generate 
-	for(i=0; i< NE; i=i+1) begin : endpoints
-		
-		endp_addr_encoder #( .TOPOLOGY(TOPOLOGY), .T1(T1), .T2(T2), .T3(T3), .EAw(EAw),  .NE(NE)) encode1 ( .id(i[NEw-1 :0]), .code(current_e_addr[i]));
-		
-		packet_injector #(
-			.NOC_ID(NOC_ID)
-		) pck_inj (
-			//general
-			.current_e_addr(current_e_addr[i]),
-			.reset(reset),
-			.clk(clk),		
-   			//noc port
-			.chan_in(chan_out_all[i]),
-			.chan_out(chan_in_all[i]),  
-			//control interafce
-			.pck_injct_in(pck_injct_in[i]),
-			.pck_injct_out(pck_injct_out[i])		
-		);			
-	
-
-		endp_addr_encoder #( .TOPOLOGY(TOPOLOGY), .T1(T1), .T2(T2), .T3(T3), .EAw(EAw),  .NE(NE)) encode2 ( .id(dest_id[i]), .code(pck_injct_in[i].endp_addr));
-		
-		
-	   reg [31:0]k;
-
-		initial begin 
-			k=0;
-			pck_injct_in[i].data =0;
-			#10
-			pck_injct_in[i].class_num=0; 
-			pck_injct_in[i].init_weight=1;
-			pck_injct_in[i].vc=1;
-			pck_injct_in[i].pck_wr=1'b0; 
-			#100;
-			@(posedge clk) #1;
-			#100;
-			@(posedge clk) #1;
-			if(i==1) begin 
-				repeat(10) begin 
-					while (pck_injct_out[i].ready[0] == 1'b0) @(posedge clk)   #1;
-						
-					pck_injct_in[i].data='h123456789ABCDEFEDCBA987654321+k;
-					pck_injct_in[i].size=3+(k%18);
-					dest_id[i]=0;				
-					pck_injct_in[i].pck_wr=1'b1;  	
-					@(posedge clk)	#1 k++;
-					pck_injct_in[i].pck_wr=1'b0;
-					@(posedge clk)	#1 k++;
-
-				end
-
-				#8000
-			@(posedge clk) $stop;
-
-			end
-			
-			
-			
-			
-			
-			
-		end
-		
-		endp_addr_decoder  #(   .TOPOLOGY(TOPOLOGY), .T1(T1), .T2(T2), .T3(T3), .EAw(EAw),  .NE(NE)) decode1 ( .id(src_id[i]), .code(pck_injct_out[i].endp_addr));    
-		
-		always @(posedge clk) begin
-			if(pck_injct_out[i].pck_wr) begin 
-				$display ("%t:pck_inj(%d) got a packet from source_id=%d, with size=%d flits and data=%h",$time,i,
-						src_id[i],pck_injct_out[i].size,pck_injct_out[i].data);
-			end		
-			
-		end
-		
-	
-	  
-	end//for
-	endgenerate
-       
-	
-
-
-
-	
-	
-
-	
-	
-
+        #110;
+            @(posedge clk) #1;
+        reset=~reset;
+    end
+    
+    smartflit_chanel_t chan_in_all  [NE-1 : 0];
+    smartflit_chanel_t chan_out_all [NE-1 : 0];
+    
+    pck_injct_t pck_injct_in [NE-1 : 0];
+    pck_injct_t pck_injct_out[NE-1 : 0];    
+    noc_top  the_noc (
+        .reset(reset),
+        .clk(clk),    
+        .chan_in_all(chan_in_all),
+        .chan_out_all(chan_out_all),
+        .router_event( )
+    );
+        
+    reg  [NEw-1 : 0] dest_id [NE-1 : 0];
+    wire [NEw-1 : 0] src_id  [NE-1 : 0];
+    wire [NEw-1: 0] current_e_addr [NE-1 : 0];
+        
+    genvar i;
+    generate 
+    for(i=0; i< NE; i=i+1) begin : endpoints
+        
+        endp_addr_encoder encode1 ( .id_in(i[NEw-1 :0]), .code_out(current_e_addr[i]));
+        
+        packet_injector pck_inj (
+            //general
+            .current_e_addr(current_e_addr[i]),
+            .reset(reset),
+            .clk(clk),        
+               //noc port
+            .chan_in(chan_out_all[i]),
+            .chan_out(chan_in_all[i]),  
+            //control interafce
+            .pck_injct_in(pck_injct_in[i]),
+            .pck_injct_out(pck_injct_out[i])        
+        );
+        endp_addr_encoder encode2 ( .id_in(dest_id[i]), .code_out(pck_injct_in[i].endp_addr));
+        reg [31:0]k;
+        initial begin 
+            k=0;
+            pck_injct_in[i].data =0;
+            #10
+            pck_injct_in[i].class_num=0; 
+            pck_injct_in[i].init_weight=1;
+            pck_injct_in[i].vc=1;
+            pck_injct_in[i].pck_wr=1'b0; 
+            #100;
+            @(posedge clk) #1;
+            #100;
+            @(posedge clk) #1;
+            if(i==1) begin 
+                repeat(10) begin 
+                    while (pck_injct_out[i].ready[0] == 1'b0) @(posedge clk)   #1;
+                    
+                    pck_injct_in[i].data='h123456789ABCDEFEDCBA987654321+k;
+                    pck_injct_in[i].size=3+(k%18);
+                    dest_id[i]=0;                
+                    pck_injct_in[i].pck_wr=1'b1;      
+                    @(posedge clk)    #1 k++;
+                    pck_injct_in[i].pck_wr=1'b0;
+                    @(posedge clk)    #1 k++;
+                end
+                #8000
+            @(posedge clk) $stop;
+            end
+        end
+        
+        endp_addr_decoder decode1 ( .id_out(src_id[i]), .code_in(pck_injct_out[i].endp_addr));
+        
+        always @(posedge clk) begin
+            if(pck_injct_out[i].pck_wr) begin 
+                $display ("%t:pck_inj(%d) got a packet from source_id=%d, with size=%d flits and data=%h",$time,i,
+                        src_id[i],pck_injct_out[i].size,pck_injct_out[i].data);
+            end
+        end
+    end//for
+    endgenerate
 endmodule
 // synthesis translate_on
 
diff --git a/mpsoc/rtl/src_modelsim/testbench_noc.sv b/mpsoc/rtl/src_modelsim/testbench_noc.sv
index a3d212d..24bfabb 100755
--- a/mpsoc/rtl/src_modelsim/testbench_noc.sv
+++ b/mpsoc/rtl/src_modelsim/testbench_noc.sv
@@ -1,915 +1,708 @@
-// synthesis translate_off
 `include "pronoc_def.v"
+`ifdef SIMULATION
 
 `define STND_DEV_EN
 
 module testbench_noc;
-	parameter NOC_ID=0;
-	`NOC_CONF
-	 
-	`define INCLUDE_SIM_PARAM
-	`include "sim_param.sv" //will be generated by ProNoC GUI
-	// simulation parameter setting
-	// injected packet class percentage
-	localparam 
-		C0_p=100,
-		C1_p=0,
-		C2_p=0,
-		C3_p=0;
-				
-	
-	localparam RATIOw=$clog2(100);
-   
-
-	reg     reset ,clk;
-	reg     start,stop;
-	wire    sent_done;
-	reg    done;
-	reg [RATIOw-1:0] ratio;
-
-	
-
-
-	initial begin 
-		clk = 1'b0;
-		forever clk = #10 ~clk;
-	end 
-
-	
-
-	initial begin 
-`ifdef ACTIVE_LOW_RESET_MODE 
+    
+    import pronoc_pkg::*;
+    
+    `define INCLUDE_SIM_PARAM
+    `include "sim_param.sv" //will be generated by ProNoC GUI
+    // simulation parameter setting
+    // injected packet class percentage
+    localparam 
+        C0_p=100,
+        C1_p=0,
+        C2_p=0,
+        C3_p=0;
+    
+    localparam RATIOw=$clog2(100);
+    
+    reg     reset ,clk;
+    reg     start,stop;
+    wire    sent_done;
+    reg    done;
+    reg [RATIOw-1:0] ratio;
+    
+    initial begin 
+        clk = 1'b0;
+        forever clk = #10 ~clk;
+    end 
+    
+    initial begin 
+    `ifdef ACTIVE_LOW_RESET_MODE 
         reset = 1'b0;
- `else 
+    `else 
         reset = 1'b1;
-`endif  
-		
-		start = 1'b0;
-		stop  = 1'b0;
-		ratio =INJRATIO;
-		#80
-		@(posedge clk) reset = ~reset;
-		#200
-		@(posedge clk) start = 1'b1;
-		@(posedge clk) start = 1'b0;
-		@(posedge sent_done) 
-		stop=1;//stop all packet injectprs
-		@(posedge done) //wait for all sent flits to be received at their destination
-		#450
-		@(posedge clk)
-		$stop;
-	end
-	
-	  
-	localparam     
-	/* verilator lint_off WIDTH */
-            	/* verilator lint_on WIDTH */
-                    
-		
-                    
-
-		PCK_CNTw=   $clog2(MAX_PCK_NUM+1),
-		CLK_CNTw=   $clog2(MAX_SIM_CLKs+1),
-		
-		AVG_PCK_SIZ = (MAX_PACKET_SIZE + MIN_PACKET_SIZE)/2 ;
-                   
-                    
+    `endif  
+        start = 1'b0;
+        stop  = 1'b0;
+        ratio =INJRATIO;
+        #80
+        @(posedge clk) reset = ~reset;
+        #200
+        @(posedge clk) start = 1'b1;
+        @(posedge clk) start = 1'b0;
+        @(posedge sent_done) 
+        stop=1;//stop all packet injectprs
+        @(posedge done) //wait for all sent flits to be received at their destination
+        #450
+        @(posedge clk)
+        $stop;
+    end
+    
+    localparam     
+        PCK_CNTw=   $clog2(MAX_PCK_NUM+1),
+        CLK_CNTw=   $clog2(MAX_SIM_CLKs+1),
+        AVG_PCK_SIZ = (MAX_PACKET_SIZE + MIN_PACKET_SIZE)/2 ;
+        
     typedef struct  {
-		logic [PCK_CNTw-1     :0] pck_num;
-		integer flit_num;
-		integer worst_latency;
-		integer min_latency;
-		real sum_clk_h2h;
-		real sum_clk_h2t;
-		real sum_clk_per_hop;
-`ifdef STND_DEV_EN
-		real sum_clk_pow2;
-`endif
-	} statistic_t;
-   
-
-	typedef struct  { 
-		real avg_latency_per_hop;
-		real avg_latency_flit;
-		real avg_latency_pck;
-		real avg_throughput;
-		real avg_pck_siz;
-`ifdef STND_DEV_EN
-		real std_dev;
-`endif
-	} avg_st_t;
-
-	integer m,c;
-	localparam STAT_NUM= (C==0)? 1 : C;
-	statistic_t sent_stat [NE][STAT_NUM];
-	statistic_t rsvd_stat [NE][STAT_NUM];	
-	statistic_t sent_stat_class [NE];
-	statistic_t rsvd_stat_class [NE];
-	statistic_t sent_stat_per_class [STAT_NUM];
-	statistic_t rsvd_stat_per_class [STAT_NUM];
-	statistic_t rsvd_stat_total;
-	statistic_t sent_stat_total;
-
-	initial begin 
-		reset_st (rsvd_stat_total);
-		reset_st (sent_stat_total);
-		for(m=0;m<NE;m++) begin
-			for (c=0;c<STAT_NUM;c++)begin			
-				reset_st(sent_stat[m][c]);
-				reset_st(rsvd_stat[m][c]);			
-			end
-			reset_st(rsvd_stat_class[m]);
-			reset_st(sent_stat_class[m]);
-		end
-		for (c=0; c<STAT_NUM;c++)begin 
-			reset_st(sent_stat_per_class [c]);
-			reset_st(rsvd_stat_per_class [c]);
-		end			
-	end
-
-	
-	task  reset_st;
-		output  statistic_t stat_in;
-		begin
-			stat_in.pck_num={PCK_CNTw{1'b0}};
-			stat_in.flit_num=0;
-			stat_in.worst_latency=0;
-			stat_in.min_latency=0;
-			stat_in.sum_clk_h2h=0;
-			stat_in.sum_clk_h2t=0;
-			stat_in.sum_clk_per_hop=0;
-	`ifdef STND_DEV_EN
-			stat_in.sum_clk_pow2=0;
-	`endif
-		end
-	endtask
-	
-
-
+        logic [PCK_CNTw-1 :0] pck_num;
+        integer flit_num;
+        integer worst_latency;
+        integer min_latency;
+        real sum_clk_h2h;
+        real sum_clk_h2t;
+        real sum_clk_per_hop;
+    `ifdef STND_DEV_EN
+        real sum_clk_pow2;
+    `endif
+    } statistic_t;
+    
+    typedef struct  { 
+        real avg_latency_per_hop;
+        real avg_latency_flit;
+        real avg_latency_pck;
+        real avg_throughput;
+        real avg_pck_siz;
+    `ifdef STND_DEV_EN
+        real std_dev;
+    `endif
+    } avg_st_t;
+    
+    integer m,c;
+    localparam STAT_NUM= (C==0)? 1 : C;
+    statistic_t sent_stat [NE][STAT_NUM];
+    statistic_t rsvd_stat [NE][STAT_NUM];    
+    statistic_t sent_stat_class [NE];
+    statistic_t rsvd_stat_class [NE];
+    statistic_t sent_stat_per_class [STAT_NUM];
+    statistic_t rsvd_stat_per_class [STAT_NUM];
+    statistic_t rsvd_stat_total;
+    statistic_t sent_stat_total;
+    statistic_t endp_to_endp[NE][NE];
+    
+    task  update_rsvd_st(
+        inout statistic_t rsvd_stat,
+        input int clk_num_h2h,
+        input int clk_num_h2t,
+        input int latency,
+        input int distance//,
+        //input int pck_size
+    );
+    begin
+        rsvd_stat.pck_num++;
+        //rsvd_stat.flit_num += pck_size;
+        rsvd_stat.sum_clk_h2h += real'(clk_num_h2h);
+        rsvd_stat.sum_clk_h2t += real'(clk_num_h2t);
+        rsvd_stat.sum_clk_per_hop += (distance != 0) ? (real'(clk_num_h2h) / real'(distance)) : 0.0;
+        rsvd_stat.worst_latency = (rsvd_stat.worst_latency < latency) ? latency : rsvd_stat.worst_latency;
+        if (rsvd_stat.min_latency == 0 || rsvd_stat.min_latency > latency) begin
+            rsvd_stat.min_latency = latency;
+        end
+        `ifdef STND_DEV_EN
+        rsvd_stat.sum_clk_pow2 += real'(clk_num_h2h) * real'(clk_num_h2h);
+        `endif
+    end
+    endtask
+    
+    task print_endp_to_endp_st(string st);
+    $write("\n\tEndp_to_Endp %s:\n\t#EID,", st);    
+    // Print header row
+    for (int src = 0; src < NE; src++) 
+        $write("%0d,", src);
+    $display("");
+    // Print data rows
+    for (int src = 0; src < NE; src++) begin
+        $write("\t%0d,", src);
+        for (int dst = 0; dst < NE; dst++) begin
+            if (st == "pck_num") 
+                $write("%0d,", endp_to_endp[src][dst].pck_num);
+            else if (st == "flit_num") 
+                $write("%0d,", endp_to_endp[src][dst].flit_num);
+        end
+        $display("");
+    end
+    endtask
+    
+    task update_send_st (
+        inout statistic_t sent_stat,
+        input int latency
+    );
+    begin
+        sent_stat.worst_latency = (sent_stat.worst_latency < latency) ? latency : sent_stat.worst_latency;
+        if ((sent_stat.min_latency == 0)  || (sent_stat.min_latency > latency)) begin 
+            sent_stat.min_latency = latency;
+        end
+    end
+    endtask
+    
+    initial begin 
+        reset_st (rsvd_stat_total);
+        reset_st (sent_stat_total);
+        for(m=0;m<NE;m++) begin
+            for (c=0;c<STAT_NUM;c++)begin
+                reset_st(sent_stat[m][c]);
+                reset_st(rsvd_stat[m][c]);
+            end
+            reset_st(rsvd_stat_class[m]);
+            reset_st(sent_stat_class[m]);
+            for (c=0;c<NE;c++)begin
+                reset_st(endp_to_endp[m][c]);
+            end
+        end
+        for (c=0; c<STAT_NUM;c++)begin 
+            reset_st(sent_stat_per_class [c]);
+            reset_st(rsvd_stat_per_class [c]);
+        end            
+    end
+    
+    task  reset_st;
+        output  statistic_t stat_in;
+        begin
+            stat_in.pck_num={PCK_CNTw{1'b0}};
+            stat_in.flit_num=0;
+            stat_in.worst_latency=0;
+            stat_in.min_latency=0;
+            stat_in.sum_clk_h2h=0;
+            stat_in.sum_clk_h2t=0;
+            stat_in.sum_clk_per_hop=0;
+    `ifdef STND_DEV_EN
+            stat_in.sum_clk_pow2=0;
+    `endif
+        end
+    endtask
+    
     reg print_router_st;
+    smartflit_chanel_t chan_in_all  [NE-1 : 0];
+    smartflit_chanel_t chan_out_all [NE-1 : 0];
+    router_event_t router_event [NR-1 : 0] [MAX_P-1 : 0];
     
-	smartflit_chanel_t chan_in_all  [NE-1 : 0];
-	smartflit_chanel_t chan_out_all [NE-1 : 0];
-	router_event_t router_event [NR-1 : 0] [MAX_P-1 : 0];
-    
-    
-    
-   
-	wire [NE-1      :   0]  hdr_flit_sent;
-	wire [DAw-1     :   0]  dest_e_addr             [NE-1           :0];  
-	wire [EAw-1     :   0]  src_e_addr				[NE-1           :0]; 
-	wire [Cw-1      :   0]  pck_class_in            [NE-1           :0]; 
-	wire [Cw-1      :   0]  flit_out_class          [NE-1           :0]; 
-	wire [NEw-1     :   0]  src_id					[NE-1           :0]; 
-    
-	wire [PCK_SIZw-1:   0] pck_size_in [NE-1        :0]; 
-	wire [PCK_SIZw-1:   0] pck_size_o  [NE-1        :0];   
-        wire [NEw-1 : 0] mcast_dst_num [NE-1        :0];   
-    
-	//   wire    [NE-1           :0] report;
-	reg     [CLK_CNTw-1             :0] clk_counter;
-    
-    
- 
-	wire    [PCK_CNTw-1     :0] pck_counter     [NE-1        :0];
-	wire    [NE-1           :0] noc_report;
-	wire    [NE-1           :0] update;
-	wire    [CLK_CNTw-1     :0] time_stamp_h2t  [NE-1           :0];
-	wire    [CLK_CNTw-1     :0] time_stamp_h2h  [NE-1           :0];
-	wire    [DISTw-1         :0] distance        [NE-1           :0];    
-	wire    [Cw-1           :0] pck_class_out       [NE-1           :0];    
-    
-	reg                         count_en;
-  	//reg [NE-1 : 0] start_o;
-  	logic [DELAYw-1 : 0] start_delay [NE-1 : 0];
-  	
-  
-  	
-  	
-  	integer  rsv_size_array [MAX_PACKET_SIZE - MIN_PACKET_SIZE : 0];
-  		
-  	
-    
-	always @(`pronoc_clk_reset_edge) begin 
-		if (`pronoc_reset) begin 
-			count_en <=1'b0;
-		end else begin 
-			if(start) count_en <=1'b1;
-			else if(noc_report) count_en <=1'b0;
-		end 
-	end//always
-    
-       
-	noc_top  #( 
-		.NOC_ID(NOC_ID)
-	) the_noc (
-		.reset(reset),
-		.clk(clk),    
-		.chan_in_all(chan_in_all),
-		.chan_out_all(chan_out_all),
-		.router_event(router_event)
-	);
-          
-      
-    
-	always @ (`pronoc_clk_reset_edge)begin 
-		if (`pronoc_reset  ) begin clk_counter  <= 0;  end
-		else  begin 
-			if  (count_en) clk_counter  <= clk_counter+1'b1;    
-	        
-		end
-	end
-    
-    
-    
-	function integer addrencode;
-		input integer pos,k,n,kw;
-		integer pow,i,tmp;begin
-			addrencode=0;
-			pow=1;
-			for (i = 0; i <n; i=i+1 ) begin 
-				tmp=(pos/pow);
-				tmp=tmp%k;
-				tmp=tmp<<i*kw;
-				addrencode=addrencode | tmp;
-				pow=pow * k;
-			end
-		end   
-	endfunction 
-    
-    
-	genvar i;
-    wire [NE-1 : 0] valid_dst;
+    wire [NE-1 : 0] hdr_flit_sent;
+    wire [DAw-1 : 0] dest_e_addr [NE-1 : 0];  
+    wire [EAw-1 : 0] src_e_addr [NE-1 : 0]; 
+    wire [Cw-1 : 0] pck_class_in [NE-1 : 0]; 
+    wire [Cw-1 : 0] flit_out_class [NE-1 : 0]; 
+    wire [NEw-1 : 0] src_id [NE-1 : 0]; 
+    
+    wire [PCK_SIZw-1: 0] pck_size_in [NE-1 :0]; 
+    wire [PCK_SIZw-1: 0] pck_size_o  [NE-1 :0];   
+    wire [NEw-1 : 0] mcast_dst_num [NE-1 :0];   
+    
+    //   wire    [NE-1 :0] report;
+    reg     [CLK_CNTw-1 :0] clk_counter;
+    wire    [PCK_CNTw-1 :0] pck_counter     [NE-1 :0];
+    wire    [NE-1 :0] noc_report;
+    wire    [NE-1 :0] update;
+    wire    [CLK_CNTw-1 :0] time_stamp_h2t  [NE-1 :0];
+    wire    [CLK_CNTw-1 :0] time_stamp_h2h  [NE-1 :0];
+    wire    [DISTw-1 :0] distance        [NE-1 :0];    
+    wire    [Cw-1 :0] pck_class_out       [NE-1 :0];    
+    reg                         count_en;
+    //reg [NE-1 : 0] start_o;
+    logic [DELAYw-1 : 0] start_delay [NE-1 : 0];
+    
+    always @(`pronoc_clk_reset_edge) begin 
+        if (`pronoc_reset) begin 
+            count_en <=1'b0;
+        end else begin 
+            if(start) count_en <=1'b1;
+            else if(noc_report) count_en <=1'b0;
+        end 
+    end//always
+    
+    noc_top  the_noc (
+        .reset(reset),
+        .clk(clk),
+        .chan_in_all(chan_in_all),
+        .chan_out_all(chan_out_all),
+        .router_event(router_event)
+    );
     
-	generate 
-	for(i=0; i< NE; i=i+1) begin : endpoints
-			
-       		wire [EAw-1 : 0] current_e_addr [NE-1 : 0];
-			
-			endp_addr_encoder #(
-				.TOPOLOGY(TOPOLOGY),
-				.T1(T1),
-				.T2(T2),
-				.T3(T3),
-				.EAw(EAw),
-				.NE(NE)
-			)
-			encoder
-			(
-				.id(i[NEw-1 : 0]),
-				.code(current_e_addr[i])
-			);    
-			
+    always @ (`pronoc_clk_reset_edge)begin 
+        if (`pronoc_reset  ) begin clk_counter  <= 0;  end
+        else  begin 
+            if  (count_en) clk_counter  <= clk_counter+1'b1;    
             
-			        
-			    
-			traffic_gen_top #(
-				.NOC_ID(NOC_ID),
-				.MAX_RATIO(100),
-				.ENDP_ID(i)
-			)
-			the_traffic_gen
-			(
-       			.ratio (ratio),					
-				.pck_size_in(pck_size_in[i]),
-				.current_e_addr(current_e_addr[i]),
-				.dest_e_addr(dest_e_addr[i]),
-				.pck_class_in(pck_class_in[i]),  
-				.init_weight({{(WEIGHTw-1){1'b0}},1'b1}),
-				.hdr_flit_sent(hdr_flit_sent[i]),
-				.pck_number(pck_counter[i]),
-				.reset(reset),
-				.clk(clk),
-				.start(start),
-				.stop(stop | ~valid_dst[i]),
-				.sent_done(),
-				.update(update[i]),
-				.time_stamp_h2h(time_stamp_h2h[i]),
-				.time_stamp_h2t(time_stamp_h2t[i]),
-				.distance(distance[i]),
-				.src_e_addr(src_e_addr[i] ),
-				.pck_class_out(pck_class_out[i]),
-				.report (1'b0),
-				.pck_size_o(pck_size_o[i]),
-				.chan_in(chan_out_all[i]),
-				.chan_out(chan_in_all[i]),
-				.start_delay(start_delay[i]),
-                .flit_out_class(flit_out_class[i]),
-				.flit_out_wr(),
-				.flit_in_wr(),
-				.mcast_dst_num_o(mcast_dst_num[i])
-          
-			);
-			
-			endp_addr_decoder #(
-				.TOPOLOGY(TOPOLOGY),
-				.T1(T1),
-				.T2(T2),
-				.T3(T3),
-				.EAw(EAw),
-				.NE(NE)
-			)
-			decoder
-			(
-				.id(src_id[i]),
-				.code(src_e_addr[i])
-			);    
-     
-
-			pck_class_in_gen #(
-				.C(C),
-				.C0_p(C0_p),
-				.C1_p(C1_p),
-				.C2_p(C2_p),
-				.C3_p(C3_p)            
-			)
-			the_pck_class_in_gen
-			(
-				.en(hdr_flit_sent[i]),
-				.pck_class_o(pck_class_in[i]),
-				.reset(reset),
-				.clk(clk)
-			);
-   
-   
-   
-  
-			pck_dst_gen #(
-				.NOC_ID(NOC_ID),
-				.TRAFFIC(TRAFFIC),
-				.HOTSPOT_NODE_NUM(HOTSPOT_NODE_NUM),
-				.MCAST_TRAFFIC_RATIO(MCAST_TRAFFIC_RATIO),
-				.MCAST_PCK_SIZ_MIN(MCAST_PCK_SIZ_MIN),
-				.MCAST_PCK_SIZ_MAX(MCAST_PCK_SIZ_MAX),
-				.MIN_PACKET_SIZE(MIN_PACKET_SIZE),
-				.MAX_PACKET_SIZE(MAX_PACKET_SIZE),
-				.PCK_SIZ_SEL(PCK_SIZ_SEL),
-				.DISCRETE_PCK_SIZ_NUM(DISCRETE_PCK_SIZ_NUM)				
-			)
-			the_pck_dst_gen
-			(
-				.reset(reset),
-				.clk(clk),
-				.en(hdr_flit_sent[i]),
-				.core_num(i[NEw-1  :   0]),
-				.pck_number(pck_counter[i]),
-				.current_e_addr(current_e_addr[i]),
-				.dest_e_addr(dest_e_addr[i]),
-				.valid_dst(valid_dst[i]),
-				.hotspot_info(hotspot_info),
-				.pck_size_o( pck_size_in[i]) ,
-				.rnd_discrete(rnd_discrete),
-				.custom_traffic_t(custom_traffic_t[i]),  // defined in sim_param.sv
-				.custom_traffic_en(custom_traffic_en[i])  // defined in sim_param.sv
-			);
-       
-			
-  
-	end
-	endgenerate
-
-       
-	
-
-
-
-
-	
-	real				sum_clk_h2h,sum_clk_h2t;
-	real 				sum_clk_pow2;
-	real 				sum_clk_pow2_per_class [C-1 : 0];
-	real				sum_clk_per_hop;
-	integer             total_rsv_pck_num_per_class         [C-1    :   0];
-	real				sum_clk_h2h_per_class			[C-1    :   0];
-	real				sum_clk_h2t_per_class  			[C-1    :   0];
-	real				sum_clk_per_hop_per_class		[C-1	:	0];
-	integer				rsvd_core_total_rsv_pck_num			[NE-1   :   0];
-	integer				rsvd_core_worst_delay			[NE-1   :   0];
-	integer             sent_core_worst_delay           [NE-1   :   0];
-	integer				total_active_endp;
-	integer             total_rsv_pck_num,total_rsv_flit_number;
-	integer				total_sent_pck_num,total_sent_flit_number,total_expect_rsv_flit_num;
-	
-	integer core_num,k;
-	always @(`pronoc_clk_reset_edge)begin
-		if (`pronoc_reset) begin 
-			total_rsv_pck_num=0;
-			total_sent_pck_num=0;
-			sum_clk_h2h=0;
-			sum_clk_h2t=0;
-			sum_clk_pow2=0;
-			sum_clk_per_hop=0;
-			total_sent_flit_number=0;
-			total_rsv_flit_number=0;
-			total_expect_rsv_flit_num=0;
-			for (k=0;k<C;k=k+1) begin 
-					sum_clk_pow2_per_class[k]=0;
-					total_rsv_pck_num_per_class[k]=0;
-					sum_clk_h2h_per_class [k]=0;
-					sum_clk_h2t_per_class [k]=0;
-					sum_clk_per_hop_per_class[k]=0;
-			end
-			for (k=0;k<NE;k=k+1) begin 
-				rsvd_core_total_rsv_pck_num[k]=0;
-				rsvd_core_worst_delay[k]=0;
-				sent_core_worst_delay[k]=0;
-			end
-			for (k=0; k<= MAX_PACKET_SIZE - MIN_PACKET_SIZE; k++) 	rsv_size_array[k]=0;
-			
-		end
-		
-		
-		for (core_num=0; core_num<NE; core_num=core_num+1)begin 
-			if(chan_in_all[core_num].flit_chanel.flit_wr)begin 
-				total_sent_flit_number+=1;
-				if (CAST_TYPE != "UNICAST") total_expect_rsv_flit_num+=mcast_dst_num[core_num];
-				else   total_expect_rsv_flit_num++;
-				
-				
-				if (C>1) sent_stat [core_num][flit_out_class[core_num]].flit_num++;
-				else  	 sent_stat [core_num][0].flit_num++;
-				if(chan_in_all[core_num].flit_chanel.flit[Fw-1])begin
-					total_sent_pck_num+=1;
-					if (C>1) sent_stat [core_num][flit_out_class[core_num]].pck_num++;
-					else  	 sent_stat [core_num][0].pck_num++;
-					
-				end		
-			end
-
-			if(chan_out_all[core_num].flit_chanel.flit_wr)begin 
-				total_rsv_flit_number+=1;	
-				if (C>1) rsvd_stat [core_num][pck_class_out[core_num]].flit_num++;
-				else  	 rsvd_stat [core_num][0].flit_num++;					
-			end 
-			
-			
-			if( update [core_num] ) begin 
-				total_rsv_pck_num = total_rsv_pck_num+1;
-				
-				if (AVG_LATENCY_METRIC == "HEAD_2_TAIL") 
-				update_statistic ( 
-					core_num,		 			
-					pck_class_out[core_num],
-					 $itor(time_stamp_h2h[core_num]),
-					 $itor(time_stamp_h2t[core_num]),
-					src_id[core_num],
-					time_stamp_h2t[core_num],
-					distance[core_num]
-				);
-				else 
-				update_statistic ( 
-					core_num,		 			
-					pck_class_out[core_num],
-					$itor(time_stamp_h2h[core_num]),
-					$itor(time_stamp_h2t[core_num]),
-					src_id[core_num],
-					time_stamp_h2h[core_num],
-					distance[core_num]
-				);
-
-
-				if((total_rsv_pck_num & 'hffff )==0 ) $display(" packet received total=%0d",total_rsv_pck_num);
-				sum_clk_h2h +=  time_stamp_h2h[core_num];
-				sum_clk_h2t +=  time_stamp_h2t[core_num];
-				`ifdef STND_DEV_EN
-					sum_clk_pow2+=time_stamp_h2h[core_num] * time_stamp_h2h[core_num];
-					sum_clk_pow2_per_class[pck_class_out[core_num]]+=time_stamp_h2h[core_num] * time_stamp_h2h[core_num];
-				`endif
-				if(distance[core_num] > 0) sum_clk_per_hop+= $itor(time_stamp_h2h[core_num])/$itor(distance[core_num]);
-				total_rsv_pck_num_per_class[pck_class_out[core_num]]+=1;
-				sum_clk_h2h_per_class[pck_class_out[core_num]]+=time_stamp_h2h[core_num] ;
-				sum_clk_h2t_per_class[pck_class_out[core_num]]+=time_stamp_h2t[core_num] ;
-				if(distance[core_num]>0) sum_clk_per_hop_per_class[pck_class_out[core_num]]+= $itor(time_stamp_h2h[core_num])/$itor(distance[core_num]);
-				rsvd_core_total_rsv_pck_num[core_num]+=1;
-				if (rsvd_core_worst_delay[core_num] < time_stamp_h2t[core_num]) rsvd_core_worst_delay[core_num] = ( AVG_LATENCY_METRIC == "HEAD_2_TAIL")? time_stamp_h2t[core_num] : time_stamp_h2h[core_num];
-				if (sent_core_worst_delay[src_id[core_num]] < time_stamp_h2t[core_num]) sent_core_worst_delay[src_id[core_num]] = (AVG_LATENCY_METRIC == "HEAD_2_TAIL")?  time_stamp_h2t[core_num] : time_stamp_h2h[core_num];
-				if (pck_size_o[core_num] >= MIN_PACKET_SIZE && pck_size_o[core_num] <=MAX_PACKET_SIZE) rsv_size_array[pck_size_o[core_num]-MIN_PACKET_SIZE] = rsv_size_array[pck_size_o[core_num]-MIN_PACKET_SIZE]+1;
-
-					
-			end			
-		end		
-	end//always
-
-	
+        end
+    end
+    
+    function integer addrencode;
+        input integer pos,k,n,kw;
+        integer pow,i,tmp;begin
+            addrencode=0;
+            pow=1;
+            for (i = 0; i <n; i=i+1 ) begin 
+                tmp=(pos/pow);
+                tmp=tmp%k;
+                tmp=tmp<<i*kw;
+                addrencode=addrencode | tmp;
+                pow=pow * k;
+            end
+        end   
+    endfunction 
+    
+    genvar i;
+    wire [NE-1 : 0] valid_dst;
+    wire [EAw-1 : 0] current_e_addr [NE-1 : 0];
+    generate 
+    for(i=0; i< NE; i=i+1) begin : endpoints
+        endp_addr_encoder encoder (
+            .id_in(i[NEw-1 : 0]),
+            .code_out(current_e_addr[i])
+        );
+        
+        traffic_gen_top #(
+            .MAX_RATIO(100),
+            .ENDP_ID(i)
+        ) the_traffic_gen (
+            .ratio (ratio),
+            .pck_size_in(pck_size_in[i]),
+            .current_e_addr(current_e_addr[i]),
+            .dest_e_addr(dest_e_addr[i]),
+            .pck_class_in(pck_class_in[i]),  
+            .init_weight({{(WEIGHTw-1){1'b0}},1'b1}),
+            .hdr_flit_sent(hdr_flit_sent[i]),
+            .pck_number(pck_counter[i]),
+            .reset(reset),
+            .clk(clk),
+            .start(start),
+            .stop(stop | ~valid_dst[i]),
+            .sent_done(),
+            .update(update[i]),
+            .time_stamp_h2h(time_stamp_h2h[i]),
+            .time_stamp_h2t(time_stamp_h2t[i]),
+            .distance(distance[i]),
+            .src_e_addr(src_e_addr[i] ),
+            .pck_class_out(pck_class_out[i]),
+            .report (1'b0),
+            .pck_size_o(pck_size_o[i]),
+            .chan_in(chan_out_all[i]),
+            .chan_out(chan_in_all[i]),
+            .start_delay(start_delay[i]),
+            .flit_out_class(flit_out_class[i]),
+            .flit_out_wr(),
+            .flit_in_wr(),
+            .mcast_dst_num_o(mcast_dst_num[i])
+        );
+        
+        endp_addr_decoder decoder (
+            .id_out(src_id[i]),
+            .code_in(src_e_addr[i])
+        );    
+        
+        pck_class_in_gen #(
+            .C(C),
+            .C0_p(C0_p),
+            .C1_p(C1_p),
+            .C2_p(C2_p),
+            .C3_p(C3_p)
+        )
+        the_pck_class_in_gen
+        (
+            .en(hdr_flit_sent[i]),
+            .pck_class_o(pck_class_in[i]),
+            .reset(reset),
+            .clk(clk)
+        );
+        
+        pck_dst_gen #(
+            .TRAFFIC(TRAFFIC),
+            .HOTSPOT_NODE_NUM(HOTSPOT_NODE_NUM),
+            .MCAST_TRAFFIC_RATIO(MCAST_TRAFFIC_RATIO),
+            .MCAST_PCK_SIZ_MIN(MCAST_PCK_SIZ_MIN),
+            .MCAST_PCK_SIZ_MAX(MCAST_PCK_SIZ_MAX),
+            .MIN_PACKET_SIZE(MIN_PACKET_SIZE),
+            .MAX_PACKET_SIZE(MAX_PACKET_SIZE),
+            .PCK_SIZ_SEL(PCK_SIZ_SEL),
+            .DISCRETE_PCK_SIZ_NUM(DISCRETE_PCK_SIZ_NUM)
+        ) the_pck_dst_gen (
+            .reset(reset),
+            .clk(clk),
+            .en(hdr_flit_sent[i]),
+            .core_num(i[NEw-1 : 0]),
+            .pck_number(pck_counter[i]),
+            .current_e_addr(current_e_addr[i]),
+            .dest_e_addr(dest_e_addr[i]),
+            .valid_dst(valid_dst[i]),
+            .hotspot_info(hotspot_info),
+            .pck_size_o( pck_size_in[i]) ,
+            .rnd_discrete(rnd_discrete),
+            .custom_traffic_t(custom_traffic_t[i]),  // defined in sim_param.sv
+            .custom_traffic_en(custom_traffic_en[i])  // defined in sim_param.sv
+        );
+    end
+    endgenerate
+    
+    real      sum_clk_h2h,sum_clk_h2t;
+    real      sum_clk_pow2;
+    real      sum_clk_pow2_per_class      [C-1 : 0];
+    real      sum_clk_per_hop;
+    integer   total_rsv_pck_num_per_class [C-1 : 0];
+    real      sum_clk_h2h_per_class       [C-1 : 0];
+    real      sum_clk_h2t_per_class       [C-1 : 0];
+    real      sum_clk_per_hop_per_class   [C-1 : 0];
+    integer   rsvd_core_total_rsv_pck_num [NE-1 : 0];
+    integer   rsvd_core_worst_delay       [NE-1 : 0];
+    integer   sent_core_worst_delay       [NE-1 : 0];
+    integer   total_active_endp;
+    integer   total_rsv_pck_num,total_rsv_flit_number;
+    integer   total_sent_pck_num,total_sent_flit_number,total_expect_rsv_flit_num;
+    integer   rsv_size_array [MAX_PACKET_SIZE - MIN_PACKET_SIZE : 0]; 
+    integer core_num,k;
+    integer latency_tmp,class_tmp,src_tmp;;
+    
+    always @(`pronoc_clk_reset_edge)begin
+        if (`pronoc_reset) begin 
+            total_rsv_pck_num=0;
+            total_sent_pck_num=0;
+            sum_clk_h2h=0;
+            sum_clk_h2t=0;
+            sum_clk_pow2=0;
+            sum_clk_per_hop=0;
+            total_sent_flit_number=0;
+            total_rsv_flit_number=0;
+            total_expect_rsv_flit_num=0;
+            for (k=0;k<C;k=k+1) begin 
+                sum_clk_pow2_per_class[k]=0;
+                total_rsv_pck_num_per_class[k]=0;
+                sum_clk_h2h_per_class [k]=0;
+                sum_clk_h2t_per_class [k]=0;
+                sum_clk_per_hop_per_class[k]=0;
+            end
+            for (k=0;k<NE;k=k+1) begin 
+                rsvd_core_total_rsv_pck_num[k]=0;
+                rsvd_core_worst_delay[k]=0;
+                sent_core_worst_delay[k]=0;
+            end
+            for (k=0; k<= MAX_PACKET_SIZE - MIN_PACKET_SIZE; k++)     rsv_size_array[k]=0;
+        end
+        
+        for (core_num=0; core_num<NE; core_num=core_num+1)begin 
+            src_tmp = src_id[core_num];
+            class_tmp = (C>1)? pck_class_out[core_num] : 0; 
+            if(chan_in_all[core_num].flit_chanel.flit_wr)begin 
+                total_sent_flit_number+=1;
+                if (CAST_TYPE != "UNICAST") total_expect_rsv_flit_num+=mcast_dst_num[core_num];
+                else   total_expect_rsv_flit_num++;
+                if (C>1) sent_stat [core_num][flit_out_class[core_num]].flit_num++;
+                else       sent_stat [core_num][0].flit_num++;
+                if(chan_in_all[core_num].flit_chanel.flit[Fw-1])begin
+                    total_sent_pck_num+=1;
+                    if (C>1) sent_stat [core_num][flit_out_class[core_num]].pck_num++;
+                    else       sent_stat [core_num][0].pck_num++;
+                end        
+            end
+            if(chan_out_all[core_num].flit_chanel.flit_wr)begin 
+                total_rsv_flit_number+=1;    
+                endp_to_endp[src_tmp][core_num].flit_num++;
+                rsvd_stat [core_num][class_tmp].flit_num++;
+            end           
+            if( update [core_num] ) begin 
+                total_rsv_pck_num = total_rsv_pck_num+1;
+                latency_tmp =(AVG_LATENCY_METRIC == "HEAD_2_TAIL")?
+                            time_stamp_h2t[core_num]:time_stamp_h2h[core_num];                                
+                update_rsvd_st(
+                    rsvd_stat[core_num][class_tmp],
+                    $itor(time_stamp_h2h[core_num]),//clk_num_h2h,
+                    $itor(time_stamp_h2t[core_num]),//clk_num_h2t,
+                    latency_tmp,
+                    distance[core_num]
+                );
+                update_send_st(
+                    sent_stat[src_tmp][class_tmp],
+                    latency_tmp
+                );
+                update_rsvd_st( 
+                    endp_to_endp[src_tmp][core_num],
+                    $itor(time_stamp_h2h[core_num]),//clk_num_h2h,
+                    $itor(time_stamp_h2t[core_num]),//clk_num_h2t,     
+                    latency_tmp,
+                    distance[core_num]
+                );
+                if((total_rsv_pck_num & 'hffff )==0 ) $display(" packet received total=%0d",total_rsv_pck_num);
+                sum_clk_h2h +=  time_stamp_h2h[core_num];
+                sum_clk_h2t +=  time_stamp_h2t[core_num];
+                `ifdef STND_DEV_EN
+                    sum_clk_pow2+=time_stamp_h2h[core_num] * time_stamp_h2h[core_num];
+                    sum_clk_pow2_per_class[pck_class_out[core_num]]+=time_stamp_h2h[core_num] * time_stamp_h2h[core_num];
+                `endif
+                if(distance[core_num] > 0) sum_clk_per_hop+= $itor(time_stamp_h2h[core_num])/$itor(distance[core_num]);
+                total_rsv_pck_num_per_class[pck_class_out[core_num]]+=1;
+                sum_clk_h2h_per_class[pck_class_out[core_num]]+=time_stamp_h2h[core_num] ;
+                sum_clk_h2t_per_class[pck_class_out[core_num]]+=time_stamp_h2t[core_num] ;
+                if(distance[core_num]>0) sum_clk_per_hop_per_class[pck_class_out[core_num]]+= $itor(time_stamp_h2h[core_num])/$itor(distance[core_num]);
+                rsvd_core_total_rsv_pck_num[core_num]+=1;
+                if (rsvd_core_worst_delay[core_num] < time_stamp_h2t[core_num]) rsvd_core_worst_delay[core_num] = ( AVG_LATENCY_METRIC == "HEAD_2_TAIL")? time_stamp_h2t[core_num] : time_stamp_h2h[core_num];
+                if (sent_core_worst_delay[src_id[core_num]] < time_stamp_h2t[core_num]) sent_core_worst_delay[src_id[core_num]] = (AVG_LATENCY_METRIC == "HEAD_2_TAIL")?  time_stamp_h2t[core_num] : time_stamp_h2h[core_num];
+                if (pck_size_o[core_num] >= MIN_PACKET_SIZE && pck_size_o[core_num] <=MAX_PACKET_SIZE) rsv_size_array[pck_size_o[core_num]-MIN_PACKET_SIZE] = rsv_size_array[pck_size_o[core_num]-MIN_PACKET_SIZE]+1;
+            end
+        end
+    end//always
     
-	
-	
-
     integer rsv_ideal_cnt,total_rsv_flit_number_old;
-	reg all_done_reg;
-	wire all_done_in;
-	assign all_done_in = (clk_counter > STOP_SIM_CLK) || ( total_sent_pck_num >  STOP_PCK_NUM );
-	assign sent_done = all_done_in & ~ all_done_reg;
-	
-	always @(`pronoc_clk_reset_edge)begin
-		if (`pronoc_reset) begin 
-			all_done_reg <= 1'b0;
-			rsv_ideal_cnt<=0;
-			done<=1'b0;
-			total_rsv_flit_number_old<=0;
-		end  else  begin 
-			all_done_reg <= all_done_in;
-			total_rsv_flit_number_old<=total_rsv_flit_number;
-			if(all_done_in) begin //All injectors stopped injecting packets 
-				if(total_rsv_flit_number_old==total_rsv_flit_number) rsv_ideal_cnt<=rsv_ideal_cnt+1;//count the number of cycle when no flit is received by any injector  
-				else rsv_ideal_cnt=0;
-				if(total_expect_rsv_flit_num == total_rsv_flit_number) begin // All injected packets are consumed
-					done<=1'b1;
-				end
-				if(rsv_ideal_cnt >= 100) begin //  Injectors stopped sending packets, number of received and sent flits are not equal yet and for 100 cycles no flit is consumed. 
-					done<=1'b1;
-					#100 $display ("ERROR: The number of expected (%d) & received flits (%d) were not equal at the end of simulation",total_expect_rsv_flit_num ,total_rsv_flit_number);
-					
-					$stop;
-				end
-			end
-		end
-	end    
- 
-	initial total_active_endp=0;
- 
-	
-	real avg_throughput,avg_latency_flit,avg_latency_pck,std_dev,avg_latency_per_hop,min_avg_latency_per_class;
-	
-	
-	initial begin 
-		for(m=0;m<NE;m++) start_delay[m] =$urandom_range((2**DELAYw)-2,0);  
-	end
-	
-
-	initial print_router_st=1'b0;
-	
-	//report 
-	always @( posedge done) begin
-		
-		
-		for (core_num=0; core_num<NE; core_num=core_num+1) begin  
-			if(pck_counter[core_num]>0) total_active_endp   	= 	total_active_endp +1;
-		end
-		
-		avg_throughput= ((total_sent_flit_number*100)/total_active_endp )/clk_counter;
-		avg_latency_flit =sum_clk_h2h/$itor(total_rsv_pck_num);
-		avg_latency_pck	 =sum_clk_h2t/$itor(total_rsv_pck_num);
-		avg_latency_per_hop    = sum_clk_per_hop/$itor(total_rsv_pck_num);
-		$display("simulation results-------------------");
-		$display("\tSimulation clock cycles:%0d",clk_counter);
-		
-		print_router_st=1'b1;
-		#1
-		
-/*
-		$display(" total sent/received packets:%d/%d",total_sent_pck_num,total_rsv_pck_num);
-		$display(" total sent/received flits:%d/%d",total_sent_flit_number,total_rsv_flit_number);
-		$display(" Total active Endpoint: %d \n",total_active_endp);
-		$display(" Avg throughput is: %f (flits/clk/Total active Endpoint %%)",   avg_throughput);
-			
-		
-		
-		$display("\nall : ");		
-		$display(" Total number of packet = %d \n average latency per hop = %f ",total_rsv_pck_num,avg_latency_per_hop);
-		$display(" average packet latency = %f \n average flit latency = %f ",avg_latency_pck, avg_latency_flit);
-*/		
-		$display("\n\tTotal injected packet in different size:");
-		$write("\tflit_size,");
-		for (m=0;m<=(MAX_PACKET_SIZE - MIN_PACKET_SIZE);m++) begin			
-			if(rsv_size_array[m]>0)$write("%0d,",m+ MIN_PACKET_SIZE);
-		end
-		$write("\n\t#pck,");
-		for (m=0;m<=(MAX_PACKET_SIZE - MIN_PACKET_SIZE);m++) begin			
-			if(rsv_size_array[m]>0)$write("%0d,",rsv_size_array[m]);
-		end
-		
-		//		if(ratio==RATIO_INIT) first_avg_latency_flit=avg_latency_flit;
-		//`ifdef STND_DEV_EN
-				//std_dev= standard_dev( sum_clk_pow2,total_rsv_pck_num, avg_latency_flit);
-				//$display(" standard_dev = %f",std_dev);
-		//`endif
-		$display("\n\n\tEndpoints' statistics");
-		$write("\t#node,sent_stat.pck_num,rsvd_stat.pck_num,sent_stat.flit_num,rsvd_stat.flit_num,sent_stat.worst_latency,rsvd_stat.worst_latency,sent_stat.min_latency,rsvd_stat.min_latency,avg_latency_per_hop,avg_latency_flit,avg_latency_pck,avg_throughput(%%),avg_pck_size,");
-`ifdef STND_DEV_EN
-		$write("avg.std_dev");
-`endif
-		$write("\n");	
-		
-		for (m=0; m<NE;m++)begin
-			for (c=0; c<STAT_NUM;c++)begin
-				merge_statistic (rsvd_stat_class[m],rsvd_stat[m][c],rsvd_stat_class[m]);
-				merge_statistic (sent_stat_class[m],sent_stat[m][c],sent_stat_class[m]);
-				if(C>1) begin 
-					merge_statistic (rsvd_stat_per_class[c],rsvd_stat[m][c],rsvd_stat_per_class[c]);
-					merge_statistic (sent_stat_per_class[c],sent_stat[m][c],sent_stat_per_class[c]);
-				end
-			end
-		end
-	
-
-	
-	for (m=0; m<NE;m++)begin
-		
-		merge_statistic (rsvd_stat_total,rsvd_stat_class[m],rsvd_stat_total);
-		merge_statistic (sent_stat_total,sent_stat_class[m],sent_stat_total);
-		
-	end
-	
-	$write("\ttotal,");
-	print_st_single (clk_counter, rsvd_stat_total,sent_stat_total);
-
-	if(C>1)begin
-		for (c=0; c<C;c++)begin
-			$write("\ttotal_class%0d,",c);
-			print_st_single (clk_counter, rsvd_stat_per_class[c],sent_stat_per_class[c]);
-		end
-	end
-
-    for (m=0; m<NE;m++)begin
-    	$write("\t%0d,",m);
-		if(C>1) begin 
-    			print_st_single (clk_counter, rsvd_stat_class[m],sent_stat_class[m] );
-		end else begin 
-			print_st_single (clk_counter, rsvd_stat[m][0],sent_stat[m][0] );
-		end
+    reg all_done_reg;
+    wire all_done_in;
+    assign all_done_in = (clk_counter > STOP_SIM_CLK) || ( total_sent_pck_num >  STOP_PCK_NUM );
+    assign sent_done = all_done_in & ~ all_done_reg;
+    logic report_active_ivcs;
+    always @(`pronoc_clk_reset_edge)begin
+        if (`pronoc_reset) begin 
+            all_done_reg <= 1'b0;
+            rsv_ideal_cnt<=0;
+            done<=1'b0;
+            total_rsv_flit_number_old<=0;
+            report_active_ivcs<='0;
+        end  else  begin 
+            all_done_reg <= all_done_in;
+            total_rsv_flit_number_old<=total_rsv_flit_number;
+            if(all_done_in) begin //All injectors stopped injecting packets 
+                if(total_rsv_flit_number_old==total_rsv_flit_number) rsv_ideal_cnt<=rsv_ideal_cnt+1;//count the number of cycle when no flit is received by any injector  
+                else rsv_ideal_cnt=0;
+                if(total_expect_rsv_flit_num == total_rsv_flit_number) begin // All injected packets are consumed
+                    done<=1'b1;
+                end
+                if(rsv_ideal_cnt >= 100) begin //  Injectors stopped sending packets, number of received and sent flits are not equal yet and for 100 cycles no flit is consumed. 
+                    done<=1'b1;
+                    #50;
+                    report_active_ivcs<=1'b1;
+                    #50;
+                    $display ("ERROR: The number of expected (%d) & received flits (%d) were not equal at the end of simulation",total_expect_rsv_flit_num ,total_rsv_flit_number);
+                    $stop;
+                end
+            end
+        end
     end
-
-
-
-
-
-
-
-
-/*	
-		min_avg_latency_per_class=1000000;
-		for(m=0;m<C;m++) begin
-			avg_throughput		 = (total_rsv_pck_num_per_class[m]>0)? ((total_rsv_pck_num_per_class[m]*AVG_PCK_SIZ*100)/total_active_endp )/clk_counter:0;
-			avg_latency_flit 	 = (total_rsv_pck_num_per_class[m]>0)? sum_clk_h2h_per_class[m]/total_rsv_pck_num_per_class[m]:0;
-			avg_latency_pck	   	 = (total_rsv_pck_num_per_class[m]>0)? sum_clk_h2t_per_class[m]/total_rsv_pck_num_per_class[m]:0;
-			avg_latency_per_hop  = (total_rsv_pck_num_per_class[m]>0)? sum_clk_per_hop_per_class[m]/total_rsv_pck_num_per_class[m]:0;
-			if(AVG_LATENCY_METRIC == "HEAD_2_TAIL") begin
-						$display ("\nclass : %d  ",m);
-						$display (" Total number of packet  = %d \n avg_throughput = %f \n average latency per hop = %f \n average latency = %f",total_rsv_pck_num_per_class[m],avg_throughput,avg_latency_per_hop,avg_latency_pck);
-						
-			end else begin 
-
-						$display ("\nclass : %d  ",m);
-						$display (" Total number of packet  = %d \n avg_throughput = %f \n average latency per hop = %f \n average latency = %f",total_rsv_pck_num_per_class[m],avg_throughput,avg_latency_per_hop,avg_latency_flit);
-			end
-			if(min_avg_latency_per_class > avg_latency_flit) min_avg_latency_per_class=avg_latency_flit;
-
-					//#if (STND_DEV_EN)
-					//std_dev= (total_rsv_pck_num_per_class[i]>0)?  standard_dev( sum_clk_pow2_per_class[i],total_rsv_pck_num_per_class[i], avg_latency_flit):0;
-					// sprintf(file_name,"%s_std%u.txt",out_file_name,i);
-					// update_file( file_name,avg_throughput,std_dev);
-
-					//#endif
-		end//for
-		
-				
-
-		for (m=0;m<NE;m++) begin
-			$display	 ("\n\nEndpoint %d",m);
-			$display	 ("\n\ttotal number of received packets: %d",rsvd_core_total_rsv_pck_num[m]);
-			$display	 ("\n\tworst-case-delay of received packets (clks): %d",rsvd_core_worst_delay[m] );
-			$display	 ("\n\ttotal number of sent packets: %d",pck_counter[m]);
-			$display	 ("\n\tworst-case-delay of sent packets (clks): %d",sent_core_worst_delay[m] );
-		end
-
-*/
-
-	end
-
-		
-	
-
-   
-	initial begin
-		display_noc_parameters();		
-		$display ("Simulation parameters-------------");
-		if(DEBUG_EN)
-			$display ("\tDebuging is enabled");
-		else
-			$display ("\tDebuging is disabled");
-
-		//if( AVG_LATENCY_METRIC == "HEAD_2_TAIL")  $display ("\tOutput is the average latency on sending the packet header until receiving tail");
-		//else $display ("\tOutput is the average latency on sending the packet header until receiving header flit at destination node");
-		$display ("\tTraffic pattern:%s",TRAFFIC);
-		if(C>0) $display ("\ttraffic percentage of class 0 is : %0d", C0_p);
-		if(C>1) $display ("\ttraffic percentage of class 1 is : %0d", C1_p);
-		if(C>2) $display ("\ttraffic percentage of class 2 is : %0d", C2_p);
-		if(C>3) $display ("\ttraffic percentage of class 3 is : %0d", C3_p);
-		if(TRAFFIC == "HOTSPOT")begin
-			//$display ("\tHot spot percentage: %u\n", HOTSPOT_PERCENTAGE);
-			$display ("\tNumber of hot spot cores: %0d", HOTSPOT_NODE_NUM);
-		end
-		if (CAST_TYPE != "UNICAST")begin
-			$display ("\tMULTICAST traffic ratio: %d(%%), min: %d, max: %d\n", MCAST_TRAFFIC_RATIO,MCAST_PCK_SIZ_MIN,MCAST_PCK_SIZ_MAX);
-		end 
-
-		
-		
-		//$display ("\tTotal packets sent by one router: %u\n", TOTAL_PKT_PER_ROUTER);
-		$display ("\tSimulation timeout =%0d", STOP_SIM_CLK);
-		$display ("\tSimulation ends on total packet num of =%0d", STOP_PCK_NUM);
-		$display ("\tPacket size (min,max,average) in flits: (%0d,%0d,%0d)",MIN_PACKET_SIZE,MAX_PACKET_SIZE,AVG_PCK_SIZ);
-		$display ("\tPacket injector FIFO width in flit:%0d\n\n",TIMSTMP_FIFO_NUM);
-		$display ("\tFlit injection ratio per router is =%f (flits/clk/Total Endpoint %%)",ratio);
-
-		$display ("Simulation parameters-------------");
-
-	end//initial
-
-
-
-
-
-	task update_statistic;
-		input integer core_num;
-		input [Cw-1 : 0] class_num;
-		input real clk_num_h2h;
-		input real clk_num_h2t;	
-		input [NEw-1     :   0]  src;	
-		input real latency;
-		input [DISTw-1         :0] distance	;
-		begin 
-		
-
-		if(C>1) begin
-
-			rsvd_stat[core_num][class_num].pck_num ++;
-			rsvd_stat[core_num][class_num].sum_clk_h2h +=clk_num_h2h;
-			rsvd_stat[core_num][class_num].sum_clk_h2t +=clk_num_h2t;
-			rsvd_stat[core_num][class_num].sum_clk_per_hop+= (clk_num_h2h/$itor(distance));
-			if (rsvd_stat[core_num][class_num].worst_latency < latency ) rsvd_stat[core_num][class_num].worst_latency =latency;
-			if (rsvd_stat[core_num][class_num].min_latency==0          ) rsvd_stat[core_num][class_num].min_latency   =latency;
-			if (rsvd_stat[core_num][class_num].min_latency   > latency ) rsvd_stat[core_num][class_num].min_latency   =latency;
-			if (sent_stat[src     ][class_num].worst_latency < latency ) sent_stat[src     ][class_num].worst_latency =latency;
-			if (sent_stat[src     ][class_num].min_latency==0          ) sent_stat[src     ][class_num].min_latency   =latency;
-			if (sent_stat[src     ][class_num].min_latency   > latency ) sent_stat[src     ][class_num].min_latency   =latency;
-
-			`ifdef STND_DEV_EN
-		    	rsvd_stat[core_num][class_num].sum_clk_pow2 += clk_num_h2h * clk_num_h2h;
-			`endif
-		end else begin
-			rsvd_stat[core_num][0].pck_num ++;
-		    rsvd_stat[core_num][0].sum_clk_h2h +=clk_num_h2h;
-		    rsvd_stat[core_num][0].sum_clk_h2t +=clk_num_h2t;
-		    if(distance>0) rsvd_stat[core_num][0].sum_clk_per_hop+= (clk_num_h2h/$itor(distance));
-		    if (rsvd_stat[core_num][0].worst_latency < latency ) rsvd_stat[core_num][0].worst_latency=latency;
-		    if (rsvd_stat[core_num][0].min_latency==0          ) rsvd_stat[core_num][0].min_latency  =latency;
-		    if (rsvd_stat[core_num][0].min_latency   > latency ) rsvd_stat[core_num][0].min_latency  =latency;
-		    if (sent_stat[src     ][0].worst_latency < latency ) sent_stat[src     ][0].worst_latency=latency;
-		    if (sent_stat[src     ][0].min_latency==0          ) sent_stat[src     ][0].min_latency  =latency;
-		    if (sent_stat[src     ][0].min_latency   > latency ) sent_stat[src     ][0].min_latency  =latency;
-
-			`ifdef STND_DEV_EN
-		    	rsvd_stat[core_num][0].sum_clk_pow2 += clk_num_h2h * clk_num_h2h;
-			`endif
-		end
-
-	end
-	endtask
-
-
-
-
-	task merge_statistic;
-	input statistic_t merge_stat;
-	input statistic_t stat_in;
-	output statistic_t stat_out;
-	begin 
-		stat_out.pck_num =    merge_stat.pck_num+stat_in.pck_num;
-		stat_out.flit_num =   merge_stat.flit_num+stat_in.flit_num;
-		if(merge_stat.worst_latency <  stat_in.worst_latency) stat_out.worst_latency= stat_in.worst_latency;
-		if(merge_stat.min_latency   == 0                       ) stat_out.min_latency  = stat_in.min_latency;
-		if(merge_stat.min_latency   > stat_in.min_latency  && stat_in.min_latency!=0   ) stat_out.min_latency  = stat_in.min_latency;
-		stat_out.sum_clk_h2h = merge_stat.sum_clk_h2h      +stat_in.sum_clk_h2h    ;
-		stat_out.sum_clk_h2t = merge_stat.sum_clk_h2t      +stat_in.sum_clk_h2t    ;
-		stat_out.sum_clk_per_hop =   merge_stat.sum_clk_per_hop  +stat_in.sum_clk_per_hop;
-		`ifdef STND_DEV_EN
-			stat_out.sum_clk_pow2 = merge_stat.sum_clk_pow2 +stat_in.sum_clk_pow2;
-    	`endif
-
-	end
-	endtask
-
-
-	
-
-
-
-	task print_st_single;
-		input [CLK_CNTw-1 : 0]total_clk;
-		input statistic_t rsvd_stat;
-		input statistic_t sent_stat;
-		begin 
-
-
-
-		avg_st_t avg;
-		finilize_statistic (total_clk,  rsvd_stat, avg);
-
-		$write("%0d,",sent_stat.pck_num);
-		$write("%0d,",rsvd_stat.pck_num);
-		$write("%0d,",sent_stat.flit_num);
-		$write("%0d,",rsvd_stat.flit_num);
-		$write("%0d,",sent_stat.worst_latency);
-		$write("%0d,",rsvd_stat.worst_latency);
-		$write("%0d,",sent_stat.min_latency);
-		$write("%0d,",rsvd_stat.min_latency);
-		$write("%f,",avg.avg_latency_per_hop);
-		$write("%f,",avg.avg_latency_flit);
-		$write("%f,",avg.avg_latency_pck);
-		$write("%f,",avg.avg_throughput);
-		$write("%f,",avg.avg_pck_siz);
-	`ifdef STND_DEV_EN
-		$write("%f,",avg.std_dev);
-	`endif
-		$write("\n");
-	//	printf("\n");
-		end
-	endtask
-
-
-
-	task finilize_statistic;
-		input [CLK_CNTw-1 : 0]total_clk;
-		input statistic_t rsvd_stat;
-		output avg_st_t avg_statistic;
-		begin
-
-		 
-		 avg_statistic.avg_throughput = ($itor(rsvd_stat.flit_num*100)/NE )/total_clk;
-		 avg_statistic.avg_latency_flit =(rsvd_stat.pck_num>0)? rsvd_stat.sum_clk_h2h/rsvd_stat.pck_num : 0;
-		 avg_statistic.avg_latency_pck = (rsvd_stat.pck_num>0)? rsvd_stat.sum_clk_h2t/rsvd_stat.pck_num :0;
-		 avg_statistic.avg_latency_per_hop = ( rsvd_stat.pck_num==0)? 0 : rsvd_stat.sum_clk_per_hop/rsvd_stat.pck_num;
-		 avg_statistic.avg_pck_siz  = ( rsvd_stat.pck_num==0)? 0 : $itor(rsvd_stat.flit_num) / $itor(rsvd_stat.pck_num);
-		 `ifdef STND_DEV_EN
-		 	standard_dev( rsvd_stat.sum_clk_pow2,rsvd_stat.pck_num, avg_statistic.avg_latency_flit,avg_statistic.std_dev);
-		 `endif
-	end
-	endtask
-
-
-
-	`ifdef STND_DEV_EN
-	/************************
-	 * std_dev = sqrt[(B-A^2/N)/N]  = sqrt [(B/N)- (A/N)^2] = sqrt [B/N - mean^2]
-	 * A = sum of the values
-	 * B = sum of the squarded values 
-	 * *************/
-
-	task standard_dev;
-		input real sum_pow2;
-		input [PCK_CNTw-1     :0]  total_num;
-		input real average;
-		output real std_dev;
-		begin
-		/*
-		double  A, B, N;
-		N= total_num;
-		A= average * N;
-		B= sum_pow2;
-
-		A=(A*A)/N;
-		std_dev = (B-A)/N;
-		std_dev = sqrt(std_dev);
-	*/	
-		if(total_num==0) std_dev= 0;
-		else begin
-			std_dev = sum_pow2/$itor(total_num); //B/N
-			std_dev -= (average*average);// (B/N) - mean^2
-			std_dev = $sqrt(std_dev);// sqrt [B/N - mean^2]
-
-		end
-	end
-	endtask
-
-	`endif
-
-
-	
-	/*
-	start_delay_gen #(
-			.NC(NE)
-		)
-		delay_gen
-		(
-			.clk(clk),
-			.reset(reset),
-			.start_i(start),
-			.start_o(start_o)
-		);
-	 */
-	
-	
-	routers_statistic_collector #(
-		.NOC_ID(NOC_ID)
-	) router_stat ( 
-		.reset(reset),
-		.clk(clk),		
-		.router_event(router_event),
-		.print(print_router_st)
-	);
-
+    
+    initial total_active_endp=0;
+    real avg_throughput,avg_latency_flit,avg_latency_pck,std_dev,avg_latency_per_hop,min_avg_latency_per_class;
+    
+    initial begin 
+        for(m=0;m<NE;m++) start_delay[m] =$urandom_range((2**DELAYw)-2,0);  
+    end
+    
+    initial print_router_st=1'b0;
+    
+    //report 
+    always @( posedge done) begin     
+        for (core_num=0; core_num<NE; core_num=core_num+1) begin  
+            if(pck_counter[core_num]>0) total_active_endp       =     total_active_endp +1;
+        end
+        avg_throughput= ((total_sent_flit_number*100)/total_active_endp )/clk_counter;
+        avg_latency_flit =sum_clk_h2h/$itor(total_rsv_pck_num);
+        avg_latency_pck     =sum_clk_h2t/$itor(total_rsv_pck_num);
+        avg_latency_per_hop    = sum_clk_per_hop/$itor(total_rsv_pck_num);
+        $display("\nsimulation results-------------------");
+        $display("\tSimulation clock cycles:%0d",clk_counter);
+        $display("\n\tTotal received packet in different size:");
+        $write("\tflit_size,");
+        for (m=0;m<=(MAX_PACKET_SIZE - MIN_PACKET_SIZE);m++) begin            
+            if(rsv_size_array[m]>0)$write("%0d,",m+ MIN_PACKET_SIZE);
+        end
+        $write("\n\t#pck,");
+        for (m=0;m<=(MAX_PACKET_SIZE - MIN_PACKET_SIZE);m++) begin            
+            if(rsv_size_array[m]>0)$write("%0d,",rsv_size_array[m]);
+        end        
+        print_router_st=1'b1;
+        #1
+        // if(ratio==RATIO_INIT) first_avg_latency_flit=avg_latency_flit;
+        //`ifdef STND_DEV_EN
+                //std_dev= standard_dev( sum_clk_pow2,total_rsv_pck_num, avg_latency_flit);
+                //$display(" standard_dev = %f",std_dev);
+        //`endif
+        print_endp_to_endp_st("pck_num");
+        print_endp_to_endp_st("flit_num");
+        $display("\n\n\tEndpoints Statistics:");
+        $write("\t#EID,sent_stat.pck_num,rsvd_stat.pck_num,sent_stat.flit_num,rsvd_stat.flit_num,sent_stat.worst_latency,rsvd_stat.worst_latency,sent_stat.min_latency,rsvd_stat.min_latency,avg_latency_per_hop,avg_latency_flit,avg_latency_pck,avg_throughput(%%),avg_pck_size,");
+        `ifdef STND_DEV_EN
+        $write("avg.std_dev");
+        `endif
+        $write("\n");       
+        for (m=0; m<NE;m++)begin
+            for (c=0; c<STAT_NUM;c++)begin
+                merge_statistic (rsvd_stat_class[m],rsvd_stat[m][c],rsvd_stat_class[m]);
+                merge_statistic (sent_stat_class[m],sent_stat[m][c],sent_stat_class[m]);
+                if(C>1) begin 
+                    merge_statistic (rsvd_stat_per_class[c],rsvd_stat[m][c],rsvd_stat_per_class[c]);
+                    merge_statistic (sent_stat_per_class[c],sent_stat[m][c],sent_stat_per_class[c]);
+                end
+            end
+        end
+        for (m=0; m<NE;m++)begin
+            merge_statistic (rsvd_stat_total,rsvd_stat_class[m],rsvd_stat_total);
+            merge_statistic (sent_stat_total,sent_stat_class[m],sent_stat_total);
+        end
+        $write("\ttotal,");
+        print_st_single (clk_counter, rsvd_stat_total,sent_stat_total);
+        if(C>1)begin
+            for (c=0; c<C;c++)begin
+                $write("\ttotal_class%0d,",c);
+                print_st_single (clk_counter, rsvd_stat_per_class[c],sent_stat_per_class[c]);
+            end
+        end
+        for (m=0; m<NE;m++)begin
+            $write("\t%0d,",m);
+            if(C>1) begin 
+                    print_st_single (clk_counter, rsvd_stat_class[m],sent_stat_class[m] );
+            end else begin 
+                print_st_single (clk_counter, rsvd_stat[m][0],sent_stat[m][0] );
+            end
+        end        
+    end //always
+    
+    initial begin
+        display_noc_parameters();        
+        $display ("Simulation parameters-------------");
+        if(DEBUG_EN)
+            $display ("\tDebuging is enabled");
+        else
+            $display ("\tDebuging is disabled");
+        //if( AVG_LATENCY_METRIC == "HEAD_2_TAIL")  $display ("\tOutput is the average latency on sending the packet header until receiving tail");
+        //else $display ("\tOutput is the average latency on sending the packet header until receiving header flit at destination node");
+        $display ("\tTraffic pattern:%s",TRAFFIC);
+        if(C>0) $display ("\ttraffic percentage of class 0 is : %0d", C0_p);
+        if(C>1) $display ("\ttraffic percentage of class 1 is : %0d", C1_p);
+        if(C>2) $display ("\ttraffic percentage of class 2 is : %0d", C2_p);
+        if(C>3) $display ("\ttraffic percentage of class 3 is : %0d", C3_p);
+        if(TRAFFIC == "HOTSPOT")begin
+            //$display ("\tHot spot percentage: %u\n", HOTSPOT_PERCENTAGE);
+            $display ("\tNumber of hot spot cores: %0d", HOTSPOT_NODE_NUM);
+        end
+        if (CAST_TYPE != "UNICAST")begin
+            $display ("\tMULTICAST traffic ratio: %d(%%), min: %d, max: %d\n", MCAST_TRAFFIC_RATIO,MCAST_PCK_SIZ_MIN,MCAST_PCK_SIZ_MAX);
+        end 
+        //$display ("\tTotal packets sent by one router: %u\n", TOTAL_PKT_PER_ROUTER);
+        $display ("\tSimulation timeout =%0d", STOP_SIM_CLK);
+        $display ("\tSimulation ends on total packet num of =%0d", STOP_PCK_NUM);
+        $display ("\tPacket size (min,max,average) in flits: (%0d,%0d,%0d)",MIN_PACKET_SIZE,MAX_PACKET_SIZE,AVG_PCK_SIZ);
+        $display ("\tPacket injector FIFO width in flit:%0d",TIMSTMP_FIFO_NUM);
+        $display ("\tFlit injection ratio per router is =%f (flits/clk/Total Endpoint %%)",ratio);
+        $display ("Simulation parameters-------------");
+    end//initial   
+    
+    task merge_statistic;
+    input statistic_t merge_stat;
+    input statistic_t stat_in;
+    output statistic_t stat_out;
+    begin 
+        stat_out.pck_num =    merge_stat.pck_num+stat_in.pck_num;
+        stat_out.flit_num =   merge_stat.flit_num+stat_in.flit_num;
+        if(merge_stat.worst_latency <  stat_in.worst_latency) stat_out.worst_latency= stat_in.worst_latency;
+        if(merge_stat.min_latency   == 0                       ) stat_out.min_latency  = stat_in.min_latency;
+        if(merge_stat.min_latency   > stat_in.min_latency  && stat_in.min_latency!=0   ) stat_out.min_latency  = stat_in.min_latency;
+        stat_out.sum_clk_h2h = merge_stat.sum_clk_h2h      +stat_in.sum_clk_h2h    ;
+        stat_out.sum_clk_h2t = merge_stat.sum_clk_h2t      +stat_in.sum_clk_h2t    ;
+        stat_out.sum_clk_per_hop =   merge_stat.sum_clk_per_hop  +stat_in.sum_clk_per_hop;
+        `ifdef STND_DEV_EN
+            stat_out.sum_clk_pow2 = merge_stat.sum_clk_pow2 +stat_in.sum_clk_pow2;
+        `endif
+    end
+    endtask
+    
+    task print_st_single;
+    input [CLK_CNTw-1 : 0]total_clk;
+    input statistic_t rsvd_stat;
+    input statistic_t sent_stat;
+    begin 
+        avg_st_t avg;
+        finilize_statistic (total_clk,  rsvd_stat, avg);
+        $write("%0d,",sent_stat.pck_num);
+        $write("%0d,",rsvd_stat.pck_num);
+        $write("%0d,",sent_stat.flit_num);
+        $write("%0d,",rsvd_stat.flit_num);
+        $write("%0d,",sent_stat.worst_latency);
+        $write("%0d,",rsvd_stat.worst_latency);
+        $write("%0d,",sent_stat.min_latency);
+        $write("%0d,",rsvd_stat.min_latency);
+        $write("%f,",avg.avg_latency_per_hop);
+        $write("%f,",avg.avg_latency_flit);
+        $write("%f,",avg.avg_latency_pck);
+        $write("%f,",avg.avg_throughput);
+        $write("%f,",avg.avg_pck_siz);
+        `ifdef STND_DEV_EN
+        $write("%f,",avg.std_dev);
+        `endif
+        $write("\n");
+    end
+    endtask
+    
+    task finilize_statistic;
+    input [CLK_CNTw-1 : 0]total_clk;
+    input statistic_t rsvd_stat;
+    output avg_st_t avg_statistic;
+    begin   
+        avg_statistic.avg_throughput = ($itor(rsvd_stat.flit_num*100)/NE )/total_clk;
+        avg_statistic.avg_latency_flit =(rsvd_stat.pck_num>0)? rsvd_stat.sum_clk_h2h/rsvd_stat.pck_num : 0;
+        avg_statistic.avg_latency_pck = (rsvd_stat.pck_num>0)? rsvd_stat.sum_clk_h2t/rsvd_stat.pck_num :0;
+        avg_statistic.avg_latency_per_hop = ( rsvd_stat.pck_num==0)? 0 : rsvd_stat.sum_clk_per_hop/rsvd_stat.pck_num;
+        avg_statistic.avg_pck_siz  = ( rsvd_stat.pck_num==0)? 0 : $itor(rsvd_stat.flit_num) / $itor(rsvd_stat.pck_num);
+        `ifdef STND_DEV_EN
+            standard_dev( rsvd_stat.sum_clk_pow2,rsvd_stat.pck_num, avg_statistic.avg_latency_flit,avg_statistic.std_dev);
+        `endif
+    end
+    endtask
+    
+    `ifdef STND_DEV_EN
+    /************************
+     * std_dev = sqrt[(B-A^2/N)/N]  = sqrt [(B/N)- (A/N)^2] = sqrt [B/N - mean^2]
+     * A = sum of the values
+     * B = sum of the squarded values 
+     * *************/
+    task standard_dev;
+    input real sum_pow2;
+    input [PCK_CNTw-1 :0]  total_num;
+    input real average;
+    output real std_dev;
+    begin
+        /*
+        double  A, B, N;
+        N= total_num;
+        A= average * N;
+        B= sum_pow2;
+        A=(A*A)/N;
+        std_dev = (B-A)/N;
+        std_dev = sqrt(std_dev);
+        */    
+        if(total_num==0) std_dev= 0;
+        else begin
+            std_dev = sum_pow2/$itor(total_num); //B/N
+            std_dev -= (average*average);// (B/N) - mean^2
+            std_dev = $sqrt(std_dev);// sqrt [B/N - mean^2]
+        end
+    end
+    endtask
+    `endif
+    
+    /*
+    start_delay_gen #(
+            .NC(NE)
+        )
+        delay_gen
+        (
+            .clk(clk),
+            .reset(reset),
+            .start_i(start),
+            .start_o(start_o)
+        );
+     */
+
+    routers_statistic_collector router_stat ( 
+        .reset(reset),
+        .clk(clk),        
+        .router_event(router_event),
+        .print(print_router_st)
+    );
+    
 endmodule
-// synthesis translate_on
-
+`endif
diff --git a/mpsoc/rtl/src_modelsim/traffic_pattern.sv b/mpsoc/rtl/src_modelsim/traffic_pattern.sv
index 804fe73..6c6c530 100755
--- a/mpsoc/rtl/src_modelsim/traffic_pattern.sv
+++ b/mpsoc/rtl/src_modelsim/traffic_pattern.sv
@@ -1,91 +1,74 @@
 /**************************************
 * Module: traffic_pattern
-* Date:2015-10-05  
-* Author: alireza     
+* Date:2015-10-05
+* Author: alireza 
 *
 * Description: 
 ***************************************/
 
 `include "pronoc_def.v"
 
-
- 
 /************************************
-
-        pck_class_in_gen
-
+*      pck_class_in_gen
 ***********************************/ 
- 
+
 module pck_class_in_gen #(
     parameter C = 4,    //  number of packet class 
     parameter C0_p = 25,    //  the percentage of injected packets with class 0 
     parameter C1_p = 25,
     parameter C2_p = 25,
-    parameter C3_p = 25    
+    parameter C3_p = 25
 )(
     pck_class_o,
-    en,   
+    en,
     reset,
     clk
-
 ); 
-     
+    
     function integer log2;
-      input integer number; begin   
-         log2=(number <=1) ? 1: 0;    
-         while(2**log2<number) begin    
-            log2=log2+1;    
-         end 	   
-      end   
+    input integer number; begin
+        log2=(number <=1) ? 1: 0;
+        while(2**log2<number) begin
+            log2=log2+1;
+        end
+    end
     endfunction // log2 
-     
-   
+    
     localparam 
     Cw = (C>1)? log2(C) : 1,
     RNDw = log2(100);
-               
+    
     output reg [Cw-1    :   0]  pck_class_o;
-    input                       reset,clk,en;
-    reg       [RNDw-1  :   0]  rnd;
-   
- 
-   
- // generate a random num between 0 to 99
+    input  reset,clk,en;
+    reg   [RNDw-1 :  0]  rnd;
+    // generate a random num between 0 to 99
     always @(posedge clk ) begin 
-    	if(en | `pronoc_reset) begin 
-    		rnd =     $urandom_range(99,0);    		
-    	end    		
+        if(en | `pronoc_reset) begin 
+            rnd =  $urandom_range(99,0);
+        end
     end
     
-    always @(*) begin 
+    always_comb begin 
         if      ( rnd <   C0_p)                 pck_class_o =0;
         else if ( rnd <   (C0_p+C1_p))          pck_class_o =1;
         else if ( rnd <   (C0_p+C1_p+C2_p))     pck_class_o =2;
         else                                    pck_class_o =3;
     end
- 
-   
-   
 endmodule
 
 /**********************************
-
-        pck_dst_gen
-
+*      pck_dst_gen
 *********************************/
-module  pck_dst_gen
-   #(
-    parameter NOC_ID=0,
-	parameter TRAFFIC = "RANDOM",
+module  pck_dst_gen  #(
+    parameter TRAFFIC = "RANDOM",
     parameter HOTSPOT_NODE_NUM =  4,
     parameter MCAST_TRAFFIC_RATIO =50,
     parameter MCAST_PCK_SIZ_MIN = 2,
     parameter MCAST_PCK_SIZ_MAX = 4,
     parameter MIN_PACKET_SIZE=5,
     parameter MAX_PACKET_SIZE=5,
-    parameter PCK_SIZ_SEL="random-discrete",	
+    parameter PCK_SIZ_SEL="random-discrete",
     parameter DISCRETE_PCK_SIZ_NUM=1
-	
 )(
     en,
     current_e_addr,
@@ -100,19 +83,13 @@ module  pck_dst_gen
     custom_traffic_en,
     pck_size_o,
     rnd_discrete
-    
-    
 ); 
- 
-    `NOC_CONF
- 
-    localparam      ADDR_DIMENSION =   (TOPOLOGY ==    "MESH" || TOPOLOGY ==  "TORUS") ? 2 : 1;  // "RING" and FULLY_CONNECT 
- 
- 
- 
-     
-    localparam  PCK_CNTw = log2(MAX_PCK_NUM+1),
-                HOTSPOT_NUM= (TRAFFIC=="HOTSPOT")? HOTSPOT_NODE_NUM : 1;
+    import pronoc_pkg::*;
+    localparam  ADDR_DIMENSION =   (IS_MESH | IS_TORUS) ? 2 : 1;  // "RING" and FULLY_CONNECT 
+    
+    localparam  
+        PCK_CNTw = log2(MAX_PCK_NUM+1),
+        HOTSPOT_NUM= (TRAFFIC=="HOTSPOT")? HOTSPOT_NODE_NUM : 1;
     
     input                       reset,clk,en;
     input   [NEw-1      :   0]  core_num;
@@ -122,172 +99,147 @@ module  pck_dst_gen
     output                      valid_dst;
     input  [NEw-1 : 0] custom_traffic_t;
     input  custom_traffic_en;
-  
     
     output [PCK_SIZw-1:0]  pck_size_o;
     input rnd_discrete_t rnd_discrete [DISCRETE_PCK_SIZ_NUM-1: 0];
     
     input hotspot_t  hotspot_info [HOTSPOT_NUM-1 : 0];
-
-
-	wire [EAw-1      :   0] unicast_dest_e_addr; 
-	wire [PCK_SIZw-1 : 0] pck_size_uni;
-
-	pck_dst_gen_unicast #(
-		.NOC_ID(NOC_ID),
-		.TRAFFIC(TRAFFIC),
-		.HOTSPOT_NODE_NUM(HOTSPOT_NODE_NUM)
-	)
-	unicast
-	(
-		.en               (en              ),
-		.current_e_addr   (current_e_addr  ),
-		.core_num         (core_num        ),
-		.pck_number       (pck_number      ),
-		.dest_e_addr      (unicast_dest_e_addr),
-		.clk              (clk             ),
-		.reset            (reset           ),
-		.valid_dst        (valid_dst       ),
-		.hotspot_info     (hotspot_info    ),
-		.custom_traffic_t (custom_traffic_t),
-		.custom_traffic_en(custom_traffic_en)
-	); 
-	
-	pck_size_gen #(
-		.NOC_ID(NOC_ID),
-		.MIN(MIN_PACKET_SIZE),
-		.MAX(MAX_PACKET_SIZE),
-		.PCK_SIZ_SEL(PCK_SIZ_SEL),
-		.DISCRETE_PCK_SIZ_NUM(DISCRETE_PCK_SIZ_NUM)
-	)
-	unicast_pck_size
-	(
-		.reset(reset),
-		.clk(clk),
-		.en(en),
-		.pck_size(pck_size_uni) ,
-		.rnd_discrete(rnd_discrete)
-	);	
-	
-
-	generate
-	if(CAST_TYPE == "UNICAST") begin :uni
-		assign dest_e_addr =	unicast_dest_e_addr;
-		assign pck_size_o  =   pck_size_uni;		
-	end else begin :multi
-		reg [DAw-1      :   0] multicast_dest_e_addr,temp; 
-		reg [6: 0] rnd_reg;
-		wire [PCK_SIZw-1 : 0] pck_size_mcast;
-		reg  [PCK_SIZw-1 : 0] pck_siz_tmp;
-		wire [NEw-1 : 0] unicast_id_num;  
-			
-			
-		endp_addr_decoder  #(
-			.T1(T1),
-			.T2(T2),
-			.T3(T3),
-			.NE(NE),
-			.EAw(EAw),
-			.TOPOLOGY(TOPOLOGY)
-		) enc (
-			.code(unicast_dest_e_addr),
-			.id(unicast_id_num)
-		);    
-		
-		
-		pck_size_gen #(
-			.NOC_ID(NOC_ID),			
-			.MIN(MCAST_PCK_SIZ_MIN),
-			.MAX(MCAST_PCK_SIZ_MAX),
-			.PCK_SIZ_SEL("random-range"),
-			.DISCRETE_PCK_SIZ_NUM(DISCRETE_PCK_SIZ_NUM)
-		) mcast_pck_size (
-			.reset(reset),
-			.clk(clk),
-			.en(en),
-			.pck_size(pck_size_mcast) ,
-			.rnd_discrete(rnd_discrete)
-		);	
-		
-		always @(posedge clk ) begin 
-			if(en | reset) begin 
-				rnd_reg <=     $urandom_range(99,0);
-			end
-		end		
-		
-		if(CAST_TYPE == "MULTICAST_FULL") begin :mful
-		
-			always @( * ) begin 
-				multicast_dest_e_addr = {DAw{1'b0}};
-				temp={DAw{1'b0}};
-				temp[unicast_id_num]=1'b1;
-				pck_siz_tmp= pck_size_uni;
-				if(rnd_reg >= MCAST_TRAFFIC_RATIO) begin 
-					multicast_dest_e_addr[unicast_id_num]=1'b1;				
-				end
-				else begin 
-					multicast_dest_e_addr =  $urandom();
-					pck_siz_tmp=pck_size_mcast;
-				end
-				if(SELF_LOOP_EN	== "NO") multicast_dest_e_addr[core_num]=1'b0;
-			end
-			
-			
-			
-			assign dest_e_addr = (multicast_dest_e_addr=={DAw{1'b0}} )? temp : multicast_dest_e_addr ;
-			assign pck_size_o = pck_siz_tmp;
-			
-		end else if(CAST_TYPE == "MULTICAST_PARTIAL") begin :mpar
-			
-			always @( * ) begin 
-				multicast_dest_e_addr = {DAw{1'b0}};
-				temp={unicast_dest_e_addr,1'b1};
-				pck_siz_tmp= pck_size_uni;
-				if(rnd_reg >= MCAST_TRAFFIC_RATIO) begin 
-					multicast_dest_e_addr = {unicast_dest_e_addr,1'b1};
-				end
-				else begin 
-					multicast_dest_e_addr =  $urandom();
-					multicast_dest_e_addr[0] =1'b0;
-					pck_siz_tmp=pck_size_mcast;
-					if(SELF_LOOP_EN	== "NO") begin						
-						if(MCAST_ENDP_LIST[core_num]==1'b1) multicast_dest_e_addr[endp_id_to_mcast_id(core_num)+1]=1'b0;
-					end
-				end
-			end
-			
-			assign dest_e_addr = (multicast_dest_e_addr=={DAw{1'b0}} )? temp : multicast_dest_e_addr ;
-			assign pck_size_o = pck_siz_tmp;
-			
-			
-			
-		end else begin //Broadcast
-			
-			always @( * ) begin 
-				multicast_dest_e_addr = {DAw{1'b0}};				
-				pck_siz_tmp = pck_size_uni;
-				if(rnd_reg >= MCAST_TRAFFIC_RATIO) begin 
-					multicast_dest_e_addr = {unicast_dest_e_addr,1'b1};
-				end
-				else begin							
-					pck_siz_tmp=pck_size_mcast;					
-				end
-			end
-			assign dest_e_addr =  multicast_dest_e_addr ;
-			assign pck_size_o = pck_siz_tmp;
-			
-			
-		end
-
-	end endgenerate
-
+    wire [EAw-1      :   0] unicast_dest_e_addr; 
+    wire [PCK_SIZw-1 : 0] pck_size_uni;
+    
+    pck_dst_gen_unicast #(
+        .TRAFFIC(TRAFFIC),
+        .HOTSPOT_NODE_NUM(HOTSPOT_NODE_NUM)
+    )  unicast  (
+        .en               (en              ),
+        .current_e_addr   (current_e_addr  ),
+        .core_num         (core_num        ),
+        .pck_number       (pck_number      ),
+        .dest_e_addr      (unicast_dest_e_addr),
+        .clk              (clk             ),
+        .reset            (reset           ),
+        .valid_dst        (valid_dst       ),
+        .hotspot_info     (hotspot_info    ),
+        .custom_traffic_t (custom_traffic_t),
+        .custom_traffic_en(custom_traffic_en)
+    ); 
+    
+    pck_size_gen #(
+        .MIN(MIN_PACKET_SIZE),
+        .MAX(MAX_PACKET_SIZE),
+        .PCK_SIZ_SEL(PCK_SIZ_SEL),
+        .DISCRETE_PCK_SIZ_NUM(DISCRETE_PCK_SIZ_NUM)
+    )  unicast_pck_size  (
+        .reset(reset),
+        .clk(clk),
+        .en(en),
+        .pck_size(pck_size_uni) ,
+        .rnd_discrete(rnd_discrete)
+    );
+    
+    generate
+    if(CAST_TYPE == "UNICAST") begin :uni
+        assign dest_e_addr =    unicast_dest_e_addr;
+        assign pck_size_o  =   pck_size_uni;
+    end else begin :multi
+        reg [DAw-1      :   0] multicast_dest_e_addr,temp; 
+        reg [6: 0] rnd_reg;
+        wire [PCK_SIZw-1 : 0] pck_size_mcast;
+        reg  [PCK_SIZw-1 : 0] pck_siz_tmp;
+        wire [NEw-1 : 0] unicast_id_num;  
+        
+        endp_addr_decoder enc (
+            .code_in(unicast_dest_e_addr),
+            .id_out(unicast_id_num)
+        );
+        
+        pck_size_gen #(
+            .MIN(MCAST_PCK_SIZ_MIN),
+            .MAX(MCAST_PCK_SIZ_MAX),
+            .PCK_SIZ_SEL("random-range"),
+            .DISCRETE_PCK_SIZ_NUM(DISCRETE_PCK_SIZ_NUM)
+        ) mcast_pck_size (
+            .reset(reset),
+            .clk(clk),
+            .en(en),
+            .pck_size(pck_size_mcast) ,
+            .rnd_discrete(rnd_discrete)
+        );    
+        
+        always @(posedge clk ) begin 
+            if(en | reset) begin 
+                rnd_reg <=   $urandom_range(99,0);
+            end
+        end
+        
+        if(CAST_TYPE == "MULTICAST_FULL") begin :mful
+        
+            always_comb begin 
+                multicast_dest_e_addr = {DAw{1'b0}};
+                temp={DAw{1'b0}};
+                temp[unicast_id_num]=1'b1;
+                pck_siz_tmp= pck_size_uni;
+                if(rnd_reg >= MCAST_TRAFFIC_RATIO) begin 
+                    multicast_dest_e_addr[unicast_id_num]=1'b1;
+                end
+                else begin 
+                    multicast_dest_e_addr =  $urandom();
+                    pck_siz_tmp=pck_size_mcast;
+                end
+                if(SELF_LOOP_EN  == 0) multicast_dest_e_addr[core_num]=1'b0;
+            end
+            
+            assign dest_e_addr = (multicast_dest_e_addr=={DAw{1'b0}} )? temp : multicast_dest_e_addr ;
+            assign pck_size_o = pck_siz_tmp;
+            
+        end else if(CAST_TYPE == "MULTICAST_PARTIAL") begin :mpar
+            
+            always_comb begin 
+                multicast_dest_e_addr = {DAw{1'b0}};
+                temp={unicast_dest_e_addr,1'b1};
+                pck_siz_tmp= pck_size_uni;
+                if(rnd_reg >= MCAST_TRAFFIC_RATIO) begin 
+                    multicast_dest_e_addr = {unicast_dest_e_addr,1'b1};
+                end
+                else begin 
+                    multicast_dest_e_addr =  $urandom();
+                    multicast_dest_e_addr[0] =1'b0;
+                    pck_siz_tmp=pck_size_mcast;
+                    if(SELF_LOOP_EN  == 0) begin
+                        if(MCAST_ENDP_LIST[core_num]==1'b1) multicast_dest_e_addr[endp_id_to_mcast_id(core_num)+1]=1'b0;
+                    end
+                end
+            end
+            
+            assign dest_e_addr = (multicast_dest_e_addr=={DAw{1'b0}} )? temp : multicast_dest_e_addr ;
+            assign pck_size_o = pck_siz_tmp;
+            
+        end else begin //Broadcast
+            
+            always_comb begin 
+                multicast_dest_e_addr = {DAw{1'b0}};
+                pck_siz_tmp = pck_size_uni;
+                if(rnd_reg >= MCAST_TRAFFIC_RATIO) begin 
+                    multicast_dest_e_addr = {unicast_dest_e_addr,1'b1};
+                end
+                else begin
+                    pck_siz_tmp=pck_size_mcast;
+                end
+            end
+            assign dest_e_addr =  multicast_dest_e_addr ;
+            assign pck_size_o = pck_siz_tmp;
+            
+            
+        end
+    end endgenerate
 endmodule
- 
- 
+
+/**********************************
+*      pck_dst_gen_unicast
+*********************************/
 module  pck_dst_gen_unicast  
 #(
-    parameter NOC_ID=0,
-	parameter TRAFFIC =   "RANDOM",
+    parameter TRAFFIC =   "RANDOM",
     parameter HOTSPOT_NODE_NUM =  4
 )(
     en,
@@ -299,16 +251,14 @@ module  pck_dst_gen_unicast
     reset,
     valid_dst,
     hotspot_info,
-	custom_traffic_t,
-	custom_traffic_en
+    custom_traffic_t,
+    custom_traffic_en
 ); 
- 
-    `NOC_CONF
-    localparam      ADDR_DIMENSION =   (TOPOLOGY ==    "MESH" || TOPOLOGY ==  "TORUS") ? 2 : 1;  // "RING" and FULLY_CONNECT 
-    
-     
-    localparam  PCK_CNTw = log2(MAX_PCK_NUM+1),
-                HOTSPOT_NUM= (TRAFFIC=="HOTSPOT")? HOTSPOT_NODE_NUM : 1;
+    import pronoc_pkg::*;
+    localparam
+        ADDR_DIMENSION =   (IS_MESH | IS_TORUS) ? 2 : 1,  // "RING" and FULLY_CONNECT 
+        PCK_CNTw = log2(MAX_PCK_NUM+1),
+        HOTSPOT_NUM= (TRAFFIC=="HOTSPOT")? HOTSPOT_NODE_NUM : 1;
     
     input                       reset,clk,en;
     input   [NEw-1      :   0]  core_num;
@@ -316,45 +266,32 @@ module  pck_dst_gen_unicast
     input   [EAw-1      :   0]  current_e_addr; 
     output  [EAw-1      :   0]  dest_e_addr; 
     output                      valid_dst; 
-	input  [NEw-1 : 0] custom_traffic_t;
-	input  custom_traffic_en;
-    
+    input  [NEw-1 : 0] custom_traffic_t;
+    input  custom_traffic_en;
     input hotspot_t  hotspot_info [HOTSPOT_NUM-1 : 0];
- 
- 
     generate 
-    if ( ADDR_DIMENSION == 2) begin :two_dim
-     
-        two_dimension_pck_dst_gen #(
-			.NOC_ID(NOC_ID),
-        	.TRAFFIC(TRAFFIC),
-        	.HOTSPOT_NODE_NUM(HOTSPOT_NODE_NUM)
-        	
-        )
-        the_two_dimension_pck_dst_gen
-        (
-        	.reset(reset),
-        	.clk(clk),
-        	.en(en),
-        	.core_num(core_num),
-        	.pck_number(pck_number),
-        	.current_e_addr(current_e_addr),
+    if ( IS_2D_TOPO | IS_3D_TOPO) begin : MD_
+        multi_dimension_pck_dst_gen #(
+            .TRAFFIC(TRAFFIC),
+            .HOTSPOT_NODE_NUM(HOTSPOT_NODE_NUM)
+        ) the_multi_dim_pck_dst_gen (
+            .reset(reset),
+            .clk(clk),
+            .en(en),
+            .core_num(core_num),
+            .pck_number(pck_number),
+            .current_e_addr(current_e_addr),
             .dest_e_addr(dest_e_addr),
-        	.valid_dst(valid_dst),
-        	.hotspot_info(hotspot_info),
-			.custom_traffic_t(custom_traffic_t),
-			.custom_traffic_en(custom_traffic_en)
+            .valid_dst(valid_dst),
+            .hotspot_info(hotspot_info),
+            .custom_traffic_t(custom_traffic_t),
+            .custom_traffic_en(custom_traffic_en)
         );
-        
     end else begin : one_dim
-      
         one_dimension_pck_dst_gen #(
-       		.NOC_ID(NOC_ID),
-			.TRAFFIC(TRAFFIC),
-       		.HOTSPOT_NODE_NUM(HOTSPOT_NODE_NUM)
-        )
-        the_one_dimension_pck_dst_gen
-        (
+            .TRAFFIC(TRAFFIC),
+            .HOTSPOT_NODE_NUM(HOTSPOT_NODE_NUM)
+        ) the_one_dimension_pck_dst_gen  (
             .reset(reset),
             .clk(clk),
             .en(en),
@@ -364,23 +301,20 @@ module  pck_dst_gen_unicast
             .dest_e_addr(dest_e_addr),
             .valid_dst(valid_dst),
             .hotspot_info(hotspot_info),
-			.custom_traffic_t(custom_traffic_t),
-			.custom_traffic_en(custom_traffic_en)
-        );       
-       
-    end     
+            .custom_traffic_t(custom_traffic_t),
+            .custom_traffic_en(custom_traffic_en)
+        );
+    end
     endgenerate 
 endmodule
- 
- 
- 
- 
-module two_dimension_pck_dst_gen  
+
+/**********************************
+*    multi_dimension_pck_dst_gen
+**********************************/
+module multi_dimension_pck_dst_gen  
 #(
-    parameter NOC_ID=0,
-	parameter TRAFFIC =   "RANDOM",
+    parameter TRAFFIC =   "RANDOM",
     parameter HOTSPOT_NODE_NUM =  4
-
 )(
     en,
     current_e_addr,
@@ -393,348 +327,151 @@ module two_dimension_pck_dst_gen
     hotspot_info,
     custom_traffic_t,
     custom_traffic_en
-);    
-    
-    `NOC_CONF
-
-   
-     
-     
-    localparam  PCK_CNTw = log2(MAX_PCK_NUM+1),
-                HOTSPOT_NUM= (TRAFFIC=="HOTSPOT")? HOTSPOT_NODE_NUM : 1;
-    
+);
+    import pronoc_pkg::*;
+    localparam  
+        PCK_CNTw = log2(MAX_PCK_NUM+1),
+        HOTSPOT_NUM= (TRAFFIC=="HOTSPOT")? HOTSPOT_NODE_NUM : 1;
     input                       reset,clk,en;
     input   [NEw-1      :   0]  core_num;
     input   [PCK_CNTw-1 :   0]  pck_number; 
     input   [EAw-1 : 0] current_e_addr;
-    output  [EAw-1 : 0]  dest_e_addr;
-    output                      valid_dst;  
+    output logic [EAw-1 : 0]  dest_e_addr;
+    output                      valid_dst;
     input hotspot_t  hotspot_info [HOTSPOT_NUM-1 : 0];
-	input  [NEw-1 : 0] custom_traffic_t;
-	input  custom_traffic_en;
-    
-  
+    input  [NEw-1 : 0] custom_traffic_t;
+    input  custom_traffic_en;
     
-    wire [NXw-1 : 0] current_x; 
-    wire [NYw-1 : 0] current_y;  
-    wire [NLw-1  : 0] current_l;    
-    wire [NXw-1 : 0] dest_x; 
-    wire [NYw-1 : 0] dest_y;
-    wire [NLw-1  : 0] dest_l;   
-        
-    mesh_tori_endp_addr_decode #(
-    	.TOPOLOGY(TOPOLOGY),
-    	.T1(T1),
-    	.T2(T2),
-    	.T3(T3),
-    	.EAw(EAw)
-    )
-    src_addr_decode
-    (
-    	.e_addr(current_e_addr),
-    	.ex(current_x),
-    	.ey(current_y),
-    	.el(current_l),
-    	.valid( )
-    );    
+    regular_topo_endp_addr_t current_addr, dest_addr;
+    always_comb begin 
+        current_addr = regular_topo_endp_addr_t'(current_e_addr);
+        //for 2d we need to re-extact the l
+        current_addr.l=current_e_addr[EAw-1: EAw-NLw];
+    end
     
     wire off_flag;
-  
-    
-    
-    
-    
-    wire    [NEw-1  :   0]  dest_ip_num;
+    wire [NEw-1  :   0]  dest_ip_num;
     genvar i;
-            
-    generate     
+    generate
     if (TRAFFIC == "RANDOM") begin 
-        
-    	logic [6 : 0] rnd_reg;
-    
-    	always @(posedge clk ) begin 
-    		if(en | `pronoc_reset) begin 
-    			rnd_reg =     $urandom_range(NE-1,0);
-    			if(SELF_LOOP_EN	== "NO")	while(rnd_reg==core_num) rnd_reg =     $urandom_range(NE-1,0);// get a random IP core, make sure its not same as sender core   			
-    			
-     		end    		
-    	end
-    	assign dest_ip_num = rnd_reg;
-       
-       endp_addr_encoder #(
-       	.T1(T1),
-       	.T2(T2),
-       	.T3(T3),
-       	.NE(NE),
-       	.EAw(EAw),
-       	.TOPOLOGY(TOPOLOGY)
-       )
-       addr_encoder
-       (
-       	.id(dest_ip_num),
-       	.code(dest_e_addr)
-       );
-           
-     end else if (TRAFFIC == "HOTSPOT") begin 
-                      
-     	hot_spot_dest_gen  #(
-			.NOC_ID(NOC_ID),
-     		.HOTSPOT_NUM(HOTSPOT_NUM),	
-     		.NE(NE),
-     		.NEw(NEw)
-     	) hspot (
-     		.reset(reset),
-     		.clk(clk),
-     		.en(en),
-     		.hotspot_info(hotspot_info),
-     		.dest_ip_num (dest_ip_num),
-     		.core_num(core_num),
-     		.off_flag(off_flag)
-     	);
-       
-        endp_addr_encoder #(
-            .T1(T1),
-            .T2(T2),
-            .T3(T3),
+        logic [6 : 0] rnd_reg;
+        always @(posedge clk ) begin 
+            if(en | `pronoc_reset) begin 
+                rnd_reg =     $urandom_range(NE-1,0);
+                if(SELF_LOOP_EN == 0)    while(rnd_reg==core_num) rnd_reg =     $urandom_range(NE-1,0);// get a random IP core, make sure its not same as sender core               
+            end
+        end
+        assign dest_ip_num = rnd_reg;
+        endp_addr_encoder addr_encoder (.id_in(dest_ip_num), .code_out(dest_e_addr));
+    end else if (TRAFFIC == "HOTSPOT") begin 
+        hot_spot_dest_gen  #(
+            .HOTSPOT_NUM(HOTSPOT_NUM),    
             .NE(NE),
-            .EAw(EAw),
-            .TOPOLOGY(TOPOLOGY)
-        ) addr_encoder (
-            .id(dest_ip_num),
-            .code(dest_e_addr)
-        ); 
-       
-        
+            .NEw(NEw)
+        ) hspot (
+            .reset(reset),
+            .clk(clk),
+            .en(en),
+            .hotspot_info(hotspot_info),
+            .dest_ip_num (dest_ip_num),
+            .core_num(core_num),
+            .off_flag(off_flag)
+        );
+        endp_addr_encoder addr_encoder (.id_in(dest_ip_num), .code_out(dest_e_addr));
+    end else if( TRAFFIC == "BIT_REVERSE") begin :bitreverse
+        for(i=0; i<(EAw); i=i+1'b1) begin :lp //reverse the address
+            assign dest_e_addr[i]  = current_e_addr [((EAw)-1)-i];
+        end
+        endp_addr_decoder enc (.code_in(dest_e_addr),.id_out(dest_ip_num));
+    end else if( TRAFFIC == "BIT_COMPLEMENT") begin :bitcomp
+        assign dest_e_addr  = ~ current_e_addr;
+        endp_addr_decoder enc (.code_in(dest_e_addr),.id_out(dest_ip_num));
     end else if( TRAFFIC == "TRANSPOSE1") begin 
-       
-        assign dest_x   = NX-current_y-1;
-        assign dest_y   = NY-current_x-1;
-        assign dest_l   = NL-current_l-1; 
-        assign dest_e_addr = (T3==1)? {dest_y,dest_x} : {dest_l,dest_y,dest_x};
-        
-        endp_addr_decoder  #(
-        	.T1(T1),
-        	.T2(T2),
-        	.T3(T3),
-        	.NE(NE),
-        	.EAw(EAw),
-        	.TOPOLOGY(TOPOLOGY)
-        )enc
-        (
-        	.code(dest_e_addr),
-        	.id(dest_ip_num)
-        );    
-        
-     
-        
-        
-      
-        
+        assign dest_addr.x = (NZ==1 && NY==1)? NX-current_addr.x-1 : NY-current_addr.y-1 ;
+        assign dest_addr.y = (NZ==1)? NX-current_addr.x-1 : NZ-current_addr.z-1 ;
+        assign dest_addr.z = NX-current_addr.x-1;
+        assign dest_addr.l = NL-current_addr.l-1;
+        always @(*) begin
+            dest_e_addr = EAw'(dest_addr);
+            if(NL>1) dest_e_addr[EAw-1: EAw-NLw]=dest_addr.l;
+        end
+        endp_addr_decoder enc (.code_in(dest_e_addr),.id_out(dest_ip_num));
     end else if( TRAFFIC == "TRANSPOSE2") begin :transpose2
-        
-        assign dest_x   = current_y;
-        assign dest_y   = current_x;
-        assign dest_l   = current_l;
-        assign dest_e_addr = (T3==1)? {dest_y,dest_x} : {dest_l,dest_y,dest_x};
-        
-        endp_addr_decoder  #(
-        		.T1(T1),
-        		.T2(T2),
-        		.T3(T3),
-        		.NE(NE),
-        		.EAw(EAw),
-        		.TOPOLOGY(TOPOLOGY)
-        	)enc
-        	(
-        		.code(dest_e_addr),
-        		.id(dest_ip_num)
-        	);    
-        
-          
-         
-    end  else if( TRAFFIC == "BIT_REVERSE") begin :bitreverse
-        
-        for(i=0; i<(EAw); i=i+1'b1) begin :lp//reverse the address
-            assign dest_ip_num[i]  = current_e_addr [((EAw)-1)-i];
+        assign dest_addr.x = (NZ==1 && NY==1)? NX-current_addr.x-1 : current_addr.y;
+        assign dest_addr.y = ( NZ==1)?  current_addr.x : current_addr.z;
+        assign dest_addr.z   = current_addr.x;
+        assign dest_addr.l = current_addr.l;
+        always @(*) begin 
+            dest_e_addr = EAw'(dest_addr);
+            if(NL>1) dest_e_addr[EAw-1: EAw-NLw]=dest_addr.l;
         end
-                   
-        endp_addr_encoder #(
-            .T1(T1),
-            .T2(T2),
-            .T3(T3),
-            .NE(NE),
-            .EAw(EAw),
-            .TOPOLOGY(TOPOLOGY)
-        )
-        addr_encoder(
-            .id(dest_ip_num),
-            .code(dest_e_addr)
-        ); 
-              
-   
-    end  else if( TRAFFIC == "BIT_COMPLEMENT") begin :bitcomp
-
-        assign dest_x   = ~current_x;
-        assign dest_y   = ~current_y;  
-        assign dest_l   = ~dest_l;
-        assign dest_e_addr = (T3==1)? {dest_y,dest_x} : {dest_l,dest_y,dest_x};
-       
-        endp_addr_decoder  #(
-        		.T1(T1),
-        		.T2(T2),
-        		.T3(T3),
-        		.NE(NE),
-        		.EAw(EAw),
-        		.TOPOLOGY(TOPOLOGY)
-        	)enc
-        	(
-        		.code(dest_e_addr),
-        		.id(dest_ip_num)
-        	);    
-        
-        
-        
-                    
+        endp_addr_decoder enc (.code_in(dest_e_addr),.id_out(dest_ip_num));
     end else if( TRAFFIC == "TORNADO" ) begin :tornado
         //[(x+(k/2-1)) mod k, (y+(k/2-1)) mod k],
-        assign dest_x  = (current_x> ((NX+1)/2))? current_x- ((NX+1)/2) -1   :  (NX/2)+current_x-1;  //  = ((current_x + ((NX/2)-1))%NX); 
-        assign dest_y  = (current_y> ((NY+1)/2))? current_y- ((NY+1)/2) -1   :  (NY/2)+current_y-1;  //  = ((current_y + ((NY/2)-1))%NY);
-        assign dest_l   = current_l;
-        assign dest_e_addr = (T3==1)? {dest_y,dest_x} : {dest_l,dest_y,dest_x};
-      
-        endp_addr_decoder  #(
-        		.T1(T1),
-        		.T2(T2),
-        		.T3(T3),
-        		.NE(NE),
-        		.EAw(EAw),
-        		.TOPOLOGY(TOPOLOGY)
-        	)enc
-        	(
-        		.code(dest_e_addr),
-        		.id(dest_ip_num)
-        	);    
-        
-        
-        
-   
-	end else if( TRAFFIC == "NEIGHBOR")  begin :neighbor
-		//dx = sx + 1 mod k
-		 assign dest_x = (current_x + 1) >= NX? 0 : (current_x + 1);
-		 assign dest_y = (current_y + 1) >= NY? 0 : (current_y + 1);
-		 assign dest_l = current_l;
-		 assign dest_e_addr = (T3==1)? {dest_y,dest_x} : {dest_l,dest_y,dest_x};
-		
-		 endp_addr_decoder  #(
-		 		.T1(T1),
-		 		.T2(T2),
-		 		.T3(T3),
-		 		.NE(NE),
-		 		.EAw(EAw),
-		 		.TOPOLOGY(TOPOLOGY)
-		 	)enc
-		 	(
-		 		.code(dest_e_addr),
-		 		.id(dest_ip_num)
-		 	);    
-		 
-		 
-		 
-		 
-	end else if( TRAFFIC == "SHUFFLE") begin: shuffle
-		//di = si−1 mod b
-		for(i=1; i<(EAw); i=i+1'b1) begin :lp//reverse the address
-            assign dest_ip_num[i]  = current_e_addr [i-1];
+        assign dest_addr.x  = (current_addr.x> ((NX+1)/2))? current_addr.x- ((NX+1)/2) -1   :  (NX/2)+current_addr.x-1;  //  = ((current_x + ((NX/2)-1))%NX); 
+        assign dest_addr.y  = (current_addr.y> ((NY+1)/2))? current_addr.y- ((NY+1)/2) -1   :  (NY/2)+current_addr.y-1;  //  = ((current_y + ((NY/2)-1))%NY);
+        assign dest_addr.z  = (current_addr.z> ((NZ+1)/2))? current_addr.z- ((NZ+1)/2) -1   :  (NZ/2)+current_addr.z-1;  //  = ((current_z + ((NZ/2)-1))%NZ);
+        assign dest_addr.l  = current_addr.l;
+        always @(*) begin 
+            dest_e_addr = EAw'(dest_addr);
+            if(NL>1) dest_e_addr[EAw-1: EAw-NLw]=dest_addr.l;
         end
-		assign dest_ip_num[0]  = current_e_addr [EAw-1];		
-		 endp_addr_encoder #(
-            .T1(T1),
-            .T2(T2),
-            .T3(T3),
-            .NE(NE),
-            .EAw(EAw),
-            .TOPOLOGY(TOPOLOGY)
-        )
-        addr_encoder(
-            .id(dest_ip_num),
-            .code(dest_e_addr)
-        );
-		
-		
+        endp_addr_decoder enc (.code_in(dest_e_addr),.id_out(dest_ip_num));
+    end else if( TRAFFIC == "NEIGHBOR")  begin :neighbor
+        //dx = sx + 1 mod k
+        assign dest_addr.x = ((current_addr.x + 1) >= NX) ? 0 : (current_addr.x + 1);
+        assign dest_addr.y = ((current_addr.y + 1) >= NY) ? 0 : (current_addr.y + 1);
+        assign dest_addr.z = ((current_addr.z + 1) >= NZ) ? 0 : (current_addr.z + 1);
+        assign dest_addr.l = current_addr.l;
+        always @(*) begin 
+            dest_e_addr = EAw'(dest_addr);
+            if(NL>1) dest_e_addr[EAw-1: EAw-NLw]=dest_addr.l;
+        end
+        endp_addr_decoder enc (.code_in(dest_e_addr),.id_out(dest_ip_num));
+    end else if( TRAFFIC == "SHUFFLE") begin: shuffle
+        //di = si-1 mod b
+        for(i=1; i<(EAw); i=i+1'b1) begin :lp//reverse the address
+            assign dest_e_addr[i]  = current_e_addr [i-1];
+        end
+        assign dest_e_addr[0]  = current_e_addr [EAw-1];
+        endp_addr_decoder enc (.code_in(dest_e_addr),.id_out(dest_ip_num));
     end else if(TRAFFIC == "BIT_ROTATION") begin :bitrot
-		//di = si+1 mod b
-		for(i=0; i<(EAw-1); i=i+1'b1) begin :lp//reverse the address
-            assign dest_ip_num[i]  = current_e_addr [i+1];
+        //di = si+1 mod b
+        for(i=0; i<(EAw-1); i=i+1'b1) begin :lp//reverse the address
+            assign dest_e_addr[i]  = current_e_addr [i+1];
         end
-		assign dest_ip_num[EAw-1]  = current_e_addr [0];		
-		endp_addr_encoder #(
-            .T1(T1),
-            .T2(T2),
-            .T3(T3),
-            .NE(NE),
-            .EAw(EAw),
-            .TOPOLOGY(TOPOLOGY)
-        )
-        addr_encoder(
-            .id(dest_ip_num),
-            .code(dest_e_addr)
-        ); 
-		
-	end else if(TRAFFIC == "CUSTOM" )begin 
-		
+        assign dest_e_addr[EAw-1]  = current_e_addr [0];
+        endp_addr_decoder enc (.code_in(dest_e_addr),.id_out(dest_ip_num));
+    end else if(TRAFFIC == "CUSTOM" )begin 
         assign dest_ip_num = custom_traffic_t;
-		 endp_addr_encoder #(
-            .T1(T1),
-            .T2(T2),
-            .T3(T3),
-            .NE(NE),
-            .EAw(EAw),
-            .TOPOLOGY(TOPOLOGY)
-        )
-        addr_encoder
-        (
-            .id(dest_ip_num),
-            .code(dest_e_addr)
+        endp_addr_encoder addr_encoder (
+            .id_in(dest_ip_num),
+            .code_out(dest_e_addr)
         );
-	
-		assign  off_flag  =  ~custom_traffic_en;	
-		 
-		      
+        assign  off_flag  =  ~custom_traffic_en;    
     end  else begin 
-			initial begin 
-				$display("ERROR: Undefined Traffic pattern:%s",TRAFFIC);
-				$stop;
-			end
-	end
+            initial begin 
+                $display("ERROR: Undefined Traffic pattern:%s",TRAFFIC);
+                $stop;
+            end
+    end
     
-    	
-    	
-    	wire valid_temp  =    (dest_ip_num  <= (NE-1));	
-    	
-    	if (TRAFFIC == "HOTSPOT" || TRAFFIC == "CUSTOM") begin 
-    		assign valid_dst  = ~off_flag & valid_temp;
-    	end else begin 
-    		assign valid_dst  =  valid_temp;
-    	end	
-     
+    wire valid_temp  =    (dest_ip_num  <= (NE-1));    
     
+    if (TRAFFIC == "HOTSPOT" || TRAFFIC == "CUSTOM") begin 
+        assign valid_dst  = ~off_flag & valid_temp;
+    end else begin 
+        assign valid_dst  =  valid_temp;
+    end
     endgenerate
-     
 endmodule
 
-
-
-/************
-
+/************ 
+*
 ************/
-
-
-module one_dimension_pck_dst_gen 
-#(
-	parameter NOC_ID=0,
-	parameter TRAFFIC =   "RANDOM",
-	parameter HOTSPOT_NODE_NUM =  4
-
+module one_dimension_pck_dst_gen #(
+    parameter TRAFFIC =   "RANDOM",
+    parameter HOTSPOT_NODE_NUM =  4
 )(
     en,
     core_num,
@@ -748,10 +485,7 @@ module one_dimension_pck_dst_gen
     custom_traffic_t,
     custom_traffic_en
 ); 
-      
-    `NOC_CONF 
-
-     
+    import pronoc_pkg::*; 
     localparam 
         PCK_CNTw = log2(MAX_PCK_NUM+1),
         HOTSPOT_NUM= (TRAFFIC=="HOTSPOT")? HOTSPOT_NODE_NUM : 1;
@@ -763,248 +497,201 @@ module one_dimension_pck_dst_gen
     output  [EAw-1       :   0]  dest_e_addr;   
     output  valid_dst;  
     input hotspot_t  hotspot_info [HOTSPOT_NUM-1 : 0];
-	input  [NEw-1 : 0] custom_traffic_t; 
-	input  custom_traffic_en;
+    input  [NEw-1 : 0] custom_traffic_t; 
+    input  custom_traffic_en;
         
     wire [NEw-1 : 0] dest_ip_num;
     wire off_flag;
     genvar i;            
     generate     
     if (TRAFFIC == "RANDOM") begin 
-    	logic [6 : 0] rnd_reg;
-    
-    	always @(posedge clk ) begin 
-    		if(en | `pronoc_reset) begin 
-    			rnd_reg =     $urandom_range(NE-1,0);
-    			if(SELF_LOOP_EN	== "NO")	while(rnd_reg==core_num) rnd_reg =     $urandom_range(NE-1,0);// get a random IP core, make sure its not same as sender core   			
-     		end    		
-    	end
-    	assign dest_ip_num = rnd_reg;
-         
-        
-     end else if (TRAFFIC == "HOTSPOT") begin 
-        
-     	hot_spot_dest_gen  #(
-     		.NOC_ID(NOC_ID),
-			.HOTSPOT_NUM(HOTSPOT_NUM),	
-     		.NE(NE),
-     		.NEw(NEw)
-		) hspot (
-     		.clk(clk),
-     		.en(en),
-     		.hotspot_info(hotspot_info),
-     		.dest_ip_num (dest_ip_num),
-     		.core_num(core_num),
-     		.off_flag(off_flag)
-     	);     	
-     	
-       
+        logic [6 : 0] rnd_reg;
+        always @(posedge clk ) begin 
+            if(en | `pronoc_reset) begin 
+                rnd_reg =     $urandom_range(NE-1,0);
+                if(SELF_LOOP_EN == 0)    while(rnd_reg==core_num) rnd_reg =     $urandom_range(NE-1,0);// get a random IP core, make sure its not same as sender core               
+            end
+        end
+        assign dest_ip_num = rnd_reg;
+    end else if (TRAFFIC == "HOTSPOT") begin 
+        hot_spot_dest_gen  #(
+            .HOTSPOT_NUM(HOTSPOT_NUM),
+            .NE(NE),
+            .NEw(NEw)
+        ) hspot (
+            .clk(clk),
+            .en(en),
+            .hotspot_info(hotspot_info),
+            .dest_ip_num (dest_ip_num),
+            .core_num(core_num),
+            .off_flag(off_flag)
+        );
     end else if( TRAFFIC == "TRANSPOSE1") begin :tran1
-    
         assign dest_ip_num   = NE-core_num-1;                  
-        
     end  else if( TRAFFIC == "BIT_REVERSE") begin :bitreverse
-    
         for(i=0; i<NEw; i=i+1'b1) begin :lp//reverse the address
             assign dest_ip_num[i]  = core_num [NEw-1-i];
         end
-        
     end  else if( TRAFFIC == "BIT_COMPLEMENT") begin :bitcomp
-                              
-            assign dest_ip_num   = ~core_num;
-    
+        assign dest_ip_num   = ~core_num;
     end else if( TRAFFIC == "TORNADO" ) begin :tornado
         //[(x+(k/2-1)) mod k, (y+(k/2-1)) mod k],
-          assign dest_ip_num  = (core_num > ((NE+1)/2))? core_num- ((NE+1)/2) -1   :  (NE/2)+core_num-1;  //  = ((current_x + ((NX/2)-1))%NX);
-           
-	end else if( TRAFFIC == "NEIGHBOR")  begin :neighbor
-		//dx = sx + 1 mod k
-		 assign dest_ip_num = ((core_num + 1) >= NE) ? 0 : (core_num + 1);
-		
-	end else if( TRAFFIC == "SHUFFLE") begin: shuffle
-		//di = si−1 mod b
-		for(i=1; i<(NEw); i=i+1'b1) begin :lp
+         assign dest_ip_num  = (core_num > ((NE+1)/2))? core_num- ((NE+1)/2) -1   :  (NE/2)+core_num-1;  //  = ((current_x + ((NX/2)-1))%NX);
+    end else if( TRAFFIC == "NEIGHBOR")  begin :neighbor
+        //dx = sx + 1 mod k
+        assign dest_ip_num = ((core_num + 1) >= NE) ? 0 : (core_num + 1);
+        
+    end else if( TRAFFIC == "SHUFFLE") begin: shuffle
+        //di = si−1 mod b
+        for(i=1; i<(NEw); i=i+1'b1) begin :lp
             assign dest_ip_num[i]  = core_num [i-1];
         end
-		assign dest_ip_num[0]  = core_num [NEw-1];				 
-		
+        assign dest_ip_num[0]  = core_num [NEw-1];                 
     end else if(TRAFFIC == "BIT_ROTATION") begin :bitrot
-		//di = si+1 mod b
-		for(i=0; i<(NEw-1); i=i+1) begin :lp//reverse the address
+        //di = si+1 mod b
+        for(i=0; i<(NEw-1); i=i+1) begin :lp//reverse the address
             assign dest_ip_num[i]  = core_num [i+1];
         end
-		assign dest_ip_num[NEw-1]  = core_num [0];		
-	
-	end else if(TRAFFIC == "CUSTOM" )begin
-		assign off_flag = ~custom_traffic_en;
-         assign dest_ip_num = custom_traffic_t;
-    end   
-   
-    endp_addr_encoder #(
-        .T1(T1),
-        .T2(T2),
-        .T3(T3),
-        .NE(NE),
-        .EAw(EAw),
-        .TOPOLOGY(TOPOLOGY)
-    )
-    addr_encoder
-    (
-        .id(dest_ip_num),
-        .code(dest_e_addr)
+        assign dest_ip_num[NEw-1]  = core_num [0];        
+    end else if(TRAFFIC == "CUSTOM" )begin
+        assign off_flag = ~custom_traffic_en;
+        assign dest_ip_num = custom_traffic_t;
+    end
+    
+    endp_addr_encoder  addr_encoder  (
+        .id_in(dest_ip_num),
+        .code_out(dest_e_addr)
     );
-      
-    wire valid_temp  =    (dest_ip_num  <= (NE-1));	
-    	
+    
+    wire valid_temp  =    (dest_ip_num  <= (NE-1));    
     if (TRAFFIC == "HOTSPOT" || TRAFFIC == "CUSTOM") begin 
-    	assign valid_dst  = ~off_flag & valid_temp;
+        assign valid_dst  = ~off_flag & valid_temp;
     end else begin 
-    	assign valid_dst  =  valid_temp;
+        assign valid_dst  =  valid_temp;
     end
-   
     endgenerate
-     
+    
 endmodule
- 
+
 /***************************
  *  pck_size_gen
  * *************************/
-
 module pck_size_gen
 #(
-    parameter NOC_ID=0,
-	parameter MIN = 2,
+    parameter MIN = 2,
     parameter MAX = 5,
-    parameter PCK_SIZ_SEL="random-discrete",	
+    parameter PCK_SIZ_SEL="random-discrete",
     parameter DISCRETE_PCK_SIZ_NUM=1
-)
-(
+)(
     reset,
     clk,
     en,
     pck_size,
     rnd_discrete
 );
-
-	`NOC_CONF
-
-	input rnd_discrete_t rnd_discrete [DISCRETE_PCK_SIZ_NUM-1: 0];
-     
-
+    import pronoc_pkg::*;
+    input rnd_discrete_t rnd_discrete [DISCRETE_PCK_SIZ_NUM-1: 0];
     input reset, clk, en;
     output [PCK_SIZw-1 : 0] pck_size;
-
     
     generate
-	if(PCK_SIZ_SEL == "random-discrete"	) begin :discrete
-		if(DISCRETE_PCK_SIZ_NUM==1) begin :single 
-			assign pck_size = rnd_discrete[0].value;
-		end else begin :multi
-			reg [PCK_SIZw-1 : 0] rnd,rnd_next;
-			integer rnd2;
-			integer k;
-			always @(*) begin 
-				rnd_next = rnd;
-				if(en) begin 
-					if(rnd2 < rnd_discrete[0].percentage) rnd_next = rnd_discrete[0].value;
-					for (k=1;k<DISCRETE_PCK_SIZ_NUM;k++)begin 
-						if(rnd2 >= rnd_discrete[k-1].percentage && rnd2 < rnd_discrete[k].percentage) rnd_next = rnd_discrete[k].value;
-					end
-				end	
-			end//always
-			
-			
-			always @(posedge clk) begin 
-				if(`pronoc_reset)  begin 
-					rnd2<= 0;
-					rnd <= rnd_discrete[0].value;					
-				end else  begin 
-					if(en) rnd2<= $urandom_range(99,0);
-					rnd <= rnd_next;
-				end
-			end//always
-			
-			assign pck_size = rnd;
-		end//multi
-		
-	end else begin :range
-		if (MIN == MAX) begin :eq 
-	        assign pck_size = MIN;
-	    end  else begin :noteq
-	        reg [PCK_SIZw-1 : 0] rnd;
-	        always @(posedge clk) begin 
-	            if(`pronoc_reset) rnd = MIN;
-	            else if(en) rnd = $urandom_range(MAX,MIN);
-	        end
-	        assign pck_size = rnd;
-	    end
-	end
-	endgenerate
+    if(PCK_SIZ_SEL == "random-discrete"    ) begin :discrete
+        if(DISCRETE_PCK_SIZ_NUM==1) begin :single 
+            assign pck_size = rnd_discrete[0].value;
+        end else begin :multi
+            reg [PCK_SIZw-1 : 0] rnd,rnd_next;
+            integer rnd2;
+            integer k;
+            always_comb begin 
+                rnd_next = rnd;
+                if(en) begin 
+                    if(rnd2 < rnd_discrete[0].percentage) rnd_next = rnd_discrete[0].value;
+                    for (k=1;k<DISCRETE_PCK_SIZ_NUM;k++)begin 
+                        if(rnd2 >= rnd_discrete[k-1].percentage && rnd2 < rnd_discrete[k].percentage) rnd_next = rnd_discrete[k].value;
+                    end
+                end    
+            end//always
+            
+            always @(posedge clk) begin 
+                if(`pronoc_reset)  begin 
+                    rnd2<= 0;
+                    rnd <= rnd_discrete[0].value;                    
+                end else  begin 
+                    if(en) rnd2<= $urandom_range(99,0);
+                    rnd <= rnd_next;
+                end
+            end//always
+            assign pck_size = rnd;
+        end//multi
+    end else begin :range
+        if (MIN == MAX) begin :eq 
+            assign pck_size = MIN;
+        end  else begin :noteq
+            reg [PCK_SIZw-1 : 0] rnd;
+            always @(posedge clk) begin 
+                if(`pronoc_reset) rnd = MIN;
+                else if(en) rnd = $urandom_range(MAX,MIN);
+            end
+            assign pck_size = rnd;
+        end
+    end
+    endgenerate
 endmodule 
 
 
-
-
+/**********************
+* hot_spot_dest_gen 
+************************/
 module hot_spot_dest_gen 
 #(
-   parameter NOC_ID=0,
-   parameter HOTSPOT_NUM=2
+    parameter HOTSPOT_NUM=2
 ) (
-   clk,
-   reset,
-   en,
-   hotspot_info,
-   core_num,
-   dest_ip_num,
-   off_flag
+    clk,
+    reset,
+    en,
+    hotspot_info,
+    core_num,
+    dest_ip_num,
+    off_flag
 );
-	
-   `NOC_CONF
-
-	input clk,en,reset;
-	input hotspot_t  hotspot_info [HOTSPOT_NUM-1 : 0];
-	input   [NEw-1 : 0] core_num;
-	output  [NEw-1 : 0] dest_ip_num;
-	output reg off_flag;
-	
-	logic [6 : 0] rnd_reg, hotspot_node;
-	reg [9 : 0] rnd1000;
-	always @(posedge clk ) begin 
-		if(en | `pronoc_reset) begin 
-			rnd_reg =     $urandom_range(NE-1,0);
-			if(SELF_LOOP_EN	== "NO")	while(rnd_reg==core_num) rnd_reg =     $urandom_range(NE-1,0);// get a random IP core, make sure its not same as sender core    			
-     			
-			rnd1000 =     $urandom_range(999,0);// generate a random number between 0 & 1000     					
-		end    		
-	end
-     	
-	logic hotspot_flag;
-	integer i;
-	
-	always @(*)begin 
-		off_flag=0;
-		for (i=0;i<HOTSPOT_NUM; i=i+1)begin
-			if ( hotspot_info[i].send_enable == 0 && core_num ==hotspot_info[i].ip_num)begin
-				off_flag=1;
-			end
-		end
-		hotspot_flag=0;
-		hotspot_node=0;
-		if ( rnd1000 < hotspot_info[0].percentage && core_num !=hotspot_info[0].ip_num)begin 
-			hotspot_flag=1;
-			hotspot_node=hotspot_info[0].ip_num;
-		end else begin
-			for (i=1;i<HOTSPOT_NUM; i=i+1)begin
-				if (rnd1000 >= hotspot_info[i-1].percentage && rnd1000 < hotspot_info[i].percentage && core_num !=hotspot_info[i].ip_num) begin
-					hotspot_flag=1;
-					hotspot_node=hotspot_info[i].ip_num;
-				end
-			end end
-     		
-	end  
-	
-	
-	assign dest_ip_num = (off_flag)? core_num : (hotspot_flag)? hotspot_node : rnd_reg;
-     	
-     	
-endmodule	
+    import pronoc_pkg::*;
+    input clk,en,reset;
+    input hotspot_t  hotspot_info [HOTSPOT_NUM-1 : 0];
+    input   [NEw-1 : 0] core_num;
+    output  [NEw-1 : 0] dest_ip_num;
+    output reg off_flag;
+    
+    logic [6 : 0] rnd_reg, hotspot_node;
+    reg [9 : 0] rnd1000;
+    always @(posedge clk ) begin 
+        if(en | `pronoc_reset) begin 
+            rnd_reg =     $urandom_range(NE-1,0);
+            if(SELF_LOOP_EN    == 0)    while(rnd_reg==core_num) rnd_reg =     $urandom_range(NE-1,0);// get a random IP core, make sure its not same as sender core                
+            rnd1000 =     $urandom_range(999,0);// generate a random number between 0 & 1000
+        end
+    end
+    logic hotspot_flag;
+    integer i;
+    always_comb begin 
+        off_flag=0;
+        for (i=0;i<HOTSPOT_NUM; i=i+1)begin
+            if ( hotspot_info[i].send_enable == 0 && core_num ==hotspot_info[i].ip_num)begin
+                off_flag=1;
+            end
+        end
+        hotspot_flag=0;
+        hotspot_node=0;
+        if ( rnd1000 < hotspot_info[0].percentage && core_num !=hotspot_info[0].ip_num)begin 
+            hotspot_flag=1;
+            hotspot_node=hotspot_info[0].ip_num;
+        end else begin
+            for (i=1;i<HOTSPOT_NUM; i=i+1)begin
+                if (rnd1000 >= hotspot_info[i-1].percentage && rnd1000 < hotspot_info[i].percentage && core_num !=hotspot_info[i].ip_num) begin
+                    hotspot_flag=1;
+                    hotspot_node=hotspot_info[i].ip_num;
+                end
+            end 
+        end
+    end
+    assign dest_ip_num = (off_flag)? core_num : (hotspot_flag)? hotspot_node : rnd_reg;
+endmodule
diff --git a/mpsoc/rtl/src_multi_mesh/mesh_cluster.sv b/mpsoc/rtl/src_multi_mesh/mesh_cluster.sv
new file mode 100644
index 0000000..e916691
--- /dev/null
+++ b/mpsoc/rtl/src_multi_mesh/mesh_cluster.sv
@@ -0,0 +1,645 @@
+`include "pronoc_def.v"
+/**********************************************************************
+**    File:  mesh_cluster.sv
+**
+**    Copyright (C) 2014-2017  Alireza Monemi
+**
+**    This file is part of ProNoC
+**
+**    ProNoC ( stands for Prototype Network-on-chip)  is free software:
+**    you can redistribute it and/or modify it under the terms of the GNU
+**    Lesser General Public License as published by the Free Software Foundation,
+**    either version 2 of the License, or (at your option) any later version.
+**
+**     ProNoC is distributed in the hope that it will be useful, but WITHOUT
+**     ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+**     or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
+**     Public License for more details.
+**
+**     You should have received a copy of the GNU Lesser General Public
+**     License along with ProNoC. If not, see <http:**www.gnu.org/licenses/>.
+**
+**
+**
+**    Description:
+**    A `mesh_cluster` refers to a group of interconnected routers arranged in a **3D Mesh topology**
+**    within a larger **Multi-Mesh NoC** for chiplets. In this architecture, each chiplet functions
+**    as an independent cluster of nodes, featuring its own local mesh-based communication network.
+**
+**    Each router in the `mesh_cluster` drives two I/O channels:
+**    1. **Endpoint Channel** – Connects to processing elements (PEs) or memory endpoints.
+**    2. **Vertical Link Channel** – Facilitates inter-cluster communication.
+**
+**    If an endpoint or vertical link is not present in the target Multi-Mesh topology,
+**    the corresponding input is tied to **ground**, enabling synthesis optimizations
+**    that effectively remove unused logic.
+**
+***************************************/
+
+
+module mesh_cluster
+    import pronoc_pkg::*;
+#(
+    parameter
+        CLUSTER_ID = 0,
+        RID_INIT = 0,
+            // The initial value of Router IDs (RIDs) in this mesh cluster.
+            // This parameter is used to generate unique RIDs for each router in the cluster.
+            // It ensures that RIDs are distinct across multiple meshes when used in a multi-mesh configuration.
+        CLUSTER_NX = 2,
+            //Total number of nodes in the X dimension (horizontal axis) of the mesh cluster.
+        CLUSTER_NY = 2,
+            //Total number of nodes in the Y dimension (vertical axis) of the mesh cluster.
+        CLUSTER_NZ = 2,
+            //Total number of nodes in the Z dimension (depth axis) of the mesh cluster.
+        CLUSTER_NE = 8,
+            // Total number of endpoints (processing elements)
+
+    localparam
+        CLUSTER_NR = CLUSTER_NX * CLUSTER_NY * CLUSTER_NZ,
+            // Total number of routers in cluster
+        CLUSTER_NVP =
+            // Total number of vertical ports per router used for inter-cluster
+            // communication i.e. the down ports of the routers on the first
+            // layer and the up ports of the routers in the last layer
+            (CLUSTER_NX * CLUSTER_NY) * 2,
+        CLUSTER_MAX_P = 7
+)(
+    input logic clk,
+    input logic reset,
+    input logic [CLUSTER_IDw-1:0] cluster_id,
+    // Endpoints ports
+    input  smartflit_chanel_t endpoint_chan_in [CLUSTER_NE-1:0],
+    output smartflit_chanel_t endpoint_chan_out[CLUSTER_NE-1:0],
+    // Inter-Cluster interconnect ports
+    input  smartflit_chanel_t inter_cluster_chan_in [CLUSTER_NVP-1:0],
+    output smartflit_chanel_t inter_cluster_chan_out[CLUSTER_NVP-1:0],
+    // Events
+    output router_event_t router_event[CLUSTER_NR-1:0][CLUSTER_MAX_P-1:0]
+);
+    // Indididual routers interconnect ports
+    smartflit_chanel_t router_chan_in [CLUSTER_NZ-1:0][CLUSTER_NY-1:0][CLUSTER_NX-1:0][CLUSTER_MAX_P-1:0];
+    smartflit_chanel_t router_chan_out[CLUSTER_NZ-1:0][CLUSTER_NY-1:0][CLUSTER_NX-1:0][CLUSTER_MAX_P-1:0];
+
+    // Unused Input channels are connected to ground
+    smartflit_chanel_t is_grounded;
+    assign is_grounded = {SMARTFLIT_CHANEL_w{1'b0}};
+
+    multimesh_router_addr_t current_r_addr[CLUSTER_NR-1:0];
+    router_config_t router_config_in[CLUSTER_NR-1:0];
+
+    genvar x, y, z;
+    generate
+    for (z = 0; z < CLUSTER_NZ; z = z + 1) begin: Z_
+        for (y = 0; y < CLUSTER_NY; y = y + 1) begin: Y_
+            for (x = 0; x < CLUSTER_NX; x = x + 1) begin: X_
+                localparam
+                    V_DOWN_ID = (y * CLUSTER_NX) + x,
+                    V_UP_ID = (y * CLUSTER_NX) + x + (CLUSTER_NX * CLUSTER_NY),
+                    RID = z * (CLUSTER_NX * CLUSTER_NY) + (y * CLUSTER_NX) + x,
+                    EID = RID,
+                    // NOTE: as an optimization, we could disable the Up/Down
+                    // ICR also when no VL reaches the router
+                    UP_ICR_EN    = (z == 0),
+                    DOWN_ICR_EN  = (z == (CLUSTER_NZ-1)),
+                    // NOTE: as an optimization, we could disable it if there
+                    // is no endpoint connected
+                    LOCAL_ICR_EN = 1,
+                    // NOTE: as an optimization, we could only enable the ICR
+                    // of the 2D ports when an endpoint is connected
+                    NORTH_ICR_EN = 1,
+                    SOUTH_ICR_EN = 1,
+                    WEST_ICR_EN  = 1,
+                    EAST_ICR_EN  = 1;
+
+                assign current_r_addr[RID] = '{x:x, y:y, z:z, c:cluster_id};
+
+                depth_first_router #(
+                    .ROUTER_ID(RID+RID_INIT),
+                    .P(CLUSTER_MAX_P),
+                    // NOTE: ICR must be enable for:
+                    // (*) The port Up (or Down) when a VL leaves or (reaches)
+                    //     the port and the Router Z dimension is 0 or Max_Z ;
+                    // (*) The local port, if an endpoint is connected to it ;
+                    // (*) Any 2D port (N/S/W/E) where an endpoint is connected
+                    //     to it ;
+                    .UP_ICR_EN(UP_ICR_EN),
+                    .DOWN_ICR_EN(DOWN_ICR_EN),
+                    .LOCAL_ICR_EN(LOCAL_ICR_EN),
+                    .NORTH_ICR_EN(NORTH_ICR_EN),
+                    .SOUTH_ICR_EN(SOUTH_ICR_EN),
+                    .WEST_ICR_EN(WEST_ICR_EN),
+                    .EAST_ICR_EN(EAST_ICR_EN)
+`ifndef DYNAMIC_CLUSTER_INIT
+                    ,.CLUSTER_ID(CLUSTER_ID),
+                    .CLUSTER_RID(RID)
+`endif
+                ) the_router(
+                    .clk(clk),
+                    .reset(reset),
+`ifdef DYNAMIC_CLUSTER_INIT
+                    // NOTE: The dynamic ICRT has not been integrated for now
+                    .program_port(),
+`endif
+                    .router_config_in(router_config_in[RID]),
+                    .chan_in(router_chan_in [z][y][x]),
+                    .chan_out(router_chan_out[z][y][x]),
+                    .router_event(router_event[RID])
+                );
+                assign router_config_in[RID].router_addr = current_r_addr[RID];
+                assign router_config_in[RID].endp_addrs = current_r_addr[RID];
+                assign router_config_in[RID].router_id = RID+RID_INIT;
+                assign router_config_in[RID].endp_ids = RID+RID_INIT;
+                // **Mesh Interconnect Logic**
+`ifndef PITON_EXTRA_MEMS
+                assign router_chan_in[z][y][x][EAST] = (x < CLUSTER_NX-1) ?
+                    router_chan_out[z][y][x+1][WEST] : is_grounded;
+                assign router_chan_in[z][y][x][NORTH] = (y > 0) ?
+                    router_chan_out[z][y-1][x][SOUTH] : is_grounded;
+    // ProNoC is used standalone, without OpenPiton
+    `ifndef PITON_PRONOC
+                assign router_chan_in[z][y][x][WEST] =  (x > 0) ?
+                    router_chan_out[z][y][x-1][EAST] : is_grounded;
+    `else // PITON_PRONOC
+                if (CLUSTER_ID == 0) begin
+                    // Leave the western connection (x=0) unconnected
+                    if (x > 0) begin
+                        assign router_chan_in[z][y][x][WEST] =
+                            router_chan_out[z][y][x-1][EAST];
+                    end
+                end else begin
+                    assign router_chan_in[z][y][x][WEST] =  (x > 0) ?
+                        router_chan_out[z][y][x-1][EAST] : is_grounded;
+                end
+    `endif // PITON_PRONOC
+                assign router_chan_in[z][y][x][SOUTH] = (y < CLUSTER_NY-1) ?
+                    router_chan_out[z][y+1][x][NORTH] : is_grounded;
+`else // PITON_EXTRA_MEMS
+                // Only for Chiplet 0 (Interposer)
+                if (CLUSTER_ID == 0) begin
+                    // Compared to the code below, this connects the outputs
+                    // (coming in) of the endpoints on the edges of the mesh,
+                    // to the router's incoming traffic
+                    assign router_chan_in[z][y][x][EAST] = (x < CLUSTER_NX-1) ?
+                        router_chan_out[z][y][x+1][WEST] :
+                        endpoint_chan_in[CLUSTER_NX*CLUSTER_NY+CLUSTER_NX*2+CLUSTER_NY+y];
+                    assign router_chan_in[z][y][x][NORTH] = (y > 0) ?
+                        router_chan_out[z][y-1][x][SOUTH] :
+                        endpoint_chan_in[CLUSTER_NX*CLUSTER_NY+x];
+                    assign router_chan_in[z][y][x][WEST] =  (x > 0) ?
+                        router_chan_out[z][y][x-1][EAST] :
+                        endpoint_chan_in[CLUSTER_NX*CLUSTER_NY+CLUSTER_NX*2+y];
+                    assign router_chan_in[z][y][x][SOUTH] = (y < CLUSTER_NY-1) ?
+                        router_chan_out[z][y+1][x][NORTH] :
+                        endpoint_chan_in[CLUSTER_NX*CLUSTER_NY+CLUSTER_NX+x];
+                // Other chiplets
+                end else begin
+                    assign router_chan_in[z][y][x][EAST] = (x < CLUSTER_NX-1) ?
+                        router_chan_out[z][y][x+1][WEST] : is_grounded;
+                    assign router_chan_in[z][y][x][NORTH] = (y > 0) ?
+                        router_chan_out[z][y-1][x][SOUTH] : is_grounded;
+                    assign router_chan_in[z][y][x][WEST] =  (x > 0) ?
+                        router_chan_out[z][y][x-1][EAST] : is_grounded;
+                    assign router_chan_in[z][y][x][SOUTH] = (y < CLUSTER_NY-1) ?
+                        router_chan_out[z][y+1][x][NORTH] : is_grounded;
+                end
+`endif // PITON_EXTRA_MEMS
+                assign router_chan_in[z][y][x][UP] = (z < CLUSTER_NZ-1) ?
+                        router_chan_out[z+1][y][x][DOWN] : inter_cluster_chan_in[V_UP_ID];
+                assign router_chan_in[z][y][x][DOWN] = (z > 0) ?
+                        router_chan_out[z-1][y][x][UP] : inter_cluster_chan_in[V_DOWN_ID];
+                //endpoint connections
+                assign router_chan_in[z][y][x][LOCAL] =   endpoint_chan_in[EID];
+                assign endpoint_chan_out[EID] = router_chan_out[z][y][x][LOCAL];
+                //inter_cluster connections
+                if (z==0) begin
+                    assign inter_cluster_chan_out[V_UP_ID] = router_chan_out[z][y][x][UP];
+                end
+                if (z==CLUSTER_NZ-1) begin
+                    assign inter_cluster_chan_out[V_DOWN_ID] = router_chan_out[z][y][x][DOWN];
+                end
+            end //X
+        end //Y
+    end //Z
+    endgenerate
+`ifndef PITON_EXTRA_MEMS
+    `ifdef PITON_PRONOC
+    generate
+        if (CLUSTER_ID == 0) begin
+            // Tile 0-0 W <-> Chipset connections
+            assign router_chan_in[0][0][0][WEST] =
+                endpoint_chan_in[CLUSTER_NX*CLUSTER_NY*CLUSTER_NZ];
+            assign endpoint_chan_out[CLUSTER_NX*CLUSTER_NY*CLUSTER_NZ] =
+                router_chan_out[0][0][0][WEST];
+        end
+    endgenerate
+    `endif // PITON_PRONOC
+`else // PITON_EXTRA_MEMS
+    genvar ex, ey;
+    generate
+        if (CLUSTER_ID == 0) begin
+            // Connect the routers output connections on the edges of the mesh
+            // (north and south) to the corresponding endpoints (MCs)
+            for (ex = 0; ex < CLUSTER_NX; ex = ex + 1) begin: EX_
+                assign endpoint_chan_out[CLUSTER_NX*CLUSTER_NY+ex] =
+                    router_chan_out[0][0][ex][NORTH];
+                assign endpoint_chan_out[CLUSTER_NX*CLUSTER_NY+CLUSTER_NX+ex] =
+                    router_chan_out[0][CLUSTER_NY-1][ex][SOUTH];
+            end
+
+            // Connect the routers output connections on the edges of the mesh
+            // (west and east) to the corresponding endpoints (MCs)
+            for (ey = 0; ey < CLUSTER_NY; ey = ey + 1) begin: EY_
+                // NOTE: Chipset is now connected to endpoint
+                // CLUSTER_NX * CLUSTER_NY + CLUSTER_NX * 2
+                // NOTE: Must be kept in sync with CHIP_SET_ID in chip.sv.pyv
+                assign endpoint_chan_out[CLUSTER_NX*CLUSTER_NY+CLUSTER_NX*2+ey] =
+                    router_chan_out[0][ey][0][WEST];
+                assign endpoint_chan_out[CLUSTER_NX*CLUSTER_NY+CLUSTER_NX*2+CLUSTER_NY+ey] =
+                    router_chan_out[0][ey][CLUSTER_NX-1][EAST];
+            end
+        end
+    endgenerate
+`endif // PITON_EXTRA_MEMS
+endmodule
+
+
+module mesh_cluster_route_xyz
+    import pronoc_pkg::*;
+(
+    input  multimesh_router_addr_t current_router_addr_i,
+    input  multimesh_router_addr_t destination_router_addr_i,
+    output logic [DSTPw-1:0] router_port_out
+);
+
+    // State type
+    typedef enum logic [2:0] {
+        MASS  = 3'b001,
+        LESS  = 3'b010,
+        EQUAL = 3'b100
+    } state_t;
+
+    state_t Dx, Dy, Dz;
+    assign Dx = (destination_router_addr_i.x >  current_router_addr_i.x) ? MASS  :
+                (destination_router_addr_i.x == current_router_addr_i.x) ? EQUAL :
+                LESS;
+    assign Dy = (destination_router_addr_i.y >  current_router_addr_i.y) ? MASS  :
+                (destination_router_addr_i.y == current_router_addr_i.y) ? EQUAL :
+                LESS;
+    assign Dz = (destination_router_addr_i.z >  current_router_addr_i.z) ? MASS  :
+                (destination_router_addr_i.z == current_router_addr_i.z) ? EQUAL :
+                LESS;
+
+    always_comb begin
+        router_port_out = 0;
+        if      (Dx == MASS) router_port_out = EAST;
+        else if (Dx == LESS) router_port_out = WEST;
+        else if (Dy == MASS) router_port_out = SOUTH;
+        else if (Dy == LESS) router_port_out = NORTH;
+        else if (Dz == MASS) router_port_out = UP;
+        else if (Dz == LESS) router_port_out = DOWN;
+        else                 router_port_out = LOCAL;
+    end
+endmodule
+
+
+module multi_mesh_ovc_sel
+    import pronoc_pkg::*;
+#(
+    // Input port number. Zero is LOCAL
+    parameter SW_LOC = 0
+)(
+    input  multimesh_router_addr_t current_router_addr_i,
+    input  multimesh_router_addr_t global_dst_i,
+    input  logic up_dir_sel_i,
+    input  logic [DSTPw-1:0] destport_out_i,
+    input  logic [V-1:0] vc_num_i,
+    output logic [V-1:0] ovc_sel_o
+);
+
+    logic [V-1:0] pre_ovc_sel;
+
+    typedef enum logic [1:0] {
+        VDIR_UP    = 2'b01,
+        VDIR_DOWN  = 2'b10,
+        VDIR_EQUAL = 2'b00
+    } vdir_t;
+
+    vdir_t vdir;
+    assign vdir =
+        (global_dst_i.c == current_router_addr_i.c) ? VDIR_EQUAL :
+        (up_dir_sel_i) ? VDIR_UP : VDIR_DOWN;
+
+    logic  dest_reached;
+    assign dest_reached = global_dst_i.c == current_router_addr_i.c &&
+                          global_dst_i.x == current_router_addr_i.x &&
+                          global_dst_i.y == current_router_addr_i.y &&
+                          global_dst_i.z == current_router_addr_i.z;
+
+    always_comb begin
+        // NOTE: The memory controllers on the interposer will inject packets
+        // in the NoC using the N/S/W/E ports of the routers (localized on the
+        // edges of the 2D-mesh). The packets are injected by default on Z-
+        // and stay on this VC until taking an ascending VL or arriving to
+        // destination. Conversely, the packets emitted on the (Z-) local port
+        // on the interposer, will switch and stay on Z+.
+
+        // Packets injected on local port
+        if (SW_LOC == LOCAL) begin
+            pre_ovc_sel = (vdir == VDIR_UP)   ? Z_PLUS_VC :
+                          (vdir == VDIR_DOWN) ? Z_MIN_VC  :
+                          Z_PLUS_VC;
+        end
+        // Z- to Z+ transition when going up
+        else if (destport_out_i == UP && vc_num_i == Z_MIN_VC) begin
+            pre_ovc_sel = Z_PLUS_VC;
+        end
+        else begin
+            // Stay on the same VC
+            pre_ovc_sel = vc_num_i;
+        end
+    end
+
+    // If arrived, forward the packet to the local port (Z+)
+    assign ovc_sel_o = (dest_reached) ? Z_PLUS_VC : pre_ovc_sel;
+endmodule
+
+
+module multi_mesh_ovc_list_per_ivc
+    import pronoc_pkg::*;
+#(
+    parameter IVC_NUM = 0, // Input port VC number
+    parameter P = 7 // Router IO number
+)(
+    input  logic [Cw-1:0] class_in,
+    input  logic [P-1:0]  destport_one_hot,
+    input  ctrl_chanel_t  ctrl_in[P-1:0],
+    input  logic [V-1:0]  ovc_sel,
+    output logic [V-1:0]  ovcs_out
+);
+    localparam Pw = $clog2(P);
+    localparam [V-1:0] ALL_VCS = {V{1'b1}};
+
+    logic [V-1:0] candidate_ovcs_message_class;
+    logic [V-1:0] ovc_out_general;
+    logic [V-1:0] ovc_presence;
+    logic [V-1:0] ovc_list;
+    logic [V-1:0] ovc_list_reverse;
+
+    // Destination port decimal
+    logic [Pw-1:0] destp;
+
+    ovc_list ovcList(
+        .class_in(class_in),
+        .ovcs_out(candidate_ovcs_message_class)
+    );
+
+    always_comb begin
+        destp = '0;
+        for (int i = 0; i < P; i++) begin
+            if (destport_one_hot[i])
+                destp = i[Pw-1:0];
+        end
+    end
+
+    assign ovc_out_general = ovc_sel;
+    assign ovc_presence = (HETERO_VC > 0) ? ctrl_in[destp].hetero_ovc_presence : ALL_VCS;
+    assign ovc_list = ovc_out_general & candidate_ovcs_message_class & ovc_presence;
+    assign ovc_list_reverse = ~ovc_out_general & candidate_ovcs_message_class & ovc_presence;
+    // If the listed VCs are not present in the connected router port, we swap
+    // the listed VCs (for example, if the connected port has only one VC (Z-),
+    // and ovc_out_general is Z+).
+    assign ovcs_out = (ovc_list == {V{1'b0}}) ? ovc_list_reverse : ovc_list;
+endmodule
+
+
+module icr_modifier
+    import pronoc_pkg::*;
+#(
+    parameter logic ICR_EN = 1
+`ifndef DYNAMIC_CLUSTER_INIT
+    , parameter CLUSTER_ID = 0,
+    parameter CLUSTER_RID = 0
+`endif
+)(
+`ifdef DYNAMIC_CLUSTER_INIT
+    input  cluster_hid_entry_t     address_table[DYN_ICRT_MAX_ENTRY],
+    input  multimesh_router_addr_t local_cluster_endp_addr_down_dir,
+    input  logic [CLUSTER_IDw-1:0] current_cluster_id,
+`endif
+    input  smartflit_chanel_t      chan_in,
+    input  multimesh_router_addr_t current_r_addr,
+    output smartflit_chanel_t      chan_out
+);
+
+    hdr_flit_t hdr_flit_i;
+    // Global / Local / ICRT Destination fields
+    multimesh_router_addr_t global_dst, local_dst, local_dst_icr;
+    // Local destination port, computed to reach the local destination
+    logic [DSTPw-1:0] ldestport_o;
+    // Final destination port, accounts for ascending / descending vertically
+    // and FBITS
+    logic [DSTPw-1:0] fdestport_o;
+    // Take the FBITS into account (encoded with ProNoC's port)
+    logic [DSTPw-1:0] fbits_encoded;
+    // Depth-First Multi-mesh routing fields
+    logic local_routing_en;
+    logic next_chip_vdir;
+    logic curr_next_chip_vdir;
+    logic up_dir_sel;
+
+    header_flit_info #(
+        .DATA_w(0)
+    ) extractor(
+        .flit(chan_in.flit_chanel.flit),
+        .hdr_flit(hdr_flit_i),
+        .data_o(/* unused */)
+    );
+
+    // Unpacket all the fields from the destination address
+    assign {local_routing_en,
+            curr_next_chip_vdir,
+            fbits_encoded,
+            local_dst,
+            global_dst} = hdr_flit_i.dest_e_addr[DAw-1:0];
+
+    // Next vertical direction is either the one from the Inter-Chiplet Routing
+    // Table, or the previously computed one (local routing)
+    assign next_chip_vdir = (ICR_EN && !local_routing_en) ?
+                            up_dir_sel : curr_next_chip_vdir;
+
+`ifdef MULTI_MESH_ASSERTIONS
+    // synthesis translate_off
+    assert property (@(posedge chan_in.flit_chanel.flit.hdr_flag)
+            local_routing_en == 1'b0 |-> ICR_EN == 1)
+        else
+            $fatal("A flit was freshly injected in the NoC on a non-ICR port");
+    // synthesis translate_on
+`endif // MULTI_MESH_ASSERTIONS
+
+    generate
+    if (ICR_EN) begin
+        global_id_to_local_cluster_endp #(
+`ifndef DYNAMIC_CLUSTER_INIT
+            .CLUSTER_ID(CLUSTER_ID),
+            .RID(CLUSTER_RID)
+`endif
+        ) global_to_local(
+`ifdef DYNAMIC_CLUSTER_INIT
+            .address_table(address_table),
+            .local_cluster_endp_addr_down_dir(local_cluster_endp_addr_down_dir),
+            .current_cluster_id(current_cluster_id),
+`endif
+            .dest_address(global_dst),
+            .local_cluster_endp_addr(local_dst_icr),
+            .up_dir_sel(up_dir_sel)
+        );
+
+        // Local routing decision
+        mesh_cluster_route_xyz dor(
+            .current_router_addr_i(current_r_addr),
+            .destination_router_addr_i((local_routing_en) ?
+                                       local_dst : local_dst_icr),
+            .router_port_out(ldestport_o)
+        );
+    end else begin
+        // Retrieve previously computed local destination
+        assign local_dst_icr = local_dst;
+
+        // Local routing decision
+        mesh_cluster_route_xyz dor(
+            .current_router_addr_i(current_r_addr),
+            .destination_router_addr_i(local_dst_icr),
+            .router_port_out(ldestport_o)
+        );
+    end
+    endgenerate
+
+    always_comb begin
+        chan_out = chan_in;
+        // Base value for the final destination port
+        fdestport_o = '0;
+        // Header flit
+        if (chan_in.flit_chanel.flit.hdr_flag == 1'b1) begin
+            // Override the endpoint destination address of the header
+            // with the new local routing data
+            if (ICR_EN && !local_routing_en)
+                chan_out.flit_chanel.flit[E_DST_MSB:E_DST_LSB] = {
+                    1'b1, // enable local routing
+                    next_chip_vdir,
+                    fbits_encoded,
+                    local_dst_icr,
+                    global_dst
+                };
+
+            // By default, the next hop is the computed DOR decision
+            fdestport_o = ldestport_o;
+
+            // If arrived to a boundary router which is not the global
+            // destination, route vertically
+            if (ldestport_o == LOCAL && local_dst_icr.c != global_dst.c) begin
+                fdestport_o = (next_chip_vdir) ? UP : DOWN;
+                // Set to 0 the local_routing field
+                chan_out.flit_chanel.flit[E_DST_MSB:E_DST_MSB] = 1'b0;
+            end
+
+            // When arrived to destination, route to the FBITS if present,
+            // otherwise route to the local port
+            chan_out.flit_chanel.flit[DST_P_MSB:DST_P_LSB] =
+                (fdestport_o == LOCAL && fbits_encoded != LOCAL) ?
+                    fbits_encoded : fdestport_o;
+        end
+    end
+endmodule
+
+
+module depth_first_router
+    import pronoc_pkg::*;
+#(
+    parameter logic LOCAL_ICR_EN = 1,
+    parameter logic UP_ICR_EN    = 1,
+    parameter logic DOWN_ICR_EN  = 1,
+    parameter logic NORTH_ICR_EN = 1,
+    parameter logic SOUTH_ICR_EN = 1,
+    parameter logic WEST_ICR_EN  = 1,
+    parameter logic EAST_ICR_EN  = 1,
+
+    parameter ROUTER_ID = 0,
+`ifndef DYNAMIC_CLUSTER_INIT
+    parameter CLUSTER_ID  = 0,
+    parameter CLUSTER_RID = 0,
+`endif
+    parameter P = 7
+)(
+    input  logic clk,
+    input  logic reset,
+`ifdef DYNAMIC_CLUSTER_INIT
+    input  program_port_t program_port,
+`endif
+    input  router_config_t router_config_in,
+    input  smartflit_chanel_t chan_in [P-1:0],
+    output smartflit_chanel_t chan_out[P-1:0],
+    output router_event_t router_event[P-1:0]
+);
+
+    localparam [P-1:0] ICR_PORT_EN =
+        (LOCAL_ICR_EN << LOCAL) +
+        (UP_ICR_EN    << UP)    +
+        (DOWN_ICR_EN  << DOWN)  +
+        (SOUTH_ICR_EN << SOUTH) +
+        (NORTH_ICR_EN << NORTH) +
+        (WEST_ICR_EN  << WEST)  +
+        (EAST_ICR_EN  << EAST);
+
+    smartflit_chanel_t chan_in_wire[P-1:0];
+
+    // Instanciate the regular ProNoC router
+    router_top #(
+        .ROUTER_ID(ROUTER_ID),
+        .P(P)
+    ) the_router (
+        .router_config_in(router_config_in),
+        .chan_in(chan_in_wire),
+        .chan_out(chan_out),
+        .router_event(router_event),
+        .clk(clk),
+        .reset(reset)
+    );
+
+`ifdef DYNAMIC_CLUSTER_INIT
+    cluster_hid_entry_t address_table[DYN_ICRT_MAX_ENTRY];
+    multimesh_router_addr_t local_cluster_endp_addr_down_dir;
+    logic [CLUSTER_IDw-1:0] current_cluster_id;
+
+    dynamic_hids_per_router dynamic_hids(
+        .local_cluster_endp_addr_down_dir(local_cluster_endp_addr_down_dir),
+        .address_table(address_table),
+        .current_cluster_id(current_cluster_id),
+        .program_port(program_port),
+        .reset(reset),
+        .clk(clk)
+    );
+`endif
+
+    genvar i;
+    generate
+    for(i = 0; i < P; i++) begin : P_
+        icr_modifier #(
+`ifndef DYNAMIC_CLUSTER_INIT
+            .CLUSTER_ID(CLUSTER_ID),
+            .CLUSTER_RID(CLUSTER_RID),
+`endif
+            .ICR_EN(ICR_PORT_EN[i])
+        ) icr(
+`ifdef DYNAMIC_CLUSTER_INIT
+            .address_table(address_table),
+            .local_cluster_endp_addr_down_dir(local_cluster_endp_addr_down_dir),
+            .current_cluster_id(current_cluster_id),
+`endif
+            .current_r_addr(router_config_in.router_addr),
+            .chan_in(chan_in[i]),
+            .chan_out(chan_in_wire[i])
+        );
+    end//P
+    endgenerate
+endmodule
diff --git a/mpsoc/rtl/src_multi_mesh/multi_mesh.flist b/mpsoc/rtl/src_multi_mesh/multi_mesh.flist
new file mode 100644
index 0000000..629903a
--- /dev/null
+++ b/mpsoc/rtl/src_multi_mesh/multi_mesh.flist
@@ -0,0 +1,5 @@
++incdir+./build
+./mesh_cluster.sv
+./build/multi_mesh_icr.sv
+./build/multi_mesh_routing.sv
+./build/multi_mesh.sv
diff --git a/mpsoc/rtl/src_multi_mesh/piton_wrapper.sv b/mpsoc/rtl/src_multi_mesh/piton_wrapper.sv
new file mode 100644
index 0000000..6a3b98f
--- /dev/null
+++ b/mpsoc/rtl/src_multi_mesh/piton_wrapper.sv
@@ -0,0 +1,627 @@
+/**************************************************************
+ * File        : piton_wrapper.sv
+ * Description : Contains the necessary modules for adapting
+ *               Depth-First ProNoC with OpenPiton's Endpoints
+ *
+ * Authors     :  Davy Million, Alireza Monemi
+ * Date        :  2025
+ **************************************************************/
+`include "define.tmp.h"
+`include "jtag.vh"
+`include "pronoc_def.v"
+
+
+// The following modules allows the conversion of an OpenPiton Flit into a
+// ProNoC Depth-First Flit, and the other way around.
+//
+// (A) Valid Flit, Additionnal Flags and Backpressure
+// The OpenPiton valid flit signal is plugged directly into the ProNoC flit
+// write signal.
+//
+// To keep track of the number of flits in a packet, OpenPiton has a dedicated
+// LENGTH attributes in the header flit. This is not the case of ProNoC, which
+// rely on explicit signals, which are asserted for the head and tail flits.
+// The module piton_tail_hdr_detect (shared with the FMesh OpenPiton wrapper)
+// is used to convert these two ways of managing the number of flits.
+//
+// As Depth-First relies on two VCs, and OpenPiton's endpoints only support a
+// single source of credits, we modified the routing algorithm to only use VC0
+// (Z-) for packet injection, and the other one (Z+) for packet reception,
+// leveraging the fact that the algorithm supports passing from Z- to Z+ (but
+// not the other way around). Switching between these two VCs is necessary to
+// support all "Multi-Mesh" routing paths, because some X-Y/Z turns are
+// disabled for both VC to garantee deadlock-freeness. Hence, the OpenPiton
+// backpressure signal (yummy) is connected directly to the Z- ProNoC credit
+// signal.
+//
+// (B) Data Payload
+// The conversion is almost straightforward: the ProNoC data payload is the
+// same as the OpenPiton data payload, except when the OpenPiton flit present
+// the 1st 64-bit Header word (which is the case for any 1st Header Flit of an
+// OpenPiton packet).
+//
+// For this corner case, the conversion consists of the following:
+//  OpenPiton
+// Fpay-1  ...  64-bit                      30-bit                           0
+//   |____________|___________________________|______________________________|
+//   |            |                           |                              |
+//   |    ...     | CHIPID, XPOS, YPOS, FBITS | LENGTH, TYPE, MSHR, OPTIONS1 |
+//   |____________|___________________________|______________________________|
+//   |            |                           |<-------PRESERVED_DATw------->|
+//   | Word 2...n |            (OpenPiton Header Flit Word 1)                |
+//   |_____  _____|_________________________________________  _______________|
+//         ||                                               ||
+//         ||                      _________________________||
+//         ||  MSB_BE + 1 +       ||
+// FPAYw-1 ||  PRESERVED_DATw     ||   pronoc_pkg::MSB_BE+1                  0
+//   |_____VV_____|_______________VV_____________|___________________________|
+//   |            |                              | Depth-First ProNoC Header |
+//   |    ...     | LENGTH, TYPE, MSHR, OPTIONS1 |    DST Addr | SRC Addr    |
+//   |____________|______________________________|___________________________|
+//   |<-----------|------DATA_w----------------->|                           |
+//   |                   ProNoC Header Flit Payload                          |
+//   |_______________________________________________________________________|
+//   ProNoC
+//
+// Where:
+// (*) Fpay, the size of the OpenPiton data flit
+// --> Fpay NoC1: {64, 128, 256, 512}
+// --> Fpay NoC2/3: {64, 128, 256, 512, 576, 704}
+//
+// (*) FPAYw, the size of the ProNoC data payload
+//
+// The size of FPAYw depends on the size of the Depth-First (DP) DST/SRC
+// address fields. These fields are computed based on the original CHIPID,
+// XPOS, YPOS and FBITS values. The width of the DP DST/SRC addresses can vary
+// and depend primarily on the values of the CLUSTER_IDw, CLUSTER_Xw and
+// CLUSTER_Yw parameters, which themselves depends on the max X/Y dimensions
+// among all chips and the number of chips in the system.
+// FPAYw will be larger than Fpay if:
+// ==> size(DP DST Addr) + size(DP SRC Addr) > size(CHIPID, XPOS, YPOS, FBITS)
+// which is likely the case for a large system.
+//
+// (C) Control Channels
+// ProNoC has dedicated control channels to support different buffer depths
+// (credit_init_val) and number of VCs between routers (hetero_ovc_presence).
+// The credit_init_val signal is initialized with the same value as the buffer
+// size in the OpenPiton endpoints. The hetero_ovc_presence is used to check if
+// the Z+ VC exists on the interposer chip, and use Z- as a fallback VC for
+// packet reception otherwise.
+
+
+module piton_to_pronoc_multimesh_endp_src_addr_converter
+    import pronoc_pkg::*;
+(
+    input  logic [`NOC_CHIPID_WIDTH-1:0] piton_chipid_i,
+    input  logic [`NOC_X_WIDTH-1:0]      piton_coreid_x_i,
+    input  logic [`NOC_Y_WIDTH-1:0]      piton_coreid_y_i,
+    output logic [EAw-1:0]               pronoc_endp_src_addr_o
+);
+    // Encode endpoint source address
+    assign pronoc_endp_src_addr_o = {
+        piton_chipid_i[CLUSTER_IDw-1:0],
+        {CLUSTER_Zw{1'b0}},
+        piton_coreid_y_i[CLUSTER_Yw-1:0],
+        piton_coreid_x_i[CLUSTER_Xw-1:0]
+    };
+endmodule
+
+
+module piton_to_pronoc_multimesh_endp_dst_addr_converter
+    import pronoc_pkg::*;
+(
+    input  logic [`NOC_CHIPID_WIDTH-1:0]    piton_chipid_i,
+    input  logic [`NOC_X_WIDTH-1:0]         piton_coreid_x_i,
+    input  logic [`NOC_Y_WIDTH-1:0]         piton_coreid_y_i,
+    input  logic [`MSG_DST_FBITS_WIDTH-1:0] piton_fbits_i,
+    output logic [DAw-1:0]                  pronoc_endp_dst_addr_o
+);
+    // Destination FBITS
+    logic [DSTPw-1:0] pronoc_dest_fbits;
+    // Global destination address
+    logic [RAw-1:0] global_dst_i;
+
+    assign pronoc_dest_fbits =
+        (piton_fbits_i == `NOC_FBITS_NORTH) ? NORTH :
+        (piton_fbits_i == `NOC_FBITS_WEST ) ? WEST  :
+        (piton_fbits_i == `NOC_FBITS_SOUTH) ? SOUTH :
+        (piton_fbits_i == `NOC_FBITS_EAST ) ? EAST  : LOCAL;
+
+    assign global_dst_i = {piton_chipid_i[CLUSTER_IDw-1:0],
+                           {CLUSTER_Zw{1'b0}},
+                           piton_coreid_y_i[CLUSTER_Yw-1:0],
+                           piton_coreid_x_i[CLUSTER_Xw-1:0]};
+
+    // Endpoint destination address encoding
+    assign pronoc_endp_dst_addr_o = {
+        1'b0, // local_routing_en
+        1'b0, // next_chip_vdir
+        pronoc_dest_fbits,
+        {RAw{1'b0}}, // local_dst
+        global_dst_i
+    };
+endmodule
+
+
+module pronoc_to_piton_multimesh_endp_addr_converter
+    import pronoc_pkg::*;
+(
+    input  logic [DAw-1:0] piton_endp_dst_addr_i,
+    output logic [`NOC_CHIPID_WIDTH-1:0] piton_chipid_o,
+    output logic [`NOC_X_WIDTH-1:0] piton_coreid_x_o,
+    output logic [`NOC_Y_WIDTH-1:0] piton_coreid_y_o,
+    output logic [`MSG_DST_FBITS_WIDTH-1:0] piton_fbits_o
+);
+    // Starting Position of the CLUSTER_ID field
+    localparam CLUSTER_ID_IDX = CLUSTER_Xw + CLUSTER_Yw + CLUSTER_Zw;
+
+    // Destination FBITS encoded as a ProNoC port
+    logic [DSTPw-1:0] piton_dest_fbits_enc;
+
+    always_comb begin
+        piton_coreid_x_o = {`MSG_DST_X_WIDTH{1'b0}};
+        piton_coreid_y_o = {`MSG_DST_Y_WIDTH{1'b0}};
+        piton_chipid_o   = {`NOC_CHIPID_WIDTH{1'b0}};
+        piton_dest_fbits_enc = {DSTPw{1'b0}};
+
+        // Extract x/y from the global destination
+        {piton_coreid_y_o[CLUSTER_Yw-1:0],
+         piton_coreid_x_o[CLUSTER_Xw-1:0]} =
+         piton_endp_dst_addr_i[CLUSTER_Yw + CLUSTER_Xw-1:0];
+
+        piton_chipid_o = piton_endp_dst_addr_i[CLUSTER_ID_IDX +: CLUSTER_IDw];
+        piton_dest_fbits_enc = piton_endp_dst_addr_i[2*RAw +: DSTPw];
+    end
+
+    // Decode FBITS into OpenPiton format
+    assign piton_fbits_o =
+        (piton_dest_fbits_enc == EAST ) ? `NOC_FBITS_EAST  :
+        (piton_dest_fbits_enc == NORTH) ? `NOC_FBITS_NORTH :
+        (piton_dest_fbits_enc == WEST ) ? `NOC_FBITS_WEST  :
+        (piton_dest_fbits_enc == SOUTH) ? `NOC_FBITS_SOUTH :
+        `NOC_FBITS_PROCESSOR;
+endmodule
+
+
+module piton_to_pronoc_multimesh_wrapper
+    import pronoc_pkg::*;
+#(
+    parameter TILE_NUM = 0,
+    parameter FLATID_WIDTH = 8,
+    parameter Z_MINUS_VC_INJECTION = 1,
+    parameter CONNECTED_TO_ENDP = 1
+)(
+    input  logic clk,
+    input  logic reset,
+    // OpenPiton
+    input  logic [`NOC_CHIPID_WIDTH-1:0] default_chipid,
+    input  logic [`NOC_X_WIDTH-1:0] default_coreid_x,
+    input  logic [`NOC_Y_WIDTH-1:0] default_coreid_y,
+    input  logic [FLATID_WIDTH-1:0] flat_tileid,
+    input  logic [Fpay-1:0] dataIn,
+    input  logic validIn,
+    input  logic yummyIn,
+    // ProNoC
+    input  logic [RAw-1:0] current_r_addr_i,
+    input  logic [V-1:0] ovc_presence_i,
+    output smartflit_chanel_t chan_out
+);
+    // Size of the OpenPiton header fields remaining in the ProNoC header
+    localparam PRESERVED_DATw = (`MSG_LENGTH_WIDTH + `MSG_TYPE_WIDTH +
+                                 `MSG_MSHRID_WIDTH + `MSG_OPTIONS_1_WIDTH);
+
+    // NOTE: the OpenPiton NoC protocol contains some packet fields that are
+    // not necessary for routing with ProNoC because they are either related to
+    // the decoding of the packet, or to give necessary information to the
+    // destination endpoint, so the destination can create a response. Also,
+    // when the Piton NoC > 64-bit, the endpoint packs multiple 64-bit words
+    // together in a single flit. If the message is a cache coherence request,
+    // the header flit will contain the targeted address (and also details
+    // about the source endpoint if Piton NoC > 128-bit), see Flit (2, 3) of
+    // Table 1 in OpenPiton Microarchitecture Specification.
+    // All these "non-necessary for routing" fields will be placed in the
+    // ProNoC packet header, as additional payload data, so they can be
+    // retrieved once the packet is arrived to the destination endpoint.
+    // DATA_w is the size of the additionnal payload data.
+    localparam DATA_w = Fpay - 64 + PRESERVED_DATw;
+
+    logic [`MSG_DST_CHIPID_WIDTH-1:0] piton_dest_chipid;
+    logic [`MSG_DST_X_WIDTH-1:0]      piton_dest_x;
+    logic [`MSG_DST_Y_WIDTH-1:0]      piton_dest_y;
+    logic [`MSG_DST_FBITS_WIDTH-1:0]  piton_dest_fbits;
+    logic [`MSG_LENGTH_WIDTH-1:0]     piton_length;
+    logic [`MSG_TYPE_WIDTH-1:0]       piton_msg_type;
+    logic [`MSG_MSHRID_WIDTH-1:0]     piton_mshrid;
+    logic [`MSG_OPTIONS_1_WIDTH-1:0]  piton_option1;
+
+    logic [EAw-1:0] pronoc_src_endp_addr;
+    logic [DAw-1:0] pronoc_dest_endp_addr;
+    logic [DATA_w-1:0] pronoc_hdr_data;
+
+    logic piton_is_tail;
+    logic piton_is_head;
+
+    logic [Fw-1:0] pronoc_hdr_flit;
+    logic [WEIGHTw-1:0] pronoc_win;
+    logic [V-1:0] pronoc_vc_num_in;
+
+    piton_tail_hdr_detect #(
+        .FLIT_WIDTH(Fpay)
+    ) piton_hdr(
+        .clk(clk),
+        .reset(reset),
+        .length_in(dataIn[`MSG_LENGTH]),
+        .valid(validIn),
+        .ready(1'b1),
+        .is_tail(piton_is_tail),
+        .is_header(piton_is_head)
+    );
+
+    piton_to_pronoc_multimesh_endp_src_addr_converter src_conv(
+        .piton_chipid_i(default_chipid),
+        .piton_coreid_x_i(default_coreid_x),
+        .piton_coreid_y_i(default_coreid_y),
+        .pronoc_endp_src_addr_o(pronoc_src_endp_addr)
+    );
+
+    assign piton_dest_chipid = dataIn[`MSG_DST_CHIPID];
+    assign piton_dest_x      = dataIn[`MSG_DST_X];
+    assign piton_dest_y      = dataIn[`MSG_DST_Y];
+    assign piton_dest_fbits  = dataIn[`MSG_DST_FBITS];
+    assign piton_length      = dataIn[`MSG_LENGTH];
+    assign piton_msg_type    = dataIn[`MSG_TYPE];
+    assign piton_mshrid      = dataIn[`MSG_MSHRID];
+    assign piton_option1     = dataIn[`MSG_OPTIONS_1];
+
+    piton_to_pronoc_multimesh_endp_dst_addr_converter dst_conv(
+        .piton_chipid_i(piton_dest_chipid),
+        .piton_coreid_x_i(piton_dest_x),
+        .piton_coreid_y_i(piton_dest_y),
+        .piton_fbits_i(piton_dest_fbits),
+        .pronoc_endp_dst_addr_o(pronoc_dest_endp_addr)
+    );
+
+    generate
+    if (Fpay == 64) begin: F64
+        assign pronoc_hdr_data = {piton_length, piton_msg_type, piton_mshrid,
+                                  piton_option1};
+    end else begin: FL
+        assign pronoc_hdr_data = {dataIn[Fpay-1:64], piton_length,
+                                  piton_msg_type, piton_mshrid, piton_option1};
+    end
+    endgenerate
+
+    always_comb begin
+        pronoc_win = {WEIGHTw{1'b0}};
+        pronoc_win[0] = 1'b1;
+    end
+
+    generate
+    if (Z_MINUS_VC_INJECTION) begin
+        // Injection of the packet on Z-
+        assign pronoc_vc_num_in = Z_MIN_VC;
+    end else begin
+        // Injection of the packet on Z+
+        // This is used to reconstruct a packet to cross a vertical link,
+        // between two NoC domains with different channel widths
+        assign pronoc_vc_num_in = Z_PLUS_VC;
+    end
+    endgenerate
+
+    header_flit_generator #(
+        .DATA_w(DATA_w)
+    ) pronoc_hdr_gen(
+        .flit_out(pronoc_hdr_flit),
+        .src_e_addr_in(pronoc_src_endp_addr),
+        .dest_e_addr_in(pronoc_dest_endp_addr),
+        // NOTE: we do not really care about the destport here as the router
+        // will override it anyway
+        .destport_in({DSTPw{1'b0}}),
+        .class_in(1'b0),
+        .weight_in(pronoc_win),
+        .vc_num_in(pronoc_vc_num_in),
+        .be_in(1'b0),
+        .data_in(pronoc_hdr_data)
+    );
+
+    // ProNoC Control Channels
+    assign chan_out.ctrl_chanel.endp_port = CONNECTED_TO_ENDP;
+    assign chan_out.ctrl_chanel.endp_addr =
+        (CONNECTED_TO_ENDP) ? pronoc_src_endp_addr : '0;
+    assign chan_out.ctrl_chanel.router_addr =
+        (CONNECTED_TO_ENDP) ? pronoc_src_endp_addr : current_r_addr_i;
+    // By default, our implementation of Depth-First uses Z+ to place a packet
+    // in the destination router's ports. If this VC is not available (on the
+    // interposer, Z- could be the only VC), use Z- in this case.
+    assign chan_out.ctrl_chanel.credit_init_val =
+        // Select Z+ if it exists, otherwise Z-
+        ovc_presence_i[Z_PLUS_VC_IDX] ?
+            Z_PLUS_VC[0] ? {{CRDTw{1'b0}}, pronoc_pkg::B} :
+                           {pronoc_pkg::B, {CRDTw{1'b0}}}
+            : Z_MIN_VC[0] ? {{CRDTw{1'b0}}, pronoc_pkg::B} :
+                            {pronoc_pkg::B, {CRDTw{1'b0}}};
+    assign chan_out.ctrl_chanel.credit_release_en   = '0;
+    assign chan_out.ctrl_chanel.hetero_ovc_presence = ovc_presence_i;
+
+    // ProNoC Flit Channels
+    assign chan_out.flit_chanel.flit.hdr_flag  = piton_is_head;
+    assign chan_out.flit_chanel.flit.tail_flag = piton_is_tail;
+    assign chan_out.flit_chanel.flit.vc        = pronoc_vc_num_in;
+    assign chan_out.flit_chanel.flit_wr        = validIn;
+    // "Z+" credit, an endpoint consumed the flit (arrived to its destination)
+    assign chan_out.flit_chanel.credit = ovc_presence_i[Z_PLUS_VC_IDX] ?
+        Z_PLUS_VC & {yummyIn, yummyIn} : Z_MIN_VC & {yummyIn, yummyIn};
+    assign chan_out.flit_chanel.flit.payload = (piton_is_head) ?
+        pronoc_hdr_flit[FPAYw-1:0] : dataIn;
+    assign chan_out.smart_chanel = {SMART_CHANEL_w{1'b0}};
+    assign chan_out.flit_chanel.congestion = {CONGw{1'b0}};
+
+`ifndef ASIC_SYNTH
+`ifndef DISABLE_ALL_MONITORS
+`ifndef MINIMAL_MONITORING
+    // synthesis translate_off
+    always @ (posedge clk) begin
+        if (CONNECTED_TO_ENDP && validIn == 1'b1 && piton_is_head) begin
+            $display("%t Pi2Pr * Chip %d/Tile %d * NoC %d * payload length %d",
+                     $time, default_chipid, TILE_NUM, NOC_ID[1:0], piton_length);
+            $display("%t *** src (c=%d,x=%d,y=%d) sends to dst (c=%d,x=%d,y=%d chan_out=%x)",
+                     $time, default_chipid, default_coreid_x, default_coreid_y, piton_dest_chipid,
+                     piton_dest_x, piton_dest_y, chan_out);
+        end
+    end
+    // synthesis translate_on
+`endif // MINIMAL_MONITORING
+`endif // DISABLE_ALL_MONITORS
+`endif // ASIC_SYNTH
+endmodule
+
+
+module pronoc_to_piton_multimesh_wrapper
+    import pronoc_pkg::*;
+#(
+    parameter TILE_NUM = 0,
+    parameter FLATID_WIDTH = 8,
+    parameter CONNECTED_TO_ENDP = 1
+)(
+    input  logic clk,
+    input  logic reset,
+    // OpenPiton
+    input  logic [`NOC_CHIPID_WIDTH-1:0] default_chipid,
+    input  logic [`NOC_X_WIDTH-1:0] default_coreid_x,
+    input  logic [`NOC_Y_WIDTH-1:0] default_coreid_y,
+    input  logic [FLATID_WIDTH-1:0] flat_tileid,
+    output logic [Fpay-1:0] dataOut,
+    output logic validOut,
+    output logic yummyOut,
+    output logic [RAw-1:0] current_r_addr_o,
+    // ProNoC
+    input  smartflit_chanel_t chan_in,
+    output multimesh_router_addr_t received_packet_src_addr_o,
+    output logic [V-1:0] ovc_presence_o
+);
+    // Size of the OpenPiton header fields remaining in the ProNoC header
+    localparam
+        PRESERVED_DATw = (`MSG_LENGTH_WIDTH + `MSG_TYPE_WIDTH +
+                          `MSG_MSHRID_WIDTH + `MSG_OPTIONS_1_WIDTH);
+    // Size of the OpenPiton payload remaining in the ProNoC header flit
+    localparam DATA_w = Fpay - 64 + PRESERVED_DATw;
+
+    hdr_flit_t pronoc_hdr_flit;
+    logic pronoc_is_hdr;
+    logic [DATA_w-1:0] pronoc_hdr_data;
+
+    logic [Fpay-1:0] piton_hdr_flit;
+    // Source FBITS encoded as a ProNoC port
+    logic [DSTPw-1:0] piton_src_fbits_enc;
+
+    logic [`MSG_DST_CHIPID_WIDTH-1:0] piton_dest_chipid;
+    logic [`MSG_DST_X_WIDTH-1:0]      piton_dest_x;
+    logic [`MSG_DST_Y_WIDTH-1:0]      piton_dest_y;
+    logic [`MSG_DST_FBITS_WIDTH-1:0]  piton_dest_fbits;
+    logic [`MSG_LENGTH_WIDTH-1:0]     piton_length;
+    logic [`MSG_TYPE_WIDTH-1:0]       piton_msg_type;
+    logic [`MSG_MSHRID_WIDTH-1:0]     piton_mshrid;
+    logic [`MSG_OPTIONS_1_WIDTH-1:0]  piton_option1;
+
+    // Extract ProNoC header flit data
+    header_flit_info #(
+        .DATA_w(DATA_w)
+    ) extract(
+        .flit(chan_in.flit_chanel.flit),
+        .hdr_flit(pronoc_hdr_flit),
+        .data_o(pronoc_hdr_data)
+    );
+
+    pronoc_to_piton_multimesh_endp_addr_converter addr_conv(
+        .piton_endp_dst_addr_i(pronoc_hdr_flit.dest_e_addr),
+        .piton_chipid_o(piton_dest_chipid),
+        .piton_coreid_x_o(piton_dest_x),
+        .piton_coreid_y_o(piton_dest_y),
+        .piton_fbits_o(piton_dest_fbits)
+    );
+
+    assign {piton_length, piton_msg_type, piton_mshrid, piton_option1} =
+        pronoc_hdr_data[PRESERVED_DATw-1:0];
+
+    assign piton_hdr_flit[`MSG_DST_CHIPID] = piton_dest_chipid;
+    assign piton_hdr_flit[`MSG_DST_X]      = piton_dest_x;
+    assign piton_hdr_flit[`MSG_DST_Y]      = piton_dest_y;
+    assign piton_hdr_flit[`MSG_DST_FBITS]  = piton_dest_fbits;
+    assign piton_hdr_flit[`MSG_LENGTH ]    = piton_length;
+    assign piton_hdr_flit[`MSG_TYPE ]      = piton_msg_type;
+    assign piton_hdr_flit[`MSG_MSHRID ]    = piton_mshrid;
+    assign piton_hdr_flit[`MSG_OPTIONS_1]  = piton_option1;
+
+    generate
+    if (Fpay > 64) begin: R_
+        assign piton_hdr_flit[Fpay-1:64] =
+            pronoc_hdr_data[DATA_w-1:PRESERVED_DATw];
+    end
+    endgenerate
+
+    assign validOut = chan_in.flit_chanel.flit_wr;
+    // "Z-" credit, a flit was removed from the router's internal port
+    assign yummyOut = chan_in.flit_chanel.credit[Z_MIN_VC_IDX];
+    assign pronoc_is_hdr = chan_in.flit_chanel.flit.hdr_flag;
+    assign dataOut  = (pronoc_is_hdr)? piton_hdr_flit[Fpay-1:0] :
+                                       chan_in.flit_chanel.flit.payload;
+
+    // Signals used by the pronoc_to_piton endpointer encoder
+    assign current_r_addr_o = chan_in.ctrl_chanel.router_addr;
+    assign {piton_src_fbits_enc, received_packet_src_addr_o}
+        = pronoc_hdr_flit.src_e_addr;
+    assign ovc_presence_o = chan_in.ctrl_chanel.hetero_ovc_presence;
+
+`ifndef ASIC_SYNTH
+`ifndef DISABLE_ALL_MONITORS
+`ifndef MINIMAL_MONITORING
+    // synthesis translate_off
+    always @ (posedge clk) begin
+        if (CONNECTED_TO_ENDP && validOut==1'b1 && pronoc_is_hdr) begin
+            $display("%t Pr2Pi * Chip %d/Tile %d * NoC %d * payload length %d",
+                     $time, default_chipid, TILE_NUM, NOC_ID[1:0], piton_length);
+            $display("%t *** Received Packet Header (chan_out=%x) from src (c=%d,x=%d,y=%d)",
+                     $time, dataOut, received_packet_src_addr_o.c, received_packet_src_addr_o.x,
+                     received_packet_src_addr_o.y);
+        end
+    end
+    // synthesis translate_on
+`endif // MINIMAL_MONITORING
+`endif // DISABLE_ALL_MONITORS
+`endif // ASIC_SYNTH
+endmodule
+
+
+module pronoc_noc
+    import pronoc_pkg::*;
+#(
+    parameter CHIP_ID = 0,
+    // Inherited from the base wrapper.sv file, kept for consistency
+    parameter CHIP_SET_PORT = 3,
+    parameter FLATID_WIDTH  = `JTAG_FLATID_WIDTH,
+    parameter CLUSTER_NX = 1,
+    parameter CLUSTER_NY = 1,
+    parameter CLUSTER_NZ = 1,
+    parameter CLUSTER_ID_OFFSET = 0,
+`ifndef PITON_EXTRA_MEMS
+`ifdef PITON_PRONOC
+    localparam NE = (CHIP_ID == 0) ? CLUSTER_NX * CLUSTER_NY * CLUSTER_NZ + 1 :
+                     CLUSTER_NX * CLUSTER_NY * CLUSTER_NZ
+`else // PITON_PRONOC
+    localparam NE = CLUSTER_NX * CLUSTER_NY * CLUSTER_NZ
+`endif // PITON_PRONOC
+`else // PITON_EXTRA_MEMS
+    // For OpenPiton, the total number of available endpoints is one endpoint
+    // per tile + an endpoint on each edge of the 2D-Mesh to connect an MC and
+    // the chipset (only for the north-western one)
+    localparam NE = (CHIP_ID == 0) ? CLUSTER_NX * CLUSTER_NY * CLUSTER_NZ +
+                                     CLUSTER_NX * 2 + CLUSTER_NY * 2 :
+                     CLUSTER_NX * CLUSTER_NY * CLUSTER_NZ
+`endif // PITON_EXTRA_MEMS
+)(
+    input  logic clk,
+    input  logic reset,
+    input  logic [Fpay*NE-1:0] dataIn_flatten,
+    input  logic [NE-1:0] validIn,
+    input  logic [NE-1:0] yummyIn,
+    output logic [Fpay*NE-1:0] dataOut_flatten,
+    output logic [NE-1:0] validOut,
+    output logic [NE-1:0] yummyOut,
+    input  logic [`NOC_X_WIDTH*NE-1:0] default_coreid_x_flatten,
+    input  logic [`NOC_Y_WIDTH*NE-1:0] default_coreid_y_flatten,
+    input  logic [FLATID_WIDTH*NE-1:0] flat_tileid_flatten
+`ifdef PITON_MULTICHIP
+    ,
+    // NoC Vertical Links
+    input  smartflit_chanel_t pronoc_inter_chip_in [CLUSTER_NX*CLUSTER_NY*2-1:0],
+    output smartflit_chanel_t pronoc_inter_chip_out[CLUSTER_NX*CLUSTER_NY*2-1:0]
+`endif // PITON_MULTICHIP
+);
+
+    logic [Fpay-1:0] dataIn[NE-1:0];
+    logic [Fpay-1:0] dataOut[NE-1:0];
+    logic [`NOC_X_WIDTH-1:0] default_coreid_x[NE-1:0];
+    logic [`NOC_Y_WIDTH-1:0] default_coreid_y[NE-1:0];
+    logic [FLATID_WIDTH-1:0] flat_tileid[NE-1:0];
+
+    smartflit_chanel_t pronoc_chan_in [NE-1:0];
+    smartflit_chanel_t pronoc_chan_out[NE-1:0];
+    logic [RAw-1:0] current_r_addr[NE-1:0];
+    logic [V-1:0] ovc_presence[NE-1:0];
+
+    genvar i;
+    generate
+    for (i = 0; i < NE; i++) begin: E_
+        assign dataIn[i] = dataIn_flatten[(i+1)*Fpay-1:i*Fpay];
+        assign dataOut_flatten[(i+1)*Fpay-1:i*Fpay] = dataOut[i];
+        assign default_coreid_x[i] = default_coreid_x_flatten[(i+1)*`NOC_X_WIDTH-1:i*`NOC_X_WIDTH];
+        assign default_coreid_y[i] = default_coreid_y_flatten[(i+1)*`NOC_Y_WIDTH-1:i*`NOC_Y_WIDTH];
+        assign flat_tileid[i] = flat_tileid_flatten[(i+1)*FLATID_WIDTH-1:i*FLATID_WIDTH];
+
+        pronoc_to_piton_multimesh_wrapper
+        #(
+            .TILE_NUM(i),
+            .FLATID_WIDTH(FLATID_WIDTH),
+            .CONNECTED_TO_ENDP(1)
+        ) pr2pi(
+            .default_chipid(CHIP_ID[`NOC_CHIPID_WIDTH-1:0]),
+            .default_coreid_x(default_coreid_x[i]),
+            .default_coreid_y(default_coreid_y[i]),
+            .flat_tileid(flat_tileid[i]),
+            .reset(reset),
+            .clk(clk),
+            .dataOut(dataOut[i]),
+            .validOut(validOut[i]),
+            .yummyOut(yummyOut[i]),
+            .current_r_addr_o(current_r_addr[i]),
+            .chan_in(pronoc_chan_out[i]),
+            .received_packet_src_addr_o(/* unused */),
+            .ovc_presence_o(ovc_presence[i])
+        );
+
+        piton_to_pronoc_multimesh_wrapper
+        #(
+            .TILE_NUM(i),
+            .FLATID_WIDTH(FLATID_WIDTH),
+            .CONNECTED_TO_ENDP(1)
+        ) pi2pr(
+            .default_chipid(CHIP_ID[`NOC_CHIPID_WIDTH-1:0]),
+            .default_coreid_x(default_coreid_x[i]),
+            .default_coreid_y(default_coreid_y[i]),
+            .flat_tileid(flat_tileid[i]),
+            .reset(reset),
+            .clk(clk),
+            .dataIn(dataIn[i]),
+            .validIn(validIn[i]),
+            .yummyIn(yummyIn[i]),
+            .current_r_addr_i(current_r_addr[i]),
+            .chan_out(pronoc_chan_in[i]),
+            .ovc_presence_i(ovc_presence[i])
+        );
+    end
+    endgenerate
+
+    // Instanciate directly the mesh_cluster
+    mesh_cluster #(
+        .CLUSTER_ID(CHIP_ID),
+        .RID_INIT(CLUSTER_ID_OFFSET),
+        .CLUSTER_NX(CLUSTER_NX),
+        .CLUSTER_NY(CLUSTER_NY),
+        .CLUSTER_NZ(CLUSTER_NZ),
+        .CLUSTER_NE(NE)
+    ) local_noc(
+        .reset(reset),
+        .clk(clk),
+        .cluster_id(CHIP_ID[CLUSTER_IDw-1:0]),
+        .endpoint_chan_in(pronoc_chan_in),
+        .endpoint_chan_out(pronoc_chan_out),
+`ifdef PITON_MULTICHIP
+        .inter_cluster_chan_in(pronoc_inter_chip_in),
+        .inter_cluster_chan_out(pronoc_inter_chip_out),
+`else
+        .inter_cluster_chan_in('{default: '{default: '0}}),
+        .inter_cluster_chan_out(/* unused */),
+`endif // PITON_MULTICHIP
+        .router_event(/* unused */)
+    );
+endmodule
diff --git a/mpsoc/rtl/src_noc/class_table.v b/mpsoc/rtl/src_noc/class_table.v
deleted file mode 100755
index 70e5282..0000000
--- a/mpsoc/rtl/src_noc/class_table.v
+++ /dev/null
@@ -1,129 +0,0 @@
-`timescale      1ns/1ps
-
-/**********************************************************************
-**	File: class_table.v
-**    
-**	Copyright (C) 2014-2017  Alireza Monemi
-**    
-**	This file is part of ProNoC 
-**
-**	ProNoC ( stands for Prototype Network-on-chip)  is free software: 
-**	you can redistribute it and/or modify it under the terms of the GNU
-**	Lesser General Public License as published by the Free Software Foundation,
-**	either version 2 of the License, or (at your option) any later version.
-**
-** 	ProNoC is distributed in the hope that it will be useful, but WITHOUT
-** 	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
-** 	or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
-** 	Public License for more details.
-**
-** 	You should have received a copy of the GNU Lesser General Public
-** 	License along with ProNoC. If not, see <http:**www.gnu.org/licenses/>.
-**
-**
-**	Description: 
-**	
-*************************************/
-
-
- module class_ovc_table #(
-    parameter C= 4,//number of class 
-    parameter V= 4, //VC number per port
-    parameter CVw=(C==0)? V : C * V,
-    parameter [CVw-1:   0] CLASS_SETTING = {CVw{1'b1}} // shows how each class can use VCs   
-
-
-    )
-    (
-        class_in,
-        candidate_ovcs
-    );
-    
-   
-    function integer log2;
-      input integer number; begin   
-         log2=(number <=1) ? 1: 0;    
-         while(2**log2<number) begin    
-            log2=log2+1;    
-         end 	   
-      end   
-    endfunction // log2 
-    
-    localparam Cw= (C>1)?  log2(C): 1;
-    
-    input [Cw-1    :    0]    class_in;
-    output[V-1    :    0]    candidate_ovcs;
-    
-    genvar i;    
-    generate 
-        if(C == 0 || C == 1) begin: no_class // 
-    
-          assign  candidate_ovcs={V{1'b1}};
-    
-        end else begin: width_class
-        
-           wire [V-1  :   0] class_table [C-1  :   0];
-           for(i=0;i<C;i=i+1) begin : class_loop
-               assign class_table[i]= CLASS_SETTING[(i+1)*V-1  :   i*V];
-           end
-           
-                      
-           assign  candidate_ovcs=class_table[class_in];
-        
-        
-        
-        end
-     endgenerate
-    
-        
-endmodule
-
-
-module vc_priority_based_dest_port #(
-    parameter P=5,
-    parameter V=4
-
-)(
-    dest_port,
-    vc_pririty
-);
-
-    localparam      P_1       =  (P-1),
-                    OFFSET      =  V/(P_1);
-    
-    input   [P_1-1        :   0] dest_port;
-    reg     [V-1          :   0] vc_pririty_init;
-    output  [V-1          :   0] vc_pririty;
-    
-    genvar i;
-    integer j;  
-    generate 
-        if(P_1 == V  )begin :b1
-            always @(*) begin vc_pririty_init =  dest_port; end
-        
-        end else if (P_1 > V  )begin :b2
-          for (i=0;i<V; i=i+1)begin:yy
-            always @(*) begin 
-                  vc_pririty_init[i] = | dest_port[((i+1)*(P_1))/V-1:    (i*(P_1))/V ];          
-            end
-          end
-        end else begin :b3
-            always @(*) begin //P_1 < V
-                vc_pririty_init={V{1'b0}};
-                for (j=0;j<P_1; j=j+1)  vc_pririty_init[j+OFFSET] =  dest_port[j];            
-           
-            end
-       
-        end
-    endgenerate
-
-    assign vc_pririty=(vc_pririty_init==0)? {{(V-1){1'b0}},1'b1}: vc_pririty_init;
-
-endmodule
-
-
-
-
-
-
-
diff --git a/mpsoc/rtl/src_noc/comb-spec1.v b/mpsoc/rtl/src_noc/comb-spec1.sv
similarity index 58%
rename from mpsoc/rtl/src_noc/comb-spec1.v
rename to mpsoc/rtl/src_noc/comb-spec1.sv
index c2e0f47..805c7f9 100755
--- a/mpsoc/rtl/src_noc/comb-spec1.v
+++ b/mpsoc/rtl/src_noc/comb-spec1.sv
@@ -1,73 +1,65 @@
-`timescale    1ns/1ps
+`include "pronoc_def.v"
 
 /**********************************************************************
-**	File: comb_spec1.v
+**    File: comb_spec1.v
 **    
-**	Copyright (C) 2014-2017  Alireza Monemi
+**    Copyright (C) 2014-2017  Alireza Monemi
 **    
-**	This file is part of ProNoC 
+**    This file is part of ProNoC 
 **
-**	ProNoC ( stands for Prototype Network-on-chip)  is free software: 
-**	you can redistribute it and/or modify it under the terms of the GNU
-**	Lesser General Public License as published by the Free Software Foundation,
-**	either version 2 of the License, or (at your option) any later version.
+**    ProNoC ( stands for Prototype Network-on-chip)  is free software: 
+**    you can redistribute it and/or modify it under the terms of the GNU
+**    Lesser General Public License as published by the Free Software Foundation,
+**    either version 2 of the License, or (at your option) any later version.
 **
-** 	ProNoC is distributed in the hope that it will be useful, but WITHOUT
-** 	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
-** 	or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
-** 	Public License for more details.
+**     ProNoC is distributed in the hope that it will be useful, but WITHOUT
+**     ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+**     or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
+**     Public License for more details.
 **
-** 	You should have received a copy of the GNU Lesser General Public
-** 	License along with ProNoC. If not, see <http:**www.gnu.org/licenses/>.
+**     You should have received a copy of the GNU Lesser General Public
+**     License along with ProNoC. If not, see <http:**www.gnu.org/licenses/>.
 **
 **
-**	Description: 
-**	VC allocator combined with speculative switch allo-
-**	cator where free VC availability is checked at the end
-**	of switch allocation (comb-spec1).
+**    Description: 
+**    VC allocator combined with speculative switch allo-
+**    cator where free VC availability is checked at the end
+**    of switch allocation (comb-spec1).
 **
 ***********************************************************************/    
     
 module comb_spec1_allocator #(
-    parameter V = 4,// Virtual chanel num per port
-    parameter P = 5,
-    parameter DEBUG_EN = 1,
-    parameter SWA_ARBITER_TYPE = "WRRA",
-    parameter MIN_PCK_SIZE=2, //minimum packet size in flits. The minimum value is 1. 
-    parameter SELF_LOOP_EN = "NO"
-)(    
-        dest_port_all,
-        masked_ovc_request_all,
-        ovc_is_assigned_all,
-        ivc_request_all,
-        assigned_ovc_not_full_all,
-        ovc_allocated_all,
-        granted_ovc_num_all,
-        ivc_num_getting_ovc_grant,
-        ivc_num_getting_sw_grant,
-        spec_first_arbiter_granted_ivc_all,
-        nonspec_first_arbiter_granted_ivc_all,
-        granted_dest_port_all,
-        nonspec_granted_dest_port_all, 
-        any_ivc_sw_request_granted_all,
-        vc_weight_is_consumed_all,
-        iport_weight_is_consumed_all,
-        pck_is_single_flit_all,
-        granted_dst_is_from_a_single_flit_pck,
-        clk,reset
-
+    parameter P = 5
+)(
+    dest_port_all,
+    masked_ovc_request_all,
+    ovc_is_assigned_all,
+    ivc_request_all,
+    assigned_ovc_not_full_all,
+    ovc_allocated_all,
+    granted_ovc_num_all,
+    ivc_num_getting_ovc_grant,
+    ivc_num_getting_sw_grant,
+    nonspec_first_arbiter_granted_ivc_all,
+    granted_dest_port_all,
+    nonspec_granted_dest_port_all, 
+    any_ivc_sw_request_granted_all,
+    vc_weight_is_consumed_all,
+    iport_weight_is_consumed_all,
+    pck_is_single_flit_all,
+    granted_dst_is_from_a_single_flit_pck,
+    clk,reset
 );
-
+    import pronoc_pkg::*;
     localparam 
         PV = V * P,
         VV = V * V,
         PVV = PV * V,   
-        P_1 = (SELF_LOOP_EN=="NO")?  P-1 : P,
-        VP_1 = V * P_1,                
+        P_1 = (SELF_LOOP_EN )?  P : P-1,
+        VP_1 = V * P_1,
         PP_1 = P_1 * P,
         PVP_1 = PV * P_1;
-                    
-                  
+    
     input  [PVP_1-1 : 0] dest_port_all; 
     input  [PVV-1 : 0] masked_ovc_request_all; 
     input  [PV-1 : 0] ovc_is_assigned_all;
@@ -75,48 +67,28 @@ module comb_spec1_allocator #(
     input  [PV-1 : 0] assigned_ovc_not_full_all;
     input  [PV-1 : 0] vc_weight_is_consumed_all;
     input  [P-1 : 0] iport_weight_is_consumed_all;
-    
     output [PV-1 : 0] ovc_allocated_all;
     output [PVV-1 : 0] granted_ovc_num_all;
     output [PV-1 : 0] ivc_num_getting_ovc_grant;
     output [PV-1 : 0] ivc_num_getting_sw_grant;
     output [PV-1 : 0] nonspec_first_arbiter_granted_ivc_all;
-    output [PV-1 : 0] spec_first_arbiter_granted_ivc_all;
-        
     output [PP_1-1 : 0]  granted_dest_port_all;
     output [PP_1-1 : 0]  nonspec_granted_dest_port_all; 
     output [P-1 : 0] any_ivc_sw_request_granted_all;
-    
     input  [PV-1 : 0] pck_is_single_flit_all;
     output [P-1 : 0] granted_dst_is_from_a_single_flit_pck;
-    
     input clk,reset;
-
-    
     
-    
-
     //internal wires switch allocator
-    
     wire    [PV-1 : 0]  spec_first_arbiter_granted_ivc_all;
     wire    [PP_1-1 : 0]  spec_granted_dest_port_all;
     wire    [P-1 : 0] spec_any_ivc_grant_valid;
     wire    [P-1 : 0]  valid_speculation;
-   
-    
     
     //speculative switch allocator 
     spec_sw_alloc #(
-        .V(V),
-        .P(P),
-        .DEBUG_EN(DEBUG_EN),
-        .SWA_ARBITER_TYPE(SWA_ARBITER_TYPE),
-        .MIN_PCK_SIZE(MIN_PCK_SIZE)
-        
-    )
-    speculative_sw_allocator
-    (
-
+        .P(P)
+    ) speculative_sw_allocator (
         .ivc_granted_all(ivc_num_getting_sw_grant),
         .ivc_request_all(ivc_request_all),
         .ovc_is_assigned_all(ovc_is_assigned_all),
@@ -134,152 +106,95 @@ module comb_spec1_allocator #(
         .iport_weight_is_consumed_all(iport_weight_is_consumed_all),
         .pck_is_single_flit_all(pck_is_single_flit_all),
         .granted_dst_is_from_a_single_flit_pck(granted_dst_is_from_a_single_flit_pck),
-    
         .clk(clk),
         .reset(reset)
-    
     );
-      
-    wire    [V-1 : 0]  masked_non_assigned_request [PV-1 : 0]  ;   
-    wire    [VV-1 : 0]  masked_candidate_ovc_per_port   [P-1 : 0]  ;
-    wire    [V-1 : 0]  spec_first_arbiter_granted_ivc_per_port[P-1 : 0]  ;
-    wire    [V-1 : 0]  spec_first_arbiter_ovc_request  [P-1 : 0]  ;
-    wire    [V-1 : 0]  spec_first_arbiter_ovc_granted  [P-1 : 0]  ;
-    wire    [P_1-1 : 0]  spec_granted_dest_port_per_port [P-1 : 0];
-    wire    [VP_1-1 : 0] cand_ovc_granted                     [P-1 : 0];
-    wire    [P_1-1 : 0]  ovc_allocated_all_gen               [PV-1 : 0];
-    wire    [V-1 : 0]  granted_ovc_local_num_per_port  [P-1 : 0];
-    wire    [V-1 : 0]  ivc_local_num_getting_ovc_grant [P-1 : 0];
-     
-    genvar i,j;
-    generate 
- 
-    
-    // IVC loop
-    for(i=0;i< PV;i=i+1) begin :total_vc_loop
-        //seprate input/output
-        assign masked_non_assigned_request    [i]     =   masked_ovc_request_all [(i+1)*V-1 : i*V ];
-            
-    end//for
     
+    wire [V-1 : 0]  masked_non_assigned_request [PV-1 : 0]  ;   
+    wire [VV-1 : 0]  masked_candidate_ovc_per_port [P-1 : 0]  ;
+    wire [V-1 : 0]  spec_first_arbiter_granted_ivc_per_port[P-1 : 0]  ;
+    wire [V-1 : 0]  spec_first_arbiter_ovc_request [P-1 : 0]  ;
+    wire [V-1 : 0]  spec_first_arbiter_ovc_granted [P-1 : 0]  ;
+    wire [P_1-1 : 0]  spec_granted_dest_port_per_port [P-1 : 0];
+    wire [VP_1-1 : 0] cand_ovc_granted [P-1 : 0];
+    wire [P_1-1 : 0]  ovc_allocated_all_gen [PV-1 : 0];
+    wire [V-1 : 0]  granted_ovc_local_num_per_port  [P-1 : 0];
+    wire [V-1 : 0]  ivc_local_num_getting_ovc_grant [P-1 : 0];
     
-    for(i=0;i< P;i=i+1) begin :port_loop3
-            for(j=0;j< V;j=j+1) begin :vc_loop
-                //merge masked_candidate_ovc in each port
-                assign masked_candidate_ovc_per_port[i][(j+1)*V-1 : j*V]    =   masked_non_assigned_request [i*V+j];
-            end//for j
-            
-            assign spec_first_arbiter_granted_ivc_per_port[i]   =spec_first_arbiter_granted_ivc_all[(i+1)*V-1 : i*V];
-            assign spec_granted_dest_port_per_port[i]               =spec_granted_dest_port_all[(i+1)*P_1-1 : i*P_1];
-            // multiplex candidate OVC of first level switch allocatore winner
-            
+    genvar i,j;
+    generate 
+    for(i=0;i< P;i=i+1) begin :P_
+        for(j=0;j< V;j=j+1) begin : V_
+            //merge masked_candidate_ovc in each port
+            assign masked_candidate_ovc_per_port[i][(j+1)*V-1 : j*V] = masked_non_assigned_request [i*V+j];
+            assign granted_ovc_num_all[(i*VV)+((j+1)*V)-1 : (i*VV)+(j*V)]=granted_ovc_local_num_per_port[i];
+        end//for j
+        assign spec_first_arbiter_granted_ivc_per_port[i] = spec_first_arbiter_granted_ivc_all[(i+1)*V-1 : i*V];
+        assign spec_granted_dest_port_per_port[i] = spec_granted_dest_port_all[(i+1)*P_1-1 : i*P_1];
+        // multiplex candidate OVC of first level switch allocatore winner
         one_hot_mux #(
-            .IN_WIDTH       (VV),
-            .SEL_WIDTH      (V)
-        )
-        multiplexer2
-        (
-            .mux_in         (masked_candidate_ovc_per_port  [i]),
-            .mux_out            (spec_first_arbiter_ovc_request [i]),
-            .sel                (spec_first_arbiter_granted_ivc_per_port        [i])
-
+            .IN_WIDTH (VV),
+            .SEL_WIDTH (V)
+        ) mux2 (
+            .mux_in (masked_candidate_ovc_per_port [i]),
+            .mux_out (spec_first_arbiter_ovc_request [i]),
+            .sel (spec_first_arbiter_granted_ivc_per_port [i])
         );
-            
         //first level arbiter to candidate only one OVC 
         arbiter #(
-            .ARBITER_WIDTH  (V)            
-        )
-        second_arbiter
-        (   
-            .clk            (clk), 
-            .reset      (reset), 
-            .request        (spec_first_arbiter_ovc_request[i]), 
-            .grant      (spec_first_arbiter_ovc_granted[i]),
-            .any_grant   (valid_speculation[i])
-        );
-    
-        
-        //demultiplexer
-        
-        one_hot_demux   #(
-            .IN_WIDTH   (V),
-            .SEL_WIDTH  (P_1)
-        )demux1
-        (
-            .demux_sel  (spec_granted_dest_port_per_port [i]),//selectore
-            .demux_in   (spec_first_arbiter_ovc_granted[i]),//repeated
-            .demux_out  (cand_ovc_granted[i])
+            .ARBITER_WIDTH (V)
+        )  second_arbiter (
+            .clk (clk), 
+            .reset (reset), 
+            .request (spec_first_arbiter_ovc_request[i]), 
+            .grant (spec_first_arbiter_ovc_granted[i]),
+            .any_grant(valid_speculation[i])
         );
-    
-        
+        //Onehot demultiplexer
+        for (j = 0; j < P_1; j++) begin : P_
+            assign cand_ovc_granted [i][j*V +: V] = (spec_granted_dest_port_per_port [i][j]==1'b1) ? spec_first_arbiter_ovc_granted[i] : {V{1'b0}};
+        end
         assign granted_ovc_local_num_per_port[i]=(spec_any_ivc_grant_valid[i])?  spec_first_arbiter_ovc_granted[i] : {V{1'b0}};
         assign ivc_local_num_getting_ovc_grant[i]= (spec_any_ivc_grant_valid[i] & valid_speculation[i])?spec_first_arbiter_granted_ivc_per_port [i] : {V{1'b0}};
         assign ivc_num_getting_ovc_grant[(i+1)*V-1 : i*V] = ivc_local_num_getting_ovc_grant[i];
-        for(j=0;j<V;    j=j+1)begin: assign_loop3
-            assign granted_ovc_num_all[(i*VV)+((j+1)*V)-1 : (i*VV)+(j*V)]=granted_ovc_local_num_per_port[i];
-        end//j
     end//i
     
-
     wire [PV-1 : 0]  result;
-    for(i=0;i< PV;i=i+1) begin :total_vc_loop2
-        for(j=0;j<P;    j=j+1)begin: assign_loop2
-            if((i/V)<j )begin: jj
+    for(i=0;i< PV;i=i+1) begin : PV_
+        //seprate input/output
+        assign masked_non_assigned_request [i] = masked_ovc_request_all [(i+1)*V-1 : i*V ];
+        for(j=0;j<P; j=j+1)begin : P_
+            if((i/V)<j ) begin 
                 assign ovc_allocated_all_gen[i][j-1]    = cand_ovc_granted[j][i];
-            end else if((i/V)>j) begin: hh
+            end else if((i/V)>j) begin
                 assign ovc_allocated_all_gen[i][j]  = cand_ovc_granted[j][i-V];
                 
             end
         end//j
-        
         assign ovc_allocated_all [i] = |ovc_allocated_all_gen[i];
-        
-    //synthesis translate_off
-    //synopsys  translate_off
-    if(DEBUG_EN)begin :dbg
-    
-        is_onehot0 #(
-            .IN_WIDTH(P_1)
-        )
-        check_ovc_allocated
-        (
-            .in(ovc_allocated_all_gen[i]),
-            .result(result[i])
-    
-        );
-    
-        always @(posedge clk ) begin 
-            if(~result[i]) $display("%t,Error: An OVC is assigned to more than one IVC %m",$time);
-        end
-    end //DEBUG_EN
-    //synopsys  translate_on
-    //synthesis translate_on
-
+        `ifdef SIMULATION
+        if(DEBUG_EN) begin : dbg
+            is_onehot0 #(
+                .IN_WIDTH(P_1)
+            ) check_ovc_allocated (
+                .D_in(ovc_allocated_all_gen[i]),
+                .result(result[i])
+            );
+            always @(posedge clk ) begin 
+                if(~result[i]) $display("%t,Error: An OVC is assigned to more than one IVC %m",$time);
+            end
+        end //DEBUG_EN
+        `endif
     end//i   
-    
     endgenerate
-    
 endmodule 
 
-
-
 /******************************
-*
 *    speculative switch allocator
-*
 ******************************/
-
-        
-    
 module spec_sw_alloc #(
-    parameter V = 4,
-    parameter P = 5,
-    parameter DEBUG_EN = 1,
-    parameter SWA_ARBITER_TYPE="RRA",
-    parameter MIN_PCK_SIZE=2 //minimum packet size in flits. The minimum value is 1.    
-
+    parameter P = 5
 )(
-
     ivc_granted_all,
     ivc_request_all,
     ovc_is_assigned_all,
@@ -299,17 +214,15 @@ module spec_sw_alloc #(
     granted_dst_is_from_a_single_flit_pck,  
     clk,
     reset
-    
 );
-
-
-    localparam  
+    import pronoc_pkg::*;
+    localparam
         P_1 = P-1,//assumed that no port request for itself!
         PV = V * P,
-        VP_1 = V * P_1,                
-        PVP_1 = P * VP_1,   
+        VP_1 = V * P_1,
+        PVP_1 = P * VP_1,
         PP_1 = P_1 * P;
-
+    
     output  [PV-1 : 0]  ivc_granted_all;
     input   [PV-1 : 0] ivc_request_all;
     input   [PV-1 : 0] ovc_is_assigned_all;
@@ -327,11 +240,8 @@ module spec_sw_alloc #(
     input   [P-1 : 0] iport_weight_is_consumed_all;
     input  [PV-1 : 0] pck_is_single_flit_all;
     output [P-1 : 0] granted_dst_is_from_a_single_flit_pck;
-    
     input   clk, reset;
     
-    
-
     //internal wire 
     wire    [PV-1 : 0]  spec_ivc_granted_all,nonspec_ivc_granted_all;
     wire    [PV-1 : 0] spec_ivc_request_all,nonspec_ivc_request_all;
@@ -340,7 +250,6 @@ module spec_sw_alloc #(
     wire    [PP_1-1 : 0]  spec_granted_dest_port_all,spec_granted_dest_port_all_accepted;
     wire    [P-1 : 0]  nonspec_inport_granted_all,nonspec_outport_granted_all;
     wire    [PP_1-1 : 0]  spec_granted_dest_port_all_pre;
-    
     wire    [P_1-1 : 0]  nonspec_portsel_granted [P-1 : 0];
     wire    [PP_1-1 : 0]  spec_request_acceptable;
     wire    [P_1-1 : 0]  spec_request_accepted [P-1 : 0];
@@ -348,16 +257,9 @@ module spec_sw_alloc #(
     wire    [PV-1 : 0]  spec_ivc_granted_all_accepted;
     wire    [P-1 : 0]  spec_any_ivc_grant,nonspec_any_ivc_grant;
     
-    
     sw_alloc_sub#(
-        .V(V),
-        .P(P),
-        .SWA_ARBITER_TYPE(SWA_ARBITER_TYPE),
-        .MIN_PCK_SIZE(MIN_PCK_SIZE)
-            
-    )
-    speculative_alloc
-    (
+        .P(P)
+    )  speculative_alloc (
         .ivc_granted_all(spec_ivc_granted_all),
         .ivc_request_all(spec_ivc_request_all),
         .assigned_ovc_not_full_all(spec_assigned_ovc_not_full_all),
@@ -375,16 +277,10 @@ module spec_sw_alloc #(
         .clk (clk),
         .reset (reset) 
     );
-
-
+    
     sw_alloc_sub#(
-        .V(V),
-        .P(P),
-        .SWA_ARBITER_TYPE(SWA_ARBITER_TYPE),
-        .MIN_PCK_SIZE(MIN_PCK_SIZE) 
-    )
-    nonspeculative_alloc
-    (
+        .P(P)
+    ) nonspeculative_alloc(
         .ivc_granted_all (nonspec_ivc_granted_all),
         .ivc_request_all (nonspec_ivc_request_all),
         .assigned_ovc_not_full_all (nonspec_assigned_ovc_not_full_all),
@@ -400,40 +296,37 @@ module spec_sw_alloc #(
         .pck_is_single_flit_all( ),
         .granted_dst_is_from_a_single_flit_pck( ),
         .clk (clk),
-        .reset (reset)   
+        .reset (reset)
     );
     
-    assign nonspec_ivc_request_all      = ivc_request_all &  ovc_is_assigned_all;
-    assign spec_ivc_request_all         = ivc_request_all &  ~ovc_is_assigned_all;
-    assign spec_assigned_ovc_not_full_all           = {PV{1'b1}};
-    assign nonspec_assigned_ovc_not_full_all        = assigned_ovc_not_full_all;    
-    assign spec_dest_port_all               = dest_port_all;
-    assign nonspec_dest_port_all            = dest_port_all;
-    
-   
+    assign nonspec_ivc_request_all = ivc_request_all &  ovc_is_assigned_all;
+    assign spec_ivc_request_all = ivc_request_all &  ~ovc_is_assigned_all;
+    assign spec_assigned_ovc_not_full_all   = {PV{1'b1}};
+    assign nonspec_assigned_ovc_not_full_all   = assigned_ovc_not_full_all;    
+    assign spec_dest_port_all  = dest_port_all;
+    assign nonspec_dest_port_all  = dest_port_all;
     
     genvar i,j;
     generate 
-    for(i=0;i<P; i=i+1) begin :port_lp
+    for(i=0;i<P; i=i+1) begin : P_
         //remove non-spec inport from the nonspec_outport_granted_all
-        for(j=0;j<P;    j=j+1)begin: port_loop2
-            if(i<j)begin: jj
-                assign nonspec_portsel_granted[i][j-1]  = nonspec_outport_granted_all[j];
-            end else if(i>j)begin: hh
-                assign nonspec_portsel_granted[i][j]        = nonspec_outport_granted_all [j];
+        for(j=0;j<P; j=j+1)begin :P_
+            if(i<j)begin
+                assign nonspec_portsel_granted[i][j-1] = nonspec_outport_granted_all[j];
+            end else if(i>j)begin
+                assign nonspec_portsel_granted[i][j] = nonspec_outport_granted_all [j];
             end
             //if(i==j) wires are left disconnected  
         end//j
         // an speculative grant is acceptable if the non-speculative request is not granted for both inport request and outport grant
         assign spec_request_acceptable[(i+1)*P_1-1 : i*P_1] = (nonspec_inport_granted_all[i])? {P_1{1'b0}} : ~nonspec_portsel_granted[i];
-        assign spec_request_accepted  [i]= spec_request_acceptable[(i+1)*P_1-1 : i*P_1] & spec_granted_dest_port_all_pre[(i+1)*P_1-1 : i*P_1];
-        assign any_spec_request_accepted [i] = |spec_request_accepted  [i];
+        assign spec_request_accepted [i]= spec_request_acceptable[(i+1)*P_1-1 : i*P_1] & spec_granted_dest_port_all_pre[(i+1)*P_1-1 : i*P_1];
+        assign any_spec_request_accepted [i] = |spec_request_accepted [i];
         assign spec_ivc_granted_all_accepted[(i+1)*V-1 : i*V] = (any_spec_request_accepted [i] & valid_speculation[i])? spec_ivc_granted_all[(i+1)*V-1 : i*V]: {V{1'b0}};
         assign spec_granted_dest_port_all_accepted[(i+1)*P_1-1 : i*P_1]=(valid_speculation[i])? spec_request_accepted  [i]: {P_1{1'b0}};
-    
-    //synthesis translate_off
-    //synopsys  translate_off
-        if(DEBUG_EN)begin :dbg
+        
+        `ifdef SIMULATION
+        if(DEBUG_EN) begin : dbg
             wire [P_1-1 : 0]  nonspec_check [P-1:0];
             wire [P_1-1 : 0]  spec_check [P-1:0];
             assign nonspec_check[i] = nonspec_granted_dest_port_all[(i+1)*P_1-1 : i*P_1];
@@ -443,21 +336,15 @@ module spec_sw_alloc #(
                 if(nonspec_ivc_granted_all [(i+1)*V-1 : i*V] >0 && spec_ivc_granted_all_accepted[(i+1)*V-1 : i*V]>0 ) $display("%t: Error: Both speculative and nonspeculative is granted for one port",$time);
             end
         end //DEBUG
-    //synopsys  translate_on
-    //synthesis translate_on
-   
-    
-    
+        `endif
     end//i
     endgenerate
     
     assign spec_any_ivc_grant_valid = any_spec_request_accepted & valid_speculation & spec_any_ivc_grant;
     assign any_ivc_sw_request_granted_all = nonspec_any_ivc_grant | spec_any_ivc_grant_valid;    
-    
     assign granted_dest_port_all = nonspec_granted_dest_port_all | spec_granted_dest_port_all_accepted;
     assign ivc_granted_all = nonspec_ivc_granted_all | spec_ivc_granted_all_accepted;
     assign spec_granted_dest_port_all = spec_granted_dest_port_all_accepted;    
-    
 endmodule
 
 /**********************************
@@ -465,14 +352,8 @@ endmodule
 *    canonical switch allocator
 *
 **********************************/
-
-    
 module sw_alloc_sub#(
-    parameter V = 4,
-    parameter P = 5,
-    parameter SWA_ARBITER_TYPE="RRA",
-    parameter MIN_PCK_SIZE=2 //minimum packet size in flits. The minimum value is 1.       
-
+    parameter P = 5
 )(
     ivc_granted_all,
     ivc_request_all,
@@ -489,20 +370,18 @@ module sw_alloc_sub#(
     pck_is_single_flit_all,
     granted_dst_is_from_a_single_flit_pck,
     clk,
-    reset    
+    reset
 );
-
-
+    import pronoc_pkg::*;
     localparam  
         P_1 = P-1,//assumed that no port request for itself!
         PV = V * P,
-        VP_1 = V * P_1,                
-        PVP_1 = P * VP_1,   
+        VP_1 = V * P_1,
+        PVP_1 = P * VP_1,
         PP_1 = P_1 * P,
         PP = P * P;
-                    
-
-    output [PV-1 : 0]  ivc_granted_all;
+    
+    output [PV-1 : 0] ivc_granted_all;
     input  [PV-1 : 0] ivc_request_all;
     input  [PV-1 : 0] assigned_ovc_not_full_all;
     input  [PVP_1-1 : 0]  dest_port_all;
@@ -525,26 +404,23 @@ module sw_alloc_sub#(
     wire [V-1 : 0]  ivc_not_full [P-1 : 0];
     wire [VP_1-1 : 0] dest_port_ivc [P-1 : 0];
     wire [P_1-1 : 0]  granted_dest_port [P-1 : 0];
-    
     // internal wires
-    wire [V-1 : 0] ivc_masked [P-1 : 0];//output of mask and             
-    wire [V-1 : 0] first_arbiter_grant [P-1 : 0];//output of first arbiter            
+    wire [V-1 : 0] ivc_masked [P-1 : 0];//output of mask and
+    wire [V-1 : 0] first_arbiter_grant [P-1 : 0];//output of first arbiter
     wire [P_1-1 : 0] dest_port [P-1 : 0];//output of multiplexer
-    wire [P_1-1 : 0] second_arbiter_request [P-1 : 0]; 
-    wire [P_1-1 : 0] second_arbiter_grant [P-1 : 0];             
+    wire [P_1-1 : 0] second_arbiter_request [P-1 : 0];
+    wire [P_1-1 : 0] second_arbiter_grant [P-1 : 0];
     wire [P_1-1 : 0] second_arbiter_weight_consumed [P-1 : 0]; 
     wire [V-1 : 0] vc_weight_is_consumed [P-1 : 0]; 
     wire [P-1 : 0] winner_weight_consumed;     
-    
     wire [P_1-1 : 0] single_flit_granted_dst [P-1 : 0];
-    wire [PP-1 : 0] single_flit_granted_dst_all;
-    wire [V-1 : 0] pck_is_single_flit [P-1 : 0]; 
-    wire    [P-1 : 0] single_flit_pck_local_grant;   
-          
+    wire [P-1 : 0] single_flit_granted_dst_all [P-1 : 0];
+    wire [V-1 : 0] pck_is_single_flit [P-1 : 0];
+    wire [P-1 : 0] single_flit_pck_local_grant;
+    
     genvar i,j;
     generate
-    
-    for(i=0;i< P;i=i+1) begin :port_loop
+    for(i=0;i< P;i=i+1) begin : P_
         //assign in/out to the port based wires
         //output
         assign ivc_granted_all          [(i+1)*V-1 : i*V]    =   ivc_granted [i];
@@ -555,134 +431,93 @@ module sw_alloc_sub#(
         assign ivc_not_full[i]      = assigned_ovc_not_full_all[(i+1)*V-1 : i*V];
         assign dest_port_ivc[i]     = dest_port_all [(i+1)*VP_1-1 : i*VP_1];
         assign vc_weight_is_consumed[i]  =  vc_weight_is_consumed_all [(i+1)*V-1 : i*V];
-        
         //mask
         assign ivc_masked[i]    = ivc_request[i] & ivc_not_full[i];
-        
-        //first level arbiter        
+        //first level arbiter
         swa_input_port_arbiter #(
-         	.ARBITER_WIDTH(V),
-         	.EXT_P_EN(0),
-         	.ARBITER_TYPE(SWA_ARBITER_TYPE)
-        )
-        input_arbiter
-        (
-         	.ext_pr_en_i(1'b1),// not used here anyway
-         	.request(ivc_masked [i]),
-         	.grant(first_arbiter_grant[i]),
-         	.any_grant( ),
-         	.clk(clk),
-         	.reset(reset),
-         	.vc_weight_is_consumed(vc_weight_is_consumed[i]),
+            .ARBITER_WIDTH(V),
+            .EXT_P_EN(0)
+        ) input_arbiter (
+            .ext_pr_en_i(1'b1),// not used here anyway
+            .request(ivc_masked [i]),
+            .grant(first_arbiter_grant[i]),
+            .any_grant( ),
+            .clk(clk),
+            .reset(reset),
+            .vc_weight_is_consumed(vc_weight_is_consumed[i]),
             .winner_weight_consumed(winner_weight_consumed[i])
         );
-       
         //destination port multiplexer
         one_hot_mux #(
             .IN_WIDTH(VP_1),
             .SEL_WIDTH(V)
-        )
-        multiplexer
-        (
-            .mux_in (dest_port_ivc  [i]),
-            .mux_out(dest_port      [i]),
+        ) mux  (
+            .mux_in (dest_port_ivc[i]),
+            .mux_out(dest_port[i]),
             .sel(first_arbiter_grant[i])    
         );
-        
-        assign first_arbiter_granted_port_all[(i+1)*P_1-1 : i*P_1]  = dest_port     [i];
-    
-
-    if(MIN_PCK_SIZE == 1) begin :single_flit_supported 
-         assign pck_is_single_flit[i] = pck_is_single_flit_all [(i+1)*V-1 : i*V];
+        assign first_arbiter_granted_port_all[(i+1)*P_1-1 : i*P_1]  = dest_port [i];
+        if(MIN_PCK_SIZE == 1) begin 
+            assign pck_is_single_flit[i] = pck_is_single_flit_all [(i+1)*V-1 : i*V];
             //single_flit req multiplexer
             one_hot_mux #(
-                .IN_WIDTH       (V),
-                .SEL_WIDTH      (V)
-            )
-            multiplexer2
-            (
-                .mux_in (pck_is_single_flit  [i]),
-                .mux_out (single_flit_pck_local_grant[i]),
-                .sel (first_arbiter_grant[i])
-        
-            );   
-            
-            assign  single_flit_granted_dst[i] = (single_flit_pck_local_grant[i])?  granted_dest_port[i] : {P_1{1'b0}};
-    
+                .IN_WIDTH(V),
+                .SEL_WIDTH(V)
+            ) mux2 (
+                .mux_in(pck_is_single_flit[i]),
+                .mux_out(single_flit_pck_local_grant[i]),
+                .sel(first_arbiter_grant[i])
+            );
+            assign single_flit_granted_dst[i] = (single_flit_pck_local_grant[i]) ? granted_dest_port[i] : {P_1{1'b0}};
             add_sw_loc_one_hot #(
                 .P(P),
                 .SW_LOC(i)
-            )
-            add_sw_loc
-            (
+            ) add_sw_loc (
                 .destport_in(single_flit_granted_dst[i]),
-                .destport_out(single_flit_granted_dst_all[(i+1)*P-1 : i*P])
+                .destport_out(single_flit_granted_dst_all[i])
             );
-            
         end else begin : single_flit_notsupported 
             assign single_flit_pck_local_grant[i] = 1'b0;
             assign single_flit_granted_dst[i] = {P_1{1'b0}};
-            assign single_flit_granted_dst_all[(i+1)*P-1 : i*P]={P{1'b0}};
+            assign single_flit_granted_dst_all[i] = {P{1'b0}};
         end
-
-
-
-//second arbiter input/output generate
-    for(j=0;j<P;    j=j+1)begin: assign_loop
-            if(i<j)begin: jj
+        //second arbiter input/output generate
+        for(j=0;j<P; j=j+1)begin: P_
+            if(i<j)begin
                 assign second_arbiter_request[i][j-1]   = dest_port[j][i]   ;
                 //assign second_arbiter_weight_consumed[i][j-1]  =winner_weight_consumed[j] ;
                 assign second_arbiter_weight_consumed[i][j-1]  =iport_weight_is_consumed_all[j];
                 assign granted_dest_port[j][i]  = second_arbiter_grant  [i][j-1]    ;
-            end else if(i>j)begin: hh
+            end else if(i>j)begin
                 assign second_arbiter_request[i][j] = dest_port [j][i-1];
                 //assign second_arbiter_weight_consumed[i][j]  =winner_weight_consumed[j];
                 assign second_arbiter_weight_consumed[i][j]  =iport_weight_is_consumed_all[j];
                 assign granted_dest_port[j][i-1]    = second_arbiter_grant  [i][j];
             end
             //if(i==j) wires are left disconnected  
-        
         end
-    
-        
-       
         //second level arbiter 
         swa_output_port_arbiter #(
-            .ARBITER_WIDTH(P_1),
-            .ARBITER_TYPE(SWA_ARBITER_TYPE) // RRA, WRRA
-        )
-        output_arbiter        
-        (
+            .ARBITER_WIDTH(P_1)
+        ) output_arbiter (
            .weight_consumed(second_arbiter_weight_consumed[i]),  // only used for WRRA
-           .clk(clk), 
-           .reset(reset), 
-           .request(second_arbiter_request [i]), 
-           .grant(second_arbiter_grant [i]),
-           .any_grant(outport_granted_all [i])  
+            .clk(clk), 
+            .reset(reset), 
+            .request(second_arbiter_request [i]), 
+            .grant(second_arbiter_grant [i]),
+            .any_grant(outport_granted_all [i])  
         );
-        
-        
-        
         //any ivc 
         assign  any_ivc_grant[i] = | granted_dest_port[i];
-        
         assign  ivc_granted[i] =  (any_ivc_grant[i]) ? first_arbiter_grant[i] : {V{1'b0}};
-                
         assign      inport_granted_all[i]   =any_ivc_grant[i];
     end//for
     endgenerate 
-     
-      custom_or #(
-            .IN_NUM(P),
-            .OUT_WIDTH(P)
-         )
-         or_dst
-         (
-            .or_in(single_flit_granted_dst_all),
-            .or_out(granted_dst_is_from_a_single_flit_pck)
-        );
-        
-    
-endmodule
-  
-
+    reduction_or #(
+        .W(P),
+        .N(P)
+    ) or_dst (
+        .D_in(single_flit_granted_dst_all),
+        .Q_out(granted_dst_is_from_a_single_flit_pck)
+    );
+endmodule
\ No newline at end of file
diff --git a/mpsoc/rtl/src_noc/comb_nonspec.sv b/mpsoc/rtl/src_noc/comb_nonspec.sv
index 5f48418..57b857f 100755
--- a/mpsoc/rtl/src_noc/comb_nonspec.sv
+++ b/mpsoc/rtl/src_noc/comb_nonspec.sv
@@ -1,52 +1,49 @@
 `include "pronoc_def.v"
 
 /**********************************************************************
-**	File: comb-nonspec.v
+**    File: comb-nonspec.v
 **    
-**	Copyright (C) 2014-2017  Alireza Monemi
+**    Copyright (C) 2014-2017  Alireza Monemi
 **    
-**	This file is part of ProNoC 
+**    This file is part of ProNoC 
 **
-**	ProNoC ( stands for Prototype Network-on-chip)  is free software: 
-**	you can redistribute it and/or modify it under the terms of the GNU
-**	Lesser General Public License as published by the Free Software Foundation,
-**	either version 2 of the License, or (at your option) any later version.
+**    ProNoC ( stands for Prototype Network-on-chip)  is free software: 
+**    you can redistribute it and/or modify it under the terms of the GNU
+**    Lesser General Public License as published by the Free Software Foundation,
+**    either version 2 of the License, or (at your option) any later version.
 **
-** 	ProNoC is distributed in the hope that it will be useful, but WITHOUT
-** 	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
-** 	or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
-** 	Public License for more details.
+**     ProNoC is distributed in the hope that it will be useful, but WITHOUT
+**     ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+**     or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
+**     Public License for more details.
 **
-** 	You should have received a copy of the GNU Lesser General Public
-** 	License along with ProNoC. If not, see <http:**www.gnu.org/licenses/>.
+**     You should have received a copy of the GNU Lesser General Public
+**     License along with ProNoC. If not, see <http:**www.gnu.org/licenses/>.
 **
 **
-**	Description: 
-**	VC allocator combined with non-speculative switch
-**	allocator where the free VC availability is checked at
-**	the beginning of switch allocation (comb-nonspec).        
+**    Description: 
+**    VC allocator combined with non-speculative switch
+**    allocator where the free VC availability is checked at
+**    the beginning of switch allocation (comb-nonspec).        
 **
 ***********************************************************************/    
 
-    
 module comb_nonspec_allocator # (
-    parameter NOC_ID = 0,
     parameter P = 5 //port number
 )(
     //VC allocator
     //input 
-    dest_port_all,         // from input port
+    dest_port_all,  // from input port
     masked_ovc_request_all,
     pck_is_single_flit_all,
     
-    
     //output 
     ovc_allocated_all,//to the output port
     granted_ovc_num_all, // to the input port
     ivc_num_getting_ovc_grant,
     
     //switch_alloc
-    ivc_info,   
+    ivc_info,
     vc_weight_is_consumed_all,
     iport_weight_is_consumed_all,
     
@@ -61,68 +58,46 @@ module comb_nonspec_allocator # (
     // global
     clk,
     reset
-
 );
-
-	`NOC_CONF
-       
+    import pronoc_pkg::*; 
     localparam
-        P_1 = (SELF_LOOP_EN == "NO")? P-1 : P,
+        P_1 = (SELF_LOOP_EN)? P : P-1,
         PV = V * P,
         VV = V * V,
-        VP_1 = V * P_1,                
+        VP_1 = V * P_1,
         PP_1 = P_1 * P,
         PVV = PV * V,
-        PVP_1 = PV * P_1;            
-
-    
+        PVP_1 = PV * P_1;
     input  ivc_info_t ivc_info [P-1 : 0][V-1 : 0]; 
-        
     input  [PVV-1 : 0] masked_ovc_request_all;
     input  [PVP_1-1 : 0] dest_port_all;
-   
     input  [PV-1 : 0] pck_is_single_flit_all;
     output [PV-1 : 0] ovc_allocated_all;
     output [PVV-1 : 0] granted_ovc_num_all;
     output [PV-1 : 0] ivc_num_getting_ovc_grant;
-    
-    
     output [PP_1-1 : 0] granted_dest_port_all;
     output [PV-1 : 0] ivc_num_getting_sw_grant;
     output [P-1 : 0] any_ivc_sw_request_granted_all;
     output [P-1 : 0] any_ovc_granted_in_outport_all;
     output [PV-1 : 0] nonspec_first_arbiter_granted_ivc_all;
-
     input  clk,reset;
     input  [PV-1 : 0] vc_weight_is_consumed_all;
     input  [P-1 : 0] iport_weight_is_consumed_all;
     output [P-1 : 0] granted_dst_is_from_a_single_flit_pck;
-        
-
-
+    
     //internal wires switch allocator
     wire  [PV-1 : 0] first_arbiter_granted_ivc_all;
     wire  [PV-1 : 0] ivc_request_masked_all;
-    wire  [P-1 : 0] any_cand_ovc_exsit;    
-    
     wire  [PV-1 : 0] ivc_request_all;
     wire  [PV-1 : 0] ovc_is_assigned_all;
     wire  [PV-1 : 0] assigned_ovc_not_full_all;    
     
     assign nonspec_first_arbiter_granted_ivc_all = first_arbiter_granted_ivc_all;
-        
+    
     //nonspeculative switch allocator 
     nonspec_sw_alloc #(
-        .V(V),
-        .P(P),
-        .FIRST_ARBITER_EXT_P_EN(FIRST_ARBITER_EXT_P_EN),
-        .SWA_ARBITER_TYPE (SWA_ARBITER_TYPE),
-        .MIN_PCK_SIZE(MIN_PCK_SIZE),
-        .SELF_LOOP_EN(SELF_LOOP_EN)
-    )
-    nonspeculative_sw_allocator
-    (
-
+        .P(P)
+    ) nonspeculative_sw_allocator (
         .ivc_granted_all (ivc_num_getting_sw_grant),
         .ivc_request_masked_all (ivc_request_masked_all),
         .pck_is_single_flit_all(pck_is_single_flit_all),
@@ -137,202 +112,106 @@ module comb_nonspec_allocator # (
         .clk (clk),
         .reset (reset)    
     );
-        
+    
     wire   [PVV-1 : 0] masked_ovc_request_all;
-    wire   [V-1 : 0] masked_non_assigned_request    [PV-1 : 0] ;    
+    wire   [V-1 : 0] masked_non_assigned_request [PV-1 : 0] ;    
     wire   [PV-1 : 0] masked_assigned_request;
     wire   [PV-1 : 0] assigned_ovc_request_all ;
-    wire   [VV-1 : 0] masked_candidate_ovc_per_port    [P-1 : 0] ;
+    wire   [V-1 : 0] masked_candidate_ovc_per_port [P-1 : 0][V-1:0];
     wire   [V-1 : 0] first_arbiter_granted_ivc_per_port[P-1 : 0] ;
-    wire   [V-1 : 0] candidate_ovc_local_num   [P-1 : 0] ;
-    wire   [V-1 : 0] first_arbiter_ovc_granted        [PV-1 : 0];
-    wire   [P_1-1 : 0] granted_dest_port_per_port        [P-1 : 0];
-    wire   [VP_1-1 : 0] cand_ovc_granted           [P-1 : 0];
-    wire   [P_1-1 : 0] ovc_allocated_all_gen   [PV-1 : 0];
-    wire   [V-1 : 0] granted_ovc_local_num_per_port     [P-1 : 0];
+    logic  [V-1 : 0] candidate_ovc_local_num [P-1 : 0] ;
+    wire   [V-1 : 0] first_arbiter_ovc_granted [PV-1 : 0];
+    wire   [P_1-1 : 0] granted_dest_port_per_port [P-1 : 0];
+    wire   [VP_1-1 : 0] cand_ovc_granted [P-1 : 0];
+    wire   [P_1-1 : 0] ovc_allocated_all_gen  [PV-1 : 0];
+    wire   [V-1 : 0] granted_ovc_local_num_per_port [P-1 : 0];
     wire   [V-1 : 0] ivc_local_num_getting_ovc_grant[P-1 : 0];
     wire   [V : 0] summ_in [PV-1 : 0];
-    wire   [V-1 : 0]  vc_pririty [PV-1 : 0] ;
     
     assign assigned_ovc_request_all =   ivc_request_all &   ovc_is_assigned_all;
-        
-    genvar i,j;    
+    //One-hot multiplex candidate OVC of first level switch allocator winner
+    always_comb begin
+        for(int m=0;m< P;m++) begin
+            candidate_ovc_local_num [m] = '0;
+            for (int k = 0; k < V; k++)
+                candidate_ovc_local_num [m] |= (first_arbiter_granted_ivc_per_port[m][k]) ?  masked_candidate_ovc_per_port[m][k] :  '0;
+        end
+    end
+    genvar i,j;
     generate 
     // IVC loop
-    for(i=0;i< PV;i=i+1) begin :total_vc_loop      
-    	
-    	// mask unavailable ovc from requests
-        assign masked_non_assigned_request    [i]  =    masked_ovc_request_all [(i+1)*V-1 : i*V ];
-        assign masked_assigned_request        [i]  =    assigned_ovc_not_full_all [i] & assigned_ovc_request_all [i]; 
-        
+    for(i=0;i< PV;i=i+1) begin :PV_
+        // mask unavailable ovc from requests
+        assign masked_non_assigned_request [i] = masked_ovc_request_all [(i+1)*V-1 : i*V ];
+        assign masked_assigned_request [i] = assigned_ovc_not_full_all [i] & assigned_ovc_request_all [i]; 
         // summing assigned and non-assigned VC requests
-        assign summ_in[i] ={masked_non_assigned_request    [i],masked_assigned_request        [i]};
+        assign summ_in[i] ={masked_non_assigned_request [i], masked_assigned_request [i]};
         assign ivc_request_masked_all[i] = | summ_in[i];        
-    
         //first level arbiter to candidate only one OVC 
         //if(VC_ARBITER_TYPE=="RRA")begin :round_robin
-        
-            arbiter #(
-                .ARBITER_WIDTH(V)
-              )
-              ovc_arbiter
-              (    
-                .clk        (clk), 
-                .reset        (reset), 
-                .request    (masked_non_assigned_request    [i]), 
-                .grant        (first_arbiter_ovc_granted[i]),
-                .any_grant    ()
-              );
-       /*       
-        end  else begin :fixarb
-        
-            vc_priority_based_dest_port#(
-                .P(P),
-                .V(V) 
-             ) 
-             priority_setting
-             (
-                .dest_port(lk_destination_all [((i+1)*P_1)-1 : i*P_1]),
-                .vc_pririty(vc_pririty[i])
-             );
-        
-        
-        
-            arbiter_ext_priority #(
-              .ARBITER_WIDTH (V)
-            )
-            ovc_arbiter
-            ( 
-                 .request (masked_non_assigned_request    [i]), 
-                 .priority_in(vc_pririty[i]),
-                 .grant(first_arbiter_ovc_granted[i]),
-                 .any_grant()
-              ); 
-         
-         end
-       */ 
-    
+        arbiter #(
+            .ARBITER_WIDTH(V)
+        ) ovc_arbiter (
+            .clk (clk), 
+            .reset (reset), 
+            .request (masked_non_assigned_request    [i]), 
+            .grant (first_arbiter_ovc_granted[i]),
+            .any_grant()
+        );
     end//for
     
     wire [P-1 : 0] ovc_assigned_local;
-    	
-    for(i=0;i< P;i=i+1) begin :port_loop3
-            for(j=0;j< V;j=j+1) begin :vc_loop
-                //merge masked_candidate_ovc in each port
-            	
-            	assign ivc_request_all[i*V+j] = ivc_info[i][j].ivc_req;
-            	assign ovc_is_assigned_all[i*V+j] = ivc_info[i][j].ovc_is_assigned;  
-            	assign assigned_ovc_not_full_all[i*V+j] =ivc_info[i][j].assigned_ovc_not_full;
-            	
-            	
-                assign masked_candidate_ovc_per_port[i][(j+1)*V-1 : j*V] =    first_arbiter_ovc_granted    [i*V+j];
-            end//for j
-            
-            assign first_arbiter_granted_ivc_per_port[i]=first_arbiter_granted_ivc_all[(i+1)*V-1 : i*V];
-            assign granted_dest_port_per_port[i]=granted_dest_port_all[(i+1)*P_1-1 : i*P_1];
-            
-        
-        // multiplex candidate OVC of first level switch allocatore winner    
-        onehot_mux_1D #(
-            .W (V),
-            .N (V)
-        )
-        multiplexer2
-        (
-        	.in            (masked_candidate_ovc_per_port    [i]),
-        	.out            (candidate_ovc_local_num    [i]),
-            .sel                (first_arbiter_granted_ivc_per_port        [i])
-
-        );
-        
-        
-        
-        onehot_mux_1D #(
-        		.W (1),
-        		.N (V)
-        	)
-        	multiplexer2_1
-        	(
-        		.in  (ovc_is_assigned_all[(i+1)*V-1 : i*V]),
-        		.out (ovc_assigned_local[i]),
-        		.sel (first_arbiter_granted_ivc_per_port [i])
-
-        	);
-        
-        
-     //   assign any_cand_ovc_exsit[i] = | candidate_ovc_local_num    [i];
-    
-        
-        //demultiplexer        
-        one_hot_demux #(
-            .IN_WIDTH(V),
-            .SEL_WIDTH(P_1)
-        )
-        demux1
-        (
-            .demux_sel(granted_dest_port_per_port [i]),//selectore
-            .demux_in(candidate_ovc_local_num[i]),//repeated
-            .demux_out(cand_ovc_granted [i])
-        );
-    
-        assign granted_ovc_local_num_per_port    [i]=(any_ivc_sw_request_granted_all[i] )?  candidate_ovc_local_num[i] : {V{1'b0}};
-        assign ivc_local_num_getting_ovc_grant    [i]= (any_ivc_sw_request_granted_all[i] & ~ovc_assigned_local[i])?     first_arbiter_granted_ivc_per_port [i] : {V{1'b0}};
-        assign ivc_num_getting_ovc_grant   [(i+1)*V-1 : i*V] = ivc_local_num_getting_ovc_grant[i];
-        for(j=0;j<V;    j=j+1)begin: assign_loop3
+    for(i=0;i< P;i=i+1) begin : P_
+        for(j=0;j< V;j=j+1) begin : V_
+            //merge masked_candidate_ovc in each port
+            assign ivc_request_all[i*V+j] = ivc_info[i][j].ivc_req;
+            assign ovc_is_assigned_all[i*V+j] = ivc_info[i][j].ovc_is_assigned;  
+            assign assigned_ovc_not_full_all[i*V+j] =ivc_info[i][j].assigned_ovc_not_full;           
+            assign masked_candidate_ovc_per_port[i][j] = first_arbiter_ovc_granted [i*V+j];
             assign granted_ovc_num_all[(i*VV)+((j+1)*V)-1 : (i*VV)+(j*V)]=granted_ovc_local_num_per_port[i];
-        end//j
+        end//for j
+        assign first_arbiter_granted_ivc_per_port[i]=first_arbiter_granted_ivc_all[(i+1)*V-1 : i*V];
+        assign granted_dest_port_per_port[i]=granted_dest_port_all[(i+1)*P_1-1 : i*P_1];
+        //one hot mux to select granted OVC
+        assign ovc_assigned_local[i] = |(ovc_is_assigned_all[(i+1)*V-1 : i*V] & first_arbiter_granted_ivc_per_port [i]);
+        //Onehot demultiplexer
+        for (j = 0; j < P_1; j++) begin : P_
+            assign cand_ovc_granted [i][j*V +: V] = (granted_dest_port_per_port [i][j]==1'b1) ? candidate_ovc_local_num[i] : {V{1'b0}};
+        end
+        assign granted_ovc_local_num_per_port[i] = (any_ivc_sw_request_granted_all[i] )?  candidate_ovc_local_num[i] : {V{1'b0}};
+        assign ivc_local_num_getting_ovc_grant [i] = (any_ivc_sw_request_granted_all[i] & ~ovc_assigned_local[i])?     first_arbiter_granted_ivc_per_port [i] : {V{1'b0}};
+        assign ivc_num_getting_ovc_grant   [(i+1)*V-1 : i*V] = ivc_local_num_getting_ovc_grant[i];
     end//i
     
-    
-    for(i=0;i< PV;i=i+1) begin :total_vc_loop2
-        for(j=0;j<P;    j=j+1)begin: assign_loop2
-            if(SELF_LOOP_EN == "NO") begin :nslp
-                if((i/V)<j )begin: jj
+    for(i=0;i< PV;i=i+1) begin :_PV
+        for(j=0;j<P; j=j+1) begin : P_
+            if(SELF_LOOP_EN == 0) begin 
+                if((i/V)<j )begin
                     assign ovc_allocated_all_gen[i][j-1] = cand_ovc_granted[j][i];
-                end else if((i/V)>j) begin: hh
+                end else if((i/V)>j) begin
                     assign ovc_allocated_all_gen[i][j] = cand_ovc_granted[j][i-V];
-                    
                 end
-            end else begin : slp
-                 assign ovc_allocated_all_gen[i][j] = cand_ovc_granted[j][i];            
+            end else begin
+                assign ovc_allocated_all_gen[i][j] = cand_ovc_granted[j][i];
             end
         end//j
-        
         assign ovc_allocated_all [i] = |ovc_allocated_all_gen[i];
-        
     end//i
-    
     endgenerate  
-    
 endmodule    
 
-
-
-
 /**************************************************************
-*
 *             comb_nonspec_v2
-*            
-* first arbiter has been shifted after first multiplexer            
-*
-*
+*       first arbiter has been shifted 
+*         after first multiplexer
 *********************************************************/
-
-    
-    
 module  comb_nonspec_v2_allocator #(
-    parameter V = 4,
-    parameter P = 5,
-    parameter FIRST_ARBITER_EXT_P_EN = 1,
-    parameter SWA_ARBITER_TYPE = "WRRA",
-    parameter MIN_PCK_SIZE=2, //minimum packet size in flits. The minimum value is 1.
-    parameter SELF_LOOP_EN= "NO"
-
+    parameter P = 5
 )(
     //VC allocator
-    //input    
-    dest_port_all,      // from input port
-    ovc_is_assigned_all,    // 
+    //input
+    dest_port_all, // from input port
+    ovc_is_assigned_all, 
     masked_ovc_request_all,
     pck_is_single_flit_all,
     
@@ -358,26 +237,21 @@ module  comb_nonspec_v2_allocator #(
     // global
     clk,
     reset
-
 );
-
-     
+    import pronoc_pkg::*;
     localparam
-        P_1 = (SELF_LOOP_EN == "NO") ?  P-1 :P,
+        P_1 = (SELF_LOOP_EN) ? P : P-1,
         PV = V * P,
         VV = V * V,
-        VP_1 = V * P_1,                
+        VP_1 = V * P_1,
         PP_1 = P_1 * P,
         PVV = PV * V,
-        PVP_1 = PV * P_1;    
+        PVP_1 = PV * P_1;
         
-   
-
-                    
     input   [PVV-1 : 0] masked_ovc_request_all;
     input   [PVP_1-1 : 0] dest_port_all;
     input   [PV-1 : 0] ovc_is_assigned_all;
-    input  [PV-1 : 0] pck_is_single_flit_all;
+    input   [PV-1 : 0] pck_is_single_flit_all;
     output  [PV-1 : 0] ovc_allocated_all;
     output  [PVV-1 : 0] granted_ovc_num_all;
     output  [PV-1 : 0] ivc_num_getting_ovc_grant;
@@ -391,26 +265,18 @@ module  comb_nonspec_v2_allocator #(
     input   clk,reset;
     input   [PV-1 : 0] vc_weight_is_consumed_all;
     input   [P-1 : 0] iport_weight_is_consumed_all;
-
+    output  [P-1 : 0] granted_dst_is_from_a_single_flit_pck;
     //internal wires switch allocator
     wire    [PV-1 : 0] first_arbiter_granted_ivc_all;
     wire    [PV-1 : 0] ivc_request_masked_all;
     wire    [P-1 : 0] any_cand_ovc_exsit;
-    output  [P-1 : 0] granted_dst_is_from_a_single_flit_pck;
-     
+    
     assign nonspec_first_arbiter_granted_ivc_all = first_arbiter_granted_ivc_all;
-     
+    
     //nonspeculative switch allocator    
     nonspec_sw_alloc #(
-        .V(V),
-        .P(P),
-        .FIRST_ARBITER_EXT_P_EN(FIRST_ARBITER_EXT_P_EN),
-        .SWA_ARBITER_TYPE(SWA_ARBITER_TYPE),
-        .MIN_PCK_SIZE(MIN_PCK_SIZE) 
-    )
-    nonspeculative_sw_allocator
-    (
-
+        .P(P)
+    ) nonspeculative_sw_allocator (
         .ivc_granted_all (ivc_num_getting_sw_grant),
         .ivc_request_masked_all (ivc_request_masked_all),
         .pck_is_single_flit_all(pck_is_single_flit_all),
@@ -425,141 +291,94 @@ module  comb_nonspec_v2_allocator #(
         .iport_weight_is_consumed_all(iport_weight_is_consumed_all),
         .clk  (clk),
         .reset (reset)
-    
     );
     
-    wire    [V-1 : 0] masked_non_assigned_request [PV-1 : 0] ;   
-    wire    [PV-1 : 0] masked_assigned_request;
-    wire    [PV-1 : 0] assigned_ovc_request_all;
-    wire    [VV-1 : 0] masked_non_assigned_request_per_port [P-1 : 0] ;
-    wire    [V-1 : 0] first_arbiter_granted_ivc_per_port[P-1 : 0] ;
-    wire    [V-1 : 0] candidate_ovc_local_num     [P-1 : 0] ;
-    wire    [V-1 : 0] first_arbiter_ovc_granted [P-1:0];
-    wire    [P_1-1 : 0] granted_dest_port_per_port  [P-1 : 0];
-    wire    [VP_1-1 : 0] cand_ovc_granted    [P-1 : 0];
-    wire    [P_1-1 : 0] ovc_allocated_all_gen   [PV-1 : 0];
-    wire    [V-1 : 0] granted_ovc_local_num_per_port [P-1 : 0];
-    wire    [V-1 : 0] ivc_local_num_getting_ovc_grant[P-1 : 0];
-    wire    [V : 0] summ_in   [PV-1 : 0];
+    wire  [V-1 : 0] masked_non_assigned_request [PV-1 : 0];
+    wire  [PV-1 : 0] masked_assigned_request;
+    wire  [PV-1 : 0] assigned_ovc_request_all;
+    wire  [V-1 : 0] masked_non_assigned_request_per_port [P-1 : 0][V-1 : 0];
+    wire  [V-1 : 0] first_arbiter_granted_ivc_per_port[P-1 : 0] ;
+    logic [V-1 : 0] candidate_ovc_local_num [P-1 : 0] ;
+    wire  [V-1 : 0] first_arbiter_ovc_granted [P-1:0];
+    wire  [P_1-1 : 0] granted_dest_port_per_port  [P-1 : 0];
+    wire  [VP_1-1 : 0] cand_ovc_granted [P-1 : 0];
+    wire  [P_1-1 : 0] ovc_allocated_all_gen [PV-1 : 0];
+    wire  [V-1 : 0] granted_ovc_local_num_per_port [P-1 : 0];
+    wire  [V-1 : 0] ivc_local_num_getting_ovc_grant[P-1 : 0];
+    wire  [V : 0] summ_in [PV-1 : 0];
     
-    
-    assign assigned_ovc_request_all        =   ivc_request_all &   ovc_is_assigned_all;
+    assign assigned_ovc_request_all =   ivc_request_all &   ovc_is_assigned_all;
+    //One-hot multiplex candidate OVC of first level switch allocator winner
+    always_comb begin
+        for(int m=0;m< P;m++) begin
+            candidate_ovc_local_num [m] = '0;
+            for (int k = 0; k < V; k++)
+                candidate_ovc_local_num [m] |= (first_arbiter_granted_ivc_per_port[m][k]) ?  masked_non_assigned_request_per_port[m][k] :  '0;
+        end
+    end
     
     genvar i,j;
     generate 
-   
     // IVC loop
-    for(i=0;i< PV;i=i+1) begin :total_vc_loop
-                
+    for(i=0;i< PV;i=i+1) begin : PV_
         // mask unavailable ovc from requests
-        assign masked_non_assigned_request  [i]  =   masked_ovc_request_all [(i+1)*V-1 : i*V ];
-        assign masked_assigned_request      [i]  =   assigned_ovc_not_full_all[i] & assigned_ovc_request_all[i]; 
-        
+        assign masked_non_assigned_request [i] = masked_ovc_request_all [(i+1)*V-1 : i*V ];
+        assign masked_assigned_request [i] = assigned_ovc_not_full_all[i] & assigned_ovc_request_all[i]; 
         // summing assigned and non-assigned VC requests
         assign summ_in[i]  ={masked_non_assigned_request   [i],masked_assigned_request     [i]};
         assign ivc_request_masked_all[i] = | summ_in[i];
-        
     end//for
     
-    
-    for(i=0;i< P;i=i+1) begin :port_loop3
-            for(j=0;j< V;j=j+1) begin :vc_loop
-                //merge masked_candidate_ovc in each port
-                assign masked_non_assigned_request_per_port[i][(j+1)*V-1 : j*V] =           masked_non_assigned_request [i*V+j];
-            end//for j
-            
-            assign first_arbiter_granted_ivc_per_port[i]=first_arbiter_granted_ivc_all[(i+1)*V-1 : i*V];
-            
-            assign granted_dest_port_per_port[i]=granted_dest_port_all[(i+1)*P_1-1 : i*P_1];
-            
-            
-        onehot_mux_1D #(
-            .W  (V),
-            .N  (V)
-        )
-        multiplexer2
-        (
-            .in          (masked_non_assigned_request_per_port   [i]),
-            .out         (candidate_ovc_local_num    [i]),
-            .sel         (first_arbiter_granted_ivc_per_port     [i])
-
-        );
+    for(i=0;i< P;i=i+1) begin : P_
+        for(j=0;j< V;j=j+1) begin : V_
+            //merge masked_candidate_ovc in each port
+            assign masked_non_assigned_request_per_port[i][j] = masked_non_assigned_request [i*V+j];
+            assign granted_ovc_num_all[(i*VV)+((j+1)*V)-1 : (i*VV)+(j*V)]=granted_ovc_local_num_per_port[i];
+        end//for j
+        assign first_arbiter_granted_ivc_per_port[i]=first_arbiter_granted_ivc_all[(i+1)*V-1 : i*V];
+        assign granted_dest_port_per_port[i]=granted_dest_port_all[(i+1)*P_1-1 : i*P_1];
         
         
         assign any_cand_ovc_exsit[i] = | candidate_ovc_local_num    [i];
-    
         //first level arbiter to candidate only one OVC 
         arbiter #(
             .ARBITER_WIDTH (V)
-        )
-        first_arbiter
-        (   
-            .clk (clk), 
-            .reset (reset), 
-            .request (candidate_ovc_local_num[i]), 
+        ) arbiter1 (
+            .clk (clk),
+            .reset (reset),
+            .request (candidate_ovc_local_num[i]),
             .grant (first_arbiter_ovc_granted[i]),
             .any_grant ( )
         );
-    
-        
-        //demultiplexer
-        one_hot_demux   #(
-            .IN_WIDTH (V),
-            .SEL_WIDTH (P_1)
-        )
-        demux1
-        (
-            .demux_sel (granted_dest_port_per_port [i]),//selectore
-            .demux_in (first_arbiter_ovc_granted[i]),//repeated
-            .demux_out (cand_ovc_granted [i])
-        );
-    
-          
-        assign granted_ovc_local_num_per_port   [i]=(any_ivc_sw_request_granted_all[i] )?  first_arbiter_ovc_granted[i] : {V{1'b0}};
-        assign ivc_local_num_getting_ovc_grant  [i]= (any_ivc_sw_request_granted_all[i] & any_cand_ovc_exsit[i])?   first_arbiter_granted_ivc_per_port [i] : {V{1'b0}};
-        assign ivc_num_getting_ovc_grant   [(i+1)*V-1 : i*V] = ivc_local_num_getting_ovc_grant[i];
-        for(j=0;j<V;    j=j+1)begin: assign_loop3
-            assign granted_ovc_num_all[(i*VV)+((j+1)*V)-1 : (i*VV)+(j*V)]=granted_ovc_local_num_per_port[i];
-        end//j
+        //Onehot demultiplexer 
+        for (j = 0; j < P_1; j++) begin : P_
+            assign cand_ovc_granted [i][j*V +: V] = (granted_dest_port_per_port [i][j]==1'b1) ? first_arbiter_ovc_granted[i] : {V{1'b0}};
+        end
+        assign granted_ovc_local_num_per_port [i]=(any_ivc_sw_request_granted_all[i] )?  first_arbiter_ovc_granted[i] : {V{1'b0}};
+        assign ivc_local_num_getting_ovc_grant [i]= (any_ivc_sw_request_granted_all[i] & any_cand_ovc_exsit[i]) ? first_arbiter_granted_ivc_per_port [i] : {V{1'b0}};
+        assign ivc_num_getting_ovc_grant [(i+1)*V-1 : i*V] = ivc_local_num_getting_ovc_grant[i];
     end//i
     
-    
-    for(i=0;i< PV;i=i+1) begin :total_vc_loop2
-        for(j=0;j<P;    j=j+1)begin: assign_loop2
-            if((i/V)<j )begin: jj
+    for(i=0;i< PV;i=i+1) begin : PV2_
+        for(j=0;j<P; j=j+1)begin : P_
+            if((i/V)<j )begin 
                 assign ovc_allocated_all_gen[i][j-1] = cand_ovc_granted[j][i];
-            end else if((i/V)>j) begin: hh
+            end else if((i/V)>j) begin 
                 assign ovc_allocated_all_gen[i][j] = cand_ovc_granted[j][i-V];
-                
             end
         end//j
-        
         assign ovc_allocated_all [i] = |ovc_allocated_all_gen[i];
-        
     end//i
-    
     endgenerate
     
-    
-endmodule   
-
+endmodule
 
 /********************************************
-*
 *    nonspeculative switch allocator
-*
 ******************************************/
-
 module nonspec_sw_alloc #(
-    parameter V = 4,
-    parameter P = 5,
-    parameter FIRST_ARBITER_EXT_P_EN = 1, 
-    parameter SWA_ARBITER_TYPE = "WRRA",
-    parameter MIN_PCK_SIZE=2, //minimum packet size in flits. The minimum value is 1.
-    parameter SELF_LOOP_EN="NO"
-
+    parameter P = 5
 )(
-
     ivc_granted_all,
     ivc_request_masked_all,
     pck_is_single_flit_all,
@@ -574,18 +393,14 @@ module nonspec_sw_alloc #(
     iport_weight_is_consumed_all,
     clk,
     reset
-    
 );
-
-   localparam
-        P_1 = (SELF_LOOP_EN== "NO") ? P-1 : P,
+    import pronoc_pkg::*;
+    localparam
+        P_1 = (SELF_LOOP_EN) ? P : P-1,
         PV = V * P,
-        VP_1 = V * P_1,                
         PP_1 = P_1 * P,
-        PVP_1 = PV * P_1,
-        PP = P*P;  
-                    
-
+        PVP_1 = PV * P_1;
+    
     output [PV-1 : 0] ivc_granted_all;
     output [P-1 : 0] granted_dst_is_from_a_single_flit_pck;
     input  [PV-1 : 0] ivc_request_masked_all;
@@ -601,198 +416,152 @@ module nonspec_sw_alloc #(
     input [P-1: 0] iport_weight_is_consumed_all;
     
     //separte input per port
-    wire [V-1 : 0] ivc_granted        [P-1 : 0];
-    wire [V-1 : 0] pck_is_single_flit [P-1 : 0];  
-    wire [VP_1-1 : 0] dest_port_ivc       [P-1 : 0];
-    wire [P_1-1 : 0] granted_dest_port  [P-1 : 0];
+    wire [V-1 : 0] ivc_granted [P-1 : 0];
+    wire [V-1 : 0] pck_is_single_flit [P-1 : 0];
+    wire [P_1-1 : 0] dest_port_ivc [P-1 : 0][V-1 : 0];
+    wire [P_1-1 : 0] granted_dest_port [P-1 : 0];
     wire [P_1-1 : 0] single_flit_granted_dst [P-1 : 0];
-    wire [PP-1 : 0] single_flit_granted_dst_all;
-    
+    logic [P-1 : 0] single_flit_granted_dst_all [P-1 : 0];
     // internal wires
-    wire    [V-1 : 0] ivc_masked     [P-1 : 0];//output of mask and             
-    wire    [V-1 : 0] first_arbiter_grant     [P-1 : 0];//output of first arbiter 
-    wire    [P-1 : 0] single_flit_pck_local_grant;           
-    wire    [P_1-1 : 0] dest_port      [P-1 : 0];//output of multiplexer
-    wire    [P_1-1 : 0] second_arbiter_request  [P-1 : 0]; 
-    wire    [P_1-1 : 0] second_arbiter_grant    [P-1 : 0]; 
-    wire    [P_1-1 : 0] second_arbiter_weight_consumed [P-1 : 0]; 
-    wire    [V-1 : 0] vc_weight_is_consumed [P-1 : 0]; 
-    wire    [P-1    :0] winner_weight_consumed;            
-     
+    wire [V-1 : 0] ivc_masked [P-1 : 0];//output of mask and  
+    wire [V-1 : 0] first_arbiter_grant [P-1 : 0];//output of first arbiter 
+    wire [P-1 : 0] single_flit_pck_local_grant;  
+    logic [P_1-1 : 0] dest_port  [P-1 : 0];//output of multiplexer
+    wire [P_1-1 : 0] second_arbiter_request [P-1 : 0]; 
+    wire [P_1-1 : 0] second_arbiter_grant [P-1 : 0]; 
+    wire [P_1-1 : 0] second_arbiter_weight_consumed [P-1 : 0]; 
+    wire [V-1 : 0] vc_weight_is_consumed [P-1 : 0]; 
+    wire [P-1 : 0] winner_weight_consumed;
+    
+    //onehot_mux to select destination port
+    always_comb begin
+        for (int m = 0; m < P; m++) begin
+            dest_port[m] = '0;
+            for (int k = 0; k < V; k++) begin
+                dest_port[m] |= (first_arbiter_grant[m][k]) ?  dest_port_ivc [m][k] :  '0;
+            end
+        end
+    end
+    
+    //add_sw_loc_one_hot 
+    always_comb begin 
+        for(int m=0;m< P;m++) begin 
+            if(MIN_PCK_SIZE == 1) begin 
+                if (SELF_LOOP_EN == 0) begin
+                    for(int k=0;k<P; k++) begin 
+                        if (k>m) single_flit_granted_dst_all[m][k] = single_flit_granted_dst[m][k-1];
+                        else if (k==m) single_flit_granted_dst_all[m][k] = 1'b0;
+                        else single_flit_granted_dst_all[m][k] = single_flit_granted_dst[m][k];
+                    end//for 
+                end else single_flit_granted_dst_all[m][P_1-1 : 0] = single_flit_granted_dst[m];
+            end else single_flit_granted_dst_all[m] = {P{1'b0}};
+        end//for
+    end//always
+    
     genvar i,j;
     generate
-    
-    for(i=0;i< P;i=i+1) begin :port_loop
+    for(i=0;i< P;i=i+1) begin : P_
         //assign in/out to the port based wires
         //output
         assign ivc_granted_all [(i+1)*V-1 : i*V] =   ivc_granted [i];
-        assign granted_dest_port_all    [(i+1)*P_1-1 : i*P_1]   =   granted_dest_port[i];
-        assign first_arbiter_granted_ivc_all[(i+1)*V-1 : i*V]=           first_arbiter_grant[i];
+        assign granted_dest_port_all [(i+1)*P_1-1 : i*P_1]  =   granted_dest_port[i];
+        assign first_arbiter_granted_ivc_all[(i+1)*V-1 : i*V] =  first_arbiter_grant[i];
         //input 
         assign ivc_masked[i]  = ivc_request_masked_all [(i+1)*V-1 : i*V];
-       
-        assign dest_port_ivc[i]  = dest_port_all [(i+1)*VP_1-1 : i*VP_1];
+        //assign dest_port_ivc[i]  = dest_port_all [(i+1)*VP_1-1 : i*VP_1];
         assign vc_weight_is_consumed[i]  =  vc_weight_is_consumed_all [(i+1)*V-1 : i*V];
-        
+        for (j=0;j<V;j=j+1) begin : V_
+            assign dest_port_ivc [i][j] = dest_port_all [(i*V+j)*P_1 +: P_1];
+        end //V_
         //first level arbiter
         swa_input_port_arbiter #(
-        	.ARBITER_WIDTH(V),
-        	.EXT_P_EN(FIRST_ARBITER_EXT_P_EN),
-        	.ARBITER_TYPE(SWA_ARBITER_TYPE)
-        )
-        input_arbiter
-        (
-        	.ext_pr_en_i(any_ivc_granted_all[i]),
-        	.request(ivc_masked [i]),
-        	.grant(first_arbiter_grant[i]),
-        	.any_grant( ),
-        	.clk(clk),
-        	.reset(reset),
-        	.vc_weight_is_consumed(vc_weight_is_consumed[i]),
-        	.winner_weight_consumed(winner_weight_consumed[i])
-        );
-        
-        
-  
-        //destination port multiplexer
-        onehot_mux_1D #(
-            .W (P_1),
-            .N (V)
-        )
-        multiplexer
-        (
-            .in (dest_port_ivc  [i]),
-            .out (dest_port      [i]),
-            .sel(first_arbiter_grant[i])
-    
+            .ARBITER_WIDTH(V),
+            .EXT_P_EN(FIRST_ARBITER_EXT_P_EN)
+        ) input_arbiter (
+            .ext_pr_en_i(any_ivc_granted_all[i]),
+            .request(ivc_masked [i]),
+            .grant(first_arbiter_grant[i]),
+            .any_grant( ),
+            .clk(clk),
+            .reset(reset),
+            .vc_weight_is_consumed(vc_weight_is_consumed[i]),
+            .winner_weight_consumed(winner_weight_consumed[i])
         );
-        if(MIN_PCK_SIZE == 1) begin :single_flit_supported             
+        if(MIN_PCK_SIZE == 1) begin
             //single_flit req multiplexer
             assign pck_is_single_flit[i] = pck_is_single_flit_all [(i+1)*V-1 : i*V];
-            onehot_mux_1D #(
-                .W (1),
-                .N (V)
-            )
-            multiplexer2
-            (
-                .in (pck_is_single_flit  [i]),
-                .out (single_flit_pck_local_grant[i]),
-                .sel (first_arbiter_grant[i])
-        
-            );   
-            
-            assign  single_flit_granted_dst[i] = (single_flit_pck_local_grant[i])?  granted_dest_port[i] : {P_1{1'b0}};
-    
-            if (SELF_LOOP_EN == "NO") begin :nslp
-                add_sw_loc_one_hot #(
-                    .P(P),
-                    .SW_LOC(i)
-                )
-                add_sw_loc
-                (
-                    .destport_in(single_flit_granted_dst[i]),
-                    .destport_out(single_flit_granted_dst_all[(i+1)*P-1 : i*P])
-                );
-            end else begin :slp
-                assign single_flit_granted_dst_all[(i+1)*P-1 : i*P] = single_flit_granted_dst[i];
-            end
-            
-        end else begin : single_flit_notsupported 
-            assign single_flit_pck_local_grant[i] = 1'bx;
-            assign single_flit_granted_dst[i] = {P_1{1'bx}};
-            assign single_flit_granted_dst_all[(i+1)*P-1 : i*P]={P{1'b0}};
+            //one hot mux to select single flit packet
+            assign single_flit_pck_local_grant[i] = |(pck_is_single_flit[i] & first_arbiter_grant[i]);
+            assign single_flit_granted_dst[i] = (single_flit_pck_local_grant[i])?  granted_dest_port[i] : {P_1{1'b0}};
+        end else begin 
+            assign single_flit_pck_local_grant[i] = 1'b0;
+            assign single_flit_granted_dst[i] = {P_1{1'b0}};
         end
-    //second arbiter input/output generate
-
-
-    for(j=0;j<P;    j=j+1)begin: assign_loop
-         if (SELF_LOOP_EN == "NO") begin :nslp
-            if(i<j)begin: jj
-                assign second_arbiter_request[i][j-1]  = dest_port[j][i];
-                //assign second_arbiter_weight_consumed[i][j-1]  =winner_weight_consumed[j] ;
-                assign second_arbiter_weight_consumed[i][j-1]  =iport_weight_is_consumed_all[j] ;
-                assign granted_dest_port[j][i] = second_arbiter_grant  [i][j-1] ;
-                
-            end else if(i>j)begin: hh
-                assign second_arbiter_request[i][j] = dest_port [j][i-1] ;
-                //assign second_arbiter_weight_consumed[i][j]  =winner_weight_consumed[j];
-                assign second_arbiter_weight_consumed[i][j]  =iport_weight_is_consumed_all[j];
-                assign granted_dest_port[j][i-1] = second_arbiter_grant  [i][j] ;
+        //second arbiter input/output generate
+        for(j=0;j<P; j=j+1) begin : P_
+            if (SELF_LOOP_EN == 0) begin 
+                if(i<j) begin
+                    assign second_arbiter_request[i][j-1]  = dest_port[j][i];
+                    //assign second_arbiter_weight_consumed[i][j-1]  =winner_weight_consumed[j] ;
+                    assign second_arbiter_weight_consumed[i][j-1]  =iport_weight_is_consumed_all[j] ;
+                    assign granted_dest_port[j][i] = second_arbiter_grant  [i][j-1] ;
+                end else if(i>j)begin
+                    assign second_arbiter_request[i][j] = dest_port [j][i-1] ;
+                    //assign second_arbiter_weight_consumed[i][j]  =winner_weight_consumed[j];
+                    assign second_arbiter_weight_consumed[i][j]  =iport_weight_is_consumed_all[j];
+                    assign granted_dest_port[j][i-1] = second_arbiter_grant  [i][j] ;
+                end
+                //if(i==j) wires are left disconnected 
+            end else begin 
+                assign second_arbiter_request[i][j]  = dest_port[j][i];
+                assign second_arbiter_weight_consumed[i][j]  =iport_weight_is_consumed_all[j] ;
+                assign granted_dest_port[j][i] = second_arbiter_grant  [i][j] ;
             end
-            //if(i==j) wires are left disconnected 
-        end else begin :slp
-            assign second_arbiter_request[i][j]  = dest_port[j][i];
-            assign second_arbiter_weight_consumed[i][j]  =iport_weight_is_consumed_all[j] ;
-            assign granted_dest_port[j][i] = second_arbiter_grant  [i][j] ;        
-        end
-    end
-    
-        
+        end //P_
         //second level arbiter 
         swa_output_port_arbiter #(
-            .ARBITER_WIDTH(P_1),
-            .ARBITER_TYPE(SWA_ARBITER_TYPE) // RRA, WRRA
-        )
-        output_arbiter        
-        (
-           .weight_consumed(second_arbiter_weight_consumed[i]),  // only used for WRRA
-           .clk(clk), 
-           .reset(reset), 
-           .request(second_arbiter_request [i]), 
-           .grant(second_arbiter_grant [i]),
-           .any_grant(any_ovc_granted_all [i])  
+            .ARBITER_WIDTH(P_1)
+        ) output_arbiter (
+            .weight_consumed(second_arbiter_weight_consumed[i]),  // only used for WRRA
+            .clk(clk), 
+            .reset(reset), 
+            .request(second_arbiter_request [i]),
+            .grant(second_arbiter_grant [i]),
+            .any_grant(any_ovc_granted_all [i])
         );
-            
-        
         //any ivc 
         assign  any_ivc_granted_all[i] = | granted_dest_port[i];
         assign  ivc_granted[i] =  (any_ivc_granted_all[i]) ? first_arbiter_grant[i] : {V{1'b0}};
-
-       
-    end//for
+    end//for P_
     endgenerate 
-        
-
-	  custom_or #(
-            .IN_NUM(P),
-            .OUT_WIDTH(P)
-         )
-         or_dst
-         (
-            .or_in(single_flit_granted_dst_all),
-            .or_out(granted_dst_is_from_a_single_flit_pck)
-        );
-
+    
+    reduction_or #(
+        .W(P),
+        .N(P)
+    ) or_dst (
+        .D_in(single_flit_granted_dst_all),
+        .Q_out(granted_dst_is_from_a_single_flit_pck)
+    );
 endmodule
 
 
-
 /*******************
 *    swa_input_port_arbiter
-*
 ********************/
-
-
 module swa_input_port_arbiter #(
     parameter ARBITER_WIDTH =4,
-    parameter EXT_P_EN = 1,
-    parameter ARBITER_TYPE = "WRRA"// RRA, WRRA
-   
+    parameter EXT_P_EN = 1
 )(
-   ext_pr_en_i,  // it is used only if the EXT_P_EN is 1
-   clk, 
-   reset, 
-   request, 
-   grant,
-   any_grant,
-   vc_weight_is_consumed, // only for WRRA
-   winner_weight_consumed // only for WRRA
+    ext_pr_en_i,  // it is used only if the EXT_P_EN is 1
+    clk, 
+    reset, 
+    request, 
+    grant,
+    any_grant,
+    vc_weight_is_consumed, // only for WRRA
+    winner_weight_consumed // only for WRRA
 );
-
-
-
-   
-
+    import pronoc_pkg::*;
     input ext_pr_en_i;
     input [ARBITER_WIDTH-1 : 0] request;
     output[ARBITER_WIDTH-1 : 0] grant;
@@ -801,34 +570,16 @@ module swa_input_port_arbiter #(
     input  reset;
     input  [ARBITER_WIDTH-1 : 0] vc_weight_is_consumed;
     output winner_weight_consumed;
-
-
-    generate 
-    /* verilator lint_off WIDTH */
-    if(ARBITER_TYPE != "RRA") begin : wrra_m
-    /* verilator lint_on WIDTH */
-        
-        // one hot mux    
-        onehot_mux_1D #(
-            .W(1),
-            .N(ARBITER_WIDTH)            
-        )
-        mux
-        (
-            .in(vc_weight_is_consumed),
-            .out(winner_weight_consumed),
-            .sel(grant)
-        );
     
+    generate 
+    if(IS_WRRA) begin: wrra_
+        // one hot mux
+        assign  winner_weight_consumed = |(vc_weight_is_consumed & grant);
         wire priority_en = (EXT_P_EN == 1) ? ext_pr_en_i & winner_weight_consumed : winner_weight_consumed;
-
         //round robin arbiter with external priority
-    
         arbiter_priority_en #(
             .ARBITER_WIDTH(ARBITER_WIDTH)
-        )
-        rra
-        (
+        ) rra (
             .request(request),
             .grant(grant),
             .any_grant(any_grant),
@@ -836,151 +587,98 @@ module swa_input_port_arbiter #(
             .reset(reset),
             .priority_en(priority_en)
         );
-    
     end else begin : rra_m //RRA
-        assign winner_weight_consumed = 1'bx;
-        if(EXT_P_EN==1) begin : arbiter_ext_en
-            
+        assign winner_weight_consumed = 1'b0;
+        if(EXT_P_EN==1) begin 
             arbiter_priority_en #(
                 .ARBITER_WIDTH (ARBITER_WIDTH)
-            )
-            arb
-            (   
+            ) arb (
                 .clk (clk), 
                 .reset (reset), 
                 .request (request), 
                 .grant (grant),
                 .any_grant (any_grant ),
-                .priority_en (ext_pr_en_i)        
+                .priority_en (ext_pr_en_i)
             );
- 
-        end else  begin: first_lvl_arbiter_internal_en
-        
+        end else  begin 
             arbiter #(
                 .ARBITER_WIDTH (ARBITER_WIDTH)
-            )
-            arb
-            (   
+            ) arb(
                 .clk (clk), 
                 .reset (reset), 
                 .request (request), 
                 .grant (grant),
                 .any_grant (any_grant )
             );
-            
         end//else
-
     end
     endgenerate
-    
 endmodule
 
-
-
-
 /*******************
 *    swa_output_port_arbiter
-*
 ********************/
-
-
 module swa_output_port_arbiter #(
-    parameter ARBITER_WIDTH =4,
-    parameter ARBITER_TYPE = "WRRA" // RRA, WRRA
-       
-
+    parameter ARBITER_WIDTH =4
 )(
-   weight_consumed,  // only used for WRRA
-   clk, 
-   reset, 
-   request, 
-   grant,
-   any_grant  
+    weight_consumed,  // only used for WRRA
+    clk,
+    reset,
+    request,
+    grant,
+    any_grant
 );
-
-
-  
+    import pronoc_pkg::*;
     input     [ARBITER_WIDTH-1  :    0]    request;
     output    [ARBITER_WIDTH-1  :    0]    grant;
     output                                 any_grant;
     input                                  clk;
     input                                  reset;
     input    [ARBITER_WIDTH-1  :    0]     weight_consumed;
-
-
-
- generate 
-    /* verilator lint_off WIDTH */
-    if(ARBITER_TYPE == "WRRA") begin : wrra_mine
-    /* verilator lint_on WIDTH */
+    
+    generate 
+    if(IS_WRRA) begin : wrra
         // second level wrra priority is only changed if the granted request weight is consumed 
         wire pr_en;
-        
-        onehot_mux_1D #(
-            .W(1),
-            .N(ARBITER_WIDTH)
-        )
-        multiplexer
-        (
-            .in(weight_consumed),
-            .out(pr_en),
-            .sel(grant)
-    
-        );
-        
-    
+        //one hot mux
+        assign pr_en = |(weight_consumed & grant);
         arbiter_priority_en #(
             .ARBITER_WIDTH (ARBITER_WIDTH)
-        )
-        arb
-        (   
+        ) arb  (   
             .clk (clk), 
             .reset (reset), 
             .request (request), 
             .grant (grant),
             .any_grant (any_grant ),
-            .priority_en (pr_en)        
+            .priority_en (pr_en)
         );
-    
-    
-     /* verilator lint_off WIDTH */
-    end else if(ARBITER_TYPE == "WRRA_CLASSIC") begin : wrra_classic 
-    /* verilator lint_on WIDTH */
-        // use classic WRRA. only for compasrion with propsoed wrra 
+    end else if(IS_RRA) begin : rra
         
-        wire  [ARBITER_WIDTH-1  :    0] masked_req=       request & ~weight_consumed;
-        wire sel = |masked_req;
-        wire  [ARBITER_WIDTH-1  :    0] mux_req = (sel==1'b1)? masked_req : request;
-       
         arbiter #(
             .ARBITER_WIDTH  (ARBITER_WIDTH )
-        )
-        arb
-        (   
+        ) arb  (   
             .clk (clk), 
             .reset (reset), 
-            .request (mux_req), 
+            .request (request), 
             .grant (grant),
             .any_grant (any_grant )
         );
-    
-    
-    
-    end else begin : rra_m   
-
+        
+    end else  begin : wrra_classic  //(ARBITER_TYPE == "WRRA_CLASSIC")   
+        // use classic WRRA. only for compasrion with propsoed wrra 
+        wire  [ARBITER_WIDTH-1  :    0] masked_req =  request & ~weight_consumed;
+        wire sel = |masked_req;
+        wire  [ARBITER_WIDTH-1  :    0] mux_req = (sel==1'b1)? masked_req : request;
+        
         arbiter #(
             .ARBITER_WIDTH  (ARBITER_WIDTH )
-        )
-        arb
-        (   
+        ) arb  (
             .clk (clk), 
             .reset (reset), 
-            .request (request), 
+            .request (mux_req), 
             .grant (grant),
             .any_grant (any_grant )
         );
-        
-   end
-   endgenerate
+    end
+    endgenerate
 endmodule
-
diff --git a/mpsoc/rtl/src_noc/comb_spec2.v b/mpsoc/rtl/src_noc/comb_spec2.sv
similarity index 53%
rename from mpsoc/rtl/src_noc/comb_spec2.v
rename to mpsoc/rtl/src_noc/comb_spec2.sv
index 07d841a..341aabd 100755
--- a/mpsoc/rtl/src_noc/comb_spec2.v
+++ b/mpsoc/rtl/src_noc/comb_spec2.sv
@@ -1,42 +1,36 @@
-`timescale      1ns/1ps
+`include "pronoc_def.v"
 
 /**********************************************************************
-**	File: comb_spec2.v
+**    File: comb_spec2.v
 **
-**	Copyright (C) 2014-2017  Alireza Monemi
+**    Copyright (C) 2014-2017  Alireza Monemi
 **
-**	This file is part of ProNoC
+**    This file is part of ProNoC
 **
-**	ProNoC ( stands for Prototype Network-on-chip)  is free software:
-**	you can redistribute it and/or modify it under the terms of the GNU
-**	Lesser General Public License as published by the Free Software Foundation,
-**	either version 2 of the License, or (at your option) any later version.
+**    ProNoC ( stands for Prototype Network-on-chip)  is free software:
+**    you can redistribute it and/or modify it under the terms of the GNU
+**    Lesser General Public License as published by the Free Software Foundation,
+**    either version 2 of the License, or (at your option) any later version.
 **
-** 	ProNoC is distributed in the hope that it will be useful, but WITHOUT
-** 	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
-** 	or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
-** 	Public License for more details.
+**     ProNoC is distributed in the hope that it will be useful, but WITHOUT
+**     ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+**     or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
+**     Public License for more details.
 **
-** 	You should have received a copy of the GNU Lesser General Public
-** 	License along with ProNoC. If not, see <http:**www.gnu.org/licenses/>.
+**     You should have received a copy of the GNU Lesser General Public
+**     License along with ProNoC. If not, see <http:**www.gnu.org/licenses/>.
 **
 **
-**	Description:
-**	VC allocator combined with speculative switch allocator
-**	where the free VC availability is checked in the middle
-**	of switch allocator after first level of arbitration
-**	(comb-spec2).
+**    Description:
+**    VC allocator combined with speculative switch allocator
+**    where the free VC availability is checked in the middle
+**    of switch allocator after first level of arbitration
+**    (comb-spec2).
 **
-**************************************************************/
-
+*************************************************************/
 
 module  comb_spec2_allocator #(
-    parameter V = 4,// Virtual chanel num per port
-    parameter P = 5,
-    parameter DEBUG_EN = 1,
-    parameter SWA_ARBITER_TYPE = "WRRA",
-    parameter MIN_PCK_SIZE=2, //minimum packet size in flits. The minimum value is 1.
-    parameter SELF_LOOP_EN="NO"
+    parameter P = 5 //number of ports
 )(
     dest_port_all,
     masked_ovc_request_all,
@@ -47,7 +41,6 @@ module  comb_spec2_allocator #(
     granted_ovc_num_all,
     ivc_num_getting_ovc_grant,
     ivc_num_getting_sw_grant,
-    spec_first_arbiter_granted_ivc_all,
     nonspec_first_arbiter_granted_ivc_all,
     granted_dest_port_all,
     nonspec_granted_dest_port_all,
@@ -58,56 +51,43 @@ module  comb_spec2_allocator #(
     granted_dst_is_from_a_single_flit_pck,
     clk,reset
 );
-
+    import pronoc_pkg::*;
     localparam
         PV = V * P,
         VV = V * V,
         PVV = PV * V,
-        P_1 = (SELF_LOOP_EN == "NO")?  P-1 : P,
+        P_1 = (SELF_LOOP_EN )?  P : P-1,
         VP_1 = V * P_1,
         PP_1 = P_1 * P,
         PVP_1 = PV * P_1;
-
     input  [PVP_1-1 : 0] dest_port_all;
-    input  [PVV-1 :  0] masked_ovc_request_all;
+    input  [PVV-1 : 0] masked_ovc_request_all;
     input  [PV-1 : 0] ovc_is_assigned_all;
     input  [PV-1 : 0] ivc_request_all;
     input  [PV-1 : 0] assigned_ovc_not_full_all;
     input  [PV-1 : 0] vc_weight_is_consumed_all;
     input  [P-1 : 0] iport_weight_is_consumed_all;
-
     output [PV-1 : 0] ovc_allocated_all;
     output [PVV-1 : 0] granted_ovc_num_all;
     output [PV-1 : 0] ivc_num_getting_ovc_grant;
     output [PV-1 : 0] ivc_num_getting_sw_grant;
     output [PV-1 : 0] nonspec_first_arbiter_granted_ivc_all;
-    output [PV-1 : 0] spec_first_arbiter_granted_ivc_all;
-
     output [PP_1-1 : 0] granted_dest_port_all;
     output [PP_1-1 : 0] nonspec_granted_dest_port_all;
     output [P-1 : 0] any_ivc_sw_request_granted_all;
-
     input  [PV-1 : 0] pck_is_single_flit_all;
     output [P-1 : 0] granted_dst_is_from_a_single_flit_pck;
     input  clk,reset;
-
     //internal wires switch allocator
-
     wire [PV-1 : 0] spec_first_arbiter_granted_ivc_all;
     wire [PP_1-1 : 0] spec_granted_dest_port_all;
     wire [P-1 : 0] spec_any_ivc_grant_valid;
     wire [PV-1 : 0]  valid_speculation;
-
+    
     //speculative switch allocator
     spec_sw_alloc2 #(
-        .V (V),
-        .P (P),
-        .DEBUG_EN (DEBUG_EN),
-        .SWA_ARBITER_TYPE (SWA_ARBITER_TYPE),
-        .MIN_PCK_SIZE(MIN_PCK_SIZE)
-    )
-    speculative_sw_allocator
-    (
+        .P (P)
+    ) speculative_sw_allocator (
         .ivc_granted_all(ivc_num_getting_sw_grant),
         .ivc_request_all(ivc_request_all),
         .ovc_is_assigned_all(ovc_is_assigned_all),
@@ -128,7 +108,7 @@ module  comb_spec2_allocator #(
         .clk(clk),
         .reset(reset)
     );
-
+    
     wire  [V-1 : 0] masked_non_assigned_request [PV-1 : 0];
     wire  [VV-1 : 0] masked_candidate_ovc_per_port [P-1 : 0];
     wire  [V-1 : 0] spec_first_arbiter_granted_ivc_per_port[P-1 : 0];
@@ -139,126 +119,84 @@ module  comb_spec2_allocator #(
     wire  [P_1-1 : 0] ovc_allocated_all_gen [PV-1 : 0];
     wire  [V-1 : 0] granted_ovc_local_num_per_port [P-1 : 0];
     wire  [V-1 : 0] ivc_local_num_getting_ovc_grant [P-1 : 0];
-
+    
     genvar i,j;
     generate
-
-    // IVC loop
-    for(i=0;i< PV;i=i+1) begin :total_vc_loop
-
-        // mask unavailable ovc from requests
-        assign masked_non_assigned_request    [i]     =   masked_ovc_request_all [(i+1)*V-1 :  i*V ];
-        assign valid_speculation                [i]        = | masked_non_assigned_request    [i];
-
-    end//for
-
-    for(i=0;i< P;i=i+1) begin :port_loop3
-            for(j=0;j< V;j=j+1) begin :vc_loop
-                //merge masked_candidate_ovc in each port
-                assign masked_candidate_ovc_per_port[i][(j+1)*V-1 : j*V]    =    masked_non_assigned_request    [i*V+j];
-
-            end//for j
-
+    for(i=0;i< P;i=i+1) begin : P_
+        for(j=0;j< V;j=j+1) begin : V_
+            //merge masked_candidate_ovc in each port
+            assign masked_candidate_ovc_per_port[i][(j+1)*V-1 : j*V] = masked_non_assigned_request    [i*V+j];
+            assign granted_ovc_num_all[(i*VV)+((j+1)*V)-1 : (i*VV)+(j*V)]=granted_ovc_local_num_per_port[i];
+        end//for j
         assign spec_first_arbiter_granted_ivc_per_port[i]    =spec_first_arbiter_granted_ivc_all[(i+1)*V-1 : i*V];
         assign spec_granted_dest_port_per_port[i]                =spec_granted_dest_port_all[(i+1)*P_1-1 : i*P_1];
         // multiplex candidate OVC of first level switch allocatore winner
-
         one_hot_mux #(
             .IN_WIDTH (VV),
             .SEL_WIDTH (V)
-        )
-        multiplexer2
-        (
+        ) multiplexer2(
             .mux_in(masked_candidate_ovc_per_port [i]),
             .mux_out(spec_first_arbiter_ovc_request [i]),
             .sel(spec_first_arbiter_granted_ivc_per_port [i])
-        );
-
+        );        
         //first level arbiter to candidate only one OVC
         arbiter #(
             .ARBITER_WIDTH (V)
-        )
-        second_arbiter
-        (
+        )second_arbiter (
             .clk(clk),
             .reset(reset),
             .request(spec_first_arbiter_ovc_request[i]),
             .grant(spec_first_arbiter_ovc_granted[i]),
             .any_grant( )
         );
-
-        //demultiplexer
-        one_hot_demux #(
-            .IN_WIDTH(V),
-            .SEL_WIDTH(P_1)
-        )
-        demux1
-        (
-            .demux_sel(spec_granted_dest_port_per_port [i]),//selectore
-            .demux_in(spec_first_arbiter_ovc_granted[i]),//repeated
-            .demux_out(cand_ovc_granted[i])
-        );
-
-        //assign cand_ovc_granted [i]    =             (spec_any_ivc_grant_valid[i])?  cand_ovc_demuxed[i]: {VP_1{1'b0}};
-        assign granted_ovc_local_num_per_port[i]=(spec_any_ivc_grant_valid[i])?  spec_first_arbiter_ovc_granted[i] : {V{1'b0}};
-        assign ivc_local_num_getting_ovc_grant[i]= (spec_any_ivc_grant_valid[i])? spec_first_arbiter_granted_ivc_per_port [i] : {V{1'b0}};
+        //Onehot demultiplexer
+        for (j = 0; j < P_1; j++) begin : P_
+            assign cand_ovc_granted [i][j*V +: V] = (spec_granted_dest_port_per_port [i][j]==1'b1) ? spec_first_arbiter_ovc_granted[i] : {V{1'b0}};
+        end
+        //assign cand_ovc_granted [i] = (spec_any_ivc_grant_valid[i])?  cand_ovc_demuxed[i]: {VP_1{1'b0}};
+        assign granted_ovc_local_num_per_port[i] = (spec_any_ivc_grant_valid[i]) ?  spec_first_arbiter_ovc_granted[i] : {V{1'b0}};
+        assign ivc_local_num_getting_ovc_grant[i] = (spec_any_ivc_grant_valid[i]) ? spec_first_arbiter_granted_ivc_per_port [i] : {V{1'b0}};
         assign ivc_num_getting_ovc_grant[(i+1)*V-1 : i*V] = ivc_local_num_getting_ovc_grant[i];
-        for(j=0;j<V;    j=j+1)begin: assign_loop3
-            assign granted_ovc_num_all[(i*VV)+((j+1)*V)-1 : (i*VV)+(j*V)]=granted_ovc_local_num_per_port[i];
-        end//j
     end//i
-
-    //wire     [PORT_SEL-1 : 0]    ovc_allocated_all_gen    [PV-1 : 0];
-    //wire    [VP_1-1 : 0] cand_ovc_granted    [P-1 : 0];
-    wire [PV-1 : 0]    result;
-    for(i=0;i< PV;i=i+1) begin :total_vc_loop2
-        for(j=0;j<P;    j=j+1)begin: assign_loop2
-            if((i/V)<j )begin: jj
+    //wire [PORT_SEL-1 : 0]    ovc_allocated_all_gen    [PV-1 : 0];
+    //wire [VP_1-1 : 0] cand_ovc_granted    [P-1 : 0];
+    wire [PV-1 : 0] result;
+    for(i=0;i< PV;i=i+1) begin : PV_
+         // mask unavailable ovc from requests
+        assign masked_non_assigned_request [i] =  masked_ovc_request_all [(i+1)*V-1 : i*V ];
+        assign valid_speculation [i] = | masked_non_assigned_request [i];
+        for(j=0;j<P;    j=j+1) begin: P_
+            if((i/V)<j )begin
                 assign ovc_allocated_all_gen[i][j-1]    = cand_ovc_granted[j][i];
-            end else if((i/V)>j) begin: hh
+            end else if((i/V)>j) begin
                 assign ovc_allocated_all_gen[i][j]    = cand_ovc_granted[j][i-V];
             end
         end//j
-
         assign ovc_allocated_all [i] = |ovc_allocated_all_gen[i];
-
-        //synthesis translate_off
-        //synopsys  translate_off
-        if(DEBUG_EN)begin :dbg
+        
+        `ifdef SIMULATION
+        if(DEBUG_EN)begin : dbg
             is_onehot0 #(
                 .IN_WIDTH(P_1)
-            )
-            check_ovc_allocated
-            (
-                .in        (ovc_allocated_all_gen[i]),
-                .result    (result[i])
+            ) check_ovc_allocated (
+                .D_in(ovc_allocated_all_gen[i]),
+                .result (result[i])
             );
-
             always @(posedge clk ) begin
                 if(~result[i]) $display("%t,Error: An OVC is assigned to more than one IVC %m",$time);
             end
         end //DEBUG
-        //synopsys  translate_on
-        //synthesis translate_on
-
+        `endif//SIMULATION
     end//i
-
     endgenerate
-
 endmodule
 
 /***************************
 speculative switch allocator for
         comb_spec2
 ****************************/
-
-
 module spec_sw_alloc2 #(
-    parameter V = 4,
-    parameter P = 5,
-    parameter DEBUG_EN = 1,
-    parameter SWA_ARBITER_TYPE="RRA",
-    parameter MIN_PCK_SIZE=2 //minimum packet size in flits. The minimum value is 1.
+    parameter P = 5
 )(
     ivc_granted_all,
     ivc_request_all,
@@ -280,58 +218,49 @@ module spec_sw_alloc2 #(
     clk,
     reset
 );
-
-    localparam  
+    import pronoc_pkg::*;
+    localparam
         P_1 = P-1,//assumed that no port request for itself!
         PV  = V * P,
         VP_1= V * P_1,
         PVP_1 = P * VP_1,
         PP_1 = P_1 * P;
-
-    output [PV-1 :  0]  ivc_granted_all;
-    input  [PV-1 :  0] ivc_request_all;
-    input  [PV-1 :  0] ovc_is_assigned_all;
-    input  [PV-1 :  0] assigned_ovc_not_full_all;
+    output [PV-1 : 0]  ivc_granted_all;
+    input  [PV-1 : 0] ivc_request_all;
+    input  [PV-1 : 0] ovc_is_assigned_all;
+    input  [PV-1 : 0] assigned_ovc_not_full_all;
     input  [PVP_1-1 : 0]  dest_port_all;
-    output [PP_1-1 :  0]  granted_dest_port_all;
-    output [PP_1-1 :  0]  nonspec_granted_dest_port_all;
-    input  [PV-1 :  0]  valid_speculation;
-    output [PV-1 :  0]  spec_first_arbiter_granted_ivc_all;
-    output [PV-1 :  0]  nonspec_first_arbiter_granted_ivc_all;
+    output [PP_1-1 : 0]  granted_dest_port_all;
+    output [PP_1-1 : 0]  nonspec_granted_dest_port_all;
+    input  [PV-1 : 0]  valid_speculation;
+    output [PV-1 : 0]  spec_first_arbiter_granted_ivc_all;
+    output [PV-1 : 0]  nonspec_first_arbiter_granted_ivc_all;
     output [PP_1-1 : 0]  spec_granted_dest_port_all;
-    output [P-1 :  0]  spec_any_ivc_grant_valid;
-    output [P-1 :  0]  any_ivc_sw_request_granted_all;
+    output [P-1 : 0]  spec_any_ivc_grant_valid;
+    output [P-1 : 0]  any_ivc_sw_request_granted_all;
     input  [PV-1 : 0] vc_weight_is_consumed_all;
     input  [P-1 : 0] iport_weight_is_consumed_all;
     input  [PV-1 : 0] pck_is_single_flit_all;
-    output [P-1 : 0] granted_dst_is_from_a_single_flit_pck;
-
+    output [P-1 : 0] granted_dst_is_from_a_single_flit_pck;    
     input clk,reset;
-
     //internal wire
-    wire  [PV-1 :  0]  spec_ivc_granted_all,nonspec_ivc_granted_all;
-    wire  [PV-1 :  0] spec_ivc_request_all,nonspec_ivc_request_all;
-    wire  [PV-1 :  0] spec_assigned_ovc_not_full_all,nonspec_assigned_ovc_not_full_all;
-    wire  [PVP_1-1 :  0]  spec_dest_port_all,nonspec_dest_port_all;
-    wire  [PP_1-1 :  0]  spec_granted_dest_port_all,spec_granted_dest_port_all_accepted;
-    wire  [P-1 :  0]  nonspec_inport_granted_all,nonspec_outport_granted_all;
-    wire  [PP_1-1 :  0]  spec_granted_dest_port_all_pre;
-
-    wire  [P_1-1 :  0] nonspec_portsel_granted [P-1 :  0];
-    wire  [PP_1-1 :  0] spec_request_acceptable;
-    wire  [P_1-1 :  0] spec_request_accepted [P-1 :  0];
-    wire  [P-1 :  0] any_spec_request_accepted;
-    wire  [PV-1 :  0] spec_ivc_granted_all_accepted;
-    wire  [P-1 :  0] spec_any_ivc_grant,nonspec_any_ivc_grant;
-
+    wire  [PV-1 : 0]  spec_ivc_granted_all,nonspec_ivc_granted_all;
+    wire  [PV-1 : 0] spec_ivc_request_all,nonspec_ivc_request_all;
+    wire  [PV-1 : 0] spec_assigned_ovc_not_full_all,nonspec_assigned_ovc_not_full_all;
+    wire  [PVP_1-1 : 0]  spec_dest_port_all,nonspec_dest_port_all;
+    wire  [PP_1-1 : 0]  spec_granted_dest_port_all,spec_granted_dest_port_all_accepted;
+    wire  [P-1 : 0]  nonspec_inport_granted_all,nonspec_outport_granted_all;
+    wire  [PP_1-1 : 0]  spec_granted_dest_port_all_pre;
+    wire  [P_1-1 : 0] nonspec_portsel_granted [P-1 : 0];
+    wire  [PP_1-1 : 0] spec_request_acceptable;
+    wire  [P_1-1 : 0] spec_request_accepted [P-1 : 0];
+    wire  [P-1 : 0] any_spec_request_accepted;
+    wire  [PV-1 : 0] spec_ivc_granted_all_accepted;
+    wire  [P-1 : 0] spec_any_ivc_grant,nonspec_any_ivc_grant;
+    
     spec_sw_alloc_sub2#(
-        .V(V),
-        .P(P),
-        .SWA_ARBITER_TYPE(SWA_ARBITER_TYPE),
-        .MIN_PCK_SIZE(MIN_PCK_SIZE)
-    )
-    speculative_alloc
-    (
+        .P(P)
+    ) speculative_alloc (
         .valid_speculation (valid_speculation),
         .ivc_granted_all (spec_ivc_granted_all),
         .ivc_request_all (spec_ivc_request_all),
@@ -350,16 +279,10 @@ module spec_sw_alloc2 #(
         .clk (clk),
         .reset (reset)
     );
-
+    
     sw_alloc_sub2#(
-        .V (V),
-        .P (P),
-        .SWA_ARBITER_TYPE(SWA_ARBITER_TYPE),
-        .MIN_PCK_SIZE(MIN_PCK_SIZE)
-    )
-    nonspeculative_alloc
-    (
-
+        .P (P)
+    ) nonspeculative_alloc (
         .ivc_granted_all (nonspec_ivc_granted_all),
         .ivc_request_all (nonspec_ivc_request_all),
         .assigned_ovc_not_full_all (nonspec_assigned_ovc_not_full_all),
@@ -377,58 +300,54 @@ module spec_sw_alloc2 #(
         .clk (clk),
         .reset (reset)
     );
-
-    assign nonspec_ivc_request_all      = ivc_request_all &  ovc_is_assigned_all;
-    assign spec_ivc_request_all         = ivc_request_all &  ~ovc_is_assigned_all;
-    assign spec_assigned_ovc_not_full_all           = {PV{1'b1}};
-    assign nonspec_assigned_ovc_not_full_all        = assigned_ovc_not_full_all;
-    assign spec_dest_port_all               = dest_port_all;
-    assign nonspec_dest_port_all            = dest_port_all;
-
-    wire [P_1-1 :  0]  nonspec_check [P-1:0];
-    wire [P_1-1 :  0]  spec_check [P-1:0];
-
+    
+    assign nonspec_ivc_request_all = ivc_request_all &  ovc_is_assigned_all;
+    assign spec_ivc_request_all  = ivc_request_all &  ~ovc_is_assigned_all;
+    assign spec_assigned_ovc_not_full_all = {PV{1'b1}};
+    assign nonspec_assigned_ovc_not_full_all = assigned_ovc_not_full_all;
+    assign spec_dest_port_all = dest_port_all;
+    assign nonspec_dest_port_all = dest_port_all;
+    
+    wire [P_1-1 : 0]  nonspec_check [P-1:0];
+    wire [P_1-1 : 0]  spec_check [P-1:0];
+    
     genvar i,j;
     generate
-    for(i=0;i<P; i=i+1) begin :port_lp
+    for(i=0;i<P; i=i+1) begin : P_
         //remove non-spec inport from the nonspec_outport_granted_all
-        for(j=0;j<P;    j=j+1)begin: port_loop2
-            if(i<j)begin: jj
-                assign nonspec_portsel_granted[i][j-1]  = nonspec_outport_granted_all[j];
-            end else if(i>j)begin: hh
-                assign nonspec_portsel_granted[i][j]        = nonspec_outport_granted_all [j];
+        for(j=0;j<P;    j=j+1)begin: P_
+            if(i<j)begin
+                assign nonspec_portsel_granted[i][j-1] = nonspec_outport_granted_all[j];
+            end else if(i>j)begin
+                assign nonspec_portsel_granted[i][j] = nonspec_outport_granted_all [j];
             end
             //if(i==j) wires are left disconnected
         end//j
         // an speculative grant is acceptable if the non-speculative request is not granted for both inport request and outport grant
-        assign spec_request_acceptable[(i+1)*P_1-1 :  i*P_1] = (nonspec_inport_granted_all[i])? {P_1{1'b0}} : ~nonspec_portsel_granted[i];
-        assign spec_request_accepted  [i]= spec_request_acceptable[(i+1)*P_1-1 :  i*P_1] & spec_granted_dest_port_all_pre[(i+1)*P_1-1 :  i*P_1];
+        assign spec_request_acceptable[(i+1)*P_1-1 : i*P_1] = (nonspec_inport_granted_all[i])? {P_1{1'b0}} : ~nonspec_portsel_granted[i];
+        assign spec_request_accepted  [i]= spec_request_acceptable[(i+1)*P_1-1 : i*P_1] & spec_granted_dest_port_all_pre[(i+1)*P_1-1 : i*P_1];
         assign any_spec_request_accepted [i] = |spec_request_accepted  [i];
-        assign spec_ivc_granted_all_accepted[(i+1)*V-1 :  i*V] = (any_spec_request_accepted [i] )? spec_ivc_granted_all[(i+1)*V-1 :  i*V]: {V{1'b0}};
-        assign spec_granted_dest_port_all_accepted[(i+1)*P_1-1 :  i*P_1]= spec_request_accepted  [i];
-
-        //synthesis translate_off
-        //synopsys  translate_off
-        if(DEBUG_EN)begin :dbg
-            assign nonspec_check[i] = nonspec_granted_dest_port_all[(i+1)*P_1-1 :  i*P_1];
-            assign spec_check[i]= spec_granted_dest_port_all_accepted[(i+1)*P_1-1 :  i*P_1];
+        assign spec_ivc_granted_all_accepted[(i+1)*V-1 : i*V] = (any_spec_request_accepted [i] )? spec_ivc_granted_all[(i+1)*V-1 : i*V]: {V{1'b0}};
+        assign spec_granted_dest_port_all_accepted[(i+1)*P_1-1 : i*P_1]= spec_request_accepted  [i];
+        
+        `ifdef SIMULATION
+        if(DEBUG_EN)begin : dbg
+            assign nonspec_check[i] = nonspec_granted_dest_port_all[(i+1)*P_1-1 : i*P_1];
+            assign spec_check[i]= spec_granted_dest_port_all_accepted[(i+1)*P_1-1 : i*P_1];
             always @(posedge clk) begin
-                if(nonspec_granted_dest_port_all[(i+1)*P_1-1 :  i*P_1] >0 && spec_granted_dest_port_all_accepted[(i+1)*P_1-1 :  i*P_1]>0 ) $display("%t: Error: Both speculative and nonspeculative is granted for one port",$time);
-                if(nonspec_ivc_granted_all [(i+1)*V-1 :  i*V] >0 && spec_ivc_granted_all_accepted[(i+1)*V-1 :  i*V]>0 ) $display("%t: Error: Both speculative and nonspeculative is granted for one port",$time);
+                if(nonspec_granted_dest_port_all[(i+1)*P_1-1 : i*P_1] >0 && spec_granted_dest_port_all_accepted[(i+1)*P_1-1 : i*P_1]>0 ) $display("%t: Error: Both speculative and nonspeculative is granted for one port",$time);
+                if(nonspec_ivc_granted_all [(i+1)*V-1 : i*V] >0 && spec_ivc_granted_all_accepted[(i+1)*V-1 : i*V]>0 ) $display("%t: Error: Both speculative and nonspeculative is granted for one port",$time);
             end//always
         end // DEBUG
-        //synopsys  translate_on
-        //synthesis translate_on
+        `endif //SIMULATION
     end//i
     endgenerate
-
-    assign spec_any_ivc_grant_valid         = any_spec_request_accepted &  spec_any_ivc_grant;
-    assign any_ivc_sw_request_granted_all   = nonspec_any_ivc_grant | spec_any_ivc_grant_valid;
-
-    assign granted_dest_port_all                = nonspec_granted_dest_port_all | spec_granted_dest_port_all_accepted;
-    assign ivc_granted_all                      = nonspec_ivc_granted_all         | spec_ivc_granted_all_accepted;
-    assign spec_granted_dest_port_all       = spec_granted_dest_port_all_accepted;
-
+    
+    assign spec_any_ivc_grant_valid  = any_spec_request_accepted &  spec_any_ivc_grant;
+    assign any_ivc_sw_request_granted_all = nonspec_any_ivc_grant | spec_any_ivc_grant_valid;
+    assign granted_dest_port_all = nonspec_granted_dest_port_all | spec_granted_dest_port_all_accepted;
+    assign ivc_granted_all  = nonspec_ivc_granted_all  | spec_ivc_granted_all_accepted;
+    assign spec_granted_dest_port_all = spec_granted_dest_port_all_accepted;
 endmodule
 
 
@@ -438,11 +357,7 @@ endmodule
 *
 *******************************************/
 module sw_alloc_sub2#(
-    parameter V = 4,
-    parameter P = 5,
-    parameter SWA_ARBITER_TYPE="RRA",
-    parameter MIN_PCK_SIZE=2 //minimum packet size in flits. The minimum value is 1.
-
+    parameter P = 5
 )(
     ivc_granted_all,
     ivc_request_all,
@@ -461,7 +376,7 @@ module sw_alloc_sub2#(
     clk,
     reset
 );
-
+    import pronoc_pkg::*;
     localparam
         P_1 = P-1,//assumed that no port request for itself!
         PV = V * P,
@@ -469,73 +384,66 @@ module sw_alloc_sub2#(
         PVP_1 = P * VP_1,
         PP_1 = P_1 * P,
         PP = P * P;
-
-    output [PV-1 :  0]  ivc_granted_all;
-    input  [PV-1 :  0] ivc_request_all;
-    input  [PV-1 :  0] assigned_ovc_not_full_all;
-    input  [PVP_1-1 :  0]  dest_port_all;
-    output [PP_1-1 :  0]  granted_dest_port_all;
-    output [P-1 :  0]  inport_granted_all;
-    output [P-1 :  0]  outport_granted_all;
-    output [PV-1 :  0]  first_arbiter_granted_ivc_all;
-    output [PP_1-1 :  0]  first_arbiter_granted_port_all;
-    output [P-1 :  0]  any_ivc_grant;
+    
+    output [PV-1 : 0]  ivc_granted_all;
+    input  [PV-1 : 0] ivc_request_all;
+    input  [PV-1 : 0] assigned_ovc_not_full_all;
+    input  [PVP_1-1 : 0]  dest_port_all;
+    output [PP_1-1 : 0]  granted_dest_port_all;
+    output [P-1 : 0]  inport_granted_all;
+    output [P-1 : 0]  outport_granted_all;
+    output [PV-1 : 0]  first_arbiter_granted_ivc_all;
+    output [PP_1-1 : 0]  first_arbiter_granted_port_all;
+    output [P-1 : 0]  any_ivc_grant;
     input  [PV-1 : 0 ] vc_weight_is_consumed_all;
     input  [P-1 : 0 ] iport_weight_is_consumed_all;
     input  [PV-1 : 0] pck_is_single_flit_all;
     output [P-1 : 0] granted_dst_is_from_a_single_flit_pck;
     input  clk;
     input  reset;
-
+    
     //separte input per port
-    wire [V-1 :  0]  ivc_granted [P-1 :  0];
-    wire [V-1 :  0]  ivc_request [P-1 :  0];
-    wire [V-1 :  0]  ivc_not_full [P-1 :  0];
-    wire [VP_1-1 :  0] dest_port_ivc [P-1 :  0];
-    wire [P_1-1 :  0]  granted_dest_port [P-1 :  0];
-
+    wire [V-1 : 0]  ivc_granted [P-1 : 0];
+    wire [V-1 : 0]  ivc_request [P-1 : 0];
+    wire [V-1 : 0]  ivc_not_full [P-1 : 0];
+    wire [VP_1-1 : 0] dest_port_ivc [P-1 : 0];
+    wire [P_1-1 : 0]  granted_dest_port [P-1 : 0];
+    
     // internal wires
-    wire [V-1 :  0] ivc_masked [P-1 :  0];//output of mask and
-    wire [V-1 :  0] first_arbiter_grant [P-1 :  0];//output of first arbiter
-    wire [P_1-1 :  0]  dest_port [P-1 :  0];//output of multiplexer
-    wire [P_1-1 :  0]  second_arbiter_request [P-1 :  0];
-    wire [P_1-1 :  0]  second_arbiter_grant [P-1 :  0];
+    wire [V-1 : 0] ivc_masked [P-1 : 0];//output of mask and
+    wire [V-1 : 0] first_arbiter_grant [P-1 : 0];//output of first arbiter
+    wire [P_1-1 : 0]  dest_port [P-1 : 0];//output of multiplexer
+    wire [P_1-1 : 0]  second_arbiter_request [P-1 : 0];
+    wire [P_1-1 : 0]  second_arbiter_grant [P-1 : 0];
     wire [P_1-1 : 0] second_arbiter_weight_consumed [P-1 : 0];
     wire [V-1 : 0] vc_weight_is_consumed [P-1 : 0];
     wire [P-1 : 0] winner_weight_consumed;
-
+    
     wire [P_1-1 : 0] single_flit_granted_dst [P-1 : 0];
-    wire [PP-1 : 0] single_flit_granted_dst_all;
+    wire [P-1 : 0] single_flit_granted_dst_all [P-1 : 0];
     wire [V-1 : 0] pck_is_single_flit [P-1 : 0];
     wire [P-1 : 0] single_flit_pck_local_grant;
-
+    
     genvar i,j;
     generate
-
-    for(i=0;i< P;i=i+1) begin :port_loop
+    for(i=0;i< P;i=i+1) begin : P_
         //assign in/out to the port based wires
         //output
-        assign ivc_granted_all          [(i+1)*V-1 :  i*V]    =   ivc_granted [i];
-        assign granted_dest_port_all    [(i+1)*P_1-1 :  i*P_1]      =   granted_dest_port[i];
-        assign first_arbiter_granted_ivc_all[(i+1)*V-1 :  i*V]=           first_arbiter_grant[i];
+        assign ivc_granted_all [(i+1)*V-1 : i*V] = ivc_granted [i];
+        assign granted_dest_port_all [(i+1)*P_1-1 : i*P_1] = granted_dest_port[i];
+        assign first_arbiter_granted_ivc_all[(i+1)*V-1 : i*V] = first_arbiter_grant[i];
         //input
-        assign ivc_request[i]       = ivc_request_all [(i+1)*V-1 :  i*V];
-        assign ivc_not_full[i]      = assigned_ovc_not_full_all[(i+1)*V-1 :  i*V];
-        assign dest_port_ivc[i]     = dest_port_all [(i+1)*VP_1-1 :  i*VP_1];
-        assign vc_weight_is_consumed[i]  =  vc_weight_is_consumed_all [(i+1)*V-1 : i*V];
-
+        assign ivc_request[i] = ivc_request_all [(i+1)*V-1 : i*V];
+        assign ivc_not_full[i] = assigned_ovc_not_full_all[(i+1)*V-1 : i*V];
+        assign dest_port_ivc[i] = dest_port_all [(i+1)*VP_1-1 : i*VP_1];
+        assign vc_weight_is_consumed[i] = vc_weight_is_consumed_all [(i+1)*V-1 : i*V];
         //mask
-        assign ivc_masked[i]    = ivc_request[i] & ivc_not_full[i];
-
-
-         //first level arbiter
+        assign ivc_masked[i] = ivc_request[i] & ivc_not_full[i];
+        //first level arbiter
         swa_input_port_arbiter #(
             .ARBITER_WIDTH(V),
-            .EXT_P_EN(0),
-            .ARBITER_TYPE(SWA_ARBITER_TYPE)
-        )
-        input_arbiter
-        (
+            .EXT_P_EN(0)
+        )input_arbiter (
             .ext_pr_en_i(1'b1),// not used here anyway
             .request(ivc_masked [i]),
             .grant(first_arbiter_grant[i]),
@@ -545,60 +453,50 @@ module sw_alloc_sub2#(
             .vc_weight_is_consumed(vc_weight_is_consumed[i]),
             .winner_weight_consumed(winner_weight_consumed[i])
         );
-
         //destination port multiplexer
         one_hot_mux #(
             .IN_WIDTH (VP_1),
             .SEL_WIDTH(V)
-        )
-        multiplexer
-        (
+        ) multiplexer (
             .mux_in(dest_port_ivc [i]),
             .mux_out(dest_port [i]),
             .sel(first_arbiter_grant [i])
-
         );
-        assign first_arbiter_granted_port_all[(i+1)*P_1-1 :  i*P_1]  = dest_port     [i];
-        if(MIN_PCK_SIZE == 1) begin :single_flit_supported
+        assign first_arbiter_granted_port_all[(i+1)*P_1-1 : i*P_1] = dest_port     [i];
+        if(MIN_PCK_SIZE == 1) begin 
             assign pck_is_single_flit[i] = pck_is_single_flit_all [(i+1)*V-1 : i*V];
             //single_flit req multiplexer
             one_hot_mux #(
-                .IN_WIDTH       (V),
-                .SEL_WIDTH      (V)
-            )
-            multiplexer2
-            (
+                .IN_WIDTH (V),
+                .SEL_WIDTH (V)
+            ) multiplexer2 (
                 .mux_in (pck_is_single_flit  [i]),
                 .mux_out (single_flit_pck_local_grant[i]),
                 .sel (first_arbiter_grant[i])
             );
-
+            
             assign  single_flit_granted_dst[i] = (single_flit_pck_local_grant[i])?  granted_dest_port[i] : {P_1{1'b0}};
-
+            
             add_sw_loc_one_hot #(
                 .P(P),
                 .SW_LOC(i)
-            )
-            add_sw_loc
-            (
+            ) add_sw_loc (
                 .destport_in(single_flit_granted_dst[i]),
-                .destport_out(single_flit_granted_dst_all[(i+1)*P-1 : i*P])
+                .destport_out(single_flit_granted_dst_all[i])
             );
-
-        end else begin : single_flit_notsupported
+        end else begin 
             assign single_flit_pck_local_grant[i] = 1'b0;
             assign single_flit_granted_dst[i] = {P_1{1'b0}};
-            assign single_flit_granted_dst_all[(i+1)*P-1 : i*P]={P{1'b0}};
+            assign single_flit_granted_dst_all[i] = {P{1'b0}};
         end
-
         //second arbiter input/output generate
-        for(j=0;j<P;    j=j+1)begin: assign_loop
-            if(i<j)begin: jj
+        for(j=0;j<P; j=j+1) begin : P_
+            if(i<j)begin
                     assign second_arbiter_request[i][j-1] = dest_port[j][i];
                     //assign second_arbiter_weight_consumed[i][j-1]  = winner_weight_consumed[j];
                     assign second_arbiter_weight_consumed[i][j-1]  = iport_weight_is_consumed_all[j];
                     assign granted_dest_port[j][i] = second_arbiter_grant  [i][j-1];
-            end else if(i>j)begin: hh
+            end else if(i>j)begin
                     assign second_arbiter_request[i][j] = dest_port [j][i-1];
                 // assign second_arbiter_weight_consumed[i][j]  = winner_weight_consumed[j];
                     assign second_arbiter_weight_consumed[i][j]  = iport_weight_is_consumed_all[j];
@@ -606,14 +504,11 @@ module sw_alloc_sub2#(
             end
                 //if(i==j) wires are left disconnected
         end
-
+        
        //second level arbiter
         swa_output_port_arbiter #(
-            .ARBITER_WIDTH(P_1),
-            .ARBITER_TYPE(SWA_ARBITER_TYPE) // RRA, WRRA
-        )
-        output_arbiter
-        (
+            .ARBITER_WIDTH(P_1)
+        ) output_arbiter(
             .weight_consumed(second_arbiter_weight_consumed[i]),  // only used for WRRA
             .clk(clk),
             .reset(reset),
@@ -621,33 +516,26 @@ module sw_alloc_sub2#(
             .grant(second_arbiter_grant [i]),
             .any_grant(outport_granted_all [i])
         );
-
+        
         //any ivc
         assign  any_ivc_grant[i] = | granted_dest_port[i];
-
         assign  ivc_granted[i] =  (any_ivc_grant[i]) ? first_arbiter_grant[i] : {V{1'b0}};
-
         assign      inport_granted_all[i]   =any_ivc_grant[i];
     end//for i
     endgenerate
-
-    custom_or #(
-        .IN_NUM(P),
-        .OUT_WIDTH(P)
-    )
-    or_dst
-    (
-        .or_in(single_flit_granted_dst_all),
-        .or_out(granted_dst_is_from_a_single_flit_pck)
+    
+    reduction_or #(
+        .W(P),
+        .N(P)
+    ) or_dst (
+        .D_in(single_flit_granted_dst_all),
+        .Q_out(granted_dst_is_from_a_single_flit_pck)
     );
-
 endmodule
 
+
 module spec_sw_alloc_sub2#(
-    parameter V = 4,
-    parameter P = 5,
-    parameter SWA_ARBITER_TYPE="RRA",
-    parameter MIN_PCK_SIZE=2 //minimum packet size in flits. The minimum value is 1.
+    parameter P = 5
 )(
     valid_speculation,
     ivc_granted_all,
@@ -667,7 +555,7 @@ module spec_sw_alloc_sub2#(
     clk,
     reset
 );
-
+    import pronoc_pkg::*;
     localparam
         P_1 = P-1,//assumed that no port request for itself!
         PV = V * P,
@@ -675,73 +563,66 @@ module spec_sw_alloc_sub2#(
         PVP_1 = P * VP_1,
         PP_1 = P_1 * P,
         PP = P * P;
-
-    input  [PV-1 :  0] valid_speculation;
-    output [PV-1 :  0]  ivc_granted_all;
-    input  [PV-1 :  0] ivc_request_all;
-    input  [PV-1 :  0] assigned_ovc_not_full_all;
-    input  [PVP_1-1 :  0]  dest_port_all;
-    output [PP_1-1 :  0]  granted_dest_port_all;
-    output [P-1 :  0]  inport_granted_all;
-    output [P-1 :  0]  outport_granted_all;
-    output [PV-1 :  0]  first_arbiter_granted_ivc_all;
-    output [PP_1-1 :  0]  first_arbiter_granted_port_all;
-    output [P-1 :  0]  any_ivc_grant;
+    
+    input  [PV-1 : 0] valid_speculation;
+    output [PV-1 : 0]  ivc_granted_all;
+    input  [PV-1 : 0] ivc_request_all;
+    input  [PV-1 : 0] assigned_ovc_not_full_all;
+    input  [PVP_1-1 : 0]  dest_port_all;
+    output [PP_1-1 : 0]  granted_dest_port_all;
+    output [P-1 : 0]  inport_granted_all;
+    output [P-1 : 0]  outport_granted_all;
+    output [PV-1 : 0]  first_arbiter_granted_ivc_all;
+    output [PP_1-1 : 0]  first_arbiter_granted_port_all;
+    output [P-1 : 0]  any_ivc_grant;
     input  [PV-1 : 0 ] vc_weight_is_consumed_all;
     input  [P-1 : 0 ] iport_weight_is_consumed_all;
     input  [PV-1 : 0] pck_is_single_flit_all;
     output [P-1 : 0] granted_dst_is_from_a_single_flit_pck;
     input  clk, reset;
-
+    
     //separte input per port
-    wire  [V-1 : 0] ivc_granted [P-1 :  0];
-    wire  [V-1 : 0] ivc_request [P-1 :  0];
-    wire  [V-1 : 0] ivc_not_full [P-1 :  0];
-    wire  [VP_1-1 : 0] dest_port_ivc [P-1 :  0];
-    wire  [P_1-1 : 0] granted_dest_port [P-1 :  0];
-
+    wire  [V-1 : 0] ivc_granted [P-1 : 0];
+    wire  [V-1 : 0] ivc_request [P-1 : 0];
+    wire  [V-1 : 0] ivc_not_full [P-1 : 0];
+    wire  [VP_1-1 : 0] dest_port_ivc [P-1 : 0];
+    wire  [P_1-1 : 0] granted_dest_port [P-1 : 0];
+    
     // internal wires
-    wire [V-1 :  0] ivc_masked [P-1 :  0];//output of mask and
-    wire [V-1 :  0] first_arbiter_grant  [P-1 :  0];//output of first arbiter
-    wire [V-1 :  0] first_arbiter_grant_masked [P-1 :  0];//output of first arbiter
-    wire [P_1-1 :  0] dest_port [P-1 :  0];//output of multiplexer
-    wire [P_1-1 :  0] second_arbiter_request [P-1 :  0];
-    wire [P_1-1 :  0] second_arbiter_grant  [P-1 :  0];
+    wire [V-1 : 0] ivc_masked [P-1 : 0];//output of mask and
+    wire [V-1 : 0] first_arbiter_grant  [P-1 : 0];//output of first arbiter
+    wire [V-1 : 0] first_arbiter_grant_masked [P-1 : 0];//output of first arbiter
+    wire [P_1-1 : 0] dest_port [P-1 : 0];//output of multiplexer
+    wire [P_1-1 : 0] second_arbiter_request [P-1 : 0];
+    wire [P_1-1 : 0] second_arbiter_grant  [P-1 : 0];
     wire [P_1-1 : 0] second_arbiter_weight_consumed [P-1 : 0];
     wire [V-1 : 0] vc_weight_is_consumed [P-1 : 0];
-    wire [P-1 : 0] winner_weight_consumed;
-
+    wire [P-1 : 0] winner_weight_consumed;    
     wire [P_1-1 : 0] single_flit_granted_dst [P-1 : 0];
-    wire [PP-1 : 0] single_flit_granted_dst_all;
+    wire [P-1 : 0] single_flit_granted_dst_all [P-1 : 0];
     wire [V-1 : 0] pck_is_single_flit [P-1 : 0];
-    wire    [P-1 : 0] single_flit_pck_local_grant;
-
+    wire [P-1 : 0] single_flit_pck_local_grant;
+    
     genvar i,j;
     generate
-
-    for(i=0;i< P;i=i+1) begin :port_loop
+    for(i=0;i< P;i=i+1) begin : P_
         //assign in/out to the port based wires
         //output
-        assign ivc_granted_all [(i+1)*V-1 :  i*V] =   ivc_granted [i];
-        assign granted_dest_port_all [(i+1)*P_1-1:  i*P_1] = granted_dest_port[i];
-        assign first_arbiter_granted_ivc_all[(i+1)*V-1 :  i*V]  = first_arbiter_grant_masked[i];
+        assign ivc_granted_all [(i+1)*V-1 : i*V] = ivc_granted [i];
+        assign granted_dest_port_all [(i+1)*P_1-1: i*P_1] = granted_dest_port[i];
+        assign first_arbiter_granted_ivc_all[(i+1)*V-1 : i*V] = first_arbiter_grant_masked[i];
         //input
-        assign ivc_request[i] = ivc_request_all [(i+1)*V-1 :  i*V];
-        assign ivc_not_full[i] = assigned_ovc_not_full_all[(i+1)*V-1 :  i*V];
-        assign dest_port_ivc[i] = dest_port_all [(i+1)*VP_1-1 :  i*VP_1];
+        assign ivc_request[i] = ivc_request_all [(i+1)*V-1 : i*V];
+        assign ivc_not_full[i] = assigned_ovc_not_full_all[(i+1)*V-1 : i*V];
+        assign dest_port_ivc[i] = dest_port_all [(i+1)*VP_1-1 : i*VP_1];
         assign vc_weight_is_consumed[i]  =  vc_weight_is_consumed_all [(i+1)*V-1 : i*V];
-
         //mask
         assign ivc_masked[i] = ivc_request[i] & ivc_not_full[i];
-
         //first level arbiter
         swa_input_port_arbiter #(
             .ARBITER_WIDTH(V),
-            .EXT_P_EN(0),
-            .ARBITER_TYPE(SWA_ARBITER_TYPE)
-        )
-        input_arbiter
-        (
+            .EXT_P_EN(0)
+        ) input_arbiter (
             .ext_pr_en_i(1'b1),// not used here anyway
             .request(ivc_masked [i]),
             .grant(first_arbiter_grant[i]),
@@ -750,107 +631,82 @@ module spec_sw_alloc_sub2#(
             .reset(reset),
             .vc_weight_is_consumed(vc_weight_is_consumed[i]),
             .winner_weight_consumed(winner_weight_consumed[i])
-        );
-
+        );        
         // mask unvalid speculation
-        assign first_arbiter_grant_masked[i]= first_arbiter_grant[i] & valid_speculation [(i+1)*V-1 :  i*V];
-
-        if(MIN_PCK_SIZE == 1) begin :single_flit_supported
-
+        assign first_arbiter_grant_masked[i]= first_arbiter_grant[i] & valid_speculation [(i+1)*V-1 : i*V];
+        if(MIN_PCK_SIZE == 1) begin 
             assign pck_is_single_flit[i] = pck_is_single_flit_all [(i+1)*V-1 : i*V];
             
             //single_flit req multiplexer
             one_hot_mux #(
-                .IN_WIDTH       (V),
-                .SEL_WIDTH      (V)
-            )
-            multiplexer2
-            (
+                .IN_WIDTH  (V),
+                .SEL_WIDTH (V)
+            ) multiplexer2  (
                 .mux_in (pck_is_single_flit  [i]),
                 .mux_out (single_flit_pck_local_grant[i]),
                 .sel (first_arbiter_grant[i])
             );
-
-            assign  single_flit_granted_dst[i] = (single_flit_pck_local_grant[i])?  granted_dest_port[i] : {P_1{1'b0}};
-
+            assign  single_flit_granted_dst[i] = (single_flit_pck_local_grant[i])? granted_dest_port[i] : {P_1{1'b0}};
             add_sw_loc_one_hot #(
                 .P(P),
                 .SW_LOC(i)
-            )
-            add_sw_loc
-            (
+            ) add_sw_loc  (
                 .destport_in(single_flit_granted_dst[i]),
-                .destport_out(single_flit_granted_dst_all[(i+1)*P-1 : i*P])
+                .destport_out(single_flit_granted_dst_all[i])
             );
-
-        end else begin : single_flit_notsupported
+        end else begin
             assign single_flit_pck_local_grant[i] = 1'b0;
             assign single_flit_granted_dst[i] = {P_1{1'b0}};
-            assign single_flit_granted_dst_all[(i+1)*P-1 : i*P]={P{1'b0}};
+            assign single_flit_granted_dst_all[i] = {P{1'b0}};
         end
-
         //destination port multiplexer
         one_hot_mux #(
             .IN_WIDTH (VP_1),
             .SEL_WIDTH (V)
-        )
-        multiplexer
-        (
+        ) multiplexer (
             .mux_in (dest_port_ivc [i]),
             .mux_out (dest_port [i]),
             .sel (first_arbiter_grant_masked[i])
         );
-        assign first_arbiter_granted_port_all[(i+1)*P_1-1 :  i*P_1]  = dest_port     [i];
-
-
+        assign first_arbiter_granted_port_all[(i+1)*P_1-1 : i*P_1] = dest_port [i];        
         //second arbiter input/output generate
-        for(j=0;j<P;    j=j+1)begin: assign_loop
-            if(i<j)begin: jj
-                assign second_arbiter_request[i][j-1]   = dest_port[j][i];
+        for(j=0;j<P;    j=j+1)begin : P_
+            if(i<j)begin
+                assign second_arbiter_request[i][j-1] = dest_port[j][i];
                 //assign second_arbiter_weight_consumed[i][j-1]  =winner_weight_consumed[j] ;
-                assign second_arbiter_weight_consumed[i][j-1]  = iport_weight_is_consumed_all[j] ;
+                assign second_arbiter_weight_consumed[i][j-1] = iport_weight_is_consumed_all[j] ;
                 assign granted_dest_port[j][i]  = second_arbiter_grant  [i][j-1]    ;
-            end else if(i>j)begin: hh
+            end else if(i>j)begin
                 assign second_arbiter_request[i][j] = dest_port [j][i-1];
                 //assign second_arbiter_weight_consumed[i][j]  =winner_weight_consumed[j];
-                assign second_arbiter_weight_consumed[i][j]  =iport_weight_is_consumed_all[j];
-                assign granted_dest_port[j][i-1]    = second_arbiter_grant  [i][j]  ;
+                assign second_arbiter_weight_consumed[i][j] = iport_weight_is_consumed_all[j];
+                assign granted_dest_port[j][i-1] = second_arbiter_grant  [i][j]  ;
             end
             //if(i==j) wires are left disconnected
-        end
-
+        end        
         //second level arbiter
         swa_output_port_arbiter #(
-            .ARBITER_WIDTH(P_1),
-            .ARBITER_TYPE(SWA_ARBITER_TYPE) // RRA, WRRA
-        )
-        output_arbiter
-        (
+            .ARBITER_WIDTH(P_1)
+        ) output_arbiter  (
            .weight_consumed(second_arbiter_weight_consumed[i]),  // only used for WRRA
             .clk(clk),
             .reset(reset),
             .request(second_arbiter_request [i]),
             .grant(second_arbiter_grant [i]),
             .any_grant(outport_granted_all [i])
-        );
-
+        );        
         //any ivc
         assign  any_ivc_grant[i] = | granted_dest_port[i];
-
         assign  ivc_granted[i] =  (any_ivc_grant[i]) ? first_arbiter_grant_masked[i] : {V{1'b0}};
-
-        assign      inport_granted_all[i]   =any_ivc_grant[i];
-    end//for
+        assign  inport_granted_all[i] = any_ivc_grant[i];
+    end//for P_
     endgenerate
-
-    custom_or #(
-        .IN_NUM(P),
-        .OUT_WIDTH(P)
-    )
-    or_dst
-    (
-        .or_in(single_flit_granted_dst_all),
-        .or_out(granted_dst_is_from_a_single_flit_pck)
+    
+    reduction_or #(
+        .W(P),
+        .N(P)
+    ) or_dst (
+        .D_in(single_flit_granted_dst_all),
+        .Q_out(granted_dst_is_from_a_single_flit_pck)
     );
-
-endmodule
+endmodule
\ No newline at end of file
diff --git a/mpsoc/rtl/src_noc/combined_vc_sw_alloc.sv b/mpsoc/rtl/src_noc/combined_vc_sw_alloc.sv
index 375ced9..82c94a8 100755
--- a/mpsoc/rtl/src_noc/combined_vc_sw_alloc.sv
+++ b/mpsoc/rtl/src_noc/combined_vc_sw_alloc.sv
@@ -1,33 +1,31 @@
 `include "pronoc_def.v"
 /**********************************************************************
-**	File: combined_vc_sw_alloc.v
+**    File: combined_vc_sw_alloc.v
 **    
-**	Copyright (C) 2014-2017  Alireza Monemi
+**    Copyright (C) 2014-2017  Alireza Monemi
 **    
-**	This file is part of ProNoC 
+**    This file is part of ProNoC 
 **
-**	ProNoC ( stands for Prototype Network-on-chip)  is free software: 
-**	you can redistribute it and/or modify it under the terms of the GNU
-**	Lesser General Public License as published by the Free Software Foundation,
-**	either version 2 of the License, or (at your option) any later version.
+**    ProNoC ( stands for Prototype Network-on-chip)  is free software: 
+**    you can redistribute it and/or modify it under the terms of the GNU
+**    Lesser General Public License as published by the Free Software Foundation,
+**    either version 2 of the License, or (at your option) any later version.
 **
-** 	ProNoC is distributed in the hope that it will be useful, but WITHOUT
-** 	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
-** 	or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
-** 	Public License for more details.
+**     ProNoC is distributed in the hope that it will be useful, but WITHOUT
+**     ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+**     or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
+**     Public License for more details.
 **
-** 	You should have received a copy of the GNU Lesser General Public
-** 	License along with ProNoC. If not, see <http:**www.gnu.org/licenses/>.
+**     You should have received a copy of the GNU Lesser General Public
+**     License along with ProNoC. If not, see <http:**www.gnu.org/licenses/>.
 **
 **
-**	Description: 
-**	combined VC/SW allocator. VC allocation is done in parallel with swich allocator 
-**	for header flits which are successfully get sw grant 
+**    Description: 
+**    combined VC/SW allocator. VC allocation is done in parallel with swich allocator 
+**    for header flits which are successfully get sw grant 
 *************************************/
 
-
 module combined_vc_sw_alloc #(
-    parameter NOC_ID=0,
     parameter P = 5 //port number
 )(
     ivc_info,
@@ -37,7 +35,6 @@ module combined_vc_sw_alloc #(
     granted_ovc_num_all,
     ivc_num_getting_ovc_grant,
     ivc_num_getting_sw_grant,
-    spec_first_arbiter_granted_ivc_all,
     nonspec_first_arbiter_granted_ivc_all,
     granted_dest_port_all,
     nonspec_granted_dest_port_all,
@@ -50,42 +47,35 @@ module combined_vc_sw_alloc #(
     granted_dst_is_from_a_single_flit_pck,
     clk,
     reset
-
 );
-	`NOC_CONF
-
+    import pronoc_pkg::*;
+    
     localparam
         PV = V * P,
-        PVV = PV * V,    
-        P_1 = (SELF_LOOP_EN == "NO")? P-1 : P,
+        PVV = PV * V,
+        P_1 = (SELF_LOOP_EN )?  P : P-1,
         PP_1 = P_1 * P,
-        PVP_1 = PV * P_1;   
+        PVP_1 = PV * P_1;
         
-    input  ivc_info_t ivc_info [P-1 : 0][V-1 : 0];     
+    input  ivc_info_t ivc_info [P-1 : 0][V-1 : 0];
     input  [PVP_1-1 : 0] dest_port_all;
-    input  [PVV-1 :  0] masked_ovc_request_all;  
-   
-     
+    input  [PVV-1 :  0] masked_ovc_request_all;
     output [PV-1 : 0] ovc_allocated_all;
     output [PVV-1 : 0] granted_ovc_num_all;
     output [PV-1 : 0] ivc_num_getting_ovc_grant;
     output [PV-1 : 0] ivc_num_getting_sw_grant;
     output [PV-1 : 0] nonspec_first_arbiter_granted_ivc_all;
-    output [PV-1 : 0] spec_first_arbiter_granted_ivc_all;
     output [P-1 : 0] any_ivc_sw_request_granted_all;
     output [P-1 :  0] any_ovc_granted_in_outport_all;    
     output [PP_1-1 : 0] granted_dest_port_all;
     output [PP_1-1 : 0] nonspec_granted_dest_port_all;
     output [PP_1-1 : 0] spec_granted_dest_port_all; 
     output [PVV-1 : 0] spec_ovc_num_all;
-   
     input  [PV-1 :  0] vc_weight_is_consumed_all;
     input  [P-1 :  0] iport_weight_is_consumed_all;
-  
     output [P-1 : 0] granted_dst_is_from_a_single_flit_pck;
-    
     input clk,reset;
-
+    
     wire  [PV-1 : 0] ivc_request_all;
     wire  [PV-1 : 0] assigned_ovc_not_full_all;  
     wire  [PV-1 : 0] ovc_is_assigned_all;
@@ -93,22 +83,16 @@ module combined_vc_sw_alloc #(
     
     genvar i;
     generate
-   	for (i=0; i<PV; i=i+1) begin : vc_loop
+    for (i=0; i<PV; i=i+1) begin : V_
+        localparam  C_PORT  = i/V;
+        assign ivc_request_all[i] = ivc_info[C_PORT][i%V].ivc_req;
+        assign assigned_ovc_not_full_all[i] = ivc_info[C_PORT][i%V].assigned_ovc_not_full;
+        assign ovc_is_assigned_all[i] = ivc_info[C_PORT][i%V].ovc_is_assigned;
+        assign pck_is_single_flit_all[i] =ivc_info[C_PORT][i%V].single_flit_pck;
+    end//for    
     
-    		localparam  C_PORT  = i/V;
-    	       
-    		assign ivc_request_all[i] = ivc_info[C_PORT][i%V].ivc_req;
-    		assign assigned_ovc_not_full_all[i] = ivc_info[C_PORT][i%V].assigned_ovc_not_full;
-    		assign ovc_is_assigned_all[i] = ivc_info[C_PORT][i%V].ovc_is_assigned;
-    		assign pck_is_single_flit_all[i] =ivc_info[C_PORT][i%V].single_flit_pck;
-    	
-    end//for	
-    	
-    	
-    	
     /* 
     if(COMBINATION_TYPE    ==    "BASELINE") begin : canonical_comb_gen
-
         baseline_allocator #(
             .V(V),    
             .P(P),                        
@@ -116,9 +100,7 @@ module combined_vc_sw_alloc #(
             .DEBUG_EN(DEBUG_EN),
             .SWA_ARBITER_TYPE (SWA_ARBITER_TYPE),
             .SELF_LOOP_EN(SELF_LOOP_EN)
-        )
-        the_base_line
-        (
+        )the_base_line (
             .dest_port_all(dest_port_all), 
             .masked_ovc_request_all(masked_ovc_request_all),
             .ovc_is_assigned_all(ovc_is_assigned_all), 
@@ -139,24 +121,13 @@ module combined_vc_sw_alloc #(
             .iport_weight_is_consumed_all(iport_weight_is_consumed_all),
             .clk(clk), 
             .reset(reset)
-        
         );
-         end else
+        end else
     */    
-    /* verilator lint_off WIDTH */
-    if(COMBINATION_TYPE    ==    "COMB_SPEC1") begin : spec1
-    /* verilator lint_on WIDTH */
+    if(IS_COMB_SPEC1) begin : spec1
         comb_spec1_allocator #(
-            .V(V),    
-            .P(P),
-            .DEBUG_EN(DEBUG_EN),
-            .SWA_ARBITER_TYPE (SWA_ARBITER_TYPE),
-            .MIN_PCK_SIZE(MIN_PCK_SIZE),
-            .SELF_LOOP_EN(SELF_LOOP_EN)
-            
-        )
-        the_comb_spec1
-        (
+            .P(P)
+        )the_comb_spec1(
             .dest_port_all(dest_port_all), 
             .masked_ovc_request_all(masked_ovc_request_all),
             .ovc_is_assigned_all(ovc_is_assigned_all), 
@@ -166,7 +137,6 @@ module combined_vc_sw_alloc #(
             .granted_ovc_num_all(granted_ovc_num_all), 
             .ivc_num_getting_ovc_grant(ivc_num_getting_ovc_grant), 
             .ivc_num_getting_sw_grant(ivc_num_getting_sw_grant), 
-            .spec_first_arbiter_granted_ivc_all(spec_first_arbiter_granted_ivc_all), 
             .nonspec_first_arbiter_granted_ivc_all(nonspec_first_arbiter_granted_ivc_all), 
             .granted_dest_port_all(granted_dest_port_all), 
             .nonspec_granted_dest_port_all(nonspec_granted_dest_port_all), 
@@ -179,60 +149,39 @@ module combined_vc_sw_alloc #(
             .reset(reset)
         );        
         
-        assign spec_granted_dest_port_all = {PP_1{1'bx}};
-        assign spec_ovc_num_all = {PVV{1'bx}};
-    /* verilator lint_off WIDTH */    
-    end else if (COMBINATION_TYPE    == "COMB_SPEC2") begin :spec2
-    /* verilator lint_on WIDTH */
-            comb_spec2_allocator #(
-                .V(V),    
-                .P(P),
-                .DEBUG_EN(DEBUG_EN),
-                .SWA_ARBITER_TYPE (SWA_ARBITER_TYPE),
-                .MIN_PCK_SIZE(MIN_PCK_SIZE),
-                .SELF_LOOP_EN(SELF_LOOP_EN)
-            )
-            the_comb_spec2
-            (
-                .dest_port_all(dest_port_all), 
-                .masked_ovc_request_all(masked_ovc_request_all),
-                .ovc_is_assigned_all(ovc_is_assigned_all), 
-                .ivc_request_all(ivc_request_all), 
-                .assigned_ovc_not_full_all(assigned_ovc_not_full_all), 
-                .ovc_allocated_all(ovc_allocated_all), 
-                .granted_ovc_num_all(granted_ovc_num_all), 
-                .ivc_num_getting_ovc_grant(ivc_num_getting_ovc_grant), 
-                .ivc_num_getting_sw_grant(ivc_num_getting_sw_grant), 
-                .spec_first_arbiter_granted_ivc_all(spec_first_arbiter_granted_ivc_all), 
-                .nonspec_first_arbiter_granted_ivc_all(nonspec_first_arbiter_granted_ivc_all), 
-                .granted_dest_port_all(granted_dest_port_all), 
-                .nonspec_granted_dest_port_all(nonspec_granted_dest_port_all), 
-                .any_ivc_sw_request_granted_all(any_ivc_sw_request_granted_all),
-                .vc_weight_is_consumed_all(vc_weight_is_consumed_all),
-                .iport_weight_is_consumed_all(iport_weight_is_consumed_all),
-                .pck_is_single_flit_all(pck_is_single_flit_all),
-                .granted_dst_is_from_a_single_flit_pck(granted_dst_is_from_a_single_flit_pck),  
-                .clk(clk), 
-                .reset(reset)
-            );
-            
-            assign spec_granted_dest_port_all = {PP_1{1'bx}};
-            assign spec_ovc_num_all = {PVV{1'bx}};
-
-    
+        assign spec_granted_dest_port_all = {PP_1{1'b0}};
+        assign spec_ovc_num_all = {PVV{1'b0}};
+    end else if (IS_COMB_SPEC2) begin : spec2
+        comb_spec2_allocator #(
+            .P(P)
+        ) the_comb_spec2 (
+            .dest_port_all(dest_port_all), 
+            .masked_ovc_request_all(masked_ovc_request_all),
+            .ovc_is_assigned_all(ovc_is_assigned_all), 
+            .ivc_request_all(ivc_request_all), 
+            .assigned_ovc_not_full_all(assigned_ovc_not_full_all), 
+            .ovc_allocated_all(ovc_allocated_all), 
+            .granted_ovc_num_all(granted_ovc_num_all), 
+            .ivc_num_getting_ovc_grant(ivc_num_getting_ovc_grant), 
+            .ivc_num_getting_sw_grant(ivc_num_getting_sw_grant), 
+            .nonspec_first_arbiter_granted_ivc_all(nonspec_first_arbiter_granted_ivc_all), 
+            .granted_dest_port_all(granted_dest_port_all), 
+            .nonspec_granted_dest_port_all(nonspec_granted_dest_port_all), 
+            .any_ivc_sw_request_granted_all(any_ivc_sw_request_granted_all),
+            .vc_weight_is_consumed_all(vc_weight_is_consumed_all),
+            .iport_weight_is_consumed_all(iport_weight_is_consumed_all),
+            .pck_is_single_flit_all(pck_is_single_flit_all),
+            .granted_dst_is_from_a_single_flit_pck(granted_dst_is_from_a_single_flit_pck),  
+            .clk(clk), 
+            .reset(reset)
+        );   
+        assign spec_granted_dest_port_all = {PP_1{1'b0}};
+        assign spec_ovc_num_all = {PVV{1'b0}};
     end else begin :   nonspec
-        if(V>7)begin :cmb_v2
-        
-             comb_nonspec_v2_allocator #(
-                .V(V),    
-                .P(P),
-                .FIRST_ARBITER_EXT_P_EN(FIRST_ARBITER_EXT_P_EN),
-                .SWA_ARBITER_TYPE (SWA_ARBITER_TYPE),
-                .MIN_PCK_SIZE(MIN_PCK_SIZE),
-                .SELF_LOOP_EN(SELF_LOOP_EN)
-            )
-            nonspec_comb
-            (
+        if(V>7)begin : cmb_v2
+            comb_nonspec_v2_allocator #(
+                .P(P)
+            ) nonspec_comb (
                 .dest_port_all(dest_port_all), 
                 .masked_ovc_request_all(masked_ovc_request_all),
                 .ovc_is_assigned_all(ovc_is_assigned_all),
@@ -253,18 +202,13 @@ module combined_vc_sw_alloc #(
                 .clk(clk), 
                 .reset(reset)
             );
-            
         end else begin :cmb_v1
-        
             comb_nonspec_allocator #(
-                .NOC_ID(NOC_ID),
                 .P(P)
-            )
-            nonspec_comb
-            (
-            	.ivc_info(ivc_info),
-            	.dest_port_all(dest_port_all), 
-                .masked_ovc_request_all(masked_ovc_request_all),               
+            ) nonspec_comb (
+                .ivc_info(ivc_info),
+                .dest_port_all(dest_port_all), 
+                .masked_ovc_request_all(masked_ovc_request_all),
                 .ovc_allocated_all(ovc_allocated_all), 
                 .granted_ovc_num_all(granted_ovc_num_all), 
                 .ivc_num_getting_ovc_grant(ivc_num_getting_ovc_grant), 
@@ -281,11 +225,9 @@ module combined_vc_sw_alloc #(
                 .reset(reset)
             );
         end
-        
-        assign nonspec_granted_dest_port_all      = granted_dest_port_all;
-        assign spec_granted_dest_port_all         = {PP_1{1'bx}};
-        assign spec_ovc_num_all                      = {PVV{1'bx}};
-        assign spec_first_arbiter_granted_ivc_all =  nonspec_first_arbiter_granted_ivc_all ;
+        assign nonspec_granted_dest_port_all = granted_dest_port_all;
+        assign spec_granted_dest_port_all  = {PP_1{1'b0}};
+        assign spec_ovc_num_all = {PVV{1'b0}};        
     end
 endgenerate
-endmodule
+endmodule
\ No newline at end of file
diff --git a/mpsoc/rtl/src_noc/congestion_analyzer.sv b/mpsoc/rtl/src_noc/congestion_analyzer.sv
new file mode 100755
index 0000000..d616d6e
--- /dev/null
+++ b/mpsoc/rtl/src_noc/congestion_analyzer.sv
@@ -0,0 +1,1019 @@
+`include "pronoc_def.v"
+/**********************************************************************
+** File: congestion_analyzer.v
+** 
+** Copyright (C) 2014-2017  Alireza Monemi
+** 
+** This file is part of ProNoC 
+**
+** ProNoC ( stands for Prototype Network-on-chip)  is free software: 
+** you can redistribute it and/or modify it under the terms of the GNU
+** Lesser General Public License as published by the Free Software Foundation,
+** either version 2 of the License, or (at your option) any later version.
+**
+**  ProNoC is distributed in the hope that it will be useful, but WITHOUT
+**  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+**  or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
+**  Public License for more details.
+**
+**  You should have received a copy of the GNU Lesser General Public
+**  License along with ProNoC. If not, see <http:**www.gnu.org/licenses/>.
+**
+**
+** Description: 
+** This file includes all files for getting congestion information and
+** Port selection modules for supporting adaptive routing 
+**
+**************************************************************/
+
+/***************************************
+*     
+*  port_presel_based_dst_ports_vc
+*       CONGESTION_INDEX==0
+***************************************/
+//congestion analyzer based on number of occupied VCs
+module   port_presel_based_dst_ports_vc #(
+    parameter P = 5
+    )(
+        ovc_status,
+        port_pre_sel
+    );
+    import pronoc_pkg::*;
+    localparam  
+        P_1 = P-1,
+        P_1V = P_1*V,
+        CNTw = log2(V+1);
+    
+    input [P_1V-1 : 0] ovc_status; 
+    output [PPSw-1 : 0] port_pre_sel;
+    wire [P_1-1 : 0] conjestion_cmp;
+    //VC counter on all ports exept the local    
+    wire [V-1 : 0] ovc_status_per_port [P-1-1 : 0];
+    wire [CNTw -1 : 0] vc_counter [P_1-1 : 0];
+    
+    genvar i;
+    generate
+    for( i= 0;i<P_1;i=i+1) begin : P_
+    //seperate all credit counters 
+        assign ovc_status_per_port[i] = ovc_status[(i+1)*V-1 : i*V];
+        //count number of busy OVCs
+        accumulator #(
+            .INw(V),
+            .OUTw(CNTw),
+            .NUM(V)
+        ) counter (
+            .in_all(ovc_status_per_port[i]),
+            .sum_o(vc_counter[i])
+        );
+    end//for
+    endgenerate
+    /******************* 
+    * pre-sel[xy]
+    *  y
+    * 1   |   3
+    *  |
+    * ---------- x
+    * 0   |   2
+    *  |    
+    * 
+    * pre_sel
+    *  0: xdir is preferable
+    *  1: ydir is preferable
+    *******************/
+    //location in counter  
+    localparam 
+        X_PLUS = 0,//EAST
+        Y_PLUS = 1,//NORTH
+        X_MINUS = 2,//WEST
+        Y_MINUS = 3;//SOUTH
+    //location in port-pre-select           
+    localparam 
+        X_PLUS_Y_PLUS = 3,
+        X_MINUS_Y_PLUS = 1,
+        X_PLUS_Y_MINUS = 2,
+        X_MINUS_Y_MINUS= 0;
+    
+    assign conjestion_cmp[X_PLUS_Y_PLUS] = (vc_counter[X_PLUS] >  vc_counter[Y_PLUS]);
+    assign conjestion_cmp[X_MINUS_Y_PLUS] = (vc_counter[X_MINUS] >  vc_counter[Y_PLUS]);
+    assign conjestion_cmp[X_PLUS_Y_MINUS] = (vc_counter[X_PLUS] >  vc_counter[Y_MINUS]);
+    assign conjestion_cmp[X_MINUS_Y_MINUS]= (vc_counter[X_MINUS] >  vc_counter[Y_MINUS]);
+    //assign port_pre_sel = conjestion_cmp;
+    assign port_pre_sel = conjestion_cmp;
+endmodule
+
+/*************************************
+* port_presel_based_dst_ports_credit
+*        CONGESTION_INDEX==1
+*************************************/
+//congestion analyzer based on number of total available credit of a port
+module  port_presel_based_dst_ports_credit #(
+    parameter P = 5
+)(
+    credit_decreased_all,
+    credit_increased_all,
+    port_pre_sel,
+    clk,
+    reset
+);
+    import pronoc_pkg::*; 
+    localparam  
+        P_1 = P-1,
+        P_1V = (P_1)*V,
+        BV = B*V,
+        BV_1 = BV-1,
+        BVw = log2(BV);
+    localparam [BVw-1 : 0] C_INT = BV_1 [BVw-1 : 0]; 
+    
+    input [P_1V-1 : 0] credit_decreased_all;  
+    input [P_1V-1 : 0] credit_increased_all; 
+    input             reset,clk;
+    output [PPSw-1 : 0] port_pre_sel;
+    
+    logic [BVw-1 : 0] credit_per_port_next [P_1-1 : 0];
+    logic [BVw-1 : 0] credit_per_port [P_1-1 : 0];
+    wire [P_1-1 : 0] credit_increased_per_port;
+    wire [P_1-1 : 0] credit_decreased_per_port;
+    wire [P_1-1 : 0] conjestion_cmp;
+    
+    genvar i;
+    generate   
+    for(i=0;   i<P_1; i=i+1) begin : P_           
+        assign  credit_increased_per_port[i]=|credit_increased_all[((i+1)*V)-1 : i*V];
+        assign  credit_decreased_per_port[i]=|credit_decreased_all[((i+1)*V)-1 : i*V];
+        always_ff @ (`pronoc_clk_reset_edge )begin 
+            if(`pronoc_reset) begin     
+                credit_per_port[i] <= BVw'(C_INT);
+            end else begin
+                credit_per_port[i] <= credit_per_port_next[i];
+            end
+        end
+    end//for
+    
+    for(i=0; i<P; i=i+1) begin :blk1
+        always @(*) begin
+            credit_per_port_next[i] = credit_per_port[i];
+            if(credit_increased_per_port[i] & ~credit_decreased_per_port[i]) begin 
+                credit_per_port_next[i] = credit_per_port[i]+1'b1;
+            end else if (~credit_increased_per_port[i] & credit_decreased_per_port[i])begin 
+                credit_per_port_next[i] = credit_per_port[i]-1'b1;
+            end
+        end//for
+    end//always
+    endgenerate
+    //location in counter  
+    localparam 
+        X_PLUS = 0,//EAST
+        Y_PLUS = 1,//NORTH
+        X_MINUS = 2,//WEST
+        Y_MINUS = 3;//SOUTH
+    //location in port-pre-select           
+    localparam 
+        X_PLUS_Y_PLUS = 3,
+        X_MINUS_Y_PLUS = 1,
+        X_PLUS_Y_MINUS = 2,
+        X_MINUS_Y_MINUS= 0;
+    
+    assign conjestion_cmp[X_PLUS_Y_PLUS] = (credit_per_port[X_PLUS] <  credit_per_port[Y_PLUS]);
+    assign conjestion_cmp[X_MINUS_Y_PLUS] = (credit_per_port[X_MINUS] <  credit_per_port[Y_PLUS]);
+    assign conjestion_cmp[X_PLUS_Y_MINUS] = (credit_per_port[X_PLUS] <  credit_per_port[Y_MINUS]);
+    assign conjestion_cmp[X_MINUS_Y_MINUS]= (credit_per_port[X_MINUS] <  credit_per_port[Y_MINUS]);
+    // assign port_pre_sel = conjestion_cmp;
+    assign port_pre_sel = conjestion_cmp;
+endmodule  
+
+
+/*********************************
+* port_presel_based_dst_routers_ovc
+* CONGESTION_INDEX==2,3,4,5,6,7,9
+********************************/ 
+module regular_topo_port_presel_based_dst_routers_vc #(
+    parameter P=5
+)(
+    port_pre_sel,    
+    congestion_in_all,
+    reset,clk
+);
+    import pronoc_pkg::*;
+    localparam  CONG_ALw = CONGw* P;   //  congestion width per router;
+    localparam XDIR =1'b0;
+    localparam YDIR =1'b1;
+    //location in port-pre-select           
+    localparam 
+        X_PLUS_Y_PLUS = 3,
+        X_MINUS_Y_PLUS = 1,
+        X_PLUS_Y_MINUS = 2,
+        X_MINUS_Y_MINUS= 0;            
+    input [CONG_ALw-1 : 0] congestion_in_all;
+    output reg [PPSw-1 : 0] port_pre_sel;
+    input reset,clk;
+    wire [CONGw-1 : 0] congestion_x_plus,congestion_y_plus,congestion_x_min,congestion_y_min;
+    wire [PPSw-1 : 0] conjestion_cmp;
+    
+    assign {congestion_y_min,congestion_x_min,congestion_y_plus,congestion_x_plus} = congestion_in_all[(CONGw*5)-1 : CONGw];
+    /****************
+    * congestion: 
+    *      0: list congested
+    *      3: most congested
+    * pre_sel
+    *      0: xdir
+    *      1: ydir
+    *******************/
+    assign conjestion_cmp[X_PLUS_Y_PLUS] = (congestion_x_plus  >  congestion_y_plus)? YDIR : XDIR;
+    assign conjestion_cmp[X_MINUS_Y_PLUS] = (congestion_x_min   >  congestion_y_plus)? YDIR : XDIR;
+    assign conjestion_cmp[X_PLUS_Y_MINUS] = (congestion_x_plus  >  congestion_y_min)?  YDIR : XDIR;
+    assign conjestion_cmp[X_MINUS_Y_MINUS]= (congestion_x_min   >  congestion_y_min)?  YDIR : XDIR;
+    // assign port_pre_sel = conjestion_cmp;
+    always_ff @ (`pronoc_clk_reset_edge )begin 
+        if(`pronoc_reset) begin
+            port_pre_sel <= {PPSw{1'b0}};
+        end else begin
+            port_pre_sel <= conjestion_cmp;
+        end
+    end
+endmodule
+
+
+/*********************************
+* port_presel_based_dst_routers_ovc
+* CONGESTION_INDEX==8,10
+********************************/ 
+module port_presel_based_dst_routers_ovc #(
+    parameter P=5
+)(
+    port_pre_sel,    
+    congestion_in_all   
+);
+    import pronoc_pkg::*;
+    localparam  
+        P_1 = P-1,
+        CONG_ALw = CONGw* P;   //  congestion width per router;
+    
+    input [CONG_ALw-1 : 0] congestion_in_all;
+    output [PPSw-1 : 0] port_pre_sel;    
+    /*************
+    *  N
+    * Q1 | Q3
+    * w--------E
+    * Q0 | Q2
+    *  S
+    ***************/
+    localparam 
+        Q3 = 3,
+        Q1 = 1,
+        Q2 = 2,
+        Q0 = 0;  
+        
+    localparam 
+        XDIR =1'b0,
+        YDIR =1'b1;
+    wire [CONGw-1 : 0] congestion_in [P-1 : 0];   
+    genvar i;
+    generate
+        for(i=0;i<P;i=i+1) begin :P_
+            assign congestion_in[i] = congestion_in_all[CONGw*(i+1)-1 : CONGw*i];
+        end         
+    endgenerate
+    
+    wire [(CONGw/2)-1 : 0]cong_from_west_Q1   , cong_from_west_Q0;
+    wire [(CONGw/2)-1 : 0]cong_from_south_Q0  , cong_from_south_Q2;
+    wire [(CONGw/2)-1 : 0]cong_from_east_Q2   , cong_from_east_Q3; 
+    wire [(CONGw/2)-1 : 0]cong_from_north_Q3  , cong_from_north_Q1;
+    
+    assign {cong_from_west_Q1   ,cong_from_west_Q0  }=congestion_in[WEST];
+    assign {cong_from_south_Q0  ,cong_from_south_Q2 }=congestion_in[SOUTH];
+    assign {cong_from_east_Q2   ,cong_from_east_Q3  }=congestion_in[EAST];
+    assign {cong_from_north_Q3  ,cong_from_north_Q1 }=congestion_in[NORTH];
+    /****************
+    *congestion: 
+    *      0: list congested
+    *      3: most congested
+    *pre_sel
+    *      0: xdir
+    *      1: ydir
+    ********************/
+    wire [P_1-1 : 0] conjestion_cmp;
+    assign conjestion_cmp[Q3] = (cong_from_east_Q3  >  cong_from_north_Q3)? YDIR :XDIR;
+    assign conjestion_cmp[Q2] = (cong_from_east_Q2  >  cong_from_south_Q2)? YDIR :XDIR;
+    assign conjestion_cmp[Q1] = (cong_from_west_Q1  >  cong_from_north_Q1)? YDIR :XDIR;
+    assign conjestion_cmp[Q0] = (cong_from_west_Q0  >  cong_from_south_Q0)? YDIR :XDIR;
+    assign port_pre_sel = conjestion_cmp;
+endmodule
+
+/***********************
+* port_pre_sel_gen
+************************/
+module port_pre_sel_gen #(
+    parameter P=5
+)(
+    port_pre_sel,
+    ovc_status,
+    congestion_in_all,
+    credit_decreased_all,
+    credit_increased_all,
+    reset,
+    clk
+);
+    import pronoc_pkg::*;
+    localparam 
+        PV = P * V,
+        CONG_ALw = CONGw * P;
+    output [PPSw-1 : 0] port_pre_sel;
+    input [PV-1 : 0] ovc_status;
+    input [PV-1 : 0] credit_decreased_all;
+    input [PV-1 : 0] credit_increased_all;
+    input [CONG_ALw-1 : 0] congestion_in_all;  
+    input reset,clk;
+    
+    generate
+    if( IS_DETERMINISTIC ) begin : detrministic
+        assign port_pre_sel = {PPSw{1'b0}};
+    end else begin : adaptive
+        if(CONGESTION_INDEX==0) begin:indx0
+            port_presel_based_dst_ports_vc #(
+                .P(P)
+            ) port_presel_gen (
+                .ovc_status (ovc_status [PV-1 : V]),
+                .port_pre_sel(port_pre_sel)
+            );
+        end else if(CONGESTION_INDEX==1) begin :indx1
+            port_presel_based_dst_ports_credit #(
+                .P(P)
+            ) port_presel_gen (
+                .credit_decreased_all (credit_decreased_all [PV-1 : V]),//remove local port signals
+                .credit_increased_all(credit_increased_all [PV-1 : V]),
+                .port_pre_sel(port_pre_sel),
+                .clk(clk),
+                .reset(reset)
+            );
+        end else if (
+            (CONGESTION_INDEX==2) || (CONGESTION_INDEX==3) ||
+            (CONGESTION_INDEX==4) || (CONGESTION_INDEX==5) ||
+            (CONGESTION_INDEX==6) || (CONGESTION_INDEX==7) || 
+            (CONGESTION_INDEX==9) ||
+            (CONGESTION_INDEX==11)|| (CONGESTION_INDEX==12))      begin :dst_vc
+            regular_topo_port_presel_based_dst_routers_vc #(
+                .P(P)
+            ) port_presel_gen (
+                .congestion_in_all(congestion_in_all),
+                .port_pre_sel(port_pre_sel),
+                .reset(reset),
+                .clk(clk)
+            );
+        end else if((CONGESTION_INDEX==8) || (CONGESTION_INDEX==10) )begin :dst_ovc
+            port_presel_based_dst_routers_ovc #(
+                .P(P)
+            ) port_presel_gen (
+                .port_pre_sel(port_pre_sel),
+                .congestion_in_all(congestion_in_all)
+            );
+        end 
+    end 
+    endgenerate
+endmodule
+
+/*******************************
+*   congestion based on number of active ivc 
+*       CONGESTION_INDEX==2  CONGw = 2
+*       CONGESTION_INDEX==3  CONGw = 3
+* ********************************/
+module congestion_out_based_ivc_req #(
+    parameter P=5
+)(
+    ivc_request_all,
+    congestion_out_all  
+);
+    import pronoc_pkg::*;
+    localparam  
+        PV = (V*P),
+        CONG_ALw = (CONGw* P);   //  congestion width per router;
+    
+    input [PV-1 : 0] ivc_request_all;
+    output [CONG_ALw-1 : 0] congestion_out_all;
+    wire [CONGw-1 : 0] congestion_out ;
+    
+    parallel_count_normalize #(
+        .INw (PV),
+        .OUTw (CONGw) 
+    ) ivc_req_counter  (
+        .D_in(ivc_request_all),
+        .Q_out(congestion_out)
+    );
+    
+    assign  congestion_out_all = {P{congestion_out}};     
+endmodule
+
+/*******************************
+*    congestion based on number of
+* active ivc requests that are not granted    
+*     CONGESTION_INDEX==4  CONGw = 2
+*     CONGESTION_INDEX==5  CONGw = 3
+ ********************************/
+module congestion_out_based_ivc_notgrant #(
+    parameter P=5
+)(
+    ivc_request_all,
+    congestion_out_all,
+    ivc_num_getting_sw_grant,
+    clk,
+    reset  
+);
+    import pronoc_pkg::*;
+    localparam  
+        PV = (V * P),
+        CONG_ALw = CONGw* P,   //  congestion width per router;
+        IVC_CNTw = log2(PV+1);
+    
+    input [PV-1 : 0] ivc_request_all,ivc_num_getting_sw_grant; 
+    output [CONG_ALw-1 : 0] congestion_out_all;                 
+    input clk,reset;
+    
+    wire [IVC_CNTw-1 : 0] ivc_req_num;
+    reg [CONGw-1 : 0] congestion_out ; 
+    logic [PV-1 : 0] ivc_request_not_granted; 
+    always_ff @ (`pronoc_clk_reset_edge )begin 
+        if(`pronoc_reset) begin 
+            ivc_request_not_granted <= {PV{1'b0}};
+        end else begin
+            ivc_request_not_granted <= ivc_request_all & ~ivc_num_getting_sw_grant;
+        end
+    end
+    
+    accumulator #(
+        .INw(PV),
+        .OUTw(IVC_CNTw),
+        .NUM(PV)
+    ) ivc_req_counter (
+        .in_all(ivc_request_not_granted),
+        .sum_o(ivc_req_num)
+    );
+    
+    generate 
+    if(CONGw==2)begin :w2
+        always @(*)begin
+            if      (ivc_req_num <= (PV/10) )   congestion_out=2'd0;    //0~10
+            else if (ivc_req_num <= (PV/5)  )   congestion_out=2'd1;    //10~20
+            else if (ivc_req_num <= (PV/2)  )   congestion_out=2'd2;    //20~50
+            else                                congestion_out=2'd3;    //50~100
+        end
+    end else begin :w3 // CONGw==3
+        always @(*)begin
+            if      (ivc_req_num < ((PV*1)/8) )   congestion_out=3'd0;    
+            else if (ivc_req_num < ((PV*2)/8) )   congestion_out=3'd1;    
+            else if (ivc_req_num < ((PV*3)/8) )   congestion_out=3'd2;    
+            else if (ivc_req_num < ((PV*4)/8) )   congestion_out=3'd3;    
+            else if (ivc_req_num < ((PV*5)/8) )   congestion_out=3'd4;      
+            else if (ivc_req_num < ((PV*6)/8) )   congestion_out=3'd5;   
+            else if (ivc_req_num < ((PV*7)/8) )   congestion_out=3'd6;    
+            else                                  congestion_out=3'd7;     
+        end  
+    end
+    endgenerate       
+    assign  congestion_out_all = {P{congestion_out}};     
+endmodule
+
+/*******************************
+*     congestion based on number of
+* availabe ovc in all 3ports of next router   
+*     CONGESTION_INDEX==6 CONGw=2
+*     CONGESTION_INDEX==7 CONGw=3
+*********************************/
+module congestion_out_based_other_port_avb_ovc #(
+    parameter P=5
+)(
+    ovc_avalable_all,
+    congestion_out_all   
+);
+    import pronoc_pkg::*;
+    localparam
+        PV = (V * P),
+        CONG_ALw = CONGw* P;
+        
+    input [PV-1 : 0] ovc_avalable_all; 
+    output [CONG_ALw-1 : 0] congestion_out_all;                 
+    
+    wire [PV-1 : 0] ovc_not_avb_all;
+    wire [PV-1 : 0] counter_in [P-1 : 0];
+    wire [CONGw-1 : 0] congestion_out[P-1 : 0];
+    assign  ovc_not_avb_all = ~ovc_avalable_all;
+    genvar i;
+    generate 
+    for (i=0;i<P;i=i+1) begin : P_
+        localparam [PV-1:0] MASK = 
+            (i==LOCAL) ? '0 : 
+            {PV{1'b1}} & ~({V{1'b1}}) & ~({V{1'b1}} << (i));//mask local and cuurent port
+            assign counter_in[i] = ovc_not_avb_all & MASK;
+        parallel_count_normalize #(
+            .INw(PV),
+            .MAX_IN(PV - 2*V),
+            .OUTw(CONGw)
+        )  ovc_avb_east  (
+            .D_in(counter_in[i]),
+            .Q_out(congestion_out_all[CONGw*i +: CONGw])
+        );   
+    end
+    endgenerate
+endmodule
+
+/*******************************
+*     congestion based on number of
+* availabe ovc in destination router   
+*     CONGESTION_INDEX==8  CONGw=2
+********************************/
+module congestion_out_based_avb_ovc_w2 #(
+    parameter P=5
+)(
+    ovc_avalable_all,
+    congestion_out_all   
+);
+    import pronoc_pkg::*;
+    localparam 
+        CONGw=2, //congestion width per port
+        P_1 = P-1,
+        PV = (V * P),
+        CONG_ALw = CONGw* P,
+        CNT_Iw = 2*V;    
+    input [PV-1 : 0] ovc_avalable_all; 
+    output [CONG_ALw-1 : 0] congestion_out_all;                 
+    
+    localparam 
+        Q3 = 3,
+        Q1 = 1,
+        Q2 = 2,
+        Q0 = 0;  
+    
+    wire [V-1 : 0] ovc_not_avb [P-1 : 0];
+    wire [CNT_Iw-1 : 0] counter_in [P_1-1 : 0];
+    wire [CONGw-1 : 0] congestion_out [P-1 : 0];
+    wire [P_1-1 : 0] threshold;
+    assign  {ovc_not_avb[SOUTH], ovc_not_avb[WEST], ovc_not_avb[NORTH],  ovc_not_avb[EAST],ovc_not_avb[LOCAL]}= ~ovc_avalable_all;  
+    assign  counter_in[Q3] ={ovc_not_avb[EAST ],ovc_not_avb[NORTH]};
+    assign  counter_in[Q1] ={ovc_not_avb[NORTH],ovc_not_avb[WEST ]};
+    assign  counter_in[Q2] ={ovc_not_avb[SOUTH],ovc_not_avb[EAST ]};
+    assign  counter_in[Q0] ={ovc_not_avb[WEST ],ovc_not_avb[SOUTH]};
+    genvar i;
+    generate
+    for (i=0;i<4;i=i+1) begin :lp
+        parallel_count_normalize #(
+            .INw(CNT_Iw),
+            .OUTw(1)
+        ) ovc_not_avb_cnt (
+            .D_in(counter_in[i]),
+            .Q_out(threshold[i])
+        );   
+    end
+    endgenerate
+    assign congestion_out[LOCAL] = '0;
+    assign congestion_out[EAST]  = {threshold[Q1],threshold[Q0]};
+    assign congestion_out[NORTH] = {threshold[Q0],threshold[Q2]};
+    assign congestion_out[WEST]  = {threshold[Q2],threshold[Q3]};
+    assign congestion_out[SOUTH] = {threshold[Q3],threshold[Q1]};
+    assign congestion_out_all    = {congestion_out[SOUTH],congestion_out[WEST],congestion_out[NORTH],congestion_out[EAST],congestion_out[LOCAL]};   
+endmodule
+
+/*******************************
+* 
+*     congestion based on number of
+* availabe ovc in destination router   
+*     CONGESTION_INDEX==9  CONGw=3
+*********************************/
+module congestion_out_based_avb_ovc_w3 #(
+    parameter P=5
+)(
+    ovc_avalable_all,
+    congestion_out_all   
+);
+    import pronoc_pkg::*;
+    localparam 
+        CONGw=3, //congestion width per port
+        P_1 = P-1,
+        PV = (V * P),
+        CONG_ALw = CONGw* P;
+        
+    input [PV-1 : 0] ovc_avalable_all; 
+    output [CONG_ALw-1 : 0] congestion_out_all;                 
+    
+    wire [V-1 : 0] ovc_not_avb [P-1 : 0];
+    wire [CONGw-1 : 0] congestion_out[P-1 : 0];
+    wire [P_1-1 : 0] threshold;
+    assign  {ovc_not_avb[SOUTH],  ovc_not_avb[WEST], ovc_not_avb[NORTH],   ovc_not_avb[EAST]}=~ovc_avalable_all[PV-1 : V];
+    genvar i;
+    generate 
+    for (i=0;i<4;i=i+1) begin :lp
+        parallel_count_normalize #(
+            .INw(V),
+            .OUTw(1)
+        ) ovc_avb_east(
+            .D_in(ovc_not_avb[i]),
+            .Q_out(threshold[i])
+        );   
+    end
+    endgenerate
+    
+    assign congestion_out[EAST] = {threshold[NORTH],threshold[WEST ],threshold[SOUTH]};
+    assign congestion_out[NORTH] = {threshold[WEST ],threshold[SOUTH],threshold[EAST ]};
+    assign congestion_out[WEST] = {threshold[SOUTH],threshold[EAST ],threshold[NORTH]};
+    assign congestion_out[SOUTH] = {threshold[EAST ],threshold[NORTH],threshold[WEST ]};
+    assign  congestion_out_all = {congestion_out[SOUTH],congestion_out[WEST],congestion_out[NORTH],congestion_out[EAST],{CONGw{1'b0}}};   
+endmodule
+
+/*******************************
+*     congestion based on number of
+* availabe ovc in destination router   
+*     CONGESTION_INDEX==10  CONGw=4
+*********************************/
+module congestion_out_based_avb_ovc_w4 #(
+    parameter P=5
+)(
+    ovc_avalable_all,
+    congestion_out_all   
+);
+    import pronoc_pkg::*;
+    localparam 
+        CONGw=4, //congestion width per port
+        P_1 = P-1,
+        PV = (V * P),
+        CONG_ALw = CONGw* P,
+        CNT_Iw = 2*V;    
+    input [PV-1 : 0] ovc_avalable_all; 
+    output [CONG_ALw-1 : 0] congestion_out_all;                 
+    
+    localparam
+        Q3 = 3,
+        Q1 = 1,
+        Q2 = 2,
+        Q0 = 0;  
+    
+    wire [V-1 : 0] ovc_not_avb [P-1 : 0];
+    wire [CNT_Iw-1 : 0] counter_in [P_1-1 : 0];
+    wire [CONGw-1 : 0] congestion_out [P-1 : 0];
+    wire [1 : 0] threshold [P_1-1 : 0];
+    assign  {ovc_not_avb[SOUTH], ovc_not_avb[WEST], ovc_not_avb[NORTH],  ovc_not_avb[EAST],ovc_not_avb[LOCAL]}= ~ovc_avalable_all;  
+    assign  counter_in[Q3] ={ovc_not_avb[EAST ],ovc_not_avb[NORTH]};
+    assign  counter_in[Q1] ={ovc_not_avb[NORTH],ovc_not_avb[WEST ]};
+    assign  counter_in[Q2] ={ovc_not_avb[SOUTH],ovc_not_avb[EAST ]};
+    assign  counter_in[Q0] ={ovc_not_avb[WEST ],ovc_not_avb[SOUTH]};
+    genvar i;
+    generate
+    for (i=0;i<4;i=i+1) begin :lp
+        parallel_count_normalize #(
+            .INw(CNT_Iw),
+            .OUTw(2)
+        ) ovc_not_avb_cnt (
+            .D_in(counter_in[i]),
+            .Q_out(threshold[i])
+        );   
+    end
+    endgenerate
+    assign congestion_out[LOCAL] = '0;
+    assign congestion_out[EAST] = {threshold[Q1],threshold[Q0]};
+    assign congestion_out[NORTH] = {threshold[Q0],threshold[Q2]};
+    assign congestion_out[WEST] = {threshold[Q2],threshold[Q3]};
+    assign congestion_out[SOUTH] = {threshold[Q3],threshold[Q1]};
+    assign congestion_out_all = {congestion_out[SOUTH],congestion_out[WEST],congestion_out[NORTH],congestion_out[EAST],congestion_out[LOCAL]};   
+endmodule
+
+
+/*******************************
+*    congestion based on number of 
+*    availabe ovc and not granted
+*        ivc in next router  
+*    CONGESTION_INDEX==11 CONGw=2
+*    CONGESTION_INDEX==12 CONGw=3
+*********************************/
+module congestion_out_based_avb_ovc_not_granted_ivc #(
+    parameter P=5
+)(
+    ovc_avalable_all,
+    ivc_request_all,
+    ivc_num_getting_sw_grant,
+    clk,
+    reset,    
+    congestion_out_all   
+);
+    import pronoc_pkg::*;
+    localparam
+        P_1 = P-1,
+        PV = (V * P),
+        CONG_ALw = CONGw* P,
+        CNT_Iw = 3*V,
+        CNT_Ow = log2((3*V)+1),
+        CNG_w = log2((6*V)+1),
+        CNT_Vw = log2(V+1);
+        
+    input [PV-1 : 0] ovc_avalable_all; 
+    output [CONG_ALw-1 : 0] congestion_out_all;                 
+    input [PV-1 : 0] ivc_request_all,ivc_num_getting_sw_grant; 
+    input                    reset,clk;
+    // counting not available ovc            
+    wire [V-1 : 0] ovc_not_avb [P-1 : 0];
+    wire [CNT_Iw-1 : 0] counter_in [P-1 : 0];
+    wire [CNT_Ow-1 : 0] counter_o [P-1 : 0];
+    wire [CONGw-1 : 0] congestion_out[P-1 : 0];
+    assign  {ovc_not_avb[SOUTH], ovc_not_avb[WEST], ovc_not_avb[NORTH],  ovc_not_avb[EAST],ovc_not_avb[LOCAL]}= ~ovc_avalable_all;  
+    assign  counter_in[LOCAL] ='0;
+    assign  counter_in[EAST] ={ovc_not_avb[NORTH],ovc_not_avb[WEST] ,ovc_not_avb[SOUTH]};
+    assign  counter_in[NORTH] ={ovc_not_avb[EAST] ,ovc_not_avb[WEST] ,ovc_not_avb[SOUTH]};
+    assign  counter_in[WEST] ={ovc_not_avb[EAST] ,ovc_not_avb[NORTH] ,ovc_not_avb[SOUTH]};
+    assign  counter_in[SOUTH] ={ovc_not_avb[EAST] ,ovc_not_avb[NORTH] ,ovc_not_avb[WEST]};
+    
+    // counting not granted requests
+    logic [PV-1 : 0] ivc_request_not_granted; 
+    wire [V-1 : 0] ivc_not_grnt [P-1 : 0];
+    wire [CNT_Vw-1 : 0] ivc_not_grnt_num [P-1 : 0];
+    
+    always_ff @ (`pronoc_clk_reset_edge )begin 
+        if(`pronoc_reset) begin 
+            ivc_request_not_granted <= {PV{1'b0}};
+        end else begin
+            ivc_request_not_granted <= ivc_request_all & ~ivc_num_getting_sw_grant;
+        end
+    end
+    
+    assign  {ivc_not_grnt[SOUTH], ivc_not_grnt[WEST], ivc_not_grnt[NORTH],ivc_not_grnt[EAST],ivc_not_grnt[LOCAL]}= ivc_request_not_granted;  
+    genvar i;
+    generate 
+    for (i=0;i<P;i=i+1) begin :P_
+        accumulator #(
+            .INw(CNT_Iw),
+            .OUTw(CNT_Ow),
+            .NUM(CNT_Iw)
+        ) ovc_counter (
+            .in_all(counter_in[i]),
+            .sum_o(counter_o[i])
+        );
+        accumulator #(
+            .INw(V),
+            .OUTw(CNT_Vw),
+            .NUM(V)
+        ) ivc_counter (
+            .in_all(ivc_not_grnt[i]),
+            .sum_o(ivc_not_grnt_num[i])
+        );
+        wire [CNG_w-1 : 0] congestion_num [P-1 : 0];
+        assign congestion_num [i] = counter_o[i] + ivc_not_grnt_num[i] + {ivc_not_grnt_num[i],1'b0};
+        normalizer #(
+            .MAX_IN(6*V),
+            .INw(CNG_w),
+            .OUTw(CONGw)
+        )norm (
+            .D_in(congestion_num [i]),
+            .Q_out(congestion_out[i])
+        );
+    end//for
+    endgenerate
+    assign  congestion_out_all = {congestion_out[SOUTH],congestion_out[WEST],congestion_out[NORTH],congestion_out[EAST],{CONGw{1'b0}}};   
+endmodule
+
+/**********************
+*    parallel_count_normalize
+**********************/
+module parallel_count_normalize #(
+    parameter INw = 12,
+    parameter MAX_IN=INw,
+    parameter OUTw= 2
+)(
+    D_in,
+    Q_out
+);
+    function integer log2;
+    input integer number; begin   
+        log2=(number <=1) ? 1: 0;    
+        while(2**log2<number) begin    
+            log2=log2+1;    
+        end        
+    end   
+    endfunction // log2 
+    
+    input [INw-1 : 0] D_in;
+    output [OUTw-1 : 0] Q_out;
+    localparam CNTw = log2(INw+1);
+    wire [CNTw-1 : 0] counter;
+    accumulator #(
+        .INw(INw),
+        .OUTw(CNTw),
+        .NUM(INw)
+    ) ovc_avb_cnt (
+        .in_all(D_in),
+        .sum_o(counter)
+    );
+    
+    normalizer #(
+        .MAX_IN(MAX_IN),
+        .INw(CNTw),
+        .OUTw(OUTw)
+    )norm (
+        .D_in(counter),
+        .Q_out(Q_out)
+    );
+endmodule    
+
+/**************
+*   normalizer
+***************/
+module normalizer #(
+    parameter INw   = 5,
+    parameter MAX_IN = 10,
+    parameter OUTw  = 2
+)(
+    input  logic [INw-1:0] D_in,
+    output logic [OUTw-1:0] Q_out
+);
+    localparam OUT_ON_HOT_NUM = 2 ** OUTw;
+    localparam [INw-1 : 0] MAX = (MAX_IN > (2**INw)-1) ? {INw{1'b1}} : INw'(MAX_IN);
+    // One-hot output
+    logic [OUT_ON_HOT_NUM-1:0] one_hot_out;
+    // Saturate input
+    logic [INw-1:0] D_clamped;
+    assign D_clamped = (D_in > MAX) ? MAX : D_in;
+    // Generate one-hot bins
+    genvar i;
+    generate
+    for (i = 0; i < OUT_ON_HOT_NUM; i++) begin : BIN_GEN
+        localparam LOW  = (MAX_IN * i)     / OUT_ON_HOT_NUM;
+        localparam HIGH = (MAX_IN * (i+1)) / OUT_ON_HOT_NUM;
+        assign one_hot_out[i] =
+            (i == 0) ?  (D_clamped < INw'(HIGH)) :   // first bin: include MIN_IN
+            (i == OUT_ON_HOT_NUM-1) ?  (D_clamped >= INw'(LOW)) :   // last bin: include MAX_IN
+            (D_clamped >= INw'(LOW)) && (D_clamped < INw'(HIGH));
+    end
+    endgenerate
+    // Convert one-hot to binary
+    one_hot_to_bin #(
+        .ONE_HOT_WIDTH(OUT_ON_HOT_NUM)
+    ) cnv (
+        .one_hot_code(one_hot_out),
+        .bin_code(Q_out)
+    );
+endmodule
+
+
+
+/**************************
+*    congestion_out_gen
+*************************/
+module congestion_out_gen #(
+    parameter P=5
+)(
+    ivc_request_all, 
+    ivc_num_getting_sw_grant,
+    ovc_avalable_all,
+    congestion_out_all,
+    clk,
+    reset
+);
+    import pronoc_pkg::*;
+    localparam 
+        PV = P*V,
+        CONG_ALw = CONGw* P;   //  congestion width per router;;
+    
+    input [PV-1 : 0] ovc_avalable_all; 
+    input [PV-1 : 0] ivc_request_all;    
+    input [PV-1 : 0] ivc_num_getting_sw_grant; 
+    output reg [CONG_ALw-1 : 0] congestion_out_all;                 
+    input clk,reset;
+    
+    wire [CONG_ALw-1 : 0] congestion_out_all_next;  
+    wire [V-1 : 0] ovc_avalable [P-1 : 0];
+    genvar i;
+    generate
+    for (i=0;i<P;i=i+1) begin :lp
+        assign ovc_avalable[i]= ovc_avalable_all[(i*V)+:V];
+    end
+    if(ROUTE_TYPE != "DETERMINISTIC") begin :adpt
+        if((CONGESTION_INDEX==2) || (CONGESTION_INDEX==3)) begin :based_ivc
+            congestion_out_based_ivc_req #(
+                .P(P)
+            ) the_congestion_out_gen (
+                .ivc_request_all(ivc_request_all),
+                .congestion_out_all(congestion_out_all_next)
+            );
+        end else if((CONGESTION_INDEX==4) || (CONGESTION_INDEX==5)) begin :based_ng_ivc
+            congestion_out_based_ivc_notgrant #(
+                .P(P)
+            )  the_congestion_out_gen (
+                .ivc_num_getting_sw_grant(ivc_num_getting_sw_grant),
+                .ivc_request_all(ivc_request_all),
+                .congestion_out_all(congestion_out_all_next),
+                .clk(clk),
+                .reset(reset)
+            );
+        end else if  ((CONGESTION_INDEX==6) || (CONGESTION_INDEX==7)) begin :avb_ovc1
+            congestion_out_based_other_port_avb_ovc#(
+                .P(P)
+            ) the_congestion_out_gen (      
+                .ovc_avalable_all(ovc_avalable_all),
+                .congestion_out_all(congestion_out_all_next)
+            );
+        end  else if  (CONGESTION_INDEX==8) begin :indx8
+            congestion_out_based_avb_ovc_w2 #(
+                .P(P)
+            ) the_congestion_out_gen (
+                .ovc_avalable_all(ovc_avalable_all),
+                .congestion_out_all(congestion_out_all_next)   
+            );
+        end  else if  (CONGESTION_INDEX==9) begin :indx9
+            congestion_out_based_avb_ovc_w3 #(
+                .P(P)
+            ) the_congestion_out_gen (
+                .ovc_avalable_all(ovc_avalable_all),
+                .congestion_out_all(congestion_out_all_next)   
+            );
+        end  else if  (CONGESTION_INDEX==10) begin :indx10
+            congestion_out_based_avb_ovc_w4 #(
+                .P(P)
+            ) the_congestion_out_gen (
+                .ovc_avalable_all(ovc_avalable_all),
+                .congestion_out_all(congestion_out_all_next)
+            );
+        end  else if  (CONGESTION_INDEX==11 || CONGESTION_INDEX==12) begin :indx11
+            congestion_out_based_avb_ovc_not_granted_ivc #(
+                .P(P)
+            ) the_congestion_out_gen (
+                .ovc_avalable_all(ovc_avalable_all),
+                .ivc_request_all(ivc_request_all),
+                .ivc_num_getting_sw_grant(ivc_num_getting_sw_grant),
+                .clk(clk),
+                .reset(reset),    
+                .congestion_out_all(congestion_out_all_next)
+            );
+        end  else begin :nocong assign  congestion_out_all_next = {CONG_ALw{1'b0}};   end
+    end else begin :dtrmn
+        assign  congestion_out_all_next = {CONG_ALw{1'b0}};
+    end
+    endgenerate
+    always_ff @ (`pronoc_clk_reset_edge )begin 
+        if(`pronoc_reset) begin 
+            congestion_out_all <= {CONG_ALw{1'b0}};
+        end else begin
+            congestion_out_all <= congestion_out_all_next;
+        end
+    end
+endmodule
+
+
+/*************************
+*    deadlock_detector
+**************************/
+module  deadlock_detector #(
+    parameter P=5,
+    parameter MAX_CLK = 16
+)(
+    ivc_num_getting_sw_grant,
+    ivc_request_all,
+    reset,
+    clk,
+    detect
+);
+    import pronoc_pkg::*;
+    localparam  
+        PV = P*V,
+        CNTw = log2(MAX_CLK);
+    input [PV-1 : 0] ivc_num_getting_sw_grant, ivc_request_all;
+    input      reset,clk;
+    output       detect;
+    
+    logic [CNTw-1 : 0] counter [V-1 : 0];
+    reg [CNTw-1 : 0] counter_next [V-1 : 0];
+    wire [P-1 : 0] counter_rst_gen [V-1 : 0];
+    wire [P-1 : 0] counter_en_gen [V-1 : 0];
+    wire [V-1 : 0] counter_rst,counter_en,detect_gen;
+    logic [PV-1 : 0] ivc_num_getting_sw_grant_reg;
+    always_ff @ (`pronoc_clk_reset_edge )begin 
+        if(`pronoc_reset) begin 
+            ivc_num_getting_sw_grant_reg <= {PV{1'b0}};
+        end else begin
+            ivc_num_getting_sw_grant_reg <= ivc_num_getting_sw_grant;
+        end
+    end
+    
+    //seperate all same virtual chanels requests
+    genvar i,j;
+    generate 
+    for (i=0;i<V;i=i+1)begin:V_
+        for (j=0;j<P;j=j+1)begin :P_
+            assign counter_rst_gen[i][j]=ivc_num_getting_sw_grant_reg[j*V+i];
+            assign counter_en_gen [i][j]=ivc_request_all[j*V+i];
+        end//j
+        //sum all signals belong to the same VC
+        assign counter_rst[i] =|counter_rst_gen[i];
+        assign counter_en[i] =|counter_en_gen [i]; 
+        // generate the counter
+        always @ (*) begin 
+            counter_next[i] = counter[i];
+            if(counter_rst[i])      counter_next[i] = {CNTw{1'b0}};
+            else if(counter_en[i])  counter_next[i] = counter[i]+1'b1;
+        end//always
+        
+        always_ff @ (`pronoc_clk_reset_edge )begin 
+            if(`pronoc_reset) begin 
+                counter[i] <= {CNTw{1'b0}};
+            end else begin
+                counter[i] <= counter_next[i];
+            end
+        end
+        // check counters value to detect deadlock
+        assign detect_gen[i] = (counter[i]== MAX_CLK-1);
+    end//i 
+    endgenerate
+    assign detect=|detect_gen;
+endmodule
diff --git a/mpsoc/rtl/src_noc/congestion_analyzer.v b/mpsoc/rtl/src_noc/congestion_analyzer.v
deleted file mode 100755
index 486e83b..0000000
--- a/mpsoc/rtl/src_noc/congestion_analyzer.v
+++ /dev/null
@@ -1,1687 +0,0 @@
-`timescale	1ns/1ps
-/**********************************************************************
-**	File:  congestion_analyzer.v
-**    
-**	Copyright (C) 2014-2017  Alireza Monemi
-**    
-**	This file is part of ProNoC 
-**
-**	ProNoC ( stands for Prototype Network-on-chip)  is free software: 
-**	you can redistribute it and/or modify it under the terms of the GNU
-**	Lesser General Public License as published by the Free Software Foundation,
-**	either version 2 of the License, or (at your option) any later version.
-**
-** 	ProNoC is distributed in the hope that it will be useful, but WITHOUT
-** 	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
-** 	or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
-** 	Public License for more details.
-**
-** 	You should have received a copy of the GNU Lesser General Public
-** 	License along with ProNoC. If not, see <http:**www.gnu.org/licenses/>.
-**
-**
-**	Description: 
-**	This file includes all files for getting congestion information and
-**	Port selection modules for supporting adaptive routing 
-**
-**************************************************************/
-
-
-
-
-                                    /*****************************
-                                    
-                                                port_presel
-                                    
-                                    *****************************/
-
-
-
-/***************************************
-        
-     port_presel_based_dst_ports_vc
-          CONGESTION_INDEX==0
-***************************************/
-
-
-//congestion analyzer based on number of occupied VCs
-module   port_presel_based_dst_ports_vc #(
-    parameter PPSw=4,
-    parameter P   =   5,
-    parameter V   =   4
-    )
-    (
-        ovc_status,
-        port_pre_sel
-     );
-     
-    
-    function integer log2;
-      input integer number; begin   
-         log2=(number <=1) ? 1: 0;    
-         while(2**log2<number) begin    
-            log2=log2+1;    
-         end 	   
-      end   
-    endfunction // log2 
-         
-    localparam  P_1     =       P-1,
-                P_1V    =       P_1*V,
-                CNTw    =       log2(V+1);
-     
-    input   [P_1V-1     :   0]  ovc_status; 
-    output  [PPSw-1      :   0]  port_pre_sel;
-    wire    [P_1-1      :   0]  conjestion_cmp;
-    //VC counter on all ports exept the local    
-    wire    [V-1        :   0]  ovc_status_per_port [P-1-1  :   0];
-    wire    [CNTw -1    :   0]  vc_counter          [P_1-1  :   0];
-    
-    genvar i;
-    generate
-        for( i= 0;i<P_1;i=i+1) begin : p_loop
-                //seperate all credit counters 
-               
-                assign ovc_status_per_port[i]   = ovc_status[(i+1)*V-1       :   i*V];
-                //count number of busy OVCs
-                accumulator #(
-                	.INw(V),
-                	.OUTw(CNTw),
-                	.NUM(V)
-                )
-                counter
-                (
-                	.in_all(ovc_status_per_port[i]),
-                	.out(vc_counter[i])
-                );
-                
-                
-                /*
-                parallel_counter #(
-                    .IN_WIDTH(V)
-                )counter
-                (
-                    .in    (ovc_status_per_port[i]),
-                    .out   (vc_counter[i])
-                );
-                */
-               
-                
-       end//for
-    endgenerate
-/*******************    
-pre-sel[xy]
-    y
-1   |   3
-    |
- -------x
-0   |   2
-    |    
-    
-    
-pre_sel
-             0: xdir is preferable
-             1: ydir is preferable
-*******************/
-
-   
-  
-    //location in counter  
-    localparam X_PLUS   =   0,//EAST
-               Y_PLUS   =   1,//NORTH
-               X_MINUS  =   2,//WEST
-               Y_MINUS  =   3;//SOUTH
-               
-    //location in port-pre-select           
-    localparam X_PLUS_Y_PLUS  = 3,
-               X_MINUS_Y_PLUS = 1,
-               X_PLUS_Y_MINUS = 2,
-               X_MINUS_Y_MINUS= 0;
-               
-    assign conjestion_cmp[X_PLUS_Y_PLUS]  = (vc_counter[X_PLUS]   >  vc_counter[Y_PLUS]);
-    assign conjestion_cmp[X_MINUS_Y_PLUS] = (vc_counter[X_MINUS]  >  vc_counter[Y_PLUS]);
-    assign conjestion_cmp[X_PLUS_Y_MINUS] = (vc_counter[X_PLUS]   >  vc_counter[Y_MINUS]);
-    assign conjestion_cmp[X_MINUS_Y_MINUS]= (vc_counter[X_MINUS]  >  vc_counter[Y_MINUS]);
-    
-    //assign port_pre_sel = conjestion_cmp;
-    
-   
-    assign port_pre_sel = conjestion_cmp;
-   
-     
-         
-     
-   
- endmodule
-         
-/*************************************
-*
-*    port_presel_based_dst_ports_credit
-*           CONGESTION_INDEX==1
-*************************************/
-
-
-//congestion analyzer based on number of total available credit of a port
-module  port_presel_based_dst_ports_credit #(
-    parameter PPSw=4,
-    parameter P =   5,
-    parameter V =   4,
-    parameter B =   4
-) 
-(
-    credit_decreased_all,
-    credit_increased_all,
-    port_pre_sel,
-    clk,
-    reset
-);
-
-
-    function integer log2;
-      input integer number; begin   
-         log2=(number <=1) ? 1: 0;    
-         while(2**log2<number) begin    
-            log2=log2+1;    
-         end 	   
-      end   
-    endfunction // log2 
-    
-    localparam  P_1     =       P-1,
-                P_1V    =       (P_1)*V,
-                BV      =       B*V,
-                BV_1    =       BV-1,
-                BVw     =       log2(BV);
-                
-   localparam [BVw-1    :   0] C_INT    =  BV_1 [BVw-1    :   0]; 
-   
-   
-   input    [P_1V-1 :   0]  credit_decreased_all;  
-   input    [P_1V-1 :   0]  credit_increased_all; 
-   input                    reset,clk;
-   output   [PPSw-1  :   0]  port_pre_sel;
-   
-   
-   
-    reg     [BVw-1  :   0]  credit_per_port_next    [P_1-1    :   0];
-    wire    [BVw-1  :   0]  credit_per_port         [P_1-1    :   0];
-    wire    [P_1-1  :   0]  credit_increased_per_port;
-    wire    [P_1-1  :   0]  credit_decreased_per_port;
-    wire    [P_1-1  :   0]  conjestion_cmp;
-  
-     
-    genvar i;
-    generate   
-        for(i=0;   i<P_1; i=i+1) begin :sep           
-           assign  credit_increased_per_port[i]=|credit_increased_all[((i+1)*V)-1   : i*V];
-           assign  credit_decreased_per_port[i]=|credit_decreased_all[((i+1)*V)-1   : i*V];
-        end//for
-      
-   
-        for(i=0;   i<P; i=i+1'b1) begin :blk1
-     always @(*) begin
-            credit_per_port_next[i]  =   credit_per_port[i];
-            if(credit_increased_per_port[i]  & ~credit_decreased_per_port[i]) begin 
-                credit_per_port_next[i]  = credit_per_port[i]+1'b1;
-            end else if (~credit_increased_per_port[i]   & credit_decreased_per_port[i])begin 
-                credit_per_port_next[i]  = credit_per_port[i]-1'b1;
-            end
-        end//for
-    end//always
-    
-  for(i=0;    i<P_1; i=i+1'b1) begin :blk2
-  
-      pronoc_register #(
-           .W(BVw),
-           .RESET_TO(C_INT)
-      ) reg1 ( 
-           .in(credit_per_port_next[i]),
-           .reset(reset),    
-           .clk(clk),      
-           .out(credit_per_port[i])
-      );
-      
-   end //for
-    
- endgenerate
-
-    /*******************    
-pre-sel[xy]
-    y
-1   |   3
-    |
- -------x
-0   |   2
-    |    
-    
-    
-pre_sel
-             0: xdir
-             1: ydir
-*******************/
-    
-    //location in counter  
-    localparam X_PLUS   =   0,//EAST
-               Y_PLUS   =   1,//NORTH
-               X_MINUS  =   2,//WEST
-               Y_MINUS  =   3;//SOUTH
-               
-    //location in port-pre-select           
-    localparam X_PLUS_Y_PLUS  = 3,
-               X_MINUS_Y_PLUS = 1,
-               X_PLUS_Y_MINUS = 2,
-               X_MINUS_Y_MINUS= 0;
-               
-    assign conjestion_cmp[X_PLUS_Y_PLUS]  = (credit_per_port[X_PLUS]   <  credit_per_port[Y_PLUS]);
-    assign conjestion_cmp[X_MINUS_Y_PLUS] = (credit_per_port[X_MINUS]  <  credit_per_port[Y_PLUS]);
-    assign conjestion_cmp[X_PLUS_Y_MINUS] = (credit_per_port[X_PLUS]   <  credit_per_port[Y_MINUS]);
-    assign conjestion_cmp[X_MINUS_Y_MINUS]= (credit_per_port[X_MINUS]  <  credit_per_port[Y_MINUS]);
-          
-  // assign port_pre_sel = conjestion_cmp;
-   
-     
-    
-     assign port_pre_sel = conjestion_cmp;
-    
-     
-    
- endmodule  
- 
- 
-/*********************************
-
-port_presel_based_dst_routers_ovc
-    CONGESTION_INDEX==2,3,4,5,6,7,9
-********************************/ 
- 
- 
-module mesh_torus_port_presel_based_dst_routers_vc #(
-    parameter PPSw=4,
-    parameter P=5,
-    parameter CONGw=2 //congestion width per port
-)
-(
-    port_pre_sel,    
-    congestion_in_all,
-    reset,clk
-);
-  
-         
-    localparam  CONG_ALw=       CONGw* P;   //  congestion width per router;
-                
-    localparam XDIR =1'b0;
-    localparam YDIR =1'b1;
-                               
-//location in port-pre-select           
-    localparam X_PLUS_Y_PLUS  = 3,
-               X_MINUS_Y_PLUS = 1,
-               X_PLUS_Y_MINUS = 2,
-               X_MINUS_Y_MINUS= 0;            
-                   
-     
-    
-    input   [CONG_ALw-1 :   0]  congestion_in_all;
-    output  [PPSw-1      :   0]  port_pre_sel;
-    input reset,clk;
-    
-    wire    [CONGw-1    :   0]  congestion_x_plus,congestion_y_plus,congestion_x_min,congestion_y_min;
-    wire    [PPSw-1      :   0]  conjestion_cmp;
-   
-    
-    assign {congestion_y_min,congestion_x_min,congestion_y_plus,congestion_x_plus} = congestion_in_all[(CONGw*5)-1   : CONGw];
-    
-/****************
-    congestion:  
-             0: list congested
-             3: most congested
-    pre_sel
-             0: xdir
-             1: ydir
-*******************/
-    assign conjestion_cmp[X_PLUS_Y_PLUS]  = (congestion_x_plus  >  congestion_y_plus)? YDIR : XDIR;
-    assign conjestion_cmp[X_MINUS_Y_PLUS] = (congestion_x_min   >  congestion_y_plus)? YDIR : XDIR;
-    assign conjestion_cmp[X_PLUS_Y_MINUS] = (congestion_x_plus  >  congestion_y_min)?  YDIR : XDIR;
-    assign conjestion_cmp[X_MINUS_Y_MINUS]= (congestion_x_min   >  congestion_y_min)?  YDIR : XDIR;
-
- 
- 
-   
-   // assign port_pre_sel = conjestion_cmp;
-   pronoc_register #(.W(PPSw)) reg1 (.in(conjestion_cmp ), .reset(reset), .clk(clk), .out(port_pre_sel));    
- 
- 
-endmodule
-
-
-/*********************************
-
-port_presel_based_dst_routers_ovc
-    CONGESTION_INDEX==8,10
-********************************/ 
- 
- 
-module port_presel_based_dst_routers_ovc #(
-    parameter PPSw=4,
-    parameter P=5,
-    parameter V=4,
-    parameter CONGw=2 //congestion width per port
-)
-(
-    port_pre_sel,    
-    congestion_in_all   
-);
-  
-         
-    localparam  P_1     =       P-1,
-                CONG_ALw=       CONGw* P;   //  congestion width per router;
-       
-    
-    input   [CONG_ALw-1 :   0]  congestion_in_all;
-    output  [PPSw-1      :   0]  port_pre_sel;    
-       
-     
-    
-  
-   /*************
-        N
-     Q1 | Q3
-   w--------E
-     Q0 | Q2
-        S
-   ***************/
-   
-    localparam Q3   = 3,
-               Q1   = 1,
-               Q2   = 2,
-               Q0   = 0;  
-
-    localparam EAST =   0,
-               NORTH=   1,
-               WEST =   2,
-               SOUTH=   3;                         
-                   
-    localparam XDIR =1'b0,
-               YDIR =1'b1;
-    
-    wire [CONGw-1   :   0] congestion_in [P_1-1 :   0];           
-    assign {congestion_in[SOUTH],congestion_in[WEST],congestion_in[NORTH],congestion_in[EAST]} = congestion_in_all[CONG_ALw-1   : CONGw];               
-   
-    wire [(CONGw/2)-1   :   0]cong_from_west_Q1   , cong_from_west_Q0;
-    wire [(CONGw/2)-1   :   0]cong_from_south_Q0  , cong_from_south_Q2;
-    wire [(CONGw/2)-1   :   0]cong_from_east_Q2   , cong_from_east_Q3; 
-    wire [(CONGw/2)-1   :   0]cong_from_north_Q3  , cong_from_north_Q1;
-    
-
-                
-    assign {cong_from_west_Q1   ,cong_from_west_Q0  }=congestion_in[WEST];
-    assign {cong_from_south_Q0  ,cong_from_south_Q2 }=congestion_in[SOUTH];
-    assign {cong_from_east_Q2   ,cong_from_east_Q3  }=congestion_in[EAST];
-    assign {cong_from_north_Q3  ,cong_from_north_Q1 }=congestion_in[NORTH];
-    
-    /****************
-    congestion:  
-             0: list congested
-             3: most congested
-    pre_sel
-             0: xdir
-             1: ydir
-    *******************/            
-     wire    [P_1-1      :   0]  conjestion_cmp;
-     
-     
- 
-    assign conjestion_cmp[Q3]  =  (cong_from_east_Q3  >  cong_from_north_Q3)? YDIR :XDIR;
-    assign conjestion_cmp[Q2]  =  (cong_from_east_Q2  >  cong_from_south_Q2)? YDIR :XDIR;
-    assign conjestion_cmp[Q1]  =  (cong_from_west_Q1  >  cong_from_north_Q1)? YDIR :XDIR;
-    assign conjestion_cmp[Q0]  =  (cong_from_west_Q0  >  cong_from_south_Q0)? YDIR :XDIR;
-  
-                            
-
-    
-    
-    
-        assign port_pre_sel = conjestion_cmp;
-   
-       
-     
- 
- 
-endmodule
-
-/***********************
-
-    port_pre_sel_gen
-
-
-************************/
-
-
-
-module port_pre_sel_gen #(
-    parameter PPSw=4,
-    parameter P=5,
-    parameter V=4,
-    parameter B=4,
-    parameter CONGESTION_INDEX=2,
-    parameter CONGw=2,
-    parameter ROUTE_TYPE="ADAPTIVE",
-    parameter [V-1  :   0] ESCAP_VC_MASK= 4'b0001
-
-)(
-    port_pre_sel,
-    ovc_status,
-    ovc_avalable_all,
-    congestion_in_all,
-    credit_decreased_all,
-    credit_increased_all,
-    reset,
-    clk
-
-);
-
-    localparam P_1      =   P-1,
-               PV       =   P   *   V,
-               CONG_ALw =   CONGw * P;
-
-    output [PPSw-1      :   0]  port_pre_sel;
-    input  [PV-1        :   0]  ovc_status;
-    input  [PV-1        :   0]  ovc_avalable_all;
-    input  [PV-1        :   0]  credit_decreased_all;
-    input  [PV-1        :   0]  credit_increased_all;
-    input  [CONG_ALw-1 :    0]  congestion_in_all;  
-    input  reset,clk;
-    
-    
-generate
-    /* verilator lint_off WIDTH */
-    if(ROUTE_TYPE    ==   "DETERMINISTIC") begin : detrministic
-    /* verilator lint_on WIDTH */
-       assign port_pre_sel = {PPSw{1'b0}};
-    
-    end else begin : adaptive
-        if(CONGESTION_INDEX==0) begin:indx0
-             
-                port_presel_based_dst_ports_vc #(
-                    .PPSw(PPSw),
-                    .P(P),
-                    .V(V)
-                
-                )
-                port_presel_gen
-                (
-                    .ovc_status (ovc_status [PV-1   :   V]),
-                    .port_pre_sel(port_pre_sel)
-                    
-        
-                );
-                
-        end else if(CONGESTION_INDEX==1) begin :indx1
-                      
-                port_presel_based_dst_ports_credit #(
-                    .PPSw(PPSw),
-                    .P(P),
-                    .V(V),
-                    .B(B)
-                ) 
-                port_presel_gen
-                (
-                    .credit_decreased_all   (credit_decreased_all   [PV-1  :   V]),//remove local port signals
-                    .credit_increased_all   (credit_increased_all   [PV-1  :   V]),
-                    .port_pre_sel           (port_pre_sel),
-                    .clk                    (clk),
-                    .reset                  (reset)
-                );
-        end else if (   (CONGESTION_INDEX==2) || (CONGESTION_INDEX==3) ||
-                        (CONGESTION_INDEX==4) || (CONGESTION_INDEX==5) ||
-                        (CONGESTION_INDEX==6) || (CONGESTION_INDEX==7) || 
-                        (CONGESTION_INDEX==9) ||
-                        (CONGESTION_INDEX==11)|| (CONGESTION_INDEX==12))      begin :dst_vc
-              
-                mesh_torus_port_presel_based_dst_routers_vc #(
-                    .PPSw(PPSw),
-                    .P(P),
-                    .CONGw(CONGw)
-                )
-                port_presel_gen
-                (                    
-                    .congestion_in_all(congestion_in_all),
-                    .port_pre_sel(port_pre_sel),
-                    .reset(reset),
-                    .clk(clk)
-                );
-          end else if((CONGESTION_INDEX==8) || (CONGESTION_INDEX==10) )begin :dst_ovc
-            
-            port_presel_based_dst_routers_ovc #(
-                .PPSw(PPSw),
-                .P(P),
-                .V(V),
-                .CONGw(CONGw)
-            )
-             port_presel_gen
-            (
-                .port_pre_sel(port_pre_sel),    
-                .congestion_in_all(congestion_in_all)   
-            );
-        
-        
-        end 
-    end 
-    endgenerate
-endmodule
-
- 
- 
-                                                    /*********************************
- 
-                                                            congestion_out_gen
- 
-                                                    ********************************/
-                                                    
-                                                    
-                                                    
-                                                    
- 
- /*******************************
- 
-       congestion based on number of active ivc 
-            CONGESTION_INDEX==2  CONGw   =   2
-            CONGESTION_INDEX==3  CONGw   =   3
- ********************************/
- module congestion_out_based_ivc_req #(
-    parameter P=5,
-    parameter V=4,
-    parameter CONGw   =   2 //congestion width per port
- 
- )
- (
-    ivc_request_all,
-    congestion_out_all  
- 
- );
-    
- 
-    localparam  PV      =   (V     *  P),
-                CONG_ALw=   (CONGw* P);   //  congestion width per router;
-         
-   
-   
-   
-    input       [PV-1       :   0]  ivc_request_all; 
-    output      [CONG_ALw-1 :   0]  congestion_out_all;                 
-                
-  
-    wire    [CONGw-1    :   0]  congestion_out ;  
-    
-    parallel_count_normalize #(
-        .INw    (PV),
-        .OUTw   (CONGw) 
-    )
-    ivc_req_counter
-    (
-        .in     (ivc_request_all),
-        .out    (congestion_out)
-
-    );
-    
-    
-           
-    assign  congestion_out_all = {P{congestion_out}};     
- 
-endmodule
-
-
-
-
-/*******************************
- 
-       congestion based on number of
- active ivc requests that are not granted    
-            CONGESTION_INDEX==4  CONGw   =   2
-            CONGESTION_INDEX==5  CONGw   =   3
- ********************************/
- module congestion_out_based_ivc_notgrant #(
-    parameter P=5,
-    parameter V=4,
-    parameter CONGw=2 //congestion width per port
- 
- )
- (
-    ivc_request_all,
-    congestion_out_all,
-    ivc_num_getting_sw_grant,
-    clk,
-    reset  
- 
- );
-
-    function integer log2;
-      input integer number; begin   
-         log2=(number <=1) ? 1: 0;    
-         while(2**log2<number) begin    
-            log2=log2+1;    
-         end 	   
-      end   
-    endfunction // log2 
- 
-    localparam  PV      =   (V     *  P),
-                CONG_ALw=   CONGw* P,   //  congestion width per router;
-                IVC_CNTw=   log2(PV+1);
-    
-   
-   
-   
-    input       [PV-1       :   0]  ivc_request_all,ivc_num_getting_sw_grant; 
-    output      [CONG_ALw-1 :   0]  congestion_out_all;                 
-    input                           clk,reset;
-                
-    wire    [IVC_CNTw-1 :   0]  ivc_req_num;
-    reg     [CONGw-1    :   0]  congestion_out ; 
-    wire    [PV-1       :   0]  ivc_request_not_granted; 
-   
-    
-    pronoc_register #(
-           .W(PV)          
-      ) reg1 ( 
-           .in(ivc_request_all & ~ivc_num_getting_sw_grant),
-           .reset(reset),    
-           .clk(clk),      
-           .out(ivc_request_not_granted)
-      );
-  
-    
-    accumulator #(
-      	.INw(PV),
-      	.OUTw(IVC_CNTw),
-      	.NUM(PV)
-    )
-    ivc_req_counter
-    (
-      	.in_all(ivc_request_not_granted),
-      	.out(ivc_req_num)
-    );
-    
-    /*
-    parallel_counter #(
-        .IN_WIDTH(PV)
-    )
-    ivc_req_counter
-    (
-        .in(ivc_request_not_granted),
-        .out(ivc_req_num)
-    );
-    */
-    
-    
-    generate 
-    if(CONGw==2)begin :w2
-        always @(*)begin
-            if      (ivc_req_num <= (PV/10) )   congestion_out=2'd0;    //0~10
-            else if (ivc_req_num <= (PV/5)  )   congestion_out=2'd1;    //10~20
-            else if (ivc_req_num <= (PV/2)  )   congestion_out=2'd2;    //20~50
-            else                                congestion_out=2'd3;    //50~100
-        end
-    end else begin :w3 // CONGw==3
-        always @(*)begin
-            if      (ivc_req_num < ((PV*1)/8) )   congestion_out=3'd0;    
-            else if (ivc_req_num < ((PV*2)/8) )   congestion_out=3'd1;    
-            else if (ivc_req_num < ((PV*3)/8) )   congestion_out=3'd2;    
-            else if (ivc_req_num < ((PV*4)/8) )   congestion_out=3'd3;    
-            else if (ivc_req_num < ((PV*5)/8) )   congestion_out=3'd4;      
-            else if (ivc_req_num < ((PV*6)/8) )   congestion_out=3'd5;   
-            else if (ivc_req_num < ((PV*7)/8) )   congestion_out=3'd6;    
-            else                                  congestion_out=3'd7;     
-        end  
-    end
-    endgenerate       
-    assign  congestion_out_all = {P{congestion_out}};     
- 
-endmodule
-
-
-
-
-
-
-/*******************************
- 
-     congestion based on number of
- availabe ovc in all 3ports of next router   
-            CONGESTION_INDEX==6 CONGw=2
-            CONGESTION_INDEX==7 CONGw=3
- ********************************/
- module congestion_out_based_3port_avb_ovc #(
-    parameter P=5,
-    parameter V=4,
-    parameter CONGw=2 //congestion width per port
- 
- )
- (
-    ovc_avalable_all,
-    congestion_out_all   
- 
- );
-    
- 
-    localparam  P_1     =   P-1,
-                PV      =   (V     *  P),
-                CONG_ALw=   CONGw* P;
-    
-   
-   localparam EAST      =0,
-              NORTH     =1,
-              WEST      =2,
-              SOUTH     =3;
-              
-    localparam  CNT_Iw = 3*V;            
-   
-    input       [PV-1       :   0]  ovc_avalable_all; 
-    output      [CONG_ALw-1 :   0]  congestion_out_all;                 
-  
-               
-                
-    wire    [V-1        :   0] ovc_not_avb [P_1-1  :   0];
-    wire    [CNT_Iw-1   :   0] counter_in   [P_1-1  :   0];
-    wire    [CONGw-1    :   0] congestion_out[P_1-1  :   0];
-  
-    assign  {ovc_not_avb[SOUTH], ovc_not_avb[WEST], ovc_not_avb[NORTH],  ovc_not_avb[EAST]}= ~ovc_avalable_all[PV-1     :   V];  
-    assign  counter_in[EAST]    ={ovc_not_avb[NORTH],ovc_not_avb[WEST]  ,ovc_not_avb[SOUTH]};
-    assign  counter_in[NORTH]   ={ovc_not_avb[EAST] ,ovc_not_avb[WEST]  ,ovc_not_avb[SOUTH]};
-    assign  counter_in[WEST]    ={ovc_not_avb[EAST] ,ovc_not_avb[NORTH] ,ovc_not_avb[SOUTH]};
-    assign  counter_in[SOUTH]   ={ovc_not_avb[EAST] ,ovc_not_avb[NORTH] ,ovc_not_avb[WEST]};
-       
-  
-  
-    genvar i;
-    generate 
-    for (i=0;i<4;i=i+1) begin :lp
-       
-        parallel_count_normalize #(
-            .INw(CNT_Iw),
-            .OUTw(CONGw)
-        )
-        ovc_avb_east
-        (
-            .in(counter_in[i]),
-            .out(congestion_out[i])
-        );   
-    
-    
-    end
-    endgenerate
-    
-    
-   
-    assign  congestion_out_all = {congestion_out[SOUTH],congestion_out[WEST],congestion_out[NORTH],congestion_out[EAST],{CONGw{1'b0}}};   
-
-endmodule
-
-
-
-
-
-
-
-/*******************************
- 
-     congestion based on number of
- availabe ovc in destination router   
-            CONGESTION_INDEX==8  CONGw=2
- ********************************/
- 
- 
- module congestion_out_based_avb_ovc_w2 #(
-    parameter P=5,
-    parameter V=4
-   
- 
- )
- (
-    ovc_avalable_all,
-    congestion_out_all   
- 
- );
-   localparam CONGw=2; //congestion width per port
- 
-    localparam  P_1     =   P-1,
-                PV      =   (V     *  P),
-                CONG_ALw=   CONGw* P,
-                CNT_Iw = 2*V;    
-    
-   
- 
-  
-   
-    input       [PV-1       :   0]  ovc_avalable_all; 
-    output      [CONG_ALw-1 :   0]  congestion_out_all;                 
-  
-   /*************
-        N
-     Q1 | Q3
-   w--------E
-     Q0 | Q2
-        S
-   ***************/
-   
-    localparam Q3   = 3,
-               Q1   = 1,
-               Q2   = 2,
-               Q0   = 0;  
-
-    localparam EAST =   0,
-               NORTH=   1,
-               WEST =   2,
-               SOUTH=   3;         
-     
-   
-          
-  
-               
-                
-    wire    [V-1        :   0] ovc_not_avb      [P_1-1  :   0];
-    wire    [CNT_Iw-1   :   0] counter_in       [P_1-1  :   0];
-    wire    [CONGw-1    :   0] congestion_out   [P_1-1  :   0];
-    wire    [P_1-1      :   0] threshold;
-    
-    
-    assign  {ovc_not_avb[SOUTH], ovc_not_avb[WEST], ovc_not_avb[NORTH],  ovc_not_avb[EAST]}= ~ovc_avalable_all[PV-1     :   V];  
-    
-    assign  counter_in[Q3]    ={ovc_not_avb[EAST ],ovc_not_avb[NORTH]};
-    assign  counter_in[Q1]    ={ovc_not_avb[NORTH],ovc_not_avb[WEST ]};
-    assign  counter_in[Q2]    ={ovc_not_avb[SOUTH],ovc_not_avb[EAST ]};
-    assign  counter_in[Q0]    ={ovc_not_avb[WEST ],ovc_not_avb[SOUTH]};
-    
-    genvar i;
-    generate
-    for (i=0;i<4;i=i+1) begin :lp
-      
-        parallel_count_normalize #(
-            .INw(CNT_Iw),
-            .OUTw(1)
-        )
-        ovc_not_avb_cnt
-        (
-            .in(counter_in[i]),
-            .out(threshold[i])
-        );   
-    
-    
-    end
-    endgenerate
-       
-       
-               
-                
-   
-    
-    assign congestion_out[EAST]     = {threshold[Q1],threshold[Q0]};
-    assign congestion_out[NORTH]    = {threshold[Q0],threshold[Q2]};
-    assign congestion_out[WEST]     = {threshold[Q2],threshold[Q3]};
-    assign congestion_out[SOUTH]    = {threshold[Q3],threshold[Q1]};
-   
-    assign  congestion_out_all = {congestion_out[SOUTH],congestion_out[WEST],congestion_out[NORTH],congestion_out[EAST],{CONGw{1'b0}}};   
-
-endmodule
-
-
-
-
-
-
-/*******************************
- 
-     congestion based on number of
- availabe ovc in destination router   
-            CONGESTION_INDEX==9  CONGw=3
- ********************************/
- 
- module congestion_out_based_avb_ovc_w3 #(
-    parameter P=5,
-    parameter V=4
-   
- 
- )
- (
-    ovc_avalable_all,
-    congestion_out_all   
- 
- );
-   localparam CONGw=3; //congestion width per port
- 
-    localparam  P_1     =   P-1,
-                PV      =   (V     *  P),
-                CONG_ALw=   CONGw* P;
-    
-   
-   localparam EAST      =0,
-              NORTH     =1,
-              WEST      =2,
-              SOUTH     =3;
-              
-  
-   
-    input       [PV-1       :   0]  ovc_avalable_all; 
-    output      [CONG_ALw-1 :   0]  congestion_out_all;                 
-  
-               
-                
-    wire    [V-1        :   0] ovc_not_avb [P_1-1  :   0];
-    wire    [CONGw-1    :   0] congestion_out[P_1-1  :   0];
-    
-    wire [P_1-1  :   0] threshold;
-  
-    assign  {ovc_not_avb[SOUTH],  ovc_not_avb[WEST], ovc_not_avb[NORTH],   ovc_not_avb[EAST]}=~ovc_avalable_all[PV-1     :   V];
-
- 
-   
-  
-    genvar i;
-    generate 
-    
-    
-    for (i=0;i<4;i=i+1) begin :lp
-      
-        parallel_count_normalize #(
-            .INw(V),
-            .OUTw(1)
-        )
-        ovc_avb_east
-        (
-            .in(ovc_not_avb[i]),
-            .out(threshold[i])
-        );   
-    
-    
-    end
-    endgenerate
-    
-    assign congestion_out[EAST]     = {threshold[NORTH],threshold[WEST ],threshold[SOUTH]};
-    assign congestion_out[NORTH]    = {threshold[WEST ],threshold[SOUTH],threshold[EAST ]};
-    assign congestion_out[WEST]     = {threshold[SOUTH],threshold[EAST ],threshold[NORTH]};
-    assign congestion_out[SOUTH]    = {threshold[EAST ],threshold[NORTH],threshold[WEST ]};
-   
-    assign  congestion_out_all = {congestion_out[SOUTH],congestion_out[WEST],congestion_out[NORTH],congestion_out[EAST],{CONGw{1'b0}}};   
-
-endmodule
-
-
-/*******************************
- 
-     congestion based on number of
- availabe ovc in destination router   
-            CONGESTION_INDEX==10  CONGw=4
- ********************************/
- module congestion_out_based_avb_ovc_w4 #(
-    parameter P=5,
-    parameter V=4
-   
- 
- )
- (
-    ovc_avalable_all,
-    congestion_out_all   
- 
- );
-   localparam CONGw=4; //congestion width per port
- 
-    localparam  P_1     =   P-1,
-                PV      =   (V     *  P),
-                CONG_ALw=   CONGw* P,
-                CNT_Iw = 2*V;    
-    
-   
-  
-   
-    input       [PV-1       :   0]  ovc_avalable_all; 
-    output      [CONG_ALw-1 :   0]  congestion_out_all;                 
-  
-  
-     
-   
-    /*************
-        N
-     Q1 | Q3
-   w--------E
-     Q0 | Q2
-        S
-   ***************/
-   
-    localparam Q3   = 3,
-               Q1   = 1,
-               Q2   = 2,
-               Q0   = 0;  
-
-    localparam EAST =   0,
-               NORTH=   1,
-               WEST =   2,
-               SOUTH=   3;         
-     
-             
-  
-               
-                
-    wire    [V-1        :   0] ovc_not_avb      [P_1-1  :   0];
-    wire    [CNT_Iw-1   :   0] counter_in       [P_1-1  :   0];
-    wire    [CONGw-1    :   0] congestion_out   [P_1-1  :   0];
-    wire    [1          :   0] threshold        [P_1-1  :   0];
-    
-    
-    assign  {ovc_not_avb[SOUTH], ovc_not_avb[WEST], ovc_not_avb[NORTH],  ovc_not_avb[EAST]}= ~ovc_avalable_all[PV-1     :   V];  
-    
-    assign  counter_in[Q3]    ={ovc_not_avb[EAST ],ovc_not_avb[NORTH]};
-    assign  counter_in[Q1]    ={ovc_not_avb[NORTH],ovc_not_avb[WEST ]};
-    assign  counter_in[Q2]    ={ovc_not_avb[SOUTH],ovc_not_avb[EAST ]};
-    assign  counter_in[Q0]    ={ovc_not_avb[WEST ],ovc_not_avb[SOUTH]};
-  
-    
-    genvar i;
-    generate
-    for (i=0;i<4;i=i+1) begin :lp
-      
-        parallel_count_normalize #(
-            .INw(CNT_Iw),
-            .OUTw(2)
-        )
-        ovc_not_avb_cnt
-        (
-            .in(counter_in[i]),
-            .out(threshold[i])
-        );   
-    
-    
-    end
-    endgenerate
-       
-       
-               
-                
-   
-    
-    assign congestion_out[EAST]     = {threshold[Q1],threshold[Q0]};
-    assign congestion_out[NORTH]    = {threshold[Q0],threshold[Q2]};
-    assign congestion_out[WEST]     = {threshold[Q2],threshold[Q3]};
-    assign congestion_out[SOUTH]    = {threshold[Q3],threshold[Q1]};
-   
-    assign  congestion_out_all = {congestion_out[SOUTH],congestion_out[WEST],congestion_out[NORTH],congestion_out[EAST],{CONGw{1'b0}}};   
-
-endmodule
-
-
- 
-
-/*******************************
- 
-    congestion based on number of 
-    availabe ovc and not granted
-        ivc in next router  
-    CONGESTION_INDEX==11 CONGw=2
-    CONGESTION_INDEX==12 CONGw=3
-    
-            
- ********************************/
- module congestion_out_based_avb_ovc_not_granted_ivc #(
-    parameter P=5,
-    parameter V=4,
-    parameter CONGw=3 //congestion width per port
- 
- )
- (
-    ovc_avalable_all,
-    ivc_request_all,
-    ivc_num_getting_sw_grant,
-    clk,
-    reset,    
-    congestion_out_all   
- 
- );
-    
-
-    function integer log2;
-      input integer number; begin   
-         log2=(number <=1) ? 1: 0;    
-         while(2**log2<number) begin    
-            log2=log2+1;    
-         end 	   
-      end   
-    endfunction // log2 
-    
-   
-     
- 
-    localparam  P_1         =   P-1,
-                PV          =   (V     *  P),
-                CONG_ALw    =   CONGw* P,
-                CNT_Iw      =   3*V,
-                CNT_Ow      =   log2((3*V)+1),
-                CNG_w       =   log2((6*V)+1),
-                CNT_Vw      =   log2(V+1),
-                EAST        =   0,
-                NORTH       =   1,
-                WEST        =   2,
-                SOUTH       =   3;
-              
-                 
-   
-    input       [PV-1       :   0]  ovc_avalable_all; 
-    output      [CONG_ALw-1 :   0]  congestion_out_all;                 
-    input       [PV-1       :   0]  ivc_request_all,ivc_num_getting_sw_grant; 
-    
-    input                           reset,clk;
-               
-    // counting not available ovc            
-    wire    [V-1        :   0] ovc_not_avb  [P_1-1  :   0];
-    wire    [CNT_Iw-1   :   0] counter_in   [P_1-1  :   0];
-    wire    [CNT_Ow-1   :   0] counter_o    [P_1-1  :   0];
-    wire    [CONGw-1    :   0] congestion_out[P_1-1  :   0];
-  
-    assign  {ovc_not_avb[SOUTH], ovc_not_avb[WEST], ovc_not_avb[NORTH],  ovc_not_avb[EAST]}= ~ovc_avalable_all[PV-1     :   V];  
-    assign  counter_in[EAST]    ={ovc_not_avb[NORTH],ovc_not_avb[WEST]  ,ovc_not_avb[SOUTH]};
-    assign  counter_in[NORTH]   ={ovc_not_avb[EAST] ,ovc_not_avb[WEST]  ,ovc_not_avb[SOUTH]};
-    assign  counter_in[WEST]    ={ovc_not_avb[EAST] ,ovc_not_avb[NORTH] ,ovc_not_avb[SOUTH]};
-    assign  counter_in[SOUTH]   ={ovc_not_avb[EAST] ,ovc_not_avb[NORTH] ,ovc_not_avb[WEST]};
-    
-    // counting not granted requests
-    wire    [PV-1       :   0]  ivc_request_not_granted; 
-    wire    [V-1        :   0]  ivc_not_grnt  [P_1-1  :   0];
-    wire    [CNT_Vw-1   :   0]  ivc_not_grnt_num [P_1-1  :   0];
-    
-    
-     pronoc_register #(
-           .W(PV)          
-      ) reg1 ( 
-           .in(ivc_request_all & ~ivc_num_getting_sw_grant),
-           .reset(reset),    
-           .clk(clk),      
-           .out(ivc_request_not_granted)
-      );
-    
-     assign  {ivc_not_grnt[SOUTH], ivc_not_grnt[WEST], ivc_not_grnt[NORTH],ivc_not_grnt[EAST]}= ivc_request_not_granted[PV-1     :   V];  
-    
-     
-   
-    genvar i;
-    generate 
-    for (i=0;i<4;i=i+1) begin :lp
-   
-   /*
-        parallel_counter #(
-            .IN_WIDTH(CNT_Iw)
-        )
-        ovc_counter
-        (
-            .in(counter_in[i]),
-            .out(counter_o[i])
-        );
-   */
-   
-       accumulator #(
-       	.INw(CNT_Iw),
-       	.OUTw(CNT_Ow),
-       	.NUM(CNT_Iw)
-       )
-       ovc_counter
-       (
-       	.in_all(counter_in[i]),
-       	.out(counter_o[i])
-       );
-   
-   
-   
-     /*
-        parallel_counter #(
-            .IN_WIDTH(V)
-            
-        )
-        ivc_counter
-        (
-            .in(ivc_not_grnt[i]),
-            .out(ivc_not_grnt_num[i])
-        );
-  */      
-   
-   
-       accumulator #(
-       	.INw(V),
-       	.OUTw(CNT_Vw),
-       	.NUM(V)
-       )
-        ivc_counter
-        (
-       	.in_all(ivc_not_grnt[i]),
-       	.out(ivc_not_grnt_num[i])
-       );
-       
-           
-       wire [CNG_w-1 :   0] congestion_num  [P_1-1  :   0];
-
-
-       assign congestion_num [i]=  counter_o[i]+ ivc_not_grnt_num[i]+ {ivc_not_grnt_num[i],1'b0};
-   
-       normalizer #(
-            .MAX_IN(6*V),
-            .OUTw(CONGw)
-  
-        )norm
-        (
-            .in(congestion_num [i]),
-            .out(congestion_out[i])
-        
-         );
-       
-           
-    end//for
-    endgenerate
-    
- 
-   
-   
-    assign  congestion_out_all = {congestion_out[SOUTH],congestion_out[WEST],congestion_out[NORTH],congestion_out[EAST],{CONGw{1'b0}}};   
-
-endmodule
-
-
-
-/**********************
-
-    parallel_count_normalize
-
-**********************/
-module parallel_count_normalize #(
-    parameter INw = 12,
-    parameter OUTw= 2
-
-)(
-    in,
-    out
-
-);
-
-    function integer log2;
-      input integer number; begin   
-         log2=(number <=1) ? 1: 0;    
-         while(2**log2<number) begin    
-            log2=log2+1;    
-         end 	   
-      end   
-    endfunction // log2 
-    
-    input   [INw-1      :   0]  in;
-    output  [OUTw-1     :   0]  out;
-
-    localparam CNTw = log2(INw+1);
-    wire    [CNTw-1     :    0] counter;
-/*
-    parallel_counter #(
-        .IN_WIDTH(INw)
-    )
-    ovc_avb_cnt
-    (
-        .in(in),
-        .out(counter)
-    );  
-  */
-  
-      accumulator #(
-      	.INw(INw),
-      	.OUTw(CNTw),
-      	.NUM(INw)
-      )
-      ovc_avb_cnt
-      (
-      	.in_all(in),
-      	.out(counter)
-      );
-  
-       
-    normalizer #(
-        .MAX_IN(INw),
-        .OUTw(OUTw)
-  
-    )norm
-    (
-        .in(counter),
-        .out(out)
-     );
-    
-           
- endmodule    
-   
-   /**************
-   
-   normalizer
-   
-   ***************/
-   
- module normalizer #(
-    parameter MAX_IN= 10,
-    parameter OUTw= 2
-  
- )(
-    in,
-    out
- 
- );
- 
- 
-    function integer log2;
-      input integer number; begin   
-         log2=(number <=1) ? 1: 0;    
-         while(2**log2<number) begin    
-            log2=log2+1;    
-         end 	   
-      end   
-    endfunction // log2 
-    
-    localparam INw= log2(MAX_IN+1),
-               OUT_ON_HOT_NUM = 2**OUTw;
-    
- 
-    input   [INw-1   :   0]  in;
-    output  [OUTw-1  :   0]  out; 
-    
-    wire [OUT_ON_HOT_NUM-1   :   0]  one_hot_out;
- 
- 
- 
-    genvar i;
-    generate 
-    for(i=0;i< OUT_ON_HOT_NUM;i=i+1)begin :lp
-	/* verilator lint_off WIDTH */
-       if(i==0) begin : i0 assign one_hot_out[i]= (in<= (MAX_IN /OUT_ON_HOT_NUM)); end
-       else begin :ib0   assign one_hot_out[i]= ((in> ((MAX_IN *i)/OUT_ON_HOT_NUM)) &&  (in<= ((MAX_IN *(i+1))/OUT_ON_HOT_NUM))); end
-    	/* verilator lint_on WIDTH */
-    end//for
-    endgenerate
-    
- 
-    
-    one_hot_to_bin#( 
-        .ONE_HOT_WIDTH(OUT_ON_HOT_NUM)
-    )
-    conv
-    (
-        .one_hot_code(one_hot_out),
-        .bin_code(out)
-    );
- 
- 
- endmodule
- 
-   
-   
-   
-   
-
-   
-   
-   
-   
-   
-   
-   
-
-/**************************
-
-
-        congestion_out_gen
-        
-
-**************************/
-
-
-
-
-module congestion_out_gen #(
-    parameter P=5,
-    parameter V=4,
-    parameter ROUTE_TYPE ="ADAPTIVE", 
-    parameter CONGESTION_INDEX=2,
-    parameter CONGw=2
-
-)
-(
-   ivc_request_all, 
-   ivc_num_getting_sw_grant,
-   ovc_avalable_all,
-   congestion_out_all,
-   clk,
-   reset
-);
-
-localparam PV       = P*V,
-           CONG_ALw = CONGw* P;   //  congestion width per router;;
-
- input    [PV-1       :   0]  ovc_avalable_all; 
- input    [PV-1       :   0]  ivc_request_all;    
- input    [PV-1       :   0]  ivc_num_getting_sw_grant; 
- output   [CONG_ALw-1 :   0]  congestion_out_all;                 
- input                        clk,reset;
-
-  wire [CONG_ALw-1 :   0]  congestion_out_all_next;  
-generate
-if(ROUTE_TYPE  !=  "DETERMINISTIC") begin :adpt
-        if((CONGESTION_INDEX==2) || (CONGESTION_INDEX==3)) begin :based_ivc
-           congestion_out_based_ivc_req #(
-               .P(P),
-               .V(V),
-               .CONGw(CONGw)
-           )
-           the_congestion_out_gen
-           (
-               .ivc_request_all(ivc_request_all),
-               .congestion_out_all(congestion_out_all_next)
-           );
-        end else if((CONGESTION_INDEX==4) || (CONGESTION_INDEX==5)) begin :based_ng_ivc
-      
-           congestion_out_based_ivc_notgrant #(
-               .P(P),
-               .V(V),
-               .CONGw(CONGw)
-           )
-           the_congestion_out_gen
-           (
-               .ivc_num_getting_sw_grant(ivc_num_getting_sw_grant),
-               .ivc_request_all(ivc_request_all),
-               .congestion_out_all(congestion_out_all_next),
-               .clk(clk),
-               .reset(reset)
-           );
-           
-        end else if  ((CONGESTION_INDEX==6) || (CONGESTION_INDEX==7)) begin :avb_ovc1
-       
-            congestion_out_based_3port_avb_ovc#(
-               .P(P),
-               .V(V),
-               .CONGw(CONGw)
-             )
-             the_congestion_out_gen
-             (      
-            	.ovc_avalable_all(ovc_avalable_all),
-                .congestion_out_all(congestion_out_all_next)
-              );
-       
-       
-       end  else if  (CONGESTION_INDEX==8) begin :indx8
-              
-       
-            congestion_out_based_avb_ovc_w2 #(
-                .P(P),
-                .V(V)
-            )
-            the_congestion_out_gen
-            (
-                .ovc_avalable_all(ovc_avalable_all),
-                .congestion_out_all(congestion_out_all_next)   
- 
-            );
-         end  else if  (CONGESTION_INDEX==9) begin :indx9
- 
-            congestion_out_based_avb_ovc_w3 #(
-                .P(P),
-                .V(V)
-            )
-            the_congestion_out_gen
-            (
-                .ovc_avalable_all(ovc_avalable_all),
-                .congestion_out_all(congestion_out_all_next)   
- 
-            );
-         end  else if  (CONGESTION_INDEX==10) begin :indx10
-            
-            congestion_out_based_avb_ovc_w4 #(
-                .P(P),
-                .V(V)
-            )
-            the_congestion_out_gen
-            (
-                .ovc_avalable_all(ovc_avalable_all),
-                .congestion_out_all(congestion_out_all_next)   
- 
-            );
-            
-          end  else if  (CONGESTION_INDEX==11 || CONGESTION_INDEX==12) begin :indx11
-            
-            congestion_out_based_avb_ovc_not_granted_ivc #(
-                .P(P),
-                .V(V),
-                .CONGw(CONGw) //congestion width per port
-            )
-            the_congestion_out_gen
-            (
-                .ovc_avalable_all(ovc_avalable_all),
-                .ivc_request_all(ivc_request_all),
-                .ivc_num_getting_sw_grant(ivc_num_getting_sw_grant),
-                .clk(clk),
-                .reset(reset),    
-                .congestion_out_all(congestion_out_all_next)   
-            );
-             
-       
-        end  else begin :nocong assign  congestion_out_all_next = {CONG_ALw{1'bx}};   end
-    
-    
-    end else begin :dtrmn
-           assign  congestion_out_all_next = {CONG_ALw{1'bx}};   
-    
-    end
-
-endgenerate
-
-
- pronoc_register #(
-           .W(CONG_ALw)          
-      ) reg1 ( 
-           .in(congestion_out_all_next),
-           .reset(reset),    
-           .clk(clk),      
-           .out(congestion_out_all)
-      );
-  
-
-endmodule
-
-
-/*************************
-
-    deadlock_detector
-
-**************************/
-
-module  deadlock_detector #(
-    parameter P=5,
-    parameter V=4,
-    parameter MAX_CLK = 16
-
-)(
-    ivc_num_getting_sw_grant,
-    ivc_request_all,
-    reset,
-    clk,
-    detect
-
-);
-    
- 
-    function integer log2;
-      input integer number; begin   
-         log2=(number <=1) ? 1: 0;    
-         while(2**log2<number) begin    
-            log2=log2+1;    
-         end 	   
-      end   
-    endfunction // log2 
-    
-    
-    
-    
-    localparam  PV      =  P*V,
-                CNTw    = log2(MAX_CLK);
-
-    
-    input [PV-1   :   0]  ivc_num_getting_sw_grant, ivc_request_all;
-    input             reset,clk;
-    output            detect;
-
-    wire  [CNTw-1 :   0]  counter         [V-1   :   0];
-    reg   [CNTw-1 :   0]  counter_next    [V-1   :   0];
-    wire  [P-1    :   0]  counter_rst_gen [V-1   :   0];
-    wire  [P-1    :   0]  counter_en_gen  [V-1   :   0];
-    wire  [V-1    :   0]  counter_rst,counter_en,detect_gen;
-    wire  [PV-1   :   0]  ivc_num_getting_sw_grant_reg;
- 
- 
-    pronoc_register #(
-           .W(PV)          
-      ) reg1 ( 
-           .in(ivc_num_getting_sw_grant),
-           .reset(reset),    
-           .clk(clk),      
-           .out(ivc_num_getting_sw_grant_reg)
-      );
-  
-
- 
-    //seperate all same virtual chanels requests
-    genvar i,j;
-    generate 
-    for (i=0;i<V;i=i+1)begin:v_loop
-        for (j=0;j<P;j=j+1)begin :p_loop
-            assign counter_rst_gen[i][j]=ivc_num_getting_sw_grant_reg[j*V+i];
-            assign counter_en_gen [i][j]=ivc_request_all[j*V+i];
-        end//j
-		//sum all signals belong to the same VC
-		assign counter_rst[i]   =|counter_rst_gen[i];
-		assign counter_en[i]    =|counter_en_gen [i]; 
-		// generate the counter
-		
-		
-		 always @ (*) begin 
-		    counter_next[i] = counter[i];
-		    if(counter_rst[i])      counter_next[i] = {CNTw{1'b0}};
-		    else if(counter_en[i])  counter_next[i] = counter[i]+1'b1;
-		 end//always
-		
-		
-		pronoc_register #(
-		       .W(CNTw)          
-		  ) reg2 ( 
-		       .in(counter_next[i]),
-		       .reset(reset),    
-		       .clk(clk),      
-		       .out(counter[i])
-		  );
-
-		// check counters value to detect deadlock
-		assign detect_gen[i]=     (counter[i]== MAX_CLK-1);
-    
-    end//i 
-    endgenerate
-
-    assign detect=|detect_gen;
-
-
-
-endmodule
-
-
-
-
- 
-
diff --git a/mpsoc/rtl/src_noc/crossbar.sv b/mpsoc/rtl/src_noc/crossbar.sv
new file mode 100755
index 0000000..273ccbc
--- /dev/null
+++ b/mpsoc/rtl/src_noc/crossbar.sv
@@ -0,0 +1,130 @@
+`include "pronoc_def.v"
+/**********************************************************************
+**    File: crossbar.v
+**    
+**    Copyright (C) 2014-2017  Alireza Monemi
+**    
+**    This file is part of ProNoC 
+**
+**    ProNoC ( stands for Prototype Network-on-chip)  is free software: 
+**    you can redistribute it and/or modify it under the terms of the GNU
+**    Lesser General Public License as published by the Free Software Foundation,
+**    either version 2 of the License, or (at your option) any later version.
+**
+**     ProNoC is distributed in the hope that it will be useful, but WITHOUT
+**     ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+**     or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
+**     Public License for more details.
+**
+**     You should have received a copy of the GNU Lesser General Public
+**     License along with ProNoC. If not, see <http:**www.gnu.org/licenses/>.
+**
+**
+**    Description: 
+**    NoC router crosbar module
+**
+**************************************************************/
+
+module crossbar #(
+    parameter P = 5// router port num
+)(
+    granted_dest_port_all,
+    flit_in_all,
+    flit_out_all,
+    flit_out_wr_all,
+    ssa_flit_wr_all
+);
+    import pronoc_pkg::*;
+    
+    localparam 
+        P_1 = (SELF_LOOP_EN )?  P : P-1,
+        P_1w = log2(P_1);
+    
+    input [P_1-1 : 0] granted_dest_port_all[P-1 : 0];
+    input [Fw-1 : 0] flit_in_all[P-1 : 0];
+    output logic [Fw-1 : 0] flit_out_all [P-1 : 0];
+    output [P-1 : 0] flit_out_wr_all;
+    input  [P-1 : 0] ssa_flit_wr_all;
+    
+    wire [P-1 : 0]  flit_we_mux_out;
+    wire [Fw-1 : 0] mux_in [P-1 : 0][P_1-1 : 0];
+    wire [P_1-1 : 0] mux_sel_pre [P-1 : 0];
+    wire [P_1-1 : 0]  mux_sel [P-1 : 0];
+    logic [P_1w-1 : 0] mux_sel_bin [P-1 : 0];
+    logic [P-1 : 0] flit_out_wr_gen [P-1 : 0];
+    
+    //one_hot_to_bin
+    always_comb begin
+        for(int m=0;m<P;m++) begin
+            mux_sel_bin[m] = '0;
+            for (int k = 0; k < P_1; k++) begin
+                if (mux_sel[m][k]) mux_sel_bin[m] = P_1w'(k);
+            end
+        end
+    end
+    
+    //add_sw_loc_one_hot 
+    always_comb begin 
+        for(int m=0;m< P;m++) begin 
+            if (SELF_LOOP_EN == 0) begin
+                for(int k=0;k<P; k++) begin 
+                    if (k>m) flit_out_wr_gen[m][k] = granted_dest_port_all[m][k-1];
+                    else if (k==m) flit_out_wr_gen[m][k] = 1'b0;
+                    else flit_out_wr_gen[m][k] = granted_dest_port_all[m][k];
+                end//for 
+            end else flit_out_wr_gen[m][P_1-1 : 0] = granted_dest_port_all[m];
+        end//for
+    end//always
+    
+    genvar i,j;
+    generate
+    for(i=0;i<P;i=i+1) begin : P_
+        for(j=0;j<P;j=j+1)begin : P_ 
+            if(SELF_LOOP_EN == 0) begin : nslp
+                //remove sender port flit from flit list
+                if(i>j)    begin 
+                    assign mux_in[i][j] = flit_in_all[j];
+                    assign mux_sel_pre[i][j] = granted_dest_port_all[j][i-1];
+                end
+                else if(i<j) begin 
+                    assign mux_in[i][j-1] = flit_in_all[j];
+                    assign mux_sel_pre[i][j-1] = granted_dest_port_all[j][i];
+                end
+            end else begin : slp
+                assign mux_in[i][j] = flit_in_all[j];
+                assign mux_sel_pre[i][j] = granted_dest_port_all[j][i];            
+            end
+        end//for j
+        
+        if (SSA_EN) begin : predict //If no output is granted replace the output port with SS port
+            add_ss_port #(
+                .SW_LOC(i),
+                .P(P)
+            ) ss_port (
+                .destport_in (mux_sel_pre[i]),
+                .destport_out(mux_sel [i])
+            );        
+        end else begin : nopredict
+            assign mux_sel[i]= mux_sel_pre[i];
+        end
+        if (IS_ONE_HOT_MUX) begin : one_hot_gen
+            // One-hot mux
+            always_comb begin
+                flit_out_all[i] = {Fw{1'b0}};
+                for (int k = 0; k < P_1; k++)
+                    flit_out_all[i] |= (mux_sel[i][k]) ?  mux_in[i][k] : {Fw{1'b0}};
+            end
+        end else begin : binary
+            assign flit_out_all[i]= mux_in[i][mux_sel_bin[i]];
+        end//binary
+    end//for i
+    endgenerate
+    reduction_or #(
+        .W(P),
+        .N(P)
+    ) wide_or (
+        .D_in(flit_out_wr_gen),
+        .Q_out(flit_we_mux_out)
+    );
+    assign flit_out_wr_all = flit_we_mux_out | ssa_flit_wr_all;
+endmodule
diff --git a/mpsoc/rtl/src_noc/crossbar.v b/mpsoc/rtl/src_noc/crossbar.v
deleted file mode 100755
index 31131e4..0000000
--- a/mpsoc/rtl/src_noc/crossbar.v
+++ /dev/null
@@ -1,200 +0,0 @@
-`timescale     1ns/1ps
-/**********************************************************************
-**	File: crossbar.v
-**    
-**	Copyright (C) 2014-2017  Alireza Monemi
-**    
-**	This file is part of ProNoC 
-**
-**	ProNoC ( stands for Prototype Network-on-chip)  is free software: 
-**	you can redistribute it and/or modify it under the terms of the GNU
-**	Lesser General Public License as published by the Free Software Foundation,
-**	either version 2 of the License, or (at your option) any later version.
-**
-** 	ProNoC is distributed in the hope that it will be useful, but WITHOUT
-** 	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
-** 	or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
-** 	Public License for more details.
-**
-** 	You should have received a copy of the GNU Lesser General Public
-** 	License along with ProNoC. If not, see <http:**www.gnu.org/licenses/>.
-**
-**
-**	Description: 
-**	NoC router crosbar module
-**
-**************************************************************/
-
-module crossbar #(
-    parameter NOC_ID=0,
-    parameter TOPOLOGY = "MESH",
-    parameter V    = 4,     // vc_num_per_port
-    parameter P    = 5,     // router port num
-    parameter Fw     = 36,
-    parameter MUX_TYPE="BINARY",        //"ONE_HOT" or "BINARY"    
-    parameter SSA_EN="YES", // "YES" , "NO"
-    parameter SELF_LOOP_EN= "NO"
-)
-(
-    granted_dest_port_all,
-    flit_in_all,
-    flit_out_all,
-    flit_out_wr_all,
-    ssa_flit_wr_all
- );    
-    
-
-    function integer log2;
-      input integer number; begin   
-         log2=(number <=1) ? 1: 0;    
-         while(2**log2<number) begin    
-            log2=log2+1;    
-         end        
-      end   
-    endfunction // log2 
-    
-    localparam 
-        PV = V * P,
-        VV = V * V,
-        PP = P * P,        
-        PVV = PV * V,    
-        P_1 = (SELF_LOOP_EN == "NO")? P-1 : P,
-        VP_1 = V * P_1,                
-        PP_1 = P_1 * P,
-        PVP_1 = PV * P_1,
-        PFw = P*Fw,
-        P_1Fw = P_1 * Fw,
-        P_1w = log2(P_1);
-    
-    
-    input [PP_1-1 : 0] granted_dest_port_all;
-    input [PFw-1 : 0] flit_in_all;
-    output [PFw-1 : 0] flit_out_all;
-    output [P-1 : 0] flit_out_wr_all;
-    input  [P-1 : 0] ssa_flit_wr_all;
-  
-
-    wire [P-1 : 0]  flit_we_mux_out;
-    wire [P_1-1 : 0] granted_dest_port [P-1 : 0];
-    wire [P_1Fw-1 : 0] mux_in [P-1 : 0];
-    wire [P_1-1 : 0] mux_sel_pre [P-1 : 0];
-    wire [P_1-1 : 0]  mux_sel [P-1 : 0];
-    wire [P_1w-1 : 0] mux_sel_bin [P-1 : 0];
-    wire [PP-1 : 0] flit_out_wr_gen;
-    
-    genvar i,j;
-    generate
-    for(i=0;i<P;i=i+1)begin : port_loop
-        assign granted_dest_port[i] = granted_dest_port_all[(i+1)*P_1-1 : i*P_1];
-        for(j=0;j<P;j=j+1)begin : port_loop2 
-            if(SELF_LOOP_EN == "NO") begin : nslp
-                //remove sender port flit from flit list
-                if(i>j)    begin :if1
-                    assign mux_in[i][(j+1)*Fw-1 : j*Fw]=     flit_in_all[(j+1)*Fw-1 : j*Fw];
-                    assign mux_sel_pre[i][j] =    granted_dest_port[j][i-1];
-                end
-                else if(i<j) begin :if2
-                    assign mux_in[i][j*Fw-1 : (j-1)*Fw]=     flit_in_all[(j+1)*Fw-1 : j*Fw];
-                    assign mux_sel_pre[i][j-1] =    granted_dest_port[j][i];
-                end
-            end else begin : slp
-                assign mux_in[i][(j+1)*Fw-1 : j*Fw]=     flit_in_all[(j+1)*Fw-1 : j*Fw];
-                assign mux_sel_pre[i][j] =    granted_dest_port[j][i];            
-            end
-        end//for j
-        
-        
-        
-        /* verilator lint_off WIDTH */
-        if (SSA_EN =="YES")begin :predict //If no output is granted replace the output port with SS port
-        /* verilator lint_on WIDTH */
-            add_ss_port #(               
-                .NOC_ID(NOC_ID),
-                .SW_LOC(i),
-    		    .P(P)
-            )
-            ss_port
-            (
-                .destport_in (mux_sel_pre[i]),
-                .destport_out(mux_sel [i])
-            );        
-        
-        end else begin :nopredict
-               assign mux_sel[i]= mux_sel_pre[i];
-          
-        end
-        
-        /* verilator lint_off WIDTH */
-        if    (MUX_TYPE    ==    "ONE_HOT") begin : one_hot_gen
-        /* verilator lint_on WIDTH */
-            onehot_mux_1D #(
-                .W (Fw),
-                .N (P_1)
-            )
-            cross_mux
-            (
-                .in (mux_in [i]),
-                .out (flit_out_all[(i+1)*Fw-1 : i*Fw]),
-                .sel (mux_sel[i])
-    
-            );
-        end else begin : binary
-        
-            one_hot_to_bin #(
-                .ONE_HOT_WIDTH(P_1),
-                .BIN_WIDTH(P_1w)
-            )
-            conv
-            (
-                .one_hot_code(mux_sel[i]),
-                .bin_code(mux_sel_bin[i])
-        
-            );
-            
-            
-            binary_mux #(
-                .IN_WIDTH(P_1Fw),
-                .OUT_WIDTH(Fw)
-            )
-            cross_mux
-            (
-                .mux_in(mux_in [i]),
-                .mux_out(flit_out_all[(i+1)*Fw-1 : i*Fw]),
-                .sel(mux_sel_bin[i])
-        
-            );
-        end//binary
-    
-    
-        if(SELF_LOOP_EN == "NO") begin : nslp
-            add_sw_loc_one_hot #(
-                .P(P),
-                .SW_LOC(i)
-            )
-            add_sw_loc
-            (
-                .destport_in(granted_dest_port_all[(i+1)*P_1-1 : i*P_1]),
-                .destport_out(flit_out_wr_gen [(i+1)*P-1 : i*P])
-            );
-        end else begin :slp 
-            assign flit_out_wr_gen [(i+1)*P-1 : i*P] = granted_dest_port_all[(i+1)*P_1-1 : i*P_1];
-        end
-     
-    end//for i    
-    endgenerate
-    
-    custom_or #(
-        .IN_NUM(P),
-        .OUT_WIDTH(P)
-    )
-    wide_or
-    (
-        .or_in(flit_out_wr_gen),
-        .or_out(flit_we_mux_out)
-    );
-    
-    assign    flit_out_wr_all = flit_we_mux_out | ssa_flit_wr_all;
-    
-       
-    
-endmodule
diff --git a/mpsoc/rtl/src_noc/debug.sv b/mpsoc/rtl/src_noc/debug.sv
new file mode 100644
index 0000000..818a9f1
--- /dev/null
+++ b/mpsoc/rtl/src_noc/debug.sv
@@ -0,0 +1,429 @@
+`include "pronoc_def.v"
+/**************************************
+* Module: debug
+* Date:2019-04-01  
+* Author: alireza     
+*
+* Description: this file contain modules which are used for error checking/debiging of the NoC. 
+***************************************/
+
+//check if flits are recived in correct order in a VC
+
+module check_flit_chanel_type_is_in_order 
+(
+    hdr_flg_in,
+    flit_in_wr,
+    tail_flg_in,
+    vc_num_in,
+    clk,
+    reset 
+);
+    import pronoc_pkg::*;
+    
+    input clk, reset;
+    input hdr_flg_in, tail_flg_in, flit_in_wr;
+    input [V-1 : 0] vc_num_in;
+    
+    wire [V-1 : 0] vc_num_hdr_wr, vc_num_tail_wr,vc_num_bdy_wr ;
+    logic [V-1 : 0] hdr_passed;
+    reg  [V-1 : 0] hdr_passed_next;
+    wire [V-1 : 0] single_flit_pck;
+    
+    assign  vc_num_hdr_wr =(hdr_flg_in & flit_in_wr) ?    vc_num_in :  {V{1'b0}};
+    assign  vc_num_tail_wr =(tail_flg_in & flit_in_wr)?    vc_num_in : {V{1'b0}};
+    assign  vc_num_bdy_wr =({hdr_flg_in,tail_flg_in} == 2'b00 && flit_in_wr)?  vc_num_in : {V{1'b0}};
+    assign  single_flit_pck = vc_num_hdr_wr & vc_num_tail_wr;
+    always_comb begin
+        hdr_passed_next = (hdr_passed | vc_num_hdr_wr) & ~vc_num_tail_wr; 
+    end
+    
+    `ifdef SIMULATION
+    always_ff @ (`pronoc_clk_reset_edge )begin 
+        if(`pronoc_reset) begin 
+            hdr_passed <= {V{1'b0}};
+        end else begin
+            hdr_passed <= hdr_passed_next;
+        end
+    end
+    
+    always @ (posedge clk ) begin 
+        if(( hdr_passed & vc_num_hdr_wr)>0  )begin 
+            $display("%t ERROR: a header flit is received in  an active IVC %m",$time);
+            $finish;
+        end
+        if((~hdr_passed & vc_num_tail_wr & ~single_flit_pck )>0 ) begin 
+            $display("%t ERROR: a tail flit is received in an inactive IVC %m",$time);
+            $finish;
+        end
+        if ((~hdr_passed & vc_num_bdy_wr )>0)begin 
+            $display("%t ERROR: a body flit is received in an inactive IVC %m",$time);
+            $finish;
+        end
+        if( IS_SINGLE_FLIT  &  flit_in_wr & ~(hdr_flg_in &  tail_flg_in )) begin 
+            $display("%t ERROR: both tail and header flit flags must be asserted in SINGLE_FLIT mode %m",$time);
+            $finish;
+        end 
+        if( (MIN_PCK_SIZE !=1) &  flit_in_wr & hdr_flg_in &  tail_flg_in ) begin 
+            $display("%t ERROR: A single flit packet is injected while the minimum packet size is set to %d.  %m",$time,MIN_PCK_SIZE);
+            $finish;
+        end
+        //TODO check that the injected packet size meets the MIN_PCK_SIZE
+    end//always
+    `endif
+endmodule
+
+
+module debug_regular_topo_route_ckeck #(
+    parameter SW_LOC=0
+    )(
+    reset,
+    clk,
+    hdr_flg_in,
+    flit_in_wr,
+    flit_is_tail,
+    ivc_num_getting_sw_grant,
+    vc_num_in,
+    current_r_addr,
+    dest_e_addr_in,
+    src_e_addr_in,
+    destport_in  
+);
+    import pronoc_pkg::*;
+    
+    input reset,clk;
+    input hdr_flg_in , flit_in_wr;
+    input [V-1 : 0] vc_num_in, flit_is_tail,  ivc_num_getting_sw_grant;
+    input [RAw-1 : 0] current_r_addr;
+    input [DAw-1 : 0] dest_e_addr_in;
+    input [EAw-1 : 0] src_e_addr_in;
+    input [DSTPw-1 : 0]  destport_in; 
+    
+    localparam
+        RXw = log2(NX),    // number of node in x axis
+        RYw = (TOPOLOGY=="RING" || TOPOLOGY == "LINE") ? 1 : log2(NY),
+        EXw = log2(NX),    // number of node in x axis
+        EYw = (TOPOLOGY=="RING" || TOPOLOGY == "LINE") ? 1 : log2(NY);   // number of node in y axis
+    
+    wire [RXw-1 : 0] current_x;
+    wire [EXw-1 : 0] x_dst_in,x_src_in;
+    wire [RYw-1 : 0] current_y;
+    wire [EYw-1 : 0] y_dst_in,y_src_in;
+    regular_topo_router_addr_t src_router_addr, dest_router_addr, current_router_addr;
+    assign src_router_addr = regular_topo_router_addr_t'(src_e_addr_in);
+    assign dest_router_addr = regular_topo_router_addr_t'(dest_e_addr_in);
+    assign current_router_addr = regular_topo_router_addr_t'(current_r_addr);
+    assign x_src_in = src_router_addr.x;
+    assign y_src_in = src_router_addr.y;
+    assign x_dst_in = dest_router_addr.x;
+    assign y_dst_in = dest_router_addr.y;
+    assign current_x = current_router_addr.x;
+    assign current_y = current_router_addr.y;   
+    
+    `ifdef SIMULATION 
+    generate
+    if(IS_DETERMINISTIC & ~IS_MESH_3D)begin :dtrmn
+        always@( posedge clk) begin 
+            if(flit_in_wr & hdr_flg_in )   
+                if( destport_in[1:0]==2'b11) begin 
+                    $display ( "%t\t  ERROR: destport port %x is illegal for determistic routing.  %m",$time,destport_in );                   
+                    $finish;
+                end
+            end//if
+        end//always
+    if(IS_FULL_ADAPTIVE) begin :full_adpt
+        reg [V-1 : 0] not_empty;
+        reg [V-1 : 0] not_empty_next;
+        always_ff @ (`pronoc_clk_reset_edge )begin 
+            if(`pronoc_reset) begin 
+                not_empty <= {V{1'b0}};
+            end else begin
+                not_empty <= not_empty_next;
+            end
+        end
+        always @ (*) begin
+            not_empty_next = not_empty;
+            if(hdr_flg_in & flit_in_wr) begin
+                not_empty_next = not_empty | vc_num_in;
+            end//hdr_wr_in
+            if((flit_is_tail & ivc_num_getting_sw_grant)>0)begin
+                not_empty_next = not_empty & ~ivc_num_getting_sw_grant;
+            end//tail wr out
+        end//always
+        always@( posedge clk ) begin
+            if(hdr_flg_in & flit_in_wr) begin
+                if( ((AVC_ATOMIC_EN==1)&& (SW_LOC != LOCAL)) || (SW_LOC == NORTH) || (SW_LOC == SOUTH) )begin
+                    if((vc_num_in  & ~ESCAP_VC_MASK)>0) begin // adaptive VCs
+                        if( (not_empty & vc_num_in)>0) $display("%t  :Error AVC allocated nonatomicly in %d port %m",$time,SW_LOC);
+                    end
+                end//( AVC_ATOMIC_EN || SW_LOC== NORTH || SW_LOC== SOUTH )
+                if((vc_num_in  & ESCAP_VC_MASK)>0 && (SW_LOC== SOUTH || SW_LOC== NORTH) )  begin // escape vc
+                    // if (a & b) $display("%t  :Error EVC allocation violate subfunction routing rules %m",$time);
+                    if ((current_x - x_dst_in) !=0 && (current_y- y_dst_in) !=0) $display("%t  :Error EVC allocation violate subfunction routing rules src_x=%d src_y=%d dst_x%d   dst_y=%d %m",$time,x_src_in, y_src_in, x_dst_in,y_dst_in);
+                end
+            end//hdr_wr_in
+        end//always
+    end 
+    if( IS_MESH )begin :mesh
+        wire  [EXw-1 : 0] low_x,high_x;
+        wire  [EYw-1 : 0] low_y,high_y;
+        assign low_x = (x_src_in < x_dst_in)?  x_src_in : x_dst_in;
+        assign low_y = (y_src_in < y_dst_in)?  y_src_in : y_dst_in;
+        assign high_x = (x_src_in < x_dst_in)?  x_dst_in : x_src_in;
+        assign high_y = (y_src_in < y_dst_in)?  y_dst_in : y_src_in;
+        always@( posedge clk)begin 
+            if((current_x <low_x) | (current_x > high_x) | (current_y <low_y) | (current_y > high_y) )  begin
+                if(flit_in_wr & hdr_flg_in )begin 
+                    $display ( "%t\t  ERROR: non_minimal routing %m",$time );
+                    $finish;
+                end
+            end
+        end
+    end// mesh  
+    endgenerate
+    `endif  
+endmodule
+
+
+module debug_mesh_edges #(
+    parameter P=5
+)(
+    clk,
+    current_r_addr,
+    flit_out_wr_all
+);
+    import pronoc_pkg::*;
+    
+    input clk;
+    input  [RAw-1 :  0]  current_r_addr;
+    input  [P-1 :  0]  flit_out_wr_all;
+    
+    wire [NXw-1 : 0] current_rx;
+    wire [NYw-1 : 0] current_ry;
+    regular_topo_router_addr_t current_router_addr_struct;
+    assign current_router_addr_struct = regular_topo_router_addr_t'(current_r_addr);
+    assign current_rx = current_router_addr_struct.x;
+    assign current_ry = current_router_addr_struct.y;
+    
+    `ifdef SIMULATION
+    always @(posedge clk) begin 
+        if(current_rx == {NXw{1'b0}} && flit_out_wr_all[WEST]) $display ( "%t\t  ERROR: a packet is going to the WEST in a router located in first column in mesh topology %m",$time ); 
+        if(current_rx == NXw'(T1-1)  && flit_out_wr_all[EAST]) $display ( "%t\t  ERROR: a packet is going to the EAST in a router located in last column in mesh topology %m",$time ); 
+        if(current_ry == {NYw{1'b0}} && flit_out_wr_all[NORTH])$display ( "%t\t  ERROR: a packet is going to the NORTH in a router located in first row in mesh topology %m",$time ); 
+        if(current_ry == NYw'(T2-1)  && flit_out_wr_all[SOUTH])$display ( "%t\t  ERROR: a packet is going to the SOUTH in a router located in last row in mesh topology %m",$time); 
+    end//always
+    `endif  
+endmodule
+
+
+module check_destination_addr(
+    dest_is_valid,
+    dest_e_addr,
+    current_e_addr
+);
+    import pronoc_pkg::*;
+    input [DAw-1 : 0]  dest_e_addr;
+    input [EAw-1 : 0]  current_e_addr;
+    output dest_is_valid;
+    // general rules
+    wire valid_self_loop  = (SELF_LOOP_EN == 0 )? (dest_e_addr[EAw-1 : 0]  !=  current_e_addr) : 1'b1;
+    wire valid;
+    generate
+    if(CAST_TYPE != "UNICAST") begin
+        wire [NE-1 : 0] dest_mcast_all_endp;
+        mcast_dest_list_decode decode (
+            .dest_e_addr(dest_e_addr),
+            .dest_o(dest_mcast_all_endp),
+            .row_has_any_dest( ),
+            .is_unicast()
+        );
+        //wire valid_dst_multi_r1  = (SELF_LOOP_EN   == 0) ? ~(dest_mcast_all_endp[current_e_addr] == 1'b1) : 1'b1;
+        wire valid_dst_multi_r2  = ~(dest_mcast_all_endp == {NE{1'b0}}); // there should be atleast one asserted destination
+        assign  dest_is_valid =  valid_dst_multi_r2;// & valid_dst_multi_r1 ;  
+    end else     
+    /* verilator lint_off WIDTH */ 
+    if(IS_REGULAR_TOPO) begin : Regular
+   /* verilator lint_on WIDTH */ 
+        regular_topo_address_validator check (
+            .addr(dest_e_addr),
+            .valid(valid)
+        );
+        assign  dest_is_valid = valid_self_loop & valid;
+    end else begin : tree
+        assign  dest_is_valid = valid_self_loop;
+    end
+    endgenerate
+endmodule
+
+
+module  endp_addr_encoder (
+    id_in,
+    code_out
+);
+
+    import pronoc_pkg::*;
+    localparam NEw= log2(NE);
+    input [NEw-1 :0] id_in;
+    output [EAw-1 : 0] code_out;
+    
+    generate 
+    if( IS_FATTREE  | IS_TREE ) begin : tree
+        fattree_addr_encoder #(
+            .K(T1),
+            .L(T2)
+        ) addr_encoder (
+        .id(id_in),
+        .code(code_out)
+        );
+    end else if  (IS_REGULAR_TOPO) begin : regular
+        regular_topo_endp_addr_encoder  addr_encoder  (
+            .id(id_in),
+            .code(code_out)
+        );
+    end else if (IS_FMESH) begin :fmesh
+        fmesh_addr_encoder addr_encoder (
+            .id(id_in),
+            .code(code_out)
+        );
+    end else if ( IS_MULTI_MESH) begin :mmesh
+        multimesh_address_encoder addr_encoder (
+            .rid_in(id_in),
+            .addr_st_o(code_out)
+        );
+    end else begin :custom
+        assign code_out =id_in;
+    end
+    endgenerate
+endmodule
+
+
+module endp_addr_decoder  (
+    code_in,
+    id_out
+);
+    import pronoc_pkg::*;
+    
+    output [NEw-1 :0] id_out;
+    input  [EAw-1 : 0] code_in;
+    generate 
+    if(IS_FATTREE | IS_TREE ) begin : tree
+        fattree_addr_decoder #(
+            .K(T1),
+            .L(T2)
+        )decoder(
+            .id(id_out),
+            .code(code_in)
+        );
+    end else if  ( IS_REGULAR_TOPO ) begin : regular
+        regular_topo_addr_coder  addr_coder (
+            .id    (id_out), 
+            .code  (code_in )
+        );
+    end else if (IS_FMESH) begin :fmesh
+        fmesh_addr_coder addr_coder (
+            .id(id_out),
+            .code(code_in)
+        );
+    end else if ( IS_MULTI_MESH) begin 
+        multimesh_address_decoder addr_coder (
+            .rid_out(id_out),
+            .addr_st_i(code_in)
+        );
+    end else begin :custom
+        assign id_out = code_in;
+    end
+    endgenerate
+endmodule  
+
+
+module check_pck_size (
+    hdr_flg_in,
+    flit_in_wr,
+    tail_flg_in,
+    vc_num_in,  
+    dest_e_addr_in,
+    clk,
+    reset  
+);
+    import pronoc_pkg::*;
+    input clk, reset;
+    input hdr_flg_in, tail_flg_in, flit_in_wr;
+    input [V-1 : 0] vc_num_in;
+    input [DAw-1: 0] dest_e_addr_in;
+    wire [NE-1 : 0] dest_mcast_all_endp [V-1 : 0];
+    logic [31 : 0] pck_size_counter [V-1: 0];
+    reg  [31 : 0] pck_size_counter_next [V-1: 0];
+    logic [DAw-1 : 0] dest_e_addr [V-1:0];
+    wire [V-1 : 0] vc_hdr_wr_en;
+    wire [V-1 : 0] onehot;
+    localparam MIN_B =  (B<LB)? B : LB;
+    `ifdef SIMULATION
+    genvar i;
+    generate 
+    for (i=0;i<V;i=i+1) begin :V_
+        localparam logic [V-1:0] VC = V'(i);
+        always @(*) begin 
+            pck_size_counter_next [i] = pck_size_counter [i];
+            if (vc_num_in == VC)begin 
+                if(flit_in_wr) begin  
+                    if(hdr_flg_in) pck_size_counter_next[i]= 1;
+                    else pck_size_counter_next[i]=pck_size_counter[i]+1;
+                end 
+            end
+        end
+        always_ff @ (`pronoc_clk_reset_edge )begin 
+            if(`pronoc_reset) begin
+                pck_size_counter[i] <= 32'b0;
+            end else begin
+                pck_size_counter[i] <= pck_size_counter_next[i];
+            end
+        end
+        
+        always @(posedge clk) begin 
+            if (vc_num_in == VC)begin 
+                if(flit_in_wr & tail_flg_in) begin 
+                    if( pck_size_counter_next[i] < MIN_PCK_SIZE) begin 
+                        $display ( "%t\t  ERROR: A packet is injected to the router with packet size (%d flits) that is smaller than MIN_PCK_SIZE (%d flits) parameter  %m",$time,pck_size_counter_next[i],MIN_PCK_SIZE);
+                        $finish;
+                    end
+                end
+            end
+        end
+        
+        if(!IS_UNICAST) begin
+        //Check that the size of multicast/broadcast packets <= buffer size
+            assign vc_hdr_wr_en [i] = flit_in_wr & hdr_flg_in & (vc_num_in == VC);
+            always_ff @ (`pronoc_clk_reset_edge )begin 
+                if(`pronoc_reset)
+                    dest_e_addr[i] <= '0; // or use specific reset value if needed
+                else if (vc_hdr_wr_en[i])
+                    dest_e_addr[i] <= dest_e_addr_in;
+            end
+            
+            mcast_dest_list_decode decode (
+                .dest_e_addr(dest_e_addr[i]),
+                .dest_o(dest_mcast_all_endp[i]),
+                .row_has_any_dest(),
+                .is_unicast()
+            ); 
+            
+            is_onehot0 #(
+                .IN_WIDTH(NE)
+            ) one_h (
+                .D_in(dest_mcast_all_endp[i]),
+                .result(onehot[i])
+            );
+            always @(posedge clk) begin 
+                if (vc_num_in == VC) begin 
+                    if(flit_in_wr & ~onehot[i])begin 
+                        if(pck_size_counter_next[i]>MIN_B) begin 
+                            $display ( "%t\t  ERROR: A multicast packet is injected to the router with packet size (%d flits) that is larger than the minimum router buffer size (%d flits) parameter  %m",$time,pck_size_counter_next[i],MIN_B);
+                            $finish;
+                        end// size
+                    end//flit_wr
+                end//vc_num
+            end//always
+        end//multicast
+    end  //for
+    endgenerate
+    `endif
+endmodule
diff --git a/mpsoc/rtl/src_noc/debug.v b/mpsoc/rtl/src_noc/debug.v
deleted file mode 100644
index ebea46d..0000000
--- a/mpsoc/rtl/src_noc/debug.v
+++ /dev/null
@@ -1,725 +0,0 @@
-`timescale 1ns / 1ps
-
-/**************************************
-* Module: debug
-* Date:2019-04-01  
-* Author: alireza     
-*
-* Description: this file contain modules which are used for error checking/debiging of the NoC. 
-***************************************/
-
-//check if flits are recived in correct order in a VC
-
-module check_flit_chanel_type_is_in_order #(
-    parameter V=4,
-    parameter PCK_TYPE = "SINGLE_FLIT",
-    parameter MIN_PCK_SIZE=2
-)(
-    hdr_flg_in,
-    flit_in_wr,
-    tail_flg_in,
-    vc_num_in,    
-    clk,
-    reset  
-
-);
-
-    input clk, reset;
-    input hdr_flg_in, tail_flg_in, flit_in_wr;
-    input [V-1 : 0] vc_num_in;
-    
-   
-    
-
-    wire [V-1 : 0] vc_num_hdr_wr, vc_num_tail_wr,vc_num_bdy_wr ;
-    wire [V-1 : 0] hdr_passed;
-    reg  [V-1 : 0] hdr_passed_next;
-    wire [V-1 : 0] single_flit_pck;
-    
-    assign  vc_num_hdr_wr =(hdr_flg_in & flit_in_wr) ?    vc_num_in : 0;
-    assign  vc_num_tail_wr =(tail_flg_in & flit_in_wr)?    vc_num_in : 0;
-    assign  vc_num_bdy_wr =({hdr_flg_in,tail_flg_in} == 2'b00 && flit_in_wr)?    vc_num_in : 0;
-    assign  single_flit_pck = vc_num_hdr_wr & vc_num_tail_wr;
-    always @(*)begin
-        hdr_passed_next = (hdr_passed | vc_num_hdr_wr) & ~vc_num_tail_wr; 
-    end
-    
-    // synthesis translate_off
-    
-    pronoc_register #(
-           .W(V)          
-      ) reg2 ( 
-           .in(hdr_passed_next),
-           .reset(reset),    
-           .clk(clk),      
-           .out(hdr_passed)
-      );    
-    
-    
-    
-    always @ (posedge clk ) begin 
-            if(( hdr_passed & vc_num_hdr_wr)>0  )begin 
-                $display("%t ERROR: a header flit is received in  an active IVC %m",$time);               
-                $finish;
-            end
-            if((~hdr_passed & vc_num_tail_wr & ~single_flit_pck )>0 ) begin 
-                $display("%t ERROR: a tail flit is received in an inactive IVC %m",$time);                
-                $finish;
-            end                
-            if ((~hdr_passed & vc_num_bdy_wr    )>0)begin 
-                $display("%t ERROR: a body flit is received in an inactive IVC %m",$time);                
-                $finish;
-            end
-            /* verilator lint_off WIDTH */
-            if((PCK_TYPE == "SINGLE_FLIT") &  flit_in_wr & ~(hdr_flg_in &  tail_flg_in )) begin 
-                $display("%t ERROR: both tail and header flit flags must be asserted in SINGLE_FLIT mode %m",$time);
-                $finish;
-            end 
-            /* verilator lint_on WIDTH */
-            if( (MIN_PCK_SIZE !=1) &  flit_in_wr & hdr_flg_in &  tail_flg_in ) begin 
-                $display("%t ERROR: A single flit packet is injected while the minimum packet size is set to %d.  %m",$time,MIN_PCK_SIZE);
-                $finish;
-            end
-            //TODO check that the injected packet size meets the MIN_PCK_SIZE            
-       
-    end//always
-    // synthesis translate_on
-endmodule
-
-
-
-
-
-
-module debug_mesh_tori_route_ckeck #(
-    parameter T1=4,
-    parameter T2=4,
-    parameter T3=4,
-    parameter ROUTE_TYPE = "FULL_ADAPTIVE",
-    parameter V=4,
-    parameter AVC_ATOMIC_EN=1,
-    parameter SW_LOC = 0,
-    parameter [V-1 : 0] ESCAP_VC_MASK= 4'b0001,
-    parameter TOPOLOGY="MESH",
-    parameter DSTPw=4,
-    parameter RAw=4,
-    parameter EAw=4,
-    parameter DAw=EAw
-)(
-    reset,
-    clk,
-    hdr_flg_in,
-    flit_in_wr,
-    flit_is_tail,
-    ivc_num_getting_sw_grant,
-    vc_num_in,
-    current_r_addr,
-    dest_e_addr_in,
-    src_e_addr_in,
-    destport_in  
-);
-
-    function integer log2;
-        input integer number; begin   
-           log2=(number <=1) ? 1: 0;    
-           while(2**log2<number) begin    
-              log2=log2+1;    
-           end        
-        end   
-    endfunction // log2 
-    
-    
-    input reset,clk;
-    input hdr_flg_in , flit_in_wr;
-    input [V-1 : 0] vc_num_in, flit_is_tail,  ivc_num_getting_sw_grant;
-    input [RAw-1 : 0] current_r_addr;
-    input [DAw-1 : 0] dest_e_addr_in;
-    input [EAw-1 : 0] src_e_addr_in;
-    input [DSTPw-1 : 0]  destport_in; 
-    
-    localparam
-      NX = T1,
-      NY = T2,
-      RXw = log2(NX),    // number of node in x axis
-      RYw = (TOPOLOGY=="RING" || TOPOLOGY == "LINE") ? 1 : log2(NY),
-      EXw = log2(NX),    // number of node in x axis
-      EYw = (TOPOLOGY=="RING" || TOPOLOGY == "LINE") ? 1 : log2(NY);   // number of node in y axis
-    
-    
-    wire [RXw-1 : 0] current_x;
-    wire [EXw-1 : 0] x_dst_in,x_src_in;
-    wire [RYw-1 : 0] current_y;
-    wire [EYw-1 : 0] y_dst_in,y_src_in;      
-    
-    mesh_tori_router_addr_decode #(
-    	.TOPOLOGY(TOPOLOGY),
-    	.T1(T1),
-    	.T2(T2),
-    	.T3(T3),
-    	.RAw(RAw)
-    )
-    r_addr_decode
-    (
-    	.r_addr(current_r_addr),
-    	.rx(current_x),
-    	.ry(current_y),
-    	.valid()
-    );
-    
-    mesh_tori_endp_addr_decode #(
-    	.TOPOLOGY(TOPOLOGY),
-        .T1(T1),
-        .T2(T2),
-        .T3(T3),
-    	.EAw(EAw)
-    )
-    dst_addr_decode
-    (
-    	.e_addr(dest_e_addr_in),
-    	.ex(x_dst_in),
-    	.ey(y_dst_in),
-    	.el( ),
-    	.valid()
-    );
-    
-    mesh_tori_endp_addr_decode #(
-        .TOPOLOGY(TOPOLOGY),
-        .T1(T1),
-        .T2(T2),
-        .T3(T3),
-        .EAw(EAw)
-    )
-    src_addr_decode
-    (
-        .e_addr(src_e_addr_in),
-        .ex(x_src_in),
-        .ey(y_src_in),
-        .el( ),
-        .valid()
-    );
-   
-    
-localparam  
-    LOCAL =  0, 
-    NORTH =  2,  
-    SOUTH =  4; 
- // synthesis translate_off 
-generate
-
-/* verilator lint_off WIDTH */
-if(ROUTE_TYPE == "DETERMINISTIC")begin :dtrmn
-/* verilator lint_on WIDTH */  
-    
-   
-    always@( posedge clk)begin 
-        if(flit_in_wr & hdr_flg_in )   
-               if( destport_in[1:0]==2'b11) begin 
-                    $display ( "%t\t  ERROR: destport port %x is illegal for determistic routing.  %m",$time,destport_in );                   
-                    $finish;
-               end
-        end//if
-    end//always
-    
-    
-/* verilator lint_off WIDTH */
-if(ROUTE_TYPE == "FULL_ADAPTIVE")begin :full_adpt
-/* verilator lint_on WIDTH */    
-      
-    wire [V-1 : 0] not_empty;
-    reg  [V-1 : 0] not_empty_next;
-        
-    pronoc_register #(
-           .W(V)          
-      ) reg2 ( 
-           .in(not_empty_next),
-           .reset(reset),    
-           .clk(clk),      
-           .out(not_empty)
-      );
-
-     always@(*) begin
-        not_empty_next = not_empty;
-        if(hdr_flg_in & flit_in_wr) begin
-            not_empty_next = not_empty | vc_num_in;
-        end//hdr_wr_in
-        if((flit_is_tail & ivc_num_getting_sw_grant)>0)begin
-            not_empty_next = not_empty & ~ivc_num_getting_sw_grant;
-        end//tail wr out
-     end//always
-        
-    always@( posedge clk ) begin
-        if(hdr_flg_in & flit_in_wr) begin
-            if( ((AVC_ATOMIC_EN==1)&& (SW_LOC!= LOCAL)) || (SW_LOC== NORTH) || (SW_LOC== SOUTH) )begin   
-                if((vc_num_in  & ~ESCAP_VC_MASK)>0) begin // adaptive VCs
-                    if( (not_empty & vc_num_in)>0) $display("%t  :Error AVC allocated nonatomicly in %d port %m",$time,SW_LOC);
-                end
-             end//( AVC_ATOMIC_EN || SW_LOC== NORTH || SW_LOC== SOUTH )
-             if((vc_num_in  & ESCAP_VC_MASK)>0 && (SW_LOC== SOUTH || SW_LOC== NORTH) )  begin // escape vc
-                       // if (a & b) $display("%t  :Error EVC allocation violate subfunction routing rules %m",$time);
-                    if ((current_x - x_dst_in) !=0 && (current_y- y_dst_in) !=0) $display("%t  :Error EVC allocation violate subfunction routing rules src_x=%d src_y=%d dst_x%d   dst_y=%d %m",$time,x_src_in, y_src_in, x_dst_in,y_dst_in);
-             end                     
-         end//hdr_wr_in            
-        end//always
-    end //SW_LOC
-
-
-    /* verilator lint_off WIDTH */ 
-    if(TOPOLOGY=="MESH")begin :mesh
-    /* verilator lint_on WIDTH */
-        wire  [EXw-1 : 0] low_x,high_x;
-        wire  [EYw-1 : 0] low_y,high_y;    
-        
-           
-        
-        assign low_x = (x_src_in < x_dst_in)?  x_src_in : x_dst_in;
-        assign low_y = (y_src_in < y_dst_in)?  y_src_in : y_dst_in;
-        assign high_x = (x_src_in < x_dst_in)?  x_dst_in : x_src_in;
-        assign high_y = (y_src_in < y_dst_in)?  y_dst_in : y_src_in;
-        
-          
-        always@( posedge clk)begin 
-               if((current_x <low_x) | (current_x > high_x) | (current_y <low_y) | (current_y > high_y) )  
-                    if(flit_in_wr & hdr_flg_in )begin 
-                        $display ( "%t\t  ERROR: non_minimal routing %m",$time );
-                        $finish;
-                    end
-                    
-        end
-           
-    
-    end// mesh  
-  endgenerate
-  
-  // synthesis translate_on
-  
-  endmodule
-  
-  
- module debug_mesh_edges #(
-    parameter T1=2,
-    parameter T2=2,
-    parameter T3=3,
-    parameter T4=3,
-    parameter RAw=4,
-    parameter P=5
- )(
-    clk,
-    current_r_addr,
-    flit_out_wr_all
- );
- 
-    function integer log2;
-        input integer number; begin   
-           log2=(number <=1) ? 1: 0;    
-           while(2**log2<number) begin    
-              log2=log2+1;    
-           end        
-        end   
-    endfunction // log2 
-  
-    input clk;
-    input  [RAw-1 :  0]  current_r_addr;
-    input  [P-1 :  0]  flit_out_wr_all;
-    
-    localparam 
-        RXw = log2(T1),    // number of node in x axis
-        RYw = log2(T2);    // number of node in y axis
-  
-  
-  wire [RXw-1 : 0] current_rx;
-  wire [RYw-1 : 0] current_ry;
-    
-    mesh_tori_router_addr_decode #(
-    	.TOPOLOGY("MESH"),
-    	.T1(T1),
-    	.T2(T2),
-    	.T3(T3),
-    	.RAw(RAw)
-    )
-    addr_decode
-    (
-    	.r_addr(current_r_addr),
-    	.rx(current_rx),
-    	.ry(current_ry),
-    	.valid()
-    );
-       
-    
-    localparam
-        EAST = 1,
-        NORTH = 2,
-        WEST = 3,
-        SOUTH = 4;
-  // synthesis translate_off 
-        always @(posedge clk) begin 
-        /* verilator lint_off WIDTH */ 
-                if(current_rx == {RXw{1'b0}}         && flit_out_wr_all[WEST]) $display ( "%t\t  ERROR: a packet is going to the WEST in a router located in first column in mesh topology %m",$time ); 
-                if(current_rx == T1-1     && flit_out_wr_all[EAST]) $display ( "%t\t   ERROR: a packet is going to the EAST in a router located in last column in mesh topology %m",$time ); 
-                if(current_ry == {RYw{1'b0}}         && flit_out_wr_all[NORTH])$display ( "%t\t  ERROR: a packet is going to the NORTH in a router located in first row in mesh topology %m",$time ); 
-                if(current_ry == T2-1    && flit_out_wr_all[SOUTH])$display ( "%t\t  ERROR: a packet is going to the SOUTH in a router located in last row in mesh topology %m",$time); 
-      /* verilator lint_on WIDTH */ 
-        end//always
-  // synthesis translate_on  
-endmodule
-
-
-/*******************
- * 
- * *****************/
- 
- module check_destination_addr #(
-    parameter NOC_ID=0,
-    parameter TOPOLOGY = "MESH",
-    parameter T1=2,
-    parameter T2=2,
-    parameter T3=2,
-    parameter T4=2,
-    parameter EAw=2,
-    parameter DAw=2,
-    parameter SELF_LOOP_EN="NO",
-    parameter CAST_TYPE = "UNICAST",
-    parameter NE=8
- )(
-     dest_is_valid,
-     dest_e_addr,
-     current_e_addr    
- );
- 
-    input [DAw-1 : 0]  dest_e_addr;
-    input [EAw-1 : 0]  current_e_addr;
-    output dest_is_valid;
- 
-    // general rules
-    /* verilator lint_off WIDTH */
-    wire valid_dst  = (SELF_LOOP_EN   == "NO")? dest_e_addr  !=  current_e_addr : 1'b1;
-    /* verilator lint_on WIDTH */
-    wire valid;
-    generate
-    if(CAST_TYPE != "UNICAST") begin     
-           
-            wire [NE-1 : 0] dest_mcast_all_endp;            
-            
-            mcast_dest_list_decode #(
-                .NOC_ID(NOC_ID)        
-            ) decode (
-                .dest_e_addr(dest_e_addr),
-                .dest_o(dest_mcast_all_endp),
-                .row_has_any_dest( ),
-                .is_unicast()
-            );
-        //wire valid_dst_multi_r1  = (SELF_LOOP_EN   == "NO") ? ~(dest_mcast_all_endp[current_e_addr] == 1'b1) : 1'b1;
-        wire valid_dst_multi_r2  = ~(dest_mcast_all_endp == {NE{1'b0}}); // there should be atleast one asserted destination
-        
-        assign  dest_is_valid =  valid_dst_multi_r2;// & valid_dst_multi_r1 ;  
-    end else     
-    /* verilator lint_off WIDTH */ 
-    if(TOPOLOGY=="MESH" || TOPOLOGY == "TORUS" || TOPOLOGY=="RING" || TOPOLOGY == "LINE") begin : mesh        
-   /* verilator lint_on WIDTH */ 
-        mesh_tori_endp_addr_decode #(
-        	.TOPOLOGY(TOPOLOGY),
-        	.T1(T1),
-        	.T2(T2),
-        	.T3(T3),
-        	.EAw(EAw)
-        )
-        mesh_tori_endp_addr_decode(
-        	.e_addr(dest_e_addr),
-        	.ex(),
-        	.ey(),
-        	.el(),
-        	.valid(valid)
-        );
-       assign  dest_is_valid = valid_dst & valid;
-    
-    end else begin : tree
-        assign  dest_is_valid = valid_dst;    
-    end
-    endgenerate
- 
- endmodule
- 
- 
- 
-module  endp_addr_encoder #(
-    parameter TOPOLOGY ="MESH",
-    parameter T1=4,
-    parameter T2=4,
-    parameter T3=4,
-    parameter EAw=4,
-    parameter NE=16
-)
-(
-    id,
-    code
- );    
-
-    function integer log2;
-      input integer number; begin   
-         log2=(number <=1) ? 1: 0;    
-         while(2**log2<number) begin    
-            log2=log2+1;    
-         end        
-      end   
-    endfunction // log2 
-    
-    localparam NEw= log2(NE);
-    
-     input [NEw-1 :0] id;
-     output [EAw-1 : 0] code;
-     
-     generate 
-     /* verilator lint_off WIDTH */ 
-     if(TOPOLOGY == "FATTREE" || TOPOLOGY == "TREE" ) begin : tree
-     /* verilator lint_on WIDTH */ 
-       fattree_addr_encoder #(
-        .K(T1),
-        .L(T2)
-       )
-       addr_encoder
-       (
-        .id(id),
-        .code(code)
-       );
-     
-     /* verilator lint_off WIDTH */ 
-     end else if  (TOPOLOGY == "MESH" || TOPOLOGY == "TORUS" || TOPOLOGY == "RING" || TOPOLOGY == "LINE") begin :tori
-     /* verilator lint_on WIDTH */ 
-        mesh_tori_addr_encoder #(
-            .NX(T1),
-            .NY(T2),
-            .NL(T3),
-            .NE(NE),
-            .EAw(EAw),
-            .TOPOLOGY(TOPOLOGY)
-        ) 
-        addr_encoder
-        (
-            .id(id),
-            .code(code)
-        );
-     end else if (TOPOLOGY == "FMESH") begin :fmesh
-        fmesh_addr_encoder #(
-            .NX(T1),
-            .NY(T2),
-            .NL(T3),
-            .NE(NE),
-            .EAw(EAw)
-        )
-        addr_encoder
-        (
-        .id(id),
-        .code(code)
-        );
-        
-     end else begin :custom
-     
-        assign code =id;
-     
-     end
-     endgenerate
-endmodule
- 
-
-module endp_addr_decoder  #(
-        parameter TOPOLOGY ="MESH",
-        parameter T1=4,
-        parameter T2=4,
-        parameter T3=4,
-        parameter EAw=4,
-        parameter NE=16
-        )
-        (
-        id,
-        code
-        );    
-
-    function integer log2;
-        input integer number; begin   
-            log2=(number <=1) ? 1: 0;    
-            while(2**log2<number) begin    
-                log2=log2+1;    
-            end        
-        end   
-    endfunction // log2 
-    
-    localparam NEw= log2(NE);
-    
-    output [NEw-1 :0] id;
-    input  [EAw-1 : 0] code;
-     
-    generate 
-    /* verilator lint_off WIDTH */ 
-    if(TOPOLOGY == "FATTREE" || TOPOLOGY == "TREE" ) begin : tree
-    /* verilator lint_on WIDTH */ 
-        fattree_addr_decoder #(
-                .K(T1),
-                .L(T2)
-
-            )decoder(
-                .id(id),
-                .code(code)
-            );
-    /* verilator lint_off WIDTH */     
-    end else if  (TOPOLOGY == "MESH" || TOPOLOGY == "TORUS" || TOPOLOGY == "RING" || TOPOLOGY == "LINE") begin :tori
-    /* verilator lint_on WIDTH */      
-        mesh_tori_addr_coder #(
-            .TOPOLOGY(TOPOLOGY),
-            .NX    (T1   ), 
-            .NY    (T2   ), 
-            .NL    (T3   ), 
-            .NE    (NE   ), 
-            .EAw   (EAw  )
-            ) addr_coder (
-            .id    (id   ), 
-            .code  (code ));
-      /* verilator lint_off WIDTH */          
-     end else if (TOPOLOGY == "FMESH") begin :fmesh
-      /* verilator lint_on WIDTH */   
-        fmesh_addr_coder #(
-            .NX(T1),
-            .NY(T2),
-            .NL(T3),
-            .NE(NE),
-            .EAw(EAw)
-        )
-        addr_coder
-        (
-        .id(id),
-        .code(code)
-        );
-            
-    end else begin :custom
-     
-        assign id = code;
-     
-    end
-    endgenerate
-endmodule  
-  
-
-module check_pck_size #(
-    parameter NOC_ID=0,
-    parameter V=2,
-    parameter MIN_PCK_SIZE=2,
-    parameter Fw=36,
-    parameter DAw=4,
-    parameter CAST_TYPE="UNICAST",
-    parameter NE=4,
-    parameter B=4,
-    parameter LB=4
-)(
-    hdr_flg_in,
-    flit_in_wr,
-    tail_flg_in,
-    vc_num_in,  
-    dest_e_addr_in,
-    clk,
-    reset  
-
-);
-
-    input clk, reset;
-    input hdr_flg_in, tail_flg_in, flit_in_wr;
-    input [V-1 : 0] vc_num_in;
-    input [DAw-1: 0] dest_e_addr_in;
-
-    wire [NE-1 : 0] dest_mcast_all_endp [V-1 : 0];
-    wire [31 : 0] pck_size_counter [V-1: 0];
-    reg  [31 : 0] pck_size_counter_next [V-1: 0];
-    wire [DAw-1 : 0] dest_e_addr [V-1:0];
-    wire [V-1 : 0] vc_hdr_wr_en;
-    wire [V-1 : 0] onehot;
-
-    localparam MIN_B =  (B<LB)? B : LB;       
-        
-    genvar i;
-    generate 
-    for (i=0;i<V;i=i+1) begin :V_
-        
-        always @(*) begin 
-            pck_size_counter_next [i] = pck_size_counter [i];
-            if (vc_num_in == i)begin 
-                if(flit_in_wr) begin  
-                    if(hdr_flg_in) pck_size_counter_next[i]= 1;
-                    else pck_size_counter_next[i]=pck_size_counter[i]+1;      
-                end 
-            end
-        end     
-        
-        
-        pronoc_register #(.W(32)) reg1(
-            .in     (pck_size_counter_next[i]), 
-            .reset  (reset ), 
-            .clk    (clk   ), 
-            .out    (pck_size_counter[i]   ));
-            
-         always @(posedge clk) begin 
-            if (vc_num_in == i)begin 
-                if(flit_in_wr & tail_flg_in) begin 
-                    if( pck_size_counter_next[i] < MIN_PCK_SIZE) begin 
-                        $display ( "%t\t  ERROR: A packet is injected to the router with packet size (%d flits) that is smaller than MIN_PCK_SIZE (%d flits) parameter  %m",$time,pck_size_counter_next[i],MIN_PCK_SIZE);
-                        $finish;
-                    end
-                end       
-            end
-         end
-         
-        /* verilator lint_off WIDTH */   
-        if(CAST_TYPE!="UNICAST") begin
-        /* verilator lint_on WIDTH */   
-        //Check that the size of multicast/broadcast packets <= buffer size
-            assign vc_hdr_wr_en [i] = flit_in_wr & hdr_flg_in & (vc_num_in == i);
-            pronoc_register_ld_en #(.W(DAw)) reg2(
-                .in     (dest_e_addr_in), 
-                .reset  (reset ), 
-                .clk    (clk   ), 
-                .ld     (vc_hdr_wr_en [i] ),
-                .out    (dest_e_addr[i])
-            );
-            
-            
-            mcast_dest_list_decode #(
-                .NOC_ID(NOC_ID)
-            ) decode (
-                .dest_e_addr(dest_e_addr[i]),
-                .dest_o(dest_mcast_all_endp[i]),
-                .row_has_any_dest(),
-                .is_unicast()
-            ); 
-            
-            is_onehot0 #(
-                .IN_WIDTH(NE)    
-            )
-            one_h
-            (
-                .in(dest_mcast_all_endp[i]),
-                .result(onehot[i])
-    
-            );
-            
-            
-            
-            
-            always @(posedge clk) begin 
-                if (vc_num_in == i)begin 
-                    if(flit_in_wr & ~onehot[i])begin 
-                        if(pck_size_counter_next[i]>MIN_B) begin 
-                            $display ( "%t\t  ERROR: A multicast packet is injected to the router with packet size (%d flits) that is larger than the minimum router buffer size (%d flits) parameter  %m",$time,pck_size_counter_next[i],MIN_B);
-                            $finish;
-                        end// size
-                    end//flit_wr
-                end//vc_num
-            end//always
-            
-        end//multicast
-   
-            
-    
-   
-   end  //for
-   endgenerate
-    
-    
-
-endmodule
-
diff --git a/mpsoc/rtl/src_noc/fattree_noc_top.sv b/mpsoc/rtl/src_noc/fattree_noc_top.sv
index b78f036..6e9ebb6 100644
--- a/mpsoc/rtl/src_noc/fattree_noc_top.sv
+++ b/mpsoc/rtl/src_noc/fattree_noc_top.sv
@@ -1,58 +1,68 @@
 `include "pronoc_def.v"
-/**************************************
-* Module: fattree
-* Date:2019-01-01  
-* Author: alireza     
-*
-* 
-Description: 
-
-    FatTree
-
-      Each level of the hierarchical indirect Network has
-      k^(l-1) Routers. The Routers are organized such that 
-      each node has k descendents, and each parent is
-      replicated k  times.
-      most routers has 2K ports, excep the top level has only K
-
-***************************************/
-
-
-module  fattree_noc_top #(
-    parameter NOC_ID=0
-) (
-	reset,
-	clk,    
-	chan_in_all,
-	chan_out_all,
-	router_event
+/**********************************************************************
+**    File:  fattree_noc_top.v
+**    
+**    Copyright (C) 2014-2017  Alireza Monemi
+**    
+**    This file is part of ProNoC 
+**
+**    ProNoC ( stands for Prototype Network-on-chip)  is free software: 
+**    you can redistribute it and/or modify it under the terms of the GNU
+**    Lesser General Public License as published by the Free Software Foundation,
+**    either version 2 of the License, or (at your option) any later version.
+**
+**     ProNoC is distributed in the hope that it will be useful, but WITHOUT
+**     ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+**     or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
+**     Public License for more details.
+**
+**     You should have received a copy of the GNU Lesser General Public
+**     License along with ProNoC. If not, see <http:**www.gnu.org/licenses/>.
+**
+**
+**    Description:
+**
+**    Fat-Tree NoC Top Module
+**
+**    This module implements a hierarchical indirect Fat-Tree 
+**    Network-on-Chip (NoC) topology. The network is organized 
+**    into multiple levels, with each level containing k^(l-1) 
+**    routers, where *k* is the radix and *l* is the current level.
+**
+**    Key Features:
+**    - Each router connects to *k* child routers in the level below.
+**    - Each parent router is replicated *k* times to ensure 
+**      balanced connectivity.
+**    - Most routers have 2K ports, except for the top-level routers, 
+**      which have only K ports due to reduced fan-out requirements.
+**
+**************************************************************/
+
+module  fattree_noc_top (
+    reset,
+    clk,
+    chan_in_all,
+    chan_out_all,
+    router_event
 );
-  
-     `NOC_CONF
-  
-	input   clk,reset;
-	//Endpoints ports 
-	input   smartflit_chanel_t chan_in_all  [NE-1 : 0];
-	output  smartflit_chanel_t chan_out_all [NE-1 : 0];
-	//Events
-	output  router_event_t  router_event [NR-1 : 0][MAX_P-1 : 0];
-	
-	//all routers port 
-	smartflit_chanel_t    router_chan_in   [NR-1 :0][MAX_P-1 : 0];
-	smartflit_chanel_t    router_chan_out  [NR-1 :0][MAX_P-1 : 0];
-
-	
- 
-		localparam
-			PV = V * MAX_P,
-			PFw = MAX_P * Fw,       
-			NRL= NE/K, //number of router in  each layer       
-			CONG_ALw = CONGw * MAX_P,
-			PLKw = MAX_P * LKw,
-			PLw = MAX_P * Lw,       
-			PRAw = MAX_P * RAw; // {layer , Pos} width     
+    
+    import pronoc_pkg::*;
+    
+    input   clk,reset;
+    //Endpoints ports 
+    input   smartflit_chanel_t chan_in_all  [NE-1 : 0];
+    output  smartflit_chanel_t chan_out_all [NE-1 : 0];
+    //Events
+    output  router_event_t  router_event [NR-1 : 0][MAX_P-1 : 0];
+    
+    //all routers port 
+    smartflit_chanel_t    router_chan_in   [NR-1 :0][MAX_P-1 : 0];
+    smartflit_chanel_t    router_chan_out  [NR-1 :0][MAX_P-1 : 0];
+    
+    localparam
+        NRL= NE/K;
         
-  function integer addrencode;
+    function integer addrencode;
         input integer pos,k,n,kw;
         integer pow,i,tmp;begin
         addrencode=0;
@@ -66,129 +76,111 @@ module  fattree_noc_top #(
         end
         end   
     endfunction 
-        
+    
     wire [LKw-1 : 0] current_pos_addr [NR-1 :0];
-    wire [Lw-1  : 0] current_layer_addr [NR-1 :0];   
+    wire [Lw-1  : 0] current_layer_addr [NR-1 :0];
     wire [RAw-1 : 0] current_r_addr [NR-1 : 0];
+    router_config_t router_config_in [NR-1 :0];
     
-//add roots
-
-genvar pos,level,port;
-
-
-
-generate 
-for( pos=0; pos<NRL; pos=pos+1) begin : root 
-	  localparam RID = pos;
+    /****************
+    *    add roots
+    *****************/
+    genvar pos,level,port;
+    generate 
+    for( pos=0; pos<NRL; pos=pos+1) begin : root 
+        localparam RID = pos;
+        localparam BOUND=(MAX_P > K)? K : MAX_P;
+        assign router_config_in[RID].router_id = RID [NRw-1 : 0];
+        assign router_config_in[RID].router_addr = current_r_addr [RID];
         router_top # (
-            .NOC_ID(NOC_ID),
-            .P(K)               
-        ) the_router (              
-            .current_r_id    (RID),
-      		.current_r_addr  (current_r_addr [RID]), 
-           	.chan_in         (router_chan_in [RID][K-1 : 0]), 
-           	.chan_out        (router_chan_out[RID][K-1 : 0]), 
-           	.router_event    (router_event[RID][K-1 : 0]),
-           	.clk             (clk), 
-           	.reset           (reset )
-      );  
-end   
-
-//add leaves
-
-for( level=1; level<L; level=level+1) begin :level_lp
-   for( pos=0; pos<NRL; pos=pos+1) begin : pos_lp 
-    localparam RID = NRL*level+pos;
-   	   	
-   	router_top # (
-        .NOC_ID(NOC_ID),
-        .P(2*K)         
-    ) the_router (              
-  			.current_r_id    (RID),
-   			.current_r_addr  (current_r_addr [RID]), 
-   			.chan_in         (router_chan_in [RID]), 
-   			.chan_out        (router_chan_out[RID]), 
-   			.router_event    (router_event[RID]), 
-   			.clk             (clk            ), 
-   			.reset           (reset          )
-   		);           
-   
+            .ROUTER_ID(RID),
+            .P(K)
+        ) the_router (
+            .router_config_in(router_config_in[RID]),
+            .chan_in (router_chan_in [RID][BOUND-1 : 0]), 
+            .chan_out(router_chan_out[RID][BOUND-1 : 0]), 
+            .router_event (router_event[RID][BOUND-1 : 0]),
+            .clk (clk), 
+            .reset (reset)
+        );  
     end
-end
-      
-   
-//connect all down input chanels
-localparam NPOS = powi( K, L-1);
-localparam CHAN_PER_DIRECTION = (K * powi( L , L-1 )); //up or down
-localparam CHAN_PER_LEVEL = 2*(K * powi( K , L-1 )); //up+down
-
-for (level = 0; level<L-1; level=level+1) begin : level_c
-/* verilator lint_off WIDTH */
-    localparam [Lw-1 : 0] LEAVE_L = L-1-level;
-/* verilator lint_on WIDTH */    
-    //input chanel are numbered interleavely, the interleaev depends on level
-    localparam ROUTERS_PER_NEIGHBORHOOD = powi(K,L-1-(level)); 
-    localparam ROUTERS_PER_BRANCH = powi(K,L-1-(level+1)); 
-    localparam LEVEL_OFFSET = ROUTERS_PER_NEIGHBORHOOD*K;
-    for ( pos = 0; pos < NPOS; pos=pos+1 ) begin : pos_c
-        localparam ADRRENCODED=addrencode(pos,K,L,Kw);
-        localparam NEIGHBORHOOD = (pos/ROUTERS_PER_NEIGHBORHOOD);
-        localparam NEIGHBORHOOD_POS = pos % ROUTERS_PER_NEIGHBORHOOD;
-        for ( port = 0; port < K; port=port+1 ) begin : port_c
-            localparam LINK = 
-                ((level+1)*CHAN_PER_LEVEL - CHAN_PER_DIRECTION)  //which levellevel
-                +NEIGHBORHOOD* LEVEL_OFFSET   //region in level
-                +port*ROUTERS_PER_BRANCH*K //sub region in region
-                +(NEIGHBORHOOD_POS)%ROUTERS_PER_BRANCH*K //router in subregion
-                +(NEIGHBORHOOD_POS)/ROUTERS_PER_BRANCH; //port on router
-
-
-            localparam L2= (LINK+CHAN_PER_DIRECTION)/CHAN_PER_LEVEL;
-            localparam POS2 = ((LINK+CHAN_PER_DIRECTION) % CHAN_PER_LEVEL)/K;
-            localparam PORT2= (((LINK+CHAN_PER_DIRECTION) % CHAN_PER_LEVEL)  %K)+K;
-            localparam ID1 =NRL*level+pos;
-            localparam ID2 =NRL*L2 + POS2;
-            localparam POS_ADR_CODE2= addrencode(POS2,K,L,Kw);
-            localparam POS_ADR_CODE1= addrencode(pos,K,L,Kw);
-           
+    
+    /****************
+    *    add leaves
+    *****************/
+    for( level=1; level<L; level=level+1) begin :level_lp
+        for( pos=0; pos<NRL; pos=pos+1) begin : pos_lp 
             
-           // $dotfile=$dotfile.node_connection('R',$id1,undef,$port,'R',$connect_id,undef,$connect_port);    
-       		assign  router_chan_in [ID1][port ] = router_chan_out [ID2][PORT2];
-			assign  router_chan_in [ID2][PORT2] = router_chan_out [ID1][port ];
-                   
-            assign current_layer_addr [ID1] = LEAVE_L;
-            assign current_pos_addr [ID1] = ADRRENCODED[LKw-1 :0];         
-            assign current_r_addr [ID1] = {current_layer_addr [ID1],current_pos_addr[ID1]};
-
-			if(level==L-2)begin 
-				 assign current_layer_addr [ID2] ={Lw{1'b0}};
-            	 assign current_pos_addr [ID2] = POS_ADR_CODE2[LKw-1 :0];         
-            	 assign current_r_addr [ID2] = {current_layer_addr [ID2],current_pos_addr[ID2]};
-			end
-
-         
-         end
+            localparam RID = NRL*level+pos;
+            assign router_config_in[RID].router_id = RID [NRw-1 : 0];
+            assign router_config_in[RID].router_addr = current_r_addr [RID];
+            
+            router_top # (
+                .ROUTER_ID(RID),
+                .P(2*K)
+            ) the_router (
+                .router_config_in(router_config_in[RID]),
+                .chan_in         (router_chan_in [RID]),
+                .chan_out        (router_chan_out[RID]),
+                .router_event    (router_event[RID]),
+                .clk             (clk),
+                .reset           (reset)
+            );
+            
+        end
     end
-end 
-   
-   
-   
- for ( pos = 0; pos <  NE; pos=pos+1 ) begin : endpoints
-    localparam RID= NRL*(L-1)+(pos/K);
-    localparam RPORT = pos%K;
     
-     //$dotfile=$dotfile.node_connection('T',$i,undef,undef,'R',$r,undef,$i%($k));    
- 
-            assign router_chan_in [RID][RPORT] =    chan_in_all [pos];                     
-            assign chan_out_all [pos] = router_chan_out [RID][RPORT];             
- 
- 
- end
- endgenerate    
-
-
-endmodule
-
-
-
-
+    //connect all down input chanels
+    localparam NPOS = powi( K, L-1);
+    localparam CHAN_PER_DIRECTION = (K * powi( L , L-1 )); //up or down
+    localparam CHAN_PER_LEVEL = 2*(K * powi( K , L-1 )); //up+down
+    for (level = 0; level<L-1; level=level+1) begin : level_c
+        /* verilator lint_off WIDTH */
+        localparam [Lw-1 : 0] LEAVE_L = L-1-level;
+        /* verilator lint_on WIDTH */    
+        //input chanel are numbered interleavely, the interleaev depends on level
+        localparam ROUTERS_PER_NEIGHBORHOOD = powi(K,L-1-(level)); 
+        localparam ROUTERS_PER_BRANCH = powi(K,L-1-(level+1)); 
+        localparam LEVEL_OFFSET = ROUTERS_PER_NEIGHBORHOOD*K;
+        for ( pos = 0; pos < NPOS; pos=pos+1 ) begin : pos_c
+            localparam ADRRENCODED=addrencode(pos,K,L,Kw);
+            localparam NEIGHBORHOOD = (pos/ROUTERS_PER_NEIGHBORHOOD);
+            localparam NEIGHBORHOOD_POS = pos % ROUTERS_PER_NEIGHBORHOOD;
+            for ( port = 0; port < K; port=port+1 ) begin : port_c
+                localparam LINK = 
+                    ((level+1)*CHAN_PER_LEVEL - CHAN_PER_DIRECTION)  //which levellevel
+                    +NEIGHBORHOOD* LEVEL_OFFSET   //region in level
+                    +port*ROUTERS_PER_BRANCH*K //sub region in region
+                    +(NEIGHBORHOOD_POS)%ROUTERS_PER_BRANCH*K //router in subregion
+                    +(NEIGHBORHOOD_POS)/ROUTERS_PER_BRANCH; //port on router
+                localparam L2= (LINK+CHAN_PER_DIRECTION)/CHAN_PER_LEVEL;
+                localparam POS2 = ((LINK+CHAN_PER_DIRECTION) % CHAN_PER_LEVEL)/K;
+                localparam PORT2= (((LINK+CHAN_PER_DIRECTION) % CHAN_PER_LEVEL)  %K)+K;
+                localparam ID1 =NRL*level+pos;
+                localparam ID2 =NRL*L2 + POS2;
+                localparam POS_ADR_CODE2= addrencode(POS2,K,L,Kw);
+                //localparam POS_ADR_CODE1= addrencode(pos,K,L,Kw);
+                //$dotfile=$dotfile.node_connection('R',$id1,undef,$port,'R',$connect_id,undef,$connect_port);
+                assign  router_chan_in [ID1][port ] = router_chan_out [ID2][PORT2];
+                assign  router_chan_in [ID2][PORT2] = router_chan_out [ID1][port ];
+                assign current_layer_addr [ID1] = LEAVE_L;
+                assign current_pos_addr [ID1] = ADRRENCODED[LKw-1 :0];
+                assign current_r_addr [ID1] = {current_layer_addr [ID1],current_pos_addr[ID1]};
+                if(level==L-2)begin 
+                    assign current_layer_addr [ID2] ={Lw{1'b0}};
+                    assign current_pos_addr [ID2] = POS_ADR_CODE2[LKw-1 :0];
+                    assign current_r_addr [ID2] = {current_layer_addr [ID2],current_pos_addr[ID2]};
+                end
+            end
+        end
+    end 
+    
+    for ( pos = 0; pos <  NE; pos=pos+1 ) begin : endpoints
+        localparam RID= NRL*(L-1)+(pos/K);
+        localparam RPORT = pos%K;
+        //$dotfile=$dotfile.node_connection('T',$i,undef,undef,'R',$r,undef,$i%($k));
+        assign router_chan_in [RID][RPORT] =    chan_in_all [pos];
+        assign chan_out_all [pos] = router_chan_out [RID][RPORT];
+    end
+    endgenerate
+endmodule
\ No newline at end of file
diff --git a/mpsoc/rtl/src_noc/fattree_route.v b/mpsoc/rtl/src_noc/fattree_route.sv
similarity index 66%
rename from mpsoc/rtl/src_noc/fattree_route.v
rename to mpsoc/rtl/src_noc/fattree_route.sv
index 2af54b1..21b9141 100644
--- a/mpsoc/rtl/src_noc/fattree_route.v
+++ b/mpsoc/rtl/src_noc/fattree_route.sv
@@ -1,4 +1,4 @@
-`timescale 1ns / 1ps
+`include "pronoc_def.v"
 /**************************************
 *
 *   fattree rout function
@@ -12,78 +12,59 @@
 module fattree_nca_random_up_routing  #(
    parameter K   = 2, // number of last level individual router`s endpoints.
    parameter L   = 2 // Fattree layer number (The height of FT)
-  
-)
-(
+)(
     reset,
     clk,
     current_addr_encoded,    // connected to current router x address
     current_level,    //connected to current router y address
     dest_addr_encoded,        // destination address
     destport_encoded    // router output port
-        
 );
-    
 
     function integer log2;
-      input integer number; begin   
-         log2=(number <=1) ? 1: 0;    
-         while(2**log2<number) begin    
+    input integer number; begin   
+        log2=(number <=1) ? 1: 0;    
+        while(2**log2<number) begin    
             log2=log2+1;    
-         end        
-      end   
+        end        
+    end   
     endfunction // log2 
-
-        
+    
     localparam
         Kw = log2(K),
         LKw= L*Kw,
         Lw = log2(L);
-       
-       
-        
+    
     input reset,clk;
     input  [LKw-1 :0]    current_addr_encoded;
     input  [Lw-1  :0]    current_level;    
     input  [LKw-1 :0]    dest_addr_encoded;
     output [K :0]    destport_encoded;
     /******************
-        destport_encoded format in fat tree. K+1 bit
-        destport[K] 
-            1'b0  : go down 
-            1'b1  : go up
-        destport[K-1: 0]: 
-            onehot coded. asserted bit show the output port locatation     
+    *    destport_encoded format in fat tree. K+1 bit
+    *    destport[K] 
+    *        1'b0  : go down 
+    *        1'b1  : go up
+    *    destport[K-1: 0]: 
+    *        onehot coded. asserted bit show the output port locatation     
     *******************/
-    
-    
-    
     wire  [Kw-1 :0]  current_addr [L-1 : 0];
     wire  [Kw-1 :0]  parrent_dest_addr [L-1 : 0];
     wire  [Kw-1 :0]  dest_addr [L-1 : 0];
     wire  [Kw-1 :0]  current_node_dest_port;
     
     wire [L-1 : 0] parrents_node_missmatch; 
-    
-    wire [K-1 : 0] counter; // a one hot counter. The value of the counter is used as a random destination port number when going to the up ports
-        
-     pronoc_register #(
-           .W(K),
-           .RESET_TO(1)
-      ) reg1 ( 
-           .in({counter[0],counter[K-1:1]}),
-           .reset(reset),    
-           .clk(clk),      
-           .out(counter)
-      );
-      
-    
-    
-
+    logic [K-1 : 0] counter; // a one hot counter. The value of the counter is used as a random destination port number when going to the up ports
+    always_ff @ (`pronoc_clk_reset_edge ) begin 
+        if(`pronoc_reset) begin 
+            counter <= K'(1);
+        end else begin
+            counter <= {counter[0],counter[K-1:1]};
+        end
+    end
     
     assign current_addr [0]={Kw{1'b0}}; 
     assign parrent_dest_addr [0]={Kw{1'b0}}; 
-       
     genvar i;
     generate 
     for(i=1; i<L; i=i+1)begin : caddr
@@ -93,34 +74,24 @@ module fattree_nca_random_up_routing  #(
         /* verilator lint_on WIDTH */ 
     end
     
-    
     for(i=0; i<L; i=i+1) begin : daddr
        // assign current_addr [i] = (current_level >=i)? current_addr_encoded[(i+1)*Kw-1 : i*Kw] : {Kw{1'b0}};
-       
         assign dest_addr [i] =  dest_addr_encoded[(i+1)*Kw-1 : i*Kw];
         assign parrents_node_missmatch[i]=  current_addr [i] !=  parrent_dest_addr [i]; 
     end//for
     endgenerate
-   
-   assign current_node_dest_port = dest_addr[current_level];
-   wire [K-1:0] current_node_dest_port_one_hot;
-   
-   bin_to_one_hot #(
-    .BIN_WIDTH(Kw),
-    .ONE_HOT_WIDTH(K)
-   )
-   conv
-   (
-    .bin_code(current_node_dest_port),
-    .one_hot_code(current_node_dest_port_one_hot)
-   ); 
+    assign current_node_dest_port = dest_addr[current_level];
+    logic [K-1:0] current_node_dest_port_one_hot;
+    
+    //bin_to_one_hot
+    always_comb begin
+        current_node_dest_port_one_hot = {K{1'b0}};
+        current_node_dest_port_one_hot[current_node_dest_port] = 1'b1;
+    end
     
     assign destport_encoded = (parrents_node_missmatch != {L{1'b0}}) ? /*go up*/{1'b1,counter} :  /*go down*/{1'b0,current_node_dest_port_one_hot};
-      
 endmodule
 
-
-
 // ============================================================
 //  FATTREE: Nearest Common Ancestor w/ destination port Up. 
 //  The up port is selected based on destination connected port num
@@ -129,105 +100,82 @@ endmodule
 module fattree_nca_destp_up_routing  #(
    parameter K   = 2, // number of last level individual router`s endpoints.
    parameter L   = 2 // Fattree layer number (The height of FT)
-  
-)
-(
+)(
     reset,
     clk,
     current_addr_encoded,    // connected to current router x address
     current_level,    //connected to current router y address
     dest_addr_encoded,        // destination address
     destport_encoded    // router output port
-        
 );
-    
 
     function integer log2;
-      input integer number; begin   
-         log2=(number <=1) ? 1: 0;    
-         while(2**log2<number) begin    
+    input integer number; begin   
+        log2=(number <=1) ? 1: 0;    
+        while(2**log2<number) begin    
             log2=log2+1;    
-         end        
-      end   
+        end        
+    end   
     endfunction // log2 
-
-        
+    
     localparam
         Kw = log2(K),
         LKw= L*Kw,
         Lw = log2(L);
-       
-       
-        
+    
     input reset,clk;
     input  [LKw-1 :0]    current_addr_encoded;
     input  [Lw-1  :0]    current_level;    
     input  [LKw-1 :0]    dest_addr_encoded;
     output [K :0]    destport_encoded;
     /******************
-        destport_encoded format in fat tree. K+1 bit
-        destport[K] 
-            1'b0  : go down 
-            1'b1  : go up
-        destport[K-1: 0]: 
-            onehot coded. asserted bit show the output port locatation     
+    *    destport_encoded format in fat tree. K+1 bit
+    *    destport[K] 
+    *        1'b0  : go down 
+    *        1'b1  : go up
+    *    destport[K-1: 0]: 
+    *        onehot coded. asserted bit show the output port locatation     
     *******************/
     
-    
-    
     wire  [Kw-1 :0]  current_addr [L-1 : 0];
     wire  [Kw-1 :0]  parrent_dest_addr [L-1 : 0];
     wire  [Kw-1 :0]  dest_addr [L-1 : 0];
-    wire  [Kw-1 :0]  current_node_dest_port;
-    
+    wire  [Kw-1 :0]  current_node_dest_port;    
     wire [L-1 : 0] parrents_node_missmatch; 
+    logic [K-1 : 0] counter; // a one hot counter. The value of the counter is used as a random destination port number when going to the up ports
+    always_ff @ (`pronoc_clk_reset_edge ) begin 
+        if(`pronoc_reset) begin 
+            counter <= K'(1);
+        end else begin
+            counter <= {counter[0],counter[K-1:1]};
+        end
+    end
     
-    wire [K-1 : 0] counter; // a one hot counter. The value of the counter is used as a random destination port number when going to the up ports
-    
-     pronoc_register #(
-           .W(K),
-           .RESET_TO(1)
-      ) reg1 ( 
-           .in({counter[0],counter[K-1:1]}),
-           .reset(reset),    
-           .clk(clk),      
-           .out(counter)
-      );
-   
     assign current_addr [0]={Kw{1'b0}}; 
     assign parrent_dest_addr [0]={Kw{1'b0}}; 
-       
+    
     genvar i;
     generate 
     for(i=1; i<L; i=i+1) begin : caddr
         assign current_addr [i] = (current_level <i)? current_addr_encoded[i*Kw-1 : (i-1)*Kw] : {Kw{1'b0}};
         assign parrent_dest_addr [i] = (current_level<i)? dest_addr_encoded[(i+1)*Kw-1 : i*Kw] : {Kw{1'b0}};
     end
-    
-    
     for(i=0; i<L; i=i+1) begin : daddr
        // assign current_addr [i] = (current_level >=i)? current_addr_encoded[(i+1)*Kw-1 : i*Kw] : {Kw{1'b0}};
-       
         assign dest_addr [i] =  dest_addr_encoded[(i+1)*Kw-1 : i*Kw];
         assign parrents_node_missmatch[i]=  current_addr [i] !=  parrent_dest_addr [i]; 
     end//for
     endgenerate
-   
-   assign current_node_dest_port = dest_addr[current_level];
-   wire [K-1:0] current_node_dest_port_one_hot;
-   
-   bin_to_one_hot #(
-    .BIN_WIDTH(Kw),
-    .ONE_HOT_WIDTH(K)
-   )
-   conv
-   (
-    .bin_code(current_node_dest_port),
-    .one_hot_code(current_node_dest_port_one_hot)
-   ); 
+    assign current_node_dest_port = dest_addr[current_level];
+    logic [K-1:0] current_node_dest_port_one_hot;
+    
+    //bin_to_one_hot
+    always_comb begin
+        current_node_dest_port_one_hot = {K{1'b0}};
+        current_node_dest_port_one_hot[current_node_dest_port] = 1'b1;
+    end
     
     assign destport_encoded = (parrents_node_missmatch != {L{1'b0}}) ? /*go up*/{1'b1,current_node_dest_port_one_hot} :  /*go down*/{1'b0,current_node_dest_port_one_hot};
-      
 endmodule
 
 
@@ -239,179 +187,120 @@ endmodule
 module fattree_nca_straight_up_routing  #(
    parameter K   = 2, // number of last level individual router`s endpoints.
    parameter L   = 2 // Fattree layer number (The height of FT)
-   
-)
-(
+) (
     reset,
     clk,
     current_addr_encoded,    // connected to current router x address
     current_level,    //connected to current router y address
     dest_addr_encoded,        // destination address
     destport_encoded    // router output port
-        
 );
-    
-   
-    
 
     function integer log2;
-      input integer number; begin   
-         log2=(number <=1) ? 1: 0;    
-         while(2**log2<number) begin    
+    input integer number; begin   
+        log2=(number <=1) ? 1: 0;    
+        while(2**log2<number) begin    
             log2=log2+1;    
-         end        
-      end   
+        end        
+    end   
     endfunction // log2 
-
-        
+    
     localparam
         Kw = log2(K),
         LKw= L*Kw,
         Lw = log2(L);
-       
-       
-        
+    
     input reset,clk;
-   
     input  [LKw-1 :0]    current_addr_encoded;
     input  [Lw-1  :0]    current_level;    
     input  [LKw-1 :0]    dest_addr_encoded;
     output [K :0]    destport_encoded;
-   
     /******************
-        destport_encoded format in fat tree. K+1 bit
-        destport[K] 
-            1'b0  : go down 
-            1'b1  : go up
-        destport[K-1: 0]: 
-            onehot coded. asserted bit show the output port locatation     
-    *******************/
-    
-    
+    *    destport_encoded format in fat tree. K+1 bit
+    *    destport[K] 
+    *        1'b0  : go down 
+    *        1'b1  : go up
+    *    destport[K-1: 0]: 
+    *        onehot coded. asserted bit show the output port locatation     
+    ********************/
     
     wire  [Kw-1 :0]  current_addr [L-1 : 0];
     wire  [Kw-1 :0]  parrent_dest_addr [L-1 : 0];
     wire  [Kw-1 :0]  dest_addr [L-1 : 0];
     wire  [Kw-1 :0]  current_node_dest_port;
-    
     wire [L-1 : 0] parrents_node_missmatch; 
-    
-    wire  [K-1 : 0] counter; // a one hot counter. The value of the counter is used as a random destination port number when going to the up ports
-    
-     pronoc_register #(
-           .W(K),
-           .RESET_TO(1)
-      ) reg1 ( 
-           .in({counter[0],counter[K-1:1]}),
-           .reset(reset),    
-           .clk(clk),      
-           .out(counter)
-      );
+    logic [K-1 : 0] counter; // a one hot counter. The value of the counter is used as a random destination port number when going to the up ports
+    always_ff @ (`pronoc_clk_reset_edge )begin 
+        if(`pronoc_reset) begin 
+            counter <= K'(1);
+        end else begin
+            counter <= {counter[0],counter[K-1:1]};
+        end
+    end
     
     assign current_addr [0]={Kw{1'b0}}; 
     assign parrent_dest_addr [0]={Kw{1'b0}}; 
-       
+    
     genvar i;
     generate 
     for(i=1; i<L; i=i+1)begin : caddr
         assign current_addr [i] = (current_level <i)? current_addr_encoded[i*Kw-1 : (i-1)*Kw] : {Kw{1'b0}};
         assign parrent_dest_addr [i] = (current_level<i)? dest_addr_encoded[(i+1)*Kw-1 : i*Kw] : {Kw{1'b0}};
     end
-    
-    
     for(i=0; i<L; i=i+1)begin : daddr
-       // assign current_addr [i] = (current_level >=i)? current_addr_encoded[(i+1)*Kw-1 : i*Kw] : {Kw{1'b0}};
-       
+        // assign current_addr [i] = (current_level >=i)? current_addr_encoded[(i+1)*Kw-1 : i*Kw] : {Kw{1'b0}};
         assign dest_addr [i] =  dest_addr_encoded[(i+1)*Kw-1 : i*Kw];
         assign parrents_node_missmatch[i]=  current_addr [i] !=  parrent_dest_addr [i]; 
     end//for
     endgenerate
-   
-   assign current_node_dest_port = dest_addr[current_level];
-   wire [K-1:0] current_node_dest_port_one_hot;
-   
-   bin_to_one_hot #(
-    .BIN_WIDTH(Kw),
-    .ONE_HOT_WIDTH(K)
-   )
-   conv
-   (
-    .bin_code(current_node_dest_port),
-    .one_hot_code(current_node_dest_port_one_hot)
-   ); 
+    assign current_node_dest_port = dest_addr[current_level];
+    logic [K-1:0] current_node_dest_port_one_hot;
+    
+    //bin_to_one_hot
+    always_comb begin
+        current_node_dest_port_one_hot = {K{1'b0}};
+        current_node_dest_port_one_hot[current_node_dest_port] = 1'b1;
+    end
     
     // if going up the destination port num is statis straigh. It will be filled at reciver port of the next router so leave it empty
     assign destport_encoded = (parrents_node_missmatch != {L{1'b0}}) ? /*go up*/{1'b1,{K{1'b0}}} :  /*go down*/{1'b0,current_node_dest_port_one_hot};
-      
 endmodule
 
 
 module    fattree_destport_up_select #(
-      parameter   K=3,
-      parameter   SW_LOC=0
+    parameter   K=3,
+    parameter   SW_LOC=0
 )(
-        destport_in,
-        destport_o
+    destport_in,
+    destport_o
 );
-
+    
     input  [K :0]    destport_in;
     output [K :0]    destport_o;
-
+    
     localparam [K-1 : 0] SW_LOC_ONHOT = 1<< SW_LOC; 
     
-   
     wire going_up = destport_in[K];
     assign destport_o = (going_up)?  {1'b1,SW_LOC_ONHOT[K-1 : 0]} : destport_in;
-
 endmodule
 
-
-
 /*************************
  *  fattree_conventional_routing 
  * **********************/
-
-
-module fattree_conventional_routing #(
-    parameter ROUTE_NAME = "NCA_RND_UP",
-    parameter K   = 2, // number of last level individual router`s endpoints.
-    parameter L   = 2 // Fattree layer number (The height of FT)
- )
-(
+module fattree_conventional_routing (
     reset,
     clk,
     current_addr_encoded,    // connected to current router x address
     current_level,    //connected to current router y address
     dest_addr_encoded,        // destination address
     destport_encoded    // router output port
-        
 );
-    
-
-    function integer log2;
-      input integer number; begin   
-         log2=(number <=1) ? 1: 0;    
-         while(2**log2<number) begin    
-            log2=log2+1;    
-         end        
-      end   
-    endfunction // log2 
-
-        
-    localparam
-        Kw = log2(K),
-        LKw= L*Kw,
-        Lw = log2(L);
-       
-       
-        
+    import pronoc_pkg::*;
     input reset,clk;
     input  [LKw-1 :0]    current_addr_encoded;
     input  [Lw-1  :0]    current_level;    
     input  [LKw-1 :0]    dest_addr_encoded;
     output [K :0]    destport_encoded;
-
-
     generate 
     /* verilator lint_off WIDTH */ 
     if( ROUTE_NAME == "NCA_RND_UP")begin :nca_rnd
@@ -419,9 +308,7 @@ module fattree_conventional_routing #(
         fattree_nca_random_up_routing #(
             .K(K),
             .L(L)
-        )
-        nca_random_up
-        (
+        ) nca_random_up (
             .reset(reset),
             .clk(clk),
             .current_addr_encoded(current_addr_encoded),
@@ -435,9 +322,7 @@ module fattree_conventional_routing #(
         fattree_nca_destp_up_routing #(
             .K(K),
             .L(L)
-        )
-        nca_random_up
-        (
+        )nca_random_up (
             .reset(reset),
             .clk(clk),
             .current_addr_encoded(current_addr_encoded),
@@ -445,15 +330,13 @@ module fattree_conventional_routing #(
             .dest_addr_encoded(dest_addr_encoded),
             .destport_encoded(destport_encoded)
         );
-   /* verilator lint_off WIDTH */ 
-   end else if ( ROUTE_NAME == "NCA_STRAIGHT_UP")begin :nca_straight
+    /* verilator lint_off WIDTH */ 
+    end else if ( ROUTE_NAME == "NCA_STRAIGHT_UP")begin :nca_straight
     /* verilator lint_on WIDTH */ 
         fattree_nca_straight_up_routing #(
             .K(K),
             .L(L)
-        )
-        nca_straight_up
-        (
+        )  nca_straight_up (
             .reset(reset),
             .clk(clk),
             .current_addr_encoded(current_addr_encoded),
@@ -462,76 +345,49 @@ module fattree_conventional_routing #(
             .destport_encoded(destport_encoded)
         );
     end else begin 
-        // synthesis translate_off
+        `ifdef SIMULATION
         initial begin 
             $display( "\t ERROR: %s is an undefined routing algorithm for FATTREE topology",ROUTE_NAME);
             $finish;
         end
-        // synthesis translate_on
+        `endif
     end
     endgenerate
-
 endmodule
 
-
 /************************************
-
-     fattree_look_ahead_routing
-
-*************************************/
-
+*    fattree_look_ahead_routing
+**************************************/
 module fattree_look_ahead_routing #(
-    parameter ROUTE_NAME = "NCA_RND_UP",
-    parameter P = 4,
-    parameter L = 2,
-    parameter K = 2
-   
-)
-(
+    parameter P = 4
+)(
     reset,
     clk,
     destport_encoded,// current router destination port 
     dest_addr_encoded,
     neighbors_rx,
     neighbors_ry,
-    lkdestport_encoded // look ahead destination port     
+    lkdestport_encoded // look ahead destination port
 );
+    import pronoc_pkg::*;
     
-   function integer log2;
-      input integer number; begin   
-         log2=(number <=1) ? 1: 0;    
-         while(2**log2<number) begin    
-            log2=log2+1;    
-         end        
-      end   
-    endfunction // log2 
-
-        
     localparam
-        Kw = log2(K),
-        LKw= L*Kw,
-        Lw = log2(L),
         PLw = P * Lw,
         PLKw = P * LKw;
-   
+    
     input  [K :0]    destport_encoded;
     input  [LKw-1 :0]    dest_addr_encoded;
     input  [PLKw-1 : 0]  neighbors_rx;
     input  [PLw-1 : 0]  neighbors_ry;
     output [K: 0]    lkdestport_encoded;
-    input                   reset,clk;
+    input  reset,clk;
     
-    wire  [K :0]    destport_encoded_delayed;
-    wire  [LKw-1 :0]    dest_addr_encoded_delayed;
+    logic [K :0] destport_encoded_delayed;
+    logic [LKw-1 :0] dest_addr_encoded_delayed;
     
-     fattree_deterministic_look_ahead_routing #(
-        .P(P),
-        .ROUTE_NAME(ROUTE_NAME),
-        .K(K),
-        .L(L)
-     )
-     look_ahead_routing
-     (
+    fattree_deterministic_look_ahead_routing #(
+        .P(P)
+    ) look_ahead_routing (
         .reset(reset),
         .clk(clk),
         .destport_encoded(destport_encoded_delayed),
@@ -539,53 +395,27 @@ module fattree_look_ahead_routing #(
         .neighbors_rx(neighbors_rx),
         .neighbors_ry(neighbors_ry),
         .lkdestport_encoded(lkdestport_encoded)
-     );
-     
-     
-      pronoc_register #(
-           .W(K+1)
-      ) reg1 ( 
-           .in(destport_encoded),
-           .reset(reset),    
-           .clk(clk),      
-           .out(destport_encoded_delayed)
-      );
-     
-       pronoc_register #(
-           .W(LKw)
-      ) reg2 ( 
-           .in(dest_addr_encoded),
-           .reset(reset),    
-           .clk(clk),      
-           .out(dest_addr_encoded_delayed)
-      );
-     
-     
-        
-
+    );
     
+    always_ff @ (`pronoc_clk_reset_edge ) begin
+        if(`pronoc_reset) begin
+            // reset the delayed values
+            destport_encoded_delayed   <= {(K+1){1'b0}};
+            dest_addr_encoded_delayed  <= {LKw{1'b0}};
+        end else begin
+            destport_encoded_delayed   <= destport_encoded;
+            dest_addr_encoded_delayed  <= dest_addr_encoded;
+        end
+    end
 endmodule
 
 
-
-
-
- 
-
 /************************************************
-
-        deterministic_look_ahead_routing
+*        deterministic_look_ahead_routing
 **********************************************/
-
-
 module  fattree_deterministic_look_ahead_routing #(
-    parameter P=4,
-    parameter ROUTE_NAME = "NCA_RND_UP",
-    parameter K   = 2, // number of last level individual router`s endpoints.
-    parameter L   = 2 // Fattree layer number (The height of FT)
-    
-  )
-  (
+    parameter P=4
+)(
     reset,
     clk,
     destport_encoded,// current router destination port 
@@ -593,34 +423,20 @@ module  fattree_deterministic_look_ahead_routing #(
     neighbors_rx,
     neighbors_ry,
     lkdestport_encoded // look ahead destination port     
- );
+);
+    import pronoc_pkg::*;
     
-   
-   function integer log2;
-      input integer number; begin   
-         log2=(number <=1) ? 1: 0;    
-         while(2**log2<number) begin    
-            log2=log2+1;    
-         end        
-      end   
-    endfunction // log2 
-
-        
     localparam
-        Kw = log2(K),
-        LKw= L*Kw,
-        Lw = log2(L),
         PLw = P * Lw,
         PLKw = P * LKw;
-                    
+        
     input reset,clk;
     input  [K :0]    destport_encoded;
     input  [LKw-1 :0]    dest_addr_encoded;
     input  [PLKw-1 : 0]  neighbors_rx;
     input  [PLw-1 : 0]  neighbors_ry;
     output [K: 0]    lkdestport_encoded;
-      
-      
+    
     wire  [LKw-1 :0]    next_addr_encoded;
     wire  [Lw-1  :0]    next_level;  
     wire  [K : 0] lkdestport_encoded;  
@@ -628,35 +444,24 @@ module  fattree_deterministic_look_ahead_routing #(
     
     fattree_destport_decoder #(
         .K(K)
-    )
-    fattree_destport_decoder(
+    ) fattree_destport_decoder(
         .destport_encoded_i(destport_encoded),
         .destport_decoded_o(destport_decoded)
     ); 
-        
     
     next_router_addr_selector_onehot #(
-         .P(P),
-         .RXw(LKw), 
-         .RYw(Lw)
-    )
-    addr_predictor
-    (
+        .P(P),
+        .RXw(LKw), 
+        .RYw(Lw)
+    ) addr_predictor (
         .destport_onehot(destport_decoded[P-1 : 0]),
         .neighbors_rx(neighbors_rx),
         .neighbors_ry(neighbors_ry),
         .next_rx(next_addr_encoded),
         .next_ry(next_level)
     );
-      
-  
-    fattree_conventional_routing #(        
-        .ROUTE_NAME(ROUTE_NAME),
-        .K(K),
-        .L(L)        
-    )
-    conv_routing
-    (
+    
+    fattree_conventional_routing  conv_routing (
         .reset(reset),
         .clk(clk),
         .current_addr_encoded(next_addr_encoded),
@@ -664,27 +469,22 @@ module  fattree_deterministic_look_ahead_routing #(
         .dest_addr_encoded(dest_addr_encoded),
         .destport_encoded(lkdestport_encoded)
     );
-     
- endmodule
- 
- module fattree_destport_decoder #(
-     parameter K=2
- 
- )(
+    
+endmodule
+
+
+module fattree_destport_decoder #(
+    parameter K=2
+)(
     destport_decoded_o,
     destport_encoded_i  
- );
- 
+);
     input [K:0] destport_encoded_i;
     output [2*K-1 : 0] destport_decoded_o;     
-    
-    assign destport_decoded_o =   (destport_encoded_i[K])? /*go up*/    {destport_encoded_i[K-1:0],{K{1'b0}}}:
-                                                           /*go down*/   {{K{1'b0}},destport_encoded_i[K-1:0]};    
-   
+    assign destport_decoded_o =   
+        (destport_encoded_i[K])? /*go up*/    {destport_encoded_i[K-1:0],{K{1'b0}}}:
+                                /*go down*/   {{K{1'b0}},destport_encoded_i[K-1:0]};    
 endmodule
- 
-
-
 
 /**********
  *  fattree_mask_non_assignable_destport
@@ -694,15 +494,12 @@ module fattree_mask_non_assignable_destport #(
     parameter K=4,
     parameter P=2*K,
     parameter SW_LOC = 0        
-)
-(
+)(
     destport_in,
     destport_out        
 );
-
     input [2*K-1 : 0] destport_in;
     output [2*K-1 : 0] destport_out;
-    
     generate 
     if(P<=K)begin :root //This is a root node there is conectivety between all ports
         assign destport_out = destport_in;    
@@ -718,11 +515,8 @@ module fattree_mask_non_assignable_destport #(
 endmodule
 
 /********************
-
-    distance_gen 
-     
+*    distance_gen 
 ********************/
-
 module fattree_distance_gen #(
     parameter K= 4,    
     parameter L= 4
@@ -730,34 +524,25 @@ module fattree_distance_gen #(
     src_addr_encoded,    
     dest_addr_encoded,       
     distance
-
 );
-
     function integer log2;
-      input integer number; begin   
-         log2=(number <=1) ? 1: 0;    
-         while(2**log2<number) begin    
+    input integer number; begin   
+        log2=(number <=1) ? 1: 0;    
+        while(2**log2<number) begin    
             log2=log2+1;    
-         end       
-      end   
+        end       
+    end   
     endfunction // log2 
-
-     localparam
+    localparam
         Kw = log2(K),
         LKw= L*Kw,
         DISTw= log2(2*L+1);
-
-     input  [LKw-1 :0]    src_addr_encoded;
-     input  [LKw-1 :0]    dest_addr_encoded;
-     output reg [DISTw-1 : 0] distance;
-     
-    
-     
-     wire  [Kw-1 :0]  dest_addr [L-1 : 0];
-     wire  [Kw-1 :0]  src_addr [L-1 : 0];
-     wire  [L-1 : 0] diffrent;
-     
-    
+    input  [LKw-1 :0]    src_addr_encoded;
+    input  [LKw-1 :0]    dest_addr_encoded;
+    output reg [DISTw-1 : 0] distance;
+    wire  [Kw-1 :0]  dest_addr [L-1 : 0];
+    wire  [Kw-1 :0]  src_addr [L-1 : 0];
+    wire  [L-1 : 0] diffrent;
     genvar i;
     generate 
     for(i=0; i<L; i=i+1)begin : daddr      
@@ -766,7 +551,7 @@ module fattree_distance_gen #(
         assign diffrent[i] = dest_addr [i] != src_addr [i];
     end//for
     endgenerate
-     
+    
     wire [11:0] tmp;
     assign tmp= {{(12-L){1'b0}},diffrent};
     /* verilator lint_off WIDTH */
@@ -784,10 +569,6 @@ module fattree_distance_gen #(
         else distance =1;    
     end
     /* verilator lint_on WIDTH */
-
-
-  
-
 endmodule
 
 /**************
@@ -798,19 +579,18 @@ endmodule
 module  fattree_addr_encoder #(
     parameter   K=2,
     parameter   L=2
-
 )(
     id,
     code
 );
     
     function integer log2;
-      input integer number; begin   
-         log2=(number <=1) ? 1: 0;    
-         while(2**log2<number) begin    
+    input integer number; begin   
+        log2=(number <=1) ? 1: 0;    
+        while(2**log2<number) begin    
             log2=log2+1;    
-         end        
-      end   
+        end        
+    end   
     endfunction // log2 
     
     function integer powi;
@@ -822,7 +602,7 @@ module  fattree_addr_encoder #(
         end
         end   
     endfunction // log2 
-        
+    
     function integer addrencode;
         input integer pos,k,n,kw;
         integer pow,i,tmp;begin
@@ -837,18 +617,15 @@ module  fattree_addr_encoder #(
         end
         end   
     endfunction // log2 
-        
-      
+    
     localparam       
         NE = powi( K,L ),  //total number of endpoints
         NEw = log2(NE),
         Kw=log2(K),
         LKw=L*Kw;
-
-
-     input [NEw-1 :0] id;
-     output [LKw-1 : 0] code;
-
+    input [NEw-1 :0] id;
+    output [LKw-1 : 0] code;
+    
     wire [LKw-1 : 0 ] codes [NE-1 : 0];
     genvar i;
     generate 
@@ -858,33 +635,30 @@ module  fattree_addr_encoder #(
         assign codes[i] = ENDPX;            
     end
     endgenerate
-
+    
     assign code = codes[id];
 endmodule
 
 
-
 /**************
-    fattree_addr_decoder
-    most probably it is only needed for simulation 
+*    fattree_addr_decoder
+*    most probably it is only needed for simulation 
 ***************/  
-
 module  fattree_addr_decoder #(
     parameter   K=2,
     parameter   L=2
-
 )(
     id,
     code
 );
     
     function integer log2;
-      input integer number; begin   
-         log2=(number <=1) ? 1: 0;    
-         while(2**log2<number) begin    
+    input integer number; begin   
+        log2=(number <=1) ? 1: 0;    
+        while(2**log2<number) begin    
             log2=log2+1;    
-         end        
-      end   
+        end        
+    end   
     endfunction // log2 
     
     function integer powi;
@@ -896,7 +670,7 @@ module  fattree_addr_decoder #(
         end
         end   
     endfunction // log2 
-        
+    
     function integer addrencode;
         input integer pos,k,n,kw;
         integer pow,i,tmp;begin
@@ -911,18 +685,15 @@ module  fattree_addr_decoder #(
         end
         end   
     endfunction // log2 
-        
-      
+    
     localparam       
         NE = powi( K,L ),  //total number of endpoints
         NEw = log2(NE),
         Kw=log2(K),
         LKw=L*Kw;
-
-
-     output [NEw-1 :0] id;
-     input  [LKw-1 : 0] code;
-
+    output [NEw-1 :0] id;
+    input  [LKw-1 : 0] code;
+    
     wire  [NEw-1 : 0] codes  [2**LKw-1 : 0 ];
     genvar i;
     generate 
@@ -934,48 +705,40 @@ module  fattree_addr_decoder #(
         assign codes[ENDPX] = i;            
     end
     endgenerate
-
+    
     assign id = codes[code];
 endmodule
 
 /**************
- * mesh_torus_ssa_check_destport_conflict
+ * fattree_ssa_check_destport_conflict
  * check if the incomming flit goes to SS port
  * ************/
-
 module fattree_ssa_check_destport #(
     parameter DSTPw = 5,
     parameter SS_PORT=0
-)
-(
+)(
     destport_encoded, //exsited packet dest port
     destport_in_encoded, // incomming packet dest port
     ss_port_hdr_flit, // asserted if the header incomming flit goes to ss port
     ss_port_nonhdr_flit // asserted if the body or tail incomming flit goes to ss port
- );
-
+);
     localparam K= DSTPw-1;
     localparam SS_LOC = (SS_PORT < K)? SS_PORT : SS_PORT-K;
     
     input [DSTPw-1 : 0] destport_encoded, destport_in_encoded; 
     output ss_port_hdr_flit, ss_port_nonhdr_flit;
-
-
-/******************
-        destport_encoded format in fat tree. K+1 bit
-        destport[K] 
-            1'b0  : go down 
-            1'b1  : go up
-        destport[K-1: 0]: 
-            onehot coded. asserted bit show the output port locatation     
-*******************/
-    
+    /******************
+    *        destport_encoded format in fat tree. K+1 bit
+    *        destport[K] 
+    *            1'b0  : go down 
+    *            1'b1  : go up
+    *        destport[K-1: 0]: 
+    *            onehot coded. asserted bit show the output port locatation     
+    *******************/
     wire up_flg = destport_encoded[DSTPw-1];
     wire up_flg_in = destport_in_encoded[DSTPw-1];
     wire down_flg = ~destport_encoded[DSTPw-1];
     wire down_flg_in = ~destport_in_encoded[DSTPw-1];   
-    
-    
     generate 
     if(SS_PORT < K) begin :SS_DOWN // the ssa port is located in down router side
         assign ss_port_hdr_flit = destport_in_encoded [SS_LOC] & down_flg_in;   
@@ -985,7 +748,6 @@ module fattree_ssa_check_destport #(
         assign ss_port_nonhdr_flit =  destport_encoded[SS_LOC] & up_flg;       
     end
     endgenerate    
-    
 endmodule
 
 /*
@@ -1005,122 +767,74 @@ module fattree_add_ss_port #(
                                         (SW_LOC < ((P+1)/2) )? ((P+1)/2)+ SW_LOC-1 : SW_LOC - ((P+1)/2);
         
     localparam  SS_PORT_FATTREE = (P[0]==1'b0) ? SS_PORT_FATTREE_EVEN : SS_PORT_FATTREE_ODD;
-
     localparam  SS_PORT      =   SS_PORT_FATTREE;
-     
-          
-    
-     
     input       [P_1-1  :   0] destport_in;
     output reg  [P_1-1  :   0] destport_out; 
-     
-     
-     
     always @(*)begin 
         destport_out=destport_in;
         if( SS_PORT != DISABLED ) begin 
             if(destport_in=={P_1{1'b0}}) destport_out[SS_PORT]= 1'b1;
         end    
     end 
-     
-
 endmodule
  */
-module fattree_router_addr_decode #(
-    parameter K=4,
-    parameter L=4
-)(
+
+
+module fattree_router_addr_decode (
     r_addr,
     rx,
     rl
     //valid
 );
-
-    function integer log2;
-      input integer number; begin   
-         log2=(number <=1) ? 1: 0;    
-         while(2**log2<number) begin    
-            log2=log2+1;    
-         end        
-      end   
-    endfunction // log2 
-    
-    
-    localparam
-        Kw = log2(K),
-        LKw= L*Kw,
-        Lw = log2(L),
-        RAw= LKw + Lw;
-    
+    import pronoc_pkg::*;
     input   [RAw-1 : 0]   r_addr;
     output  [LKw-1 :0]    rx;
-    output  [Lw-1  :0]    rl;  
-    
+    output  [Lw-1  :0]    rl;
     assign {rl,rx} = r_addr;
-    
 endmodule
 
-  
+
 //decode and mask destport  
 module  fattree_destp_generator #(
     parameter K=2,
     parameter P=2*K,
     parameter SW_LOC=0,
     parameter DSTPw=4,
-    parameter SELF_LOOP_EN = "NO"
+    parameter SELF_LOOP_EN = 0
 )(
     dest_port_in_encoded,
     dest_port_out
 );
 
-    localparam P_1 = (SELF_LOOP_EN == "NO")? P-1 : P;
+    localparam P_1 = (SELF_LOOP_EN )?  P : P-1;
     input  [DSTPw-1:0] dest_port_in_encoded;
     output [P_1-1 : 0] dest_port_out;
     
-    
     wire [2*K-1 : 0] destport_decoded;
     wire [2*K-1 : 0] destport_masked;
-    
 
-        fattree_destport_decoder #(           
-            .K(K)
-        )
-        destport_decoder
-        (
-            .destport_encoded_i(dest_port_in_encoded),
-            .destport_decoded_o(destport_decoded)
-        );
-       
-        fattree_mask_non_assignable_destport #(
-            .K(K),
-            .P(P),
-            .SW_LOC(SW_LOC)        
-        )
-        mask
-        (
-            .destport_in(destport_decoded),
-            .destport_out(destport_masked)        
-        );
-       
-        generate 
-        if(SELF_LOOP_EN == "NO") begin : nslp
-            remove_sw_loc_one_hot #(
-                .P(P),
-                .SW_LOC(SW_LOC)
-            )
-            conv
-            (
-                .destport_in(destport_masked[P-1 : 0]),
-                .destport_out(dest_port_out[P_1-1  :   0 ])
-            );  
-        end else begin : slp 
-            assign dest_port_out= destport_masked [P_1-1  :   0 ];
-        end
-        endgenerate
- endmodule
- 
- 
- 
- 
-
- 
+    fattree_destport_decoder #(
+        .K(K)
+    )destport_decoder (
+        .destport_encoded_i(dest_port_in_encoded),
+        .destport_decoded_o(destport_decoded)
+    );
+    
+    fattree_mask_non_assignable_destport #(
+        .K(K),
+        .P(P),
+        .SW_LOC(SW_LOC)
+    ) mask  (
+        .destport_in(destport_decoded),
+        .destport_out(destport_masked)
+    );
+    
+    destport_non_selfloop_fix #(
+        .SELF_LOOP_EN(SELF_LOOP_EN),
+        .P(P),
+        .SW_LOC(SW_LOC)
+    ) conv (
+        .destport_in(destport_masked[P-1 : 0]),
+        .destport_out(dest_port_out[P_1-1  :   0 ])
+    );  
+endmodule
diff --git a/mpsoc/rtl/src_noc/flit_buffer.sv b/mpsoc/rtl/src_noc/flit_buffer.sv
index 1b7241a..0d948f6 100755
--- a/mpsoc/rtl/src_noc/flit_buffer.sv
+++ b/mpsoc/rtl/src_noc/flit_buffer.sv
@@ -1,1310 +1,959 @@
 `include "pronoc_def.v"
 /**********************************************************************
- **	File:  flit_buffer.v
+ **    File: flit_buffer.v
  **    
- **	Copyright (C) 2014-2017  Alireza Monemi
+ **    Copyright (C) 2014-2017  Alireza Monemi
  **    
- **	This file is part of ProNoC 
+ **    This file is part of ProNoC
  **
- **	ProNoC ( stands for Prototype Network-on-chip)  is free software: 
- **	you can redistribute it and/or modify it under the terms of the GNU
- **	Lesser General Public License as published by the Free Software Foundation,
- **	either version 2 of the License, or (at your option) any later version.
+ **    ProNoC ( stands for Prototype Network-on-chip)  is free software: 
+ **    you can redistribute it and/or modify it under the terms of the GNU
+ **    Lesser General Public License as published by the Free Software Foundation,
+ **    either version 2 of the License, or (at your option) any later version.
  **
- ** 	ProNoC is distributed in the hope that it will be useful, but WITHOUT
- ** 	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
- ** 	or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
- ** 	Public License for more details.
+ **     ProNoC is distributed in the hope that it will be useful, but WITHOUT
+ **     ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ **     or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
+ **     Public License for more details.
  **
- ** 	You should have received a copy of the GNU Lesser General Public
- ** 	License along with ProNoC. If not, see <http:**www.gnu.org/licenses/>.
+ **     You should have received a copy of the GNU Lesser General Public
+ **     License along with ProNoC. If not, see <http:**www.gnu.org/licenses/>.
  **
  **
- **	Description: 
- **	Input buffer module. All VCs located in the same router 
- **	input port share one single FPGA BRAM 
+ **    Description: 
+ **    Input buffer module. All VCs located in the same router
+ **    input port share one single FPGA BRAM
  **
  **************************************************************/
 
 
-module flit_buffer 
-	#(
-		parameter B =4,
-		parameter SSA_EN="YES", // "YES" , "NO" 
-		parameter Fw=32,
-		parameter PCK_TYPE ="MULTI_FLIT",
-		parameter CAST_TYPE = "UNICAST",
-		parameter DEBUG_EN = 1,
-		parameter V=1
-		)	
-		(
-			din,     // Data in
-			vc_num_wr,//write virtual channel   
-			vc_num_rd,//read virtual channel    
-			wr_en,   // Write enable
-			rd_en,   // Read the next word
-			dout,    // Data out
-			vc_not_empty,
-			reset,
-			clk,
-			ssa_rd,
+module flit_buffer #(
+    parameter PORT_IVC = 1,
+    parameter PORT_B = 4
+)(
+    din,  // Data in
+    vc_num_wr,//write virtual channel
+    vc_num_rd,//read virtual channel
+    wr_en,   // Write enable
+    rd_en,   // Read the next word
+    dout,    // Data out
+    vc_not_empty,
+    reset,
+    clk,
+    ssa_rd,
+    //for multicast
+    multiple_dest, // incr rd-sub
+    sub_rd_ptr_ld,  // load rd_ptr to sub_rd_pt
+    flit_is_tail
+);
+    
+    import pronoc_pkg::*;
+    localparam
+        PORT_Bw = (PORT_B==1)? 1 : log2(PORT_B),
+        BV = PORT_B   *   PORT_IVC,
+        BVw = log2(BV),
+        PORT_Vw = (PORT_IVC==1)? 1 : log2(PORT_IVC),
+        DEPTHw = log2(PORT_B+1),
+        RESTw = Fw - 2 - V,
+        PTRw = ((2**PORT_Bw)==PORT_B)? PORT_Bw : BVw, // if B is power of 2 PTRw is Bw else is BVw
+        ARRAYw = PTRw * PORT_IVC,
+        RAM_DATA_WIDTH = (IS_MULTI_FLIT)? Fw - V : Fw - V - 2;
+    
+    input [Fw-1 :0]   din;     // Data in
+    input [PORT_IVC-1 :0]   vc_num_wr;//write virtual chanel
+    input [PORT_IVC-1 :0]   vc_num_rd;//read virtual chanel
+    input wr_en;   // Write enable
+    input rd_en;   // Read the next word
+    output [Fw-1 :0]  dout;    // Data out
+    output [PORT_IVC-1 :0]  vc_not_empty;
+    input  reset;
+    input  clk;
+    input [PORT_IVC-1 :0]  ssa_rd;
+    input [PORT_IVC-1 :0]  multiple_dest;
+    input [PORT_IVC-1 :0]  sub_rd_ptr_ld;
+    output [PORT_IVC-1 : 0]  flit_is_tail;
+    
+    //pointers
+    logic [PTRw- 1 : 0] rd_ptr [PORT_IVC-1 :0];
+    logic [PTRw- 1 : 0] wr_ptr [PORT_IVC-1 :0];
+    reg [PTRw- 1 : 0] rd_ptr_next [PORT_IVC-1 :0];
+    reg [PTRw- 1 : 0] wr_ptr_next [PORT_IVC-1 :0];
+    reg [PTRw- 1 : 0] sub_rd_ptr_next [PORT_IVC-1 :0];
+    logic [PTRw- 1 : 0] sub_rd_ptr [PORT_IVC-1 :0];
+    
+    wire [RAM_DATA_WIDTH-1 : 0] fifo_ram_din;
+    wire [RAM_DATA_WIDTH-1 : 0] fifo_ram_dout;
+    wire [PORT_IVC-1 : 0] wr;
+    wire [PORT_IVC-1 : 0] rd;
+    logic [DEPTHw-1 : 0] depth [PORT_IVC-1 :0];
+    logic [DEPTHw-1 : 0] depth_next [PORT_IVC-1 :0];
+    logic [DEPTHw-1 : 0] sub_depth [PORT_IVC-1 :0];
+    logic [DEPTHw-1 : 0] sub_depth_next  [PORT_IVC-1 :0];
+    
+    reg [PORT_B-1 : 0] tail_fifo [PORT_IVC-1 : 0];
+    wire [1 : 0] flgs_in, flgs_out;
+    wire [V-1: 0] vc_in;
+    wire [RESTw-1 :0      ] flit_rest_in,flit_rest_out;
+    wire [PORT_IVC-1 : 0] sub_rd;
+    wire [PORT_IVC-1 : 0] sub_restore;
+    
+    assign  wr = (wr_en)?  vc_num_wr : {PORT_IVC{1'b0}};
+    
+    genvar i;
+    generate
+    if (~IS_UNICAST) begin : nouni
+        assign  sub_rd = (rd_en)?  vc_num_rd : ssa_rd; 
+        assign  sub_restore = sub_rd_ptr_ld; 
+        assign  rd = (rd_en)?  vc_num_rd & ~multiple_dest : ssa_rd & ~multiple_dest;
+    end else begin : unicast
+        assign  rd = (rd_en)?  vc_num_rd : ssa_rd;
+        assign  sub_rd = '0;
+        assign  sub_restore = '0;
+    end
+    
+    if (IS_MULTI_FLIT) begin :multi
+        assign {flgs_in,vc_in,flit_rest_in}=din;
+        assign fifo_ram_din = {flgs_in,flit_rest_in};
+        assign {flgs_out,flit_rest_out} = fifo_ram_dout;
+        assign dout = {flgs_out,{V{1'b0}},flit_rest_out};
+    end else begin : single
+        assign fifo_ram_din = din[RAM_DATA_WIDTH-1 : 0];
+        assign dout = {2'b11,{V{1'b0}},fifo_ram_dout};
+    end
+    
+    always_comb begin
+        for(int k=0;k<V;k++) begin 
+            if (~IS_UNICAST) begin
+                sub_depth_next [k] = sub_depth [k];
+                if(sub_restore[k]) sub_depth_next [k]= depth_next[k];
+                else if (wr[k] & ~sub_rd[k]) sub_depth_next [k] = sub_depth[k] + 1'h1;
+                else if (~wr[k] & sub_rd[k]) sub_depth_next [k] = sub_depth[k] - 1'h1;
+            end else sub_depth_next [k] = '0;
+        end
+    end
+    
+    always_comb begin
+        for(int k=0;k<PORT_IVC;k++) begin 
+            if (~IS_UNICAST) begin 
+                sub_rd_ptr_next[k] = sub_rd_ptr[k];
+                if((2**PORT_Bw)==PORT_B) begin 
+                    if (sub_restore[k]) sub_rd_ptr_next[k] = rd_ptr_next [k];
+                    else if(sub_rd[k])  sub_rd_ptr_next[k] = sub_rd_ptr[k]+ 1'h1;
+                end else begin 
+                    if (sub_restore[k]) sub_rd_ptr_next[k] = rd_ptr_next [k];
+                    else if(sub_rd[k])  sub_rd_ptr_next[k] = (sub_rd_ptr[k] == PTRw'((PORT_B * (k + 1)) - 1)) ?  PTRw'(PORT_B * k) :  sub_rd_ptr[k] + PTRw'(1);
+                end // PORT_Bw
+            end else sub_rd_ptr_next[k] = '0;
+        end //for
+    end //always_comb
+    
+    for(i=0;i<PORT_IVC;i=i+1) begin :V_
+        localparam RESET_TO = ((2**PORT_Bw)==PORT_B)? 0 : PORT_B*i;
+        always_ff @ (`pronoc_clk_reset_edge )begin 
+            if(`pronoc_reset) begin 
+                sub_rd_ptr[i] <= PTRw'(RESET_TO);
+                sub_depth[i]  <= {DEPTHw{1'b0}};
+            end else begin
+                sub_rd_ptr[i] <= sub_rd_ptr_next[i];
+                sub_depth[i]  <= sub_depth_next[i];
+            end
+        end
+        if (~IS_UNICAST) begin
+            assign  vc_not_empty [i] = (sub_depth[i] > 0);
+        end else begin : unicast
+            assign  vc_not_empty [i] = (depth[i] > 0);
+        end
+    end//for
+    
+    always_comb begin
+        for(int k=0;k<PORT_IVC;k=k+1) begin
+            rd_ptr_next [k] = rd_ptr  [k];
+            wr_ptr_next [k] = wr_ptr  [k];
+            depth_next  [k] = depth   [k];
+            if((2**PORT_Bw)==PORT_B) begin
+                if (wr[k]  ) wr_ptr_next [k] = wr_ptr [k]+ 1'h1;
+                if (rd[k]  ) rd_ptr_next [k] = rd_ptr [k]+ 1'h1;
+            end else begin 
+                if (wr[k] ) wr_ptr_next[k] =(wr_ptr[k]==PTRw'(PORT_B*(k+1)-1)) ? PTRw'(PORT_B*k) : wr_ptr [k] + PTRw'(1);
+                if (rd[k] ) rd_ptr_next[k] =(rd_ptr[k]==PTRw'(PORT_B*(k+1)-1)) ? PTRw'(PORT_B*k) : rd_ptr [k] + PTRw'(1);
+            end
+            if (wr[k] & ~rd[k]) depth_next [k] = depth[k] + 1'h1;
+            else if (~wr[k] & rd[k]) depth_next [k] = depth[k] - 1'h1;
+        end
+    end//always
+    
+    logic [PTRw-1 : 0]  vc_wr_addr, vc_rd_addr; 
+    logic [PORT_Vw-1 : 0]  wr_select_addr, rd_select_addr; 
+    always_comb begin
+        vc_wr_addr = '0;
+        vc_rd_addr = '0;
+        wr_select_addr = '0;
+        rd_select_addr = '0;
+        for (int k = 0; k < PORT_IVC; k++) begin
+            //One-hot_mux
+            vc_wr_addr |= (vc_num_wr[k]) ?  wr_ptr[k] :  '0;
+            if (IS_UNICAST) vc_rd_addr |= (vc_num_rd[k]) ?  rd_ptr[k] :  '0;
+            else vc_rd_addr |= (vc_num_rd[k]) ?  sub_rd_ptr[k] :  '0;
+            //One-hot to binary
+            if (vc_num_wr[k]) wr_select_addr = PORT_Vw'(k);
+            if (vc_num_rd[k]) rd_select_addr = PORT_Vw'(k);
+        end
+    end
+    
+    if((2**PORT_Bw)==PORT_B)begin : pow2
+    /***************************
+    * Buffer width is power of 2
+    ***************************/
+        wire [PORT_Bw+PORT_Vw-1 : 0]  wr_addr, rd_addr;
+        assign  wr_addr = {wr_select_addr,vc_wr_addr};
+        assign  rd_addr = {rd_select_addr,vc_rd_addr};
         
-			//for multicast
-			multiple_dest, // incr rd-sub
-			sub_rd_ptr_ld,  // load rd_ptr to sub_rd_pt  
-			flit_is_tail
-		);
-
-     function  integer log2;
-      input integer number; begin   
-         log2=(number <=1) ? 1: 0;    
-         while(2**log2<number) begin    
-            log2=log2+1;    
-         end       
-      end   
-    endfunction // log2 
-   
-    
-	localparam      
-		Bw      =   (B==1)? 1 : log2(B),
-		BV      =   B   *   V,
-		BVw              =   log2(BV),              
-		Vw               =  (V==1)? 1 : log2(V),
-		DEPTHw           =   log2(B+1),
-		BwV              =   Bw * V,
-		BVwV             =   BVw * V,               
-		RESTw = Fw -2-V , 
-		PTRw = ((2**Bw)==B)? Bw : BVw, // if B is power of 2 PTRw is Bw else is BVw
-		ARRAYw = PTRw * V,
-		/* verilator lint_off WIDTH */ 
-		RAM_DATA_WIDTH   = (PCK_TYPE == "MULTI_FLIT")? Fw - V :  Fw - V -2;
-	/* verilator lint_on WIDTH */ 
-    	
-    	
-    
-    
-	input  [Fw-1      :0]   din;     // Data in
-	input  [V-1       :0]   vc_num_wr;//write virtual chanel   
-	input  [V-1       :0]   vc_num_rd;//read virtual chanel    
-	input                   wr_en;   // Write enable
-	input                   rd_en;   // Read the next word
-	output [Fw-1       :0]  dout;    // Data out
-	output [V-1        :0]  vc_not_empty;
-	input                   reset;
-	input                   clk;
-	input  [V-1        :0]  ssa_rd;   
-	input  [V-1        :0]  multiple_dest;
-	input  [V-1        :0]  sub_rd_ptr_ld;       
-	output [V-1 : 0]        flit_is_tail; 				    
-       
-    
-	//pointers
-	wire [PTRw- 1     :   0] rd_ptr [V-1          :0];
-	wire [PTRw- 1     :   0] wr_ptr [V-1          :0];    
-	reg  [PTRw- 1     :   0] rd_ptr_next [V-1          :0];
-	reg  [PTRw- 1     :   0] wr_ptr_next [V-1          :0];
-	reg  [PTRw- 1     :   0] sub_rd_ptr_next [V-1          :0];
-	wire [PTRw- 1     :   0] sub_rd_ptr [V-1          :0];    	
-	wire [PTRw-1      :   0] ptr_tmp  [V-1 : 0];
-	wire [ARRAYw-1    :   0] rd_ptr_array;
-	wire [ARRAYw-1    :   0] wr_ptr_array;    
-   
-               
-	wire  [RAM_DATA_WIDTH-1     :   0] fifo_ram_din;
-	wire  [RAM_DATA_WIDTH-1     :   0] fifo_ram_dout;
-	wire  [V-1                  :   0] wr;
-	wire  [V-1                  :   0] rd;  
-	wire  [DEPTHw-1             :   0] depth      [V-1            :0];
-	reg   [DEPTHw-1             :   0] depth_next [V-1            :0];
-	wire  [DEPTHw-1             :   0] sub_depth       [V-1            :0];  
-	reg   [DEPTHw-1             :   0] sub_depth_next  [V-1            :0];  
-    
-    
-	reg   [B-1 : 0] tail_fifo [V-1 : 0];    
-	wire  [1  : 0] flgs_in, flgs_out;
-	wire  [V-1: 0] vc_in;
-	wire  [RESTw-1 :0      ] flit_rest_in,flit_rest_out;
-	wire  [V-1       :   0] sub_rd;
-	wire  [V-1       :   0] sub_restore;
-    
-	assign  wr  =   (wr_en)?  vc_num_wr : {V{1'b0}};
-   
-  
-
-	genvar i;
-
-	generate 
-	/* verilator lint_off WIDTH */ 
-		if (CAST_TYPE != "UNICAST") begin 
-			/* verilator lint_on WIDTH */ 
-			assign  sub_rd  =  (rd_en)?  vc_num_rd  : ssa_rd; 
-			assign  sub_restore = sub_rd_ptr_ld; 
-			assign  rd  =   (rd_en)?  vc_num_rd & ~multiple_dest : ssa_rd & ~multiple_dest;		    	
-		end else begin : unicast
-			assign  rd  =   (rd_en)?  vc_num_rd : ssa_rd;    	
-		end
-	
-		/* verilator lint_off WIDTH */ 
-		if (PCK_TYPE == "MULTI_FLIT") begin :multi
-			/* verilator lint_on WIDTH */    
-			assign {flgs_in,vc_in,flit_rest_in}=din;    
-			assign fifo_ram_din = {flgs_in,flit_rest_in};
-			assign {flgs_out,flit_rest_out} = fifo_ram_dout;
-			assign dout = {flgs_out,{V{1'bX}},flit_rest_out};    
-		end else begin : single
-			assign fifo_ram_din = din[RAM_DATA_WIDTH-1     :   0];
-			assign dout = {2'b11,{V{1'bX}},fifo_ram_dout};    
-		end
-    	
-    	
-		for(i=0;i<V;i=i+1) begin :V_
-			assign  wr_ptr_array[(i+1)*PTRw- 1        :   i*PTRw]   =       wr_ptr[i];  
-			
-			/* verilator lint_off WIDTH */ 
-			if (CAST_TYPE != "UNICAST") begin 
-				/* verilator lint_on WIDTH */ 
-				assign  rd_ptr_array[(i+1)*PTRw- 1 :   i*PTRw]   =       sub_rd_ptr[i]; 
-				localparam RESET_TO = ((2**Bw)==B)? 0 : B*i;
-				pronoc_register #(.W(PTRw),.RESET_TO(RESET_TO)) reg4 (.in(sub_rd_ptr_next[i]), .out(sub_rd_ptr[i]), .reset(reset), .clk(clk));
-				
-				
-				pronoc_register #(.W(DEPTHw)) sub_depth_reg (.in(sub_depth_next[i] ), .out(sub_depth [i]), .reset(reset), .clk(clk));
-				always @ (*)begin 
-					sub_depth_next  [i] = sub_depth   [i];
-					if(sub_restore[i]) sub_depth_next  [i]= depth_next[i];
-					else if (wr[i] & ~sub_rd[i]) sub_depth_next [i] = sub_depth[i] + 1'h1;
-					else if (~wr[i] & sub_rd[i]) sub_depth_next [i] = sub_depth[i] - 1'h1;    
-				end//always
-				
-				assign  vc_not_empty    [i] =   (sub_depth[i] > 0);
-				
-				
-				
-				
-			end else begin : unicast
-				assign  rd_ptr_array[(i+1)*PTRw- 1 :   i*PTRw]   =       rd_ptr[i];   
-				assign  vc_not_empty    [i] =   (depth[i] > 0);
-			end    	
-		end//for
-      	
- 	   	
-    
-
-		if((2**Bw)==B)begin :pow2
-			/*****************      
-          Buffer width is power of 2
-			 ******************/
-	
-			wire [Bw-1     :    0]  vc_wr_addr;
-			wire [Bw-1     :    0]  vc_rd_addr; 
-			wire [Vw-1     :    0]  wr_select_addr;
-			wire [Vw-1     :    0]  rd_select_addr; 
-			wire [Bw+Vw-1  :    0]  wr_addr;
-			wire [Bw+Vw-1  :    0]  rd_addr;	    
-    
-			assign  wr_addr =   {wr_select_addr,vc_wr_addr};
-			assign  rd_addr =   {rd_select_addr,vc_rd_addr};
-    
-        
-			onehot_mux_1D #(
-					.W(Bw),
-					.N(V) 
-				)
-				wr_ptr_mux
-				(
-					.in(wr_ptr_array),
-					.out(vc_wr_addr),
-					.sel(vc_num_wr)
-				);   
-	        
-	    
-			onehot_mux_1D #(
-					.W(Bw),
-					.N(V) 
-				)
-				rd_ptr_mux
-				(
-					.in(rd_ptr_array),
-					.out(vc_rd_addr),
-					.sel(vc_num_rd)
-				);    
-	    
-			one_hot_to_bin #(
-					.ONE_HOT_WIDTH(V)    
-				)
-				wr_vc_start_addr
-				(
-					.one_hot_code(vc_num_wr),
-					.bin_code(wr_select_addr)
-				);
-	    
-			one_hot_to_bin #(
-					.ONE_HOT_WIDTH(V)    
-				)
-				rd_vc_start_addr
-				(
-					.one_hot_code(vc_num_rd),
-					.bin_code(rd_select_addr)
-				);
-	
-			fifo_ram    #(
-					.DATA_WIDTH (RAM_DATA_WIDTH),
-					.ADDR_WIDTH (BVw ),
-					.SSA_EN(SSA_EN)       
-				)
-				the_queue
-				(
-					.wr_data(fifo_ram_din), 
-					.wr_addr(wr_addr[BVw-1  :   0]),
-					.rd_addr(rd_addr[BVw-1  :   0]),
-					.wr_en(wr_en),
-					.rd_en(rd_en),
-					.clk(clk),
-					.rd_data(fifo_ram_dout)
-				);  
-
-			for(i=0;i<V;i=i+1) begin :loop0
-    	
-				always @(posedge clk) begin
-					if(wr[i]) tail_fifo[i][wr_ptr[i]] <= din[Fw-2];
-				end     	
-          
-				pronoc_register #(.W(Bw    )) reg1 (.in(rd_ptr_next[i]), .out(rd_ptr[i]), .reset(reset), .clk(clk));
-				pronoc_register #(.W(Bw    )) reg2 (.in(wr_ptr_next[i]), .out(wr_ptr[i]), .reset(reset), .clk(clk));
-				pronoc_register #(.W(DEPTHw)) reg3 (.in(depth_next[i] ), .out(depth [i]), .reset(reset), .clk(clk));
-	          
-
-				always @ (*)begin 
-					rd_ptr_next [i] = rd_ptr  [i];
-					wr_ptr_next [i] = wr_ptr  [i];
-					depth_next  [i] = depth   [i];
-	        
-					if (wr[i]  ) wr_ptr_next [i] = wr_ptr [i]+ 1'h1;
-					if (rd[i]  ) rd_ptr_next [i] = rd_ptr [i]+ 1'h1;
-					if (wr[i] & ~rd[i]) depth_next [i] = depth[i] + 1'h1;
-					else if (~wr[i] & rd[i]) depth_next [i] = depth[i] - 1'h1;
-	    
-				end//always
-
-				/* verilator lint_off WIDTH */ 
-				if (CAST_TYPE != "UNICAST") begin :multicast
-					/* verilator lint_on WIDTH */ 	      
-					always @ (*)begin 
-						sub_rd_ptr_next[i] = sub_rd_ptr[i];
-						if (sub_restore[i]) sub_rd_ptr_next[i] = rd_ptr_next [i];
-						else if(sub_rd[i])  sub_rd_ptr_next[i] = sub_rd_ptr[i]+ 1'h1;        		
-					end	        	
-	        	
-					/* verilator lint_off WIDTH */
-					assign  flit_is_tail[i] = (PCK_TYPE == "MULTI_FLIT")? tail_fifo[i][sub_rd_ptr[i]]  : 1'b1;
-					/* verilator lint_on WIDTH */
-	        	
-        	
-				end else begin : unicast
-	        	
-					/* verilator lint_off WIDTH */
-					assign  flit_is_tail[i] = (PCK_TYPE == "MULTI_FLIT")?  tail_fifo[i][rd_ptr[i]] : 1'b1;
-					/* verilator lint_on WIDTH */
-				end
-			end//for
-    
-    
-    
-		end  else begin :no_pow2    
-			/*****************      
-    	Buffer width is not power of 2
-			 ******************/
-			// memory address
-			wire [BVw- 1    :   0]  wr_addr;
-			wire [BVw- 1    :   0]  rd_addr;
-			for(i=0;i<V;i=i+1) begin :V_   
-    
-				pronoc_register #(.W(BVw),.RESET_TO(B*i)) reg1 (.in(rd_ptr_next[i]), .out(rd_ptr[i]), .reset(reset), .clk(clk));
-				pronoc_register #(.W(BVw),.RESET_TO(B*i)) reg2 (.in(wr_ptr_next[i]), .out(wr_ptr[i]), .reset(reset), .clk(clk));
-				pronoc_register #(.W(DEPTHw)            ) reg3 (.in(depth_next[i] ), .out(depth [i]), .reset(reset), .clk(clk));         
-    
-     		        
-				always @(posedge clk) begin
-					/* verilator lint_off WIDTH */ 
-					if(wr[i]) tail_fifo[i][wr_ptr[i]-(B*i)] <= din[Fw-2];
-					/* verilator lint_on WIDTH */
-				end    
+        fifo_ram    #(
+            .DATA_WIDTH (RAM_DATA_WIDTH),
+            .ADDR_WIDTH (BVw ),
+            .SSA_EN(SSA_EN)
+        ) the_queue (
+            .wr_data(fifo_ram_din), 
+            .wr_addr(wr_addr[BVw-1 : 0]),
+            .rd_addr(rd_addr[BVw-1 : 0]),
+            .wr_en(wr_en),
+            .rd_en(rd_en),
+            .clk(clk),
+            .rd_data(fifo_ram_dout)
+        );  
         
-				always @ (*) begin 
-					rd_ptr_next [i] = rd_ptr  [i];
-					wr_ptr_next [i] = wr_ptr  [i];
-					depth_next  [i] = depth   [i];
-					/* verilator lint_off WIDTH */ 
-					if (wr[i] ) wr_ptr_next[i] =(wr_ptr[i]==(B*(i+1))-1)? (B*i) : wr_ptr [i]+ 1'h1;
-					if (rd[i] ) rd_ptr_next[i] =(rd_ptr[i]==(B*(i+1))-1)? (B*i) : rd_ptr [i]+ 1'h1;
-					/* verilator lint_on WIDTH */ 
-					if (wr[i] & ~rd[i]) depth_next [i] = depth[i] + 1'h1;
-					else if (~wr[i] & rd[i]) depth_next [i] = depth[i] - 1'h1;
-				end//always  
-         	
+        for(i=0;i<PORT_IVC;i=i+1) begin :V_
+            always @(posedge clk) begin
+                if(wr[i]) tail_fifo[i][wr_ptr[i]] <= din[Fw-2];
+            end
+            always_ff @ (`pronoc_clk_reset_edge )begin 
+                if(`pronoc_reset) begin 
+                    rd_ptr[i] <= {PORT_Bw{1'b0}};
+                    wr_ptr[i] <= {PORT_Bw{1'b0}};
+                    depth[i]  <= {DEPTHw{1'b0}};
+                end else begin
+                    rd_ptr[i] <= rd_ptr_next[i];
+                    wr_ptr[i] <= wr_ptr_next[i];
+                    depth[i]  <= depth_next[i];
+                end
+            end            
+            if (~IS_UNICAST) begin :multicast
+                assign  flit_is_tail[i] = (IS_MULTI_FLIT)? tail_fifo[i][sub_rd_ptr[i]] : 1'b1;
+            end else begin : unicast
+                assign  flit_is_tail[i] = (IS_MULTI_FLIT)?  tail_fifo[i][rd_ptr[i]] : 1'b1;
+            end
+        end//for V_
         
+    end  else begin :no_pow2
+    /***************************
+    * Buffer width is not power of 2
+    ***************************/
+        // memory address
+        wire [BVw- 1 : 0] wr_addr, rd_addr;
+        wire [PTRw-1 : 0] rd_ptr_tmp  [PORT_IVC-1 : 0];
+        wire [PTRw-1 : 0] wr_ptr_tmp  [PORT_IVC-1 : 0];
+        assign  wr_addr = vc_wr_addr;
+        assign  rd_addr = vc_rd_addr;
+        for(i=0;i<PORT_IVC;i=i+1) begin :V_
+            localparam [PTRw-1 : 0] BI = PTRw'(PORT_B*i);
+            always_ff @ (`pronoc_clk_reset_edge )begin 
+                if(`pronoc_reset) begin
+                    rd_ptr[i] <= BI;
+                    wr_ptr[i] <= BI;
+                    depth[i]  <= {DEPTHw{1'b0}};
+                end else begin
+                    rd_ptr[i] <= rd_ptr_next[i];
+                    wr_ptr[i] <= wr_ptr_next[i];
+                    depth[i]  <= depth_next[i];
+                end
+            end            
+            assign wr_ptr_tmp [i] = wr_ptr[i]-BI;
+            always @(posedge clk) begin
+                if(wr[i]) tail_fifo[i][wr_ptr_tmp[i][PORT_Bw-1:0]] <= din[Fw-2];
+            end
+            if (~IS_UNICAST) begin :multicast
+                assign  rd_ptr_tmp [i] = sub_rd_ptr[i]-BI;
+                assign  flit_is_tail[i] = (IS_MULTI_FLIT)?  tail_fifo[i][rd_ptr_tmp [i][PORT_Bw-1:0]] : 1'b1;
+            end else begin : unicast
+                assign  rd_ptr_tmp [i] =rd_ptr[i]-BI;
+                assign  flit_is_tail[i] = (IS_MULTI_FLIT)?  tail_fifo[i][rd_ptr_tmp [i][PORT_Bw-1:0]] : 1'b1;
+            end
+        end// for V_
         
-				/* verilator lint_off WIDTH */ 
-				if (CAST_TYPE != "UNICAST") begin :multicast
-				/* verilator lint_on WIDTH */ 
-        	
-					
-					
-      
-					always @ (*)begin 
-						sub_rd_ptr_next[i] = sub_rd_ptr[i];
-						if (sub_restore[i]) sub_rd_ptr_next[i] = rd_ptr_next [i];
-						/* verilator lint_off WIDTH */ 
-						else if(sub_rd[i])  sub_rd_ptr_next[i] = (sub_rd_ptr[i]==(B*(i+1))-1)? (B*i) : sub_rd_ptr [i]+ 1'h1; 
-						/* verilator lint_on WIDTH */ 
-					end        	
-        	
-					/* verilator lint_off WIDTH */ 
-					assign  ptr_tmp [i] = sub_rd_ptr[i]-(B*i);
-					assign  flit_is_tail[i] = (PCK_TYPE == "MULTI_FLIT")?  tail_fifo[i][ptr_tmp [i]] :1'b1;
-					/* verilator lint_on WIDTH */ 
-        	      	
-        	
-				end else begin : unicast
-					/* verilator lint_off WIDTH */ 
-					assign  flit_is_tail[i] = (PCK_TYPE == "MULTI_FLIT")?  tail_fifo[i][rd_ptr[i]-(B*i)] : 1'b1;
-					/* verilator lint_on WIDTH */ 
-				end
-			end//FOR
-    
-    
-			onehot_mux_1D #(
-					.W(BVw),
-					.N(V)        
-				)
-				wr_mux
-				(
-					.in(wr_ptr_array),
-					.out(wr_addr),
-					.sel(vc_num_wr)
-				);
-	    
-			onehot_mux_1D #(
-					.W(BVw),
-					.N(V)        
-				)
-				rd_mux
-				(
-					.in(rd_ptr_array),
-					.out(rd_addr),
-					.sel(vc_num_rd)
-				);
-	    
-			fifo_ram_mem_size #(
-					.DATA_WIDTH (RAM_DATA_WIDTH),
-					.MEM_SIZE (BV ),
-					.SSA_EN(SSA_EN)       
-				)
-				the_queue
-				(
-					.wr_data        (fifo_ram_din), 
-					.wr_addr        (wr_addr),
-					.rd_addr        (rd_addr),
-					.wr_en          (wr_en),
-					.rd_en          (rd_en),
-					.clk            (clk),
-					.rd_data        (fifo_ram_dout)
-				);  
-		end
-	endgenerate
-    
-    
-    
-    
-  
-
-	//synthesis translate_off
-	//synopsys  translate_off
-    
-	
-    
-	generate
-		
-		if(DEBUG_EN) begin :dbg 
-			always @(posedge clk) begin	       
-				if(wr_en && vc_num_wr == {V{1'b0}})begin 
-					$display("%t: ERROR: Attempt to write when no wr VC is asserted: %m",$time);
-					$finish;
-				end
-				if(rd_en && vc_num_rd == {V{1'b0}})begin
-					$display("%t: ERROR: Attempt to read when no rd VC is asserted: %m",$time);
-					$finish;
-				end
-			end    
-		end //DEBUG_EN
-	
-	
-		for(i=0;i<V;i=i+1) begin :loop0
-	
-			/* verilator lint_off WIDTH */ 
-			if (CAST_TYPE != "UNICAST") begin :multicast
-				/* verilator lint_on WIDTH */ 	 
-	
-				
-			
-				always @(posedge clk) begin          
-					if (wr[i] && (sub_depth[i] == B [DEPTHw-1 : 0]) && !sub_rd[i]) begin
-						$display("%t: ERROR: Attempt to write to full FIFO:FIFO size is %d. %m",$time,B);
-						$finish;
-					end   
-					/* verilator lint_off WIDTH */
-					if (sub_rd[i] && (sub_depth[i] == {DEPTHw{1'b0}} &&  SSA_EN !="YES"  ))begin 
-						/* verilator lint_on WIDTH */
-						$display("%t: ERROR: Attempt to read an empty FIFO: %m",$time);
-						$finish;
-					end  
-					/* verilator lint_off WIDTH */
-					if (sub_rd[i] && !wr[i] && (sub_depth[i] == {DEPTHw{1'b0}} &&  SSA_EN =="YES" ))begin 
-						/* verilator lint_on WIDTH */
-						$display("%t: ERROR: Attempt to read an empty FIFO: %m",$time);
-						$finish;
-					end  
-				end//always	
-			end	//multicast
-	
-	
-			always @(posedge clk) begin	          
-				if (wr[i] && (depth[i] == B [DEPTHw-1 : 0]) && !rd[i])begin
-					$display("%t: ERROR: Attempt to write to full FIFO:FIFO size is %d. %m",$time,B);
-					$finish;
-				end    
-				/* verilator lint_off WIDTH */
-				if (rd[i] && (depth[i] == {DEPTHw{1'b0}} &&  SSA_EN !="YES"  ))begin
-					/* verilator lint_on WIDTH */
-					$display("%t: ERROR: Attempt to read an empty FIFO: %m",$time);
-					$finish;
-				end   
-				/* verilator lint_off WIDTH */
-				if (rd[i] && !wr[i] && (depth[i] == {DEPTHw{1'b0}} &&  SSA_EN =="YES" ))begin 
-					/* verilator lint_on WIDTH */	
-					$display("%t: ERROR: Attempt to read an empty FIFO: %m",$time);
-					$finish;
-				end                
-				//if (wr_en)       $display($time, " %h is written on fifo ",din);
-			end//always
-		end//for	
-	endgenerate 
-	//synopsys  translate_on
-	//synthesis translate_on	
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-endmodule 
-
+        fifo_ram_mem_size #(
+            .DATA_WIDTH (RAM_DATA_WIDTH),
+            .MEM_SIZE (BV ),
+            .SSA_EN(SSA_EN)
+        ) the_queue (
+            .wr_data(fifo_ram_din), 
+            .wr_addr(wr_addr),
+            .rd_addr(rd_addr),
+            .wr_en(wr_en),
+            .rd_en(rd_en),
+            .clk(clk),
+            .rd_data (fifo_ram_dout)
+        );  
+    end
+    endgenerate
+    
+    /*********************************************
+    *        Validating Parameters/Simulation
+    *********************************************/
+    `ifdef SIMULATION
+    generate
+    if(DEBUG_EN) begin :dbg 
+        always @(posedge clk) begin
+        if(wr_en && vc_num_wr == {PORT_IVC{1'b0}})begin
+            $display("%t: ERROR: Attempt to write when no wr VC is asserted: %m",$time);
+            $finish;
+        end
+        if(rd_en && vc_num_rd == {PORT_IVC{1'b0}})begin
+            $display("%t: ERROR: Attempt to read when no rd VC is asserted: %m",$time);
+            $finish;
+        end
+        end
+    end //DEBUG_EN
+    
+    for(i=0;i<PORT_IVC;i=i+1) begin :VC_
+        if (~IS_UNICAST) begin :multicast
+            always @(posedge clk) begin
+                if (wr[i] && (sub_depth[i] == PORT_B [DEPTHw-1 : 0]) && !sub_rd[i]) begin
+                $display("%t: ERROR: Attempt to write to full FIFO:FIFO size is %d. %m",$time,PORT_B);
+                $finish;
+                end
+                if (sub_rd[i] && (sub_depth[i] == {DEPTHw{1'b0}} &&  (SSA_EN != 1) ))begin 
+                $display("%t: ERROR: Attempt to read an empty FIFO: %m",$time);
+                $finish;
+                end
+                if (sub_rd[i] && !wr[i] && (sub_depth[i] == {DEPTHw{1'b0}} &&  (SSA_EN == 1) ))begin 
+                $display("%t: ERROR: Attempt to read an empty FIFO: %m",$time);
+                $finish;
+                end
+            end//always
+        end    //multicast
+        always @(posedge clk) begin
+            if (wr[i] && (depth[i] == PORT_B [DEPTHw-1 : 0]) && !rd[i])begin
+                $display("%t: ERROR: Attempt to write to full FIFO:FIFO size is %d. %m",$time,B);
+                $finish;
+            end
+            if (rd[i] && (depth[i] == {DEPTHw{1'b0}} &&  (SSA_EN != 1) ))begin
+                $display("%t: ERROR: Attempt to read an empty FIFO: %m",$time);
+                $finish;
+            end
+            if (rd[i] && !wr[i] && (depth[i] == {DEPTHw{1'b0}} &&  (SSA_EN == 1)))begin
+                $display("%t: ERROR: Attempt to read an empty FIFO: %m",$time);
+                $finish;
+            end
+        //if (wr_en)       $display($time, " %h is written on fifo ",din);
+        end//always
+    end//for
+    endgenerate 
+    `endif //SIMULATION
+endmodule
 
 
 /****************************
-
-     fifo_ram
-
- *****************************/
-
-
-
-module fifo_ram     #(
-		parameter DATA_WIDTH    = 32,
-		parameter ADDR_WIDTH    = 8,
-		parameter SSA_EN="YES" // "YES" , "NO"       
-		)
-		(
-		wr_data,        
-		wr_addr,
-		rd_addr,
-		wr_en,
-		rd_en,
-		clk,
-		rd_data
-		);  
-    
-    
-	input [DATA_WIDTH-1         :       0]  wr_data;        
-	input [ADDR_WIDTH-1         :       0]  wr_addr;
-	input [ADDR_WIDTH-1         :       0]  rd_addr;
-	input                                   wr_en;
-	input                                   rd_en;
-	input                                   clk;
-	output [DATA_WIDTH-1   :       0]       rd_data;
-    
-    
-
-	reg [DATA_WIDTH-1:0] memory_rd_data; 
-	// memory
-	reg [DATA_WIDTH-1:0] queue [2**ADDR_WIDTH-1:0] /* synthesis ramstyle = "no_rw_check , M9K" */;
-	always @(posedge clk ) begin
-		if (wr_en)
-			queue[wr_addr] <= wr_data;
-		if (rd_en)
-			memory_rd_data <=  queue[rd_addr];
-	end
-	
- 
-
-	 	 
-	 
-	
-	 
-	generate 
-	/* verilator lint_off WIDTH */
-		if(SSA_EN =="YES") begin :predict
-			/* verilator lint_on WIDTH */
-			//add bypass
-			reg [DATA_WIDTH-1:0]  bypass_reg;
-			reg rd_en_delayed;
-			always @(posedge clk ) begin
-				bypass_reg 	<=wr_data;
-				rd_en_delayed	<=rd_en;
-			end
-		  
-			assign rd_data = (rd_en_delayed)? memory_rd_data  : bypass_reg;
-		  
-		  
-    
-		end else begin : no_predict
-			assign rd_data =  memory_rd_data;
-		end
-	endgenerate
+*       fifo_ram
+*****************************/
+module fifo_ram #(
+    parameter DATA_WIDTH = 32,
+    parameter ADDR_WIDTH = 8,
+    parameter SSA_EN=1 // 1: enable SSA, 0: disable SSA
+    )(
+    wr_data,
+    wr_addr,
+    rd_addr,
+    wr_en,
+    rd_en,
+    clk,
+    rd_data
+);
+    
+    input [DATA_WIDTH-1 :    0]  wr_data;
+    input [ADDR_WIDTH-1 :    0]  wr_addr;
+    input [ADDR_WIDTH-1 :    0]  rd_addr;
+    input                      wr_en;
+    input                      rd_en;
+    input                      clk;
+    output [DATA_WIDTH-1 :    0]       rd_data;
+    
+    reg [DATA_WIDTH-1:0] memory_rd_data; 
+    // memory
+    reg [DATA_WIDTH-1:0] queue [2**ADDR_WIDTH-1:0] /* synthesis ramstyle = "no_rw_check , M9K" */;
+    always @(posedge clk ) begin
+    if (wr_en)
+        queue[wr_addr] <= wr_data;
+    if (rd_en)
+        memory_rd_data <= queue[rd_addr];
+    end
+    
+    generate
+    if(SSA_EN == 1) begin :predict
+        //add bypass
+        reg [DATA_WIDTH-1:0]  bypass_reg;
+        reg rd_en_delayed;
+        always @(posedge clk ) begin
+            bypass_reg <=wr_data;
+            rd_en_delayed    <=rd_en;
+        end
+        
+        assign rd_data = (rd_en_delayed)? memory_rd_data : bypass_reg;
+        
+    end else begin : no_predict
+        assign rd_data = memory_rd_data;
+    end
+    endgenerate
 endmodule
 
 
-
 /*********************
- *
  *   fifo_ram_mem_size
- *
  **********************/
-
-
-module fifo_ram_mem_size     #(
-		parameter DATA_WIDTH  = 32,
-		parameter MEM_SIZE    = 200,
-		parameter SSA_EN  = "YES" // "YES" , "NO"       
-		)
-		(
-		wr_data,        
-		wr_addr,
-		rd_addr,
-		wr_en,
-		rd_en,
-		clk,
-		rd_data
-		); 
-     
-    
-	function integer log2;
-		input integer number; begin   
-			log2=(number <=1) ? 1: 0;    
-			while(2**log2<number) begin    
-				log2=log2+1;    
-			end 	   
-		end   
-	endfunction // log2 
-
-	localparam ADDR_WIDTH=log2(MEM_SIZE);
-    
-	input  [DATA_WIDTH-1         :       0]  wr_data;       
-	input  [ADDR_WIDTH-1         :       0]  wr_addr;
-	input  [ADDR_WIDTH-1         :       0]  rd_addr;
-	input                                    wr_en;
-	input                                    rd_en;
-	input                                    clk;
-	output [DATA_WIDTH-1        :       0]   rd_data;
-    
-    
-     
-    
-    
-    
-	reg [DATA_WIDTH-1:0] memory_rd_data; 
-	// memory
-	reg [DATA_WIDTH-1:0] queue [MEM_SIZE-1:0] /* synthesis ramstyle = "no_rw_check , M9K" */;
-	always @(posedge clk ) begin
-		if (wr_en)
-			queue[wr_addr] <= wr_data;
-		if (rd_en)
-			memory_rd_data <=  queue[rd_addr];
-	end
-         
-	generate 
-	/* verilator lint_off WIDTH */
-		if(SSA_EN =="YES") begin :predict
-			/* verilator lint_on WIDTH */
-			//add bypass
-			reg [DATA_WIDTH-1:0]  bypass_reg;
-			reg rd_en_delayed;
-			always @(posedge clk ) begin
-				bypass_reg     <=wr_data;
-				rd_en_delayed  <=rd_en;
-			end
-          
-			assign rd_data = (rd_en_delayed)? memory_rd_data  : bypass_reg;
-          
-          
-    
-		end else begin : no_predict
-			assign rd_data =  memory_rd_data;
-		end
-	endgenerate
+module fifo_ram_mem_size #(
+    parameter DATA_WIDTH = 32,
+    parameter MEM_SIZE = 200,
+    parameter SSA_EN = 1 // 1: enable SSA, 0: disable SSA
+    ) (
+    wr_data,
+    wr_addr,
+    rd_addr,
+    wr_en,
+    rd_en,
+    clk,
+    rd_data
+); 
+    
+    function integer log2;
+    input integer number; begin
+        log2=(number <=1) ? 1: 0;
+        while(2**log2<number) begin
+        log2=log2+1;
+        end
+    end
+    endfunction // log2
+    
+    localparam ADDR_WIDTH=log2(MEM_SIZE);
+    
+    input [DATA_WIDTH-1 :    0]  wr_data;
+    input [ADDR_WIDTH-1 :    0]  wr_addr;
+    input [ADDR_WIDTH-1 :    0]  rd_addr;
+    input                       wr_en;
+    input                       rd_en;
+    input                       clk;
+    output [DATA_WIDTH-1 :    0]   rd_data;
+    reg [DATA_WIDTH-1:0] memory_rd_data;
+    // memory
+    reg [DATA_WIDTH-1:0] queue [MEM_SIZE-1:0] /* synthesis ramstyle = "no_rw_check , M9K" */;
+    always @(posedge clk ) begin
+    if (wr_en)
+        queue[wr_addr] <= wr_data;
+    if (rd_en)
+        memory_rd_data <= queue[rd_addr];
+    end
+    
+    generate 
+    if(SSA_EN == 1) begin :predict
+        //add bypass
+        reg [DATA_WIDTH-1:0]  bypass_reg;
+        reg rd_en_delayed;
+        always @(posedge clk ) begin
+            bypass_reg <=wr_data;
+            rd_en_delayed  <=rd_en;
+        end
+        
+        assign rd_data = (rd_en_delayed)? memory_rd_data : bypass_reg;
+        
+    end else begin : no_predict
+        assign rd_data = memory_rd_data;
+    end
+    endgenerate
 endmodule
     
     
-
-
-
 /**********************************
-
-An small  First Word Fall Through FIFO. The code will use LUTs
-    and  optimized for low LUTs utilization.
-
- **********************************/
-
-
+*    fwft_fifo
+*    An small  First Word Fall Through FIFO. 
+*    The code will use LUTs and  optimized
+*    for low LUTs utilization.
+**********************************/
 module fwft_fifo #(
-		parameter DATA_WIDTH = 2,
-		parameter MAX_DEPTH = 2,
-		parameter IGNORE_SAME_LOC_RD_WR_WARNING="YES" // "YES" , "NO" 
-		)
-		(
-		input [DATA_WIDTH-1:0] din,     // Data in
-		input          wr_en,   // Write enable
-		input          rd_en,   // Read the next word
-		output [DATA_WIDTH-1:0]  dout,    // Data out
-		output         full,
-		output         nearly_full,
-		output          recieve_more_than_0,
-		output          recieve_more_than_1,
-		input          reset,
-		input          clk
-    
-		);
-    
-   
-	function integer log2;
-		input integer number; begin   
-			log2=(number <=1) ? 1: 0;    
-			while(2**log2<number) begin    
-				log2=log2+1;    
-			end 	   
-		end   
-	endfunction // log2 
-    
-
-    
-	localparam DEPTH_DATA_WIDTH = log2(MAX_DEPTH +1);
-	localparam MUX_SEL_WIDTH     = log2(MAX_DEPTH-1);
-    
-	wire                                        out_ld ;
-	wire    [DATA_WIDTH-1                   :   0] dout_next;
-	wire[DEPTH_DATA_WIDTH-1         :   0]  depth;
-	reg [DEPTH_DATA_WIDTH-1         :   0]  depth_next;
-	reg [DATA_WIDTH-1:0]  dout_next_ld;
-    
-	genvar i;
-	generate 
-    
-		if(MAX_DEPTH>2) begin :mwb2
-			wire    [MUX_SEL_WIDTH-1    :   0] mux_sel;
-			wire    [DEPTH_DATA_WIDTH-1 :   0] depth_2;
-			wire                               empty;
-			wire                               out_sel ;
-			if(DATA_WIDTH>1) begin :wb1
-				wire    [MAX_DEPTH-2        :   0] mux_in  [DATA_WIDTH-1       :0];
-				wire    [DATA_WIDTH-1       :   0] mux_out;
-				reg     [MAX_DEPTH-2        :   0] shiftreg [DATA_WIDTH-1      :0];
-       
-				for(i=0;i<DATA_WIDTH; i=i+1) begin : lp
-					always @(posedge clk ) begin 
-						//if (`pronoc_reset) begin 
-						//  shiftreg[i] <= {MAX_DEPTH{1'b0}};
-						//end else begin
-						if(wr_en) shiftreg[i] <= {shiftreg[i][MAX_DEPTH-3   :   0]  ,din[i]};
-						//end
-					end
-               
-					assign mux_in[i]    = shiftreg[i];
-					assign mux_out[i]   = mux_in[i][mux_sel];
-					assign dout_next[i] = (out_sel) ? mux_out[i] : din[i];  
-				end //for
-       
-       
-			end else begin :w1
-				wire    [MAX_DEPTH-2        :   0] mux_in;
-				wire    mux_out;
-				reg     [MAX_DEPTH-2        :   0] shiftreg; 
-       
-				always @(posedge clk ) begin 
-					if(wr_en) shiftreg <= {shiftreg[MAX_DEPTH-3   :   0]  ,din};
-				end
-               
-				assign mux_in    = shiftreg;
-				assign mux_out   = mux_in[mux_sel];
-				assign dout_next = (out_sel) ? mux_out : din;  
-        
-       
-       
-       
-			end
-        
-            
-			assign full                         = depth == MAX_DEPTH [DEPTH_DATA_WIDTH-1            :   0];
-			assign nearly_full              = depth >= MAX_DEPTH [DEPTH_DATA_WIDTH-1            :   0] -1'b1;
-			assign empty     = depth == {DEPTH_DATA_WIDTH{1'b0}};
-			assign recieve_more_than_0  = ~ empty;
-			assign recieve_more_than_1  = ~( depth == {DEPTH_DATA_WIDTH{1'b0}} ||  depth== 1 );
-			assign out_sel                  = (recieve_more_than_1)  ? 1'b1 : 1'b0;
-			assign out_ld                       = (depth !=0 )?  rd_en : wr_en;
-			assign depth_2                      = depth - 2;       
-			assign mux_sel                  = depth_2[MUX_SEL_WIDTH-1   :   0]  ;   
-   
-		end else if  ( MAX_DEPTH == 2) begin :mw2   
-        
-			reg     [DATA_WIDTH-1       :   0] register;
-            
-        
-			always @(posedge clk ) begin 
-				if(wr_en) register <= din;
-			end //always
-        
-			assign full             = depth == MAX_DEPTH [DEPTH_DATA_WIDTH-1            :   0];
-			assign nearly_full      = depth >= MAX_DEPTH [DEPTH_DATA_WIDTH-1            :   0] -1'b1;
-			assign out_ld           = (depth !=0 )?  rd_en : wr_en;
-			assign recieve_more_than_0  =  (depth != {DEPTH_DATA_WIDTH{1'b0}});
-			assign recieve_more_than_1  = ~( depth == 0 ||  depth== 1 );
-			assign dout_next        = (recieve_more_than_1) ? register  : din;  
-   
-   
-		end else begin :mw1 // MAX_DEPTH == 1 
-			assign out_ld       = wr_en;
-			assign dout_next    =   din;
-			assign full         = depth == MAX_DEPTH [DEPTH_DATA_WIDTH-1            :   0];
-			assign nearly_full= 1'b1;
-			assign recieve_more_than_0 = full;
-			assign recieve_more_than_1 = 1'b0;
-		end
-
-
-    
-	endgenerate
-    
-    
-	pronoc_register #(.W(DEPTH_DATA_WIDTH)) reg1 (.in(depth_next), .out(depth), .reset(reset), .clk(clk));
-	pronoc_register #(.W(DATA_WIDTH))       reg2 (.in(dout_next_ld), .out(dout ), .reset(reset), .clk(clk));
-   
-	always @ (*)begin 
-		depth_next  =  depth;
-		dout_next_ld   =  dout;
-		if (wr_en & ~rd_en) depth_next  =  depth + 1'h1;
-		else if (~wr_en & rd_en) depth_next  =  depth - 1'h1;  
-		if (out_ld) dout_next_ld = dout_next;
-	end//always
-    
-       
-   
-        
-	//synthesis translate_off
-	//synopsys  translate_off
-	always @(posedge clk)
-	begin
-         
-		if (wr_en & ~rd_en & full) begin
-			$display("%t: ERROR: Attempt to write to full FIFO:FIFO size is %d. %m",$time,MAX_DEPTH);
-			$finish;
-		end
-		/* verilator lint_off WIDTH */
-		if (rd_en & !recieve_more_than_0 & IGNORE_SAME_LOC_RD_WR_WARNING == "NO") begin
-			$display("%t ERROR: Attempt to read an empty FIFO: %m", $time);
-			$finish;
-		end
-		if (rd_en & ~wr_en & !recieve_more_than_0 & (IGNORE_SAME_LOC_RD_WR_WARNING == "YES")) begin
-			$display("%t ERROR: Attempt to read an empty FIFO: %m", $time);
-			$finish;
-		end
-		/* verilator lint_on WIDTH */
-           
-	end // always @ (posedge clk)
-    
-	//synopsys  translate_on
-	//synthesis translate_on  
-
-
-
-
-endmodule   
-
-
-
-
-
-
-
-
-
-
-/*********************
-
-    fwft_fifo_with_output_clear
-    each individual output bit has 
-    its own clear signal
-
- **********************/
-
-
-
-
+    parameter DATA_WIDTH = 2,
+    parameter MAX_DEPTH = 2,
+    parameter IGNORE_SAME_LOC_RD_WR_WARNING=1 //  1 : "YES", 0: "NO"
+    ) (
+    din,     // Data in
+    wr_en,   // Write enable
+    dout,    // Data out
+    rd_en,   // Read the next word
+    status_o,// fifo status
+    reset,
+    clk
+);
+    import pronoc_pkg::*;
+    input [DATA_WIDTH-1:0] din;    // Data in
+    input wr_en;   // Write enable
+    input rd_en;   // Read the next word
+    output logic [DATA_WIDTH-1:0]  dout;   // Data out
+    input reset, clk;
+    output fifo_stat_t status_o;
+    
+    localparam DEPTHw = log2(MAX_DEPTH +1);
+    localparam MUX_SEL_WIDTH = log2(MAX_DEPTH-1);
+    
+    wire out_ld ;
+    wire [DATA_WIDTH-1 : 0] dout_next;
+    logic [DEPTHw-1 : 0]  depth;
+    reg [DEPTHw-1 : 0]  depth_next;
+    reg [DATA_WIDTH-1:0]  dout_next_ld;
+    
+    genvar i;
+    generate
+    if(MAX_DEPTH > 2) begin :mwb2
+        wire [MUX_SEL_WIDTH-1 : 0] mux_sel;
+        wire [DEPTHw-1 : 0] depth_2;
+        wire out_sel ;
+        if(DATA_WIDTH>1) begin :wb1
+            wire [MAX_DEPTH-2 : 0] mux_in  [DATA_WIDTH-1 :0];
+            wire [DATA_WIDTH-1 : 0] mux_out;
+            reg [MAX_DEPTH-2 : 0] shiftreg [DATA_WIDTH-1 :0];
+            for(i=0;i<DATA_WIDTH; i=i+1) begin : lp
+                always @(posedge clk ) begin
+                //if (`pronoc_reset) begin
+                //  shiftreg[i] <= {MAX_DEPTH{1'b0}};
+                //end else begin
+                    if(wr_en) shiftreg[i] <= {shiftreg[i][MAX_DEPTH-3 : 0]  ,din[i]};
+                //end
+                end
+                assign mux_in[i] = shiftreg[i];
+                assign mux_out[i] = mux_in[i][mux_sel];
+                assign dout_next[i] = (out_sel) ? mux_out[i] : din[i];
+            end //for
+        end else begin :w1
+            wire [MAX_DEPTH-2 : 0] mux_in;
+            wire mux_out;
+            reg [MAX_DEPTH-2 : 0] shiftreg;
+            always @(posedge clk ) begin
+                if(wr_en) shiftreg <= {shiftreg[MAX_DEPTH-3 : 0]  ,din};
+            end
+            assign mux_in = shiftreg;
+            assign mux_out = mux_in[mux_sel];
+            assign dout_next = (out_sel) ? mux_out : din;
+        end
+        assign out_sel = (status_o.has_multiple)  ? 1'b1 : 1'b0;
+        assign out_ld = (depth !=DEPTHw'(0) )?  rd_en : wr_en;
+        assign depth_2 = depth - DEPTHw'(2);
+        assign mux_sel = depth_2[MUX_SEL_WIDTH-1 : 0];
+    end else if  ( MAX_DEPTH == 2) begin :mw2
+        reg [DATA_WIDTH-1 : 0] din_f;
+        always @(posedge clk ) begin
+            if(wr_en) din_f <= din;
+        end //always
+        assign out_ld = (depth !=0 )?  rd_en : wr_en;
+        assign dout_next = (status_o.has_multiple) ? din_f : din;
+    end else begin :mw1 // MAX_DEPTH == 1
+        assign out_ld = wr_en;
+        assign dout_next = din;
+    end
+    endgenerate
+    
+    always_ff @ (`pronoc_clk_reset_edge ) begin 
+        if(`pronoc_reset) begin
+            depth <= {DEPTHw{1'b0}};
+            dout  <= {DATA_WIDTH{1'b0}};
+        end else begin
+            depth <= depth_next;
+            dout  <= dout_next_ld;
+        end
+    end
+    
+    always_comb begin
+        depth_next = depth;
+        dout_next_ld = dout;
+        if (wr_en & ~rd_en) depth_next = depth + 1'h1;
+        else if (~wr_en & rd_en) depth_next = depth - 1'h1;
+        if (out_ld) dout_next_ld = dout_next;
+        status_o.full = (depth == MAX_DEPTH [DEPTHw-1 : 0]);
+        status_o.nearly_full = 
+            (MAX_DEPTH == 1)? 1'b1 : 
+            (depth >= MAX_DEPTH [DEPTHw-1 : 0] -1'b1);
+        status_o.empty = (depth == {DEPTHw{1'b0}});
+        status_o.has_data = ~ status_o.empty;
+        status_o.has_multiple =  
+            (MAX_DEPTH == 1)? 1'b0 : 
+            ~( depth == DEPTHw'(0) ||  depth== DEPTHw'(1) );
+    end//always
+    
+    /*********************************************
+    *        Validating Parameters/Simulation
+    *********************************************/
+    `ifdef SIMULATION
+    always @(posedge clk) begin
+        if (wr_en & ~rd_en & status_o.full) begin
+            $display("%t: ERROR: Attempt to write to full FIFO:FIFO size is %d. %m",$time,MAX_DEPTH);
+            $finish;
+        end
+        if (rd_en & status_o.empty & IGNORE_SAME_LOC_RD_WR_WARNING == 0) begin
+            $display("%t ERROR: Attempt to read an empty FIFO: %m", $time);
+            $finish;
+        end
+        if (rd_en & ~wr_en & status_o.empty & (IGNORE_SAME_LOC_RD_WR_WARNING == 1)) begin
+            $display("%t ERROR: Attempt to read an empty FIFO: %m", $time);
+            $finish;
+        end
+    end // always @ (posedge clk)
+    `endif//SIMULATION
+endmodule
 
+/***************************
+ *    
+ *    fwft_fifo_with_output_clear
+ *    each individual output bit has
+ *    its own clear signal
+ *    
+ ***************************/
 module fwft_fifo_with_output_clear #(
-		parameter DATA_WIDTH = 2,
-		parameter MAX_DEPTH = 2,
-		parameter IGNORE_SAME_LOC_RD_WR_WARNING="NO" // "YES" , "NO" 
-		)
-		(
-		din,     // Data in
-		wr_en,   // Write enable
-		rd_en,   // Read the next word
-		dout,    // Data out
-		full,
-		nearly_full,
-		recieve_more_than_0,
-		recieve_more_than_1,
-		reset,
-		clk,
-		clear
-    
-		);
-    
-	input   [DATA_WIDTH-1:0] din;     
-	input          wr_en;
-	input          rd_en;
-	output  [DATA_WIDTH-1:0]  dout;
-	output         full;
-	output         nearly_full;
-	output         recieve_more_than_0;
-	output         recieve_more_than_1;
-	input          reset;
-	input          clk;
-	input    [DATA_WIDTH-1:0]  clear;    
-  
-	function integer log2;
-		input integer number; begin   
-			log2=(number <=1) ? 1: 0;    
-			while(2**log2<number) begin    
-				log2=log2+1;    
-			end 	   
-		end   
-	endfunction // log2 
-    
-	localparam DEPTH_DATA_WIDTH = log2(MAX_DEPTH +1);
-	localparam MUX_SEL_WIDTH     = log2(MAX_DEPTH-1);
-    
-	wire out_ld;
-	wire [DATA_WIDTH-1 : 0] dout_next;
-	wire [DEPTH_DATA_WIDTH-1 : 0]  depth;
-	reg  [DEPTH_DATA_WIDTH-1 : 0]  depth_next;
-	reg  [DATA_WIDTH-1:0]  dout_next_ld;
-     
-	genvar i;
-	generate     
-		if(MAX_DEPTH>2) begin :mwb2
-			wire    [MUX_SEL_WIDTH-1    :   0] mux_sel;
-			wire    [DEPTH_DATA_WIDTH-1 :   0] depth_2;
-			wire                               empty;
-			wire                               out_sel ;
-			if(DATA_WIDTH>1) begin :wb1
-				wire    [MAX_DEPTH-2        :   0] mux_in  [DATA_WIDTH-1       :0];
-				wire    [DATA_WIDTH-1       :   0] mux_out;
-				reg     [MAX_DEPTH-2        :   0] shiftreg [DATA_WIDTH-1      :0];
-       
-				for(i=0;i<DATA_WIDTH; i=i+1) begin : lp
-					always @(posedge clk ) begin 
-						//if (`pronoc_reset) begin 
-						//  shiftreg[i] <= {MAX_DEPTH{1'b0}};
-						//end else begin
-						if(wr_en) shiftreg[i] <= {shiftreg[i][MAX_DEPTH-3   :   0]  ,din[i]};
-						//end
-					end
-               
-					assign mux_in[i]    = shiftreg[i];
-					assign mux_out[i]   = mux_in[i][mux_sel];
-					assign dout_next[i] = (out_sel) ? mux_out[i] : din[i];  
-				end //for       
-       
-			end else begin :w1
-				wire    [MAX_DEPTH-2        :   0] mux_in;
-				wire    mux_out;
-				reg     [MAX_DEPTH-2        :   0] shiftreg; 
-       
-				always @(posedge clk ) begin 
-					if(wr_en) shiftreg <= {shiftreg[MAX_DEPTH-3   :   0]  ,din};
-				end
-            
-				assign mux_in    = shiftreg;
-				assign mux_out   = mux_in[mux_sel];
-				assign dout_next = (out_sel) ? mux_out : din;  
- 
-			end
-       
-			assign full = depth == MAX_DEPTH [DEPTH_DATA_WIDTH-1            :   0];
-			assign nearly_full = depth >= MAX_DEPTH [DEPTH_DATA_WIDTH-1            :   0] -1'b1;
-			assign empty  = depth == {DEPTH_DATA_WIDTH{1'b0}};
-			assign recieve_more_than_0  = ~ empty;
-			assign recieve_more_than_1  = ~( depth == {DEPTH_DATA_WIDTH{1'b0}} ||  depth== 1 );
-			assign out_sel  = (recieve_more_than_1)  ? 1'b1 : 1'b0;
-			assign out_ld = (depth !=0 )?  rd_en : wr_en;
-			assign depth_2 = depth-'d2;       
-			assign mux_sel = depth_2[MUX_SEL_WIDTH-1   :   0]  ;   
-   
-		end else if  ( MAX_DEPTH == 2) begin :mw2   
-        
-			reg     [DATA_WIDTH-1       :   0] register;            
-        
-			always @(posedge clk ) begin 
-				if(wr_en) register <= din;
-			end //always
-        
-			assign full = depth == MAX_DEPTH [DEPTH_DATA_WIDTH-1            :   0];
-			assign nearly_full = depth >= MAX_DEPTH [DEPTH_DATA_WIDTH-1            :   0] -1'b1;
-			assign out_ld = (depth !=0 )?  rd_en : wr_en;
-			assign recieve_more_than_0  =  (depth != {DEPTH_DATA_WIDTH{1'b0}});
-			assign recieve_more_than_1  = ~( depth == 0 ||  depth== 1 );
-			assign dout_next = (recieve_more_than_1) ? register  : din;     
-   
-		end else begin :mw1 // MAX_DEPTH == 1 
-			assign out_ld       = wr_en;
-			assign dout_next    =   din;
-			assign full         = depth == MAX_DEPTH [DEPTH_DATA_WIDTH-1            :   0];
-			assign nearly_full= 1'b1;
-			assign recieve_more_than_0 = full;
-			assign recieve_more_than_1 = 1'b0;
-		end    
-	endgenerate
-
-
-
-
-	pronoc_register #(.W(DEPTH_DATA_WIDTH)) reg1 (.in(depth_next), .out(depth), .reset(reset), .clk(clk));
-	pronoc_register #(.W(DATA_WIDTH))       reg2 (.in(dout_next_ld), .out(dout ), .reset(reset), .clk(clk));
-   
-	always @ (*)begin 
-		depth_next  =  depth;
-		if (wr_en & ~rd_en) depth_next  =  depth + 1'h1;
-		else if (~wr_en & rd_en) depth_next  =  depth - 1'h1;       
-	end//always
-
-
-          
-	generate 
-		for(i=0;i<DATA_WIDTH; i=i+1) begin : lp
-			always @(*)begin
-				dout_next_ld[i] = dout[i];
-				if (clear[i]) dout_next_ld[i]   = 1'b0;
-				else if (out_ld) dout_next_ld[i]   = dout_next[i];           
-			end//always
-		end
-	endgenerate
-       
-	//synthesis translate_off
-	//synopsys  translate_off
-	always @(posedge clk)
-
-	begin
-		if(`pronoc_reset==0)begin
-			if (wr_en && ~rd_en && full) begin
-				$display("%t: ERROR: Attempt to write to full FIFO:FIFO size is %d. %m",$time,MAX_DEPTH);
-				$finish;
-			end
-			/* verilator lint_off WIDTH */
-			if (rd_en && !recieve_more_than_0 && IGNORE_SAME_LOC_RD_WR_WARNING == "NO") begin
-				$display("%t ERROR: Attempt to read an empty FIFO: %m", $time);
-				$finish;
-			end
-			if (rd_en && ~wr_en && !recieve_more_than_0 && IGNORE_SAME_LOC_RD_WR_WARNING == "YES") begin
-				$display("%t ERROR: Attempt to read an empty FIFO: %m", $time);
-				$finish;
-			end
-			/* verilator lint_on WIDTH */
-		end// ~reset
-	end // always @ (posedge clk)
-   
-	//synopsys  translate_on
-	//synthesis translate_on  
-endmodule   
-
-
-/***************
-fwft_fifo_bram
-****************/
+    parameter DATA_WIDTH = 2,
+    parameter MAX_DEPTH = 2,
+    parameter IGNORE_SAME_LOC_RD_WR_WARNING=0 //  1 : "YES", 0: "NO"
+    ) (
+    din,     // Data in
+    wr_en,   // Write enable
+    dout,    // Data out
+    rd_en,   // Read the next word
+    status_o,// fifo status
+    reset,
+    clk,
+    clear
+);
+    
+    import pronoc_pkg::*;
+    input [DATA_WIDTH-1:0] din;     // Data in
+    input wr_en;   // Write enable
+    input rd_en;   // Read the next word
+    output logic [DATA_WIDTH-1:0]  dout;    // Data out
+    input reset, clk;
+    output fifo_stat_t status_o;
+    input [DATA_WIDTH-1:0]  clear;
+    
+    localparam DEPTHw = log2(MAX_DEPTH +1);
+    localparam MUX_SEL_WIDTH = log2(MAX_DEPTH-1);
+    
+    wire out_ld;
+    wire [DATA_WIDTH-1 : 0] dout_next;
+    logic [DEPTHw-1 : 0]  depth;
+    reg [DEPTHw-1 : 0]  depth_next;
+    reg [DATA_WIDTH-1:0]  dout_next_ld;
+    
+    genvar i;
+    generate
+    if(MAX_DEPTH>2) begin :mwb2
+        wire [MUX_SEL_WIDTH-1 : 0] mux_sel;
+        wire [DEPTHw-1 : 0] depth_2;
+        wire out_sel ;
+        if(DATA_WIDTH>1) begin :wb1
+            wire [MAX_DEPTH-2 : 0] mux_in  [DATA_WIDTH-1 :0];
+            wire [DATA_WIDTH-1 : 0] mux_out;
+            reg [MAX_DEPTH-2 : 0] shiftreg [DATA_WIDTH-1 :0];
+            for(i=0;i<DATA_WIDTH; i=i+1) begin : D_
+                always @(posedge clk ) begin
+                //if (`pronoc_reset) begin
+                //  shiftreg[i] <= {MAX_DEPTH{1'b0}};
+                //end else begin
+                    if(wr_en) shiftreg[i] <= {shiftreg[i][MAX_DEPTH-3 : 0]  ,din[i]};
+                //end
+                end
+                assign mux_in[i] = shiftreg[i];
+                assign mux_out[i] = mux_in[i][mux_sel];
+                assign dout_next[i] = (out_sel) ? mux_out[i] : din[i];
+            end //D_
+        end else begin : w1
+            wire [MAX_DEPTH-2 : 0] mux_in;
+            wire mux_out;
+            reg [MAX_DEPTH-2 : 0] shiftreg;
+            always @(posedge clk ) begin
+                if(wr_en) shiftreg <= {shiftreg[MAX_DEPTH-3 : 0]  ,din};
+            end
+            assign mux_in = shiftreg;
+            assign mux_out = mux_in[mux_sel];
+            assign dout_next = (out_sel) ? mux_out : din;
+        end //w1
+        assign out_sel = (status_o.has_multiple)  ? 1'b1 : 1'b0;
+        assign out_ld = (depth !=0 )?  rd_en : wr_en;
+        assign depth_2 = depth-'d2;
+        assign mux_sel = depth_2[MUX_SEL_WIDTH-1 : 0];
+    end else if  ( MAX_DEPTH == 2) begin :mw2
+        reg [DATA_WIDTH-1 : 0] din_f;
+        always @(posedge clk ) begin
+            if(wr_en) din_f <= din;
+        end //always
+        assign out_ld = (depth !=0 )?  rd_en : wr_en;
+        assign dout_next = (status_o.has_multiple) ? din_f : din;
+    end else begin :mw1 // MAX_DEPTH == 1
+        assign out_ld = wr_en;
+        assign dout_next = din;
+    end
+    endgenerate
+    always_ff @ (`pronoc_clk_reset_edge) begin
+        if (`pronoc_reset) begin
+            depth <= '0;
+            dout  <= '0;
+        end else begin
+            depth <= depth_next;
+            dout  <= dout_next_ld;
+        end
+    end
+    
+    always_comb begin
+        depth_next = depth;
+        if (wr_en & ~rd_en) depth_next = depth + 1'h1;
+        else if (~wr_en & rd_en) depth_next = depth - 1'h1;
+        status_o.full = (depth == MAX_DEPTH [DEPTHw-1 : 0]);
+        status_o.nearly_full = 
+            (MAX_DEPTH == 1)? 1'b1 : 
+            (depth >= MAX_DEPTH [DEPTHw-1 : 0] -1'b1);
+        status_o.empty = (depth == {DEPTHw{1'b0}});
+        status_o.has_data = ~ status_o.empty;
+        status_o.has_multiple =  
+            (MAX_DEPTH == 1)? 1'b0 : 
+            ~( depth == DEPTHw'(0) ||  depth== DEPTHw'(1) );
+    end//always
+    
+    always_comb begin
+        for(int k=0;k<DATA_WIDTH; k++) begin
+            dout_next_ld[k] = dout[k];
+            if (clear[k]) dout_next_ld[k] = 1'b0;
+            else if (out_ld) dout_next_ld[k] = dout_next[k];
+        end
+    end
+    
+    /*********************************************
+    *        Validating Parameters/Simulation
+    *********************************************/
+    `ifdef SIMULATION
+    always @(posedge clk) begin
+        if(`pronoc_reset==0)begin
+            if (wr_en && ~rd_en && status_o.full) begin
+            $display("%t: ERROR: Attempt to write to full FIFO:FIFO size is %d. %m",$time,MAX_DEPTH);
+            $finish;
+            end
+            if (rd_en && status_o.empty && (IGNORE_SAME_LOC_RD_WR_WARNING == 0)) begin
+            $display("%t ERROR: Attempt to read an empty FIFO: %m", $time);
+            $finish;
+            end
+            if (rd_en && ~wr_en && status_o.empty && (IGNORE_SAME_LOC_RD_WR_WARNING == 1)) begin
+            $display("%t ERROR: Attempt to read an empty FIFO: %m", $time);
+            $finish;
+            end
+        end// ~reset
+    end // always @ (posedge clk)
+    `endif // SIMULATION
+endmodule
 
+/***************************
+*fwft_fifo_bram
+* An FWFT FIFO implementation based on BRAMs
+* optimized for low LUTs utilization.
+***************************/
 module fwft_fifo_bram #(
-		parameter DATA_WIDTH = 2,
-		parameter MAX_DEPTH = 2,
-		parameter IGNORE_SAME_LOC_RD_WR_WARNING="YES" // "YES" , "NO" 
-		)
-		(
-		input [DATA_WIDTH-1:0] din,     // Data in
-		input          wr_en,   // Write enable
-		input          rd_en,   // Read the next word
-		output [DATA_WIDTH-1:0]  dout,    // Data out
-		output         full,
-		output         nearly_full,
-		output         recieve_more_than_0,
-		output         recieve_more_than_1,
-		input          reset,
-		input          clk
-    
-		);
-    
-   
-	function integer log2;
-		input integer number; begin   
-			log2=(number <=1) ? 1: 0;    
-			while(2**log2<number) begin    
-				log2=log2+1;    
-			end       
-		end   
-	endfunction // log2 
-    
-
-    
-	localparam DEPTH_DATA_WIDTH = log2(MAX_DEPTH +1);
-    
-	reg  valid_next;  
-	wire valid;
-	wire pass_din_to_out_reg, out_reg_wr_en, bram_out_is_valid_next;
-	wire bram_out_is_valid;
-	wire bram_empty, bram_rd_en, bram_wr_en;
-	wire [DATA_WIDTH-1 : 0] bram_dout;
-	wire [DATA_WIDTH-1 : 0] out_reg;
-	reg  [DATA_WIDTH-1 : 0] out_reg_next;
-	
-	wire [DEPTH_DATA_WIDTH-1         :   0]  depth;
-	reg  [DEPTH_DATA_WIDTH-1         :   0]  depth_next;
-     
-	assign dout = (bram_out_is_valid)?  bram_dout : out_reg;
-
-  
-	assign  pass_din_to_out_reg = (wr_en & ~valid)| // a write has been recived while the reg_flit is not valid
-		(wr_en & valid & bram_empty & rd_en); //or its valid but bram is empty and its got a read request
-
-	assign bram_rd_en = (rd_en & ~bram_empty);
-	assign bram_wr_en = (pass_din_to_out_reg)?  1'b0 :wr_en ; //make sure not write on the Bram if the reg fifo is empty 
- 
-   
-	assign  out_reg_wr_en = pass_din_to_out_reg | bram_out_is_valid;    
-
-	assign  bram_out_is_valid_next = (bram_rd_en )? (rd_en &  ~bram_empty): 1'b0;
-    
-   
-	always @(*) begin
-		valid_next = valid;
-		if(depth_next == {DEPTH_DATA_WIDTH{1'b0}}) valid_next =1'b0;
-		else if(out_reg_wr_en) valid_next =1'b1;
-		else if(bram_empty & rd_en) valid_next =1'b0;
-	end   
-    
-    
-	bram_based_fifo  #(
-			.Dw(DATA_WIDTH),//data_width
-			.B(MAX_DEPTH)// buffer num
-		)bram_fifo(
-			.din(din),   
-			.wr_en(bram_wr_en), 
-			.rd_en(bram_rd_en), 
-			.dout(bram_dout),  
-			.full(),
-			.nearly_full(),
-			.empty(bram_empty),
-			.reset(reset),
-			.clk(clk)
-		);
-    
-	
-   
-   
-	pronoc_register #(.W(DATA_WIDTH)      ) reg1 (.in(out_reg_next           ), .out(out_reg), .reset(reset), .clk(clk));
-	pronoc_register #(.W(1)               ) reg2 (.in(valid_next             ), .out(valid), .reset(reset), .clk(clk));
-	pronoc_register #(.W(1)               ) reg3 (.in(bram_out_is_valid_next ), .out(bram_out_is_valid), .reset(reset), .clk(clk));
-	pronoc_register #(.W(DEPTH_DATA_WIDTH)) reg4 (.in(depth_next             ), .out(depth), .reset(reset), .clk(clk));
-   
-   
-   
-	always @(*) begin 
-		out_reg_next = out_reg; 
-		depth_next   = depth;
-		if (wr_en & ~rd_en) depth_next =   depth + 1'h1;
-		else if (~wr_en & rd_en) depth_next  = depth - 1'h1;  
-		if(pass_din_to_out_reg) out_reg_next = din;
-		else if(bram_out_is_valid)   out_reg_next = bram_dout; 
-	end  
-    
-       
-          
-      
-	wire empty;    
-	assign full                         = depth == MAX_DEPTH [DEPTH_DATA_WIDTH-1            :   0];
-	assign nearly_full              = depth >= MAX_DEPTH [DEPTH_DATA_WIDTH-1            :   0] -1'b1;
-	assign empty     = depth == {DEPTH_DATA_WIDTH{1'b0}};
-	assign recieve_more_than_0  = ~ empty;
-	assign recieve_more_than_1  = ~( depth == {DEPTH_DATA_WIDTH{1'b0}} ||  depth== 1 );
-       
-         
-        
-        
-	//synthesis translate_off
-	//synopsys  translate_off
-	always @(posedge clk)
-	begin
-		if (wr_en & ~rd_en & full) begin
-			$display("%t: ERROR: Attempt to write to full FIFO:FIFO size is %d. %m",$time,MAX_DEPTH);
-			$finish;
-		end
-		/* verilator lint_off WIDTH */
-		if (rd_en & !recieve_more_than_0 & IGNORE_SAME_LOC_RD_WR_WARNING == "NO") begin
-			$display("%t ERROR: Attempt to read an empty FIFO: %m", $time);
-			$finish;
-		end
-		if (rd_en & ~wr_en & !recieve_more_than_0 & (IGNORE_SAME_LOC_RD_WR_WARNING == "YES")) begin
-			$display("%t ERROR: Attempt to read an empty FIFO: %m", $time);
-			$finish;
-		end
-		/* verilator lint_on WIDTH */           
-	end // always @ (posedge clk)
-    
-	//synopsys  translate_on
-	//synthesis translate_on  
-
-
-
-
-endmodule   
-
-
-
-
-
-
-
-
+    parameter DATA_WIDTH = 2,
+    parameter MAX_DEPTH = 2,
+    parameter IGNORE_SAME_LOC_RD_WR_WARNING=1 // 1 : "YES" , 0: "NO"
+    )(
+    din,     // Data in
+    wr_en,   // Write enable
+    rd_en,   // Read the next word
+    dout,    // Data out
+    stat_o,
+    reset,
+    clk
+);
+    import pronoc_pkg::*;
+    input [DATA_WIDTH-1:0] din;     // Data in
+    input wr_en;   // Write enable
+    input rd_en;   // Read the next word
+    output [DATA_WIDTH-1:0]  dout;    // Data out
+    output fifo_stat_t stat_o;
+    input reset;
+    input clk;
+    
+    localparam DEPTHw = log2(MAX_DEPTH +1);
+    
+    reg valid_next;  
+    reg valid;
+    wire pass_din_to_out_reg, out_reg_wr_en, bram_out_is_valid_next;
+    logic bram_out_is_valid;
+    wire bram_rd_en, bram_wr_en;
+    fifo_stat_t brams_stat_o;
+    wire [DATA_WIDTH-1 : 0] bram_dout;
+    reg [DATA_WIDTH-1 : 0] out_reg;
+    reg [DATA_WIDTH-1 : 0] out_reg_next;
+    
+    logic [DEPTHw-1 : 0]  depth;
+    reg [DEPTHw-1 : 0]  depth_next;
+    
+    assign dout = (bram_out_is_valid)?  bram_dout : out_reg;
+    assign  pass_din_to_out_reg = (wr_en & ~valid)| // a write has been recived while the reg_flit is not valid
+    (wr_en & valid & brams_stat_o.empty & rd_en); //or its valid but bram is empty and its got a read request
+    
+    assign bram_rd_en = (rd_en & brams_stat_o.has_data);
+    assign bram_wr_en = (pass_din_to_out_reg)?  1'b0 :wr_en ; //make sure not write on the Bram if the reg fifo is empty 
+    
+    assign  out_reg_wr_en = pass_din_to_out_reg | bram_out_is_valid;
+    assign  bram_out_is_valid_next = (bram_rd_en )? (rd_en &  brams_stat_o.has_data): 1'b0;
+    
+    always_comb begin
+        valid_next = valid;
+        if(depth_next == {DEPTHw{1'b0}}) valid_next =1'b0;
+        else if(out_reg_wr_en) valid_next =1'b1;
+        else if(brams_stat_o.empty & rd_en) valid_next =1'b0;
+    end
+    
+    bram_based_fifo  #(
+        .Dw(DATA_WIDTH),//data_width
+        .B(MAX_DEPTH)// buffer num
+    ) bram_fifo (
+        .din(din),   
+        .wr_en(bram_wr_en), 
+        .rd_en(bram_rd_en), 
+        .dout(bram_dout),  
+        .stat_o(brams_stat_o),
+        .reset(reset),
+        .clk(clk)
+    );  
+    
+    always_ff @ (`pronoc_clk_reset_edge) begin
+        if (`pronoc_reset) begin
+            out_reg            <= '0;
+            valid              <= 1'b0;
+            bram_out_is_valid  <= 1'b0;
+            depth              <= '0;
+        end else begin
+            out_reg            <= out_reg_next;
+            valid              <= valid_next;
+            bram_out_is_valid  <= bram_out_is_valid_next;
+            depth              <= depth_next;
+        end
+    end
+    always_comb begin
+        out_reg_next = out_reg; 
+        depth_next = depth;
+        if (wr_en & ~rd_en) depth_next = depth + 1'h1;
+        else if (~wr_en & rd_en) depth_next = depth - 1'h1;  
+        if(pass_din_to_out_reg) out_reg_next = din;
+        else if(bram_out_is_valid)   out_reg_next = bram_dout; 
+    end
+    
+    assign stat_o.full = (depth == MAX_DEPTH [DEPTHw-1 : 0]);
+    assign stat_o.nearly_full = (depth >= MAX_DEPTH [DEPTHw-1 : 0] -1'b1);
+    assign stat_o.empty = (depth == {DEPTHw{1'b0}});
+    assign stat_o.has_data = ~(depth == {DEPTHw{1'b0}});
+    assign stat_o.has_multiple = ~((depth == DEPTHw'(0)) ||  (depth == DEPTHw'(1)));
+    
+    `ifdef SIMULATION
+    always @(posedge clk) begin
+        if (wr_en & ~rd_en & stat_o.full) begin
+            $display("%t: ERROR: Attempt to write to full FIFO:FIFO size is %d. %m",$time,MAX_DEPTH);
+            $finish;
+        end
+        if (rd_en & stat_o.empty & (IGNORE_SAME_LOC_RD_WR_WARNING == 0)) begin
+            $display("%t ERROR: Attempt to read an empty FIFO: %m", $time);
+            $finish;
+        end
+        if (rd_en & ~wr_en & stat_o.empty & (IGNORE_SAME_LOC_RD_WR_WARNING == 1)) begin
+            $display("%t ERROR: Attempt to read an empty FIFO: %m", $time);
+            $finish;
+        end
+    end // always
+    `endif // SIMULATION
+endmodule
 
 /**********************************
-
-            bram_based_fifo
-
- *********************************/
-
-
+*        bram_based_fifo
+*********************************/
 module bram_based_fifo  #(
-		parameter Dw = 72,//data_width
-		parameter B  = 10// buffer num
-		)(
-		din,   
-		wr_en, 
-		rd_en, 
-		dout,  
-		full,
-		nearly_full,
-		empty,
-		reset,
-		clk
-		);
-
- 
-	function integer log2;
-		input integer number; begin   
-			log2=(number <=1) ? 1: 0;    
-			while(2**log2<number) begin    
-				log2=log2+1;    
-			end 	   
-		end   
-	endfunction // log2 
-
-	localparam  B_1 = B-1,
-		Bw = log2(B),
-		DEPTHw=log2(B+1);
-	localparam  [Bw-1   :   0] Bint =   B_1[Bw-1    :   0];
-
-	input [Dw-1:0] din;     // Data in
-	input          wr_en;   // Write enable
-	input          rd_en;   // Read the next word
-
-	output reg [Dw-1:0]  dout;    // Data out
-	output         full;
-	output         nearly_full;
-	output         empty;
-
-	input          reset;
-	input          clk;
-
-
-
-	reg [Dw-1       :   0] queue [B-1 : 0] /* synthesis ramstyle = "no_rw_check" */;
-	reg [Bw- 1      :   0] rd_ptr;
-	reg [Bw- 1      :   0] wr_ptr;
-	reg [DEPTHw-1   :   0] depth;
-
-	// Sample the data
-	always @(posedge clk)
-	begin
-		if (wr_en)
-			queue[wr_ptr] <= din;
-		if (rd_en)
-			dout <=   queue[rd_ptr];
-	end
-
-	always @(posedge clk)
-	begin
-		if (`pronoc_reset) begin
-			rd_ptr <= {Bw{1'b0}};
-			wr_ptr <= {Bw{1'b0}};
-			depth  <= {DEPTHw{1'b0}};
-		end
-		else begin
-			if (wr_en) wr_ptr <= (wr_ptr==Bint)? {Bw{1'b0}} : wr_ptr + 1'b1;
-			if (rd_en) rd_ptr <= (rd_ptr==Bint)? {Bw{1'b0}} : rd_ptr + 1'b1;
-			if (wr_en & ~rd_en) depth <=  depth + 1'b1;
-			else if (~wr_en & rd_en) depth <=  depth - 1'b1;
-		end
-	end
-
-	//assign dout = queue[rd_ptr];
-	localparam  [DEPTHw-1   :   0] Bint2 =   B_1[DEPTHw-1   :   0];
-
-
-	assign full = depth == B [DEPTHw-1   :   0];
-	assign nearly_full = depth >=Bint2; //  B-1
-	assign empty = depth == {DEPTHw{1'b0}};
-
-	//synthesis translate_off
-	//synopsys  translate_off
-	always @(posedge clk)
-	begin
-		if(`pronoc_reset==1'b0)begin
-			if (wr_en && depth == B[DEPTHw-1   :   0] && !rd_en) begin
-				$display(" %t: ERROR: Attempt to write to full FIFO: %m",$time);
-				$finish;
-			end   
-			if (rd_en && depth == {DEPTHw{1'b0}}) begin
-				$display("%t: ERROR: Attempt to read an empty FIFO: %m",$time);
-				$finish;
-			end
-		end//~reset
-	end
-	//synopsys  translate_on
-	//synthesis translate_on
-
-endmodule // fifo
-
+    parameter Dw = 72,//data_width
+    parameter B = 10// buffer num
+)(
+    din,
+    wr_en,
+    rd_en,
+    dout,
+    stat_o,
+    reset,
+    clk
+);
+    import pronoc_pkg::*;
+    localparam
+        B_1 = B-1,
+        Bw = log2(B),
+        DEPTHw=log2(B+1);
+    localparam  [Bw-1 : 0] Bint = B_1[Bw-1 : 0];
+    
+    input [Dw-1:0] din; // Data in
+    input wr_en;   // Write enable
+    input rd_en;   // Read the next word
+    output reg [Dw-1:0]  dout;    // Data out
+    output fifo_stat_t stat_o;
+    input reset;
+    input clk;
+    
+    reg [Dw-1 : 0] queue [B-1 : 0] /* synthesis ramstyle = "no_rw_check" */;
+    reg [Bw- 1 : 0] rd_ptr,rd_ptr_next;
+    reg [Bw- 1 : 0] wr_ptr,wr_ptr_next;
+    reg [DEPTHw-1 : 0] depth,depth_next;
+    
+    // Sample the data
+    always @(posedge clk) begin
+        if (wr_en)
+            queue[wr_ptr] <= din;
+        if (rd_en)
+            dout <= queue[rd_ptr];
+    end
+    
+    always_comb begin 
+        rd_ptr_next = rd_ptr;
+        wr_ptr_next = wr_ptr;
+        depth_next = depth;
+        if (wr_en) wr_ptr_next = (wr_ptr==Bint)? {Bw{1'b0}} : wr_ptr + 1'b1;
+        if (rd_en) rd_ptr_next = (rd_ptr==Bint)? {Bw{1'b0}} : rd_ptr + 1'b1;
+        if (wr_en & ~rd_en) depth_next = depth + 1'b1;
+        else if (~wr_en & rd_en) depth_next = depth - 1'b1;
+    end
+    
+    always @(`pronoc_clk_reset_edge) begin
+        if (`pronoc_reset) begin
+            rd_ptr <= {Bw{1'b0}};
+            wr_ptr <= {Bw{1'b0}};
+            depth  <= {DEPTHw{1'b0}};
+        end
+        else begin
+            rd_ptr <= rd_ptr_next;
+            wr_ptr <= wr_ptr_next;
+            depth <= depth_next;
+        end
+    end
+    
+    //assign dout = queue[rd_ptr];
+    localparam  [DEPTHw-1 : 0] Bint2 = B_1[DEPTHw-1 : 0];
+    always_comb begin
+        stat_o.full = depth == B [DEPTHw-1 : 0];
+        stat_o.nearly_full = depth >=Bint2; //  B-1
+        stat_o.empty = depth == {DEPTHw{1'b0}};
+        stat_o.has_data = ~(depth == {DEPTHw{1'b0}});
+        stat_o.has_multiple = ~((depth == DEPTHw'(0)) ||  (depth == DEPTHw'(1)));
+    end
+    `ifdef SIMULATION
+    always @(posedge clk) begin
+        if(`pronoc_reset==1'b0)begin
+            if (wr_en && depth == B[DEPTHw-1 : 0] && !rd_en) begin
+            $display(" %t: ERROR: Attempt to write to full FIFO: %m",$time);
+            $finish;
+            end
+            if (rd_en && depth == {DEPTHw{1'b0}}) begin
+            $display("%t: ERROR: Attempt to read an empty FIFO: %m",$time);
+            $finish;
+            end
+        end//~reset
+    end
+    `endif
+endmodule 
diff --git a/mpsoc/rtl/src_noc/fmesh.sv b/mpsoc/rtl/src_noc/fmesh.sv
index 3ec8309..bb8642f 100644
--- a/mpsoc/rtl/src_noc/fmesh.sv
+++ b/mpsoc/rtl/src_noc/fmesh.sv
@@ -1,489 +1,234 @@
 `include "pronoc_def.v"
 /************************
  *      fmesh
- * 
- * **********************/
-
-
-
-
-module  fmesh_addr_encoder #(
-		parameter   NX=2,
-		parameter   NY=2,
-		parameter   NL=2,
-		parameter   NE=16,
-		parameter   EAw=4
-		)(
-		id,
-		code
-		);
+ ***********************/
+module  fmesh_addr_encoder (
+    id,
+    code
+);
+    import pronoc_pkg::*;
     
-	function integer log2;
-		input integer number; begin   
-			log2=(number <=1) ? 1: 0;    
-			while(2**log2<number) begin    
-				log2=log2+1;    
-			end        
-		end   
-	endfunction // log2 
+    input  [NEw-1 :0] id;
+    output [EAw-1 : 0] code;
     
-	localparam  LOCAL   =   0,  
-		EAST    =   1, 
-		NORTH   =   2,  
-		WEST    =   3,  
-		SOUTH   =   4;  
-        
-
-   
-	function integer addrencode; 
-		input integer in,nx,nxw,nl,nyw,ny;
-		integer  y, x, l,p, diff,mul;begin
-			mul  = nx*ny*nl;            
-			if(in < mul) begin 
-				y = ((in/nl) / nx ); 
-				x = ((in/nl) % nx ); 
-				l = (in % nl); 
-				p = (l==0)? LOCAL : 4+l;            
-			end else begin      
-				diff = in -  mul ;
-				if( diff <  nx) begin //top mesh edge 
-					y = 0;
-					x = diff;
-					p = NORTH;
-				end else if  ( diff < 2* nx) begin //bottom mesh edge 
-					y = ny-1;
-					x = diff-nx;
-					p = SOUTH;
-				end else if  ( diff < (2* nx)+ny ) begin //left mesh edge 
-					y = diff - (2* nx);
-					x = 0;
-					p = WEST;
-				end else begin //right mesh edge 
-					y = diff - (2* nx) -ny;
-					x = nx-1;
-					p = EAST; 
-				end
-			end//else 
-			addrencode = ( p<<(nxw+nyw) | (y<<nxw) | x);      
-		end   
-	endfunction // addrencode    
-        
-        
-      
-	localparam 
-		NXw= log2(NX),
-		NYw= log2(NY),
-		NEw = log2(NE);    
-
-
-	input  [NEw-1 :0] id;
-	output [EAw-1 : 0] code;
-
-	wire [EAw-1 : 0 ] codes [NE-1 : 0];
-	genvar i;
-	generate 
-		for(i=0; i< NE; i=i+1) begin : endpoints
-			//Endpoint decoded address
-			/* verilator lint_off WIDTH */          
-			localparam [EAw-1 : 0] ENDP= addrencode(i,NX,NXw,NL,NYw,NY);
-			/* verilator lint_on WIDTH */
-			assign codes[i] = ENDP;            
-		end
-	endgenerate
-
-	assign code = codes[id];
+    wire [EAw-1 : 0 ] codes [NE-1 : 0];
+    genvar i;
+    generate 
+        for(i=0; i< NE; i=i+1) begin : endpoints
+            //Endpoint decoded address
+            localparam  unsigned ENDP = fmesh_endp_addr(i);
+            assign codes[i] = EAw'(ENDP);
+        end
+    endgenerate
+    assign code = codes[id];
 endmodule
 
 
-module  fmesh_addr_coder #(
-		parameter   NX=2,
-		parameter   NY=2,
-		parameter   NL=2,
-		parameter   NE=16,
-		parameter   EAw=4
-		)(
-		id,
-		code
-		);
+module  fmesh_addr_coder (
+    id,
+    code
+);
+    import pronoc_pkg::*;
     
-	function integer log2;
-		input integer number; begin   
-			log2=(number <=1) ? 1: 0;    
-			while(2**log2<number) begin    
-				log2=log2+1;    
-			end        
-		end   
-	endfunction // log2 
+    output [NEw-1 :0] id;
+    input [EAw-1 : 0] code;
     
-	localparam  LOCAL   =   0,  
-		EAST    =   1, 
-		NORTH   =   2,  
-		WEST    =   3,  
-		SOUTH   =   4;  
-  
-        
-	function integer addrencode; 
-		input integer in,nx,nxw,nl,nyw,ny;
-		integer  y, x, l,p, diff,mul;begin
-			mul  = nx*ny*nl;            
-			if(in < mul) begin 
-				y = ((in/nl) / nx ); 
-				x = ((in/nl) % nx ); 
-				l = (in % nl); 
-				p = (l==0)? LOCAL : 4+l;            
-			end else begin      
-				diff = in -  mul ;
-				if( diff <  nx) begin //top mesh edge 
-					y = 0;
-					x = diff;
-					p = NORTH;
-				end else if  ( diff < 2* nx) begin //bottom mesh edge 
-					y = ny-1;
-					x = diff-nx;
-					p = SOUTH;
-				end else if  ( diff < (2* nx)+ny ) begin //left mesh edge 
-					y = diff - (2* nx);
-					x = 0;
-					p = WEST;
-				end else begin //right mesh edge 
-					y = diff - (2* nx) -ny;
-					x = nx-1;
-					p = EAST; 
-				end
-			end//else 
-			addrencode = ( p<<(nxw+nyw) | (y<<nxw) | x);      
-		end   
-	endfunction // addrencode   
-        
-      
-	localparam 
-		NXw= log2(NX),
-		NYw= log2(NY),
-		NEw = log2(NE);    
-
-
-	output [NEw-1 :0] id;
-	input [EAw-1 : 0] code;
-
-	wire   [NEw-1 : 0]  codes   [(2**EAw)-1 : 0 ];
-	genvar i;
-	generate 
-		for(i=0; i< NE; i=i+1) begin : endpoints
-			//Endpoint decoded address
-			/* verilator lint_off WIDTH */
-			localparam [EAw-1 : 0] ENDP= addrencode(i,NX,NXw,NL,NYw,NY);
-			/* verilator lint_on WIDTH */
-			assign codes[ENDP] = i;            
-		end
-	endgenerate
-
-	assign id = codes[code];
+    wire   [NEw-1 : 0]  codes   [(2**EAw)-1 : 0 ];
+    genvar i;
+    generate 
+        for(i=0; i< NE; i=i+1) begin : endpoints
+            //Endpoint decoded address
+            localparam unsigned ENDP= fmesh_endp_addr(i);
+            assign codes[EAw'(ENDP)] = i;            
+        end
+    endgenerate
+    assign id = codes[code];
 endmodule
 
-
-
-
-module fmesh_endp_addr_decode #(
-		parameter T1=4,
-		parameter T2=4,
-		parameter T3=4,
-		parameter EAw=9
-		)(
-		e_addr,
-		ex,
-		ey,
-		ep,
-		valid
-		);
-
-	function integer log2;
-		input integer number; begin   
-			log2=(number <=1) ? 1: 0;    
-			while(2**log2<number) begin    
-				log2=log2+1;    
-			end        
-		end   
-	endfunction // log2 
-
-	localparam
-		NX = T1,
-		NY = T2,
-		NL = T3, 
-		EXw = log2(NX),   
-		EYw = log2(NY),
-		EPw = EAw - EXw - EYw,
-		P   = 5 + NL -1;    
-    
-	/* verilator lint_off WIDTH */ 
-	localparam [EXw-1 : 0]    MAXX = (NX-1); 
-	localparam [EYw-1 : 0]    MAXY = (NY-1);
-	localparam [EPw-1 : 0]    MAXP = (P-1);	
-	/* verilator lint_on WIDTH */ 
-    
+module fmesh_endp_addr_decode (
+    e_addr,
+    ex,
+    ey,
+    ep,
+    valid
+);
+    import pronoc_pkg::*;
     
-	input  [EAw-1 : 0] e_addr;
-	output [EXw-1 : 0] ex;
-	output [EYw-1 : 0] ey;
-	output [EPw-1 : 0] ep;
-	output valid;
+    localparam
+        EXw = log2(NX),
+        EYw = log2(NY),
+        EPw = EAw - EXw - EYw,
+        P   = 5 + NL -1;
     
-	assign {ep,ey,ex} = e_addr; 
-	/* verilator lint_off CMPCONST */
-	assign valid = ( (ex<= MAXX) & (ey <= MAXY) & (ep<= MAXP) );
-	/* verilator lint_on CMPCONST */
-	   
+    /* verilator lint_off WIDTH */ 
+    localparam [EXw-1 : 0]    MAXX = (NX-1); 
+    localparam [EYw-1 : 0]    MAXY = (NY-1);
+    localparam [EPw-1 : 0]    MAXP = (P-1);
+    /* verilator lint_on WIDTH */ 
     
+    input  [EAw-1 : 0] e_addr;
+    output [EXw-1 : 0] ex;
+    output [EYw-1 : 0] ey;
+    output [EPw-1 : 0] ep;
+    output valid;
+    assign {ep,ey,ex} = e_addr; 
+    /* verilator lint_off CMPCONST */
+    assign valid = ( (ex<= MAXX) & (ey <= MAXY) & (ep<= MAXP) );
+    /* verilator lint_on CMPCONST */
 endmodule
 
 
 module fmesh_destp_generator #(
-		parameter ROUTE_NAME = "XY",  
-		parameter ROUTE_TYPE = "DETERMINISTIC",
-		parameter P=5,
-		parameter DSTPw=4,
-		parameter NL=1,
-		parameter PLw=1,
-		parameter PPSw=4,
-		parameter SW_LOC=0,
-		parameter SELF_LOOP_EN="NO" 
-		)(
-		dest_port_out,
-		dest_port_coded,
-		endp_localp_num,
-		swap_port_presel,
-		port_pre_sel,
-		odd_column
-		);
-	localparam P_1 =  ( SELF_LOOP_EN=="NO")?  P-1 : P;
+    parameter P=5,
+    parameter PLw=1,
+    parameter SW_LOC=0
+)(
+    dest_port_out,
+    dest_port_coded,
+    endp_localp_num,
+    swap_port_presel,
+    port_pre_sel,
+    odd_column
+    );
+    import pronoc_pkg::*;
+    localparam P_1 = (SELF_LOOP_EN )?  P : P-1;
     
-	input  [DSTPw-1 : 0] dest_port_coded;
-	input  [PLw-1 : 0] endp_localp_num;
-	output [P_1-1 : 0] dest_port_out;
-	input           swap_port_presel;
-	input  [PPSw-1 : 0] port_pre_sel;
-	input odd_column;
-        
-	wire [P_1-1 : 0] dest_port_in;
-
-	fmesh_destp_decoder #(
-		.ROUTE_TYPE(ROUTE_TYPE),
-		.P(P),
-		.DSTPw(DSTPw),
-		.NL(NL),
-		.PLw(PLw),
-		.PPSw(PPSw),
-		.SW_LOC(SW_LOC),
-		.SELF_LOOP_EN(SELF_LOOP_EN)
-	)
-	decoder
-	(
-		.dest_port_coded(dest_port_coded),             
-		.dest_port_out(dest_port_in),
-		.endp_localp_num(endp_localp_num),
-		.swap_port_presel(swap_port_presel),
-		.port_pre_sel(port_pre_sel)
-		);
-
-	assign dest_port_out = dest_port_in;
-
+    input  [DSTPw-1 : 0] dest_port_coded;
+    input  [PLw-1 : 0] endp_localp_num;
+    output [P_1-1 : 0] dest_port_out;
+    input           swap_port_presel;
+    input  [PPSw-1 : 0] port_pre_sel;
+    input odd_column;
+    
+    wire [P_1-1 : 0] dest_port_in;
+    
+    fmesh_destp_decoder #(
+        .P(P),
+        .PLw(PLw),
+        .SW_LOC(SW_LOC)
+    ) decoder  (
+        .dest_port_coded(dest_port_coded),
+        .dest_port_out(dest_port_in),
+        .endp_localp_num(endp_localp_num),
+        .swap_port_presel(swap_port_presel),
+        .port_pre_sel(port_pre_sel)
+        );
+    assign dest_port_out = dest_port_in;
 endmodule
 
 
 
-
-
-
-
-
-
-
-
-
-
 module fmesh_destp_decoder #(
-		parameter ROUTE_TYPE="DETERMINISTIC",
-		parameter P=6,
-		parameter DSTPw=4,
-		parameter NL=2,
-		parameter PLw=1,
-		parameter PPSw=4,
-		parameter SW_LOC=0,
-		parameter SELF_LOOP_EN="NO"
-		)(
-		dest_port_coded,
-		endp_localp_num,
-		dest_port_out,
-		swap_port_presel,
-		port_pre_sel
-		);
-  
-	localparam P_1 = ( SELF_LOOP_EN=="NO")?  P-1 : P;
-  
-	input  [DSTPw-1 : 0] dest_port_coded;
-	input  [PLw-1 : 0] endp_localp_num;
-	output [P_1-1 : 0] dest_port_out;
-	input           swap_port_presel;
-	input  [PPSw-1 : 0] port_pre_sel;
+    parameter P=6,
+    parameter PLw=1,
+    parameter SW_LOC=0
+)(
+    dest_port_coded,
+    endp_localp_num,
+    dest_port_out,
+    swap_port_presel,
+    port_pre_sel
+);
+    import pronoc_pkg::*;
+    localparam P_1 = (SELF_LOOP_EN )?  P : P-1;
     
-	wire [P-1 : 0] endp_localp_onehot;
-   
-	reg [4:0] portout;
-   
-	generate 
-		if( ROUTE_TYPE == "DETERMINISTIC") begin :dtrmn
-         
-       
-			wire x,y,a,b;
-			assign {x,y,a,b} = dest_port_coded;
-          
-			always @(*)begin 
-				case({a,b})
-					2'b10 : portout = {1'b0,~x,1'b0,x,1'b0};
-					2'b01 : portout = {~y,1'b0,y,1'b0,1'b0};
-					2'b00 : portout =  5'b00001;
-					2'b11 : portout = {~y,1'b0,y,1'b0,1'b0}; //invalid condition in determinstic routing
-				endcase
-			end //always
-          
-		end else begin : adpv
-        
-			wire x,y,a,b;
-			assign {x,y,a,b} = dest_port_coded;        
-			wire [PPSw-1:0] port_pre_sel_final;
-			assign port_pre_sel_final= (swap_port_presel)? ~port_pre_sel: port_pre_sel;
-        
-			always @(*)begin 
-				case({a,b})
-					2'b10 : portout = {1'b0,~x,1'b0,x,1'b0};
-					2'b01 : portout = {~y,1'b0,y,1'b0,1'b0};
-					2'b11 : portout = (port_pre_sel_final[{x,y}])?  {~y,1'b0,y,1'b0,1'b0} : {1'b0,~x,1'b0,x,1'b0};
-					2'b00 : portout =  5'b00001;
-				endcase
-			end //always
-		end //adaptive
-
-		wire [P-1 : 0] destport_onehot;
-	
-		bin_to_one_hot #(
-			.BIN_WIDTH(PLw),
-			.ONE_HOT_WIDTH(P)
-		)
-		conv
-		(
-			.bin_code(endp_localp_num),
-			.one_hot_code(endp_localp_onehot)
-		);
-		if(NL>1) begin :multi    
-			assign destport_onehot =(portout[0])? endp_localp_onehot : /*select local destination*/ 
-				{ {(NL-1){1'b0}} ,portout};
-		end else begin 
-			assign destport_onehot =(portout[0])? endp_localp_onehot : /*select local destination*/ 
-				portout;
-		end
-		
-		if(SELF_LOOP_EN == "NO") begin :nslp
-			remove_sw_loc_one_hot #(
-					.P(P),
-					.SW_LOC(SW_LOC)
-				)
-				remove_sw_loc
-				(
-					.destport_in(destport_onehot),
-					.destport_out(dest_port_out)
-				);
-		end else begin: slp
-				assign dest_port_out = destport_onehot;            
-		end
-	
-		endgenerate
+    input  [DSTPw-1 : 0] dest_port_coded;
+    input  [PLw-1 : 0] endp_localp_num;
+    output [P_1-1 : 0] dest_port_out;
+    input           swap_port_presel;
+    input  [PPSw-1 : 0] port_pre_sel;
+    
+    logic [P-1 : 0] endp_localp_onehot;
+    reg [4:0] portout;
+    wire x,y,a,b;
+    assign {x,y,a,b} = dest_port_coded;
+    wire [PPSw-1:0] port_pre_sel_final;
+    assign port_pre_sel_final = 
+        ( IS_DETERMINISTIC ) ? {PPSw{1'b1}}:
+        (swap_port_presel) ? ~port_pre_sel : port_pre_sel;
+    always_comb begin 
+        case({a,b})
+            2'b10 : portout = {1'b0,~x,1'b0,x,1'b0};
+            2'b01 : portout = {~y,1'b0,y,1'b0,1'b0};
+            2'b00 : portout = 5'b00001;
+            2'b11 : portout = (port_pre_sel_final[{x,y}]) ?  {~y,1'b0,y,1'b0,1'b0} : {1'b0,~x,1'b0,x,1'b0};
+        endcase
+    end //always
+    
+    logic [P-1 : 0] destport_onehot;    
+    //bin_to_one_hot
+    always_comb begin
+        endp_localp_onehot = {P{1'b0}};
+        endp_localp_onehot[endp_localp_num] = 1'b1;
+    end
+    
+    generate 
+    if(NL>1) begin :multi    
+        assign destport_onehot =(portout[0])? endp_localp_onehot : /*select local destination*/ 
+            { {(NL-1){1'b0}} ,portout};
+    end else begin 
+        assign destport_onehot =(portout[0])? endp_localp_onehot : /*select local destination*/ 
+            portout;
+    end 
+    endgenerate   
+    
+    destport_non_selfloop_fix #(
+        .SELF_LOOP_EN(SELF_LOOP_EN),
+        .P(P),
+        .SW_LOC(SW_LOC)
+    ) fix (
+        .destport_in(destport_onehot),
+        .destport_out(dest_port_out)
+    );
 endmodule
 
 
-
 /********************
-
-    distance_gen 
-     
+*    distance_gen 
  ********************/
-
-module fmesh_distance_gen #(
-		parameter T1= 4,    // number of router in x axis
-		parameter T2= 4,    // number of router in y axis
-		parameter T3= 4,
-		parameter EAw=4,
-		parameter DISTw=4
-)(
-		src_e_addr,
-		dest_e_addr,
-		distance
+module fmesh_distance_gen (
+    src_e_addr,
+    dest_e_addr,
+    distance
 );
-
-	function integer log2;
-		input integer number; begin   
-			log2=(number <=1) ? 1: 0;    
-			while(2**log2<number) begin    
-				log2=log2+1;    
-			end       
-		end   
-	endfunction // log2 
- 
- 
-	localparam 
-		Xw  =   log2(T1),   // number of node in x axis
-		Yw  =   log2(T2);    // number of node in y axis 
-	localparam [Xw : 0] NX  = T1;
-	localparam [Yw : 0] NY  = T2;
-              
-     
-	input [EAw-1 : 0] src_e_addr;
-	input [EAw-1 : 0] dest_e_addr;               
-	output[DISTw-1:   0]distance;                     
-
-	wire [Xw-1 :   0]src_x,dest_x;
-	wire [Yw-1 :   0]src_y,dest_y;
-   
-	fmesh_endp_addr_decode #(
-		.T1(T1),
-		.T2(T2),
-		.T3(T3),
-		.EAw(EAw)
-	)
-	src_addr_decode
-	(
-		.e_addr(src_e_addr),
-		.ex(src_x),
-		.ey(src_y),
-		.ep(),
-		.valid()
-	);
+    import pronoc_pkg::*;
     
-	fmesh_endp_addr_decode #(
-		.T1(T1),
-		.T2(T2),
-		.T3(T3),
-		.EAw(EAw)
-	)
-	dest_addr_decode
-	(
-		.e_addr(dest_e_addr),
-		.ex(dest_x),
-		.ey(dest_y),
-		.ep(),
-		.valid()
-	);
-       
-	reg [Xw-1  :   0] x_offset;
-	reg [Yw-1  :   0] y_offset;
+    localparam 
+        Xw  =   log2(T1),   // number of node in x axis
+        Yw  =   log2(T2);    // number of node in y axis 
+    localparam [Xw : 0] NX  = T1;
+    localparam [Yw : 0] NY  = T2;
     
-	always @(*) begin 
-			x_offset     = (src_x> dest_x)? src_x - dest_x : dest_x - src_x;
-			y_offset     = (src_y> dest_y)? src_y - dest_y : dest_y - src_y;
-	end
-               
-			
-	/* verilator lint_off WIDTH */ 
-	assign distance =  x_offset + y_offset +1'b1;
-	/* verilator lint_on WIDTH */ 
-endmodule
-
-
+    input [EAw-1 : 0] src_e_addr;
+    input [EAw-1 : 0] dest_e_addr;
+    output[DISTw-1:   0]distance;
+    
+    wire [Xw-1 :   0]src_x,dest_x;
+    wire [Yw-1 :   0]src_y,dest_y;
+    
+    fmesh_endp_addr_decode src_addr_decode (
+        .e_addr(src_e_addr),
+        .ex(src_x),
+        .ey(src_y),
+        .ep(),
+        .valid()
+    );
+    
+    fmesh_endp_addr_decode dest_addr_decode (
+        .e_addr(dest_e_addr),
+        .ex(dest_x),
+        .ey(dest_y),
+        .ep(),
+        .valid()
+    );
+    
+    reg [Xw-1  :   0] x_offset;
+    reg [Yw-1  :   0] y_offset;    
+    always_comb begin 
+            x_offset     = (src_x> dest_x)? src_x - dest_x : dest_x - src_x;
+            y_offset     = (src_y> dest_y)? src_y - dest_y : dest_y - src_y;
+    end      
+    /* verilator lint_off WIDTH */ 
+    assign distance =  x_offset + y_offset +1'b1;
+    /* verilator lint_on WIDTH */ 
+endmodule
\ No newline at end of file
diff --git a/mpsoc/rtl/src_noc/header_flit.sv b/mpsoc/rtl/src_noc/header_flit.sv
index 62f77a2..f237b3a 100644
--- a/mpsoc/rtl/src_noc/header_flit.sv
+++ b/mpsoc/rtl/src_noc/header_flit.sv
@@ -30,9 +30,8 @@
 ***************/
 
 module header_flit_generator #(
-    parameter NOC_ID=0,
     parameter DATA_w=9 // header flit can carry Optional data. The data will be placed after control data.  Fpay >= DATA_w + CTRL_BITS_w  
-)(    
+)(
     flit_out,    
     src_e_addr_in,
     dest_e_addr_in,
@@ -42,16 +41,15 @@ module header_flit_generator #(
     vc_num_in,
     be_in,
     data_in    
-);	
+);
     
-	`NOC_CONF   
- 
+    import pronoc_pkg::*;   
     localparam    HDR_FLAG  =   2'b10;        
-
     localparam 
         Dw = (DATA_w==0)? 1 : DATA_w,      
-        DATA_LSB= MSB_BE+1,               DATA_MSB= (DATA_LSB + DATA_w)<FPAYw ? DATA_LSB + Dw-1 : FPAYw-1;
-        
+        DATA_LSB= MSB_BE+1,  
+        DATA_MSB= ((DATA_LSB + DATA_w)<FPAYw) ? DATA_LSB + Dw-1 : FPAYw-1;
+    
     output   [Fw-1  :   0] flit_out; 
     input    [Cw-1  :   0] class_in;    
     input    [DAw-1 :   0] dest_e_addr_in;
@@ -61,58 +59,52 @@ module header_flit_generator #(
     input    [DSTPw-1   :   0] destport_in;
     input    [BEw-1 : 0] be_in;
     input    [Dw-1  :   0] data_in;
- 
+    
    // assign flit_out [W+Cw+P_1+Xw+Yw+Xw+Yw-1 :0] = {weight_i,class_i,destport_i,x_dst_i,y_dst_i,x_src_i,y_src_i};
     assign flit_out [E_SRC_MSB : E_SRC_LSB] = src_e_addr_in;
     assign flit_out [E_DST_MSB : E_DST_LSB] = dest_e_addr_in;
     assign flit_out [DST_P_MSB : DST_P_LSB] = destport_in; 
     
-   
     generate
     if(C>1)begin :have_class 
         assign flit_out [CLASS_MSB :CLASS_LSB] = class_in; 
     end 
-
-    /* verilator lint_off WIDTH */
-    if(SWA_ARBITER_TYPE != "RRA")begin  : wrra_b
-    /* verilator lint_on WIDTH */
-        assign flit_out [WEIGHT_MSB :WEIGHT_LSB] = weight_in;   
+    
+    if(~IS_RRA)begin  : wrra_b
+        assign flit_out [WEIGHT_MSB :WEIGHT_LSB] = weight_in;
     end 
     
     if( BYTE_EN ) begin : be_1
-        assign flit_out [BE_MSB : BE_LSB] = be_in;    
+        assign flit_out [BE_MSB : BE_LSB] = be_in;
     end
     
-    
     if (DATA_w ==0) begin :no_data
         if(FPAYw>DATA_LSB) begin: dontcare
-                 assign flit_out [FPAYw-1 : DATA_LSB] = {(FPAYw-DATA_LSB){1'bX}};        
+            assign flit_out [FPAYw-1 : DATA_LSB] = {(FPAYw-DATA_LSB){1'b0}};
         end
     end else begin :have_data
-                 assign flit_out [DATA_MSB : DATA_LSB] = data_in[DATA_MSB-DATA_LSB : 0]; // we have enough space for adding whole of the data                 
+        if (FPAYw > DATA_MSB+1) begin
+            assign flit_out [FPAYw-1 : DATA_MSB+1] = {(FPAYw-DATA_MSB-1){1'b0}};
+        end
+        assign flit_out [DATA_MSB : DATA_LSB] = data_in[DATA_MSB-DATA_LSB : 0]; // we have enough space for adding whole of the data                 
     end    
     endgenerate    
-     
+    
     assign flit_out [FPAYw+V-1    :   FPAYw] = vc_num_in;
     assign flit_out [Fw-1        :    Fw-2] = HDR_FLAG;  
     
-    
-    //synthesis translate_off 
-    //synopsys  translate_off
+    `ifdef SIMULATION
     initial begin
         if((DATA_LSB + DATA_w)-1 > FPAYw)begin
             $display("%t: ERROR: The reqired header flit size is %d which is larger than %d payload size   ",$time,(DATA_LSB + DATA_w)-1,FPAYw);
-            $finish;        
+            $finish;
         end
-    end    
-    //synopsys  translate_on
-    //synthesis translate_on     
-
+    end
+    `endif
 endmodule
 
 
 module extract_header_flit_info # (
-    parameter NOC_ID=0,
     parameter DATA_w = 0
 ) (
     //inputs
@@ -130,20 +122,19 @@ module extract_header_flit_info # (
     vc_num_o,  
     hdr_flit_wr_o,
     be_o    
-); 	
+);     
+    
+    import pronoc_pkg::*;
     
- 	`NOC_CONF
-       
     localparam       
         W = WEIGHTw,
         Dw = (DATA_w==0)? 1 : DATA_w,
-        DATA_LSB= MSB_BE+1,               DATA_MSB= (DATA_LSB + DATA_w)<FPAYw ? DATA_LSB + Dw-1 : FPAYw-1,
+        DATA_LSB= MSB_BE+1,               
+        DATA_MSB= ((DATA_LSB + DATA_w)<FPAYw) ? DATA_LSB + Dw-1 : FPAYw-1,
         OFFSETw = DATA_MSB - DATA_LSB +1; 
-     
     
     input [Fw-1 : 0] flit_in;
     input flit_in_wr;
-    
     output [EAw-1 : 0] src_e_addr_o;
     output [DAw-1 : 0] dest_e_addr_o;
     output [DSTPw-1 : 0] destport_o;    
@@ -156,76 +147,90 @@ module extract_header_flit_info # (
     output [BEw-1 : 0] be_o;
     output [Dw-1  :   0] data_o;
     
-    
-   
-   
-   
     wire [OFFSETw-1 : 0 ] offset;
-  
+    
     assign src_e_addr_o = flit_in [E_SRC_MSB : E_SRC_LSB];
     assign dest_e_addr_o = flit_in [E_DST_MSB : E_DST_LSB];
     assign destport_o = flit_in [DST_P_MSB : DST_P_LSB];
     
-   
     generate
     if(C>1)begin :have_class 
         assign class_o = flit_in [CLASS_MSB : CLASS_LSB];
     end else begin : no_class
-     assign class_o = {Cw{1'b0}};
-    end   
-
-    /* verilator lint_off WIDTH */
-    if(SWA_ARBITER_TYPE != "RRA")begin  : wrra_b
-    /* verilator lint_on WIDTH */
+        assign class_o = {Cw{1'b0}};
+    end 
+    if(~IS_RRA)begin  : wrra_b
         assign weight_o =  flit_in [WEIGHT_MSB : WEIGHT_LSB];    
     end else begin : rra_b
         assign weight_o = {WEIGHTw{1'bX}};        
     end 
-    
     if( BYTE_EN ) begin : be_1
         assign be_o = flit_in [BE_MSB : BE_LSB];    
     end else begin : be_0    
         assign be_o = {BEw{1'bX}};
     end
-    
-    
     assign offset = flit_in [DATA_MSB : DATA_LSB];    
-    
-    
     if(Dw > OFFSETw) begin : if1     
         assign data_o={{(Dw-OFFSETw){1'b0}},offset};
     end else begin : if2 
         assign data_o=offset[Dw-1 : 0];
     end    
-    
     endgenerate          
-   
-   /* verilator lint_off WIDTH */     
-    assign hdr_flg_o  = (PCK_TYPE == "MULTI_FLIT") ? flit_in [Fw-1]  : 1'b1;
-    assign tail_flg_o = (PCK_TYPE == "MULTI_FLIT") ? flit_in [Fw-2]  : 1'b1;
-   /* verilator lint_on WIDTH */    
-   
-   
+    
+    assign hdr_flg_o  = (IS_MULTI_FLIT) ? flit_in [Fw-1]  : 1'b1;
+    assign tail_flg_o = (IS_MULTI_FLIT) ? flit_in [Fw-2]  : 1'b1;
     assign vc_num_o = flit_in [FPAYw+V-1 : FPAYw];
     assign hdr_flit_wr_o= (flit_in_wr & hdr_flg_o )? vc_num_o : {V{1'b0}};
-
 endmodule
 
-
-
-
-
+module header_flit_info #(
+    parameter DATA_w = 0 
+)(
+    flit,
+    hdr_flit,
+    data_o
+);
+    
+    import pronoc_pkg::*;
+    
+    localparam 
+        Dw = (DATA_w==0)? 1 : DATA_w;
+    
+    input flit_t flit;
+    output hdr_flit_t hdr_flit;
+    output [Dw-1 : 0] data_o;
+    
+    localparam
+        DATA_LSB= MSB_BE+1,
+        DATA_MSB= (DATA_LSB + DATA_w)<FPAYw ? DATA_LSB + Dw-1 : FPAYw-1,
+        OFFSETw = DATA_MSB - DATA_LSB +1;
+    
+    always_comb begin
+        hdr_flit.src_e_addr  = flit.payload [E_SRC_MSB : E_SRC_LSB];
+        hdr_flit.dest_e_addr = flit.payload [E_DST_MSB : E_DST_LSB];
+        hdr_flit.destport    = flit.payload [DST_P_MSB : DST_P_LSB];
+        hdr_flit.message_class = (C>1)? flit.payload [CLASS_MSB : CLASS_LSB] :  {Cw{1'b0}};
+        hdr_flit.weight = (IS_WRRA)? flit.payload [WEIGHT_MSB : WEIGHT_LSB] : {WEIGHTw{1'b0}};
+        hdr_flit.be = (BYTE_EN)? flit.payload [BE_MSB : BE_LSB]: {BEw{1'b0}};
+    end
+    
+    wire [OFFSETw-1 : 0 ] offset = flit.payload [DATA_MSB : DATA_LSB];
+    generate
+    if(Dw > OFFSETw) begin : if1
+        assign data_o={{(Dw-OFFSETw){1'b0}},offset};
+    end else begin : if2 
+        assign data_o=offset[Dw-1 : 0];
+    end
+    endgenerate
+endmodule
 
 /***********************************    
 *  flit_update
 *  update the header flit look ahead routing and output VC
-**********************************/
-
+*********************************/
 module header_flit_update_lk_route_ovc #(
-    parameter NOC_ID=0,
     parameter P = 5
-)
-(
+)(
     flit_in ,
     flit_out,
     vc_num_in,
@@ -237,145 +242,102 @@ module header_flit_update_lk_route_ovc #(
     reset,
     clk
 );
-
-	`NOC_CONF
-	
-    localparam  
-        VDSTPw = V * DSTPw,
-        VV = V * V;        
-
+    import pronoc_pkg::*;
+    
     input [Fw-1 : 0]  flit_in;
     output reg [Fw-1 : 0]  flit_out;
     input [V-1 : 0]  vc_num_in;
-    input [VDSTPw-1 : 0]  lk_dest_all_in;
-    input                           reset,clk;
-    input [VV-1 : 0]  assigned_ovc_num;
+    input [DSTPw-1 : 0]  lk_dest_all_in [V-1:0];
+    input reset,clk;
+    input [V-1 : 0]  assigned_ovc_num[V-1:0];
     input [V-1 : 0]  sel;
-    input                    any_ivc_sw_request_granted;
+    input any_ivc_sw_request_granted;
     input [DSTPw-1 : 0]  lk_dest_not_registered;
     
     wire hdr_flag;
     logic [V-1 : 0]  vc_num_delayed;
-    wire [V-1 : 0]  ovc_num; 
+    logic [V-1 : 0]  ovc_num; 
     wire [DSTPw-1 : 0]  lk_dest,dest_coded;
-    wire [DSTPw-1 : 0]  lk_mux_out;
-
-    pronoc_register #(.W(V)) reg1 (.in(vc_num_in), .out(vc_num_delayed), .reset(reset), .clk(clk));   
-
-    /* verilator lint_off WIDTH */
-    assign hdr_flag = ( PCK_TYPE == "MULTI_FLIT")? flit_in[Fw-1]: 1'b1;
-    /* verilator lint_on WIDTH */
-      
-    onehot_mux_1D #(
-        .W(DSTPw),
-        .N(V) 
-    )
-    lkdest_mux
-    (
-        .in(lk_dest_all_in),
-        .out(lk_mux_out),
-        .sel(vc_num_delayed)
-    );
-
+    logic [DSTPw-1 : 0]  lk_mux_out;
+    always_ff @ (`pronoc_clk_reset_edge) begin
+        if (`pronoc_reset) begin
+            vc_num_delayed <= '0;
+        end else begin
+            vc_num_delayed <= vc_num_in;
+        end
+    end
+    assign hdr_flag = (IS_MULTI_FLIT)? flit_in[Fw-1]: 1'b1;
+    //One-hot mux
+    always_comb begin
+        lk_mux_out = '0;
+        ovc_num = '0;
+        for (int k = 0; k < V; k++) begin
+            lk_mux_out |= (vc_num_delayed[k]) ?  lk_dest_all_in[k] :  '0;
+            ovc_num |= (vc_num_delayed[k]) ?  assigned_ovc_num[k] :  '0;
+        end
+    end
     generate 
-    /* verilator lint_off WIDTH */
-    if( SSA_EN == "YES" ) begin : predict // bypass the lk fifo when no ivc is granted
-    /* verilator lint_on WIDTH */
+    if( SSA_EN == 1 ) begin : predict // bypass the lk fifo when no ivc is granted
         logic ivc_any_delayed;
-        
-        pronoc_register #(.W(1)) reg2 (.in(any_ivc_sw_request_granted ), .out(ivc_any_delayed), .reset(reset), .clk(clk));
-       
+        always_ff @ (`pronoc_clk_reset_edge) begin
+            if (`pronoc_reset) begin
+                ivc_any_delayed <= 1'b0;
+            end else begin
+                ivc_any_delayed <= any_ivc_sw_request_granted;
+            end
+        end
         assign lk_dest = (ivc_any_delayed == 1'b0)? lk_dest_not_registered : lk_mux_out;
-
     end else begin : no_predict
         assign lk_dest =lk_mux_out;
     end 
     endgenerate
-
-   onehot_mux_1D #(
-        .W(V),
-        .N(V) 
-    )
-    ovc_num_mux
-    (
-        .in(assigned_ovc_num),
-        .out(ovc_num),
-        .sel(vc_num_delayed)
-    );
-       
+    
     generate 
-    /* verilator lint_off WIDTH */ 
-    if((TOPOLOGY == "MESH" || TOPOLOGY == "FMESH" || TOPOLOGY == "TORUS"  || TOPOLOGY ==  "RING") && ROUTE_TYPE != "DETERMINISTIC" )begin :coded
-    /* verilator lint_on WIDTH */ 
-        mesh_torus_adaptive_lk_dest_encoder #(
-            .V(V),
-            .P(P),
-            .DSTPw(DSTPw),
-            .Fw(Fw),
-            .DST_P_MSB(DST_P_MSB),
-            .DST_P_LSB(DST_P_LSB)
-        )
-        dest_encoder
-        (
+    if(IS_REGULAR_TOPO & (~IS_DETERMINISTIC))begin :coded
+        regular_topo_adaptive_lk_dest_encoder  dest_encoder  (
             .sel(sel),
             .dest_coded_out(dest_coded),
             .vc_num_delayed(vc_num_delayed),
             .lk_dest(lk_dest),
             .flit_in(flit_in)
         );
-    
-    
     end else begin : dtrmn1
         assign dest_coded = lk_dest;
         /*
-         mesh_torus_dtrmn_dest_encoder #(
+        regular_topo_dtrmn_dest_encoder #(
             .P(P),
             .DSTPw(DSTPw),
             .Fw(Fw),
             .DST_P_MSB(DST_P_MSB),
             .DST_P_LSB(DST_P_LSB)
-        )
-         dest_encoder
-        (
-         	.dest_coded_out(dest_coded),
-         	.lk_dest(lk_dest),
-         	.flit_in(flit_in)
-         );
+        ) dest_encoder  (
+            .dest_coded_out(dest_coded),
+            .lk_dest(lk_dest),
+            .flit_in(flit_in)
+        );
          */
     end
-        
-    always @(*)begin 
-         flit_out = {flit_in[Fw-1 : Fw-2],ovc_num,flit_in[FPAYw-1 :0]};
-         if(hdr_flag) flit_out[DST_P_MSB : DST_P_LSB]= dest_coded;
-    end
-      
     
+    always_comb begin 
+        flit_out = {flit_in[Fw-1 : Fw-2],ovc_num,flit_in[FPAYw-1 :0]};
+        if(hdr_flag & IS_LOOKAHEAD) flit_out[DST_P_MSB : DST_P_LSB]= dest_coded;
+    end
     endgenerate
-
-
-    
-
 endmodule
 
 /******************
  *  hdr_flit_weight_update
  * ****************/
-
-module hdr_flit_weight_update #(
-    parameter NOC_ID = 0
-) (
+module hdr_flit_weight_update  (
     new_weight,
     flit_in,
     flit_out    
 );
-
-	`NOC_CONF
+    import pronoc_pkg::*;
     
     input [WEIGHTw-1 : 0] new_weight;
     input [Fw-1 : 0] flit_in;
     output [Fw-1 : 0] flit_out;
     
     assign flit_out =  {flit_in[Fw-1 : WEIGHT_LSB+WEIGHTw ] ,new_weight, flit_in[WEIGHT_LSB-1 : 0] };
-
-endmodule
-
+endmodule
\ No newline at end of file
diff --git a/mpsoc/rtl/src_noc/inout_ports.sv b/mpsoc/rtl/src_noc/inout_ports.sv
index 1ff14e6..4b4a6f3 100755
--- a/mpsoc/rtl/src_noc/inout_ports.sv
+++ b/mpsoc/rtl/src_noc/inout_ports.sv
@@ -1,39 +1,38 @@
 `include "pronoc_def.v"
 /**********************************************************************
-**	File: inout_ports.v
+**    File: inout_ports.v
 **    
-**	Copyright (C) 2014-2017  Alireza Monemi
+**    Copyright (C) 2014-2017  Alireza Monemi
 **    
-**	This file is part of ProNoC 
+**    This file is part of ProNoC 
 **
-**	ProNoC ( stands for Prototype Network-on-chip)  is free software: 
-**	you can redistribute it and/or modify it under the terms of the GNU
-**	Lesser General Public License as published by the Free Software Foundation,
-**	either version 2 of the License, or (at your option) any later version.
+**    ProNoC ( stands for Prototype Network-on-chip)  is free software: 
+**    you can redistribute it and/or modify it under the terms of the GNU
+**    Lesser General Public License as published by the Free Software Foundation,
+**    either version 2 of the License, or (at your option) any later version.
 **
-** 	ProNoC is distributed in the hope that it will be useful, but WITHOUT
-** 	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
-** 	or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
-** 	Public License for more details.
+**     ProNoC is distributed in the hope that it will be useful, but WITHOUT
+**     ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+**     or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
+**     Public License for more details.
 **
-** 	You should have received a copy of the GNU Lesser General Public
-** 	License along with ProNoC. If not, see <http:**www.gnu.org/licenses/>.
+**     You should have received a copy of the GNU Lesser General Public
+**     License along with ProNoC. If not, see <http:**www.gnu.org/licenses/>.
 **
 **
-**	Description: 
-**	NoC router Input/output module 
+**    Description: 
+**    NoC router Input/output module 
 **
 **************************************************************/
 
 module inout_ports #(
-    parameter NOC_ID=0,
-    parameter P=5    
-) (
-    current_r_addr,
-    neighbors_r_addr,
+    parameter ROUTER_ID=0,
+    parameter P=5
+)(
     clk,
-    reset,    
-       
+    reset,
+    router_info,
+    
     // to/from neighboring router
     flit_in_all,
     flit_in_wr_all,
@@ -43,6 +42,7 @@ module inout_ports #(
     congestion_out_all,
     credit_init_val_in,
     credit_init_val_out,
+    ctrl_in,
     
     // from vsa: local vc/sw allocator
     vsa_ovc_allocated_all,
@@ -50,7 +50,6 @@ module inout_ports #(
     ivc_num_getting_ovc_grant,
     spec_ovc_num_all,
     nonspec_first_arbiter_granted_ivc_all,
-    spec_first_arbiter_granted_ivc_all,
     nonspec_granted_dest_port_all,
     spec_granted_dest_port_all,
     granted_dest_port_all,
@@ -67,15 +66,14 @@ module inout_ports #(
     vc_weight_is_consumed_all, 
     iport_weight_is_consumed_all, 
     flit_is_tail_all,
-        
+    
     // to crossbar
     flit_out_all,
     ssa_flit_wr_all,
     iport_weight_all,
     oports_weight_all,
     refresh_w_counter,
-    crossbar_flit_out_wr_all,    
-   
+    
     // status
     vsa_credit_decreased_all,
     vsa_ovc_released_all,
@@ -83,55 +81,46 @@ module inout_ports #(
     ovc_info,
     oport_info,
     vsa_ctrl_in,
-    smart_ctrl_in    
+    smart_ctrl_in
 );
-	
-	`NOC_CONF
-   
+    
+    import pronoc_pkg::*;
+    
     localparam
         PV = V * P,
-        PVV = PV * V,    
-        P_1 = ( SELF_LOOP_EN=="NO")?  P-1 : P,
+        PVV = PV * V,
+        P_1 = (SELF_LOOP_EN )?  P : P-1,
         PP_1 = P_1 * P,
-        PVP_1 = PV * P_1,       
+        PVP_1 = PV * P_1,
         PFw = P * Fw,
         CONG_ALw = CONGw*P,    //  congestion width per router 
         W = WEIGHTw,
         WP = W * P,
-        WPP = WP * P,
-        PVDSTPw= PV * DSTPw,
-        PRAw= P * RAw;
-       
-
-    input [RAw-1 : 0] current_r_addr;
-    input [PRAw-1: 0] neighbors_r_addr;
-           
-                    
-    input [PFw-1 : 0] flit_in_all;
+        WPP = WP * P;
+    
+    input router_info_t router_info;
+    input flit_t flit_in_all [P-1 : 0];
     input [P-1 : 0] flit_in_wr_all;
     output[PV-1 : 0] credit_out_all;
     input [PV-1 : 0] credit_in_all;
     input [PV-1 : 0] vsa_ovc_allocated_all;
     input [PVV-1 : 0] granted_ovc_num_all;
+    input ctrl_chanel_t ctrl_in  [P-1 : 0];
     
-   
-   
     input [PV-1 : 0] ivc_num_getting_ovc_grant;
     input [PVV-1 : 0] spec_ovc_num_all;
     input [PV-1 : 0] nonspec_first_arbiter_granted_ivc_all;
-    input [PV-1 : 0] spec_first_arbiter_granted_ivc_all;
     input [PP_1-1 : 0] nonspec_granted_dest_port_all;
     input [PP_1-1 : 0] spec_granted_dest_port_all;    
     input [PP_1-1 : 0] granted_dest_port_all;
     input [P-1 : 0] any_ivc_sw_request_granted_all;
     input [P-1 : 0] any_ovc_granted_in_outport_all;   
-   
+    
     input [CONG_ALw-1 : 0] congestion_in_all;
     output[CONG_ALw-1 : 0] congestion_out_all;
     output[PV-1 : 0] vc_weight_is_consumed_all;
-    output[P-1 : 0] iport_weight_is_consumed_all;  
-    input [P-1 : 0] granted_dst_is_from_a_single_flit_pck;  
-    
+    output[P-1 : 0] iport_weight_is_consumed_all;
+    input [P-1 : 0] granted_dst_is_from_a_single_flit_pck;
     
     // to vc/sw allocator
     output [PVP_1-1 : 0] dest_port_all;
@@ -140,15 +129,14 @@ module inout_ports #(
     output [PV-1 : 0] assigned_ovc_not_full_all;
     output [PVV-1: 0] masked_ovc_request_all;
     output [PV-1 : 0] flit_is_tail_all;
-
+    
     // to crossbar
-    output [PFw-1 : 0] flit_out_all;
-    output [P-1 : 0] ssa_flit_wr_all;
+    output [Fw-1 : 0] flit_out_all [P-1:0];
+    output logic [P-1 : 0] ssa_flit_wr_all;
     output [WP-1: 0] iport_weight_all;
     output [WPP-1:0] oports_weight_all;
     input refresh_w_counter;
-    input [P-1 : 0] crossbar_flit_out_wr_all;
-
+    
     input clk,reset;
     
     output  [PV-1 : 0] vsa_ovc_released_all;
@@ -160,9 +148,8 @@ module inout_ports #(
     input   smart_ctrl_t   smart_ctrl_in [P-1 : 0];
     input   vsa_ctrl_t   vsa_ctrl_in [P-1 : 0];
     input   [CRDTw-1 : 0 ] credit_init_val_in  [P-1 : 0][V-1 : 0];
-    output  [CRDTw-1 : 0 ] credit_init_val_out [P-1 : 0][V-1 : 0]; 
- 
-
+    output  [CRDTw-1 : 0 ] credit_init_val_out [P-1 : 0][V-1 : 0];
+    
     wire [PPSw-1 : 0] port_pre_sel;
     wire [PV-1 :  0]  swap_port_presel;
     wire [PV-1 : 0] reset_ivc_all;     
@@ -174,312 +161,255 @@ module inout_ports #(
     
     ssa_ctrl_t ssa_ctrl [P-1 : 0];   
     
-
-	input_ports #(
-		.NOC_ID(NOC_ID),
-        .P(P)        
-	) the_input_port (
-		.current_r_addr (current_r_addr),    
-		.neighbors_r_addr(neighbors_r_addr),
-		.ivc_num_getting_sw_grant (ivc_num_getting_sw_grant ),
-		.any_ivc_sw_request_granted_all (any_ivc_sw_request_granted_all),    
-		.flit_in_all (flit_in_all),
-		.flit_in_wr_all (flit_in_wr_all),
-		.reset_ivc_all (reset_ivc_all),
-		.flit_is_tail_all (flit_is_tail_all),
-		.ivc_request_all (ivc_request_all),    
-		.dest_port_all(dest_port_all),
-		.flit_out_all (flit_out_all),
-		.assigned_ovc_not_full_all(assigned_ovc_not_full_all),
-		.ovc_is_assigned_all(ovc_is_assigned_all),
-		.sel (sel),
-		.port_pre_sel(port_pre_sel),
-		.swap_port_presel(swap_port_presel),
-		.credit_out_all(credit_out_all),
-		// .lk_destination_encoded_all (lk_destination_encoded_all),
-		.nonspec_first_arbiter_granted_ivc_all(nonspec_first_arbiter_granted_ivc_all),       
-		.destport_clear (destport_clear),
-		.vc_weight_is_consumed_all (vc_weight_is_consumed_all),
-		.iport_weight_is_consumed_all (iport_weight_is_consumed_all),
-		.iport_weight_all(iport_weight_all),
-		.oports_weight_all(oports_weight_all),
-		.granted_dest_port_all(granted_dest_port_all),
-		.refresh_w_counter(refresh_w_counter),
-		.ivc_info(ivc_info),
-		.smart_ctrl_in(smart_ctrl_in),
-		.vsa_ctrl_in(vsa_ctrl_in),
-		.ssa_ctrl_in(ssa_ctrl),
-		.credit_init_val_out(credit_init_val_out),		
-		.reset (reset),
-		.clk (clk)
-	);               
-	
-	
-	output_ports #(
-        .NOC_ID(NOC_ID),
-		.P (P)               
-	) output_ports (		
-		.vsa_ovc_allocated_all                      (vsa_ovc_allocated_all),
-		.flit_is_tail_all                           (flit_is_tail_all),
-		.dest_port_all                              (dest_port_all),
-		.nonspec_granted_dest_port_all              (nonspec_granted_dest_port_all),
-		.credit_in_all                              (credit_in_all),
-		.nonspec_first_arbiter_granted_ivc_all      (nonspec_first_arbiter_granted_ivc_all),
-		.ivc_num_getting_sw_grant                   (ivc_num_getting_sw_grant ),
-		.ovc_avalable_all                           (ovc_avalable_all),
-		.assigned_ovc_not_full_all                  (assigned_ovc_not_full_all),
-		.port_pre_sel                               (port_pre_sel),//only valid for adaptive routing
-		.congestion_in_all                          (congestion_in_all),//only valid for adaptive routing
-		.granted_ovc_num_all 						(granted_ovc_num_all),                  
-               
-		.granted_dst_is_from_a_single_flit_pck      (granted_dst_is_from_a_single_flit_pck),
-		.reset                                      (reset),
-		.clk                                        (clk),
-		.crossbar_flit_out_wr_all					(crossbar_flit_out_wr_all),
-		.any_ovc_granted_in_outport_all ( any_ovc_granted_in_outport_all),  
-		.vsa_ovc_released_all (vsa_ovc_released_all),
-		.vsa_credit_decreased_all(vsa_credit_decreased_all),
-		.oport_info (oport_info),
-		.ivc_info(ivc_info),
-		.ovc_info (ovc_info),
-		.smart_ctrl_in(smart_ctrl_in),
-		.vsa_ctrl_in(vsa_ctrl_in),
-		.ssa_ctrl_in(ssa_ctrl),
-		.credit_init_val_in(credit_init_val_in)
-	);
-
-
+    input_ports #(
+        .ROUTER_ID(ROUTER_ID),
+        .P(P)
+    ) the_input_port (
+        .router_info(router_info),
+        .ivc_num_getting_sw_grant (ivc_num_getting_sw_grant ),
+        .any_ivc_sw_request_granted_all (any_ivc_sw_request_granted_all),    
+        .flit_in_all (flit_in_all),
+        .flit_in_wr_all (flit_in_wr_all),
+        .reset_ivc_all (reset_ivc_all),
+        .flit_is_tail_all (flit_is_tail_all),
+        .ivc_request_all (ivc_request_all),    
+        .dest_port_all(dest_port_all),
+        .flit_out_all (flit_out_all),
+        .assigned_ovc_not_full_all(assigned_ovc_not_full_all),
+        .ovc_is_assigned_all(ovc_is_assigned_all),
+        .sel (sel),
+        .port_pre_sel(port_pre_sel),
+        .swap_port_presel(swap_port_presel),
+        .credit_out_all(credit_out_all),
+        // .lk_destination_encoded_all (lk_destination_encoded_all),
+        .nonspec_first_arbiter_granted_ivc_all(nonspec_first_arbiter_granted_ivc_all),
+        .destport_clear (destport_clear),
+        .vc_weight_is_consumed_all (vc_weight_is_consumed_all),
+        .iport_weight_is_consumed_all (iport_weight_is_consumed_all),
+        .iport_weight_all(iport_weight_all),
+        .oports_weight_all(oports_weight_all),
+        .granted_dest_port_all(granted_dest_port_all),
+        .refresh_w_counter(refresh_w_counter),
+        .ivc_info(ivc_info),
+        .smart_ctrl_in(smart_ctrl_in),
+        .vsa_ctrl_in(vsa_ctrl_in),
+        .ssa_ctrl_in(ssa_ctrl),
+        .credit_init_val_out(credit_init_val_out),
+        .ctrl_in(ctrl_in),
+        .reset (reset),
+        .clk (clk)
+    );   
+    
+    output_ports #(
+        .P (P)
+    ) output_ports (
+        .vsa_ovc_allocated_all(vsa_ovc_allocated_all),
+        .flit_is_tail_all(flit_is_tail_all),
+        .dest_port_all(dest_port_all),
+        .nonspec_granted_dest_port_all(nonspec_granted_dest_port_all),
+        .credit_in_all(credit_in_all),
+        .nonspec_first_arbiter_granted_ivc_all(nonspec_first_arbiter_granted_ivc_all),
+        .ivc_num_getting_sw_grant(ivc_num_getting_sw_grant ),
+        .ovc_avalable_all(ovc_avalable_all),
+        .assigned_ovc_not_full_all(assigned_ovc_not_full_all),
+        .port_pre_sel(port_pre_sel),//only valid for adaptive routing
+        .congestion_in_all(congestion_in_all),//only valid for adaptive routing
+        .granted_ovc_num_all(granted_ovc_num_all),
+        .granted_dst_is_from_a_single_flit_pck(granted_dst_is_from_a_single_flit_pck),
+        .reset(reset),
+        .clk(clk),
+        .any_ovc_granted_in_outport_all(any_ovc_granted_in_outport_all),
+        .vsa_ovc_released_all (vsa_ovc_released_all),
+        .vsa_credit_decreased_all(vsa_credit_decreased_all),
+        .oport_info (oport_info),
+        .ivc_info(ivc_info),
+        .ovc_info (ovc_info),
+        .smart_ctrl_in(smart_ctrl_in),
+        .vsa_ctrl_in(vsa_ctrl_in),
+        .ssa_ctrl_in(ssa_ctrl),
+        .credit_init_val_in(credit_init_val_in)
+    );    
+    
     vc_alloc_request_gen #(
-       	.NOC_ID(NOC_ID),
-        .P(P)    	
+        .P(P)        
     ) vc_alloc_req_gen (
-    	.ivc_info(ivc_info),
-    	.ovc_avalable_all(ovc_avalable_all),    	
-    	.dest_port_decoded_all(dest_port_all),
-    	.masked_ovc_request_all(masked_ovc_request_all),
-    	
-    	.port_pre_sel(port_pre_sel),
-    	.swap_port_presel(swap_port_presel),
-    	.sel(sel),
-    	.reset(reset),
-    	.clk(clk),
-    	.destport_clear(destport_clear),
-    	.ivc_num_getting_ovc_grant(ivc_num_getting_ovc_grant),
-    	//.ssa_ivc_num_getting_ovc_grant_all(nla_ivc_num_getting_ovc_grant_all),
-    	.smart_ctrl_in (smart_ctrl_in),
-    	.ssa_ctrl_in (ssa_ctrl)
-    );
-
-   
-   congestion_out_gen #(
-        .P(P),
-        .V(V),
-        .ROUTE_TYPE(ROUTE_TYPE),
-        .CONGESTION_INDEX(CONGESTION_INDEX),
-        .CONGw(CONGw)
-   )
-   congestion_out
-   (
+        .ivc_info(ivc_info),
+        .ovc_avalable_all(ovc_avalable_all),        
+        .dest_port_decoded_all(dest_port_all),
+        .masked_ovc_request_all(masked_ovc_request_all),
+        .ctrl_in(ctrl_in),   
+        .port_pre_sel(port_pre_sel),
+        .swap_port_presel(swap_port_presel),
+        .sel(sel),
+        .reset(reset),
+        .clk(clk),
+        .destport_clear(destport_clear),
+        .ivc_num_getting_ovc_grant(ivc_num_getting_ovc_grant),
+        //.ssa_ivc_num_getting_ovc_grant_all(nla_ivc_num_getting_ovc_grant_all),
+        .smart_ctrl_in (smart_ctrl_in),
+        .ssa_ctrl_in (ssa_ctrl)
+    );    
+    
+    congestion_out_gen #(
+        .P(P)
+    ) congestion_out (
         .ovc_avalable_all(ovc_avalable_all),
         .ivc_request_all(ivc_request_all),
         .ivc_num_getting_sw_grant(ivc_num_getting_sw_grant ),
         .congestion_out_all(congestion_out_all),
         .clk(clk),
         .reset(reset)
-   );   
-     
-     
-  
-    
-    
-  
-    
-   genvar i;
-   generate  
-    	
-	    /* verilator lint_off WIDTH */
-	   	if( SSA_EN =="YES" ) begin : ssa 
-	   	/* verilator lint_on WIDTH */
-		   	ss_allocator #(
-		   		.NOC_ID(NOC_ID),
-                .P(P)
-		   	)
-		   	the_ssa
-		   	(
-		   		.ivc_info(ivc_info),
-		   		.ovc_info(ovc_info),
-		   		.flit_in_wr_all(flit_in_wr_all),
-		   		.flit_in_all(flit_in_all),
-		   		.any_ivc_sw_request_granted_all(any_ivc_sw_request_granted_all),
-		   		.any_ovc_granted_in_outport_all(any_ovc_granted_in_outport_all),
-		   		.ovc_avalable_all(ovc_avalable_all),
-		   		.clk(clk),
-		   		.reset(reset),		    	    	
-		    	.ssa_ctrl_o(ssa_ctrl)
-		    );
-	
-		end else begin :non_ssa
-			for(i=0;i< P;i=i+1) begin :p_
-				assign  ssa_ctrl[i] = {SSA_CTRL_w{1'b0}};
-			end
-		end
-    
-    	
-    	   	
-	    for(i=0;i< P;i=i+1) begin :p_	    	
-	    	assign ssa_flit_wr_all [i] = ssa_ctrl[i].ssa_flit_wr;
-	    end//for    
-
-    	//synthesis translate_off 
-    	//synopsys  translate_off     
-    	if(DEBUG_EN && MIN_PCK_SIZE >1 )begin :dbg  
-    		wire [PV-1 : 0] non_vsa_ivc_num_getting_ovc_grant_all;
-	    	integer kk;
-	    	for(i=0;i< P;i=i+1) begin :p_
-	    		assign non_vsa_ivc_num_getting_ovc_grant_all [(i+1)*V-1 : i*V] = ssa_ctrl[i].ivc_num_getting_ovc_grant | smart_ctrl_in[i].ivc_num_getting_ovc_grant;	    		
-	    	end//for 
-	    	always @(posedge clk ) begin
-	    		for(kk=0; kk< PV; kk=kk+1'b1 ) if(reset_ivc_all[kk] & (ivc_num_getting_ovc_grant[kk] | non_vsa_ivc_num_getting_ovc_grant_all[kk])) begin 
-	    			$display("%t: ERROR: the ovc %d released and allocat signal is asserted in the same clock cycle : %m",$time,kk);
-	    			$finish;	
-	    		end
-	   	 	end
-		end  
-		//synopsys  translate_on
-		//synthesis translate_on	
-	endgenerate			
+    );   
+    
+    genvar i;
+    generate  
+    
+    if( SSA_EN == 1 ) begin : ssa
+        ss_allocator #(
+            .P(P)
+        ) the_ssa (
+            .ivc_info(ivc_info),
+            .ovc_info(ovc_info),
+            .flit_in_wr_all(flit_in_wr_all),
+            .flit_in_all(flit_in_all),
+            .any_ivc_sw_request_granted_all(any_ivc_sw_request_granted_all),
+            .any_ovc_granted_in_outport_all(any_ovc_granted_in_outport_all),
+            .ovc_avalable_all(ovc_avalable_all),
+            .clk(clk),
+            .reset(reset),
+            .ssa_ctrl_o(ssa_ctrl)
+        );
+        
+    end else begin :non_ssa
+        for(i=0;i< P;i=i+1) begin :P_
+            assign  ssa_ctrl[i] = {SSA_CTRL_w{1'b0}};
+        end
+    end //ssa
+    always_comb begin
+        for(int k=0;k< P;k++) begin 
+            ssa_flit_wr_all [k] = ssa_ctrl[k].ssa_flit_wr;
+        end//for
+    end
+    `ifdef SIMULATION
+    if(DEBUG_EN && MIN_PCK_SIZE >1 )begin :dbg  
+        wire [PV-1 : 0] non_vsa_ivc_num_getting_ovc_grant_all;
+        integer kk;
+        for(i=0;i< P;i=i+1) begin :p_
+            assign non_vsa_ivc_num_getting_ovc_grant_all [(i+1)*V-1 : i*V] = ssa_ctrl[i].ivc_num_getting_ovc_grant | smart_ctrl_in[i].ivc_num_getting_ovc_grant;                
+        end//for 
+        always @(posedge clk ) begin
+            for(kk=0; kk< PV; kk=kk+1'b1 ) if(reset_ivc_all[kk] & (ivc_num_getting_ovc_grant[kk] | non_vsa_ivc_num_getting_ovc_grant_all[kk])) begin 
+                $display("%t: ERROR: the ovc %d released and allocat signal is asserted in the same clock cycle : %m",$time,kk);
+                $finish;
+            end
+            end
+    end  
+    `endif// SIMULATION
+    endgenerate
 endmodule
 
-
-
-
-
- /******************
- 
-    output_vc_status
- 
- ******************/
- 
- module output_vc_status #(
-    parameter V =  4,
-    parameter B =  16,
+/******************
+*    output_vc_status
+******************/
+module output_vc_status #(
+    parameter PORT_B =  16,
     parameter CAND_VC_SEL_MODE = 0,   // 0: use arbiteration between not full vcs, 1: select the vc with most availble free space
     parameter CRDTw = 4
 )(
- 	credit_init_val_in,
- 	wr_in,
- 	credit_in,
- 	nearly_full_vc,
- 	full_vc,
- 	empty_vc,
- 	cand_vc,
- 	cand_wr_vc_en,
- 	clk,
- 	reset
+    credit_init_val_in,
+    ovc_presence,
+    wr_in,
+    credit_in,
+    nearly_full_vc,
+    full_vc,
+    empty_vc,
+    cand_vc,
+    cand_wr_vc_en,
+    clk,
+    reset
 );
-
-
- 	input   [V-1 : 0] [CRDTw-1 : 0 ] credit_init_val_in ;
- 	input   [V-1 :0] wr_in;
- 	input   [V-1 :0] credit_in;
- 	output  [V-1 :0] nearly_full_vc;
- 	output  [V-1 : 0] full_vc;
- 	output  [V-1 :0] empty_vc;
- 	output  [V-1 :0] cand_vc;
- 	input   cand_wr_vc_en;
- 	input   clk;
- 	input   reset;
- 	
-    
-    function integer log2;
-      input integer number; begin   
-         log2=(number <=1) ? 1: 0;    
-         while(2**log2<number) begin    
-            log2=log2+1;    
-         end 	   
-      end   
-    endfunction // log2 
-    
-  
-    localparam  DEPTH_WIDTH =   log2(B+1);
- 
+    import pronoc_pkg::*;
+    input   [V-1 : 0] [CRDTw-1 : 0 ] credit_init_val_in ;
+    input   [V-1 : 0] ovc_presence;
+    input   [V-1 : 0] wr_in;
+    input   [V-1 : 0] credit_in;
+    output  [V-1 : 0] nearly_full_vc;
+    output  [V-1 : 0] full_vc;
+    output  [V-1 : 0] empty_vc;
+    output  logic [V-1 : 0] cand_vc;
+    input   cand_wr_vc_en;
+    input   clk;
+    input   reset;
+    
+    localparam  DEPTH_WIDTH =   log2(PORT_B+1);
     
     logic  [DEPTH_WIDTH-1 : 0] credit    [V-1 : 0];
     logic  [DEPTH_WIDTH-1 : 0] credit_next    [V-1 : 0];
     wire  [V-1 : 0] cand_vc_next;
-   
     wire  [V-1 :0] request;
     
+    always_comb begin 
+        for(int k=0;k<V;k++) begin
+            credit_next[k] = credit [k];
+            if(  wr_in[k]  && ~credit_in[k])   credit_next[k] = credit[k]-1'b1;
+            if( ~wr_in[k]  &&  credit_in[k])   credit_next[k] = credit[k]+1'b1;
+        end
+    end//always
+    
     genvar i;
     generate
-        for(i=0;i<V;i=i+1) begin : vc_loop
-        	
-        	
-        	      	
-        	
-        	pronoc_register_reset_init #(
-        			.W(DEPTH_WIDTH)			
-        		)reg1( 
-        			.in(credit_next[i]),
-        			.reset(reset),	
-        			.clk(clk),		
-        			.out(credit[i]),
-        			.reset_to(credit_init_val_in[i][DEPTH_WIDTH-1:0])
-        		);
-        		
-      
-
-            always @ ( * )begin 
-                  credit_next[i] = credit [i];
-                  if(  wr_in[i]  && ~credit_in[i])   credit_next[i] = credit[i]-1'b1;
-                  if( ~wr_in[i]  &&  credit_in[i])   credit_next[i] = credit[i]+1'b1;                 
-            end//always
-
-            assign  full_vc[i]   = (credit[i] == {DEPTH_WIDTH{1'b0}});
-            assign  nearly_full_vc[i]=  (credit[i] == 1) |  full_vc[i];
-            assign  empty_vc[i]  = (credit[i] == credit_init_val_in[i][DEPTH_WIDTH-1:0]);
-
-            assign  request[i]   = ~ nearly_full_vc[i] & cand_wr_vc_en;
-  	end//for
-	
+    for(i=0;i<V;i=i+1) begin : vc_loop
+        always_ff @ (`pronoc_clk_reset_edge) begin
+            if (`pronoc_reset) begin
+                credit[i] <= credit_init_val_in[i][DEPTH_WIDTH-1:0];
+            end else begin
+                credit[i] <= credit_next[i];
+            end
+        end
+        assign  full_vc[i]   = (credit[i] == {DEPTH_WIDTH{1'b0}});
+        assign  nearly_full_vc[i]=  (credit[i] == 1) |  full_vc[i];
+        assign  empty_vc[i]  = (credit[i] == credit_init_val_in[i][DEPTH_WIDTH-1:0]);
+        assign  request[i]   = (HETERO_VC>0)?
+                    ~ nearly_full_vc[i] & cand_wr_vc_en & ovc_presence[i]:
+                    ~ nearly_full_vc[i] & cand_wr_vc_en;
+    end//for
     endgenerate
-        		
-
-            arbiter #(
-                .ARBITER_WIDTH      (V)
-                )
-                the_nic_arbiter
-                (
-                    .clk                (clk),
-                    .reset          (reset),
-                    .request            (request),
-                    .grant          (cand_vc_next),
-                    .any_grant       ()
-                );
-
-    logic [V-1 : 0] cand_vc_ld_next;  
-	pronoc_register #(.W(V)) reg2 (.in(cand_vc_ld_next ), .out(cand_vc), .reset(reset), .clk(clk));
-            
-	always  @ ( *) begin 
-		cand_vc_ld_next = cand_vc;
-		if(cand_wr_vc_en)    cand_vc_ld_next  =  cand_vc_next;
+    
+    arbiter #(
+        .ARBITER_WIDTH (V)
+    ) the_nic_arbiter (
+        .clk (clk),
+        .reset (reset),
+        .request (request),
+        .grant (cand_vc_next),
+        .any_grant()
+    );
+    
+    logic [V-1 : 0] cand_vc_ld_next;
+    always_ff @ (`pronoc_clk_reset_edge) begin
+        if (`pronoc_reset) begin
+            cand_vc <= '0;
+        end else begin
+            cand_vc <= cand_vc_ld_next;
+        end
+    end
+    always_comb begin 
+        cand_vc_ld_next = cand_vc;
+        if(cand_wr_vc_en) cand_vc_ld_next  =  cand_vc_next;
+        // For Depth-First, only inject on VC0 (Z-)
+        if (IS_MULTI_MESH) cand_vc_ld_next = 'd1;
     end
-
 endmodule
 
 
 /*************************
-    vc_alloc_request_gen
-
+*    vc_alloc_request_gen
 ************************/
-
-
 module  vc_alloc_request_gen #(
-    parameter NOC_ID=0,
     parameter P=5
 ) (
-	ivc_info,
-	ovc_avalable_all,
+    ivc_info,
+    ovc_avalable_all,
     dest_port_decoded_all,
     masked_ovc_request_all,    
     port_pre_sel,
@@ -490,152 +420,71 @@ module  vc_alloc_request_gen #(
     destport_clear,
     ivc_num_getting_ovc_grant, 
     smart_ctrl_in,
-    ssa_ctrl_in
+    ssa_ctrl_in,
+    ctrl_in
 );
-	
-	`NOC_CONF
-
-    localparam  P_1     = (SELF_LOOP_EN == "NO")?  P-1 : P,
-    			PV      =   V       *   P,
-                PVV     =   PV      *  V,
-                PVP_1   =   PV      *   P_1,
-                PVDSTPw= PV * DSTPw;
-
     
+    import pronoc_pkg::*;
+    
+    localparam  
+        P_1 = (SELF_LOOP_EN )?  P : P-1,
+        PV      =   V       *   P,
+        PVV     =   PV      *  V,
+        PVP_1   =   PV      *   P_1,
+        PVDSTPw= PV * DSTPw;
     
     input   [PV-1       :   0]  ovc_avalable_all;
     input   [PVP_1-1    :   0]  dest_port_decoded_all;   
     output  [PVV-1      :   0]  masked_ovc_request_all;
-      
+    
     input   [PPSw-1 : 0] port_pre_sel;
     output  [PV-1   : 0] sel;
     output  [PV-1   : 0] swap_port_presel;
     input   reset;
     input   clk;
-    output  [DSTPw-1 : 0] destport_clear [P-1 : 0][V-1 : 0];   
+    output  [DSTPw-1 : 0] destport_clear [P-1 : 0][V-1 : 0];
     
     input   [PV-1 : 0] ivc_num_getting_ovc_grant; 
     input   ssa_ctrl_t  ssa_ctrl_in [P-1: 0];
     input   smart_ctrl_t  smart_ctrl_in [P-1: 0];
     input   ivc_info_t   ivc_info    [P-1 : 0][V-1 : 0];
+    input   ctrl_chanel_t ctrl_in  [P-1 : 0];
     
     wire   [PV-1       :   0]  ivc_request_all;
     wire   [PVDSTPw-1  :   0]  dest_port_encoded_all;
     wire   [PVV-1      :   0]  candidate_ovc_all; 
     wire   [PV-1       :   0]  ovc_is_assigned_all;
-   
-    wire [PV-1 : 0] ovc_avalable_all_masked;
+    
+    wire [PV-1 : 0] ovc_avalable_all_masked,hetero_ovc_peresence_all;
     wire [PV-1 : 0] non_vsa_ivc_num_getting_ovc_grant_all;   
     wire [PVDSTPw-1 : 0] destport_clear_all;
     
     genvar i,j;
-    generate 
+    generate
     
     for(i=0;i< P;i=i+1) begin :p_
-		assign ovc_avalable_all_masked [(i+1)*V-1 : i*V] = (SMART_EN)?  ovc_avalable_all [(i+1)*V-1 : i*V] & ~smart_ctrl_in[i].mask_available_ovc : ovc_avalable_all [(i+1)*V-1 : i*V];
-    	assign non_vsa_ivc_num_getting_ovc_grant_all [(i+1)*V-1 : i*V] = ssa_ctrl_in[i].ivc_num_getting_ovc_grant | smart_ctrl_in[i].ivc_num_getting_ovc_grant;
-    	for(j=0;j< V;j=j+1) begin :V_
-    		assign ivc_request_all[i*V+j] = ivc_info[i][j].ivc_req;
-    		assign ovc_is_assigned_all[i*V+j] = ivc_info[i][j].ovc_is_assigned;                  
-    		assign dest_port_encoded_all [(i*V+j+1)*DSTPw-1  :  (i*V+j)*DSTPw]=ivc_info[i][j].dest_port_encoded;
-    		assign candidate_ovc_all[(i*V+j+1)*V-1  :  (i*V+j)*V]= ivc_info[i][j].candidate_ovc;
-    		assign destport_clear [i][j]=destport_clear_all [(i*V+j+1)*DSTPw-1  :  (i*V+j)*DSTPw];
-    	end    	
-    end//for
-    
-    	
+        assign hetero_ovc_peresence_all [(i+1)*V-1 : i*V] = (HETERO_VC >0 )?  ctrl_in[i].hetero_ovc_presence : {V{1'b1}};
+        assign ovc_avalable_all_masked [(i+1)*V-1 : i*V] = (SMART_EN)? 
+            //TODO for smart, we need to make sure, the hetrro ovc presence in all down stream routers 
+            ovc_avalable_all [(i+1)*V-1 : i*V] & ~smart_ctrl_in[i].mask_available_ovc & hetero_ovc_peresence_all[(i+1)*V-1 : i*V] : 
+            ovc_avalable_all [(i+1)*V-1 : i*V] & hetero_ovc_peresence_all[(i+1)*V-1 : i*V];
+        assign non_vsa_ivc_num_getting_ovc_grant_all [(i+1)*V-1 : i*V] = ssa_ctrl_in[i].ivc_num_getting_ovc_grant | smart_ctrl_in[i].ivc_num_getting_ovc_grant;
+        for(j=0;j< V;j=j+1) begin :V_
+            assign ivc_request_all[i*V+j] = ivc_info[i][j].ivc_req;
+            assign ovc_is_assigned_all[i*V+j] = ivc_info[i][j].ovc_is_assigned;                  
+            assign dest_port_encoded_all [(i*V+j+1)*DSTPw-1  :  (i*V+j)*DSTPw]=ivc_info[i][j].dest_port_encoded;
+            assign candidate_ovc_all[(i*V+j+1)*V-1  :  (i*V+j)*V]= ivc_info[i][j].candidate_ovc;
+            assign destport_clear [i][j]=destport_clear_all [(i*V+j+1)*DSTPw-1  :  (i*V+j)*DSTPw];
+        end        
+    end//for    
     
     /* verilator lint_off WIDTH */
     if(ROUTE_TYPE == "DETERMINISTIC") begin : dtrmn
-    /* verilator lint_on WIDTH */          
-                          
-        vc_alloc_request_gen_determinstic #(
-        	.P(P),
-        	.V(V),
-        	.SELF_LOOP_EN(SELF_LOOP_EN),
-        	.CAST_TYPE(CAST_TYPE)
-        )
-        vc_request_gen
-        (
-        	.ovc_avalable_all(ovc_avalable_all_masked),
-        	.ivc_request_all(ivc_request_all),
-        	.ovc_is_assigned_all(ovc_is_assigned_all),
-        	.dest_port_in_all(dest_port_decoded_all),
-        	.masked_ovc_request_all(masked_ovc_request_all),
-        	.candidate_ovc_all(candidate_ovc_all)
-        );
+    /* verilator lint_on WIDTH */
         
-        assign swap_port_presel = {PV{1'bx}};
-        assign destport_clear_all={PVDSTPw{1'b0}};
-        assign sel = {PV{1'bx}};
-    
-    end else begin: adptv     
-      
-      if(P==5 && SELF_LOOP_EN == "NO" )begin:sl_mesh // combine portsel and available VC mux as proposed in ProNoC paper
-      
-      mesh_torus_vc_alloc_request_gen_adaptive #(
-       	.ROUTE_TYPE(ROUTE_TYPE),
-      	.V(V),
-      	.DSTPw(DSTPw),
-      	.SSA_EN(SSA_EN),
-      	.ESCAP_VC_MASK(ESCAP_VC_MASK),
-      	.PPSw(PPSw)      	
-      )
-      vc_alloc_request_gen
-      (
-      	.ovc_avalable_all(ovc_avalable_all_masked),
-      	.dest_port_coded_all(dest_port_encoded_all),
-      	.ivc_request_all(ivc_request_all),
-      	.ovc_is_assigned_all(ovc_is_assigned_all),
-      	.masked_ovc_request_all(masked_ovc_request_all),
-      	.candidate_ovc_all(candidate_ovc_all),
-      	.port_pre_sel(port_pre_sel),
-      	.swap_port_presel(swap_port_presel),
-      	.sel(sel),
-      	.destport_clear_all(destport_clear_all),
-      	.ivc_num_getting_ovc_grant(ivc_num_getting_ovc_grant),
-      	.ssa_ivc_num_getting_ovc_grant_all(non_vsa_ivc_num_getting_ovc_grant_all),
-      	.reset(reset),
-      	.clk(clk)
-      ); 
-      
-      end else begin :ml_mesh // there are several local ports connected to one router or self loop is enabled 
-      //select the port first then select the available vc
-        
-                
-        
-         mesh_torus_dynamic_portsel_control #(
-         	.P(P),
-         	.ROUTE_TYPE(ROUTE_TYPE),
-         	.V(V),
-         	.DSTPw(DSTPw),
-         	.SSA_EN(SSA_EN),
-         	.PPSw(PPSw),
-         	.ESCAP_VC_MASK(ESCAP_VC_MASK)
-         )
-         dynamic_portsel_control
-         (
-         	.dest_port_coded_all(dest_port_encoded_all),
-         	.ivc_request_all(ivc_request_all),
-         	.ovc_is_assigned_all(ovc_is_assigned_all),
-         	.port_pre_sel(port_pre_sel),
-         	.swap_port_presel(swap_port_presel),
-         	.masked_ovc_request_all(masked_ovc_request_all),
-         	.sel(sel),
-         	.destport_clear_all(destport_clear_all),
-         	.ivc_num_getting_ovc_grant(ivc_num_getting_ovc_grant),
-         	.ssa_ivc_num_getting_ovc_grant_all(non_vsa_ivc_num_getting_ovc_grant_all),
-         	.reset(reset),
-         	.clk(clk)
-         );
-         
         vc_alloc_request_gen_determinstic #(
-            .P(P),
-            .V(V),
-            .SELF_LOOP_EN(SELF_LOOP_EN)
-        )
-        vc_request_gen
-        (
+            .P(P)
+        ) vc_request_gen (
             .ovc_avalable_all(ovc_avalable_all_masked),
             .ivc_request_all(ivc_request_all),
             .ovc_is_assigned_all(ovc_is_assigned_all),
@@ -643,22 +492,73 @@ module  vc_alloc_request_gen #(
             .masked_ovc_request_all(masked_ovc_request_all),
             .candidate_ovc_all(candidate_ovc_all)
         );
-                 
-      
-      end      
-    
+        
+        assign swap_port_presel = {PV{1'b0}};
+        assign destport_clear_all={PVDSTPw{1'b0}};
+        assign sel = {PV{1'b0}};
+        
+    end else begin: adptv
+        
+        if(P==5 && SELF_LOOP_EN == 0 )begin : sl_mesh // combine portsel and available VC mux as proposed in ProNoC paper
+            
+            regular_topo_vc_alloc_request_gen_adaptive  vc_alloc_request_gen (
+                .ovc_avalable_all(ovc_avalable_all_masked),
+                .dest_port_coded_all(dest_port_encoded_all),
+                .ivc_request_all(ivc_request_all),
+                .ovc_is_assigned_all(ovc_is_assigned_all),
+                .masked_ovc_request_all(masked_ovc_request_all),
+                .candidate_ovc_all(candidate_ovc_all),
+                .port_pre_sel(port_pre_sel),
+                .swap_port_presel(swap_port_presel),
+                .sel(sel),
+                .destport_clear_all(destport_clear_all),
+                .ivc_num_getting_ovc_grant(ivc_num_getting_ovc_grant),
+                .ssa_ivc_num_getting_ovc_grant_all(non_vsa_ivc_num_getting_ovc_grant_all),
+                .reset(reset),
+                .clk(clk)
+            ); 
+            
+        end else begin :ml_mesh 
+          // there are several local ports connected to one router or self loop is enabled 
+          //select the port first then select the available vc
+            
+            regular_topo_dynamic_portsel_control #(
+                .P(P)
+            ) dynamic_portsel_control (
+                .dest_port_coded_all(dest_port_encoded_all),
+                .ivc_request_all(ivc_request_all),
+                .ovc_is_assigned_all(ovc_is_assigned_all),
+                .port_pre_sel(port_pre_sel),
+                .swap_port_presel(swap_port_presel),
+                .masked_ovc_request_all(masked_ovc_request_all),
+                .sel(sel),
+                .destport_clear_all(destport_clear_all),
+                .ivc_num_getting_ovc_grant(ivc_num_getting_ovc_grant),
+                .ssa_ivc_num_getting_ovc_grant_all(non_vsa_ivc_num_getting_ovc_grant_all),
+                .reset(reset),
+                .clk(clk)
+            );
+            
+            vc_alloc_request_gen_determinstic #(
+                .P(P)
+            ) vc_request_gen (
+                .ovc_avalable_all(ovc_avalable_all_masked),
+                .ivc_request_all(ivc_request_all),
+                .ovc_is_assigned_all(ovc_is_assigned_all),
+                .dest_port_in_all(dest_port_decoded_all),
+                .masked_ovc_request_all(masked_ovc_request_all),
+                .candidate_ovc_all(candidate_ovc_all)
+            );
+            
+        end//  l_mesh   
     end
     endgenerate
-
+    
 endmodule
 
 
-module  vc_alloc_request_gen_determinstic #(    
-    parameter P = 5,
-    parameter V = 4,
-    parameter SELF_LOOP_EN="NO",
-    parameter CAST_TYPE = "UNICAST" 
-    
+module  vc_alloc_request_gen_determinstic #(
+    parameter P = 5
 )(
     ovc_avalable_all,
     candidate_ovc_all,
@@ -667,13 +567,14 @@ module  vc_alloc_request_gen_determinstic #(
     dest_port_in_all,
     masked_ovc_request_all
 );
-
- 	localparam  P_1     =  (SELF_LOOP_EN == "NO")?  P-1 : P,
-                PV      =   V       *   P,
-                PVV     =   PV      *   V,
-                PVP_1   =   PV      *   P_1,
-                VP_1    =   V       *   P_1;             
-
+    import pronoc_pkg::*;
+    localparam  
+        P_1 = (SELF_LOOP_EN )?  P : P-1,
+        PV = V * P,
+        PVV = PV * V,
+        PVP_1 = PV * P_1,
+        VP_1 = V * P_1;
+    
     input   [PV-1       :   0]  ovc_avalable_all;
     input   [PV-1       :   0]  ivc_request_all;
     input   [PV-1       :   0]  ovc_is_assigned_all;
@@ -683,55 +584,49 @@ module  vc_alloc_request_gen_determinstic #(
     
     wire    [PV-1       :   0]  non_assigned_ovc_request_all; 
     wire    [VP_1-1     :   0]  ovc_avalable_perport        [P-1    :   0];
-    wire    [VP_1-1     :   0]  ovc_avalable_ivc            [PV-1   :   0];
+    wire    [V-1        :   0]  ovc_avalable_ivc [PV-1 : 0] [P_1-1:0];
     wire    [P_1-1      :   0]  dest_port_ivc               [PV-1   :   0];
-    wire    [V-1        :   0]  ovc_avb_muxed               [PV-1   :   0];  
+    logic   [V-1        :   0]  ovc_avb_muxed               [PV-1   :   0];  
     wire    [V-1        :   0]  ovc_request_ivc             [PV-1   :   0];
- 
+    
     assign non_assigned_ovc_request_all =   ivc_request_all & ~ovc_is_assigned_all;
-   
     
-  genvar i;
-
-generate
-	if(SELF_LOOP_EN == "NO" ) begin :nslp
-		//remove available ovc of receiver port 
-		for(i=0;i< P;i=i+1) begin :port_loop
-	        if(i==0) begin : first assign ovc_avalable_perport[i]=ovc_avalable_all [PV-1              :   V]; end
-	        else if(i==(P-1)) begin : last assign ovc_avalable_perport[i]=ovc_avalable_all [PV-V-1               :   0]; end
-	        else  begin : midle  assign ovc_avalable_perport[i]={ovc_avalable_all [PV-1  :   (i+1)*V],ovc_avalable_all [(i*V)-1  :   0]}; end
-	    end
+    genvar i,j;
+    generate
+    if(SELF_LOOP_EN == 0 ) begin :nslp
+        //remove available ovc of receiver port 
+        for(i=0;i< P;i=i+1) begin :port_loop
+            if(i==0) begin : first assign ovc_avalable_perport[i]=ovc_avalable_all [PV-1              :   V]; end
+            else if(i==(P-1)) begin : last assign ovc_avalable_perport[i]=ovc_avalable_all [PV-V-1               :   0]; end
+            else  begin : midle  assign ovc_avalable_perport[i]={ovc_avalable_all [PV-1  :   (i+1)*V],ovc_avalable_all [(i*V)-1  :   0]}; end
+        end
     end else begin :slp
-    	for(i=0;i< P;i=i+1) begin :port_loop
-    		 assign ovc_avalable_perport[i]=ovc_avalable_all;
-	    end
+        for(i=0;i< P;i=i+1) begin :port_loop
+            assign ovc_avalable_perport[i]=ovc_avalable_all;
+        end
     end
+    
+    //Onehot mux to select available ovc
+    always_comb begin
+        for(int m=0;m< PV;m++) begin 
+            ovc_avb_muxed[m] = '0;
+            for (int k = 0; k < P_1; k++) begin
+                ovc_avb_muxed[m] |= (dest_port_ivc[m][k]) ?  ovc_avalable_ivc [m][k] :  '0;
+            end
+        end
+    end//always
     // IVC loop
-    for(i=0;i< PV;i=i+1) begin :total_vc_loop
+    for(i=0;i< PV;i=i+1) begin :PV_
         //separate input/output
-        assign ovc_avalable_ivc[i]  =   ovc_avalable_perport[(i/V)];
+        //assign ovc_avalable_ivc[i]  =   ovc_avalable_perport[(i/V)];
         assign dest_port_ivc   [i]  =   dest_port_in_all [(i+1)*P_1-1  :   i*P_1   ];
         assign ovc_request_ivc [i]  = (non_assigned_ovc_request_all[i])? candidate_ovc_all  [(i+1)*V-1  :   i*V ]: {V{1'b0}};          
-       
-        //available ovc multiplexer
-        onehot_mux_1D #(
-            .W       (V),
-            .N      (P_1)
-        )
-        multiplexer
-        (
-            .in     (ovc_avalable_ivc   [i]),
-            .out    (ovc_avb_muxed      [i]),
-            .sel    (dest_port_ivc      [i])
-
-        );  
+        for(j=0;j< P_1;j=j+1) begin :V_
+            assign ovc_avalable_ivc[i][j] = ovc_avalable_perport[i / V][j*V +: V];
+        end//for       
         
         // mask unavailable ovc from requests
-        assign masked_ovc_request_all  [(i+1)*V-1   :   i*V ]     =   ovc_avb_muxed[i] & ovc_request_ivc [i];
-        
+        assign masked_ovc_request_all  [(i+1)*V-1 : i*V ] = ovc_avb_muxed[i] & ovc_request_ivc [i];
     end
-   endgenerate
+    endgenerate
 endmodule
-
-
- 
diff --git a/mpsoc/rtl/src_noc/input_ports.sv b/mpsoc/rtl/src_noc/input_ports.sv
index 536417c..0c81d1e 100755
--- a/mpsoc/rtl/src_noc/input_ports.sv
+++ b/mpsoc/rtl/src_noc/input_ports.sv
@@ -2,1409 +2,1040 @@
 //`define MONITORE_PATH
 
 /**********************************************************************
- **	File: input_ports.sv
+ **    File: input_ports.sv
  **    
- **	Copyright (C) 2014-2017  Alireza Monemi
+ **    Copyright (C) 2014-2017  Alireza Monemi
  **    
- **	This file is part of ProNoC 
+ **    This file is part of ProNoC 
  **
- **	ProNoC ( stands for Prototype Network-on-chip)  is free software: 
- **	you can redistribute it and/or modify it under the terms of the GNU
- **	Lesser General Public License as published by the Free Software Foundation,
- **	either version 2 of the License, or (at your option) any later version.
+ **    ProNoC ( stands for Prototype Network-on-chip)  is free software: 
+ **    you can redistribute it and/or modify it under the terms of the GNU
+ **    Lesser General Public License as published by the Free Software Foundation,
+ **    either version 2 of the License, or (at your option) any later version.
  **
- ** 	ProNoC is distributed in the hope that it will be useful, but WITHOUT
- ** 	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
- ** 	or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
- ** 	Public License for more details.
+ **     ProNoC is distributed in the hope that it will be useful, but WITHOUT
+ **     ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ **     or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
+ **     Public License for more details.
  **
- ** 	You should have received a copy of the GNU Lesser General Public
- ** 	License along with ProNoC. If not, see <http:**www.gnu.org/licenses/>.
+ **     You should have received a copy of the GNU Lesser General Public
+ **     License along with ProNoC. If not, see <http:**www.gnu.org/licenses/>.
  **
  **
- **	Description: 
- **	NoC router input Port. It consists of input buffer, control FIFO 
- **	and request masking/generation control modules
+ **    Description: 
+ **    NoC router input Port. It consists of input buffer, control FIFO 
+ **    and request masking/generation control modules
  **
  **************************************************************/
-
+    
 module input_ports #(
-	parameter NOC_ID=0,
-	parameter P=5
-) (
-	current_r_addr,
-	neighbors_r_addr,
-	ivc_num_getting_sw_grant,// for non spec ivc_num_getting_first_sw_grant,
-	any_ivc_sw_request_granted_all,
-	flit_in_all,
-	flit_in_wr_all,
-	reset_ivc_all,
-	flit_is_tail_all,
-	ivc_request_all,
-	dest_port_all,			
-	flit_out_all,
-	
-	assigned_ovc_not_full_all,
-	ovc_is_assigned_all,
-	sel,
-	port_pre_sel,
-	swap_port_presel,
-	nonspec_first_arbiter_granted_ivc_all,
-	credit_out_all,
-	
-	destport_clear,
-	vc_weight_is_consumed_all,
-	iport_weight_is_consumed_all,
-	iport_weight_all,
-	oports_weight_all,
-	granted_dest_port_all,
-	refresh_w_counter,
-	ivc_info,
-	vsa_ctrl_in,
-	ssa_ctrl_in,
-	smart_ctrl_in,
-	credit_init_val_out,
-	reset,
-	clk
+    parameter ROUTER_ID=0,
+    parameter P=5
+)(
+    router_info,
+    ivc_num_getting_sw_grant,// for non spec ivc_num_getting_first_sw_grant,
+    any_ivc_sw_request_granted_all,
+    flit_in_all,
+    flit_in_wr_all,
+    reset_ivc_all,
+    flit_is_tail_all,
+    ivc_request_all,
+    dest_port_all,
+    flit_out_all,
+    
+    assigned_ovc_not_full_all,
+    ovc_is_assigned_all,
+    sel,
+    port_pre_sel,
+    swap_port_presel,
+    nonspec_first_arbiter_granted_ivc_all,
+    credit_out_all,
+    
+    destport_clear,
+    vc_weight_is_consumed_all,
+    iport_weight_is_consumed_all,
+    iport_weight_all,
+    oports_weight_all,
+    granted_dest_port_all,
+    refresh_w_counter,
+    ivc_info,
+    vsa_ctrl_in,
+    ssa_ctrl_in,
+    smart_ctrl_in,
+    credit_init_val_out,
+    ctrl_in,
+    reset,
+    clk
 );  
-   
-	`NOC_CONF    
-     
-	localparam
-		PV = V * P,
-		VV = V * V,
-		PVV = PV * V,    
-		P_1 = ( SELF_LOOP_EN=="NO")?  P-1 : P,
-		PP_1 = P * P_1, 
-		VP_1 = V * P_1,
-		PVP_1 = PV * P_1,
-		PFw = P*Fw,
-		W= WEIGHTw,
-		WP= W * P,
-		WPP = WP * P,
-		PVDSTPw= PV * DSTPw,
-		PRAw= P * RAw;	
-       
-        
-	input   reset,clk;
-	input   [RAw-1 : 0] current_r_addr;
-	input   [PRAw-1:  0]  neighbors_r_addr;
-	output  [PV-1 : 0] ivc_num_getting_sw_grant;
-	input   [P-1 : 0] any_ivc_sw_request_granted_all;
-	input   [PFw-1 : 0] flit_in_all;
-	input   [P-1 : 0] flit_in_wr_all;
-	output  [PV-1 : 0] reset_ivc_all;
-	output  [PV-1 : 0] flit_is_tail_all;
-	output  [PV-1 : 0] ivc_request_all;
-	output  [PV-1 : 0] credit_out_all;
-	
-	output  [PVP_1-1 : 0] dest_port_all;
-	output  [PFw-1 : 0] flit_out_all;
-	
-	input   [PV-1  : 0] assigned_ovc_not_full_all;
-	output  [PV-1  : 0] ovc_is_assigned_all;
-	input   [PV-1 : 0] sel;
-	input   [PPSw-1 : 0] port_pre_sel;
-	input   [PV-1  : 0]  swap_port_presel;
-	input   [PV-1 : 0] nonspec_first_arbiter_granted_ivc_all;	
-	
-	output  [WP-1 : 0] iport_weight_all;
-	output  [PV-1 : 0] vc_weight_is_consumed_all;
-	output  [P-1 : 0] iport_weight_is_consumed_all;
-	input   [PP_1-1 : 0] granted_dest_port_all;
-	output  [WPP-1 : 0] oports_weight_all;	
-
-	output  ivc_info_t ivc_info [P-1 : 0][V-1 : 0]; 
-	input   vsa_ctrl_t  vsa_ctrl_in [P-1: 0];
-	input   ssa_ctrl_t  ssa_ctrl_in [P-1: 0];
-	input   smart_ctrl_t  smart_ctrl_in [P-1 : 0];
-	output  [CRDTw-1 : 0 ] credit_init_val_out [P-1 : 0][V-1 : 0];
-	
-	input refresh_w_counter;
+    import pronoc_pkg::*;
+    localparam
+        PV = V * P,
+        P_1 = (SELF_LOOP_EN )?  P : P-1,
+        PP_1 = P * P_1, 
+        PVP_1 = PV * P_1,
+        PFw = P*Fw,
+        W= WEIGHTw,
+        WP= W * P,
+        WPP = WP * P;
     
-	input   [DSTPw-1 : 0] destport_clear [P-1 : 0][V-1 : 0];   
-
-	genvar i;
-	generate 
-		for(i=0;i<P;i=i+1)begin : Port_ 			
+    input   reset,clk;
+    input   router_info_t router_info;
+    output  [PV-1 : 0] ivc_num_getting_sw_grant;
+    input   [P-1 : 0] any_ivc_sw_request_granted_all;
+    input   flit_t flit_in_all [P-1 : 0];
+    input   [P-1 : 0] flit_in_wr_all;
+    output  [PV-1 : 0] reset_ivc_all;
+    output  [PV-1 : 0] flit_is_tail_all;
+    output  [PV-1 : 0] ivc_request_all;
+    output  [PV-1 : 0] credit_out_all;
+    output  [PVP_1-1 : 0] dest_port_all;
+    output  flit_t flit_out_all [P-1 : 0];
+    input   [PV-1  : 0] assigned_ovc_not_full_all;
+    output  [PV-1  : 0] ovc_is_assigned_all;
+    input   [PV-1 : 0] sel;
+    input   [PPSw-1 : 0] port_pre_sel;
+    input   [PV-1  : 0]  swap_port_presel;
+    input   [PV-1 : 0] nonspec_first_arbiter_granted_ivc_all;    
+    output  [WP-1 : 0] iport_weight_all;
+    output  [PV-1 : 0] vc_weight_is_consumed_all;
+    output  [P-1 : 0] iport_weight_is_consumed_all;
+    input   [PP_1-1 : 0] granted_dest_port_all;
+    output  [WPP-1 : 0] oports_weight_all;    
+    output  ivc_info_t ivc_info [P-1 : 0][V-1 : 0]; 
+    input   vsa_ctrl_t  vsa_ctrl_in [P-1: 0];
+    input   ssa_ctrl_t  ssa_ctrl_in [P-1: 0];
+    input   smart_ctrl_t  smart_ctrl_in [P-1 : 0];
+    output  [CRDTw-1 : 0 ] credit_init_val_out [P-1 : 0][V-1 : 0];
     
-			input_queue_per_port
-			// iport_reg_base
-			#(
-				.NOC_ID(NOC_ID),
-				.SW_LOC(i),
-				.P(P)   	
-			) the_input_queue_per_port 	(
-				.credit_out(credit_out_all [(i+1)*V-1 : i*V]),
-				.current_r_addr(current_r_addr),    
-				.neighbors_r_addr(neighbors_r_addr),
-				.ivc_num_getting_sw_grant(ivc_num_getting_sw_grant  [(i+1)*V-1 : i*V]),// for non spec ivc_num_getting_first_sw_grant,
-				.any_ivc_sw_request_granted(any_ivc_sw_request_granted_all  [i]),    
-				.flit_in(flit_in_all[(i+1)*Fw-1 : i*Fw]),
-				.flit_in_wr(flit_in_wr_all[i]),
-				.reset_ivc(reset_ivc_all [(i+1)*V-1 : i*V]),
-				.flit_is_tail(flit_is_tail_all  [(i+1)*V-1 : i*V]),
-				.ivc_request(ivc_request_all [(i+1)*V-1 : i*V]),    
-				.dest_port(dest_port_all [(i+1)*P_1*V-1 : i*P_1*V]),
-				.flit_out(flit_out_all [(i+1)*Fw-1 : i*Fw]),
-				.assigned_ovc_not_full(assigned_ovc_not_full_all [(i+1)*V-1 : i*V]), 
-				.ovc_is_assigned(ovc_is_assigned_all [(i+1)*V-1 : i*V]), 
-				.sel(sel [(i+1)*V-1 : i*V]),
-				.port_pre_sel(port_pre_sel),
-				.swap_port_presel(swap_port_presel[(i+1)*V-1 : i*V]),
-				.nonspec_first_arbiter_granted_ivc(nonspec_first_arbiter_granted_ivc_all[(i+1)*V-1 : i*V]),
-				.reset(reset),
-				.clk(clk),
-				
-				.destport_clear(destport_clear [i]),
-				.iport_weight(iport_weight_all[(i+1)*W-1 : i*W]),
-				.oports_weight(oports_weight_all[(i+1)*WP-1 : i*WP]),
-				.vc_weight_is_consumed(vc_weight_is_consumed_all [(i+1)*V-1 : i*V]),
-				.iport_weight_is_consumed(iport_weight_is_consumed_all[i]),
-				.refresh_w_counter(refresh_w_counter),
-				.granted_dest_port(granted_dest_port_all[(i+1)*P_1-1 : i*P_1]),
-				.ivc_info(ivc_info[i]),
-				.vsa_ctrl_in(vsa_ctrl_in [i]),
-				.smart_ctrl_in(smart_ctrl_in [i]),
-				.ssa_ctrl_in(ssa_ctrl_in [i]),
-				.credit_init_val_out(credit_init_val_out[i])
-			);
+    input refresh_w_counter;
     
-		end//for      
-	endgenerate
-
+    input   [DSTPw-1 : 0] destport_clear [P-1 : 0][V-1 : 0];
+    input   ctrl_chanel_t ctrl_in  [P-1 : 0];
+    
+    genvar i;
+    generate 
+    for(i=0;i<P;i=i+1)begin : Port_
+        
+        input_queue_per_port
+        // iport_reg_base
+        #(
+            .ROUTER_ID(ROUTER_ID),
+            .SW_LOC(i),
+            .P(P)
+        ) the_input_queue_per_port (
+            .router_info(router_info),
+            .credit_out(credit_out_all [(i+1)*V-1 : i*V]),
+            .ivc_num_getting_sw_grant(ivc_num_getting_sw_grant  [(i+1)*V-1 : i*V]),// for non spec ivc_num_getting_first_sw_grant,
+            .any_ivc_sw_request_granted(any_ivc_sw_request_granted_all  [i]),
+            .flit_in(flit_in_all[i]),
+            .flit_in_wr(flit_in_wr_all[i]),
+            .reset_ivc(reset_ivc_all [(i+1)*V-1 : i*V]),
+            .flit_is_tail(flit_is_tail_all  [(i+1)*V-1 : i*V]),
+            .ivc_request(ivc_request_all [(i+1)*V-1 : i*V]),    
+            .dest_port(dest_port_all [(i+1)*P_1*V-1 : i*P_1*V]),
+            .flit_out(flit_out_all [i]),
+            .assigned_ovc_not_full(assigned_ovc_not_full_all [(i+1)*V-1 : i*V]), 
+            .ovc_is_assigned(ovc_is_assigned_all [(i+1)*V-1 : i*V]), 
+            .sel(sel [(i+1)*V-1 : i*V]),
+            .port_pre_sel(port_pre_sel),
+            .swap_port_presel(swap_port_presel[(i+1)*V-1 : i*V]),
+            .nonspec_first_arbiter_granted_ivc(nonspec_first_arbiter_granted_ivc_all[(i+1)*V-1 : i*V]),
+            .reset(reset),
+            .clk(clk),
+            .destport_clear(destport_clear [i]),
+            .iport_weight(iport_weight_all[(i+1)*W-1 : i*W]),
+            .oports_weight(oports_weight_all[(i+1)*WP-1 : i*WP]),
+            .vc_weight_is_consumed(vc_weight_is_consumed_all [(i+1)*V-1 : i*V]),
+            .iport_weight_is_consumed(iport_weight_is_consumed_all[i]),
+            .refresh_w_counter(refresh_w_counter),
+            .granted_dest_port(granted_dest_port_all[(i+1)*P_1-1 : i*P_1]),
+            .ivc_info(ivc_info[i]),
+            .vsa_ctrl_in(vsa_ctrl_in [i]),
+            .smart_ctrl_in(smart_ctrl_in [i]),
+            .ssa_ctrl_in(ssa_ctrl_in [i]),
+            .credit_init_val_out(credit_init_val_out[i]),
+            .ctrl_in(ctrl_in)
+        );
+    end//for
+    endgenerate
 endmodule 
 
 
 /**************************
-
-    input_queue_per_port
-
- **************************/
-
+*    input_queue_per_port
+**************************/
 module input_queue_per_port #(
-	parameter NOC_ID=0,
-	parameter P = 5,     // router port num
-	parameter SW_LOC = 0
+    parameter ROUTER_ID=0,
+    parameter P = 5,     // router port num
+    parameter SW_LOC = 0
 ) (
-	current_r_addr,
-	credit_out,
-	neighbors_r_addr,
-	ivc_num_getting_sw_grant,// for non spec ivc_num_getting_first_sw_grant,
-	any_ivc_sw_request_granted,
-	flit_in,
-	flit_in_wr,
-	reset_ivc,
-	flit_is_tail,
-	ivc_request,
-	dest_port,
-	flit_out,			
-	assigned_ovc_not_full,
-	ovc_is_assigned,
-	sel,
-	port_pre_sel,
-	swap_port_presel,
-	reset,
-	clk,
-	nonspec_first_arbiter_granted_ivc,
-	destport_clear,
-		
-	iport_weight,
-	oports_weight,  
-	vc_weight_is_consumed,
-	iport_weight_is_consumed,
-	refresh_w_counter,
-	granted_dest_port,
-	ivc_info,
-	smart_ctrl_in,
-	vsa_ctrl_in,
-	ssa_ctrl_in,
-	credit_init_val_out
+    router_info,
+    credit_out,
+    ivc_num_getting_sw_grant,// for non spec ivc_num_getting_first_sw_grant,
+    any_ivc_sw_request_granted,
+    flit_in,
+    flit_in_wr,
+    reset_ivc,
+    flit_is_tail,
+    ivc_request,
+    dest_port,
+    flit_out,
+    assigned_ovc_not_full,
+    ovc_is_assigned,
+    sel,
+    port_pre_sel,
+    swap_port_presel,
+    reset,
+    clk,
+    nonspec_first_arbiter_granted_ivc,
+    destport_clear,
+    iport_weight,
+    oports_weight,
+    vc_weight_is_consumed,
+    iport_weight_is_consumed,
+    refresh_w_counter,
+    granted_dest_port,
+    ivc_info,
+    smart_ctrl_in,
+    vsa_ctrl_in,
+    ssa_ctrl_in,
+    credit_init_val_out,
+    ctrl_in
 );
- 	
-	`NOC_CONF
-		
-	localparam 
-		PORT_B = port_buffer_size(SW_LOC),
-		PORT_Bw= log2(PORT_B);	
-	   
-	localparam
-		VV = V * V,
-		VDSTPw = V * DSTPw,		
-		W = WEIGHTw,
-		WP = W * P,
-		P_1=( SELF_LOOP_EN=="NO")?  P-1 : P,
-		VP_1 = V * P_1;    
-
-	localparam
-	/* verilator lint_off WIDTH */
-		OFFSET = (PORT_B%MIN_PCK_SIZE)? 1 :0,
-		NON_ATOM_PCKS =  (PORT_B>MIN_PCK_SIZE)?  (PORT_B/MIN_PCK_SIZE)+ OFFSET : 1,
-		MAX_PCK = (VC_REALLOCATION_TYPE== "ATOMIC")?  1 : NON_ATOM_PCKS + OVC_ALLOC_MODE,// min packet size is two hence the max packet number in buffer is (B/2)
-		IGNORE_SAME_LOC_RD_WR_WARNING = ((SSA_EN=="YES")| SMART_EN)? "YES" : "NO";
-	         
-
-	localparam 
-		ELw = log2(T3),
-		Pw  = log2(P),
-		PLw = (TOPOLOGY == "FMESH") ? Pw : ELw,
-		VPLw= V * PLw,
-		PRAw= P * RAw;
-	/* verilator lint_on WIDTH */   
-   
- 
-	input reset, clk;
-	output  [V-1 : 0] credit_out;
-	input   [RAw-1 : 0] current_r_addr;
-	input   [PRAw-1:  0]  neighbors_r_addr;
-	output  [V-1 : 0] ivc_num_getting_sw_grant;
-	input                      any_ivc_sw_request_granted;
-	input   [Fw-1 : 0] flit_in;
-	input                       flit_in_wr;
-	output  [V-1 : 0] reset_ivc;
-	output  [V-1 : 0] flit_is_tail;
-	output  [V-1 : 0] ivc_request;
-	output  [VP_1-1 : 0] dest_port;
-	output  [Fw-1 : 0] flit_out;
-	input   [V-1  : 0] assigned_ovc_not_full;
-	output  [V-1  : 0] ovc_is_assigned;
-	input   [V-1 : 0] sel;    
-	input   [V-1 : 0] nonspec_first_arbiter_granted_ivc;
-	   
-	input   [DSTPw-1 : 0] destport_clear [V-1 : 0];            
-	output  [WEIGHTw-1 : 0] iport_weight;
-	output  [V-1 : 0] vc_weight_is_consumed;
-	output  iport_weight_is_consumed;
-	input   refresh_w_counter;
-	input   [P_1-1 : 0] granted_dest_port; 
-	output  [WP-1 : 0] oports_weight;  
-	input   [PPSw-1 : 0] port_pre_sel;
-	input   [V-1  : 0]  swap_port_presel;
-  
-	output  ivc_info_t ivc_info [V-1 : 0]; 
-	input   smart_ctrl_t  smart_ctrl_in;
-	input   vsa_ctrl_t  vsa_ctrl_in;
-	input   ssa_ctrl_t  ssa_ctrl_in;
-	output  [CRDTw-1 : 0 ] credit_init_val_out [V-1 : 0];
+    import pronoc_pkg::*;
     
-	wire  [DSTPw-1 : 0] dest_port_encoded [V-1 : 0];
-	//for multicast
-	wire  [DSTPw-1 : 0] dest_port_multi   [V-1 : 0];
-	wire  [V-1 : 0] multiple_dest,dst_onhot0;
-	wire   [DSTPw-1 : 0] clear_dspt_mulicast  [V-1 : 0];
-	
-	wire  [VV-1 : 0] candidate_ovcs;
-	
-	wire [Cw-1 : 0] class_in;
-	wire [DSTPw-1 : 0] destport_in,destport_in_encoded;
-	wire [VDSTPw-1 : 0] lk_destination_encoded;
-	
-	wire [DAw-1 : 0] dest_e_addr_in;
-	wire [EAw-1 : 0] src_e_addr_in;
-	wire [V-1 : 0] vc_num_in;
-	wire [V-1 : 0] hdr_flit_wr,flit_wr;
-	wire [VV-1 : 0] assigned_ovc_num;
-	
-	wire [DSTPw-1 : 0] lk_destination_in_encoded;
-	wire [WEIGHTw-1  : 0] weight_in;   
-	wire [Fw-1 : 0] buffer_out;
-	wire hdr_flg_in,tail_flg_in;  
-	wire [V-1 : 0] ivc_not_empty;
-	wire [Cw-1 : 0] class_out [V-1 : 0];
-	wire [VPLw-1 : 0] endp_localp_num;
-	          
-	wire [V-1 : 0] smart_hdr_en;
-	wire [ELw-1 : 0] endp_l_in;
-	wire [Pw-1 : 0] endp_p_in;
-	
-	wire [V-1 : 0] rd_hdr_fwft_fifo,wr_hdr_fwft_fifo,rd_hdr_fwft_fifo_delay,wr_hdr_fwft_fifo_delay;
+    localparam 
+        PORT_B = port_buffer_size(SW_LOC),
+        //PORT_IVC is equal to V if HETERO_VC=0
+        PORT_IVC = hetero_ivc_decimal(ROUTER_ID, SW_LOC);
     
-	logic [V-1  : 0] ovc_is_assigned_next;
-	logic [VV-1 : 0] assigned_ovc_num_next;
-	
-	wire odd_column = current_r_addr[0]; 
-	wire [P-1 : 0] destport_one_hot [V-1 :0];		
-	wire [V-1 : 0] mux_out[V-1 : 0];
-	
-	wire [V-1 : 0] dstport_fifo_not_empty;
-
-	logic  [WEIGHTw-1 : 0] iport_weight_next;
-	
-	assign smart_hdr_en  = (SMART_EN) ? smart_ctrl_in.ivc_num_getting_ovc_grant: {V{1'b0}};
-	assign reset_ivc  = smart_ctrl_in.ivc_reset | ssa_ctrl_in.ivc_reset | vsa_ctrl_in.ivc_reset;
-	assign ivc_num_getting_sw_grant = ssa_ctrl_in.ivc_num_getting_sw_grant | vsa_ctrl_in.ivc_num_getting_sw_grant;
-	assign flit_wr =(flit_in_wr )? vc_num_in : {V{1'b0}};
-	assign rd_hdr_fwft_fifo  = (ssa_ctrl_in.ivc_reset | vsa_ctrl_in.ivc_reset | (smart_ctrl_in.ivc_reset  & ~ smart_ctrl_in.ivc_single_flit_pck)) & ~ multiple_dest;
-	assign wr_hdr_fwft_fifo  = hdr_flit_wr | (smart_hdr_en & ~ smart_ctrl_in.ivc_single_flit_pck);
-	assign ivc_request = ivc_not_empty;    
-	
-	
-	wire  [V-1 : 0] flit_is_tail2;
-	
-	
-	pronoc_register #(.W(V)) reg1(
-			.in		(ovc_is_assigned_next), 
-			.reset  (reset ), 
-			.clk    (clk   ), 
-			.out    (ovc_is_assigned   ));
-		
-	pronoc_register #(.W(VV)) reg2(
-			.in		(assigned_ovc_num_next), 
-			.reset  (reset ), 
-			.clk    (clk   ), 
-			.out    (assigned_ovc_num  ));
-	
-	pronoc_register #(.W(V)) reg3(
-			.in		(rd_hdr_fwft_fifo), 
-			.reset  (reset ), 
-			.clk    (clk   ), 
-			.out    (rd_hdr_fwft_fifo_delay ));
-	
-	pronoc_register #(.W(V)) reg4(
-			.in		(wr_hdr_fwft_fifo), 
-			.reset  (reset ), 
-			.clk    (clk   ), 
-			.out    (wr_hdr_fwft_fifo_delay ));
-	
-	pronoc_register #(.W(WEIGHTw), .RESET_TO(1)) reg5(
-			.in		(iport_weight_next ), 
-			.reset  (reset ), 
-			.clk    (clk   ), 
-			.out    (iport_weight  ));
-	
-	
-	pronoc_register #(.W(V)) credit_reg (
-			.in     (ivc_num_getting_sw_grant & ~ multiple_dest),
-			.reset  (reset),
-			.clk    (clk),
-			.out    (credit_out)); 
+    localparam
+        W = WEIGHTw,
+        WP = W * P,
+        P_1 = (SELF_LOOP_EN )?  P : P-1,
+        VP_1 = V * P_1;
+// -------------------------------------------------------------------------
+// MAX_PCKS calculation explanation for non atomic vc allocation:
+// We want to compute the maximum number of packets that can be present in 
+// a FIFO buffer of size PORT_B flits, where each packet has a minimum size 
+// of MIN_PCK_SIZE flits. Packets are read and written flit by flit.
+//
+// Worst-case scenario:
+// - One packet is partially read (only the tail remains in the FIFO).
+// - One packet may be partially written (only header or part of the body written).
+// - The remaining (PORT_B - 1) flits can be filled with full min-size packets.
+//
+// Formula:
+//   MAX_PCKS = floor((PORT_B - 1) / MIN_PCK_SIZE)  // full packets
+//            + 1                                   // for partially read packet
+//            + (if (PORT_B - 1) % MIN_PCK_SIZE > 0) 1 else 0 // partial write
+//
+// This ensures the FIFO is fully utilized and accounts for partially present packets.
+// -------------------------------------------------------------------------
+    localparam
+        OFFSET = (((PORT_B-1) % MIN_PCK_SIZE)>0) ? 1 : 0,
+        NON_ATOM_PCKS =  (PORT_B <= MIN_PCK_SIZE) ?  1 : ((PORT_B-1) / MIN_PCK_SIZE) + OFFSET +1,
+        MAX_PCK = 
+            (IS_VCA_ATOMIC) ?  1 : 
+            (OVC_ALLOC_MODE) ? (NON_ATOM_PCKS + 1) : NON_ATOM_PCKS,
+        IGNORE_SAME_LOC_RD_WR_WARNING = ((SSA_EN == 1) || (SMART_EN==1) ) ? 1 : 0;
     
+    localparam
+        ELw = log2(T3),
+        Pw  = log2(P),
+        PLw = (IS_FMESH) ? Pw : ELw,
+        VPLw= V * PLw,
+        PRAw= P * RAw;
     
-	
-	
-	always @ (*)begin 
-		iport_weight_next = iport_weight;
-		if(hdr_flit_wr != {V{1'b0}})  iport_weight_next = (weight_in=={WEIGHTw{1'b0}})? 1 : weight_in; // the minimum weight is 1
-	end
-
-	
-	//extract header flit info
-	extract_header_flit_info #(
-		.NOC_ID(NOC_ID),
-		.DATA_w(0)			
-	) header_extractor (
-		.flit_in(flit_in),
-		.flit_in_wr(flit_in_wr),         
-		.class_o(class_in),
-		.destport_o(destport_in),
-		.dest_e_addr_o(dest_e_addr_in),
-		.src_e_addr_o(src_e_addr_in),
-		.vc_num_o(vc_num_in),
-		.hdr_flit_wr_o(hdr_flit_wr),
-		.hdr_flg_o(hdr_flg_in),
-		.tail_flg_o(tail_flg_in),
-		.weight_o(weight_in),
-		.be_o( ),
-		.data_o( )
-	);
-         
+    input   reset, clk;
+    input   router_info_t router_info;
+    output  logic [V-1 : 0] credit_out;
+    output  [V-1 : 0] ivc_num_getting_sw_grant;
+    input   any_ivc_sw_request_granted;
+    input   flit_t flit_in;
+    input   flit_in_wr;
+    output  [V-1 : 0] reset_ivc;
+    output  [V-1 : 0] flit_is_tail;
+    output  [V-1 : 0] ivc_request;
+    output  [VP_1-1 : 0] dest_port;
+    output  [Fw-1 : 0] flit_out;
+    input   [V-1  : 0] assigned_ovc_not_full;
+    output  logic [V-1  : 0] ovc_is_assigned;
+    input   [V-1 : 0] sel;    
+    input   [V-1 : 0] nonspec_first_arbiter_granted_ivc;
+    
+    input   [DSTPw-1 : 0] destport_clear [V-1 : 0];
+    output  logic [WEIGHTw-1 : 0] iport_weight;
+    output  [V-1 : 0] vc_weight_is_consumed;
+    output  iport_weight_is_consumed;
+    input   refresh_w_counter;
+    input   [P_1-1 : 0] granted_dest_port; 
+    output  [WP-1 : 0] oports_weight;  
+    input   [PPSw-1 : 0] port_pre_sel;
+    input   [V-1  : 0]  swap_port_presel;
+    
+    output  ivc_info_t ivc_info [V-1 : 0]; 
+    input   smart_ctrl_t  smart_ctrl_in;
+    input   vsa_ctrl_t  vsa_ctrl_in;
+    input   ssa_ctrl_t  ssa_ctrl_in;
+    output  [CRDTw-1 : 0 ] credit_init_val_out [V-1 : 0];
+    input   ctrl_chanel_t ctrl_in  [P-1 : 0];
+    
+    wire   [RAw-1 : 0] current_r_addr = router_info.router_addr;
+    wire   [PRAw-1: 0] neighbors_r_addr = router_info.neighbors_r_addr[PRAw-1: 0];
     
-		
-	genvar i;
-	generate
-		/* verilator lint_off WIDTH */  
-		if (( TOPOLOGY == "RING" || TOPOLOGY == "LINE" || TOPOLOGY == "MESH" || TOPOLOGY == "TORUS") && (T3>1) && CAST_TYPE== "UNICAST") begin : multi_local
-		/* verilator lint_on WIDTH */  
-		
-				
-		
-				mesh_tori_endp_addr_decode #(
-					.TOPOLOGY(TOPOLOGY),
-					.T1(T1),
-					.T2(T2),
-					.T3(T3),
-					.EAw(EAw)
-				)
-				endp_addr_decode
-				(
-					.e_addr(dest_e_addr_in),
-					.ex( ),
-					.ey( ),
-					.el(endp_l_in),
-					.valid( )
-				);
-		end
-		/* verilator lint_off WIDTH */  
-		if ( TOPOLOGY == "FMESH" && CAST_TYPE== "UNICAST" ) begin : fmesh
-		/* verilator lint_on WIDTH */  
-				
-			
-			
-			fmesh_endp_addr_decode #(
-					.T1(T1),
-					.T2(T2),
-					.T3(T3),
-					.EAw(EAw)
-				)
-				endp_addr_decode
-				(
-					.e_addr(dest_e_addr_in),
-					.ex(),
-					.ey(),
-					.ep(endp_p_in),
-					.valid()
-				);
-		
-		end	
-		/* verilator lint_off WIDTH */  
-		if(TOPOLOGY=="FATTREE" && ROUTE_NAME == "NCA_STRAIGHT_UP") begin : fat
-			/* verilator lint_on WIDTH */  
-     
-			fattree_destport_up_select #(
-					.K(T1),
-					.SW_LOC(SW_LOC)
-				)
-				static_sel
-				(
-					.destport_in(destport_in),
-					.destport_o(destport_in_encoded)
-				);
-     
-		end else begin : other
-			assign destport_in_encoded = destport_in;    
-		end
-		
-		
-		for (i=0;i<V; i=i+1) begin: V_
-	
-			assign credit_init_val_out [i] = PORT_B [CRDTw-1 : 0 ];
-				
-			
-			one_hot_to_bin #(.ONE_HOT_WIDTH(V),.BIN_WIDTH(Vw)) conv (
-					.one_hot_code(assigned_ovc_num[(i+1)*V-1 : i*V]), 
-					.bin_code(ivc_info[i].assigned_ovc_bin)
-				);	
-    	
-        	assign ivc_info[i].single_flit_pck =
-        		/* verilator lint_off WIDTH */
-        		(PCK_TYPE == "SINGLE_FLIT")? 1'b1  :
-        		/* verilator lint_on WIDTH */
-        		(MIN_PCK_SIZE == 1)? flit_is_tail[i] & ~ovc_is_assigned[i] :  1'b0; 
-			assign ivc_info[i].ivc_req = ivc_request[i];
-			assign ivc_info[i].class_num = class_out[i];
-			assign ivc_info[i].flit_is_tail = flit_is_tail[i];
-			assign ivc_info[i].assigned_ovc_not_full=assigned_ovc_not_full[i];
-			assign ivc_info[i].candidate_ovc=   candidate_ovcs [(i+1)*V-1 : i*V];
-			assign ivc_info[i].ovc_is_assigned = ovc_is_assigned[i];
-			assign ivc_info[i].assigned_ovc_num= assigned_ovc_num[(i+1)*V-1 : i*V];
-			assign ivc_info[i].dest_port_encoded=dest_port_encoded[i];
-			//assign ivc_info[i].getting_swa_first_arbiter_grant=nonspec_first_arbiter_granted_ivc[i];
-			//assign ivc_info[i].getting_swa_grant=ivc_num_getting_sw_grant[i];
-			if(P==MAX_P) begin :max_
-				assign ivc_info[i].destport_one_hot= destport_one_hot[i];
-			end else begin : no_max
-				assign ivc_info[i].destport_one_hot= {{(MAX_P-P){1'b0}},destport_one_hot[i]};
-			end	
-			//synthesis translate_off
-			//check ivc info
-			//assigned ovc must be onehot coded
-			//assert property (@(posedge clk) $onehot0(ivc_info[i].assigned_ovc_num));
-			always @ (posedge clk )begin 
-				if(~ $onehot0(ivc_info[i].assigned_ovc_num)) begin 
-					$display ("ERROR: assigned OVC is not ont-hot coded %d,%m",ivc_info[i].assigned_ovc_num);
-					$finish;
-				end
-			end	
-			//synthesis translate_on
-			
-			
-			
-			
-			
-			class_ovc_table #(
-					.CVw(CVw),
-					.CLASS_SETTING(CLASS_SETTING),   
-					.C(C),
-					.V(V)
-				)
-				class_table
-				(
-					.class_in(class_out[i]),
-					.candidate_ovcs(candidate_ovcs [(i+1)*V-1 : i*V])
-				);    
+    wire  [DSTPw-1 : 0] dest_port_encoded [V-1 : 0];
+    //for multicast
+    wire  [DSTPw-1 : 0] dest_port_multi   [V-1 : 0];
+    wire  [V-1 : 0] multiple_dest,dst_onhot0;
+    wire   [DSTPw-1 : 0] clear_dspt_mulicast  [V-1 : 0];
+    
+    logic  [V-1 : 0] candidate_ovcs [V-1 : 0];
+    
+    wire [DSTPw-1 : 0] destport_in_encoded;
+    wire [DSTPw-1 : 0] lk_destination_encoded [V-1:0];
+    
+    wire [EAw-1 : 0] dest_e_addr_out [V-1 : 0];
+    wire [V-1 : 0] hdr_flit_wr;
+    logic [V-1 : 0] assigned_ovc_num [V-1:0];
+    logic [V-1 : 0] assigned_ovc_one_hot [V-1 : 0];
+    logic [Vw-1 : 0] assigned_onc_bin [V-1 : 0];
+    
+    wire [DSTPw-1 : 0] lk_destination_in_encoded;
+    wire [Fw-1 : 0] buffer_out;
+    wire [V-1 : 0] ivc_not_empty;
+    wire [Cw-1 : 0] class_out [V-1 : 0];
+    wire [VPLw-1 : 0] endp_localp_num;
+    wire [V-1 : 0] smart_hdr_en;
+    
+    wire [V-1 : 0] rd_hdr_fwft_fifo,wr_hdr_fwft_fifo;
+    logic [V-1 : 0] rd_hdr_fwft_fifo_delay,wr_hdr_fwft_fifo_delay;
+    logic [V-1  : 0] ovc_is_assigned_next;
+    logic [V-1 : 0] assigned_ovc_num_next [V-1 : 0];
+    
+    wire odd_column = current_r_addr[0]; 
+    wire [P-1 : 0] destport_one_hot [V-1 :0];
+    wire [V-1 : 0] mux_out[V-1 : 0];
+    
+    wire [V-1 : 0] dstport_fifo_not_empty;
+    logic  [WEIGHTw-1 : 0] iport_weight_next;
+    hdr_flit_t hdr_flit_i;
+    
+    assign smart_hdr_en  = (SMART_EN) ? smart_ctrl_in.ivc_num_getting_ovc_grant: {V{1'b0}};
+    assign reset_ivc  = smart_ctrl_in.ivc_reset | ssa_ctrl_in.ivc_reset | vsa_ctrl_in.ivc_reset;
+    assign ivc_num_getting_sw_grant = ssa_ctrl_in.ivc_num_getting_sw_grant | vsa_ctrl_in.ivc_num_getting_sw_grant;
+    assign rd_hdr_fwft_fifo  = (ssa_ctrl_in.ivc_reset | vsa_ctrl_in.ivc_reset | (smart_ctrl_in.ivc_reset  & ~ smart_ctrl_in.ivc_single_flit_pck)) & ~ multiple_dest;
+    assign wr_hdr_fwft_fifo  = hdr_flit_wr | (smart_hdr_en & ~ smart_ctrl_in.ivc_single_flit_pck);
+    assign ivc_request = ivc_not_empty;
+    
+    always_ff @ (`pronoc_clk_reset_edge) begin
+        if (`pronoc_reset) begin
+            ovc_is_assigned        <= '0;
+            rd_hdr_fwft_fifo_delay <= '0;
+            wr_hdr_fwft_fifo_delay <= '0;
+            iport_weight           <= WEIGHTw'(1);
+            credit_out             <= '0;
+        end else begin
+            ovc_is_assigned        <= ovc_is_assigned_next;
+            rd_hdr_fwft_fifo_delay <= rd_hdr_fwft_fifo;
+            wr_hdr_fwft_fifo_delay <= wr_hdr_fwft_fifo;
+            iport_weight           <= iport_weight_next;
+            credit_out             <= ivc_num_getting_sw_grant & ~multiple_dest;
+        end
+    end
+    always_comb begin 
+        iport_weight_next = iport_weight;
+        if(hdr_flit_wr != {V{1'b0}})  iport_weight_next = (hdr_flit_i.weight=={WEIGHTw{1'b0}})? WEIGHT_INIT : hdr_flit_i.weight; // the minimum weight is 1
+    end
+    
+    header_flit_info #(
+        .DATA_w(0)
+    ) header_info (
+        .flit(flit_in),
+        .hdr_flit(hdr_flit_i),
+        .data_o( )
+    );
+    assign hdr_flit_wr = (flit_in_wr & flit_in.hdr_flag) ? flit_in.vc : {V{1'b0}};    
+    
+    genvar i;
+    generate
+    for (i=0; i<V; i=i+1) begin : O_
+        assign assigned_ovc_one_hot [i] = assigned_ovc_num[i];
+        always_ff @ (`pronoc_clk_reset_edge) begin
+            if (`pronoc_reset) begin
+                assigned_ovc_num[i] <= '0;
+            end else begin
+                assigned_ovc_num[i] <= assigned_ovc_num_next[i];
+            end
+        end
+    end
+    
+    /* verilator lint_off WIDTH */  
+    if(IS_FATTREE & (ROUTE_NAME == "NCA_STRAIGHT_UP")) begin : fat
+    /* verilator lint_on WIDTH */  
+        fattree_destport_up_select #(
+            .K(T1),
+            .SW_LOC(SW_LOC)
+        ) static_sel (
+            .destport_in(hdr_flit_i.destport),
+            .destport_o(destport_in_encoded)
+        );
+        
+    end else begin : other
+        assign destport_in_encoded = hdr_flit_i.destport;
+    end
+    
+    logic [1:0] ovc_sel_i;
+    logic [1:0] ovc_sel_ivc [V-1 : 0];
+    if(IS_MULTI_MESH) begin : mmesh_
+        multi_mesh_ovc_sel #(
+            .SW_LOC(SW_LOC)
+        ) ovc_sel(
+            .global_dst_i(hdr_flit_i.dest_e_addr[RAw-1:0]),
+            .current_router_addr_i(router_info.router_addr),
+            .up_dir_sel_i(hdr_flit_i.dest_e_addr[DAw-2:DAw-2]),
+            .destport_out_i(hdr_flit_i.destport),
+            .vc_num_i(flit_in.vc),
+            .ovc_sel_o(ovc_sel_i)
+        );
+    end // "MULTI_MESH"
+    
+    always_comb begin
+        for (int k=0; k<PORT_IVC; k=k+1) begin
+            ivc_info[k].single_flit_pck = 
+                ( IS_SINGLE_FLIT ) ? 1'b1  :
+                ( MIN_PCK_SIZE == 1 ) ? flit_is_tail[k] & ~ovc_is_assigned[k] :  1'b0; 
+            ivc_info[k].ivc_req = ivc_request[k];
+            ivc_info[k].class_num = class_out[k];
+            ivc_info[k].flit_is_tail = flit_is_tail[k];
+            ivc_info[k].assigned_ovc_not_full = assigned_ovc_not_full[k];
+            ivc_info[k].candidate_ovc = candidate_ovcs [k];
+            ivc_info[k].ovc_is_assigned = ovc_is_assigned[k];
+            ivc_info[k].assigned_ovc_num = assigned_ovc_one_hot[k];
+            ivc_info[k].dest_port_encoded = dest_port_encoded[k];
+            //ivc_info[k].getting_swa_first_arbiter_grant=nonspec_first_arbiter_granted_ivc[k];
+            //ivc_info[k].getting_swa_grant=ivc_num_getting_sw_grant[k];
+            ivc_info[k].destport_one_hot = {MAX_P{1'b0}};
+            ivc_info[k].destport_one_hot[P-1 : 0] = destport_one_hot[k];
+            ivc_info[k].assigned_ovc_bin = assigned_onc_bin[k];
+            ivc_info[k].dest_e_addr = dest_e_addr_out[k];
+`ifdef MULTI_MESH_ASSERTIONS
+            // synthesis translate_off
+            if (IS_MULTI_MESH) begin
+                assert property (@(posedge clk)
+                    ovc_is_assigned[k] |->
+                        k != Z_PLUS_VC_IDX ||
+                        assigned_ovc_one_hot[k] != Z_MIN_VC)
+                    else
+                        $fatal("Z- OVC assigned to a Z+ IVC");
+            end
+            // synthesis translate_on
+`endif // MULTI_MESH_ASSERTIONS
+        end //for k
+        for (int k=PORT_IVC; k<V; k=k+1) begin 
+            ivc_info[k] = {IVC_INFO_w{1'b0}};
+        end//k
+    end
+    
+    always_comb begin
+        ovc_is_assigned_next = {V{1'b0}}; //for single flit mode
+        for ( int k=0; k<PORT_IVC; k++) begin
+            assigned_ovc_num_next[k]  = assigned_ovc_one_hot [k];
+            if( IS_MULTI_FLIT) begin 
+                ovc_is_assigned_next[k] = ovc_is_assigned[k];
+                if( vsa_ctrl_in.ivc_reset[k] |
+                        ssa_ctrl_in.ivc_reset[k] |
+                        smart_ctrl_in.ivc_reset[k] 
+                    )   ovc_is_assigned_next[k] = 1'b0;
+                else if( vsa_ctrl_in.ivc_num_getting_ovc_grant[k] |
+                        (ssa_ctrl_in.ivc_num_getting_ovc_grant[k] & ~  ssa_ctrl_in.ivc_single_flit_pck[k])|
+                        (smart_ctrl_in.ivc_num_getting_ovc_grant[k] & ~  smart_ctrl_in.ivc_single_flit_pck[k])
+                    )   ovc_is_assigned_next[k] = 1'b1;
+                if(vsa_ctrl_in.ivc_num_getting_ovc_grant[k] | ssa_ctrl_in.ivc_num_getting_ovc_grant[k] | smart_ctrl_in.ivc_num_getting_ovc_grant[k] ) begin 
+                    assigned_ovc_num_next[k] = mux_out[k];
+                end
+            end// "IS_MULTI_FLIT"
+            else begin //single flit mode
+                if(vsa_ctrl_in.ivc_num_getting_ovc_grant[k] | ssa_ctrl_in.ivc_num_getting_ovc_grant[k]) begin 
+                    assigned_ovc_num_next[k] = mux_out[k];
+                end
+            end
+        end //for k
+    end//always 
+    
+    //One-hot to binary
+    always_comb begin
+        for (int m=0;m<PORT_IVC; m++) begin
+            assigned_onc_bin[m] = '0;
+            for (int k = 0; k < V; k++) begin
+                if (assigned_ovc_one_hot[m][k]) assigned_onc_bin[m] = Vw'(k);
+            end
+        end
+    end
+    for (i=0;i<PORT_IVC; i=i+1) begin: V_
+        assign credit_init_val_out [i] = PORT_B [CRDTw-1 : 0 ];
         
-			if(PCK_TYPE == "MULTI_FLIT") begin : multi_flit 
-				
-				always @ (*) begin
-					ovc_is_assigned_next[i] = ovc_is_assigned[i];		
-					if( vsa_ctrl_in.ivc_reset[i] |
-							ssa_ctrl_in.ivc_reset[i] |
-							smart_ctrl_in.ivc_reset[i] 
-						)  	ovc_is_assigned_next[i] = 1'b0;
-				
-					else if( vsa_ctrl_in.ivc_num_getting_ovc_grant[i] |
-							(ssa_ctrl_in.ivc_num_getting_ovc_grant[i] & ~  ssa_ctrl_in.ivc_single_flit_pck[i])|
-							(smart_ctrl_in.ivc_num_getting_ovc_grant[i] & ~  smart_ctrl_in.ivc_single_flit_pck[i])
-						)       ovc_is_assigned_next[i] = 1'b1;		
-				end//always
-				
-				
-				always @(*) begin
-					assigned_ovc_num_next[(i+1)*V-1 : i*V] = assigned_ovc_num[(i+1)*V-1 : i*V] ;
-					if(vsa_ctrl_in.ivc_num_getting_ovc_grant[i] | ssa_ctrl_in.ivc_num_getting_ovc_grant[i] | smart_ctrl_in.ivc_num_getting_ovc_grant[i] ) begin 
-						assigned_ovc_num_next[(i+1)*V-1 : i*V] = mux_out[i];
-					end
-				end
-			
-				onehot_mux_1D #(
-						.N  (3), 
-						.W  (V)
-					) hot_mux (
-						.in     ({vsa_ctrl_in.ivc_granted_ovc_num[(i+1)*V-1 : i*V], 
-								ssa_ctrl_in.ivc_granted_ovc_num[(i+1)*V-1 : i*V],
-								smart_ctrl_in.ivc_granted_ovc_num[(i+1)*V-1 : i*V]}), 
-						.sel        ({vsa_ctrl_in.ivc_num_getting_ovc_grant[i],ssa_ctrl_in.ivc_num_getting_ovc_grant[i],smart_ctrl_in.ivc_num_getting_ovc_grant[i]}  ),
-						.out    (mux_out[i]   ) 
-					);
-					
-				
-				/*
-				//tail fifo
-				fwft_fifo #(
-					.DATA_WIDTH(1),
-					.MAX_DEPTH (PORT_B),
-					.IGNORE_SAME_LOC_RD_WR_WARNING(IGNORE_SAME_LOC_RD_WR_WARNING)
-				)
-				tail_fifo
-				(
-					.din (tail_flg_in),
-					.wr_en (flit_wr[i]),   // Write enable
-					.rd_en (ivc_num_getting_sw_grant[i]),   // Read the next word
-					.dout (flit_is_tail[i]),    // Data out
-					.full ( ),
-					.nearly_full ( ),
-					.recieve_more_than_0 ( ),
-					.recieve_more_than_1 ( ),
-					.reset (reset),
-					.clk (clk)            
-				);
-				*/
-				
-			end else begin :single_flit
-				//assign flit_is_tail[i]=1'b1;
-				assign ovc_is_assigned_next[i] = 1'b0;
-				
-				always @(*) begin
-					assigned_ovc_num_next[(i+1)*V-1 : i*V] = assigned_ovc_num[(i+1)*V-1 : i*V] ;
-					if(vsa_ctrl_in.ivc_num_getting_ovc_grant[i] | ssa_ctrl_in.ivc_num_getting_ovc_grant[i]) begin 
-						assigned_ovc_num_next[(i+1)*V-1 : i*V] = mux_out[i];
-					end
-				end
-			
-				onehot_mux_1D #(
-						.N  (2), 
-						.W  (V)
-					) hot_mux (
-						.in     ({vsa_ctrl_in.ivc_granted_ovc_num[(i+1)*V-1 : i*V], 
-								ssa_ctrl_in.ivc_granted_ovc_num[(i+1)*V-1 : i*V]}), 
-						.sel        ({vsa_ctrl_in.ivc_num_getting_ovc_grant[i],ssa_ctrl_in.ivc_num_getting_ovc_grant[i]}  ),
-						.out    (mux_out[i]   ) 
-					);
-					
-				
-				
-			end
-			//dest_e_addr_in fifo
-			if(SMART_EN) begin : smart_
-        	
-				fwft_fifo #(
-						.DATA_WIDTH(EAw),
-						.MAX_DEPTH (MAX_PCK),
-						.IGNORE_SAME_LOC_RD_WR_WARNING(IGNORE_SAME_LOC_RD_WR_WARNING)
-					)
-					dest_e_addr_fifo
-					(
-						.din (dest_e_addr_in),
-						.wr_en (wr_hdr_fwft_fifo[i]),   // Write enable
-						.rd_en (rd_hdr_fwft_fifo[i]),   // Read the next word
-						.dout (ivc_info[i].dest_e_addr),    // Data out
-						.full ( ),
-						.nearly_full ( ),
-						.recieve_more_than_0 ( ),
-						.recieve_more_than_1 ( ),
-						.reset (reset),
-						.clk (clk)            
-					);   	
-        	
-			end	else begin : no_smart
-				assign ivc_info[i].dest_e_addr = {EAw{1'bx}};
-			end	
+        `ifdef SIMULATION
+        //check ivc info
+        //assigned ovc must be onehot coded
+        //assert property (@(posedge clk) $onehot0(ivc_info[i].assigned_ovc_num));
+        always @ (posedge clk )begin 
+            if(~ $onehot0(ivc_info[i].assigned_ovc_num)) begin 
+                $display ("ERROR: assigned OVC is not ont-hot coded %d,%m",ivc_info[i].assigned_ovc_num);
+                $finish;
+            end
+        end
+        `endif
+        if(IS_MULTI_MESH==0) begin :ovc_
+            ovc_list  OvcList(
+                .class_in(class_out[i]),
+                .ovcs_out(candidate_ovcs [i])
+            );
+        end else begin :mmesh_ovc
+            fwft_fifo #(
+                .DATA_WIDTH(2),
+                .MAX_DEPTH (MAX_PCK),
+                .IGNORE_SAME_LOC_RD_WR_WARNING(IGNORE_SAME_LOC_RD_WR_WARNING)
+            ) ovc_fifo (
+                .din (ovc_sel_i),
+                .wr_en (wr_hdr_fwft_fifo[i]),   // Write enable
+                .rd_en (rd_hdr_fwft_fifo[i]),   // Read the next word
+                .dout (ovc_sel_ivc[i]),    // Data out
+                .status_o(),
+                .reset (reset),
+                .clk (clk)
+            );
+            multi_mesh_ovc_list_per_ivc #(
+                .IVC_NUM(i), //Input port VC number
+                .P(P) //router IO number
+            )OvcList(
+                .destport_one_hot(destport_one_hot[i]),
+                .ctrl_in(ctrl_in),
+                .class_in(class_out[i]),
+                .ovc_sel(ovc_sel_ivc[i]),
+                .ovcs_out(candidate_ovcs [i])
+            );
+        end
+        if( IS_MULTI_FLIT) begin : multi_flit
+            //onehot mux
+            assign mux_out[i] = 
+                (vsa_ctrl_in.ivc_num_getting_ovc_grant[i]) ? vsa_ctrl_in.ivc_granted_ovc_num[(i+1)*V-1 : i*V] :
+                (ssa_ctrl_in.ivc_num_getting_ovc_grant[i]) ? ssa_ctrl_in.ivc_granted_ovc_num[(i+1)*V-1 : i*V] :
+                (smart_ctrl_in.ivc_num_getting_ovc_grant[i]) ? smart_ctrl_in.ivc_granted_ovc_num[(i+1)*V-1 : i*V] :
+                {V{1'b0}};
+        end else begin :single_flit
+            //assign flit_is_tail[i]=1'b1;
+            assign mux_out[i] = 
+                (vsa_ctrl_in.ivc_num_getting_ovc_grant[i]) ? vsa_ctrl_in.ivc_granted_ovc_num[(i+1)*V-1 : i*V] :
+                (ssa_ctrl_in.ivc_num_getting_ovc_grant[i]) ? ssa_ctrl_in.ivc_granted_ovc_num[(i+1)*V-1 : i*V] :
+                {V{1'b0}};
+        end
+        //dest_e_addr_in fifo
+        if(SMART_EN) begin : smart_
+            fwft_fifo #(
+                .DATA_WIDTH(EAw),
+                .MAX_DEPTH (MAX_PCK),
+                .IGNORE_SAME_LOC_RD_WR_WARNING(IGNORE_SAME_LOC_RD_WR_WARNING)
+            ) dest_e_addr_fifo (
+                .din (hdr_flit_i.dest_e_addr),
+                .wr_en (wr_hdr_fwft_fifo[i]),   // Write enable
+                .rd_en (rd_hdr_fwft_fifo[i]),   // Read the next word
+                .dout (dest_e_addr_out[i]),    // Data out
+                .status_o(),
+                .reset (reset),
+                .clk (clk)
+            );
+        end else begin : no_smart
+            assign dest_e_addr_out[i]= {EAw{1'b0}};
+        end    
         
-    	
-    	
-			//class_fifo
-			if(C>1)begin :cb1
-				fwft_fifo #(
-						.DATA_WIDTH(Cw),
-						.MAX_DEPTH (MAX_PCK),
-						.IGNORE_SAME_LOC_RD_WR_WARNING(IGNORE_SAME_LOC_RD_WR_WARNING)
-					)
-					class_fifo
-					(
-						.din (class_in),
-						.wr_en (wr_hdr_fwft_fifo[i]),   // Write enable
-						.rd_en (rd_hdr_fwft_fifo[i]),   // Read the next word
-						.dout (class_out[i]),    // Data out
-						.full ( ),
-						.nearly_full ( ),
-						.recieve_more_than_0 ( ),
-						.recieve_more_than_1 ( ),
-						.reset (reset),
-						.clk (clk)
-            
-					);
-			end else begin :c_num_1
-				assign class_out[i] = 1'b0;
-			end
-       
-			
-			//localparam CAST_TYPE = "UNICAST"; // multicast is not yet supported
-			/* verilator lint_off WIDTH */    
-			if(CAST_TYPE!= "UNICAST") begin : muticast
-			/* verilator lint_on WIDTH */
-				
-				// for multicast we send one packet to each direction in order. The priority is according to DoR routing dimentions 
-				
-				fwft_fifo_with_output_clear #(
-					.DATA_WIDTH(DSTPw),
-					.MAX_DEPTH (MAX_PCK),
-					.IGNORE_SAME_LOC_RD_WR_WARNING(IGNORE_SAME_LOC_RD_WR_WARNING)
-				)
-				dest_fifo
-				(
-					.din(destport_in_encoded),
-					.wr_en(wr_hdr_fwft_fifo[i]),   // Write enable
-					.rd_en(rd_hdr_fwft_fifo[i]),   // Read the next word
-					.dout(dest_port_multi[i]),    // Data out
-					.full(),
-					.nearly_full(),
-					.recieve_more_than_0(),
-					.recieve_more_than_1(),
-					.reset(reset),
-					.clk(clk),
-					.clear(clear_dspt_mulicast [i])   // clear the  destination port once it got  the entire packet
-				);               
-				
-				//TODO remove multiple_dest[i] to see if it works?
-				
-				assign clear_dspt_mulicast [i] = (reset_ivc[i] & multiple_dest[i]) ? dest_port_encoded[i] : {DSTPw{1'b0}}; 
-				
-				// a fix priority arbiter. 
-				multicast_dst_sel #(
-					.NOC_ID(NOC_ID)
-				) sel_arb(
-					.destport_in(dest_port_multi[i]),
-					.destport_out(dest_port_encoded[i])						
-				);
-				
-				//check if we have multiple port to send a packet to 
-				is_onehot0 #(
-					.IN_WIDTH(DSTPw)
-    			)
-    			one_h
-				(
-					.in(dest_port_multi[i]),
-					.result(dst_onhot0[i])
-    			);
-				assign multiple_dest[i]=~dst_onhot0[i];
-				
-			
-		end	else begin : unicast
-			assign multiple_dest[i] = 1'b0;
-			
-			
-			//lk_dst_fifo
-			fwft_fifo #(
-					.DATA_WIDTH(DSTPw),
-					.MAX_DEPTH (MAX_PCK),
-					.IGNORE_SAME_LOC_RD_WR_WARNING(IGNORE_SAME_LOC_RD_WR_WARNING)
-				)
-				lk_dest_fifo
-				(
-					.din (lk_destination_in_encoded),
-					.wr_en (wr_hdr_fwft_fifo_delay [i]),   // Write enable
-					.rd_en (rd_hdr_fwft_fifo_delay [i]),   // Read the next word
-					.dout (lk_destination_encoded  [(i+1)*DSTPw-1 : i*DSTPw]),    // Data out
-					.full (),
-					.nearly_full (),
-					.recieve_more_than_0 (),
-					.recieve_more_than_1 (),
-					.reset (reset),
-					.clk (clk)
-             
-				);
-			
-			
-				
-				/* verilator lint_off WIDTH */    
-				if( ROUTE_TYPE=="DETERMINISTIC") begin : dtrmn_dest
-				/* verilator lint_on WIDTH */
-					//destport_fifo
-					fwft_fifo #(
-							.DATA_WIDTH(DSTPw),
-							.MAX_DEPTH (MAX_PCK),
-							.IGNORE_SAME_LOC_RD_WR_WARNING(IGNORE_SAME_LOC_RD_WR_WARNING)
-						)
-						dest_fifo
-						(
-							.din(destport_in_encoded),
-							.wr_en(wr_hdr_fwft_fifo[i]),   // Write enable
-							.rd_en(rd_hdr_fwft_fifo[i]),   // Read the next word
-							.dout(dest_port_encoded[i]),    // Data out
-							.full(),
-							.nearly_full(),
-							.recieve_more_than_0(),
-							.recieve_more_than_1(),
-							.reset(reset),
-							.clk(clk) 
-						);               
-	                         
-				end else begin : adptv_dest   
-	
-					fwft_fifo_with_output_clear #(
-							.DATA_WIDTH(DSTPw),
-							.MAX_DEPTH (MAX_PCK),
-							.IGNORE_SAME_LOC_RD_WR_WARNING(IGNORE_SAME_LOC_RD_WR_WARNING)
-						)
-						dest_fifo
-						(
-							.din(destport_in_encoded),
-							.wr_en(wr_hdr_fwft_fifo[i]),   // Write enable
-							.rd_en(rd_hdr_fwft_fifo[i]),   // Read the next word
-							.dout(dest_port_encoded[i]),    // Data out
-							.full(),
-							.nearly_full(),
-							.recieve_more_than_0(),
-							.recieve_more_than_1(),
-							.reset(reset),
-							.clk(clk),
-							.clear(destport_clear[i])   // clear other destination ports once one of them is selected
-						);                  
-	    
-	                
-				end        	
-		end//unicast
-                     
-                     
-			destp_generator #(
-					.TOPOLOGY(TOPOLOGY),
-					.ROUTE_NAME(ROUTE_NAME),
-					.ROUTE_TYPE(ROUTE_TYPE),
-					.T1(T1),
-					.NL(T3),
-					.P(P),
-					.DSTPw(DSTPw),
-					.PLw(PLw),
-					.PPSw(PPSw),
-					.SELF_LOOP_EN (SELF_LOOP_EN),
-					.SW_LOC(SW_LOC),
-					.CAST_TYPE(CAST_TYPE)
-				)
-				decoder
-				(
-					.destport_one_hot (destport_one_hot[i]),
-					.dest_port_encoded(dest_port_encoded[i]),             
-					.dest_port_out(dest_port[(i+1)*P_1-1 : i*P_1]),   
-					.endp_localp_num(endp_localp_num[(i+1)*PLw-1 : i*PLw]),
-					.swap_port_presel(swap_port_presel[i]),
-					.port_pre_sel(port_pre_sel),
-					.odd_column(odd_column)
-				);
-         
-         
-			/* verilator lint_off WIDTH */  
-			if (( TOPOLOGY == "RING" || TOPOLOGY == "LINE" || TOPOLOGY == "MESH" || TOPOLOGY == "TORUS") && (T3>1) && (CAST_TYPE== "UNICAST")) begin : multi_local
-				/* verilator lint_on WIDTH */  
-				// the router has multiple local ports. Save the destination local port 
-                
-				
+        //class_fifo
+        if(C>1)begin :cb1
+            fwft_fifo #(
+                .DATA_WIDTH(Cw),
+                .MAX_DEPTH (MAX_PCK),
+                .IGNORE_SAME_LOC_RD_WR_WARNING(IGNORE_SAME_LOC_RD_WR_WARNING)
+            ) class_fifo (
+                .din (hdr_flit_i.message_class),
+                .wr_en (wr_hdr_fwft_fifo[i]),   // Write enable
+                .rd_en (rd_hdr_fwft_fifo[i]),   // Read the next word
+                .dout (class_out[i]),    // Data out
+                .status_o(),
+                .reset (reset),
+                .clk (clk)
             
-				fwft_fifo #(
-						.DATA_WIDTH(ELw),
-						.MAX_DEPTH (MAX_PCK),
-						.IGNORE_SAME_LOC_RD_WR_WARNING(IGNORE_SAME_LOC_RD_WR_WARNING)
-					)
-					local_dest_fifo
-					(
-						.din(endp_l_in),
-						.wr_en(wr_hdr_fwft_fifo[i]),   // Write enable
-						.rd_en(rd_hdr_fwft_fifo[i]),   // Read the next word
-						.dout(endp_localp_num[(i+1)*PLw-1 : i*PLw]),    // Data out
-						.full( ),
-						.nearly_full( ),
-						.recieve_more_than_0(),
-						.recieve_more_than_1(),
-						.reset(reset),
-						.clk(clk) 
-					);       
-			/* verilator lint_off WIDTH */  
-			end else if ( TOPOLOGY == "FMESH" && CAST_TYPE== "UNICAST") begin : fmesh
-			/* verilator lint_on WIDTH */  
-				
-				fwft_fifo #(
-						.DATA_WIDTH(Pw),
-						.MAX_DEPTH (MAX_PCK),
-						.IGNORE_SAME_LOC_RD_WR_WARNING(IGNORE_SAME_LOC_RD_WR_WARNING)
-					)
-					local_dest_fifo
-					(
-						.din(endp_p_in),
-						.wr_en(wr_hdr_fwft_fifo[i]),   // Write enable
-						.rd_en(rd_hdr_fwft_fifo[i]),   // Read the next word
-						.dout(endp_localp_num[(i+1)*PLw-1 : i*PLw]),    // Data out
-						.full( ),
-						.nearly_full( ),
-						.recieve_more_than_0(),
-						.recieve_more_than_1(),
-						.reset(reset),
-						.clk(clk) 
-					);       
-				
-			end else begin : single_local 
-				assign endp_localp_num[(i+1)*PLw-1 : i*PLw] = {PLw{1'bx}}; 
-			end
+            );
+        end else begin :c_num_1
+            assign class_out[i] = 1'b0;
+        end
         
-			/* verilator lint_off WIDTH */    
-			if(SWA_ARBITER_TYPE != "RRA")begin  : wrra
-				/* verilator lint_on WIDTH */
-				/*
-                weight_control #(
-                    .WEIGHTw(WEIGHTw)
-                )
-                wctrl_per_vc
-                (   
-                    .sw_is_granted(ivc_num_getting_sw_grant[i]),
-                    .flit_is_tail(flit_is_tail[i]),               
-                    .weight_is_consumed_o(vc_weight_is_consumed[i]),    
-                    .iport_weight(1),  //(iport_weight),               
+        if(~IS_UNICAST) begin : muticast
+            // for multicast we send one packet to each direction in order. The priority is according to DoR routing dimentions 
+            fwft_fifo_with_output_clear #(
+                .DATA_WIDTH(DSTPw),
+                .MAX_DEPTH (MAX_PCK),
+                .IGNORE_SAME_LOC_RD_WR_WARNING(IGNORE_SAME_LOC_RD_WR_WARNING)
+            ) dest_fifo (
+                .din(destport_in_encoded),
+                .wr_en(wr_hdr_fwft_fifo[i]),   // Write enable
+                .rd_en(rd_hdr_fwft_fifo[i]),   // Read the next word
+                .dout(dest_port_multi[i]),    // Data out
+                .status_o(),
+                .reset(reset),
+                .clk(clk),
+                .clear(clear_dspt_mulicast [i])   // clear the  destination port once it got  the entire packet
+            );
+            
+            //TODO remove multiple_dest[i] to see if it works?
+            
+            assign clear_dspt_mulicast [i] = (reset_ivc[i] & multiple_dest[i]) ? dest_port_encoded[i] : {DSTPw{1'b0}}; 
+            
+            // a fix priority arbiter. 
+            multicast_dst_sel sel_arb(
+                .destport_in(dest_port_multi[i]),
+                .destport_out(dest_port_encoded[i])
+            );
+            //check if we have multiple port to send a packet to 
+            is_onehot0 #(
+                .IN_WIDTH(DSTPw)
+            ) one_h (
+                .D_in(dest_port_multi[i]),
+                .result(dst_onhot0[i])
+            );
+            assign multiple_dest[i]=~dst_onhot0[i];
+            
+        end else begin : unicast
+            assign multiple_dest[i] = 1'b0;
+            if(IS_LOOKAHEAD) begin 
+            //lk_dst_fifo
+                fwft_fifo #(
+                    .DATA_WIDTH(DSTPw),
+                    .MAX_DEPTH (MAX_PCK),
+                    .IGNORE_SAME_LOC_RD_WR_WARNING(IGNORE_SAME_LOC_RD_WR_WARNING)
+                ) lk_dest_fifo (
+                    .din (lk_destination_in_encoded),
+                    .wr_en (wr_hdr_fwft_fifo_delay [i]),   // Write enable
+                    .rd_en (rd_hdr_fwft_fifo_delay [i]),   // Read the next word
+                    .dout (lk_destination_encoded  [i]),    // Data out
+                    .status_o(),
+                    .reset (reset),
+                    .clk (clk)
+                );
+            end else begin 
+                assign lk_destination_encoded  [i] = {DSTPw{1'b0}};
+            end// IS_LOOKAHEAD
+            if( IS_DETERMINISTIC ) begin : dtrmn_dest
+                //destport_fifo
+                fwft_fifo #(
+                    .DATA_WIDTH(DSTPw),
+                    .MAX_DEPTH (MAX_PCK),
+                    .IGNORE_SAME_LOC_RD_WR_WARNING(IGNORE_SAME_LOC_RD_WR_WARNING)
+                ) dest_fifo (
+                    .din(destport_in_encoded),
+                    .wr_en(wr_hdr_fwft_fifo[i]),   // Write enable
+                    .rd_en(rd_hdr_fwft_fifo[i]),   // Read the next word
+                    .dout(dest_port_encoded[i]),    // Data out
+                    .status_o(),
+                    .reset(reset),
+                    .clk(clk) 
+                );
+                
+            end else begin : adptv_dest
+                
+                fwft_fifo_with_output_clear #(
+                    .DATA_WIDTH(DSTPw),
+                    .MAX_DEPTH (MAX_PCK),
+                    .IGNORE_SAME_LOC_RD_WR_WARNING(IGNORE_SAME_LOC_RD_WR_WARNING)
+                ) dest_fifo (
+                    .din(destport_in_encoded),
+                    .wr_en(wr_hdr_fwft_fifo[i]),   // Write enable
+                    .rd_en(rd_hdr_fwft_fifo[i]),   // Read the next word
+                    .dout(dest_port_encoded[i]),    // Data out
+                    .status_o(),
+                    .reset(reset),
                     .clk(clk),
-                    .reset(reset)           
+                    .clear(destport_clear[i])   // clear other destination ports once one of them is selected
                 );
-				 */     
-				assign vc_weight_is_consumed[i] = 1'b1;
-			end else begin :no_wrra
-				assign vc_weight_is_consumed[i] = 1'bX;        
-			end                  
+                
+            end//   : adptv_dest
+        end//unicast
+        
+        destp_generator #(
+            .P(P),
+            .SW_LOC(SW_LOC)
+        ) decoder (
+            .destport_one_hot (destport_one_hot[i]),
+            .dest_port_encoded(dest_port_encoded[i]),
+            .dest_port_out(dest_port[(i+1)*P_1-1 : i*P_1]),
+            .endp_localp_num(endp_localp_num[(i+1)*PLw-1 : i*PLw]),
+            .swap_port_presel(swap_port_presel[i]),
+            .port_pre_sel(port_pre_sel),
+            .odd_column(odd_column)
+        );
+        
+        if ( IS_REGULAR_TOPO & IS_MULTI_ENDP_ROUTER & IS_UNICAST ) begin : multi_local
+            // the router has multiple local ports. Save the destination local port
+            fwft_fifo #(
+                .DATA_WIDTH(ELw),
+                .MAX_DEPTH (MAX_PCK),
+                .IGNORE_SAME_LOC_RD_WR_WARNING(IGNORE_SAME_LOC_RD_WR_WARNING)
+            ) local_dest_fifo (
+                .din(hdr_flit_i.dest_e_addr[DAw-1 : DAw-ELw]),// local endpoint number
+                .wr_en(wr_hdr_fwft_fifo[i]),   // Write enable
+                .rd_en(rd_hdr_fwft_fifo[i]),   // Read the next word
+                .dout(endp_localp_num[(i+1)*PLw-1 : i*PLw]),    // Data out
+                .status_o(),
+                .reset(reset),
+                .clk(clk) 
+            );
+        end else if ( IS_FMESH & IS_UNICAST) begin : fmesh
+            fwft_fifo #(
+                .DATA_WIDTH(Pw),
+                .MAX_DEPTH (MAX_PCK),
+                .IGNORE_SAME_LOC_RD_WR_WARNING(IGNORE_SAME_LOC_RD_WR_WARNING)
+            ) local_dest_fifo (
+                .din(hdr_flit_i.dest_e_addr[DAw-1 : DAw-Pw]),// local endpoint number
+                .wr_en(wr_hdr_fwft_fifo[i]),   // Write enable
+                .rd_en(rd_hdr_fwft_fifo[i]),   // Read the next word
+                .dout(endp_localp_num[(i+1)*PLw-1 : i*PLw]),    // Data out
+                .status_o(),
+                .reset(reset),
+                .clk(clk) 
+            );
             
-		end//for i
+        end else begin : single_local 
+            assign endp_localp_num[(i+1)*PLw-1 : i*PLw] = {PLw{1'b0}}; 
+        end
+        assign vc_weight_is_consumed[i] = (~IS_RRA);
+    end//for i
     
-
-		/* verilator lint_off WIDTH */    
-		if(SWA_ARBITER_TYPE != "RRA")begin  : wrra
-			/* verilator lint_on WIDTH */
-			wire granted_flit_is_tail;
+    if(~IS_RRA) begin  : wrra
+        wire granted_flit_is_tail;
+        assign granted_flit_is_tail = |(flit_is_tail & ivc_num_getting_sw_grant);        
+        
+        weight_control#(
+            .ARBITER_TYPE(SWA_ARBITER_TYPE),
+            .SW_LOC(SW_LOC),
+            .WEIGHTw(WEIGHTw),
+            .WRRA_CONFIG_INDEX(WRRA_CONFIG_INDEX),
+            .P(P),
+            .SELF_LOOP_EN(SELF_LOOP_EN)
+        ) wctrl_iport (
+            .sw_is_granted(any_ivc_sw_request_granted),
+            .flit_is_tail(granted_flit_is_tail),
+            .weight_is_consumed_o(iport_weight_is_consumed),
+            .iport_weight(iport_weight),
+            .oports_weight(oports_weight),
+            .granted_dest_port(granted_dest_port),
+            .refresh_w_counter(refresh_w_counter),
+            .clk(clk),
+            .reset(reset)
+        );
         
-			onehot_mux_1D #( 
-					.W(1),
-					.N(V)
-				)onehot_mux(
-					.in(flit_is_tail),
-					.out(granted_flit_is_tail),
-					.sel(ivc_num_getting_sw_grant)
-				);
+    end else begin :no_wrra
+        assign iport_weight_is_consumed=1'b0;
+        assign oports_weight = {WP{1'b0}};
+    end
+    wire [V-1 : 0] flit_buffer_vc_num_rd;
+    assign flit_buffer_vc_num_rd = ( IS_COMB_NONSPEC ) ? nonspec_first_arbiter_granted_ivc : ivc_num_getting_sw_grant;
     
-			weight_control#(
-					.ARBITER_TYPE(SWA_ARBITER_TYPE),
-					.SW_LOC(SW_LOC),
-					.WEIGHTw(WEIGHTw),
-					.WRRA_CONFIG_INDEX(WRRA_CONFIG_INDEX),
-					.P(P),
-					.SELF_LOOP_EN(SELF_LOOP_EN)
-				)
-				wctrl_iport
-				(   
-					.sw_is_granted(any_ivc_sw_request_granted),
-					.flit_is_tail(granted_flit_is_tail),               
-					.weight_is_consumed_o(iport_weight_is_consumed),    
-					.iport_weight(iport_weight),
-					.oports_weight(oports_weight),
-					.granted_dest_port(granted_dest_port), 
-					.refresh_w_counter(refresh_w_counter),              
-					.clk(clk),
-					.reset(reset)           
-				);     
-  
-		end else begin :no_wrra
-			assign iport_weight_is_consumed=1'bX;
-			assign oports_weight = {WP{1'bX}};          
-		end   
+    flit_buffer #(
+        .PORT_B(PORT_B),   // buffer space :flit per VC,
+        .PORT_IVC(PORT_IVC)
+    ) the_flit_buffer (
+        .din(flit_in),     // Data in
+        .vc_num_wr(flit_in.vc [PORT_IVC-1 : 0]),//write virtual channel
+        .vc_num_rd(flit_buffer_vc_num_rd [PORT_IVC-1 : 0]),//read virtual channel
+        .wr_en(flit_in_wr),   // Write enable
+        .rd_en(any_ivc_sw_request_granted),     // Read the next word
+        .dout(buffer_out),    // Data out
+        .vc_not_empty(ivc_not_empty [PORT_IVC-1 : 0]),
+        .reset(reset),
+        .clk(clk),
+        .ssa_rd(ssa_ctrl_in.ivc_num_getting_sw_grant[PORT_IVC-1 : 0]),
+        .multiple_dest( multiple_dest [PORT_IVC-1 : 0]),
+        .sub_rd_ptr_ld(reset_ivc [PORT_IVC-1 : 0]) ,
+        .flit_is_tail(flit_is_tail [PORT_IVC-1 : 0])
+    );
+    
+    if(PORT_IVC != V) begin : hetero
+        assign ivc_not_empty [V-1 : PORT_IVC]={(V-PORT_IVC){1'b0}};
+        assign flit_is_tail [V-1 : PORT_IVC]={(V-PORT_IVC){1'b0}};
+        for (i=PORT_IVC;i<V; i=i+1) begin: V_
+            assign credit_init_val_out [i] = {CRDTw{1'b0}};
+            assign candidate_ovcs [i] = {V{1'b0}};
+            assign class_out[i]={Cw{1'b0}};
+            assign dest_port_multi[i]={DSTPw{1'b0}};
+            assign dest_port_encoded[i]={DSTPw{1'b0}};
+            assign lk_destination_encoded [i]={DSTPw{1'b0}};
+            assign endp_localp_num[(i+1)*PLw-1 : i*PLw]={PLw{1'b0}};
+            assign vc_weight_is_consumed[i]=1'b0;
+        end
+    end
+    
+    if( IS_UNICAST & IS_LOOKAHEAD) begin : unicast
+        look_ahead_routing #(
+            .P(P)
+        ) lk_routing (
+            .current_r_addr(current_r_addr),
+            .neighbors_r_addr(neighbors_r_addr),
+            .dest_e_addr(hdr_flit_i.dest_e_addr),
+            .src_e_addr(hdr_flit_i.src_e_addr),
+            .destport_encoded(destport_in_encoded),
+            .lkdestport_encoded(lk_destination_in_encoded),
+            .reset(reset),
+            .clk(clk)
+        );
+    end // unicast
+    endgenerate
+    header_flit_update_lk_route_ovc #(
+        .P(P)
+    ) the_flit_update (
+        .flit_in (buffer_out),
+        .flit_out (flit_out),
+        .vc_num_in(ivc_num_getting_sw_grant),
+        .lk_dest_all_in (lk_destination_encoded),
+        .assigned_ovc_num (assigned_ovc_num),
+        .any_ivc_sw_request_granted(any_ivc_sw_request_granted),
+        .lk_dest_not_registered(lk_destination_in_encoded),
+        .sel (sel),
+        .reset (reset),
+        .clk (clk)
+    );
+    
+    `ifdef SIMULATION
+    generate
+    if(DEBUG_EN) begin :debg
         
-		/* verilator lint_off WIDTH */
-		if(COMBINATION_TYPE == "COMB_NONSPEC") begin  : nonspec  
-			/* verilator lint_on WIDTH */ 
-			
-			
-			
-			
-			 /* 
-			
-			always @(posedge clk) 
-				if ((ivc_not_empty & flit_is_tail2) != (ivc_not_empty & flit_is_tail))begin 
-					$display("ERROR:    %b !=%b",flit_is_tail2 , flit_is_tail ) ;
-					$finish;
-				end
-			*/
-			
-           
-			flit_buffer #(
-					.V(V),
-					.B(PORT_B),   // buffer space :flit per VC 
-					.SSA_EN(SSA_EN),
-        			.Fw(Fw),
-					.PCK_TYPE(PCK_TYPE),
-					.CAST_TYPE(CAST_TYPE),
-					.DEBUG_EN(DEBUG_EN)
-				)
-				the_flit_buffer
-				(
-					
-					.din(flit_in),     // Data in
-					.vc_num_wr(vc_num_in),//write virtual channel   
-					.vc_num_rd(nonspec_first_arbiter_granted_ivc),//read virtual channel     
-					.wr_en(flit_in_wr),   // Write enable
-					.rd_en(any_ivc_sw_request_granted),     // Read the next word
-					.dout(buffer_out),    // Data out
-					.vc_not_empty(ivc_not_empty),
-					.reset(reset),
-					.clk(clk),
-					.ssa_rd(ssa_ctrl_in.ivc_num_getting_sw_grant),
-					.multiple_dest( multiple_dest ),
-					.sub_rd_ptr_ld(reset_ivc) ,
-					.flit_is_tail(flit_is_tail)
-				);
-   
-		end else begin :spec//not nonspec comb
- 
-
-			flit_buffer #(
-					.V(V),
-					.B(PORT_B),   // buffer space :flit per VC 
-					.SSA_EN(SSA_EN),
-        			.Fw(Fw),
-					.PCK_TYPE(PCK_TYPE),
-					.CAST_TYPE(CAST_TYPE),
-					.DEBUG_EN(DEBUG_EN)
-				)
-				the_flit_buffer
-				(
-					.din(flit_in),     // Data in
-					.vc_num_wr(vc_num_in),//write virtual channel   
-					.vc_num_rd(ivc_num_getting_sw_grant),//read virtual channel     
-					.wr_en(flit_in_wr),   // Write enable
-					.rd_en(any_ivc_sw_request_granted),     // Read the next word
-					.dout(buffer_out),    // Data out
-					.vc_not_empty(ivc_not_empty),
-					.reset(reset),
-					.clk(clk),
-					.ssa_rd(ssa_ctrl_in.ivc_num_getting_sw_grant),
-					.multiple_dest(  multiple_dest ),
-					.sub_rd_ptr_ld(reset_ivc) ,
-					.flit_is_tail(flit_is_tail)  
-				
-				);  
-  
-		end  
-
-			
-		/* verilator lint_off WIDTH */    
-		if(CAST_TYPE== "UNICAST") begin : unicast
-		/* verilator lint_on WIDTH */
-			look_ahead_routing #(
-				.NOC_ID(NOC_ID),
-				.T1(T1),
-				.T2(T2),
-				.T3(T3),
-				.T4(T4), 
-				.P(P),       
-				.RAw(RAw),  
-				.EAw(EAw), 
-				.DAw(DAw),
-				.DSTPw(DSTPw),
-				.SW_LOC(SW_LOC),
-				.TOPOLOGY(TOPOLOGY),
-				.ROUTE_NAME(ROUTE_NAME),
-				.ROUTE_TYPE(ROUTE_TYPE)
-			)
-			lk_routing
-			(
-				.current_r_addr(current_r_addr),
-				.neighbors_r_addr(neighbors_r_addr),
-				.dest_e_addr(dest_e_addr_in),
-				.src_e_addr(src_e_addr_in),
-				.destport_encoded(destport_in_encoded),
-				.lkdestport_encoded(lk_destination_in_encoded),
-				.reset(reset),
-				.clk(clk)
-			);
-		end // unicast				
-			
-	endgenerate    
-
-	
-
-	header_flit_update_lk_route_ovc #(
-		.NOC_ID(NOC_ID),
-		.P(P)    
-	) the_flit_update (
-		.flit_in (buffer_out),
-		.flit_out (flit_out),
-		.vc_num_in(ivc_num_getting_sw_grant),
-		.lk_dest_all_in (lk_destination_encoded),
-		.assigned_ovc_num (assigned_ovc_num),
-		.any_ivc_sw_request_granted(any_ivc_sw_request_granted),
-		.lk_dest_not_registered(lk_destination_in_encoded),
-		.sel (sel),
-		.reset (reset),
-		.clk (clk)
-	);
-    		
-   
-	//synthesis translate_off
-	//synopsys  translate_off
-	generate 
-	if(DEBUG_EN) begin :debg	
-		
-		always @ (posedge clk) begin			
-			if((|vsa_ctrl_in.ivc_num_getting_sw_grant)  & (|ssa_ctrl_in.ivc_num_getting_sw_grant))begin 
-				$display("%t: ERROR: VSA/SSA conflict: an input port cannot get both sva and ssa grant at the same time %m",$time);
-				$finish;
-			end			
-		end//always
-		
-		for (i=0;i<V;i=i+1)begin : V_       
-		always @ (posedge clk) begin
-			if(vsa_ctrl_in.ivc_num_getting_ovc_grant[i] | ssa_ctrl_in.ivc_num_getting_ovc_grant[i] | (smart_ctrl_in.ivc_num_getting_ovc_grant[i] & (PCK_TYPE == "MULTI_FLIT"))  )begin 
-				if( ~ $onehot (mux_out[i])) begin 
-					$display("%t: ERROR: granted OVC num is not onehot coded %b: %m",$time,mux_out[i]);
-					$finish;
-				end
-			end					
-			if( ~ $onehot0( {vsa_ctrl_in.ivc_num_getting_ovc_grant[i],ssa_ctrl_in.ivc_num_getting_ovc_grant[i],(smart_ctrl_in.ivc_num_getting_ovc_grant[i]&& (PCK_TYPE == "MULTI_FLIT"))})) begin 
-				$display("%t: ERROR: ivc num %d getting more than one ovc grant from VSA,SSA,SMART: %m",$time,i);
-				$finish;
-			end		
-		end//always
-		
-		
-		
-		always @(posedge clk) begin
-			if((dest_port [(i+1)*P_1-1 : i*P_1] == {P_1{1'b0}})  && (ivc_request[i]==1'b1)) begin 
-				$display ("%t: ERROR: The destination port is not set for an active IVC request: %m \n",$time);
-				$finish;
-			end
-		end		
-		end//for
-		
-		/* verilator lint_off WIDTH */  
-		if (( TOPOLOGY == "RING" || TOPOLOGY == "LINE" || TOPOLOGY == "MESH" || TOPOLOGY == "TORUS") && CAST_TYPE== "UNICAST") begin : mesh_based
-		/* verilator lint_on WIDTH */  
-
-				debug_mesh_tori_route_ckeck #(
-						.T1(T1),
-						.T2(T2),
-						.T3(T3),
-						.ROUTE_TYPE(ROUTE_TYPE),
-						.V(V),
-						.AVC_ATOMIC_EN(AVC_ATOMIC_EN),
-						.SW_LOC(SW_LOC),
-						.ESCAP_VC_MASK(ESCAP_VC_MASK),
-						.TOPOLOGY(TOPOLOGY),
-						.DSTPw(DSTPw),
-						.RAw(RAw),
-						.EAw(EAw)
-					)
-					route_ckeck
-					(
-						.reset(reset),
-						.clk(clk),
-						.hdr_flg_in(hdr_flg_in),
-						.flit_in_wr(flit_in_wr),
-						.vc_num_in(vc_num_in),
-						.flit_is_tail(flit_is_tail),
-						.ivc_num_getting_sw_grant(ivc_num_getting_sw_grant),
-						.current_r_addr(current_r_addr),
-						.dest_e_addr_in(dest_e_addr_in),
-						.src_e_addr_in(src_e_addr_in),
-						.destport_in(destport_in)      
-					);   
-		end//mesh  
-	end//DEBUG_EN 
-	endgenerate 
-		                                 
-	`ifdef MONITORE_PATH     
-		genvar j;
-		reg[V-1 :0] t1;
-		generate
-			for (j=0;j<V;j=j+1)begin : lp        
-				always @(posedge clk) begin
-					if(`pronoc_reset)begin 
-						t1[j]<=1'b0;               
-					end else begin 
-						if(flit_in_wr >0 && vc_num_in[j] && t1[j]==0)begin 
-							$display("%t : Parser:current_r=%h, class_in=%h, destport_in=%h, dest_e_addr_in=%h, src_e_addr_in=%h, vc_num_in=%h,hdr_flit_wr=%h, hdr_flg_in=%h,tail_flg_in=%h ",$time,current_r_addr, class_in, destport_in, dest_e_addr_in, src_e_addr_in, vc_num_in,hdr_flit_wr, hdr_flg_in,tail_flg_in);
-							t1[j]<=1;
-						end           
-					end
-				end
-			end
-		endgenerate
-	`endif
-	// synopsys  translate_on   
-	// synthesis translate_on
-	 	
-			
-			
-
+        always @ (posedge clk) begin
+            if((|vsa_ctrl_in.ivc_num_getting_sw_grant)  & (|ssa_ctrl_in.ivc_num_getting_sw_grant))begin
+                $display("%t: ERROR: VSA/SSA conflict: an input port cannot get both sva and ssa grant at the same time %m",$time);
+                $finish;
+            end
+        end//always
+        
+        for (i=0;i<V;i=i+1)begin : V_
+            always @ (posedge clk) begin
+                if(vsa_ctrl_in.ivc_num_getting_ovc_grant[i] | ssa_ctrl_in.ivc_num_getting_ovc_grant[i] | (smart_ctrl_in.ivc_num_getting_ovc_grant[i] & (PCK_TYPE == "MULTI_FLIT"))  )begin 
+                    if( ~ $onehot (mux_out[i])) begin 
+                        $display("%t: ERROR: granted OVC num is not onehot coded %b: %m",$time,mux_out[i]);
+                        $finish;
+                    end
+                end
+                if( ~ $onehot0( {vsa_ctrl_in.ivc_num_getting_ovc_grant[i],ssa_ctrl_in.ivc_num_getting_ovc_grant[i],(smart_ctrl_in.ivc_num_getting_ovc_grant[i]&& (PCK_TYPE == "MULTI_FLIT"))})) begin 
+                    $display("%t: ERROR: ivc num %d getting more than one ovc grant from VSA,SSA,SMART: %m",$time,i);
+                    $finish;
+                end
+            end//always
+            
+            always @(posedge clk) begin
+                if((dest_port [(i+1)*P_1-1 : i*P_1] == {P_1{1'b0}})  && (ivc_request[i]==1'b1)) begin 
+                    $display ("%t: ERROR: The destination port is not set for an active IVC request: %m \n",$time);
+                    $finish;
+                end
+            end
+        end//for
+        if (IS_REGULAR_TOPO & IS_UNICAST) begin : mesh_based
+            
+            debug_regular_topo_route_ckeck #(
+                .SW_LOC(SW_LOC)
+            ) route_ckeck (
+                .reset(reset),
+                .clk(clk),
+                .hdr_flg_in(flit_in.hdr_flag),
+                .flit_in_wr(flit_in_wr),
+                .vc_num_in(flit_in.vc),
+                .flit_is_tail(flit_is_tail),
+                .ivc_num_getting_sw_grant(ivc_num_getting_sw_grant),
+                .current_r_addr(current_r_addr),
+                .dest_e_addr_in(hdr_flit_i.dest_e_addr),
+                .src_e_addr_in(hdr_flit_i.src_e_addr),
+                .destport_in(hdr_flit_i.destport)
+            );
+        end//mesh
+        if (PORT_IVC != V) begin : hetero
+            always @(posedge clk) begin
+                if (flit_in_wr &  (|flit_in.vc & ~hetero_ovc_unary(router_info.router_id , SW_LOC))) begin
+                    $display("%t: ERROR: Input port supports %0d VCs, but received a flit targeting an out-of-bound VC: %b. Module: %m\n", 
+                    $time, PORT_IVC, flit_in.vc[V-1 : PORT_IVC]);
+                    $finish;
+                end
+            end
+        end // hetero
+    end//DEBUG_EN
+    
+    `ifdef MONITORE_PATH
+    genvar j;
+    reg[V-1 :0] t1;
+    for (j=0;j<V;j=j+1)begin : lp
+        always @(posedge clk) begin
+            if(`pronoc_reset)begin
+                t1[j]<=1'b0;
+            end else begin
+                if(flit_in_wr > 0 && flit_in.vc[j] && t1[j]==0)begin
+                    $display("%t : Parser:current_r=%h, hdr_info:%p, vc_num_in=%h,hdr_flit_wr=%h",$time,current_r_addr, hdr_flit_i, flit_in.vc,hdr_flit_wr);
+                    t1[j]<=1;
+                end
+            end
+        end
+    end
+    `endif//MONITORE_PATH
+    endgenerate
+`endif// SIMULATION
 endmodule
 
 
-
-
-
 // decode and mask the destination port according to routing algorithm and topology
 module destp_generator #(
-	parameter TOPOLOGY="MESH",
-	parameter ROUTE_NAME="XY",
-	parameter ROUTE_TYPE="DETERMINISTIC",
-	parameter T1=3,
-	parameter NL=1,
-	parameter P=5,
-	parameter DSTPw=4,
-	parameter PLw=1,
-	parameter PPSw=4,
-	parameter SW_LOC=0,
-	parameter SELF_LOOP_EN="NO",
-	parameter CAST_TYPE = "UNICAST"
-
-)
-(
-	destport_one_hot,
-	dest_port_encoded,             
-	dest_port_out,   
-	endp_localp_num,
-	swap_port_presel,
-	port_pre_sel,
-	odd_column
+    parameter P=5,
+    parameter SW_LOC=0
+)(
+    destport_one_hot,
+    dest_port_encoded,
+    dest_port_out,
+    endp_localp_num,
+    swap_port_presel,
+    port_pre_sel,
+    odd_column
 );
-
-	localparam P_1= ( SELF_LOOP_EN=="NO")?  P-1 : P;
-	input [DSTPw-1 : 0]  dest_port_encoded;             
-	input [PLw-1 : 0] endp_localp_num;
-	output [P_1-1: 0] dest_port_out;  
-	output [P-1 : 0] destport_one_hot;
-	input             swap_port_presel;
-	input  [PPSw-1 : 0] port_pre_sel;
-	input odd_column;
-    
-	generate
-		
-	/* verilator lint_off WIDTH */    
-	if(CAST_TYPE!= "UNICAST") begin : muticast
-	/* verilator lint_on WIDTH */
-		// destination port is not coded for multicast/broadcast
-		if( SELF_LOOP_EN=="NO") begin : nslp
-			remove_sw_loc_one_hot #(
-					.P(P),
-					.SW_LOC(SW_LOC)
-				)
-				remove_sw_loc
-				(
-					.destport_in(dest_port_encoded),
-					.destport_out(dest_port_out)
-				);
-		end else begin : slp		
-			assign dest_port_out = dest_port_encoded;
-		end
-	/* verilator lint_off WIDTH */
-	end else if(TOPOLOGY == "FATTREE" ) begin : fat
-	/* verilator lint_on WIDTH */
-			fattree_destp_generator #(
-				.K(T1),
-				.P(P),
-				.SW_LOC(SW_LOC),
-				.DSTPw(DSTPw),
-				.SELF_LOOP_EN(SELF_LOOP_EN)
-				)
-			destp_generator
-			(
-				.dest_port_in_encoded(dest_port_encoded),
-				.dest_port_out(dest_port_out)
-			);
-	/* verilator lint_off WIDTH */ 
-	end else  if (TOPOLOGY == "TREE") begin :tree
-	/* verilator lint_on WIDTH */
-		tree_destp_generator #(
-			.K(T1),
-			.P(P),
-			.SW_LOC(SW_LOC),
-			.DSTPw(DSTPw),
-			.SELF_LOOP_EN(SELF_LOOP_EN)
-		)
-		destp_generator
-		(
-			.dest_port_in_encoded(dest_port_encoded),
-			.dest_port_out(dest_port_out)
-		);    
-	/* verilator lint_off WIDTH */
-	end else if(TOPOLOGY == "RING" || TOPOLOGY == "LINE" || TOPOLOGY == "MESH"|| TOPOLOGY == "TORUS") begin : mesh
-		/* verilator lint_on WIDTH */
-		mesh_torus_destp_generator #(
-			.TOPOLOGY(TOPOLOGY),
-			.ROUTE_NAME(ROUTE_NAME),
-			.ROUTE_TYPE(ROUTE_TYPE),
-			.P(P),
-			.DSTPw(DSTPw),
-			.NL(NL),
-			.PLw(PLw),
-			.PPSw(PPSw),
-			.SW_LOC(SW_LOC),
-			.SELF_LOOP_EN(SELF_LOOP_EN)
-		)
-		destp_generator
-		(
-			.dest_port_coded(dest_port_encoded),
-			.endp_localp_num(endp_localp_num),
-			.dest_port_out(dest_port_out),
-			.swap_port_presel(swap_port_presel),
-			.port_pre_sel(port_pre_sel),
-			.odd_column(odd_column)// only needed for odd even routing
-		);
-		/* verilator lint_off WIDTH */
-	end else if (TOPOLOGY == "FMESH") begin :fmesh
-		/* verilator lint_on WIDTH */
-		fmesh_destp_generator  #(
-			.ROUTE_NAME(ROUTE_NAME),
-			.ROUTE_TYPE(ROUTE_TYPE),
-			.P(P),
-			.DSTPw(DSTPw),
-			.NL(NL),
-			.PLw(PLw),
-			.PPSw(PPSw),
-			.SW_LOC(SW_LOC),
-			.SELF_LOOP_EN(SELF_LOOP_EN)
-			)
-			destp_generator
-			(
-				.dest_port_coded(dest_port_encoded),
-				.endp_localp_num(endp_localp_num),
-				.dest_port_out(dest_port_out),
-				.swap_port_presel(swap_port_presel),
-				.port_pre_sel(port_pre_sel),
-				.odd_column(odd_column)				// only needed for odd even routing
-			);
-	end else begin :custom
-    
-		custom_topology_destp_decoder #(
-			.ROUTE_TYPE(ROUTE_TYPE),
-			.DSTPw(DSTPw),
-			.P(P),
-			.SW_LOC(SW_LOC),
-			.SELF_LOOP_EN(SELF_LOOP_EN)
-		)
-		destp_generator
-		(
-			.dest_port_in_encoded(dest_port_encoded),
-			.dest_port_out(dest_port_out)
-		);    
-	end
-	
-	if(SELF_LOOP_EN=="NO") begin : nslp
-		add_sw_loc_one_hot #(
-				.P(P),
-				.SW_LOC(SW_LOC)    
-		)add
-		(
-				.destport_in(dest_port_out),
-				.destport_out(destport_one_hot)
-		);
-		
-	end else begin : slp
-		assign destport_one_hot = dest_port_out;		
-	end
-				
-	endgenerate
-    
-	
-	
-		
-    
-    
+    import pronoc_pkg::*;
+    localparam
+        ELw = log2(T3),
+        Pw  = log2(P),
+        PLw = (IS_FMESH) ? Pw : ELw,
+        P_1 = (SELF_LOOP_EN )?  P : P-1;
     
+    input [DSTPw-1 : 0]  dest_port_encoded;
+    input [PLw-1 : 0] endp_localp_num;
+    output [P_1-1: 0] dest_port_out;
+    output logic [P-1 : 0] destport_one_hot;
+    input  swap_port_presel;
+    input  [PPSw-1 : 0] port_pre_sel;
+    input odd_column;
     
+    generate
+    if( ~IS_UNICAST ) begin : muticast
+        destport_non_selfloop_fix #(
+            .SELF_LOOP_EN(SELF_LOOP_EN),
+            .P(P),
+            .SW_LOC(SW_LOC)
+        ) fix_sw_loc (
+            .destport_in(dest_port_encoded),
+            .destport_out(dest_port_out)
+        );
+    end else if( IS_FATTREE ) begin : fat
+        fattree_destp_generator #(
+            .K(T1),
+            .P(P),
+            .SW_LOC(SW_LOC),
+            .DSTPw(DSTPw),
+            .SELF_LOOP_EN(SELF_LOOP_EN)
+            )
+        destp_generator
+        (
+            .dest_port_in_encoded(dest_port_encoded),
+            .dest_port_out(dest_port_out)
+        );
+    end else  if ( IS_TREE ) begin :tree
+        tree_destp_generator #(
+            .K(T1),
+            .P(P),
+            .SW_LOC(SW_LOC),
+            .DSTPw(DSTPw),
+            .SELF_LOOP_EN(SELF_LOOP_EN)
+        ) destp_generator (
+            .dest_port_in_encoded(dest_port_encoded),
+            .dest_port_out(dest_port_out)
+        );
+    end else if( IS_REGULAR_TOPO ) begin : regular
+        regular_topo_destp_generator #(
+            .P(P),
+            .PLw(PLw),
+            .SW_LOC(SW_LOC)
+        ) destp_generator (
+            .dest_port_coded(dest_port_encoded),
+            .endp_localp_num(endp_localp_num),
+            .dest_port_out(dest_port_out),
+            .swap_port_presel(swap_port_presel),
+            .port_pre_sel(port_pre_sel),
+            .odd_column(odd_column)// only needed for odd even routing
+        );
+    end else if ( IS_FMESH ) begin :fmesh
+        fmesh_destp_generator  #(
+            .P(P),
+            .PLw(PLw),
+            .SW_LOC(SW_LOC)
+        ) destp_generator (
+            .dest_port_coded(dest_port_encoded),
+            .endp_localp_num(endp_localp_num),
+            .dest_port_out(dest_port_out),
+            .swap_port_presel(swap_port_presel),
+            .port_pre_sel(port_pre_sel),
+            .odd_column(odd_column) // only needed for odd even routing
+        );
+    end else begin :custom
+        custom_topology_destp_decoder #(
+            .P(P),
+            .SW_LOC(SW_LOC)
+        ) destp_generator (
+            .dest_port_in_encoded(dest_port_encoded),
+            .dest_port_out(dest_port_out)
+        );
+    end
+    endgenerate
+    //add_sw_loc_one_hot
+    always_comb begin 
+        if (SELF_LOOP_EN == 0) begin
+            for(int k=0;k<P; k++) begin 
+                if (k>SW_LOC) destport_one_hot[k] = dest_port_out[k-1];
+                else if (k==SW_LOC) destport_one_hot[k] = 1'b0;
+                else destport_one_hot[k] = dest_port_out[k];
+            end//for 
+        end else destport_one_hot[P_1-1 : 0] = dest_port_out;
+    end//always
 endmodule
 
 /******************
  *   custom_topology_destp_decoder
  * ***************/
-
-
 module custom_topology_destp_decoder #(
-		parameter ROUTE_TYPE="DETERMINISTIC",
-		parameter DSTPw=4,
-		parameter P=5,
-		parameter SW_LOC=0,
-		parameter SELF_LOOP_EN="NO"
-		)(
-		dest_port_in_encoded,
-		dest_port_out
-		);
-  
-	localparam
-		P_1 = ( SELF_LOOP_EN=="NO")?  P-1 : P,
-		MAXW =2**DSTPw;
-  
-	input  [DSTPw-1 : 0] dest_port_in_encoded;
-	output [P_1-1 : 0] dest_port_out;
-      
-   
-	wire [MAXW-1 : 0] dest_port_one_hot;
+    parameter P=5,
+    parameter SW_LOC=0
+)(
+    dest_port_in_encoded,
+    dest_port_out
+);
+    
+    import pronoc_pkg::*;
+    localparam
+        P_1 = (SELF_LOOP_EN )?  P : P-1,
+        MAXW =2**DSTPw;
+    
+    input  [DSTPw-1 : 0] dest_port_in_encoded;
+    output [P_1-1 : 0] dest_port_out;
+    
+    logic [MAXW-1 : 0] dest_port_one_hot;
+    //bin_to_one_hot
+    always_comb begin
+        dest_port_one_hot = {MAXW{1'b0}};
+        dest_port_one_hot[dest_port_in_encoded] = 1'b1;
+    end
+    
+    destport_non_selfloop_fix #(
+        .SELF_LOOP_EN(SELF_LOOP_EN),
+        .P(P),
+        .SW_LOC(SW_LOC)
+    ) remove_sw_loc (
+        .destport_in(dest_port_one_hot[P-1 : 0]),
+        .destport_out(dest_port_out)
+    );
     
-	bin_to_one_hot #(
-			.BIN_WIDTH(DSTPw),
-			.ONE_HOT_WIDTH(MAXW)
-		)
-		conv
-		(
-			.bin_code(dest_port_in_encoded),
-			.one_hot_code(dest_port_one_hot)
-		);
-	generate
-	if( SELF_LOOP_EN=="NO") begin : nslp
-	remove_sw_loc_one_hot #(
-			.P(P),
-			.SW_LOC(SW_LOC)
-		)
-		remove_sw_loc
-		(
-			.destport_in(dest_port_one_hot[P-1 : 0]),
-			.destport_out(dest_port_out)
-		);
-	end else begin : slp		
-		assign dest_port_out = dest_port_one_hot;
-	end
-	endgenerate
-	//synthesis translate_off 
-	//synopsys  translate_off
-   
-	initial begin
-		if( ROUTE_TYPE != "DETERMINISTIC") begin
-			$display("%t: ERROR: Custom topologies can only support deterministic routing in the current version of ProNoC",$time);
-			$finish; 
-		end
-	end
-   
-   
-	//synopsys  translate_on
-	//synthesis translate_on 
-   
+    `ifdef SIMULATION
+    initial begin
+        if( ROUTE_TYPE != "DETERMINISTIC") begin
+            $display("%t: ERROR: Custom topologies can only support deterministic routing in the current version of ProNoC",$time);
+            $finish;
+        end
+    end
+    `endif
 endmodule
diff --git a/mpsoc/rtl/src_noc/mesh_3d_top.sv b/mpsoc/rtl/src_noc/mesh_3d_top.sv
new file mode 100644
index 0000000..43048e4
--- /dev/null
+++ b/mpsoc/rtl/src_noc/mesh_3d_top.sv
@@ -0,0 +1,157 @@
+`include "pronoc_def.v"
+/**********************************************************************
+**    File:  mesh_cluster.sv
+**    
+**    Copyright (C) 2014-2017  Alireza Monemi
+**    
+**    This file is part of ProNoC 
+**
+**    ProNoC ( stands for Prototype Network-on-chip)  is free software: 
+**    you can redistribute it and/or modify it under the terms of the GNU
+**    Lesser General Public License as published by the Free Software Foundation,
+**    either version 2 of the License, or (at your option) any later version.
+**
+**     ProNoC is distributed in the hope that it will be useful, but WITHOUT
+**     ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+**     or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
+**     Public License for more details.
+**
+**     You should have received a copy of the GNU Lesser General Public
+**     License along with ProNoC. If not, see <http:**www.gnu.org/licenses/>.
+**
+**
+**
+**    Description: 
+**    A `mesh_cluster` refers to a group of interconnected routers arranged in a **3D Mesh topology** 
+**    within a larger **Multi-Mesh NoC** for chiplets. In this architecture, each chiplet functions 
+**    as an independent cluster of nodes, featuring its own local mesh-based communication network.
+**
+**    Each router in the `mesh_cluster` drives two I/O channels:
+**    1. **Endpoint Channel** – Connects to processing elements (PEs) or memory endpoints.
+**    2. **Vertical Link Channel** – Facilitates inter-cluster communication.
+**
+**    If an endpoint or vertical link is not present in the target Multi-Mesh topology, 
+**    the corresponding input is tied to **ground**, enabling synthesis optimizations 
+**    that effectively remove unused logic.
+**
+***************************************/
+
+module mesh_3d_noc_top (
+    reset,
+    clk,
+    chan_in_all,
+    chan_out_all,
+    router_event
+);
+    import pronoc_pkg::*;
+    input   clk,reset;
+    //Endpoints ports 
+    input   smartflit_chanel_t chan_in_all  [NE-1 : 0];
+    output  smartflit_chanel_t chan_out_all [NE-1 : 0];
+    //Events
+    output  router_event_t  router_event [NR-1 : 0][MAX_P-1 : 0];
+    
+    //indididual routers interconnect ports
+    smartflit_chanel_t router_chan_in   [NZ-1:0][NY-1:0][NX-1:0][MAX_P-1:0];
+    smartflit_chanel_t router_chan_out  [NZ-1:0][NY-1:0][NX-1:0][MAX_P-1:0];
+    //Unused Input channels are connected to ground
+    smartflit_chanel_t is_grounded;
+    assign  is_grounded= {SMARTFLIT_CHANEL_w{1'b0}};
+    
+    regular_topo_router_addr_t current_r_addr [NR-1:0];
+    regular_topo_endp_addr_t endp_addr [NE-1:0];
+    router_config_t router_config_in [NR-1 : 0];
+    
+    genvar x,y,z,l;
+    generate
+    if(IS_MESH_3D) begin 
+    for (z=0; z<NZ; z=z+1) begin: Z_
+        for (y=0; y<NY; y=y+1) begin: Y_
+            for (x=0; x<NX; x=x+1) begin: X_
+                localparam 
+                    RID =z*(NX * NY) + (y * NX) + x,
+                    XP1 = (x+1)%NX,
+                    XM1 = (x-1+NX)%NX,
+                    YP1 = (y+1)%NY,
+                    YM1 = (y-1+NY)%NY,
+                    ZP1 = (z+1)%NZ,
+                    ZM1 = (z-1+NZ)%NZ;
+                assign current_r_addr[RID ]='{x:x,y:y,z:z};
+                router_top #(
+                    .ROUTER_ID(RID),
+                    .P(MAX_P)
+                ) the_router (
+                    .router_config_in(router_config_in[RID]),
+                    .chan_in(router_chan_in [z][y][x]),
+                    .chan_out(router_chan_out[z][y][x]),
+                    .router_event(router_event[RID] ),
+                    .clk(clk),
+                    .reset(reset)
+                );
+                assign router_config_in[RID].router_addr=current_r_addr[RID];
+                assign router_config_in[RID].router_id=RID;
+                // **Mesh Interconnect Logic**
+                assign router_chan_in[z][y][x][EAST]  = (x < NX-1) ?
+                    router_chan_out[z][y][XP1][WEST]  : is_grounded;
+                assign router_chan_in[z][y][x][NORTH] = (y > 0   ) ?
+                    router_chan_out[z][YM1][x][SOUTH] : is_grounded;
+                assign router_chan_in[z][y][x][WEST]  =  (x > 0  ) ?
+                    router_chan_out[z][y][XM1][EAST]  : is_grounded;
+                assign router_chan_in[z][y][x][SOUTH] = (y < NY-1) ?
+                    router_chan_out[z][YP1][x][NORTH] : is_grounded;
+                assign router_chan_in[z][y][x][UP]    = (z < NZ-1) ?
+                    router_chan_out[ZP1][y][x][DOWN]  : is_grounded;
+                assign router_chan_in[z][y][x][DOWN]  = (z > 0   ) ?
+                    router_chan_out[ZM1][y][x][UP]    : is_grounded;
+                //endpoint connections
+                for (l=0;l<NL;l++) begin 
+                    localparam EID = RID*NL+l;
+                    localparam LOCALP = (l==0) ? l : l + R2R_CHANELS_REGULAR; // first local port is connected to router port 0. The rest are connected at the end  
+                    assign endp_addr[EID]='{x:x,y:y,z:z,l:l};
+                    assign router_chan_in [z][y][x][LOCALP] = chan_in_all [EID];
+                    assign chan_out_all [EID] = router_chan_out [z][y][x][LOCALP];
+                    assign router_config_in[RID].endp_addrs[(l+1)*EAw -1 :  l*EAw] = EAw'(endp_addr[EID]);
+                    assign router_config_in[RID].endp_ids[(l+1)*NEw -1 :  l*NEw] = NEw'(EID);
+                end
+            end//X
+        end//Y
+    end//Z
+    end
+    endgenerate
+endmodule
+
+
+
+module mesh_3d_route_xyz (
+    current_router_addr_i,
+    dest_router_addr_i,
+    destport
+);
+    import pronoc_pkg::*;
+    input regular_topo_router_addr_t current_router_addr_i;
+    input regular_topo_router_addr_t dest_router_addr_i;
+    output logic [DSTPw-1 : 0] destport;
+    
+    // Define state type using typedef
+    typedef enum logic [2:0] {
+        MASS  = 3'b001,
+        LESS  = 3'b010,
+        EQUAL = 3'b100
+    } state_t;
+    state_t Dx,Dy,Dz;
+    assign  Dx = (dest_router_addr_i.x > current_router_addr_i.x)? MASS:(dest_router_addr_i.x == current_router_addr_i.x)?EQUAL : LESS;
+    assign  Dy = (dest_router_addr_i.y > current_router_addr_i.y)? MASS:(dest_router_addr_i.y == current_router_addr_i.y)?EQUAL : LESS;
+    assign  Dz = (dest_router_addr_i.z > current_router_addr_i.z)? MASS:(dest_router_addr_i.z == current_router_addr_i.z)?EQUAL : LESS;
+    
+    always_comb begin
+        destport=0;
+        if(Dx==MASS) destport =DSTPw'(EAST);
+        else if(Dx==LESS) destport =DSTPw'(WEST);
+        else if(Dy==MASS) destport =DSTPw'(SOUTH);
+        else if(Dy==LESS) destport =DSTPw'(NORTH);
+        else if(Dz==MASS) destport =DSTPw'(UP);
+        else if(Dz==LESS) destport =DSTPw'(DOWN);
+        else destport =  DSTPw'(LOCAL);
+    end
+endmodule
+
diff --git a/mpsoc/rtl/src_noc/mesh_torus.sv b/mpsoc/rtl/src_noc/mesh_torus.sv
index f0e9896..5b40cd1 100755
--- a/mpsoc/rtl/src_noc/mesh_torus.sv
+++ b/mpsoc/rtl/src_noc/mesh_torus.sv
@@ -1,56 +1,39 @@
 `include "pronoc_def.v"
-
 /**********************************************************************
-**	File:  mesh_torus.v
+**    File: regular_topo.v
 **    
-**	Copyright (C) 2014-2017  Alireza Monemi
+**    Copyright (C) 2014-2017  Alireza Monemi
 **    
-**	This file is part of ProNoC 
+**    This file is part of ProNoC 
 **
-**	ProNoC ( stands for Prototype Network-on-chip)  is free software: 
-**	you can redistribute it and/or modify it under the terms of the GNU
-**	Lesser General Public License as published by the Free Software Foundation,
-**	either version 2 of the License, or (at your option) any later version.
+**    ProNoC ( stands for Prototype Network-on-chip)  is free software: 
+**    you can redistribute it and/or modify it under the terms of the GNU
+**    Lesser General Public License as published by the Free Software Foundation,
+**    either version 2 of the License, or (at your option) any later version.
 **
-** 	ProNoC is distributed in the hope that it will be useful, but WITHOUT
-** 	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
-** 	or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
-** 	Public License for more details.
+**     ProNoC is distributed in the hope that it will be useful, but WITHOUT
+**     ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+**     or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
+**     Public License for more details.
 **
-** 	You should have received a copy of the GNU Lesser General Public
-** 	License along with ProNoC. If not, see <http:**www.gnu.org/licenses/>.
+**     You should have received a copy of the GNU Lesser General Public
+**     License along with ProNoC. If not, see <http:**www.gnu.org/licenses/>.
 **
 **
-**	Description: 
-**		
+**    Description: 
+**        
 **
 ***************************************/
 
 
-
-
-/*****************************************
-
-pre-sel[xy]
-    y
-1   |   3
-    |
- -------x
-0   |   2
-    |
-
-*****************************************/
-
-
-module  mesh_torus_vc_alloc_request_gen_adaptive #(
-    parameter ROUTE_TYPE =  "FULL_ADAPTIVE",    // "FULL_ADAPTIVE", "PAR_ADAPTIVE"  
-    parameter V = 4,
-    parameter DSTPw=4,
-    parameter SSA_EN ="NO",
-    parameter PPSw=4,
-    parameter [V-1  :   0] ESCAP_VC_MASK = 4'b1000   // mask scape vc, valid only for full adaptive       
-   
-)(
+/**************************
+*        pre-sel[xy]
+*            y
+*        1   |   3
+*        ---------x
+*        0   |   2
+***************************/
+module  regular_topo_vc_alloc_request_gen_adaptive (
     ovc_avalable_all,
     dest_port_coded_all,
     candidate_ovc_all,
@@ -64,234 +47,179 @@ module  mesh_torus_vc_alloc_request_gen_adaptive #(
     ssa_ivc_num_getting_ovc_grant_all,
     sel,
     reset,
-    clk
-    
+    clk    
 );
-    localparam  P = 5;
-    
-    localparam  P_1     =   P-1,
-                PV      =   V       *   P,
-                PVV     =   PV      *  V,
-                VP_1    =   V       *   P_1,
-                PVDSTPw = PV * DSTPw;
-                
-     localparam LOCAL   =   3'd0,  
-                EAST    =   3'd1, 
-                NORTH   =   3'd2,  
-                WEST    =   3'd3,  
-                SOUTH   =   3'd4;  
-
-    input   [PV-1       :   0]  ovc_avalable_all;
-    input   [PVDSTPw-1  :   0]  dest_port_coded_all;
-    input   [PV-1       :   0]  ivc_request_all;
-    input   [PV-1       :   0]  ovc_is_assigned_all;  
-    output  [PVV-1      :   0]  masked_ovc_request_all;
-    input   [PVV-1      :   0]  candidate_ovc_all;
-    input   [PPSw-1     :   0]  port_pre_sel;
-    output  [PV-1       :   0]  swap_port_presel;   
-    output  [PV-1       :   0]  sel;
+    import pronoc_pkg::*;
+    localparam  
+        P = 5,
+        P_1 = P-1,
+        PV = V * P,
+        PVV = PV * V,
+        VP_1 = V * P_1,
+        PVDSTPw = PV * DSTPw;
+        
+    input   [PV-1 : 0]  ovc_avalable_all;
+    input   [PVDSTPw-1 : 0]  dest_port_coded_all;
+    input   [PV-1 : 0]  ivc_request_all;
+    input   [PV-1 : 0]  ovc_is_assigned_all;  
+    output  [PVV-1 : 0]  masked_ovc_request_all;
+    input   [PVV-1 : 0]  candidate_ovc_all;
+    input   [PPSw-1 : 0]  port_pre_sel;
+    output  [PV-1 : 0]  swap_port_presel;   
+    output  [PV-1 : 0]  sel;
     output  [PVDSTPw-1 : 0] destport_clear_all;
     input   [PV-1 : 0] ivc_num_getting_ovc_grant; 
     input   [PV-1 : 0] ssa_ivc_num_getting_ovc_grant_all;       
     input                       reset,clk;  
     
-
-    wire    [PV-1       :   0]  non_assigned_ovc_request_all; 
-    wire    [PV-1       :   0]  y_evc_forbiden,x_evc_forbiden;
-    wire    [V-1        :   0]  ovc_avb_x_plus,ovc_avb_x_minus,ovc_avb_y_plus,ovc_avb_y_minus,ovc_avb_local;
-    wire    [VP_1-1     :   0]  ovc_avalable_perport            [P-1    :   0];
-    wire    [PPSw-1     :   0]  port_pre_sel_perport            [P-1    :   0];
-    wire    [PVV-1      :   0]  candidate_ovc_x_all, candidate_ovc_y_all;
-   
+    wire    [PV-1 : 0]  non_assigned_ovc_request_all; 
+    wire    [PV-1 : 0]  y_evc_forbiden,x_evc_forbiden;
+    wire    [V-1 : 0]  ovc_avb_x_plus,ovc_avb_x_minus,ovc_avb_y_plus,ovc_avb_y_minus,ovc_avb_local;
+    wire    [VP_1-1 : 0]  ovc_avalable_perport            [P-1 : 0];
+    wire    [PPSw-1 : 0]  port_pre_sel_perport            [P-1 : 0];
+    wire    [PVV-1 : 0]  candidate_ovc_x_all, candidate_ovc_y_all;
     
-    assign non_assigned_ovc_request_all =   ivc_request_all & ~ovc_is_assigned_all;   
+    assign non_assigned_ovc_request_all = ivc_request_all & ~ovc_is_assigned_all;   
     assign {ovc_avb_y_minus,ovc_avb_x_minus,ovc_avb_y_plus,ovc_avb_x_plus,ovc_avb_local} = ovc_avalable_all;
-
-    
-   
-        assign ovc_avalable_perport[LOCAL]  = {ovc_avb_x_plus,ovc_avb_x_minus,ovc_avb_y_plus,ovc_avb_y_minus};
-        assign ovc_avalable_perport[EAST]   = {ovc_avb_local,ovc_avb_x_minus,ovc_avb_y_plus,ovc_avb_y_minus};
-        assign ovc_avalable_perport[NORTH]  = {ovc_avb_x_plus,ovc_avb_x_minus,ovc_avb_local,ovc_avb_y_minus};
-        assign ovc_avalable_perport[WEST]   = {ovc_avb_x_plus,ovc_avb_local,ovc_avb_y_plus,ovc_avb_y_minus};
-        assign ovc_avalable_perport[SOUTH]  = {ovc_avb_x_plus,ovc_avb_x_minus,ovc_avb_y_plus,ovc_avb_local};
-    
-    
-    
-    assign port_pre_sel_perport[LOCAL]   = port_pre_sel;
-    assign port_pre_sel_perport[EAST]    = {2'b00,port_pre_sel[1:0]};
-    assign port_pre_sel_perport[NORTH]   = {1'b0,port_pre_sel[2],1'b0,port_pre_sel[0]};
-    assign port_pre_sel_perport[WEST]    = {port_pre_sel[3:2],2'b0};
-    assign port_pre_sel_perport[SOUTH]   = {port_pre_sel[3],1'b0,port_pre_sel[1],1'b0};
-    
-   
-    wire    [PV-1   :   0]  avc_unavailable; 
+    assign ovc_avalable_perport[LOCAL] = {ovc_avb_x_plus,ovc_avb_x_minus,ovc_avb_y_plus,ovc_avb_y_minus};
+    assign ovc_avalable_perport[EAST] = {ovc_avb_local,ovc_avb_x_minus,ovc_avb_y_plus,ovc_avb_y_minus};
+    assign ovc_avalable_perport[NORTH] = {ovc_avb_x_plus,ovc_avb_x_minus,ovc_avb_local,ovc_avb_y_minus};
+    assign ovc_avalable_perport[WEST] = {ovc_avb_x_plus,ovc_avb_local,ovc_avb_y_plus,ovc_avb_y_minus};
+    assign ovc_avalable_perport[SOUTH] = {ovc_avb_x_plus,ovc_avb_x_minus,ovc_avb_y_plus,ovc_avb_local};
+    assign port_pre_sel_perport[LOCAL] = port_pre_sel;
+    assign port_pre_sel_perport[EAST] = {2'b00,port_pre_sel[1:0]};
+    assign port_pre_sel_perport[NORTH] = {1'b0,port_pre_sel[2],1'b0,port_pre_sel[0]};
+    assign port_pre_sel_perport[WEST] = {port_pre_sel[3:2],2'b0};
+    assign port_pre_sel_perport[SOUTH] = {port_pre_sel[3],1'b0,port_pre_sel[1],1'b0};
+    
+    wire    [PV-1 : 0]  avc_unavailable; 
     genvar i;
     generate   
-    
-    
-    for(i=0;i< PV;i=i+1) begin :all_vc_loop
+    for(i=0;i< PV;i=i+1) begin : PV_
+        regular_topo_adaptive_avb_ovc_mux #(
+            .V(V)           
+        ) ovc_mux (
+            .ovc_avalable               (ovc_avalable_perport   [i/V]),
+            .sel                        (sel                    [i]),
+            .candidate_ovc_x            (candidate_ovc_x_all    [((i+1)*V)-1 : i*V]),
+            .candidate_ovc_y            (candidate_ovc_y_all    [((i+1)*V)-1 : i*V]),
+            .non_assigned_ovc_request   (non_assigned_ovc_request_all[i]),
+            .xydir                      (dest_port_coded_all     [((i+1)*DSTPw)-1 : ((i+1)*DSTPw)-2]),
+            .masked_ovc_request         (masked_ovc_request_all [((i+1)*V)-1 : i*V])
+        );
         
-       mesh_torus_adaptive_avb_ovc_mux #(
-       	.V(V)       	
-       )
-       the_adaptive_avb_ovc_mux
-       (
-       	.ovc_avalable               (ovc_avalable_perport   [i/V]),
-       	.sel                        (sel                    [i]),
-       	.candidate_ovc_x            (candidate_ovc_x_all    [((i+1)*V)-1 : i*V]),
-       	.candidate_ovc_y            (candidate_ovc_y_all    [((i+1)*V)-1 : i*V]),
-       	.non_assigned_ovc_request   (non_assigned_ovc_request_all[i]),
-       	.xydir                      (dest_port_coded_all     [((i+1)*DSTPw)-1 : ((i+1)*DSTPw)-2]),
-       	.masked_ovc_request         (masked_ovc_request_all [((i+1)*V)-1 : i*V])
-       );
-              
-        mesh_torus_port_selector #(
-	       .SW_LOC     (i/V),
-	       .PPSw(PPSw)
-        )
-        the_portsel
-        (
-	       .port_pre_sel       (port_pre_sel_perport[i/V]),
-	       .swap_port_presel   (swap_port_presel[i]),
-	       .sel                (sel[i]),
-	       .dest_port_in       (dest_port_coded_all[((i+1)*DSTPw)-1 : i*DSTPw]),
-	       .y_evc_forbiden     (y_evc_forbiden[i]),
-           .x_evc_forbiden     (x_evc_forbiden[i])
-	      );
-
-        mesh_tori_dspt_clear_gen #(
-        	.SSA_EN(SSA_EN),
-        	.DSTPw(DSTPw),
-        	.SW_LOC(i/V)
-        )
-        dspt_clear_gen
-        (
-        	.destport_clear(destport_clear_all[((i+1)*DSTPw)-1 : i*DSTPw]),
-        	.ivc_num_getting_ovc_grant(ivc_num_getting_ovc_grant[i]),
-        	.sel(sel[i]),
-        	.ssa_ivc_num_getting_ovc_grant(ssa_ivc_num_getting_ovc_grant_all[i])
-        );             	             
-	      	             
-	      
-	    /* verilator lint_off WIDTH */   
-        if(ROUTE_TYPE ==  "FULL_ADAPTIVE") begin: full_adpt
+        regular_topo_port_selector #(
+            .SW_LOC     (i/V)
+        ) the_portsel (
+            .port_pre_sel       (port_pre_sel_perport[i/V]),
+            .swap_port_presel   (swap_port_presel[i]),
+            .sel                (sel[i]),
+            .dest_port_in       (dest_port_coded_all[((i+1)*DSTPw)-1 : i*DSTPw]),
+            .y_evc_forbiden     (y_evc_forbiden[i]),
+            .x_evc_forbiden     (x_evc_forbiden[i])
+        );
+        
+        regular_topo_dspt_clear_gen #(
+            .SW_LOC(i/V)
+        ) dspt_clear_gen (
+            .destport_clear(destport_clear_all[((i+1)*DSTPw)-1 : i*DSTPw]),
+            .ivc_num_getting_ovc_grant(ivc_num_getting_ovc_grant[i]),
+            .sel(sel[i]),
+            .ssa_ivc_num_getting_ovc_grant(ssa_ivc_num_getting_ovc_grant_all[i])
+        );                              
+        
+        /* verilator lint_off WIDTH */   
+        if(ROUTE_TYPE == "FULL_ADAPTIVE") begin: full_adpt
         /* verilator lint_on WIDTH */ 
-            assign candidate_ovc_y_all[((i+1)*V)-1 : i*V] =  (y_evc_forbiden[i]) ? candidate_ovc_all[((i+1)*V)-1 : i*V] & (~ESCAP_VC_MASK) :  candidate_ovc_all[((i+1)*V)-1 : i*V];
-            assign candidate_ovc_x_all[((i+1)*V)-1 : i*V] =  (x_evc_forbiden[i]) ? candidate_ovc_all[((i+1)*V)-1 : i*V] & (~ESCAP_VC_MASK) :  candidate_ovc_all[((i+1)*V)-1 : i*V];
+            assign candidate_ovc_y_all[((i+1)*V)-1 : i*V] = (y_evc_forbiden[i]) ? candidate_ovc_all[((i+1)*V)-1 : i*V] & (~ESCAP_VC_MASK) : candidate_ovc_all[((i+1)*V)-1 : i*V];
+            assign candidate_ovc_x_all[((i+1)*V)-1 : i*V] = (x_evc_forbiden[i]) ? candidate_ovc_all[((i+1)*V)-1 : i*V] & (~ESCAP_VC_MASK) : candidate_ovc_all[((i+1)*V)-1 : i*V];
             assign avc_unavailable[i] = (masked_ovc_request_all [((i+1)*V)-1 : i*V] & ~ESCAP_VC_MASK) == {V{1'b0}};
             
-                        
-            mesh_torus_swap_port_presel_gen #(
-                .V(V),
-                .ESCAP_VC_MASK(ESCAP_VC_MASK),       
+            regular_topo_swap_port_presel_gen #(
                 .VC_NUM(i)
-            )           
-            the_swap_port_presel
-            (
-            	.avc_unavailable(avc_unavailable[i]),
-            	.y_evc_forbiden(y_evc_forbiden[i]),
-            	.x_evc_forbiden(x_evc_forbiden[i]),
-            	.non_assigned_ovc_request(non_assigned_ovc_request_all[i]),
-            	.sel(sel[i]),
-            	.clk(clk),
-            	.reset(reset),
-            	.swap_port_presel(swap_port_presel[i])
+            ) swap_presel (
+                .avc_unavailable(avc_unavailable[i]),
+                .y_evc_forbiden(y_evc_forbiden[i]),
+                .x_evc_forbiden(x_evc_forbiden[i]),
+                .non_assigned_ovc_request(non_assigned_ovc_request_all[i]),
+                .sel(sel[i]),
+                .clk(clk),
+                .reset(reset),
+                .swap_port_presel(swap_port_presel[i])
             );
-                       
-            
         end else begin : partial_adpt
-            assign candidate_ovc_y_all[((i+1)*V)-1 : i*V] =   candidate_ovc_all [((i+1)*V)-1 : i*V];
-            assign candidate_ovc_x_all[((i+1)*V)-1 : i*V] =   candidate_ovc_all [((i+1)*V)-1 : i*V];
+            assign candidate_ovc_y_all[((i+1)*V)-1 : i*V] = candidate_ovc_all [((i+1)*V)-1 : i*V];
+            assign candidate_ovc_x_all[((i+1)*V)-1 : i*V] = candidate_ovc_all [((i+1)*V)-1 : i*V];
             assign swap_port_presel[i]=1'b0;
             assign avc_unavailable[i]=1'b0;
-            
         end// ROUTE_TYPE
     end//for    
-     
 endgenerate
 endmodule
 
 
-
-module mesh_tori_dspt_clear_gen #(
-    parameter SSA_EN="YES",
-    parameter DSTPw =4,
+module regular_topo_dspt_clear_gen #(
     parameter SW_LOC=0
-
 )(
     destport_clear,
     ivc_num_getting_ovc_grant,
     sel,
     ssa_ivc_num_getting_ovc_grant
-
 );
-
+    import pronoc_pkg::*;
     output [DSTPw-1 : 0] destport_clear;
     input ivc_num_getting_ovc_grant;
     input sel;
     input ssa_ivc_num_getting_ovc_grant;
-
- localparam 
-    LOCAL   =   3'd0,  
-    EAST    =   3'd1, 
-    WEST    =   3'd3;
-
-generate
-    /* verilator lint_off WIDTH */    
-    if ( SSA_EN=="YES" ) begin :predict_if    
-    /* verilator lint_on WIDTH */   
+    
+    generate
+    if ( SSA_EN==1 ) begin :predict_if
         if (SW_LOC == LOCAL ) begin :local_if
             assign destport_clear= (ivc_num_getting_ovc_grant)?{2'b00,sel,~sel} :{DSTPw{1'b0}};                  
         end else if (SW_LOC == EAST || SW_LOC == WEST ) begin :xdir_if
-            assign destport_clear = (ivc_num_getting_ovc_grant)? {2'b00,sel,~sel} :
-                                                                   (ssa_ivc_num_getting_ovc_grant)? 4'b0001: //clear b
-                                                                   4'b0000;                  
+            assign destport_clear = (ivc_num_getting_ovc_grant)? 
+                {2'b00,sel,~sel} : 
+                (ssa_ivc_num_getting_ovc_grant)? 4'b0001: //clear b
+                4'b0000;
         end else begin : ydir_if
-             assign destport_clear = (ivc_num_getting_ovc_grant)? {2'b00,sel,~sel} :
-                                                                    (ssa_ivc_num_getting_ovc_grant)? 4'b0010: //clear a
-                                                                    4'b0000;              
+            assign destport_clear = (ivc_num_getting_ovc_grant)? 
+                {2'b00,sel,~sel} :
+                (ssa_ivc_num_getting_ovc_grant)? 4'b0010: //clear a
+                4'b0000;
         end
         end else begin :nopredict_if 
-              assign destport_clear = (ivc_num_getting_ovc_grant )? {2'b00,sel,~sel} :{DSTPw{1'b0}}; 
-        end//   nopredict_if    
-endgenerate
+            assign destport_clear = (ivc_num_getting_ovc_grant )? {2'b00,sel,~sel} :{DSTPw{1'b0}}; 
+        end//   nopredict_if
+    endgenerate
 endmodule
 
 
-
-module   mesh_torus_mask_non_assignable_destport #(
-    parameter TOPOLOGY="MESH",
-    parameter ROUTE_NAME="XY",
+module  regular_topo_mask_non_assignable_destport #(
     parameter SW_LOC=0,
-    parameter P=5,
-    parameter SELF_LOOP_EN="NO"    
-)
-(
-   odd_column,// use only for odd even routing
-   dest_port_in,
-   dest_port_out
+    parameter P=5
+) (
+    odd_column,// use only for odd even routing
+    dest_port_in,
+    dest_port_out
 );
-
-    localparam P_1 = (SELF_LOOP_EN=="NO") ? P-1 : P;
+    import pronoc_pkg::*;
+    localparam P_1 = (SELF_LOOP_EN )?  P : P-1;
     input  [P_1-1 : 0 ] dest_port_in;
     output [P_1-1 : 0 ] dest_port_out;
     input odd_column;
-
-    wire  [P-2 : 0] dest_port_in_tmp,dest_port_out_tmp;
     
+    wire  [P-2 : 0] dest_port_in_tmp,dest_port_out_tmp;
     generate 
-    if(SELF_LOOP_EN == "NO") begin :nslp
+    if(SELF_LOOP_EN == 0) begin :nslp
         assign dest_port_in_tmp = dest_port_in;
         assign dest_port_out = dest_port_out_tmp;
     end else begin :slp
         remove_sw_loc_one_hot #(
             .P(P),
             .SW_LOC(SW_LOC)
-        )
-        remove_sw_loc
-        (
-        	.destport_in(dest_port_in),
-        	.destport_out(dest_port_in_tmp)
+        ) remove_sw_loc (
+            .destport_in(dest_port_in),
+            .destport_out(dest_port_in_tmp)
         );
         //currently loop-back only can happen in local ports. 
         //Current supported routing algorithms does not results in loop-back in other ports
@@ -300,102 +228,74 @@ module   mesh_torus_mask_non_assignable_destport #(
         add_sw_loc_one_hot_val #(
             .P(P),
             .SW_LOC(SW_LOC)
-        )add_sw_loc
-        (
+        )add_sw_loc (
             .sw_loc_val(sw_loc_val),
             .destport_in (dest_port_out_tmp),
             .destport_out(dest_port_out)
         );
-
-       
-       
-        
     end    
     endgenerate
-
-    mesh_torus_mask_non_assignable_destport_no_self_loop # (
-        .TOPOLOGY(TOPOLOGY),
-        .ROUTE_NAME(ROUTE_NAME),
+    
+    regular_topo_mask_non_assignable_destport_no_self_loop # (
         .SW_LOC(SW_LOC),
         .P(P)    
-    )   
-    mask_no_self_loop
-    (
-    	.dest_port_in(dest_port_in_tmp),
-    	.dest_port_out(dest_port_out_tmp),
-    	.odd_column(odd_column)
+    ) mask_no_self_loop (
+        .dest_port_in(dest_port_in_tmp),
+        .dest_port_out(dest_port_out_tmp),
+        .odd_column(odd_column)
     );
-
-
 endmodule
 
-module   mesh_torus_mask_non_assignable_destport_no_self_loop #(
-    parameter TOPOLOGY="MESH",
-    parameter ROUTE_NAME="XY",
+module regular_topo_mask_non_assignable_destport_no_self_loop #(
     parameter SW_LOC=0,
     parameter P=5
-)
-(
-   odd_column,// use only for odd even routing
-   dest_port_in,
-   dest_port_out
+)(
+    odd_column,// use only for odd even routing
+    dest_port_in,
+    dest_port_out
 );
-
-localparam
-    EAST    =       1, 
-    NORTH   =       2, 
-    WEST    =       3,
-    SOUTH   =       4; 
-
-//port number in north port 
-localparam 
-    N_LOCAL   =       0, 
-    N_EAST    =       1, 
-    N_WEST    =       2,  
-    N_SOUTH   =       3; 
-    
- // port number in south port   
- localparam
-    S_LOCAL   =       0, 
-    S_EAST    =       1, 
-    S_NORTH   =       2,  
-    S_WEST    =       3;
-
- // port number in east port   
- localparam
-    E_LOCAL   =       0, 
-    E_NORTH   =       1,  
-    E_WEST    =       2,  
-    E_SOUTH   =       3; 
-    
-   // port number in east port   
- localparam
-    W_LOCAL   =       0,
-    W_EAST    =       1, 
-    W_NORTH   =       2,  
-    W_SOUTH   =       3;   
-    
-
-    localparam P_1 = P-1;
-    input [P_1-1  : 0 ] dest_port_in;
+    import pronoc_pkg::*;
+    //port number in north port 
+    localparam 
+        N_LOCAL = 0, 
+        N_EAST = 1, 
+        N_WEST = 2,  
+        N_SOUTH = 3; 
+    // port number in south port   
+    localparam
+        S_LOCAL = 0, 
+        S_EAST = 1, 
+        S_NORTH = 2,  
+        S_WEST = 3;
+    // port number in east port   
+    localparam
+        E_LOCAL = 0, 
+        E_NORTH = 1,  
+        E_WEST = 2,  
+        E_SOUTH = 3; 
+    // port number in east port   
+    localparam
+        W_LOCAL = 0,
+        W_EAST = 1, 
+        W_NORTH = 2,  
+        W_SOUTH = 3;   
+    localparam 
+        P_1 = P-1;
+    input [P_1-1 : 0 ] dest_port_in;
     output [P_1-1 : 0 ] dest_port_out;
     input odd_column;
     
-    
-    generate 
-    if(P>5)begin :p5
-            assign dest_port_out[P_1-1:4] = dest_port_in[P_1-1:4]; //other local ports
-            end      
-
-
+    generate    
     /* verilator lint_off WIDTH */ 
     if (TOPOLOGY == "RING" || TOPOLOGY == "LINE") begin : oneD // A port can send packets to all other ports in these topologies
     /* verilator lint_on WIDTH */ 
         assign  dest_port_out = dest_port_in;    
     end else begin : towD
-    /*XY*/
+        if(P>5)begin :p5
+            assign dest_port_out[P_1-1:4] = dest_port_in[P_1-1:4]; //other local ports
+        end    
         /* verilator lint_off WIDTH */ 
-        if ( ROUTE_NAME == "XY" || ROUTE_NAME  == "TRANC_XY") begin :xy
+        if ( ROUTE_NAME == "DOR" || ROUTE_NAME == "TRANC_DOR") begin :xy
         /* verilator lint_on WIDTH */ 
             if (SW_LOC == NORTH  ) begin : nort_p // The port located in y axsis does not send packets to x dimension
                 assign dest_port_out[N_LOCAL]= dest_port_in[N_LOCAL]; 
@@ -408,13 +308,12 @@ localparam
                 assign dest_port_out[S_NORTH]= dest_port_in[S_NORTH]; 
                 assign dest_port_out[S_WEST]= 1'b0; // mask west port                                
             end else begin : non_vertical
-                 assign  dest_port_out[3:0] = dest_port_in[3:0];             
+                assign  dest_port_out[3:0] = dest_port_in[3:0];             
             end
-    /*WEST-FIRST*/
         /* verilator lint_off WIDTH */ 
-        end else  if ( ROUTE_NAME == "WEST_FIRST" || ROUTE_NAME  == "TRANC_WEST_FIRST") begin :west_first
+        end else  if ( ROUTE_NAME == "WEST_FIRST" || ROUTE_NAME == "TRANC_WEST_FIRST") begin :west_first
         /* verilator lint_on WIDTH */ 
-         // SW &  NW are forbidden 
+        // SW &  NW are forbidden 
             if (SW_LOC == NORTH  ) begin : nort_p // north port does not send packets to the west port. 
                 assign dest_port_out[N_LOCAL]= dest_port_in[N_LOCAL]; 
                 assign dest_port_out[N_EAST]= dest_port_in[N_EAST]; 
@@ -426,11 +325,10 @@ localparam
                 assign dest_port_out[S_NORTH]= dest_port_in[S_NORTH]; 
                 assign dest_port_out[S_WEST]= 1'b0; // mask west port                                  
             end else begin : non_vertical
-                 assign  dest_port_out[3:0] = dest_port_in[3:0];             
+                assign  dest_port_out[3:0] = dest_port_in[3:0];             
             end        
-    /*NORTH_LAST*/ 
         /* verilator lint_off WIDTH */ 
-        end else  if ( ROUTE_NAME == "NORTH_LAST" || ROUTE_NAME  == "TRANC_NORTH_LAST") begin :north_last
+        end else  if ( ROUTE_NAME == "NORTH_LAST" || ROUTE_NAME == "TRANC_NORTH_LAST") begin :north_last
         /* verilator lint_on WIDTH */ 
             //NE & NW are forbidden
             if (SW_LOC == SOUTH  ) begin : south_p // north port does not send packets to the east nor to the west port. 
@@ -439,13 +337,12 @@ localparam
                 assign dest_port_out[S_WEST]= 1'b0; // mask west port   
                 assign dest_port_out[S_NORTH]= dest_port_in[S_NORTH];                       
             end else begin : other_p
-                 assign  dest_port_out[3:0] = dest_port_in[3:0];             
+                assign  dest_port_out[3:0] = dest_port_in[3:0];             
             end        
-    /*NEGETIVE_FIRST*/
         /* verilator lint_off WIDTH */     
-        end else  if ( ROUTE_NAME == "NEGETIVE_FIRST" || ROUTE_NAME  == "TRANC_NEGETIVE_FIRST") begin :negetive_first
+        end else  if ( ROUTE_NAME == "NEGETIVE_FIRST" || ROUTE_NAME == "TRANC_NEGETIVE_FIRST") begin :negetive_first
         /* verilator lint_on WIDTH */ 
-          //ES & NW is forbiden
+            //ES & NW is forbiden
             if (SW_LOC == SOUTH  ) begin : south_p // south port does not send packets to the west port. NW is forbiden
                 assign dest_port_out[S_LOCAL]= dest_port_in[S_LOCAL]; 
                 assign dest_port_out[S_EAST]= dest_port_in[S_EAST]; 
@@ -457,15 +354,13 @@ localparam
                 assign dest_port_out[W_EAST] = dest_port_in[W_EAST]; 
                 assign dest_port_out[W_SOUTH]= 1'b0; //mask south port
             end else begin : other_p
-                 assign  dest_port_out[3:0] = dest_port_in[3:0];             
+                assign  dest_port_out[3:0] = dest_port_in[3:0];             
             end  
-    /*ODD_EVEN*/
         /* verilator lint_off WIDTH */ 
         end else  if ( ROUTE_NAME == "ODD_EVEN" ) begin : odd_even   
         /* verilator lint_on WIDTH */ 
         //Odd column : NW and SW turns are not allowed
         //Even column: EN and ES turns are not allowed
-    
            if (SW_LOC == NORTH  ) begin : nort_p // north port does not send packets to the west port in odd columns. SW is forbiden
                 assign dest_port_out[N_LOCAL]= dest_port_in[N_LOCAL]; 
                 assign dest_port_out[N_EAST]= dest_port_in[N_EAST]; 
@@ -476,8 +371,6 @@ localparam
                 assign dest_port_out[S_EAST]= dest_port_in[S_EAST]; 
                 assign dest_port_out[S_NORTH]= dest_port_in[S_NORTH]; 
                 assign dest_port_out[S_WEST]= (odd_column)? 1'b0: dest_port_in[S_WEST];  // mask west port   in odd columns 
-            
-            
            end else if (SW_LOC == WEST) begin : west_p // WEST port does not sends packet to north and south ports in even columns
             //ES & EN forbiden 
                 assign dest_port_out[W_LOCAL]= dest_port_in[W_LOCAL]; 
@@ -487,8 +380,7 @@ localparam
             end else begin: other_p
                 assign  dest_port_out[3:0] = dest_port_in[3:0]; 
             end
-
-    end else begin : f_adptv
+        end else begin : f_adptv
                 assign  dest_port_out[3:0] = dest_port_in[3:0];               
         end
     end
@@ -496,19 +388,8 @@ localparam
 endmodule
 
 
-
-
-/**********************
-
-    swap_port_presel_gen
-
-**********************/
-
-module   mesh_torus_swap_port_presel_gen #(
-    parameter V = 4,
-    parameter [V-1  :   0] ESCAP_VC_MASK = 4'b1000,   // mask scape vc, valid only for full adaptive       
+module  regular_topo_swap_port_presel_gen #(
     parameter VC_NUM=0
-
 )(
     avc_unavailable,
     swap_port_presel,
@@ -518,73 +399,48 @@ module   mesh_torus_swap_port_presel_gen #(
     sel,
     clk,
     reset
-
 );
-
-    localparam LOCAL_VC_NUM= VC_NUM % V;
-    
-    
-
-    input    avc_unavailable;
-    input    y_evc_forbiden,x_evc_forbiden;
-    input    non_assigned_ovc_request,sel;
-    input    clk,reset;
-    output   swap_port_presel;
-    wire     swap_reg;
-    
+    import pronoc_pkg::*;
+    localparam LOCAL_VC_NUM= VC_NUM % V;    
+    input avc_unavailable;
+    input y_evc_forbiden,x_evc_forbiden;
+    input non_assigned_ovc_request,sel;
+    input clk,reset;
+    output swap_port_presel;
+    
+    logic swap_reg;
     wire swap_port_presel_next;
-
-   
     wire  evc_forbiden; 
-   
-    
     /************************
-                
-        destination-port_in
-            x:  1 EAST, 0 WEST  
-            y:  1 NORTH, 0 SOUTH
-            ab: 00 : LOCAL, 10: xdir, 01: ydir, 11 x&y dir 
-        sel:
-             0: xdir
-             1: ydir
-        port_pre_sel
-             0: xdir
-             1: ydir  
-
-************************/
-    
-    
+    *            
+    *    destination-port_in
+    *        x: 1 EAST, 0 WEST  
+    *        y: 1 NORTH, 0 SOUTH
+    *        ab: 00 : LOCAL, 10: xdir, 01: ydir, 11 x&y dir 
+    *    sel:
+    *         0: xdir
+    *         1: ydir
+    *    port_pre_sel
+    *         0: xdir
+    *         1: ydir  
+    ************************/
     //For an EVC sender, if the use of EVC in destination port is restricted while the destination port has no available AVC,
     //the port pre selection must swap 
-  
-    
-   // generate
-    // check if it is an evc sender
-   // if(ESCAP_VC_MASK[LOCAL_VC_NUM]== 1'b0)begin 
-    //its not EVC
-    //   assign swap_port_presel=1'b0;
-    
-   // end else begin // the sender is an EVC
-       
-       assign  evc_forbiden = (sel)? y_evc_forbiden : x_evc_forbiden;
-       assign  swap_port_presel_next= non_assigned_ovc_request & evc_forbiden & avc_unavailable;
-       assign swap_port_presel = swap_reg;
-          
-       pronoc_register #(.W(1)) reg2 (.in(swap_port_presel_next ), .out(swap_reg), .reset(reset), .clk(clk));
- 
- endmodule
-
-
-
-
-/************************
-
-    adaptive_avb_ovc_mux
+    assign  evc_forbiden = (sel)? y_evc_forbiden : x_evc_forbiden;
+    assign  swap_port_presel_next= non_assigned_ovc_request & evc_forbiden & avc_unavailable;
+    assign swap_port_presel = swap_reg;
+    always_ff @ (`pronoc_clk_reset_edge) begin
+        if (`pronoc_reset) begin
+            swap_reg <= 1'b0;
+        end else begin
+            swap_reg <= swap_port_presel_next;
+        end
+    end
+endmodule
 
 
-************************/
-module  mesh_torus_adaptive_avb_ovc_mux #(
-   parameter V= 4
+module  regular_topo_adaptive_avb_ovc_mux #(
+    parameter V= 4
 )(
     ovc_avalable,
     sel,
@@ -593,67 +449,47 @@ module  mesh_torus_adaptive_avb_ovc_mux #(
     non_assigned_ovc_request,
     xydir,
     masked_ovc_request
-    
-
 );
-    localparam  P       =   5;
-    localparam  P_1     =   P-1,
-                VP_1    =   V  *  P_1;
-                
-    input   [VP_1-1    :    0] ovc_avalable;
-    input                      sel;
-    input   [V-1       :    0] candidate_ovc_x;
-    input   [V-1       :    0] candidate_ovc_y;
-    input                      non_assigned_ovc_request;
-    input   [1         :    0] xydir;
-    output  [V-1        :   0] masked_ovc_request;
+    localparam
+        P = 5,
+        P_1 = P-1,
+        VP_1 = V  *  P_1;
+        
+    input   [VP_1-1 :  0] ovc_avalable;
+    input   sel;
+    input   [V-1 :  0] candidate_ovc_x;
+    input   [V-1 :  0] candidate_ovc_y;
+    input   non_assigned_ovc_request;
+    input   [1 :  0] xydir;
+    output  [V-1 : 0] masked_ovc_request;
     wire    x,y;
-    wire    [V-1        :   0] ovc_avb_x_plus,ovc_avb_x_minus,ovc_avb_y_plus,ovc_avb_y_minus;
-    wire    [V-1        :   0] mux_out_x,mux_out_y;
-    wire    [V-1        :   0] ovc_request_x,ovc_request_y,masked_ovc_request_x,masked_ovc_request_y;
+    wire    [V-1 : 0] ovc_avb_x_plus,ovc_avb_x_minus,ovc_avb_y_plus,ovc_avb_y_minus;
+    wire    [V-1 : 0] mux_out_x,mux_out_y;
+    wire    [V-1 : 0] ovc_request_x,ovc_request_y,masked_ovc_request_x,masked_ovc_request_y;
     
     assign {x,y}= xydir;
     assign {ovc_avb_x_plus,ovc_avb_x_minus,ovc_avb_y_plus,ovc_avb_y_minus}=ovc_avalable;
     //first level mux
-    //assign mux_out_x = (x)?  ovc_avb_x_plus :  ovc_avb_x_minus;
-    //assign mux_out_y = (y)?  ovc_avb_y_plus :  ovc_avb_y_minus;
+    //assign mux_out_x = (x)?  ovc_avb_x_plus : ovc_avb_x_minus;
+    //assign mux_out_y = (y)?  ovc_avb_y_plus : ovc_avb_y_minus;
     assign mux_out_x = (ovc_avb_x_plus &{V{x}}) |  (ovc_avb_x_minus &{V{~x}});
     assign mux_out_y = (ovc_avb_y_plus &{V{y}}) |  (ovc_avb_y_minus &{V{~y}});
-     
-     
     //assign ovc_request_x = (non_assigned_ovc_request)? candidate_ovc_x : {V{1'b0}};
     //assign ovc_request_y = (non_assigned_ovc_request)? candidate_ovc_y : {V{1'b0}};
-    assign ovc_request_x =  candidate_ovc_x & {V{non_assigned_ovc_request}};
-    assign ovc_request_y =  candidate_ovc_y & {V{non_assigned_ovc_request}};
-    
+    assign ovc_request_x = candidate_ovc_x & {V{non_assigned_ovc_request}};
+    assign ovc_request_y = candidate_ovc_y & {V{non_assigned_ovc_request}};
     //mask unavailble ovc
     assign masked_ovc_request_x = mux_out_x & ovc_request_x;
     assign masked_ovc_request_y = mux_out_y & ovc_request_y;
-    
     //second mux 
-   // assign masked_ovc_request = (sel)?  masked_ovc_request_y: masked_ovc_request_x;
-     assign masked_ovc_request =  (masked_ovc_request_y & {V{sel}})| (masked_ovc_request_x & {V{~sel}});
-
-
+    // assign masked_ovc_request = (sel)?  masked_ovc_request_y: masked_ovc_request_x;
+    assign masked_ovc_request = (masked_ovc_request_y & {V{sel}})| (masked_ovc_request_x & {V{~sel}});
 endmodule
 
 
-
-
-
-/*****************************************************
-
-                port_selector
-
-
-*****************************************************/
-
-
-module mesh_torus_port_selector #(
-    parameter SW_LOC    = 0,
-    parameter PPSw=4
-)
-(
+module regular_topo_port_selector #(
+    parameter SW_LOC = 0
+)(
     port_pre_sel,
     dest_port_in,
     swap_port_presel,
@@ -661,774 +497,420 @@ module mesh_torus_port_selector #(
     y_evc_forbiden,
     x_evc_forbiden
 );
-
-/************************
-                
-        destination-port_in
-            x:  1 EAST, 0 WEST  
-            y:  1 NORTH, 0 SOUTH
-            ab: 00 : LOCAL, 10: xdir, 01: ydir, 11 x&y dir 
-        sel:
-             0: xdir
-             1: ydir
-        port_pre_sel
-             0: xdir
-             1: ydir  
-
-************************/
-
-
+    import pronoc_pkg::*;
+    /************************
+    *
+    *        destination-port_in
+    *            x: 1 EAST, 0 WEST  
+    *            y: 1 NORTH, 0 SOUTH
+    *            ab: 00 : LOCAL, 10: xdir, 01: ydir, 11 x&y dir 
+    *        sel:
+    *             0: xdir
+    *             1: ydir
+    *        port_pre_sel
+    *             0: xdir
+    *             1: ydir  
+    ************************/
     //input           reset,clk;
     input   [PPSw-1:0]   port_pre_sel;
-   // input           port_pre_sel_ld;
+    // input           port_pre_sel_ld;
     output          sel;
     input   [3:0]   dest_port_in;
     input           swap_port_presel;
-   // output          route_subfunc_violated;
+    // output          route_subfunc_violated;
     output          y_evc_forbiden, x_evc_forbiden;
     
     wire  x,y,a,b;
     wire [PPSw-1:0] port_pre_sel_final;
     //reg  [3:0] port_pre_sel_delayed , port_pre_sel_latched;
-  //  wire o1,o2;
-   
-
-    localparam LOCAL    =       0,  
-               EAST     =       1, 
-               NORTH    =       2,  
-               WEST     =       3,  
-               SOUTH    =       4;  
-
-    localparam LOCAL_SEL = (SW_LOC == NORTH || SW_LOC == SOUTH )? 1'b1 : 1'b0; 
+    //  wire o1,o2;
+    localparam 
+        LOCAL = 0,  
+        EAST = 1, 
+        NORTH = 2,  
+        WEST = 3,  
+        SOUTH = 4;  
+    localparam 
+        LOCAL_SEL = (SW_LOC == NORTH || SW_LOC == SOUTH )? 1'b1 : 1'b0; 
     assign port_pre_sel_final= (swap_port_presel)? ~port_pre_sel: port_pre_sel;   
     assign {x,y,a,b} = dest_port_in;
-     
- 
-     wire sel_in,sel_pre, overwrite;
-     wire [1:0] xy;
- 
-     assign xy={x,y};
-     assign sel_pre= port_pre_sel_final[xy];
-     
-     assign overwrite= a&b;
-     generate 
-        if(LOCAL_SEL)begin :local_p
-             assign sel_in= b | ~a; 
-        end else begin :nonlocal_p
-             assign sel_in= b ;    
-        end
-     endgenerate
- 
+    wire sel_in,sel_pre, overwrite;
+    wire [1:0] xy;
+    assign xy={x,y};
+    assign sel_pre= port_pre_sel_final[xy];
+    assign overwrite= a&b;
+    generate 
+    if(LOCAL_SEL)begin :local_p
+        assign sel_in= b | ~a; 
+    end else begin :nonlocal_p
+        assign sel_in= b ;    
+    end
+    endgenerate
     assign sel= (overwrite)? sel_pre : sel_in;
- 
-// check if EVC is allowed to be used     
-    
-        // Using of all EVCs located in y dimension are restricted when the packet can be sent into both x&y direction 
-        assign y_evc_forbiden = a&b;
-        
-        //there is no restriction in using EVCs located in x dimension
-        assign x_evc_forbiden = 1'b0; 
-        //assign route_subfunc_violated = a&b;
-    /* verilator lint_off WIDTH */     
- endmodule
-
+    // check if EVC is allowed to be used     
+    // Using of all EVCs located in y dimension are restricted when the packet can be sent into both x&y direction 
+    assign y_evc_forbiden = a&b;
+    //there is no restriction in using EVCs located in x dimension
+    assign x_evc_forbiden = 1'b0; 
+    //assign route_subfunc_violated = a&b;
+endmodule
 
 
 /*******************
-    mesh_torus_adaptive_lk_dest_encoder
-********************/    
-
-
-
-module  mesh_torus_adaptive_lk_dest_encoder #(
-    parameter V=4,
-    parameter P=5,
-    parameter DSTPw=P-1,
-    parameter Fw=37,
-    parameter DST_P_MSB=11, 
-    parameter DST_P_LSB=8
-
-)(
+*    regular_topo_adaptive_lk_dest_encoder
+********************/
+module  regular_topo_adaptive_lk_dest_encoder (
     sel,
     flit_in,
     dest_coded_out,
     vc_num_delayed,
     lk_dest
 );
-    
+    import pronoc_pkg::*;
     input [V-1 : 0]  sel;
     output [DSTPw-1 : 0]dest_coded_out;
     input [V-1 : 0]  vc_num_delayed;
     input [DSTPw-1 : 0]  lk_dest;
     input [Fw-1 : 0]  flit_in;
-
+    
     wire [1 : 0]  ab,xy;
     wire sel_muxed;
-
-    onehot_mux_1D #(
-        .W(1),
-        .N(V) 
-    )
-    sel_mux
-    (
-        .in(sel),
-        .out(sel_muxed),
-        .sel(vc_num_delayed)
-    );
-    
-    
+    assign sel_muxed = |(sel & vc_num_delayed);
+    localparam 
+        //To avoid warning for Tree topology
+        MSB1 = (DSTPw >= 4)? 3 : 1,
+        LSB1 = (DSTPw >= 4)? 2 : 0,
+        BIT_CHANGE = (DSTPw >= 4)? 2 : 0;
     //lkdestport = {lkdestport_x[1:0],lkdestport_y[1:0]};
     // sel: 0: xdir     1: ydir
-    assign ab = (sel_muxed)? lk_dest[1:0] : lk_dest[3:2];
+    assign ab = (sel_muxed)? lk_dest[1:0] : lk_dest[MSB1:LSB1];
     //if ab==00 change x and y direction
-    assign xy = (ab>0)? flit_in[DST_P_MSB  : DST_P_LSB+2] : ~flit_in[DST_P_MSB  : DST_P_LSB+2] ;
-
+    assign xy = (ab>0)? flit_in[DST_P_MSB : DST_P_LSB+BIT_CHANGE] : ~flit_in[DST_P_MSB : DST_P_LSB+BIT_CHANGE] ;
     assign dest_coded_out={xy,ab};
-
 endmodule
 
 
-module  mesh_torus_dtrmn_dest_encoder #(
+module  regular_topo_dtrmn_dest_encoder #(
     parameter P=5,
     parameter DSTPw=P-1,
     parameter Fw=37,
     parameter DST_P_MSB=11, 
     parameter DST_P_LSB=8
-
 )(
     flit_in,
     dest_coded_out,
     lk_dest
 );
-    
-    
     output [DSTPw-1 : 0]dest_coded_out;
-   
     input [DSTPw-1 : 0]  lk_dest;
     input [Fw-1 : 0]  flit_in;
-
     wire [1 : 0]  ab,xy;
-     
-    
     //lkdestport = {lkdestport_x[1:0],lkdestport_y[1:0]};
     // sel: 0: xdir     1: ydir
-    assign ab =  lk_dest[1:0];
+    assign ab = lk_dest[1:0];
     //if ab==00 change x and y direction
-    assign xy = (ab>0)? flit_in[DST_P_MSB  : DST_P_LSB+2] : ~flit_in[DST_P_MSB  : DST_P_LSB+2] ;
-
+    assign xy = (ab>0)? flit_in[DST_P_MSB : DST_P_LSB+2] : ~flit_in[DST_P_MSB : DST_P_LSB+2] ;
     assign dest_coded_out={xy,ab};
-
 endmodule
 
- 
 /********************
-
-    distance_gen 
-     
+*    distance_gen 
 ********************/
-
-module mesh_torus_distance_gen #(
-    parameter T1= 4,    // number of node in x axis
-    parameter T2= 4,    // number of node in y axis
-    parameter T3= 4,
-    parameter EAw=4,
-    parameter DISTw=4,
-    parameter TOPOLOGY  = "MESH"
-
-)(
+module mesh_line_distance_gen (
     src_e_addr,
     dest_e_addr,
     distance
 );
-
-    function integer log2;
-      input integer number; begin   
-         log2=(number <=1) ? 1: 0;    
-         while(2**log2<number) begin    
-            log2=log2+1;    
-         end       
-      end   
-    endfunction // log2 
- 
- 
-    localparam 
-        Xw  =   log2(T1),   // number of node in x axis
-        Yw  =   log2(T2);    // number of node in y axis 
-    localparam [Xw : 0] NX  = T1;
-    localparam [Yw : 0] NY  = T2;
-              
-     
-   input [EAw-1 : 0] src_e_addr;
-   input [EAw-1 : 0] dest_e_addr;               
-   output[DISTw-1:   0]distance;                     
-
-    wire [Xw-1 :   0]src_x,dest_x;
-    wire [Yw-1 :   0]src_y,dest_y;
-   
-    mesh_tori_endp_addr_decode #(
-    	.TOPOLOGY(TOPOLOGY),
-    	.T1(T1),
-    	.T2(T2),
-    	.T3(T3),
-    	.EAw(EAw)
-    )
-    src_addr_decode
-    (
-    	.e_addr(src_e_addr),
-    	.ex(src_x),
-    	.ey(src_y),
-    	.el(),
-    	.valid()
-    );
-    
-     mesh_tori_endp_addr_decode #(
-        .TOPOLOGY(TOPOLOGY),
-        .T1(T1),
-        .T2(T2),
-        .T3(T3),
-        .EAw(EAw)
-    )
-    dest_addr_decode
-    (
-        .e_addr(dest_e_addr),
-        .ex(dest_x),
-        .ey(dest_y),
-        .el(),
-        .valid()
-    );
-       
-    reg [Xw-1  :   0] x_offset;
-    reg [Yw-1  :   0] y_offset;
-    
-    generate 
+    import pronoc_pkg::*;
+    input [EAw-1 : 0] src_e_addr;
+    input [EAw-1 : 0] dest_e_addr;
+    output[DISTw-1: 0]distance;
+    regular_topo_router_addr_t src_router_addr, dest_router_addr;
+    assign src_router_addr = regular_topo_router_addr_t'(src_e_addr);
+    assign dest_router_addr = regular_topo_router_addr_t'(dest_e_addr);
+    
+    logic [NXw-1 : 0] x_offset;
+    logic [NYw-1 : 0] y_offset;
+    always_comb begin 
+        x_offset = (src_router_addr.x > dest_router_addr.x) ? src_router_addr.x - dest_router_addr.x : dest_router_addr.x - src_router_addr.x;
+        y_offset = (src_router_addr.y > dest_router_addr.y) ? src_router_addr.y - dest_router_addr.y : dest_router_addr.y - src_router_addr.y;
+    end
     /* verilator lint_off WIDTH */ 
-    if( TOPOLOGY == "MESH" || TOPOLOGY == "LINE") begin : oneD
+    assign distance = x_offset+y_offset+1'b1;
     /* verilator lint_on WIDTH */ 
-        
-        always @(*) begin 
-            x_offset     = (src_x> dest_x)? src_x - dest_x : dest_x - src_x;
-            y_offset     = (src_y> dest_y)? src_y - dest_y : dest_y - src_y;
-         end
-        
-    
-    
-    end else begin : twoD //torus ring
-    
-        wire tranc_x_plus,tranc_x_min,tranc_y_plus,tranc_y_min,same_x,same_y;
-        
-        /* verilator lint_off WIDTH */
-        always @ (*) begin 
-            x_offset= {Xw{1'b0}};
-            y_offset= {Yw{1'b0}};
-            
-            //x_offset
-            if(same_x) x_offset= {Xw{1'b0}};
-            else if(tranc_x_plus) begin 
-                if(dest_x   > src_x)    x_offset= dest_x-src_x; 
-                else                    x_offset= (NX-src_x)+dest_x;
-            end
-            else if(tranc_x_min)  begin 
-                if(dest_x   <  src_x)    x_offset= src_x-dest_x; 
-                else                     x_offset= src_x+(NX-dest_x);
-            
-            end
-        
-             //y_offset
-            if(same_y) y_offset= {Yw{1'b0}};
-            else if(tranc_y_plus) begin 
-                if(dest_y   > src_y)    y_offset= dest_y-src_y; 
-                else                    y_offset= (NY-src_y)+dest_y;
-            end
-            else if(tranc_y_min)  begin 
-                if(dest_y   <  src_y)    y_offset= src_y-dest_y; 
-                else                     y_offset= src_y+(NY-dest_y);
-            
-            end
-        
-        
-        end      
-        /* verilator lint_on WIDTH */
-          
-            
-        tranc_dir #(
-            .NX(NX),
-            .NY(NY)
-        )
-        tranc_dir
-        (
-            .tranc_x_plus(tranc_x_plus),
-            .tranc_x_min(tranc_x_min),
-            .tranc_y_plus(tranc_y_plus),
-            .tranc_y_min(tranc_y_min),
-            .same_x(same_x),
-            .same_y(same_y),
-            .current_x(src_x),
-            .current_y(src_y),
-            .dest_x(dest_x),
-            .dest_y(dest_y)
-        );
-    
-    
-    end    
-    endgenerate
+endmodule
+
+module ring_torus_distance_gen (
+    src_e_addr,
+    dest_e_addr,
+    distance
+);
+    import pronoc_pkg::*;
+    input [EAw-1 : 0] src_e_addr;
+    input [EAw-1 : 0] dest_e_addr;
+    output[DISTw-1: 0]distance;
+    wire [NXw-1 : 0]src_x,dest_x;
+    wire [NYw-1 : 0]src_y,dest_y;
+    regular_topo_router_addr_t src_router_addr, dest_router_addr;
+    assign src_router_addr = regular_topo_router_addr_t'(src_e_addr);
+    assign dest_router_addr = regular_topo_router_addr_t'(dest_e_addr);
+    assign src_x = src_router_addr.x;
+    assign src_y = src_router_addr.y;
+    assign dest_x = dest_router_addr.x;
+    assign dest_y = dest_router_addr.y;
+    logic [NXw-1 : 0] x_offset;
+    logic [NYw-1 : 0] y_offset;
+    wire tranc_x_plus,tranc_x_min,tranc_y_plus,tranc_y_min,same_x,same_y;
+    /* verilator lint_off WIDTH */
+    always_comb begin 
+        x_offset= {NXw{1'b0}};
+        y_offset= {NYw{1'b0}};
+        //x_offset
+        if(same_x) x_offset= {NXw{1'b0}};
+        else if(tranc_x_plus) begin 
+            if(dest_x   > src_x)    x_offset= dest_x-src_x; 
+            else                    x_offset= (NX-src_x)+dest_x;
+        end
+        else if(tranc_x_min)  begin 
+            if(dest_x   <  src_x)    x_offset= src_x-dest_x; 
+            else                     x_offset= src_x+(NX-dest_x);
+        end
+        //y_offset
+        if(same_y) y_offset= {NYw{1'b0}};
+        else if(tranc_y_plus) begin 
+            if(dest_y   > src_y)    y_offset= dest_y-src_y; 
+            else                    y_offset= (NY-src_y)+dest_y;
+        end
+        else if(tranc_y_min)  begin 
+            if(dest_y   <  src_y)    y_offset= src_y-dest_y; 
+            else                     y_offset= src_y+(NY-dest_y);
+        end
+    end      
+    /* verilator lint_on WIDTH */    
+    tranc_dir #(
+        .NX(NX),
+        .NY(NY)
+    ) tranc_dir (
+        .tranc_x_plus(tranc_x_plus),
+        .tranc_x_min(tranc_x_min),
+        .tranc_y_plus(tranc_y_plus),
+        .tranc_y_min(tranc_y_min),
+        .same_x(same_x),
+        .same_y(same_y),
+        .current_x(src_x),
+        .current_y(src_y),
+        .dest_x(dest_x),
+        .dest_y(dest_y)
+    );
     /* verilator lint_off WIDTH */ 
-    assign distance     =   x_offset+y_offset+1'b1;
+    assign distance = x_offset+y_offset+1'b1;
     /* verilator lint_on WIDTH */ 
 endmodule
- 
- 
-module mesh_torus_ssa_check_destport #(
-    parameter ROUTE_TYPE="DETERMINISTIC",
+
+
+module two_dim_ssa_check_destport #(
     parameter SW_LOC = 0,
-    parameter P=5,
-    parameter DEBUG_EN = 0,
-    parameter DSTPw = P-1,
     parameter SS_PORT=0
 )(
     destport_encoded, //exsited packet dest port
     destport_in_encoded, // incomming packet dest port
     ss_port_hdr_flit,
-    ss_port_nonhdr_flit 
-//synthesis translate_off 
-//synopsys  translate_off
+    ss_port_nonhdr_flit
+    `ifdef SIMULATION 
     ,clk,
     ivc_num_getting_sw_grant,
     hdr_flg
-//synopsys  translate_on
-//synthesis translate_on    
-    
+    `endif
 );
-
+    import pronoc_pkg::*;
     input [DSTPw-1 : 0] destport_encoded, destport_in_encoded; 
     output ss_port_hdr_flit, ss_port_nonhdr_flit;
-//synthesis translate_off 
-//synopsys  translate_off
-    input clk,   ivc_num_getting_sw_grant,hdr_flg;
-//synopsys  translate_on
-//synthesis translate_on    
-
-//MESH, TORUS Topology p=5           
-    localparam   LOCAL   =   0,  
-                 EAST    =   1,
-                 WEST    =   3;
-
-
-/************************
-        destination port is coded        
-        destination-port_in
-            x:  1 EAST, 0 WEST  
-            y:  1 NORTH, 0 SOUTH
-            ab: 00 : LOCAL, 10: xdir, 01: ydir, 11 x&y dir 
-        sel:
-             0: xdir
-             1: ydir
-        port_pre_sel
-             0: xdir
-             1: ydir  
-
+    `ifdef SIMULATION 
+    input clk, ivc_num_getting_sw_grant,hdr_flg;
+    `endif
+/*************************
+*        destination port is coded        
+*        destination-port_in
+*            x: 1 EAST, 0 WEST  
+*            y: 1 NORTH, 0 SOUTH
+*            ab: 00 : LOCAL, 10: xdir, 01: ydir, 11 x&y dir 
+*        sel:
+*             0: xdir
+*             1: ydir
+*        port_pre_sel
+*             0: xdir
+*             1: ydir  
+*
 ************************/
-wire  a,b,aa,bb;
-assign {a,b} = destport_in_encoded[1:0];
-assign {aa,bb} = destport_encoded[1:0];
-
-generate
+    wire  a,b,aa,bb;
+    assign {a,b} = destport_in_encoded[1:0];
+    assign {aa,bb} = destport_encoded[1:0];
+    generate
     if( SS_PORT == LOCAL) begin :local_p
-         assign ss_port_hdr_flit = 1'b0;
-         assign ss_port_nonhdr_flit =   1'b0;
+        assign ss_port_hdr_flit = 1'b0;
+        assign ss_port_nonhdr_flit = 1'b0;
     end else if ((SS_PORT == EAST) || SS_PORT == WEST )begin :xdir
-         assign ss_port_hdr_flit = a;
-         assign ss_port_nonhdr_flit =   aa;
+        assign ss_port_hdr_flit = a;
+        assign ss_port_nonhdr_flit = aa;
     end else begin :ydir
         assign ss_port_hdr_flit = b;
-        assign ss_port_nonhdr_flit =   bb;
+        assign ss_port_nonhdr_flit = bb;
     end
-
-//synthesis translate_off 
-//synopsys  translate_off
-
-if(DEBUG_EN) begin :dbg
-    always @(posedge clk) begin
-       //if(!reset)begin 
-            if(ivc_num_getting_sw_grant & aa & bb & ~hdr_flg) begin 
-                $display("%t: SSA ERROR: There are two output ports that a non-header flit can be sent to. %m",$time);
-                $finish;
-            end
-       //end
-    end 
-end //dbg
-
-//synopsys  translate_on
-//synthesis translate_on
-
-
+    `ifdef SIMULATION 
+    if(DEBUG_EN) begin :dbg
+        always @(posedge clk) begin
+           //if(!reset)begin 
+                if(ivc_num_getting_sw_grant & aa & bb & ~hdr_flg) begin 
+                    $display("%t: SSA ERROR: There are two output ports that a non-header flit can be sent to. %m",$time);
+                    $finish;
+                end
+           //end
+        end 
+    end //dbg
+    `endif
 endgenerate
 endmodule
 
 
-module line_ring_ssa_check_destport #(
-    parameter ROUTE_TYPE="DETERMINISTIC",
+module one_dim_ssa_check_destport #(
     parameter SW_LOC = 0,
-    parameter P=3,
-    parameter DEBUG_EN = 0,
-    parameter DSTPw = P-1,
     parameter SS_PORT=0
 )(
     destport_encoded, //exsited packet dest port
     destport_in_encoded, // incomming packet dest port
     ss_port_hdr_flit,
     ss_port_nonhdr_flit 
-
 );
-
+    import pronoc_pkg::*;
     input [DSTPw-1 : 0] destport_encoded, destport_in_encoded; 
     output ss_port_hdr_flit, ss_port_nonhdr_flit;
-
-
-
-wire [P-1   :   0] dest_port_num,assigned_dest_port_num;
+    wire [MAX_P-1 : 0] dest_port_num,assigned_dest_port_num;
     
-  
-
-  line_ring_decode_dstport cnv1(
-  	.dstport_one_hot(dest_port_num),
-  	.dstport_encoded(destport_in_encoded)
-  );
-  
-   line_ring_decode_dstport cnv2(
-   	.dstport_one_hot(assigned_dest_port_num),
-   	.dstport_encoded(destport_encoded)
-   );
-   
-     assign ss_port_hdr_flit = dest_port_num [SS_PORT];
-   
-    assign ss_port_nonhdr_flit =  assigned_dest_port_num[SS_PORT];
-
-endmodule
-
-
-/*
-module mesh_torus_add_ss_port #(   
-    parameter SW_LOC=1,
-    parameter P=5,
-    parameter SELF_LOOP_EN="NO"
-)(
-    destport_in,
-    destport_out 
-);
-     localparam
-        P_1     = (SELF_LOOP_EN == "NO") ? P-1 : P,
-        LOCAL   =   0,  
-        EAST    =   1,
-        NORTH   =   2, 
-        WEST    =   3,
-        SOUTH   =   4;
-
-
-     localparam  NO_SELF_LOOP  = (SELF_LOOP_EN == "NO") ? 1 : 0;
-     localparam  SS_PORT_P5 = (SW_LOC== EAST   )? WEST- NO_SELF_LOOP : // the sender port must be removed from destination port code  
-                              (SW_LOC== NORTH  )? SOUTH- NO_SELF_LOOP: // the sender port must be removed from destination port code  
-                              (SW_LOC== WEST   )? EAST  :
-                                                  NORTH ; 
-
-     localparam  SS_PORT_P3 =  (SELF_LOOP_EN == "NO") ? 1 :   
-                                 
-
-     localparam  SS_PORT      =   (P==5) ? SS_PORT_P5: SS_PORT_P3;
-
-        
+    line_ring_decode_dstport cnv1(
+        .dstport_one_hot(dest_port_num),
+        .dstport_encoded(destport_in_encoded)
+    );
+    line_ring_decode_dstport cnv2(
+        .dstport_one_hot(assigned_dest_port_num),
+        .dstport_encoded(destport_encoded)
+    );
     
-     
-    input       [P_1-1  :   0] destport_in;
-    output reg  [P_1-1  :   0] destport_out; 
-     
-     
-     
-    always @(*)begin 
-        destport_out=destport_in;
-        if( SW_LOC != LOCAL ) begin 
-            if(destport_in=={P_1{1'b0}}) destport_out[SS_PORT]= 1'b1;
-        end    
-    end 
-     
-
+    assign ss_port_hdr_flit = dest_port_num [SS_PORT];
+    assign ss_port_nonhdr_flit = assigned_dest_port_num[SS_PORT];
 endmodule
-*/
 
-/**************
- * 
- * ************/
- 
-  module mesh_tori_router_addr_decode #(
-    parameter TOPOLOGY = "MESH",
-    parameter T1=4,
-    parameter T2=4,
-    parameter T3=4,
-    parameter RAw=6
-)(
+
+module regular_topo_router_addr_decode (
     r_addr,
     rx,
     ry,
     valid
 );
-
-    function integer log2;
-      input integer number; begin   
-         log2=(number <=1) ? 1: 0;    
-         while(2**log2<number) begin    
-            log2=log2+1;    
-         end        
-      end   
-    endfunction // log2 
-
+    import pronoc_pkg::*;
+    
     localparam
-        NX = T1,
-        NY = T2,
         RXw = log2(NX),    // number of node in x axis
-        RYw = (TOPOLOGY=="RING" || TOPOLOGY == "LINE") ? 1 : log2(NY);    // number of node in y axis
-    
+        RYw = (IS_1D_TOPO) ? 1 : log2(NY);    // number of node in y axis
     /* verilator lint_off WIDTH */ 
     localparam [RXw-1 : 0]    MAXX = (NX-1); 
     localparam [RYw-1 : 0]    MAXY = (NY-1); 
     /* verilator lint_on WIDTH */ 
     
-    
     input  [RAw-1 : 0] r_addr;
     output [RXw-1 : 0] rx;
     output [RYw-1 : 0] ry;
     output valid;
     
     generate 
-    if ((TOPOLOGY == "RING") || (TOPOLOGY == "LINE")) begin :oneD 
-         assign rx = r_addr;   
-         assign ry = 1'b0;
+    if (IS_1D_TOPO) begin :D1_
+        assign rx = r_addr;
+        assign ry = 1'b0;
     end else begin : twoD
-        assign {ry,rx} = r_addr;    
+        assign {ry,rx} = r_addr;
     end
     endgenerate
-    
     /* verilator lint_off CMPCONST */
     assign valid = (rx<= MAXX ) & (ry <= MAXY);
     /* verilator lint_on CMPCONST */
 endmodule
- 
 
- 
-module mesh_tori_endp_addr_decode #(
-    parameter TOPOLOGY = "MESH",
-    parameter T1=4,
-    parameter T2=4,
-    parameter T3=4,
-    parameter EAw=9
-)(
-    e_addr,
-    ex,
-    ey,
-    el,
+module regular_topo_address_validator (
+    addr,
     valid
 );
-
-    function integer log2;
-      input integer number; begin   
-         log2=(number <=1) ? 1: 0;    
-         while(2**log2<number) begin    
-            log2=log2+1;    
-         end        
-      end   
-    endfunction // log2 
-
-    localparam
-        NX = T1,
-        NY = T2,
-        NL = T3, 
-        EXw = log2(NX),    // number of node in x axis
-        EYw = (TOPOLOGY=="RING" || TOPOLOGY == "LINE")? 1 : log2(NY),
-        ELw = log2(NL);    // number of node in y axis
-    
-    /* verilator lint_off WIDTH */ 
-    localparam [EXw-1 : 0]    MAXX = (NX-1); 
-    localparam [EYw-1 : 0]    MAXY = (NY-1); 
-    localparam [ELw-1 : 0]    MAXL = (NL-1); 
-    /* verilator lint_on WIDTH */ 
-    
-    
-    input  [EAw-1 : 0] e_addr;
-    output [EXw-1 : 0] ex;
-    output [EYw-1 : 0] ey;
-    output [ELw-1 : 0] el;
-    output valid;
-    
-    generate 
-    if ((TOPOLOGY == "RING") || (TOPOLOGY == "LINE")) begin :oneD 
-        if(NL==1)begin:one_local 
-             assign ex = e_addr;   
-             assign ey = 1'b0;
-             assign el = 1'b0;
-             /* verilator lint_off CMPCONST */
-             assign valid = ex<= MAXX;
-             /* verilator lint_on CMPCONST */
-        end else begin: multi_local 
-             assign {el,ex} = e_addr;   
-             assign ey = 1'b0;
-             /* verilator lint_off CMPCONST */
-             assign valid = ((ex<= MAXX) & (el<=MAXL));
-             /* verilator lint_on CMPCONST */
+    import pronoc_pkg::*;
+    input  [EAw-1 : 0] addr;
+    output logic valid;
+    regular_topo_endp_addr_t endp_addr;
+    always_comb begin 
+        endp_addr = regular_topo_endp_addr_t'(addr);
+        //for 2/1d we need to re-extact the l
+        endp_addr.l=addr[EAw-1: EAw-NLw];
+    end
+    always_comb begin 
+        valid = 1'b1;
+        if(32'(endp_addr.x) >= NX) valid = 1'b0;
+        if((IS_2D_TOPO | IS_3D_TOPO) && ((NY & (NY - 1)) != 0) ) begin
+            if(32'(endp_addr.y) >= NY) valid = 1'b0;
         end
-    end else begin : twoD
-        if(NL==1)begin:one_local 
-            assign {ey,ex} = e_addr; 
-            assign el = 1'b0;  
-            /* verilator lint_off CMPCONST */
-            assign valid = (ex<= MAXX) & (ey <= MAXY);
-            /* verilator lint_on CMPCONST */
-        end else begin :multi_l
-            assign {el,ey,ex} = e_addr; 
-            /* verilator lint_off CMPCONST */
-            assign valid = ( (ex<= MAXX) & (ey <= MAXY) & (el<=MAXL) );
-            /* verilator lint_on CMPCONST */
+        if(IS_3D_TOPO) begin
+            if(32'(endp_addr.z) >= NZ) valid = 1'b0;
+        end
+        if(NL>1) begin
+            if(32'(endp_addr.l) >= NL) valid = 1'b0;
         end
     end
-    endgenerate   
-    
 endmodule
 
 
 /**************
-    mesh_tori_addr_encoder
-    most probably it is only needed for simulation purposes
+*    Regular_topo_endp_addr_encoder
+*    most probably it is only needed for simulation purposes
 ***************/  
-
-module  mesh_tori_addr_encoder #(
-    parameter   NX=2,
-    parameter   NY=2,
-    parameter   NL=2,
-    parameter   NE=16,
-    parameter   EAw=4,
-    parameter   TOPOLOGY="MESH"
-)(
+module  regular_topo_endp_addr_encoder 
+(    
     id,
     code
 );
-    
-    function integer log2;
-      input integer number; begin   
-         log2=(number <=1) ? 1: 0;    
-         while(2**log2<number) begin    
-            log2=log2+1;    
-         end        
-      end   
-    endfunction // log2 
-    
-  
-        
-    function integer addrencode;
-        input integer in,nx,nxw,nl,nyw;
-        integer  y, x, l;begin
-            addrencode=0;
-            y = ((in/nl) / nx ); 
-            x = ((in/nl) % nx ); 
-            l = (in % nl);  
-            addrencode =(nl==1)?   (y<<nxw | x) : (l<<(nxw+nyw)|  (y<<nxw) | x);      
-        end   
-    endfunction // addrencode
-        
-      
-    localparam 
-        NXw= log2(NX),
-        NYw= (TOPOLOGY=="RING" || TOPOLOGY=="LINE")? 0 : log2(NY),
-        NEw = log2(NE);    
-
-
-     input [NEw-1 :0] id;
-     output [EAw-1 : 0] code;
-
+    import pronoc_pkg::*;
+    input [NEw-1 :0] id;
+    output [EAw-1 : 0] code;
     wire [EAw-1 : 0 ] codes [NE-1 : 0];
     genvar i;
     generate 
     for(i=0; i< NE; i=i+1) begin : endpoints
         //Endpoint decoded address
-       /* verilator lint_off WIDTH */
-        localparam [EAw-1 : 0] ENDP= addrencode(i,NX,NXw,NL,NYw);
-       /* verilator lint_on WIDTH */
+        localparam [EAw-1 : 0] ENDP = EAw'(regular_topo_endp_addr(i));
         assign codes[i] = ENDP;            
     end
     endgenerate
-
     assign code = codes[id];
 endmodule
 
 
-module  mesh_tori_addr_coder #(
-    parameter   TOPOLOGY = "MESH",
-    parameter   NX=2,
-    parameter   NY=2,
-    parameter   NL=2,
-    parameter   NE=16,
-    parameter   EAw=4
-)(
+module  regular_topo_addr_coder (
     id,
     code
 );
-    
-    function integer log2;
-      input integer number; begin   
-         log2=(number <=1) ? 1: 0;    
-         while(2**log2<number) begin    
-            log2=log2+1;    
-         end        
-      end   
-    endfunction // log2 
-    
-  
-        
-    function integer addrencode;
-        input integer in,nx,nxw,nl,nyw;
-        integer  y, x, l;begin
-            addrencode=0;
-            y = ((in/nl) / nx ); 
-            x = ((in/nl) % nx ); 
-            l = (in % nl);  
-            addrencode =(nl==1)?   (y<<nxw | x) : (l<<(nxw+nyw)|  (y<<nxw) | x);      
-        end   
-    endfunction // addrencode
-        
-      
-    localparam 
-        NXw= log2(NX),
-        NYw= (TOPOLOGY=="RING" || TOPOLOGY=="LINE")? 0 : log2(NY),
-        NEw = log2(NE);    
-
-
-     output [NEw-1 :0] id;
-     input [EAw-1 : 0] code;
-
+    import pronoc_pkg::*;    
+    output [NEw-1 :0] id;
+    input [EAw-1 : 0] code;
     wire   [NEw-1 : 0]  codes   [(2**EAw)-1 : 0 ];
     genvar i;
     generate 
     for(i=0; i< NE; i=i+1) begin : endpoints
         //Endpoint decoded address
-       /* verilator lint_off WIDTH */
-        localparam [EAw-1 : 0] ENDP= addrencode(i,NX,NXw,NL,NYw);
-       /* verilator lint_on WIDTH */
+        localparam [EAw-1 : 0] ENDP= EAw'(regular_topo_endp_addr(i));
         assign codes[ENDP] = i;            
     end
     endgenerate
-
     assign id = codes[code];
 endmodule
 
-
-
-module mesh_torus_destp_generator #(
-    parameter TOPOLOGY = "MESH",
-    parameter ROUTE_NAME = "XY",  
-    parameter ROUTE_TYPE = "DETERMINISTIC",
+module regular_topo_destp_generator #(
     parameter P=5,
-    parameter DSTPw=4,
-    parameter NL=1,
     parameter PLw=1,
-    parameter PPSw=4,
-    parameter SW_LOC=0,
-    parameter SELF_LOOP_EN="NO" 
+    parameter SW_LOC=0
 )(
     dest_port_out,
     dest_port_coded,
@@ -1437,295 +919,204 @@ module mesh_torus_destp_generator #(
     port_pre_sel,
     odd_column
 );
-    localparam P_1 =  ( SELF_LOOP_EN=="NO")?  P-1 : P;
+    import pronoc_pkg::*;
+    localparam 
+        P_1 = (SELF_LOOP_EN )?  P : P-1,
+        Pw = log2(P);
     
     input  [DSTPw-1 : 0] dest_port_coded;
     input  [PLw-1 : 0] endp_localp_num;
     output [P_1-1 : 0] dest_port_out;
-    input           swap_port_presel;
+    input  swap_port_presel;
     input  [PPSw-1 : 0] port_pre_sel;
     input odd_column;
     
-    
     wire [P_1-1 : 0] dest_port_in;
     
-   
-        generate 
-        /* verilator lint_off WIDTH */
-        if (TOPOLOGY == "RING" || TOPOLOGY == "LINE" ) begin : one_D
-        /* verilator lint_on WIDTH */
-         
-            line_ring_destp_decoder #(
-                .ROUTE_TYPE(ROUTE_TYPE),
-                .P(P),
-                .DSTPw(DSTPw),
-                .NL(NL),
-                .ELw(PLw),
-                .PPSw(PPSw),
-                .SW_LOC(SW_LOC),
-                .SELF_LOOP_EN(SELF_LOOP_EN)
-            )
-            decoder
-            (
-                .dest_port_coded(dest_port_coded),             
-                .dest_port_out(dest_port_in),
-                .endp_localp_num(endp_localp_num)               
-            );
-       
-        
-       end else begin :two_D
-       
-            mesh_torus_destp_decoder #(
-                .ROUTE_TYPE(ROUTE_TYPE),
-                .P(P),
-                .DSTPw(DSTPw),
-                .NL(NL),
-                .ELw(PLw),
-                .PPSw(PPSw),
-                .SW_LOC(SW_LOC),
-                .SELF_LOOP_EN(SELF_LOOP_EN)
-            )
-            decoder
-            (
-                .dest_port_coded(dest_port_coded),             
-                .dest_port_out(dest_port_in),
-                .endp_localp_num(endp_localp_num),
-                .swap_port_presel(swap_port_presel),
-                .port_pre_sel(port_pre_sel)
-            );
-      end
- endgenerate     
-          
-      mesh_torus_mask_non_assignable_destport #(
-                .TOPOLOGY(TOPOLOGY),
-                .ROUTE_NAME(ROUTE_NAME),
-                .SW_LOC(SW_LOC),
-                .P(P),
-                .SELF_LOOP_EN(SELF_LOOP_EN)
-            )
-            mask_destport
-            (
-                .dest_port_in(dest_port_in),
-                .dest_port_out(dest_port_out),
-                .odd_column(odd_column)
-            ); 
-
+    generate 
+    if (IS_1D_TOPO) begin : D1_
+        line_ring_destp_decoder #(
+            .P(P),
+            .ELw(PLw),
+            .SW_LOC(SW_LOC)
+        ) decoder (
+            .dest_port_coded(dest_port_coded),
+            .dest_port_out(dest_port_in),
+            .endp_localp_num(endp_localp_num)       
+        );
+    end else if (IS_MESH_3D) begin : three_D
+        logic [P-1  : 0] mesh_3d_one_hot_dest_port;
+        logic [Pw-1 : 0] local_dest_port;
+        always @(*) begin
+            local_dest_port =Pw'(endp_localp_num) + Pw'(DOWN);
+            mesh_3d_one_hot_dest_port = {P{1'b0}};
+            if(dest_port_coded == 0 && endp_localp_num!=0 && NL >1) mesh_3d_one_hot_dest_port[local_dest_port] = 1'b1;
+            else mesh_3d_one_hot_dest_port[dest_port_coded] = 1'b1;
+        end
+        destport_non_selfloop_fix #(
+            .SELF_LOOP_EN(SELF_LOOP_EN),
+            .P(P),
+            .SW_LOC(SW_LOC)
+        ) remove_sw_loc (
+            .destport_in(mesh_3d_one_hot_dest_port[P-1 : 0]),
+            .destport_out(dest_port_out)
+        );
+    end else begin :two_D
+        regular_topo_destp_decoder #(
+            .P(P),
+            .ELw(PLw),
+            .SW_LOC(SW_LOC)
+        ) decoder (
+            .dest_port_coded(dest_port_coded),             
+            .dest_port_out(dest_port_in),
+            .endp_localp_num(endp_localp_num),
+            .swap_port_presel(swap_port_presel),
+            .port_pre_sel(port_pre_sel)
+        );
+    end
+    endgenerate     
+    
+    regular_topo_mask_non_assignable_destport #(
+        .SW_LOC(SW_LOC),
+        .P(P)
+    ) mask_destport (
+        .dest_port_in(dest_port_in),
+        .dest_port_out(dest_port_out),
+        .odd_column(odd_column)
+    ); 
 endmodule
 
-module mesh_torus_destp_decoder #(
-    parameter ROUTE_TYPE="DETERMINISTIC",
+module regular_topo_destp_decoder #(
     parameter P=6,
-    parameter DSTPw=4,
-    parameter NL=2,
     parameter ELw=1,
-    parameter PPSw=4,
-    parameter SW_LOC=0,
-    parameter SELF_LOOP_EN="NO"
+    parameter SW_LOC=0
 )(
     dest_port_coded,
     endp_localp_num,
     dest_port_out,
     swap_port_presel,
     port_pre_sel
- );
-  
-    localparam P_1 = ( SELF_LOOP_EN=="NO")?  P-1 : P;
-  
+);
+    import pronoc_pkg::*;
+    localparam P_1 = (SELF_LOOP_EN )?  P : P-1;
     input  [DSTPw-1 : 0] dest_port_coded;
     input  [ELw-1 : 0] endp_localp_num;
     output [P_1-1 : 0] dest_port_out;
-    input           swap_port_presel;
+    input  swap_port_presel;
     input  [PPSw-1 : 0] port_pre_sel;
     
-    wire [NL-1 : 0] endp_localp_onehot;
-   
+    logic [NL-1 : 0] endp_localp_onehot;
     reg [4:0] portout;
-   
-    generate 
-    if( ROUTE_TYPE == "DETERMINISTIC") begin :dtrmn
-         
-       
-        wire x,y,a,b;
-        assign {x,y,a,b} = dest_port_coded;
-          
-        always @(*)begin 
-            case({a,b})
-                2'b10 : portout = {1'b0,~x,1'b0,x,1'b0};
-                2'b01 : portout = {~y,1'b0,y,1'b0,1'b0};
-                2'b00 : portout =  5'b00001;
-                2'b11 : portout = {~y,1'b0,y,1'b0,1'b0}; //invalid condition in determinstic routing
-            endcase
-        end //always
-          
-    end else begin : adpv
-        
-        wire x,y,a,b;
-        assign {x,y,a,b} = dest_port_coded;        
-        wire [PPSw-1:0] port_pre_sel_final;
-        assign port_pre_sel_final= (swap_port_presel)? ~port_pre_sel: port_pre_sel;
-        
-        always @(*)begin 
-            case({a,b})
-                2'b10 : portout = {1'b0,~x,1'b0,x,1'b0};
-                2'b01 : portout = {~y,1'b0,y,1'b0,1'b0};
-                2'b11 : portout = (port_pre_sel_final[{x,y}])?  {~y,1'b0,y,1'b0,1'b0} : {1'b0,~x,1'b0,x,1'b0};
-                2'b00 : portout =  5'b00001;
-            endcase
-        end //always
-     end 
-     
-     
-     if(NL==1) begin :slp        
-        if(SELF_LOOP_EN == "NO") begin :nslp
-            remove_sw_loc_one_hot #(
-                .P(5),
-                .SW_LOC(SW_LOC)
-            )
-            conv
-            (
-                .destport_in(portout),
-                .destport_out(dest_port_out)
-            ); 
-         end else begin : slp
-            assign dest_port_out = portout;  
-         end
-     end else begin :mlp
-
-            wire [P-1 : 0] destport_onehot;
-	
-            bin_to_one_hot #(
-            	.BIN_WIDTH(ELw),
-            	.ONE_HOT_WIDTH(NL)
-            )
-            conv
-            (
-            	.bin_code(endp_localp_num),
-            	.one_hot_code(endp_localp_onehot)
-            );
-            
-           assign destport_onehot =(portout[0])?  { endp_localp_onehot[NL-1 : 1] ,{(P-NL){1'b0}},endp_localp_onehot[0]}: /*select local destination*/ 
-			                                      { {(NL-1){1'b0}} ,portout};
-           if(SELF_LOOP_EN == "NO") begin :nslp
-                remove_sw_loc_one_hot #(
-                    .P(P),
-                    .SW_LOC(SW_LOC)
-                )
-                remove_sw_loc
-                (
-                    .destport_in(destport_onehot),
-                    .destport_out(dest_port_out)
-                );
-            end else begin: slp
-                assign dest_port_out = destport_onehot;            
-            end
+    wire x,y,a,b;
+    assign {x,y,a,b} = dest_port_coded;
+    wire [PPSw-1:0] port_pre_sel_final;
+    assign port_pre_sel_final = 
+        ( ROUTE_TYPE == "DETERMINISTIC") ? {PPSw{1'b1}}:
+        (swap_port_presel) ? ~port_pre_sel : port_pre_sel;
+    always_comb begin 
+        case({a,b})
+            2'b10 : portout = {1'b0,~x,1'b0,x,1'b0};
+            2'b01 : portout = {~y,1'b0,y,1'b0,1'b0};
+            2'b00 : portout = 5'b00001;
+            2'b11 : portout = (port_pre_sel_final[{x,y}]) ?  {~y,1'b0,y,1'b0,1'b0} : {1'b0,~x,1'b0,x,1'b0};
+        endcase
+    end //always
+    
+    //bin_to_one_hot
+    always_comb begin
+        endp_localp_onehot = {NL{1'b0}};
+        endp_localp_onehot[endp_localp_num] = 1'b1;
+    end
+    generate     
+    if(NL==1) begin :slp
+        destport_non_selfloop_fix #(
+            .SELF_LOOP_EN(SELF_LOOP_EN),
+            .P(5),
+            .SW_LOC(SW_LOC)
+        ) conv (
+            .destport_in(portout),
+            .destport_out(dest_port_out)
+        ); 
+    end else begin :mlp
+        wire [P-1 : 0] destport_onehot;
+        assign destport_onehot =(portout[0])? 
+            { endp_localp_onehot[NL-1 : 1] ,{(P-NL){1'b0}},endp_localp_onehot[0]}: /*select local destination*/ 
+            { {(NL-1){1'b0}} ,portout};
+        destport_non_selfloop_fix #(
+            .SELF_LOOP_EN(SELF_LOOP_EN),
+            .P(P),
+            .SW_LOC(SW_LOC)
+        ) remove_sw_loc (
+            .destport_in(destport_onehot),
+            .destport_out(dest_port_out)
+        );
     end
     endgenerate
 endmodule
 
 
 /**************************
- * line_ring_destp_decoder 
- * ************************/
-
+* line_ring_destp_decoder 
+**************************/
 module line_ring_destp_decoder #(
-    parameter ROUTE_TYPE="DETERMINISTIC",
     parameter P=4,
-    parameter DSTPw=2,
-    parameter NL=2,
     parameter ELw=1,
-    parameter PPSw=4,
-    parameter SW_LOC=0,
-    parameter SELF_LOOP_EN= "NO"
+    parameter SW_LOC=0
 )(
     dest_port_coded,
     endp_localp_num,
     dest_port_out   
- );
-  
-    localparam P_1 = (SELF_LOOP_EN == "NO")?  P-1 : P;
-  
+);
+    import pronoc_pkg::*;
+    localparam P_1 = (SELF_LOOP_EN )?  P : P-1;
     input  [DSTPw-1 : 0] dest_port_coded;
     input  [ELw-1 : 0] endp_localp_num;
     output [P_1-1 : 0] dest_port_out;
-   
-    
-    wire [NL-1 : 0] endp_localp_onehot;
-   
+    logic [NL-1 : 0] endp_localp_onehot;
     wire [2:0] portout;
-   
-          
-      line_ring_decode_dstport decoder(
-      	.dstport_one_hot(portout),
-      	.dstport_encoded(dest_port_coded)
-      );
-          
-       
     
-     
-     generate
-     if(NL==1) begin :slp        
-        if(SELF_LOOP_EN == "NO") begin :nslp
-            remove_sw_loc_one_hot #(
-                .P(3),
-                .SW_LOC(SW_LOC)
-            )
-            conv
-            (
-                .destport_in(portout),
-                .destport_out(dest_port_out)
-            ); 
-         end else begin : slp 
-            assign dest_port_out = portout;
-         end
-     end else begin :mlp
-
-            wire [P-1 : 0] destport_onehot;
+    line_ring_decode_dstport decoder(
+        .dstport_one_hot(portout),
+        .dstport_encoded(dest_port_coded)
+    );
     
-            bin_to_one_hot #(
-                .BIN_WIDTH(ELw),
-                .ONE_HOT_WIDTH(NL)
-            )
-            conv
-            (
-                .bin_code(endp_localp_num),
-                .one_hot_code(endp_localp_onehot)
-            );
-            
-           assign destport_onehot =(portout[0])?  { endp_localp_onehot[NL-1 : 1] ,{(P-NL){1'b0}},endp_localp_onehot[0]}: /*select local destination*/ 
-                                                  { {(NL-1){1'b0}} ,portout};
-            if(SELF_LOOP_EN == "NO") begin :nslp
-                remove_sw_loc_one_hot #(
-                    .P(P),
-                    .SW_LOC(SW_LOC)
-                )
-                remove_sw_loc
-                (
-                    .destport_in(destport_onehot),
-                    .destport_out(dest_port_out)
-                ); 
-            end else begin :slp
-                assign dest_port_out = destport_onehot;            
-            end
+    //bin_to_one_hot
+    always_comb begin
+        endp_localp_onehot = {NL{1'b0}};
+        endp_localp_onehot[endp_localp_num] = 1'b1;
+    end
+    generate
+    if(NL==1) begin :_se
+        destport_non_selfloop_fix #(
+            .SELF_LOOP_EN(SELF_LOOP_EN),
+            .P(3),
+            .SW_LOC(SW_LOC)
+        ) conv (
+            .destport_in(portout),
+            .destport_out(dest_port_out)
+        ); 
+    end else begin :_me
+        wire [P-1 : 0] destport_onehot;
+        assign destport_onehot =(portout[0])? 
+            { endp_localp_onehot[NL-1 : 1] ,{(P-NL){1'b0}},endp_localp_onehot[0]}: /*select local destination*/ 
+            { {(NL-1){1'b0}} ,portout};
+        destport_non_selfloop_fix #(
+            .SELF_LOOP_EN(SELF_LOOP_EN),
+            .P(P),
+            .SW_LOC(SW_LOC)
+        ) remove_sw_loc (
+            .destport_in(destport_onehot),
+            .destport_out(dest_port_out)
+        ); 
     end
     endgenerate
 endmodule
 
-
-
-
 /*****************
-*   mesh_torus_dynamic_portsel_control
+*   regular_topo_dynamic_portsel_control
 *****************/
-
-
-module  mesh_torus_dynamic_portsel_control #(
-    parameter  P = 5,
-    parameter ROUTE_TYPE =  "FULL_ADAPTIVE",    // "FULL_ADAPTIVE", "PAR_ADAPTIVE"  
-    parameter V = 4,
-    parameter DSTPw=4,
-    parameter SSA_EN ="NO",
-    parameter PPSw=4,
-    parameter [V-1  :   0] ESCAP_VC_MASK = 4'b1000   // mask scape vc, valid only for full adaptive       
+module  regular_topo_dynamic_portsel_control #(
+    parameter  P = 5
 )(   
     dest_port_coded_all,
     ivc_request_all,
@@ -1740,100 +1131,63 @@ module  mesh_torus_dynamic_portsel_control #(
     reset,
     clk    
 );
-    
-    
+    import pronoc_pkg::*;
     localparam
         PV = V * P,
         PVV= PV * V,    
         PVDSTPw = PV * DSTPw;
-                
-     localparam LOCAL   =   0,  
-                EAST    =   1, 
-                NORTH   =   2,  
-                WEST    =   3,  
-                SOUTH   =   4;  
-
-   
-    input   [PVDSTPw-1  :   0]  dest_port_coded_all;
-    input   [PV-1       :   0]  ivc_request_all;
-    input   [PV-1       :   0]  ovc_is_assigned_all;  
-    input   [PVV-1      :   0]  masked_ovc_request_all;
- 
- 
-    input   [PPSw-1      :   0]  port_pre_sel;
-    output  [PV-1       :   0]  swap_port_presel;   
-    output  [PV-1       :   0]  sel;
+    
+    input   [PVDSTPw-1 : 0]  dest_port_coded_all;
+    input   [PV-1 : 0]  ivc_request_all;
+    input   [PV-1 : 0]  ovc_is_assigned_all;  
+    input   [PVV-1 : 0]  masked_ovc_request_all;
+    input   [PPSw-1 : 0]  port_pre_sel;
+    output  [PV-1 : 0]  swap_port_presel;   
+    output  [PV-1 : 0]  sel;
     output  [PVDSTPw-1 : 0] destport_clear_all;
     input   [PV-1 : 0] ivc_num_getting_ovc_grant; 
     input   [PV-1 : 0] ssa_ivc_num_getting_ovc_grant_all;       
-    input                       reset,clk;  
-    
-
-    wire    [PV-1       :   0]  non_assigned_ovc_request_all; 
-    wire    [PV-1       :   0]  y_evc_forbiden,x_evc_forbiden;  
-    wire    [PPSw-1      :   0]  port_pre_sel_perport            [P-1    :   0];
-  
-   
-    
-    assign non_assigned_ovc_request_all =   ivc_request_all & ~ovc_is_assigned_all;  
-    
-    
-    assign port_pre_sel_perport[LOCAL]   = port_pre_sel;
-    assign port_pre_sel_perport[EAST]    = {2'b00,port_pre_sel[1:0]};
-    assign port_pre_sel_perport[NORTH]   = {1'b0,port_pre_sel[2],1'b0,port_pre_sel[0]};
-    assign port_pre_sel_perport[WEST]    = {port_pre_sel[3:2],2'b0};
-    assign port_pre_sel_perport[SOUTH]   = {port_pre_sel[3],1'b0,port_pre_sel[1],1'b0};
-    
-   
-    wire    [PV-1   :   0]  avc_unavailable; 
+    input   reset,clk;  
+    
+    wire [PV-1 : 0]  non_assigned_ovc_request_all; 
+    wire [PV-1 : 0]  y_evc_forbiden,x_evc_forbiden;  
+    wire [PPSw-1 : 0]  port_pre_sel_perport [P-1 : 0];
+    assign non_assigned_ovc_request_all = ivc_request_all & ~ovc_is_assigned_all;  
+    assign port_pre_sel_perport[LOCAL] = port_pre_sel;
+    assign port_pre_sel_perport[EAST] = {2'b00,port_pre_sel[1:0]};
+    assign port_pre_sel_perport[NORTH] = {1'b0,port_pre_sel[2],1'b0,port_pre_sel[0]};
+    assign port_pre_sel_perport[WEST] = {port_pre_sel[3:2],2'b0};
+    assign port_pre_sel_perport[SOUTH] = {port_pre_sel[3],1'b0,port_pre_sel[1],1'b0};
+    wire    [PV-1 : 0]  avc_unavailable; 
     genvar i;
     generate   
-    
-    
-    for(i=0;i< PV;i=i+1) begin :all_vc_loop
+    for(i=0;i< PV;i=i+1) begin : PV_
         localparam SW_LOC = ((i/V)<5)? i/V : LOCAL;
-     
-              
-        mesh_torus_port_selector #(
-           .SW_LOC     (SW_LOC),
-           .PPSw(PPSw)
-        )
-        the_portsel
-        (
-           .port_pre_sel       (port_pre_sel_perport[SW_LOC]),
-           .swap_port_presel   (swap_port_presel[i]),
-           .sel                (sel[i]),
-           .dest_port_in       (dest_port_coded_all[((i+1)*DSTPw)-1 : i*DSTPw]),
-           .y_evc_forbiden     (y_evc_forbiden[i]),
-           .x_evc_forbiden     (x_evc_forbiden[i])
-          );
-
-        mesh_tori_dspt_clear_gen #(
-            .SSA_EN(SSA_EN),
-            .DSTPw(DSTPw),
+        regular_topo_port_selector #(
+            .SW_LOC (SW_LOC)
+        ) the_portsel (
+            .port_pre_sel       (port_pre_sel_perport[SW_LOC]),
+            .swap_port_presel   (swap_port_presel[i]),
+            .sel                (sel[i]),
+            .dest_port_in       (dest_port_coded_all[((i+1)*DSTPw)-1 : i*DSTPw]),
+            .y_evc_forbiden     (y_evc_forbiden[i]),
+            .x_evc_forbiden     (x_evc_forbiden[i])
+        );
+        regular_topo_dspt_clear_gen #(
             .SW_LOC(SW_LOC)
-        )
-        dspt_clear_gen
-        (
+        ) dspt_clear_gen(
             .destport_clear(destport_clear_all[((i+1)*DSTPw)-1 : i*DSTPw]),
             .ivc_num_getting_ovc_grant(ivc_num_getting_ovc_grant[i]),
             .sel(sel[i]),
             .ssa_ivc_num_getting_ovc_grant(ssa_ivc_num_getting_ovc_grant_all[i])
         );                           
-                         
-          
         /* verilator lint_off WIDTH */   
-        if(ROUTE_TYPE ==  "FULL_ADAPTIVE") begin: full_adpt
+        if(ROUTE_TYPE == "FULL_ADAPTIVE") begin: full_adpt
         /* verilator lint_on WIDTH */ 
-        assign avc_unavailable[i] = (masked_ovc_request_all [((i+1)*V)-1 : i*V] & ~ESCAP_VC_MASK) == {V{1'b0}};
-                        
-            mesh_torus_swap_port_presel_gen #(
-                .V(V),
-                .ESCAP_VC_MASK(ESCAP_VC_MASK),       
+            assign avc_unavailable[i] = (masked_ovc_request_all [((i+1)*V)-1 : i*V] & ~ESCAP_VC_MASK) == {V{1'b0}};
+            regular_topo_swap_port_presel_gen #(
                 .VC_NUM(i)
-            )           
-            the_swap_port_presel
-            (
+            ) the_swap_port_presel (
                 .avc_unavailable(avc_unavailable[i]),
                 .y_evc_forbiden(y_evc_forbiden[i]),
                 .x_evc_forbiden(x_evc_forbiden[i]),
@@ -1843,21 +1197,10 @@ module  mesh_torus_dynamic_portsel_control #(
                 .reset(reset),
                 .swap_port_presel(swap_port_presel[i])
             );
-                       
-            
         end else begin : partial_adpt
-          
             assign swap_port_presel[i]=1'b0;
             assign avc_unavailable[i]=1'b0;
-            
         end// ROUTE_TYPE
     end//for    
-     
 endgenerate
-endmodule        
-
-
-
-
-    
-
+endmodule
diff --git a/mpsoc/rtl/src_noc/mesh_torus_noc_top.sv b/mpsoc/rtl/src_noc/mesh_torus_noc_top.sv
index 9c08930..64099a5 100644
--- a/mpsoc/rtl/src_noc/mesh_torus_noc_top.sv
+++ b/mpsoc/rtl/src_noc/mesh_torus_noc_top.sv
@@ -1,7 +1,6 @@
 `include "pronoc_def.v"
-
 /**********************************************************************
-**    File:  mesh_torus_noc.v
+**    File:  regular_topo_noc_top.v
 **    
 **    Copyright (C) 2014-2017  Alireza Monemi
 **    
@@ -27,220 +26,163 @@
 **
 **************************************************************/
 
-
-//`define router_id(x,y)                         ((y * NX) +    x)
-//`define endp_id(x,y,l)                         ((y * NX) +    x) * NL + l 
-
-
-
-module mesh_torus_noc_top #(
-	parameter NOC_ID=0
-) (
+module regular_topo_noc_top  (
     reset,
-    clk,    
+    clk,
     chan_in_all,
     chan_out_all,
     router_event
 );
-
-    `NOC_CONF
     
-	input   clk,reset;
-	//Endpoints ports 
-	input   smartflit_chanel_t chan_in_all  [NE-1 : 0];
-	output  smartflit_chanel_t chan_out_all [NE-1 : 0];
-	
-	//Events
-	output  router_event_t  router_event [NR-1 : 0][MAX_P-1 : 0];
-	
-	//all routers port 
-	smartflit_chanel_t    router_chan_in   [NR-1 :0][MAX_P-1 : 0];
-	smartflit_chanel_t    router_chan_out  [NR-1 :0][MAX_P-1 : 0];
-
-	wire [RAw-1 : 0] current_r_addr [NR-1 : 0];	
+    import pronoc_pkg::*;
 
-	genvar x,y,l;
-	generate 
-	/* verilator lint_off WIDTH */ 
-		if( TOPOLOGY == "RING" || TOPOLOGY == "LINE") begin : ring_line 
-			/* verilator lint_on WIDTH */ 
-			for  (x=0;   x<NX; x=x+1) begin :Router_
-             
-                       
-				assign current_r_addr [x] = x[RAw-1: 0];   
-	
-				router_top #(
-					.NOC_ID(NOC_ID),
-					.P               (MAX_P          )
-					) the_router (
-					.current_r_id    (x),
-					.current_r_addr  (current_r_addr [x]), 
-					.chan_in         (router_chan_in [x]), 
-					.chan_out        (router_chan_out[x]), 
-					.router_event    (router_event[x]),
-					.clk             (clk            ), 
-					.reset           (reset          ));
-	
-				if(x    <   NX-1) begin: not_last_node            
-					assign  router_chan_in[x][FORWARD] = router_chan_out [(x+1)][BACKWARD];
-				end else begin :last_node
-					/* verilator lint_off WIDTH */ 
-					if(TOPOLOGY == "LINE") begin : line_last_x
-					/* verilator lint_on WIDTH */ 
-						assign  router_chan_in[x][FORWARD]= {SMARTFLIT_CHANEL_w{1'b0}};										      
-					end else begin : ring_last_x
-						assign router_chan_in[x][FORWARD]= router_chan_out [0][BACKWARD];
-					end
-				end 
-            
-				if(x>0)begin :not_first_x
-					assign router_chan_in[x][BACKWARD]= router_chan_out [(x-1)][FORWARD];					
-				end else begin :first_x
-					/* verilator lint_off WIDTH */ 
-					if(TOPOLOGY == "LINE") begin : line_first_x
-						/* verilator lint_on WIDTH */ 
-						assign  router_chan_in[x][BACKWARD]={SMARTFLIT_CHANEL_w{1'b0}};					
-					end else begin : ring_first_x
-						assign  router_chan_in[x][BACKWARD]= router_chan_out [(NX-1)][FORWARD];											
-					end
-				end            
-            
-				// connect other local ports
-				for  (l=0;   l<NL; l=l+1) begin :locals
-					localparam ENDPID = fmesh_endp_id(x,0,l); 
-					localparam LOCALP = (l==0) ? l : l + R2R_CHANELS_MESH_TORI; // first local port is connected to router port 0. The rest are connected at the end  
-					assign router_chan_in[x][LOCALP]= chan_in_all [ENDPID];
-					assign chan_out_all [ENDPID] = router_chan_out[x][LOCALP];
-					                
-				end// locals               
-			end//x    
-			
-		end else begin :mesh_torus
-			for (y=0;    y<NY;    y=y+1) begin: y_loop
-				for (x=0;    x<NX; x=x+1) begin :x_loop
-				localparam R_ADDR = (y<<NXw) + x;            
-				localparam RID = (y * NX) +    x;					
-				assign current_r_addr [RID] = R_ADDR[RAw-1 :0];
-             	
-					router_top #(
-						.NOC_ID(NOC_ID),
-						.P               (MAX_P          )
-					) the_router (					
-						.current_r_id    (RID),
-						.current_r_addr  (current_r_addr [RID]),    
-						.chan_in         (router_chan_in [RID]), 
-						.chan_out        (router_chan_out[RID]), 
-						.router_event    (router_event[RID]),
-						.clk             (clk            ), 
-						.reset           (reset          ));
-					
-							
-				/*
-    in [x,y][east] <------  out [x+1 ,y  ][west] ;
-    in [x,y][north] <------ out [x   ,y-1][south] ;
-    in [x,y][west] <------  out [x-1 ,y  ][east] ;
-    in [x,y][south] <------ out [x   ,y+1][north] ;
-				 */    
-        
-        
-				if(x    <    NX-1) begin: not_last_x
-					assign router_chan_in[fmesh_router_id(x,y)][EAST]= router_chan_out [fmesh_router_id(x+1,y)][WEST];
-					//assign    router_credit_in_all [`SELECT_WIRE(x,y,EAST,V)] = router_credit_out_all [`SELECT_WIRE((x+1),y,WEST,V)];					
-				end else begin :last_x
-					/* verilator lint_off WIDTH */ 
-					if(TOPOLOGY == "MESH") begin :last_x_mesh
-					/* verilator lint_on WIDTH */ 
-						assign router_chan_in[fmesh_router_id(x,y)][EAST] = {SMARTFLIT_CHANEL_w{1'b0}};					
-					/* verilator lint_off WIDTH */ 
-					end else if(TOPOLOGY == "TORUS") begin : last_x_torus
-					/* verilator lint_on WIDTH */ 
-						assign router_chan_in[fmesh_router_id(x,y)][EAST] = router_chan_out [fmesh_router_id(0,y)][WEST];						
-					/* verilator lint_off WIDTH */ 
-					end else if(TOPOLOGY == "FMESH") begin : last_x_fmesh //connect to endp
-					/* verilator lint_on WIDTH */ 
-						localparam EAST_ID = NX*NY*NL + 2*NX + NY +y; 
-						assign router_chan_in [fmesh_router_id(x,y)][EAST] =    chan_in_all [EAST_ID];
-						assign chan_out_all [EAST_ID] = router_chan_out [fmesh_router_id(x,y)][EAST];						 
-					end //topology
-				end 
-            
-        
-				if(y>0) begin : not_first_y
-					assign router_chan_in[fmesh_router_id(x,y)][NORTH] =  router_chan_out [fmesh_router_id(x,(y-1))][SOUTH];					
-				end else begin :first_y
-					/* verilator lint_off WIDTH */ 
-					if(TOPOLOGY == "MESH") begin : first_y_mesh
-					/* verilator lint_on WIDTH */ 
-						assign router_chan_in[fmesh_router_id(x,y)][NORTH] =  {SMARTFLIT_CHANEL_w{1'b0}};												
-					/* verilator lint_off WIDTH */ 
-					end else if(TOPOLOGY == "TORUS") begin :first_y_torus
-					/* verilator lint_on WIDTH */ 
-						assign router_chan_in[fmesh_router_id(x,y)][NORTH] =  router_chan_out [fmesh_router_id(x,(NY-1))][SOUTH];						
-					/* verilator lint_off WIDTH */ 
-					end else if(TOPOLOGY == "FMESH") begin : first_y_fmesh //connect to endp
-					/* verilator lint_on WIDTH */ 	
-						localparam NORTH_ID = NX*NY*NL + x; 
-						assign router_chan_in [fmesh_router_id(x,y)][NORTH] =    chan_in_all [NORTH_ID];
-						assign chan_out_all [NORTH_ID] = router_chan_out [fmesh_router_id(x,y)][NORTH];
-					end//topology
-				end//y>0
-            
-            
-				if(x>0)begin :not_first_x
-					assign    router_chan_in[fmesh_router_id(x,y)][WEST] =  router_chan_out [fmesh_router_id((x-1),y)][EAST];					
-				end else begin :first_x
-					/* verilator lint_off WIDTH */ 
-					if(TOPOLOGY == "MESH") begin :first_x_mesh
-					/* verilator lint_on WIDTH */ 
-						assign    router_chan_in[fmesh_router_id(x,y)][WEST] =   {SMARTFLIT_CHANEL_w{1'b0}};						
-					/* verilator lint_off WIDTH */                
-					end else if(TOPOLOGY == "TORUS") begin :first_x_torus
-					/* verilator lint_on WIDTH */ 
-						assign    router_chan_in[fmesh_router_id(x,y)][WEST] =   router_chan_out [fmesh_router_id((NX-1),y)][EAST] ;						
-					/* verilator lint_off WIDTH */ 
-					end else if(TOPOLOGY == "FMESH") begin : first_x_fmesh //connect to endp
-					/* verilator lint_on WIDTH */ 	
-						localparam WEST_ID = NX*NY*NL +2*NX + y; 
-						assign router_chan_in [fmesh_router_id(x,y)][WEST] =    chan_in_all [WEST_ID];
-						assign chan_out_all [WEST_ID] = router_chan_out [fmesh_router_id(x,y)][WEST];						
-					end//topology
-				end    
+    input   clk,reset;
+    //Endpoints ports 
+    input   smartflit_chanel_t chan_in_all  [NE-1 : 0];
+    output  smartflit_chanel_t chan_out_all [NE-1 : 0];
+    
+    //Events
+    output  router_event_t  router_event [NR-1 : 0][MAX_P-1 : 0];
+    
+    //all routers port 
+    smartflit_chanel_t    router_chan_in   [NR-1 :0][MAX_P-1 : 0];
+    smartflit_chanel_t    router_chan_out  [NR-1 :0][MAX_P-1 : 0];
+    
+    router_config_t router_config_in [NR-1 :0];
+    
+    //Unused Input channels are connected to ground
+    smartflit_chanel_t is_grounded;
+    assign  is_grounded= {SMARTFLIT_CHANEL_w{1'b0}};   
+    
+    genvar x,y,l;
+    generate 
+    if( IS_1D_TOPO ) begin : D1_
+        for  (x=0; x<NX; x=x+1) begin :R_
+            localparam RID =  x;
+            assign router_config_in[x].router_addr = RID[RAw-1: 0];
+            assign router_config_in[x].router_id = RID[NRw-1: 0];
+            router_top #(
+                .ROUTER_ID(RID),
+                .P (MAX_P)
+            ) the_router (
+                .router_config_in(router_config_in[RID]),
+                .chan_in(router_chan_in [RID]),
+                .chan_out(router_chan_out[RID]),
+                .router_event(router_event[RID]),
+                .clk(clk), 
+                .reset(reset)
+            );
+            localparam XFWD=(x < NX-1)? x+1 : 0;
+            assign router_chan_in[x][FORWARD] = 
+                (IS_LINE & (x == NX-1))? is_grounded : router_chan_out[XFWD][BACKWARD];
+            localparam XBCK=(x > 0)? x-1 : NX-1;
+            assign router_chan_in[x][BACKWARD] =  
+                (IS_LINE & (x==0))? is_grounded : router_chan_out[XBCK][FORWARD];
             
-				if(y    <    NY-1) begin : firsty
-					assign  router_chan_in[fmesh_router_id(x,y)][SOUTH] =    router_chan_out [fmesh_router_id(x,(y+1))][NORTH];					
-				end else     begin : lasty
-					/* verilator lint_off WIDTH */ 
-					if(TOPOLOGY == "MESH") begin :ly_mesh
-						/* verilator lint_on WIDTH */ 
-						assign  router_chan_in[fmesh_router_id(x,y)][SOUTH]=  {SMARTFLIT_CHANEL_w{1'b0}};						
-						/* verilator lint_off WIDTH */ 
-					end else if(TOPOLOGY == "TORUS") begin :ly_torus
-						/* verilator lint_on WIDTH */ 
-						assign  router_chan_in[fmesh_router_id(x,y)][SOUTH]=    router_chan_out [fmesh_router_id(x,0)][NORTH];						
-					end else if(TOPOLOGY == "FMESH") begin : ly_fmesh //connect to endp
-						/* verilator lint_on WIDTH */ 	
-						localparam SOUTH_ID = NX*NY*NL + NX + x; 
-						assign router_chan_in [fmesh_router_id(x,y)][SOUTH] =    chan_in_all [SOUTH_ID];
-						assign chan_out_all [SOUTH_ID] = router_chan_out [fmesh_router_id(x,y)][SOUTH];
-					end//topology
-				end          
-        
+            // connect other local ports
+            for  (l=0;   l<NL; l=l+1) begin :locals
+                    localparam ENDP_ID = fmesh_endp_id(x,0,l); 
+                    localparam LOCALP = (l==0) ? l : l + R2R_CHANELS_REGULAR; // first local port is connected to router port 0. The rest are connected at the end  
+                    assign router_chan_in[x][LOCALP]= chan_in_all [ENDP_ID];
+                    assign chan_out_all [ENDP_ID] = router_chan_out[x][LOCALP];
+            end// locals
+        end//x
         
-				// endpoint(s) connection
-				// connect other local ports
-				for  (l=0;   l<NL; l=l+1) begin :locals
-					localparam ENDPID = fmesh_endp_id(x,y,l); 
-					localparam LOCALP = (l==0) ? l : l + R2R_CHANELS_MESH_TORI; // first local port is connected to router port 0. The rest are connected at the end  
+    end else if (IS_2D_TOPO) begin : D2_
+        for (y=0; y<NY; y=y+1) begin: Y_
+            for (x=0; x<NX; x=x+1) begin :X_
+                localparam R_ADDR = (y<<NXw) + x;
+                localparam RID = (y * NX) + x;
+                //FMESH IDs
+                localparam EAST_ID  = (IS_FMESH) ? (NX*NY*NL) + (2*NX) + NY + y : 0;
+                localparam NORTH_ID = (IS_FMESH) ? (NX*NY*NL) + x : 0; 
+                localparam WEST_ID  = (IS_FMESH) ? (NX*NY*NL) + (2*NX) + y : 0;
+                localparam SOUTH_ID = (IS_FMESH) ? (NX*NY*NL) + NX + x : 0;  
+                assign router_config_in[RID].router_addr = R_ADDR[RAw-1 :0];
+                assign router_config_in[RID].router_id = RID[NRw-1: 0];
                 
-					assign router_chan_in [fmesh_router_id(x,y)][LOCALP] =    chan_in_all [ENDPID];
-					assign chan_out_all [ENDPID] = router_chan_out [fmesh_router_id(x,y)][LOCALP];			
-                              
-				end// locals                 
-    
-				end //y
-				end //x
-				end// mesh_torus        
-    
-				endgenerate
-	
-endmodule	
+                router_top #(
+                    .ROUTER_ID(RID),
+                    .P(MAX_P)
+                ) the_router (
+                    .router_config_in(router_config_in[RID]), 
+                    .chan_in(router_chan_in [RID]), 
+                    .chan_out(router_chan_out[RID]), 
+                    .router_event(router_event[RID]),
+                    .clk(clk), 
+                    .reset(reset)
+                );
+                /*
+                in [x,y][east] <------  out [x+1 ,y  ][west] ;
+                in [x,y][north] <------ out [x   ,y-1][south] ;
+                in [x,y][west] <------  out [x-1 ,y  ][east] ;
+                in [x,y][south] <------ out [x   ,y+1][north] ;
+                 */
+                localparam EAST_RID = (x < NX-1) ? fmesh_router_id(x+1, y) : fmesh_router_id(0, y);
+                assign router_chan_in[fmesh_router_id(x, y)][EAST] = 
+                    ((x < NX-1) | IS_TORUS) ? router_chan_out[ EAST_RID][WEST] : //not_last_x
+                    (IS_MESH)  ? is_grounded : chan_in_all[EAST_ID]; //last_x_fmesh
+                
+                localparam NORTH_RID = (y > 0) ? fmesh_router_id(x, y-1) : fmesh_router_id(x, NY-1);
+                assign router_chan_in[fmesh_router_id(x, y)][NORTH] = 
+                    ((y > 0) | IS_TORUS ) ? router_chan_out[NORTH_RID][SOUTH] : //not_first_y
+                    (IS_MESH) ? is_grounded : chan_in_all[NORTH_ID]; //first_y_fmesh
+                
+                localparam WEST_RID = (x > 0) ? fmesh_router_id(x-1, y) : fmesh_router_id(NX-1, y);  //not_first_x
+                assign router_chan_in[fmesh_router_id(x, y)][WEST] = 
+                    ((x > 0) | IS_TORUS) ? router_chan_out[WEST_RID][EAST] :  //not_first_x
+                    (IS_MESH) ? is_grounded :  chan_in_all[WEST_ID]; //first_x_fmesh
+                
+                localparam SOUTH_RID = (y < NY-1) ? fmesh_router_id(x, y+1) : fmesh_router_id(x, 0);
+                assign router_chan_in[fmesh_router_id(x, y)][SOUTH] = 
+                    (y < NY-1 || IS_TORUS)? router_chan_out[SOUTH_RID][NORTH] : //not_last_y
+                    (IS_MESH)?  is_grounded : chan_in_all[SOUTH_ID];  //last_y_fmesh
+                
+                if(IS_FMESH) begin : fmesh //connect to endpoints
+                    localparam EAST_ENDP_LOC=NL;
+                    localparam NORTH_ENDP_LOC=NL+1;
+                    localparam WEST_ENDP_LOC= (NX==1) ? (NL+2) : EAST_ENDP_LOC;
+                    localparam SOUTH_ENDP_LOC= 
+                        (NY==1 && NX==1) ? (NL+3) :
+                        (NY==1) ? (NL+2) : NORTH_ENDP_LOC;
+                    if(x == NX-1)  begin 
+                        localparam [EAw-1 : 0] EAST_ADDR =  EAw'(fmesh_endp_addr(EAST_ID));
+                        assign chan_out_all [EAST_ID] = router_chan_out [fmesh_router_id(x,y)][EAST];
+                        assign router_config_in[RID].endp_addrs[(EAST_ENDP_LOC+1)*EAw -1 :  EAST_ENDP_LOC*EAw] = EAST_ADDR[EAw-1:0];
+                        assign router_config_in[RID].endp_ids[(EAST_ENDP_LOC+1)*NEw -1 :  EAST_ENDP_LOC*NEw] = EAST_ID[NEw-1:0];
+                    end
+                    if(y == 0 ) begin 
+                        localparam [EAw-1 : 0] NORTH_ADDR =  EAw'(fmesh_endp_addr(NORTH_ID));
+                        assign chan_out_all [NORTH_ID] = router_chan_out [fmesh_router_id(x,y)][NORTH];
+                        assign router_config_in[RID].endp_addrs[(NORTH_ENDP_LOC+1)*EAw -1 :  NORTH_ENDP_LOC*EAw] = NORTH_ADDR[EAw-1:0];
+                        assign router_config_in[RID].endp_ids[(NORTH_ENDP_LOC+1)*NEw -1 :  NORTH_ENDP_LOC*NEw] =NORTH_ID[NEw-1:0];
+                    end
+                    if (x == 0 ) begin
+                        localparam [EAw-1 : 0] WEST_ADDR =   EAw'(fmesh_endp_addr(WEST_ID));
+                        assign chan_out_all [WEST_ID] = router_chan_out[fmesh_router_id(x, y)][WEST];
+                        assign router_config_in[RID].endp_addrs[(WEST_ENDP_LOC+1)*EAw -1 :  WEST_ENDP_LOC*EAw] = WEST_ADDR[EAw-1:0];
+                        assign router_config_in[RID].endp_ids[(WEST_ENDP_LOC+1)*NEw -1 :  WEST_ENDP_LOC*NEw] =WEST_ID[NEw-1:0];
+                    end
+                    if(y == NY-1 ) begin 
+                        localparam [EAw-1 : 0] SOUTH_ADDR =  EAw'(fmesh_endp_addr(SOUTH_ID));
+                        assign chan_out_all [SOUTH_ID] = router_chan_out[fmesh_router_id(x, y)][SOUTH];
+                        assign router_config_in[RID].endp_addrs[(SOUTH_ENDP_LOC+1)*EAw -1 :  SOUTH_ENDP_LOC*EAw] = SOUTH_ADDR[EAw-1:0];
+                        assign router_config_in[RID].endp_ids[(SOUTH_ENDP_LOC+1)*NEw -1 :  SOUTH_ENDP_LOC*NEw] =SOUTH_ID[NEw-1:0];
+                    end
+                end
+                // endpoint(s) connection
+                // connect other local ports
+                for  (l=0; l<NL; l=l+1) begin : L_
+                    localparam ENDP_ID = fmesh_endp_id(x,y,l); 
+                    localparam LOCALP = (l==0) ? l : l + R2R_CHANELS_REGULAR; // first local port is connected to router port 0. The rest are connected at the end  
+                    localparam ENDP_ADDR = (IS_REGULAR_TOPO) ? regular_topo_endp_addr(ENDP_ID): fmesh_endp_addr(ENDP_ID);
+                    assign router_chan_in [fmesh_router_id(x,y)][LOCALP] =    chan_in_all [ENDP_ID];
+                    assign chan_out_all [ENDP_ID] = router_chan_out [fmesh_router_id(x,y)][LOCALP];
+                    assign router_config_in[RID].endp_addrs[(l+1)*EAw -1 :  l*EAw] = EAw'(ENDP_ADDR);
+                    assign router_config_in[RID].endp_ids[(l+1)*NEw -1 :  l*NEw] = NEw'(ENDP_ID);
+                end// locals
+            end //y
+        end //x
+    end// D2_
+    endgenerate
+endmodule
diff --git a/mpsoc/rtl/src_noc/mesh_torus_routting.sv b/mpsoc/rtl/src_noc/mesh_torus_routting.sv
new file mode 100644
index 0000000..22af96a
--- /dev/null
+++ b/mpsoc/rtl/src_noc/mesh_torus_routting.sv
@@ -0,0 +1,842 @@
+`include "pronoc_def.v"
+/************************************
+*
+*    regular_topo_look_ahead_routing
+*
+*************************************/
+
+module regular_topo_look_ahead_routing (
+    dest_router_addr_i,
+    destport_encoded,   // current router destination port number
+    lkdestport_encoded, // look ahead destination port number
+    neighbors_r_addr,
+    reset,
+    clk
+);
+    import pronoc_pkg::*;
+    localparam  P = (IS_MESH_3D)? 7 : ( IS_MESH || IS_FMESH || IS_TORUS ) ? 5 : 3;
+    
+    localparam  P_1 = P-1;
+    input regular_topo_router_addr_t dest_router_addr_i;
+    input  [DSTPw-1  :   0] destport_encoded;
+    output [DSTPw-1  :   0] lkdestport_encoded;
+    input  [RAw-1:  0]  neighbors_r_addr [P-1 : 0];
+    input  reset,clk;
+    
+    regular_topo_router_addr_t dest_router_addr_f;
+    logic [DSTPw-1  :   0]  destport_delayed;
+    // routing algorithm
+    generate 
+    if( IS_DETERMINISTIC ) begin :dtrmst
+        regular_topo_deterministic_look_ahead_routing #(
+            .P(P)
+        ) deterministic_look_ahead(
+            .dest_router_addr_i(dest_router_addr_f),
+            .destport(destport_delayed),
+            .lkdestport(lkdestport_encoded),
+            .neighbors_r_addr(neighbors_r_addr)
+        );
+    end else begin :adapt
+        regular_topo_adaptive_look_ahead_routing #(
+            .P(P)
+        ) adaptive_look_ahead (
+            .dest_router_addr_i(dest_router_addr_f),
+            .destport_encoded(destport_delayed),
+            .lkdestport_encoded(lkdestport_encoded),
+            .neighbors_r_addr(neighbors_r_addr)
+        );
+    end
+    endgenerate
+    always_ff @ (`pronoc_clk_reset_edge) begin
+        if (`pronoc_reset) begin
+            dest_router_addr_f <= '0;
+            destport_delayed <= '0;
+        end else begin
+            dest_router_addr_f <= dest_router_addr_i;
+            destport_delayed <= destport_encoded;
+        end
+    end
+endmodule
+
+
+/************************************************
+*    deterministic_look_ahead_routing
+**********************************************/
+module  regular_topo_deterministic_look_ahead_routing #(
+    parameter P =5
+) (
+    dest_router_addr_i,
+    destport,   // current router destination port number
+    neighbors_r_addr,
+    lkdestport // look ahead destination port number
+);
+    import pronoc_pkg::*;
+    localparam  
+        P_1 = P-1,
+        Pw= log2(P);
+    
+    input regular_topo_router_addr_t dest_router_addr_i;
+    input [DSTPw-1  :   0]  destport;
+    input [RAw-1 : 0]  neighbors_r_addr [P-1 : 0];
+    output [DSTPw-1  :   0] lkdestport;
+    wire [Pw-1 : 0]  dstport_decimal;
+    genvar i;
+    generate 
+    if(IS_MESH_3D) begin: threeD
+        assign dstport_decimal = destport;
+    end else if (IS_MESH || IS_TORUS || IS_FMESH ) begin: twoD
+        regular_topo_destport_decode_decimal decoder(
+            .destport_encoded(destport),
+            .destport_decimal(dstport_decimal)
+        );       
+    end else begin :oneD
+        line_ring_destport_decode_decimal  decoder(
+            .destport_encoded(destport),
+            .destport_decimal(dstport_decimal)
+        );
+    end
+    endgenerate 
+    wire [RAw-1 : 0] next_router_addr = neighbors_r_addr[dstport_decimal];
+    
+    wire [DSTPw-1  :   0] lkdestport_encoded;
+    regular_topo_router_addr_t next_router_addr_struct;
+    assign next_router_addr_struct = regular_topo_router_addr_t'(next_router_addr);
+    regular_topo_conventional_routing #(
+        .LOCATED_IN_NI(0)
+    ) conv_routing (
+        .current_router_addr_i(next_router_addr_struct),
+        .dest_router_addr_i(dest_router_addr_i),
+        .destport(lkdestport_encoded)
+    );
+    
+    //take the value of a&b only.  x&y can be obtained from destport in the router
+    assign lkdestport = lkdestport_encoded;//[1: 0];
+endmodule
+
+
+/************************************************
+*        adaptive_look_ahead_routing
+**********************************************/
+module  regular_topo_adaptive_look_ahead_routing #(
+    parameter P =5
+)(
+    dest_router_addr_i, 
+    neighbors_r_addr,
+    destport_encoded,   // current router destination port      
+    lkdestport_encoded // look ahead destination port 
+);
+    import pronoc_pkg::*;
+    localparam 
+        P_1 = P-1,
+        Pw = log2(P);
+    input regular_topo_router_addr_t   dest_router_addr_i;
+    input [RAw-1 : 0]  neighbors_r_addr [P-1 : 0];
+    input [P_1-1 : 0]  destport_encoded;
+    output  [P_1-1 : 0]  lkdestport_encoded;
+    /**************************
+    *    destination-port coded
+    *            x: 1 EAST, 0 WEST  
+    *            y: 1 NORTH, 0 SOUTH
+    *            ab: 00 : LOCAL, 10: xdir, 01: ydir, 11 x&y dir 
+    **************************/       
+    wire x,y,a,b;
+    wire [P_1-1 : 0]  lkdestport_x,lkdestport_y;
+    reg [Pw-1 : 0]  destport_x, destport_y;
+    
+    assign {x,y,a,b} = destport_encoded;
+    
+    always_comb begin
+    destport_x = 0;
+    destport_y = 0;
+    case ({a, b})   
+        2'b10: destport_x = (x) ? Pw'(EAST) : Pw'(WEST); // 1=East, 2=West
+        2'b01: destport_y = (y) ? Pw'(NORTH) : Pw'(SOUTH); // 3=North, 4=South
+        2'b11: begin
+            // Both directions
+            destport_x = (x) ? Pw'(EAST) : Pw'(WEST);
+            destport_y = (y) ? Pw'(NORTH) : Pw'(SOUTH);
+        end
+        2'b00: begin
+            // Local node
+            destport_x = Pw'(LOCAL);
+            destport_y = Pw'(LOCAL);
+        end
+    endcase
+    end
+    
+    regular_topo_router_addr_t next_router_addr_x, next_router_addr_y;
+    assign next_router_addr_x = regular_topo_router_addr_t'(neighbors_r_addr[destport_x]);
+    assign next_router_addr_y = regular_topo_router_addr_t'(neighbors_r_addr[destport_y]);
+    
+    regular_topo_conventional_routing #(
+        .LOCATED_IN_NI(0)
+    ) conv_route_x (
+        .current_router_addr_i(next_router_addr_x),
+        .dest_router_addr_i(dest_router_addr_i),
+        .destport(lkdestport_x)
+    );
+    
+    regular_topo_conventional_routing #(
+        .LOCATED_IN_NI(0)
+    ) conv_route_y (
+        .current_router_addr_i(next_router_addr_y),
+        .dest_router_addr_i(dest_router_addr_i),
+        .destport(lkdestport_y)
+    );
+    //take the value of a&b only.  x&y can be obtained from destport in the router
+    assign lkdestport_encoded = {lkdestport_x[1: 0],lkdestport_y[1: 0]};
+endmodule
+
+/***********************************
+*            remove_sw_loc_one_hot
+*remove port number that is holding the packet
+************************************/
+module remove_sw_loc_one_hot #(
+    parameter P = 5,
+    parameter SW_LOC = 0
+)(
+    destport_in,
+    destport_out
+);
+    localparam P_1 = P-1;
+    
+    input [P-1 : 0] destport_in;
+    output  [P_1-1 : 0] destport_out;
+    
+    generate 
+    if(SW_LOC==0)begin :local_p
+        assign destport_out= destport_in[P-1 : 1];
+    end else if (SW_LOC==P_1)begin :last_p
+        assign destport_out= destport_in[P_1-1 : 0];
+    end else begin :midle_p
+        assign destport_out= {destport_in[P-1 : SW_LOC+1],destport_in[SW_LOC-1 :  0]};
+    end
+    endgenerate
+endmodule
+
+module destport_non_selfloop_fix #(
+    parameter SELF_LOOP_EN = 0,
+    parameter P = 5,
+    parameter SW_LOC = 0
+)(
+    destport_in,
+    destport_out
+);
+    localparam P_1 = (SELF_LOOP_EN)?  P : P-1;
+    
+    input [P-1 : 0] destport_in;
+    output [P_1-1 : 0] destport_out;
+    
+    generate 
+    if (SELF_LOOP_EN) begin
+        assign destport_out = destport_in;
+    end else begin
+        if(SW_LOC==0)begin :local_p
+            assign destport_out= destport_in[P-1 : 1];
+        end else if (SW_LOC==P_1)begin :last_p
+            assign destport_out= destport_in[P_1-1 : 0];
+        end else begin :midle_p
+            assign destport_out= {destport_in[P-1 : SW_LOC+1],destport_in[SW_LOC-1 :  0]};
+        end
+    end 
+    endgenerate
+endmodule
+
+
+
+/***********************************
+*     remove_receive_port_one_hot
+*                
+************************************/
+module remove_receive_port_one_hot #(
+    parameter P = 5    
+)(
+    receiver_port,
+    destport_in,
+    destport_out
+);
+    import pronoc_pkg::*;
+    
+    localparam 
+        P_1 = P-1,
+        Pw = log2(P),
+        P_1w = log2(P_1);
+    input [P-1 : 0] destport_in;
+    input [P-1 : 0] receiver_port;
+    output logic [P_1-1 : 0] destport_out;
+    logic [Pw-1 : 0] receiver_port_bin,destport_in_bin;
+    wire [P_1w-1 : 0]  destport_out_bin;
+    
+    always_comb begin
+        receiver_port_bin = '0;
+        destport_in_bin = '0;
+        destport_out ='0;
+        //bin to one_hot
+        destport_out[destport_out_bin] = 1'b1;
+        //one_hot_to_bin
+        for (int k = 0; k < P; k++) begin
+            if (receiver_port[k]) receiver_port_bin = Pw'(k);
+            if (destport_in[k]) destport_in_bin = Pw'(k);
+        end
+    end
+    
+    wire [Pw-1 : 0] temp;
+    assign temp = (receiver_port_bin > destport_in_bin ) ? destport_in_bin : destport_in_bin  -1'b1;
+    assign destport_out_bin=temp[P_1w-1 : 0];
+endmodule
+
+/**************************************
+*        add_sw_loc_one_hot
+****************************************/
+module add_sw_loc_one_hot #(
+    parameter P = 5,
+    parameter SW_LOC = 1
+)(
+    destport_in,
+    destport_out
+);
+    localparam P_1 = P-1;
+    input [P_1-1 : 0] destport_in;
+    output reg [P-1 : 0] destport_out;
+    
+    always_comb begin 
+        for(int i=0;i<P; i++)begin 
+            if (i>SW_LOC) destport_out[i] = destport_in[i-1];
+            else if (i==SW_LOC) destport_out[i] = 1'b0;
+            else destport_out[i] = destport_in[i];
+        end//for 
+    end
+endmodule  
+
+
+module add_sw_loc_one_hot_val #(
+    parameter P = 5,
+    parameter SW_LOC = 1
+    
+)(
+    sw_loc_val,
+    destport_in,
+    destport_out
+);
+    localparam P_1 = P-1;
+    input sw_loc_val;
+    input [P_1-1 : 0] destport_in;
+    output reg [P-1 : 0] destport_out;
+    
+    integer i;   
+    always @(*)begin 
+        for(i=0;i<P;i=i+1)begin :port_loop
+            if (i>SW_LOC)      destport_out[i] = destport_in[i-1];
+            else if (i==SW_LOC)     destport_out[i] = sw_loc_val;
+            else                    destport_out[i] = destport_in[i];
+        end//for 
+    end
+endmodule  
+
+
+/***************************************************
+*            conventional routing 
+***************************************************/
+module regular_topo_conventional_routing #(
+    parameter LOCATED_IN_NI = 0 //used only for odd-even routing
+    ) (   
+    current_router_addr_i,
+    dest_router_addr_i,
+    destport
+    );
+    
+    import pronoc_pkg::*;   
+    input regular_topo_router_addr_t current_router_addr_i;
+    input regular_topo_router_addr_t dest_router_addr_i;
+    output logic [DSTPw-1 : 0] destport;
+    
+    generate 
+    if (IS_MESH_3D) begin 
+        mesh_3d_route_xyz the_conventional_routing(
+            .current_router_addr_i(current_router_addr_i),
+            .dest_router_addr_i(dest_router_addr_i),
+            .destport(destport)
+        );
+    end else if (IS_MESH || IS_FMESH) begin :mesh
+    /* verilator lint_off WIDTH */ 
+        if(ROUTE_NAME == "DOR") begin : xy_routing_blk
+    /* verilator lint_on WIDTH */ 
+            xy_mesh_routing #(
+                .NX(NX),
+                .NY(NY)                   
+            ) xy_routing (
+                .current_x(current_router_addr_i.x),
+                .current_y(current_router_addr_i.y),
+                .dest_x(dest_router_addr_i.x),
+                .dest_y(dest_router_addr_i.y),
+                .dstport_encoded(destport)
+            );        
+        end //"DOR"
+        /* verilator lint_off WIDTH */ 
+        else if(ROUTE_NAME == "WEST_FIRST") begin : west_first_routing_blk
+        /* verilator lint_on WIDTH */ 
+            west_first_routing #(
+                .NX (NX),
+                .NY (NY)
+            ) west_first (
+                .current_x (current_router_addr_i.x),
+                .current_y (current_router_addr_i.y),
+                .dest_x (dest_router_addr_i.x),
+                .dest_y (dest_router_addr_i.y),
+                .destport (destport)
+            );
+        end // WEST_FIRST
+        /* verilator lint_off WIDTH */ 
+        else if(ROUTE_NAME == "NORTH_LAST") begin : north_last_routing_blk
+        /* verilator lint_on WIDTH */ 
+            north_last_routing #(
+                .NX (NX),
+                .NY (NY)
+            ) north_last (
+                .current_x (current_router_addr_i.x),
+                .current_y (current_router_addr_i.y),
+                .dest_x (dest_router_addr_i.x),
+                .dest_y (dest_router_addr_i.y),
+                .destport (destport)
+            );
+        end // NORTH_LAST
+        /* verilator lint_off WIDTH */ 
+        else if(ROUTE_NAME == "NEGETIVE_FIRST") begin : negetive_first_routing_blk
+        /* verilator lint_on WIDTH */ 
+            negetive_first_routing #(
+                .NX (NX),
+                .NY (NY)
+            )  negetive_first (
+                .current_x (current_router_addr_i.x),
+                .current_y (current_router_addr_i.y),
+                .dest_x (dest_router_addr_i.x),
+                .dest_y (dest_router_addr_i.y),
+                .destport (destport)
+            );
+        end // NEGETIVE_FIRST           
+        /* verilator lint_off WIDTH */ 
+        else if(ROUTE_NAME == "ODD_EVEN") begin : odd_even_routing_blk
+        /* verilator lint_on WIDTH */ 
+            odd_even_routing #(
+                .NX (NX),
+                .NY (NY),
+                .LOCATED_IN_NI (LOCATED_IN_NI)
+            ) odd_even (
+                .current_x (current_router_addr_i.x),
+                .current_y (current_router_addr_i.y),
+                .dest_x (dest_router_addr_i.x),
+                .dest_y (dest_router_addr_i.y),
+                .destport (destport)
+            );
+        end //ODD_EVEN
+        /* verilator lint_off WIDTH */ 
+        else if(ROUTE_NAME == "FULL_ADPT") begin : duato_routing_blk
+        /* verilator lint_on WIDTH */ 
+            duato_mesh_routing #(
+                .NX (NX),
+                .NY (NY)
+            ) duato_full_adaptive (
+                .current_x (current_router_addr_i.x),
+                .current_y (current_router_addr_i.y),
+                .dest_x (dest_router_addr_i.x),
+                .dest_y (dest_router_addr_i.y),
+                .destport (destport)
+            );
+        end //FULL_ADPT
+    `ifdef SIMULATION
+        else begin : not_supported initial $display ("Error: %s is an unsupported routing algorithm for %s topology \n",ROUTE_NAME,TOPOLOGY); end
+    `endif
+    /* verilator lint_off WIDTH */ 
+    end else if (TOPOLOGY == "TORUS" ) begin :torus
+        if(ROUTE_NAME == "TRANC_DOR") begin : tranc_routing_blk
+    /* verilator lint_on WIDTH */ 
+            tranc_xy_routing #(
+                .NX (NX),
+                .NY (NY)
+            ) tranc_xy (
+                .current_x (current_router_addr_i.x),
+                .current_y (current_router_addr_i.y),
+                .dest_x (dest_router_addr_i.x),
+                .dest_y (dest_router_addr_i.y),
+                .destport_encoded (destport)
+            );
+        end //"TRANC_DOR"
+        /* verilator lint_off WIDTH */ 
+        else if(ROUTE_NAME == "TRANC_WEST_FIRST") begin : tranc_west_first_routing_blk
+        /* verilator lint_on WIDTH */ 
+            tranc_west_first_routing #(
+                .NX (NX),
+                .NY(NY)
+            ) tranc_west_first (
+                .current_x (current_router_addr_i.x),
+                .current_y (current_router_addr_i.y),
+                .dest_x (dest_router_addr_i.x),
+                .dest_y (dest_router_addr_i.y),
+                .destport (destport)
+            );
+        end // TRANC_WEST_FIRST
+        /* verilator lint_off WIDTH */ 
+        else if(ROUTE_NAME == "TRANC_NORTH_LAST") begin : tranc_north_last_routing_blk
+        /* verilator lint_on WIDTH */ 
+            tranc_north_last_routing #(
+                .NX (NX),
+                .NY (NY)
+            ) tranc_north_last (
+                .current_x (current_router_addr_i.x),
+                .current_y (current_router_addr_i.y),
+                .dest_x (dest_router_addr_i.x),
+                .dest_y (dest_router_addr_i.y),
+                .destport (destport)
+            );
+        end // TRANC_NORTH_LAST
+        /* verilator lint_off WIDTH */ 
+        else if(ROUTE_NAME == "TRANC_NEGETIVE_FIRST") begin : tranc_negetive_first_routing_blk
+        /* verilator lint_on WIDTH */ 
+            tranc_negetive_first_routing #(
+                .NX (NX),
+                .NY (NY)
+            ) tranc_negetive_first(
+                .current_x (current_router_addr_i.x),
+                .current_y (current_router_addr_i.y),
+                .dest_x (dest_router_addr_i.x),
+                .dest_y (dest_router_addr_i.y),
+                .destport (destport)
+            );
+        end // TRANC_NEGETIVE_FIRST
+        /* verilator lint_off WIDTH */ 
+        else if(ROUTE_NAME == "TRANC_FULL_ADPT") begin : tranc_duato_routing_blk
+        /* verilator lint_on WIDTH */ 
+            tranc_duato_routing #(
+                .NX (NX),
+                .NY (NY)
+            ) duato_full_adaptive (
+                .current_x (current_router_addr_i.x),
+                .current_y (current_router_addr_i.y),
+                .dest_x (dest_router_addr_i.x),
+                .dest_y (dest_router_addr_i.y),
+                .destport (destport)
+            );
+        end //TRANC_FULL_ADPT
+        `ifdef SIMULATION
+        else begin : not_supported2 initial $display("Error: %s is an unsupported routing algorithm for %s topology",ROUTE_NAME,TOPOLOGY); end
+        `endif
+    end //TORUS
+    /* verilator lint_off WIDTH */ 
+    else if (TOPOLOGY == "RING" ) begin :ring
+        if(ROUTE_NAME == "TRANC_DOR") begin : tranc_ring_blk
+    /* verilator lint_on WIDTH */ 
+            tranc_ring_routing #(
+                .NX(NX)       
+            ) tranc_ring (
+                .current_x(current_router_addr_i.x),
+                .dest_x(dest_router_addr_i.x),
+                .destport(destport)    
+            );
+        end // "TRANC"
+        `ifdef SIMULATION
+        else begin : not_supported2 initial $display("Error: %s is an unsupported routing algorithm for %s topology",ROUTE_NAME,TOPOLOGY); end  
+        `endif    
+        end //"RING"       
+    /* verilator lint_off WIDTH */ 
+    else if (TOPOLOGY == "LINE" ) begin :ring
+        if(ROUTE_NAME == "DOR") begin : tranc_ring_blk
+    /* verilator lint_on WIDTH */ 
+            xy_line_routing #(
+                .NX(NX)                    
+            ) xy_routing (
+                .current_x(current_router_addr_i.x),
+                .dest_x(dest_router_addr_i.x),
+                .destport(destport)
+            );       
+        end // "DOR"
+        `ifdef SIMULATION
+        else begin : not_supported2 initial $display("Error: %s is an unsupported routing algorithm for %s topology",ROUTE_NAME,TOPOLOGY); end
+        `endif           
+        end //"LINE" 
+    `ifdef SIMULATION
+    else begin : wrong_topology initial $display("Error: %s is an unsupported topology",TOPOLOGY); end
+    `endif
+    endgenerate
+endmodule
+
+
+/*************************
+*        TRANC_ring
+**************************/
+module tranc_ring_routing #(
+    parameter NX = 4
+)(
+    current_x,
+    dest_x,
+    destport
+    
+);
+    function integer log2;
+    input integer number; begin   
+        log2=(number <=1) ? 1: 0;    
+        while(2**log2<number) begin    
+            log2=log2+1;    
+        end        
+    end   
+    endfunction // log2 
+    
+    localparam
+        P = 3,
+        Xw = log2(NX),
+        DSTw = P-1;
+    
+    input [Xw-1 : 0] current_x;
+    input [Xw-1 : 0] dest_x;
+    output  [DSTw -1 : 0] destport;
+    
+    localparam      
+        LOCAL = 3'b001,  
+        PLUS = 3'b010,   
+        MINUS = 3'b100;    
+    
+    reg [P-1 : 0] destport_one_hot;
+    reg tranc_x_plus;
+    reg tranc_x_min;
+    wire same_x;
+    localparam SIGNED_X_WIDTH = (Xw<3) ? 4 : Xw+1;
+    
+    wire signed [SIGNED_X_WIDTH-1 : 0] xc;//current 
+    wire signed [SIGNED_X_WIDTH-1 : 0] xd;//destination
+    wire signed [SIGNED_X_WIDTH-1 : 0] xdiff;
+    
+    assign  xd ={{(SIGNED_X_WIDTH-Xw){1'b0}}, dest_x};
+    assign  xc ={{(SIGNED_X_WIDTH-Xw){1'b0}}, current_x [Xw-1 : 0]};
+    assign  xdiff = xd-xc;
+    
+    always@ (*)begin 
+        tranc_x_plus =1'b0;
+        tranc_x_min =1'b0;
+        if(xdiff!=0)begin 
+            if ((xdiff ==1) || 
+                (xdiff == (-NX+1)) ||
+                ((xc == (NX-4)) && (xd == (NX-2))) ||
+                ((xc >= (NX-2)) && (xd <= (NX-4))) ||
+                ((xdiff> 0) && (xd<= (NX-3)))) 
+                    tranc_x_plus = 1'b1;
+            else    tranc_x_min = 1'b1;
+        end
+    end//always
+    assign same_x = (xdiff == 0);
+    
+    always@(*)begin
+        destport_one_hot= LOCAL;
+        if (same_x ) destport_one_hot= LOCAL;
+        else begin 
+            if (tranc_x_plus)  destport_one_hot= PLUS;
+            else if (tranc_x_min)   destport_one_hot= MINUS;
+        end
+    end
+    line_ring_encode_dstport encode(
+        .dstport_one_hot(destport_one_hot),
+        .dstport_encoded(destport)
+    );
+    
+endmodule
+
+
+
+/********************************************
+*                        xy_line
+*********************************************/
+module xy_line_routing #(
+    parameter NX = 8      
+)(
+    current_x,
+    dest_x,
+    destport
+);
+    function integer log2;
+    input integer number; begin   
+        log2=(number <=1) ? 1: 0;    
+        while(2**log2<number) begin    
+            log2=log2+1;    
+        end        
+    end   
+    endfunction // log2 
+    
+    localparam  
+        OUT_BIN = 0,
+        P = 3,
+        Xw = log2(NX);
+    
+    input [Xw-1 : 0] current_x;
+    input [Xw-1 : 0] dest_x;
+    output  [1 : 0] destport;
+    
+    localparam      
+        LOCAL = (OUT_BIN)?  3'd0 : 3'b001,  
+        PLUS = (OUT_BIN)?  3'd1 : 3'b010,   
+        MINUS = (OUT_BIN)?  3'd2 : 3'b100;         
+        
+    reg [P-1 : 0] destport_one_hot;
+    
+    always@(*)begin
+        destport_one_hot = LOCAL [2 : 0];
+        if (dest_x    > current_x)        destport_one_hot = PLUS  [2 : 0];
+        else if (dest_x    < current_x)        destport_one_hot = MINUS [2 : 0];            
+    end
+    
+    line_ring_encode_dstport encode(
+        .dstport_one_hot(destport_one_hot),
+        .dstport_encoded(destport)
+    );
+    
+endmodule
+
+
+module line_ring_encode_dstport (
+    dstport_one_hot,
+    dstport_encoded
+);
+    input [2 : 0] dstport_one_hot;
+    output [1 : 0] dstport_encoded; 
+    
+    
+    localparam  
+        FORWARD = 2'd1,
+        BACKWARD = 2'd2;
+    /************************   
+    *   destination-port_in
+    *       2'b11 : FORWARD or BACKWARD // can be sent to any of them
+    *       2'b10 : BACKWARD
+    *       2'b01 : FORWARD
+    *       2'b00 : LOCAL
+    *******************/
+    // code the destination port
+    assign dstport_encoded = {dstport_one_hot[BACKWARD], dstport_one_hot[FORWARD]};
+endmodule
+
+
+module line_ring_decode_dstport (
+    dstport_one_hot,
+    dstport_encoded
+);
+    output  reg [2 : 0] dstport_one_hot;
+    input [1 : 0] dstport_encoded;
+    
+    always @(*)begin 
+        dstport_one_hot = 3'b000;
+        case(dstport_encoded)
+            2'b10 : dstport_one_hot=3'b100;
+            2'b01 : dstport_one_hot=3'b010;
+            2'b00 : dstport_one_hot=3'b001;
+            2'b11 : dstport_one_hot=3'b110; //invalid condition in determinstic routing
+        endcase
+    end //always
+endmodule
+
+module line_ring_destport_decode_decimal (
+    destport_decimal,
+    destport_encoded
+);
+    import pronoc_pkg::*;
+    output  reg [1 : 0] destport_decimal;
+    input [1 : 0] destport_encoded;
+    localparam Pw=2;
+    
+    always @(*)begin 
+        destport_decimal = Pw'(LOCAL);
+        case(destport_encoded)
+            2'b10 : destport_decimal=Pw'(BACKWARD);
+            2'b01 : destport_decimal=Pw'(FORWARD);
+            2'b00 : destport_decimal=Pw'(LOCAL);
+            2'b11 : destport_decimal=Pw'(LOCAL); //invalid condition in determinstic routing
+        endcase
+    end //always
+endmodule
+
+module regular_topo_decode_dstport (
+    dstport_encoded,
+    dstport_one_hot
+);
+    input [3 : 0] dstport_encoded; 
+    output  reg [4 : 0] dstport_one_hot;
+    wire x,y,a,b;
+    assign {x,y,a,b} = dstport_encoded;
+    always @(*)begin 
+        dstport_one_hot = 5'd0;
+        case({a,b})
+            2'b10 : dstport_one_hot = {1'b0,~x,1'b0,x,1'b0};
+            2'b01 : dstport_one_hot = {~y,1'b0,y,1'b0,1'b0};
+            2'b11 : dstport_one_hot = {1'b0,~x,1'b0,x,1'b0}; //illegal
+            2'b00 : dstport_one_hot = 5'b00001;
+        endcase
+   end //always
+endmodule 
+
+module regular_topo_destport_decode_decimal (
+    destport_encoded,
+    destport_decimal
+);
+    import pronoc_pkg::*;
+    input [3 : 0] destport_encoded;
+    output reg [2 : 0] destport_decimal;
+    localparam Pw=3;
+    wire x,y,a,b;
+    assign {x,y,a,b} = destport_encoded;
+    
+    always_comb begin
+    destport_decimal = 0;
+    case ({a, b})   
+        2'b10: destport_decimal = (x) ? Pw'(EAST) : Pw'(WEST); // 1=East, 2=West
+        2'b01: destport_decimal = (y) ? Pw'(NORTH) : Pw'(SOUTH); // 3=North, 4=South
+        2'b11: begin
+            // Both directions is illegal for decimal output
+            destport_decimal = (x) ? Pw'(EAST) : Pw'(WEST);
+        end
+        2'b00: begin
+            // Local node
+            destport_decimal = Pw'(LOCAL);
+        end
+    endcase
+    end
+endmodule
+
+
+module regular_topo_full_adapt_ovc_avail #(
+    parameter P = 4
+) (
+    reset,clk,
+    empty_all_next,
+    full_all_next,
+    nearly_full_all_next,
+    ovc_status,
+    ovc_avalable_all
+);
+    import pronoc_pkg::*;
+    localparam PV = P * V;
+    localparam [V-1 : 0] ADAPTIVE_VC_MASK = ~ ESCAP_VC_MASK;
+    input [PV-1 : 0] empty_all_next, full_all_next,  nearly_full_all_next,ovc_status;
+    output [PV-1 : 0]ovc_avalable_all;
+    input reset,clk;
+    reg [PV-1 : 0] full_adaptive_ovc_mask,full_adaptive_ovc_mask_next; 
+    always_comb begin
+        for( int k=0; k<PV; k=k+1) begin
+        //in full adaptive routing, adaptive VCs located in y axies can not be reallocated non-atomicly
+            if( AVC_ATOMIC_EN == 0) begin :avc_atomic
+                if((((k/V) == NORTH ) || ((k/V) == SOUTH )) && (  ADAPTIVE_VC_MASK[k%V]))  
+                    full_adaptive_ovc_mask_next[k] = empty_all_next[k];
+                else 
+                    full_adaptive_ovc_mask_next[k] = (OVC_ALLOC_MODE)? ~full_all_next[k] : ~nearly_full_all_next[k];
+            end else begin :avc_nonatomic
+                if(  ADAPTIVE_VC_MASK[k%V])  
+                    full_adaptive_ovc_mask_next[k] = empty_all_next[k];
+                else    
+                    full_adaptive_ovc_mask_next[k] = (OVC_ALLOC_MODE)? ~full_all_next[k] :~nearly_full_all_next[k];
+            end
+         end // for  
+    end//always
+    always_ff @ (`pronoc_clk_reset_edge) begin
+        if (`pronoc_reset) begin
+            full_adaptive_ovc_mask <= '0;
+        end else begin
+            full_adaptive_ovc_mask <= full_adaptive_ovc_mask_next;
+        end
+    end    
+    assign ovc_avalable_all   = ~ovc_status & full_adaptive_ovc_mask;
+endmodule
diff --git a/mpsoc/rtl/src_noc/mesh_torus_routting.v b/mpsoc/rtl/src_noc/mesh_torus_routting.v
deleted file mode 100644
index f97c029..0000000
--- a/mpsoc/rtl/src_noc/mesh_torus_routting.v
+++ /dev/null
@@ -1,1303 +0,0 @@
-`timescale 1ns / 1ps
-
-/************************************
-
-     mesh_torus_look_ahead_routing
-
-*************************************/
-
-module mesh_torus_look_ahead_routing #(
-    parameter NX        =4,
-    parameter NY        =4,
-    parameter SW_LOC    =0,
-    parameter TOPOLOGY  ="MESH",//"MESH","TORUS"
-    parameter ROUTE_NAME="XY",// 
-    parameter ROUTE_TYPE="DETERMINISTIC"// "DETERMINISTIC", "FULL_ADAPTIVE", "PAR_ADAPTIVE"
-)
-(
-    current_x,  //current router x address
-    current_y,  //current router y address
-    dest_x,  // destination router x address          
-    dest_y,  // destination router y address                  
-    destport_encoded,   // current router destination port number       
-    lkdestport_encoded, // look ahead destination port number
-    reset,
-    clk
-);
-    
-     /* verilator lint_off WIDTH */ 
-    localparam  P = (TOPOLOGY == "MESH" || TOPOLOGY == "FMESH" || TOPOLOGY == "TORUS")?  5:3;
-     /* verilator lint_on WIDTH */ 
-    
-    function integer log2;
-      input integer number; begin   
-         log2=(number <=1) ? 1: 0;    
-         while(2**log2<number) begin    
-            log2=log2+1;    
-         end        
-      end   
-    endfunction // log2 
-   
-    localparam  P_1     =   P-1,
-                Xw      =   log2(NX),   // number of node in x axis
-                Yw      =  (TOPOLOGY=="RING" || TOPOLOGY == "LINE") ? 1 : log2(NY);    // number of node in y axis
-   
-    input   [Xw-1   :   0]  current_x;
-    input   [Yw-1   :   0]  current_y;                  
-    input   [Xw-1   :   0]  dest_x;
-    input   [Yw-1   :   0]  dest_y;
-    input   [P_1-1  :   0]  destport_encoded;
-    output  [P_1-1  :   0]  lkdestport_encoded;
-    input                   reset,clk;
-    
-    wire     [Xw-1   :   0]  destx_delayed;
-    wire     [Yw-1   :   0]  desty_delayed;
-    wire     [P_1-1  :   0]  destport_delayed;
-    
-    
-    // routing algorithm
-    generate 
-    /* verilator lint_off WIDTH */ 
-    if(ROUTE_TYPE=="DETERMINISTIC") begin :dtrmst
-    /* verilator lint_on WIDTH */ 
-         mesh_torus_deterministic_look_ahead_routing #(
-             .P(P),
-             .NX(NX),
-             .NY(NY),
-             .SW_LOC(SW_LOC),
-             .TOPOLOGY(TOPOLOGY),
-             .ROUTE_NAME(ROUTE_NAME)
-         )
-         deterministic_look_ahead(
-             .current_x(current_x),
-             .current_y(current_y),
-             .dest_x(destx_delayed),
-             .dest_y(desty_delayed),
-             .destport(destport_delayed),
-             .lkdestport(lkdestport_encoded)
-         );
-    
-    end else begin :adapt
-        mesh_torus_adaptive_look_ahead_routing #(
-            .P(P),
-            .NX(NX),
-            .NY(NY),
-            .TOPOLOGY(TOPOLOGY),
-            .ROUTE_NAME(ROUTE_NAME),
-            .ROUTE_TYPE(ROUTE_TYPE)
-         )
-         adaptive_look_ahead
-         (
-            .current_x(current_x),
-            .current_y(current_y),
-            .dest_x(destx_delayed),
-            .dest_y(desty_delayed),
-            .destport_encoded(destport_delayed),
-            .lkdestport_encoded(lkdestport_encoded)
-         );
-    
-    
-    end
-    endgenerate
-    
-     pronoc_register #(.W(Xw) ) reg1 (.in(dest_x ), .out(destx_delayed), .reset(reset), .clk(clk));
-     pronoc_register #(.W(Yw) ) reg2 (.in(dest_y ), .out(desty_delayed), .reset(reset), .clk(clk));
-     pronoc_register #(.W(P_1)) reg3 (.in(destport_encoded ), .out(destport_delayed), .reset(reset), .clk(clk));
-    
-endmodule
-
-
-
-/************************************************
-
-
-        deterministic_look_ahead_routing
-
-
-**********************************************/
-
-
-module  mesh_torus_deterministic_look_ahead_routing #(
-    parameter P         =5,
-    parameter NX        =4,
-    parameter NY        =4,
-    parameter SW_LOC    =0,
-    parameter TOPOLOGY  ="MESH",//"MESH","TORUS"
-    parameter ROUTE_NAME="XY"// "XY", "TRANC_XY"
-  )
-  (
-        current_x,  //current router x address
-        current_y,  //current router y address
-        dest_x,  // destination router x address          
-        dest_y,  // destination router y address                  
-        destport,   // current router destination port number       
-        lkdestport // look ahead destination port number
-      
- );
-    
-   
-    function integer log2;
-      input integer number; begin   
-         log2=(number <=1) ? 1: 0;    
-         while(2**log2<number) begin    
-            log2=log2+1;    
-         end        
-      end   
-    endfunction // log2 
- 
- 
-    localparam  P_1     =   P-1,
-                Xw      =   log2(NX),   // number of node in x axis
-                Yw      = (TOPOLOGY=="RING" || TOPOLOGY == "LINE") ? 1 :  log2(NY);    // number of node in y axis
-                    
- 
-    input   [Xw-1   :   0]  current_x;
-    input   [Yw-1   :   0]  current_y;                  
-    input   [Xw-1   :   0]  dest_x;
-    input   [Yw-1   :   0]  dest_y;
-    input   [P_1-1  :   0]  destport;
-    output  [P_1-1  :   0]  lkdestport;
-   
- 
-   
-    wire    [Xw-1   :   0]  next_x;
-    wire    [Yw-1   :   0]  next_y; 
- 
-  wire     [P-1    :   0]  destport_one_hot;
-  
- generate 
-  /* verilator lint_off WIDTH */ 
- if (TOPOLOGY == "MESH" || TOPOLOGY == "TORUS" || TOPOLOGY == "FMESH" ) begin: twoD
-   /* verilator lint_on WIDTH */   
-    mesh_tori_decode_dstport decoder(
-        .dstport_encoded(destport),
-        .dstport_one_hot(destport_one_hot)
-    );
-      
-    
-   end else begin :oneD
-    line_ring_decode_dstport decoder(
-        .dstport_encoded(destport),
-        .dstport_one_hot(destport_one_hot)
-    );
-    
-   
-   end
-   endgenerate 
-    
-    
-    mesh_torus_next_router_addr_predictor #(
-        .P(P),
-        .TOPOLOGY(TOPOLOGY),
-        .NX(NX),
-        .NY(NY)
-    )
-    addr_predictor
-    (
-        .destport(destport_one_hot),
-        .current_x(current_x),
-        .current_y(current_y),
-        .next_x(next_x),
-        .next_y(next_y)
-    );
- 
-   
-   wire [P_1-1  :   0] lkdestport_encoded;
- 
-    mesh_torus_conventional_routing #(
-        .TOPOLOGY(TOPOLOGY),
-        .ROUTE_NAME(ROUTE_NAME),
-        .ROUTE_TYPE("DETERMINISTIC"),
-        .NX(NX),
-        .NY(NY),
-        .LOCATED_IN_NI(0)
-    )
-    conv_routing
-    (
-        .current_x(next_x),
-        .current_y(next_y),
-        .dest_x(dest_x),
-        .dest_y(dest_y),
-        .destport(lkdestport_encoded)
-        
-    );
- 
-    //take the value of a&b only.  x&y can be obtained from destport in the router
-    assign lkdestport = lkdestport_encoded;//[1:0];
-  
-    
- 
- endmodule
-
-
-
-/************************************************
-
-
-        adaptive_look_ahead_routing
-
-
-**********************************************/
-
-
-module  mesh_torus_adaptive_look_ahead_routing #(
-    parameter P         =5,
-    parameter NX        =4,
-    parameter NY        =4,
-    parameter TOPOLOGY  ="MESH",//"MESH","TORUS"
-    parameter ROUTE_NAME="WEST_FIRST",
-    parameter ROUTE_TYPE="DETERMINISTIC"
-  )
-  (
-        current_x,  //current router x address
-        current_y,  //current router y address
-        dest_x,  // destination router x address          
-        dest_y,  // destination router y address                  
-        destport_encoded,   // current router destination port      
-        lkdestport_encoded // look ahead destination port 
-     
- );
-    
-    
-    function integer log2;
-      input integer number; begin   
-         log2=(number <=1) ? 1: 0;    
-         while(2**log2<number) begin    
-            log2=log2+1;    
-         end        
-      end   
-    endfunction // log2 
- 
- 
-    localparam  P_1     =   P-1,
-                Xw      =   log2(NX),   // number of node in x axis
-                Yw      =   log2(NY);    // number of node in y axis
-                    
- 
-    input   [Xw-1   :   0]  current_x;
-    input   [Yw-1   :   0]  current_y;                  
-    input   [Xw-1   :   0]  dest_x;
-    input   [Yw-1   :   0]  dest_y;
-    input   [P_1-1  :   0]  destport_encoded;
-    output  [P_1-1  :   0]  lkdestport_encoded;
-   
- /*
- destination-port coded
-            x:  1 EAST, 0 WEST  
-            y:  1 NORTH, 0 SOUTH
-            ab: 00 : LOCAL, 10: xdir, 01: ydir, 11 x&y dir 
-        
-*/
-                
-     
-
-    wire x,y,a,b;
-    wire    [Xw-1   :   0]  next_x;
-    wire    [Yw-1   :   0]  next_y; 
-    wire    [P_1-1  :   0]  lkdestport_x,lkdestport_y;
-    reg     [P-1    :   0]  destport_x, destport_y;
-    
-    assign {x,y,a,b} = destport_encoded;
-  
-   always @(*)begin 
-        destport_x = 5'd0;
-        destport_y = 5'd0;
-        case({a,b})
-            2'b10 : destport_x = {1'b0,~x,1'b0,x,1'b0};
-            2'b01 : destport_y = {~y,1'b0,y,1'b0,1'b0};
-            2'b11 : begin destport_x = {1'b0,~x,1'b0,x,1'b0}; destport_y = {~y,1'b0,y,1'b0,1'b0}; end
-            2'b00 : begin destport_x =  5'b00001;destport_y =  5'b00001; end 
-         endcase
-   end //always
-    
-    mesh_torus_next_router_addr_predictor #(
-        .P(P),
-        .TOPOLOGY(TOPOLOGY),
-        .NX(NX),
-        .NY(NY)
-    )
-    addr_predictor_x
-    (
-        .destport(destport_x),
-        .current_x(current_x),
-        .current_y(current_y),
-        .next_x(next_x),
-        .next_y()
-    );
-    
-    
-     mesh_torus_next_router_addr_predictor #(
-        .P(P),
-        .TOPOLOGY(TOPOLOGY),
-        .NX(NX),
-        .NY(NY)
-    )
-    addr_predictor_y
-    (
-        .destport(destport_y),
-        .current_x(current_x),
-        .current_y(current_y),
-        .next_x(),
-        .next_y(next_y)
-    );
-    
- 
- 
-    mesh_torus_conventional_routing #(
-        .TOPOLOGY(TOPOLOGY),
-        .ROUTE_NAME(ROUTE_NAME),
-        .ROUTE_TYPE(ROUTE_TYPE),
-        .NX(NX),
-        .NY(NY),
-        .LOCATED_IN_NI(0)
-    )
-    conv_route_x
-    (
-        .current_x(next_x),
-        .current_y(current_y),
-        .dest_x(dest_x),
-        .dest_y(dest_y),
-        .destport(lkdestport_x)
-    );
- 
-    mesh_torus_conventional_routing #(
-        .TOPOLOGY(TOPOLOGY),
-        .ROUTE_NAME(ROUTE_NAME),
-        .ROUTE_TYPE(ROUTE_TYPE),
-        .NX(NX),
-        .NY(NY),
-        .LOCATED_IN_NI(0)
-    )
-    conv_route_y
-    (
-        .current_x(current_x),
-        .current_y(next_y),
-        .dest_x(dest_x),
-        .dest_y(dest_y),
-        .destport(lkdestport_y)
-    );
- //take the value of a&b only.  x&y can be obtained from destport in the router
- assign lkdestport_encoded = {lkdestport_x[1:0],lkdestport_y[1:0]};
-    
- 
- endmodule
-
-
-
-
-/********************************************************
-
-                    next_router_addr_predictor
-                    
-Determine the next router address based on the packet destination port   
-
-********************************************************/
-
-module mesh_torus_next_router_addr_predictor #(
-    parameter P     =   5,
-    parameter TOPOLOGY  ="MESH",
-    parameter NX    =   4,//toutal number of router in x direction 
-    parameter NY    =   4//toutal number of router in y direction 
-    )
-    (
-    destport,
-    current_x,
-    current_y,
-    next_x,
-    next_y  
-    
-    );
- 
-    function integer log2;
-      input integer number; begin   
-         log2=(number <=1) ? 1: 0;    
-         while(2**log2<number) begin    
-            log2=log2+1;    
-         end        
-      end   
-    endfunction // log2 
-    
-    localparam  Xw          =   log2(NX),
-                Yw          =  (TOPOLOGY=="RING" || TOPOLOGY == "LINE")? 1 : log2(NY);
-    // mesh torus            
-    localparam  EAST   =       3'd1, 
-                NORTH  =       3'd2,  
-                WEST   =       3'd3,  
-                SOUTH  =       3'd4;
-    //ring line            
-    localparam  FORWARD =  2'd1,
-                BACKWARD=  2'd2;
-    
-    localparam [Xw-1  :   0] LAST_X_ADDR  =(NX[Xw-1 :   0]-1'b1);
-    localparam [Yw-1  :   0] LAST_Y_ADDR  =(NY[Yw-1 :   0]-1'b1);                
-        
-    input       [P-1   :    0]  destport;
-    input       [Xw-1  :    0]  current_x;
-    input       [Yw-1  :    0]  current_y;
-    output reg  [Xw-1  :    0]  next_x;
-    output reg  [Yw-1  :    0]  next_y;  
-    
-    generate 
-    /* verilator lint_off WIDTH */                                             
-    if(TOPOLOGY=="MESH" || TOPOLOGY == "TORUS" || TOPOLOGY == "FMESH" ) begin : mesh
-    /* verilator lint_on WIDTH */ 
-        always @(*) begin
-             //default values 
-            next_x= current_x;
-            next_y= current_y;
-            if(destport[EAST]) begin   
-                next_x= (current_x==LAST_X_ADDR ) ? {Xw{1'b0}} : current_x+1'b1;
-                next_y=  current_y;    
-            end       
-            else if(destport[NORTH])  begin   
-                next_x= current_x;
-                next_y= (current_y==0)? LAST_Y_ADDR  : current_y-1'b1;
-            end
-            else  if(destport[WEST])       begin 
-                next_x= (current_x==0) ? LAST_X_ADDR  : current_x-1'b1;
-                next_y=  current_y;
-             end
-            else  if(destport[SOUTH])  begin
-                next_x= current_x;
-                next_y= (current_y== LAST_Y_ADDR ) ? {Yw{1'b0}}: current_y+1'b1;
-            end
-        end//always
-    /* verilator lint_off WIDTH */     
-    end else  if(TOPOLOGY=="RING" || TOPOLOGY == "LINE") begin : ring
-    /* verilator lint_on WIDTH */ 
-       
-        always @(*) begin
-             //default values 
-            next_x= current_x;
-            next_y= 1'b0;
-            if(destport[FORWARD]) begin   
-                next_x= (current_x==LAST_X_ADDR ) ? {Xw{1'b0}} : current_x+1'b1;
-                
-            end       
-            else if(destport[BACKWARD])  begin   
-                next_x= (current_x=={Xw{1'b0}} ) ? LAST_X_ADDR  : current_x-1'b1;
-                 
-            end
-           
-        end//always
-    
-        
-    end
-    //synthesis translate_off
-    //synopsys  translate_off
-    else begin : wrong_topology initial $display("Error: next router inport is not predicted for %s   topology",TOPOLOGY); end
-    //synopsys  translate_on
-    //synthesis translate_on
-        
-        
-        
-     endgenerate 
-endmodule       
-
-/*******************************************************
-
-            next_router_inport_predictor
-            
-
-********************************************************/
-
-module mesh_torus_next_router_inport_predictor #(
-    parameter TOPOLOGY  ="MESH",
-    parameter P =5
-)(
-    destport,
-    receive_port
-   
-);
-
-    
-
-    input   [P-1    :   0] destport;
-    output  [P-1    :   0] receive_port; 
-           
-    localparam  LOCAL   =       3'd0, 
-                EAST    =       3'd1, 
-                NORTH   =       3'd2,  
-                WEST    =       3'd3,  
-                SOUTH   =       3'd4; 
-    generate
-    /* verilator lint_off WIDTH */ 
-    if(TOPOLOGY=="MESH" || TOPOLOGY == "TORUS" || TOPOLOGY == "FMESH") begin : mesh
-    /* verilator lint_on WIDTH */ 
-      
-        assign  receive_port[LOCAL]   = destport[LOCAL];
-        assign  receive_port[WEST]    = destport[EAST];
-        assign  receive_port[EAST]    = destport[WEST];
-        assign  receive_port[NORTH]   = destport[SOUTH];
-        assign  receive_port[SOUTH]   = destport[NORTH];
-    /* verilator lint_off WIDTH */ 
-    end else  if(TOPOLOGY=="RING" || TOPOLOGY == "LINE") begin : ring
-    /* verilator lint_on WIDTH */ 
-        assign  receive_port[0] = destport[0];
-        assign  receive_port[1] = destport[2];
-        assign  receive_port[2] = destport[1];
-    end
-    //synthesis translate_off
-    //synopsys  translate_off
-            else begin : wrong_topology initial $display("Error: next router inport is not predicted for %s   topology",TOPOLOGY); end
-    //synopsys  translate_on
-    //synthesis translate_on
-
-
-     
-
-    endgenerate
-                                         
-endmodule 
-
-/***********************************
-
-            remove_sw_loc_one_hot
-remove port number that is holdind the packet               
-
-************************************/
-
-module remove_sw_loc_one_hot #(
-    parameter P              =   5,
-    parameter SW_LOC     = 0
-    
-)
-(
-    destport_in,
-    destport_out
-);
-
-    localparam P_1 = P-1;
-   
-    input   [P-1         :   0] destport_in;
-    output  [P_1-1       :   0] destport_out;
-    
-    
-    generate 
-
-    if(SW_LOC==0)begin :local_p
-        assign destport_out= destport_in[P-1    :   1];
-
-    end else if (SW_LOC==P_1)begin :last_p
-        assign destport_out= destport_in[P_1-1  :   0];
-
-    end else begin :midle_p
-        assign destport_out= {destport_in[P-1   :   SW_LOC+1],destport_in[SW_LOC-1  :   0]};
-
-    end
-    endgenerate
-
-endmodule
-
-
-/***********************************
-
-     remove_receive_port_one_hot
-                
-
-************************************/
-
-
-module remove_receive_port_one_hot #(
-    parameter P              =   5    
-)
-(
-    receiver_port,
-    destport_in,
-    destport_out
-);
-    
-
-
-    function integer log2;
-      input integer number; begin   
-         log2=(number <=1) ? 1: 0;    
-         while(2**log2<number) begin    
-            log2=log2+1;    
-         end        
-      end   
-    endfunction // log2 
-    
-    localparam P_1  =   P-1,
-               Pw   =   log2(P),
-               P_1w =   log2(P_1);
-   
-    input  [P-1        :   0]  destport_in;
-    input  [P-1        :   0]  receiver_port;
-    output [P_1-1      :   0]  destport_out;
-       
-    wire        [Pw-1       :   0]  receiver_port_bin,destport_in_bin;
-    wire        [P_1w-1     :   0]  destport_out_bin;
-    
-       
-    one_hot_to_bin #(
-        .ONE_HOT_WIDTH(P),
-        .BIN_WIDTH(Pw)
-    )
-    convert1(
-        .one_hot_code(receiver_port),
-        .bin_code(receiver_port_bin)
-    );
-    
-     one_hot_to_bin #(
-        .ONE_HOT_WIDTH(P),
-        .BIN_WIDTH(Pw)
-    )
-    convert2(
-        .one_hot_code(destport_in),
-        .bin_code(destport_in_bin)
-    );
-    
-    
-    wire [Pw-1      :   0] temp;
-    assign temp = (receiver_port_bin > destport_in_bin ) ? destport_in_bin   : destport_in_bin  -1'b1;
-    assign destport_out_bin=temp[P_1w-1     :0];
-    
-    bin_to_one_hot #(
-        .BIN_WIDTH(P_1w),
-        .ONE_HOT_WIDTH(P_1)
-    )
-    convert3(
-        .bin_code(destport_out_bin),
-        .one_hot_code(destport_out)
-    );
-    
-    
-    
-endmodule
-
-/**************************************
-
-        add_sw_loc_one_hot
-
-
-****************************************/
-
-module add_sw_loc_one_hot #(
-    parameter P          =   5,
-    parameter SW_LOC     = 1
-    
-)
-(
-    destport_in,
-    destport_out
-);
-
-    localparam P_1 = P-1;
-   
-    input       [P_1-1     :   0] destport_in;
-    output reg  [P-1       :   0] destport_out;
-    
-    integer i;   
-    always @(*)begin 
-        for(i=0;i<P;i=i+1)begin :port_loop
-            if      (i>SW_LOC)      destport_out[i]      =   destport_in[i-1];
-            else if (i==SW_LOC)     destport_out[i]      =   1'b0;
-            else                    destport_out[i]      =   destport_in[i];
-        end//for 
-    end
-    
-    
-    
- endmodule  
-
-
-module add_sw_loc_one_hot_val #(
-    parameter P          =   5,
-    parameter SW_LOC     = 1
-    
-)
-(
-    sw_loc_val,
-    destport_in,
-    destport_out
-);
-
-    localparam P_1 = P-1;
-    input sw_loc_val;
-    input       [P_1-1     :   0] destport_in;
-    output reg  [P-1       :   0] destport_out;
-    
-    integer i;   
-    always @(*)begin 
-        for(i=0;i<P;i=i+1)begin :port_loop
-            if      (i>SW_LOC)      destport_out[i]      =   destport_in[i-1];
-            else if (i==SW_LOC)     destport_out[i]      =   sw_loc_val;
-            else                    destport_out[i]      =   destport_in[i];
-        end//for 
-    end
-    
-    
-    
- endmodule  
-
-
-/***************************************************
-
-                    conventional routing 
-   
-***************************************************/
-
-module mesh_torus_conventional_routing #(
-    parameter TOPOLOGY          =   "MESH", 
-    parameter ROUTE_NAME        =   "XY",
-    parameter ROUTE_TYPE        =   "DETERMINISTIC",    
-    parameter NX                =   4,
-    parameter NY                =   4,
-    parameter LOCATED_IN_NI     =   0//use for add even only
-        
-    )
-    (   
-    current_x,
-    current_y,
-    dest_x,
-    dest_y,
-    destport
-
-    );
-    
-
-    function integer log2;
-      input integer number; begin   
-         log2=(number <=1) ? 1: 0;    
-         while(2**log2<number) begin    
-            log2=log2+1;    
-         end        
-      end   
-    endfunction // log2 
-   /* verilator lint_off WIDTH */ 
-   localparam P =  (TOPOLOGY=="RING" || TOPOLOGY=="LINE" )? 3 : 5,
-   /* verilator lint_on WIDTH */ 
-              P_1   =   P-1,
-              Xw    =   log2(NX),
-              Yw    =  (TOPOLOGY=="RING" || TOPOLOGY=="LINE" )? 1 : log2(NY);
-              
-    localparam DSTw     =    P_1;               
-              
-    input   [Xw-1         :0] current_x;
-    input   [Yw-1         :0] current_y;
-    input   [Xw-1         :0] dest_x;
-    input   [Yw-1         :0] dest_y;
-    
-    output  [DSTw-1       :0] destport;
-  
-  
-    generate 
-        /* verilator lint_off WIDTH */ 
-        if (TOPOLOGY == "MESH" || TOPOLOGY == "FMESH")begin :mesh
-            if(ROUTE_NAME ==  "XY") begin : xy_routing_blk
-        /* verilator lint_on WIDTH */ 
-                
-                xy_mesh_routing #(
-                    .NX(NX),
-                    .NY(NY)                   
-                )
-                 xy_routing
-                (
-                    .current_x(current_x),
-                    .current_y(current_y),
-                    .dest_x(dest_x),
-                    .dest_y(dest_y),
-                    .dstport_encoded(destport)
-                 );        
-                
-                
-            end //"XY"
-            /* verilator lint_off WIDTH */ 
-            else if(ROUTE_NAME    ==  "WEST_FIRST") begin : west_first_routing_blk
-            /* verilator lint_on WIDTH */ 
-                west_first_routing #(
-                    .NX         (NX),
-                    .NY         (NY)
-                ) 
-                west_first
-                (
-                    .current_x          (current_x),
-                    .current_y          (current_y),
-                    .dest_x             (dest_x),
-                    .dest_y             (dest_y),
-                    .destport           (destport)
-                   
-                );
-            end // WEST_FIRST
-            /* verilator lint_off WIDTH */ 
-            else if(ROUTE_NAME    ==  "NORTH_LAST") begin : north_last_routing_blk
-            /* verilator lint_on WIDTH */ 
-                north_last_routing #(
-                    .NX         (NX),
-                    .NY         (NY)
-                ) 
-                north_last
-                (
-                    .current_x          (current_x),
-                    .current_y          (current_y),
-                    .dest_x             (dest_x),
-                    .dest_y             (dest_y),
-                    .destport           (destport)
-                   
-                );
-                       
-            end // NORTH_LAST
-            /* verilator lint_off WIDTH */ 
-            else if(ROUTE_NAME    ==  "NEGETIVE_FIRST") begin : negetive_first_routing_blk
-            /* verilator lint_on WIDTH */ 
-                negetive_first_routing #(
-                    .NX         (NX),
-                    .NY         (NY)
-                ) 
-                negetive_first
-                (
-                    .current_x          (current_x),
-                    .current_y          (current_y),
-                    .dest_x             (dest_x),
-                    .dest_y             (dest_y),
-                    .destport           (destport)
-                   
-                );
-                       
-            end // NEGETIVE_FIRST           
-            /* verilator lint_off WIDTH */ 
-            else if(ROUTE_NAME    ==  "ODD_EVEN") begin : odd_even_routing_blk
-            /* verilator lint_on WIDTH */ 
-                odd_even_routing #(
-                    .NX         (NX),
-                    .NY         (NY),
-                    .LOCATED_IN_NI      (LOCATED_IN_NI)
-                    
-                ) odd_even
-                (
-                    .current_x          (current_x),
-                    .current_y          (current_y),
-                    .dest_x             (dest_x),
-                    .dest_y             (dest_y),
-                    .destport           (destport)
-                );
-                
-            end //ODD_EVEN
-            /* verilator lint_off WIDTH */ 
-            else if(ROUTE_NAME    ==  "DUATO") begin : duato_routing_blk
-            /* verilator lint_on WIDTH */ 
-                duato_mesh_routing #(
-                    .NX         (NX),
-                    .NY         (NY)                    
-                ) 
-                duato_full_adaptive
-                (
-                    .current_x          (current_x),
-                    .current_y          (current_y),
-                    .dest_x             (dest_x),
-                    .dest_y             (dest_y),
-                    .destport           (destport)
-                    
-                    
-                );
-            end //DUATO
-        //synthesis translate_off
-        //synopsys  translate_off
-            else begin : not_supported initial $display ("Error: %s is an unsupported routing algorithm for %s topology \n",ROUTE_NAME,TOPOLOGY); end
-        //synopsys  translate_on
-        //synthesis translate_on
-        /* verilator lint_off WIDTH */ 
-        end else if (TOPOLOGY == "TORUS" ) begin :torus
-            if(ROUTE_NAME ==  "TRANC_XY") begin : tranc_routing_blk
-        /* verilator lint_on WIDTH */ 
-                tranc_xy_routing #(
-                    .NX (NX),
-                    .NY (NY)
-                ) 
-                tranc_xy
-                (
-                    .current_x          (current_x),
-                    .current_y          (current_y),
-                    .dest_x             (dest_x),
-                    .dest_y             (dest_y),
-                    .destport_encoded   (destport)
-                   
-                
-                );
-                
-            end //"TRANC_XY"
-            /* verilator lint_off WIDTH */ 
-            else if(ROUTE_NAME    ==  "TRANC_WEST_FIRST") begin : tranc_west_first_routing_blk
-            /* verilator lint_on WIDTH */ 
-                tranc_west_first_routing #(
-                    .NX         (NX),
-                    .NY         (NY)
-                ) 
-                tranc_west_first
-                (
-                    .current_x          (current_x),
-                    .current_y          (current_y),
-                    .dest_x             (dest_x),
-                    .dest_y             (dest_y),
-                    .destport           (destport)
-                   
-                );
-             end // TRANC_WEST_FIRST
-             /* verilator lint_off WIDTH */ 
-             else if(ROUTE_NAME    ==  "TRANC_NORTH_LAST") begin : tranc_north_last_routing_blk
-             /* verilator lint_on WIDTH */ 
-                tranc_north_last_routing #(
-                    .NX         (NX),
-                    .NY         (NY)
-                ) 
-                tranc_north_last
-                (
-                    .current_x          (current_x),
-                    .current_y          (current_y),
-                    .dest_x             (dest_x),
-                    .dest_y             (dest_y),
-                    .destport           (destport)
-                   
-                );
-             end // TRANC_NORTH_LAST
-             /* verilator lint_off WIDTH */ 
-             else if(ROUTE_NAME    ==  "TRANC_NEGETIVE_FIRST") begin : tranc_negetive_first_routing_blk
-             /* verilator lint_on WIDTH */ 
-                tranc_negetive_first_routing #(
-                    .NX         (NX),
-                    .NY         (NY)
-                ) 
-                tranc_negetive_first
-                (
-                    .current_x          (current_x),
-                    .current_y          (current_y),
-                    .dest_x             (dest_x),
-                    .dest_y             (dest_y),
-                    .destport           (destport)
-                   
-                );
-             end // TRANC_NEGETIVE_FIRST
-            /* verilator lint_off WIDTH */ 
-            else if(ROUTE_NAME    ==  "TRANC_DUATO") begin : tranc_duato_routing_blk
-            /* verilator lint_on WIDTH */ 
-                tranc_duato_routing #(
-                    .NX         (NX),
-                    .NY         (NY)
-                )
-                duato_full_adaptive
-                (
-                    .current_x          (current_x),
-                    .current_y          (current_y),
-                    .dest_x             (dest_x),
-                    .dest_y             (dest_y),
-                    .destport           (destport)
-                   
-                );
-            end //TRANC_DUATO
-        //synthesis translate_off
-        //synopsys  translate_off
-            else begin : not_supported2 initial $display("Error: %s is an unsupported routing algorithm for %s topology",ROUTE_NAME,TOPOLOGY); end
-        //synopsys  translate_on
-        //synthesis translate_on
-        end //TORUS
-        
-        /* verilator lint_off WIDTH */ 
-        else if (TOPOLOGY == "RING" ) begin :ring
-            if(ROUTE_NAME == "TRANC_XY") begin : tranc_ring_blk
-        /* verilator lint_on WIDTH */ 
-                tranc_ring_routing #(
-                    .NX(NX)       
-                )
-                tranc_ring                
-                (
-                    .current_x(current_x),
-                    .dest_x(dest_x),
-                    .destport(destport)    
-                );
-            end // "TRANC"
-    //synthesis translate_off
-        //synopsys  translate_off
-        else begin : not_supported2 initial $display("Error: %s is an unsupported routing algorithm for %s topology",ROUTE_NAME,TOPOLOGY); end  
-    //synopsys  translate_on
-        //synthesis translate_on     
-        end //"RING" 
-        
-        /* verilator lint_off WIDTH */ 
-        else if (TOPOLOGY == "LINE" ) begin :ring
-            if(ROUTE_NAME == "XY") begin : tranc_ring_blk
-        /* verilator lint_on WIDTH */ 
-                xy_line_routing #(
-                    .NX(NX)                    
-                )
-                 xy_routing
-                (
-                    .current_x(current_x),
-                    .dest_x(dest_x),
-                    .destport(destport)
-                 );       
-            end // "XY"
-    //synthesis translate_off
-        //synopsys  translate_off
-        else begin : not_supported2 initial $display("Error: %s is an unsupported routing algorithm for %s topology",ROUTE_NAME,TOPOLOGY); end
-    //synopsys  translate_on
-        //synthesis translate_on           
-        end //"LINE" 
-        
-        
-       
-    //synthesis translate_off
-    //synopsys  translate_off
-            else begin : wrong_topology initial $display("Error: %s is an unsupported topology",TOPOLOGY); end
-    //synopsys  translate_on
-    //synthesis translate_on
-            
-    endgenerate
-
-    //force modelsim to add route_mesh & turos files
-    
-    
-    
-endmodule
-
-
-
-
-
-/********************************************
-                        TRANC_ring
-*********************************************/
-
-module tranc_ring_routing #(
-    parameter NX   =    4    
-)
-(
-    current_x,
-    dest_x,
-    destport
-    
-);
-
- 
-    function integer log2;
-      input integer number; begin   
-         log2=(number <=1) ? 1: 0;    
-         while(2**log2<number) begin    
-            log2=log2+1;    
-         end        
-      end   
-    endfunction // log2 
-
-    
-    localparam  P           =   3,
-                Xw          =   log2(NX),
-                DSTw        =   P-1;
-    
-    
-    input   [Xw-1       :   0] current_x;
-    input   [Xw-1       :   0] dest_x;
-    output  [DSTw -1    :   0] destport;
-    
-    localparam      LOCAL   =    3'b001,  
-                    PLUS    =    3'b010,   
-                    MINUS   =    3'b100;    
-                    
-    reg [P-1            :0] destport_one_hot;
-   
-   
-
-    reg tranc_x_plus;
-    reg tranc_x_min;
-    wire same_x;
-    
-    
-
-    localparam SIGNED_X_WIDTH   =  (Xw<3) ? 4 : Xw+1;
-  
-    
-    wire signed [SIGNED_X_WIDTH-1       :0] xc;//current 
-    wire signed [SIGNED_X_WIDTH-1       :0] xd;//destination
-    wire signed [SIGNED_X_WIDTH-1       :0] xdiff;
-   
-    
-    assign  xd  ={{(SIGNED_X_WIDTH-Xw){1'b0}}, dest_x};
-    assign  xc  ={{(SIGNED_X_WIDTH-Xw){1'b0}}, current_x [Xw-1      :0]};
-    assign  xdiff   = xd-xc;
-   
-    
-    always@ (*)begin 
-        tranc_x_plus    =1'b0;
-        tranc_x_min     =1'b0;
-        if(xdiff!=0)begin 
-            if ((xdiff ==1) || 
-                 (xdiff == (-NX+1)) ||
-                 ((xc == (NX-4)) && (xd == (NX-2))) ||
-                 ((xc >= (NX-2)) && (xd <= (NX-4))) ||
-                 ((xdiff> 0) && (xd<= (NX-3)))) 
-                    tranc_x_plus    = 1'b1;
-            else    tranc_x_min     = 1'b1;
-        end
-        
-    end//always
-    
-    assign same_x = (xdiff == 0);
-
-
-
-        
-    always@(*)begin
-        if (same_x ) destport_one_hot= LOCAL;
-        else    begin 
-            if          (tranc_x_plus)  destport_one_hot= PLUS;
-            else if     (tranc_x_min)   destport_one_hot= MINUS;
-         end
-    end
-
- line_ring_encode_dstport encode(
-        .dstport_one_hot(destport_one_hot),
-        .dstport_encoded(destport)
-    );
-   
-    
-endmodule
-
-
-
-/********************************************
-                        xy_line
-*********************************************/
-
-module xy_line_routing #(
-    parameter NX   =    8      
-)
-(
-    current_x,
-    dest_x,
-    destport
-    
-);
-
- 
-    function integer log2;
-      input integer number; begin   
-         log2=(number <=1) ? 1: 0;    
-         while(2**log2<number) begin    
-            log2=log2+1;    
-         end        
-      end   
-    endfunction // log2 
-
-    
-    localparam  OUT_BIN     =   0,
-                P           =   3,
-                Xw          =   log2(NX);
-               
-    
-    
-    input   [Xw-1       :   0] current_x;
-    input   [Xw-1       :   0] dest_x;
-    output  [1       :   0] destport;
-    
-    localparam      LOCAL   =   (OUT_BIN)?  3'd0    : 3'b001,  
-                    PLUS    =   (OUT_BIN)?  3'd1    : 3'b010,   
-                    MINUS   =   (OUT_BIN)?  3'd2    : 3'b100;         
-                    
-            
-                    
-    reg [P-1            :0] destport_one_hot;
-    
-    
-    always@(*)begin
-            destport_one_hot    = LOCAL [2    :0];
-            if           (dest_x    > current_x)        destport_one_hot    = PLUS  [2    :0];
-            else if      (dest_x    < current_x)        destport_one_hot    = MINUS [2    :0];            
-    end
-    
-    
-    line_ring_encode_dstport encode(
-    	.dstport_one_hot(destport_one_hot),
-    	.dstport_encoded(destport)
-    );
-   
-    
-endmodule
-
-
-module line_ring_encode_dstport (
-    dstport_one_hot,
-    dstport_encoded
-);
-
-    input  [2 : 0] dstport_one_hot;
-    output [1 : 0] dstport_encoded; 
-    
-    
-              
-     localparam  FORWARD =  2'd1,
-                 BACKWARD=  2'd2;
-    
-    /************************   
-    
-        destination-port_in
-            2'b11 : FORWARD or BACKWARD // can be sent to any of them
-            2'b10 : BACKWARD
-            2'b01 : FORWARD
-            2'b00 : LOCAL
-    *******************/
-// code the destination port
-    assign dstport_encoded = {dstport_one_hot[BACKWARD], dstport_one_hot[FORWARD]};
-
-endmodule
-
-
-module line_ring_decode_dstport (
-    dstport_one_hot,
-    dstport_encoded
-);
-
-    output  reg [2 : 0] dstport_one_hot;
-    input   [1 : 0] dstport_encoded; 
-     
-         /************************   
-      localparam  FORWARD =  2'd1,
-                 BACKWARD=  2'd2;
-        destination-port_in
-            2'b11 : FORWARD or BACKWARD // can be sey to any of them
-            2'b10 : BACKWARD
-            2'b01 : FORWARD
-            2'b00 : LOCAL
-    *******************/
-// code the destination port
-    //assign dstport_encoded = {dstport_one_hot[BACKWARD], dstport_one_hot[FORWARD]};
-       
-      
-          
-        always @(*)begin 
-            dstport_one_hot = 3'b000;
-            case(dstport_encoded)
-                2'b10 : dstport_one_hot=3'b100;
-                2'b01 : dstport_one_hot=3'b010;
-                2'b00 : dstport_one_hot=3'b001;
-                2'b11 : dstport_one_hot=3'b110; //invalid condition in determinstic routing
-            endcase
-        end //always
-endmodule
-
-
-
-module mesh_tori_decode_dstport (
-    dstport_encoded,
-    dstport_one_hot
-    
-);
-
-    
-    input   [3 : 0] dstport_encoded; 
-    output  reg [4 : 0] dstport_one_hot;
-    
-    wire x,y,a,b;
-   
-    
-    assign {x,y,a,b} = dstport_encoded;
-  
-   always @(*)begin 
-        dstport_one_hot = 5'd0;
-        case({a,b})
-            2'b10 : dstport_one_hot = {1'b0,~x,1'b0,x,1'b0};
-            2'b01 : dstport_one_hot = {~y,1'b0,y,1'b0,1'b0};
-            2'b11 : dstport_one_hot = {1'b0,~x,1'b0,x,1'b0}; //illegal
-            2'b00 : dstport_one_hot =  5'b00001;
-         endcase
-   end //always
-   
-endmodule   
diff --git a/mpsoc/rtl/src_noc/multicast.sv b/mpsoc/rtl/src_noc/multicast.sv
index 6943f44..8da717e 100644
--- a/mpsoc/rtl/src_noc/multicast.sv
+++ b/mpsoc/rtl/src_noc/multicast.sv
@@ -1,5 +1,4 @@
 `include "pronoc_def.v"
-
 /**************************************
  * Module: router_bypass
  * Date:2021-11-14  
@@ -9,829 +8,590 @@
  *   This file contains HDL modules that can be added
  *   to NoC router to provide multicasting
  ***************************************/
- 
-
-
-
 
 /************************************
-
-     look_ahead_routing
-
- *************************************/
- 
+*     look_ahead_routing
+*************************************/
 module multicast_routing # (
-	parameter NOC_ID=0,
-	parameter SW_LOC=0,    
- 	parameter P=5
+    parameter SW_LOC=0,    
+    parameter P=5
 )(
-	current_r_addr,  //current router  address
-	dest_e_addr,  // destination endpoint address		
-	destport		
+    current_r_addr,  //current router  address
+    dest_e_addr,  // destination endpoint address        
+    destport        
 );
-
-	`NOC_CONF	
-		
-	input   [RAw-1   :   0]  current_r_addr;
-	input   [DAw-1   :   0]  dest_e_addr;
-	output  [DSTPw-1  :   0] destport;
-	
- 	generate
- 	/* verilator lint_off WIDTH */	
- 	if(TOPOLOGY=="MESH") begin: mesh
- 	/* verilator lint_on WIDTH */	
-		multicast_routing_mesh #(
- 			.NOC_ID(NOC_ID),
-			.P(P) ,
- 			.SW_LOC(SW_LOC)		
- 		) routing (
- 			.current_r_addr(current_r_addr),  //current router  address
- 			.dest_e_addr(dest_e_addr),  // destination endpoint address		
- 			.destport(destport)		
- 		);
- 	/* verilator lint_off WIDTH */	
- 	end else if (TOPOLOGY == "FMESH") begin : fmesh 
- 	/* verilator lint_on WIDTH */
- 		multicast_routing_fmesh #(
- 			.NOC_ID(NOC_ID),
-			.P(P) ,
- 			.SW_LOC(SW_LOC)		
- 		) routing (
- 			.current_r_addr(current_r_addr),  //current router  address
- 			.dest_e_addr(dest_e_addr),  // destination endpoint address		
- 			.destport(destport)		
- 		);
- 	
-	/* verilator lint_off WIDTH */	
- 	end else if (TOPOLOGY == "STAR") begin : star
- 	/* verilator lint_on WIDTH */
- 		multicast_routing_star #(
- 			.NOC_ID(NOC_ID),
-			.P(P) ,
- 			.SW_LOC(SW_LOC)		
- 		) routing (
- 			.current_r_addr(current_r_addr),  //current router  address
- 			.dest_e_addr(dest_e_addr),  // destination endpoint address		
- 			.destport(destport)		
- 		);
- 	end else begin 
- 		initial begin 
- 			$display ("ERROR: Multicast/Broadcast is not yet supported for %s Topology",TOPOLOGY);
- 			$finish;
- 		end
- 	end
- 	endgenerate
- 	
- 
- 
+    import pronoc_pkg::*;    
+    input   [RAw-1 : 0]  current_r_addr;
+    input   [DAw-1 : 0]  dest_e_addr;
+    output  [DSTPw-1 : 0] destport;
+    generate
+    if(IS_MESH) begin: mesh
+        multicast_routing_mesh #(
+            .SW_LOC(SW_LOC)
+        ) routing (
+            .current_r_addr(current_r_addr),  //current router  address
+            .dest_e_addr(dest_e_addr),  // destination endpoint address
+            .destport(destport)
+        );
+    end else if (IS_FMESH) begin : fmesh 
+        multicast_routing_fmesh #(
+            .P(P) ,
+            .SW_LOC(SW_LOC)        
+        ) routing (
+            .current_r_addr(current_r_addr),  //current router  address
+            .dest_e_addr(dest_e_addr),  // destination endpoint address
+            .destport(destport)        
+        );
+    end else if (IS_STAR) begin : star
+        multicast_routing_star #(
+            .P(P) ,
+            .SW_LOC(SW_LOC)        
+        ) routing (
+            .current_r_addr(current_r_addr),  //current router  address
+            .dest_e_addr(dest_e_addr),  // destination endpoint address        
+            .destport(destport)        
+        );
+    end 
+    `ifdef SIMULATION
+    else begin 
+        initial begin 
+            $display ("ERROR: Multicast/Broadcast is not yet supported for %s Topology",TOPOLOGY);
+            $finish;
+        end
+    end
+    `endif
+    endgenerate
 endmodule
 
-module multicast_routing_mesh	#(
-	parameter NOC_ID=0,
-	parameter SW_LOC=0,   
- 	parameter P=5
-) (
-	current_r_addr,  //current router  address
-	dest_e_addr,  // destination endpoint address		
-	destport		
+
+module multicast_routing_mesh #(
+    parameter SW_LOC=0
+)(
+    current_r_addr,  //current router  address
+    dest_e_addr,  // destination endpoint address
+    destport
 );   
     
-   `NOC_CONF
-	
-	input   [RAw-1   :   0]  current_r_addr;
-	input   [DAw-1   :   0]  dest_e_addr;
-	output  [DSTPw-1  :   0] destport;
-
+    import pronoc_pkg::*;
     
-	localparam
-		RXw = log2(NX),   
-		RYw = log2(NY),  
-		EXw = RXw,
-		EYw = RYw;
-		
-		
-	//mask gen. x_plus: all rows larger than current router x address are asserted.
-	wire [NX-1 : 0] x_plus,x_minus;
-	//mask generation. Only the corresponding bits to destination located in current column are asserted in each mask 	
-	wire [NE-1 : 0] y_plus,y_min;
-	//Only one-bit is asserted for each local_p[i]
-	wire [NE-1 : 0] local_p [NL-1 : 0];
-        
-	wire   [RXw-1   :   0]  current_rx;
-	wire   [RYw-1   :   0]  current_ry;                  
-			
-    	mesh_tori_router_addr_decode #(
-			.TOPOLOGY(TOPOLOGY),
-			.T1(T1),
-			.T2(T2),
-			.T3(T3),
-			.RAw(RAw)
-		)
-		router_addr_decode
-		(
-			.r_addr(current_r_addr),
-			.rx(current_rx),
-			.ry(current_ry),
-			.valid( )
-		);
-			
-			
-		
-		wire [NX-1 : 0] row_has_any_dest;
-		wire [NE-1 : 0] dest_mcast_all_endp;			
-		
-		mcast_dest_list_decode #(
-			.NOC_ID(NOC_ID)
-		) decode (
-			.dest_e_addr(dest_e_addr),
-			.dest_o(dest_mcast_all_endp),
-			.row_has_any_dest(row_has_any_dest),
-			.is_unicast()
-		);
-				
-		genvar i,j;
-		generate 
-			
-			for(i=0; i< NX; i=i+1) begin : X_
-				assign x_plus[i]  = (current_rx	>	i);
-				/* verilator lint_off UNSIGNED */
-				assign x_minus[i] = (current_rx	<	i);
-				/* verilator lint_on UNSIGNED */
-			end
-								
-			//get all endp addresses located in the same x
-			for(i=0; i< NE; i=i+1) begin : endpoints
-			//Endpoint decoded address
-							
-					localparam						
-						Y_LOC = ((i/NL) / NX ), 
-						X_LOC = ((i/NL) % NX ), 
-						LL = (i % NL);
-					localparam [RYw-1   :   0] YY = Y_LOC [RYw-1   :   0];
-					localparam [RXw-1   :   0] XX = X_LOC [RXw-1   :   0];
-					
-					/* verilator lint_off CMPCONST */
-					assign y_plus[i]  = (current_rx	==	XX) && (current_ry >  YY);
-					/* verilator lint_on CMPCONST */
-						
-					/* verilator lint_off UNSIGNED */
-					assign y_min[i]   = (current_rx	==	XX) && (current_ry <  YY);
-					/* verilator lint_on UNSIGNED */
-					for(j=0;j<NL;j++)begin : lp
-						assign local_p[j][i] = (current_rx	==	XX) && (current_ry == YY) && (LL == j);
-					end		
-					
-			end //i	
-					
-			
-			wire goto_north = |(y_plus  & dest_mcast_all_endp);
-			wire goto_south = |(y_min   & dest_mcast_all_endp);
-			wire goto_east  = |(x_minus & row_has_any_dest);
-			wire goto_west  = |(x_plus  & row_has_any_dest);
-			
-			
-			wire [NL-1 : 0] goto_local;
-			for(i=0; i< NL; i=i+1) begin : endps
-				assign goto_local[i] = |(local_p[i] & dest_mcast_all_endp);// will be synthesized as single bit assign
-			end//for
-			
-			
-			
-			reg [4  :   0] destport_tmp;
-			
-			always @(*) begin 
-				destport_tmp = {5{1'b0}};
-				destport_tmp[LOCAL]=goto_local[LOCAL];				
-				if     (SW_LOC == SOUTH) destport_tmp [NORTH] = goto_north;
-				else if(SW_LOC == NORTH) destport_tmp [SOUTH] = goto_south;
-				else if(SW_LOC == WEST)begin 
-					destport_tmp [NORTH] = goto_north;
-					destport_tmp [SOUTH] = goto_south;
-					destport_tmp [EAST ] = goto_east;					
-				end
-				else if(SW_LOC == EAST) begin 
-					destport_tmp [NORTH] = goto_north;
-					destport_tmp [SOUTH] = goto_south;
-					destport_tmp [WEST ] = goto_west;					
-				end
-				else if(SW_LOC == LOCAL || SW_LOC > SOUTH) begin
-					destport_tmp [NORTH] = goto_north;
-					destport_tmp [SOUTH] = goto_south;
-					destport_tmp [EAST]  = goto_east;
-					destport_tmp [WEST]  = goto_west;
-				end							
-			end
-			
-			localparam MSB_DSTP = (DSTPw-1 < SOUTH)? DSTPw-1: SOUTH;
-				
-			assign destport [MSB_DSTP : 0] =destport_tmp;
-			for(i=1;i<NL;i++) begin :other_local
-				assign destport[MSB_DSTP+i]=goto_local[i];			
-			end	
-	endgenerate
-	
+    input   [RAw-1 : 0]  current_r_addr;
+    input   [DAw-1 : 0]  dest_e_addr;
+    output  [DSTPw-1 : 0] destport;
+    
+    //mask gen. x_plus: all rows larger than current router x address are asserted.
+    wire [NX-1 : 0] x_plus,x_minus;
+    //mask generation. Only the corresponding bits to destination located in current column are asserted in each mask     
+    wire [NE-1 : 0] y_plus,y_min;
+    //Only one-bit is asserted for each local_p[i]
+    wire [NE-1 : 0] local_p [NL-1 : 0];
+    wire   [NXw-1 : 0]  current_rx;
+    wire   [NYw-1 : 0]  current_ry;
+    regular_topo_router_addr_t current_router_addr_struct;
+    assign current_router_addr_struct = regular_topo_router_addr_t'(current_r_addr);
+    assign current_rx = current_router_addr_struct.x;
+    assign current_ry = current_router_addr_struct.y;
+    wire [NX-1 : 0] row_has_any_dest;
+    wire [NE-1 : 0] dest_mcast_all_endp;
+    mcast_dest_list_decode decode (
+        .dest_e_addr(dest_e_addr),
+        .dest_o(dest_mcast_all_endp),
+        .row_has_any_dest(row_has_any_dest),
+        .is_unicast()
+    );
+    genvar i,j;
+    generate 
+    for(i=0; i< NX; i=i+1) begin : X_
+        assign x_plus[i]  = (current_rx    >    i);
+        /* verilator lint_off UNSIGNED */
+        assign x_minus[i] = (current_rx    <    i);
+        /* verilator lint_on UNSIGNED */
+    end
+    //get all endp addresses located in the same x
+    for(i=0; i< NE; i=i+1) begin : endpoints
+        //Endpoint decoded address
+        localparam                        
+            Y_LOC = ((i/NL) / NX ), 
+            X_LOC = ((i/NL) % NX ), 
+            LL = (i % NL);
+        localparam [NYw-1 : 0] YY = Y_LOC [NYw-1 : 0];
+        localparam [NXw-1 : 0] XX = X_LOC [NXw-1 : 0];
+        /* verilator lint_off CMPCONST */
+        assign y_plus[i]  = (current_rx    ==    XX) && (current_ry >  YY);
+        /* verilator lint_on CMPCONST */
+        /* verilator lint_off UNSIGNED */
+        assign y_min[i]   = (current_rx    ==    XX) && (current_ry <  YY);
+        /* verilator lint_on UNSIGNED */
+        for(j=0;j<NL;j++)begin : lp
+            assign local_p[j][i] = (current_rx    ==    XX) && (current_ry == YY) && (LL == j);
+        end //j       
+    end //i    
+    wire goto_north = |(y_plus  & dest_mcast_all_endp);
+    wire goto_south = |(y_min   & dest_mcast_all_endp);
+    wire goto_east  = |(x_minus & row_has_any_dest);
+    wire goto_west  = |(x_plus  & row_has_any_dest);
+    wire [NL-1 : 0] goto_local;
+    for(i=0; i< NL; i=i+1) begin : endps
+        assign goto_local[i] = |(local_p[i] & dest_mcast_all_endp);// will be synthesized as single bit assign
+    end//for
+    reg [4 : 0] destport_tmp;
+    always_comb begin 
+        destport_tmp = {5{1'b0}};
+        destport_tmp[LOCAL]=goto_local[LOCAL];
+        if     (SW_LOC == SOUTH) destport_tmp [NORTH] = goto_north;
+        else if(SW_LOC == NORTH) destport_tmp [SOUTH] = goto_south;
+        else if(SW_LOC == WEST)begin 
+            destport_tmp [NORTH] = goto_north;
+            destport_tmp [SOUTH] = goto_south;
+            destport_tmp [EAST ] = goto_east;
+        end
+        else if(SW_LOC == EAST) begin 
+            destport_tmp [NORTH] = goto_north;
+            destport_tmp [SOUTH] = goto_south;
+            destport_tmp [WEST ] = goto_west;
+        end
+        else if(SW_LOC == LOCAL || SW_LOC > SOUTH) begin
+            destport_tmp [NORTH] = goto_north;
+            destport_tmp [SOUTH] = goto_south;
+            destport_tmp [EAST]  = goto_east;
+            destport_tmp [WEST]  = goto_west;
+        end
+    end
+    localparam MSB_DSTP = (DSTPw-1 < SOUTH)? DSTPw-1: SOUTH;
+    assign destport [MSB_DSTP : 0] =destport_tmp;
+    for(i=1;i<NL;i++) begin :other_local
+        assign destport[MSB_DSTP+i]=goto_local[i];
+    end    
+    endgenerate
 endmodule
 
 module multicast_routing_star #(
-	parameter NOC_ID=0,
-	parameter SW_LOC=0,    
- 	parameter P=5
-) (
-	current_r_addr,  //current router  address
-	dest_e_addr,  // destination endpoint address		
-	destport		
+    parameter SW_LOC=0,    
+    parameter P=5
+)(
+    current_r_addr,  //current router  address
+    dest_e_addr,  // destination endpoint address        
+    destport        
 );
-	`NOC_CONF
-	input   [RAw-1   :   0]  current_r_addr;
-	input   [DAw-1   :   0]  dest_e_addr;
-	output  [DSTPw-1 :   0]  destport;
-	
-	
-	mcast_dest_list_decode # (
-		.NOC_ID(NOC_ID)
-	) decode (
-		.dest_e_addr(dest_e_addr),
-		.dest_o(destport),
-		.row_has_any_dest(),
-		.is_unicast()
-	);
-
+    import pronoc_pkg::*;
+    input   [RAw-1 : 0]  current_r_addr;
+    input   [DAw-1 : 0]  dest_e_addr;
+    output  [DSTPw-1 : 0]  destport;
+    
+    mcast_dest_list_decode decode (
+        .dest_e_addr(dest_e_addr),
+        .dest_o(destport),
+        .row_has_any_dest(),
+        .is_unicast()
+    );
 endmodule
 
 
 module multicast_routing_fmesh #(
-	parameter NOC_ID=0,
-	parameter SW_LOC=0,    
- 	parameter P=5
+    parameter SW_LOC=0,    
+    parameter P=5
 ) (
-	current_r_addr,  //current router  address
-	dest_e_addr,  // destination endpoint address		
-	destport		
+    current_r_addr,  //current router  address
+    dest_e_addr,  // destination endpoint address        
+    destport        
 );
-
-	`NOC_CONF
-	
-	input   [RAw-1   :   0]  current_r_addr;
-	input   [DAw-1   :   0]  dest_e_addr;
-	output  [DSTPw-1 :   0]  destport;
-
-	localparam Pw = log2(MAX_P_FMESH);
-	
-	localparam		
-		RXw = log2(NX),   
-		RYw = log2(NY),  
-		EXw = RXw,
-		EYw = RYw;
-	
-	wire   [RXw-1   :   0]  current_rx;
-	wire   [RYw-1   :   0]  current_ry;   
-	
-	
-	//mask gen. x_plus: all rows larger than current router x address are asserted.
-	wire [NX-1 : 0] x_plus,x_minus;
-	//mask generation. Only the corresponding bits to destination located in current column are asserted in each mask 	
-	wire [NE-1 : 0] y_plus,y_min;
-	//Only one-bit is asserted for each local_p[i]
-	wire [NE-1 : 0] local_p [MAX_P_FMESH-1 : 0];
-			
-	mesh_tori_router_addr_decode #(
-		.TOPOLOGY(TOPOLOGY),
-		.T1(T1),
-		.T2(T2),
-		.T3(T3),
-		.RAw(RAw)
-	)
-	router_addr_decode
-	(
-		.r_addr(current_r_addr),
-		.rx(current_rx),
-		.ry(current_ry),
-		.valid( )
-	);
-	
-	
-	wire [NX-1 : 0] row_has_any_dest;
-	wire [NE-1 : 0] dest_mcast_all_endp;			
-		
-	mcast_dest_list_decode # (
-		.NOC_ID(NOC_ID)
-	) decode (
-		.dest_e_addr(dest_e_addr),
-		.dest_o(dest_mcast_all_endp),
-		.row_has_any_dest(row_has_any_dest),
-		.is_unicast()
-	);
-	
-	
-	genvar i,j;
-	generate 
-			
-	for(i=0; i< NX; i=i+1) begin : X_
-		assign x_plus[i]  = (current_rx	>	i);
-		/* verilator lint_off UNSIGNED */
-		assign x_minus[i] = (current_rx	<	i);
-		/* verilator lint_on UNSIGNED */
-	end
-								
-	//get all endp addresses located in the same x
-	for(i=0; i< NE; i=i+1) begin : endpoints
-		//Endpoint decoded address
-		localparam 
-			ADR = fmesh_addrencode(i),			
-			XX = ADR [NXw -1 : 0],
-			YY = ADR [NXw+NYw-1 : NXw], 
-			PP = ADR [NXw+NYw+Pw-1 : NXw+NYw]; 			
-		
-		/* verilator lint_off CMPCONST */
-		assign y_plus[i]  = (current_rx	==	XX) && (current_ry >  YY);
-		/* verilator lint_on CMPCONST */
-					
-		/* verilator lint_off UNSIGNED */
-		assign y_min[i]   = (current_rx	==	XX) && (current_ry <  YY);
-		/* verilator lint_on UNSIGNED */
-		
-		for(j=0;j<MAX_P_FMESH;j++)begin : lp
-			assign local_p[j][i] = (current_rx	==	XX) && (current_ry == YY) && (PP == j);
-		end		
-	end//for ne
-	
-	wire [MAX_P_FMESH-1 : 0] goto_local;
-	for(i=0; i<MAX_P_FMESH ; i=i+1) begin : endps
-		assign goto_local[i] = |(local_p[i] & dest_mcast_all_endp);// will be synthesized as single bit assign
-	end//for	
-		
-		
-	wire goto_north = (|(y_plus  & dest_mcast_all_endp)) | goto_local[NORTH];
-	wire goto_south = (|(y_min   & dest_mcast_all_endp)) | goto_local[SOUTH];
-	wire goto_east  = (|(x_minus & row_has_any_dest))    | goto_local[EAST];
-	wire goto_west  = (|(x_plus  & row_has_any_dest))    | goto_local[WEST];
-		
-			
-	reg [4  :   0] destport_tmp;
-			
-	always @(*) begin 
-		destport_tmp = {DSTPw{1'b0}};
-		destport_tmp[LOCAL]=goto_local[LOCAL];				
-		if     (SW_LOC == SOUTH)begin 
-			destport_tmp [NORTH] = goto_north ;
-			destport_tmp [EAST]  = goto_east;
-			destport_tmp [WEST]  = goto_west;
-		end
-		else if(SW_LOC == NORTH) begin 
-			destport_tmp [SOUTH] = goto_south ;
-			destport_tmp [EAST]  = goto_east;
-			destport_tmp [WEST]  = goto_west;
-		end
-		else if(SW_LOC == WEST)begin 
-			destport_tmp [NORTH] = goto_north ;
-			destport_tmp [SOUTH] = goto_south;
-			destport_tmp [EAST ] = goto_east;					
-		end
-		else if(SW_LOC == EAST) begin 
-			destport_tmp [NORTH] = goto_north;
-			destport_tmp [SOUTH] = goto_south;
-			destport_tmp [WEST ] = goto_west;					
-		end
-		else if(SW_LOC == LOCAL || SW_LOC > SOUTH) begin
-			destport_tmp [NORTH] = goto_north;
-			destport_tmp [SOUTH] = goto_south;
-			destport_tmp [EAST]  = goto_east;
-			destport_tmp [WEST]  = goto_west;
-		end							
-	end
-			
-	localparam MSB_DSTP = (DSTPw-1 < SOUTH)? DSTPw-1: SOUTH;
-			
-	assign destport [MSB_DSTP : 0] =destport_tmp;
-	for(i=1;i<NL;i++) begin :other_local
-		assign destport[MSB_DSTP+i]=goto_local[i];			
-	end		
-		
-		
-	endgenerate	
-		
+    
+    import pronoc_pkg::*;
+    input   [RAw-1 : 0]  current_r_addr;
+    input   [DAw-1 : 0]  dest_e_addr;
+    output  [DSTPw-1 : 0]  destport;
+    localparam Pw = log2(MAX_P_FMESH);
+    
+    localparam
+        RXw = log2(NX),
+        RYw = log2(NY);
+    wire   [RXw-1 : 0]  current_rx;
+    wire   [RYw-1 : 0]  current_ry;   
+    //mask gen. x_plus: all rows larger than current router x address are asserted.
+    wire [NX-1 : 0] x_plus,x_minus;
+    //mask generation. Only the corresponding bits to destination located in current column are asserted in each mask     
+    wire [NE-1 : 0] y_plus,y_min;
+    //Only one-bit is asserted for each local_p[i]
+    wire [NE-1 : 0] local_p [MAX_P_FMESH-1 : 0];
+    regular_topo_router_addr_t current_router_addr_struct;
+    assign current_router_addr_struct = regular_topo_router_addr_t'(current_r_addr);
+    assign current_rx = current_router_addr_struct.x;
+    assign current_ry = current_router_addr_struct.y;
+    
+    wire [NX-1 : 0] row_has_any_dest;
+    wire [NE-1 : 0] dest_mcast_all_endp;
+    
+    mcast_dest_list_decode decode (
+        .dest_e_addr(dest_e_addr),
+        .dest_o(dest_mcast_all_endp),
+        .row_has_any_dest(row_has_any_dest),
+        .is_unicast()
+    );
+    
+    genvar i,j;
+    generate
+    for(i=0; i< NX; i=i+1) begin : X_
+        assign x_plus[i]  = (current_rx > i);
+        /* verilator lint_off UNSIGNED */
+        assign x_minus[i] = (current_rx < i);
+        /* verilator lint_on UNSIGNED */
+    end
+    //get all endp addresses located in the same x
+    for(i=0; i< NE; i=i+1) begin : endpoints
+        //Endpoint decoded address
+        localparam 
+            ADR = fmesh_endp_addr(i),            
+            XX = ADR [NXw -1 : 0],
+            YY = ADR [NXw+NYw-1 : NXw], 
+            PP = ADR [NXw+NYw+Pw-1 : NXw+NYw];             
+        /* verilator lint_off CMPCONST */
+        assign y_plus[i]  = (current_rx    ==    XX) && (current_ry >  YY);
+        /* verilator lint_on CMPCONST */
+        /* verilator lint_off UNSIGNED */
+        assign y_min[i]   = (current_rx    ==    XX) && (current_ry <  YY);
+        /* verilator lint_on UNSIGNED */
+        for(j=0;j<MAX_P_FMESH;j++)begin : lp
+            assign local_p[j][i] = (current_rx    ==    XX) && (current_ry == YY) && (PP == j);
+        end        
+    end//for ne
+    wire [MAX_P_FMESH-1 : 0] goto_local;
+    for(i=0; i<MAX_P_FMESH ; i=i+1) begin : endps
+        assign goto_local[i] = |(local_p[i] & dest_mcast_all_endp);// will be synthesized as single bit assign
+    end//for    
+    
+    wire goto_north = (|(y_plus  & dest_mcast_all_endp)) | goto_local[NORTH];
+    wire goto_south = (|(y_min   & dest_mcast_all_endp)) | goto_local[SOUTH];
+    wire goto_east  = (|(x_minus & row_has_any_dest))    | goto_local[EAST];
+    wire goto_west  = (|(x_plus  & row_has_any_dest))    | goto_local[WEST];
+    
+    reg [4 : 0] destport_tmp;
+    always_comb begin 
+        destport_tmp = {DSTPw{1'b0}};
+        destport_tmp[LOCAL]=goto_local[LOCAL];                
+        if     (SW_LOC == SOUTH)begin 
+            destport_tmp [NORTH] = goto_north ;
+            destport_tmp [EAST]  = goto_east;
+            destport_tmp [WEST]  = goto_west;
+        end
+        else if(SW_LOC == NORTH) begin 
+            destport_tmp [SOUTH] = goto_south ;
+            destport_tmp [EAST]  = goto_east;
+            destport_tmp [WEST]  = goto_west;
+        end
+        else if(SW_LOC == WEST)begin 
+            destport_tmp [NORTH] = goto_north ;
+            destport_tmp [SOUTH] = goto_south;
+            destport_tmp [EAST ] = goto_east;                    
+        end
+        else if(SW_LOC == EAST) begin 
+            destport_tmp [NORTH] = goto_north;
+            destport_tmp [SOUTH] = goto_south;
+            destport_tmp [WEST ] = goto_west;                    
+        end
+        else if(SW_LOC == LOCAL || SW_LOC > SOUTH) begin
+            destport_tmp [NORTH] = goto_north;
+            destport_tmp [SOUTH] = goto_south;
+            destport_tmp [EAST]  = goto_east;
+            destport_tmp [WEST]  = goto_west;
+        end                            
+    end
+    localparam MSB_DSTP = (DSTPw-1 < SOUTH)? DSTPw-1: SOUTH;
+    assign destport [MSB_DSTP : 0] =destport_tmp;
+    for(i=1;i<NL;i++) begin :other_local
+        assign destport[MSB_DSTP+i]=goto_local[i];            
+    end        
+    endgenerate    
 endmodule
 
 
-module mcast_dest_list_decode #(
-	parameter NOC_ID=0
-) (
-	dest_e_addr,
-	dest_o,
-	row_has_any_dest,
-	is_unicast
+module mcast_dest_list_decode  (
+    dest_e_addr,
+    dest_o,
+    row_has_any_dest,
+    is_unicast
 );
-	
-	`NOC_CONF
-	
-	input  [DAw-1 :0]  dest_e_addr;
-	output [NE-1 : 0]  dest_o;
-	output [NX-1 : 0] row_has_any_dest;
-	output is_unicast;
-	
-	wire   [MCASTw-1 : 0] mcast_dst_coded;
-	
-	
-	
-	
-		
-	
-	
-	genvar i;
-	generate
-        /* verilator lint_off WIDTH */ 	
-        if(TOPOLOGY == "STAR") begin :star
-		/* verilator lint_on WIDTH */ 		
-		    assign mcast_dst_coded=dest_e_addr;
-		end else begin :no_star
-		    assign {row_has_any_dest,mcast_dst_coded}=dest_e_addr;
-		end
-	/* verilator lint_off WIDTH */ 	
-	if(CAST_TYPE == "MULTICAST_FULL") begin : full
-	/* verilator lint_on WIDTH */ 
-		assign dest_o = mcast_dst_coded;
-		assign is_unicast = 1'b0;
-	/* verilator lint_off WIDTH */ 	
-	end else if (CAST_TYPE == "MULTICAST_PARTIAL") begin : partial
-	/* verilator lint_on WIDTH */ 
-		wire not_in_cast_list ;
-		wire [EAw-1 : 0] unicast_code;
-		assign {unicast_code,not_in_cast_list} = mcast_dst_coded  [EAw : 0];
-		wire [NE-1 : 0]  dest_o_multi;
-		reg  [NE-1 : 0]  dest_o_uni;
-		wire [NEw-1 : 0] unicast_id;
-		assign is_unicast = not_in_cast_list;
-		
-		endp_addr_decoder  #(
-			.TOPOLOGY (TOPOLOGY),
-			.T1(T1),
-			.T2(T2),
-			.T3(T3),
-			.EAw(EAw),
-			.NE(NE)
-			)
-			decoder
-			(
-				.code(unicast_code),
-				.id(unicast_id)				
-			);    		
-		
-		always @(*)begin 
-			dest_o_uni = {NE{1'b0}};
-			dest_o_uni[unicast_id]=1'b1;
-		end
-		
-		for(i=0; i< NE; i=i+1) begin : endpoints
-			localparam MCAST_ID = endp_id_to_mcast_id(i);
-			assign dest_o_multi [i] = (MCAST_ENDP_LIST[i]==1'b1)? mcast_dst_coded[MCAST_ID+1] : 1'b0;				
-		end
-		
-		assign dest_o = (not_in_cast_list)? dest_o_uni : dest_o_multi;
-	/* verilator lint_off WIDTH */ 	
-	end else if (CAST_TYPE == "BROADCAST_FULL") begin : bcast_full
-	/* verilator lint_on WIDTH */ 
-		wire not_broad_casted;
-		wire [EAw-1 : 0] unicast_code;
-		assign {unicast_code,not_broad_casted} = mcast_dst_coded;
-		assign is_unicast =not_broad_casted;
-		wire [NE-1 : 0]  dest_o_multi;
-		reg  [NE-1 : 0]  dest_o_uni;
-		wire [NEw-1 : 0] unicast_id;		
-		
-		endp_addr_decoder  #(
-				.TOPOLOGY (TOPOLOGY),
-				.T1(T1),
-				.T2(T2),
-				.T3(T3),
-				.EAw(EAw),
-				.NE(NE)
-			)
-			decoder
-			(
-				.code(unicast_code),
-				.id(unicast_id)				
-			);    		
-		
-		always @(*)begin 
-			dest_o_uni = {NE{1'b0}};
-			dest_o_uni[unicast_id]=1'b1;
-		end
-		
-		assign dest_o = (not_broad_casted)? dest_o_uni : {NE{1'b1}};
-		
-	end else begin //BCAST_PARTIAL
-		wire not_broad_casted;
-		wire [EAw-1 : 0] unicast_code;
-		assign {unicast_code,not_broad_casted} = mcast_dst_coded;
-		assign is_unicast =not_broad_casted;
-		wire [NE-1 : 0]  dest_o_multi;
-		reg  [NE-1 : 0]  dest_o_uni;
-		wire [NEw-1 : 0] unicast_id;
-		
-		endp_addr_decoder  #(
-				.TOPOLOGY (TOPOLOGY),
-				.T1(T1),
-				.T2(T2),
-				.T3(T3),
-				.EAw(EAw),
-				.NE(NE)
-			)
-			decoder
-			(
-				.code(unicast_code),
-				.id(unicast_id)				
-			);    		
-		
-		always @(*)begin 
-			dest_o_uni = {NE{1'b0}};
-			dest_o_uni[unicast_id]=1'b1;
-		end
-				
-		assign dest_o = (not_broad_casted)? dest_o_uni : MCAST_ENDP_LIST;
-		
-		
-		
-	end
-		
-	endgenerate		
-	
+    
+    import pronoc_pkg::*;
+    input  [DAw-1 :0]  dest_e_addr;
+    output [NE-1 : 0]  dest_o;
+    output [NX-1 : 0] row_has_any_dest;
+    output is_unicast;
+    wire   [MCASTw-1 : 0] mcast_dst_coded;
+    reg  [NE-1 : 0]  dest_o_uni;
+    wire [NEw-1 : 0] unicast_id;
+    always_comb begin 
+        dest_o_uni = {NE{1'b0}};
+        dest_o_uni[unicast_id]=1'b1;
+    end
+    
+    genvar i;
+    generate
+    if(IS_STAR) begin :star
+        assign mcast_dst_coded=dest_e_addr;
+    end else begin :no_star
+        assign {row_has_any_dest,mcast_dst_coded}=dest_e_addr;
+    end
+    if(IS_MULTICAST_FULL) begin : full
+        assign dest_o = mcast_dst_coded;
+        assign is_unicast = 1'b0;
+        assign unicast_id= {NEw{1'b0}};
+
+    end else if (IS_MULTICAST_PARTIAL) begin : partial
+        wire not_in_cast_list ;
+        wire [EAw-1 : 0] unicast_code;
+        assign {unicast_code,not_in_cast_list} = mcast_dst_coded  [EAw : 0];
+        wire [NE-1 : 0]  dest_o_multi;
+        assign is_unicast = not_in_cast_list;
+        endp_addr_decoder decoder (
+            .code_in(unicast_code),
+            .id_out(unicast_id)
+        );
+        for(i=0; i< NE; i=i+1) begin : endpoints
+            localparam MCAST_ID = (MCAST_ENDP_LIST[i]==1'b1) ? endp_id_to_mcast_id(i): 0;
+            assign dest_o_multi [i] = (MCAST_ENDP_LIST[i]==1'b1)? mcast_dst_coded[MCAST_ID+1] : 1'b0;
+        end
+        assign dest_o = (not_in_cast_list)? dest_o_uni : dest_o_multi;
+    end else if (IS_BROADCAST_FULL) begin : bcast_full
+        wire not_broad_casted;
+        wire [EAw-1 : 0] unicast_code;
+        assign {unicast_code,not_broad_casted} = mcast_dst_coded;
+        assign is_unicast = not_broad_casted;
+        wire [NE-1 : 0]  dest_o_multi;
+        endp_addr_decoder  decoder (
+            .code_in(unicast_code),
+            .id_out(unicast_id)
+        );
+        assign dest_o = (not_broad_casted)? dest_o_uni : {NE{1'b1}};
+    end else begin //BCAST_PARTIAL
+        wire not_broad_casted;
+        wire [EAw-1 : 0] unicast_code;
+        assign {unicast_code,not_broad_casted} = mcast_dst_coded;
+        assign is_unicast =not_broad_casted;
+        wire [NE-1 : 0]  dest_o_multi;
+        endp_addr_decoder decoder (
+            .code_in(unicast_code),
+            .id_out(unicast_id)
+        );
+        assign dest_o = (not_broad_casted)? dest_o_uni : MCAST_ENDP_LIST;
+    end
+    endgenerate
 endmodule
 
 
-
-
 module multicast_chan_in_process #(
-	parameter NOC_ID=0,
-	parameter SW_LOC=0,    
- 	parameter P=5
-) (
-	endp_port,
-	current_r_addr,
-	chan_in,
-	chan_out,
-	clk
+    parameter SW_LOC=0,
+    parameter P=5
+)(
+    endp_port,
+    current_r_addr,
+    chan_in,
+    chan_out,
+    clk
 );  
-
-	`NOC_CONF
-	
-	input endp_port;
-	input   [RAw-1   :   0]  current_r_addr;
-	input   flit_chanel_t chan_in;
-	input   clk;
-	output  flit_chanel_t chan_out;
-	
-	
-	wire  [MCASTw-1   :   0]  mcast_dst_coded;
-	wire  [NE-1 : 0] dest_mcast_all_endp;
-	wire [NX-1 : 0] row_has_any_dest,row_has_any_dest_in;	
-	wire  [DSTPw-1  :   0] destport,destport_o;	
-	
-	hdr_flit_t hdr_flit;
-	
-	header_flit_info #(
-		.NOC_ID (NOC_ID)
-	) extract (
-		.flit(chan_in.flit),
-		.hdr_flit(hdr_flit),		
-		.data_o()
-	);
-	
-	mcast_dest_list_decode #(
-		.NOC_ID(NOC_ID)
-	) decoder (
-		.dest_e_addr(hdr_flit.dest_e_addr),
-		.dest_o(dest_mcast_all_endp),
-		.row_has_any_dest(row_has_any_dest_in),
-		.is_unicast()
-	);
-	
-	localparam MCASTw_= (MCASTw < DAw ) ? MCASTw : DAw;
-		
-	assign mcast_dst_coded = hdr_flit.dest_e_addr[MCASTw_-1:0];	
-	
-	wire [DAw-1 : 0] dest_e_addr;
-
-	genvar i;
-	generate 
-	if(TOPOLOGY == "MESH") begin : mesh_
-		assign  dest_e_addr = {row_has_any_dest,mcast_dst_coded};
-		if(SW_LOC == LOCAL || SW_LOC > SOUTH) begin :endp
-				
-			wire [NE/NX-1   :   0] endp_mask [NX-1 : 0];		
-			for(i=0; i< NE; i=i+1) begin : endpoints
-				//Endpoint decoded address				
-				localparam 
-					MCAST_ID = endp_id_to_mcast_id(i),
-					YY = ((i/NL) / NX ), 
-					XX = ((i/NL) % NX ), 
-					LL = (i % NL),
-					PP = YY*NL + LL;
-				assign endp_mask [XX] [PP] = dest_mcast_all_endp [i];			
-			end
-				
-			for(i=0;i<NX; i++) begin : X_
-				assign row_has_any_dest[i] =| endp_mask[i];			
-			end	
-			
-			reg   [DSTPw-1  :   0] destport_tmp;
-			always @(*) begin 
-				destport_tmp = destport;
-				if(SELF_LOOP_EN   == "NO") destport_tmp [ SW_LOC ] = 1'b0; 
-			end
-			assign destport_o = destport_tmp;
-			
-		end else begin : no_endp
-			assign  row_has_any_dest = 	 row_has_any_dest_in;
-			assign  destport_o = destport;
-		end
-	end //mesh 	
-	
-	/* verilator lint_off WIDTH */ 
-	else if (TOPOLOGY == "FMESH" ) begin :fmesh_
-	/* verilator lint_on WIDTH */ 
-		
-		assign  dest_e_addr = {row_has_any_dest,mcast_dst_coded};
-		
-		localparam MAX_ENDP_NUM_IN_SAME_ROW = NY * NL + NY + 2;
-		localparam ENDP_NUM_IN_MIDLE_ROW = NY * NL + 2;
-		localparam Pw = log2(MAX_P_FMESH);
-		
-		wire [NX-1 : 0] row_has_any_dest_endp_port;	
-		wire [NY*NL-1   :   0] endp_mask [NX-1 : 0];		
-			
-		for(i=0; i< NE; i=i+1) begin : endpoints
-			//Endpoint decoded address				
-			localparam 
-				ADR = fmesh_addrencode(i),					
-				XX = ADR [NXw -1 : 0],
-				YY = ADR [NXw+NYw-1 : NXw], 
-				PP = ADR [NXw+NYw+Pw-1 : NXw+NYw]; 
-				if(PP == LOCAL || PP > SOUTH) begin 
-					localparam MM = (PP==LOCAL) ? YY*NL : (YY*NL) + PP - SOUTH;
-					assign endp_mask [XX] [MM] = dest_mcast_all_endp [i];
-				end
-		end
-			
-		wire [NX-1 : 0] north_endps;
-		wire [NY-1 : 0] west_endps;
-		wire [NX-1 : 0] south_endps;
-		wire [NY-1 : 0] east_endps;
-		
-		assign {    east_endps,    west_endps ,south_endps ,north_endps}  = dest_mcast_all_endp [NE-1 :   NY*NL*NX];
-			
-				
-		for(i=0;i<NX; i++) begin : X_
-			if(i==0) assign row_has_any_dest_endp_port[i] =(| endp_mask[i]) | ( |west_endps)  | north_endps[i] | south_endps[i];
-			else if (i==NX-1) assign row_has_any_dest_endp_port[i] =(| endp_mask[i]) | ( |east_endps)  | north_endps[i] | south_endps[i];
-			else assign row_has_any_dest_endp_port[i] =(| endp_mask[i]) |  north_endps[i] | south_endps[i];
-		end	
-			
-		reg   [DSTPw-1  :   0] destport_tmp;
-		always @(*) begin 
-			destport_tmp = destport;
-			if(SELF_LOOP_EN   == "NO") destport_tmp [ SW_LOC ] = 1'b0; 
-		end
-			
-		
-		assign  destport_o = (endp_port) ?    destport :  destport_tmp ;
-		assign  row_has_any_dest = (endp_port) ? row_has_any_dest_endp_port : row_has_any_dest_in;
-
-
-    /* verilator lint_off WIDTH */ 
-	end else if (TOPOLOGY == "STAR" ) begin :star_
-	/* verilator lint_on WIDTH */ 
-		assign  destport_o =    destport;
-		assign  dest_e_addr =   mcast_dst_coded;
-	end 
-		
-		
-		multicast_routing
-		#(
-			.NOC_ID(NOC_ID),
-			.P(P) ,
-			.SW_LOC(SW_LOC)		
-		)
-		routing
-		(
-			.current_r_addr(current_r_addr),  //current router  address
-			.dest_e_addr(dest_e_addr),  // destination endpoint address		
-			.destport(destport)		
-		);
-		
-		
-		
-		
-		always @(*) begin 
-			chan_out=chan_in;
-			if(chan_in.flit.hdr_flag == 1'b1) begin
-				chan_out.flit [E_DST_MSB : E_DST_LSB] = dest_e_addr;
-				chan_out.flit [DST_P_MSB : DST_P_LSB] = destport_o;				
-			end
-		end	
-	
-	
-	
-	//synthesis translate_off	
-	if(DEBUG_EN) begin :debg
-		always @(posedge clk) begin 
-			/* verilator lint_off WIDTH */ 
-			if(CAST_TYPE == "MULTICAST_FULL" || CAST_TYPE == "MULTICAST_PARTIAL")
-			/* verilator lint_on WIDTH */ 
-			if(chan_in.flit_wr  == 1'b1 && chan_in.flit.hdr_flag == 1'b1 && mcast_dst_coded == {MCASTw{1'b0}}) begin 
-				$display ("%t: ERROR: A multicast packet is injected to the NoC with zero mcast_dst_coded filed %m ",$time);
-				$finish;
-			end
-			
-			if(chan_in.flit_wr  == 1'b1 && chan_in.flit.hdr_flag == 1'b1 && dest_mcast_all_endp == {NE{1'b0}}) begin 
-				$display ("%t: ERROR: A multicast packet is injected to the NoC without any set destination %m ",$time);
-				$finish;
-			end
-			
-			if(chan_in.flit_wr  == 1'b1 && chan_in.flit.hdr_flag == 1'b1 && destport_o == {DSTPw{1'b0}}) begin 
-				$display ("%t: ERROR: Routing module did not set any destination port for an injected multicast packet %m ",$time);
-				$finish;
-			end
-			
-		end
-	end//debug
-	//synthesis translate_on
-		
-	endgenerate
+    
+    import pronoc_pkg::*;
+    input endp_port;
+    input   [RAw-1 : 0]  current_r_addr;
+    input   flit_chanel_t chan_in;
+    input   clk;
+    output  flit_chanel_t chan_out;
+    
+    wire  [MCASTw-1 : 0]  mcast_dst_coded;
+    wire  [NE-1 : 0] dest_mcast_all_endp;
+    wire  [NX-1 : 0] row_has_any_dest,row_has_any_dest_in;
+    wire  [DSTPw-1 : 0] destport,destport_o;
+    
+    hdr_flit_t hdr_flit;
+    header_flit_info extract (
+        .flit(chan_in.flit),
+        .hdr_flit(hdr_flit),
+        .data_o()
+    );
+
+    mcast_dest_list_decode decoder (
+        .dest_e_addr(hdr_flit.dest_e_addr),
+        .dest_o(dest_mcast_all_endp),
+        .row_has_any_dest(row_has_any_dest_in),
+        .is_unicast()
+    );
+    
+    localparam MCASTw_= (MCASTw < DAw ) ? MCASTw : DAw;
+    assign mcast_dst_coded = hdr_flit.dest_e_addr[MCASTw_-1:0];    
+    wire [DAw-1 : 0] dest_e_addr;
+    logic[DSTPw-1 : 0] destport_tmp;
+    always_comb begin 
+        destport_tmp = destport;
+        if(SELF_LOOP_EN == 0) destport_tmp [ SW_LOC ] = 1'b0; 
+    end
+    genvar i;
+    generate 
+    if(IS_MESH) begin : mesh_
+        assign  dest_e_addr = {row_has_any_dest,mcast_dst_coded};
+        if(SW_LOC == LOCAL || SW_LOC > SOUTH) begin :endp
+            wire [NE/NX-1 : 0] endp_mask [NX-1 : 0];
+            for(i=0; i< NE; i=i+1) begin : endpoints
+                //Endpoint decoded address
+                localparam 
+                    YY = ((i/NL) / NX ), 
+                    XX = ((i/NL) % NX ), 
+                    LL = (i % NL),
+                    PP = YY*NL + LL;
+                assign endp_mask [XX] [PP] = dest_mcast_all_endp [i];
+            end
+            for(i=0;i<NX; i++) begin : X_
+                assign row_has_any_dest[i] =| endp_mask[i];
+            end
+            assign destport_o = destport_tmp;
+        end else begin : no_endp
+            assign  row_has_any_dest =      row_has_any_dest_in;
+            assign  destport_o = destport;
+        end
+    end //mesh     
+    else if ( IS_FMESH ) begin :fmesh_
+        assign  dest_e_addr = {row_has_any_dest,mcast_dst_coded};
+        localparam MAX_ENDP_NUM_IN_SAME_ROW = NY * NL + NY + 2;
+        localparam ENDP_NUM_IN_MIDLE_ROW = NY * NL + 2;
+        localparam Pw = log2(MAX_P_FMESH);
+        wire [NX-1 : 0] row_has_any_dest_endp_port;
+        wire [NY*NL-1 : 0] endp_mask [NX-1 : 0];
+        for(i=0; i< NE; i=i+1) begin : _E
+            //Endpoint decoded address
+            localparam 
+                ADR = fmesh_endp_addr(i),
+                XX = ADR [NXw -1 : 0],
+                YY = ADR [NXw+NYw-1 : NXw], 
+                PP = ADR [NXw+NYw+Pw-1 : NXw+NYw]; 
+            if(PP == LOCAL || PP > SOUTH) begin 
+                localparam MM = (PP==LOCAL) ? YY*NL : (YY*NL) + PP - SOUTH;
+                assign endp_mask [XX] [MM] = dest_mcast_all_endp [i];
+            end
+        end
+        wire [NX-1 : 0] north_endps;
+        wire [NY-1 : 0] west_endps;
+        wire [NX-1 : 0] south_endps;
+        wire [NY-1 : 0] east_endps;
+        assign { east_endps, west_endps ,south_endps ,north_endps}  = dest_mcast_all_endp [NE-1 : NY*NL*NX];
+        
+        for(i=0;i<NX; i++) begin : X_
+            if(i==0) assign row_has_any_dest_endp_port[i] =(| endp_mask[i]) | ( |west_endps)  | north_endps[i] | south_endps[i];
+            else if (i==NX-1) assign row_has_any_dest_endp_port[i] =(| endp_mask[i]) | ( |east_endps)  | north_endps[i] | south_endps[i];
+            else assign row_has_any_dest_endp_port[i] =(| endp_mask[i]) |  north_endps[i] | south_endps[i];
+        end
+        assign  destport_o = (endp_port) ?    destport : destport_tmp ;
+        assign  row_has_any_dest = (endp_port) ? row_has_any_dest_endp_port : row_has_any_dest_in;
+    end else if (IS_STAR ) begin :star_
+        assign  destport_o =    destport;
+        assign  dest_e_addr =   mcast_dst_coded;
+    end   
+    
+    multicast_routing
+    #(
+        .P(P) ,
+        .SW_LOC(SW_LOC)
+    )routing(
+        .current_r_addr(current_r_addr),  //current router  address
+        .dest_e_addr(dest_e_addr),  // destination endpoint address
+        .destport(destport)
+    );  
+    always_comb begin 
+        chan_out=chan_in;
+        if(chan_in.flit.hdr_flag == 1'b1) begin
+            chan_out.flit [E_DST_MSB : E_DST_LSB] = dest_e_addr;
+            chan_out.flit [DST_P_MSB : DST_P_LSB] = destport_o;
+        end
+    end
+    `ifdef SIMULATION
+    if(DEBUG_EN) begin :debg
+        always @(posedge clk) begin 
+            if(IS_MULTICAST_FULL | IS_MULTICAST_PARTIAL)
+            if(chan_in.flit_wr  == 1'b1 && chan_in.flit.hdr_flag == 1'b1 && mcast_dst_coded == {MCASTw{1'b0}}) begin 
+                $display ("%t: ERROR: A multicast packet is injected to the NoC with zero mcast_dst_coded filed %m ",$time);
+                $finish;
+            end
+            
+            if(chan_in.flit_wr  == 1'b1 && chan_in.flit.hdr_flag == 1'b1 && dest_mcast_all_endp == {NE{1'b0}}) begin 
+                $display ("%t: ERROR: A multicast packet is injected to the NoC without any set destination %m ",$time);
+                $finish;
+            end
+            if(chan_in.flit_wr  == 1'b1 && chan_in.flit.hdr_flag == 1'b1 && destport_o == {DSTPw{1'b0}}) begin 
+                $display ("%t: ERROR: Routing module did not set any destination port for an injected multicast packet %m ",$time);
+                $finish;
+            end
+        end
+    end//debug
+    `endif
+    endgenerate
 endmodule
 
 
-
-module multicast_dst_sel # (
-	parameter NOC_ID=0
-)(
-	destport_in,
-	destport_out    
+module multicast_dst_sel  (
+    destport_in,
+    destport_out
 );
-
-	`NOC_CONF
-	
-	input  [DSTPw-1 : 0] destport_in;
-	output [DSTPw-1 : 0] destport_out; 
-
-
-	wire  [DSTPw-1 : 0] arb_in, arb_out;
+    import pronoc_pkg::*;
+    input  [DSTPw-1 : 0] destport_in;
+    output [DSTPw-1 : 0] destport_out;
+    wire  [DSTPw-1 : 0] arb_in, arb_out;
     
-	function integer mesh_tori_pririty_order;
-		input integer x;
-		begin
-			case(x)
-				0 : mesh_tori_pririty_order = EAST;
-				1 : mesh_tori_pririty_order = WEST;
-				2 : mesh_tori_pririty_order = NORTH;
-				3 : mesh_tori_pririty_order = SOUTH;
-				4 : mesh_tori_pririty_order = LOCAL;	
-				default : mesh_tori_pririty_order =x;
-			endcase
-		end
-	endfunction // pririty_order
-	
-	function integer ring_lin_pririty_order;
-		input integer x;
-		begin
-			case(x)
-				0 : ring_lin_pririty_order = FORWARD;
-				1 : ring_lin_pririty_order = BACKWARD;
-				2 : ring_lin_pririty_order = LOCAL;				
-				default : ring_lin_pririty_order =x;
-			endcase
-		end
-	endfunction // pririty_order
-	
-	
-	
-    	
-    	
-	genvar i;
-	generate 
-		for (i=0; i<DSTPw;i++) begin : lp
-			localparam PR = 
-				/* verilator lint_off WIDTH */ 
-				(TOPOLOGY == "MESH" || TOPOLOGY == "TORUS" || TOPOLOGY == "FMESH"  )?  mesh_tori_pririty_order(i):
-				(TOPOLOGY == "RING" || TOPOLOGY == "LINE") ? ring_lin_pririty_order(i) : i;
-				/* verilator lint_on WIDTH */								
-			assign arb_in[i] = destport_in[PR];
-			assign destport_out [PR] = arb_out[i];
-		end
-	endgenerate
-      
+    function integer three_dim_topo_priority_order;
+    input integer x;
+    begin
+        case(x)
+            0 : three_dim_topo_priority_order = DOWN;
+            1 : three_dim_topo_priority_order = UP;
+            2 : three_dim_topo_priority_order = EAST;
+            3 : three_dim_topo_priority_order = WEST;
+            4 : three_dim_topo_priority_order = NORTH;
+            5 : three_dim_topo_priority_order = SOUTH;
+            6 : three_dim_topo_priority_order = LOCAL;    
+            default : three_dim_topo_priority_order =x;
+        endcase
+    end
+    endfunction // pririty_order
+
+    function integer two_dim_topo_priority_order;
+    input integer x;
+    begin
+        case(x)
+            0 : two_dim_topo_priority_order = EAST;
+            1 : two_dim_topo_priority_order = WEST;
+            2 : two_dim_topo_priority_order = NORTH;
+            3 : two_dim_topo_priority_order = SOUTH;
+            4 : two_dim_topo_priority_order = LOCAL;    
+            default : two_dim_topo_priority_order =x;
+        endcase
+    end
+    endfunction // pririty_order
     
-	fixed_priority_arbiter #(
-			.ARBITER_WIDTH     (DSTPw), 
-			.HIGH_PRORITY_BIT  ("LSB")
-		) fixed_priority_arbiter (
-			.request           (arb_in), 
-			.grant             (arb_out), 
-			.any_grant         (   )
-		);
+    function integer one_dim_topo_priority_order;
+    input integer x;
+    begin
+        case(x)
+            0 : one_dim_topo_priority_order = FORWARD;
+            1 : one_dim_topo_priority_order = BACKWARD;
+            2 : one_dim_topo_priority_order = LOCAL;                
+            default : one_dim_topo_priority_order =x;
+        endcase
+    end
+    endfunction // pririty_order
     
-       
-   
+    genvar i;
+    generate 
+    for (i=0; i<DSTPw;i++) begin : lp
+        localparam PR = 
+            ( IS_3D_TOPO ) ?  three_dim_topo_priority_order(i):
+            ( IS_2D_TOPO ) ?  two_dim_topo_priority_order(i):
+            ( IS_1D_TOPO ) ? one_dim_topo_priority_order(i) : i;
+        assign arb_in[i] = destport_in[PR];
+        assign destport_out [PR] = arb_out[i];
+    end
+    endgenerate
     
+    fixed_priority_arbiter #(
+        .ARBITER_WIDTH     (DSTPw), 
+        .HIGH_PRORITY_BIT  ("LSB")
+    ) fixed_priority_arbiter (
+        .request           (arb_in), 
+        .grant             (arb_out), 
+        .any_grant         (   )
+    );
 endmodule
-
-
diff --git a/mpsoc/rtl/src_noc/noc_filelist.f b/mpsoc/rtl/src_noc/noc_filelist.f
index a7524df..d2a298c 100644
--- a/mpsoc/rtl/src_noc/noc_filelist.f
+++ b/mpsoc/rtl/src_noc/noc_filelist.f
@@ -3,37 +3,38 @@
 ./pronoc_pkg.sv
 ./../main_comp.v
 ./../arbiter.v
-./class_table.v
+./ovc_list.sv
 ./ss_allocator.sv
-./route_torus.v
+./route_torus.sv
 ./header_flit.sv
 ./noc_top.sv
 ./fattree_noc_top.sv
-./fattree_route.v
+./fattree_route.sv
 ./comb_nonspec.sv
 ./inout_ports.sv
-./wrra.v
+./wrra.sv
 ./input_ports.sv
 ./tree_noc_top.sv
-./tree_route.v
-./comb-spec1.v
+./tree_route.sv
+./comb-spec1.sv
 ./combined_vc_sw_alloc.sv
-./mesh_torus_routting.v
-./comb_spec2.v
-./route_mesh.v
+./mesh_torus_routting.sv
+./comb_spec2.sv
+./route_mesh.sv
 ./router_bypass.sv
 ./traffic_gen_top.sv
-./congestion_analyzer.v
+./congestion_analyzer.sv
 ./output_ports.sv
-./routing.v
+./routing.sv
 ./router_two_stage.sv
-./crossbar.v
+./crossbar.sv
 ./flit_buffer.sv
 ./mesh_torus.sv
-./debug.v
+./debug.sv
 ./router_top.sv
 ./mesh_torus_noc_top.sv
 ./star_noc.sv
 ./fmesh.sv
 ./packet_injector.sv
 ./multicast.sv
+./mesh_3d_top.sv
diff --git a/mpsoc/rtl/src_noc/noc_localparam.v b/mpsoc/rtl/src_noc/noc_localparam.v
index 73208db..dde11be 100644
--- a/mpsoc/rtl/src_noc/noc_localparam.v
+++ b/mpsoc/rtl/src_noc/noc_localparam.v
@@ -1,80 +1,200 @@
 
 /**************************************************************************
-**	WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT ARE LIKELY TO BE
-**	OVERWRITTEN AND LOST. Rename this file if you wish to do any modification.
+**    WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT ARE LIKELY TO BE
+**    OVERWRITTEN AND LOST. Rename this file if you wish to do any modification.
 ****************************************************************************/
 
 
 /**********************************************************************
-**	File: noc_localparam.v
+**    File: noc_localparam.v
 **    
-**	Copyright (C) 2014-2021  Alireza Monemi
+**    Copyright (C) 2014-2022  Alireza Monemi
 **    
-**	This file is part of ProNoC 2.1.0 
+**    This file is part of ProNoC 2.2.0 
 **
-**	ProNoC ( stands for Prototype Network-on-chip)  is free software: 
-**	you can redistribute it and/or modify it under the terms of the GNU
-**	Lesser General Public License as published by the Free Software Foundation,
-**	either version 2 of the License, or (at your option) any later version.
+**    ProNoC ( stands for Prototype Network-on-chip)  is free software: 
+**    you can redistribute it and/or modify it under the terms of the GNU
+**    Lesser General Public License as published by the Free Software Foundation,
+**    either version 2 of the License, or (at your option) any later version.
 **
-** 	ProNoC is distributed in the hope that it will be useful, but WITHOUT
-** 	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
-** 	or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
-** 	Public License for more details.
+**     ProNoC is distributed in the hope that it will be useful, but WITHOUT
+**     ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+**     or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
+**     Public License for more details.
 **
-** 	You should have received a copy of the GNU Lesser General Public
-** 	License along with ProNoC. If not, see <http:**www.gnu.org/licenses/>.
+**     You should have received a copy of the GNU Lesser General Public
+**     License along with ProNoC. If not, see <http:**www.gnu.org/licenses/>.
 ******************************************************************************/ 
 
-	
-	`ifdef   NOC_LOCAL_PARAM 
+    `ifdef   NOC_LOCAL_PARAM 
  
- 
-	
 
-//NoC localparams
+    
+
+//NoC parameters
+	localparam NOC_ID=0;
+            //NOC_ID : Unique identifier for the NoC. Will be modified by phy_noc_gen.pl script
+
 	localparam TOPOLOGY="MESH";
+            //TOPOLOGY : Specifies the NoC topology. 
+            //    Options include "MESH","FMESH","TORUS","RING","LINE","FATTREE","TREE","STAR","CUSTOM"
+
 	localparam T1=4;
+            //T1 : Number of NoC routers in row (X dimension)
+
 	localparam T2=4;
+            //T2 : Number of NoC routers in column (Y dimension)
+
 	localparam T3=2;
+            //T3 : Number of endpoints per router. In "MESH" topology, each router
+            //        can have up to 4 endpoint processing tile.
+
 	localparam V=2;
+            //V : Number of Virtual chanel per each router port
+
 	localparam B=4;
+            //B : Buffer queue size per VC in flits
+
 	localparam LB=7;
+            //LB : Buffer width for local router ports connected to endpoints. 
+            //    May differ from B, which is for neighboring router ports. 
+            //    Applicable to MESH, FMESH, TORUS, LINE, and RING topologies. 
+            //    In FMESH, LB does not affect extra endpoints on edge routers.
+
 	localparam Fpay=32;
-	localparam ROUTE_NAME="XY";
+            //Fpay : The packet payload width in bits
+
+	localparam ROUTE_NAME="DOR";
+            //ROUTE_NAME : Select the routing algorithm. Options are: 
+            //    - XY: Deterministic routing (Dimension-Order Routing, DoR).
+            //    - WEST_FIRST, NORTH_LAST, NEGATIVE_FIRST, ODD_EVEN:  Partially adaptive routing algorithms based on turn model restrictions.
+            //    - FULL_ADPT:  Fully adaptive routing based on Duato's algorithm; requires at least two virtual channels (VCs) per port.
+            //    options are "DOR","WEST_FIRST","NORTH_LAST","NEGETIVE_FIRST","ODD_EVEN","FULL_ADPT"
+
+	localparam ROUTE_MODE="LOOKAHEAD";
+            //ROUTE_MODE : Select the routing algorithm mode:
+            //    -Conventional: 
+            //        The destination output port is computed 
+            //        in the same cycle, prior to VC/SW allocation.
+            //    -Lookahead: 
+            //        The routing decision is performed one router
+            //        ahead, in parallel with VC/SW allocation.
+
 	localparam PCK_TYPE="MULTI_FLIT";
+            //PCK_TYPE : Packet type.
+            //    - SINGLE_FLIT: All packets are single-flit sized.
+            //    - MULTI_FLIT: Packets can be single-flit, two-flit, or multi-flit sized:
+            //        a) Single-flit: Head and tail flags set on one flit.
+            //        b) Two-flit: Separate header and tail flits.
+            //        c) Multi-flit: Header, one or more body flits, and a tail flit.
+
 	localparam MIN_PCK_SIZE=2;
+            //MIN_PCK_SIZE : Minimum packet size in flits.
+            //    - For atomic VC reallocation, any value ≥1 is valid.
+            //    - For non-atomic VC reallocation, this value defines buffer behavior.
+            //    Note: Setting a value smaller than received packet size may cause crashes.
+
 	localparam BYTE_EN=0;
+            //BYTE_EN : 0 - Disable, 1 - Enable. 
+            //    Adds a Byte Enable (BE) field to the header flit, indicating the location of 
+            //    the last valid byte in the tail flit. This is required when the data unit being 
+            //    sent is smaller than the Fpay value.
+
 	localparam CAST_TYPE="UNICAST";
+            //CAST_TYPE : Specifies NoC communication type.
+            //    - UNICAST: A packet targets a single destination.
+            //    - MULTICAST/BROADCAST: A single packet targets multiple/all destinations.
+            //    Options: FULL (all nodes) or PARTIAL (defined by MCAST_ENDP_LIST).
+            //    Select one of "UNICAST","MULTICAST_PARTIAL","MULTICAST_FULL","BROADCAST_PARTIAL","BROADCAST_FULL"
+
 	localparam MCAST_ENDP_LIST=32'hf;
-	localparam SSA_EN="NO";
+	localparam SSA_EN=0;
+            //SSA_EN : Enable single cycle latency on packets traversing in the same direction using 
+            //    static straight allocator (SSA)
+
 	localparam SMART_MAX=0;
+            //SMART_MAX : Maximum number of routers a packet can bypass in a straight direction
+            //    in a single cycle (0 = no bypass)
+
 	localparam CONGESTION_INDEX=3;
+            //CONGESTION_INDEX : Congestion index determines how congestion information is collected 
+            //    from neighboring routers. Please refer to the usere manual for more information
+
 	localparam ESCAP_VC_MASK=2'b01;
+            //ESCAP_VC_MASK : Select the escap VC for fully adaptive routing.
+
 	localparam VC_REALLOCATION_TYPE="NONATOMIC";
+            //VC_REALLOCATION_TYPE : VC reallocation policy.
+            //    - ATOMIC: Only empty VCs can be reallocated.
+            //    - NONATOMIC: Non-empty VCs with completed packets can accept new packets.
+
 	localparam COMBINATION_TYPE="COMB_NONSPEC";
+            //COMBINATION_TYPE : Specifies the joint VC/Switch allocator type as either speculative or non-speculative. 
+            //Options are: 
+            //    - SPEC: Speculative allocation.
+            //    - NONSPEC: Non-speculative allocation.
+
 	localparam MUX_TYPE="BINARY";
+            //MUX_TYPE : Crossbar multiplexer type
+
 	localparam C=0;
 	localparam DEBUG_EN=0;
+            //DEBUG_EN : Add extra Verilog code for debugging NoC for simulation
+
 	localparam ADD_PIPREG_AFTER_CROSSBAR=1'b0;
+            //ADD_PIPREG_AFTER_CROSSBAR : If is enabled it adds a pipeline register at the output port of the router.
+
 	localparam FIRST_ARBITER_EXT_P_EN=1;
+            //FIRST_ARBITER_EXT_P_EN : Enables switch allocator's input priority registers 
+            //    only when a request gets grants from both input and output arbiters.
+
 	localparam SWA_ARBITER_TYPE="RRA";
+            //SWA_ARBITER_TYPE : Switch allocator arbitration type.
+            //    - RRA: Round Robin Arbiter (local fairness only).
+            //    - WRRA: Weighted Round Robin Arbiter (global fairness based on contention).
+            //
+
 	localparam WEIGHTw=4;
-	localparam SELF_LOOP_EN="NO";
+            //WEIGHTw : Maximum weight width
+
+	localparam SELF_LOOP_EN=0;
+            //SELF_LOOP_EN : Allows a router input port to send packets to its own output port, 
+            //    enabling self-communication for tiles.
+
+	localparam HETERO_VC=0;
+            //HETERO_VC : Configures the VC (Virtual Channel) distribution across routers and ports in the NoC.
+            //    0 : Uniform VC distribution. All routers in the NoC have an equal number of VCs.
+            //    1 : Router-specific VC distribution. All ports in a specific router have the same number of VCs, 
+            //    but different routers in the NoC can have different numbers of VCs.
+            //    2 : Fully heterogeneous VC distribution. Each port in any router can have a unique number of VCs.
+
+	localparam MAX_ROUTER=1;
+	localparam MAX_PORT=1;
+	localparam int VC_CONFIG_TABLE [MAX_ROUTER][MAX_PORT]='{'{0}};
+            //int VC_CONFIG_TABLE [MAX_ROUTER][MAX_PORT] : Defines how a heterogeneous number of VCs are distributed in the NoC.
+            //    - HETERO_VC= 0: Uniform VC configuration. All routers and ports have 
+            //        the same number of VCs, and this parameter is not used.
+            //    - HETERO_VC= 1,2 : Specifies the VC count in a 2D parameter array, where:
+            //        * The first dimension represents the router ID.
+            //        * The second dimension represents the port number.
+            //    - For HETERO_VC = 1: All ports within a router have the same number of VCs, 
+            //        so only the first element of each row is considered valid.
+            //    - For HETERO_VC = 2: Each port in every router can have a unique VC count.
+
 	localparam AVC_ATOMIC_EN=0;
+            //AVC_ATOMIC_EN : AVC_ATOMIC_EN
+
 	localparam CLASS_SETTING={V{1'b1}};
  	localparam  CVw=(C==0)? V : C * V;
-  
-	
-	
-	//simulation localparam	
-	//localparam MAX_RATIO = 1000;
-	localparam MAX_PCK_NUM = 1000000000;
-	localparam MAX_PCK_SIZ = 16383; 
-	localparam MAX_SIM_CLKs=  1000000000;
-	localparam TIMSTMP_FIFO_NUM = 16;	
-	
-		
+
+    
+    //simulation parameter
+    //localparam MAX_RATIO = 1000;
+    localparam MAX_PCK_NUM = 1000000000;
+    localparam MAX_PCK_SIZ = 16383;
+    localparam MAX_SIM_CLKs=  1000000000;
+    localparam TIMSTMP_FIFO_NUM = 16;
+    
 
  
  `endif
diff --git a/mpsoc/rtl/src_noc/noc_top.sv b/mpsoc/rtl/src_noc/noc_top.sv
index 7b85ca1..a162d2e 100644
--- a/mpsoc/rtl/src_noc/noc_top.sv
+++ b/mpsoc/rtl/src_noc/noc_top.sv
@@ -20,161 +20,122 @@
 **     License along with ProNoC. If not, see <http:**www.gnu.org/licenses/>.
 **
 **
-**    Description: 
-**    the NoC top module. 
+**     Description:
+**     This is the top-level NoC (Network-on-Chip) module. It generates various network topologies, 
+**     including mesh, torus, ring, line, fattree, bintree or a user-defined custom topology,
+**     by interconnecting routers.
 **
 **************************************************************/
 
-
-
-module  noc_top #(	
-	parameter NOC_ID=0
-) (
-	reset,
-	clk,    
-	chan_in_all,
-	chan_out_all,
-	router_event
+module  noc_top (
+    reset,
+    clk,
+    chan_in_all,
+    chan_out_all,
+    router_event
 );
-  
-  	`NOC_CONF
-  	
-	input   clk,reset;
-	//Endpoints ports 
-	input   smartflit_chanel_t chan_in_all  [NE-1 : 0];
-	output  smartflit_chanel_t chan_out_all [NE-1 : 0];
-	//Events
-	output  router_event_t  router_event [NR-1 : 0][MAX_P-1 : 0];
- 
-   
-
-
-	generate 
-	/* verilator lint_off WIDTH */
-	if (TOPOLOGY ==    "MESH" || TOPOLOGY ==    "FMESH" || TOPOLOGY ==  "TORUS" || TOPOLOGY == "RING" || TOPOLOGY == "LINE") begin : tori_noc 
-	/* verilator lint_on WIDTH */
-		mesh_torus_noc_top #(
-			.NOC_ID(NOC_ID)
-		) noc_top (
-			.reset         (reset        ), 
-			.clk           (clk          ), 
-			.chan_in_all   (chan_in_all  ), 
-			.chan_out_all  (chan_out_all ),
-			.router_event  (router_event )
-		);	
     
-    end else if (TOPOLOGY == "FATTREE") begin : fat_
+    import pronoc_pkg::*;
+    
+    input   clk,reset;
+    //Endpoints ports 
+    input   smartflit_chanel_t chan_in_all  [NE-1 : 0];
+    output  smartflit_chanel_t chan_out_all [NE-1 : 0];
+    //Events
+    output  router_event_t  router_event [NR-1 : 0][MAX_P-1 : 0];
     
-        fattree_noc_top #(
-			.NOC_ID(NOC_ID)
-		) noc_top (
-        	.reset         (reset        ), 
-        	.clk           (clk          ), 
-        	.chan_in_all   (chan_in_all  ), 
-        	.chan_out_all  (chan_out_all ),
-        	.router_event  (router_event )
+    generate 
+    if ((IS_REGULAR_TOPO | IS_FMESH) & ~IS_MESH_3D) begin : regular_ 
+        regular_topo_noc_top noc_top (
+            .reset         (reset        ), 
+            .clk           (clk          ), 
+            .chan_in_all   (chan_in_all  ), 
+            .chan_out_all  (chan_out_all ),
+            .router_event  (router_event )
+        );
+    end else if (IS_MESH_3D) begin : M3D_
+        mesh_3d_noc_top noc_top (
+            .reset         (reset        ), 
+            .clk           (clk          ), 
+            .chan_in_all   (chan_in_all  ), 
+            .chan_out_all  (chan_out_all ),
+            .router_event  (router_event )
+        );
+    end else if (IS_FATTREE) begin : fat_
+        fattree_noc_top noc_top (
+            .reset         (reset        ), 
+            .clk           (clk          ), 
+            .chan_in_all   (chan_in_all  ), 
+            .chan_out_all  (chan_out_all ),
+            .router_event  (router_event )
         );
-        
-        
-    end else if (TOPOLOGY == "TREE") begin : tree_
-        tree_noc_top  #(
-			.NOC_ID(NOC_ID)
-		) noc_top ( 
-        	.reset         (reset        ), 
-        	.clk           (clk          ), 
-        	.chan_in_all   (chan_in_all  ), 
-        	.chan_out_all  (chan_out_all ),
-        	.router_event  (router_event )
+    end else if (IS_TREE) begin : tree_
+        tree_noc_top  noc_top ( 
+            .reset         (reset        ), 
+            .clk           (clk          ), 
+            .chan_in_all   (chan_in_all  ), 
+            .chan_out_all  (chan_out_all ),
+            .router_event  (router_event )
+        );
+    end else if (IS_STAR) begin : star_
+        star_noc_top  noc_top ( 
+                .reset         (reset        ), 
+                .clk           (clk          ), 
+                .chan_in_all   (chan_in_all  ), 
+                .chan_out_all  (chan_out_all ),
+                .router_event  (router_event )
+        );
+    end else if (IS_MULTI_MESH) begin : multimesh_
+        multi_mesh noc_top ( 
+                .reset         (reset        ), 
+                .clk           (clk          ), 
+                .chan_in_all   (chan_in_all  ), 
+                .chan_out_all  (chan_out_all ),
+                .router_event  (router_event )
         );
-    end else if (TOPOLOGY == "STAR") begin : star_
-    	star_noc_top  #(
-			.NOC_ID(NOC_ID)
-		) noc_top ( 
-    			.reset         (reset        ), 
-    			.clk           (clk          ), 
-    			.chan_in_all   (chan_in_all  ), 
-    			.chan_out_all  (chan_out_all ),
-    			.router_event  (router_event )
-    	);
-    	
     end else begin :custom_
 
-	custom_noc_top #(
-			.NOC_ID(NOC_ID)
-		) noc_top ( 
-			.reset         (reset        ), 
-			.clk           (clk          ), 
-			.chan_in_all   (chan_in_all  ), 
-			.chan_out_all  (chan_out_all ),
-			.router_event  (router_event )
-		);
-
-    end     
+        custom_noc_top noc_top ( 
+            .reset         (reset        ), 
+            .clk           (clk          ), 
+            .chan_in_all   (chan_in_all  ), 
+            .chan_out_all  (chan_out_all ),
+            .router_event  (router_event )
+        );
+    end
     endgenerate
 endmodule
 
-
-
-
-
-
-/**********************************
-The noc top module that can be called in Verilog module. 
-
-***********************************/
-
-module  noc_top_v  #(
-	parameter NOC_ID=0
-)(
-    flit_out_all,
-    flit_out_wr_all,
-    credit_in_all,
-    flit_in_all,
-    flit_in_wr_all,  
-    credit_out_all,
+/**************************
+ * noc_top_v:
+ * This module instantiates noc_top and
+ * serves as the top module in Verilator simulation.
+ * It resolves the Verilator error caused by
+ * noc_top being used in another module,
+ * preventing it from being defined as the top module.
+ **************************/ 
+module  noc_top_v  (
     reset,
-    clk
- );
-
-	`NOC_CONF
-	
-	input   clk,reset;
-	output [NEFw-1 : 0] flit_out_all;
-    output [NE-1 : 0] flit_out_wr_all;
-    input  [NEV-1 : 0] credit_in_all;
-    input  [NEFw-1 : 0] flit_in_all;
-    input  [NE-1 : 0] flit_in_wr_all;  
-    output [NEV-1 : 0] credit_out_all;
-
-
-	//struct typed array ports which cannot be caled in verilog 
-	smartflit_chanel_t chan_in_all  [NE-1 : 0];
-	smartflit_chanel_t chan_out_all [NE-1 : 0];
-
-	noc_top  #( 
-		.NOC_ID(NOC_ID)
-	) the_top(
-		.reset(reset),
-		.clk(clk),    
-		.chan_in_all(chan_in_all),
-		.chan_out_all(chan_out_all),
-		.router_event  (  )
-	);
-
-		
-	genvar i;
-	generate 
-	for (i=0; i<NE; i=i+1) begin : lp1
-		assign chan_in_all[i].flit_chanel.flit    = flit_in_all [Fw*(i+1)-1 : Fw*i];		
-		assign chan_in_all[i].flit_chanel.credit  = credit_in_all [V*(i+1)-1 : V*i]; 
-		assign chan_in_all[i].flit_chanel.flit_wr  = flit_in_wr_all[i]; 
-
-		assign flit_out_all [Fw*(i+1)-1 : Fw*i] = chan_out_all[i].flit_chanel.flit;		
-		assign credit_out_all [V*(i+1)-1 : V*i] = chan_out_all[i].flit_chanel.credit;
-		assign flit_out_wr_all[i] = chan_out_all[i].flit_chanel.flit_wr; 
-
-	end
-	endgenerate
-
+    clk,
+    chan_in_all,
+    chan_out_all,
+    router_event
+);
+    
+    import pronoc_pkg::*;
+    
+    input   clk,reset;
+    //Endpoints ports 
+    input   smartflit_chanel_t chan_in_all  [NE-1 : 0];
+    output  smartflit_chanel_t chan_out_all [NE-1 : 0];
+    //Events
+    output  router_event_t  router_event [NR-1 : 0][MAX_P-1 : 0];
+    
+    noc_top  the_top(
+        .reset(reset),
+        .clk(clk),
+        .chan_in_all(chan_in_all),
+        .chan_out_all(chan_out_all),
+        .router_event  (router_event)
+    );
 endmodule
- 
diff --git a/mpsoc/rtl/src_noc/output_ports.sv b/mpsoc/rtl/src_noc/output_ports.sv
index e4290e5..8fe6be0 100755
--- a/mpsoc/rtl/src_noc/output_ports.sv
+++ b/mpsoc/rtl/src_noc/output_ports.sv
@@ -1,38 +1,36 @@
 `include "pronoc_def.v"
 /**********************************************************************
-**	File:  output_ports.sv
+**    File: output_ports.sv
 **    
-**	Copyright (C) 2014-2017  Alireza Monemi
+**    Copyright (C) 2014-2017  Alireza Monemi
 **    
-**	This file is part of ProNoC 
+**    This file is part of ProNoC 
 **
-**	ProNoC ( stands for Prototype Network-on-chip)  is free software: 
-**	you can redistribute it and/or modify it under the terms of the GNU
-**	Lesser General Public License as published by the Free Software Foundation,
-**	either version 2 of the License, or (at your option) any later version.
+**    ProNoC ( stands for Prototype Network-on-chip)  is free software: 
+**    you can redistribute it and/or modify it under the terms of the GNU
+**    Lesser General Public License as published by the Free Software Foundation,
+**    either version 2 of the License, or (at your option) any later version.
 **
-** 	ProNoC is distributed in the hope that it will be useful, but WITHOUT
-** 	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
-** 	or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
-** 	Public License for more details.
+**     ProNoC is distributed in the hope that it will be useful, but WITHOUT
+**     ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+**     or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
+**     Public License for more details.
 **
-** 	You should have received a copy of the GNU Lesser General Public
-** 	License along with ProNoC. If not, see <http:**www.gnu.org/licenses/>.
+**     You should have received a copy of the GNU Lesser General Public
+**     License along with ProNoC. If not, see <http:**www.gnu.org/licenses/>.
 **
 **
-**	Description: 
-**	output_ports module: contain output VC (OVC) status registers and credit counters, 
+**    Description: 
+**    output_ports module: contain output VC (OVC) status registers and credit counters, 
 **
 **************************************************************/
 
 
 module output_ports #(
-    parameter NOC_ID=0,
     parameter P=5
 ) (
     vsa_ovc_allocated_all,
     flit_is_tail_all,
-   
     dest_port_all,
     nonspec_granted_dest_port_all,
     credit_in_all,
@@ -49,7 +47,6 @@ module output_ports #(
     any_ovc_granted_in_outport_all, 
     vsa_credit_decreased_all,
     vsa_ovc_released_all,
-    crossbar_flit_out_wr_all,
     oport_info,
     ovc_info,  
     ivc_info,
@@ -58,495 +55,400 @@ module output_ports #(
     smart_ctrl_in,
     credit_init_val_in
 );
-
-
-	`NOC_CONF    
+    import pronoc_pkg::*;
     
     localparam
-        PV      =    V        *    P,
-        VV      =   V       *  V,
-        PVV     =    PV        *  V,    
-        P_1     =   ( SELF_LOOP_EN=="NO")?  P-1 : P,
-        VP_1    =    V        *     P_1,                
-        PP_1    =    P_1    *    P,
-        PVP_1    =    PV        *    P_1;
-    
-    localparam [V-1     :   0] ADAPTIVE_VC_MASK = ~ ESCAP_VC_MASK;   
-    localparam  CONG_ALw=   CONGw * P;   //  congestion width per router;             
-                    
-    input  [PV-1       :    0] vsa_ovc_allocated_all;
-    input  [PV-1       :    0] flit_is_tail_all;   
-    input  [PVP_1-1    :    0] dest_port_all;
-    input  [PP_1-1     :    0] nonspec_granted_dest_port_all;
-    input  [PV-1       :    0] credit_in_all;
-    input  [PV-1       :    0] nonspec_first_arbiter_granted_ivc_all;
-    input  [PV-1       :    0] ivc_num_getting_sw_grant;
-    output [PV-1       :    0] ovc_avalable_all;
-    output [PV-1       :    0] assigned_ovc_not_full_all;
-    input                      reset,clk;
-    output [PPSw-1     :    0] port_pre_sel;
-    input  [CONG_ALw-1 :    0] congestion_in_all; 
-    input  [PVV-1 : 0] granted_ovc_num_all;    
-    input  [P-1 : 0] granted_dst_is_from_a_single_flit_pck;
-    input  [P-1 : 0] crossbar_flit_out_wr_all;
-    input  [P-1 : 0] any_ovc_granted_in_outport_all;    
-    output [PV-1    :    0]  vsa_ovc_released_all;
-    output [PV-1    :    0]  vsa_credit_decreased_all;
+        PV = V * P,
+        VV = V * V,
+        PVV = PV * V,
+        P_1 = (SELF_LOOP_EN )?  P : P-1,
+        VP_1 = V * P_1,
+        PP_1 = P_1 * P,
+        PVP_1 = PV * P_1,
+        CONG_ALw = CONGw * P;   //  congestion width per router;
+    
+    input [PV-1 : 0] vsa_ovc_allocated_all;
+    input [PV-1 : 0] flit_is_tail_all;   
+    input [PVP_1-1 : 0] dest_port_all;
+    input [PP_1-1 : 0] nonspec_granted_dest_port_all;
+    input [PV-1 : 0] credit_in_all;
+    input [PV-1 : 0] nonspec_first_arbiter_granted_ivc_all;
+    input [PV-1 : 0] ivc_num_getting_sw_grant;
+    output [PV-1 : 0] ovc_avalable_all;
+    output [PV-1 : 0] assigned_ovc_not_full_all;
+    input reset,clk;
+    output [PPSw-1 : 0] port_pre_sel;
+    input [CONG_ALw-1 : 0] congestion_in_all; 
+    input [PVV-1 : 0] granted_ovc_num_all;    
+    input [P-1 : 0] granted_dst_is_from_a_single_flit_pck;
+    input [P-1 : 0] any_ovc_granted_in_outport_all;    
+    output [PV-1 : 0]  vsa_ovc_released_all;
+    output [PV-1 : 0]  vsa_credit_decreased_all;
     output oport_info_t oport_info [P-1:0];
-    output ovc_info_t   ovc_info   [P-1 : 0][V-1 : 0];
-    input   ivc_info_t ivc_info [P-1 : 0][V-1 : 0]; 
-    input   vsa_ctrl_t vsa_ctrl_in [P-1: 0];
-    input   ssa_ctrl_t ssa_ctrl_in [P-1: 0];
-    input   smart_ctrl_t  smart_ctrl_in [P-1: 0];
-    input   [CRDTw-1 : 0 ] credit_init_val_in  [P-1 : 0][V-1 : 0];
-    
-    wire   [PVV-1 : 0] ssa_granted_ovc_num_all;
-    
-    logic  [PV-1    :    0]    ovc_status;
-    logic  [PV-1    :    0]    ovc_status_next;
-    wire   [PV-1    :    0]    assigned_ovc_is_full_all;
-    wire   [VP_1-1  :    0]    credit_decreased        [P-1        :    0];
-    wire   [P_1-1   :    0]    credit_decreased_gen    [PV-1        :    0];
-    
-    wire   [PV-1    :    0]  credit_increased_all;
-    wire   [VP_1-1    :    0]    ovc_released            [P-1        :    0];
-    wire   [P_1-1    :    0]    ovc_released_gen        [PV-1        :    0];
-   
-    wire   [VP_1-1    :   0]  credit_in_perport        [P-1        :    0];
-    wire   [VP_1-1    :    0]  full_perport              [P-1        :    0];
-    wire   [VP_1-1    :    0]  nearly_full_perport    [P-1        :    0];
-    
-    wire   [PV-1    :    0]    full_all,nearly_full_all, empty_all;
-    wire   [PV-1    :    0]    full_all_next,nearly_full_all_next,empty_all_next;
-  
-    
-    wire [PV-1  :   0] credit_decreased_all;
-    wire [PV-1  :   0] ovc_released_all;
-    wire [PV-1  :   0] ovc_allocated_all;
-    wire [CREDITw-1   :    0] credit_counter [PV-1  :   0]; 
-    
-    wire  [PVV-1      :    0] assigned_ovc_num_all;
-    wire  [PV-1       :    0] ovc_is_assigned_all;
-    
-    
-    pronoc_register #(.W(PV)) reg_1 ( .in(full_all_next), .reset(reset), .clk(clk), .out(full_all));
-    pronoc_register #(.W(PV)) reg_2 ( .in(nearly_full_all_next), .reset(reset), .clk(clk), .out(nearly_full_all));
-    pronoc_register #(.W(PV)) reg_3 ( .in(empty_all_next), .reset(reset), .clk(clk), .out(empty_all));
-    
-    
-    
-    integer k;
+    output ovc_info_t   ovc_info [P-1 : 0][V-1 : 0];
+    input  ivc_info_t ivc_info [P-1 : 0][V-1 : 0]; 
+    input  vsa_ctrl_t vsa_ctrl_in [P-1: 0];
+    input  ssa_ctrl_t ssa_ctrl_in [P-1: 0];
+    input  smart_ctrl_t  smart_ctrl_in [P-1: 0];
+    input [CRDTw-1 : 0 ] credit_init_val_in [P-1 : 0][V-1 : 0];
+    
+    wire [PVV-1 : 0] ssa_granted_ovc_num_all;
+    logic [PV-1 : 0]    ovc_status;
+    logic [PV-1 : 0]    ovc_status_next;
+    wire [PV-1 : 0]    assigned_ovc_is_full_all;
+    wire [VP_1-1 : 0]    credit_decreased [P-1 : 0];
+    wire [P_1-1 : 0]    credit_decreased_gen [PV-1 : 0];
+    wire [PV-1 : 0]  credit_increased_all;
+    wire [VP_1-1 : 0]    ovc_released [P-1 : 0];
+    wire [P_1-1 : 0]    ovc_released_gen [PV-1 : 0];
+    wire [VP_1-1 : 0]  credit_in_perport [P-1 : 0];
+    wire [VP_1-1 : 0]  full_perport [P-1 : 0];
+    wire [VP_1-1 : 0]  nearly_full_perport [P-1 : 0];
+    logic [PV-1 : 0]    full_all,nearly_full_all, empty_all;
+    wire [PV-1 : 0]    full_all_next,nearly_full_all_next,empty_all_next;
+    wire [PV-1 : 0] credit_decreased_all;
+    wire [PV-1 : 0] ovc_released_all;
+    wire [CREDITw-1 : 0] credit_counter [PV-1 : 0]; 
+    wire [PVV-1 : 0] assigned_ovc_num_all;
+    wire [PV-1 : 0] ovc_is_assigned_all;
+    always_ff @ (`pronoc_clk_reset_edge) begin
+        if (`pronoc_reset) begin
+            full_all <= '0;
+            nearly_full_all <= '0;
+            empty_all <= '0;
+        end else begin
+            full_all <= full_all_next;
+            nearly_full_all <= nearly_full_all_next;
+            empty_all <= empty_all_next;
+        end
+    end
     genvar i,j;
     generate
-        /* verilator lint_off WIDTH */
-        if(VC_REALLOCATION_TYPE=="ATOMIC") begin :atomic
-        /* verilator lint_on WIDTH */               
+        if(IS_VCA_ATOMIC) begin :atomic
             // in atomic architecture an OVC is available if its not allocated and its empty
-            assign ovc_avalable_all                 = ~ovc_status & empty_all;
-      
+            assign ovc_avalable_all      = ~ovc_status & empty_all;
         end else begin :nonatomic //NONATOMIC
-            /* verilator lint_off WIDTH */
-            if(ROUTE_TYPE  == "FULL_ADAPTIVE") begin :full_adpt
-            /* verilator lint_on WIDTH */
-                
-                reg [PV-1       :   0] full_adaptive_ovc_mask,full_adaptive_ovc_mask_next; 
-      
-                always @(*) begin
-                    for(k=0;    k<PV; k=k+1) begin
-                     //in full adaptive routing, adaptive VCs located in y axies can not be reallocated non-atomicly   
-                        if( AVC_ATOMIC_EN== 0) begin :avc_atomic
-                            if((((k/V) == NORTH ) || ((k/V) == SOUTH )) && (  ADAPTIVE_VC_MASK[k%V]))  
-                                    full_adaptive_ovc_mask_next[k]  =   empty_all_next[k];
-                            else    full_adaptive_ovc_mask_next[k] = (OVC_ALLOC_MODE)? ~full_all_next[k] : ~nearly_full_all_next[k];
-                        end else begin :avc_nonatomic
-                            if(  ADAPTIVE_VC_MASK[k%V])  
-                                    full_adaptive_ovc_mask_next[k]  =   empty_all_next[k];
-                            else    full_adaptive_ovc_mask_next[k] = (OVC_ALLOC_MODE)? ~full_all_next[k] :~nearly_full_all_next[k];    
-                        
-                        end                       
-                     end // for  
-                end//always
-
-                pronoc_register #(.W(PV)) reg2 ( .in(full_adaptive_ovc_mask_next), .reset(reset), .clk(clk), .out(full_adaptive_ovc_mask));
-         
-                assign ovc_avalable_all              = ~ovc_status & full_adaptive_ovc_mask;
-            
-            end else begin : par_adpt//par adaptive
-                assign ovc_avalable_all = (OVC_ALLOC_MODE)? ~(ovc_status | full_all) :  ~(ovc_status | nearly_full_all);
-            	
-           end
-        end //NONATOMIC    
+            if(IS_FULL_ADAPTIVE) begin :full_adpt
+                regular_topo_full_adapt_ovc_avail #(
+                    .P(P)
+                ) ovc_avb (
+                    .reset(reset),
+                    .clk(clk),
+                    .empty_all_next(empty_all_next),
+                    .full_all_next(full_all_next),
+                    .nearly_full_all_next(nearly_full_all_next),
+                    .ovc_status(ovc_status),
+                    .ovc_avalable_all(ovc_avalable_all)
+                );
+            end else begin : par_adpt //par adaptive
+                assign ovc_avalable_all = (OVC_ALLOC_MODE)? ~(ovc_status | full_all) : ~(ovc_status | nearly_full_all);
+            end
+        end //NONATOMIC
     endgenerate
     
-    
-    assign credit_increased_all         = credit_in_all;
-    assign assigned_ovc_not_full_all    =    ~ assigned_ovc_is_full_all;
-    
-  //  wire [PV-1 : 0] non_smart_ovc_allocated_all =    ssa_ovc_allocated_all| vsa_ovc_allocated_all;
+    assign credit_increased_all = credit_in_all;
+    assign assigned_ovc_not_full_all = ~ assigned_ovc_is_full_all;
+    //wire [PV-1 : 0] non_smart_ovc_allocated_all = ssa_ovc_allocated_all| vsa_ovc_allocated_all;
     wire [PV-1 : 0] non_smart_ovc_allocated_all;
     generate
     for(i=0;i<P;i=i+1    ) begin :P_
-    	assign ssa_granted_ovc_num_all[(i+1)*VV-1:  i*VV] = ssa_ctrl_in[i].ivc_granted_ovc_num;      	
-    	assign credit_decreased_all [(i+1)*V-1 : i*V] = vsa_ctrl_in[i].buff_space_decreased | 	ssa_ctrl_in[i].buff_space_decreased | smart_ctrl_in[i].buff_space_decreased;
-    	assign ovc_released_all 	[(i+1)*V-1 : i*V] = vsa_ctrl_in[i].ovc_is_released  | ssa_ctrl_in[i].ovc_is_released  | smart_ctrl_in[i].ovc_is_released;
-    	assign ovc_allocated_all 	[(i+1)*V-1 : i*V] = vsa_ctrl_in[i].ovc_is_allocated | ssa_ctrl_in[i].ovc_is_allocated | smart_ctrl_in[i].ovc_is_allocated;  
-    	//assign non_smart_ovc_allocated_all [(i+1)*V-1 : i*V] = ssa_ctrl_in[i].ovc_is_allocated | vsa_ctrl_in[i].ovc_is_allocated;
-
-    	assign non_smart_ovc_allocated_all [(i+1)*V-1 : i*V] =  vsa_ctrl_in[i].ovc_is_allocated;
-	
-    		
-        assign oport_info[i].non_smart_ovc_is_allocated =  non_smart_ovc_allocated_all [(i+1)*V-1        :i*V];
-        assign oport_info[i].any_ovc_granted =  any_ovc_granted_in_outport_all [i];  
-       
-       
+        assign ssa_granted_ovc_num_all[(i+1)*VV-1: i*VV] = ssa_ctrl_in[i].ivc_granted_ovc_num;
+        assign credit_decreased_all [(i+1)*V-1 : i*V] = vsa_ctrl_in[i].buff_space_decreased |     ssa_ctrl_in[i].buff_space_decreased | smart_ctrl_in[i].buff_space_decreased;
+        assign ovc_released_all [(i+1)*V-1 : i*V] = vsa_ctrl_in[i].ovc_is_released  | ssa_ctrl_in[i].ovc_is_released  | smart_ctrl_in[i].ovc_is_released;
+        //assign non_smart_ovc_allocated_all [(i+1)*V-1 : i*V] = ssa_ctrl_in[i].ovc_is_allocated | vsa_ctrl_in[i].ovc_is_allocated;
+        assign non_smart_ovc_allocated_all [(i+1)*V-1 : i*V] = vsa_ctrl_in[i].ovc_is_allocated;
+        assign oport_info[i].non_smart_ovc_is_allocated = non_smart_ovc_allocated_all [(i+1)*V-1 :i*V];
+        assign oport_info[i].any_ovc_granted = any_ovc_granted_in_outport_all [i];  
+        
         oport_ovc_sig_gen #(
-            .V    (V), // vc_num_per_port
-            .P    (P), // router port num
+            .V (V), // vc_num_per_port
+            .P (P), // router port num
             .SELF_LOOP_EN(SELF_LOOP_EN)
-        )the_oport_ovc_sig_gen
-        (
-            .flit_is_tail                    (flit_is_tail_all                        [(i+1)*V-1        :i*V]),
-            .assigned_ovc_num                (assigned_ovc_num_all                [(i+1)*VV-1        :i*VV]),
-            .ovc_is_assigned                 (ovc_is_assigned_all                    [(i+1)*V-1        :i*V]),
-            .granted_dest_port               (nonspec_granted_dest_port_all                [(i+1)*P_1-1    :i*P_1]),
-            .first_arbiter_granted_ivc       (nonspec_first_arbiter_granted_ivc_all    [(i+1)*V-1        :i*V]),
-            .credit_decreased                (credit_decreased                        [i]),
-            .ovc_released                    (ovc_released                            [i])
-            
+        )the_oport_ovc_sig_gen (
+            .flit_is_tail (flit_is_tail_all    [(i+1)*V-1 :i*V]),
+            .assigned_ovc_num (assigned_ovc_num_all [(i+1)*VV-1 :i*VV]),
+            .ovc_is_assigned (ovc_is_assigned_all [(i+1)*V-1 :i*V]),
+            .granted_dest_port(nonspec_granted_dest_port_all [(i+1)*P_1-1 :i*P_1]),
+            .first_arbiter_granted_ivc(nonspec_first_arbiter_granted_ivc_all [(i+1)*V-1 :i*V]),
+            .credit_decreased (credit_decreased[i]),
+            .ovc_released(ovc_released [i])
         );         
-        	
         for(j=0; j<V;  j=j+1)begin : V_
-        	assign 	ovc_info[i][j].avalable= ovc_avalable_all [i*V+j]; 
-        	assign 	ovc_info[i][j].status =ovc_status [i*V+j]; //1 : is allocated 0 : not_allocated
-        	assign 	ovc_info[i][j].credit = credit_counter[i*V+j];//available credit in OVC
-        	assign 	ovc_info[i][j].full =full_all[i*V+j];
-        	assign 	ovc_info[i][j].nearly_full=nearly_full_all[i*V+j];
-        	assign 	ovc_info[i][j].empty=empty_all[i*V+j];
-        end		        	
-
+            assign     ovc_info[i][j].avalable= ovc_avalable_all [i*V+j]; 
+            assign     ovc_info[i][j].status =ovc_status [i*V+j]; //1 : is allocated 0 : not_allocated
+            assign     ovc_info[i][j].credit = credit_counter[i*V+j];//available credit in OVC
+            assign     ovc_info[i][j].full =full_all[i*V+j];
+            assign     ovc_info[i][j].nearly_full=nearly_full_all[i*V+j];
+            assign     ovc_info[i][j].empty=empty_all[i*V+j];
+        end
     end//for
-        
     
     for(i=0;i< PV;i=i+1) begin :total_vc_loop2
         for(j=0;j<P;    j=j+1)begin: assign_loop2
-        	if ( SELF_LOOP_EN=="NO") begin : nslp  
-	            if((i/V)<j )begin: jj
-	                assign ovc_released_gen        [i][j-1]    = ovc_released[j][i];
-	                assign credit_decreased_gen[i][j-1]    = credit_decreased [j][i];
-	            end else if((i/V)>j) begin: hh
-	                assign ovc_released_gen        [i][j]    = ovc_released[j][i-V];
-	                assign credit_decreased_gen[i][j]    = credit_decreased[j][i-V];
-	            end
-	        end else begin :slp
-	        	assign ovc_released_gen        [i][j]    = ovc_released[j][i];
-	            assign credit_decreased_gen[i][j]    = credit_decreased [j][i];	        
-	        end
+            if ( SELF_LOOP_EN==0) begin : nslp  
+                if((i/V)<j )begin: jj
+                    assign ovc_released_gen [i][j-1] = ovc_released[j][i];
+                    assign credit_decreased_gen[i][j-1] = credit_decreased [j][i];
+                end else if((i/V)>j) begin: hh
+                    assign ovc_released_gen [i][j] = ovc_released[j][i-V];
+                    assign credit_decreased_gen[i][j] = credit_decreased[j][i-V];
+                end
+            end else begin :slp
+                assign ovc_released_gen [i][j] = ovc_released[j][i];
+                assign credit_decreased_gen[i][j] = credit_decreased [j][i];
+            end
         end//j
-        assign vsa_ovc_released_all      [i] = |ovc_released_gen[i];
+        assign vsa_ovc_released_all [i] = |ovc_released_gen[i];
         assign vsa_credit_decreased_all [i] = (|credit_decreased_gen[i])|vsa_ovc_allocated_all[i];
     end//i
     
-    
-
-    if ( SELF_LOOP_EN=="NO") begin : nslp  
-	    //remove source port from the list 
-	    for(i=0;i< P;i=i+1) begin :port_loop
-	        if(i==0)        begin :i0
-	            assign credit_in_perport    [i]=credit_in_all     [PV-1                :    V];
-	            assign full_perport             [i]=full_all              [PV-1                :    V];
-	            assign nearly_full_perport    [i]=nearly_full_all    [PV-1                :    V];
-	        end else if(i==(P-1)) begin :ip_1
-	            assign credit_in_perport    [i]=credit_in_all     [PV-V-1            :    0];
-	            assign full_perport             [i]=full_all              [PV-V-1            :    0];
-	            assign nearly_full_perport    [i]=nearly_full_all    [PV-V-1            :    0];
-	        end else begin : els
-	            assign credit_in_perport    [i]={credit_in_all     [PV-1    :    (i+1)*V],credit_in_all     [(i*V)-1    :    0]};
-	            assign full_perport             [i]={full_all          [PV-1    :    (i+1)*V],full_all         [(i*V)-1    :    0]};
-	            assign nearly_full_perport    [i]={nearly_full_all [PV-1    :    (i+1)*V],nearly_full_all[(i*V)-1    :    0]};
-	        end
-	    end//for
-    end else begin:  slp
-    	for(i=0;i< P;i=i+1) begin :port_loop
-	    	assign credit_in_perport    [i]=credit_in_all;
-		    assign full_perport         [i]=full_all;
-		    assign nearly_full_perport  [i]=nearly_full_all;
-	    end
+    if ( SELF_LOOP_EN==0) begin : nslp  
+        //remove source port from the list 
+        for(i=0;i< P;i=i+1) begin :port_loop
+            if(i==0)  begin :i0
+                assign credit_in_perport [i]=credit_in_all [PV-1     : V];
+                assign full_perport [i]=full_all [PV-1     : V];
+                assign nearly_full_perport [i]=nearly_full_all [PV-1     : V];
+            end else if(i==(P-1)) begin :ip_1
+                assign credit_in_perport [i]=credit_in_all [PV-V-1 : 0];
+                assign full_perport [i]=full_all [PV-V-1 : 0];
+                assign nearly_full_perport [i]=nearly_full_all [PV-V-1 : 0];
+            end else begin : els
+                assign credit_in_perport [i]={credit_in_all [PV-1 : (i+1)*V],credit_in_all [(i*V)-1 : 0]};
+                assign full_perport [i]={full_all [PV-1 : (i+1)*V],full_all [(i*V)-1 : 0]};
+                assign nearly_full_perport [i]={nearly_full_all [PV-1 : (i+1)*V],nearly_full_all[(i*V)-1 : 0]};
+            end
+        end//for
+    end else begin: slp
+        for(i=0;i< P;i=i+1) begin :port_loop
+            assign credit_in_perport [i]=credit_in_all;
+            assign full_perport [i]=full_all;
+            assign nearly_full_perport [i]=nearly_full_all;
+        end
     end
     
-    
-    
-   
-    
-    
-    for(i=0; i<PV; i=i+1) begin :PV_loop2
-        
-    	assign assigned_ovc_num_all[(i+1)*V-1 : i*V] = ivc_info[i/V][i%V].assigned_ovc_num;
-    	assign ovc_is_assigned_all[i]=ivc_info[i/V][i%V].ovc_is_assigned;
-    	    	
-    	credit_monitor_per_ovc	#( 
-    		.NOC_ID(NOC_ID),
+    for(i=0; i<PV; i=i+1) begin :PV_
+        assign assigned_ovc_num_all[(i+1)*V-1 : i*V] = ivc_info[i/V][i%V].assigned_ovc_num;
+        assign ovc_is_assigned_all[i]=ivc_info[i/V][i%V].ovc_is_assigned;
+        credit_monitor_per_ovc    #( 
             .SW_LOC(i/V)
-    	) 	credit_monitor (
-    		.credit_init_val_i(credit_init_val_in[i/V][i%V]),
-    		.credit_counter_o (credit_counter[i]),
-    		.credit_increased (credit_increased_all[i]),
-    		.credit_decreased(credit_decreased_all[i]),
-    		.empty_all_next(empty_all_next[i]),
-    		.full_all_next(full_all_next[i]),
-    		.nearly_full_all_next(nearly_full_all_next[i]),   
-    		.reset(reset),
-    		.clk(clk)	
-    	); 
-    	
-    	
-    	
-    	full_ovc_predictor #(
-         	.OVC_ALLOC_MODE(OVC_ALLOC_MODE),
-         	.PCK_TYPE(PCK_TYPE),
-         	.V (V), // vc_num_per_port
+        ) credit_monitor (
+            .credit_init_val_i(credit_init_val_in[i/V][i%V]),
+            .credit_counter_o (credit_counter[i]),
+            .credit_increased (credit_increased_all[i]),
+            .credit_decreased(credit_decreased_all[i]),
+            .empty_all_next(empty_all_next[i]),
+            .full_all_next(full_all_next[i]),
+            .nearly_full_all_next(nearly_full_all_next[i]),
+            .reset(reset),
+            .clk(clk)
+        ); 
+        
+        full_ovc_predictor #(
+            .OVC_ALLOC_MODE(OVC_ALLOC_MODE),
+            .PCK_TYPE(PCK_TYPE),
+            .V (V), // vc_num_per_port
             .P (P), // router port num
             .SELF_LOOP_EN (SELF_LOOP_EN)
-            
-        )
-        sw_mask
-        (
-        	.ssa_granted_ovc_num(ssa_granted_ovc_num_all[(i+1)*V-1        :i*V]),
-        	.granted_ovc_num(granted_ovc_num_all[(i+1)*V-1        :i*V]),
-        	.ovc_is_assigned(ovc_is_assigned_all[i]),
-        	.assigned_ovc_num (assigned_ovc_num_all[(i+1)*V-1        :i*V]),
-            .dest_port (dest_port_all  [(i+1)*P_1-1    :i*P_1]),
+        )sw_mask (
+            .ssa_granted_ovc_num(ssa_granted_ovc_num_all[(i+1)*V-1 :i*V]),
+            .granted_ovc_num(granted_ovc_num_all[(i+1)*V-1 :i*V]),
+            .ovc_is_assigned(ovc_is_assigned_all[i]),
+            .assigned_ovc_num (assigned_ovc_num_all[(i+1)*V-1 :i*V]),
+            .dest_port (dest_port_all [(i+1)*P_1-1 :i*P_1]),
             .full  (full_perport [i/V]),
             .credit_increased (credit_in_perport [i/V]),
-            .nearly_full (nearly_full_perport    [i/V]),
+            .nearly_full (nearly_full_perport [i/V]),
             .ivc_getting_sw_grant  (ivc_num_getting_sw_grant[i]),
             .assigned_ovc_is_full  (assigned_ovc_is_full_all[i]),
             .clk (clk),
             .reset  (reset)
-        );
+        );        
     end//for
-    
-	
-    	
-    	
-    	
-    	
-    for(i=0;    i<PV; i=i+1) begin :reg_blk
-    	always @ (*)begin 
-            ovc_status_next[i]   =  ovc_status[i];             
-            /* verilator lint_off WIDTH */
-          	if(PCK_TYPE == "SINGLE_FLIT")  ovc_status_next[i]=1'b0; // donot change VC status for single flit packet
-           	/* verilator lint_on WIDTH */
-           	else begin 
-               	if(ovc_released_all[i])        ovc_status_next[i] =1'b0;
-               	//if(ovc_allocated_all[i] & ~granted_dst_is_from_a_single_flit_pck[i/V])    ovc_status_next[i]=1'b1; // donot change VC status for single flit packet
-            	if((vsa_ctrl_in[i/V].ovc_is_allocated[i%V] & ~granted_dst_is_from_a_single_flit_pck[i/V]) |
-                	   (ssa_ctrl_in[i/V].ovc_is_allocated[i%V] & ~ssa_ctrl_in[i/V].ovc_single_flit_pck[i%V])|
-                	   (smart_ctrl_in[i/V].ovc_is_allocated[i%V] & ~smart_ctrl_in[i/V].ovc_single_flit_pck[i%V]))  
-                	   ovc_status_next[i]=1'b1; // donot change VC status for single flit packet	
-                	
-                end        
-        end//always
-    end//for     
     endgenerate
     
-    pronoc_register #(.W(PV)) reg2 (.in(ovc_status_next ), .out(ovc_status), .reset(reset), .clk(clk));
-
+    always_comb begin
+        for(int k=0; k<PV; k++) begin
+            ovc_status_next[k] = ovc_status[k];
+            if(IS_SINGLE_FLIT)  ovc_status_next[k]=1'b0; // donot change VC status for single flit packet
+            else begin 
+                if(ovc_released_all[k])  ovc_status_next[k] =1'b0;
+                //if(ovc_allocated_all[k] & ~granted_dst_is_from_a_single_flit_pck[k/V])    ovc_status_next[k]=1'b1; // donot change VC status for single flit packet
+                if((vsa_ctrl_in[k/V].ovc_is_allocated[k%V] & ~granted_dst_is_from_a_single_flit_pck[k/V]) |
+                    (ssa_ctrl_in[k/V].ovc_is_allocated[k%V] & ~ssa_ctrl_in[k/V].ovc_single_flit_pck[k%V])|
+                    (smart_ctrl_in[k/V].ovc_is_allocated[k%V] & ~smart_ctrl_in[k/V].ovc_single_flit_pck[k%V]))  
+                    ovc_status_next[k]=1'b1; // donot change VC status for single flit packet    
+            end
+        end
+    end//always
+    always_ff @ (`pronoc_clk_reset_edge) begin
+        if (`pronoc_reset) begin
+            ovc_status <= '0;
+        end else begin
+            ovc_status <= ovc_status_next;
+        end
+    end
+    
     port_pre_sel_gen #(
-        .PPSw(PPSw),
-        .P(P),
-        .V(V),
-        .B(B),
-        .CONGESTION_INDEX(CONGESTION_INDEX),
-        .CONGw(CONGw),
-        .ROUTE_TYPE(ROUTE_TYPE),
-        .ESCAP_VC_MASK(ESCAP_VC_MASK)
-
-    )
-     port_pre_sel_top    
-    (
+        .P(P)
+    ) port_pre_sel_top (
         .port_pre_sel(port_pre_sel),
         .ovc_status(ovc_status),
-        .ovc_avalable_all(ovc_avalable_all),
         .credit_decreased_all(credit_decreased_all),
         .credit_increased_all(credit_increased_all),
         .congestion_in_all(congestion_in_all),
         .reset(reset),
         .clk(clk)
-
     );
     
-
-    //synthesis translate_off 
-    //synopsys  translate_off
-generate 
-if(DEBUG_EN) begin: debug
-
-
-    always @ (posedge clk )begin 
-        for(k=0;    k<PV; k=k+1'b1) begin 
-            if(empty_all[k] & credit_increased_all[k]) begin 
-            	$display("%t: ERROR: unexpected credit recived for empty ovc[%d]: %m",$time,k);
-				$finish;
-			end
-            if(full_all[k] & credit_decreased_all[k]) begin 
-                $display("%t: ERROR: Attempt to send flit to full ovc[%d]: %m",$time,k);
-				$finish;
-			end
-            if(ovc_released_all[k] & ovc_allocated_all[k]) begin    
-                $display("%t: ERROR: simultaneous allocation and release for an OVC[%d]: %m",$time,k);
-				$finish;
-			end
-            if(ovc_released_all[k]==1'b1 && ovc_status[k]==1'b0) begin 
-                $display("%t: ERROR: Attempt to release an unallocated OVC[%d]: %m",$time,k);
-				$finish;
-			end
-			if(ovc_allocated_all[k] & ovc_status[k]) begin 
-                $display("%t: ERROR: Attempt to allocate an allocated OVC[%d]: %m",$time,k);
-				$finish;
-			end
-        end//for
-
-    end//always
-    
-
-    /* verilator lint_off WIDTH */    
-    if(CAST_TYPE== "UNICAST") begin : unicast
-    /* verilator lint_on WIDTH */
-
-	    localparam NUM_WIDTH = log2(PV+1);
-	    wire [NUM_WIDTH-1        :    0] num1,num2;
-    
-	    accumulator #(
-	    	.INw(PV),
-	    	.OUTw(NUM_WIDTH),
-	    	.NUM(PV) 
-	   	)
-	   	cnt1
-	   	(
-	   		.in_all(ovc_status),
-	    	.out(num1)         
-	    );
-    
-	    accumulator #(
-	    	.INw(PV),
-	    	.OUTw(NUM_WIDTH),
-	    	.NUM(PV) 
-	    )
-	    cnt2
-	    (
-	    	.in_all(ovc_is_assigned_all),
-	    	.out(num2)         
-	    );
-	    	
-     
-   
-    
-    always @(posedge clk) begin
-        if(num1    != num2 )begin 
-        	$display("%t: ERROR: number of assigned IVC %d mismatch the number of occupied OVC %d: %m",$time,num1,num2);
-        	$finish;
+    `ifdef SIMULATION
+    generate 
+    if(DEBUG_EN) begin: debug
+        wire [PV-1 : 0] ovc_allocated_all;
+        for(i=0;i<P;i=i+1 ) begin :P_
+            assign ovc_allocated_all [(i+1)*V-1 : i*V] = vsa_ctrl_in[i].ovc_is_allocated | ssa_ctrl_in[i].ovc_is_allocated | smart_ctrl_in[i].ovc_is_allocated;
         end
-    end
-    end //unicast
-    check_ovc #(
-        .V(V) , // vc_num_per_port
-        .P(P), // router port num
-        .SELF_LOOP_EN(SELF_LOOP_EN)
-        
-    )test
-    (
-    .ovc_status(ovc_status),
-    .assigned_ovc_num_all(assigned_ovc_num_all),
-    .ovc_is_assigned_all(ovc_is_assigned_all),
-    .dest_port_all(dest_port_all),
-    .clk(clk),
-    .reset(reset)
-    );
-
-end// DEBUG
-endgenerate 
-    //synopsys  translate_on
-    //synthesis translate_on
+        always @ (posedge clk )begin 
+            for( int k=0; k<PV; k=k+1'b1) begin 
+                if(empty_all[k] & credit_increased_all[k]) begin 
+                    $display("%t: ERROR: unexpected credit recived for empty ovc[%d]: %m",$time,k);
+                    $finish;
+                end
+                if(full_all[k] & credit_decreased_all[k]) begin 
+                    $display("%t: ERROR: Attempt to send flit to full ovc[%d]: %m",$time,k);
+                    $finish;
+                end
+                if(ovc_released_all[k] & ovc_allocated_all[k]) begin
+                    $display("%t: ERROR: simultaneous allocation and release for an OVC[%d]: %m",$time,k);
+                    $finish;
+                end
+                if(ovc_released_all[k]==1'b1 && ovc_status[k]==1'b0) begin 
+                    $display("%t: ERROR: Attempt to release an unallocated OVC[%d]: %m",$time,k);
+                    $finish;
+                end
+                if(ovc_allocated_all[k] & ovc_status[k]) begin 
+                    $display("%t: ERROR: Attempt to allocate an allocated OVC[%d]: %m",$time,k);
+                    $finish;
+                end
+            end//for
+        end//always
+        if( IS_UNICAST ) begin : unicast
+            localparam NUM_WIDTH = log2(PV+1);
+            wire [NUM_WIDTH-1 : 0] num1,num2;
+            accumulator #(
+                .INw(PV),
+                .OUTw(NUM_WIDTH),
+                .NUM(PV) 
+            )cnt1 (
+                .in_all(ovc_status),
+                .sum_o(num1)
+            );
+            accumulator #(
+                .INw(PV),
+                .OUTw(NUM_WIDTH),
+                .NUM(PV) 
+            ) cnt2 (
+                .in_all(ovc_is_assigned_all),
+                .sum_o(num2)
+            );
+            always @(posedge clk) begin
+                if(num1    != num2 )begin 
+                    $display("%t: ERROR: number of assigned IVC %d mismatch the number of occupied OVC %d: %m",$time,num1,num2);
+                    $finish;
+                end
+            end
+        end //unicast
+        check_ovc #(
+            .V(V) , // vc_num_per_port
+            .P(P), // router port num
+            .SELF_LOOP_EN(SELF_LOOP_EN)
+        ) test (
+            .ovc_status(ovc_status),
+            .assigned_ovc_num_all(assigned_ovc_num_all),
+            .ovc_is_assigned_all(ovc_is_assigned_all),
+            .dest_port_all(dest_port_all),
+            .clk(clk),
+            .reset(reset)
+        );
+    end// DEBUG
+    endgenerate 
+    `endif
 endmodule 
 
 
 /*********************
- * 	credit_monitor_per_ovc 	
+ *     credit_monitor_per_ovc 
  ********************/
- 
 module   credit_monitor_per_ovc  #(
-    parameter NOC_ID=0,
     parameter SW_LOC=0
 ) (
-	credit_init_val_i,
-	credit_increased,
-	credit_decreased,
-	credit_counter_o,
-	empty_all_next,
-	full_all_next,
-	nearly_full_all_next,   
-	reset,
-	clk
+    credit_init_val_i,
+    credit_increased,
+    credit_decreased,
+    credit_counter_o,
+    empty_all_next,
+    full_all_next,
+    nearly_full_all_next,
+    reset,
+    clk
 );
-	
-	`NOC_CONF    
-	
-	localparam 
-    	PORT_B = port_buffer_size(SW_LOC),	
-	    DEPTHw = log2(PORT_B+1);
-		
-	localparam [DEPTHw-1    :    0] Bint    =    PORT_B [DEPTHw-1    :    0];
-	
-	input  [CRDTw-1 : 0] credit_init_val_i;
-	input 	credit_increased;
-	input	credit_decreased;	
-	output  reg [CREDITw-1   :    0]    credit_counter_o ;
-	output empty_all_next;
-	output full_all_next;
-	output nearly_full_all_next; 
-	input reset,clk;
-	
-	reg    [DEPTHw-1    :    0]    credit_counter_next;
-	reg    [DEPTHw-1    :    0]    credit_counter;
-	
-	always @(*) begin		
-		credit_counter_next    =    credit_counter;
-		if(credit_increased    &   ~credit_decreased) begin 
-			credit_counter_next =   credit_counter+1'b1;
-		end else if (~credit_increased  &  credit_decreased)begin    
-			credit_counter_next =  credit_counter-1'b1;
-		end
-		credit_counter_o = {CREDITw{1'b0}};
-		credit_counter_o  [DEPTHw-1 :  0] = credit_counter;		
-	end
-	
-	
-	assign 	empty_all_next       =  (credit_counter_next  == Bint);
-	assign 	full_all_next        =  (credit_counter_next  == {DEPTHw{1'b0}});
-	assign 	nearly_full_all_next =  (credit_counter_next  <= 1);	
-	
-	
-	pronoc_register_reset_init #(
-			.W(DEPTHw)			
-		)reg1( 
-			.in(credit_counter_next),
-			.reset(reset),	
-			.clk(clk),		
-			.out(credit_counter),
-			.reset_to(credit_init_val_i [DEPTHw-1    :    0]) // Bint;
-		);
-			
-	
+    
+    import pronoc_pkg::*;
+    localparam 
+        // NOTE: For multi-mesh, B is the buffer size in the current
+        // chip/cluster and LB is the maximal buffer size across the whole
+        // topology. The size of the neighboring buffers is given by the
+        // credit_init_val_i signal. With the current implementation, if
+        // credit_init_val_i < LB (== Bint), the empty_all_next signal is never
+        // asserted as the value Bint is never reached. This is not an issue
+        // with a deterministic algorithm (such as Depth-First) but would need
+        // to be changed to support an adaptive variant.
+        PORT_B = (IS_MULTI_MESH) ? LB : port_buffer_size(SW_LOC),
+        DEPTHw = log2(PORT_B+1);
+    localparam [DEPTHw-1 : 0] Bint = PORT_B [DEPTHw-1 : 0];
+    
+    input [CRDTw-1 : 0] credit_init_val_i;
+    input credit_increased;
+    input credit_decreased;    
+    output reg [CREDITw-1 : 0]    credit_counter_o ;
+    output empty_all_next;
+    output full_all_next;
+    output nearly_full_all_next; 
+    input reset,clk;
+    
+    reg [DEPTHw-1 : 0]    credit_counter_next;
+    reg [DEPTHw-1 : 0]    credit_counter;
+    always_comb begin        
+        credit_counter_next = credit_counter;
+        if(credit_increased    &   ~credit_decreased) begin 
+            credit_counter_next = credit_counter+1'b1;
+        end else if (~credit_increased  &  credit_decreased)begin    
+            credit_counter_next = credit_counter-1'b1;
+        end
+        credit_counter_o = {CREDITw{1'b0}};
+        credit_counter_o [DEPTHw-1 : 0] = credit_counter;        
+    end
+    assign     empty_all_next = (credit_counter_next == Bint);
+    assign     full_all_next = (credit_counter_next == {DEPTHw{1'b0}});
+    assign     nearly_full_all_next = (credit_counter_next  <= 1);    
+    
+    always_ff @ (`pronoc_clk_reset_edge) begin
+        if (`pronoc_reset) begin
+            credit_counter <= credit_init_val_i[DEPTHw-1:0];
+        end else begin
+            credit_counter <= credit_counter_next;
+        end
+    end
 endmodule
 
 
 /************************************
-        oport_ovc_sig_gen
+*        oport_ovc_sig_gen
 *************************************/
 module oport_ovc_sig_gen #(
     parameter V = 4, // vc_num_per_port
     parameter P = 5, // router port num
-    parameter SELF_LOOP_EN = "NO"
+    parameter SELF_LOOP_EN = 0
 )(
     flit_is_tail,
     assigned_ovc_num,
@@ -555,95 +457,60 @@ module oport_ovc_sig_gen #(
     first_arbiter_granted_ivc,
     credit_decreased,
     ovc_released
+);
     
-);    
-    
-    localparam      VV      =    V        *    V,
-                    P_1     =    ( SELF_LOOP_EN=="NO")?  P-1 : P,
-                    VP_1    =    V        *     P_1;
-                    
-                    
-    input   [V-1         :    0]    flit_is_tail;
-    input   [VV-1        :    0]    assigned_ovc_num;
-    input   [V-1         :    0]    ovc_is_assigned;
-    input   [P_1-1       :    0]    granted_dest_port;
-    input   [V-1         :    0]    first_arbiter_granted_ivc;
-    output  [VP_1-1      :    0]    credit_decreased;
-    output  [VP_1-1      :    0]    ovc_released;
-        
-    
-    
-    wire [V-1      :    0] muxout1;
-    wire                   muxout2;
-    
-    wire   [VV-1   :    0] assigned_ovc_num_masked;
+    localparam
+        VV = V * V,
+        P_1 = (SELF_LOOP_EN )?  P : P-1,
+        VP_1 = V * P_1;
+    
+    input [V-1 : 0]  flit_is_tail;
+    input [VV-1 : 0] assigned_ovc_num;
+    input [V-1 : 0]  ovc_is_assigned;
+    input [P_1-1 : 0] granted_dest_port;
+    input [V-1 : 0] first_arbiter_granted_ivc;
+    output [VP_1-1 : 0] credit_decreased;
+    output [VP_1-1 : 0] ovc_released;
+    
+    logic [V-1 : 0] muxout1;
+    wire muxout2;
+    wire [V-1 : 0] assigned_ovc_num_masked[V-1 : 0];
     genvar i;
     generate 
-        for (i=0;i<V;i=i+1)begin: mask_lp
-            assign    assigned_ovc_num_masked[(i+1)*V-1    :    i*V] = ovc_is_assigned[i]? assigned_ovc_num [(i+1)*V-1    :    i*V] : {V{1'b0}};
+        for (i=0;i<V;i=i+1)begin: V_
+            assign assigned_ovc_num_masked[i] = ovc_is_assigned[i]? assigned_ovc_num [(i+1)*V-1 : i*V] : {V{1'b0}};
         end
     endgenerate
-      
-    
-    
-    // assigned ovc mux 
-    onehot_mux_1D #(
-        .W  (V),
-        .N  (V)
-    )assigned_ovc_mux
-    (
-        .in  (assigned_ovc_num_masked),
-        .out (muxout1),
-        .sel (first_arbiter_granted_ivc)
-    );
-    
+    //One-hot mux to select assigned ovc
+    always_comb begin
+        muxout1 = '0;
+        for (int k = 0; k < V; k++)
+            muxout1 |= (first_arbiter_granted_ivc[k]) ?  assigned_ovc_num_masked[k] :  '0;
+    end
     // tail mux 
-   	onehot_mux_1D #(
-        .W  (1),
-        .N  (V)
-    )tail_mux
-    (
-        .in        (flit_is_tail),
-        .out       (muxout2),
-        .sel       (first_arbiter_granted_ivc)
-    );
-    
-    
-    one_hot_demux    #(
-        .IN_WIDTH    (V),
-        .SEL_WIDTH    (P_1)
-        
-    ) demux
-    (
-        .demux_sel    (granted_dest_port),//selectore
-        .demux_in    (muxout1),//repeated
-        .demux_out    (credit_decreased)
-    );
-    
+    assign muxout2 = |(flit_is_tail & first_arbiter_granted_ivc);
+    //Onehot demultiplexer
+    generate for (i = 0; i < P_1; i++) begin : P_
+        assign credit_decreased [i*V +: V] = (granted_dest_port [i] == 1'b1) ? muxout1 : {V{1'b0}};
+    end endgenerate
     assign ovc_released = (muxout2)? credit_decreased : {VP_1{1'b0}};
-    
-    
 endmodule
 
 
 /**********************************
-
-    full_ovc_predictor
-
+*    full_ovc_predictor
 *********************************/
-
 module full_ovc_predictor #(
-    parameter PCK_TYPE = "MULTI_FLIT",    
-	parameter V = 4, // vc_num_per_port
+    parameter PCK_TYPE = "MULTI_FLIT",
+    parameter V = 4, // vc_num_per_port
     parameter P = 5, // router port num
     parameter OVC_ALLOC_MODE=1'b0,
-    parameter SELF_LOOP_EN = "NO"
-        
+    parameter SELF_LOOP_EN = 0
 )(
-	ssa_granted_ovc_num,
-	granted_ovc_num,
-	ovc_is_assigned,
-	assigned_ovc_num,
+    ssa_granted_ovc_num,
+    granted_ovc_num,
+    ovc_is_assigned,
+    assigned_ovc_num,
     dest_port,
     full,
     credit_increased,
@@ -653,94 +520,69 @@ module full_ovc_predictor #(
     clk,
     reset
 );
-    localparam      P_1   =  ( SELF_LOOP_EN=="NO")?  P-1 : P,
-                    VP_1    =    V        *     P_1;
-    input	clk,reset;                
-    input	ovc_is_assigned;
-    input	[V-1           :    0]	assigned_ovc_num,granted_ovc_num,ssa_granted_ovc_num;
-    input	[P_1-1         :    0]	dest_port;
-    input	[VP_1-1        :    0]	full;
-    input	[VP_1-1        :    0]	credit_increased;
-    input	[VP_1-1        :    0]	nearly_full;
-    input 	ivc_getting_sw_grant;
-    output	assigned_ovc_is_full;    
-
-
-    wire        [VP_1-1        :    0]    full_muxin1,nearly_full_muxin1;
-    wire         [V-1            :    0]    full_muxout1,nearly_full_muxout1;
-    wire                                full_muxout2,nearly_full_muxout2;
-    wire   full_reg1,full_reg2;
-    wire   full_reg1_next,full_reg2_next;
-    
-    
-    assign full_muxin1             = full & (~credit_increased);
-    assign nearly_full_muxin1     = nearly_full & (~credit_increased);
-    
-    
-    // destport mux 
-    onehot_mux_1D #(
-        .W  (V),
-        .N  (P_1)
-    )full_mux1
-    (
-        .in     (full_muxin1),
-        .out    (full_muxout1),
-        .sel    (dest_port)
-    );
-    
-    onehot_mux_1D #(
-        .W  (V),
-        .N  (P_1)
-    )nearly_full_mux1
-    (
-        .in        (nearly_full_muxin1),
-        .out       (nearly_full_muxout1),
-        .sel       (dest_port)
-    );
-    
-    // assigned ovc mux     	
-    onehot_mux_1D #(
-        .W (1),
-        .N (V)
-    )full_mux2
-    (
-        .in  (full_muxout1),
-        .out (full_muxout2),
-        .sel (assigned_ovc_num)
-    );
-    	 
-   wire [V-1 : 0]  nearlyfull_sel = (ovc_is_assigned | ~OVC_ALLOC_MODE)? assigned_ovc_num : granted_ovc_num ;// or (granted_ovc_num | ssa_granted_ovc_num) ?	
-   	
-    onehot_mux_1D #(
-        .W  (1),
-        .N  (V)
-    )nearlfull_mux2
-    (
-        .in  (nearly_full_muxout1),
-        .out (nearly_full_muxout2),
-        .sel (nearlyfull_sel)
-    );
-    
-   assign full_reg1_next    =    full_muxout2;
-   assign full_reg2_next    =    nearly_full_muxout2 & ivc_getting_sw_grant;
-   assign assigned_ovc_is_full    = (PCK_TYPE == "MULTI_FLIT")? full_reg1 | full_reg2: 1'b0;
-    
-   pronoc_register #(.W(1)) reg1 (.in(full_reg1_next ), .out(full_reg1), .reset(reset), .clk(clk));
-   pronoc_register #(.W(1)) reg2 (.in(full_reg2_next ), .out(full_reg2), .reset(reset), .clk(clk));
-   
-  
- 
+    localparam
+        P_1 = (SELF_LOOP_EN )?  P : P-1,
+        VP_1 = V * P_1;
+    input clk,reset;
+    input ovc_is_assigned;
+    input [V-1 : 0]  assigned_ovc_num,granted_ovc_num,ssa_granted_ovc_num;
+    input [P_1-1 : 0] dest_port;
+    input [VP_1-1 : 0] full;
+    input [VP_1-1 : 0] credit_increased;
+    input [VP_1-1 : 0] nearly_full;
+    input  ivc_getting_sw_grant;
+    output assigned_ovc_is_full;
+    
+    wire [VP_1-1 : 0] full_muxin1,nearly_full_muxin1;
+    logic [V-1 : 0] full_muxout1,nearly_full_muxout1;
+    wire full_muxout2,nearly_full_muxout2;
+    logic full_reg1,full_reg2;
+    wire  full_reg1_next,full_reg2_next;
+    wire [V-1: 0] full_muxin1_array [P_1-1 : 0];
+    wire [V-1: 0] nearly_full_muxin1_array [P_1-1 : 0];
+    
+    assign full_muxin1  = full & (~credit_increased);
+    assign nearly_full_muxin1 = nearly_full & (~credit_increased);
     
+    genvar i;
+    generate for(i=0;i<P_1;i++) begin : V_
+        assign full_muxin1_array[i] = full_muxin1[(i*V)+:V];
+        assign nearly_full_muxin1_array[i] = nearly_full_muxin1[(i*V)+:V];
+    end endgenerate
+    //Onehot mux to select full signal
+    always_comb begin
+        full_muxout1 = '0;
+        nearly_full_muxout1 = '0;
+        for (int k = 0; k < P_1; k++) begin
+            full_muxout1 |= (dest_port[k]) ? full_muxin1_array[k] : '0;
+            nearly_full_muxout1 |= (dest_port[k]) ? nearly_full_muxin1_array[k] : '0;
+        end
+    end//always
+    // assigned ovc mux
+    assign full_muxout2 = |(full_muxout1 & assigned_ovc_num);
+    wire [V-1 : 0]  nearlyfull_sel = (ovc_is_assigned | ~OVC_ALLOC_MODE)? assigned_ovc_num : granted_ovc_num ;// or (granted_ovc_num | ssa_granted_ovc_num) ?    
+    assign nearly_full_muxout2 =|(nearly_full_muxout1 & nearlyfull_sel);
+    
+    assign full_reg1_next = full_muxout2;
+    assign full_reg2_next = nearly_full_muxout2 & ivc_getting_sw_grant;
+    assign assigned_ovc_is_full = (PCK_TYPE == "MULTI_FLIT")? full_reg1 | full_reg2: 1'b0;
+    
+    always_ff @ (`pronoc_clk_reset_edge) begin
+        if (`pronoc_reset) begin
+            full_reg1 <= 1'b0;
+            full_reg2 <= 1'b0;
+        end else begin
+            full_reg1 <= full_reg1_next;
+            full_reg2 <= full_reg2_next;
+        end
+    end
 endmodule
 
-
-//synthesis translate_off
-//synopsys  translate_off
+`ifdef SIMULATION
 module check_ovc #(
     parameter V = 4, // vc_num_per_port
-    parameter P    = 5, // router port num
-    parameter SELF_LOOP_EN="NO"
-    
+    parameter P = 5, // router port num
+    parameter SELF_LOOP_EN=0
 )(
     ovc_status,
     assigned_ovc_num_all,
@@ -749,69 +591,48 @@ module check_ovc #(
     clk,
     reset
 );
-
-    localparam      PV        =    V        *    P,
-                    PVV     =    PV        *  V,    
-                    P_1        =   ( SELF_LOOP_EN=="NO")?  P-1 : P,
-                    PVP_1    =    PV        *    P_1;
-
-
-    input    [PV-1        :    0]    ovc_status;
-    input [PVV-1    :    0]    assigned_ovc_num_all;
-    input [PV-1        :    0]    ovc_is_assigned_all;
-    input    [PVP_1-1    :    0]    dest_port_all;
+    localparam
+        PV = V *  P,
+        PVV = PV * V,
+        P_1 = (SELF_LOOP_EN )?  P : P-1,
+        PVP_1 = PV * P_1;
+    
+    input [PV-1 : 0] ovc_status;
+    input [PVV-1 : 0] assigned_ovc_num_all;
+    input [PV-1 : 0] ovc_is_assigned_all;
+    input [PVP_1-1 : 0] dest_port_all;
     input clk,reset;
+    wire [V-1 : 0] assigned_ovc_num [PV-1 : 0];
+    wire [P_1-1 : 0] destport_sel [PV-1 : 0];
+    logic [P-1 : 0]  destport_num [PV-1 : 0];
+    wire [PV-1 : 0] ovc_num [PV-1 : 0];
+    
+    //add_sw_loc_one_hot 
+    always_comb begin 
+        for(int m=0; m < PV; m++) begin 
+            if (SELF_LOOP_EN == 0) begin
+                for(int k=0; k<P; k++) begin 
+                    if (k>m/V) destport_num[m][k] = destport_sel[m][k-1];
+                    else if (k==m/V)  destport_num[m][k] = 1'b0;
+                    else destport_num[m][k] = destport_sel[m][k];
+                end//for 
+            end else destport_num[m][P_1-1 : 0] = destport_sel[m];
+        end 
+    end//always
     
-    wire [V-1        :    0] assigned_ovc_num    [PV-1        :    0];
-    wire [P_1-1        :    0]    destport_sel        [PV-1        :    0];
-    wire [P-1        :    0]    destport_num        [PV-1        :    0];
-    
-    wire [PV-1        :    0] ovc_num                [PV-1        :    0];
-    genvar i;
+    genvar i,j;
     generate
     for(i=0; i<PV;i=i+1) begin :lp_pv
-        assign assigned_ovc_num [i]= (ovc_is_assigned_all[i])? assigned_ovc_num_all[(i+1)*V-1    :    i*V]: 0;
-        assign destport_sel        [i]= dest_port_all[(i+1)*P_1-1    :    i*P_1];    
-        
-        if(SELF_LOOP_EN=="NO") begin : nslp
-	        add_sw_loc_one_hot #(
-	            .P(P),
-	            .SW_LOC(i/V)
-	        )
-	        add_sw_loc
-	        (
-	            .destport_in(destport_sel[i]),
-	            .destport_out(destport_num[i])
-	        );
-        end else begin :slp
-        	assign destport_num[i] = destport_sel[i];        	
+        assign assigned_ovc_num [i]= (ovc_is_assigned_all[i])? assigned_ovc_num_all[(i+1)*V-1 : i*V]: {V{1'b0}};
+        assign destport_sel [i]= dest_port_all[(i+1)*P_1-1 : i*P_1];
+        //Onehot demultiplexer
+        for (j = 0; j < P; j++) begin : P_
+            assign ovc_num[i][j*V +: V] = (destport_num[i][j]==1'b1) ? assigned_ovc_num[i] : {V{1'b0}};
+        end
+        always @(posedge clk)begin 
+            if(ovc_status >0 && ovc_num[i] >0 && (ovc_num[i] & ovc_status)==0) $display ("%t: Error: OVC status%d missmatch:%b & %b, %m  ",$time,i,ovc_num[i] , ovc_status);
         end
-            
-        
-    
-                
-        one_hot_demux    #(
-            .IN_WIDTH    (V),
-            .SEL_WIDTH    (P)
-        
-        ) demux
-        (
-            .demux_sel    (destport_num[i]),//selectore
-            .demux_in    (assigned_ovc_num[i]),//repeated
-            .demux_out    (ovc_num[i])
-        );
-    always @(posedge clk)begin 
-        if(ovc_status >0 && ovc_num[i] >0 && (ovc_num[i] & ovc_status)==0) $display ("%t    :Error: OVC status%d missmatch:%b & %b, %m  ",$time,i,ovc_num[i] , ovc_status);
-    end
-    
-    
     end//for
     endgenerate
-    
-    
-    
-
 endmodule
-//synopsys  translate_on
-//synthesis translate_on
-
+`endif
diff --git a/mpsoc/rtl/src_noc/ovc_list.sv b/mpsoc/rtl/src_noc/ovc_list.sv
new file mode 100755
index 0000000..ab3d4dc
--- /dev/null
+++ b/mpsoc/rtl/src_noc/ovc_list.sv
@@ -0,0 +1,83 @@
+`include "pronoc_def.v"
+/**********************************************************************
+**    File: ovc_list.sv
+**    
+**    Copyright (C) 2014-2017  Alireza Monemi
+**    
+**    This file is part of ProNoC 
+**
+**    ProNoC ( stands for Prototype Network-on-chip)  is free software: 
+**    you can redistribute it and/or modify it under the terms of the GNU
+**    Lesser General Public License as published by the Free Software Foundation,
+**    either version 2 of the License, or (at your option) any later version.
+**
+**     ProNoC is distributed in the hope that it will be useful, but WITHOUT
+**     ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+**     or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
+**     Public License for more details.
+**
+**     You should have received a copy of the GNU Lesser General Public
+**     License along with ProNoC. If not, see <http:**www.gnu.org/licenses/>.
+**
+**
+**    Description: 
+**      This module provides a list of available output VCs for the allocator
+*************************************/
+module ovc_list (
+    class_in,
+    ovcs_out
+);
+    import pronoc_pkg::*;
+    
+    input [Cw-1 : 0] class_in;
+    output[V-1 : 0] ovcs_out;
+    function automatic logic [V-1:0] get_vc_list_section(input int c);
+    begin
+        logic [CVw-1 : 0] shiftted = CLASS_SETTING >> c*V;
+        return shiftted[V-1 : 0];
+    end
+    endfunction
+    //Masks VCs acording to message classes
+    logic [V-1 : 0] class_table [C-1 : 0];
+    logic [V-1 : 0] ovc_message_class;
+    always_comb begin
+        for(int i=0; i<C; i++) class_table[i] = get_vc_list_section(i);
+    end
+    assign  ovcs_out= (C == 0 || C == 1)? {V{1'b1}} : class_table[class_in];
+endmodule
+
+
+module vc_priority_based_dest_port #(
+    parameter P=5,
+    parameter V=4
+)(
+    dest_port,
+    vc_pririty
+);
+    localparam
+        P_1 =  (P-1),
+        OFFSET =  V/(P_1);
+    
+    input   [P_1-1 : 0] dest_port;
+    output  [V-1   : 0] vc_pririty;
+    
+    logic [V-1:0] vc_pririty_init;
+    always_comb begin
+        if (P_1 == V) begin
+            vc_pririty_init = dest_port;
+        end else if (P_1 > V) begin
+            // P_1 > V
+            for (int i = 0; i < V; i++) begin
+                vc_pririty_init[i] = |dest_port[((i+1)*P_1)/V - 1 -: ((P_1)/V)];
+                // Note: Using part-select with width (P_1/V) for clarity
+            end
+        end else begin
+            // P_1 < V
+            vc_pririty_init = '0;
+            for (int j = 0; j < P_1; j++) begin
+                vc_pririty_init[j + OFFSET] = dest_port[j];
+            end
+        end
+    end
+    assign vc_pririty = (vc_pririty_init == 0) ? {{(V-1){1'b0}}, 1'b1} : vc_pririty_init;
+endmodule
diff --git a/mpsoc/rtl/src_noc/packet_injector.sv b/mpsoc/rtl/src_noc/packet_injector.sv
index ccfdfcc..82ec1de 100644
--- a/mpsoc/rtl/src_noc/packet_injector.sv
+++ b/mpsoc/rtl/src_noc/packet_injector.sv
@@ -1,692 +1,617 @@
 `include "pronoc_def.v"
+/**********************************************************************
+**    File: packet_injector.sv
+**    
+**    Copyright (C) 2014-2017  Alireza Monemi
+**    
+**    This file is part of ProNoC 
+**
+**    ProNoC ( stands for Prototype Network-on-chip)  is free software: 
+**    you can redistribute it and/or modify it under the terms of the GNU
+**    Lesser General Public License as published by the Free Software Foundation,
+**    either version 2 of the License, or (at your option) any later version.
+**
+**     ProNoC is distributed in the hope that it will be useful, but WITHOUT
+**     ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+**     or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
+**     Public License for more details.
+**
+**     You should have received a copy of the GNU Lesser General Public
+**     License along with ProNoC. If not, see <http:**www.gnu.org/licenses/>.
+**
+**
+**    Description: 
+**    This module is responsible for injecting and ejecting packets 
+**    within the NoC router. It allows the simulation of real application 
+**    traffic by injecting pre-recorded trace data into the NoC, enabling 
+**    performance and functionality testing of NoC components under realistic 
+**    conditions.
+**
+**    It can also be used to verify the NoC's ability to handle various 
+**    traffic patterns, including stress testing with synthetic or real 
+**    application traces.
+**************************************************************/
 
-/****************************
- * This module can inject and eject packets from the NoC.
- * It can be used in simulation for injecting real application traces to the NoC 
- * *************************/
-
-
-module packet_injector #(
-	parameter NOC_ID=0
-) (
-	//general
-	current_e_addr,
-	reset,
-	clk,		
-	//noc port
-	chan_in,
-	chan_out,  
-	//control interafce
-	pck_injct_in,
-	pck_injct_out		
+module packet_injector  (
+    //general
+    current_e_addr,
+    reset,
+    clk,
+    //noc port
+    chan_in,
+    chan_out,
+    //control interafce
+    pck_injct_in,
+    pck_injct_out
 );
-	
-	`NOC_CONF
-	
-	//general
-	input reset,clk;
-	input [EAw-1 :0 ] current_e_addr;
-	
-	// the destination endpoint address
-	//NoC interface
-	input   smartflit_chanel_t 	chan_in;
-	output  smartflit_chanel_t 	chan_out;	
-	//control interafce
-	
-	input   pck_injct_t pck_injct_in;
-	output  pck_injct_t pck_injct_out;
-	
-	
-	wire  [RAw-1 :0 ] current_r_addr;    
-	
-	wire  [DSTPw-1 : 0 ] destport;   
-	reg flit_wr;
-	
-	
-	
-	
-		
-	
-	assign current_r_addr = chan_in.ctrl_chanel.neighbors_r_addr;
-	
-	
-	generate if(CAST_TYPE == "UNICAST") begin : uni 
-	
-			conventional_routing #(
-					.NOC_ID(NOC_ID),
-					.TOPOLOGY(TOPOLOGY),
-					.ROUTE_NAME(ROUTE_NAME),
-					.ROUTE_TYPE(ROUTE_TYPE),
-					.T1(T1),
-					.T2(T2),
-					.T3(T3),
-					.RAw(RAw),
-					.EAw(EAw),
-					.DSTPw(DSTPw),
-					.LOCATED_IN_NI(1)
-				)
-				routing_module
-				(
-					.reset(reset),
-					.clk(clk),
-					.current_r_addr(current_r_addr),
-					.dest_e_addr(pck_injct_in.endp_addr),
-					.src_e_addr(current_e_addr),
-					.destport(destport)
-				);
-		end endgenerate
-	
-	
-	localparam 
-		HDR_BYTE_NUM =	HDR_MAX_DATw / 8, // = HDR_MAX_DATw / (8 - HDR_MAX_DATw %8)
-		HDR_DATA_w_tmp   =  HDR_BYTE_NUM * 8,
-		HDR_DATA_w = 
-		(PCK_INJ_Dw < HDR_DATA_w_tmp)? PCK_INJ_Dw :
-		(HDR_DATA_w_tmp==0)? 1: HDR_DATA_w_tmp;
-
-	wire [HDR_DATA_w-1 : 0]	hdr_data_in = pck_injct_in.data [HDR_DATA_w-1 : 0];
-	wire [Fw-1 : 0] hdr_flit_out;
-	
-	header_flit_generator #(
-		.NOC_ID(NOC_ID),
-		.DATA_w(HDR_DATA_w)				
-	) the_header_flit_generator (
-		.flit_out			(hdr_flit_out),
-		.vc_num_in			(pck_injct_in.vc),
-		.class_in			(pck_injct_in.class_num),
-		.dest_e_addr_in		(pck_injct_in.endp_addr),
-		.src_e_addr_in		(current_e_addr),
-		.weight_in			(pck_injct_in.init_weight),
-		.destport_in		(destport),
-		.data_in			(hdr_data_in),
-		.be_in({BEw{1'b1}} )// Be is not used in simulation as we dont sent real data
-	);
-	
-	
-	localparam 
-		REMAIN_DATw =  PCK_INJ_Dw - HDR_DATA_w,
-		REMAIN_DAT_FLIT_I = (REMAIN_DATw / Fpay),
-		REMAIN_DAT_FLIT_F = (REMAIN_DATw % Fpay == 0)? 0 : 1,
-		REMAIN_DAT_FLIT   = REMAIN_DAT_FLIT_I + REMAIN_DAT_FLIT_F,
-		CNTw = log2(REMAIN_DAT_FLIT),
-		MIN_PCK_SIZ = REMAIN_DAT_FLIT +1;
-		
-	
-	logic [PCK_SIZw-1             :   0]  counter, counter_next;
-	logic [CNTw-1                 :   0]  counter2,counter2_next;
-	reg tail,head;	
-		
-	wire [Fpay -1 : 0]  remain_dat [REMAIN_DAT_FLIT -1 : 0];
-	wire [Fpay-1 : 0] dataIn =  remain_dat[counter2];
-	enum  bit [2:0] {HEADER, BODY,TAIL} flit_type,flit_type_next;
-		
-	
-	
-	wire [V-1 : 0]   wr_vc_send = (flit_wr)?   pck_injct_in.vc : {V{1'b0}};
-	wire [V-1 : 0]   vc_fifo_full;
-		
-	
-	wire noc_ready;
-		
-	localparam 
-		LAST_TMP =PCK_INJ_Dw -  (Fpay*REMAIN_DAT_FLIT_I)-HDR_DATA_w,
-		LASTw=(LAST_TMP==0)? Fpay : LAST_TMP;
-	genvar i;
-	generate 
-		for(i=0; i<REMAIN_DAT_FLIT_I; i++) begin :rem
-			assign remain_dat [i] = pck_injct_in.data [Fpay*(i+1)+HDR_DATA_w-1   : (Fpay*i)+HDR_DATA_w];				
-		end
-		if(REMAIN_DAT_FLIT_F ) begin :flt
-
-			assign remain_dat [REMAIN_DAT_FLIT_I][LASTw-1 : 0] = pck_injct_in.data [PCK_INJ_Dw-1   : (Fpay*REMAIN_DAT_FLIT_I)+HDR_DATA_w];				
-		end
-	endgenerate
-	
-		
-	
-		
-		
-	one_hot_mux #(
-			.IN_WIDTH   (V ), 
-			.SEL_WIDTH  (V ), 
-			.OUT_WIDTH  (1 )
-		) one_hot_mux1 (
-			.mux_in     (~ vc_fifo_full    ), 
-			.mux_out    (noc_ready   ), 
-			.sel        (pck_injct_in.vc       ));
-		
-		
-		
-		
-	always @ (*) begin 
-		counter_next = counter;
-		counter2_next =counter2;
-		flit_type_next =flit_type;
-		tail=1'b0;
-		head=1'b0;
-		flit_wr=0;
-		if(noc_ready)begin 
-			case(flit_type) 
-				HEADER:begin 
-					if(pck_injct_in.pck_wr)begin 
-						flit_wr=1;
-						counter_next = pck_injct_in.size-1;
-						counter2_next=0;
-						head=1'b1;
-						if(pck_injct_in.size == 1)begin
-							tail=1'b1;
-						end else if (pck_injct_in.size == 2) begin 
-							flit_type_next = TAIL;
-						end else begin 
-							flit_type_next = BODY;
-						end 
-					end
-				end
-				BODY: begin 
-					flit_wr=1;
-					counter_next = counter -1'b1;
-					counter2_next =counter2 +1'b1;
-					if(counter == 2) begin 							
-						flit_type_next = TAIL;
-					end
-				end
-				TAIL: begin						
-					flit_type_next = HEADER;
-					flit_wr=1;
-					tail=1'b1;
-				end
-				default: begin
-						
-				end	
-			endcase
-				
-		end
-	end
-		
-	logic [V-1 : 0] credit_o, credit_o_next;
-		
-	//pronoc_register #(.W(3),.RESET_TO(HEADER) ) reg1 (.in(flit_type_next ), .out(flit_type), .reset(reset), .clk(clk));
-	pronoc_register #(.W(PCK_SIZw)) reg2 (.in(counter_next ), .out(counter), .reset(reset), .clk(clk));
-	pronoc_register #(.W(CNTw))     reg3 (.in(counter2_next ), .out(counter2), .reset(reset), .clk(clk));
-	pronoc_register #(.W(V))     reg4 (.in(credit_o_next ), .out(credit_o), .reset(reset), .clk(clk));
-		
-		
-	always @ (*) begin 
-		credit_o_next = credit_o;				
-		if (chan_in.flit_chanel.flit_wr) credit_o_next =  chan_in.flit_chanel.flit.vc;
-		else credit_o_next = {V{1'b0}};		
-	end	
-		
-	always @(`pronoc_clk_reset_edge)begin 
-		if(`pronoc_reset) flit_type<=HEADER;
-		else flit_type <= flit_type_next;			
-	end
-	
-	
-		
-	injector_ovc_status #(
-			.V(V),
-			.B(LB),
-			.CRDTw(CRDTw)    
-		)
-		the_ovc_status
-		(
-			.credit_init_val_in ( chan_in.ctrl_chanel.credit_init_val),
-			.wr_in(wr_vc_send),
-			.credit_in(chan_in.flit_chanel.credit),
-			.full_vc(vc_fifo_full),
-			.nearly_full_vc( ),
-			.empty_vc( ),
-			.clk(clk),
-			.reset(reset)
-		);  	
-	
-	wire [HDR_DATA_w-1 : 0]	hdr_data_o;
-	hdr_flit_t hdr_flit_i;
-	
-	header_flit_info  #(
-		.NOC_ID (NOC_ID),	
-		.DATA_w (HDR_DATA_w)
-	) extractor (
-		.flit(chan_in.flit_chanel.flit),
-		.hdr_flit(hdr_flit_i),		
-		.data_o(hdr_data_o)    
-	);
-		
-	wire [PCK_INJ_Dw-1 : 0]  pck_data_o [V-1 : 0];
-	reg  [Fpay-1 : 0] pck_data_o_gen [V-1 : 0][REMAIN_DAT_FLIT : 0];
-	
-	genvar k;
-	
-	reg [PCK_SIZw-1 : 0] rsv_counter [V-1 : 0];
-	reg [EAw-1 : 0] sender_endp_addr_reg [V-1 : 0];
-	logic [15:0] h2t_counter [V-1 : 0];
-	logic [15:0] h2t_counter_next [V-1 : 0];	
-	
-	//synthesis translate_off
-	wire [NEw-1 : 0] current_id; 
-	wire [NEw-1 : 0] sendor_id; 
-	endp_addr_decoder #( .TOPOLOGY(TOPOLOGY), .T1(T1), .T2(T2), .T3(T3), .EAw(EAw),  .NE(NE)) encode1 ( .id(current_id), .code(current_e_addr));
-	endp_addr_decoder #( .TOPOLOGY(TOPOLOGY), .T1(T1), .T2(T2), .T3(T3), .EAw(EAw),  .NE(NE)) encode2 ( .id(sendor_id), .code(pck_injct_out.endp_addr[EAw-1 : 0]));
-	//synthesis translate_on
-	
-	wire [NE-1 :0] dest_mcast_all_endp;
-	
-	
-	
-	
-	generate 
-		if(CAST_TYPE != "UNICAST") begin
-			mcast_dest_list_decode #(
-				.NOC_ID(NOC_ID)
-			) decode (
-				.dest_e_addr(hdr_flit_i.dest_e_addr),
-				.dest_o(dest_mcast_all_endp),
-				.row_has_any_dest(),
-				.is_unicast()
-			);
-		end
-		
-		for(i=0; i<V; i++) begin: V_ 
-			always@(*) begin
-				h2t_counter_next[i]=h2t_counter[i]+1'b1;
-				if(chan_in.flit_chanel.flit.vc[i] & chan_in.flit_chanel.flit_wr & chan_in.flit_chanel.flit.hdr_flag)begin 
-					h2t_counter_next[i]= 16'd0; // reset once header flit is received
-				end//hdr flit wr
-			end//always
-			
-			
-			
-			
-			always @ (`pronoc_clk_reset_edge )begin 
-				if(`pronoc_reset)  begin
-					rsv_counter[i]<= {PCK_SIZw{1'b0}};
-					h2t_counter[i]<= 16'd0;
-					sender_endp_addr_reg [i]<= {EAw{1'b0}};
-				end else begin 
-					h2t_counter[i]<=h2t_counter_next[i];
-					if(chan_in.flit_chanel.flit.vc[i] & chan_in.flit_chanel.flit_wr ) begin 
-						if(chan_in.flit_chanel.flit.hdr_flag)begin						
-							rsv_counter[i]<= {{(PCK_SIZw-1){1'b0}}, 1'b1};
-							sender_endp_addr_reg [i]<= hdr_flit_i.src_e_addr; 
-							//synthesis translate_off
-							if(CAST_TYPE == "UNICAST") begin
-								if(hdr_flit_i.dest_e_addr[EAw-1:0] != current_e_addr) begin 
-									$display("%t: ERROR: packet destination address %d does not match receiver endp address %d. %m",$time,hdr_flit_i.dest_e_addr , current_e_addr );
-									$finish;
-								end//if hdr_flit_i
-							end else begin 
-								if(dest_mcast_all_endp[current_id] !=1'b1 ) begin 
-									$display("%t: ERROR: packet destination address %b does not match receiver endp address %d. %m",$time,hdr_flit_i.dest_e_addr , current_e_addr ,current_id );
-									$finish;
-								end
-							end//if hdr_flit_i
-							//synthesis translate_on	
-						end //if hdr_flag
-						else rsv_counter[i]<= rsv_counter[i]+1'b1;						
-					end//flit wr					
-				end//reset
-			end//always
-			
-			
-				
-
-			for (k=0;k< REMAIN_DAT_FLIT+1;k++)begin : K_
-			
-				always @ (`pronoc_clk_reset_edge )begin 
-					if(`pronoc_reset)  begin
-						pck_data_o_gen [i][k] <= {Fpay{1'b0}};
-						
-					end else begin
-						if(chan_in.flit_chanel.flit.vc[i] & chan_in.flit_chanel.flit_wr ) begin 
-							if (chan_in.flit_chanel.flit.hdr_flag )begin 
-								if ( k ==0 ) pck_data_o_gen [i][k][HDR_DATA_w-1 : 0] <= hdr_data_o;														
-							end
-							else begin 
-								if (rsv_counter[i] == k ) pck_data_o_gen [i][k] <= chan_in.flit_chanel.flit.payload[Fpay-1 : 0];
-								
-							end // else
-						end //if
-					end //else
-				end// always
-					
-				if   (k == 0 ) assign pck_data_o [i][HDR_DATA_w-1 : 0] = pck_data_o_gen [i][0][HDR_DATA_w-1 : 0];
-				else if (k == REMAIN_DAT_FLIT) assign pck_data_o [i][PCK_INJ_Dw-1 :    (k-1)*Fpay+ HDR_DATA_w] = pck_data_o_gen [i][k][LASTw-1: 0];	
-				else assign pck_data_o [i][(k)*Fpay+HDR_DATA_w -1 : (k-1)*Fpay+ HDR_DATA_w] = pck_data_o_gen [i][k];	
-					
-			end //for k
-			
-			
-			//synthesis translate_off
-			always @(posedge clk) begin 
-				if((pck_injct_out.ready[i] == 1'b0 ) & pck_injct_in.vc[i] & pck_injct_in.pck_wr )begin 
-					$display("%t: ERROR: a packet injection request is recived in core(%d), vc (%d) while packet injectore was not ready. %m",$time,current_id,i);
-					$finish;
-				end
-		
-			end	
-			//synthesis translate_on
-	
-	
-			
-					
-		end//for i			
-	endgenerate
-	
-	wire [V-1 : 0] vc_reg;
-	wire tail_flag_reg, hdr_flag_reg;
-	
-	
-	pronoc_register #(.W(V))   register1 (.in(chan_in.flit_chanel.flit.vc),        .reset  (reset ), .clk (clk),.out(vc_reg));
-	pronoc_register #(.W(1))   register2 (.in(chan_in.flit_chanel.flit.hdr_flag),	.reset  (reset ), .clk (clk),.out(hdr_flag_reg));
-	pronoc_register #(.W(1))   register3 (.in(chan_in.flit_chanel.flit.tail_flag & chan_in.flit_chanel.flit_wr ),.reset  (reset ), .clk (clk),.out(tail_flag_reg));
-	
-	wire [Vw-1 : 0] vc_bin;
-	
-	one_hot_to_bin #(
-			.ONE_HOT_WIDTH  (V), 
-			.BIN_WIDTH      (Vw )
-		) one_hot_to_bin (
-			.one_hot_code   (vc_reg  ), 
-			.bin_code       (vc_bin      )
-		);
-
-	
-	assign pck_injct_out.data  =  pck_data_o[vc_bin];
-	assign pck_injct_out.size  =  rsv_counter[vc_bin];
-	assign pck_injct_out.h2t_delay = h2t_counter[vc_bin];
-	assign pck_injct_out.ready = (flit_type == HEADER)?  ~vc_fifo_full : {V{1'b0}};	
-	assign pck_injct_out.endp_addr[EAw-1 : 0] =  sender_endp_addr_reg[vc_bin];
-	assign pck_injct_out.vc = vc_reg;
-	assign pck_injct_out.pck_wr = tail_flag_reg;  	
-	
-	assign chan_out.flit_chanel.flit.hdr_flag =head;
-	assign chan_out.flit_chanel.flit.tail_flag=tail;
-	assign chan_out.flit_chanel.flit.vc=pck_injct_in.vc;
-	assign chan_out.flit_chanel.flit_wr=flit_wr;
-    
-	generate 
-	/* verilator lint_off WIDTH */
-		if(PCK_TYPE == "SINGLE_FLIT" ) begin : single_f
-			/* verilator lint_on WIDTH */
-			assign chan_out.flit_chanel.flit.payload = hdr_flit_out[FPAYw-1 : 0];
-		end else begin	
-			assign chan_out.flit_chanel.flit.payload = (flit_type==	HEADER)? hdr_flit_out[Fpay-1 : 0] : dataIn;
-		end
-	endgenerate
-	
-	assign chan_out.smart_chanel = {SMART_CHANEL_w{1'b0}};
-	assign chan_out.flit_chanel.congestion = {CONGw{1'b0}};
-	assign chan_out.flit_chanel.credit= credit_o;	
-	assign chan_out.ctrl_chanel.credit_init_val= LB;	
-	assign chan_out.ctrl_chanel.credit_release_en={V{1'b0}};
-	assign chan_out.ctrl_chanel.endp_port =1'b1;
-	
-	
-	
-	distance_gen #(
-			.TOPOLOGY(TOPOLOGY),
-			.T1(T1),
-			.T2(T2),
-			.T3(T3),
-			.EAw(EAw),
-			.DISTw(DISTw)
-		)
-		the_distance_gen
-		(
-			.src_e_addr(sender_endp_addr_reg[vc_bin]),
-			.dest_e_addr(current_e_addr),
-			.distance(pck_injct_out.distance)
-		);
-	
-	
-	
-	
-	
-	
-	//synthesis translate_off
-	//`define MONITOR_RSV_DAT
-	
-
-	
-	always @(posedge clk) begin 
-		if((pck_injct_in.vc == {V{1'b0}} ) & pck_injct_in.pck_wr )begin 
-			$display("%t: ERROR: a packet injection request is recived while vc is not set. %m",$time);
-			$finish;
-		end
-		if(pck_injct_in.pck_wr && (pck_injct_in.size<MIN_PCK_SIZ[PCK_SIZw-1 : 0])) begin 
-			$display("%t: ERROR: requested %d flit packet size is smaller than minimum %d flits to send %d bits of data. %m",$time,pck_injct_in.size,MIN_PCK_SIZ, PCK_INJ_Dw );
-			$finish;
-		end
-		
-		`ifdef MONITOR_RSV_DAT
-		
-			
-			if(pck_injct_in.pck_wr) begin 
-				$display ("pck_inj(%d) send a packet:  size=%d, data=%h, v=%h",current_id,
-						pck_injct_in.size, pck_injct_in.data,pck_injct_in.vc);
-			end	
-			
-			if(pck_injct_out.pck_wr) begin 
-				$display ("pck_inj(%d) got a packet: source=%d, size=%d, data=%h",current_id,
-						sendor_id,pck_injct_out.size,pck_injct_out.data);
-			end	
-		
-		
-		`endif
-		
-	end	
-	
-	
-	//synthesis translate_on
-	
-	
-	
-	
-	
+    
+    import pronoc_pkg::*;
+    
+    //general
+    input reset,clk;
+    input [EAw-1 :0 ] current_e_addr;
+    
+    // the destination endpoint address
+    //NoC interface
+    input   smartflit_chanel_t chan_in;
+    output  smartflit_chanel_t chan_out;
+    //control interafce
+    
+    input   pck_injct_t pck_injct_in;
+    output  pck_injct_t pck_injct_out;
+    
+    wire  [RAw-1 :0 ] current_r_addr;
+    wire  [DSTPw-1 : 0 ] destport;
+    reg flit_wr;
+    
+    assign current_r_addr = chan_in.ctrl_chanel.router_addr;
+    
+    generate 
+    if((CAST_TYPE == "UNICAST") && (IS_LOOKAHEAD==1'b1)) begin : uni
+    //The router is configured with lookaheadrouting. 
+    //The header flit is supposed to carry the destinaion output port
+        conventional_routing #(
+            .LOCATED_IN_NI(1)
+        ) routing_module (
+            .reset(reset),
+            .clk(clk),
+            .current_r_addr(current_r_addr),
+            .dest_e_addr(pck_injct_in.endp_addr),
+            .src_e_addr(current_e_addr),
+            .destport(destport)
+        );
+    end 
+    endgenerate
+    
+    localparam 
+        HDR_BYTE_NUM = HDR_MAX_DATw / 8, // = HDR_MAX_DATw / (8 - HDR_MAX_DATw %8)
+        HDR_DATA_w_tmp = HDR_BYTE_NUM * 8,
+        HDR_DATA_w = 
+            (PCK_INJ_Dw < HDR_DATA_w_tmp)? PCK_INJ_Dw :
+            (HDR_DATA_w_tmp==0)? 1: HDR_DATA_w_tmp;
+    localparam 
+        REMAIN_DATw =  PCK_INJ_Dw - HDR_DATA_w,
+        REMAIN_DAT_FLIT_I = (REMAIN_DATw / Fpay),
+        REMAIN_DAT_FLIT_F = (REMAIN_DATw % Fpay == 0)? 0 : 1,
+        REMAIN_DAT_FLIT   = REMAIN_DAT_FLIT_I + REMAIN_DAT_FLIT_F,
+        CNTw = log2(REMAIN_DAT_FLIT),
+        MIN_PCK_SIZ = REMAIN_DAT_FLIT +1;
+    localparam 
+        LAST_TMP =PCK_INJ_Dw -  (Fpay*REMAIN_DAT_FLIT_I)-HDR_DATA_w,
+        LASTw=(LAST_TMP==0)? Fpay : LAST_TMP;
+    
+    wire [HDR_DATA_w-1 : 0] hdr_data_in = pck_injct_in.data [HDR_DATA_w-1 : 0];
+    wire [Fw-1 : 0] hdr_flit_out;
+    
+    header_flit_generator #(
+        .DATA_w(HDR_DATA_w)
+    ) the_header_flit_generator (
+        .flit_out(hdr_flit_out),
+        .vc_num_in(pck_injct_in.vc),
+        .class_in(pck_injct_in.class_num),
+        .dest_e_addr_in(pck_injct_in.endp_addr),
+        .src_e_addr_in(current_e_addr),
+        .weight_in(pck_injct_in.init_weight),
+        .destport_in(destport),
+        .data_in(hdr_data_in),
+        .be_in({BEw{1'b1}} )// Be is not used in simulation as we dont sent real data
+    );
+    
+    logic [PCK_SIZw-1 : 0]  counter, counter_next;
+    logic [CNTw-1 : 0]  counter2,counter2_next;
+    reg tail,head;
+    
+    wire [Fpay -1 : 0]  remain_dat [REMAIN_DAT_FLIT -1 : 0];
+    wire [Fpay-1 : 0] dataIn =  remain_dat[counter2];
+    enum  bit [2:0] {HEADER, BODY, TAIL_ST} flit_type,flit_type_next;
+    
+    wire [V-1 : 0]   wr_vc_send = (flit_wr)?   pck_injct_in.vc : {V{1'b0}};
+    wire [V-1 : 0]   vc_fifo_full;
+    
+    wire noc_ready;
+    
+    genvar i,k;
+    generate 
+        for(i=0; i<REMAIN_DAT_FLIT_I; i++) begin :rem
+            assign remain_dat [i] = pck_injct_in.data [Fpay*(i+1)+HDR_DATA_w-1   : (Fpay*i)+HDR_DATA_w];
+        end
+        if(REMAIN_DAT_FLIT_F ) begin :flt
+            assign remain_dat [REMAIN_DAT_FLIT_I][LASTw-1 : 0] = pck_injct_in.data [PCK_INJ_Dw-1   : (Fpay*REMAIN_DAT_FLIT_I)+HDR_DATA_w];
+        end
+    endgenerate
+    
+    one_hot_mux #(
+        .IN_WIDTH (V), 
+        .SEL_WIDTH (V), 
+        .OUT_WIDTH (1)
+    ) one_hot_mux1 (
+        .mux_in (~ vc_fifo_full), 
+        .mux_out (noc_ready), 
+        .sel (pck_injct_in.vc)
+    );
+    
+    always_comb begin 
+        counter_next = counter;
+        counter2_next =counter2;
+        flit_type_next =flit_type;
+        tail=1'b0;
+        head=1'b0;
+        flit_wr=0;
+        if(noc_ready)begin 
+            case(flit_type) 
+                HEADER:begin 
+                    if(pck_injct_in.pck_wr)begin 
+                        flit_wr=1;
+                        counter_next = pck_injct_in.size-1;
+                        counter2_next=0;
+                        head=1'b1;
+                        if(pck_injct_in.size == 1)begin
+                            tail=1'b1;
+                        end else if (pck_injct_in.size == 2) begin 
+                            flit_type_next = TAIL_ST;
+                        end else begin 
+                            flit_type_next = BODY;
+                        end 
+                    end
+                end
+                BODY: begin 
+                    flit_wr=1;
+                    counter_next = counter -1'b1;
+                    counter2_next =counter2 +1'b1;
+                    if(counter == 2) begin
+                        flit_type_next = TAIL_ST;
+                    end
+                end
+                TAIL_ST: begin
+                    flit_type_next = HEADER;
+                    flit_wr=1;
+                    tail=1'b1;
+                end
+                default: begin
+                    
+                end
+            endcase
+            
+        end
+    end
+    
+    logic [V-1 : 0] credit_o, credit_o_next;
+    always_ff @ (`pronoc_clk_reset_edge) begin
+        if (`pronoc_reset) begin
+            counter  <= '0;
+            counter2 <= '0;
+            credit_o <= '0;
+            flit_type <= HEADER;
+        end else begin
+            counter  <= counter_next;
+            counter2 <= counter2_next;
+            credit_o <= credit_o_next;
+            flit_type <= flit_type_next;
+        end
+    end
+    
+    always_comb begin
+        credit_o_next = credit_o;
+        if (chan_in.flit_chanel.flit_wr) credit_o_next =  chan_in.flit_chanel.flit.vc;
+        else credit_o_next = {V{1'b0}};
+    end 
+    injector_ovc_status #(
+        .V(V),
+        .B(LB),
+        .CRDTw(CRDTw)
+    ) the_ovc_status (
+        .credit_init_val_in ( chan_in.ctrl_chanel.credit_init_val),
+        .wr_in(wr_vc_send),
+        .credit_in(chan_in.flit_chanel.credit),
+        .full_vc(vc_fifo_full),
+        .nearly_full_vc( ),
+        .empty_vc( ),
+        .clk(clk),
+        .reset(reset)
+    );
+    
+    wire [HDR_DATA_w-1 : 0]    hdr_data_o;
+    hdr_flit_t hdr_flit_i;
+    
+    header_flit_info  #(
+        .DATA_w (HDR_DATA_w)
+    ) extractor (
+        .flit(chan_in.flit_chanel.flit),
+        .hdr_flit(hdr_flit_i),
+        .data_o(hdr_data_o)
+    );
+    
+    wire [PCK_INJ_Dw-1 : 0]  pck_data_o [V-1 : 0];
+    reg  [Fpay-1 : 0] pck_data_o_gen [V-1 : 0][REMAIN_DAT_FLIT : 0];    
+    
+    reg [PCK_SIZw-1 : 0] rsv_counter [V-1 : 0];
+    reg [EAw-1 : 0] sender_endp_addr_reg [V-1 : 0];
+    logic [Cw-1 : 0] sender_class_reg [V-1 : 0];
+    logic [15:0] h2t_counter [V-1 : 0];
+    logic [15:0] h2t_counter_next [V-1 : 0];
+    
+    `ifdef SIMULATION
+    wire [NEw-1 : 0] current_id; 
+    wire [NEw-1 : 0] sendor_id; 
+    endp_addr_decoder encode1 ( .id_out(current_id), .code_in(current_e_addr));
+    endp_addr_decoder encode2 ( .id_out(sendor_id), .code_in(pck_injct_out.endp_addr[EAw-1 : 0]));
+    `endif
+    
+    wire [NE-1 :0] dest_mcast_all_endp;   
+    
+    generate 
+    if(CAST_TYPE != "UNICAST") begin
+        mcast_dest_list_decode decode (
+            .dest_e_addr(hdr_flit_i.dest_e_addr),
+            .dest_o(dest_mcast_all_endp),
+            .row_has_any_dest(),
+            .is_unicast()
+        );
+    end
+    
+    for(i=0; i<V; i++) begin: V_
+        always@(*) begin
+            h2t_counter_next[i]=h2t_counter[i]+1'b1;
+            if(chan_in.flit_chanel.flit.vc[i] & chan_in.flit_chanel.flit_wr & chan_in.flit_chanel.flit.hdr_flag)begin 
+                h2t_counter_next[i]= 16'd0; // reset once header flit is received
+            end//hdr flit wr
+        end//always
+        
+        always @ (`pronoc_clk_reset_edge )begin 
+            if(`pronoc_reset)  begin
+                rsv_counter[i]<= {PCK_SIZw{1'b0}};
+                h2t_counter[i]<= 16'd0;
+                sender_endp_addr_reg [i]<= {EAw{1'b0}};
+                sender_class_reg [i]<= {Cw{1'b0}};
+            end else begin 
+                h2t_counter[i]<=h2t_counter_next[i];
+                if(chan_in.flit_chanel.flit.vc[i] & chan_in.flit_chanel.flit_wr ) begin 
+                    if(chan_in.flit_chanel.flit.hdr_flag)begin
+                        rsv_counter[i]<= {{(PCK_SIZw-1){1'b0}}, 1'b1};
+                        sender_endp_addr_reg [i] <= hdr_flit_i.src_e_addr;
+                        sender_class_reg [i] <= hdr_flit_i.message_class;
+                        `ifdef SIMULATION
+                        if(CAST_TYPE == "UNICAST") begin
+                            if(hdr_flit_i.dest_e_addr[EAw-1:0] != current_e_addr) begin 
+                                $display("%t: ERROR: packet destination address %d does not match receiver endp address %d. %m",$time,hdr_flit_i.dest_e_addr , current_e_addr );
+                                $finish;
+                            end//if hdr_flit_i
+                        end else begin 
+                            if(dest_mcast_all_endp[current_id] !=1'b1 ) begin 
+                                $display("%t: ERROR: packet destination address %b does not match receiver endp address %d. %m",$time,hdr_flit_i.dest_e_addr , current_e_addr ,current_id );
+                                $finish;
+                            end
+                        end//if hdr_flit_i
+                        `endif//SIMULATION
+                    end //if hdr_flag
+                    else rsv_counter[i]<= rsv_counter[i]+1'b1;
+                end//flit wr
+            end//reset
+        end//always
+        
+        for (k=0;k< REMAIN_DAT_FLIT+1;k++)begin : K_
+            
+            always @ (`pronoc_clk_reset_edge )begin 
+                if(`pronoc_reset)  begin
+                    pck_data_o_gen [i][k] <= {Fpay{1'b0}};
+                end else begin
+                    if(chan_in.flit_chanel.flit.vc[i] & chan_in.flit_chanel.flit_wr ) begin 
+                        if (chan_in.flit_chanel.flit.hdr_flag )begin 
+                            if ( k ==0 ) pck_data_o_gen [i][k][HDR_DATA_w-1 : 0] <= hdr_data_o;
+                        end else begin 
+                            if (rsv_counter[i] == k ) pck_data_o_gen [i][k] <= chan_in.flit_chanel.flit.payload[Fpay-1 : 0];
+                        end // else
+                    end //if
+                end //else
+            end// always
+            
+            if   (k == 0 ) assign pck_data_o [i][HDR_DATA_w-1 : 0] = pck_data_o_gen [i][0][HDR_DATA_w-1 : 0];
+            else if (k == REMAIN_DAT_FLIT) assign pck_data_o [i][PCK_INJ_Dw-1 :    (k-1)*Fpay+ HDR_DATA_w] = pck_data_o_gen [i][k][LASTw-1: 0];
+            else assign pck_data_o [i][(k)*Fpay+HDR_DATA_w -1 : (k-1)*Fpay+ HDR_DATA_w] = pck_data_o_gen [i][k];
+            
+        end //for k
+        
+        `ifdef SIMULATION
+        always @(posedge clk) begin 
+            if((pck_injct_out.ready[i] == 1'b0 ) & pck_injct_in.vc[i] & pck_injct_in.pck_wr )begin 
+                $display("%t: ERROR: a packet injection request is recived in core(%d), vc (%d) while packet injectore was not ready. %m",$time,current_id,i);
+                $finish;
+            end
+        end
+        `endif
+    
+    end//for i
+    endgenerate
+    
+    logic [V-1 : 0] vc_reg;
+    logic tail_flag_reg, hdr_flag_reg;
+    logic [DISTw-1:   0] distance;
+    
+    always_ff @ (`pronoc_clk_reset_edge) begin
+        if (`pronoc_reset) begin
+            vc_reg       <= '0;
+            hdr_flag_reg <= 1'b0;
+            tail_flag_reg<= 1'b0;
+        end else begin
+            vc_reg       <= chan_in.flit_chanel.flit.vc;
+            hdr_flag_reg <= chan_in.flit_chanel.flit.hdr_flag;
+            tail_flag_reg<= chan_in.flit_chanel.flit.tail_flag & chan_in.flit_chanel.flit_wr;
+        end
+    end
+    
+    wire [Vw-1 : 0] vc_bin;
+    
+    one_hot_to_bin #(
+        .ONE_HOT_WIDTH(V), 
+        .BIN_WIDTH(Vw )
+    ) one_hot_to_bin (
+        .one_hot_code(vc_reg), 
+        .bin_code(vc_bin)
+    );
+    always_comb begin
+        pck_injct_out.data  =  pck_data_o[vc_bin];
+        pck_injct_out.size  =  rsv_counter[vc_bin];
+        pck_injct_out.h2t_delay = h2t_counter[vc_bin];
+        pck_injct_out.ready = (flit_type == HEADER)?  ~vc_fifo_full : {V{1'b0}};
+        pck_injct_out.endp_addr[EAw-1 : 0] =  sender_endp_addr_reg[vc_bin];
+        pck_injct_out.class_num = sender_class_reg[vc_bin];
+        pck_injct_out.init_weight = WEIGHT_INIT;
+        pck_injct_out.vc = vc_reg;
+        pck_injct_out.pck_wr = tail_flag_reg;
+        pck_injct_out.distance = distance;
+        
+        chan_out.flit_chanel.flit.hdr_flag =head;
+        chan_out.flit_chanel.flit.tail_flag=tail;
+        chan_out.flit_chanel.flit.vc=pck_injct_in.vc;
+        chan_out.flit_chanel.flit_wr=flit_wr;
+        chan_out.flit_chanel.flit.payload =
+            (IS_SINGLE_FLIT )? hdr_flit_out[FPAYw-1 : 0] :
+            /* verilator lint_off WIDTH */
+            (flit_type==HEADER)? hdr_flit_out[Fpay-1 : 0] : dataIn [Fpay-1 : 0];
+            /* verilator lint_on WIDTH */
+        chan_out.smart_chanel = {SMART_CHANEL_w{1'b0}};
+        chan_out.flit_chanel.congestion = {CONGw{1'b0}};
+        chan_out.flit_chanel.credit= credit_o;
+        for(int i=0;i<V;i++) chan_out.ctrl_chanel.credit_init_val[i]= LB [CRDTw-1: 0];
+        chan_out.ctrl_chanel.credit_release_en={V{1'b0}};
+        chan_out.ctrl_chanel.endp_port =1'b1;
+        chan_out.ctrl_chanel.hetero_ovc_presence ={V{1'b1}};
+    end 
+    
+    distance_gen the_distance_gen (
+        .src_e_addr(sender_endp_addr_reg[vc_bin]),
+        .dest_e_addr(current_e_addr),
+        .distance(distance)
+    );
+    
+    `ifdef SIMULATION
+    //`define MONITOR_RSV_DAT
+    always @(posedge clk) begin 
+        if((pck_injct_in.vc == {V{1'b0}} ) & pck_injct_in.pck_wr )begin 
+            $display("%t: ERROR: a packet injection request is recived while vc is not set. %m",$time);
+            $finish;
+        end
+        if(pck_injct_in.pck_wr && (pck_injct_in.size<MIN_PCK_SIZ[PCK_SIZw-1 : 0])) begin 
+            $display("%t: ERROR: requested %d flit packet size is smaller than minimum %d flits to send %d bits of data. %m",$time,pck_injct_in.size,MIN_PCK_SIZ, PCK_INJ_Dw );
+            $finish;
+        end
+        
+        `ifdef MONITOR_RSV_DAT
+        if(pck_injct_in.pck_wr) begin 
+            $display ("pck_inj(%d) send a packet:  size=%d, data=%h, v=%h",current_id,
+                pck_injct_in.size, pck_injct_in.data,pck_injct_in.vc);
+        end
+        
+        if(pck_injct_out.pck_wr) begin 
+            $display ("pck_inj(%d) got a packet: source=%d, size=%d, data=%h",current_id,
+                sendor_id,pck_injct_out.size,pck_injct_out.data);
+        end
+        `endif //MONITOR_RSV_DAT
+    end
+    `endif //SIMULATION
+    
 endmodule
 
 
-
-
 /******************
  *   ovc_status
  *******************/
- 
 module injector_ovc_status #(
-		parameter V     =   4,
-		parameter B =   16,
-		parameter CRDTw =4
-		)
-		(
-   
-		input   [V-1 : 0] [CRDTw-1 : 0 ] credit_init_val_in,
-		input   [V-1            :0] wr_in,
-		input   [V-1            :0] credit_in,
-		output  [V-1            :0] full_vc,
-		output  [V-1            :0] nearly_full_vc,
-		output  [V-1            :0] empty_vc,		
-		input                       clk,
-		input                       reset
-		);
-
- 
-	function integer log2;
-		input integer number; begin   
-			log2=(number <=1) ? 1: 0;    
-			while(2**log2<number) begin    
-				log2=log2+1;    
-			end 	   
-		end   
-	endfunction // log2 
-    
-  
-	localparam  DEPTH_WIDTH =   log2(B+1);
- 
-    
-	reg  [DEPTH_WIDTH-1 : 0] credit    [V-1 : 0];
-	wire  [V-1 : 0] cand_vc_next;
-	
-    
-	genvar i;
-	generate
-		for(i=0;i<V;i=i+1) begin : vc_loop
-			always @ (`pronoc_clk_reset_edge )begin 
-				if(`pronoc_reset) begin
-					credit[i]<= credit_init_val_in[i][DEPTH_WIDTH-1:0];
-				end else begin
-					if(  wr_in[i]  && ~credit_in[i])   credit[i] <= credit[i]-1'b1;
-					if( ~wr_in[i]  &&  credit_in[i])   credit[i] <= credit[i]+1'b1;
-				end //reset
-			end//always
-
-			assign  full_vc[i]   = (credit[i] == {DEPTH_WIDTH{1'b0}});
-			assign  nearly_full_vc[i]=  (credit[i] == 1) |  full_vc[i];
-			assign  empty_vc[i]  = (credit[i] == credit_init_val_in[i][DEPTH_WIDTH-1:0]);
-		end//for
-	endgenerate
+    parameter V = 4,
+    parameter B = 16,
+    parameter CRDTw = 4
+)(
+    input   [V-1 : 0] [CRDTw-1 : 0] credit_init_val_in,
+    input   [V-1 : 0] wr_in,
+    input   [V-1 : 0] credit_in,
+    output  [V-1 : 0] full_vc,
+    output  [V-1 : 0] nearly_full_vc,
+    output  [V-1 : 0] empty_vc,
+    input clk,
+    input reset
+);
+    
+    function integer log2;
+        input integer number; begin   
+            log2=(number <=1) ? 1: 0;    
+            while(2**log2<number) begin    
+                log2=log2+1;    
+            end        
+        end   
+    endfunction // log2 
+    
+    localparam  DEPTH_WIDTH =   log2(B+1);
+    
+    reg  [DEPTH_WIDTH-1 : 0] credit    [V-1 : 0];
+    wire  [V-1 : 0] cand_vc_next;
+    
+    genvar i;
+    generate
+    for(i=0;i<V;i=i+1) begin : vc_loop
+        always @ (`pronoc_clk_reset_edge )begin 
+            if(`pronoc_reset) begin
+                credit[i]<= credit_init_val_in[i][DEPTH_WIDTH-1:0];
+            end else begin
+                if(  wr_in[i]  && ~credit_in[i])   credit[i] <= credit[i]-1'b1;
+                if( ~wr_in[i]  &&  credit_in[i])   credit[i] <= credit[i]+1'b1;
+            end //reset
+        end//always
+        assign  full_vc[i]   = (credit[i] == {DEPTH_WIDTH{1'b0}});
+        assign  nearly_full_vc[i]=  (credit[i] == 1) |  full_vc[i];
+        assign  empty_vc[i]  = (credit[i] == credit_init_val_in[i][DEPTH_WIDTH-1:0]);
+    end//for
+    endgenerate
 endmodule
 
 
-
-
 /**************************************
  * 
- * 
+ *    packet_injector_verilator
  * ***********************************/
-
-
-
-module packet_injector_verilator #(
-	parameter NOC_ID=0
-) (
-	//general
-	current_e_addr,
-	reset,
-	clk,		
-	//noc port
-	chan_in,
-	chan_out,  
-	//control interafce
-	pck_injct_in_data,         
-	pck_injct_in_size,         
-	pck_injct_in_endp_addr,    
-	pck_injct_in_class_num,    
-	pck_injct_in_init_weight,  
-	pck_injct_in_vc,           
-	pck_injct_in_pck_wr,  	 
-	pck_injct_in_ready,        
-                            
-	pck_injct_out_data,       
-	pck_injct_out_size,       
-	pck_injct_out_endp_addr,  
-	pck_injct_out_class_num,  
-	pck_injct_out_init_weight,
-	pck_injct_out_vc,         
-	pck_injct_out_pck_wr,  	 
-	pck_injct_out_ready,
-	pck_injct_out_distance,
-	pck_injct_out_h2t_delay,
-	min_pck_size
-                 
+module packet_injector_verilator (
+    //general
+    current_e_addr,
+    reset,
+    clk,
+    //noc port
+    chan_in,
+    chan_out,  
+    //control interafce
+    pck_injct_in_data,
+    pck_injct_in_size,
+    pck_injct_in_endp_addr,
+    pck_injct_in_class_num,
+    pck_injct_in_init_weight,
+    pck_injct_in_vc,
+    pck_injct_in_pck_wr,
+    pck_injct_in_ready,
+    
+    pck_injct_out_data,
+    pck_injct_out_size,
+    pck_injct_out_endp_addr,
+    pck_injct_out_class_num,
+    pck_injct_out_init_weight,
+    pck_injct_out_vc,
+    pck_injct_out_pck_wr,
+    pck_injct_out_ready,
+    pck_injct_out_distance,
+    pck_injct_out_h2t_delay,
+    min_pck_size
+    
 );
-
-	`NOC_CONF 
-	
-	//general
-	input reset,clk;
-	input [EAw-1 :0 ] current_e_addr;
-	
-	// the destination endpoint address
-	//NoC interface
-	input   smartflit_chanel_t 	chan_in;
-	output  smartflit_chanel_t 	chan_out;	
-	//control interafce
-	
-	
-	input [PCK_INJ_Dw-1 : 0] pck_injct_in_data;
-	input [PCK_SIZw-1   : 0] pck_injct_in_size;
-	input [DAw-1        : 0] pck_injct_in_endp_addr; 
-	input [Cw-1         : 0] pck_injct_in_class_num; 
-	input [WEIGHTw-1    : 0] pck_injct_in_init_weight;
-	input [V-1          : 0] pck_injct_in_vc;
-	input                    pck_injct_in_pck_wr;  	
-	input [V-1          : 0] pck_injct_in_ready;
-
-	output [PCK_INJ_Dw-1 : 0] pck_injct_out_data;             
-	output [PCK_SIZw-1   : 0] pck_injct_out_size;             
-	output [DAw-1        : 0] pck_injct_out_endp_addr;        
-	output [Cw-1         : 0] pck_injct_out_class_num;        
-	output [WEIGHTw-1    : 0] pck_injct_out_init_weight;      
-	output [V-1          : 0] pck_injct_out_vc;               
-	output                    pck_injct_out_pck_wr;  	     
-	output [V-1          : 0] pck_injct_out_ready;  
-	output [DISTw-1 	  : 0] pck_injct_out_distance;
-	output [15			  : 0] pck_injct_out_h2t_delay;
-	output [4			  : 0] min_pck_size;
- 
-	pck_injct_t pck_injct_in;
-	pck_injct_t pck_injct_out;
-
-	assign pck_injct_in.data         = pck_injct_in_data;                  
-	assign pck_injct_in.size         = pck_injct_in_size;                 
-	assign pck_injct_in.endp_addr    = pck_injct_in_endp_addr;            
-	assign pck_injct_in.class_num    = pck_injct_in_class_num;            
-	assign pck_injct_in.init_weight  = pck_injct_in_init_weight;          
-	assign pck_injct_in.vc           = pck_injct_in_vc;                   
-	assign pck_injct_in.pck_wr  	  = pck_injct_in_pck_wr;  	        
-	assign pck_injct_in.ready        = pck_injct_in_ready;                
-                                                                   
-	assign pck_injct_out_data        = pck_injct_out.data;           
-	assign pck_injct_out_size        = pck_injct_out.size;           
-	assign pck_injct_out_endp_addr   = pck_injct_out.endp_addr;      
-	assign pck_injct_out_class_num   = pck_injct_out.class_num;      
-	assign pck_injct_out_init_weight = pck_injct_out.init_weight;    
-	assign pck_injct_out_vc          = pck_injct_out.vc;             
-	assign pck_injct_out_pck_wr  	  = pck_injct_out.pck_wr;  	     
-	assign pck_injct_out_ready       = pck_injct_out.ready;          
-	assign pck_injct_out_distance    = pck_injct_out.distance;
-	assign pck_injct_out_h2t_delay   = pck_injct_out.h2t_delay;
- 	
-	packet_injector #(
-		.NOC_ID(NOC_ID)
-	) injector (
-		.current_e_addr  (current_e_addr ), 
-		.reset           (reset          ), 
-		.clk             (clk            ), 
-		.chan_in         (chan_in        ), 
-		.chan_out        (chan_out       ), 
-		.pck_injct_in    (pck_injct_in   ), 
-		.pck_injct_out   (pck_injct_out  )
-	);
- 
- 
-	localparam 
-		HDR_BYTE_NUM =	HDR_MAX_DATw / 8, // = HDR_MAX_DATw / (8 - HDR_MAX_DATw %8)
-		HDR_DATA_w_tmp   =  HDR_BYTE_NUM * 8,
-		HDR_DATA_w = 
-		(PCK_INJ_Dw < HDR_DATA_w_tmp)? PCK_INJ_Dw :
-		(HDR_DATA_w_tmp==0)? 1: HDR_DATA_w_tmp,
-		REMAIN_DATw =  PCK_INJ_Dw - HDR_DATA_w,
-		REMAIN_DAT_FLIT_I = (REMAIN_DATw / Fpay),
-		REMAIN_DAT_FLIT_F = (REMAIN_DATw % Fpay == 0)? 0 : 1,
-		REMAIN_DAT_FLIT   = REMAIN_DAT_FLIT_I + REMAIN_DAT_FLIT_F,
-		CNTw = log2(REMAIN_DAT_FLIT),
-		MIN_PCK_SIZ = REMAIN_DAT_FLIT +1;
- 
-	assign  min_pck_size = MIN_PCK_SIZ[4:0];
+    
+    import pronoc_pkg::*; 
+    
+    //general
+    input reset,clk;
+    input [EAw-1 :0 ] current_e_addr;
+    
+    // the destination endpoint address
+    //NoC interface
+    input   smartflit_chanel_t     chan_in;
+    output  smartflit_chanel_t     chan_out;    
+    //control interafce
+    
+    input [PCK_INJ_Dw-1 : 0] pck_injct_in_data;
+    input [PCK_SIZw-1   : 0] pck_injct_in_size;
+    input [DAw-1        : 0] pck_injct_in_endp_addr; 
+    input [Cw-1         : 0] pck_injct_in_class_num; 
+    input [WEIGHTw-1    : 0] pck_injct_in_init_weight;
+    input [V-1          : 0] pck_injct_in_vc;
+    input                    pck_injct_in_pck_wr;
+    input [V-1          : 0] pck_injct_in_ready;
+    
+    output [PCK_INJ_Dw-1 : 0] pck_injct_out_data;
+    output [PCK_SIZw-1   : 0] pck_injct_out_size;
+    output [DAw-1        : 0] pck_injct_out_endp_addr;
+    output [Cw-1         : 0] pck_injct_out_class_num;
+    output [WEIGHTw-1    : 0] pck_injct_out_init_weight;
+    output [V-1          : 0] pck_injct_out_vc;
+    output                    pck_injct_out_pck_wr;
+    output [V-1          : 0] pck_injct_out_ready;
+    output [DISTw-1       : 0] pck_injct_out_distance;
+    output [15              : 0] pck_injct_out_h2t_delay;
+    output [4              : 0] min_pck_size;
+    
+    pck_injct_t pck_injct_in;
+    pck_injct_t pck_injct_out;
+    
+    always_comb begin
+        pck_injct_in.data         = pck_injct_in_data;
+        pck_injct_in.size         = pck_injct_in_size;
+        pck_injct_in.endp_addr    = pck_injct_in_endp_addr;
+        pck_injct_in.class_num    = pck_injct_in_class_num;
+        pck_injct_in.init_weight  = pck_injct_in_init_weight;
+        pck_injct_in.vc           = pck_injct_in_vc;
+        pck_injct_in.pck_wr       = pck_injct_in_pck_wr;
+        pck_injct_in.ready        = pck_injct_in_ready;
+    end
+    
+    assign pck_injct_out_data        = pck_injct_out.data;
+    assign pck_injct_out_size        = pck_injct_out.size;
+    assign pck_injct_out_endp_addr   = pck_injct_out.endp_addr;
+    assign pck_injct_out_class_num   = pck_injct_out.class_num;
+    assign pck_injct_out_init_weight = pck_injct_out.init_weight;
+    assign pck_injct_out_vc          = pck_injct_out.vc;
+    assign pck_injct_out_pck_wr      = pck_injct_out.pck_wr;
+    assign pck_injct_out_ready       = pck_injct_out.ready;
+    assign pck_injct_out_distance    = pck_injct_out.distance;
+    assign pck_injct_out_h2t_delay   = pck_injct_out.h2t_delay;
 
 
-	// `ifdef VERILATOR
-	// 	logic  endp_is_active   /*verilator public_flat_rd*/ ;
-	//			
-	// 	always @ (*) begin 
-	//		endp_is_active  = 1'b0;		
-	// 		if (chan_out.flit_chanel.flit_wr) endp_is_active=1'b1;
-	// 		if (chan_out.flit_chanel.credit > {V{1'b0}} ) endp_is_active=1'b1;
-	// 		if (chan_out.smart_chanel.requests > {SMART_NUM{1'b0}} ) endp_is_active=1'b1;
-	// 	end	
-	// `endif 
- 
- 
+    packet_injector injector (
+        .current_e_addr  (current_e_addr ), 
+        .reset           (reset          ), 
+        .clk             (clk            ), 
+        .chan_in         (chan_in        ), 
+        .chan_out        (chan_out       ), 
+        .pck_injct_in    (pck_injct_in   ), 
+        .pck_injct_out   (pck_injct_out  )
+    ); 
+    
+    localparam 
+        HDR_BYTE_NUM =    HDR_MAX_DATw / 8, // = HDR_MAX_DATw / (8 - HDR_MAX_DATw %8)
+        HDR_DATA_w_tmp   =  HDR_BYTE_NUM * 8,
+        HDR_DATA_w = 
+        (PCK_INJ_Dw < HDR_DATA_w_tmp)? PCK_INJ_Dw :
+        (HDR_DATA_w_tmp==0)? 1: HDR_DATA_w_tmp,
+        REMAIN_DATw =  PCK_INJ_Dw - HDR_DATA_w,
+        REMAIN_DAT_FLIT_I = (REMAIN_DATw / Fpay),
+        REMAIN_DAT_FLIT_F = (REMAIN_DATw % Fpay == 0)? 0 : 1,
+        REMAIN_DAT_FLIT   = REMAIN_DAT_FLIT_I + REMAIN_DAT_FLIT_F,
+        CNTw = log2(REMAIN_DAT_FLIT),
+        MIN_PCK_SIZ = REMAIN_DAT_FLIT +1;
+    
+    assign  min_pck_size = MIN_PCK_SIZ[4:0];
+    
+    // `ifdef VERILATOR
+    //     logic  endp_is_active   /*verilator public_flat_rd*/ ;
+    //
+    //     always_comb begin 
+    //        endp_is_active  = 1'b0; 
+    //         if (chan_out.flit_chanel.flit_wr) endp_is_active=1'b1;
+    //         if (chan_out.flit_chanel.credit > {V{1'b0}} ) endp_is_active=1'b1;
+    //         if (chan_out.smart_chanel.requests > {SMART_NUM{1'b0}} ) endp_is_active=1'b1;
+    //     end    
+    // `endif 
 endmodule
diff --git a/mpsoc/rtl/src_noc/pronoc_pkg.sv b/mpsoc/rtl/src_noc/pronoc_pkg.sv
index a085c4f..4243e4c 100644
--- a/mpsoc/rtl/src_noc/pronoc_pkg.sv
+++ b/mpsoc/rtl/src_noc/pronoc_pkg.sv
@@ -4,334 +4,384 @@
  * pronoc_pkg.sv
  ****************************************************************************/
 
-`ifdef PRONOC_PKG	
-
-`ifdef IMPORT_PRONOC_PCK
 package pronoc_pkg; 
-`endif  
-	
-	
-	
-  
+
+
 `define NOC_LOCAL_PARAM
 `include "noc_localparam.v"
-		
-		
-		
 
 `define  INCLUDE_TOPOLOGY_LOCALPARAM
 `include "topology_localparam.v"
 
+    localparam
+        Vw=  log2(V),
+        Cw=  (C==0)? 1 : log2(C),
+        NRw = log2(NR),
+        NEw = log2(NE),
+        Bw  = log2(B),
+        WRRA_CONFIG_INDEX=0,
+        SMART_EN = (SMART_MAX !=0),
+        SMART_NUM= (SMART_EN) ? SMART_MAX : 1,
+        NEV  = NE * V,
+        BEw = (BYTE_EN)? log2(Fpay/8) : 1;
+        
+    localparam CONGw= 
+        (CONGESTION_INDEX==3)?  3:
+        (CONGESTION_INDEX==5)?  3:
+        (CONGESTION_INDEX==7)?  3:
+        (CONGESTION_INDEX==9)?  3:
+        (CONGESTION_INDEX==10)? 4:
+        (CONGESTION_INDEX==12)? 3:2;
+        
+    localparam
+        E_SRC_LSB =0,                   E_SRC_MSB = E_SRC_LSB + EAw-1,
+        E_DST_LSB = E_SRC_MSB +1,       E_DST_MSB = E_DST_LSB + DAw-1,  
+        DST_P_LSB = E_DST_MSB + 1,      DST_P_MSB = DST_P_LSB + DSTPw-1, 
+        CLASS_LSB = DST_P_MSB + 1,      CLASS_MSB = CLASS_LSB + Cw -1, 
+        MSB_CLASS = (C>1)? CLASS_MSB : DST_P_MSB,
+        WEIGHT_LSB= MSB_CLASS + 1,      WEIGHT_MSB = WEIGHT_LSB + WEIGHTw -1,
+        MSB_W = (IS_WRRA)? WEIGHT_MSB : MSB_CLASS,
+        BE_LSB =  MSB_W + 1,            BE_MSB = BE_LSB+ BEw-1,
+        MSB_BE = (BYTE_EN==1)?   BE_MSB  : MSB_W,
+        //the maximum data width that can be carried out with header flit
+        HDR_MAX_DATw = (IS_SINGLE_FLIT)? Fpay : Fpay - MSB_BE -1;
+        
+    localparam
+        DISTw =  (IS_FATTREE | IS_TREE ) ? log2(2*L+1): log2(NR+1),
+        OVC_ALLOC_MODE= ((V==1 || B <= 4) ) ?   1'b1 : 1'b0;
+    localparam [WEIGHTw-1:0] WEIGHT_INIT = 1; //initial weight for WRRA allocator
+        // 0: The new ovc is allocated only if its not nearly full. Results in a simpler sw_mask_gen logic
+        // 1: The new ovc is allocated only if its not full. Results in a little more complex sw_mask_gen logic
+        
 
-
-localparam
-	Vw=  log2(V),
-	Cw=  (C==0)? 1 : log2(C),
-	NEw = log2(NE),
-	Bw  = log2(B),	
-	WRRA_CONFIG_INDEX=0,
-	SMART_EN = (SMART_MAX !=0),
-	SMART_NUM= (SMART_EN) ? SMART_MAX : 1,	
-	NEV  = NE * V,
-	T4 = 0,
-	BEw = (BYTE_EN)? log2(Fpay/8) : 1;
-	
-
-
- localparam CONGw= (CONGESTION_INDEX==3)?  3:
-                      (CONGESTION_INDEX==5)?  3:
-                      (CONGESTION_INDEX==7)?  3:
-                      (CONGESTION_INDEX==9)?  3:
-                      (CONGESTION_INDEX==10)? 4:
-                      (CONGESTION_INDEX==12)? 3:2;
-
-
- localparam 
- 	E_SRC_LSB =0,                   E_SRC_MSB = E_SRC_LSB + EAw-1,
- 	E_DST_LSB = E_SRC_MSB +1,       E_DST_MSB = E_DST_LSB + DAw-1,  
- 	DST_P_LSB = E_DST_MSB + 1,      DST_P_MSB = DST_P_LSB + DSTPw-1, 
- 	CLASS_LSB = DST_P_MSB + 1,      CLASS_MSB = CLASS_LSB + Cw -1, 
- 	MSB_CLASS = (C>1)? CLASS_MSB : DST_P_MSB,
- 	WEIGHT_LSB= MSB_CLASS + 1,      WEIGHT_MSB = WEIGHT_LSB + WEIGHTw -1,
- 	/* verilator lint_off WIDTH */ 
- 	MSB_W = (SWA_ARBITER_TYPE== "WRRA")? WEIGHT_MSB : MSB_CLASS,
- 	/* verilator lint_on WIDTH */
- 	BE_LSB =  MSB_W + 1,            BE_MSB = BE_LSB+ BEw-1,
- 	MSB_BE = (BYTE_EN==1)?   BE_MSB  : MSB_W,
- 	/* verilator lint_off WIDTH */ 
- 	//the maximum data width that can be carried out with header flit
- 	HDR_MAX_DATw = (PCK_TYPE == "SINGLE_FLIT")? Fpay : Fpay - MSB_BE -1;
- 	/* verilator lint_on WIDTH */
- 	
- 	/* verilator lint_off WIDTH */ 
-localparam 
-	DISTw =  (TOPOLOGY=="FATTREE" || TOPOLOGY=="TREE" ) ? log2(2*L+1): log2(NR+1),
-	OVC_ALLOC_MODE= ((V==1 || B<=4) )?   1'b1 : 1'b0;
- 	/* verilator lint_on WIDTH */ 
- 	
- 	// 0: The new ovc is allocated only if its not nearly full. Results in a simpler sw_mask_gen logic    
- 	// 1: The new ovc is allocated only if its not full. Results in a little more complex sw_mask_gen logic    
-
-
- /******************
- *   vsa : Virtual channel & Switch allocator 
+/******************
+ *   vsa : Virtual channel & Switch allocator
  *   local two-stage router allocator
  *****************/
- 	typedef struct packed {
- 		logic [V-1 : 0] ovc_is_allocated;
- 		logic [V-1 : 0] ovc_is_released; 		
- 		logic [V-1 : 0] ivc_num_getting_sw_grant; 
- 		logic [V-1 : 0] ivc_num_getting_ovc_grant;
- 		logic [V-1 : 0] ivc_reset;
- 		logic [V-1 : 0] buff_space_decreased;
- 		logic [V*V-1: 0] ivc_granted_ovc_num;
- 	} vsa_ctrl_t;	
- 	localparam  VSA_CTRL_w = $bits(vsa_ctrl_t);
- 	
+    typedef struct packed {
+        logic [V-1 : 0] ovc_is_allocated;
+        logic [V-1 : 0] ovc_is_released;
+        logic [V-1 : 0] ivc_num_getting_sw_grant; 
+        logic [V-1 : 0] ivc_num_getting_ovc_grant;
+        logic [V-1 : 0] ivc_reset;
+        logic [V-1 : 0] buff_space_decreased;
+        logic [V*V-1: 0] ivc_granted_ovc_num;
+    } vsa_ctrl_t;    
+    localparam  VSA_CTRL_w = $bits(vsa_ctrl_t);
+    
 /*********************
-* 	ssa : static straight allocator:
-* 	      enable single cycle latency for flits goes to the same direction
-**********************/ 	
- 	
- 	typedef struct packed {
- 		logic [V-1 : 0] ovc_is_allocated;
- 		logic [V-1 : 0] ovc_is_released; 		
- 		logic [V-1 : 0] ivc_num_getting_sw_grant; 
- 		logic [V-1 : 0] ivc_num_getting_ovc_grant;
- 		logic [V-1 : 0] ivc_reset;
- 		logic [V-1 : 0] buff_space_decreased;
- 		logic [V-1 : 0] ivc_single_flit_pck;
- 		logic [V-1 : 0] ovc_single_flit_pck;
- 		bit      		ssa_flit_wr;
- 		logic [V*V-1: 0] ivc_granted_ovc_num;
- 	} ssa_ctrl_t;	
- 	localparam  SSA_CTRL_w = $bits(ssa_ctrl_t);
- 	
- 	
+*     ssa : static straight allocator:
+*           enable single cycle latency for flits goes to the same direction
+**********************/
+    
+    typedef struct packed {
+        logic [V-1 : 0] ovc_is_allocated;
+        logic [V-1 : 0] ovc_is_released;
+        logic [V-1 : 0] ivc_num_getting_sw_grant; 
+        logic [V-1 : 0] ivc_num_getting_ovc_grant;
+        logic [V-1 : 0] ivc_reset;
+        logic [V-1 : 0] buff_space_decreased;
+        logic [V-1 : 0] ivc_single_flit_pck;
+        logic [V-1 : 0] ovc_single_flit_pck;
+        bit             ssa_flit_wr;
+        logic [V*V-1: 0] ivc_granted_ovc_num;
+    } ssa_ctrl_t;    
+    localparam  SSA_CTRL_w = $bits(ssa_ctrl_t);
+    
 /*********************
 *    smart : straight bypass allocator:
 *    enable multihub bypassing for flits goes to the same direction
 *********************/
-	typedef struct packed {
-		logic [EAw-1 : 0] dest_e_addr;
-		logic ovc_is_assigned;
-		logic [Vw-1   : 0] assigned_ovc_bin;		
-	} smart_ivc_info_t;
-	localparam SMART_IVC_w = $bits(smart_ivc_info_t);
-	
-	
-	
-	typedef struct packed {
-		bit		smart_en;
-		bit     hdr_flit_req;
-		logic 	[V-1 : 0]        ivc_smart_en;
-		logic   [DSTPw-1  :   0] lk_destport;
-		logic   [DSTPw-1  :   0] destport;
-		logic   [V-1 : 0] credit_out;
-		logic   [V-1 : 0] buff_space_decreased;
-		logic   [V-1 : 0] ovc_is_allocated;
-		logic   [V-1 : 0] ovc_is_released;		
-		logic   [V-1 : 0] ivc_num_getting_ovc_grant;
-		logic   [V-1 : 0] ivc_reset;
-		logic   [V-1 : 0] mask_available_ovc;
-		logic   [V-1 : 0] ivc_single_flit_pck;
-		logic   [V-1 : 0] ovc_single_flit_pck;
-		logic   [V*V-1: 0] ivc_granted_ovc_num;
-	} smart_ctrl_t;	
-	localparam  SMART_CTRL_w = $bits(smart_ctrl_t);
-	
-	/*****************
-	 * port_info
-	 * **************/
-	typedef struct packed {
-		logic [V-1 : 0] ivc_req; // input vc is not empty
-		logic [V-1 : 0] swa_first_level_grant;// The vc number (one-hot) in an input port which get the first level switch allocator grant
-		logic [V-1 : 0] swa_grant; // The VC number in an input port which got the swa grant
-		logic [MAX_P-1 : 0] granted_oport_one_hot;	//The granted output port num (one-hot) for an input port	
-		logic any_ivc_get_swa_grant;
-		
-	} iport_info_t;	
-	localparam  IPORT_INFO_w = $bits(iport_info_t);
-	
-	typedef struct packed {
-		logic [V-1 : 0] non_smart_ovc_is_allocated;
-		//logic [V-1 : 0] ovc_is_released;
-		//logic [V-1 : 0] ovc_credit_increased; 
-		//logic [V-1 : 0] ovc_credit_decreased;
-		//logic [V-1 : 0] ovc_avalable;
-		bit any_ovc_granted;
-		//bit crossbar_flit_wr;
-			
-	}oport_info_t;	
-	localparam  OPORT_INFO_w = $bits(oport_info_t);
-	
+    typedef struct packed {
+        logic [EAw-1 : 0] dest_e_addr;
+        logic ovc_is_assigned;
+        logic [Vw-1   : 0] assigned_ovc_bin;
+    } smart_ivc_info_t;
+    localparam SMART_IVC_w = $bits(smart_ivc_info_t);
+    
+    typedef struct packed {
+        bit     smart_en;
+        bit     hdr_flit_req;
+        logic   [V-1 : 0] ivc_smart_en;
+        logic   [DSTPw-1  :   0] lk_destport;
+        logic   [DSTPw-1  :   0] destport;
+        logic   [V-1 : 0] credit_out;
+        logic   [V-1 : 0] buff_space_decreased;
+        logic   [V-1 : 0] ovc_is_allocated;
+        logic   [V-1 : 0] ovc_is_released;
+        logic   [V-1 : 0] ivc_num_getting_ovc_grant;
+        logic   [V-1 : 0] ivc_reset;
+        logic   [V-1 : 0] mask_available_ovc;
+        logic   [V-1 : 0] ivc_single_flit_pck;
+        logic   [V-1 : 0] ovc_single_flit_pck;
+        logic   [V*V-1: 0] ivc_granted_ovc_num;
+    } smart_ctrl_t;
+    localparam  SMART_CTRL_w = $bits(smart_ctrl_t);
+    
+/*****************
+* port_info
+****************/
+    typedef struct packed {
+        logic [V-1 : 0] ivc_req; // input vc is not empty
+        logic [V-1 : 0] swa_first_level_grant;// The vc number (one-hot) in an input port which get the first level switch allocator grant
+        logic [V-1 : 0] swa_grant; // The VC number in an input port which got the swa grant
+        logic [MAX_P-1 : 0] granted_oport_one_hot;    //The granted output port num (one-hot) for an input port
+        logic any_ivc_get_swa_grant;
+    } iport_info_t;
+    localparam  IPORT_INFO_w = $bits(iport_info_t);
+    
+    typedef struct packed {
+        logic [V-1 : 0] non_smart_ovc_is_allocated;
+        //logic [V-1 : 0] ovc_is_released;
+        //logic [V-1 : 0] ovc_credit_increased; 
+        //logic [V-1 : 0] ovc_credit_decreased;
+        //logic [V-1 : 0] ovc_avalable;
+        bit any_ovc_granted;
+        //bit crossbar_flit_wr;
+    }oport_info_t;
+    localparam  OPORT_INFO_w = $bits(oport_info_t);
+    
+/*********************
+* ivc
+*******************/
+    typedef struct packed {
+        //ivc
+        logic [EAw-1 : 0] dest_e_addr;
+        logic ovc_is_assigned;
+        logic [V-1   : 0] assigned_ovc_num;
+        logic [Vw-1  : 0] assigned_ovc_bin;
+        logic [MAX_P-1   : 0] destport_one_hot;
+        logic [DSTPw-1 : 0]  dest_port_encoded;
+        logic ivc_req; // input vc is not empty
+        logic flit_is_tail;
+        logic assigned_ovc_not_full;
+        logic [V-1  : 0] candidate_ovc;
+        logic [Cw-1 : 0] class_num;
+        logic single_flit_pck;
+    } ivc_info_t;
+    localparam  IVC_INFO_w = $bits( ivc_info_t);
+    
+    localparam     CREDITw  = (LB>B)?  log2(LB+1) : log2(B+1);
+    
+    //ovc info
+    typedef struct packed {
+        bit avalable; 
+        bit status; //1 : is allocated 0 : not_allocated
+        logic [CREDITw-1 : 0] credit;//available credit in OVC
+        bit full;
+        bit nearly_full;
+        bit empty;
+    }ovc_info_t;
+    localparam  OVC_INFO_w = $bits( ovc_info_t);
 
-	
-	
-	
-	/*********************
-	 * ivc 
-	 *******************/
-		
-	
-	typedef struct packed {
-		//ivc
-		logic [EAw-1 : 0] dest_e_addr;
-		logic ovc_is_assigned;
-		logic [V-1   : 0] assigned_ovc_num;	
-		logic [Vw-1  : 0] assigned_ovc_bin;
-		logic [MAX_P-1   : 0] destport_one_hot;
-		logic [DSTPw-1 : 0]  dest_port_encoded;
-		logic ivc_req; // input vc is not empty
-		logic flit_is_tail;
-		logic assigned_ovc_not_full;
-		logic [V-1  : 0] candidate_ovc;
-		logic [Cw-1 : 0] class_num;
-		logic single_flit_pck;
-		
-	} ivc_info_t;
-	localparam  IVC_INFO_w = $bits( ivc_info_t);
-	
-	localparam 	CREDITw  = (LB>B)?  log2(LB+1) : log2(B+1);
-	
-	//ovc info
-	typedef struct packed {
-		bit avalable; 
-		bit status; //1 : is allocated 0 : not_allocated
-		logic [CREDITw-1 : 0] credit;//available credit in OVC
-		bit full;
-		bit nearly_full;
-		bit empty;
-	}ovc_info_t;
-	localparam  OVC_INFO_w = $bits( ovc_info_t);
-	
+/**************
+*   router id
+**************/
+    typedef struct packed {
+        logic [31:0] router_id;
+        logic [RAw-1 :  0] router_addr;
+        logic [MAX_P*RAw-1:  0] neighbors_r_addr;
+    } router_info_t;
+    localparam  ROUTER_INFO_w = $bits(router_info_t);
+    
+    typedef struct packed {
+        logic [NRw-1 : 0] router_id;
+        logic [RAw-1 : 0] router_addr;
+        logic [NE_PER_R*EAw-1 : 0]  endp_addrs;
+        logic [NE_PER_R*NEw-1 : 0]  endp_ids;
+    } router_config_t;
+    localparam  ROUTER_CONFIG_w = $bits(router_config_t);
 
-		
-	
-		
 /*********************
-* router_chanels 
+* router_chanels
 *********************/
-	
-	typedef struct packed {	
-		logic [EAw-1 	: 0] src_e_addr;
-		logic [DAw-1 	: 0] dest_e_addr;
-		logic [DSTPw-1	: 0] destport;    
-		logic [Cw-1		: 0] message_class;
-		logic [WEIGHTw-1: 0] weight;
-		logic [BEw-1 	: 0] be;		
-	} hdr_flit_t;
-	localparam HDR_FLIT_w = $bits(hdr_flit_t); 
-	
-	/* verilator lint_off WIDTH */
-	localparam FPAYw = (PCK_TYPE == "SINGLE_FLIT")?   Fpay + MSB_BE: Fpay;    
-	/* verilator lint_on WIDTH */
-	
-	typedef struct packed {
-		bit hdr_flag;
-		bit tail_flag;
-		logic [V-1 : 0] vc;
-		logic [FPAYw-1 : 0] payload;		
-	} flit_t;
-	localparam FLIT_w = $bits(flit_t); 
-	
-	localparam
-		Fw = FLIT_w,
-		NEFw = NE *Fw;	
-	
-	typedef struct packed {	
-		logic  flit_wr;
-		logic  [V-1 :  0]  credit;
-		flit_t  flit;		
-		logic  [CONGw-1 :  0]  congestion;		
-	} flit_chanel_t;
-	localparam FLIT_CHANEL_w = $bits(flit_chanel_t); 
-	
-	localparam BYPASSw = log2(SMART_NUM+1);
-	typedef struct packed {
-		logic [SMART_NUM-1: 0] requests;
-		logic [V-1   	: 0] ovc;		
-		logic [EAw-1 	: 0] dest_e_addr;
-		bit   hdr_flit;
-		bit   flit_in_bypassed; 
-		logic [BYPASSw-1 : 0] bypassed_num;
-	} smart_chanel_t;
-	localparam SMART_CHANEL_w = $bits(smart_chanel_t);
-	
+    
+    typedef struct packed {
+        logic [EAw-1     : 0] src_e_addr;
+        logic [DAw-1     : 0] dest_e_addr;
+        logic [DSTPw-1    : 0] destport;
+        logic [Cw-1        : 0] message_class;
+        logic [WEIGHTw-1: 0] weight;
+        logic [BEw-1     : 0] be;
+    } hdr_flit_t;
+    localparam HDR_FLIT_w = $bits(hdr_flit_t); 
+
+`ifdef PITON_PRONOC
+    // OpenPiton CHIPID + XPOS + YPOS + FBITS widths
+    // NOTE: this is constant
+    localparam PITON_DESTw = `NOC_CHIPID_WIDTH + `NOC_X_WIDTH + `NOC_Y_WIDTH +
+                             `MSG_DST_FBITS_WIDTH;
+    // Extend the size of the Depth-First payload when necessary.
+    // The issue here is that Depth-First adds additionnal destination fields
+    // (total size is MSB_BE + 1), which might be larger than the regular
+    // 14-bit (chipid) + 8-bit x 2 (dest_x/dest_y) + 4-bit FBIT of OpenPiton.
+    // Hence, we need to increase the payload size to reserve enough room for
+    // this additionnal destination fields.
+    localparam FPAYw = (ROUTE_NAME == "DEPTH_FIRST" && MSB_BE + 1 > PITON_DESTw) ?
+                            Fpay + MSB_BE + 1 - PITON_DESTw :
+                            (PCK_TYPE == "SINGLE_FLIT")?
+                                Fpay + MSB_BE :
+                                Fpay;
+`else
+    localparam FPAYw = (IS_SINGLE_FLIT)?   Fpay + MSB_BE: Fpay;
+`endif
 
-	localparam CRDTw = (B>LB) ? log2(B+1) : log2(LB+1);
-	typedef struct packed {
-		bit    endp_port;  // if it is one, it means the corresponding port is connected o an endpoint
-		logic [RAw-1:   0]  neighbors_r_addr;
-		logic [V-1  :0] [CRDTw-1: 0] credit_init_val; // the connected port initial credit value. It is taken at reset time	
-		logic [V-1  :0] credit_release_en;		
-	} ctrl_chanel_t; 
-	localparam CTRL_CHANEL_w = $bits(ctrl_chanel_t);
-	
-	
-	
-	typedef struct packed {
-		flit_chanel_t    flit_chanel;
-		smart_chanel_t   smart_chanel; 
-		ctrl_chanel_t    ctrl_chanel;
-	} smartflit_chanel_t;
-	localparam SMARTFLIT_CHANEL_w = $bits(smartflit_chanel_t); 
-	
-	
-	
-	
+    typedef struct packed {
+        bit hdr_flag;
+        bit tail_flag;
+        logic [V-1 : 0] vc;
+        logic [FPAYw-1 : 0] payload;
+    } flit_t;
+    localparam FLIT_w = $bits(flit_t); 
+    
+    localparam
+        Fw = FLIT_w,
+        NEFw = NE *Fw;
+    
+    typedef struct packed {
+        logic  flit_wr;
+        logic  [V-1 :  0]  credit;
+        flit_t  flit;
+        logic  [CONGw-1 :  0]  congestion;
+    } flit_chanel_t;
+    localparam FLIT_CHANEL_w = $bits(flit_chanel_t); 
+    
+    localparam BYPASSw = log2(SMART_NUM+1);
+    typedef struct packed {
+        logic [SMART_NUM-1: 0] requests;
+        logic [V-1       : 0] ovc;
+        logic [EAw-1     : 0] dest_e_addr;
+        bit   hdr_flit;
+        bit   flit_in_bypassed; 
+        logic [BYPASSw-1 : 0] bypassed_num;
+    } smart_chanel_t;
+    localparam SMART_CHANEL_w = $bits(smart_chanel_t);
+    
+    localparam CRDTw = (B>LB) ? log2(B+1) : log2(LB+1);
+    typedef struct packed {
+        bit endp_port;
+            // If set to 1, the corresponding port is connected to an endpoint.
+        logic [EAw-1 : 0] endp_addr; 
+            // If endp_port is 1, this field represents the address of the connected endpoint. 
+            // This address must be set in the header flit for packets to be received by this port.
+        logic [RAw-1 : 0] router_addr; 
+            // The router address sent to the neighboring router.
+        logic [V-1 : 0] [CRDTw-1: 0] credit_init_val; 
+            // Initial credit value for the connected port, captured at reset.
+        logic [V-1 : 0] credit_release_en; 
+            // If credit_init_val is zero, a rising edge on this signal triggers credit release to the other side.
+        logic [V-1 : 0] hetero_ovc_presence; 
+            // Indicates the presence of active output virtual channels (VCs) in neighboring routers 
+            // when heterogeneous VC support is enabled.
+    } ctrl_chanel_t;
+    
+    localparam CTRL_CHANEL_w = $bits(ctrl_chanel_t);
+    
+    typedef struct packed {
+        flit_chanel_t    flit_chanel;
+        smart_chanel_t   smart_chanel; 
+        ctrl_chanel_t    ctrl_chanel;
+    } smartflit_chanel_t;
+    localparam SMARTFLIT_CHANEL_w = $bits(smartflit_chanel_t); 
+/****************
+*  fifos
+*****************/
+    typedef struct packed {
+        bit full;
+        bit nearly_full;
+        bit empty;
+        bit has_data;
+        bit has_multiple;
+    } fifo_stat_t;
+    localparam FIFO_STAT_w = $bits(fifo_stat_t);
+/****************
+*   functions
+'***************/ 
+    function automatic integer hetero_ivc_decimal;
+        input integer router_id;
+        input integer router_port_num;  //router port num
+        begin
+        `ifdef NO_HETRO_IVC
+        // This macro (`NO_HETRO_IVC) generates identical router RTL code for a NoC.
+        // All input ports will have the maximum number of virtual channels (VCs),
+        // but the redundant VCs are not utilized.
+        // This is useful for simulations with long compilation times (e.g., using Verilator).
+        // Not recommended for synthesis; intended for simulation purposes only. 
+        hetero_ivc_decimal = V; 
+        `else
+        hetero_ivc_decimal = 
+            (HETERO_VC == 0) ? V :
+            (HETERO_VC == 1) ? VC_CONFIG_TABLE [router_id][0] :
+            VC_CONFIG_TABLE [router_id][router_port_num];   
+        `endif
+        end
+    endfunction
+    
+    function automatic logic [V-1 : 0] hetero_ovc_unary;
+    input integer router_id;
+    input integer router_port_num;  //router port num
+    integer i;
+    logic [V-1:0] vc_num;
+    begin
+        vc_num = 
+            (HETERO_VC == 0) ? V'(V) :
+            (HETERO_VC == 1) ? V'(VC_CONFIG_TABLE [router_id][0]) :
+            V'(VC_CONFIG_TABLE [router_id][router_port_num]);
+        hetero_ovc_unary = '0;  // initialize to zero
+        for (i = 0; i < vc_num; i = i + 1) begin
+            hetero_ovc_unary[i] = 1'b1;
+        end
+    end
+    endfunction
+    
 /***********
  * simulation
  * **********/
-	
-	localparam DELAYw = 9; //Injector start delay counter width. 10 to 500 clk cycles delay randomly selected
-	
- 	typedef struct packed {
- 		integer   ip_num;
-		bit send_enable;
-		integer  percentage; // x10	
- 	} hotspot_t;
- 	
- 	typedef struct packed {
- 		integer value;
- 		integer percentage; 	
- 	}rnd_discrete_t;
- 	
- 	//packet injector interface
- 	localparam PCK_INJ_Dw =64;//TODO to be defined by user
- 	localparam PCK_SIZw= log2(MAX_PCK_SIZ+1);
-	
- 	
-
- 	typedef struct packed {
- 		logic [PCK_INJ_Dw-1 : 0] data;
- 		logic [PCK_SIZw-1 : 0] size;
- 		logic [DAw-1 : 0] endp_addr; 
- 		logic [Cw-1  : 0] class_num; 
- 		logic [WEIGHTw-1   : 0] init_weight;
- 		logic [V-1   : 0] vc;
- 		bit   pck_wr;  	
- 		bit   [V-1   : 0] ready;
- 		logic [DISTw-1 : 0] distance;
- 		logic [15: 0]  h2t_delay;
-    }	pck_injct_t;
-    localparam PCK_INJCT_w = $bits(pck_injct_t); 
+    
+    localparam DELAYw = 9; //Injector start delay counter width. 10 to 500 clk cycles delay randomly selected
+    
+    typedef struct packed {
+        integer   ip_num;
+        bit send_enable;
+        integer  percentage; // x10
+    } hotspot_t;
     
     typedef struct packed {
-    	logic [BYPASSw-1 : 0] bypassed_num;
-    	bit flit_wr_i;
-    	bit pck_wr_i;
-    	bit flit_wr_o;
-    	bit pck_wr_o;
-    	bit flit_in_bypassed;
-    	bit active_high_reset; // if asserted means ProNoC is configured with active high reset    	
-    	bit empty;  // if asseted means there is no flit in this router port      	
+        integer value;
+        integer percentage;
+    }rnd_discrete_t;
+    
+     //packet injector interface
+    localparam PCK_INJ_Dw =64;//TODO to be defined by user
+    localparam PCK_SIZw= log2(MAX_PCK_SIZ+1);
+    
+    typedef struct packed {
+        logic [PCK_INJ_Dw-1 : 0] data;
+        logic [PCK_SIZw-1 : 0] size;
+        logic [DAw-1 : 0] endp_addr; 
+        logic [Cw-1  : 0] class_num; 
+        logic [WEIGHTw-1   : 0] init_weight;
+        logic [V-1   : 0] vc;
+        bit   pck_wr;
+        bit   [V-1   : 0] ready;
+        logic [DISTw-1 : 0] distance;
+        logic [15: 0]  h2t_delay;
+    }    pck_injct_t;
+    localparam PCK_INJCT_w = $bits(pck_injct_t);
+    
+    typedef struct packed {
+        logic [BYPASSw-1 : 0] bypassed_num;
+        bit flit_wr_i;
+        bit pck_wr_i;
+        bit flit_wr_o;
+        bit pck_wr_o;
+        bit flit_in_bypassed;
+        bit active_high_reset; // if asserted means ProNoC is configured with active high reset
+        bit empty;  // if asseted means there is no flit in this router port
     } router_event_t;
     localparam ROUTER_EVENT_w = $bits(router_event_t); 
     
+    
 
-`ifdef IMPORT_PRONOC_PCK	
-endpackage : pronoc_pkg
-`endif
+endpackage : pronoc_pkg  
 
-`endif
diff --git a/mpsoc/rtl/src_noc/route_mesh.v b/mpsoc/rtl/src_noc/route_mesh.sv
similarity index 53%
rename from mpsoc/rtl/src_noc/route_mesh.v
rename to mpsoc/rtl/src_noc/route_mesh.sv
index cd42a96..8273883 100755
--- a/mpsoc/rtl/src_noc/route_mesh.v
+++ b/mpsoc/rtl/src_noc/route_mesh.sv
@@ -1,178 +1,149 @@
-`timescale     1ns/1ps
-
+`include "pronoc_def.v"
 /**********************************************************************
-**	File:  route_mesh.v
+**    File:  route_mesh.v
 **    
-**	Copyright (C) 2014-2017  Alireza Monemi
+**    Copyright (C) 2014-2017  Alireza Monemi
 **    
-**	This file is part of ProNoC 
+**    This file is part of ProNoC 
 **
-**	ProNoC ( stands for Prototype Network-on-chip)  is free software: 
-**	you can redistribute it and/or modify it under the terms of the GNU
-**	Lesser General Public License as published by the Free Software Foundation,
-**	either version 2 of the License, or (at your option) any later version.
+**    ProNoC ( stands for Prototype Network-on-chip)  is free software: 
+**    you can redistribute it and/or modify it under the terms of the GNU
+**    Lesser General Public License as published by the Free Software Foundation,
+**    either version 2 of the License, or (at your option) any later version.
 **
-** 	ProNoC is distributed in the hope that it will be useful, but WITHOUT
-** 	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
-** 	or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
-** 	Public License for more details.
+**     ProNoC is distributed in the hope that it will be useful, but WITHOUT
+**     ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+**     or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
+**     Public License for more details.
 **
-** 	You should have received a copy of the GNU Lesser General Public
-** 	License along with ProNoC. If not, see <http:**www.gnu.org/licenses/>.
+**     You should have received a copy of the GNU Lesser General Public
+**     License along with ProNoC. If not, see <http:**www.gnu.org/licenses/>.
 **
 **
-**	Description: 
-**	Different routing algorithms (determinstic,partially adaptive and fully adaptive)
-**	for 2D mesh-based topology
+**    Description: 
+**    Different routing algorithms (determinstic,partially adaptive and fully adaptive)
+**    for 2D mesh-based topology
 **
 **************************************************************/
 
 
 /********************************************
-                    Deterministic
+*                    Deterministic
 *********************************************/
 
-
-    /*****************************************************
-                    xy_mesh_routing
-
-    *****************************************************/
-
-
-
+/*****************************************************
+*                xy_mesh_routing
+*****************************************************/
 module xy_mesh_routing #(
     parameter NX        =    4,
     parameter NY        =    3
-)
-(
+)(
     current_x,    // current router x address
     current_y,    // current router y address
     dest_x,        // destination x address
     dest_y,        // destination y address
     dstport_encoded    // router output port
-        
 );
-    
-
     function integer log2;
-      input integer number; begin   
-         log2=(number <=1) ? 1: 0;    
-         while(2**log2<number) begin    
+    input integer number; begin   
+        log2=(number <=1) ? 1: 0;    
+        while(2**log2<number) begin    
             log2=log2+1;    
-         end        
-      end   
+        end        
+    end   
     endfunction // log2 
-
-    localparam  P            =    5;    // router port number is always 5 in a mesh topology
-    
-    localparam  Xw            =    log2(NX),
-                Yw            =    log2(NY),
-                DSTw          =    P-1;
-
-    
-    
-    input  [Xw-1        :0]    current_x;
-    input  [Yw-1        :0]    current_y;
-    input  [Xw-1        :0]    dest_x;
-    input  [Yw-1        :0]    dest_y;
-    output [DSTw-1      :0]    dstport_encoded;
-
+    localparam  
+        P = 5,    // router port number is always 5 in a mesh topology
+        Xw = log2(NX),
+        Yw = log2(NY),
+        DSTw = P-1;
+    
+    input  [Xw-1 :0]    current_x;
+    input  [Yw-1 :0]    current_y;
+    input  [Xw-1 :0]    dest_x;
+    input  [Yw-1 :0]    dest_y;
+    output [DSTw-1 :0]    dstport_encoded;
     
     localparam OUT_BIN=0;
-
-    localparam  LOCAL    =    (OUT_BIN==1)?    0    :  1 ,//5'b00001
-                EAST     =    (OUT_BIN==1)?    1    :  2 ,//5'b00010 
-                NORTH    =    (OUT_BIN==1)?    2    :  4 ,//5'b00100    
-                WEST     =    (OUT_BIN==1)?    3    :  8 ,//5'b01000  
-                SOUTH    =    (OUT_BIN==1)?    4    : 16 ;//5'b10000    
-    
-    
-    
-    
-    
+    localparam  
+        LOCAL    =    (OUT_BIN==1)?    0 :  1 ,//5'b00001
+        EAST     =    (OUT_BIN==1)?    1 :  2 ,//5'b00010 
+        NORTH    =    (OUT_BIN==1)?    2 :  4 ,//5'b00100    
+        WEST     =    (OUT_BIN==1)?    3 :  8 ,//5'b01000  
+        SOUTH    =    (OUT_BIN==1)?    4 : 16 ;//5'b10000    
     reg [P-1 : 0] dstport_one_hot;    
-   
     
     always@(*)begin
-            dstport_one_hot    = LOCAL [P-1    :0];
-            if           (dest_x    > current_x)     dstport_one_hot    = EAST [P-1    :0];
-            else if      (dest_x    < current_x)     dstport_one_hot    = WEST [P-1    :0];
-            else begin
-            if         (dest_y    > current_y)       dstport_one_hot    = SOUTH [P-1   :0];
-            else if      (dest_y    < current_y)     dstport_one_hot    = NORTH [P-1   :0];
-            end
+        dstport_one_hot    = LOCAL [P-1 :0];
+        if           (dest_x    > current_x)     dstport_one_hot    = EAST [P-1 :0];
+        else if      (dest_x    < current_x)     dstport_one_hot    = WEST [P-1 :0];
+        else begin
+        if         (dest_y    > current_y)       dstport_one_hot    = SOUTH [P-1 :0];
+        else if      (dest_y    < current_y)     dstport_one_hot    = NORTH [P-1 :0];
+        end
     end
     
-    mesh_tori_encode_dstport conv(
-    	.dstport_one_hot(dstport_one_hot),
-    	.dstport_encoded(dstport_encoded)
+    regular_topo_encode_dstport conv(
+        .dstport_one_hot(dstport_one_hot),
+        .dstport_encoded(dstport_encoded)
     );
-    
-    
 endmodule
 
 /********************************************
-                    Partial adaptive
-The west-first routing algorithm does not allow turns from north to west or from south to west.                    
-The north last routing algorithm does not allow turns from north to east or from north to west.
-The negetive fist routing algorithm does net allow turns from north to west or from east to south.
-
-                    
+*                    Partial adaptive
+*The west-first routing algorithm does not allow turns from north to west or from south to west.                    
+*The north last routing algorithm does not allow turns from north to east or from north to west.
+*The negetive fist routing algorithm does net allow turns from north to west or from east to south.
 *********************************************/
 
 /************************************
-
-                west-first
-                 
+*          west-first
+*            
 *************************************/
 module west_first_routing #(
-        parameter NX    =   4,
-        parameter NY    =   4
-    )
-    (       
-        current_x,  // current router x address
-        current_y,  // current router y address
-        dest_x,     // destination x address
-        dest_y,     // destination y address
-        destport    // router output port
-            
+    parameter NX    =   4,
+    parameter NY    =   4
+    )  (       
+    current_x,  // current router x address
+    current_y,  // current router y address
+    dest_x,     // destination x address
+    dest_y,     // destination y address
+    destport    // router output port
     );
-   
-   
+    
     function integer log2;
-      input integer number; begin   
-         log2=(number <=1) ? 1: 0;    
-         while(2**log2<number) begin    
+    input integer number; begin   
+        log2=(number <=1) ? 1: 0;    
+        while(2**log2<number) begin    
             log2=log2+1;    
-         end 	   
-      end   
+        end        
+    end   
     endfunction // log2 
-   
-    localparam  P   =   5,
-                P_1 =    P-1,
-                Xw  =   log2(NX),
-                Yw  =   log2(NY);
-
-    input  [Xw-1        :0] current_x;
-    input  [Yw-1        :0] current_y;
-    input  [Xw-1        :0] dest_x;
-    input  [Yw-1        :0] dest_y;
-    output [P_1-1       :0] destport;
-       
-    localparam  LOCAL=   3'd0,  
-                EAST =   3'd1, 
-                NORTH=   3'd2, 
-                WEST =   3'd3,  
-                SOUTH=   3'd4;  
     
+    localparam  
+        P   =   5,
+        P_1 =    P-1,
+        Xw  =   log2(NX),
+        Yw  =   log2(NY);
+    input  [Xw-1 :0] current_x;
+    input  [Yw-1 :0] current_y;
+    input  [Xw-1 :0] dest_x;
+    input  [Yw-1 :0] dest_y;
+    output [P_1-1 :0] destport;
+    
+    localparam  
+        LOCAL=   3'd0,  
+        EAST =   3'd1, 
+        NORTH=   3'd2, 
+        WEST =   3'd3,  
+        SOUTH=   3'd4;  
     
     wire x_plus,x_min,y_plus,y_min,same_x,same_y;
     
     mesh_dir #(
         .NX(NX),
         .NY(NY)
-    )
-    dir(
+    ) dir(
         .current_x(current_x),
         .current_y(current_y),
         .dest_x(dest_x),
@@ -183,11 +154,9 @@ module west_first_routing #(
         .y_min(y_min),
         .same_x(same_x),
         .same_y(same_y)
-        
     );
     
-    reg [4  :   0]  possible_out_port;
-    
+    reg [4 :   0]  possible_out_port;
     //The west-first routing algorithm does not allow turns from north to west or from south to west. 
     always @(*)begin    
         possible_out_port = 5'd0;
@@ -227,62 +196,50 @@ endmodule
 
 
 /************************************
-              
-             
-             north-last
-              
-              
- *************************************/
-
-
+*        north-last
+*************************************/
 module north_last_routing #(
-        parameter NX    =   4,
-        parameter NY    =   4
-    )
-    (       
-        current_x,  // current router x address
-        current_y,  // current router y address
-        dest_x,     // destination x address
-        dest_y,     // destination y address
-        destport    // router output port
-            
-    );
-   
-  
+    parameter NX    =   4,
+    parameter NY    =   4
+) (       
+    current_x,  // current router x address
+    current_y,  // current router y address
+    dest_x,     // destination x address
+    dest_y,     // destination y address
+    destport    // router output port
+);
     function integer log2;
-      input integer number; begin   
-         log2=(number <=1) ? 1: 0;    
-         while(2**log2<number) begin    
+    input integer number; begin   
+        log2=(number <=1) ? 1: 0;    
+        while(2**log2<number) begin    
             log2=log2+1;    
-         end 	   
-      end   
+        end        
+    end   
     endfunction // log2 
-   
-    localparam  P   =   5,
-                P_1 =    P-1,
-                Xw  =   log2(NX),
-                Yw  =   log2(NY);
-
-    input  [Xw-1        :0] current_x;
-    input  [Yw-1        :0] current_y;
-    input  [Xw-1        :0] dest_x;
-    input  [Yw-1        :0] dest_y;
-    output [P_1-1       :0] destport;
-       
-    localparam  LOCAL=   3'd0,  
-                EAST =   3'd1, 
-                NORTH=   3'd2, 
-                WEST =   3'd3,  
-                SOUTH=   3'd4;  
     
+    localparam
+        P   =   5,
+        P_1 =    P-1,
+        Xw  =   log2(NX),
+        Yw  =   log2(NY);
+    input  [Xw-1 :0] current_x;
+    input  [Yw-1 :0] current_y;
+    input  [Xw-1 :0] dest_x;
+    input  [Yw-1 :0] dest_y;
+    output [P_1-1 :0] destport;
+    
+    localparam  
+        LOCAL=   3'd0,  
+        EAST =   3'd1, 
+        NORTH=   3'd2, 
+        WEST =   3'd3,  
+        SOUTH=   3'd4;  
     
     wire x_plus,x_min,y_plus,y_min,same_x,same_y;
-    
     mesh_dir #(
         .NX(NX),
         .NY(NY)
-    )
-    dir(
+    ) dir(
         .current_x(current_x),
         .current_y(current_y),
         .dest_x(dest_x),
@@ -293,13 +250,10 @@ module north_last_routing #(
         .y_min(y_min),
         .same_x(same_x),
         .same_y(same_y)
-        
     );
     
-    reg [4  :   0]  possible_out_port;
-    
-   // north last routing algorithm does not allow turns from north to east or from north to west.
-    
+    reg [4 :   0]  possible_out_port;
+    // north last routing algorithm does not allow turns from north to east or from north to west.
     always @(*)begin   
         possible_out_port   = 5'd0;
         if(same_x &&  same_y) begin 
@@ -334,8 +288,7 @@ module north_last_routing #(
             possible_out_port   [SOUTH]= 1'b1;
         end
     end
-       
-   
+    
     // code the destination port
     wire x,y,a,b;
     assign x = x_plus;
@@ -347,62 +300,50 @@ endmodule
 
 
 /****************************
-
-        
-        negetive-first
-        
-
+*    negetive-first
 ******************************/
-
-
 module negetive_first_routing #(
-        parameter NX    =   4,
-        parameter NY    =   4
-    )
-    (       
-        current_x,  // current router x address
-        current_y,  // current router y address
-        dest_x,     // destination x address
-        dest_y,     // destination y address
-        destport    // router output port
-            
-    );
-   
-    
+    parameter NX    =   4,
+    parameter NY    =   4
+) (       
+    current_x,  // current router x address
+    current_y,  // current router y address
+    dest_x,     // destination x address
+    dest_y,     // destination y address
+    destport    // router output port
+);
     function integer log2;
-      input integer number; begin   
-         log2=(number <=1) ? 1: 0;    
-         while(2**log2<number) begin    
+    input integer number; begin   
+        log2=(number <=1) ? 1: 0;    
+        while(2**log2<number) begin    
             log2=log2+1;    
-         end 	   
-      end   
+        end        
+    end   
     endfunction // log2 
-   
-    localparam  P   =   5,
-                P_1 =    P-1,
-                Xw  =   log2(NX),
-                Yw  =   log2(NY);
-
-    input  [Xw-1        :0] current_x;
-    input  [Yw-1        :0] current_y;
-    input  [Xw-1        :0] dest_x;
-    input  [Yw-1        :0] dest_y;
-    output [P_1-1       :0] destport;
-       
-    localparam  LOCAL=   3'd0,  
-                EAST =   3'd1, 
-                NORTH=   3'd2, 
-                WEST =   3'd3,  
-                SOUTH=   3'd4;  
-    
     
+    localparam  
+        P   =   5,
+        P_1 =    P-1,
+        Xw  =   log2(NX),
+        Yw  =   log2(NY);
+    input  [Xw-1 :0] current_x;
+    input  [Yw-1 :0] current_y;
+    input  [Xw-1 :0] dest_x;
+    input  [Yw-1 :0] dest_y;
+    output [P_1-1 :0] destport;
+    
+    localparam  
+        LOCAL=   3'd0,  
+        EAST =   3'd1, 
+        NORTH=   3'd2, 
+        WEST =   3'd3,  
+        SOUTH=   3'd4;  
     wire x_plus,x_min,y_plus,y_min,same_x,same_y;
     
     mesh_dir #(
         .NX(NX),
         .NY(NY)
-    )
-    dir(
+    ) dir(
         .current_x(current_x),
         .current_y(current_y),
         .dest_x(dest_x),
@@ -413,13 +354,10 @@ module negetive_first_routing #(
         .y_min(y_min),
         .same_x(same_x),
         .same_y(same_y)
-        
     );
     
-    reg [4  :   0]  possible_out_port;
-    
- // The negetive fist routing algorithm does net allow turns from north to west or from east to south.
-    
+    reg [4 :   0]  possible_out_port;
+    // The negetive fist routing algorithm does net allow turns from north to west or from east to south.
     always @(*)begin   
         possible_out_port   = 5'd0;
         if(same_x &&  same_y) begin 
@@ -454,7 +392,7 @@ module negetive_first_routing #(
             possible_out_port   [SOUTH]= 1'b1;
         end
     end
-      
+    
     // code the destination port
     wire x,y,a,b;
     assign x = x_plus;
@@ -466,83 +404,66 @@ endmodule
 
 
 /****************************************
-
-            odd_even
-
+*        odd_even
 ***************************************/
-
-
-
-
 module odd_even_routing #(
-        parameter NX        =    4,
-        parameter NY        =    4,
-        parameter LOCATED_IN_NI        =    1 // 1: the router locaed inside ni                     
-                                                  // 0: the routing module located inside router
-    )
-    (
-        current_x,    // current router x address
-        current_y,    // current router y address
-        dest_x,        // destination x address
-        dest_y,        // destination y address
-        destport    // router output port
-        
-    );
-
-        
-    
-   
+    parameter NX = 4,
+    parameter NY = 4,
+    parameter LOCATED_IN_NI = 1 // 1: the router locaed inside ni                     
+                                // 0: the routing module located inside router
+) (
+    current_x,    // current router x address
+    current_y,    // current router y address
+    dest_x,        // destination x address
+    dest_y,        // destination y address
+    destport    // router output port
+);
     function integer log2;
-      input integer number; begin   
-         log2=(number <=1) ? 1: 0;    
-         while(2**log2<number) begin    
+    input integer number; begin   
+        log2=(number <=1) ? 1: 0;    
+        while(2**log2<number) begin    
             log2=log2+1;    
-         end 	   
-      end   
+        end        
+    end   
     endfunction // log2 
     
-    localparam     P    =    5,
-                P_1 =   P-1,               
-                Xw    =    log2(NX),
-                Yw    =    log2(NY);
-
-    input  [Xw-1        :0]    current_x;
-    input  [Yw-1        :0]    current_y;
-    input  [Xw-1        :0]    dest_x;
-    input  [Yw-1        :0]    dest_y;
-    output [P_1-1         :0]    destport;
-    
-    
-    
-    localparam LOCAL   =        3'd0;  
-    localparam EAST       =        3'd1; 
-    localparam NORTH   =        3'd2;  
-    localparam WEST       =        3'd3;  
-    localparam SOUTH   =        3'd4;  
-    
-    wire signed [Xw        :0] xc;//current 
-    wire signed [Xw        :0] xd;//destination
-    wire signed [Yw        :0] yc;//current 
-    wire signed [Yw        :0] yd;//destination
-    wire signed [Xw        :0] xdiff;
-    wire signed [Yw        :0] ydiff; 
-    
-    
-    assign     xc     ={1'b0, current_x [Xw-1        :0]};
-    assign     yc     ={1'b0, current_y [Yw-1        :0]};
-    assign    xd    ={1'b0, dest_x};
-    assign    yd     ={1'b0, dest_y};
-    assign     xdiff    = xd-xc;
-    assign    ydiff    = yd-yc;
-    
-    reg [P-1    :    0]    possible_out_port;
-    
-    
+    localparam 
+        P =  5,
+        P_1 =  P-1,               
+        Xw = log2(NX),
+        Yw = log2(NY);
+    input  [Xw-1 : 0]    current_x;
+    input  [Yw-1 : 0]    current_y;
+    input  [Xw-1 : 0]    dest_x;
+    input  [Yw-1 : 0]    dest_y;
+    output [P_1-1 : 0]    destport;   
+    
+    localparam LOCAL =  3'd0;  
+    localparam EAST  =  3'd1; 
+    localparam NORTH =  3'd2;  
+    localparam WEST  =  3'd3;  
+    localparam SOUTH =  3'd4;  
+    
+    wire signed [Xw :0] xc;//current 
+    wire signed [Xw :0] xd;//destination
+    wire signed [Yw :0] yc;//current 
+    wire signed [Yw :0] yd;//destination
+    wire signed [Xw :0] xdiff;
+    wire signed [Yw :0] ydiff; 
+    
+    assign xc = {1'b0, current_x [Xw-1 :0]};
+    assign yc = {1'b0, current_y [Yw-1 :0]};
+    assign xd = {1'b0, dest_x};
+    assign yd = {1'b0, dest_y};
+    assign xdiff = xd-xc;
+    assign ydiff = yd-yc;
+    
+    reg [P-1 : 0] possible_out_port;
     
     always @(*)begin     
         possible_out_port = 5'd0;
         if (xdiff == 0 && ydiff == 0) begin 
-                possible_out_port [LOCAL]=1'b1;
+            possible_out_port [LOCAL]=1'b1;
         end
         else if(xdiff ==0) begin //currently in the same column as destination
             if( ydiff<0) begin 
@@ -587,10 +508,8 @@ module odd_even_routing #(
                 end
             end
         end
-        end
-        
-        
-        
+    end     
+    
     // code the destination port
     wire x,y,a,b;
     assign x = (xdiff > 0);
@@ -598,79 +517,63 @@ module odd_even_routing #(
     assign a = possible_out_port[EAST] | possible_out_port[WEST]; 
     assign b = possible_out_port[NORTH]| possible_out_port[SOUTH];
     assign destport = {x,y,a,b};
-
-    
-    
-    
 endmodule 
-    
-/***********************************
-        fully adaptive
 
+
+/***********************************
+*     fully adaptive
 ***********************************/
-    
-    
-    /************************************
 
-        Duato’s Fully Adaptive
-The packet which can travel in both x & y dimension can not use the reserved VC in y axies
-    *************************************/    
-    
-    
-    
+/************************************
+*        Duato’s Fully Adaptive
+* The packet which can travel in both x & y dimension 
+* can not use the reserved VC in y axies
+**************************************/    
 module duato_mesh_routing #(
-        parameter NX    =    4,
-        parameter NY    =    4
-    )
-    (        
-        current_x,    // current router x address
-        current_y,    // current router y address
-        dest_x,        // destination x address
-        dest_y,        // destination y address
-        destport    // router output port
-        
-    );
+    parameter NX    =    4,
+    parameter NY    =    4
+)(        
+    current_x,    // current router x address
+    current_y,    // current router y address
+    dest_x,        // destination x address
+    dest_y,        // destination y address
+    destport    // router output port
+);
 
-        
-    
-  
     function integer log2;
-      input integer number; begin   
-         log2=(number <=1) ? 1: 0;    
-         while(2**log2<number) begin    
+    input integer number; begin   
+        log2=(number <=1) ? 1: 0;    
+        while(2**log2<number) begin    
             log2=log2+1;    
-         end 	   
-      end   
+        end        
+    end   
     endfunction // log2 
     
+    localparam
+        P  =  5,
+        P_1 =  P-1,    
+        Xw =  log2(NX),
+        Yw = log2(NY);
     
-    localparam     P    =    5,
-                P_1 =   P-1,    
-                Xw    =    log2(NX),
-                Yw    =    log2(NY);
-
-    input  [Xw-1        :0]    current_x;
-    input  [Yw-1        :0]    current_y;
-    input  [Xw-1        :0]    dest_x;
-    input  [Yw-1        :0]    dest_y;
-    output [P_1-1        :0]    destport;
-    
-
-    
-    localparam  LOCAL=   3'd0,  
-                EAST =   3'd1, 
-                NORTH=   3'd2, 
-                WEST =   3'd3,  
-                SOUTH=   3'd4;  
+    input  [Xw-1 :0]    current_x;
+    input  [Yw-1 :0]    current_y;
+    input  [Xw-1 :0]    dest_x;
+    input  [Yw-1 :0]    dest_y;
+    output [P_1-1 :0]    destport;
     
+    localparam  
+        LOCAL=   3'd0,  
+        EAST =   3'd1, 
+        NORTH=   3'd2, 
+        WEST =   3'd3,  
+        SOUTH=   3'd4;  
     
     wire x_plus,x_min,y_plus,y_min,same_x,same_y;
     
     mesh_dir #(
         .NX(NX),
         .NY(NY)
-    )
-    dir(
+    ) dir(
         .current_x(current_x),
         .current_y(current_y),
         .dest_x(dest_x),
@@ -681,12 +584,9 @@ module duato_mesh_routing #(
         .y_min(y_min),
         .same_x(same_x),
         .same_y(same_y)
-        
     );
-        
-    
-    reg [P-1    :    0]    possible_out_port;
     
+    reg [P-1 :    0]    possible_out_port;
     always @(*)begin   
         possible_out_port       = 5'd0;
         if(same_x &&  same_y) begin 
@@ -721,7 +621,6 @@ module duato_mesh_routing #(
             possible_out_port   [SOUTH]= 1'b1;
         end
     end
-   
     
     // code the destination port
     wire   x,y,a,b;
@@ -730,15 +629,9 @@ module duato_mesh_routing #(
     assign a = possible_out_port[EAST] | possible_out_port[WEST]; 
     assign b = possible_out_port[NORTH]| possible_out_port[SOUTH];
     assign destport = {x,y,a,b};
-    
-    
-    
 endmodule
-    
-        
 
 
-        
 module mesh_dir #(
     parameter NX   =    4,
     parameter NY   =    4
@@ -755,78 +648,63 @@ module mesh_dir #(
     same_y
 );
 
- 
     function integer log2;
-      input integer number; begin   
-         log2=(number <=1) ? 1: 0;    
-         while(2**log2<number) begin    
+    input integer number; begin   
+        log2=(number <=1) ? 1: 0;    
+        while(2**log2<number) begin    
             log2=log2+1;    
-         end 	   
-      end   
+        end        
+    end   
     endfunction // log2 
-        
-    localparam  Xw          =   log2(NX),
-                Yw          =   log2(NY);
-
+    
+    localparam  
+        Xw  =   log2(NX),
+        Yw  =   log2(NY);
+    
     output x_plus;
     output x_min;
     output y_plus;
     output y_min;
     output same_x,same_y;
     
-    input   [Xw-1       :   0] current_x;
-    input   [Yw-1       :   0] current_y;
-    input   [Xw-1       :   0] dest_x;
-    input   [Yw-1       :   0] dest_y;
-
-   
-
+    input   [Xw-1 :   0] current_x;
+    input   [Yw-1 :   0] current_y;
+    input   [Xw-1 :   0] dest_x;
+    input   [Yw-1 :   0] dest_y;
+    
     assign same_x = (current_x == dest_x);
     assign same_y = (current_y == dest_y);
     assign x_plus = (dest_x  > current_x);
     assign x_min  = (dest_x  < current_x);
     assign y_plus = (dest_y  > current_y);
     assign y_min  = (dest_y  < current_y);
-   
-   
-
 endmodule
 
 
-
-
-module mesh_tori_encode_dstport (
+module regular_topo_encode_dstport (
     dstport_one_hot,
     dstport_encoded
 );
-
     input  [4 : 0] dstport_one_hot;
     output [3 : 0] dstport_encoded; 
     
-    
-     localparam
+    localparam
         //LOCAL=   3'd0,  
         EAST =   3'd1, 
         NORTH=   3'd2, 
         WEST =   3'd3,  
         SOUTH=   3'd4;  
-    
     /************************                
-        destination-port_in
-            x:  1 EAST, 0 WEST  
-            y:  1 NORTH, 0 SOUTH
-            ab: 00 : LOCAL, 10: xdir, 01: ydir, 11 x&y dir 
+    *    destination-port_in
+    *        x:  1 EAST, 0 WEST  
+    *        y:  1 NORTH, 0 SOUTH
+    *        ab: 00 : LOCAL, 10: xdir, 01: ydir, 11 x&y dir 
     *******************/
-// code the destination port
+    // code the destination port
     wire   x,y,a,b;
     assign x = dstport_one_hot[EAST];
     assign y = dstport_one_hot[NORTH];
     assign a = dstport_one_hot[EAST] | dstport_one_hot[WEST]; 
     assign b = dstport_one_hot[NORTH]| dstport_one_hot[SOUTH];
     assign dstport_encoded = {x,y,a,b};
-
-endmodule
-
-
-
-
+endmodule
\ No newline at end of file
diff --git a/mpsoc/rtl/src_noc/route_torus.v b/mpsoc/rtl/src_noc/route_torus.sv
similarity index 59%
rename from mpsoc/rtl/src_noc/route_torus.v
rename to mpsoc/rtl/src_noc/route_torus.sv
index b7e4c16..66c3539 100755
--- a/mpsoc/rtl/src_noc/route_torus.v
+++ b/mpsoc/rtl/src_noc/route_torus.sv
@@ -1,75 +1,71 @@
-`timescale 1ns/1ps
+`include "pronoc_def.v"
 
 /**********************************************************************
-**	File:  route_torus.v
+**    File: route_torus.v
 **    
-**	Copyright (C) 2014-2017  Alireza Monemi
+**    Copyright (C) 2014-2017  Alireza Monemi
 **    
-**	This file is part of ProNoC 
+**    This file is part of ProNoC 
 **
-**	ProNoC ( stands for Prototype Network-on-chip)  is free software: 
-**	you can redistribute it and/or modify it under the terms of the GNU
-**	Lesser General Public License as published by the Free Software Foundation,
-**	either version 2 of the License, or (at your option) any later version.
+**    ProNoC ( stands for Prototype Network-on-chip)  is free software: 
+**    you can redistribute it and/or modify it under the terms of the GNU
+**    Lesser General Public License as published by the Free Software Foundation,
+**    either version 2 of the License, or (at your option) any later version.
 **
-** 	ProNoC is distributed in the hope that it will be useful, but WITHOUT
-** 	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
-** 	or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
-** 	Public License for more details.
+**     ProNoC is distributed in the hope that it will be useful, but WITHOUT
+**     ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+**     or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
+**     Public License for more details.
 **
-** 	You should have received a copy of the GNU Lesser General Public
-** 	License along with ProNoC. If not, see <http:**www.gnu.org/licenses/>.
+**     You should have received a copy of the GNU Lesser General Public
+**     License along with ProNoC. If not, see <http:**www.gnu.org/licenses/>.
 **
 **
-**	Description: 
-**	Different routing algorithms (determinstic,partially adaptive and fully adaptive)
-**	for 2D torus-based topology
+**    Description: 
+**    Different routing algorithms (determinstic,partially adaptive and fully adaptive)
+**    for 2D torus-based topology
 **
 **************************************************************/
 
 
 /********************************************
-                    Deterministic
+*                    Deterministic
 *********************************************/
 
-    /********************************************
-                        TRANC
-    *********************************************/
+/********************************************
+*                    TRANC
+*********************************************/
 module tranc_xy_routing #(
     parameter NX   =    4,
     parameter NY   =    4   
-)
-(
+)(
     current_x,
     current_y,
     dest_x,
     dest_y,
     destport_encoded
-    
 );
-
-
     function integer log2;
-      input integer number; begin   
-         log2=(number <=1) ? 1: 0;    
-         while(2**log2<number) begin    
+    input integer number; begin   
+        log2=(number <=1) ? 1: 0;    
+        while(2**log2<number) begin    
             log2=log2+1;    
-         end 	   
-      end   
+        end        
+    end   
     endfunction // log2 
     
-    localparam  P           =   5,
-                Xw          =   log2(NX),
-                Yw          =   log2(NY),
-                Pw          =   log2(P),
-                DSTw        =   P-1;
-    
+    localparam  
+        P           =   5,
+        Xw          =   log2(NX),
+        Yw          =   log2(NY),
+        Pw          =   log2(P),
+        DSTw        =   P-1;
     
-    input   [Xw-1       :   0] current_x;
-    input   [Yw-1       :   0] current_y;
-    input   [Xw-1       :   0] dest_x;
-    input   [Yw-1       :   0] dest_y;
-    output  [DSTw -1    :   0] destport_encoded;
+    input   [Xw-1 : 0] current_x;
+    input   [Yw-1 : 0] current_y;
+    input   [Xw-1 : 0] dest_x;
+    input   [Yw-1 : 0] dest_y;
+    output  [DSTw -1 : 0] destport_encoded;
     
     localparam      
         LOCAL   =   5'b00001,  
@@ -77,17 +73,13 @@ module tranc_xy_routing #(
         NORTH   =   5'b00100,    
         WEST    =   5'b01000,  
         SOUTH   =   5'b10000;    
-    
-   
     wire tranc_x_plus,tranc_y_plus,tranc_x_min,tranc_y_min;
-    wire same_x,same_y;
-    
+    wire same_x,same_y; 
     
     tranc_dir #(
         .NX(NX),
         .NY(NY)
-    )
-    tranc_dir(
+    ) tranc_dir(
         .tranc_x_plus(tranc_x_plus),
         .tranc_x_min(tranc_x_min),
         .tranc_y_plus(tranc_y_plus),
@@ -98,12 +90,9 @@ module tranc_xy_routing #(
         .current_y(current_y),
         .dest_x(dest_x),
         .dest_y(dest_y)
-        
     );
-       
-        reg [P-1 : 0] dstport_one_hot;
-        
-        
+    reg [P-1 : 0] dstport_one_hot;
+    
     always@(*)begin
         if (same_x & same_y) dstport_one_hot= LOCAL;
         else    begin 
@@ -114,80 +103,64 @@ module tranc_xy_routing #(
         end
     end
     
-    mesh_tori_encode_dstport conv(
-    	.dstport_one_hot(dstport_one_hot),
-    	.dstport_encoded(destport_encoded)
+    regular_topo_encode_dstport conv(
+        .dstport_one_hot(dstport_one_hot),
+        .dstport_encoded(destport_encoded)
     );
-    
-
-  
-    
-    endmodule
+endmodule
 
 /********************************************
-                    Partial adaptive
+*                    Partial adaptive
 *********************************************/
 
-    /********************************************
-                    TRANC West-First 
-    *********************************************/
-
-    
-    module tranc_west_first_routing #(
-       parameter NX   =   4,
-       parameter NY    =   4
-    )
-    (       
-        current_x,  // current router x address
-        current_y,  // current router y address
-        dest_x,     // destination x address
-        dest_y,     // destination y address
-        destport    // router output port
-        
-        
-    );
+/********************************************
+*                   TRANC West-First 
+*********************************************/
 
-        
     
-
+module tranc_west_first_routing #(
+    parameter NX   =   4,
+    parameter NY    =   4
+) (       
+    current_x,  // current router x address
+    current_y,  // current router y address
+    dest_x,     // destination x address
+    dest_y,     // destination y address
+    destport    // router output port
+);
     function integer log2;
-      input integer number; begin   
-         log2=(number <=1) ? 1: 0;    
-         while(2**log2<number) begin    
+    input integer number; begin   
+        log2=(number <=1) ? 1: 0;    
+        while(2**log2<number) begin    
             log2=log2+1;    
-         end        
-      end   
+        end        
+    end   
     endfunction // log2 
     
+    localparam  
+        P   =   5,
+        P_1 =   P-1,
+        Xw  =   log2(NX),
+        Yw  =   log2(NY);
+    input  [Xw-1 :0] current_x;
+    input  [Yw-1 :0] current_y;
+    input  [Xw-1 :0] dest_x;
+    input  [Yw-1 :0] dest_y;
+    output [P_1-1 :0] destport;
     
-    localparam  P   =   5,
-                P_1 =   P-1,
-                Xw  =   log2(NX),
-                Yw  =   log2(NY);
-
-    input  [Xw-1        :0] current_x;
-    input  [Yw-1        :0] current_y;
-    input  [Xw-1        :0] dest_x;
-    input  [Yw-1        :0] dest_y;
-    output [P_1-1       :0] destport;
-   
-
-        
     localparam LOCAL=   3'd0;  
     localparam EAST =   3'd1; 
     localparam NORTH=   3'd2;  
     localparam WEST =   3'd3;  
     localparam SOUTH=   3'd4;  
-        
+    
     wire tranc_x_plus,tranc_y_plus,tranc_x_min,tranc_y_min;
     wire same_x,same_y;
     
-    
     tranc_dir #(
         .NX(NX),
         .NY(NY)
-    )
-    tranc_dir(
+    ) tranc_dir(
         .tranc_x_plus(tranc_x_plus),
         .tranc_x_min(tranc_x_min),
         .tranc_y_plus(tranc_y_plus),
@@ -198,11 +171,9 @@ module tranc_xy_routing #(
         .current_y(current_y),
         .dest_x(dest_x),
         .dest_y(dest_y)
-        
     );
     
-    reg [P-1    :    0]    possible_out_port;
-    
+    reg [P-1 : 0]    possible_out_port;
     always @(*)begin     
         possible_out_port = 5'd0;
         if(same_x && same_y) begin
@@ -237,73 +208,56 @@ module tranc_xy_routing #(
     assign a = possible_out_port[EAST] | possible_out_port[WEST]; 
     assign b = possible_out_port[NORTH]| possible_out_port[SOUTH];
     assign destport = {x,y,a,b};
-    
-    
-    endmodule
-    
-    
-    
-    /********************************************
-                    TRANC North-Last 
-    *********************************************/
+endmodule
 
-    
-    module tranc_north_last_routing #(
-       parameter NX   =   4,
-       parameter NY    =   4
-    )
-    (       
-        current_x,  // current router x address
-        current_y,  // current router y address
-        dest_x,     // destination x address
-        dest_y,     // destination y address
-        destport    // router output port
-        
-        
-    );
 
-        
-    
- 
-    
+
+/********************************************
+*                 TRANC North-Last 
+*********************************************/
+
+module tranc_north_last_routing #(
+    parameter NX   =   4,
+    parameter NY    =   4
+) (       
+    current_x,  // current router x address
+    current_y,  // current router y address
+    dest_x,     // destination x address
+    dest_y,     // destination y address
+    destport    // router output port
+);
     function integer log2;
-      input integer number; begin   
-         log2=(number <=1) ? 1: 0;    
-         while(2**log2<number) begin    
+    input integer number; begin   
+        log2=(number <=1) ? 1: 0;    
+        while(2**log2<number) begin    
             log2=log2+1;    
-         end 	   
-      end   
+        end        
+    end   
     endfunction // log2 
     
+    localparam  
+        P   =   5,
+        P_1 =   P-1,
+        Xw  =   log2(NX),
+        Yw  =   log2(NY);
+    input  [Xw-1 :0] current_x;
+    input  [Yw-1 :0] current_y;
+    input  [Xw-1 :0] dest_x;
+    input  [Yw-1 :0] dest_y;
+    output [P_1-1 :0] destport;
     
-    localparam  P   =   5,
-                P_1 =   P-1,
-                Xw  =   log2(NX),
-                Yw  =   log2(NY);
-
-    input  [Xw-1        :0] current_x;
-    input  [Yw-1        :0] current_y;
-    input  [Xw-1        :0] dest_x;
-    input  [Yw-1        :0] dest_y;
-    output [P_1-1       :0] destport;
-   
-
-        
     localparam LOCAL=   3'd0;  
     localparam EAST =   3'd1; 
     localparam NORTH=   3'd2;  
     localparam WEST =   3'd3;  
     localparam SOUTH=   3'd4;  
-        
+    
     wire tranc_x_plus,tranc_y_plus,tranc_x_min,tranc_y_min;
     wire same_x,same_y;
-    
-    
     tranc_dir #(
         .NX(NX),
         .NY(NY)
-    )
-    tranc_dir(
+    )tranc_dir(
         .tranc_x_plus(tranc_x_plus),
         .tranc_x_min(tranc_x_min),
         .tranc_y_plus(tranc_y_plus),
@@ -314,14 +268,11 @@ module tranc_xy_routing #(
         .current_y(current_y),
         .dest_x(dest_x),
         .dest_y(dest_y)
-        
     );
     
-    reg [P-1    :   0]  possible_out_port;
-    
-     // north last routing algorithm does not allow turns from north to east or from north to west.
-    
-   always @(*)begin     
+    reg [P-1 : 0]  possible_out_port;
+    // north last routing algorithm does not allow turns from north to east or from north to west.
+    always @(*)begin     
         possible_out_port       = 5'd0;
         if(same_x &&  same_y) begin 
             possible_out_port [LOCAL]=1'b1;
@@ -337,7 +288,6 @@ module tranc_xy_routing #(
         else if (tranc_x_plus &&  tranc_y_min) begin 
             possible_out_port   [EAST]= 1'b1;
            // possible_out_port   [NORTH]= 1'b1;
-            
         end
         else if (tranc_x_plus &&  tranc_y_plus) begin 
             possible_out_port   [EAST]= 1'b1;
@@ -364,73 +314,56 @@ module tranc_xy_routing #(
     assign a = possible_out_port[EAST] | possible_out_port[WEST]; 
     assign b = possible_out_port[NORTH]| possible_out_port[SOUTH];
     assign destport = {x,y,a,b};
-    
-    
-    endmodule
-    
-    
-
+endmodule
 
-    /********************************************
-                    TRANC North-Last 
-    *********************************************/
 
-    
-    module tranc_negetive_first_routing #(
-       parameter NX   =   4,
-       parameter NY   =   4
-    )
-    (       
-        current_x,  // current router x address
-        current_y,  // current router y address
-        dest_x,     // destination x address
-        dest_y,     // destination y address
-        destport    // router output port
-        
-        
-    );
-
-        
-    
+/********************************************
+*            TRANC North-Last 
+*********************************************/
 
+module tranc_negetive_first_routing #(
+    parameter NX   =   4,
+    parameter NY   =   4
+)(       
+    current_x,  // current router x address
+    current_y,  // current router y address
+    dest_x,     // destination x address
+    dest_y,     // destination y address
+    destport    // router output port
+);
     function integer log2;
-      input integer number; begin   
-         log2=(number <=1) ? 1: 0;    
-         while(2**log2<number) begin    
+    input integer number; begin   
+        log2=(number <=1) ? 1: 0;    
+        while(2**log2<number) begin    
             log2=log2+1;    
-         end        
-      end   
+        end        
+    end   
     endfunction // log2 
     
+    localparam  
+        P   =   5,
+        P_1 =   P-1,
+        Xw  =   log2(NX),
+        Yw  =   log2(NY);
+    input  [Xw-1 :0] current_x;
+    input  [Yw-1 :0] current_y;
+    input  [Xw-1 :0] dest_x;
+    input  [Yw-1 :0] dest_y;
+    output [P_1-1 :0] destport;
     
-    localparam  P   =   5,
-                P_1 =   P-1,
-                Xw  =   log2(NX),
-                Yw  =   log2(NY);
-
-    input  [Xw-1        :0] current_x;
-    input  [Yw-1        :0] current_y;
-    input  [Xw-1        :0] dest_x;
-    input  [Yw-1        :0] dest_y;
-    output [P_1-1       :0] destport;
-   
-
-        
     localparam LOCAL=   3'd0;  
     localparam EAST =   3'd1; 
     localparam NORTH=   3'd2;  
     localparam WEST =   3'd3;  
     localparam SOUTH=   3'd4;  
-        
+    
     wire tranc_x_plus,tranc_y_plus,tranc_x_min,tranc_y_min;
     wire same_x,same_y;
     
-    
     tranc_dir #(
         .NX(NX),
         .NY(NY)
-    )
-    tranc_dir(
+    ) tranc_dir(
         .tranc_x_plus(tranc_x_plus),
         .tranc_x_min(tranc_x_min),
         .tranc_y_plus(tranc_y_plus),
@@ -441,14 +374,11 @@ module tranc_xy_routing #(
         .current_y(current_y),
         .dest_x(dest_x),
         .dest_y(dest_y)
-        
     );
     
-    reg [P-1    :   0]  possible_out_port;
-    
-     // The negetive fist routing algorithm does net allow turns from north to west or from east to south.
-    
-   always @(*)begin     
+    reg [P-1 : 0]  possible_out_port;
+    // The negetive fist routing algorithm does net allow turns from north to west or from east to south.
+    always @(*)begin     
         possible_out_port       = 5'd0;
         if(same_x &&  same_y) begin 
             possible_out_port [LOCAL]=1'b1;
@@ -491,81 +421,59 @@ module tranc_xy_routing #(
     assign a = possible_out_port[EAST] | possible_out_port[WEST]; 
     assign b = possible_out_port[NORTH]| possible_out_port[SOUTH];
     assign destport = {x,y,a,b};
-    
-    
-    endmodule
-    
-
+endmodule
 
 /***********************************
-        fully adaptive
-
+*        fully adaptive
 ***********************************/
 
-    /************************************
-
-        Duato’s Fully Adaptive
-
-    *************************************/    
-    
-    
-    
-    module tranc_duato_routing #(
-        parameter NX  =   4,
-        parameter NY  =   4
-    )
-    (       
-        current_x,  // current router x address
-        current_y,  // current router y address
-        dest_x,     // destination x address
-        dest_y,     // destination y address
-        destport    // router output port
-       
-        
-    );
-
-        
-    
-
+/************************************
+*        Duato’s Fully Adaptive
+*************************************/    
+module tranc_duato_routing #(
+    parameter NX  =   4,
+    parameter NY  =   4
+) (       
+    current_x,  // current router x address
+    current_y,  // current router y address
+    dest_x,     // destination x address
+    dest_y,     // destination y address
+    destport    // router output port
+);
     function integer log2;
-      input integer number; begin   
-         log2=(number <=1) ? 1: 0;    
-         while(2**log2<number) begin    
+    input integer number; begin   
+        log2=(number <=1) ? 1: 0;    
+        while(2**log2<number) begin    
             log2=log2+1;    
-         end        
-      end   
+        end        
+    end   
     endfunction // log2 
     
-    
-    localparam  P   =   5,
-                P_1 =   P-1,
-                Xw  =   log2(NX),
-                Yw  =   log2(NY);
+    localparam  
+        P   =   5,
+        P_1 =   P-1,
+        Xw  =   log2(NX),
+        Yw  =   log2(NY);
 
-    input  [Xw-1        :0] current_x;
-    input  [Yw-1        :0] current_y;
-    input  [Xw-1        :0] dest_x;
-    input  [Yw-1        :0] dest_y;
-    output [P_1-1       :0] destport;
-   
-
-        
+    input  [Xw-1 :0] current_x;
+    input  [Yw-1 :0] current_y;
+    input  [Xw-1 :0] dest_x;
+    input  [Yw-1 :0] dest_y;
+    output [P_1-1 :0] destport;
+    
     localparam LOCAL=   3'd0;  
     localparam EAST =   3'd1; 
     localparam NORTH=   3'd2;  
     localparam WEST =   3'd3;  
     localparam SOUTH=   3'd4;  
     
-    
     wire tranc_x_plus,tranc_y_plus,tranc_x_min,tranc_y_min;
     wire same_x,same_y;
     
-    
     tranc_dir #(
         .NX(NX),
         .NY(NY)
-    )
-    tranc_dir(
+    ) tranc_dir(
         .tranc_x_plus(tranc_x_plus),
         .tranc_x_min(tranc_x_min),
         .tranc_y_plus(tranc_y_plus),
@@ -576,13 +484,9 @@ module tranc_xy_routing #(
         .current_y(current_y),
         .dest_x(dest_x),
         .dest_y(dest_y)
-        
     );
     
-    
-    reg [P-1    :    0]    possible_out_port;
-    
-    
+    reg [P-1 : 0]    possible_out_port;
     always @(*)begin     
         possible_out_port         = 5'd0;
         if(same_x &&  same_y) begin 
@@ -626,19 +530,12 @@ module tranc_xy_routing #(
     assign a = possible_out_port[EAST] | possible_out_port[WEST]; 
     assign b = possible_out_port[NORTH]| possible_out_port[SOUTH];
     assign destport = {x,y,a,b};
+endmodule
     
     
-    endmodule
-    
-    
-    
-    /****************************************
-    
-       tranc_dir
-    
-    
-    ****************************************/
-
+/****************************************
+*    tranc_dir
+****************************************/
 module tranc_dir #(
     parameter NX   =    4,
     parameter NY   =    4
@@ -655,52 +552,48 @@ module tranc_dir #(
     same_y
 );
 
-
- 
     function integer log2;
-      input integer number; begin   
-         log2=(number <=1) ? 1: 0;    
-         while(2**log2<number) begin    
+    input integer number; begin   
+        log2=(number <=1) ? 1: 0;    
+        while(2**log2<number) begin    
             log2=log2+1;    
-         end        
-      end   
+        end        
+    end   
     endfunction // log2 
     
     /* verilator lint_off WIDTH */
-    localparam  Xw          =   log2(NX),
-                Yw          =   log2(NY);
+    localparam  
+        Xw = log2(NX),
+        Yw = log2(NY);
     
-      
     output reg tranc_x_plus;
     output reg tranc_x_min;
     output reg tranc_y_plus;
     output reg tranc_y_min;
-    output     same_x,same_y;
+    output wire same_x,same_y;
+    
+    input   [Xw-1 : 0] current_x;
+    input   [Yw-1 : 0] current_y;
+    input   [Xw-1 : 0] dest_x;
+    input   [Yw-1 : 0] dest_y;
     
-    input   [Xw-1       :   0] current_x;
-    input   [Yw-1       :   0] current_y;
-    input   [Xw-1       :   0] dest_x;
-    input   [Yw-1       :   0] dest_y;
-
     localparam SIGNED_X_WIDTH   =  (Xw<3) ? 4 : Xw+1;
     localparam SIGNED_Y_WIDTH   =  (Yw<3) ? 4 : Yw+1;
     
-    wire signed [SIGNED_X_WIDTH-1       :0] xc;//current 
-    wire signed [SIGNED_X_WIDTH-1       :0] xd;//destination
-    wire signed [SIGNED_Y_WIDTH-1       :0] yc;//current 
-    wire signed [SIGNED_Y_WIDTH-1       :0] yd;//destination
-    wire signed [SIGNED_X_WIDTH-1       :0] xdiff;
-    wire signed [SIGNED_Y_WIDTH-1       :0] ydiff; 
-    
+    wire signed [SIGNED_X_WIDTH-1 :0] xc;//current 
+    wire signed [SIGNED_X_WIDTH-1 :0] xd;//destination
+    wire signed [SIGNED_Y_WIDTH-1 :0] yc;//current 
+    wire signed [SIGNED_Y_WIDTH-1 :0] yd;//destination
+    wire signed [SIGNED_X_WIDTH-1 :0] xdiff;
+    wire signed [SIGNED_Y_WIDTH-1 :0] ydiff; 
     
-    assign  xc  ={{(SIGNED_X_WIDTH-Xw){1'b0}}, current_x [Xw-1      :0]};
-    assign  yc  ={{(SIGNED_Y_WIDTH-Yw){1'b0}}, current_y [Yw-1      :0]};
+    assign  xc  ={{(SIGNED_X_WIDTH-Xw){1'b0}}, current_x [Xw-1 :0]};
+    assign  yc  ={{(SIGNED_Y_WIDTH-Yw){1'b0}}, current_y [Yw-1 :0]};
     assign  xd  ={{(SIGNED_X_WIDTH-Xw){1'b0}}, dest_x};
     assign  yd  ={{(SIGNED_Y_WIDTH-Yw){1'b0}}, dest_y};
     assign  xdiff   = xd-xc;
     assign  ydiff   = yd-yc;
     
-    
     always@ (*)begin 
         tranc_x_plus    =1'b0;
         tranc_x_min     =1'b0;
@@ -708,10 +601,10 @@ module tranc_dir #(
         tranc_y_min     =1'b0;
         if(xdiff!=0)begin 
             if ((xdiff ==1) || 
-                 (xdiff == (-NX+1)) ||
-                 ((xc == (NX-4)) && (xd == (NX-2))) ||
-                 ((xc >= (NX-2)) && (xd <= (NX-4))) ||
-                 ((xdiff> 0) && (xd<= (NX-3)))) 
+                (xdiff == (-NX+1)) ||
+                ((xc == (NX-4)) && (xd == (NX-2))) ||
+                ((xc >= (NX-2)) && (xd <= (NX-4))) ||
+                ((xdiff> 0) && (xd<= (NX-3)))) 
                     tranc_x_plus    = 1'b1;
             else    tranc_x_min     = 1'b1;
         end
@@ -728,9 +621,5 @@ module tranc_dir #(
     
     assign same_x = (xdiff == 0);
     assign same_y = (ydiff == 0);
-    
     /* verilator lint_on WIDTH */
-    
-endmodule
-
-
+endmodule
\ No newline at end of file
diff --git a/mpsoc/rtl/src_noc/router_bypass.sv b/mpsoc/rtl/src_noc/router_bypass.sv
index f7d28b4..14d9d68 100644
--- a/mpsoc/rtl/src_noc/router_bypass.sv
+++ b/mpsoc/rtl/src_noc/router_bypass.sv
@@ -1,5 +1,4 @@
 `include "pronoc_def.v"
-
 /**************************************
 * Module: router_bypass
 * Date:2020-11-24  
@@ -20,959 +19,728 @@
  * lk-ahead routing, The packet can by-pass the next router once the bypassing condition are met
  ***************************/
 
-`include "pronoc_def.v"
-
-	
-module reduction_or #(
-	parameter W = 5,//out width
-	parameter N = 4 //array lenght 
-)(
-	in,
-	out	
-);
-    input  [W-1 : 0] in [N-1 : 0];
-    output reg [W-1 : 0] out;	
-	
-    // assign out = in.or(); //it is not synthesizable able by some compiler
-	always_comb begin
-		out = {W{1'b0}};
-		for (int i = 0; i < N; i++)
-			out |=   in[i];
-	end
-
-
-endmodule
-
 module onehot_mux_2D #(
-		parameter W = 5,//out width
-		parameter N = 4 //sel width 
-		)(
-		in,
-		sel,
-		out	
-		);
-
- 	input  [W-1 : 0] in [N-1 : 0];
-	input  [N-1 : 0] sel;
-	output reg [W-1 : 0] out;	
-
-    
-	always_comb begin
-		out = {W{1'b0}};
-		for (int i = 0; i < N; i++)
-			out |= (sel[i]) ?  in[i] :  {W{1'b0}};
-	end
-	
+    parameter W = 5,//out width
+    parameter N = 4 //sel width 
+)(
+    D_in,
+    sel,
+    Q_out
+    );
+    input  [W-1 : 0] D_in [N-1 : 0];
+    input  [N-1 : 0] sel;
+    output reg [W-1 : 0] Q_out;    
     
+    always_comb begin
+        Q_out = {W{1'b0}};
+        for (int i = 0; i < N; i++)
+            Q_out |= (sel[i]) ?  D_in[i] :  {W{1'b0}};
+    end
 endmodule
-	
+    
 module onehot_mux_1D #(
-		parameter W = 5,//out width
-		parameter N = 4 //sel width 
-	)(
-		input  [W*N-1 : 0] in,
-		input  [N-1 : 0] sel,
-		output [W-1 : 0] out	
-	);
-
-wire  [W-1 : 0] in_array [N-1 : 0];
+    parameter W = 5,//out width
+    parameter N = 4 //sel width 
+)(
+    input  [W*N-1 : 0] D_in,
+    input  [N-1 : 0] sel,
+    output reg [W-1 : 0] Q_out    
+);
 
-genvar i;
-generate
-for (i=0;i<N;i++)begin :sep 
-	assign in_array[i] = in[(i+1)*W-1 : i*W];
-end
-endgenerate
-	
+    wire  [W-1 : 0] in_array [N-1 : 0];
+    genvar i;
+    generate
+    for (i=0;i<N;i++)begin :sep 
+        assign in_array[i] = D_in[(i+1)*W-1 : i*W];
+    end
+    endgenerate
+    
+    //onehot_mux_2D
+    always_comb begin
+        Q_out = {W{1'b0}};
+        for (int k = 0; k < N; k++)
+            Q_out |= (sel[k]) ?  in_array[k] :  {W{1'b0}};
+    end
+endmodule
 
-	onehot_mux_2D #(
-		.W    (W), 
-		.N    (N)
-		) onehot_mux_2D (
-		.in   (in_array), 
-		.sel  (sel), 
-		.out  (out));
-	
-    
-endmodule	
-	
 
 module onehot_mux_1D_reverse #(
-		parameter W = 5,//out width  p
-		parameter N = 4 //sel width  v
-		)(
-		input  [W*N-1 : 0] in,
-		input  [N-1 : 0] sel,
-		output [W-1 : 0] out	
-		);
-
-	wire  [N-1 : 0] in_array [W-1 : 0];
-	wire  [W-1 : 0] in_array2[N-1 : 0];
-
-	genvar i,j;
-	generate
-		for (i=0;i<W;i++)begin :sep 
-			assign in_array[i] = in[(i+1)*N-1 : i*N];
-			for (j=0;j<N;j++)begin :sep
-				assign in_array2[j][i] = in_array[i][j];
-			end
-		end
-	endgenerate
-	
+    parameter W = 5,//out width  p
+    parameter N = 4 //sel width  v
+)(
+    input  [W*N-1 : 0] D_in,
+    input  [N-1 : 0] sel,
+    output [W-1 : 0] Q_out    
+);
+    wire  [N-1 : 0] in_array [W-1 : 0];
+    wire  [W-1 : 0] in_array2[N-1 : 0];
+    genvar i,j;
+    generate
+        for (i=0;i<W;i++)begin :sep 
+            assign in_array[i] = D_in[(i+1)*N-1 : i*N];
+            for (j=0;j<N;j++)begin :sep
+                assign in_array2[j][i] = in_array[i][j];
+            end
+        end
+    endgenerate
+    
+    onehot_mux_2D #(
+        .W    (N), 
+        .N    (W)
+    ) onehot_mux_2D (
+        .D_in(in_array2), 
+        .sel  (sel), 
+        .Q_out(Q_out)
+    );
+endmodule
 
-	onehot_mux_2D #(
-			.W    (N), 
-			.N    (W)
-		) onehot_mux_2D (
-			.in   (in_array2), 
-			.sel  (sel), 
-			.out  (out));
-	
-    
-endmodule	
 
+`ifdef SIMULATION
+module smart_chanel_check (
+    flit_chanel,
+    smart_chanel,
+    reset,
+    clk
+);
+    import pronoc_pkg::*;
 
+    input flit_chanel_t  flit_chanel;
+    input smart_chanel_t   smart_chanel;
+    input reset,clk;
+    
+    smart_chanel_t   smart_chanel_delay; 
+    always @(posedge clk) smart_chanel_delay<=smart_chanel;
+    
+    hdr_flit_t hdr_flit;
+    header_flit_info extract (
+        .flit(flit_chanel.flit),
+        .hdr_flit(hdr_flit),
+        .data_o()
+    );
+    
+    always @(posedge clk) begin 
+        if(flit_chanel.flit_wr) begin 
+            if(smart_chanel_delay.ovc!=flit_chanel.flit.vc) begin 
+                $display("%t: ERROR: smart ovc %d is not equal with flit ovc %d. %m",$time,smart_chanel_delay.ovc,flit_chanel.flit.vc);
+                $finish;
+            end
+            if(flit_chanel.flit.hdr_flag==1'b1 &&   hdr_flit.dest_e_addr != smart_chanel_delay.dest_e_addr) begin 
+                $display("%t: ERROR: smart dest_e_addr %d is not equal with flit dest_e_addr %d. %m",$time,smart_chanel_delay.dest_e_addr,hdr_flit.dest_e_addr);
+                $finish;
+            end
+            if(flit_chanel.flit.hdr_flag!=smart_chanel_delay.hdr_flit) begin 
+                $display("%t: ERROR: smart and current hdr flag (%d!=%d) miss-match. %m",$time, smart_chanel_delay.hdr_flit, flit_chanel.flit.hdr_flag);
+                $finish;
+            end
+        end    
+    end    
+endmodule    
+`endif 
 
-module header_flit_info #(
-	parameter NOC_ID = 0,
-	parameter DATA_w = 0	
-)(
-	flit,
-	hdr_flit,		
-	data_o    
-); 	
- 	
- 	`NOC_CONF
- 	
- 	localparam 
-	Dw = (DATA_w==0)? 1 : DATA_w;
-	
-	input flit_t flit;
-	output hdr_flit_t hdr_flit;
-	output [Dw-1 : 0] data_o;
-              
-     
-	localparam		         
-		DATA_LSB= MSB_BE+1,               DATA_MSB= (DATA_LSB + DATA_w)<FPAYw ? DATA_LSB + Dw-1 : FPAYw-1,
-		OFFSETw = DATA_MSB - DATA_LSB +1;
-   
-	wire [OFFSETw-1 : 0 ] offset;
-  
-	assign hdr_flit.src_e_addr  = flit.payload [E_SRC_MSB : E_SRC_LSB];
-	assign hdr_flit.dest_e_addr = flit.payload [E_DST_MSB : E_DST_LSB];
-	assign hdr_flit.destport    = flit.payload [DST_P_MSB : DST_P_LSB];
-    
-   
-	generate
-		if(C>1)begin : have_class 
-			assign hdr_flit.message_class = flit.payload [CLASS_MSB : CLASS_LSB];
-		end else begin : no_class
-			assign hdr_flit.message_class = {Cw{1'b0}};
-		end   
 
-		/* verilator lint_off WIDTH */
-		if(SWA_ARBITER_TYPE != "RRA")begin  : wrra_b
-		/* verilator lint_on WIDTH */
-			assign hdr_flit.weight =  flit.payload [WEIGHT_MSB : WEIGHT_LSB];    
-		end else begin : rra_b
-			assign hdr_flit.weight = {WEIGHTw{1'bX}};        
-		end 
+module smart_forward_ivc_info #(
+    parameter P=5
+) (
+    ivc_info,
+    iport_info,
+    oport_info,
+    smart_chanel,
+    ovc_locally_requested,
+    reset,clk
+);
+    import pronoc_pkg::*;    
     
-		if( BYTE_EN) begin : be_1
-			assign hdr_flit.be = flit.payload [BE_MSB : BE_LSB];    
-		end else begin : be_0    
-			assign hdr_flit.be = {BEw{1'bX}};
-		end
+    //ivc info 
+    input reset,clk;
+    input  ivc_info_t     ivc_info    [P-1 : 0][V-1 : 0];
+    input  iport_info_t iport_info  [P-1 : 0];
+    input  oport_info_t oport_info  [P-1 : 0]; 
+    output smart_chanel_t smart_chanel  [P-1 : 0];
+    output logic [V-1 : 0] ovc_locally_requested [P-1 : 0];
+
+    smart_ivc_info_t  smart_ivc_info [P-1 : 0][V-1 : 0];
+    smart_ivc_info_t  smart_ivc_mux  [P-1 : 0];
     
+    smart_ivc_info_t  smart_ivc_info_all_port [P-1 : 0] [P-1 : 0];
+    smart_ivc_info_t  smart_vc_info_o [P-1 : 0];
     
-		assign offset = flit.payload [DATA_MSB : DATA_LSB];    
+    logic [V-1 : 0] assigned_ovc [P-1:0];
+    wire [V-1 : 0] non_assigned_vc_req [P-1:0];
+    wire [P-1 : 0] mask_gen  [P-1 : 0][V-1 :0];
+    wire [V-1 : 0] ovc_locally_requested_next [P-1 : 0];
     
+    /* 
+                        P  V                   P        P  V   p
+    non_assigned_vc_req[i][j] destport_one_hot[z]-->   [z][ j][i]
+    non_assigned_vc_req[0][0] destport_one_hot[3]--> | [3][0] [0]
+    non_assigned_vc_req[1][0] destport_one_hot[3]--> | [3][0] [1]
+    non_assigned_vc_req[2][0] destport_one_hot[3]--> | [3][0] [2]
+    */
     
-		if(Dw > OFFSETw) begin : if1     
-			assign data_o={{(Dw-OFFSETw){1'b0}},offset};
-		end else begin : if2 
-			assign data_o=offset[Dw-1 : 0];
-		end    
+    smart_chanel_t smart_chanel_next  [P-1 : 0];
     
-	endgenerate          
-   
-	
-
+    genvar i,j,z;
+    generate 
+    for (i=0;i<P;i=i+1) begin : P_
+        for (j=0; j < V; j=j+1) begin : V_
+            assign smart_ivc_info[i][j].dest_e_addr = ivc_info[i][j].dest_e_addr;
+            assign smart_ivc_info[i][j].ovc_is_assigned= ivc_info[i][j].ovc_is_assigned;
+            assign smart_ivc_info[i][j].assigned_ovc_bin=ivc_info[i][j].assigned_ovc_bin;    
+            assign non_assigned_vc_req[i][j] = ~ivc_info[i][j].ovc_is_assigned & ivc_info[i][j].ivc_req;
+            for (z=0; z < P; z=z+1) begin : p_
+                assign mask_gen[z][j][i] = non_assigned_vc_req[i][j] & ivc_info[i][j].destport_one_hot[z]; 
+            end
+            assign ovc_locally_requested_next[i][j]=|mask_gen[i][j];
+        end//V
+        always_ff @ (`pronoc_clk_reset_edge) begin
+            if (`pronoc_reset)
+                ovc_locally_requested[i] <= '0;
+            else
+                ovc_locally_requested[i] <= ovc_locally_requested_next[i];
+        end
+        
+        onehot_mux_2D    #(.W(SMART_IVC_w),.N(V)) mux1 ( .D_in(smart_ivc_info[i]), .sel(iport_info[i].swa_first_level_grant), .Q_out(smart_ivc_mux[i]));
+        //demux
+        for (j=0;j<P;j=j+1) begin : port_
+            assign smart_ivc_info_all_port[j][i] = (iport_info[i].granted_oport_one_hot[j]==1'b1)? smart_ivc_mux[i] : {SMART_IVC_w{1'b0}};    
+        end        
+        //assign smart_vc_info_o[i] = smart_ivc_info_all_port[i].or; not synthesizable
+        // assign smart_vc_info_o[i] = smart_ivc_info_all_port[i].[0] | smart_ivc_info_all_port[i].[1] | smart_ivc_info_all_port[i].[2]  ... | smart_ivc_info_all_port[i].[p-1];
+        reduction_or #(
+            .W    (SMART_IVC_w), 
+            .N    (P)
+        ) _or (
+            .D_in(smart_ivc_info_all_port[i]), 
+            .Q_out(smart_vc_info_o[i])
+        );
+        
+        
+        assign smart_chanel_next[i].dest_e_addr= smart_vc_info_o[i].dest_e_addr;
+        assign smart_chanel_next[i].ovc= (smart_vc_info_o[i].ovc_is_assigned)? assigned_ovc[i] : oport_info[i].non_smart_ovc_is_allocated;
+        assign smart_chanel_next[i].hdr_flit=~smart_vc_info_o[i].ovc_is_assigned;
+        assign smart_chanel_next[i].requests = (oport_info[i].any_ovc_granted)? {SMART_NUM{1'b1}}:{SMART_NUM{1'b0}} ;
+        assign smart_chanel_next[i].bypassed_num = {BYPASSw{1'b0}} ;
+        assign smart_chanel_next[i].flit_in_bypassed=1'b0;
+        
+        if( ADD_PIPREG_AFTER_CROSSBAR == 1) begin :link_reg
+            always_ff @ (`pronoc_clk_reset_edge) begin
+                if (`pronoc_reset)
+                    smart_chanel[i] <= '0;
+                else
+                    smart_chanel[i] <= smart_chanel_next[i];
+            end
+        end else begin :no_link_reg
+                assign smart_chanel[i] = smart_chanel_next[i];
+        end
+    end//port_
+    endgenerate
+
+    //bin_to_one_hot
+    always_comb begin
+        for (int port=0; port<P; port=port+1) begin
+            assigned_ovc[port] = {V{1'b0}};
+            assigned_ovc[port][smart_vc_info_o[port].assigned_ovc_bin] = 1'b1;
+        end
+    end
 endmodule
 
-//synthesis translate_off 
-//synopsys  translate_off
-
-module smart_chanel_check #(
-	parameter NOC_ID=0
+module smart_bypass_chanels #(
+    parameter P=5
 ) (
-	flit_chanel,
-	smart_chanel,
-	reset,
-	clk		
+    ivc_info,
+    iport_info,
+    oport_info,
+    smart_chanel_new,
+    smart_chanel_in,
+    smart_chanel_out,
+    smart_req,
+    reset,
+    clk
 );
-
-	`NOC_CONF
-
-	input flit_chanel_t  flit_chanel;
-	input smart_chanel_t   smart_chanel; 		
-	input reset,clk;
-	
-	smart_chanel_t   smart_chanel_delay; 
-	always @(posedge clk) smart_chanel_delay<=smart_chanel;
-	
-	hdr_flit_t hdr_flit;
-	header_flit_info #(
-		.NOC_ID (NOC_ID)	
-	) extract (
-		.flit(flit_chanel.flit),
-		.hdr_flit(hdr_flit),		
-		.data_o()
-	);
-
-	always @(posedge clk) begin 
-		if(flit_chanel.flit_wr) begin 
-			if(smart_chanel_delay.ovc!=flit_chanel.flit.vc) begin 
-				$display("%t: ERROR: smart ovc %d is not equal with flit ovc %d. %m",$time,smart_chanel_delay.ovc,flit_chanel.flit.vc);
-				$finish;
-			end
-			if(flit_chanel.flit.hdr_flag==1'b1 &&   hdr_flit.dest_e_addr != smart_chanel_delay.dest_e_addr) begin 
-				$display("%t: ERROR: smart dest_e_addr %d is not equal with flit dest_e_addr %d. %m",$time,smart_chanel_delay.dest_e_addr,hdr_flit.dest_e_addr);
-				$finish;
-			end
-			if(flit_chanel.flit.hdr_flag!=smart_chanel_delay.hdr_flit) begin 
-				$display("%t: ERROR: smart and current hdr flag (%d!=%d) miss-match. %m",$time, smart_chanel_delay.hdr_flit, flit_chanel.flit.hdr_flag);
-				$finish;
-			end
-			
-		end	
-		
-	end	
-endmodule	
- 
-//synopsys  translate_on
-//synthesis translate_on 
+    
+    import pronoc_pkg::*;
+    input reset,clk;
+    input smart_chanel_t smart_chanel_new  [P-1 : 0];
+    input smart_chanel_t smart_chanel_in   [P-1 : 0];
+    input ivc_info_t   ivc_info    [P-1 : 0][V-1 : 0];
+    input iport_info_t iport_info  [P-1 : 0];
+    input oport_info_t oport_info  [P-1 : 0];
+    
+    output [P-1 : 0] smart_req;
+    output smart_chanel_t smart_chanel_out   [P-1 : 0];
+    
+    smart_chanel_t smart_chanel_shifted  [P-1 : 0];
+    localparam DISABLE = P;
+    
+    wire [V-1 : 0 ] ivc_forwardable [P-1 : 0];
+    wire [P-1 :0] smart_forwardable;
+    logic [P-1 :0] outport_is_granted;
+    reg [P-1 : 0] rq;
+
+    always_comb begin
+        for (int k=0;k<P;k++) begin
+            smart_chanel_shifted[k].requests={{SMART_NUM{1'b0}}};
+            rq[k]=1'b0;
+            if(strieght_port (P,k) != DISABLE) begin
+                smart_chanel_shifted[k] = smart_chanel_in [k];
+                {smart_chanel_shifted[k].requests,rq[k]} =(smart_forwardable[k])? {1'b0,smart_chanel_in[k].requests}:{{SMART_NUM{1'b0}},smart_chanel_in[k].requests[0]};
+                smart_chanel_shifted[k].bypassed_num =   smart_chanel_in [k].bypassed_num +1'b1;
+            end 
+        end
+    end
+
+    genvar i;
+    generate
+    for (i=0;i<P;i=i+1) begin: P_
+        assign ivc_forwardable[i] =  (IS_SINGLE_FLIT)?  {V{1'b1}} :~iport_info[i].ivc_req;
+        if( ADD_PIPREG_AFTER_CROSSBAR == 1) begin :link_reg
+            always @( posedge clk)begin
+                outport_is_granted[i] <= oport_info[i].any_ovc_granted;
+            end
+        end else begin 
+            assign outport_is_granted[i] = oport_info[i].any_ovc_granted;
+        end
+        localparam SS_PORT = strieght_port (P,i); // the straight port number
+        if(SS_PORT != DISABLE) begin: ssp 
+            //smart_chanel_shifter
+            assign smart_forwardable[i] = |  (ivc_forwardable[i] & smart_chanel_in[i].ovc);
+            assign smart_req[i]=rq[i];
+            // mux out smart chanel
+            assign smart_chanel_out[i] = (outport_is_granted[i])? smart_chanel_new[i] : smart_chanel_shifted[SS_PORT];
+        end else begin
+            assign smart_req[i] = 1'b0;
+            assign smart_chanel_out[i] = {SMART_CHANEL_w{1'b0}};
+        end
+    end
+    endgenerate
+endmodule 
 
 
-module smart_forward_ivc_info #(
-	parameter NOC_ID=0,
-	parameter P=5
-) (			
-	ivc_info,
-	iport_info,
-	oport_info,
-	smart_chanel,
-	ovc_locally_requested,
-	reset,clk
+module check_straight_oport #(
+    parameter SS_PORT_LOC = 1
+)(
+    destport_coded_i,
+    goes_straight_o
 );
-		
-	`NOC_CONF	
-	
-	//ivc info 
-	input reset,clk;
-	input  ivc_info_t 	ivc_info    [P-1 : 0][V-1 : 0];
-	input  iport_info_t iport_info  [P-1 : 0];
-	input  oport_info_t oport_info  [P-1 : 0]; 
-	output smart_chanel_t smart_chanel  [P-1 : 0];
-	output [V-1 : 0] ovc_locally_requested [P-1 : 0];
-			
-	smart_ivc_info_t  smart_ivc_info [P-1 : 0][V-1 : 0];
-	smart_ivc_info_t  smart_ivc_mux  [P-1 : 0];
-	
-	smart_ivc_info_t  smart_ivc_info_all_port [P-1 : 0] [P-1 : 0];
-	smart_ivc_info_t  smart_vc_info_o [P-1 : 0];
-	
-	wire [V-1 : 0] assigned_ovc [P-1:0];
-	wire [V-1 : 0] non_assigned_vc_req [P-1:0];
-	wire [P-1 : 0] mask_gen  [P-1 : 0][V-1 :0];
-	wire [V-1 : 0] ovc_locally_requested_next [P-1 : 0];
-	
-	/* 
-						P  V                   P		P  V   p
-	non_assigned_vc_req[i][j] destport_one_hot[z]-->   [z][ j][i]
-	non_assigned_vc_req[0][0] destport_one_hot[3]--> | [3][0] [0]
-	non_assigned_vc_req[1][0] destport_one_hot[3]--> | [3][0] [1]
-	non_assigned_vc_req[2][0] destport_one_hot[3]--> | [3][0] [2]
-	*/
-	
-	smart_chanel_t smart_chanel_next  [P-1 : 0];
-	
-	
-	genvar i,j,z;
-	generate 
-	for (i=0;i<P;i=i+1) begin : port_
-				
-		for (j=0; j < V; j=j+1) begin : ivc					
-			assign smart_ivc_info[i][j].dest_e_addr = ivc_info[i][j].dest_e_addr;
-			assign smart_ivc_info[i][j].ovc_is_assigned= ivc_info[i][j].ovc_is_assigned;
-			assign smart_ivc_info[i][j].assigned_ovc_bin=ivc_info[i][j].assigned_ovc_bin;	
-			assign non_assigned_vc_req[i][j] = ~ivc_info[i][j].ovc_is_assigned & ivc_info[i][j].ivc_req;
-			for (z=0; z < P; z=z+1) begin : port
-				assign mask_gen[z][j][i] = non_assigned_vc_req[i][j] & ivc_info[i][j].destport_one_hot[z]; 
-			end
-			assign ovc_locally_requested_next[i][j]=|mask_gen[i][j];
-		end//V
-		
-		pronoc_register #(.W(V)) reg1 (.in(ovc_locally_requested_next[i]), .reset(reset), .clk(clk), .out(ovc_locally_requested[i]));
-		
-		
-		
-		
-		onehot_mux_2D	#(.W(SMART_IVC_w),.N(V)) mux1 ( .in(smart_ivc_info[i]), .sel(iport_info[i].swa_first_level_grant), .out(smart_ivc_mux[i]));
-		//demux
-		for (j=0;j<P;j=j+1) begin : port_
-			assign smart_ivc_info_all_port[j][i] = (iport_info[i].granted_oport_one_hot[j]==1'b1)? smart_ivc_mux[i] : {SMART_IVC_w{1'b0}};	
-		end		
-		
-		//assign smart_vc_info_o[i] = smart_ivc_info_all_port[i].or; not synthesizable
-		// assign smart_vc_info_o[i] = smart_ivc_info_all_port[i].[0] | smart_ivc_info_all_port[i].[1] | smart_ivc_info_all_port[i].[2]  ... | smart_ivc_info_all_port[i].[p-1];
-		reduction_or #(
-			.W    (SMART_IVC_w), 
-			.N    (P)
-		) _or (
-			.in   (smart_ivc_info_all_port[i]), 
-			.out  (smart_vc_info_o[i])
-		);
-		/*
-		always_comb begin
-			smart_vc_info_o[i] = {SMART_IVC_w{1'b0}};
-			for (int ii = 0; ii < P; ii++)
-				smart_vc_info_o[i] |= smart_ivc_info_all_port[i][ii];
-		end
-		*/
-		
-		
-		bin_to_one_hot #(
-			.BIN_WIDTH      (Vw), 
-			.ONE_HOT_WIDTH  (V)
-		) conv (
-			.bin_code       (smart_vc_info_o[i].assigned_ovc_bin), 
-			.one_hot_code   (assigned_ovc[i])
-		);
-				
-		
-		
-		assign smart_chanel_next[i].dest_e_addr= smart_vc_info_o[i].dest_e_addr;	
-		assign smart_chanel_next[i].ovc= (smart_vc_info_o[i].ovc_is_assigned)? assigned_ovc[i] : oport_info[i].non_smart_ovc_is_allocated;
-		assign smart_chanel_next[i].hdr_flit=~smart_vc_info_o[i].ovc_is_assigned;
-		assign smart_chanel_next[i].requests = (oport_info[i].any_ovc_granted)? {SMART_NUM{1'b1}}:{SMART_NUM{1'b0}} ;
-		assign smart_chanel_next[i].bypassed_num = {BYPASSw{1'b0}} ;
-		
-		
-		if( ADD_PIPREG_AFTER_CROSSBAR == 1) begin :link_reg
-			pronoc_register #(
-				.W      ( SMART_CHANEL_w)
-				) register (
-				.in     (smart_chanel_next[i]), 
-				.reset  (reset), 
-				.clk    (clk), 
-				.out    (smart_chanel[i]));
-		
-		end else begin :no_link_reg
-				assign smart_chanel[i] = smart_chanel_next[i];		
-		end
-		/*
-		
-			always @ (`pronoc_clk_reset_edge)begin 
-				if(`pronoc_reset) begin 	
-					smart_chanel[i].dest_e_addr<= {EAw{1'b0}};	
-					smart_chanel[i].ovc<= {V{1'b0}};
-					smart_chanel[i].hdr_flit<=1'b0;
-				end else begin 	
-					smart_chanel[i].dest_e_addr<= smart_vc_info_o[i].dest_e_addr;	
-					smart_chanel[i].ovc<= (smart_vc_info_o[i].ovc_is_assigned)? assigned_ovc[i] : oport_info[i].non_smart_ovc_is_allocated;
-					smart_chanel[i].hdr_flit<=~smart_vc_info_o[i].ovc_is_assigned;
-					smart_chanel[i].requests <= (oport_info[i].any_ovc_granted)? {SMART_NUM{1'b1}}:{SMART_NUM{1'b0}} ;					
-				end
-			end		
-	
-		*/
-			
-			
-			
-	
-		
-		end//port_
-		endgenerate	
-	
-//	generate for (i=0; i < P; i=i+1) begin : port
-//			assign smart_ivc_info_o[i] = (granted_dest_port[i]==1'b1)? ivc_info_mux : {SMART_IVC_w{1'b0}};		
-//		end endgenerate 	
-
-			
+    import pronoc_pkg::*;
+    input   [DSTPw-1 : 0] destport_coded_i;
+    output  goes_straight_o;
+
+    generate 
+    if(IS_3D_TOPO) begin : D3_
+        if (SS_PORT_LOC == 0 || SS_PORT_LOC > DOWN) begin : local_ports
+            assign goes_straight_o = 1'b0; // There is not a next router in this case at all
+        end else begin :non_local
+            logic [MAX_P-1 : 0 ] destport_one_hot;
+            always @(*) begin 
+                destport_one_hot = '0;
+                //for deterministic routing destination port is decimal encoded
+                if(IS_DETERMINISTIC) destport_one_hot[destport_coded_i] = 1'b1;
+                //for non-deterministic routing destination port is one-hot encoded
+                else destport_one_hot [DSTPw-1 : 0] = destport_coded_i;
+            end
+            assign goes_straight_o = destport_one_hot [SS_PORT_LOC];    
+        end//else
+    end//regular_topo
+    if(IS_2D_TOPO) begin : D2_
+        if (SS_PORT_LOC == 0 || SS_PORT_LOC > SOUTH) begin : local_ports
+            assign goes_straight_o = 1'b0; // There is not a next router in this case at all
+        end else begin :non_local
+            wire [4 : 0 ] destport_one_hot;
+            regular_topo_decode_dstport decoder(
+                .dstport_encoded(destport_coded_i),
+                .dstport_one_hot(destport_one_hot)
+            );
+            assign goes_straight_o = destport_one_hot [SS_PORT_LOC];    
+        end//else
+    end//regular_topo
+    else if(IS_1D_TOPO) begin : D1_
+        if (SS_PORT_LOC == 0 || SS_PORT_LOC > BACKWARD) begin : local_ports
+            assign goes_straight_o = 1'b0; // There is not a next router in this case at all
+        end else begin :non_local
+            wire [2: 0 ] destport_one_hot;
+            line_ring_decode_dstport decoder(
+                .dstport_encoded(destport_coded_i),
+                .dstport_one_hot(destport_one_hot)
+            );
+            assign goes_straight_o = destport_one_hot [SS_PORT_LOC];
+        end    //non_local
+    end// oneD
+    //TODO Add fattree & custom 
+endgenerate
 endmodule
- 
- 
- 
- 
-module smart_bypass_chanels #(
-	parameter NOC_ID=0,
-	parameter P=5	
-) (			
-	ivc_info,
-	iport_info,
-	oport_info,
-	smart_chanel_new,
-	smart_chanel_in,
-	smart_chanel_out,
-	smart_req,
-	reset,
-	clk	
-);
-		
-	`NOC_CONF	
 
-	input reset,clk;	
-	input smart_chanel_t smart_chanel_new  [P-1 : 0];
-	input smart_chanel_t smart_chanel_in   [P-1 : 0];
-	input ivc_info_t   ivc_info    [P-1 : 0][V-1 : 0];
- 	input iport_info_t iport_info  [P-1 : 0];
- 	input oport_info_t oport_info  [P-1 : 0];
- 	
- 	output [P-1 : 0] smart_req;
- 	output smart_chanel_t smart_chanel_out   [P-1 : 0];
- 	
- 	
-	smart_chanel_t smart_chanel_shifted  [P-1 : 0];
-	localparam DISABLE = P;
-	
-	wire [V-1 : 0 ] ivc_forwardable [P-1 : 0];
-	wire [P-1 :0] smart_forwardable;
-	logic [P-1 :0] outport_is_granted;
-	reg [P-1 : 0] rq;
-	genvar i;
-	generate
-	for (i=0;i<P;i=i+1) begin: port	
-		/* verilator lint_off WIDTH */
-		assign ivc_forwardable[i] =  (PCK_TYPE == "SINGLE_FLIT")?  1'b1 :~iport_info[i].ivc_req;
-		/* verilator lint_on WIDTH */
-		
-		
-		if( ADD_PIPREG_AFTER_CROSSBAR == 1) begin :link_reg
-		always @( posedge clk)begin
-		    outport_is_granted[i] <= oport_info[i].any_ovc_granted;
-		end	
-		end else begin 
-			assign outport_is_granted[i] = oport_info[i].any_ovc_granted;
-		end
-		
-		localparam SS_PORT = strieght_port (P,i); // the straight port number
-		if(SS_PORT != DISABLE) begin: ssp 
-			
-			//smart_chanel_shifter
-			assign smart_forwardable[i] = |  (ivc_forwardable[i] & smart_chanel_in[i].ovc);
-			always @(*) begin 
-				smart_chanel_shifted[i] = smart_chanel_in [i];
-				{smart_chanel_shifted[i].requests,rq[i]} =(smart_forwardable[i])? {1'b0,smart_chanel_in[i].requests}:{{SMART_NUM{1'b0}},smart_chanel_in[i].requests[0]};
-				smart_chanel_shifted[i].bypassed_num =   smart_chanel_in [i].bypassed_num +1'b1;
-			end
-			assign smart_req[i]=rq[i];
-			// mux out smart chanel
-			assign smart_chanel_out[i] = (outport_is_granted[i])? smart_chanel_new[i] : smart_chanel_shifted[SS_PORT];
-			
-			
-			
-			
-		end else begin
-			assign {smart_chanel_shifted[i].requests,smart_req[i]} = {(SMART_NUM+1){1'b0}};
-			assign smart_chanel_out[i] = {SMART_CHANEL_w{1'b0}};
-		end
-		
-	end	
-	endgenerate
- 
- 
-endmodule 
- 
- 
- 
- 
- 
 
-module check_straight_oport #(
-		parameter TOPOLOGY          =   "MESH", 
-		parameter ROUTE_NAME        =   "XY",
-		parameter ROUTE_TYPE        =   "DETERMINISTIC", 
-		parameter DSTPw             =   4,
-		parameter SS_PORT_LOC     =   1
-		)(
-		destport_coded_i,
-		goes_straight_o
-		);
-	
-	input   [DSTPw-1 : 0] destport_coded_i;
-	output  goes_straight_o;
-		
-	generate 
-	/* verilator lint_off WIDTH */ 
-		if(TOPOLOGY == "MESH" || TOPOLOGY == "TORUS" || TOPOLOGY =="FMESH") begin :twoD		
-			/* verilator lint_on WIDTH */ 
-			if (SS_PORT_LOC == 0 || SS_PORT_LOC > 4) begin : local_ports
-				assign goes_straight_o = 1'b0; // There is not a next router in this case at all	
-			end	
-			else begin :non_local
-								
-				wire [4 : 0 ] destport_one_hot;
-				mesh_tori_decode_dstport decoder(
-						.dstport_encoded(destport_coded_i),
-						.dstport_one_hot(destport_one_hot)
-					);
-				
-				assign goes_straight_o = destport_one_hot [SS_PORT_LOC];	
-			end//else
-		end//mesh_tori
-		/* verilator lint_off WIDTH */ 
-		else if(TOPOLOGY ==  "RING" || TOPOLOGY ==  "LINE") begin :oneD		
-			/* verilator lint_on WIDTH */ 
-			if (SS_PORT_LOC == 0 || SS_PORT_LOC > 2) begin : local_ports
-				assign goes_straight_o = 1'b0; // There is not a next router in this case at all	
-			end	
-			else begin :non_local
-				
-				wire [2: 0 ] destport_one_hot;
-    
-				line_ring_decode_dstport decoder(
-						.dstport_encoded(destport_coded_i),
-						.dstport_one_hot(destport_one_hot)
-						
-					);
-				assign goes_straight_o = destport_one_hot [SS_PORT_LOC];	
-				
-			end	//non_local
-		end// oneD
-		
-		//TODO Add fattree & custom 
-			
-	endgenerate	
-	
-endmodule	
 
- 
-
-	
 module smart_validity_check_per_ivc  #(
-	parameter NOC_ID=0,
-	parameter IVC_NUM = 0
+    parameter IVC_NUM = 0
 ) (
-	reset,
-	clk,
-	//smart channel
-	goes_straight ,
-	smart_requests_i,
-	smart_ivc_i,
-	smart_hdr_flit,		
-	//flit		               
-	flit_hdr_flag_i,
-	flit_tail_flag_i,
-	flit_wr_i,
-	//router ivc status
-	ovc_locally_requested,
-	assigned_to_ss_ovc,
-	assigned_ovc_not_full,
-	ovc_is_assigned,
-	ivc_request,
-	//ss port status		                    
-	ss_ovc_avalable_in_ss_port,
-	ss_port_link_reg_flit_wr,
-	ss_ovc_crossbar_wr,
-	//output                          
-	smart_single_flit_pck_o,
-	smart_ivc_smart_en_o,
-	smart_credit_o,
-	smart_buff_space_decreased_o,
-	smart_ss_ovc_is_allocated_o,
-	smart_ss_ovc_is_released_o,
-	smart_mask_available_ss_ovc_o, 
-	smart_ivc_num_getting_ovc_grant_o,
-	smart_ivc_reset_o,			
-	smart_ivc_granted_ovc_num_o
+    reset,
+    clk,
+    //smart channel
+    goes_straight ,
+    smart_requests_i,
+    smart_ivc_i,
+    smart_hdr_flit,
+    //flit
+    flit_hdr_flag_i,
+    flit_tail_flag_i,
+    flit_wr_i,
+    //router ivc status
+    ovc_locally_requested,
+    assigned_to_ss_ovc,
+    assigned_ovc_not_full,
+    ovc_is_assigned,
+    ivc_request,
+    //ss port status
+    ss_ovc_avalable_in_ss_port,
+    ss_port_link_reg_flit_wr,
+    ss_ovc_crossbar_wr,
+    //output
+    smart_single_flit_pck_o,
+    smart_ivc_smart_en_o,
+    smart_credit_o,
+    smart_buff_space_decreased_o,
+    smart_ss_ovc_is_allocated_o,
+    smart_ss_ovc_is_released_o,
+    smart_mask_available_ss_ovc_o, 
+    smart_ivc_num_getting_ovc_grant_o,
+    smart_ivc_reset_o,
+    smart_ivc_granted_ovc_num_o
 );
-	
-	
-	`NOC_CONF
-
-	
-	input reset, clk;
-	//smart channel
-	input goes_straight,
-	smart_requests_i,
-	smart_ivc_i,
-	smart_hdr_flit,		
-	//flit		               
-	flit_hdr_flag_i ,
-	flit_tail_flag_i,
-	flit_wr_i,
-	//router ivc status
-	ovc_locally_requested,
-	assigned_to_ss_ovc,
-	assigned_ovc_not_full,
-	ovc_is_assigned,
-	ivc_request,
-	//ss port status		                    
-	ss_ovc_avalable_in_ss_port,
-	ss_ovc_crossbar_wr,
-	ss_port_link_reg_flit_wr;
-//output                          
-output 
-	smart_single_flit_pck_o	,
-	smart_ivc_smart_en_o,
-	smart_credit_o,
-	smart_buff_space_decreased_o,
-	smart_ss_ovc_is_allocated_o,
-	smart_ss_ovc_is_released_o,
-	smart_ivc_num_getting_ovc_grant_o,
-	smart_ivc_reset_o,			
-	smart_mask_available_ss_ovc_o;	
-		
-output reg [V-1 : 0] smart_ivc_granted_ovc_num_o;
-
-always @(*) begin 
-	smart_ivc_granted_ovc_num_o={V{1'b0}};
-	smart_ivc_granted_ovc_num_o[IVC_NUM]=smart_ivc_num_getting_ovc_grant_o;
-end	
-		
-		
-		
-wire  smart_req_valid_next  = smart_requests_i &  smart_ivc_i & goes_straight;
-logic smart_req_valid;	
-wire  smart_hdr_flit_req_next = smart_req_valid_next  & smart_hdr_flit;
-logic smart_hdr_flit_req;
-	
-pronoc_register #(.W(1)) req1 (.in(smart_req_valid_next), .reset(reset), .clk(clk), .out(smart_req_valid));
-pronoc_register #(.W(1)) req2 (.in(smart_hdr_flit_req_next), .reset(reset), .clk(clk), .out(smart_hdr_flit_req));
-
-
-
-	
-// condition1: new smart vc allocation condition
-wire hdr_flit_condition    = ~ovc_locally_requested & ss_ovc_avalable_in_ss_port;	
-wire nonhdr_flit_condition = assigned_to_ss_ovc & assigned_ovc_not_full;
-wire condition1 = 
-	/* verilator lint_off WIDTH */
-	(PCK_TYPE == "SINGLE_FLIT")?  hdr_flit_condition :
-	/* verilator lint_on WIDTH */	
-	(ovc_is_assigned)? nonhdr_flit_condition : hdr_flit_condition;
-wire condition2;
-generate
-
-/* verilator lint_off WIDTH */
-wire non_empty_ivc_condition =(PCK_TYPE == "SINGLE_FLIT")?  1'b0 :ivc_request;
-/* verilator lint_on WIDTH */
-
-	
-if( ADD_PIPREG_AFTER_CROSSBAR == 1) begin :link_reg
-	assign condition2= ~(non_empty_ivc_condition | ss_port_link_reg_flit_wr| ss_ovc_crossbar_wr);
-end else begin : no_link_reg
-	assign condition2= ~(non_empty_ivc_condition | ss_port_link_reg_flit_wr); // ss_port_link_reg_flit_wr are identical with ss_ovc_crossbar_wr when there is no link reg
-end
-	
-endgenerate	
-wire conditions_met = condition1 & condition2;
-assign smart_ivc_smart_en_o = conditions_met & smart_req_valid;
-	
-
-
-assign smart_single_flit_pck_o     = 
-	/* verilator lint_off WIDTH */
-	(PCK_TYPE == "SINGLE_FLIT")? 1'b1 :
-	/* verilator lint_on WIDTH */
-	(MIN_PCK_SIZE==1)?  flit_tail_flag_i & flit_hdr_flag_i : 1'b0; 
-
-assign smart_buff_space_decreased_o =  smart_ivc_smart_en_o & flit_wr_i ;
-assign smart_ivc_num_getting_ovc_grant_o  =  smart_buff_space_decreased_o & !ovc_is_assigned  & flit_hdr_flag_i;
-assign smart_ivc_reset_o   =  smart_buff_space_decreased_o & flit_tail_flag_i;
-assign smart_ss_ovc_is_released_o = smart_ivc_reset_o & ~smart_single_flit_pck_o;
-assign smart_ss_ovc_is_allocated_o = smart_ivc_num_getting_ovc_grant_o & ~smart_single_flit_pck_o;
-
+    import pronoc_pkg::*;
+    
+    input reset, clk;
+    //smart channel
+    input goes_straight,
+    smart_requests_i,
+    smart_ivc_i,
+    smart_hdr_flit,
+    //flit
+    flit_hdr_flag_i ,
+    flit_tail_flag_i,
+    flit_wr_i,
+    //router ivc status
+    ovc_locally_requested,
+    assigned_to_ss_ovc,
+    assigned_ovc_not_full,
+    ovc_is_assigned,
+    ivc_request,
+    //ss port status
+    ss_ovc_avalable_in_ss_port,
+    ss_ovc_crossbar_wr,
+    ss_port_link_reg_flit_wr;
+    //output
+    output 
+    smart_single_flit_pck_o,
+    smart_ivc_smart_en_o,    
+    smart_buff_space_decreased_o,
+    smart_ss_ovc_is_allocated_o,
+    smart_ss_ovc_is_released_o,
+    smart_ivc_num_getting_ovc_grant_o,
+    smart_ivc_reset_o,
+    smart_mask_available_ss_ovc_o;
+    
+    output reg [V-1 : 0] smart_ivc_granted_ovc_num_o;
+    output logic smart_credit_o;
+    always_comb begin 
+        smart_ivc_granted_ovc_num_o={V{1'b0}};
+        smart_ivc_granted_ovc_num_o[IVC_NUM]=smart_ivc_num_getting_ovc_grant_o;
+    end    
+    
+    wire  smart_req_valid_next  = smart_requests_i &  smart_ivc_i & goes_straight;
+    logic smart_req_valid;    
+    wire  smart_hdr_flit_req_next = smart_req_valid_next  & smart_hdr_flit;
+    logic smart_hdr_flit_req;
+    always_ff @ (`pronoc_clk_reset_edge) begin
+        if (`pronoc_reset) begin
+            smart_req_valid <= 1'b0;
+            smart_hdr_flit_req <= 1'b0;
+        end else begin
+            smart_req_valid <= smart_req_valid_next;
+            smart_hdr_flit_req <= smart_hdr_flit_req_next;
+        end
+    end
+    
+    // condition1: new smart vc allocation condition
+    wire hdr_flit_condition    = ~ovc_locally_requested & ss_ovc_avalable_in_ss_port;    
+    wire nonhdr_flit_condition = assigned_to_ss_ovc & assigned_ovc_not_full;
+    wire condition1 = 
+        (IS_SINGLE_FLIT)?  hdr_flit_condition :
+        (ovc_is_assigned)? nonhdr_flit_condition : hdr_flit_condition;
+    wire condition2;
+    wire non_empty_ivc_condition =(IS_SINGLE_FLIT)?  1'b0 :ivc_request;
+    
+    assign condition2=( ADD_PIPREG_AFTER_CROSSBAR == 1)? 
+        ~(non_empty_ivc_condition | ss_port_link_reg_flit_wr| ss_ovc_crossbar_wr):
+        ~(non_empty_ivc_condition | ss_port_link_reg_flit_wr); // ss_port_link_reg_flit_wr are identical with ss_ovc_crossbar_wr when there is no link reg
+    wire conditions_met = condition1 & condition2;
+    assign smart_ivc_smart_en_o = conditions_met & smart_req_valid;
+    assign smart_single_flit_pck_o = 
+        (IS_SINGLE_FLIT)? 1'b1 :
+        (MIN_PCK_SIZE==1)?  flit_tail_flag_i & flit_hdr_flag_i : 1'b0; 
+    assign smart_buff_space_decreased_o =  smart_ivc_smart_en_o & flit_wr_i ;
+    assign smart_ivc_num_getting_ovc_grant_o  =  smart_buff_space_decreased_o & !ovc_is_assigned  & flit_hdr_flag_i;
+    assign smart_ivc_reset_o   =  smart_buff_space_decreased_o & flit_tail_flag_i;
+    assign smart_ss_ovc_is_released_o = smart_ivc_reset_o & ~smart_single_flit_pck_o;
+    assign smart_ss_ovc_is_allocated_o = smart_ivc_num_getting_ovc_grant_o & ~smart_single_flit_pck_o;
+    //mask the available SS OVC for local requests allocation if the following conditions met
+    assign smart_mask_available_ss_ovc_o = smart_hdr_flit_req & ~ovc_locally_requested & condition2;
+    always_ff @ (`pronoc_clk_reset_edge) begin
+        if (`pronoc_reset)
+            smart_credit_o <= 1'b0;
+        else
+            smart_credit_o <= smart_buff_space_decreased_o;
+    end
+endmodule
 
 
-	
-//mask the available SS OVC for local requests allocation if the following conditions met
-assign smart_mask_available_ss_ovc_o = smart_hdr_flit_req & ~ovc_locally_requested & condition2;
-	
-	
-pronoc_register #(.W(1)) credit(.in(smart_buff_space_decreased_o), .reset(reset), .clk(clk), .out(smart_credit_o));
-	
-endmodule
-	
-	
-	
 module smart_allocator_per_iport # (
-	parameter NOC_ID=0,
-	parameter P=5,
-	parameter SW_LOC=0,
-	parameter SS_PORT_LOC=1
+    parameter P=5,
+    parameter SW_LOC=0,
+    parameter SS_PORT_LOC=1
 ) (
-	//general
-	clk,
-	reset,
-	current_r_addr_i,
-	neighbors_r_addr_i,
-	//smart_chanel & flit in
-	smart_chanel_i,
-	flit_chanel_i,
-	//router status signals
-	ivc_info,			
-	ss_ovc_info,
-	ovc_locally_requested,//make sure no conflict is existed between local & SMART VC allocation
-	ss_port_link_reg_flit_wr,
-	ss_smart_chanel_new,
-	//output
-	smart_destport_o,
-	smart_lk_destport_o,
-	smart_ivc_smart_en_o,              		
-	smart_credit_o,             	
-	smart_buff_space_decreased_o, 
-	smart_ss_ovc_is_allocated_o,     
-	smart_ss_ovc_is_released_o, 
-	smart_ivc_num_getting_ovc_grant_o,
-	smart_ivc_reset_o,
-	smart_mask_available_ss_ovc_o,
-	smart_hdr_flit_req_o,
-	smart_ivc_granted_ovc_num_o,	
-	smart_ivc_single_flit_pck_o,
-	smart_ovc_single_flit_pck_o
+    //general
+    clk,
+    reset,
+    current_r_addr_i,
+    neighbors_r_addr_i,
+    //smart_chanel & flit in
+    smart_chanel_i,
+    flit_chanel_i,
+    //router status signals
+    ivc_info,            
+    ss_ovc_info,
+    ovc_locally_requested,//make sure no conflict is existed between local & SMART VC allocation
+    ss_port_link_reg_flit_wr,
+    ss_smart_chanel_new,
+    //output
+    smart_destport_o,
+    smart_lk_destport_o,
+    smart_ivc_smart_en_o,
+    smart_credit_o,
+    smart_buff_space_decreased_o,
+    smart_ss_ovc_is_allocated_o,
+    smart_ss_ovc_is_released_o, 
+    smart_ivc_num_getting_ovc_grant_o,
+    smart_ivc_reset_o,
+    smart_mask_available_ss_ovc_o,
+    smart_hdr_flit_req_o,
+    smart_ivc_granted_ovc_num_o,
+    smart_ivc_single_flit_pck_o,
+    smart_ovc_single_flit_pck_o
 );
-	
-	`NOC_CONF
+    import pronoc_pkg::*;
+    //general
+    input clk, reset;
+    input [RAw-1   :0]  current_r_addr_i;
+    input [RAw-1:  0]  neighbors_r_addr_i [P-1 : 0];
+    //channels
+    input smart_chanel_t smart_chanel_i;
+    input flit_chanel_t flit_chanel_i;
+    //ivc
+    input ivc_info_t ivc_info [V-1 : 0];
+    input [V-1 : 0] ovc_locally_requested;
+    //ss port
+    input ovc_info_t   ss_ovc_info [V-1 : 0];
+    input ss_port_link_reg_flit_wr;    
+    input smart_chanel_t ss_smart_chanel_new;
+    //output
+    output logic [DSTPw-1 : 0] smart_destport_o,smart_lk_destport_o;
+    output logic smart_hdr_flit_req_o;
+    output [V-1 : 0] 
+        smart_ivc_smart_en_o,
+        smart_credit_o,
+        smart_buff_space_decreased_o, 
+        smart_ss_ovc_is_allocated_o,
+        smart_ss_ovc_is_released_o, 
+        smart_mask_available_ss_ovc_o,
+        smart_ivc_num_getting_ovc_grant_o,
+        smart_ivc_reset_o,
+        smart_ivc_single_flit_pck_o,
+        smart_ovc_single_flit_pck_o;
+    output [V*V-1 : 0] smart_ivc_granted_ovc_num_o;
+    
+    assign smart_ovc_single_flit_pck_o = smart_ivc_single_flit_pck_o;
+    wire  [DSTPw-1  :   0]  destport,lkdestport;
+    wire  goes_straight;
+    
+    localparam  LOCATED_IN_NI =  
+        (IS_1D_TOPO) ? (SW_LOC == 0 || SW_LOC > 2) :
+        (IS_2D_TOPO) ? (SW_LOC == 0 || SW_LOC > 4 ) : 0;
+    
+    // does the route computation for the current router
+    conventional_routing #(
+        .LOCATED_IN_NI   (LOCATED_IN_NI)
+    ) routing (
+        .reset (reset), 
+        .clk (clk), 
+        .current_r_addr (current_r_addr_i), 
+        .src_e_addr ( ),// needed only for custom routing
+        .dest_e_addr (smart_chanel_i.dest_e_addr), 
+        .destport (destport)
+    ); 
+    
+    always_ff @ (`pronoc_clk_reset_edge) begin
+        if (`pronoc_reset)
+            smart_destport_o <= '0;  // Reset to zero by default, adjust if needed
+        else
+            smart_destport_o <= destport;
+    end
+    check_straight_oport #(
+        .SS_PORT_LOC   ( SS_PORT_LOC)
+    ) check_straight (
+        .destport_coded_i (destport),
+        .goes_straight_o  (goes_straight)
+    );   
+    
+    //look ahead routing. take straight next router address as input
+    conventional_routing #(
+        .LOCATED_IN_NI   (LOCATED_IN_NI)
+    ) lkrouting (
+        .reset (reset), 
+        .clk (clk), 
+        .current_r_addr  (neighbors_r_addr_i[SS_PORT_LOC]), 
+        .src_e_addr ( ),// needed only for custom routing
+        .dest_e_addr (smart_chanel_i.dest_e_addr), 
+        .destport (lkdestport)
+    ); 
+    always_ff @ (`pronoc_clk_reset_edge) begin
+        if (`pronoc_reset)
+            smart_lk_destport_o <= '0;
+        else
+            smart_lk_destport_o <= lkdestport;
+    end    
+    
+    wire [V-1 : 0] ss_ovc_crossbar_wr;//If asserted, a flit will be injected to ovc at next clk cycle 
+    assign ss_ovc_crossbar_wr = (ss_smart_chanel_new.requests[0]) ? ss_smart_chanel_new.ovc : {V{1'b0}};
+    //assign smart_ivc_num_getting_ovc_grant_o = smart_ss_ovc_is_allocated_o;
+    //assign smart_ivc_reset_o = smart_ss_ovc_is_released_o;
+    
+    genvar i,j;
+    generate
+    for (i=0;i<V; i=i+1) begin : V_
+        smart_validity_check_per_ivc #(
+            .IVC_NUM(i)        
+        ) validity_check (
+            .reset(reset), 
+            .clk (clk), 
+            .goes_straight (goes_straight),
+            .smart_requests_i (smart_chanel_i.requests[0]), 
+            .smart_ivc_i(smart_chanel_i.ovc  [i]),
+            .smart_hdr_flit (smart_chanel_i.hdr_flit),
+            .flit_hdr_flag_i (flit_chanel_i.flit.hdr_flag),
+            .flit_tail_flag_i(flit_chanel_i.flit.tail_flag),
+            .flit_wr_i (flit_chanel_i.flit_wr),
+            .ovc_locally_requested(ovc_locally_requested[i]    ), 
+            .assigned_to_ss_ovc(ivc_info[i].assigned_ovc_num[i]),
+            .assigned_ovc_not_full(~ss_ovc_info[i].full), 
+            .ovc_is_assigned  (ivc_info[i].ovc_is_assigned), 
+            .ivc_request (ivc_info[i].ivc_req      ),
+            .ss_ovc_avalable_in_ss_port(ss_ovc_info[i].avalable), 
+            .ss_port_link_reg_flit_wr (ss_port_link_reg_flit_wr), 
+            .ss_ovc_crossbar_wr  (ss_ovc_crossbar_wr[i]),    
+            .smart_single_flit_pck_o (smart_ivc_single_flit_pck_o[i]),
+            .smart_ivc_smart_en_o   (smart_ivc_smart_en_o[i] ),
+            .smart_credit_o(smart_credit_o[i]), 
+            .smart_buff_space_decreased_o(smart_buff_space_decreased_o[i]), 
+            .smart_ss_ovc_is_allocated_o(smart_ss_ovc_is_allocated_o[i]), 
+            .smart_ss_ovc_is_released_o(smart_ss_ovc_is_released_o[i]),
+            .smart_mask_available_ss_ovc_o(smart_mask_available_ss_ovc_o[i]),
+            .smart_ivc_num_getting_ovc_grant_o(smart_ivc_num_getting_ovc_grant_o[i]),
+            .smart_ivc_reset_o(smart_ivc_reset_o[i]),            
+            .smart_ivc_granted_ovc_num_o (smart_ivc_granted_ovc_num_o[(i+1)*V-1 : i*V])
+        );    
+    end//for
+    endgenerate    
+    always_ff @ (`pronoc_clk_reset_edge) begin
+        if (`pronoc_reset) begin
+            smart_hdr_flit_req_o <= 1'b0;
+        end else begin
+            smart_hdr_flit_req_o <= smart_chanel_i.hdr_flit;
+        end
+    end
+endmodule    
+
 
-	//general
- 	input clk, reset;
- 	input [RAw-1   :0]  current_r_addr_i;
- 	input [RAw-1:  0]  neighbors_r_addr_i [P-1 : 0];	
-	//channels
-	input smart_chanel_t smart_chanel_i;
-	input flit_chanel_t flit_chanel_i;
-	//ivc
-	input ivc_info_t ivc_info [V-1 : 0];
-	input [V-1 : 0] ovc_locally_requested;
-	//ss port
-	input ovc_info_t   ss_ovc_info [V-1 : 0];
-	input ss_port_link_reg_flit_wr;	
-	input smart_chanel_t ss_smart_chanel_new;
-	//output
-	output [DSTPw-1 : 0] smart_destport_o,smart_lk_destport_o;
-	output smart_hdr_flit_req_o;
-	output [V-1 : 0] 
-		smart_ivc_smart_en_o,              		
-		smart_credit_o,             	
-		smart_buff_space_decreased_o, 
-		smart_ss_ovc_is_allocated_o,     
-		smart_ss_ovc_is_released_o, 
-		smart_mask_available_ss_ovc_o,
-		smart_ivc_num_getting_ovc_grant_o,
-		smart_ivc_reset_o,		
-		smart_ivc_single_flit_pck_o,
-		smart_ovc_single_flit_pck_o;	
-	output [V*V-1 : 0] smart_ivc_granted_ovc_num_o;
-	
-	assign smart_ovc_single_flit_pck_o = smart_ivc_single_flit_pck_o;
-	wire  [DSTPw-1  :   0]  destport,lkdestport;
-	wire  goes_straight;
-	
-	
-	
-	/* verilator lint_off WIDTH */ 
-	localparam  LOCATED_IN_NI=  
-		(TOPOLOGY=="RING" || TOPOLOGY=="LINE") ? (SW_LOC == 0 || SW_LOC>2) :
-		(TOPOLOGY =="MESH" || TOPOLOGY=="TORUS" || TOPOLOGY == "FMESH")? (SW_LOC == 0 || SW_LOC>4) : 0;
-	/* verilator lint_on WIDTH */ 
-	
-	// does the route computation for the current router
-	conventional_routing #(
-		.NOC_ID          (NOC_ID),
-		.TOPOLOGY        (TOPOLOGY), 
-		.ROUTE_NAME      (ROUTE_NAME), 
-		.ROUTE_TYPE      (ROUTE_TYPE), 
-		.T1              (T1), 
-		.T2              (T2), 
-		.T3              (T3), 
-		.RAw             (RAw), 
-		.EAw             (EAw), 
-		.DSTPw           (DSTPw),
-		.LOCATED_IN_NI   (LOCATED_IN_NI)
-	) routing (
-		.reset           (reset), 
-		.clk             (clk), 
-		.current_r_addr  (current_r_addr_i), 
-		.src_e_addr  	 (			),// needed only for custom routing
-		.dest_e_addr     (smart_chanel_i.dest_e_addr), 
-		.destport        (destport)
-	); 
-	
-	pronoc_register #(.W(DSTPw)) reg1 (.in(destport), .reset(reset), .clk(clk), .out(smart_destport_o));
-	
-	check_straight_oport #(
-		.TOPOLOGY      ( TOPOLOGY),
-		.ROUTE_NAME    ( ROUTE_NAME),
-		.ROUTE_TYPE    ( ROUTE_TYPE),
-		.DSTPw         ( DSTPw),
-		.SS_PORT_LOC   ( SS_PORT_LOC)
-	) check_straight (
-		.destport_coded_i (destport),
-		.goes_straight_o  (goes_straight)
-	);   
-	
-	//look ahead routing. take straight next router address as input
-	conventional_routing #(
-			.NOC_ID(NOC_ID),
-			.TOPOLOGY        (TOPOLOGY), 
-			.ROUTE_NAME      (ROUTE_NAME), 
-			.ROUTE_TYPE      (ROUTE_TYPE), 
-			.T1              (T1), 
-			.T2              (T2), 
-			.T3              (T3), 
-			.RAw             (RAw), 
-			.EAw             (EAw), 
-			.DSTPw           (DSTPw),
-			.LOCATED_IN_NI   (LOCATED_IN_NI)
-		) lkrouting (
-			.reset           (reset), 
-			.clk             (clk), 
-			.current_r_addr  (neighbors_r_addr_i[SS_PORT_LOC]), 
-			.src_e_addr  	 (			),// needed only for custom routing
-			.dest_e_addr     (smart_chanel_i.dest_e_addr), 
-			.destport        (lkdestport)
-		); 
-	
-	pronoc_register #(.W(DSTPw)) reg2 (.in(lkdestport), .reset(reset), .clk(clk), .out(smart_lk_destport_o));
-	
-	wire [V-1 : 0] ss_ovc_crossbar_wr;//If asserted, a flit will be injected to ovc at next clk cycle 
-	assign ss_ovc_crossbar_wr = (ss_smart_chanel_new.requests[0]) ? ss_smart_chanel_new.ovc : {V{1'b0}};
-	
-		
-	
-	//assign smart_ivc_num_getting_ovc_grant_o = smart_ss_ovc_is_allocated_o;
-	//assign smart_ivc_reset_o = smart_ss_ovc_is_released_o;
-	
-	genvar i,j;
-	generate
-	for (i=0;i<V; i=i+1) begin : vc
-		smart_validity_check_per_ivc #(
-			.NOC_ID(NOC_ID),
-			.IVC_NUM(i)		
-		) validity_check (
-			.reset                       (reset), 
-			.clk                         (clk), 
-			.goes_straight				 (goes_straight),
-			.smart_requests_i              (smart_chanel_i.requests[0] 		), 
-			.smart_ivc_i                   (smart_chanel_i.ovc  [i]    		),
-			.smart_hdr_flit				 (smart_chanel_i.hdr_flit),
-						
-			.flit_hdr_flag_i         	(flit_chanel_i.flit.hdr_flag),
-			.flit_tail_flag_i        	(flit_chanel_i.flit.tail_flag),
-			.flit_wr_i               	(flit_chanel_i.flit_wr),
-				
-			.ovc_locally_requested      (ovc_locally_requested[i]	), 
-						
-			.assigned_to_ss_ovc          (ivc_info[i].assigned_ovc_num[i]),
-			.assigned_ovc_not_full       (~ss_ovc_info[i].full), 
-			.ovc_is_assigned             (ivc_info[i].ovc_is_assigned), 
-			.ivc_request                 (ivc_info[i].ivc_req  	),
-						
-			.ss_ovc_avalable_in_ss_port  (ss_ovc_info[i].avalable), 
-			.ss_port_link_reg_flit_wr    (ss_port_link_reg_flit_wr), 
-			.ss_ovc_crossbar_wr          (ss_ovc_crossbar_wr[i]),	
-			
-			.smart_single_flit_pck_o       (smart_ivc_single_flit_pck_o[i]),
-			.smart_ivc_smart_en_o      		 (smart_ivc_smart_en_o[i]	),
-			.smart_credit_o             	 (smart_credit_o[i]), 
-			.smart_buff_space_decreased_o  (smart_buff_space_decreased_o[i]), 
-			.smart_ss_ovc_is_allocated_o   (smart_ss_ovc_is_allocated_o[i]), 
-			.smart_ss_ovc_is_released_o    (smart_ss_ovc_is_released_o[i]),
-			.smart_mask_available_ss_ovc_o (smart_mask_available_ss_ovc_o[i]),
-			.smart_ivc_num_getting_ovc_grant_o(smart_ivc_num_getting_ovc_grant_o[i]),
-			.smart_ivc_reset_o			 (smart_ivc_reset_o[i]),			
-			.smart_ivc_granted_ovc_num_o   (smart_ivc_granted_ovc_num_o[(i+1)*V-1 : i*V])
-		);	
-				
-		
-		
-		
-		
-	end//for
-	endgenerate	
-	
-	
-	pronoc_register #(.W(1)) reg3 (.in(smart_chanel_i.hdr_flit), .reset(reset), .clk(clk), .out(smart_hdr_flit_req_o));
-	
-endmodule	
- 
-//
 module smart_credit_manage #(
-	parameter V=4,	
-	parameter B=2
-	)(
-		credit_in,
-		smart_credit_in,
-		credit_out,
-		reset,
-		clk
-	);
-	localparam Bw=$clog2(B);
-		
- 	input [V-1 : 0]  credit_in, smart_credit_in;
- 	input reset,	clk;
- 	output [V-1 : 0]  credit_out;
-	genvar i;
-	generate 
-	for (i=0;i<V;i=i+1)begin :v_
-	 	smart_credit_manage_per_vc #(
-	 		.Bw(Bw)
-	 		)credit(
-	 			.credit_in(credit_in[i]),
-	 			.smart_credit_in(smart_credit_in[i]),
-	 			.credit_out(credit_out[i]),
-	 			.reset(reset),
-	 			.clk(clk)
-	 		);
-	end
-	endgenerate	
-endmodule	
-	
+    parameter V=4,    
+    parameter B=2
+    )(
+        credit_in,
+        smart_credit_in,
+        credit_out,
+        reset,
+        clk
+    );
+    localparam Bw=$clog2(B);
+    
+    input [V-1 : 0]  credit_in, smart_credit_in;
+    input reset,    clk;
+    output [V-1 : 0]  credit_out;
+    genvar i;
+    generate 
+    for (i=0;i<V;i=i+1)begin :v_
+        smart_credit_manage_per_vc #(
+            .Bw(Bw)
+        )credit(
+            .credit_in(credit_in[i]),
+            .smart_credit_in(smart_credit_in[i]),
+            .credit_out(credit_out[i]),
+            .reset(reset),
+            .clk(clk)
+        );
+    end
+    endgenerate    
+endmodule    
+
+
 module smart_credit_manage_per_vc #(
-		parameter Bw=2
+    parameter Bw=2
 )(
-	credit_in,
-	smart_credit_in,
-	credit_out,
-	reset,
-	clk
+    credit_in,
+    smart_credit_in,
+    credit_out,
+    reset,
+    clk
 );
-
- 	input credit_in, smart_credit_in,	reset,	clk;
- 	output credit_out;
-
- 	logic [Bw : 0] counter, counter_next;
- 	
- 	always @(*) begin 
- 		counter_next=counter;
- 		if(credit_in & 	smart_credit_in) counter_next = counter +1'b1;
- 		else if(credit_in |	smart_credit_in) counter_next=counter;
- 		else if(counter > 0) counter_next = counter -1'b1;
- 	end
-
- 	assign credit_out = credit_in | 	smart_credit_in | (counter > 0);
-
- 	pronoc_register #(.W(Bw+1)) reg1 (.in(counter_next), .reset(reset), .clk(clk), .out(counter));
- 	
-
+    input credit_in, smart_credit_in,    reset,    clk;
+    output credit_out;
+    logic [Bw : 0] counter, counter_next;
+    
+    always_comb begin 
+        counter_next=counter;
+        if(credit_in &     smart_credit_in) counter_next = counter +1'b1;
+        else if(credit_in |    smart_credit_in) counter_next=counter;
+        else if(counter > 0) counter_next = counter -1'b1;
+    end
+    assign credit_out = credit_in |     smart_credit_in | (counter > 0);
+    always_ff @ (`pronoc_clk_reset_edge) begin
+        if (`pronoc_reset) begin
+            counter <= '0;
+        end else begin
+            counter <= counter_next;
+        end
+    end
 endmodule
 
- 
-
- 
- 
- 
- 
- 
- 
- 
- 
- 
- 
- 
-
-	
-
-
+/**************************
+*    reduction_or
+***************************/
+module reduction_or #(
+    parameter W = 5,//out width
+    parameter N = 4 //array lenght 
+)(
+    D_in,
+    Q_out
+);
+    input  [W-1 : 0] D_in [N-1 : 0];
+    output reg [W-1 : 0] Q_out;
+    
+    // assign Q_out = D_in.or(); //it is not synthesizable able by some compiler
+    always_comb begin
+        Q_out = {W{1'b0}};
+        for (int i = 0; i < N; i++)
+            Q_out |=   D_in[i];
+    end
+endmodule
diff --git a/mpsoc/rtl/src_noc/router_top.sv b/mpsoc/rtl/src_noc/router_top.sv
index 27c9662..fbb8d1d 100644
--- a/mpsoc/rtl/src_noc/router_top.sv
+++ b/mpsoc/rtl/src_noc/router_top.sv
@@ -1,470 +1,417 @@
 `include "pronoc_def.v"
+/***********************************************************************
+ **    File: router_top.v
+ ** 
+ **    Copyright (C) 2014-2017  Alireza Monemi
+ ** 
+ **    This file is part of ProNoC
+ ** 
+ **    ProNoC ( stands for Prototype Network-on-chip)  is free software:
+ **    you can redistribute it and/or modify it under the terms of the GNU
+ **    Lesser General Public License as published by the Free Software Foundation,
+ **    either version 2 of the License, or (at your option) any later version.
+ ** 
+ **     ProNoC is distributed in the hope that it will be useful, but WITHOUT
+ **     ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ **     or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
+ **     Public License for more details.
+ ** 
+ **     You should have received a copy of the GNU Lesser General Public
+ **     License along with ProNoC. If not, see <http:**www.gnu.org/licenses/>.
+ ** 
+ ** 
+ ** Description:
+ *  ProNoC Top-Level Router
+ *  This module implements a two-stage NoC router with optional bypass
+ *  links for direct connections in the straight direction.
+ **************************************************************/
     
-    
-/****************************************************************************
- * router_top.v
- ****************************************************************************/
-  
-/**
- * Module: router_top
- * 
- *  add optional bypass links to two stage router.
- */
 module router_top #(
-	parameter NOC_ID=0,
-	parameter P=5
+    parameter ROUTER_ID=0,
+    parameter P=5
 )(
-	current_r_id,
-	current_r_addr,
-					
-	chan_in,
-	chan_out,
-        
-	router_event,
-					
-	clk,
-	reset						
+    router_config_in,
+    
+    chan_in,
+    chan_out,
+    
+    router_event,
+    
+    clk,
+    reset
 );
+    import pronoc_pkg::*;
+    
+    localparam DISABLED =P;
+    input router_config_t router_config_in;
+    
+    input smartflit_chanel_t chan_in [P-1 : 0];
+    output smartflit_chanel_t chan_out [P-1 : 0];
+    
+    output router_event_t router_event [P-1 : 0];
+    input   clk,reset;
+    
+    genvar i;
+    
+    flit_chanel_t r2_chan_in  [P-1 : 0];
+    flit_chanel_t r2_chan_out [P-1 : 0];
+    
+    ivc_info_t ivc_info  [P-1 : 0][V-1 : 0];
+    ovc_info_t ovc_info  [P-1 : 0][V-1 : 0];
+    iport_info_t iport_info  [P-1 : 0];
+    oport_info_t oport_info  [P-1 : 0];
+    
+    smart_chanel_t smart_chanel_in   [P-1 : 0];
+    smart_ctrl_t   smart_ctrl        [P-1 : 0];
+    
+    ctrl_chanel_t ctrl_in  [P-1 : 0];
+    ctrl_chanel_t ctrl_out [P-1 : 0];
+    
+    
+    always_comb begin
+        for(int k=0; k<P; k++) begin
+            ctrl_in [k] = chan_in[k].ctrl_chanel;
+            router_event[k].flit_wr_i = chan_in[k].flit_chanel.flit_wr;
+            router_event[k].bypassed_num = chan_in[k].smart_chanel.bypassed_num;
+            router_event[k].pck_wr_i  = chan_in[k].flit_chanel.flit_wr & chan_in[k].flit_chanel.flit.hdr_flag;
+            router_event[k].flit_wr_o = chan_out[k].flit_chanel.flit_wr;
+            router_event[k].pck_wr_o  = chan_out[k].flit_chanel.flit_wr & chan_out[k].flit_chanel.flit.hdr_flag;
+            router_event[k].flit_in_bypassed = chan_out[k].smart_chanel.flit_in_bypassed;
+            `ifdef ACTIVE_LOW_RESET_MODE
+            router_event[k].active_high_reset = 1'b0;
+            `else
+            router_event[k].active_high_reset = 1'b1;
+            `endif
+            router_event[k].empty = ~(|iport_info[k].ivc_req) && (chan_out[k].flit_chanel.flit_wr==1'b0);
+        end
+    end
+    
+    
+    flit_chanel_t ss_flit_chanel [P-1 : 0]; //flit  bypass link goes to straight port
+    
+    router_two_stage  #(//r2
+        .ROUTER_ID(ROUTER_ID),
+        .P(P)
+    )router_ref (
+        .ivc_info(ivc_info),
+        .ovc_info(ovc_info),
+        .iport_info(iport_info),
+        .oport_info(oport_info),
+        .smart_ctrl_in(smart_ctrl),
+        .router_config_in(router_config_in),
+        .chan_in(r2_chan_in),
+        .chan_out(r2_chan_out),
+        .ctrl_in(ctrl_in),
+        .ctrl_out(ctrl_out),
+        .clk(clk),
+        .reset(reset)
+    );
+    
+    wire  [V-1  :  0]  credit_out [P-1 : 0];
+    smart_chanel_t smart_chanel_out  [P-1 : 0];
+    generate
+    if(SMART_EN) begin : smart  //smart_bypass is enabled
+        smart_chanel_t smart_chanel_new  [P-1 : 0];
+        logic [RAw-1 :  0]  current_r_addr;
+        wire [V-1 : 0] ovc_locally_requested [P-1 : 0];
+        assign current_r_addr = router_config_in.router_addr;
+        
+        smart_forward_ivc_info #(
+            .P(P)
+        ) forward_ivc (
+            .ivc_info(ivc_info),
+            .iport_info(iport_info),
+            .oport_info(oport_info),
+            .smart_chanel(smart_chanel_new),
+            .ovc_locally_requested(ovc_locally_requested),
+            .reset(reset),
+            .clk(clk)
+        );
+        
+        smart_bypass_chanels #(
+            .P(P)
+        ) smart_bypass (
+            .ivc_info(ivc_info),
+            .iport_info(iport_info),
+            .oport_info(oport_info),
+            .smart_chanel_new(smart_chanel_new),
+            .smart_chanel_in(smart_chanel_in),
+            .smart_chanel_out(smart_chanel_out),
+            .smart_req(),
+            .reset(reset),
+            .clk(clk)
+        );
+        
+        wire  [RAw-1:  0]  neighbors_r_addr [P-1: 0];
+        
+        wire  [V-1  :  0]  ivc_smart_en [P-1 : 0];
+        for(i=0;i<P;i=i+1)begin : Port_
+            localparam SS_PORT = strieght_port(P,i);
+            
+            if(SS_PORT == DISABLED) begin: smart_dis
+                assign smart_ctrl[i]={SMART_CTRL_w{1'b0}};
+            end
+            else begin :smart_en
+                assign neighbors_r_addr [i] = chan_in[i].ctrl_chanel.router_addr;
+                //smart allocator
+                smart_allocator_per_iport #(
+                    .P(P),
+                    .SW_LOC(i),
+                    .SS_PORT_LOC(SS_PORT)
+                ) smart_allocator (
+                    .clk(clk),
+                    .reset(reset),
+                    .current_r_addr_i(current_r_addr),
+                    .neighbors_r_addr_i(neighbors_r_addr),
+                    .smart_chanel_i(chan_in[i].smart_chanel),
+                    .flit_chanel_i(chan_in[i].flit_chanel),
+                    .ivc_info (ivc_info[i]),
+                    .ss_ovc_info(ovc_info[SS_PORT]),
+                    .ovc_locally_requested(ovc_locally_requested[SS_PORT]),
+                    .ss_smart_chanel_new (smart_chanel_new[SS_PORT]),
+                    .ss_port_link_reg_flit_wr(r2_chan_out[SS_PORT].flit_wr),
+                    
+                    .smart_ivc_single_flit_pck_o(smart_ctrl[i].ivc_single_flit_pck),
+                    .smart_destport_o(smart_ctrl[i].destport),
+                    .smart_lk_destport_o(smart_ctrl[i].lk_destport),
+                    .smart_hdr_flit_req_o(smart_ctrl[i].hdr_flit_req),
+                    .smart_ivc_smart_en_o(ivc_smart_en[i]),
+                    .smart_credit_o(smart_ctrl[i].credit_out),
+                    .smart_buff_space_decreased_o(smart_ctrl[SS_PORT].buff_space_decreased),
+                    .smart_ivc_num_getting_ovc_grant_o(smart_ctrl[i].ivc_num_getting_ovc_grant),
+                    .smart_ivc_reset_o(smart_ctrl[i].ivc_reset),
+                    .smart_ivc_granted_ovc_num_o(smart_ctrl[i].ivc_granted_ovc_num),
+                    .smart_ovc_single_flit_pck_o(smart_ctrl[SS_PORT].ovc_single_flit_pck),
+                    .smart_ss_ovc_is_allocated_o(smart_ctrl[SS_PORT].ovc_is_allocated),
+                    .smart_ss_ovc_is_released_o (smart_ctrl[SS_PORT].ovc_is_released),
+                    .smart_mask_available_ss_ovc_o(smart_ctrl[SS_PORT].mask_available_ovc)
+                );
+                assign smart_ctrl[i].ivc_smart_en = ivc_smart_en[i];
+                assign smart_ctrl[i].smart_en = |ivc_smart_en[i];
+                
+                `ifdef SIMULATION
+                //assign chan_out[i].smart_chanel =(smart_chanel[i].requests[0]) ? smart_chanel_new[i] : take ss shifted smart;    
+                smart_chanel_check check (
+                    .flit_chanel(chan_out[i].flit_chanel),
+                    .smart_chanel(chan_out[i].smart_chanel),
+                    .reset(reset),
+                    .clk(clk)
+                );
+                `endif //SIMULATION
+                
+                smart_credit_manage #(
+                    .V(V),
+                    .B(B)
+                ) smart_credit_manage (
+                    .credit_in(r2_chan_out[i].credit),
+                    .smart_credit_in(smart_ctrl[i].credit_out),
+                    .credit_out( credit_out[i]),
+                    .reset(reset),
+                    .clk(clk)
+                );
+                
+            end //smart_en
+        end//for Port_
+    end else begin 
+        for(i=0;i<P;i=i+1) begin : Port_
+            assign smart_ctrl[i]={SMART_CTRL_w{1'b0}};
+            assign smart_chanel_out[i] = '0;
+            assign credit_out[i] = '0;
+        end
+    end
+    endgenerate
+    
+    always_comb begin
+        for(int k=0;k<P;k++) begin 
+            r2_chan_in[k] = chan_in[k].flit_chanel;
+            chan_out[k].flit_chanel = r2_chan_out[k];
+            chan_out[k].ctrl_chanel = ctrl_out [k];
+            smart_chanel_in[k] =   chan_in[k].smart_chanel;
+            chan_out[k].smart_chanel = smart_chanel_out[k];
+            if( SMART_EN & (strieght_port(P,k) != DISABLED)) begin
+                //mask only flit_wr if smart_en is asserted
+                if(smart_ctrl[k].smart_en)r2_chan_in[k].flit_wr = 1'b0;
+                // mux out flit channel
+                chan_out[k].flit_chanel.credit = credit_out[k] ;
+                if(smart_ctrl[strieght_port(P,k)].smart_en) begin
+                    chan_out[k].flit_chanel.flit  =  ss_flit_chanel[k].flit;
+                    chan_out[k].flit_chanel.flit_wr =  ss_flit_chanel[k].flit_wr;
+                end
+                chan_out[k].smart_chanel.flit_in_bypassed =smart_ctrl[k].smart_en & chan_in[k].flit_chanel.flit_wr ;
+            end
+        end
+    end
 
-	`NOC_CONF    
-	
-	
-	localparam DISABLED =P;
-
-	input [RAw-1 :  0]  current_r_addr;
-	input [31 : 0] current_r_id;
-	
-	
-	input   smartflit_chanel_t chan_in [P-1 : 0];
-	output  smartflit_chanel_t chan_out [P-1 : 0];
-	
-	output router_event_t router_event [P-1 : 0];
-	
-	
-	
-	input   clk,reset;	
-	
-	genvar i,j;
-	
-  
-	//synthesis translate_off 
-	//synopsys  translate_off
-	/* verilator lint_off WIDTH */
-	initial begin
-		if((SSA_EN=="YES")  &&(SMART_EN==1'b1))begin
-			$display("ERROR: Only one of the SMART or SAA can be enabled at the same time");
-			$finish;        
-		end
-		if((SMART_EN==1'b1) && COMBINATION_TYPE!="COMB_NONSPEC")begin
-			$display("ERROR: SMART only works with non-speculative VSA");
-			$finish;        
-		end	
-		if((MIN_PCK_SIZE > 1) &&(PCK_TYPE == "SINGLE_FLIT")) begin 
-			$display("ERROR: The minimum packet size must be set as one for single-flit packet type NoC");
-			$finish;	
-		end
-		if(((SSA_EN=="YES")  ||(SMART_EN==1'b1)) && CAST_TYPE!="UNICAST") begin
-			$display("ERROR: SMART or SAA do not support muticast/braodcast packets");
-			$finish;        
-		end
-		
-	end	
-	/* verilator lint_on WIDTH */
-	
-	
-	
-	
-	
-	logic report_active_ivcs = 0;
-	
-	generate 
-	for(i=0; i<P; i=i+1) begin :P1_
-		for(j=0; j<V; j=j+1) begin :V_		
-			always @(posedge report_active_ivcs) begin 
-				if(ivc_info[i][j].ivc_req) $display("%t : The IVC in router[%h] port[%d] VC [%d] is not empty",$time,current_r_addr,i,j);
-			end
-		end		
-	end
-	endgenerate
-		
-	//synopsys  translate_on
-	//synthesis translate_on 
-	
-	
-	
-	
-	
-	
-	flit_chanel_t r2_chan_in  [P-1 : 0];
-	flit_chanel_t r2_chan_out [P-1 : 0];
-	
-	ivc_info_t 	 ivc_info    [P-1 : 0][V-1 : 0];
-	ovc_info_t   ovc_info    [P-1 : 0][V-1 : 0];
-	iport_info_t iport_info  [P-1 : 0];
-	oport_info_t oport_info  [P-1 : 0]; 
-	smart_chanel_t smart_chanel_new  [P-1 : 0];
-	smart_chanel_t smart_chanel_in   [P-1 : 0];
-	smart_chanel_t smart_chanel_out  [P-1 : 0]; 
-	smart_ctrl_t   smart_ctrl        [P-1 : 0];
-	
-
-	ctrl_chanel_t ctrl_in  [P-1 : 0];
-	ctrl_chanel_t ctrl_out [P-1 : 0];
-	
-	generate 
-	for(i=0; i<P; i=i+1) begin :Pt_		
-		assign  ctrl_in [i] = chan_in[i].ctrl_chanel;
-		assign  chan_out[i].ctrl_chanel= ctrl_out [i];	
-	end
-	 
-	for(i=0; i<P; i=i+1) begin :P2_
-		assign router_event[i].flit_wr_i = chan_in[i].flit_chanel.flit_wr;
-		assign router_event[i].bypassed_num = chan_in[i].smart_chanel.bypassed_num;
-		assign router_event[i].pck_wr_i  = chan_in[i].flit_chanel.flit_wr & chan_in[i].flit_chanel.flit.hdr_flag;
-		assign router_event[i].flit_wr_o = chan_out[i].flit_chanel.flit_wr;
-		assign router_event[i].pck_wr_o  = chan_out[i].flit_chanel.flit_wr & chan_out[i].flit_chanel.flit.hdr_flag;
-		assign router_event[i].flit_in_bypassed = chan_out[i].smart_chanel.flit_in_bypassed;
-`ifdef ACTIVE_LOW_RESET_MODE 
-        assign router_event[i].active_high_reset = 1'b0;
- `else 
-        assign router_event[i].active_high_reset = 1'b1;
-`endif  		
-        assign router_event[i].empty = ~(|iport_info[i].ivc_req) && (chan_out[i].flit_chanel.flit_wr==1'b0);        
-	end
-	endgenerate
-
-
-
-
-	
-	// synthesis translate_off
-	
-	//header flit info, it is useful for debugin 
-	hdr_flit_t hdr_flit_i [P-1 : 0]; // the received packet header flit info 
-	hdr_flit_t hdr_flit_o [P-1 : 0]; // the sent packet header flit info 
-		
-	generate 
-		for(i=0; i<P; i=i+1) begin :Port_				
-					
-			header_flit_info #(
-				.NOC_ID(NOC_ID)
-			) in_extract(
-				.flit(chan_in[i].flit_chanel.flit),
-				.hdr_flit( hdr_flit_i[i]),		
-				.data_o()
-			);
-		
-			header_flit_info #(
-				.NOC_ID(NOC_ID)
-			) out_extract(
-				.flit(chan_out[i].flit_chanel.flit),
-				.hdr_flit( hdr_flit_o[i]),
-				.data_o()
-			);
-			
-			if(DEBUG_EN) begin :dbg
-				check_flit_chanel_type_is_in_order #(
-					.V(V),
-					.PCK_TYPE(PCK_TYPE),
-					.MIN_PCK_SIZE(MIN_PCK_SIZE)
-				) IVC_flit_type_check(
-					.clk(clk),
-					.reset(reset),
-					.hdr_flg_in(chan_in[i].flit_chanel.flit.hdr_flag),
-					.tail_flg_in(chan_in[i].flit_chanel.flit.tail_flag),
-					.flit_in_wr(chan_in[i].flit_chanel.flit_wr),
-					.vc_num_in(chan_in[i].flit_chanel.flit.vc)
-				);
-				
-				check_pck_size #(
-					.NOC_ID(NOC_ID),
-					.V(V),
-					.MIN_PCK_SIZE(MIN_PCK_SIZE),
-					.Fw(Fw),
-					.DAw(DAw),
-					.CAST_TYPE(CAST_TYPE),
-					.NE(NE),
-					.B(B),
-					.LB(LB)
-				) check_pck_siz(
-					.clk(clk),
-					.reset(reset),
-					.hdr_flg_in(chan_in[i].flit_chanel.flit.hdr_flag),
-					.tail_flg_in(chan_in[i].flit_chanel.flit.tail_flag),
-					.flit_in_wr(chan_in[i].flit_chanel.flit_wr),
-					.vc_num_in(chan_in[i].flit_chanel.flit.vc),
-					.dest_e_addr_in(chan_in[i].flit_chanel.flit.payload[E_DST_MSB : E_DST_LSB])
-				);				
-		
-			end		
-		
-		end
-	endgenerate
-	// synthesis translate_on
-	
-	
-	
-	
-	
-	wire [V-1 : 0] ovc_locally_requested [P-1 : 0]; 
-	flit_chanel_t ss_flit_chanel [P-1 : 0]; //flit  bypass link goes to straight port
-
-	router_two_stage  #(//r2
-			.NOC_ID(NOC_ID),
-			.P(P)
-		)router_ref(
-			.ivc_info(ivc_info),
-			.ovc_info(ovc_info),
-			.iport_info(iport_info),
-			.oport_info(oport_info),
-			.smart_ctrl_in(smart_ctrl),
-			.current_r_addr(current_r_addr),
-			.current_r_id(current_r_id),
-			.chan_in(r2_chan_in), 
-			.chan_out(r2_chan_out), 
-			.ctrl_in(ctrl_in),
-			.ctrl_out(ctrl_out),
-			.clk(clk), 
-			.reset(reset)			
-		);                
-
-	generate 
-		
-		if(SMART_EN) begin :smart
-		
-		
-			smart_forward_ivc_info	#(
-				.NOC_ID(NOC_ID),
-				.P(P)
-			) forward_ivc(			
-				.ivc_info(ivc_info),
-				.iport_info(iport_info),
-				.oport_info(oport_info),
-				.smart_chanel(smart_chanel_new),
-				.ovc_locally_requested(ovc_locally_requested),
-				.reset(reset),
-				.clk(clk)
-			);
-		
-			smart_bypass_chanels #(
-				.NOC_ID(NOC_ID),
-				.P(P)
-			) smart_bypass(			
-				.ivc_info(ivc_info),
-				.iport_info(iport_info),
-				.oport_info(oport_info),
-				.smart_chanel_new(smart_chanel_new),
-				.smart_chanel_in(smart_chanel_in),
-				.smart_chanel_out(smart_chanel_out),
-				.smart_req(),
-				.reset(reset),
-				.clk(clk)			
-			);	
-		
-			wire  [RAw-1:  0]  neighbors_r_addr [P-1: 0];	
-			wire  [V-1  :  0]  credit_out [P-1 : 0];
-			wire  [V-1  :  0]  ivc_smart_en [P-1 : 0];
-			for(i=0;i<P;i=i+1)begin : Port_
-				localparam SS_PORT = strieght_port(P,i);
-				if(SS_PORT == DISABLED) begin: smart_dis 
-					assign r2_chan_in[i]   =  chan_in[i].flit_chanel;
-					assign chan_out[i].flit_chanel     =  r2_chan_out[i];	
-					assign smart_ctrl[i]={SMART_CTRL_w{1'b0}};					
-				end 
-				else begin :smart_en
-					assign neighbors_r_addr [i] = chan_in[i].ctrl_chanel.neighbors_r_addr;
-					//smart allocator
-					smart_allocator_per_iport #(
-						.NOC_ID(NOC_ID),
-						.P(P), 
-						.SW_LOC(i), 
-						.SS_PORT_LOC(SS_PORT)
-					) smart_allocator (
-						.clk(clk), 
-						.reset(reset), 
-						.current_r_addr_i(current_r_addr), 
-						.neighbors_r_addr_i(neighbors_r_addr), 
-						.smart_chanel_i(chan_in[i].smart_chanel), 
-						.flit_chanel_i(chan_in[i].flit_chanel), 
-						.ivc_info (ivc_info[i]), 
-						.ss_ovc_info(ovc_info[SS_PORT]),
-						.ovc_locally_requested(ovc_locally_requested[SS_PORT]),
-						.ss_smart_chanel_new (smart_chanel_new[SS_PORT]),
-						.ss_port_link_reg_flit_wr(r2_chan_out[SS_PORT].flit_wr), 
-							
-						.smart_ivc_single_flit_pck_o(smart_ctrl[i].ivc_single_flit_pck),
-						.smart_destport_o(smart_ctrl[i].destport),	
-						.smart_lk_destport_o(smart_ctrl[i].lk_destport),	
-						.smart_hdr_flit_req_o(smart_ctrl[i].hdr_flit_req),
-						.smart_ivc_smart_en_o(ivc_smart_en[i]),              		
-						.smart_credit_o(smart_ctrl[i].credit_out),             	
-						.smart_buff_space_decreased_o(smart_ctrl[SS_PORT].buff_space_decreased), 
-						.smart_ivc_num_getting_ovc_grant_o(smart_ctrl[i].ivc_num_getting_ovc_grant),
-						.smart_ivc_reset_o(smart_ctrl[i].ivc_reset),
-						.smart_ivc_granted_ovc_num_o(smart_ctrl[i].ivc_granted_ovc_num),
-						.smart_ovc_single_flit_pck_o(smart_ctrl[SS_PORT].ovc_single_flit_pck),
-						.smart_ss_ovc_is_allocated_o(smart_ctrl[SS_PORT].ovc_is_allocated),     
-						.smart_ss_ovc_is_released_o	(smart_ctrl[SS_PORT].ovc_is_released), 
-						.smart_mask_available_ss_ovc_o(smart_ctrl[SS_PORT].mask_available_ovc)	
-					
-					);
-				    
-					assign smart_ctrl[i].ivc_smart_en = ivc_smart_en[i];
-					assign smart_ctrl[i].smart_en = |ivc_smart_en[i];
-					
-				   
-				
-				
-					// synthesis translate_off
-					//assign chan_out[i].smart_chanel =(smart_chanel[i].requests[0]) ? smart_chanel_new[i] : take ss shifted smart;	
-					smart_chanel_check #(
-						.NOC_ID(NOC_ID)
-					) check(
-						.flit_chanel(chan_out[i].flit_chanel),
-						.smart_chanel(chan_out[i].smart_chanel),
-						.reset(reset),
-						.clk(clk)		
-					);
-					// synthesis translate_on
-					
-					assign smart_chanel_in[i] =   chan_in[i].smart_chanel;
-					
-				
-					//r2 demux
-					// flit_in_wr demux 
-					always @(*) begin 
-						chan_out[i].smart_chanel = smart_chanel_out[i];
-						chan_out[i].smart_chanel.flit_in_bypassed =smart_ctrl[i].smart_en & chan_in[i].flit_chanel.flit_wr ;
-						
-						
-						//mask only flit_wr if smart_en is asserted 
-						r2_chan_in[i]   =  chan_in[i].flit_chanel;
-						//can replace destport here and remove lk rout from internal router 
-						if(smart_ctrl[i].smart_en) r2_chan_in[i].flit_wr = 1'b0;
-						
-					
-						//send flit_in to straight out port. Replace lk destport in header flit
-						ss_flit_chanel[SS_PORT] = chan_in[i].flit_chanel;
-						if(smart_ctrl[i].hdr_flit_req) ss_flit_chanel[SS_PORT].flit[DST_P_MSB : DST_P_LSB] =  smart_ctrl[i].lk_destport;   
-					end
-
-					always @(*) begin 
-						// mux out flit channel
-						chan_out[i].flit_chanel = r2_chan_out[i];
-						chan_out[i].flit_chanel.credit    =  credit_out[i] ;
-						if(smart_ctrl[SS_PORT].smart_en) begin
-							chan_out[i].flit_chanel.flit    =  ss_flit_chanel[i].flit;
-							chan_out[i].flit_chanel.flit_wr =  ss_flit_chanel[i].flit_wr;
-						
-						end
-					end
-				
-					smart_credit_manage #(
-							.V(V), 
-							.B(B)
-						) smart_credit_manage(
-							.credit_in(r2_chan_out[i].credit), 
-							.smart_credit_in(smart_ctrl[i].credit_out), 
-							.credit_out( credit_out[i]), 
-							.reset(reset), 
-							.clk(clk));
-				
-				
-				
-				end //for
-			end//smart_en
-		
-		
-		
-		end else begin :no_smart
-			for(i=0;i<P;i=i+1)begin : Port_
-				assign r2_chan_in[i]   =  chan_in[i].flit_chanel;
-				assign chan_out[i].flit_chanel     =  r2_chan_out[i];	
-				assign smart_ctrl[i]={SMART_CTRL_w{1'b0}};
-			end//for
-		end
-	endgenerate	
+    //r2 demux
+    // flit_in_wr demux
+    always_comb begin
+        for(int k=0;k<P;k++) begin 
+            //can replace destport here and remove lk rout from internal router
+            //send flit_in to straight out port. Replace lk destport in header flit
+            automatic int straight_p= strieght_port(P,k);
+            if ((straight_p != DISABLED) & SMART_EN) begin
+                ss_flit_chanel[straight_p] = chan_in[k].flit_chanel;
+                if(smart_ctrl[k].hdr_flit_req) ss_flit_chanel[straight_p].flit[DST_P_MSB : DST_P_LSB] =  smart_ctrl[k].lk_destport;
+            end
+        end
+    end
 
-	
+/**************************************
+*        Validating Parameters 
+*        /Simulation
+***************************************/
+`ifdef SIMULATION
+    initial begin
+        if((SSA_EN==1)  && (SMART_EN==1))begin
+            $display("ERROR: Only one of the SMART or SAA can be enabled at the same time");
+            $finish;
+        end
+        if((SMART_EN==1) && (IS_COMB_NONSPEC==1'b0))begin
+            $display("ERROR: SMART only works with non-speculative VSA");
+            $finish;
+        end
+        if((MIN_PCK_SIZE > 1) && (IS_SINGLE_FLIT==1'b1)) begin 
+            $display("ERROR: The minimum packet size must be set as one for single-flit packet type NoC");
+            $finish;
+        end
+        if(((SSA_EN==1) || (SMART_EN==1)) && (IS_UNICAST==1'b0)) begin
+            $display("ERROR: SMART or SAA do not support muticast/braodcast packets");
+            $finish;
+        end
+    end
+    generate 
+    `ifdef IVC_DEBUG
+    genvar j;
+    wire report_active_ivcs = testbench_noc.report_active_ivcs;
+    for(i=0; i<P; i=i+1) begin :P1_
+        for(j=0; j<V; j=j+1) begin :V_
+            always @(posedge report_active_ivcs) begin
+                if(ivc_info[i][j].ivc_req)begin 
+                    $display("%t : The IVC in router_addr=%h, router_id=%d, port=%d VC=%d is not empty ivc_info:%p",$time,router_config_in.router_addr,router_config_in.router_id,i,j,ivc_info[i][j]);
+                end
+            end
+        end
+    end
+    `endif
+    //header flit info, it is useful for debugin
+    // hdr_flit_t hdr_flit_i [P-1 : 0]; // the received packet header flit info
+    // hdr_flit_t hdr_flit_o [P-1 : 0]; // the sent packet header flit info
+    
+    if(DEBUG_EN) begin :dbg
+        for(i=0; i<P; i=i+1) begin : P_
+            check_flit_chanel_type_is_in_order IVC_flit_type_check (
+                .clk(clk),
+                .reset(reset),
+                .hdr_flg_in(chan_in[i].flit_chanel.flit.hdr_flag),
+                .tail_flg_in(chan_in[i].flit_chanel.flit.tail_flag),
+                .flit_in_wr(chan_in[i].flit_chanel.flit_wr),
+                .vc_num_in(chan_in[i].flit_chanel.flit.vc)
+            );
+            
+            check_pck_size check_pck_siz (
+                .clk(clk),
+                .reset(reset),
+                .hdr_flg_in(chan_in[i].flit_chanel.flit.hdr_flag),
+                .tail_flg_in(chan_in[i].flit_chanel.flit.tail_flag),
+                .flit_in_wr(chan_in[i].flit_chanel.flit_wr),
+                .vc_num_in(chan_in[i].flit_chanel.flit.vc),
+                .dest_e_addr_in(chan_in[i].flit_chanel.flit.payload[E_DST_MSB : E_DST_LSB])
+            );
+        end
+    end
+    endgenerate
+    
 //`ifdef VERILATOR
-//	logic  nb_router_active [P-1 : 0] /*verilator public_flat_rd*/ ;
-//	logic  router_is_ideal /*verilator public_flat_rd*/ ;
-//	logic  not_ideal_next,not_ideal;
-//	integer ii,jj;
-//	always @(*) begin 
-//		router_is_ideal = 1'b1;
-//		not_ideal_next  = 1'b0;		
-//		for(ii=0; ii<P; ii=ii+1) begin
-//			nb_router_active[ii]= 1'b0;
-//			if(chan_out[ii].flit_chanel.flit_wr) nb_router_active[ii]=1'b1;
-//			if(chan_out[ii].flit_chanel.credit > {V{1'b0}}) nb_router_active[ii]=1'b1;
-//			if(chan_out[ii].smart_chanel.requests > {SMART_NUM{1'b0}}) nb_router_active[ii]=1'b1;
-//			
-//			for(jj=0; jj<V; jj=jj+1) begin 		
-//				//no active request is in any input queues
-//				if(ivc_info[ii][jj].ivc_req)begin 
-//					router_is_ideal=1'b0;
-//					not_ideal_next=1'b1;
-//				end
-//			end
-//			//no output flit wr 
-//			if(r2_chan_out[ii].flit_wr)  router_is_ideal=1'b0;
-//		end
-//		if(not_ideal) router_is_ideal =1'b0; // delay one clock cycle if the input req exist in last clock cycle bot not on the current one
-//	end
-//	pronoc_register #(	.W(1)) no_ideal_register(.in(not_ideal_next), .reset(reset),  .clk(clk), .out(not_ideal));
+//    logic  nb_router_active [P-1 : 0] /*verilator public_flat_rd*/ ;
+//    logic  router_is_ideal /*verilator public_flat_rd*/ ;
+//    logic  not_ideal_next,not_ideal;
+//    integer ii,jj;
+//    always_comb begin
+//        router_is_ideal = 1'b1;
+//        not_ideal_next  = 1'b0;
+//        for(ii=0; ii<P; ii=ii+1) begin
+//            nb_router_active[ii]= 1'b0;
+//            if(chan_out[ii].flit_chanel.flit_wr) nb_router_active[ii]=1'b1;
+//            if(chan_out[ii].flit_chanel.credit > {V{1'b0}}) nb_router_active[ii]=1'b1;
+//            if(chan_out[ii].smart_chanel.requests > {SMART_NUM{1'b0}}) nb_router_active[ii]=1'b1;
+//            
+//            for(jj=0; jj<V; jj=jj+1) begin
+//                //no active request is in any input queues
+//                if(ivc_info[ii][jj].ivc_req)begin
+//                    router_is_ideal=1'b0;
+//                    not_ideal_next=1'b1;
+//                end
+//            end
+//            //no output flit wr
+//            if(r2_chan_out[ii].flit_wr)  router_is_ideal=1'b0;
+//        end
+//        if(not_ideal) router_is_ideal =1'b0; // delay one clock cycle if the input req exist in last clock cycle bot not on the current one
+//    end
+//    pronoc_register #(    .W(1)) no_ideal_register(.D_in(not_ideal_next), .reset(reset),  .clk(clk), .Q_out(not_ideal));
 //`endif
-	
-	
-	
-endmodule 
-
-
-
-module router_top_v //to be used as top module in veralator
+    
+`endif //SIMULATION
+    
+endmodule
+    
+/**************************
+ * Router_top_v:
+ * This module instantiates router_top and
+ * serves as the top module in Verilator simulation.
+ * It resolves the Verilator error caused by
+ * router_top being used in another module (NoC),
+ * preventing it from being defined as the top module.
+ **************************/ 
+    
+module router_top_v
 #(
-	parameter NOC_ID=0,
-	parameter P=5
+    parameter ROUTER_ID=0,
+    parameter P=5
 )(
-	current_r_addr,
-	current_r_id,
-        
-	chan_in,
-	chan_out,
-        
-	router_event,
-			
-	clk,
-	reset
+    current_r_addr,
+    current_r_id,
+    
+    chan_in,
+    chan_out,
+    
+    router_event,
+    
+    clk,
+    reset
 );
-  
-	 
-	`NOC_CONF    	
-
-	input  [RAw-1 : 0] current_r_addr;
-	input [31:0] current_r_id;
-    
-	input   smartflit_chanel_t chan_in [P-1 : 0];
-	output  smartflit_chanel_t chan_out [P-1 : 0];
-	input   reset,clk;
-	
-	output router_event_t router_event [P-1 : 0];
-	
-	
-	router_top #(
-		.NOC_ID(NOC_ID),	
-		.P(P)           
-	) router (
-		.current_r_id(current_r_id),
-		.current_r_addr(current_r_addr),
-		.chan_in(chan_in),
-		.chan_out(chan_out), 
-		.router_event(router_event),
-		.clk(clk),
-		.reset(reset)
-	);
-	
-		
+    
+    import pronoc_pkg::*; 
+    
+    input  [RAw-1 : 0] current_r_addr;
+    input [31:0] current_r_id;
+    input   smartflit_chanel_t chan_in [P-1 : 0];
+    output  smartflit_chanel_t chan_out [P-1 : 0];
+    input   reset,clk;
+    
+    output router_event_t router_event [P-1 : 0];
+    
+    router_config_t router_config_in;
+    always_comb begin
+        router_config_in.router_id= current_r_id [NRw-1 : 0];
+        router_config_in.router_addr=current_r_addr;
+    end
+    router_top #(
+        .ROUTER_ID(ROUTER_ID),
+        .P(P)
+    ) router (
+        .router_config_in(router_config_in),
+        .chan_in(chan_in),
+        .chan_out(chan_out),
+        .router_event(router_event),
+        .clk(clk),
+        .reset(reset)
+    );
+    
+    `ifdef SIMULATION
+    initial begin
+        if (current_r_addr==0) begin
+            display_noc_parameters();
+        end 
+    end
+    `endif
 endmodule
-
-
diff --git a/mpsoc/rtl/src_noc/router_two_stage.sv b/mpsoc/rtl/src_noc/router_two_stage.sv
index 6c36df6..8aeb1fa 100644
--- a/mpsoc/rtl/src_noc/router_two_stage.sv
+++ b/mpsoc/rtl/src_noc/router_two_stage.sv
@@ -3,767 +3,691 @@
 //`define MONITORE_PATH
 
 /***********************************************************************
- **	File: router.v
+ **    File: router.v
  **    
- **	Copyright (C) 2014-2017  Alireza Monemi
+ **    Copyright (C) 2014-2017  Alireza Monemi
  **    
- **	This file is part of ProNoC 
- **
- **	ProNoC ( stands for Prototype Network-on-chip)  is free software: 
- **	you can redistribute it and/or modify it under the terms of the GNU
- **	Lesser General Public License as published by the Free Software Foundation,
- **	either version 2 of the License, or (at your option) any later version.
- **
- ** 	ProNoC is distributed in the hope that it will be useful, but WITHOUT
- ** 	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
- ** 	or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
- ** 	Public License for more details.
- **
- ** 	You should have received a copy of the GNU Lesser General Public
- ** 	License along with ProNoC. If not, see <http:**www.gnu.org/licenses/>.
- **
- **
- **	Description: 
- **	A two stage router 
+ **    This file is part of ProNoC 
+ ** 
+ **    ProNoC ( stands for Prototype Network-on-chip)  is free software: 
+ **    you can redistribute it and/or modify it under the terms of the GNU
+ **    Lesser General Public License as published by the Free Software Foundation,
+ **    either version 2 of the License, or (at your option) any later version.
+ ** 
+ **     ProNoC is distributed in the hope that it will be useful, but WITHOUT
+ **     ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ **     or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
+ **     Public License for more details.
+ ** 
+ **     You should have received a copy of the GNU Lesser General Public
+ **     License along with ProNoC. If not, see <http:**www.gnu.org/licenses/>.
+ ** 
+ ** 
+ **    Description: 
+ **    A two stage router 
  **   stage1: lk-route,sw/VC allocation
  **   stage2: switch-traversal
  **************************************************************/
-
-
+    
 module router_two_stage #(
-	parameter NOC_ID=0,
-	parameter P=5
+    parameter ROUTER_ID=0,
+    parameter P=5
 ) (
-		current_r_id,
-		current_r_addr,// connected to constant parameter  
-		
-		chan_in,
-		chan_out,	
-		
-		ctrl_in,
-		ctrl_out,
-		
-		//internal router status 
-		ivc_info, 
-		ovc_info,
-		iport_info,
-		oport_info,
-		
-		smart_ctrl_in,
-		
-		clk,
-		reset
-
+        router_config_in,
+        
+        chan_in,
+        chan_out,
+        
+        ctrl_in,
+        ctrl_out,
+        
+        //internal router status 
+        ivc_info, 
+        ovc_info,
+        iport_info,
+        oport_info,
+        
+        smart_ctrl_in,
+        
+        clk,
+        reset
 );
- 
-	`NOC_CONF    
-                
-
-	// The current/neighbor routers addresses/port. These values are fixed in each router and they are supposed to be given as parameter. 
-	// However, in order to give an identical RTL code to each router, they are given as input ports. The identical RTL code reduces the
-	// compilation time. Note that they wont be implemented as  input ports in the final synthesized code. 
-
-	input [RAw-1 :  0]  current_r_addr;
-	input [31:0] current_r_id;
-	
-	input   flit_chanel_t chan_in  [P-1 : 0];
-	output  flit_chanel_t chan_out [P-1 : 0];
-	input   ctrl_chanel_t ctrl_in  [P-1 : 0];
-	output  ctrl_chanel_t ctrl_out [P-1 : 0];
-	input   clk,reset;
-	
-	
-	output  ivc_info_t 	 ivc_info    [P-1 : 0][V-1 : 0];
-	output  ovc_info_t   ovc_info    [P-1 : 0][V-1 : 0];
-	output  iport_info_t iport_info  [P-1 : 0];
-	output  oport_info_t oport_info  [P-1 : 0]; 
-	
-	input   smart_ctrl_t   smart_ctrl_in [P-1 : 0];
-	
-	
-	vsa_ctrl_t   vsa_ctrl    [P-1 : 0];   
-	
-	localparam
-		PV = V * P,
-		VV = V*V,
-		PVV = PV * V,    
-		P_1 = ( SELF_LOOP_EN=="NO")?  P-1 : P,
-		PP_1 = P_1 * P,
-		PVP_1 = PV * P_1,		  
-		PFw = P*Fw,
-		CONG_ALw = CONGw* P,    //  congestion width per router
-		W = WEIGHTw,
-		WP = W * P, 
-		WPP=  WP * P,
-		PRAw= P * RAw;     
-	
-	
-	flit_chanel_t chan_in_tmp  [P-1 : 0];
-	
     
-
-	wire  [PFw-1 :  0]  flit_in_all;
-	wire  [P-1 :  0]  flit_in_wr_all;
-	wire  [PV-1 :  0]  credit_out_all;
-	wire  [CONG_ALw-1 :  0]  congestion_in_all;
-    
-	wire  [PFw-1 :  0]  flit_out_all;
-	wire  [P-1 :  0]  flit_out_wr_all;
-	wire  [PV-1 :  0]  credit_in_all;
-	wire  [CONG_ALw-1 :  0]  congestion_out_all;
-    
-	wire  [PV-1 : 0] credit_release_out;
-	
-
-	// old router verilog code
-    
-	 
-	
-	//internal wires
-	wire  [PV-1 : 0] ovc_allocated_all;
-	wire  [PVV-1 : 0] granted_ovc_num_all;
-	wire  [PV-1 : 0] ivc_num_getting_sw_grant;
-	wire  [PV-1 : 0] ivc_num_getting_ovc_grant;
-	wire  [PVV-1 : 0] spec_ovc_num_all;
-	wire  [PV-1 : 0] nonspec_first_arbiter_granted_ivc_all;
-	wire  [PV-1 : 0] spec_first_arbiter_granted_ivc_all;
-	wire  [PP_1-1 : 0] nonspec_granted_dest_port_all;
-	wire  [PP_1-1 : 0] spec_granted_dest_port_all;    
-	wire  [PP_1-1 : 0] granted_dest_port_all;
-	wire  [P-1 : 0] any_ivc_sw_request_granted_all;
-	wire  [P-1 :  0] any_ovc_granted_in_outport_all;    
-	wire  [P-1 : 0] granted_dst_is_from_a_single_flit_pck;
-	// to vc/sw allocator
-	wire  [PVP_1-1 :  0] dest_port_all;
-	wire  [PV-1 : 0] ovc_is_assigned_all;
-	wire  [PV-1 : 0] ivc_request_all;
-	wire  [PV-1 : 0] assigned_ovc_not_full_all;
-	wire  [PVV-1: 0] masked_ovc_request_all;
-	
-	wire  [PV-1 : 0] vc_weight_is_consumed_all;
-	wire  [P-1  : 0] iport_weight_is_consumed_all;       
+    import pronoc_pkg::*;
+    import pronoc_pkg::*;
+    import pronoc_pkg::*;
+    import pronoc_pkg::*;
+    import pronoc_pkg::*;
+    
+    // The current/neighbor routers addresses/port. These values are fixed in each router and they are supposed to be given as parameter. 
+    // However, in order to give an identical RTL code to each router, they are given as input ports. The identical RTL code reduces the
+    // compilation time. Note that they wont be implemented as  input ports in the final synthesized code. 
+    
+    input router_config_t router_config_in;
+    
+    input   flit_chanel_t chan_in  [P-1 : 0];
+    output  flit_chanel_t chan_out [P-1 : 0];
+    input   ctrl_chanel_t ctrl_in  [P-1 : 0];
+    output  ctrl_chanel_t ctrl_out [P-1 : 0];
+    input   clk,reset;
+    
+    output  ivc_info_t   ivc_info    [P-1 : 0][V-1 : 0];
+    output  ovc_info_t   ovc_info    [P-1 : 0][V-1 : 0];
+    output  iport_info_t iport_info  [P-1 : 0];
+    output  oport_info_t oport_info  [P-1 : 0]; 
+    
+    input   smart_ctrl_t  smart_ctrl_in [P-1 : 0];
+    
+    vsa_ctrl_t vsa_ctrl [P-1 : 0];
+    
+    localparam
+        PV = V * P,
+        VV = V*V,
+        PVV = PV * V,    
+        P_1 = (SELF_LOOP_EN )?  P : P-1,
+        PP_1 = P_1 * P,
+        PVP_1 = PV * P_1,
+        PFw = P*Fw,
+        CONG_ALw = CONGw* P,    //  congestion width per router
+        W = WEIGHTw,
+        WP = W * P, 
+        WPP=  WP * P,
+        PRAw= P * RAw; 
+    
+    flit_chanel_t chan_in_tmp  [P-1 : 0];
+    
+    flit_t  flit_in_all [P-1 : 0];
+    wire  [P-1 :  0]  flit_in_wr_all;
+    wire  [PV-1 :  0]  credit_out_all;
+    wire  [CONG_ALw-1 :  0]  congestion_in_all;
+    
+    flit_t flit_out_all [P-1 : 0];
+    wire  [P-1 :  0]  flit_out_wr_all;
+    wire  [PV-1 :  0]  credit_in_all;
+    wire  [CONG_ALw-1 :  0]  congestion_out_all;
+    
+    wire  [PV-1 : 0] credit_release_out;
+    
+    // old router verilog code
+    
+    //internal wires
+    wire  [PV-1 : 0] ovc_allocated_all;
+    wire  [PVV-1 : 0] granted_ovc_num_all;
+    wire  [PV-1 : 0] ivc_num_getting_sw_grant;
+    wire  [PV-1 : 0] ivc_num_getting_ovc_grant;
+    wire  [PVV-1 : 0] spec_ovc_num_all;
+    wire  [PV-1 : 0] nonspec_first_arbiter_granted_ivc_all;
+    wire  [PP_1-1 : 0] nonspec_granted_dest_port_all;
+    wire  [PP_1-1 : 0] spec_granted_dest_port_all;    
+    wire  [PP_1-1 : 0] granted_dest_port_all;
+    wire  [P-1 : 0] any_ivc_sw_request_granted_all;
+    wire  [P-1 :  0] any_ovc_granted_in_outport_all;    
+    wire  [P-1 : 0] granted_dst_is_from_a_single_flit_pck;
+    
+    // to vc/sw allocator
+    wire  [PVP_1-1 :  0] dest_port_all;
+    wire  [PV-1 : 0] ovc_is_assigned_all;
+    wire  [PV-1 : 0] ivc_request_all;
+    wire  [PV-1 : 0] assigned_ovc_not_full_all;
+    wire  [PVV-1: 0] masked_ovc_request_all;
+    wire  [PV-1 : 0] vc_weight_is_consumed_all;
+    wire  [P-1  : 0] iport_weight_is_consumed_all;
     wire  [PV-1 : 0] vsa_ovc_released_all;  
     wire  [PV-1 : 0] vsa_credit_decreased_all;
     
-	// to/from the crossbar
-	wire  [PFw-1 : 0] iport_flit_out_all;
-	wire  [P-1 : 0] ssa_flit_wr_all;
-	logic [PP_1-1 : 0] granted_dest_port_all_delayed;
-	wire  [PFw-1 :  0]  crossbar_flit_out_all;
-	wire  [P-1   :  0]  crossbar_flit_out_wr_all;
-	wire  [PFw-1 :  0]  link_flit_out_all;
-	wire  [P-1   :  0]  link_flit_out_wr_all;
-	wire  [PV-1  :  0] flit_is_tail_all;
-
+    // to/from the crossbar
+    wire  [Fw-1 : 0] iport_flit_out_all [P-1:0];
+    wire  [P-1 : 0] ssa_flit_wr_all;
+    logic [P_1-1 : 0] granted_dest_port_all_delayed[P-1 : 0];
+    wire  [Fw-1 : 0]  crossbar_flit_out_all [P-1 :0];
+    wire  [P-1 :  0]  crossbar_flit_out_wr_all;
+    wire  [Fw-1 : 0]  link_flit_out_all [P-1 :0];
+    wire  [P-1 :  0]  link_flit_out_wr_all;
+    wire  [PV-1 : 0] flit_is_tail_all;
     
-	//to weight control
-	wire [WP-1 : 0] iport_weight_all;
-	wire [WPP-1: 0] oports_weight_all;
-	wire refresh_w_counter;
-	
-
-	//ctrl port
-	wire [PRAw-1  :  0] neighbors_r_addr;
-	wire [CRDTw-1 : 0 ] credit_init_val_in  [P-1 : 0][V-1 : 0];
-	wire [CRDTw-1 : 0 ] credit_init_val_out [P-1 : 0][V-1 : 0];
-	
-	
-	
-	
-	
-	
-	genvar i,j;
-	generate 		
-		for (i=0; i<P; i=i+1 ) begin :p_
-			
-			if(CAST_TYPE == "UNICAST") begin : uni 
-				assign chan_in_tmp[i] = chan_in[i];			
-			end else begin : multi
-				multicast_chan_in_process #(
-					.NOC_ID(NOC_ID),
-					.P(P), 
-					.SW_LOC  (i)
-				) multicast_process (
-					.endp_port       (ctrl_in[i].endp_port),
-					.current_r_addr  (current_r_addr ), 
-					.chan_in         (chan_in[i]     ), 
-					.chan_out        (chan_in_tmp[i] ),
-					.clk			 (clk)
-				);
-			
-			end	
-			
-			
-			assign  neighbors_r_addr  [(i+1)*RAw-1:  i*RAw] = ctrl_in[i].neighbors_r_addr;			
-			assign  flit_in_all       [(i+1)*Fw-1:  i*Fw] = chan_in_tmp[i].flit;
-			assign  flit_in_wr_all    [i] = chan_in_tmp[i].flit_wr;   
-			assign  credit_in_all     [(i+1)*V-1:  i*V] = chan_in_tmp[i].credit;
-			assign  congestion_in_all [(i+1)*CONGw-1:  i*CONGw] = chan_in_tmp[i].congestion; 
-			
-			assign  ctrl_out[i].neighbors_r_addr = current_r_addr;
-			assign  ctrl_out[i].endp_port =1'b0;
-			
-			
-			assign  chan_out[i].flit=          flit_out_all       [(i+1)*Fw-1:  i*Fw];       
-			assign  chan_out[i].flit_wr=       flit_out_wr_all    [i];                       
-			assign  chan_out[i].credit=        credit_out_all     [(i+1)*V-1:  i*V] | credit_release_out [(i+1)*V-1:  i*V];         
-			assign  chan_out[i].congestion=    congestion_out_all [(i+1)*CONGw-1:  i*CONGw];
-			
-			
-			assign  iport_info[i].swa_first_level_grant =nonspec_first_arbiter_granted_ivc_all[(i+1)*V-1:  i*V]; 
-			assign  iport_info[i].swa_grant = ivc_num_getting_sw_grant[(i+1)*V-1:  i*V]; 			
-			assign  iport_info[i].any_ivc_get_swa_grant=	any_ivc_sw_request_granted_all[i]; 
-			assign  iport_info[i].ivc_req = ivc_request_all [(i+1)*V-1:  i*V]; 
-			
-			assign  vsa_ctrl[i].ovc_is_allocated = ovc_allocated_all [(i+1)*V-1:  i*V];
-			assign  vsa_ctrl[i].ovc_is_released  = vsa_ovc_released_all[(i+1)*V-1:  i*V];
-			assign  vsa_ctrl[i].ivc_num_getting_sw_grant = ivc_num_getting_sw_grant [(i+1)*V-1:  i*V];
-			assign  vsa_ctrl[i].ivc_num_getting_ovc_grant=ivc_num_getting_ovc_grant [(i+1)*V-1:  i*V];
-			assign  vsa_ctrl[i].ivc_reset=flit_is_tail_all[(i+1)*V-1:  i*V] & ivc_num_getting_sw_grant[(i+1)*V-1:  i*V];
-			assign  vsa_ctrl[i].buff_space_decreased =  vsa_credit_decreased_all[(i+1)*V-1:  i*V]; 
-			assign  vsa_ctrl[i].ivc_granted_ovc_num = granted_ovc_num_all[(i+1)*VV-1:  i*VV];
-			
-			if(SELF_LOOP_EN == "NO") begin :nslp
-				add_sw_loc_one_hot #(
-						.P(P),
-						.SW_LOC(i)    
-					)add
-					(
-						.destport_in(granted_dest_port_all[(i+1)*P_1-1:  i*P_1]),
-						.destport_out(iport_info[i].granted_oport_one_hot[P-1 : 0])
-					);	
-			end else begin :slp
-				assign iport_info[i].granted_oport_one_hot[P-1 : 0] = granted_dest_port_all[(i+1)*P_1-1:  i*P_1];
-			end
-			
-			for (j=0;j<V;j++)begin :V_
-				
-				//credit_release. Only activated for local ports as credit_release_en never be asserted in router to router connection.  
-				credit_release_gen #(
-					.NOC_ID(NOC_ID),
-					.CREDIT_NUM  (LB)
-				) credit_release_gen (
-					.clk         (clk        ), 
-					.reset       (reset      ), 
-					.en          (ctrl_in[i].credit_release_en[j] ), 
-					.credit_out  (credit_release_out[i*V+j] )
-				);
-				
-				
-				assign ctrl_out[i].credit_release_en[j] =1'b0;
-				assign credit_init_val_in[i][j]       = ctrl_in[i].credit_init_val[j];
-				assign ctrl_out[i].credit_init_val[j] = credit_init_val_out [i][j];		
-				
-				
-				
-				
-			end
-			
-			
-			
-		end		
-	endgenerate
-	
-	
-	
+    //to weight control
+    wire [WP-1 : 0] iport_weight_all;
+    wire [WPP-1: 0] oports_weight_all;
+    wire refresh_w_counter;
+    
+    //ctrl port
+    wire [PRAw-1  :  0] neighbors_r_addr;
+    wire [CRDTw-1 : 0 ] credit_init_val_in  [P-1 : 0][V-1 : 0];
+    wire [CRDTw-1 : 0 ] credit_init_val_out [P-1 : 0][V-1 : 0];    
+    logic [31:0] current_r_id;
+    logic [RAw-1 :  0]  current_r_addr;
+    router_info_t router_info,router_info_next;
+    wire [P-1 : 0] granted_oport_one_hot [P-1 : 0];
+    wire [EAw-1 : 0] endp_addrs [NE_PER_R-1 : 0];
+    
+    function automatic int get_enp_num(input int i);
+        if(IS_1D_TOPO) begin
+            return (i > BACKWARD) ? i - BACKWARD : LOCAL;
+        end else if(IS_2D_TOPO) begin
+            return (i > SOUTH) ? i - SOUTH : LOCAL;
+        end else if(IS_3D_TOPO) begin
+            return (i > DOWN) ? i - DOWN : LOCAL;
+        end else return 0; //TODO complete it for fattree and bin tree
+    endfunction
+    
+    always_comb begin 
+        current_r_addr = router_config_in.router_addr;
+        current_r_id = 0;
+        current_r_id [NRw-1 : 0] = router_config_in.router_id;
+    end
+    
+    //To avoid false loopback reports in Verilator
+    always_ff @ (`pronoc_clk_reset_edge) begin
+        if (`pronoc_reset) begin
+            router_info <= '0;  
+        end else begin
+            router_info <= router_info_next;
+        end
+    end
+    
+    always_comb begin 
+        router_info_next.router_id=current_r_id;
+        router_info_next.router_addr=current_r_addr;
+        router_info_next.neighbors_r_addr[PRAw-1  :  0] = neighbors_r_addr;
+        for (int port=0; port<P; port++ ) begin 
+            ctrl_out[port].router_addr = current_r_addr;
+            ctrl_out[port].endp_port =1'b0; 
+            ctrl_out[port].hetero_ovc_presence= hetero_ovc_unary(current_r_id,port);
+            ctrl_out[port].endp_addr = endp_addrs[get_enp_num(port)];
+            for (int vc=0;vc<V;vc++)begin 
+                ctrl_out[port].credit_init_val[vc] = credit_init_val_out [port][vc];
+                ctrl_out[port].credit_release_en[vc] = 1'b0; 
+            end
+        end
+    end 
+    
+    genvar i,j;
+    generate
+        for (i=0; i<NE_PER_R; i=i+1 ) begin :Endp_
+            assign endp_addrs[i] = router_config_in.endp_addrs[ (i+1)*EAw-1 : i*EAw];
+        end
+        for (i=0; i<P; i=i+1 ) begin :p_
+            always_ff @ (`pronoc_clk_reset_edge) begin
+                if (`pronoc_reset) begin
+                    granted_dest_port_all_delayed[i] <= '0; // reset to zero vector of width PP_1
+                end else begin
+                    granted_dest_port_all_delayed[i] <= granted_dest_port_all [ (i+1)*P_1-1 : i*P_1];
+                end
+            end
             
-	inout_ports #(		
-		.NOC_ID(NOC_ID),
-		.P(P)
-	) the_inout_ports (
-		.current_r_addr(current_r_addr),
-		.neighbors_r_addr(neighbors_r_addr),
-		.flit_in_all(flit_in_all),
-		.flit_in_wr_all(flit_in_wr_all),
-		.credit_out_all(credit_out_all),
-		.credit_in_all(credit_in_all),
-		.masked_ovc_request_all(masked_ovc_request_all),			
-		.granted_dst_is_from_a_single_flit_pck(granted_dst_is_from_a_single_flit_pck),
-		.vsa_ovc_allocated_all(ovc_allocated_all), 
-		.granted_ovc_num_all(granted_ovc_num_all), 
-		.ivc_num_getting_ovc_grant(ivc_num_getting_ovc_grant), 
-		.spec_ovc_num_all(spec_ovc_num_all), 
-		.nonspec_first_arbiter_granted_ivc_all(nonspec_first_arbiter_granted_ivc_all), 
-		.spec_first_arbiter_granted_ivc_all(spec_first_arbiter_granted_ivc_all), 
-		.nonspec_granted_dest_port_all(nonspec_granted_dest_port_all), 
-		.spec_granted_dest_port_all(spec_granted_dest_port_all), 
-		.granted_dest_port_all(granted_dest_port_all), 
-		.any_ivc_sw_request_granted_all(any_ivc_sw_request_granted_all), 
-		.any_ovc_granted_in_outport_all(any_ovc_granted_in_outport_all),
-		.dest_port_all(dest_port_all), 
-		.ovc_is_assigned_all(ovc_is_assigned_all), 
-		.ivc_request_all(ivc_request_all), 
-		.assigned_ovc_not_full_all(assigned_ovc_not_full_all), 
-		.flit_out_all(iport_flit_out_all),
-		.congestion_in_all(congestion_in_all),
-		.congestion_out_all(congestion_out_all),
-		//  .lk_destination_all(lk_destination_all),
-		.ssa_flit_wr_all(ssa_flit_wr_all),
-		.iport_weight_all(iport_weight_all),
-		.oports_weight_all(oports_weight_all),
-		.vc_weight_is_consumed_all(vc_weight_is_consumed_all),
-		.iport_weight_is_consumed_all(iport_weight_is_consumed_all), 
-		.refresh_w_counter(refresh_w_counter), 
-		.clk(clk), 
-		.reset(reset),
-		.ivc_info(ivc_info),
-		.ovc_info(ovc_info),
-		.oport_info(oport_info),
-		.smart_ctrl_in(smart_ctrl_in),
-		.vsa_ctrl_in(vsa_ctrl),
-		.credit_init_val_in (credit_init_val_in),
-		.credit_init_val_out (credit_init_val_out),
-		.flit_is_tail_all(flit_is_tail_all),			
-		.crossbar_flit_out_wr_all(crossbar_flit_out_wr_all),
-		.vsa_ovc_released_all(vsa_ovc_released_all),
-		.vsa_credit_decreased_all(vsa_credit_decreased_all)
-	);
-
-
-	combined_vc_sw_alloc #(
-		.NOC_ID(NOC_ID),
-		.P(P)			
-	) vsa (
-		.dest_port_all(dest_port_all), 
-		.masked_ovc_request_all(masked_ovc_request_all),			
-		.granted_dst_is_from_a_single_flit_pck(granted_dst_is_from_a_single_flit_pck),
-		.ovc_allocated_all(ovc_allocated_all), 
-		.granted_ovc_num_all(granted_ovc_num_all), 
-		.ivc_num_getting_ovc_grant(ivc_num_getting_ovc_grant), 
-		.ivc_num_getting_sw_grant(ivc_num_getting_sw_grant), 
-		.spec_first_arbiter_granted_ivc_all(spec_first_arbiter_granted_ivc_all), 
-		.nonspec_first_arbiter_granted_ivc_all(nonspec_first_arbiter_granted_ivc_all), 
-		.nonspec_granted_dest_port_all(nonspec_granted_dest_port_all), 
-		.spec_granted_dest_port_all(spec_granted_dest_port_all), 
-		.granted_dest_port_all(granted_dest_port_all), 
-		.any_ivc_sw_request_granted_all(any_ivc_sw_request_granted_all), 
-		.any_ovc_granted_in_outport_all(any_ovc_granted_in_outport_all),
-		.spec_ovc_num_all(spec_ovc_num_all),       
-		// .lk_destination_all(lk_destination_all),  
-		.vc_weight_is_consumed_all(vc_weight_is_consumed_all),  
-		.iport_weight_is_consumed_all(iport_weight_is_consumed_all),  
-		.ivc_info(ivc_info),
-		.clk(clk), 
-		.reset(reset)
-	);
-        
-	pronoc_register #(.W(PP_1)) reg2 (.in(granted_dest_port_all ), .out(granted_dest_port_all_delayed), .reset(reset), .clk(clk));
-	
-	    
-		crossbar #(	
-				.NOC_ID(NOC_ID),			
-				.TOPOLOGY(TOPOLOGY),
-				.V (V),     // vc_num_per_port
-				.P (P),     // router port num
-				.Fw (Fw),
-				.MUX_TYPE (MUX_TYPE),				
-				.SSA_EN (SSA_EN),
-				.SELF_LOOP_EN(SELF_LOOP_EN)				
-			)
-			the_crossbar
-			(
-				.granted_dest_port_all (granted_dest_port_all_delayed),
-				.flit_in_all (iport_flit_out_all),				
-				.ssa_flit_wr_all (ssa_flit_wr_all),
-				.flit_out_all (crossbar_flit_out_all),				
-				.flit_out_wr_all (crossbar_flit_out_wr_all)        
-			);    
-     
-		//link reg 
-		generate 
-		//if( ADD_PIPREG_AFTER_CROSSBAR == 1 || SMART_EN == 1) begin :link_reg
-		if( ADD_PIPREG_AFTER_CROSSBAR == 1 ) begin :link_reg
+            if(IS_UNICAST & (IS_LOOKAHEAD | IS_MULTI_MESH)) begin : lk_dp_route
+                // we are using lookahead routing or depth-first (DP) routing. So, the destination
+                // port is already computed in the previous router (computed externally in the
+                // same router for DP) and is available in the lookahead routing field of the flit
+                // (destport field for DP).
+                assign chan_in_tmp[i] = chan_in[i];                
+            end else begin : conv_route
+                local_route_computation #(
+                    .P(P),
+                    .SW_LOC(i)
+                ) conv_route (
+                    .endp_port(ctrl_in[i].endp_port),
+                    .current_r_addr(current_r_addr),
+                    .chan_in(chan_in[i]),
+                    .chan_out(chan_in_tmp[i]),
+                    .clk(clk),
+                    .reset(reset)
+                );
+            end
+            if(SELF_LOOP_EN == 0) begin :nslp
+                add_sw_loc_one_hot #(
+                    .P(P),
+                    .SW_LOC(i)
+                )add(
+                    .destport_in(granted_dest_port_all[(i+1)*P_1-1:  i*P_1]),
+                    .destport_out(granted_oport_one_hot[i])
+                );
+            end else begin :slp
+                assign granted_oport_one_hot[i] = granted_dest_port_all[(i+1)*P_1-1:  i*P_1];
+            end
             
-                
-			reg [PFw-1 : 0] flit_out_all_pipe;
-			reg [P-1 : 0] flit_out_wr_all_pipe;
-			
-			pronoc_register #(.W(PFw)) reg1 (.in(crossbar_flit_out_all    ), .out(flit_out_all_pipe), .reset(reset), .clk(clk));
-			pronoc_register #(.W(P)  ) reg2 (.in(crossbar_flit_out_wr_all ), .out(flit_out_wr_all_pipe), .reset(reset), .clk(clk));
-					
+            assign  neighbors_r_addr  [(i+1)*RAw-1:  i*RAw] = ctrl_in[i].router_addr;
+            assign  flit_in_all       [i] = chan_in_tmp[i].flit;
+            assign  flit_in_wr_all    [i] = chan_in_tmp[i].flit_wr;
+            assign  credit_in_all     [(i+1)*V-1:  i*V] = chan_in_tmp[i].credit;
+            assign  congestion_in_all [(i+1)*CONGw-1:  i*CONGw] = chan_in_tmp[i].congestion; 
             
-			assign link_flit_out_all    = flit_out_all_pipe;
-			assign link_flit_out_wr_all = flit_out_wr_all_pipe;       
+            assign  chan_out[i].flit=          flit_out_all       [i];
+            assign  chan_out[i].flit_wr=       flit_out_wr_all    [i];
+            assign  chan_out[i].credit=        credit_out_all     [(i+1)*V-1:  i*V] | credit_release_out [(i+1)*V-1:  i*V];         
+            assign  chan_out[i].congestion=    congestion_out_all [(i+1)*CONGw-1:  i*CONGw];
             
-         
-		end else begin :no_link_reg    
+            assign  iport_info[i].swa_first_level_grant =nonspec_first_arbiter_granted_ivc_all[(i+1)*V-1:  i*V]; 
+            assign  iport_info[i].swa_grant = ivc_num_getting_sw_grant[(i+1)*V-1:  i*V];
+            assign  iport_info[i].any_ivc_get_swa_grant=    any_ivc_sw_request_granted_all[i]; 
+            assign  iport_info[i].ivc_req = ivc_request_all [(i+1)*V-1:  i*V]; 
+            assign  iport_info[i].granted_oport_one_hot [P-1:0] = granted_oport_one_hot[i];
             
-			assign    link_flit_out_all     =   crossbar_flit_out_all;
-			assign    link_flit_out_wr_all  =   crossbar_flit_out_wr_all;
-           
-		end       
-        
-	
-		/* verilator lint_off WIDTH */ 
-		if (SWA_ARBITER_TYPE != "RRA" ) begin : wrra_ 
-		/* verilator lint_on WIDTH */ 
-   
-			wire [WP-1 : 0] contention_all;
-			wire [WP-1 : 0] limited_oport_weight_all;
-   
-			wrra_contention_gen #(
-				.WEIGHTw(WEIGHTw),
-				.WRRA_CONFIG_INDEX(WRRA_CONFIG_INDEX),
-				.V(V),
-				.P(P),
-				.SELF_LOOP_EN(SELF_LOOP_EN)
-			)
-			contention_gen
-			(
-				.limited_oport_weight_all(limited_oport_weight_all),
-				.dest_port_all(dest_port_all),
-				.ivc_request_all(ivc_request_all),
-				.ovc_is_assigned_all(ovc_is_assigned_all), 
-				.contention_all(contention_all),
-				.iport_weight_all(iport_weight_all),
-				.oports_weight_all(oports_weight_all)
+            assign  vsa_ctrl[i].ovc_is_allocated = ovc_allocated_all [(i+1)*V-1:  i*V];
+            assign  vsa_ctrl[i].ovc_is_released  = vsa_ovc_released_all[(i+1)*V-1:  i*V];
+            assign  vsa_ctrl[i].ivc_num_getting_sw_grant = ivc_num_getting_sw_grant [(i+1)*V-1:  i*V];
+            assign  vsa_ctrl[i].ivc_num_getting_ovc_grant=ivc_num_getting_ovc_grant [(i+1)*V-1:  i*V];
+            assign  vsa_ctrl[i].ivc_reset=flit_is_tail_all[(i+1)*V-1:  i*V] & ivc_num_getting_sw_grant[(i+1)*V-1:  i*V];
+            assign  vsa_ctrl[i].buff_space_decreased =  vsa_credit_decreased_all[(i+1)*V-1:  i*V]; 
+            assign  vsa_ctrl[i].ivc_granted_ovc_num = granted_ovc_num_all[(i+1)*VV-1:  i*VV];
             
-			); 
+            for (j=0;j<V;j++)begin :V_
+                //credit_release. Only activated for local ports as credit_release_en never be asserted in router to router connection.  
+                credit_release_gen #(
+                    .CREDIT_NUM(LB)
+                ) credit_release_gen (
+                    .clk(clk), 
+                    .reset(reset), 
+                    .en (ctrl_in[i].credit_release_en[j]), 
+                    .credit_out(credit_release_out[i*V+j])
+                );
+                assign credit_init_val_in[i][j]  = ctrl_in[i].credit_init_val[j];
+            end
+        end
+    endgenerate
+    
+    inout_ports #(
+        .ROUTER_ID(ROUTER_ID),
+        .P(P)
+    ) the_inout_ports (
+        .router_info(router_info),
+        .flit_in_all(flit_in_all),
+        .flit_in_wr_all(flit_in_wr_all),
+        .credit_out_all(credit_out_all),
+        .credit_in_all(credit_in_all),
+        .masked_ovc_request_all(masked_ovc_request_all),
+        .granted_dst_is_from_a_single_flit_pck(granted_dst_is_from_a_single_flit_pck),
+        .vsa_ovc_allocated_all(ovc_allocated_all), 
+        .granted_ovc_num_all(granted_ovc_num_all), 
+        .ivc_num_getting_ovc_grant(ivc_num_getting_ovc_grant), 
+        .spec_ovc_num_all(spec_ovc_num_all), 
+        .nonspec_first_arbiter_granted_ivc_all(nonspec_first_arbiter_granted_ivc_all), 
+        .nonspec_granted_dest_port_all(nonspec_granted_dest_port_all), 
+        .spec_granted_dest_port_all(spec_granted_dest_port_all), 
+        .granted_dest_port_all(granted_dest_port_all), 
+        .any_ivc_sw_request_granted_all(any_ivc_sw_request_granted_all), 
+        .any_ovc_granted_in_outport_all(any_ovc_granted_in_outport_all),
+        .dest_port_all(dest_port_all), 
+        .ovc_is_assigned_all(ovc_is_assigned_all), 
+        .ivc_request_all(ivc_request_all), 
+        .assigned_ovc_not_full_all(assigned_ovc_not_full_all), 
+        .flit_out_all(iport_flit_out_all),
+        .congestion_in_all(congestion_in_all),
+        .congestion_out_all(congestion_out_all),
+        //  .lk_destination_all(lk_destination_all),
+        .ssa_flit_wr_all(ssa_flit_wr_all),
+        .iport_weight_all(iport_weight_all),
+        .oports_weight_all(oports_weight_all),
+        .vc_weight_is_consumed_all(vc_weight_is_consumed_all),
+        .iport_weight_is_consumed_all(iport_weight_is_consumed_all), 
+        .refresh_w_counter(refresh_w_counter), 
+        .clk(clk), 
+        .reset(reset),
+        .ivc_info(ivc_info),
+        .ovc_info(ovc_info),
+        .oport_info(oport_info),
+        .smart_ctrl_in(smart_ctrl_in),
+        .ctrl_in(ctrl_in),
+        .vsa_ctrl_in(vsa_ctrl),
+        .credit_init_val_in (credit_init_val_in),
+        .credit_init_val_out (credit_init_val_out),
+        .flit_is_tail_all(flit_is_tail_all),
+        .vsa_ovc_released_all(vsa_ovc_released_all),
+        .vsa_credit_decreased_all(vsa_credit_decreased_all)
+    );
+    
+    combined_vc_sw_alloc #(
+        .P(P)
+    ) vsa (
+        .dest_port_all(dest_port_all), 
+        .masked_ovc_request_all(masked_ovc_request_all),            
+        .granted_dst_is_from_a_single_flit_pck(granted_dst_is_from_a_single_flit_pck),
+        .ovc_allocated_all(ovc_allocated_all), 
+        .granted_ovc_num_all(granted_ovc_num_all), 
+        .ivc_num_getting_ovc_grant(ivc_num_getting_ovc_grant), 
+        .ivc_num_getting_sw_grant(ivc_num_getting_sw_grant), 
+        .nonspec_first_arbiter_granted_ivc_all(nonspec_first_arbiter_granted_ivc_all), 
+        .nonspec_granted_dest_port_all(nonspec_granted_dest_port_all), 
+        .spec_granted_dest_port_all(spec_granted_dest_port_all), 
+        .granted_dest_port_all(granted_dest_port_all), 
+        .any_ivc_sw_request_granted_all(any_ivc_sw_request_granted_all), 
+        .any_ovc_granted_in_outport_all(any_ovc_granted_in_outport_all),
+        .spec_ovc_num_all(spec_ovc_num_all),
+        // .lk_destination_all(lk_destination_all),
+        .vc_weight_is_consumed_all(vc_weight_is_consumed_all),  
+        .iport_weight_is_consumed_all(iport_weight_is_consumed_all),  
+        .ivc_info(ivc_info),
+        .clk(clk), 
+        .reset(reset)
+    );
+    
+    
+    crossbar #(
+        .P (P) // router port num
+    ) the_crossbar (
+        .granted_dest_port_all (granted_dest_port_all_delayed),
+        .flit_in_all (iport_flit_out_all),
+        .ssa_flit_wr_all (ssa_flit_wr_all),
+        .flit_out_all (crossbar_flit_out_all),
+        .flit_out_wr_all (crossbar_flit_out_wr_all)
+    );
+    
+    //link reg 
+    generate 
+    if( ADD_PIPREG_AFTER_CROSSBAR == 1 ) begin :link_reg
+        reg [Fw-1 : 0] flit_out_all_pipe [P-1 : 0];
+        reg [P-1 : 0] flit_out_wr_all_pipe;
+        always_ff @ (`pronoc_clk_reset_edge) begin
+            if (`pronoc_reset) begin
+                flit_out_all_pipe    <= '0;
+                flit_out_wr_all_pipe <= '0;
+            end else begin
+                flit_out_all_pipe    <= crossbar_flit_out_all;
+                flit_out_wr_all_pipe <= crossbar_flit_out_wr_all;
+            end
+        end
+        assign link_flit_out_all    = flit_out_all_pipe;
+        assign link_flit_out_wr_all = flit_out_wr_all_pipe;
+        
+    end else begin :no_link_reg
         
-			weights_update #(
-				.NOC_ID(NOC_ID),
-				.ARBITER_TYPE(SWA_ARBITER_TYPE),
-				.V(V),
-				.P(P),
-				.Fw(Fw),
-				.WEIGHTw(WEIGHTw),
-				.WRRA_CONFIG_INDEX(WRRA_CONFIG_INDEX),
-				.C(C),
-				.TOPOLOGY(TOPOLOGY),
-				.EAw(EAw),
-				.DSTPw(DSTPw),
-				.ADD_PIPREG_AFTER_CROSSBAR(ADD_PIPREG_AFTER_CROSSBAR)
-        	
-			)
-			updater
-			(
-				.limited_oports_weight(limited_oport_weight_all),
-				.refresh_w_counter(refresh_w_counter),
-				.iport_weight_all(iport_weight_all),
-				.contention_all(contention_all),
-				.flit_in_all(link_flit_out_all),
-				.flit_out_all(flit_out_all),
-				.flit_out_wr_all(flit_out_wr_all),
-				.clk(clk),
-				.reset(reset)
-			);        
-         
-	end // WRRA
-	else begin : rra_    
-		assign flit_out_all  =  link_flit_out_all;   
-		assign refresh_w_counter = 1'b0;
-	end		
-	endgenerate 
-		assign  flit_out_wr_all = link_flit_out_wr_all;
-		
-       
-		//synthesis translate_off 
-		//synopsys  translate_off
-		generate 
-		/* verilator lint_off WIDTH */ 
-		if(DEBUG_EN && TOPOLOGY == "MESH")begin :dbg
-		/* verilator lint_on WIDTH */ 
-		debug_mesh_edges #(
-			.T1(T1),
-			.T2(T2),
-			.T3(T3),
-			.T4(T4),
-			.RAw(RAw),
-			.P(P)
-		)
-		debug_edges
-		(
-			.clk(clk),
-			.current_r_addr(current_r_addr),
-			.flit_out_wr_all(flit_out_wr_all)
-		);
-	end// DEBUG
-		endgenerate 
-		// synopsys  translate_on  
-		// synthesis translate_on
-      
-    
-    
-		// for testing the route path
+        assign    link_flit_out_all     =   crossbar_flit_out_all;
+        assign    link_flit_out_wr_all  =   crossbar_flit_out_wr_all;
+    end        
+        
+    /* verilator lint_off WIDTH */ 
+    if (SWA_ARBITER_TYPE != "RRA" ) begin : wrra_ 
+    /* verilator lint_on WIDTH */ 
+        
+        wire [WP-1 : 0] contention_all;
+        wire [WP-1 : 0] limited_oport_weight_all;
+        
+        wrra_contention_gen #(
+            .WEIGHTw(WEIGHTw),
+            .WRRA_CONFIG_INDEX(WRRA_CONFIG_INDEX),
+            .V(V),
+            .P(P),
+            .SELF_LOOP_EN(SELF_LOOP_EN)
+        ) contention_gen (
+            .limited_oport_weight_all(limited_oport_weight_all),
+            .dest_port_all(dest_port_all),
+            .ivc_request_all(ivc_request_all),
+            .ovc_is_assigned_all(ovc_is_assigned_all), 
+            .contention_all(contention_all),
+            .iport_weight_all(iport_weight_all),
+            .oports_weight_all(oports_weight_all)
+        ); 
+        
+        weights_update #(
+            .ARBITER_TYPE(SWA_ARBITER_TYPE),
+            .V(V),
+            .P(P),
+            .Fw(Fw),
+            .WEIGHTw(WEIGHTw),
+            .WRRA_CONFIG_INDEX(WRRA_CONFIG_INDEX),
+            .C(C),
+            .TOPOLOGY(TOPOLOGY),
+            .EAw(EAw),
+            .DSTPw(DSTPw),
+            .ADD_PIPREG_AFTER_CROSSBAR(ADD_PIPREG_AFTER_CROSSBAR)
+        )
+        updater
+        (
+            .limited_oports_weight(limited_oport_weight_all),
+            .refresh_w_counter(refresh_w_counter),
+            .iport_weight_all(iport_weight_all),
+            .contention_all(contention_all),
+            .flit_in_all(link_flit_out_all),
+            .flit_out_all(flit_out_all),
+            .flit_out_wr_all(flit_out_wr_all),
+            .clk(clk),
+            .reset(reset)
+        );        
+    end // WRRA
+    else begin : rra_    
+        assign flit_out_all  =  link_flit_out_all;
+        assign refresh_w_counter = 1'b0;
+    end
+    endgenerate 
     
-
-   
-		// synthesis translate_off
-		// synopsys  translate_off                                  
-		`ifdef MONITORE_PATH
-     
-			
-		reg[P-1 :0] t1,t2;
-		generate
-			for (i=0;i<P;i=i+1)begin : lp                     
-    
-   
-				always @(posedge clk) begin
-					if(`pronoc_reset)begin 
-						t1[i]<=1'b0;
-						t2[i]<=1'b0;             
-					end else begin 
-						if(flit_out_wr_all[i]>0 && t2[i]==0)begin 
-							$display("%t :Out router (id=%d, addr=%h, port=%d), flitout=%h",$time,current_r_id,current_r_addr,i,flit_out_all[(i+1)*Fw-1 : i*Fw]);
-							t2[i]<=1;
-						end
-						
-						if(flit_in_wr_all[i]>0 && t1[i]==0)begin 
-							$display("%t :In router (id=%d, addr=%h, port=%d), flitin=%h",$time,current_r_id,current_r_addr,i,flit_in_all[(i+1)*Fw-1 : i*Fw]);
-							t1[i]<=1;
-						end
-						
-            
-            
-					end
-				end
-			end
-		endgenerate
-	`endif
-   
-   
-   
-	/*
-
-
-
+    assign  flit_out_wr_all = link_flit_out_wr_all;
+    
+/*********************************************
+*
+*        Validating Parameters/Simulation
+*
+*********************************************/
+    
+`ifdef SIMULATION
+    generate 
+    if(DEBUG_EN & IS_MESH)begin :dbg
+        debug_mesh_edges #(
+            .P(P)
+        ) debug_edges (
+            .clk(clk),
+            .current_r_addr(current_r_addr),
+            .flit_out_wr_all(flit_out_wr_all)
+        );
+    end// DEBUG  
+    
+    // for testing the route path
+    `ifdef MONITORE_PATH    
+    reg[P-1 :0] t1,t2;    
+    for (i=0;i<P;i=i+1)begin : lp  
+        always @(posedge clk) begin
+            if(`pronoc_reset)begin 
+                t1[i]<=1'b0;
+                t2[i]<=1'b0;
+            end else begin 
+                if(flit_out_wr_all[i]>0 && t2[i]==0)begin 
+                    $display("%t :Out router (id=%d, addr=%h, port=%d), flitout=%h",$time,current_r_id,current_r_addr,i,flit_out_all[(i+1)*Fw-1 : i*Fw]);
+                    t2[i]<=1;
+                end
+                
+                if(flit_in_wr_all[i]>0 && t1[i]==0)begin 
+                    $display("%t :In router (id=%d, addr=%h, port=%d), flitin=%h",$time,current_r_id,current_r_addr,i,flit_in_all[(i+1)*Fw-1 : i*Fw]);
+                    t1[i]<=1;
+                end
+            end
+        end //always
+    end //for
+    `endif //MONITORE_PATH 
+    endgenerate
+    /*
     reg [10 :  0]  counter;
     reg [31 :  0]  flit_counter;
     
     always @ (`pronoc_clk_reset_edge )begin 
-		if(`pronoc_reset) begin 
+        if(`pronoc_reset) begin 
             flit_counter <=0;
             counter <= 0;
         end else begin 
             if(flit_in_wr_all>0 )begin 
                 counter <=0;
                 flit_counter<=flit_counter+1'b1;
-                          
             end else begin 
                 counter <= counter+1'b1;
                 if( counter == 512 ) $display("%t : total flits received in (x=%d,Y=%d) is %d ",$time,current_r_addr,current_y,flit_counter);
             end
         end
     end
-	 */
-
-
-//TRACE_DUMP_PER is defined in pronoc_def file
- 
- 
+     */
+    
+    
+//TRACE_DUMP_PER_[NOC/ROUTER/PORT] macro definition should be in pronoc_def.v file
+    
+    
 `ifdef TRACE_DUMP_PER_NoC
-	pronoc_trace_dump #(
-		.NOC_ID(NOC_ID),
-		.P(P),
-		.TRACE_DUMP_PER("NOC"), //NOC, ROUTER, PORT 
-		.CYCLE_REPORT(0) // 1 : enable, 0 : disable
-	
-	)dump1
-	(
-		.current_r_id(current_r_id),
-		.chan_in(chan_in),
-		.chan_out(chan_out),
-		.clk(clk)
-	);
-`endif	
+    pronoc_trace_dump #(
+        .P(P),
+        .TRACE_DUMP_PER("NOC"), //NOC, ROUTER, PORT 
+        .CYCLE_REPORT(0) // 1 : enable, 0 : disable    
+    ) dump1 (
+        .current_r_id(current_r_id),
+        .chan_in(chan_in),
+        .chan_out(chan_out),
+        .clk(clk)
+    );
+`endif    
 `ifdef TRACE_DUMP_PER_ROUTER
-	pronoc_trace_dump #(
-		.NOC_ID(NOC_ID),
-		.P(P),
-		.TRACE_DUMP_PER("ROUTER"), //NOC, ROUTER, PORT 
-		.CYCLE_REPORT(0) // 1 : enable, 0 : disable
-	
-	)dump2
-	(
-		.current_r_id(current_r_id),
-		.chan_in(chan_in),
-		.chan_out(chan_out),
-		.clk(clk)
-	);
-`endif	
+    pronoc_trace_dump #(
+        .P(P),
+        .TRACE_DUMP_PER("ROUTER"), //NOC, ROUTER, PORT 
+        .CYCLE_REPORT(0) // 1 : enable, 0 : disable    
+    ) dump2 (
+        .current_r_id(current_r_id),
+        .chan_in(chan_in),
+        .chan_out(chan_out),
+        .clk(clk)
+    );
+`endif    
 `ifdef TRACE_DUMP_PER_PORT
-	pronoc_trace_dump #(
-		.NOC_ID(NOC_ID),
-		.P(P),
-		.TRACE_DUMP_PER("PORT"), //NOC, ROUTER, PORT 
-		.CYCLE_REPORT(0) // 1 : enable, 0 : disable
-	
-	)dump3
-	(
-		.current_r_id(current_r_id),
-		.chan_in(chan_in),
-		.chan_out(chan_out),
-		.clk(clk)
-	);
-`endif	
-
-
-
-
-	//synopsys  translate_on
-	//synthesis translate_on 
-
+    pronoc_trace_dump #(
+        .P(P),
+        .TRACE_DUMP_PER("PORT"), //NOC, ROUTER, PORT 
+        .CYCLE_REPORT(0) // 1 : enable, 0 : disable    
+    )dump3 (
+        .current_r_id(current_r_id),
+        .chan_in(chan_in),
+        .chan_out(chan_out),
+        .clk(clk)
+    );
+`endif
+`endif //SIMULATION
 
 endmodule
 
 
-
-
-
-module credit_release_gen #(
-	parameter NOC_ID=0,
-	parameter CREDIT_NUM=4
-)
-(
-	clk,
-	reset,
-	en,
-	credit_out		
-);
-	
-	`NOC_CONF
-	
-	input  clk,	reset;
-	input  en;
-	output reg credit_out;		
-	
-	localparam W=log2(CREDIT_NUM +1);
-	
-	reg [W-1 : 0] counter;
-	wire counter_is_zero = counter=={W{1'b0}};	
-	wire counter_is_max = counter==CREDIT_NUM;
-	wire counter_incr = (en & counter_is_zero ) | (~counter_is_zero & ~counter_is_max);
-	
-	
-	
-			
-	always @ (`pronoc_clk_reset_edge )begin 
-		if(`pronoc_reset) begin 
-			counter <= {W{1'b0}};	
-			credit_out<=1'b0;
-		end else begin 
-			if(counter_incr) begin 
-				counter<= counter +1'b1;
-				credit_out<=1'b1;
-			end else begin 
-				credit_out<=1'b0;				
-			end
-		end
-	end
-			
-	
-endmodule
-
-
-
-
-//synthesis translate_off
+`ifdef SIMULATION
 module pronoc_trace_dump #(
-	parameter NOC_ID=0,
-	parameter P = 6,
-	parameter TRACE_DUMP_PER= "ROUTER", //NOC, ROUTER, PORT 
-	parameter CYCLE_REPORT=0 // 1 : enable, 0 : disable
+    parameter P = 6,
+    parameter TRACE_DUMP_PER= "ROUTER", //NOC, ROUTER, PORT 
+    parameter CYCLE_REPORT=0 // 1 : enable, 0 : disable
 )
 (
-	current_r_id,
-	chan_in,
-	chan_out,
-	clk
+    current_r_id,
+    chan_in,
+    chan_out,
+    clk
 );
-	
-
-	`NOC_CONF
-
-	input  [31:0] current_r_id;
-	input   flit_chanel_t chan_in  [P-1 : 0];
-	input   flit_chanel_t chan_out [P-1 : 0];
-	input   clk;
-
-	pronoc_trace_dump_sub #(
-		.NOC_ID(NOC_ID),
-		.P(P),
-		.TRACE_DUMP_PER(TRACE_DUMP_PER), //NOC, ROUTER, PORT 
-		.DIRECTION("in"), // in,out
-		.CYCLE_REPORT(CYCLE_REPORT) // 1 : enable, 0 : disable
-	
-	)dump_in
-	(
-		.current_r_id(current_r_id),
-		.chan_in(chan_in),
-		.clk(clk)
-	);
-
-	pronoc_trace_dump_sub #(
-		.NOC_ID(NOC_ID),
-		.P(P),
-		.TRACE_DUMP_PER(TRACE_DUMP_PER), //NOC, ROUTER, PORT 
-		.DIRECTION("out"), // in,out
-		.CYCLE_REPORT(CYCLE_REPORT) // 1 : enable, 0 : disable
-	
-	)dump_out
-	(
-		.current_r_id(current_r_id),
-		.chan_in(chan_out),
-		.clk(clk)
-	);
+    
+    import pronoc_pkg::*;
+    
+    input  [31:0] current_r_id;
+    input   flit_chanel_t chan_in  [P-1 : 0];
+    input   flit_chanel_t chan_out [P-1 : 0];
+    input   clk;
+    
+    pronoc_trace_dump_sub #(
+        .P(P),
+        .TRACE_DUMP_PER(TRACE_DUMP_PER), //NOC, ROUTER, PORT 
+        .DIRECTION("in"), // in,out
+        .CYCLE_REPORT(CYCLE_REPORT) // 1 : enable, 0 : disable
+    ) dump_in (
+        .current_r_id(current_r_id),
+        .chan_in(chan_in),
+        .clk(clk)
+    );
+    
+    pronoc_trace_dump_sub #(
+        .P(P),
+        .TRACE_DUMP_PER(TRACE_DUMP_PER), //NOC, ROUTER, PORT 
+        .DIRECTION("out"), // in,out
+        .CYCLE_REPORT(CYCLE_REPORT) // 1 : enable, 0 : disable
+    ) dump_out (
+        .current_r_id(current_r_id),
+        .chan_in(chan_out),
+        .clk(clk)
+    );
 endmodule
 
 module pronoc_trace_dump_sub #(
-	parameter NOC_ID=0,
-	parameter P = 6,
-	parameter TRACE_DUMP_PER= "ROUTER", //NOC, ROUTER, PORT 
-	parameter DIRECTION="in", // in,out
-	parameter CYCLE_REPORT=0 // 1 : enable, 0 : disable
-) (
-	current_r_id,
-	chan_in,
-	clk
+    parameter P = 6,
+    parameter TRACE_DUMP_PER= "ROUTER", //NOC, ROUTER, PORT 
+    parameter DIRECTION="in", // in,out
+    parameter CYCLE_REPORT=0 // 1 : enable, 0 : disable
+)(
+    current_r_id,
+    chan_in,
+    clk
 );
+    import pronoc_pkg::*;
+    input  [31:0] current_r_id;
+    input   flit_chanel_t chan_in  [P-1 : 0];
+    input   clk;
+    
+    integer Q_out;
+    string fname [P-1 : 0];
+    
+    genvar p;
+    generate 
+    for (p=0;p<P;p++)begin : _P
+        initial begin 
+            /* verilator lint_off WIDTH */ 
+            if(TRACE_DUMP_PER == "PORT"  ) fname[p] = $sformatf("trace_dump_R%0d_P%0d.out",current_r_id,p);
+            if(TRACE_DUMP_PER == "ROUTER") fname[p] = $sformatf("trace_dump_R%0d.out",current_r_id);
+            if(TRACE_DUMP_PER == "NOC"   ) fname[p] = $sformatf("trace_dump.out");
+            /* verilator lint_on WIDTH */ 
+            Q_out = $fopen(fname[p],"w");
+            $fclose(Q_out);
+        end
+        
+        always @(posedge clk) begin 
+            if(chan_in[p].flit_wr) begin 
+                Q_out = $fopen(fname[p],"a");
+                if(CYCLE_REPORT) $fwrite(Q_out,"%t:",$time);
+                $fwrite(Q_out, "Flit %s: Port %0d, Payload: %h\n",DIRECTION, p, chan_in[p].flit);
+                $fclose(Q_out);                
+            end
+            if(chan_in[p].credit>0) begin 
+                Q_out = $fopen(fname[p],"a");
+                if(CYCLE_REPORT) $fwrite(Q_out,"%t:",$time);
+                $fwrite(Q_out, "credit %s:%h Port %0d\n",DIRECTION, chan_in[p].credit,p);
+                $fclose(Q_out);                
+            end        
+        end    
+    end
+    endgenerate
+endmodule
+`endif // SIMULATION
 
-	
-	
-	`NOC_CONF
-
-
-
-	input  [31:0] current_r_id;
-	input   flit_chanel_t chan_in  [P-1 : 0];
-	input   clk;
-
-	integer out;
-	string fname [P-1 : 0];
-
-	genvar p;
-	generate 
-	for (p=0;p<P;p++)begin 
-	initial begin 
-	/* verilator lint_off WIDTH */ 
-		if(TRACE_DUMP_PER == "PORT"  ) fname[p] = $sformatf("trace_dump_R%0d_P%0d.out",current_r_id,p);
-		if(TRACE_DUMP_PER == "ROUTER") fname[p] = $sformatf("trace_dump_R%0d.out",current_r_id);
-		if(TRACE_DUMP_PER == "NOC"   ) fname[p] = $sformatf("trace_dump.out");
-	/* verilator lint_on WIDTH */ 
-		out = $fopen(fname[p],"w");
-		$fclose(out);
-	end
 
 
-	always @(posedge clk) begin 
-		if(chan_in[p].flit_wr) begin 
-			out = $fopen(fname[p],"a");
-			if(CYCLE_REPORT) $fwrite(out,"%t:",$time);
-			$fwrite(out, "Flit %s: Port %0d, Payload: %h\n",DIRECTION, p, chan_in[p].flit);
-			$fclose(out);				
-		end
-		if(chan_in[p].credit>0) begin 
-			out = $fopen(fname[p],"a");
-			if(CYCLE_REPORT) $fwrite(out,"%t:",$time);
-			$fwrite(out, "credit %s:%h Port %0d\n",DIRECTION, chan_in[p].credit,p);
-			$fclose(out);				
-		end		
-	end
 
-	end
-	endgenerate
+module credit_release_gen #(
+    parameter CREDIT_NUM=4
+)(
+    clk,
+    reset,
+    en,
+    credit_out
+);
+    
+    import pronoc_pkg::*;
+    
+    input  clk, reset;
+    input  en;
+    output reg credit_out;
+    
+    localparam W=log2(CREDIT_NUM +1);
+    
+    reg [W-1 : 0] counter;
+    wire counter_is_zero = counter=={W{1'b0}};
+    wire counter_is_max = (counter==CREDIT_NUM[W-1 : 0]);
+    wire counter_incr = (en & counter_is_zero ) | (~counter_is_zero & ~counter_is_max);
+    
+    always @ (`pronoc_clk_reset_edge )begin 
+        if(`pronoc_reset) begin 
+            counter <= {W{1'b0}};
+            credit_out<=1'b0;
+        end else begin 
+            if(counter_incr) begin 
+                counter<= counter +1'b1;
+                credit_out<=1'b1;
+            end else begin 
+                credit_out<=1'b0;
+            end
+        end
+    end    
+    
 endmodule
-//synthesis translate_on	
-
diff --git a/mpsoc/rtl/src_noc/routing.sv b/mpsoc/rtl/src_noc/routing.sv
new file mode 100755
index 0000000..455ea2c
--- /dev/null
+++ b/mpsoc/rtl/src_noc/routing.sv
@@ -0,0 +1,405 @@
+`include "pronoc_def.v"
+/**********************************************************************
+**    File:  routing.v
+**
+**    Copyright (C) 2014-2017  Alireza Monemi
+**
+**    This file is part of ProNoC
+**
+**    ProNoC ( stands for Prototype Network-on-chip)  is free software:
+**    you can redistribute it and/or modify it under the terms of the GNU
+**    Lesser General Public License as published by the Free Software Foundation,
+**    either version 2 of the License, or (at your option) any later version.
+**
+**     ProNoC is distributed in the hope that it will be useful, but WITHOUT
+**     ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+**     or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
+**     Public License for more details.
+**
+**     You should have received a copy of the GNU Lesser General Public
+**     License along with ProNoC. If not, see <http:**www.gnu.org/licenses/>.
+**
+**
+**    Description:
+**    look-ahead and conventional routing algorithms for Mesh and Torus NoC
+**    
+**
+**************************************************************/
+
+
+module conventional_routing #(
+    parameter LOCATED_IN_NI = 1 // only needed for mesh and odd-even routing
+)(
+    reset,
+    clk,
+    current_r_addr,
+    src_e_addr,
+    dest_e_addr,
+    destport
+);
+
+    import pronoc_pkg::*;
+    
+    input  reset,clk;
+    input   [RAw-1   :0] current_r_addr;
+    input   [EAw-1   :0] src_e_addr;
+    input   [DAw-1   :0] dest_e_addr;
+    output  [DSTPw-1 :0] destport;
+    
+    generate
+    if( IS_REGULAR_TOPO | IS_FMESH ) begin : regular_topo
+        regular_topo_router_addr_t dest_router_addr, current_router_addr;
+        always @(*) begin
+            dest_router_addr = regular_topo_router_addr_t'(dest_e_addr);
+            current_router_addr = regular_topo_router_addr_t'(current_r_addr);
+        end
+        regular_topo_conventional_routing #(
+            .LOCATED_IN_NI(LOCATED_IN_NI)
+        ) the_conventional_routing  (
+            .current_router_addr_i(current_router_addr),
+            .dest_router_addr_i(dest_router_addr),
+            .destport(destport)
+        );
+    end else if(IS_FATTREE | IS_TREE ) begin : ftree
+        wire [LKw-1 :0]    current_rx;
+        wire [Lw-1  :0]    current_rl;
+        
+        fattree_router_addr_decode router_addr_decode
+        (
+            .r_addr(current_r_addr),
+            .rx(current_rx),
+            .rl(current_rl)
+        );
+        if( IS_FATTREE ) begin : fattree
+            fattree_conventional_routing the_conventional_routing (
+                .reset(reset),
+                .clk(clk),
+                .current_addr_encoded(current_rx),
+                .current_level(current_rl),
+                .dest_addr_encoded(dest_e_addr),
+                .destport_encoded(destport)
+            );
+        end else if( IS_TREE )begin : tree
+            tree_conventional_routing #(
+                .ROUTE_NAME(ROUTE_NAME),
+                .K(T1),
+                .L(T2)
+            ) the_conventional_routing (
+                .current_addr_encoded(current_rx),
+                .current_level(current_rl),
+                .dest_addr_encoded(dest_e_addr),
+                .destport_encoded(destport)
+            );
+        end // tree
+    end else if (IS_STAR) begin : star
+    /* verilator lint_on WIDTH */
+        star_conventional_routing #(
+            .NE(T1)
+        ) the_conventional_routing  (
+            .dest_e_addr(dest_e_addr),
+            .destport(destport)
+        );
+    end else if (IS_MULTI_MESH) begin : multimesh
+        mesh_cluster_route_xyz  the_conventional_routing  (
+            .current_router_addr_i(current_r_addr),
+            .destination_router_addr_i(dest_e_addr[EAw-1:0]),
+            .router_port_out(destport)
+        );
+    end else begin :custom
+        custom_conv_routing  #(
+            .TOPOLOGY(TOPOLOGY),
+            .ROUTE_NAME(ROUTE_NAME),
+            .ROUTE_TYPE(ROUTE_TYPE),
+            .RAw(RAw),
+            .EAw(EAw),
+            .DSTPw(DSTPw)
+        ) the_conventional_routing (
+            .current_r_addr(current_r_addr),
+            .dest_e_addr(dest_e_addr),
+            .src_e_addr(src_e_addr),
+            .destport(destport)
+        );
+    end //custom
+    endgenerate
+endmodule
+
+
+/************************************
+*     look_ahead_routing
+*************************************/
+module look_ahead_routing #(
+    parameter P = 5
+)(
+    current_r_addr,  //current router  address
+    neighbors_r_addr,
+    dest_e_addr,  // destination endpoint address
+    src_e_addr, //   source endpoint address. Only needed for custom topology
+    destport_encoded,   // current router destination port number
+    lkdestport_encoded, // look ahead destination port number
+    reset,
+    clk
+);
+    import pronoc_pkg::*;
+    
+    localparam
+        PRAw= P * RAw,
+        PLw = P * Lw,
+        PLKw = P * LKw;
+    input   [PRAw-1:  0]  neighbors_r_addr;
+    input   [RAw-1   :   0]  current_r_addr;
+    input   [DAw-1   :   0]  dest_e_addr;
+    input   [EAw-1   :   0]  src_e_addr;
+    input   [DSTPw-1  :   0]  destport_encoded;
+    output  [DSTPw-1  :   0]  lkdestport_encoded;
+    input   reset,clk;
+    localparam  PP = ( IS_MESH | IS_FMESH | IS_TORUS ) ? 5 : (IS_MESH_3D) ? 7 : 3;
+    logic [RAw-1 : 0]  neighbors_r_addr_array [PP-1 : 0];
+    
+    genvar i;
+    generate
+    for (i=0;i<PP;i++)begin :sep 
+        assign neighbors_r_addr_array[i] = neighbors_r_addr[(i+1)*RAw-1 : i*RAw];
+    end
+    if(IS_REGULAR_TOPO | IS_FMESH ) begin : regular_fmesh
+        regular_topo_router_addr_t dest_router_addr;
+        always @(*) begin
+            dest_router_addr = regular_topo_router_addr_t'(dest_e_addr);
+        end
+        regular_topo_look_ahead_routing lkh_route  (
+            .dest_router_addr_i(dest_router_addr),
+            .destport_encoded(destport_encoded),
+            .neighbors_r_addr(neighbors_r_addr_array),
+            .lkdestport_encoded(lkdestport_encoded),
+            .reset(reset),
+            .clk(clk)
+        );
+    end else if (IS_FATTREE) begin: fat
+        wire  [PLKw-1 : 0]  neighbors_rx;
+        wire  [PLw-1 : 0]  neighbors_ry;
+        for (i=0; i<P; i=i+1) begin : port
+            assign neighbors_rx[(i+1)*LKw-1: i*LKw] = neighbors_r_addr[(i*RAw)+LKw-1 : i*RAw];
+            assign neighbors_ry[(i+1)*Lw-1 : i*Lw]  = neighbors_r_addr[(i+1)*RAw-1: (i*RAw)+LKw];
+        end//port
+        fattree_look_ahead_routing #(
+            .P(P)
+        ) look_ahead_route (
+            .destport_encoded(destport_encoded),
+            .dest_addr_encoded(dest_e_addr),
+            .neighbors_rx(neighbors_rx),
+            .neighbors_ry(neighbors_ry),
+            .lkdestport_encoded(lkdestport_encoded),
+            .reset(reset),
+            .clk(clk)
+        );
+    end else if ( IS_TREE) begin: tree
+        wire  [PLKw-1 : 0]  neighbors_rx_tree;
+        wire  [PLw-1 : 0]  neighbors_ry_tree;
+        for (i=0; i<P; i=i+1) begin : port
+            assign neighbors_rx_tree[(i+1)*LKw-1: i*LKw] = neighbors_r_addr[(i*RAw)+LKw-1 : i*RAw];
+            assign neighbors_ry_tree[(i+1)*Lw-1 : i*Lw]  = neighbors_r_addr[(i+1)*RAw-1: (i*RAw)+LKw];
+        end//port
+        tree_look_ahead_routing #(
+            .P(P)
+        )  look_ahead_routing (
+            .destport_encoded(destport_encoded),
+            .dest_addr_encoded(dest_e_addr),
+            .neighbors_rx(neighbors_rx_tree),
+            .neighbors_ry(neighbors_ry_tree),
+            .lkdestport_encoded(lkdestport_encoded),
+            .reset(reset),
+            .clk(clk)
+        );
+    end else if (IS_STAR) begin : star
+        //look-ahead routing is not needed in star topology as there is only one router
+        assign  lkdestport_encoded={DSTPw{1'b0}};
+    end else if (IS_MULTI_MESH) begin : multimesh
+        assign  lkdestport_encoded={DSTPw{1'b0}};
+    end else begin : custom
+        custom_lkh_routing  #(
+            .TOPOLOGY(TOPOLOGY),
+            .ROUTE_NAME(ROUTE_NAME),
+            .ROUTE_TYPE(ROUTE_TYPE),
+            .RAw(RAw),
+            .EAw(EAw),
+            .DSTPw(DSTPw)
+        )  look_ahead_routing  (
+            .current_r_addr(current_r_addr),
+            .dest_e_addr(dest_e_addr),
+            .src_e_addr(src_e_addr),
+            .destport(lkdestport_encoded),
+            .reset(reset),
+            .clk(clk)
+        );
+    end
+    endgenerate
+endmodule
+
+/********************************************************
+*               next_router_addr_selector
+* Determine the next router address based on the packet destination port
+********************************************************/
+module next_router_addr_selector_onehot #(
+    parameter P = 5,
+    parameter RXw = 3,  // The router's x dimension adress width in bits
+    parameter RYw = 3  // The router's y dimension adress width in bits
+)(
+    destport_onehot,
+    neighbors_rx,
+    neighbors_ry,
+    next_rx,
+    next_ry
+);
+    localparam
+        PRXw = P * RXw,
+        PRYw = P * RYw;
+    
+    input [P-1   : 0] destport_onehot;
+    input [PRXw-1: 0] neighbors_rx;
+    input [PRYw-1: 0] neighbors_ry;
+    output logic [RXw-1 : 0] next_rx;
+    output logic [RYw-1 : 0] next_ry;
+    
+    wire [RXw-1:0] neighbors_rx_array [P-1: 0];
+    wire [RYw-1:0] neighbors_ry_array [P-1: 0];
+    genvar i;
+    generate for(i=0;i<P;i++) begin :P_
+        assign neighbors_rx_array[i] = neighbors_rx[(i*RXw)+:RXw];
+        assign neighbors_ry_array[i] = neighbors_ry[(i*RYw)+:RYw];
+    end endgenerate
+    
+    //Onehot mux to select available ovc
+    always_comb begin
+        next_rx = '0;
+        next_ry = '0;
+        for (int k = 0; k < P; k++) begin
+            next_rx |= (destport_onehot[k]) ? neighbors_rx_array[k] : '0;
+            next_ry |= (destport_onehot[k]) ? neighbors_ry_array[k] : '0;
+        end
+    end//always
+endmodule
+
+
+module next_router_addr_selector_bin #(
+    parameter P = 5,
+    parameter RXw = 3,  // The router's x dimension adress width in bits
+    parameter RYw = 3  // The router's y dimension adress width in bits
+) (
+    destport_bin,
+    neighbors_rx,
+    neighbors_ry,
+    next_rx,
+    next_ry
+);
+    function integer log2;
+    input integer number; begin
+        log2=(number <=1) ? 1: 0;
+        while(2**log2<number) begin
+            log2=log2+1;
+        end
+    end
+    endfunction // log2
+    
+    localparam
+        Pw = log2(P),
+        PRXw = P * RXw,
+        PRYw = P * RYw;
+    
+    input [Pw-1 : 0] destport_bin;
+    input [PRXw-1: 0] neighbors_rx;
+    input [PRYw-1: 0] neighbors_ry;
+    output [RXw-1 : 0] next_rx;
+    output [RYw-1 : 0] next_ry;
+    wire [RXw-1:0] neighbors_rx_array [P-1: 0];
+    wire [RYw-1:0] neighbors_ry_array [P-1: 0];
+    genvar i;
+    generate for(i=0;i<P;i++) begin :P_
+        assign neighbors_rx_array[i] = neighbors_rx[(i*RXw)+:RXw];
+        assign neighbors_ry_array[i] = neighbors_ry[(i*RYw)+:RYw];
+    end endgenerate
+    assign next_rx = neighbors_rx_array[destport_bin];
+    assign next_ry = neighbors_ry_array[destport_bin];
+endmodule
+
+/******************
+*   local_route_computation
+*   Compute the output port based on the current router address and destination address
+*   Used when lookahead routing is not used or in multicast routing
+*******************/
+module local_route_computation #(
+    parameter P = 5,
+    parameter SW_LOC = 0 // switch location
+)(
+    endp_port,
+    current_r_addr,
+    chan_in,
+    chan_out,
+    clk,
+    reset
+);  
+    import pronoc_pkg::*;
+    input endp_port;
+    input   [RAw-1 : 0]  current_r_addr;
+    input   flit_chanel_t chan_in;
+    input   clk,reset;
+    output  flit_chanel_t chan_out;
+    
+    flit_chanel_t chan_out_tmp;
+    wire [DSTPw-1 :0] destport,destport_out;
+    always_comb begin 
+        chan_out_tmp=chan_in;
+        if(chan_in.flit.hdr_flag == 1'b1) begin
+            chan_out_tmp.flit [DST_P_MSB : DST_P_LSB] = destport_out;
+        end
+    end
+    
+    generate 
+    if(IS_UNICAST) begin : uni
+        localparam LOCATED_IN_NI=
+            (IS_3D_TOPO)? ((SW_LOC==LOCAL) || (SW_LOC > DOWN) ) :
+            (IS_2D_TOPO)? ((SW_LOC==LOCAL) || (SW_LOC > SOUTH) ) : 
+            (IS_1D_TOPO) ? ((SW_LOC==LOCAL) || (SW_LOC > BACKWARD) )  : 0;
+        hdr_flit_t hdr_flit_i;
+        wire [DSTPw-1 :0] destport;
+        header_flit_info #(
+            .DATA_w (0)
+        ) extractor (
+            .flit(chan_in.flit),
+            .hdr_flit(hdr_flit_i),
+            .data_o( )
+        );
+        conventional_routing #(
+            .LOCATED_IN_NI(LOCATED_IN_NI) // Only needed for mesh and odd-even routing
+        ) conv_route (
+            .reset(reset),
+            .clk(clk),
+            .current_r_addr(current_r_addr),
+            .src_e_addr(hdr_flit_i.src_e_addr),
+            .dest_e_addr(hdr_flit_i.dest_e_addr),
+            .destport(destport)
+        );
+        if((IS_DETERMINISTIC == 1'b0) && (LOCATED_IN_NI==0) && (IS_REGULAR_TOPO==1'b1)) begin 
+            regular_topo_adaptive_lk_dest_encoder encoder(
+                .sel({V{1'b1}}),
+                .flit_in(chan_in.flit),
+                .dest_coded_out(destport_out),
+                .vc_num_delayed({V{1'b1}}),
+                .lk_dest(destport)
+            );
+        end else begin 
+            assign destport_out = destport;
+        end
+        assign chan_out = chan_out_tmp;
+    end else begin : multi
+        multicast_chan_in_process #(
+            .SW_LOC(SW_LOC),
+            .P(P)
+        )multi_cast(
+            .endp_port(endp_port),
+            .current_r_addr(current_r_addr),
+            .chan_in(chan_in),
+            .chan_out(chan_out),
+            .clk(clk)
+        );
+    end
+    endgenerate
+endmodule
diff --git a/mpsoc/rtl/src_noc/routing.v b/mpsoc/rtl/src_noc/routing.v
deleted file mode 100755
index b775a45..0000000
--- a/mpsoc/rtl/src_noc/routing.v
+++ /dev/null
@@ -1,624 +0,0 @@
-`timescale     1ns/1ps
-/**********************************************************************
-**	File:  routing.v
-**
-**	Copyright (C) 2014-2017  Alireza Monemi
-**
-**	This file is part of ProNoC
-**
-**	ProNoC ( stands for Prototype Network-on-chip)  is free software:
-**	you can redistribute it and/or modify it under the terms of the GNU
-**	Lesser General Public License as published by the Free Software Foundation,
-**	either version 2 of the License, or (at your option) any later version.
-**
-** 	ProNoC is distributed in the hope that it will be useful, but WITHOUT
-** 	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
-** 	or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
-** 	Public License for more details.
-**
-** 	You should have received a copy of the GNU Lesser General Public
-** 	License along with ProNoC. If not, see <http:**www.gnu.org/licenses/>.
-**
-**
-**	Description:
-**	look-ahead and conventional routing algorithms for Mesh and Torus NoC
-**	
-**
-**************************************************************/
-
-
-module conventional_routing #(
-    parameter NOC_ID            = 0,
-    parameter TOPOLOGY          = "MESH",
-    parameter ROUTE_NAME        = "XY",
-    parameter ROUTE_TYPE        = "DETERMINISTIC",
-    parameter T1                = 4,
-    parameter T2                = 4,
-    parameter T3                = 4,
-    parameter RAw               = 3,
-    parameter EAw               = 3,
-    parameter DSTPw             = 4,
-    parameter LOCATED_IN_NI     = 1 // only needed for mesh and odd-even routing
-)
-(
-    reset,
-    clk,
-    current_r_addr,
-    src_e_addr,
-    dest_e_addr,
-    destport
-);
-
-    function integer log2;
-    input integer number; begin
-       log2=(number <=1) ? 1: 0;
-       while(2**log2<number) begin
-          log2=log2+1;
-       end
-    end
-    endfunction // log2
-
-    input  reset,clk;
-    input   [RAw-1   :0] current_r_addr;
-    input   [EAw-1   :0] src_e_addr;
-    input   [EAw-1   :0] dest_e_addr;
-    output  [DSTPw-1 :0] destport;
-
- generate
-    /* verilator lint_off WIDTH */
-    if(TOPOLOGY == "MESH" || TOPOLOGY == "FMESH" || TOPOLOGY == "TORUS"  || TOPOLOGY ==  "RING" || TOPOLOGY ==  "LINE") begin :mesh_torus
-    /* verilator lint_on WIDTH */
-
-    localparam
-        NX = T1,
-        NY = T2,
-        RXw = log2(NX),
-        RYw = (TOPOLOGY=="RING" || TOPOLOGY == "LINE") ? 1 :log2(NY),
-        EXw = RXw,
-        EYw = (TOPOLOGY=="RING" || TOPOLOGY == "LINE") ? 1 : RYw;
-
-        wire   [RXw-1   :   0]  current_rx;
-        wire   [RYw-1   :   0]  current_ry;
-        wire   [EXw-1   :   0]  dest_ex;
-        wire   [EYw-1   :   0]  dest_ey;
-
-
-        mesh_tori_router_addr_decode #(
-        	.TOPOLOGY(TOPOLOGY),
-            .T1(T1),
-            .T2(T2),
-            .T3(T3),
-        	.RAw(RAw)
-        )
-        router_addr_decode
-        (
-        	.r_addr(current_r_addr),
-        	.rx(current_rx),
-        	.ry(current_ry),
-        	.valid( )
-        );
-
-       /* verilator lint_off WIDTH */
-        if(TOPOLOGY == "FMESH") begin :fmesh
-         /* verilator lint_on WIDTH */
-            fmesh_endp_addr_decode #(
-                .T1(T1),
-                .T2(T2),
-                .T3(T3),
-                .EAw(EAw)
-            )
-            end_addr_decode
-            (
-                .e_addr(dest_e_addr),
-                .ex(dest_ex),
-                .ey(dest_ey),
-                .ep( ),
-                .valid()
-            );
-
-
-
-        end else begin : mesh
-            mesh_tori_endp_addr_decode #(
-            	.TOPOLOGY(TOPOLOGY),
-            	.T1(T1),
-            	.T2(T2),
-            	.T3(T3),
-            	.EAw(EAw)
-            )
-            end_addr_decode
-            (
-            	.e_addr(dest_e_addr),
-            	.ex(dest_ex),
-            	.ey(dest_ey),
-            	.el( ),
-            	.valid()
-            );
-        end//mesh
-
-            mesh_torus_conventional_routing #(
-                .TOPOLOGY(TOPOLOGY),
-                .ROUTE_NAME(ROUTE_NAME),
-                .ROUTE_TYPE(ROUTE_TYPE),
-                .NX(T1),
-                .NY(T2),
-                .LOCATED_IN_NI(LOCATED_IN_NI)
-            )
-            the_conventional_routing
-            (
-                .current_x(current_rx),
-                .current_y(current_ry),
-                .dest_x(dest_ex),
-                .dest_y(dest_ey),
-                .destport(destport)
-            );
-
-    /* verilator lint_off WIDTH */
-    end else if(TOPOLOGY == "FATTREE" || TOPOLOGY == "TREE" ) begin :tree_based
-    /* verilator lint_on WIDTH */
-
-        localparam
-            K=T1,
-            L=T2,
-            Kw = log2(K),
-            LKw= L*Kw,
-            Lw = log2(L);
-
-        wire [LKw-1 :0]    current_rx;
-        wire [Lw-1  :0]    current_rl;
-
-        fattree_router_addr_decode #(
-            .K(T1),
-            .L(T2)
-        )
-        router_addr_decode
-        (
-            .r_addr(current_r_addr),
-            .rx(current_rx),
-            .rl(current_rl)
-        );
-
-        /* verilator lint_off WIDTH */
-        if(TOPOLOGY == "FATTREE" )begin : fattree
-        /* verilator lint_on WIDTH */
-
-            fattree_conventional_routing #(
-                .ROUTE_NAME(ROUTE_NAME),
-                .K(T1),
-                .L(T2)
-            )
-            the_conventional_routing
-            (
-                .reset(reset),
-                .clk(clk),
-                .current_addr_encoded(current_rx),
-                .current_level(current_rl),
-                .dest_addr_encoded(dest_e_addr),
-                .destport_encoded(destport)
-            );
-        /* verilator lint_off WIDTH */
-        end else  if(TOPOLOGY == "TREE" )begin : tree
-        /* verilator lint_on WIDTH */
-            tree_conventional_routing #(
-                .ROUTE_NAME(ROUTE_NAME),
-                .K(T1),
-                .L(T2)
-            )
-            the_conventional_routing
-            (
-
-                .current_addr_encoded(current_rx),
-                .current_level(current_rl),
-                .dest_addr_encoded(dest_e_addr),
-                .destport_encoded(destport)
-            );
-        end // tree
-
-    /* verilator lint_off WIDTH */
-    end else if (TOPOLOGY == "STAR") begin : star
-    /* verilator lint_on WIDTH */
-        star_conventional_routing #(
-            .NE(T1)
-        )
-        the_conventional_routing
-        (
-            .dest_e_addr(dest_e_addr),
-            .destport(destport)
-        );
-
-
-
-
-    end else begin :custom
-
-        custom_ni_routing  #(
-            .TOPOLOGY(TOPOLOGY),
-            .ROUTE_NAME(ROUTE_NAME),
-            .ROUTE_TYPE(ROUTE_TYPE),
-            .RAw(RAw),
-            .EAw(EAw),
-            .DSTPw(DSTPw)
-        )
-        the_conventional_routing
-        (
-            .dest_e_addr(dest_e_addr),
-            .src_e_addr(src_e_addr),
-            .destport(destport)
-        );
-
-    end //custom
-    endgenerate
-
-endmodule
-
-
-
-
-
-
-
-
-
-
-/************************************
-
-     look_ahead_routing
-
-*************************************/
-
-module look_ahead_routing #(
-    parameter NOC_ID=0,
-    parameter P = 5,
-    parameter T1= 8,
-    parameter T2= 8,
-    parameter T3= 8,
-    parameter T4= 8,
-    parameter RAw = 3,
-    parameter EAw = 3,
-    parameter DAw = 3,
-    parameter DSTPw=P-1,
-    parameter SW_LOC    =0,
-    parameter TOPOLOGY  ="MESH",//"MESH","TORUS"
-    parameter ROUTE_NAME="XY",//
-    parameter ROUTE_TYPE="DETERMINISTIC"// "DETERMINISTIC", "FULL_ADAPTIVE", "PAR_ADAPTIVE"
-)
-(
-    current_r_addr,  //current router  address
-    neighbors_r_addr,
-    dest_e_addr,  // destination endpoint address
-    src_e_addr, //   source endpoint address. Only needed for custom topology
-    destport_encoded,   // current router destination port number
-    lkdestport_encoded, // look ahead destination port number
-    reset,
-    clk
-);
-
-    function integer log2;
-    input integer number; begin
-       log2=(number <=1) ? 1: 0;
-       while(2**log2<number) begin
-          log2=log2+1;
-       end
-    end
-    endfunction // log2
-
-    localparam
-        PRAw= P * RAw;
-    localparam
-        //K= T1,
-        //L=T2,
-            Kw = log2(T1),
-            Lw = log2(T2),
-            LKw= T2 * Kw,
-            PLw = P * Lw,
-            PLKw = P * LKw;
-
-    input   [PRAw-1:  0]  neighbors_r_addr;
-    input   [RAw-1   :   0]  current_r_addr;
-    input   [DAw-1   :   0]  dest_e_addr;
-    input   [EAw-1   :   0]  src_e_addr;
-    input   [DSTPw-1  :   0]  destport_encoded;
-    output  [DSTPw-1  :   0]  lkdestport_encoded;
-    input                   reset,clk;
-
-    genvar i;
-    generate
-    /* verilator lint_off WIDTH */
-    if(TOPOLOGY == "MESH" || TOPOLOGY == "FMESH" || TOPOLOGY == "TORUS"  || TOPOLOGY ==  "RING" || TOPOLOGY ==  "LINE")begin :mesh_torus
-    /* verilator lint_on WIDTH */
-
-       localparam
-        NX = T1,
-        NY = T2,
-        RXw = log2(NX),
-        RYw = (TOPOLOGY=="RING" || TOPOLOGY == "LINE")? 1 : log2(NY),
-        EXw = RXw,
-        EYw = RYw;
-
-        wire   [RXw-1   :   0]  current_rx;
-        wire   [RYw-1   :   0]  current_ry;
-        wire   [EXw-1   :   0]  dest_ex;
-        wire   [EYw-1   :   0]  dest_ey;
-
-        localparam SL_SW_LOC = ( SW_LOC > P-T3) ? 0 : SW_LOC; //single_local
-
-        mesh_tori_router_addr_decode #(
-            .TOPOLOGY(TOPOLOGY),
-            .T1(T1),
-            .T2(T2),
-            .T3(T3),
-            .RAw(RAw)
-        )
-        router_addr_decode
-        (
-            .r_addr(current_r_addr),
-            .rx(current_rx),
-            .ry(current_ry),
-            .valid( )
-        );
-         /* verilator lint_off WIDTH */
-        if(TOPOLOGY == "FMESH") begin :fmesh
-         /* verilator lint_on WIDTH */
-             fmesh_endp_addr_decode #(
-                .T1(T1),
-                .T2(T2),
-                .T3(T3),
-                .EAw(EAw)
-            )
-            end_addr_decode
-            (
-                .e_addr(dest_e_addr),
-                .ex(dest_ex),
-                .ey(dest_ey),
-                .ep( ),
-                .valid()
-            );
-        end else begin :mesh
-            mesh_tori_endp_addr_decode #(
-                .TOPOLOGY(TOPOLOGY),
-                .T1(T1),
-                .T2(T2),
-                .T3(T3),
-                .EAw(EAw)
-            )
-            end_addr_decode
-            (
-                .e_addr(dest_e_addr),
-                .ex(dest_ex),
-                .ey(dest_ey),
-                .el( ),
-                .valid()
-            );
-
-
-        end
-
-        mesh_torus_look_ahead_routing #(
-           	.NX(T1),
-        	.NY(T2),
-        	.SW_LOC(SL_SW_LOC),
-        	.TOPOLOGY(TOPOLOGY),
-        	.ROUTE_NAME(ROUTE_NAME),
-        	.ROUTE_TYPE(ROUTE_TYPE)
-        )
-        look_ahead_route
-        (
-        	.current_x(current_rx),
-        	.current_y(current_ry),
-        	.dest_x(dest_ex),
-        	.dest_y(dest_ey),
-        	.destport_encoded(destport_encoded),
-        	.lkdestport_encoded(lkdestport_encoded),
-        	.reset(reset),
-        	.clk(clk)
-        );
-    /* verilator lint_off WIDTH */
-    end else if (TOPOLOGY == "FATTREE") begin: fat
-    /* verilator lint_on WIDTH */
-
-        wire  [PLKw-1 : 0]  neighbors_rx;
-        wire  [PLw-1 : 0]  neighbors_ry;
-
-        for (i=0; i<P; i=i+1) begin : port
-            assign neighbors_rx[(i+1)*LKw-1: i*LKw] = neighbors_r_addr[(i*RAw)+LKw-1 : i*RAw];
-            assign neighbors_ry[(i+1)*Lw-1 : i*Lw]  = neighbors_r_addr[(i+1)*RAw-1: (i*RAw)+LKw];
-        end//port
-
-        fattree_look_ahead_routing #(
-        	.ROUTE_NAME(ROUTE_NAME),
-        	.P(P),
-        	.K(T1),
-        	.L(T2)        	
-        )
-        look_ahead_route
-        (
-        	.destport_encoded(destport_encoded),
-        	.dest_addr_encoded(dest_e_addr),
-        	.neighbors_rx(neighbors_rx),
-        	.neighbors_ry(neighbors_ry),
-        	.lkdestport_encoded(lkdestport_encoded),
-        	.reset(reset),
-        	.clk(clk)
-        );
-
-    /* verilator lint_off WIDTH */
-    end else if (TOPOLOGY == "TREE") begin: tree
-    /* verilator lint_on WIDTH */
-
-        wire  [PLKw-1 : 0]  neighbors_rx_tree;
-        wire  [PLw-1 : 0]  neighbors_ry_tree;
-
-        for (i=0; i<P; i=i+1) begin : port
-            assign neighbors_rx_tree[(i+1)*LKw-1: i*LKw] = neighbors_r_addr[(i*RAw)+LKw-1 : i*RAw];
-            assign neighbors_ry_tree[(i+1)*Lw-1 : i*Lw]  = neighbors_r_addr[(i+1)*RAw-1: (i*RAw)+LKw];
-        end//port
-
-
-        tree_look_ahead_routing #(
-        	.ROUTE_NAME(ROUTE_NAME),
-        	.P(P),
-        	.L(T2),
-        	.K(T1)
-        )
-        look_ahead_routing
-        (
-        	.destport_encoded(destport_encoded),
-        	.dest_addr_encoded(dest_e_addr),
-        	.neighbors_rx(neighbors_rx_tree),
-        	.neighbors_ry(neighbors_ry_tree),
-        	.lkdestport_encoded(lkdestport_encoded),
-        	.reset(reset),
-        	.clk(clk)
-        );
-
-      /* verilator lint_off WIDTH */
-    end else if (TOPOLOGY == "STAR") begin : star
-    /* verilator lint_on WIDTH */
-     //look-ahead routing is not needed in star topology as there is only one router
-        assign  lkdestport_encoded={DSTPw{1'b0}};
-
-     end else begin : custom
-
-        custom_lkh_routing  #(
-            .TOPOLOGY(TOPOLOGY),
-            .ROUTE_NAME(ROUTE_NAME),
-            .ROUTE_TYPE(ROUTE_TYPE),
-            .RAw(RAw),
-            .EAw(EAw),
-            .DSTPw(DSTPw)
-        )
-        look_ahead_routing
-        (
-            .current_r_addr(current_r_addr),
-            .dest_e_addr(dest_e_addr),
-            .src_e_addr(src_e_addr),
-            .destport(lkdestport_encoded),
-            .reset(reset),
-            .clk(clk)
-        );
-
-    end
-    endgenerate
-endmodule
-
-/********************************************************
-
-                    next_router_addr_selector
-
-Determine the next router address based on the packet destination port
-
-********************************************************/
-
-
-module next_router_addr_selector_onehot #(
-    parameter P = 5,
-    parameter RXw = 3,  // The router's x dimension adress width in bits
-    parameter RYw = 3  // The router's y dimension adress width in bits
-    )
-    (
-    destport_onehot,
-    neighbors_rx,
-    neighbors_ry,
-    next_rx,
-    next_ry
-    );
-
-    localparam
-        PRXw = P * RXw,
-        PRYw = P * RYw;
-
-    input [P-1   :  0]  destport_onehot;
-    input [PRXw-1:  0]  neighbors_rx;
-    input [PRYw-1:  0]  neighbors_ry;
-    output[RXw-1  :    0]  next_rx;
-    output[RYw-1  :    0]  next_ry;
-
-    onehot_mux_1D #(
-        .W(RXw),
-        .N(P)
-    )
-    next_x_mux
-    (
-        .in(neighbors_rx),
-        .out(next_rx),
-        .sel(destport_onehot)
-    );
-
-    onehot_mux_1D #(
-        .W(RYw),
-        .N(P)
-    )
-    next_y_mux
-    (
-        .in(neighbors_ry),
-        .out(next_ry),
-        .sel(destport_onehot)
-    );
-
-endmodule
-
-
-
-
-
-module next_router_addr_selector_bin #(
-    parameter P = 5,
-    parameter RXw = 3,  // The router's x dimension adress width in bits
-    parameter RYw = 3  // The router's y dimension adress width in bits
-    )
-    (
-    destport_bin,
-    neighbors_rx,
-    neighbors_ry,
-    next_rx,
-    next_ry
-
-    );
-
-    function integer log2;
-      input integer number; begin
-         log2=(number <=1) ? 1: 0;
-         while(2**log2<number) begin
-            log2=log2+1;
-         end
-      end
-    endfunction // log2
-
-    localparam
-        Pw = log2(P),
-        PRXw = P * RXw,
-        PRYw = P * RYw;
-
-    input [Pw-1   :  0]  destport_bin;
-    input [PRXw-1:  0]  neighbors_rx;
-    input [PRYw-1:  0]  neighbors_ry;
-    output[RXw-1  :    0]  next_rx;
-    output[RYw-1  :    0]  next_ry;
-
-    binary_mux #(
-        .IN_WIDTH(PRXw),
-        .OUT_WIDTH(RXw)
-    )
-    next_x_mux
-    (
-        .mux_in(neighbors_rx),
-        .mux_out(next_rx),
-        .sel(destport_bin)
-    );
-
-    binary_mux  #(
-        .IN_WIDTH(PRYw),
-        .OUT_WIDTH(RYw)
-    )
-    next_y_mux
-    (
-        .mux_in(neighbors_ry),
-        .mux_out(next_ry),
-        .sel(destport_bin)
-    );
-
-endmodule
-
-
-
-
diff --git a/mpsoc/rtl/src_noc/ss_allocator.sv b/mpsoc/rtl/src_noc/ss_allocator.sv
index a219c8d..3d0f8af 100755
--- a/mpsoc/rtl/src_noc/ss_allocator.sv
+++ b/mpsoc/rtl/src_noc/ss_allocator.sv
@@ -1,134 +1,110 @@
 `include "pronoc_def.v"
-
 /**********************************************************************
-**	File:  ss_allocator.v
-**	Date:2016-06-19  
+**    File: ss_allocator.v
+**    Date:2016-06-19  
 **    
-**	Copyright (C) 2014-2019  Alireza Monemi
+**    Copyright (C) 2014-2019  Alireza Monemi
 **    
-**	This file is part of ProNoC 
+**    This file is part of ProNoC 
 **
-**	ProNoC ( stands for Prototype Network-on-chip)  is free software: 
-**	you can redistribute it and/or modify it under the terms of the GNU
-**	Lesser General Public License as published by the Free Software Foundation,
-**	either version 2 of the License, or (at your option) any later version.
+**    ProNoC ( stands for Prototype Network-on-chip)  is free software: 
+**    you can redistribute it and/or modify it under the terms of the GNU
+**    Lesser General Public License as published by the Free Software Foundation,
+**    either version 2 of the License, or (at your option) any later version.
 **
-** 	ProNoC is distributed in the hope that it will be useful, but WITHOUT
-** 	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
-** 	or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
-** 	Public License for more details.
+**     ProNoC is distributed in the hope that it will be useful, but WITHOUT
+**     ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+**     or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
+**     Public License for more details.
 **
-** 	You should have received a copy of the GNU Lesser General Public
-** 	License along with ProNoC. If not, see <http:**www.gnu.org/licenses/>.
+**     You should have received a copy of the GNU Lesser General Public
+**     License along with ProNoC. If not, see <http:**www.gnu.org/licenses/>.
 **
 **
-**	Description: 
-**	static straight allocator : The incoming packet targeting output port located in same direction 
-** 	will be forwarded with one clock cycle latency if the following conditions met in current clock cycle:
-**	1) If no ivc is granted in the input port 
-**	2) The ss output port is not granted for any other input port 
-**	3) Packet destination port match with ss port
-**	4) The requested output VC is available in ss port 
-**	   The ss ports for each input potrt must be different with the rest
-**	   This result in one clock cycle latency                
+**    Description: 
+**    static straight allocator : The incoming packet targeting output port located in same direction 
+**     will be forwarded with one clock cycle latency if the following conditions met in current clock cycle:
+**    1) If no ivc is granted in the input port 
+**    2) The ss output port is not granted for any other input port 
+**    3) Packet destination port match with ss port
+**    4) The requested output VC is available in ss port 
+**       The ss ports for each input potrt must be different with the rest
+**       This result in one clock cycle latency                
 ***************************************/
 
 
 module  ss_allocator #(
-    parameter NOC_ID=0,
-    parameter P=5     
+    parameter P=5
 )(
-   		clk,
-   		reset,  
-   		flit_in_wr_all,
-        flit_in_all,
-        any_ovc_granted_in_outport_all ,
-        any_ivc_sw_request_granted_all ,
-        ovc_avalable_all,
-       // assigned_ovc_not_full_all,
-       // dest_port_encoded_all,
-       // assigned_ovc_num_all,
-       // ovc_is_assigned_all,    
-        ivc_info,
-        ovc_info,   
-        ssa_ctrl_o
-   );
-
-
-	`NOC_CONF    	
-	
-    localparam  PV          =   V   *   P,
-    			VV			=   V * V,
-                PVV         =   PV  *   V,
-                PVDSTPw= PV * DSTPw,                
-                PFw         =   P   *   Fw;
-                
-    localparam    DISABLED = P;                       
-             
-
-    input   [PFw-1          :   0]  flit_in_all;
-    input   [P-1            :   0]  flit_in_wr_all;
-    input   [P-1            :   0]  any_ovc_granted_in_outport_all;
-    input   [P-1            :   0]  any_ivc_sw_request_granted_all;
-    input   [PV-1           :   0]  ovc_avalable_all;
-    
-   
+    clk,
+    reset,  
+    flit_in_wr_all,
+    flit_in_all,
+    any_ovc_granted_in_outport_all ,
+    any_ivc_sw_request_granted_all ,
+    ovc_avalable_all,
+    ivc_info,
+    ovc_info,
+    ssa_ctrl_o
+);
+    import pronoc_pkg::*;
+    localparam
+        PV = V * P,
+        VV = V * V,
+        PVV = PV * V,
+        PVDSTPw= PV * DSTPw,
+        PFw = P * Fw,
+        DISABLED = P;
+    input flit_t  flit_in_all [P-1 : 0];
+    input [P-1 : 0]  flit_in_wr_all;
+    input [P-1 : 0]  any_ovc_granted_in_outport_all;
+    input [P-1 : 0]  any_ivc_sw_request_granted_all;
+    input [PV-1 : 0]  ovc_avalable_all;
     input   reset,clk;
     input   ivc_info_t   ivc_info   [P-1 : 0][V-1 : 0];
     input   ovc_info_t   ovc_info   [P-1 : 0][V-1 : 0];
     output  ssa_ctrl_t   ssa_ctrl_o [P-1 : 0]; 
-
-
-    wire   [PV-1      :   0] ovc_allocated_all;
-    wire   [PV-1      :   0] ovc_released_all;
-    wire   [PVV-1     :   0] granted_ovc_num_all;
-    wire   [PV-1      :   0] ivc_num_getting_sw_grant_all;
-    wire   [PV-1      :   0] ivc_num_getting_ovc_grant_all;
-    wire   [PV-1      :   0] ivc_reset_all;
-    wire   [PV-1      :   0] single_flit_pck_all,ovc_single_flit_pck_all;
-    wire   [PV-1      :   0] decreased_credit_in_ss_ovc_all;
-    wire   [P-1       :   0] ssa_flit_wr_all;
-  
-   
-    wire [PV-1   :   0] any_ovc_granted_in_ss_port;
-    wire [PV-1   :   0] ovc_avalable_in_ss_port;
-    wire [PV-1   :   0] ovc_allocated_in_ss_port;
-    wire [PV-1   :   0] ovc_released_in_ss_port;
-    wire [PV-1   :   0] decreased_credit_in_ss_ovc;
-    wire [PV-1   :   0] ivc_num_getting_sw_grantin_SS_all;
-
-    wire [PV-1       : 0] ivc_request_all;
-    wire [PV-1       : 0] assigned_ovc_not_full_all;  
-    wire [PVDSTPw-1  : 0] dest_port_encoded_all;
-    wire [PVV-1      : 0] assigned_ovc_num_all;
-    wire [PV-1       : 0] ovc_is_assigned_all;
-    wire [MAX_P-1     : 0] destport_one_hot [PV-1 : 0];
     
-	genvar i;
+    wire [PV-1 : 0] ovc_allocated_all;
+    wire [PV-1 : 0] ovc_released_all;
+    wire [PVV-1 : 0] granted_ovc_num_all;
+    wire [PV-1 : 0] ivc_num_getting_sw_grant_all;
+    wire [PV-1 : 0] ivc_num_getting_ovc_grant_all;
+    wire [PV-1 : 0] ivc_reset_all;
+    wire [PV-1 : 0] single_flit_pck_all,ovc_single_flit_pck_all;
+    wire [PV-1 : 0] decreased_credit_in_ss_ovc_all;
+    logic [P-1 : 0] ssa_flit_wr_all;
+    wire [PV-1 : 0] any_ovc_granted_in_ss_port;
+    wire [PV-1 : 0] ovc_avalable_in_ss_port;
+    wire [PV-1 : 0] ovc_allocated_in_ss_port;
+    wire [PV-1 : 0] ovc_released_in_ss_port;
+    wire [PV-1 : 0] decreased_credit_in_ss_ovc;
+    wire [PV-1 : 0] ivc_num_getting_sw_grantin_SS_all;
+    wire [PV-1 : 0] ivc_request_all;
+    wire [PV-1 : 0] assigned_ovc_not_full_all;
+    wire [PVDSTPw-1 : 0] dest_port_encoded_all;
+    wire [PVV-1 : 0] assigned_ovc_num_all;
+    wire [PV-1 : 0] ovc_is_assigned_all;
+    wire [MAX_P-1 : 0] destport_one_hot [PV-1 : 0];
+    
+    genvar i;
     // there is no ssa for local port in 5 and 3 port routers
     generate
-    for (i=0; i<PV; i=i+1) begin : vc_loop
-    
+    for (i=0; i<PV; i=i+1) begin : V_
         localparam  C_PORT  = i/V;
         localparam  SS_PORT = strieght_port (P,C_PORT);
-        
         assign ivc_request_all[i] = ivc_info[C_PORT][i%V].ivc_req;
-        assign assigned_ovc_not_full_all[i] = ~ovc_info[SS_PORT][i%V].full;
-        //assign assigned_ovc_not_full_all[i] = ivc_info[C_PORT][i%V].assigned_ovc_not_full;
         
+        //assign assigned_ovc_not_full_all[i] = ivc_info[C_PORT][i%V].assigned_ovc_not_full;
         assign dest_port_encoded_all [(i+1)*DSTPw-1 : i*DSTPw] = ivc_info[C_PORT][i%V].dest_port_encoded;
         assign assigned_ovc_num_all[(i+1)*V-1 : i*V] = ivc_info[C_PORT][i%V].assigned_ovc_num;
         assign ovc_is_assigned_all[i] = ivc_info[C_PORT][i%V].ovc_is_assigned;
-        
         assign destport_one_hot[i] = ivc_info[C_PORT][i%V].destport_one_hot;
         
-           
         if (SS_PORT == DISABLED)begin : no_prefrable
-       
-       
             assign   ovc_allocated_all[i]= 1'b0;
             assign   ovc_released_all [i]= 1'b0;
-            assign   granted_ovc_num_all[(i+1)*V-1   :   i*V]= {V{1'b0}};
+            assign   granted_ovc_num_all[(i+1)*V-1 : i*V]= {V{1'b0}};
             assign   ivc_num_getting_sw_grant_all [i]= 1'b0;
             assign   ivc_num_getting_ovc_grant_all [i]= 1'b0;
             assign   ivc_reset_all [i]= 1'b0;
@@ -136,42 +112,35 @@ module  ss_allocator #(
             assign   single_flit_pck_all[i]= 1'b0;
             assign   ovc_single_flit_pck_all [i] =1'b0;
             assign   ivc_num_getting_sw_grantin_SS_all[i]=1'b0;
-          
-           // assign   predict_flit_wr_all [i]=1'b0;       
-         
-       
-       end else begin : ssa
-       
+            assign   assigned_ovc_not_full_all[i]=1'b0;
+           // assign   predict_flit_wr_all [i]=1'b0;
+        end else begin : ssa
+            assign   assigned_ovc_not_full_all[i] = ~ovc_info[SS_PORT][i%V].full;
             assign   any_ovc_granted_in_ss_port[i]=any_ovc_granted_in_outport_all[SS_PORT];
             assign   ovc_avalable_in_ss_port[i]=ovc_avalable_all[(SS_PORT*V)+(i%V)];
             assign   ovc_allocated_all[(SS_PORT*V)+(i%V)]=ovc_allocated_in_ss_port[i];
             assign   ovc_released_all[(SS_PORT*V)+(i%V)]=ovc_released_in_ss_port[i];
             assign   decreased_credit_in_ss_ovc_all[(SS_PORT*V)+(i%V)]=decreased_credit_in_ss_ovc[i]; 
             assign   ivc_num_getting_sw_grantin_SS_all[i]=  ivc_num_getting_sw_grant_all[(SS_PORT*V)+(i%V)];    
-       	    assign   ovc_single_flit_pck_all [i] =  single_flit_pck_all[(SS_PORT*V)+(i%V)];
-       
-             
-       
+            assign   ovc_single_flit_pck_all [i] =  single_flit_pck_all[(SS_PORT*V)+(i%V)];
+            
             ssa_per_vc #(
-                .NOC_ID(NOC_ID),
                 .SS_PORT(SS_PORT),
                 .V_GLOBAL(i),
-                .P(P)              
-            )
-            the_ssa_per_vc
-            (
+                .P(P)
+            ) the_ssa_per_vc (
                 .flit_in_wr(flit_in_wr_all[(i/V)]),
-                .flit_in(flit_in_all[((i/V)+1)*Fw-1 :   (i/V)*Fw]),
-                .any_ivc_sw_request_granted(any_ivc_sw_request_granted_all[(i/V)]),                
-                .any_ovc_granted_in_ss_port(any_ovc_granted_in_ss_port[i]),                
-                .ovc_avalable_in_ss_port(ovc_avalable_in_ss_port[i]),                
+                .flit_in(flit_in_all[(i/V)]),
+                .any_ivc_sw_request_granted(any_ivc_sw_request_granted_all[(i/V)]),
+                .any_ovc_granted_in_ss_port(any_ovc_granted_in_ss_port[i]),
+                .ovc_avalable_in_ss_port(ovc_avalable_in_ss_port[i]),
                 .ivc_request(ivc_request_all[i]),
                 .assigned_ovc_not_full(assigned_ovc_not_full_all[i]),
-                .destport_encoded(dest_port_encoded_all[(i+1)*DSTPw-1 :   i*DSTPw]),
+                .destport_encoded(dest_port_encoded_all[(i+1)*DSTPw-1 : i*DSTPw]),
                 .assigned_to_ssovc(assigned_ovc_num_all[(i*V)+(i%V)]),
-                .ovc_is_assigned(ovc_is_assigned_all[i]),                
-                .ovc_allocated(ovc_allocated_in_ss_port[i]),                
-                .ovc_released(ovc_released_in_ss_port[i]),                
+                .ovc_is_assigned(ovc_is_assigned_all[i]),
+                .ovc_allocated(ovc_allocated_in_ss_port[i]),
+                .ovc_released(ovc_released_in_ss_port[i]),
                 .granted_ovc_num(granted_ovc_num_all[(i+1)*V-1 : i*V]),
                 .ivc_num_getting_sw_grant(ivc_num_getting_sw_grant_all[i]),
                 .ivc_num_getting_ovc_grant(ivc_num_getting_ovc_grant_all[i]),
@@ -179,140 +148,98 @@ module  ss_allocator #(
                 .single_flit_pck(single_flit_pck_all[i]),
                 .destport_one_hot(destport_one_hot[i]),
                 .decreased_credit_in_ss_ovc(decreased_credit_in_ss_ovc[i])
-                //synthesis translate_off 
-                //synopsys  translate_off
+                `ifdef SIMULATION
                 ,.clk(clk)
-                //synopsys  translate_on
-                //synthesis translate_on 
-       
-            );           
-               
+                `endif 
+            );
         end//ssa
     end// vc_loop
     
-    
-    for(i=0;i<P;i=i+1)begin: P_     
-    	
-    	
-    	pronoc_register #(.W(1)) reg1 (
-    			.in(|ivc_num_getting_sw_grantin_SS_all[(i+1)*V-1    :   i*V] ),
-    			.out(ssa_flit_wr_all[i]),
-    			.reset(reset),
-    			.clk(clk));
-    	
-
-    
-       
-            assign ssa_ctrl_o[i].ovc_is_allocated =ovc_allocated_all [(i+1)*V-1  : i*V];
-            assign ssa_ctrl_o[i].ovc_is_released = ovc_released_all  [(i+1)*V-1  : i*V];      
-            assign ssa_ctrl_o[i].ivc_num_getting_sw_grant = ivc_num_getting_sw_grant_all[(i+1)*V-1  : i*V]; 
-            assign ssa_ctrl_o[i].ivc_num_getting_ovc_grant= ivc_num_getting_ovc_grant_all[(i+1)*V-1  : i*V];
-            assign ssa_ctrl_o[i].ivc_reset= ivc_reset_all[(i+1)*V-1  : i*V];
-            assign ssa_ctrl_o[i].buff_space_decreased = decreased_credit_in_ss_ovc_all[(i+1)*V-1  : i*V];
-            assign ssa_ctrl_o[i].ivc_single_flit_pck = single_flit_pck_all [(i+1)*V-1  : i*V];
-            assign ssa_ctrl_o[i].ovc_single_flit_pck = ovc_single_flit_pck_all [(i+1)*V-1  : i*V];
-            assign ssa_ctrl_o[i].ssa_flit_wr = ssa_flit_wr_all[i] ;
-            assign ssa_ctrl_o[i].ivc_granted_ovc_num = granted_ovc_num_all[(i+1)*VV-1  : i*VV];
-            
-          
-            
-    
-    	end// port_lp
-    
-    
-    
-    
+    for(i=0;i<P;i=i+1)begin: P_
+        always_ff @ (`pronoc_clk_reset_edge) begin
+            if (`pronoc_reset) begin
+                ssa_flit_wr_all[i] <= 1'b0;
+            end else begin
+                ssa_flit_wr_all[i] <= |ivc_num_getting_sw_grantin_SS_all[(i+1)*V-1 : i*V];
+            end
+        end
+        
+        assign ssa_ctrl_o[i].ovc_is_allocated =ovc_allocated_all [(i+1)*V-1 : i*V];
+        assign ssa_ctrl_o[i].ovc_is_released = ovc_released_all  [(i+1)*V-1 : i*V];      
+        assign ssa_ctrl_o[i].ivc_num_getting_sw_grant = ivc_num_getting_sw_grant_all[(i+1)*V-1 : i*V]; 
+        assign ssa_ctrl_o[i].ivc_num_getting_ovc_grant= ivc_num_getting_ovc_grant_all[(i+1)*V-1 : i*V];
+        assign ssa_ctrl_o[i].ivc_reset= ivc_reset_all[(i+1)*V-1 : i*V];
+        assign ssa_ctrl_o[i].buff_space_decreased = decreased_credit_in_ss_ovc_all[(i+1)*V-1 : i*V];
+        assign ssa_ctrl_o[i].ivc_single_flit_pck = single_flit_pck_all [(i+1)*V-1 : i*V];
+        assign ssa_ctrl_o[i].ovc_single_flit_pck = ovc_single_flit_pck_all [(i+1)*V-1 : i*V];
+        assign ssa_ctrl_o[i].ssa_flit_wr = ssa_flit_wr_all[i] ;
+        assign ssa_ctrl_o[i].ivc_granted_ovc_num = granted_ovc_num_all[(i+1)*VV-1 : i*VV];
+    end// port_lp
     endgenerate
-
-
 endmodule
 
-
-
-
 /*************
  *  ssa_per_vc 
  * ***********/
-
 module ssa_per_vc #(
-    parameter NOC_ID=0,
     parameter P=5,
     parameter SS_PORT = "WEST",
     parameter V_GLOBAL = 1
-)
-    (
-        flit_in_wr,
-        flit_in,
-        any_ovc_granted_in_ss_port,
-        any_ivc_sw_request_granted,
-        ovc_avalable_in_ss_port,
-        ivc_request,
-        assigned_ovc_not_full,
-        granted_ovc_num,
-        ivc_num_getting_sw_grant,
-        ivc_num_getting_ovc_grant,
-        assigned_to_ssovc,
-        ovc_is_assigned,
-        destport_encoded,
-        ovc_released,
-        ovc_allocated,
-        decreased_credit_in_ss_ovc,
-        single_flit_pck,
-        destport_one_hot,
-        ivc_reset      
-//synthesis translate_off 
-//synopsys  translate_off
-        ,clk
-//synopsys  translate_on
-//synthesis translate_on 
-          
-        
-   );      
-    
-    
-    `NOC_CONF    	
-        
+) (
+    flit_in_wr,
+    flit_in,
+    any_ovc_granted_in_ss_port,
+    any_ivc_sw_request_granted,
+    ovc_avalable_in_ss_port,
+    ivc_request,
+    assigned_ovc_not_full,
+    granted_ovc_num,
+    ivc_num_getting_sw_grant,
+    ivc_num_getting_ovc_grant,
+    assigned_to_ssovc,
+    ovc_is_assigned,
+    destport_encoded,
+    ovc_released,
+    ovc_allocated,
+    decreased_credit_in_ss_ovc,
+    single_flit_pck,
+    destport_one_hot,
+    ivc_reset
+    `ifdef SIMULATION
+    ,clk
+    `endif
+);
     
+    import pronoc_pkg::*;
     //header packet filds width
-    localparam  SW_LOC             =V_GLOBAL/V,
-                V_LOCAL            =V_GLOBAL%V;
-
-    /* verilator lint_off WIDTH */ 
-    localparam SSA_EN_IN_PORT = ((TOPOLOGY== "MESH" || TOPOLOGY == "TORUS") && (ROUTE_TYPE == "FULL_ADAPTIVE") && (SS_PORT==2 || SS_PORT == 4) && ((1<<V_LOCAL &  ~ESCAP_VC_MASK ) != {V{1'b0}})) ? 1'b0 :1'b1;
-    /* verilator lint_on WIDTH */   
-      
-               
-
-    input   [Fw-1          :   0]  flit_in;
-    input                          flit_in_wr;
-    input                          any_ovc_granted_in_ss_port;
-    input                          any_ivc_sw_request_granted;
-    input                          ovc_avalable_in_ss_port;
-    input                          ivc_request; 
-    input                          assigned_ovc_not_full;  
-    input   [DSTPw-1      :    0]  destport_encoded;//exsited packet destination port
-    input                          assigned_to_ssovc;
-    input                          ovc_is_assigned;
-    input   [MAX_P-1       :    0]  destport_one_hot;
+    localparam  
+        SW_LOC = V_GLOBAL/V,
+        V_LOCAL = V_GLOBAL%V;
+    localparam logic [V-1:0] MASKED_LOCAL_VC = V'((1 << V_LOCAL)) & ~ (V'(ESCAP_VC_MASK));
+    localparam SSA_EN_IN_PORT = (((IS_MESH | IS_TORUS) & IS_FULL_ADAPTIVE) && (SS_PORT == 2 || SS_PORT == 4) && ( MASKED_LOCAL_VC != {V{1'b0}}) ) ? 1'b0 : 1'b1;
     
-    output reg [V-1          :   0]  granted_ovc_num;
-    output                        ivc_num_getting_sw_grant;
-    output                        ivc_num_getting_ovc_grant;
-    output                        ovc_released;
-    output                        ovc_allocated;
-    output                        ivc_reset;
-    output                        decreased_credit_in_ss_ovc;
-    output                        single_flit_pck;
-
-//synthesis translate_off 
-//synopsys  translate_off
+    input [Fw-1 : 0]  flit_in;
+    input flit_in_wr;
+    input any_ovc_granted_in_ss_port;
+    input any_ivc_sw_request_granted;
+    input ovc_avalable_in_ss_port;
+    input ivc_request; 
+    input assigned_ovc_not_full;  
+    input [DSTPw-1 : 0]  destport_encoded;//exsited packet destination port
+    input assigned_to_ssovc;
+    input ovc_is_assigned;
+    input [MAX_P-1 : 0]  destport_one_hot;
+    output reg [V-1 : 0]  granted_ovc_num;
+    output ivc_num_getting_sw_grant;
+    output ivc_num_getting_ovc_grant;
+    output ovc_released;
+    output ovc_allocated;
+    output ivc_reset;
+    output decreased_credit_in_ss_ovc;
+    output single_flit_pck;
+`ifdef SIMULATION
     input clk;
-//synopsys  translate_on
-//synthesis translate_on
-
-
- 
-
+`endif
 /*
 *    1) If no ivc is granted in the input port 
 *    2) The ss output port is not granted for any other input port 
@@ -321,27 +248,17 @@ module ssa_per_vc #(
 *    5) The requested output VC is available in ss port 
 * The predicted ports for each input potrt must be diffrent with the rest
 */
-
-    
-    
-   
     wire    [DSTPw-1 : 0] destport_in_encoded;//incomming packet destination port
     wire    [V-1 : 0] vc_num_in;
     wire    hdr_flg;
     wire    tail_flg;
-    /* verilator lint_off WIDTH */ 
     assign  single_flit_pck = 
-    	(PCK_TYPE == "SINGLE_FLIT")? 1'b1 :
-    	(MIN_PCK_SIZE==1)?  hdr_flg & tail_flg : 1'b0; 
-    /* verilator lint_on WIDTH */ 	
-    
-    
-    wire   condition_1_2_valid;     
+        (IS_SINGLE_FLIT)? 1'b1 :
+        (MIN_PCK_SIZE==1)?  hdr_flg & tail_flg : 1'b0; 
+    wire   condition_1_2_valid;
     wire [DAw-1 : 0]  dest_e_addr_in;
-   
     extract_header_flit_info #(
-        .NOC_ID(NOC_ID),
-    	.DATA_w(0)	
+        .DATA_w(0)
     ) extractor (
         .flit_in(flit_in),
         .flit_in_wr(flit_in_wr),
@@ -357,306 +274,191 @@ module ssa_per_vc #(
         .be_o( ),
         .data_o( )
     );
-   
+    // check condition 1 & 2
+    assign condition_1_2_valid = ~(any_ovc_granted_in_ss_port  | any_ivc_sw_request_granted);
+    //check destination port is ss
+    wire ss_port_hdr_flit, ss_port_nonhdr_flit;
     
-
-// check condition 1 & 2
-assign condition_1_2_valid = ~(any_ovc_granted_in_ss_port  | any_ivc_sw_request_granted);
-
-
-//check destination port is ss
-wire ss_port_hdr_flit, ss_port_nonhdr_flit;
-
-ssa_check_destport #(   
-    .NOC_ID(NOC_ID),
-    .SW_LOC(SW_LOC),
-    .P(P),  
-    .SS_PORT(SS_PORT)
-)
- check_destport
-(   
-    .destport_encoded(destport_encoded),
-    .destport_in_encoded(destport_in_encoded),
-    .destport_one_hot(destport_one_hot),
-    .ss_port_hdr_flit(ss_port_hdr_flit),
-    .dest_e_addr_in(dest_e_addr_in),
-
-    .ss_port_nonhdr_flit(ss_port_nonhdr_flit)
-//synthesis translate_off
-//synopsys  translate_off
-    ,.clk(clk),
-    .ivc_num_getting_sw_grant(ivc_num_getting_sw_grant),
-    .hdr_flg(hdr_flg)
-//synopsys  translate_on  
-//synthesis translate_on
-  
-);
-
-
-// check if ss_ovc is ready
-wire ss_ovc_ready;
-
-wire assigned_ss_ovc_ready;
-assign assigned_ss_ovc_ready= ss_port_nonhdr_flit & assigned_to_ssovc & assigned_ovc_not_full;
-assign ss_ovc_ready = (ovc_is_assigned)?assigned_ss_ovc_ready : ovc_avalable_in_ss_port; 
-
-// check if ssa is permited by input port
-
-wire ssa_permited_by_iport;
-
-
-generate
-if (SSA_EN_IN_PORT) begin : enable
-    assign ssa_permited_by_iport = ss_ovc_ready & (~ivc_request) & condition_1_2_valid;  
-end else begin : disabled
-    assign ssa_permited_by_iport = 1'b0;
-end
-
-endgenerate
-
-/*********************************
- check incomming packet conditions 
- *****************************/
- wire ss_vc_wr, decrease_credit_pre,allocate_ss_ovc_pre,release_ss_ovc_pre;
- assign ss_vc_wr = flit_in_wr & vc_num_in[V_LOCAL];
- assign decrease_credit_pre= ~(hdr_flg & (~ss_port_hdr_flit));
- assign allocate_ss_ovc_pre= hdr_flg & ss_port_hdr_flit;
- assign release_ss_ovc_pre= (single_flit_pck)? decrease_credit_pre : tail_flg;
-
-
-// generate output signals
-assign ivc_reset =  release_ss_ovc_pre & ss_vc_wr & ssa_permited_by_iport  ;
-assign decreased_credit_in_ss_ovc= decrease_credit_pre & ss_vc_wr & ssa_permited_by_iport;
-assign ivc_num_getting_sw_grant= decreased_credit_in_ss_ovc;
-assign ivc_num_getting_ovc_grant= allocate_ss_ovc_pre & ss_vc_wr & ssa_permited_by_iport;
-assign ovc_released = ivc_reset & ~single_flit_pck;
-assign ovc_allocated= ivc_num_getting_ovc_grant & ~single_flit_pck;
-
-
- always @(*)begin
-    granted_ovc_num={V{1'b0}};
-    granted_ovc_num[V_LOCAL]= ivc_num_getting_ovc_grant;   
- end
- 
-  
-
+    ssa_check_destport #(
+        .SW_LOC(SW_LOC),
+        .SS_PORT(SS_PORT)
+    ) check_destport (
+        .destport_encoded(destport_encoded),
+        .destport_in_encoded(destport_in_encoded),
+        .destport_one_hot(destport_one_hot),
+        .ss_port_hdr_flit(ss_port_hdr_flit),
+        .dest_e_addr_in(dest_e_addr_in),
+        .ss_port_nonhdr_flit(ss_port_nonhdr_flit)
+    `ifdef SIMULATION
+        ,.clk(clk),
+        .ivc_num_getting_sw_grant(ivc_num_getting_sw_grant),
+        .hdr_flg(hdr_flg)
+    `endif
+    );    
+    
+    // check if ss_ovc is ready
+    wire ss_ovc_ready;
+    wire assigned_ss_ovc_ready;
+    assign assigned_ss_ovc_ready= ss_port_nonhdr_flit & assigned_to_ssovc & assigned_ovc_not_full;
+    assign ss_ovc_ready = (ovc_is_assigned)?assigned_ss_ovc_ready : ovc_avalable_in_ss_port; 
+    // check if ssa is permited by input port
+    wire ssa_permited_by_iport;
+    assign ssa_permited_by_iport =  (SSA_EN_IN_PORT)?  
+        ss_ovc_ready & (~ivc_request) & condition_1_2_valid :
+        1'b0;
+    /*********************************
+    * check incomming packet conditions 
+    *********************************/
+    wire ss_vc_wr, decrease_credit_pre,allocate_ss_ovc_pre,release_ss_ovc_pre;
+    assign ss_vc_wr = flit_in_wr & vc_num_in[V_LOCAL];
+    assign decrease_credit_pre= ~(hdr_flg & (~ss_port_hdr_flit));
+    assign allocate_ss_ovc_pre= hdr_flg & ss_port_hdr_flit;
+    assign release_ss_ovc_pre= (single_flit_pck)? decrease_credit_pre : tail_flg;
+    
+    // generate output signals
+    assign ivc_reset =  release_ss_ovc_pre & ss_vc_wr & ssa_permited_by_iport  ;
+    assign decreased_credit_in_ss_ovc= decrease_credit_pre & ss_vc_wr & ssa_permited_by_iport;
+    assign ivc_num_getting_sw_grant= decreased_credit_in_ss_ovc;
+    assign ivc_num_getting_ovc_grant= allocate_ss_ovc_pre & ss_vc_wr & ssa_permited_by_iport;
+    assign ovc_released = ivc_reset & ~single_flit_pck;
+    assign ovc_allocated= ivc_num_getting_ovc_grant & ~single_flit_pck;
+    
+    always_comb begin
+        granted_ovc_num={V{1'b0}};
+        granted_ovc_num[V_LOCAL]= ivc_num_getting_ovc_grant;   
+    end   
 endmodule
 
 
 
 module ssa_check_destport #(
-    parameter NOC_ID=0,
     parameter SW_LOC = 0,
-    parameter P=5,
     parameter SS_PORT=0
-)
-	(
+) (
     destport_encoded, //non header flit dest port
     destport_in_encoded, // header flit packet dest port
     ss_port_hdr_flit, // asserted if the header incomming flit goes to ss port
     ss_port_nonhdr_flit, // assert if the body or tail incomming flit goes to ss port
     dest_e_addr_in,
-    destport_one_hot
-    
-//synthesis translate_off 
-//synopsys  translate_off
+    destport_one_hot    
+    `ifdef SIMULATION
     ,clk,
     ivc_num_getting_sw_grant,
     hdr_flg
-//synopsys  translate_on
-//synthesis translate_on    
+    `endif  
 );
-   
-
-	`NOC_CONF
-
-
-
-
-//synthesis translate_off 
-//synopsys  translate_off
-    input clk,   ivc_num_getting_sw_grant, hdr_flg;
-//synopsys  translate_on
-//synthesis translate_on    
-
+    import pronoc_pkg::*;
+    `ifdef SIMULATION
+    input clk, ivc_num_getting_sw_grant, hdr_flg;
+    `endif  
     input [DSTPw-1 : 0] destport_encoded, destport_in_encoded; 
     input [MAX_P-1 : 0] destport_one_hot; // buffered flit destination port
     input [DAw-1 : 0]  dest_e_addr_in;
     output ss_port_hdr_flit, ss_port_nonhdr_flit;
-
+    
     generate
-    /* verilator lint_off WIDTH */
-    if(TOPOLOGY == "FATTREE") begin : fat
-    /* verilator lint_on WIDTH */
-       
-       fattree_ssa_check_destport #(
-        .DSTPw(DSTPw),
-        .SS_PORT(SS_PORT)
-       )
-       check_destport
-       (
-        .destport_encoded(destport_encoded),
-        .destport_in_encoded(destport_in_encoded),
-        .ss_port_hdr_flit(ss_port_hdr_flit),
-        .ss_port_nonhdr_flit(ss_port_nonhdr_flit)
-       );
-     /* verilator lint_off WIDTH */
-    end else if (TOPOLOGY == "MESH" || TOPOLOGY == "TORUS" ) begin : mesh
-    /* verilator lint_on WIDTH */
-     
-        mesh_torus_ssa_check_destport #(
-            .ROUTE_TYPE(ROUTE_TYPE),
-            .SW_LOC(SW_LOC),
-            .P(P),
-            .DEBUG_EN(DEBUG_EN),
+    if(IS_FATTREE) begin : fat
+        fattree_ssa_check_destport #(
             .DSTPw(DSTPw),
             .SS_PORT(SS_PORT)
-        )
-        destport_check
-        (
+        ) check_destport (
             .destport_encoded(destport_encoded),
             .destport_in_encoded(destport_in_encoded),
             .ss_port_hdr_flit(ss_port_hdr_flit),
             .ss_port_nonhdr_flit(ss_port_nonhdr_flit)
-            //synthesis translate_off 
-            //synopsys  translate_off
+        );
+    end else if (IS_MESH | IS_TORUS ) begin : D2_
+        two_dim_ssa_check_destport #(
+            .SW_LOC(SW_LOC),
+            .SS_PORT(SS_PORT)
+        ) destport_check (
+            .destport_encoded(destport_encoded),
+            .destport_in_encoded(destport_in_encoded),
+            .ss_port_hdr_flit(ss_port_hdr_flit),
+            .ss_port_nonhdr_flit(ss_port_nonhdr_flit)
+            `ifdef SIMULATION
             ,.clk(clk),
             .ivc_num_getting_sw_grant(ivc_num_getting_sw_grant),
             .hdr_flg(hdr_flg)
-            //synopsys  translate_on
-            //synthesis translate_on 
-
+            `endif
         ); 
-    /* verilator lint_off WIDTH */
-    end else if (TOPOLOGY == "FMESH") begin :fmesh
-    /* verilator lint_on WIDTH */
-    	localparam 
-    		ELw = log2(T3),
-    		Pw  = log2(P),
-    		PLw = (TOPOLOGY == "FMESH") ? Pw : ELw;
-    		
-    	wire [Pw-1 : 0] endp_p_in;
-    	wire [MAX_P-1 : 0] destport_one_hot_in;
-    	
-    	fmesh_endp_addr_decode #(
-    			.T1(T1),
-    			.T2(T2),
-    			.T3(T3),
-    			.EAw(EAw)
-    		)
-    		endp_addr_decode
-    		(
-    			.e_addr(dest_e_addr_in),
-    			.ex(),
-    			.ey(),
-    			.ep(endp_p_in),
-    			.valid()
-    		);
-    	
-    	destp_generator #(
-    			.TOPOLOGY(TOPOLOGY),
-    			.ROUTE_NAME(ROUTE_NAME),
-    			.ROUTE_TYPE(ROUTE_TYPE),
-    			.T1(T1),
-    			.NL(T3),
-    			.P(P),
-    			.DSTPw(DSTPw),
-    			.PLw(PLw),
-    			.PPSw(PPSw),
-    			.SELF_LOOP_EN (SELF_LOOP_EN),
-    			.SW_LOC(SW_LOC),
-    			.CAST_TYPE(CAST_TYPE)
-    		)
-    		decoder
-    		(
-    			.destport_one_hot (destport_one_hot_in),
-    			.dest_port_encoded(destport_in_encoded),             
-    			.dest_port_out( ),   
-    			.endp_localp_num(endp_p_in),
-    			.swap_port_presel(1'b0),
-    			.port_pre_sel({PPSw{1'b0}}),
-    			.odd_column(1'b0)
-    		);
-    	
-    	
-    assign ss_port_nonhdr_flit = destport_one_hot [SS_PORT];     	
-    assign ss_port_hdr_flit    = destport_one_hot_in [SS_PORT]; 
-    
-	end else begin : line
-            line_ring_ssa_check_destport #(
-               .ROUTE_TYPE(ROUTE_TYPE),
-                .SW_LOC(SW_LOC),
-                .P(P),
-                .DEBUG_EN(DEBUG_EN),
-                .DSTPw(DSTPw),
-                .SS_PORT(SS_PORT)
-            )
-            destport_check
-            (
-                .destport_encoded(destport_encoded),
-                .destport_in_encoded(destport_in_encoded),
-                .ss_port_hdr_flit(ss_port_hdr_flit),
-                .ss_port_nonhdr_flit(ss_port_nonhdr_flit)    
-            );
-    
-     end
+    end else if (IS_FMESH) begin :fmesh
+        localparam 
+            ELw = log2(T3),
+            Pw  = log2(MAX_P);
+            
+        wire [Pw-1 : 0] endp_p_in;
+        wire [MAX_P-1 : 0] destport_one_hot_in;
+        assign endp_p_in = dest_e_addr_in[DAw-1 : DAw-Pw];
+        destp_generator #(
+            .P(MAX_P),
+            .SW_LOC(SW_LOC)
+        ) decoder (
+            .destport_one_hot (destport_one_hot_in),
+            .dest_port_encoded(destport_in_encoded),
+            .dest_port_out( ),   
+            .endp_localp_num(endp_p_in),
+            .swap_port_presel(1'b0),
+            .port_pre_sel({PPSw{1'b0}}),
+            .odd_column(1'b0)
+        );
+        assign ss_port_nonhdr_flit = destport_one_hot [SS_PORT];
+        assign ss_port_hdr_flit    = destport_one_hot_in [SS_PORT]; 
+    end else if(IS_LINE | IS_RING) begin : D1_
+        one_dim_ssa_check_destport #(
+            .SW_LOC(SW_LOC),
+            .SS_PORT(SS_PORT)
+        ) destport_check (
+            .destport_encoded(destport_encoded),
+            .destport_in_encoded(destport_in_encoded),
+            .ss_port_hdr_flit(ss_port_hdr_flit),
+            .ss_port_nonhdr_flit(ss_port_nonhdr_flit)
+        );
+    end else begin : other
+        logic [MAX_P-1 : 0] destport_one_hot_in;
+        always @(*) begin 
+            destport_one_hot_in = '0;
+            //for deterministic routing destination port is decimal encoded
+            if(IS_DETERMINISTIC) destport_one_hot_in[destport_in_encoded] = 1'b1;
+            //for non-deterministic routing destination port is one-hot encoded
+            else destport_one_hot_in [DSTPw-1 : 0] = destport_in_encoded;
+        end
+        assign ss_port_nonhdr_flit = destport_one_hot [SS_PORT];
+        assign ss_port_hdr_flit    = destport_one_hot_in [SS_PORT]; 
+    end
     endgenerate
-
-
 endmodule
 
 
 /**************************
-            add_ss_port
-If no output is granted replace the output port with ss one
+*            add_ss_port
+*If no output is granted replace 
+*the output port with ss one
 **************************/
- 
-
 module add_ss_port #(
-    parameter NOC_ID=0,
-    parameter SW_LOC=0,    
- 	parameter P=5
+    parameter SW_LOC=0,
+    parameter P=5
 )(
     destport_in,
     destport_out 
 );
-
-
-	`NOC_CONF
-
-
-	localparam SS_PORT = strieght_port(P,SW_LOC);
-	localparam DISABLED = P;   
-    localparam P_1     =   ( SELF_LOOP_EN=="NO")?  P-1 : P;   
-         
-    input  [P_1-1  :   0] destport_in;
-    output [P_1-1  :   0] destport_out; 
+    import pronoc_pkg::*;
+    localparam SS_PORT = strieght_port(P,SW_LOC);
+    localparam DISABLED = P;
+    localparam P_1 = (SELF_LOOP_EN )?  P : P-1;
     
-    generate	
-    if(SS_PORT == DISABLED) begin :no_ss
-    	assign destport_out = destport_in;    
-    end else begin : ss 
-    	reg [P_1-1  :   0] destport_temp; 
-    	/* verilator lint_off WIDTH */
-    	if( SELF_LOOP_EN=="YES") begin : slp
-    	/* verilator lint_on WIDTH */
-    		always @(*)begin 
-				destport_temp=destport_in;
-				if(destport_in=={P_1{1'b0}}) destport_temp[SS_PORT]= 1'b1;
-    		end 
-    		assign destport_out = destport_temp;
-    	end else begin : nslp
-    		localparam SS_PORT_CODE = (SW_LOC>SS_PORT) ? SS_PORT : SS_PORT-1;
-    		always @(*)begin 
-    			destport_temp=destport_in;
-    			if(destport_in=={P_1{1'b0}}) begin 
-    				destport_temp[SS_PORT_CODE]= 1'b1;
-    			end
-    		end 
-    		assign destport_out = destport_temp;    	
-    	end     	
-    end //ss
-    endgenerate
-        
+    input  [P_1-1 : 0] destport_in;
+    output [P_1-1 : 0] destport_out;
+    logic [P_1-1 : 0] destport_temp;
+    localparam SS_PORT_CODE = 
+        (SS_PORT == DISABLED) ? 0 :
+        (SELF_LOOP_EN) ? SS_PORT :
+        (SW_LOC > SS_PORT) ? SS_PORT : SS_PORT - 1;
+    always_comb begin
+        destport_temp = destport_in;
+        if (destport_in == {P_1{1'b0}}) begin
+            if((SS_PORT != DISABLED)) destport_temp[SS_PORT_CODE] = 1'b1;
+        end
+    end
+    assign destport_out = (SS_PORT == DISABLED)? destport_in : destport_temp;
 endmodule
-
diff --git a/mpsoc/rtl/src_noc/star_noc.sv b/mpsoc/rtl/src_noc/star_noc.sv
index 4ac061a..0c62740 100644
--- a/mpsoc/rtl/src_noc/star_noc.sv
+++ b/mpsoc/rtl/src_noc/star_noc.sv
@@ -1,79 +1,95 @@
 `include "pronoc_def.v"
+/**********************************************************************
+**    File:  star_noc_top.v
+**    
+**    Copyright (C) 2014-2017  Alireza Monemi
+**    
+**    This file is part of ProNoC 
+**
+**    ProNoC ( stands for Prototype Network-on-chip)  is free software: 
+**    you can redistribute it and/or modify it under the terms of the GNU
+**    Lesser General Public License as published by the Free Software Foundation,
+**    either version 2 of the License, or (at your option) any later version.
+**
+**     ProNoC is distributed in the hope that it will be useful, but WITHOUT
+**     ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+**     or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
+**     Public License for more details.
+**
+**     You should have received a copy of the GNU Lesser General Public
+**     License along with ProNoC. If not, see <http:**www.gnu.org/licenses/>.
+**
+**
+**    Description:
+**    
+**    Star Topology NoC
+**
+**    This module implements a Star Network-on-Chip (NoC) topology.
+**    In this design, a single central router connects directly to 
+**    multiple endpoints through its ports. All communication between 
+**    endpoints is routed through this central hub, enabling simple 
+**    and efficient data transfer in small-scale networks.
+**
+**    Key Features:
+**    - Single central router with multiple ports.
+**    - All ports are directly connected to endpoints.
+**    - Simplified routing with minimal latency for star configurations.
+**
+**********************************************************************/
 
-/**************************************
- * Module: tree
- * Date:2019-01-01  
- * Author: alireza     
- *
- * 
-Description: 
-
-    Star      
-
- ***************************************/
-
- 
-module  star_noc_top #(
-	parameter NOC_ID=0
-) (
-		reset,
-		clk,    
-		chan_in_all,
-		chan_out_all,
-		router_event
-	);
-  
-  	`NOC_CONF
-  
-	input   clk,reset;
-	//Endpoints ports 
-	input   smartflit_chanel_t chan_in_all  [NE-1 : 0];
-	output  smartflit_chanel_t chan_out_all [NE-1 : 0];
-	
-	//Events
-	output  router_event_t  router_event [NR-1 : 0][MAX_P-1 : 0];
-		  
- 
-	    router_top # (
-			.NOC_ID(NOC_ID),
-			.P(NE)
-		)
-		the_router
-		(              
-			.current_r_id    (0),
-			.current_r_addr  (1'b0), 
-			.chan_in         (chan_in_all), 
-			.chan_out        (chan_out_all), 
-			.router_event    (router_event[0]),
-			.clk             (clk            ), 
-			.reset           (reset          )
-		);
-	
-
+module  star_noc_top  (
+    reset,
+    clk,
+    chan_in_all,
+    chan_out_all,
+    router_event
+);
+    
+    import pronoc_pkg::*;
+    input   clk,reset;
+    //Endpoints ports 
+    input   smartflit_chanel_t chan_in_all  [NE-1 : 0];
+    output  smartflit_chanel_t chan_out_all [NE-1 : 0];
+    
+    //Events
+    output  router_event_t  router_event [NR-1 : 0][MAX_P-1 : 0];
+    router_config_t router_config_in;
+    assign router_config_in.router_addr = '0;
+    assign router_config_in.router_id ='0;
+    router_top # (
+        .ROUTER_ID(0),
+        .P(NE)
+    ) the_router (
+        .router_config_in(router_config_in),
+        .chan_in         (chan_in_all), 
+        .chan_out        (chan_out_all), 
+        .router_event    (router_event[0]),
+        .clk             (clk            ), 
+        .reset           (reset          )
+    );
+    
 endmodule
 
-
 module star_conventional_routing #(
-		parameter NE                = 8		
-		)
-		(	
-		dest_e_addr,
-		destport
-);    
-
-	function integer log2;
-		input integer number; begin   
-			log2=(number <=1) ? 1: 0;    
-			while(2**log2<number) begin    
-				log2=log2+1;    
-			end        
-		end   
-	endfunction // log2 
-  	
-	localparam EAw = log2(NE);      
-
-	input   [EAw-1   :0] dest_e_addr;
-	output  [EAw-1   :0] destport;
-	// the destination endpoint address & connection port number are the same in star topology
-	assign destport = dest_e_addr;
-endmodule	
+    parameter NE = 8
+)(
+    dest_e_addr,
+    destport
+);
+    
+    function integer log2;
+        input integer number; begin
+            log2=(number <=1) ? 1: 0;
+            while(2**log2<number) begin
+                log2=log2+1;
+            end
+        end
+    endfunction // log2 
+    
+    localparam EAw = log2(NE);
+    
+    input   [EAw-1   :0] dest_e_addr;
+    output  [EAw-1   :0] destport;
+    // the destination endpoint address & connection port number are the same in star topology
+    assign destport = dest_e_addr;
+endmodule
\ No newline at end of file
diff --git a/mpsoc/rtl/src_noc/topology_localparam.v b/mpsoc/rtl/src_noc/topology_localparam.v
index 8b33bdb..c6edc46 100644
--- a/mpsoc/rtl/src_noc/topology_localparam.v
+++ b/mpsoc/rtl/src_noc/topology_localparam.v
@@ -1,474 +1,536 @@
+`include "pronoc_def.v"
 /**************************************
 * Module: localparameter
-* Date:2019-04-08  
-* Author: alireza     
+* Date:2019-04-08
+* Author: alireza
 *
 * Description: 
 ***************************************/
- `ifdef     INCLUDE_TOPOLOGY_LOCALPARAM
- 
-     //MESH, TORUS Topology p=5           
-    localparam    LOCAL   =   0,
-                  EAST    =   1,
-                  NORTH   =   2, 
-                  WEST    =   3,
-                  SOUTH   =   4;
-                   
-               
-      
-    //LINE RING Topology p=3           
-    localparam  FORWARD =  1,
-                BACKWARD=  2;
-                
-     
-     function automatic integer log2;
-      input integer number; begin   
-         log2=(number <=1) ? 1: 0;    
-         while(2**log2<number) begin    
-            log2=log2+1;    
-         end       
-      end   
+`ifdef INCLUDE_TOPOLOGY_LOCALPARAM
+    
+    localparam [0:0]
+        /* verilator lint_off WIDTH */
+        IS_LINE =  (TOPOLOGY == "LINE"),
+        IS_RING =  (TOPOLOGY == "RING"),
+        IS_MESH =  (TOPOLOGY == "MESH"),
+        IS_FMESH=  (TOPOLOGY == "FMESH"),
+        IS_TORUS=  (TOPOLOGY == "TORUS"),
+        IS_FATTREE=(TOPOLOGY == "FATTREE"),
+        IS_TREE=   (TOPOLOGY == "TREE"),
+        IS_STAR=   (TOPOLOGY == "STAR"),
+        IS_MULTI_MESH=(TOPOLOGY == "MULTI_MESH"),
+        IS_MESH_3D= (TOPOLOGY == "MESH_3D"),
+        IS_REGULAR_TOPO = (IS_RING | IS_LINE | IS_MESH | IS_TORUS | IS_MESH_3D),
+        IS_1D_TOPO = (IS_LINE | IS_RING),
+        IS_2D_TOPO = (IS_MESH | IS_TORUS | IS_FMESH),
+        IS_3D_TOPO = (IS_MESH_3D | IS_MULTI_MESH),
+        IS_MULTI_ENDP_ROUTER = (T3 > 1) ;
+        /* verilator lint_on WIDTH */ 
+    
+    localparam [0:0]
+        /* verilator lint_off WIDTH */
+        IS_RRA = (SWA_ARBITER_TYPE == "RRA"),
+        IS_WRRA = (SWA_ARBITER_TYPE == "WRRA"),
+        IS_SINGLE_FLIT = (PCK_TYPE == "SINGLE_FLIT"),
+        IS_MULTI_FLIT = (PCK_TYPE == "MULTI_FLIT"),
+        IS_COMB_SPEC2 = (COMBINATION_TYPE == "COMB_SPEC2"),
+        IS_COMB_SPEC1 = (COMBINATION_TYPE == "COMB_SPEC1"),
+        IS_COMB_NONSPEC = (COMBINATION_TYPE == "COMB_NONSPEC"),
+        IS_MULTICAST_FULL = (CAST_TYPE == "MULTICAST_FULL"),
+        IS_MULTICAST_PARTIAL = (CAST_TYPE == "MULTICAST_PARTIAL"),
+        IS_BROADCAST_PARTIAL = (CAST_TYPE == "BROADCAST_PARTIAL"),
+        IS_UNICAST = (CAST_TYPE == "UNICAST"),
+        IS_BROADCAST_FULL = (CAST_TYPE == "BROADCAST_FULL"),
+        IS_ONE_HOT_MUX = (MUX_TYPE == "ONE_HOT"),
+        IS_VCA_ATOMIC = (VC_REALLOCATION_TYPE == "ATOMIC"),
+        IS_LOOKAHEAD = ( ROUTE_MODE=="LOOKAHEAD");
+        /* verilator lint_on WIDTH */
+    
+    //MESH, TORUS Topology p=5
+    localparam    
+        LOCAL   =   0,
+        EAST    =   1,
+        NORTH   =   2, 
+        WEST    =   3,
+        SOUTH   =   4;
+    //MULTI_MESH
+    localparam 
+        UP = 5,
+        DOWN=6;
+    
+    //LINE RING Topology p=3
+    localparam  
+        FORWARD =  1,
+        BACKWARD=  2;
+    
+    function automatic integer log2;
+    input integer number;
+    begin   
+        log2=(number <=1) ? 1: 0;
+        while(2**log2<number) begin
+            log2=log2+1;
+        end
+    end
     endfunction // log2 
     
-     function automatic integer powi; // x^y
-        input integer x,y;
-        integer i;begin //compute x to the y
+    function automatic integer powi; // x^y
+    input integer x,y;
+    integer i;
+    begin //compute x to the y
         powi=1;
         for (i = 0; i <y; i=i+1 ) begin 
             powi=powi * x;
         end
-        end   
+    end   
     endfunction // powi
     
-    
     function automatic integer  sum_powi;//x^(y-1) + x^(y-2) + ...+ 1;
-        input integer x,y;
-        integer i;begin 
+    input integer x,y;
+    integer i;
+    begin 
         sum_powi = 0;
         for (i = 0; i < y; i=i+1)begin
             sum_powi = sum_powi + powi( x, i );
-       end
+        end
     end   
     endfunction // sum_powi
     
-   
     // get the port num and return the port located at streight direction. If there is no strieght port return  router_port_num. 
     function automatic integer strieght_port;
-        input integer router_port_num;  //router port num
-        input integer current_port;
-        begin 
-        /* verilator lint_off WIDTH */ 
-        if(TOPOLOGY == "MESH" || TOPOLOGY == "FMESH" || TOPOLOGY == "TORUS") begin 
-        /* verilator lint_on WIDTH */ 
+    input integer router_port_num;  //router port num
+    input integer current_port;
+    begin 
+        if(IS_2D_TOPO | IS_3D_TOPO) begin 
             strieght_port = 
-                (current_port== EAST)?  WEST:
-                (current_port== WEST)?  EAST:
-                (current_port== SOUTH)? NORTH:
-                (current_port== NORTH)? SOUTH:
-                                 router_port_num; //DISABLED;
-        end
-        /* verilator lint_off WIDTH */ 
-        else if (TOPOLOGY ==  "RING" || TOPOLOGY ==  "LINE") begin 
-        /* verilator lint_on WIDTH */ 
+                (current_port == EAST)?  WEST:
+                (current_port == WEST)?  EAST:
+                (current_port == SOUTH)? NORTH:
+                (current_port == NORTH)? SOUTH:
+                (IS_3D_TOPO && current_port== UP)? DOWN: 
+                (IS_3D_TOPO && current_port== DOWN)? UP:
+                router_port_num; //DISABLED;
+        end else if (IS_1D_TOPO) begin 
             strieght_port = 
                 (current_port== FORWARD )? BACKWARD:
                 (current_port== BACKWARD)? FORWARD:
-                                           router_port_num; //DISABLED;
-        
-        end
-        /* verilator lint_off WIDTH */ 
-        else if (TOPOLOGY == "FATTREE" ) begin 
-        /* verilator lint_on WIDTH */ 
-             if(router_port_num[0]==1'b0) begin //even port num
-                 strieght_port =   (current_port < (router_port_num/2) )?
-                    (router_port_num/2)+ current_port : 
+                    router_port_num; //DISABLED;
+        end else if (IS_FATTREE ) begin 
+            if((router_port_num & 1) == 0) begin // even port
+                    strieght_port =   
+                    (current_port < (router_port_num/2) )? (router_port_num/2)+ current_port : 
                     current_port - (router_port_num/2);
-             end else begin 
-                 strieght_port =  (current_port == (router_port_num-1)/2) ?  router_port_num: //DISABLED;
-                                  (current_port < ((router_port_num+1)/2))? ((router_port_num+1)/2)+ current_port : 
-                                                                            current_port - ((router_port_num+1)/2);
-        
-             end
+            end else begin 
+                strieght_port = 
+                    (current_port == (router_port_num-1)/2) ?  router_port_num: //DISABLED;
+                    (current_port < ((router_port_num+1)/2))? ((router_port_num+1)/2)+ current_port : 
+                    current_port - ((router_port_num+1)/2);
+            end
         end else begin 
             strieght_port = router_port_num; //DISABLED;
         end
-        end
+    end
     endfunction
     
-    
     function automatic integer port_buffer_size;
-        input integer router_port_num;  //router port num
-        begin
+    input integer router_port_num;  //router port num
+    begin
         port_buffer_size = B;
-        /* verilator lint_off WIDTH */ 
-        if(TOPOLOGY == "MESH" || TOPOLOGY == "FMESH" || TOPOLOGY == "TORUS" || TOPOLOGY ==  "RING" || TOPOLOGY ==  "LINE")begin 
-        /* verilator lint_on WIDTH */ 
-           if (router_port_num == 0 || router_port_num > 4 ) port_buffer_size = LB;
-        end        
+        if(IS_1D_TOPO) begin 
+            if (router_port_num == 0 || router_port_num > BACKWARD ) port_buffer_size = LB;
+        end else if (IS_2D_TOPO) begin
+            if (router_port_num == 0 || router_port_num > SOUTH ) port_buffer_size = LB;
+        end else if (IS_3D_TOPO && !IS_MULTI_MESH) begin
+            if (router_port_num == 0 || router_port_num > DOWN) port_buffer_size = LB;
         end
+    end
     endfunction
-  
     
-       
-    
-    
-/*******************
-*   "RING"  "LINE"  "MESH" TORUS" "FMESH"
-******************/
-
-
-
-
-/* verilator lint_off WIDTH */
-//route type
-localparam 
-    NX = T1,
-    NY = T2,    
-    NL = T3,
-    NXw = log2(NX),
-    NYw= log2(NY),
-    NLw= log2(NL),
-    PPSw_MESH_TORI =4, //port presel width for adaptive routing
+    /*******************
+    *   REGULAR_TOPO: "RING"  "LINE"  "MESH" TORUS" "FMESH" "MESH_3D"
+    ******************/
+    localparam 
+        NX = T1,
+        NY = (IS_1D_TOPO) ? 1 : T2,
+        NL = (IS_3D_TOPO)? T4 : T3,
+        NZ = (IS_3D_TOPO)? T3 : 1,
+        NXw = log2(NX),
+        NYw = log2(NY),
+        NLw = log2(NL),
+        NZw= log2(NZ),
+        PPSw_REGULAR = 4, //port presel width for adaptive routing
+        /* verilator lint_off WIDTH */
+        ROUTE_TYPE_REGULAR = 
+            (ROUTE_NAME == "DOR" || ROUTE_NAME == "TRANC_DOR" )? "DETERMINISTIC" :
+            (ROUTE_NAME == "FULL_ADPT" || ROUTE_NAME == "TRANC_FULL_ADPT" )?   "FULL_ADAPTIVE": "PAR_ADAPTIVE",
+        /* verilator lint_on WIDTH */
+        R2R_CHANELS_REGULAR=  (IS_1D_TOPO)? 2 : (IS_3D_TOPO)? 6 : 4,
+        R2E_CHANELS_REGULAR= NL,
+        RAw_REGULAR = ( IS_1D_TOPO )? NXw : (IS_3D_TOPO)? NXw + NYw + NZw : NXw + NYw,
+        EAw_REGULAR = (NL==1 ) ? RAw_REGULAR : RAw_REGULAR + NLw,
+        NR_REGULAR = (IS_1D_TOPO)? NX :(IS_3D_TOPO)? NX*NY*NZ : NX*NY,
+        NE_REGULAR = NR_REGULAR * NL,
+        MAX_P_REGULAR = R2R_CHANELS_REGULAR + R2E_CHANELS_REGULAR,
+        DSTPw_REGULAR = (IS_3D_TOPO)? log2(MAX_P_REGULAR) : R2R_CHANELS_REGULAR, // P-1
+        NE_PER_R_REGULAR = NL;
     
-    /* verilator lint_off WIDTH */     
-    ROUTE_TYPE_MESH_TORI = (ROUTE_NAME == "XY" || ROUTE_NAME == "TRANC_XY" )?    "DETERMINISTIC" : 
-                               (ROUTE_NAME == "DUATO" || ROUTE_NAME == "TRANC_DUATO" )?   "FULL_ADAPTIVE": "PAR_ADAPTIVE",
-
-    R2R_CHANELS_MESH_TORI=  (TOPOLOGY=="RING" || TOPOLOGY=="LINE")? 2 : 4,   
-    R2E_CHANELS_MESH_TORI= NL,    
-    RAw_MESH_TORI = ( TOPOLOGY == "RING" || TOPOLOGY == "LINE")? NXw : NXw + NYw,
-    EAw_MESH_TORI = (NL==1) ? RAw_MESH_TORI : RAw_MESH_TORI + NLw,
-    NR_MESH_TORI = (TOPOLOGY=="RING" || TOPOLOGY=="LINE")? NX : NX*NY,
-    NE_MESH_TORI = NR_MESH_TORI * NL,
-    MAX_P_MESH_TORI = R2R_CHANELS_MESH_TORI + R2E_CHANELS_MESH_TORI,
-    DSTPw_MESH_TORI = R2R_CHANELS_MESH_TORI; // P-1
-   
-    /* verilator lint_on WIDTH */    
-     
-/****************
- *  FMESH
- * *************/
- localparam    
-    NE_FMESH = NE_MESH_TORI + 2 * (NX+NY),
-    NR_FMESH = NR_MESH_TORI,
-    MAX_P_FMESH = 4 + NL, 
-    EAw_FMESH = RAw_MESH_TORI + log2(MAX_P_FMESH);
-        
- 
- /******************
-  *     FATTREE
-  * *****************/
-localparam 
-    K=T1,
-    L=T2, 
-    Lw=log2(L),
-    Kw=log2(K),
-    LKw=L*Kw,
-    RAw_FATTREE =  LKw + Lw,
-    EAw_FATTREE  = LKw,
-    NE_FATTREE = powi( K,L ), 
-    NR_FATTREE = L * powi( K , L - 1 ),  // total number of routers  
-    ROUTE_TYPE_FATTREE = "DETERMINISTIC",
-    DSTPw_FATTREE = K+1,
-    MAX_P_FATTREE = 2*K,
-    DAw_MCAST_FATTREE= powi( K,L); 
-        
-   
-        
-/**********************
- *      TREE
- * ********************/
-localparam 
-    ROUTE_TYPE_TREE = "DETERMINISTIC",
-    NE_TREE = powi( K,L ),  //total number of endpoints
-    NR_TREE = sum_powi ( K,L ),  // total number of routers  
-    RAw_TREE =  LKw + Lw,
-    EAw_TREE  =  LKw,
-    DSTPw_TREE = log2(K+1),
-    MAX_P_TREE = K+1,
-    DAw_MCAST_TREE= DAw_MCAST_FATTREE; 
+    /****************
+    *  FMESH
+    **************/
+    localparam    
+        NE_FMESH = NE_REGULAR + 2 * (NX+NY),
+        NR_FMESH = NR_REGULAR,
+        MAX_P_FMESH = 4 + NL, 
+        EAw_FMESH = RAw_REGULAR + log2(MAX_P_FMESH),
+        NE_PER_R_FMESH = 
+            ((NX == 1) && (NY == 1)) ? NL + 4 :  
+            ((NX == 1) || (NY == 1)) ? NL + 3 : NL + 2; // 2 for the edge ports;
+    /******************
+    *     FATTREE
+    ******************/
+    localparam 
+        K=T1,
+        L=T2, 
+        Lw=log2(L),
+        Kw=log2(K),
+        LKw=L*Kw,
+        RAw_FATTREE =  LKw + Lw,
+        EAw_FATTREE  = LKw,
+        NE_FATTREE = powi( K,L ), 
+        NR_FATTREE = L * powi( K , L - 1 ),  // total number of routers  
+        ROUTE_TYPE_FATTREE = "DETERMINISTIC",
+        DSTPw_FATTREE = K+1,
+        MAX_P_FATTREE = 2*K,
+        DAw_MCAST_FATTREE= powi( K,L),
+        NE_PER_R_FATTREE = K; 
+    /**********************
+    *      TREE
+    *********************/
+    localparam 
+        ROUTE_TYPE_TREE = "DETERMINISTIC",
+        NE_TREE = powi( K,L ),  //total number of endpoints
+        NR_TREE = sum_powi ( K,L ),  // total number of routers  
+        RAw_TREE =  LKw + Lw,
+        EAw_TREE  =  LKw,
+        DSTPw_TREE = log2(K+1),
+        MAX_P_TREE = K+1,
+        DAw_MCAST_TREE= DAw_MCAST_FATTREE,
+        NE_PER_R_TREE = K;
+    /*********************
+    *  STAR
+    *******************/
+    localparam 
+        ROUTE_TYPE_STAR = "DETERMINISTIC",
+        NE_STAR = T1,  //total number of endpoints
+        NR_STAR = 1,  // total number of routers
+        RAw_STAR = 1,
+        EAw_STAR = log2(NE_STAR),
+        DSTPw_STAR = (~IS_UNICAST) ? NE_STAR :EAw_STAR,
+        MAX_P_STAR = NE_STAR,
+        DAw_MCAST_STAR= NE_STAR,
+        NE_PER_R_STAR = NE_STAR;
+    /************************
+    *  CUSTOM - made by netmaker
+    ***********************/
+    localparam 
+        ROUTE_TYPE_CUSTOM = "DETERMINISTIC",
+        NE_CUSTOM  = T1,  // total number of endpoints
+        NR_CUSTOM  = T2,  // total number of routers  
+        EAw_CUSTOM = log2(NE_CUSTOM),
+        RAw_CUSTOM = log2(NR_CUSTOM),
+        MAX_P_CUSTOM = T3,
+        DSTPw_CUSTOM = log2(MAX_P_CUSTOM),
+        NE_PER_R_CUSTOM = MAX_P_CUSTOM;//just take the max possible value as it can be variable per router
+    /***********************
+    *   MULTI_MESH - made by yaml noc generator
+    ************************/
+    localparam 
+        ROUTE_TYPE_MULTI_MESH = "DETERMINISTIC",
+        NE_MULTI_MESH  = T1,  // total number of endpoints
+        NR_MULTI_MESH  = T1,  // total number of routers  
+        RAw_MULTI_MESH = T2,
+        // Endpoint (source) Address width
+        // global_src
+        EAw_MULTI_MESH = T2,
+        MAX_P_MULTI_MESH = 7,
+        DSTPw_MULTI_MESH = log2(MAX_P_MULTI_MESH),
+        // Destination Address width
+        // local_routing_en / next_chip_vdir / destfbits / local_dst / global_dst
+        DAw_MULTI_MESH = 2*T2+log2(MAX_P_MULTI_MESH)+2;
 
-              
-/*********************
- *  STAR
- * ******************/
-  localparam 
-    ROUTE_TYPE_STAR = "DETERMINISTIC",
-    NE_STAR = T1,  //total number of endpoints
-    NR_STAR = 1,  // total number of routers  
-    RAw_STAR = 1,
-    EAw_STAR  =  log2(NE_STAR),
-    DSTPw_STAR = (CAST_TYPE!= "UNICAST")? NE_STAR :EAw_STAR,
-    MAX_P_STAR = NE_STAR,
-    DAw_MCAST_STAR= NE_STAR;            
- 
- /************************
-  *  CUSTOM - made by netmaker
-  * **********************/
- localparam 
-    ROUTE_TYPE_CUSTOM = "DETERMINISTIC",
-    NE_CUSTOM  = T1,  //total number of endpoints
-    NR_CUSTOM  = T2,  // total number of routers  
-    EAw_CUSTOM = log2(NE_CUSTOM),
-    RAw_CUSTOM = log2(NR_CUSTOM),
-    MAX_P_CUSTOM = T3,
-    DSTPw_CUSTOM = log2(MAX_P_CUSTOM);
+    /*************************
+    *   regular_topo address struct
+    **************************/
+    typedef struct packed {
+        logic [NZw-1 : 0] z;
+        logic [NYw-1 : 0] y;
+        logic [NXw-1 : 0] x;
+    } regular_topo_router_addr_t;
+    typedef struct packed {
+        logic [NLw-1 : 0] l;
+        logic [NZw-1 : 0] z;
+        logic [NYw-1 : 0] y;
+        logic [NXw-1 : 0] x;
+    } regular_topo_endp_addr_t;
     
- 
- 
-    /* verilator lint_off WIDTH */ 
     localparam
-        PPSw = PPSw_MESH_TORI,    
+        PPSw = PPSw_REGULAR,
         // maximum number of port in a router in the topology
         MAX_P =
-            (TOPOLOGY == "FATTREE")? MAX_P_FATTREE:
-            (TOPOLOGY == "TREE")?  MAX_P_TREE:
-            (TOPOLOGY == "RING" || TOPOLOGY == "LINE" || TOPOLOGY == "MESH" || TOPOLOGY == "TORUS")? MAX_P_MESH_TORI:
-            (TOPOLOGY == "FMESH")? MAX_P_MESH_TORI:
-            (TOPOLOGY == "STAR") ? MAX_P_STAR:
+            (IS_FATTREE)? MAX_P_FATTREE:
+            (IS_TREE)?  MAX_P_TREE:
+            (IS_REGULAR_TOPO)? MAX_P_REGULAR:
+            (IS_FMESH)? MAX_P_REGULAR:
+            (IS_STAR) ? MAX_P_STAR:
+            (IS_MULTI_MESH) ? MAX_P_MULTI_MESH:
             MAX_P_CUSTOM, 
-        
-        // destination port width in header flit           
+        // destination port width in header flit
         DSTPw =
            // Each asserted bit indicats that the flit should be sent to that port
-            (TOPOLOGY == "FATTREE")? DSTPw_FATTREE:
-            (TOPOLOGY == "TREE")?  DSTPw_TREE:
-            (CAST_TYPE!= "UNICAST")? MAX_P: 
-            (TOPOLOGY == "RING" || TOPOLOGY == "LINE" || TOPOLOGY == "MESH" || TOPOLOGY == "TORUS")? DSTPw_MESH_TORI:
-            (TOPOLOGY == "FMESH")? DSTPw_MESH_TORI:
-            (TOPOLOGY == "STAR") ? DSTPw_STAR:
+            (IS_FATTREE)? DSTPw_FATTREE :
+            (IS_TREE)?  DSTPw_TREE :
+            (~IS_UNICAST) ? MAX_P : 
+            (IS_REGULAR_TOPO)? DSTPw_REGULAR :
+            (IS_FMESH)? DSTPw_REGULAR :
+            (IS_STAR) ? DSTPw_STAR :
+            (IS_MULTI_MESH) ? DSTPw_MULTI_MESH :
             DSTPw_CUSTOM,
-        //router address width        
+        //router address width
         RAw =
-            (TOPOLOGY == "FATTREE")? RAw_FATTREE:
-            (TOPOLOGY == "TREE")?  RAw_TREE:
-            (TOPOLOGY == "RING" || TOPOLOGY == "LINE" || TOPOLOGY == "MESH" || TOPOLOGY == "TORUS")? RAw_MESH_TORI:
-            (TOPOLOGY == "FMESH")? RAw_MESH_TORI:
-            (TOPOLOGY == "STAR") ? RAw_STAR:
+            (IS_FATTREE)? RAw_FATTREE:
+            (IS_TREE)?  RAw_TREE:
+            (IS_REGULAR_TOPO)? RAw_REGULAR:
+            (IS_FMESH)? RAw_REGULAR:
+            (IS_STAR) ? RAw_STAR:
+            (IS_MULTI_MESH) ? RAw_MULTI_MESH:
             RAw_CUSTOM,
         //endpoint address width
         EAw =
-            (TOPOLOGY == "FATTREE")? EAw_FATTREE:
-            (TOPOLOGY == "TREE")?  EAw_TREE:
-            (TOPOLOGY == "RING" || TOPOLOGY == "LINE" || TOPOLOGY == "MESH" || TOPOLOGY == "TORUS")? EAw_MESH_TORI:
-            (TOPOLOGY == "FMESH")? EAw_FMESH:
-            (TOPOLOGY == "STAR") ? EAw_STAR:
-            EAw_CUSTOM,           
-        // total number of endpoints         
+            (IS_FATTREE)? EAw_FATTREE:
+            (IS_TREE)?  EAw_TREE:
+            (IS_REGULAR_TOPO)? EAw_REGULAR:
+            (IS_FMESH)? EAw_FMESH:
+            (IS_STAR) ? EAw_STAR:
+            (IS_MULTI_MESH) ? EAw_MULTI_MESH:
+            EAw_CUSTOM,
+        // total number of endpoints
         NE =
-            (TOPOLOGY == "FATTREE")? NE_FATTREE:
-            (TOPOLOGY == "TREE")?  NE_TREE:
-            (TOPOLOGY == "RING" || TOPOLOGY == "LINE" || TOPOLOGY == "MESH" || TOPOLOGY == "TORUS")? NE_MESH_TORI:
-            (TOPOLOGY == "FMESH")? NE_FMESH: 
-            (TOPOLOGY == "STAR")? NE_STAR:
+            (IS_FATTREE)? NE_FATTREE:
+            (IS_TREE)?  NE_TREE:
+            (IS_REGULAR_TOPO)? NE_REGULAR:
+            (IS_FMESH)? NE_FMESH: 
+            (IS_STAR)? NE_STAR:
+            (IS_MULTI_MESH) ? NE_MULTI_MESH:
             NE_CUSTOM,
             
+        // total number of endpoint per router
+        NE_PER_R =
+            (IS_FATTREE)? NE_PER_R_FATTREE:
+            (IS_TREE)?  NE_PER_R_TREE:
+            (IS_REGULAR_TOPO)? NE_PER_R_REGULAR:
+            (IS_FMESH)? NE_PER_R_FMESH: 
+            (IS_STAR)? NE_PER_R_STAR:
+            (IS_MULTI_MESH) ? 1:
+            NE_PER_R_CUSTOM,    
        //Destination endpoint(s) address width
-      
-              
-        DAw_OFFSETw  =  (TOPOLOGY=="MESH" || TOPOLOGY=="TORUS" ||  TOPOLOGY=="FMESH")?  NX : 0, 
-        
+        DAw_OFFSETw  =  (IS_MESH || IS_TORUS ||  IS_FMESH)?  NX : 0, 
         MCAST_PRTLw = mcast_partial_width( MCAST_ENDP_LIST),
-        
         MCASTw =
-            (CAST_TYPE == "MULTICAST_FULL") ? NE :
-            (CAST_TYPE == "MULTICAST_PARTIAL" && EAw >= MCAST_PRTLw) ? EAw +1 : 
-            (CAST_TYPE == "MULTICAST_PARTIAL" && EAw <  MCAST_PRTLw) ? MCAST_PRTLw +1 :
+            (IS_MULTICAST_FULL) ? NE :
+            ((IS_MULTICAST_PARTIAL==1'b1) && (EAw >= MCAST_PRTLw)) ? EAw +1 : 
+            ((IS_MULTICAST_PARTIAL==1'b1) && (EAw <  MCAST_PRTLw)) ? MCAST_PRTLw +1 :
             EAw +1, //broadcast
-              
-        DAw =  
-            (CAST_TYPE == "UNICAST") ?   EAw:
-            MCASTw +  DAw_OFFSETw,            
-          
-            
-                  
-            
-        //total number of routers        
+        DAw = 
+            (IS_MULTI_MESH) ? DAw_MULTI_MESH :
+            (IS_UNICAST) ?   EAw:
+            MCASTw +  DAw_OFFSETw,
+        //total number of routers
         NR =
-            (TOPOLOGY == "FATTREE")? NR_FATTREE:
-            (TOPOLOGY == "TREE")?  NR_TREE:
-            (TOPOLOGY == "RING" || TOPOLOGY == "LINE" || TOPOLOGY == "MESH" || TOPOLOGY == "TORUS")? NR_MESH_TORI:  
-            (TOPOLOGY == "FMESH")? NR_FMESH: 
-            (TOPOLOGY == "STAR") ? NR_STAR:
+            (IS_FATTREE)? NR_FATTREE:
+            (IS_TREE)?  NR_TREE:
+            (IS_REGULAR_TOPO)? NR_REGULAR:  
+            (IS_FMESH)? NR_FMESH: 
+            (IS_STAR) ? NR_STAR:
+            (IS_MULTI_MESH) ? NR_MULTI_MESH:
             NR_CUSTOM, 
-        //routing algorithm type    
+        //routing algorithm type
         ROUTE_TYPE =
-            (TOPOLOGY == "FATTREE")? ROUTE_TYPE_FATTREE:
-            (TOPOLOGY == "TREE")?  ROUTE_TYPE_TREE:
-            (TOPOLOGY == "RING" || TOPOLOGY == "LINE" || TOPOLOGY == "MESH" || TOPOLOGY == "TORUS")? ROUTE_TYPE_MESH_TORI:
-            (TOPOLOGY == "FMESH")? ROUTE_TYPE_MESH_TORI:
-            (TOPOLOGY == "STAR") ? ROUTE_TYPE_STAR:
+            (IS_FATTREE)? ROUTE_TYPE_FATTREE:
+            (IS_TREE)?  ROUTE_TYPE_TREE:
+            (IS_REGULAR_TOPO)? ROUTE_TYPE_REGULAR:
+            (IS_FMESH)? ROUTE_TYPE_REGULAR:
+            (IS_STAR) ? ROUTE_TYPE_STAR:
             ROUTE_TYPE_CUSTOM;
-        
-    /* verilator lint_on WIDTH */         
- 
- 
-          
-     
-    
+            /* verilator lint_off WIDTH */
+            localparam  [0:0] 
+                IS_DETERMINISTIC = (ROUTE_TYPE == "DETERMINISTIC"),
+                IS_FULL_ADAPTIVE = (ROUTE_TYPE == "FULL_ADAPTIVE");
+            /* verilator lint_on WIDTH */
     
     function automatic integer mcast_id_to_endp_id;
-        input integer  mcast_id;
-        reg [NE-1 : 0] mcast_list;
-        integer  k;
-        begin
-        mcast_list =MCAST_ENDP_LIST;
+    input integer  mcast_id;
+    reg [NE-1 : 0] mcast_list;
+    integer  k;
+    begin
+        mcast_list = NE'(MCAST_ENDP_LIST);
         mcast_id_to_endp_id=0;
         k=0;
-        /* verilator lint_off WIDTH */ 
-        if (CAST_TYPE == "MULTICAST_FULL")begin 
-        /* verilator lint_on WIDTH */ 
+        if (IS_MULTICAST_FULL)begin 
             mcast_id_to_endp_id =mcast_id;
         end else begin
-            while( k!=mcast_id+1) begin              
+            while( k!=mcast_id+1) begin
                 if( mcast_list[mcast_id_to_endp_id]==1'b1) begin 
-                   k=k+1;            
+                    k=k+1;
                 end
-                mcast_id_to_endp_id= mcast_id_to_endp_id+1;       
+                mcast_id_to_endp_id= mcast_id_to_endp_id+1;
             end
         end
-        end
+    end
     endfunction
-      
-   function automatic integer endp_id_to_mcast_id;
-        input integer  endp_id;
-        reg [NE-1 : 0] mcast_list;
-        integer i;       
-        begin
-         /* verilator lint_off WIDTH */ 
-        if (CAST_TYPE == "MULTICAST_FULL") begin
-         /* verilator lint_on WIDTH */ 
+    
+    function automatic integer endp_id_to_mcast_id;
+    input integer  endp_id;
+    reg [NE-1 : 0] mcast_list;
+    integer i;
+    begin
+        if (IS_MULTICAST_FULL) begin
             endp_id_to_mcast_id = endp_id;
         end else begin
-            mcast_list =MCAST_ENDP_LIST;
+            mcast_list =NE'(MCAST_ENDP_LIST);
             endp_id_to_mcast_id=0;
             for (i=0;i<endp_id;i=i+1) begin 
                 if( mcast_list[i]==1'b1) endp_id_to_mcast_id=endp_id_to_mcast_id+1;
             end
             end
-        end
+    end
     endfunction  
     
-  
-    
     function automatic integer mcast_partial_width;
-        input [NE-1 : 0] p;
-        integer i;      
-        begin 
-            
-            mcast_partial_width=0;
-            for (i=0;i<NE;i=i+1) begin
-                if (p [i]==1'b1) mcast_partial_width=mcast_partial_width+1;
-            end
-        end   
-    endfunction
-    
-    
-    
-    
-    function automatic  integer fmesh_addrencode; 
-        input integer in;
-        integer  y, x, l,p, diff,mul;begin
-                        
-            mul  = NX*NY*NL;            
-            if(in < mul) begin 
-                y = ((in/NL) / NX ); 
-                x = ((in/NL) % NX ); 
-                l = (in % NL); 
-                p = (l==0)? LOCAL : 4+l;            
-            end else begin      
-                diff = in -  mul ;
-                if( diff <  NX) begin //top mesh edge 
-                    y = 0;
-                    x = diff;
-                    p = NORTH;
-                end else if  ( diff < 2* NX) begin //bottom mesh edge 
-                    y = NY-1;
-                    x = diff-NX;
-                    p = SOUTH;
-                end else if  ( diff < (2* NX)+NY ) begin //left mesh edge 
-                    y = diff - (2* NX);
-                    x = 0;
-                    p = WEST;
-                end else begin //right mesh edge 
-                    y = diff - (2* NX) -NY;
-                    x = NX-1;
-                    p = EAST; 
-                end
-            end//else 
-            fmesh_addrencode = ( p<<(NXw+NYw) | (y<<NXw) | x);      
-        end   
-    endfunction // addrencode    
-     
-    
-     function automatic  integer fmesh_router_id; 
-        input integer x,y;
-        begin
-        fmesh_router_id=((y * NX) +  x);
-        end
-     endfunction
-     
-      function automatic  integer fmesh_endp_id; 
-        input integer x,y,l;
-        begin
-        fmesh_endp_id=((y * NX) + x) * NL + l ;
+    input [NE-1 : 0] p;
+    integer i;      
+    begin 
+        mcast_partial_width=0;
+        for (i=0;i<NE;i=i+1) begin
+            if (p [i]==1'b1) mcast_partial_width=mcast_partial_width+1;
         end
-     endfunction
-     
+    end   
+    endfunction    
     
-                        
-    // synthesis translate_off
-    /* verilator lint_off WIDTH */
-   task display_noc_parameters;  
-   begin
-      //print_parameter 
-        $display ("NoC parameters:----------------");
-        $display ("\tTopology: %s",TOPOLOGY);
-        $display ("\tRouting algorithm: %s",ROUTE_NAME);
-        $display ("\tVC_per port: %0d", V);
-        $display ("\tNon-local port buffer_width per VC: %0d", B);
-        $display ("\tLocal port buffer_width per VC: %0d", LB);
-        if(TOPOLOGY=="MESH" || TOPOLOGY=="TORUS" || TOPOLOGY == "FMESH")begin
-            $display ("\tRouter num in row: %0d",T1);
-            $display ("\tRouter num in column: %0d",T2);
-            $display ("\tEndpoint num per router: %0d",T3);
-        end else if (TOPOLOGY=="RING" || TOPOLOGY == "LINE") begin
-            $display ("\tTotal Router num: %0d",T1);
-            $display ("\tEndpoint num per router: %0d",T3);
-        end else if (TOPOLOGY == "TREE" ||  TOPOLOGY == "FATTREE")begin
-            $display ("\tK: %0d",T1);
-            $display ("\tL: %0d",T2);
-        end else begin //CUSTOM
-            $display ("\tTotal Endpoints number: %0d",T1);
-            $display ("\tTotal Routers number: %0d",T2);
-        end
-        $display ("\tNumber of Class: %0d", C);
-        $display ("\tFlit data width: %0d", Fpay);
-        $display ("\tVC reallocation mechanism: %s",  VC_REALLOCATION_TYPE);
-        $display ("\tVC/sw combination mechanism: %s", COMBINATION_TYPE);
-        $display ("\tAVC_ATOMIC_EN:%0d", AVC_ATOMIC_EN);
-        $display ("\tCongestion Index:%0d",CONGESTION_INDEX);
-        $display ("\tADD_PIPREG_AFTER_CROSSBAR:%0d",ADD_PIPREG_AFTER_CROSSBAR);
-        $display ("\tSSA_EN enabled:%s",SSA_EN);
-        $display ("\tSwitch allocator arbitration type:%s",SWA_ARBITER_TYPE);
-        $display ("\tMinimum supported packet size:%0d flit(s)",MIN_PCK_SIZE);
-        $display ("\tLoop back is enabled:%s",SELF_LOOP_EN);
-        $display ("\tNumber of multihop bypass (SMART max):%0d",SMART_MAX);
-        $display ("\tCastying type:%s.",CAST_TYPE);
-        if (CAST_TYPE == "MULTICAST_PARTIAL" || CAST_TYPE == "BROADCAST_PARTIAL")begin
-            $display ("\tNumber of nodes in Cast list:%d",   MCAST_PRTLw);
-            $display ("\tCAST LIST:%b", MCAST_ENDP_LIST);
-        end 
-        $display ("NoC parameters:----------------");
-      end
-      endtask
-      /* verilator lint_on WIDTH */
-      // synthesis translate_on
+    function automatic  integer regular_topo_endp_addr; 
+    input integer endp_id;
+    integer  y, x, z, l,rid;
+    begin
+        rid = endp_id / NL;
+        x = rid % NX;
+        y = (rid / NX) % NY;
+        z = rid / (NX * NY);
+        l = endp_id % NL;
+        regular_topo_endp_addr = 
+            (IS_3D_TOPO) ?( l << ( NXw+NYw+NZw) | (z<<NXw+NYw) | (y<<NXw) | x) : 
+            (IS_2D_TOPO) ?( l << ( NXw+NYw) | (y<<NXw) | x):
+            ( l << NXw | x);
+    end
+    endfunction
     
+    function automatic  integer fmesh_endp_addr; 
+    input integer endp_id;
+    integer  y, x, l,p, diff,mul;
+    begin
+        mul  = NX*NY*NL;
+        if(endp_id < mul) begin 
+            y = ((endp_id/NL) / NX ); 
+            x = ((endp_id/NL) % NX ); 
+            l = (endp_id % NL); 
+            p = (l==0)? LOCAL : 4+l;
+        end else begin      
+            diff = endp_id -  mul ;
+            if( diff <  NX) begin //top mesh edge 
+                y = 0;
+                x = diff;
+                p = NORTH;
+            end else if  ( diff < 2* NX) begin //bottom mesh edge 
+                y = NY-1;
+                x = diff-NX;
+                p = SOUTH;
+            end else if  ( diff < (2* NX)+NY ) begin //left mesh edge 
+                y = diff - (2* NX);
+                x = 0;
+                p = WEST;
+            end else begin //right mesh edge 
+                y = diff - (2* NX) -NY;
+                x = NX-1;
+                p = EAST; 
+            end
+        end//else 
+            fmesh_endp_addr = ( p<<(NXw+NYw) | (y<<NXw) | x);
+    end   
+    endfunction // addrencode
     
+    function automatic  integer fmesh_router_id; 
+    input integer x,y;
+    begin
+        fmesh_router_id=((y * NX) +  x);
+    end
+    endfunction
     
+    function automatic  integer fmesh_endp_id; 
+    input integer x,y,l;
+    begin
+        fmesh_endp_id=((y * NX) + x) * NL + l ;
+    end
+    endfunction
     
-   
- `endif
-
-
+    `ifdef SIMULATION
+    task automatic display_noc_parameters;
+    begin
+    // Print NoC parameters
+    $display ("NoC parameters:----------------");
+    $display("\tTopology: %s", TOPOLOGY);
+    $display("\tRouting algorithm: %s", ROUTE_NAME);
+    $display("\tVC per port: %0d", V);
+    $display("\tNon-local port buffer width per VC: %0d", B);
+    $display("\tLocal port buffer width per VC: %0d", LB);
+    if (IS_2D_TOPO) begin
+        $display("\tRouters per row: %0d", T1);
+        $display("\tRouters per column: %0d", T2);
+        $display("\tEndpoints per router: %0d", T3);
+    end else if (IS_1D_TOPO) begin
+        $display("\tTotal routers: %0d", T1);
+        $display("\tEndpoints per router: %0d", T3);
+    end else if (IS_MESH_3D) begin
+        $display("\tRouters per row: %0d", T1);
+        $display("\tRouters per column: %0d", T2);
+        $display("\tRouters per depth: %0d", T3);
+        $display("\tEndpoints per router: %0d", T4);
+    end else if (IS_MULTI_MESH) begin 
+        $display("\tTotal endpoints: %0d", T1);
+        $display("\tTotal routers: %0d", T1); 
+        $display("\tRouter address width: %0d", T2);
+    end else if (IS_TREE | IS_FATTREE) begin
+        $display("\tK: %0d", T1);
+        $display("\tL: %0d", T2);
+    end else begin // CUSTOM topology
+        $display("\tTotal endpoints: %0d", T1);
+        $display("\tTotal routers: %0d", T2);
+    end
+    $display("\tNumber of classes: %0d", C);
+    $display("\tFlit data width: %0d", Fpay);
+    $display("\tVC reallocation mechanism: %s", VC_REALLOCATION_TYPE);
+    $display("\tVC/SW combination mechanism: %s", COMBINATION_TYPE);
+    $display("\tAVC_ATOMIC_EN: %0d", AVC_ATOMIC_EN);
+    $display("\tCongestion index: %0d", CONGESTION_INDEX);
+    $display("\tADD_PIPREG_AFTER_CROSSBAR: %0d", ADD_PIPREG_AFTER_CROSSBAR);
+    $display("\tSSA_EN: %0d", SSA_EN);
+    $display("\tSwitch allocator arbiter type: %s", SWA_ARBITER_TYPE);
+    $display("\tMinimum packet size: %0d flit(s)", MIN_PCK_SIZE);
+    $display("\tLoopback enabled: %0d", SELF_LOOP_EN);
+    $display("\tMax multihop bypass (SMART): %0d", SMART_MAX);
+    $display("\tCasting type: %s", CAST_TYPE);
+    if (IS_MULTICAST_PARTIAL | IS_BROADCAST_PARTIAL) begin
+        $display("\tNumber of nodes in cast list: %0d", MCAST_PRTLw);
+        $display("\tCast list: %b", MCAST_ENDP_LIST);
+    end 
+    $display ("NoC parameters:----------------");
+    end
+    endtask
+    `endif //SIMULATION
+`endif
diff --git a/mpsoc/rtl/src_noc/traffic_gen_top.sv b/mpsoc/rtl/src_noc/traffic_gen_top.sv
index 52bc89a..a94d339 100644
--- a/mpsoc/rtl/src_noc/traffic_gen_top.sv
+++ b/mpsoc/rtl/src_noc/traffic_gen_top.sv
@@ -1,1055 +1,886 @@
 `include "pronoc_def.v"
 
-module  traffic_gen_top	#(
-	parameter NOC_ID=0,
-	parameter MAX_RATIO = 1000,
-	parameter ENDP_ID   = 100000
-)
-	(
-					
-		//noc port
-		chan_in,
-		chan_out,  
-		
-		//input 
-		ratio,// real injection ratio  = (MAX_RATIO/100)*ratio
-		pck_size_in,		
-		current_e_addr,
-		dest_e_addr,
-		pck_class_in,        
-		start, 
-		stop,  
-		report,
-		init_weight,
-		start_delay,
-		
-		//output
-		pck_number,
-		sent_done, // tail flit has been sent
-		hdr_flit_sent,
-		update, // update the noc_analayzer
-		src_e_addr,
-		flit_out_class,
-		flit_out_wr,
-		flit_in_wr,
-		
-		distance,
-		pck_class_out,   
-		time_stamp_h2h,
-		time_stamp_h2t,
-		pck_size_o,
-		mcast_dst_num_o,
-		
-		reset,
-		clk
-			
-	);
-	
-	
-	`NOC_CONF
-	
-	
-		
-	localparam
-		RATIOw= $clog2(MAX_RATIO);
-		
-	//	Vw =    $clog2(V);
-			
-	input   smartflit_chanel_t 	chan_in;
-	output  smartflit_chanel_t 	chan_out;  
-		
-		
-   
-   
-	localparam
-		PCK_CNTw = log2(MAX_PCK_NUM+1),
-		CLK_CNTw = log2(MAX_SIM_CLKs+1),		
-		AVG_PCK_SIZw = log2(10*MAX_PCK_SIZ+1),
-		/* verilator lint_off WIDTH */		
-		W=WEIGHTw,
-		PORT_B = (TOPOLOGY!="FMESH")?  LB :
-		(ENDP_ID < NE_MESH_TORI)? LB :B; // in FMESH, the buffer size of endpoints connected to edge routers non-local ports are B not LB  
-		/* verilator lint_on WIDTH */
-	input reset, clk;
-	input  [RATIOw-1                :0] ratio;
-	input                               start,stop;
-	output                              update;
-	output [CLK_CNTw-1              :0] time_stamp_h2h,time_stamp_h2t;
-	output [DISTw-1                 :0] distance;
-	output [Cw-1                    :0] pck_class_out;
-	
-	// the current endpoint address
-	input  [EAw-1                   :0] current_e_addr;    
-	// the destination endpoint address
-	input  [DAw-1                   :0] dest_e_addr;  
-    
-	output [PCK_CNTw-1              :0] pck_number;
-	input  [PCK_SIZw-1              :0] pck_size_in;
-    
-	output reg sent_done;
-	output reg hdr_flit_sent;
-	input  [Cw-1                    :0] pck_class_in;
-	input  [W-1                     :0] init_weight;
-		
-	input                               report;
-	input  [DELAYw-1           		:0] start_delay;
-	// the received packet source endpoint address
-	output [EAw-1        :   0]    src_e_addr;
-	output [PCK_SIZw-1   :   0]    pck_size_o;	
-	output [NEw-1 : 0] mcast_dst_num_o;
-	
-		
-	logic  [Fw-1                   :0] flit_out;     
-	output  logic                       flit_out_wr; 
-	output  [Cw-1 : 0] flit_out_class;
-	logic   [V-1                    :0] credit_in;
-    
-	logic   [Fw-1                   :0] flit_in;   
-	output logic                              flit_in_wr;   
-	logic  [V-1                :0] credit_out;     
-	
-	// the connected router address
-	wire  [RAw-1                   :0] current_r_addr;    
-		
-		
-	/* verilator lint_off WIDTH */
-	wire [PCK_SIZw-1 : 0] pck_size_tmp= (PCK_TYPE == "SINGLE_FLIT" )?   1 : pck_size_in;
-	/* verilator lint_on WIDTH */
-	
-	assign 	chan_out.flit_chanel.flit = flit_out; 
-	assign  chan_out.flit_chanel.flit_wr = flit_out_wr;
-	assign  chan_out.flit_chanel.credit = credit_out;
-	assign  chan_out.smart_chanel = {SMART_CHANEL_w {1'b0}};	
-		
-	assign flit_in   =  chan_in.flit_chanel.flit;   
-	assign flit_in_wr=  chan_in.flit_chanel.flit_wr; 
-	assign credit_in =  chan_in.flit_chanel.credit;  
-	assign current_r_addr = chan_in.ctrl_chanel.neighbors_r_addr;
-	
-	genvar i;
-	generate
-	for (i=0; i<V;i++) begin :V_
-		assign chan_out.ctrl_chanel.credit_init_val[i]= PORT_B;
-	end
-	endgenerate
-	
-	assign chan_out.ctrl_chanel.endp_port =1'b1;
-	assign chan_out.ctrl_chanel.credit_release_en={V{1'b0}};
-	
-	//old traffic.v file
-		
-	reg [2:0]   ps,ns;
-	localparam IDEAL =3'b001, SENT =3'b010, WAIT=3'b100;
-		
-	reg                                 inject_en,cand_wr_vc_en,pck_rd;
-	reg    [PCK_SIZw-1              :0] pck_size;    
-	logic  [DAw-1                   :0] dest_e_addr_reg,dest_e_addr_o;
-
-
-
-
-		
-	// synopsys  translate_off
-	// synthesis translate_off
-                                      
-	`ifdef MONITORE_PATH
-     
-   
-		reg tt;
-		always @(posedge clk) begin
-			if(`pronoc_reset)begin 
-				tt<=1'b0;               
-			end else begin 
-				if(flit_out_wr && tt==1'b0 )begin
-					$display( "%t: Injector: current_r_addr=%x,current_e_addr=%x,dest_e_addr=%x\n",$time, current_r_addr, current_e_addr, dest_e_addr);
-					tt<=1'b1;
-				end
-			end
-		end
-	`endif
-    
-	// synthesis translate_on
-	// synopsys  translate_on  
-     
-   
-	localparam
-		HDR_DATA_w =  (MIN_PCK_SIZE==1)? CLK_CNTw : 0,
-		HDR_Dw =  (MIN_PCK_SIZE==1)? CLK_CNTw : 1;
-   
-	wire [HDR_Dw-1 : 0] hdr_data_in,rd_hdr_data_out;
-   
-	pronoc_register #(.W(DAw)) reg2 (.in(dest_e_addr ), .out(dest_e_addr_reg), .reset(reset), .clk(clk));
-	  
-	
-   
-	wire    [DSTPw-1                :   0] destport;   
-	wire    [V-1                    :   0] ovc_wr_in;
-	wire    [V-1                    :   0] full_vc,empty_vc,nearly_full_vc;
-	reg     [V-1                    :   0] wr_vc,wr_vc_next;
-	wire    [V-1                    :   0] cand_vc;
-    
-    
-	wire    [CLK_CNTw-1             :   0] wr_timestamp,pck_timestamp;
-	wire                                   hdr_flit,tail_flit;
-	reg     [PCK_SIZw-1             :   0] flit_counter;
-	reg                                    flit_cnt_rst,flit_cnt_inc;
-	wire                                   rd_hdr_flg,rd_tail_flg;
-	wire    [Cw-1   :   0] rd_class_hdr;
-	//  wire    [P_1-1      :   0] rd_destport_hdr;
-	wire    [DAw-1      :   0] rd_des_e_addr;
-	wire    [EAw-1      :   0] rd_src_e_addr;  
-		
-	reg     [CLK_CNTw-1             :   0] rsv_counter;
-	reg     [CLK_CNTw-1             :   0] clk_counter;
-	wire    [Vw-1                   :   0] rd_vc_bin;//,wr_vc_bin;
-	reg     [CLK_CNTw-1             :   0] rsv_time_stamp[V-1:0];
-	reg     [PCK_SIZw-1             :   0] rsv_pck_size    [V-1:0];
-	wire    [V-1                    :   0] rd_vc; 
-	wire                                   wr_vc_is_full,wr_vc_avb,wr_vc_is_empty;
-	reg     [V-1                    :   0] credit_out_next;
-	reg     [EAw-1     :   0] rsv_pck_src_e_addr        [V-1:0];
-	reg     [Cw-1                   :   0] rsv_pck_class_in     [V-1:0];  
-      
-	wire [CLK_CNTw-1             :   0] hdr_flit_timestamp;    
-	wire pck_wr,buffer_full,pck_ready,valid_dst;    
-	wire [CLK_CNTw-1 : 0] rd_timestamp;
-     	    
-		
-	logic [DELAYw-1 : 0] start_delay_counter,start_delay_counter_next;
-	logic  start_en_next , start_en;
-
-	pronoc_register #(.W(1)) streg1 (.reset(reset),.clk(clk), .in(start_en_next), .out(start_en)	);
-	pronoc_register #(.W(DELAYw)) streg2 (.reset(reset),.clk(clk), .in(start_delay_counter_next), .out(start_delay_counter)	);
-			
-	always @(*) begin 
-		start_en_next =start_en;
-		start_delay_counter_next= start_delay_counter;
-		if(start)	begin 
-			start_en_next=1'b1;
-			start_delay_counter_next={DELAYw{1'b0}};
-		end else if(start_en && ~inject_en) begin 
-			start_delay_counter_next= start_delay_counter + 1'b1;
-		end
-		if(stop) begin 
-			start_en_next=1'b0;			
-		end
-	end//always
-		
-	wire start_injection = (start_delay_counter == start_delay);
-   	    
-   	check_destination_addr #(
-		.NOC_ID(NOC_ID),
-		.TOPOLOGY(TOPOLOGY),
-		.T1(T1),
-		.T2(T2),
-		.T3(T3),   
-		.EAw(EAw),
-		.SELF_LOOP_EN(SELF_LOOP_EN),
-		.DAw(DAw),
-		.CAST_TYPE(CAST_TYPE),
-		.NE(NE)
-	) check_destination_addr (
-		.dest_e_addr(dest_e_addr),
-		.current_e_addr(current_e_addr),
-		.dest_is_valid(valid_dst)
-	);
-       
-	//assign hdr_flit_sent=pck_rd;
-      
-	injection_ratio_ctrl # 	(
-		.MAX_PCK_SIZ(MAX_PCK_SIZ),
-		.MAX_RATIO(MAX_RATIO)
-	) pck_inject_ratio_ctrl (
-		.en(inject_en),
-		.pck_size_in(pck_size_tmp),
-		.clk(clk),
-		.reset(reset),
-		.freez(buffer_full),
-		.inject(pck_wr),
-		.ratio(ratio)
-	);
-         
-    
-	output_vc_status #(
-		.CRDTw(CRDTw),
-		.V  (V),
-		.B  (PORT_B)				
-	) nic_ovc_status (
-		.credit_init_val_in         ( chan_in.ctrl_chanel.credit_init_val),
-		.wr_in                      (ovc_wr_in),   
-		.credit_in                  (credit_in),
-		.nearly_full_vc             (nearly_full_vc),
-		.full_vc                    (full_vc),
-		.empty_vc                   (empty_vc),
-		.cand_vc                    (cand_vc),
-		.cand_wr_vc_en              (cand_wr_vc_en),
-		.clk                        (clk),
-		.reset                      (reset)
-	);
-    	
-    
-	packet_gen #(
-		.NOC_ID(NOC_ID),
-		.P(MAX_P)				
-	) 	packet_buffer (
-		.reset(reset),
-		.clk(clk),
-		.pck_wr(pck_wr),
-		.pck_rd(pck_rd),
-		.current_r_addr(current_r_addr),
-		.current_e_addr(current_e_addr),
-		.clk_counter(clk_counter+1'b1),//in case of zero load latency, the flit will be injected in the next clock cycle
-		.pck_number(pck_number),
-		.dest_e_addr_in(dest_e_addr),  
-		.dest_e_addr_o(dest_e_addr_o),     
-		.pck_timestamp(pck_timestamp),
-		.buffer_full(buffer_full),
-		.pck_ready(pck_ready),
-		.valid_dst(valid_dst),
-		.destport(destport),
-		.pck_size_in(pck_size_tmp),
-		.pck_size_o(pck_size)
-	);
-	   
-	assign wr_timestamp    =pck_timestamp; 
+module  traffic_gen_top  #(
+    parameter MAX_RATIO = 1000,
+    parameter ENDP_ID   = 100000
+) (
+    //noc port
+    chan_in,
+    chan_out,  
+    
+    //input 
+    ratio,// real injection ratio  = (MAX_RATIO/100)*ratio
+    pck_size_in,
+    current_e_addr,
+    dest_e_addr,
+    pck_class_in,
+    start, 
+    stop,  
+    report,
+    init_weight,
+    start_delay,
+    
+    //output
+    pck_number,
+    sent_done, // tail flit has been sent
+    hdr_flit_sent,
+    update, // update the noc_analayzer
+    src_e_addr,
+    flit_out_class,
+    flit_out_wr,
+    flit_in_wr,
+    
+    distance,
+    pck_class_out,
+    time_stamp_h2h,
+    time_stamp_h2t,
+    pck_size_o,
+    mcast_dst_num_o,
+    
+    reset,
+    clk
+);
+    
+    import pronoc_pkg::*;
+    
+    localparam
+        RATIOw= $clog2(MAX_RATIO),
+        PCK_CNTw = log2(MAX_PCK_NUM+1),
+        CLK_CNTw = log2(MAX_SIM_CLKs+1),
+        AVG_PCK_SIZw = log2(10*MAX_PCK_SIZ+1),
+        /* verilator lint_off WIDTH */
+        W=WEIGHTw,
+        PORT_B = (TOPOLOGY!="FMESH")?  LB :
+        (ENDP_ID < NE_REGULAR)? LB :B; // in FMESH, the buffer size of endpoints connected to edge routers non-local ports are B not LB  
+        /* verilator lint_on WIDTH */
+    
+    input   smartflit_chanel_t     chan_in;
+    output  smartflit_chanel_t     chan_out;
+    
+    input  reset, clk;
+    input  [RATIOw-1 :0] ratio;
+    input  start,stop;
+    output update;
+    output [CLK_CNTw-1 :0] time_stamp_h2h,time_stamp_h2t;
+    output [DISTw-1 :0] distance;
+    output [Cw-1 :0] pck_class_out;
+    
+    // the current endpoint address
+    input  [EAw-1 :0] current_e_addr;
+    // the destination endpoint address
+    input  [DAw-1 :0] dest_e_addr;  
+    
+    output [PCK_CNTw-1 :0] pck_number;
+    input  [PCK_SIZw-1 :0] pck_size_in;
+    
+    output reg sent_done;
+    output reg hdr_flit_sent;
+    input  [Cw-1 :0] pck_class_in;
+    input  [W-1 :0] init_weight;
+    
+    input report;
+    input  [DELAYw-1 :0] start_delay;
+    // the received packet source endpoint address
+    output [EAw-1 : 0] src_e_addr;
+    output [PCK_SIZw-1 : 0]    pck_size_o;
+    output [NEw-1 : 0] mcast_dst_num_o;
+    
+    logic  [Fw-1 :0] flit_out;
+    output  logic flit_out_wr;
+    output  [Cw-1 : 0] flit_out_class;
+    logic   [V-1 :0] credit_in;
+    
+    logic   [Fw-1 :0] flit_in;
+    output logic flit_in_wr;
+    logic  [V-1 :0] credit_out;
+    
+    // the connected router address
+    logic  [RAw-1 :0] current_r_addr;
+    
+    /* verilator lint_off WIDTH */
+    wire [PCK_SIZw-1 : 0] pck_size_tmp= (IS_SINGLE_FLIT )?   1 : pck_size_in;
+    /* verilator lint_on WIDTH */
+    
+    always_comb begin
+        chan_out.flit_chanel.flit = flit_out; 
+        chan_out.flit_chanel.flit_wr = flit_out_wr;
+        chan_out.flit_chanel.credit = credit_out;
+        chan_out.smart_chanel = {SMART_CHANEL_w {1'b0}};
+        for (int k=0; k<V;k++) chan_out.ctrl_chanel.credit_init_val[k] = PORT_B [CRDTw-1: 0] ;
+        chan_out.ctrl_chanel.endp_port =1'b1;
+        chan_out.ctrl_chanel.credit_release_en={V{1'b0}};
+        chan_out.ctrl_chanel.hetero_ovc_presence={V{1'b1}};
+        flit_in   =  chan_in.flit_chanel.flit;
+        flit_in_wr=  chan_in.flit_chanel.flit_wr;
+        credit_in =  chan_in.flit_chanel.credit;
+        current_r_addr = chan_in.ctrl_chanel.router_addr;
+    end
+    //old traffic.v file
+    reg [2:0]   ps,ns;
+    localparam IDEAL =3'b001, SENT =3'b010, WAIT=3'b100;
+    
+    reg inject_en,cand_wr_vc_en,pck_rd;
+    reg [PCK_SIZw-1 :0] pck_size;
+    logic [DAw-1 :0] dest_e_addr_reg,dest_e_addr_o;
+    
+    `ifdef SIMULATION
+    `ifdef MONITORE_PATH    
+    reg tt;
+    always @(posedge clk) begin
+        if(`pronoc_reset)begin
+            tt<=1'b0;
+        end else begin
+            if(flit_out_wr && tt==1'b0 )begin
+                $display( "%t: Injector: current_r_addr=%x,current_e_addr=%x,dest_e_addr=%x\n",$time, current_r_addr, current_e_addr, dest_e_addr);
+                tt<=1'b1;
+            end
+        end
+    end
+    `endif //MONITORE_PATH
+    `endif //SIMULATION
+    
+    localparam
+        HDR_DATA_w =  (MIN_PCK_SIZE==1)? CLK_CNTw : 0,
+        HDR_Dw =  (MIN_PCK_SIZE==1)? CLK_CNTw : 1;
+    
+    wire [HDR_Dw-1 : 0] hdr_data_in,rd_hdr_data_out;
+    
+    always_ff @ (`pronoc_clk_reset_edge) begin
+        if (`pronoc_reset) begin
+            dest_e_addr_reg <= '0;
+        end else begin
+            dest_e_addr_reg <= dest_e_addr;
+        end
+    end
+    
+    wire [DSTPw-1 : 0] destport;   
+    wire [V-1 : 0] ovc_wr_in;
+    wire [V-1 : 0] full_vc,empty_vc,nearly_full_vc;
+    reg  [V-1 : 0] wr_vc,wr_vc_next;
+    wire [V-1 : 0] cand_vc;
+    
+    wire [CLK_CNTw-1 : 0] wr_timestamp,pck_timestamp;
+    wire hdr_flit,tail_flit;
+    reg [PCK_SIZw-1 : 0] flit_counter;
+    reg flit_cnt_rst,flit_cnt_inc;
+    wire rd_hdr_flg,rd_tail_flg;
+    wire [Cw-1 : 0] rd_class_hdr;
+    //  wire    [P_1-1 : 0] rd_destport_hdr;
+    wire [DAw-1 : 0] rd_des_e_addr;
+    wire [EAw-1 : 0] rd_src_e_addr;  
+    
+    reg [CLK_CNTw-1 : 0] rsv_counter;
+    reg [CLK_CNTw-1 : 0] clk_counter;
+    wire [Vw-1 : 0] rd_vc_bin;//,wr_vc_bin;
+    reg  [CLK_CNTw-1 : 0] rsv_time_stamp[V-1:0];
+    reg  [PCK_SIZw-1 : 0] rsv_pck_size    [V-1:0];
+    wire [V-1 : 0] rd_vc; 
+    wire wr_vc_is_full,wr_vc_avb,wr_vc_is_empty;
+    reg  [V-1 : 0] credit_out_next;
+    reg  [EAw-1 : 0] rsv_pck_src_e_addr        [V-1:0];
+    reg  [Cw-1 : 0] rsv_pck_class_in     [V-1:0];  
+    
+    wire [CLK_CNTw-1 : 0] hdr_flit_timestamp;    
+    wire pck_wr,buffer_full,pck_ready,valid_dst;    
+    wire [CLK_CNTw-1 : 0] rd_timestamp;
+    
+    logic [DELAYw-1 : 0] start_delay_counter,start_delay_counter_next;
+    logic  start_en_next , start_en;
+    always_ff @ (`pronoc_clk_reset_edge) begin
+        if (`pronoc_reset) begin
+            start_en <= 1'b0;
+            start_delay_counter <= '0;  // zero all bits of DELAYw width
+        end else begin
+            start_en <= start_en_next;
+            start_delay_counter <= start_delay_counter_next;
+        end
+    end
+    always_comb begin 
+        start_en_next = start_en;
+        start_delay_counter_next = start_delay_counter;
+        if(start)    begin 
+            start_en_next=1'b1;
+            start_delay_counter_next={DELAYw{1'b0}};
+        end else if(start_en && ~inject_en) begin 
+            start_delay_counter_next= start_delay_counter + 1'b1;
+        end
+        if(stop) begin 
+            start_en_next=1'b0;
+        end
+    end//always
+    
+    wire start_injection = (start_delay_counter == start_delay);
+    
+    check_destination_addr  check_dest_addr (
+        .dest_e_addr(dest_e_addr),
+        .current_e_addr(current_e_addr),
+        .dest_is_valid(valid_dst)
+    );
+    
+    //assign hdr_flit_sent=pck_rd;
+    
+    injection_ratio_ctrl #     (
+        .MAX_PCK_SIZ(MAX_PCK_SIZ),
+        .MAX_RATIO(MAX_RATIO)
+    ) pck_inject_ratio_ctrl (
+        .en(inject_en),
+        .pck_size_in(pck_size_tmp),
+        .clk(clk),
+        .reset(reset),
+        .freez(buffer_full),
+        .inject(pck_wr),
+        .ratio(ratio)
+    );
+    
+    output_vc_status #(
+        .CRDTw(CRDTw),
+        .PORT_B(PORT_B)
+    ) nic_ovc_status (
+        .credit_init_val_in( chan_in.ctrl_chanel.credit_init_val),
+        .ovc_presence(chan_in.ctrl_chanel.hetero_ovc_presence),
+        .wr_in(ovc_wr_in),
+        .credit_in(credit_in),
+        .nearly_full_vc(nearly_full_vc),
+        .full_vc(full_vc),
+        .empty_vc(empty_vc),
+        .cand_vc(cand_vc),
+        .cand_wr_vc_en (cand_wr_vc_en),
+        .clk(clk),
+        .reset(reset)
+    );
+    
+    packet_gen #(
+        .P(MAX_P)
+    ) packet_buffer (
+        .reset(reset),
+        .clk(clk),
+        .pck_wr(pck_wr),
+        .pck_rd(pck_rd),
+        .current_r_addr(current_r_addr),
+        .current_e_addr(current_e_addr),
+        .clk_counter(clk_counter+1'b1),//in case of zero load latency, the flit will be injected in the next clock cycle
+        .pck_number(pck_number),
+        .dest_e_addr_in(dest_e_addr),
+        .dest_e_addr_o(dest_e_addr_o), 
+        .pck_timestamp(pck_timestamp),
+        .buffer_full(buffer_full),
+        .pck_ready(pck_ready),
+        .valid_dst(valid_dst),
+        .destport(destport),
+        .pck_size_in(pck_size_tmp),
+        .pck_size_o(pck_size)
+    );
+    
+    assign wr_timestamp    =pck_timestamp; 
     assign  update      = flit_in_wr & flit_in[Fw-2];
-	assign  hdr_flit    = (flit_counter == 0);
-	assign  tail_flit   = (flit_counter ==  pck_size-1'b1);
-       
-	assign  time_stamp_h2h  = hdr_flit_timestamp - rd_timestamp;
-	assign  time_stamp_h2t  = clk_counter - rd_timestamp;
-
-	wire [FPAYw-1    :   0] flit_out_pyload;
-	wire [1         :   0] flit_out_hdr;
-   	wire [FPAYw-1    :   0] flit_out_header_pyload;
-	wire [Fw-1      :   0] hdr_flit_out;
-      
-	assign hdr_data_in = (MIN_PCK_SIZE==1)? wr_timestamp[HDR_Dw-1 : 0]  : {HDR_Dw{1'b0}};
-    
-	header_flit_generator #(
-		.NOC_ID(NOC_ID),
-		.DATA_w(HDR_DATA_w)				
-	) the_header_flit_generator (
-		.flit_out(hdr_flit_out),
-		.vc_num_in(wr_vc),
-		.class_in(pck_class_in),
-		.dest_e_addr_in(dest_e_addr_o),
-		.src_e_addr_in(current_e_addr),
-		.weight_in(init_weight),
-		.destport_in(destport),
-		.data_in(hdr_data_in),
-		.be_in({BEw{1'b1}} )// Be is not used in simulation as we dont sent real data
-	);
+    assign  hdr_flit    = (flit_counter == 0);
+    assign  tail_flit   = (flit_counter ==  pck_size-1'b1);
+    
+    assign  time_stamp_h2h  = hdr_flit_timestamp - rd_timestamp;
+    assign  time_stamp_h2t  = clk_counter - rd_timestamp;
+    
+    wire [FPAYw-1 : 0] flit_out_pyload;
+    wire [1 : 0] flit_out_hdr;
+    wire [FPAYw-1 : 0] flit_out_header_pyload;
+    wire [Fw-1 : 0] hdr_flit_out;
+    
+    assign hdr_data_in = (MIN_PCK_SIZE==1)? wr_timestamp[HDR_Dw-1 : 0] : {HDR_Dw{1'b0}};
+    
+    header_flit_generator #(
+        .DATA_w(HDR_DATA_w)
+    ) the_header_flit_generator (
+        .flit_out(hdr_flit_out),
+        .vc_num_in(wr_vc),
+        .class_in(pck_class_in),
+        .dest_e_addr_in(dest_e_addr_o),
+        .src_e_addr_in(current_e_addr),
+        .weight_in(init_weight),
+        .destport_in(destport),
+        .data_in(hdr_data_in),
+        .be_in({BEw{1'b1}} )// Be is not used in simulation as we dont sent real data
+    );
     
     assign flit_out_class = pck_class_in;
-   	assign flit_out_hdr = {hdr_flit,tail_flit};
+    assign flit_out_hdr = {hdr_flit,tail_flit};    
+    assign flit_out_header_pyload = hdr_flit_out[FPAYw-1 : 0];
     
-	assign flit_out_header_pyload = hdr_flit_out[FPAYw-1 : 0];
-        
-        
-	/* verilator lint_off WIDTH */ 
-	assign flit_out_pyload = (hdr_flit)  ?    flit_out_header_pyload :                
-		(tail_flit) ?     wr_timestamp:
-		{pck_number,flit_counter};
-		/* verilator lint_on WIDTH */
-            
-	assign flit_out = {flit_out_hdr, wr_vc, flit_out_pyload };   
-
-	//extract header flit info
+    /* verilator lint_off WIDTH */ 
+    assign flit_out_pyload = (hdr_flit)  ?    flit_out_header_pyload :
+        (tail_flit) ? wr_timestamp : {pck_number,flit_counter};
+    /* verilator lint_on WIDTH */
+    
+    assign flit_out = {flit_out_hdr, wr_vc, flit_out_pyload };   
+    
+    //extract header flit info
     extract_header_flit_info #(
-		.NOC_ID(NOC_ID),
-		.DATA_w(HDR_DATA_w)				
-	) header_extractor (
-		.flit_in(flit_in),
-		.flit_in_wr(flit_in_wr),
-		.class_o(rd_class_hdr),
-		.destport_o(),
-		.dest_e_addr_o(rd_des_e_addr),
-		.src_e_addr_o(rd_src_e_addr),
-		.vc_num_o(rd_vc),
-		.hdr_flit_wr_o( ),
-		.hdr_flg_o(rd_hdr_flg),
-		.tail_flg_o(rd_tail_flg),
-		.weight_o( ),
-		.be_o( ),
-		.data_o(rd_hdr_data_out)
-	);   
-   
-    
-	distance_gen #(
-		.TOPOLOGY(TOPOLOGY),
-		.T1(T1),
-		.T2(T2),
-		.T3(T3),
-		.EAw(EAw),
-		.DISTw(DISTw)
-	) the_distance_gen (
-		.src_e_addr(src_e_addr),
-		.dest_e_addr(current_e_addr),
-		.distance(distance)
-	);
-    
-    
-	generate 
-	if(MIN_PCK_SIZE == 1) begin : sf_pck    
-		assign src_e_addr         = (rd_hdr_flg & rd_tail_flg)? rd_src_e_addr : rsv_pck_src_e_addr[rd_vc_bin];
-		assign pck_class_out      = (rd_hdr_flg & rd_tail_flg)? rd_class_hdr : rsv_pck_class_in[rd_vc_bin];
-		assign hdr_flit_timestamp = (rd_hdr_flg & rd_tail_flg)?  clk_counter : rsv_time_stamp[rd_vc_bin];
-		assign rd_timestamp 	  =	(rd_hdr_flg & rd_tail_flg)? rd_hdr_data_out : flit_in[CLK_CNTw-1             :   0];
-		assign pck_size_o         = (rd_hdr_flg & rd_tail_flg)? 1 : rsv_pck_size[rd_vc_bin];
-	end else begin : no_sf_pck
-		assign pck_size_o = rsv_pck_size[rd_vc_bin];
-		assign src_e_addr            = rsv_pck_src_e_addr[rd_vc_bin];
-		assign pck_class_out    = rsv_pck_class_in[rd_vc_bin];
-		assign hdr_flit_timestamp = rsv_time_stamp[rd_vc_bin];
-		assign rd_timestamp=flit_in[CLK_CNTw-1 :   0];        
-	end
-
-
-	if(V==1) begin : v1
-		assign rd_vc_bin=1'b0;
-	// assign wr_vc_bin=1'b0;
-	end else begin :vother  
-
-		one_hot_to_bin #( .ONE_HOT_WIDTH (V)) conv1 
-		(
-			.one_hot_code   (rd_vc),
-			.bin_code       (rd_vc_bin)
-		);
-	/*
+        .DATA_w(HDR_DATA_w)
+    ) header_extractor (
+        .flit_in(flit_in),
+        .flit_in_wr(flit_in_wr),
+        .class_o(rd_class_hdr),
+        .destport_o(),
+        .dest_e_addr_o(rd_des_e_addr),
+        .src_e_addr_o(rd_src_e_addr),
+        .vc_num_o(rd_vc),
+        .hdr_flit_wr_o( ),
+        .hdr_flg_o(rd_hdr_flg),
+        .tail_flg_o(rd_tail_flg),
+        .weight_o( ),
+        .be_o( ),
+        .data_o(rd_hdr_data_out)
+    );
+    
+    distance_gen the_distance_gen (
+        .src_e_addr(src_e_addr),
+        .dest_e_addr(current_e_addr),
+        .distance(distance)
+    );
+    
+    generate 
+    if(MIN_PCK_SIZE == 1) begin : sf_pck    
+        assign src_e_addr         = (rd_hdr_flg & rd_tail_flg)? rd_src_e_addr : rsv_pck_src_e_addr[rd_vc_bin];
+        assign pck_class_out      = (rd_hdr_flg & rd_tail_flg)? rd_class_hdr : rsv_pck_class_in[rd_vc_bin];
+        assign hdr_flit_timestamp = (rd_hdr_flg & rd_tail_flg)?  clk_counter : rsv_time_stamp[rd_vc_bin];
+        assign rd_timestamp       =    (rd_hdr_flg & rd_tail_flg)? rd_hdr_data_out : flit_in[CLK_CNTw-1 : 0];
+        assign pck_size_o         = (rd_hdr_flg & rd_tail_flg)? 1 : rsv_pck_size[rd_vc_bin];
+    end else begin : no_sf_pck
+        assign pck_size_o = rsv_pck_size[rd_vc_bin];
+        assign src_e_addr            = rsv_pck_src_e_addr[rd_vc_bin];
+        assign pck_class_out    = rsv_pck_class_in[rd_vc_bin];
+        assign hdr_flit_timestamp = rsv_time_stamp[rd_vc_bin];
+        assign rd_timestamp=flit_in[CLK_CNTw-1 : 0];        
+    end
+    
+    if(V==1) begin : v1
+        assign rd_vc_bin=1'b0;
+    // assign wr_vc_bin=1'b0;
+    end else begin :vother  
+        
+        one_hot_to_bin #( .ONE_HOT_WIDTH (V)) conv1 
+        (
+            .one_hot_code (rd_vc),
+            .bin_code (rd_vc_bin)
+        );
+    /*
     one_hot_to_bin #( .ONE_HOT_WIDTH (V)) conv2 
     (
         .one_hot_code   (wr_vc),
         .bin_code       (wr_vc_bin)
     );
-	 */
-	end 
-	endgenerate
-    
-    
-	assign  ovc_wr_in   = (flit_out_wr ) ?      wr_vc : {V{1'b0}};
-	
-	/* verilator lint_off WIDTH */
-	//assign  wr_vc_is_full           = (SSA_EN=="NO")?  | ( full_vc & wr_vc)  : | (nearly_full_vc & wr_vc);
-	assign  wr_vc_is_full           = | ( full_vc & wr_vc);
-    /* verilator lint_on WIDTH */ 
-    
-    
-	generate
-	/* verilator lint_off WIDTH */ 
-		if(VC_REALLOCATION_TYPE ==  "NONATOMIC") begin : nanatom_b
-			/* verilator lint_on WIDTH */  
-			assign wr_vc_avb    =  ~wr_vc_is_full; 
-		end else begin : atomic_b 
-			assign wr_vc_is_empty   =  | ( empty_vc & wr_vc);
-			assign wr_vc_avb        =  wr_vc_is_empty;      
-		end
-	endgenerate
-
-	reg not_yet_sent_aflit_next,not_yet_sent_aflit;
-
-	always @(*)begin
-		wr_vc_next          = wr_vc; 
-		cand_wr_vc_en       = 1'b0;
-		flit_out_wr         = 1'b0;
-		flit_cnt_inc        = 1'b0;
-		flit_cnt_rst        = 1'b0;
-		credit_out_next     = {V{1'd0}};
-		sent_done           = 1'b0;
-		pck_rd              = 1'b0;
-		hdr_flit_sent       =1'b0;
-		ns                  = ps;
-		pck_rd              =1'b0;
-         
-            
-		not_yet_sent_aflit_next =not_yet_sent_aflit;            
-		case (ps) 
-			IDEAL: begin                 
-				if(pck_ready ) begin 
-					if(wr_vc_avb && valid_dst)begin
-						
-						hdr_flit_sent=1'b1;
-						flit_out_wr     = 1'b1;//sending header flit
-						not_yet_sent_aflit_next = 1'b0;
-						flit_cnt_inc = 1'b1;                            
-						if (MIN_PCK_SIZE>1 || flit_out_hdr!=2'b11) begin 
-							ns              = SENT;
-						end else begin
-							pck_rd=1'b1;
-							flit_cnt_rst   = 1'b1;
-							sent_done       =1'b1;
-							cand_wr_vc_en   =1'b1;
-							if(cand_vc>0) begin 
-								wr_vc_next  = cand_vc;                                  
-							end  else ns = WAIT;                
-						end  //else                         
-					end//wr_vc                        
-				end 
+     */
+    end 
+    endgenerate
+    
+    assign  ovc_wr_in   = (flit_out_wr ) ?      wr_vc : {V{1'b0}};
+    assign  wr_vc_is_full           = | ( full_vc & wr_vc);
+    
+    generate
+    /* verilator lint_off WIDTH */ 
+    if(VC_REALLOCATION_TYPE ==  "NONATOMIC") begin : nanatom_b
+    /* verilator lint_on WIDTH */  
+        assign wr_vc_avb    =  ~wr_vc_is_full; 
+    end else begin : atomic_b 
+        assign wr_vc_is_empty   =  | ( empty_vc & wr_vc);
+        assign wr_vc_avb        =  wr_vc_is_empty;      
+    end
+    endgenerate
+    
+    reg not_yet_sent_aflit_next,not_yet_sent_aflit;
+    
+    always_comb begin
+        wr_vc_next          = wr_vc; 
+        cand_wr_vc_en       = 1'b0;
+        flit_out_wr         = 1'b0;
+        flit_cnt_inc        = 1'b0;
+        flit_cnt_rst        = 1'b0;
+        credit_out_next     = {V{1'd0}};
+        sent_done           = 1'b0;
+        pck_rd              = 1'b0;
+        hdr_flit_sent       =1'b0;
+        ns                  = ps;
+        pck_rd              =1'b0;
+        not_yet_sent_aflit_next =not_yet_sent_aflit;
+        case (ps) 
+            IDEAL: begin
+                if(pck_ready ) begin 
+                    if(wr_vc_avb && valid_dst)begin
+                        
+                        hdr_flit_sent=1'b1;
+                        flit_out_wr     = 1'b1;//sending header flit
+                        not_yet_sent_aflit_next = 1'b0;
+                        flit_cnt_inc = 1'b1;                            
+                        if (MIN_PCK_SIZE>1 || flit_out_hdr!=2'b11) begin 
+                            ns              = SENT;
+                        end else begin
+                            pck_rd=1'b1;
+                            flit_cnt_rst   = 1'b1;
+                            sent_done       =1'b1;
+                            cand_wr_vc_en   =1'b1;
+                            if(cand_vc>0) begin 
+                                wr_vc_next  = cand_vc;
+                            end  else ns = WAIT;
+                        end  //else
+                    end//wr_vc
+                end 
                 
-			end //IDEAL
-			SENT: begin  
-                  
-				if(!wr_vc_is_full )begin 
+            end //IDEAL
+            SENT: begin  
+                if(!wr_vc_is_full )begin 
                         
-					flit_out_wr     = 1'b1;
-					if(flit_counter  < pck_size-1) begin 
-						flit_cnt_inc = 1'b1;
-					end else begin 
-						flit_cnt_rst   = 1'b1;
-						sent_done       =1'b1;
-						pck_rd=1'b1;
-						cand_wr_vc_en   =1'b1;
-						if(cand_vc>0) begin 
-							wr_vc_next  = cand_vc;
-							ns          =IDEAL;
-						end     else ns = WAIT; 
-					end//else
-				end // if wr_vc_is_full
-			end//SENT
-			WAIT:begin
-                   
-				cand_wr_vc_en   =1'b1;
-				if(cand_vc>0) begin 
-					wr_vc_next  = cand_vc;
-					ns                  =IDEAL;
-				end  
-			end
-			default: begin 
-				ns                  =IDEAL;
-			end
-		endcase
-            
-        
-		// packet sink
-		if(flit_in_wr) begin 
-			credit_out_next = rd_vc;
-		end else credit_out_next = {V{1'd0}};
-	end
- 
-	
-		always @ (`pronoc_clk_reset_edge )begin 
-			if(`pronoc_reset) begin 
-				inject_en       <= 1'b0;
-				ps              <= IDEAL;
-				wr_vc           <=1; 
-				flit_counter    <= {PCK_SIZw{1'b0}};
-				credit_out      <= {V{1'd0}};
-				rsv_counter     <= 0;
-				clk_counter     <=  0;
-				not_yet_sent_aflit<=1'b1;          
+                    flit_out_wr     = 1'b1;
+                    if(flit_counter  < pck_size-1) begin 
+                        flit_cnt_inc = 1'b1;
+                    end else begin 
+                        flit_cnt_rst   = 1'b1;
+                        sent_done       =1'b1;
+                        pck_rd=1'b1;
+                        cand_wr_vc_en   =1'b1;
+                        if(cand_vc>0) begin 
+                            wr_vc_next  = cand_vc;
+                            ns          =IDEAL;
+                        end     else ns = WAIT; 
+                    end//else
+                end // if wr_vc_is_full
+            end//SENT
+            WAIT:begin
+                cand_wr_vc_en   =1'b1;
+                if(cand_vc>0) begin 
+                    wr_vc_next  = cand_vc;
+                    ns = IDEAL;
+                end  
+            end
+            default: begin 
+                ns = IDEAL;
+            end
+        endcase
+        // packet sink
+        if(flit_in_wr) begin 
+            credit_out_next = rd_vc;
+        end else credit_out_next = {V{1'd0}};
+    end //always
+    
+    always @ (`pronoc_clk_reset_edge )begin 
+        if(`pronoc_reset) begin 
+            inject_en <= 1'b0;
+            ps <= IDEAL;
+            wr_vc <= 1; 
+            flit_counter <= {PCK_SIZw{1'b0}};
+            credit_out <= {V{1'd0}};
+            rsv_counter <= 0;
+            clk_counter <= 0;
+            not_yet_sent_aflit<=1'b1;
+        end else begin 
+            //injection
+            not_yet_sent_aflit<=not_yet_sent_aflit_next;
+            inject_en <=  (start_injection |inject_en) & ~stop;  
+            ps <= ns;
+            clk_counter <= clk_counter+1'b1;
+            wr_vc <= wr_vc_next; 
+            if (flit_cnt_rst) flit_counter <= {PCK_SIZw{1'b0}};
+            else if(flit_cnt_inc) flit_counter <= flit_counter + 1'b1;     
+            credit_out <= credit_out_next;
+            //sink
+            if(flit_in_wr) begin 
+                if (flit_in[Fw-1])begin //header flit
+                    rsv_pck_src_e_addr[rd_vc_bin]    <=  rd_src_e_addr;
+                    rsv_pck_class_in[rd_vc_bin]    <= rd_class_hdr;
+                    rsv_time_stamp[rd_vc_bin]   <= clk_counter;  
+                    rsv_counter                 <= rsv_counter+1'b1;
+                    rsv_pck_size[rd_vc_bin] <=2;                    
+                    // distance        <= {{(32-8){1'b0}},flit_in[7:0]};
+                    `ifdef SIMULATION
+                    `ifdef RSV_NOTIFICATION
+                    // last_pck_time<=$time;
+                    $display ("total of %d pcks have been recived in core (%d)", rsv_counter,current_e_addr);
+                    `endif
+                    `endif
+                end else begin 
+                    rsv_pck_size[rd_vc_bin] <=rsv_pck_size[rd_vc_bin]+1; 
+                end
+            end
+            `ifdef SIMULATION
+            if(report) begin 
+                $display ("%t,\t total of %d pcks have been recived in core (%d)",$time ,rsv_counter,current_e_addr);
+            end
+            `endif
+        end //else reset
+    end//always
+    
+    wire [NE-1 :0] dest_mcast_all_endp1;    
+    
+    generate 
+    /* verilator lint_off WIDTH */
+    if(CAST_TYPE != "UNICAST") begin :mb_cast
+    /* verilator lint_on WIDTH */
         
-			end else begin 
-				//injection
-				not_yet_sent_aflit<=not_yet_sent_aflit_next;
-				inject_en <=  (start_injection |inject_en) & ~stop;  
-				ps             <= ns;
-				clk_counter     <= clk_counter+1'b1;
-				wr_vc           <=wr_vc_next; 
-				if (flit_cnt_rst)      flit_counter    <= {PCK_SIZw{1'b0}};
-				else if(flit_cnt_inc)   flit_counter    <= flit_counter + 1'b1;     
-				credit_out      <= credit_out_next;
-			
-           
-				//sink
-				if(flit_in_wr) begin 
-					if (flit_in[Fw-1])begin //header flit
-						rsv_pck_src_e_addr[rd_vc_bin]    <=  rd_src_e_addr;
-						rsv_pck_class_in[rd_vc_bin]    <= rd_class_hdr;
-						rsv_time_stamp[rd_vc_bin]   <= clk_counter;  
-						rsv_counter                 <= rsv_counter+1'b1;
-						rsv_pck_size[rd_vc_bin] <=2;                    
-						// distance        <= {{(32-8){1'b0}},flit_in[7:0]};
-						`ifdef RSV_NOTIFICATION
-							// synopsys  translate_off
-							// synthesis translate_off
-							// last_pck_time<=$time;
-							$display ("total of %d pcks have been recived in core (%d)", rsv_counter,current_e_addr);
-							// synthesis translate_on
-							// synopsys  translate_on
-						`endif
-					end else begin 
-						 rsv_pck_size[rd_vc_bin] <=rsv_pck_size[rd_vc_bin]+1; 
-					end
-				end
-				// synopsys  translate_off
-				// synthesis translate_off
-				if(report) begin 
-					$display ("%t,\t total of %d pcks have been recived in core (%d)",$time ,rsv_counter,current_e_addr);
-				end
-				// synthesis translate_on
-				// synopsys  translate_on
+        wire [NEw-1 : 0] sum_temp;
+        wire is_unicast;
         
-         
+        mcast_dest_list_decode  decode1 (
+            .dest_e_addr(dest_e_addr_o),
+            .dest_o(dest_mcast_all_endp1),
+            .row_has_any_dest(),
+            .is_unicast(is_unicast)
+        );
         
-         
+        /* verilator lint_off WIDTH */
+        if (CAST_TYPE == "BROADCAST_FULL") begin :bcastf
+            assign mcast_dst_num_o = (is_unicast) ? 1 : (SELF_LOOP_EN ) ? NE : NE-1;
+        end else  if ( CAST_TYPE == "BROADCAST_PARTIAL" )  begin :bcastp 
+            if (SELF_LOOP_EN == 0) begin 
+                //check if injector node is included in partial list
+                wire [NEw-1: 0]  current_enp_id;
+                endp_addr_decoder  decod1 ( .id_out(current_enp_id), .code_in(current_e_addr));
+                assign mcast_dst_num_o = (is_unicast) ? 1 : (MCAST_ENDP_LIST[current_enp_id]== 1'b1)?  MCAST_PRTLw-1 : MCAST_PRTLw;
+            end else begin 
+                assign mcast_dst_num_o = (is_unicast)? 1 : MCAST_PRTLw;
+            end
+        /* verilator lint_on WIDTH */
         
-			end
-		end//always
-		
-		
-		
-		
-		
-		
-		wire [NE-1 :0] dest_mcast_all_endp1;	
-		
-		
-		generate 
-			/* verilator lint_off WIDTH */
-			if(CAST_TYPE != "UNICAST") begin :mb_cast
-			/* verilator lint_on WIDTH */
-				
-				wire [NEw-1 : 0] sum_temp;
-				wire is_unicast;
-				
-				mcast_dest_list_decode #(
-					.NOC_ID(NOC_ID)
-				) decode1 (
-					.dest_e_addr(dest_e_addr_o),
-					.dest_o(dest_mcast_all_endp1),
-					.row_has_any_dest(),
-					.is_unicast(is_unicast)
-				);
-				
-				/* verilator lint_off WIDTH */
-				if (CAST_TYPE == "BROADCAST_FULL") begin :bcastf				
-					assign mcast_dst_num_o = (is_unicast) ? 1 : (SELF_LOOP_EN == "NO")? NE-1 : NE;				
-				end else  if ( CAST_TYPE == "BROADCAST_PARTIAL" )  begin :bcastp 
-				
-					if (SELF_LOOP_EN == "NO") begin 
-						//check if injector node is included in partial list
-						wire [NEw-1: 0]  current_enp_id;
-						endp_addr_decoder  #( .TOPOLOGY(TOPOLOGY), .T1(T1), .T2(T2), .T3(T3), .EAw(EAw),  .NE(NE)) decod1 ( .id(current_enp_id), .code(current_e_addr));
-						assign mcast_dst_num_o = (is_unicast) ? 1 : (MCAST_ENDP_LIST[current_enp_id]== 1'b1)?  MCAST_PRTLw-1 :  MCAST_PRTLw;
-						
-					end else begin 
-						assign mcast_dst_num_o = (is_unicast)? 1 :  MCAST_PRTLw;
-					end			
-				/* verilator lint_on WIDTH */
-				end else begin : mcast
-					accumulator #(
-							.INw(NE),
-							.OUTw(NEw),
-							.NUM(NE)
-						)accum
-						(
-							.in_all(dest_mcast_all_endp1),
-							.out(sum_temp)         
-						);				
-					assign mcast_dst_num_o = sum_temp;
-				end			
-			end
-		endgenerate
-		
-		
-		
-		
-		
-/***************************************************************
- * 			simulation code
- * ************************************************************/		
-		
-		
-		
-		
-		
-// synthesis translate_off			
-				
-		wire [NEw-1: 0]  src_id,dst_id,current_id;
-    
-		endp_addr_decoder  #( .TOPOLOGY(TOPOLOGY), .T1(T1), .T2(T2), .T3(T3), .EAw(EAw),  .NE(NE)) decod1 ( .id(current_id), .code(current_e_addr));
-		endp_addr_decoder  #( .TOPOLOGY(TOPOLOGY), .T1(T1), .T2(T2), .T3(T3), .EAw(EAw),  .NE(NE)) decod2 ( .id(dst_id), .code(rd_des_e_addr[EAw-1 : 0]));// only for unicast
-		endp_addr_decoder  #( .TOPOLOGY(TOPOLOGY), .T1(T1), .T2(T2), .T3(T3), .EAw(EAw),  .NE(NE)) decod3 ( .id(src_id), .code(rd_src_e_addr));
-    
-    
-		
-		
-		
-		wire [NE-1 :0] dest_mcast_all_endp2;	
-		generate 
-		if(CAST_TYPE != "UNICAST") begin :no_unicast		
-			mcast_dest_list_decode #(
-				.NOC_ID(NOC_ID)
-			) decode2 (
-				.dest_e_addr(rd_des_e_addr),
-				.dest_o(dest_mcast_all_endp2),
-				.row_has_any_dest(),
-				.is_unicast()
-			);
-		end 
-		endgenerate
-		
-		
-    
-		always @(posedge clk) begin     
-			/* verilator lint_off WIDTH */
-			if(CAST_TYPE == "UNICAST") begin
-				/* verilator lint_on WIDTH */	
-				if(flit_out_wr && hdr_flit && dest_e_addr_o [EAw-1 : 0]  == current_e_addr  && SELF_LOOP_EN == "NO") begin 
-					$display("%t: ERROR: The self-loop is not enabled in the router while a packet is injected to the NoC with identical source and destination address in endpoint (%h).: %m",$time, dest_e_addr_o );
-					$finish;
-				end				
-				if(flit_in_wr && rd_hdr_flg && (rd_des_e_addr[EAw-1 : 0]  != current_e_addr )) begin 
-					$display("%t: ERROR: packet with destination %d (code %h) which is sent by source %d (code %h) has been recieved in wrong destination %d (code %h).  %m",$time,dst_id,rd_des_e_addr, src_id,rd_src_e_addr, current_id,current_e_addr);
-					$finish;
-				end
-				
-			end else begin 
-				/* verilator lint_off WIDTH */
-				if((CAST_TYPE == "MULTICAST_FULL") || (CAST_TYPE == "MULTICAST_PARTIAL")) begin
-				/* verilator lint_on WIDTH */
-					
-					if(flit_out_wr && hdr_flit && dest_mcast_all_endp1[current_id]  == 1'b1  && SELF_LOOP_EN == "NO") begin 
-						$display("%t: ERROR: The self-loop is not enabled in the router while a packet is injected to the NoC with identical source and destination address in endpoint %d. destination nodes:0X%h. : %m",$time, current_id,dest_mcast_all_endp1 );
-						$finish;
-					end				
-				end			
-				if(flit_in_wr && rd_hdr_flg && (dest_mcast_all_endp2[current_id] !=1'b1 )) begin 
-					$display("%t: ERROR: packet with destination %b  which is sent by source %d (code %h) has been recieved in wrong destination %d (code %h).  %m",$time, dest_mcast_all_endp2, src_id,rd_src_e_addr, current_id,current_e_addr);
-					$finish;
-				end
-				
-				//check multicast packet size to be smaller than B & LB
-				if(flit_out_wr & hdr_flit & (mcast_dst_num_o>1) & (pck_size >B || pck_size> LB))begin 
-					$display("%t: ERROR: A multicast packat is injected to the NoC which has larger size (%d) than router buffer width.  %m",$time, pck_size);
-					$finish;
-				end
-				
-			end
-			if(update) begin
-				if (hdr_flit_timestamp<= rd_timestamp) begin 
-					$display("%t: ERROR: In destination %d packt which is sent by source %d, the time when header flit is recived (%d) should be larger than the packet timestamp %d.  %m",$time, current_id ,src_e_addr, hdr_flit_timestamp, rd_timestamp);
-					$finish;
-				end 
-				if( clk_counter <= rd_timestamp) begin 
-					$display("%t: ERROR: ERROR: In destination %d packt which is sent by source %d,, the current time (%d) should be larger than the packet timestamp %d.  %m",$time, current_id ,src_e_addr, clk_counter, rd_timestamp);
-					$finish;
-				end				
-			end//update 
-			if(tail_flit & flit_out_wr) begin 
-				if(wr_timestamp > clk_counter) begin 
-					$display("%t: ERROR: In src %d, the current time (%d) should be larger than or equal to the packet timestamp %d.  %m",$time, current_id, clk_counter, wr_timestamp);
-					$finish;
-				end
-			end				
-				
-		end
-	
-    
-		`ifdef CHECK_PCKS_CONTENT
-		
-    
-			wire     [PCK_SIZw-1             :   0] rsv_flit_counter; 
-			reg      [PCK_SIZw-1             :   0] old_flit_counter    [V-1   :   0];
-			wire     [PCK_CNTw-1             :   0] rsv_pck_number;
-			reg      [PCK_CNTw-1             :   0] old_pck_number  [V-1   :   0];
-    
-			wire [PCK_CNTw+PCK_SIZw-1 : 0] statistics;
-			generate 
-				if(PCK_CNTw+PCK_SIZw > Fw) assign statistics = {{(PCK_CNTw+PCK_SIZw-Fw){1'b0}},flit_in};
-			else  assign statistics = flit_in[PCK_CNTw+PCK_SIZw-1   :   0];
-			assign {rsv_pck_number,rsv_flit_counter}=statistics;
-               
-			endgenerate   
-    
-    
-    
-				integer ii;
-				
-				always @ (`pronoc_clk_reset_edge )begin 
-					if(`pronoc_reset) begin
-						for(ii=0;ii<V;ii=ii+1'b1)begin
-							old_flit_counter[ii]<=0;            
-						end        
-					end else begin
-						if(flit_in_wr)begin
-							if ( flit_in[Fw-1:Fw-2]==2'b10)  begin
-								old_pck_number[rd_vc_bin]<=0;
-								old_flit_counter[rd_vc_bin]<=0;
-							end else if ( flit_in[Fw-1:Fw-2]==2'b00)begin 
-								old_pck_number[rd_vc_bin]<=rsv_pck_number;
-								old_flit_counter[rd_vc_bin]<=rsv_flit_counter;
-							end                    
+        end else begin : mcast
+            accumulator #(
+                .INw(NE),
+                .OUTw(NEw),
+                .NUM(NE)
+            ) accum (
+                .in_all(dest_mcast_all_endp1),
+                .sum_o(sum_temp)
+            );
+            assign mcast_dst_num_o = sum_temp;
+        end 
+    end
+    endgenerate
+
+/**************************************
+*        Validating Parameters 
+*        /Simulation
+***************************************/
+    `ifdef SIMULATION
+    
+    wire [NEw-1: 0]  src_id,dst_id,current_id;
+    
+    endp_addr_decoder  decod1 ( .id_out(current_id), .code_in(current_e_addr));
+    endp_addr_decoder  decod2 ( .id_out(dst_id), .code_in(rd_des_e_addr[EAw-1 : 0]));// only for unicast
+    endp_addr_decoder  decod3 ( .id_out(src_id), .code_in(rd_src_e_addr));
+    
+    wire [NE-1 :0] dest_mcast_all_endp2;
+    generate 
+    if(CAST_TYPE != "UNICAST") begin :no_unicast
+        mcast_dest_list_decode decode2 (
+            .dest_e_addr(rd_des_e_addr),
+            .dest_o(dest_mcast_all_endp2),
+            .row_has_any_dest(),
+            .is_unicast()
+        );
+    end 
+    endgenerate
+    
+    always @(posedge clk) begin
+        /* verilator lint_off WIDTH */
+        if(CAST_TYPE == "UNICAST") begin
+        /* verilator lint_on WIDTH */
+            if(flit_out_wr && hdr_flit && dest_e_addr_o [EAw-1 : 0]  == current_e_addr  && SELF_LOOP_EN == 0) begin 
+                $display("%t: ERROR: The self-loop is not enabled in the router while a packet is injected to the NoC with identical source and destination address in endpoint (%h).: %m",$time, dest_e_addr_o );
+                $finish;
+            end
+            if(flit_in_wr && rd_hdr_flg && (rd_des_e_addr[EAw-1 : 0]  != current_e_addr )) begin 
+                $display("%t: ERROR: packet with destination %d (code %h) which is sent by source %d (code %h) has been recieved in wrong destination %d (code %h).  %m",$time,dst_id,rd_des_e_addr, src_id,rd_src_e_addr, current_id,current_e_addr);
+                $finish;
+            end
+        end else begin 
+            /* verilator lint_off WIDTH */
+            if((CAST_TYPE == "MULTICAST_FULL") || (CAST_TYPE == "MULTICAST_PARTIAL")) begin
+            /* verilator lint_on WIDTH */
                 
-						end //flit_in_wr      
-        
-					end    //reset
-				end//always
-    
-    
-				always @(posedge clk) begin     
-					if(flit_in_wr && (flit_in[Fw-1:Fw-2]==2'b00) && (~reset))begin 
-						if( old_flit_counter[rd_vc_bin]!=rsv_flit_counter-1) $display("%t: Error: missmatch flit counter in %m. Expected %d but recieved %d",$time,old_flit_counter[rd_vc_bin]+1,rsv_flit_counter);
-						if( old_pck_number[rd_vc_bin]!=rsv_pck_number && old_pck_number[rd_vc_bin]!=0)   $display("%t: Error: missmatch pck number in %m. expected %d but recieved %d",$time,old_pck_number[rd_vc_bin],rsv_pck_number);
-                       
-					end
-   
-				end
-				
+                if(flit_out_wr && hdr_flit && dest_mcast_all_endp1[current_id]  == 1'b1  && SELF_LOOP_EN == 0) begin 
+                    $display("%t: ERROR: The self-loop is not enabled in the router while a packet is injected to the NoC with identical source and destination address in endpoint %d. destination nodes:0X%h. : %m",$time, current_id,dest_mcast_all_endp1 );
+                    $finish;
+                end
+            end
+            if(flit_in_wr && rd_hdr_flg && (dest_mcast_all_endp2[current_id] !=1'b1 )) begin 
+                $display("%t: ERROR: packet with destination %b  which is sent by source %d (code %h) has been recieved in wrong destination %d (code %h).  %m",$time, dest_mcast_all_endp2, src_id,rd_src_e_addr, current_id,current_e_addr);
+                $finish;
+            end
+            //check multicast packet size to be smaller than B & LB
+            if(flit_out_wr & hdr_flit & (mcast_dst_num_o>1) & (pck_size >B || pck_size> LB))begin 
+                $display("%t: ERROR: A multicast packat is injected to the NoC which has larger size (%d) than router buffer width.  %m",$time, pck_size);
+                $finish;
+            end
+        end
+        if(update) begin
+            if (hdr_flit_timestamp<= rd_timestamp) begin 
+                $display("%t: ERROR: In destination %d packt which is sent by source %d, the time when header flit is recived (%d) should be larger than the packet timestamp %d.  %m",$time, current_id ,src_e_addr, hdr_flit_timestamp, rd_timestamp);
+                $finish;
+            end 
+            if( clk_counter <= rd_timestamp) begin 
+                $display("%t: ERROR: ERROR: In destination %d packt which is sent by source %d,, the current time (%d) should be larger than the packet timestamp %d.  %m",$time, current_id ,src_e_addr, clk_counter, rd_timestamp);
+                $finish;
+            end
+        end//update 
+        if(tail_flit & flit_out_wr) begin 
+            if(wr_timestamp > clk_counter) begin 
+                $display("%t: ERROR: In src %d, the current time (%d) should be larger than or equal to the packet timestamp %d.  %m",$time, current_id, clk_counter, wr_timestamp);
+                $finish;
+            end
+        end 
+    end //always
+    
+    `ifdef CHECK_PCKS_CONTENT
+    wire     [PCK_SIZw-1 : 0] rsv_flit_counter; 
+    reg      [PCK_SIZw-1 : 0] old_flit_counter    [V-1 : 0];
+    wire     [PCK_CNTw-1 : 0] rsv_pck_number;
+    reg      [PCK_CNTw-1 : 0] old_pck_number  [V-1 : 0];
+    wire [PCK_CNTw+PCK_SIZw-1 : 0] statistics;
+    
+    assign statistics = (PCK_CNTw+PCK_SIZw > Fw)? 
+        {{(PCK_CNTw+PCK_SIZw-Fw){1'b0}},flit_in} :
+        flit_in[PCK_CNTw+PCK_SIZw-1 : 0];
+    
+    assign {rsv_pck_number,rsv_flit_counter}=statistics;
+    
+    integer ii;
+    always @ (`pronoc_clk_reset_edge )begin 
+        if(`pronoc_reset) begin
+            for(ii=0;ii<V;ii=ii+1'b1)begin
+                old_flit_counter[ii]<=0;
+            end
+        end else begin
+            if(flit_in_wr)begin
+                if ( flit_in[Fw-1:Fw-2]==2'b10)  begin
+                    old_pck_number[rd_vc_bin]<=0;
+                    old_flit_counter[rd_vc_bin]<=0;
+                end else if ( flit_in[Fw-1:Fw-2]==2'b00)begin 
+                    old_pck_number[rd_vc_bin]<=rsv_pck_number;
+                    old_flit_counter[rd_vc_bin]<=rsv_flit_counter;
+                end 
+            end //flit_in_wr
+        end    //reset
+    end //always
+    
+    always @(posedge clk) begin     
+        if(flit_in_wr && (flit_in[Fw-1:Fw-2]==2'b00) && (~reset))begin 
+            if( old_flit_counter[rd_vc_bin]!=rsv_flit_counter-1) $display("%t: Error: missmatch flit counter in %m. Expected %d but recieved %d",$time,old_flit_counter[rd_vc_bin]+1,rsv_flit_counter);
+            if( old_pck_number[rd_vc_bin]!=rsv_pck_number && old_pck_number[rd_vc_bin]!=0)   $display("%t: Error: missmatch pck number in %m. expected %d but recieved %d",$time,old_pck_number[rd_vc_bin],rsv_pck_number);
+        end
+    end
+    
+    `endif //CHECK_PCKS_CONTENT
+    `endif //SIMULATION
+    
+// `ifdef VERILATOR
+//   logic  endp_is_active   /*verilator public_flat_rd*/ ;
+//  
+//    always_comb begin 
+//        endp_is_active  = 1'b0;        
+//        if (chan_out.flit_chanel.flit_wr) endp_is_active=1'b1;
+//        if (chan_out.flit_chanel.credit > {V{1'b0}} ) endp_is_active=1'b1;
+//        if (chan_out.smart_chanel.requests > {SMART_NUM{1'b0}} ) endp_is_active=1'b1;
+//    end
+//`endif
     
-			`endif
-    
-// synthesis translate_on
-
-		
-		
-		
-		
-//				`ifdef VERILATOR
-//					logic  endp_is_active   /*verilator public_flat_rd*/ ;
-//			
-//					always @ (*) begin 
-//						endp_is_active  = 1'b0;		
-//						if (chan_out.flit_chanel.flit_wr) endp_is_active=1'b1;
-//						if (chan_out.flit_chanel.credit > {V{1'b0}} ) endp_is_active=1'b1;
-//						if (chan_out.smart_chanel.requests > {SMART_NUM{1'b0}} ) endp_is_active=1'b1;
-//					end	
-//				`endif
-				
 endmodule
 
-
 /*****************************
-    injection_ratio_ctrl
-   
+*    injection_ratio_ctrl
 *****************************/
 module injection_ratio_ctrl #
-	(
-	parameter MAX_PCK_SIZ=10,
-	parameter MAX_RATIO=100
+    (
+    parameter MAX_PCK_SIZ=10,
+    parameter MAX_RATIO=100
 )(
-	en,
-	pck_size_in, // average packet size in flit x10
-	clk,
-	reset,
-	inject,// inject one packet
-	freez,
-	ratio // 0~100  flit injection ratio
+    en,
+    pck_size_in, // average packet size in flit x10
+    clk,
+    reset,
+    inject,// inject one packet
+    freez,
+    ratio // 0~100  flit injection ratio
 );
-
-
-	function integer log2;
-	input integer number; begin   
-		log2=(number <=1) ? 1: 0;    
-		while(2**log2<number) begin    
-			log2=log2+1;    
-		end       
-	end   
-	endfunction // log2 
-	
-	
-	localparam PCK_SIZw= log2(MAX_PCK_SIZ);
-	
-	
-	localparam CNTw    =   log2(MAX_RATIO);
-	localparam STATE_INIT=   MAX_PCK_SIZ*MAX_RATIO;
-	localparam STATEw    =   log2(MAX_PCK_SIZ*2*MAX_RATIO);
-	
-	input                       clk,reset,freez,en;
-	output  reg                 inject;
-	input   [CNTw-1     :   0]  ratio;
-	input  [PCK_SIZw-1          :0] pck_size_in;
-	reg    [PCK_SIZw-1          :0]pck_size;
-	
-	wire    [CNTw-1     :   0]  on_clks, off_clks;
-	reg     [STATEw-1   :   0]  state,next_state;
-	wire                        input_changed;
-	reg     [CNTw-1     :   0]  ratio_old;    
-	
-	always @(posedge clk ) ratio_old<=ratio;
-	
-	assign input_changed = (ratio_old!=ratio);
-	
-	
-	assign on_clks = ratio; 
-	assign off_clks =MAX_RATIO-ratio; 
-	
-	reg [PCK_SIZw-1 :0] flit_counter,next_flit_counter;
-	
-	
-	reg sent,next_sent,next_inject;
-	
-	
-	
-	always @(*) begin 
-		next_state        =state;
-		next_flit_counter =flit_counter;
-		next_sent         =sent;
-		if(en && ~freez ) begin
-			case(sent)
-				1'b1: begin 
-					/* verilator lint_off WIDTH */
-					next_state          = state +  off_clks; 
-					/* verilator lint_on WIDTH */
-					next_flit_counter = (flit_counter >= pck_size-1'b1) ? {PCK_SIZw{1'b0}} : flit_counter +1'b1;
-					next_inject         = (flit_counter=={PCK_SIZw{1'b0}});
-					if (next_flit_counter >= pck_size-1'b1) begin 
-						if( next_state  >= STATE_INIT ) next_sent =1'b0;
-					end
-				end
-				1'b0:begin 
-					if( next_state  <  STATE_INIT ) next_sent  = 1'b1;
-					next_inject= 1'b0;
-					/* verilator lint_off WIDTH */
-					next_state = state - on_clks;
-					/* verilator lint_on WIDTH */
-				end
-			endcase     
-		end else begin 
-			next_inject= 1'b0;
-		end
-	end     
-	
-	
-	
-	
-	always @ (`pronoc_clk_reset_edge )begin 
-		if(`pronoc_reset) begin             
-				state       <=  STATE_INIT;
-				inject      <=  1'b0; 
-				sent        <=  1'b1; 
-				flit_counter<= 0;
-				pck_size<=2;
-			end else begin 
-				if(input_changed)begin
-					state       <=  STATE_INIT;
-					inject      <=  1'b0; 
-					sent        <=  1'b1; 
-					flit_counter<= 0;
-				end
-	
-				if(flit_counter=={PCK_SIZw{1'b0}}) pck_size<=pck_size_in;
-				state       <=  next_state;
-				if(ratio!={CNTw{1'b0}}) inject      <=  next_inject; 
-				sent        <=  next_sent; 
-				flit_counter<=  next_flit_counter;
-	
-			end
-		end     
-
-	
+    
+    function integer log2;
+    input integer number; begin   
+        log2=(number <=1) ? 1: 0;    
+        while(2**log2<number) begin    
+            log2=log2+1;    
+        end       
+    end   
+    endfunction // log2 
+    
+    localparam PCK_SIZw= log2(MAX_PCK_SIZ);
+    localparam CNTw    =   log2(MAX_RATIO);
+    localparam STATE_INIT=   MAX_PCK_SIZ*MAX_RATIO;
+    localparam STATEw    =   log2(MAX_PCK_SIZ*2*MAX_RATIO);
+    
+    input  clk,reset,freez,en;
+    output  reg inject;
+    input   [CNTw-1 : 0]  ratio;
+    input  [PCK_SIZw-1 :0] pck_size_in;
+    reg    [PCK_SIZw-1 :0]pck_size;
+    
+    wire    [CNTw-1 : 0]  on_clks, off_clks;
+    reg     [STATEw-1 : 0]  state,next_state;
+    wire                        input_changed;
+    reg     [CNTw-1 : 0]  ratio_old;    
+    
+    always @(posedge clk ) ratio_old<=ratio;
+    
+    assign input_changed = (ratio_old!=ratio);
+    assign on_clks = ratio; 
+    assign off_clks =MAX_RATIO-ratio; 
+    
+    reg [PCK_SIZw-1 :0] flit_counter,next_flit_counter;
+    
+    reg sent,next_sent,next_inject;
+    
+    always_comb begin 
+        next_state        =state;
+        next_flit_counter =flit_counter;
+        next_sent         =sent;
+        if(en && ~freez ) begin
+            case(sent)
+                1'b1: begin 
+                    /* verilator lint_off WIDTH */
+                    next_state          = state +  off_clks; 
+                    /* verilator lint_on WIDTH */
+                    next_flit_counter = (flit_counter >= pck_size-1'b1) ? {PCK_SIZw{1'b0}} : flit_counter +1'b1;
+                    next_inject         = (flit_counter=={PCK_SIZw{1'b0}});
+                    if (next_flit_counter >= pck_size-1'b1) begin 
+                        if( next_state  >= STATE_INIT ) next_sent =1'b0;
+                    end
+                end
+                1'b0:begin 
+                    if( next_state  <  STATE_INIT ) next_sent  = 1'b1;
+                    next_inject= 1'b0;
+                    /* verilator lint_off WIDTH */
+                    next_state = state - on_clks;
+                    /* verilator lint_on WIDTH */
+                end
+            endcase     
+        end else begin 
+            next_inject= 1'b0;
+        end
+    end
+    
+    always @ (`pronoc_clk_reset_edge )begin 
+        if(`pronoc_reset) begin
+            state <= STATE_INIT;
+            inject <= 1'b0; 
+            sent <= 1'b1; 
+            flit_counter<= 0;
+            pck_size<=2;
+        end else begin 
+            if(input_changed)begin
+                state <= STATE_INIT;
+                inject <=  1'b0; 
+                sent <= 1'b1; 
+                flit_counter <= 0;
+                pck_size <= pck_size_in;
+            end else begin 
+                sent <=  next_sent; 
+                state <=  next_state;
+                if(ratio!={CNTw{1'b0}}) inject <=  next_inject;             
+                flit_counter <= next_flit_counter;
+                if(flit_counter=={PCK_SIZw{1'b0}}) pck_size<=pck_size_in;
+            end
+        end
+    end
 endmodule
 
-
-
- 
 /*************************************
-       packet_buffer
+*        packet_buffer
 **************************************/
-
- 
 module packet_gen 
-#(   
-	parameter NOC_ID=0,
-	parameter P = 5
+#(
+    parameter P = 5
 )(
-	clk_counter,
-	pck_wr,
-	pck_rd,
-	current_r_addr,
-	current_e_addr,
-	pck_number,
-	dest_e_addr_in,
-	dest_e_addr_o,
-	pck_timestamp,
-	destport,
-	buffer_full,
-	pck_ready,
-	valid_dst,
-	pck_size_in,
-	pck_size_o,
-	clk,
-	reset 
+    clk_counter,
+    pck_wr,
+    pck_rd,
+    current_r_addr,
+    current_e_addr,
+    pck_number,
+    dest_e_addr_in,
+    dest_e_addr_o,
+    pck_timestamp,
+    destport,
+    buffer_full,
+    pck_ready,
+    valid_dst,
+    pck_size_in,
+    pck_size_o,
+    clk,
+    reset 
 );
-	
-
-	`NOC_CONF
-     
-	localparam 
-	PCK_CNTw    =   log2(MAX_PCK_NUM+1),
-	CLK_CNTw    =   log2(MAX_SIM_CLKs+1);
-
- 
-	input  reset,clk, pck_wr, pck_rd;
-	input  [RAw-1  :0] current_r_addr;
-	input  [EAw-1 : 0] current_e_addr;
-	input  [CLK_CNTw-1 :0] clk_counter;	
-	input  [PCK_SIZw-1 :0] pck_size_in;
-	input  [DAw-1  :0] dest_e_addr_in;
-	output [DAw-1  :0] dest_e_addr_o;
-	input  valid_dst; 
-	
-	output [PCK_CNTw-1 :0] pck_number;
-	output [CLK_CNTw-1 :0] pck_timestamp;  
-	output [PCK_SIZw-1 :0] pck_size_o;
-	output buffer_full,pck_ready;
-	
-	output [DSTPw-1    :0] destport; 
-	reg    [PCK_CNTw-1 :0] packet_counter;  
-	wire   buffer_empty; 
-	
-	assign pck_ready = ~buffer_empty & valid_dst;
-    
-	generate if(CAST_TYPE == "UNICAST") begin : uni 
-	conventional_routing #(
-		.NOC_ID(NOC_ID),
-		.TOPOLOGY(TOPOLOGY),
-		.ROUTE_NAME(ROUTE_NAME),
-		.ROUTE_TYPE(ROUTE_TYPE),
-		.T1(T1),
-		.T2(T2),
-		.T3(T3),
-		.RAw(RAw),
-		.EAw(EAw),
-		.DSTPw(DSTPw),
-		.LOCATED_IN_NI(1)
-	)
-	routing_module
-	(
-		.reset(reset),
-		.clk(clk),
-		.current_r_addr(current_r_addr),
-		.dest_e_addr(dest_e_addr_o),
-		.src_e_addr(current_e_addr),
-		.destport(destport)
-	);
-	end endgenerate
-	
-	wire timestamp_fifo_nearly_full , timestamp_fifo_full;
-	assign buffer_full = (MIN_PCK_SIZE==1) ? timestamp_fifo_nearly_full : timestamp_fifo_full;
-	
-	wire  [DAw-1  :0] tmp1;
-	wire  [PCK_SIZw-1 : 0] tmp2;
-	
-	wire recieve_more_than_0;
-	fwft_fifo_bram #(
-		.DATA_WIDTH(CLK_CNTw+PCK_SIZw+DAw),
-		.MAX_DEPTH(TIMSTMP_FIFO_NUM)        
-	)
-	timestamp_fifo
-	(
-		.din({dest_e_addr_in,pck_size_in,clk_counter}),
-		.wr_en(pck_wr),
-		.rd_en(pck_rd),
-		.dout({tmp1,tmp2,pck_timestamp}),
-		.full(timestamp_fifo_full),
-		.nearly_full(timestamp_fifo_nearly_full),       
-		.recieve_more_than_0(recieve_more_than_0),
-		.recieve_more_than_1(),
-		.reset(reset),
-		.clk(clk)
-	);
-	
-	//assign dest_e_addr_o = dest_e_addr_in;
-		
-	assign dest_e_addr_o =tmp1;
-	/* verilator lint_off WIDTH */
-	assign pck_size_o = (PCK_TYPE == "SINGLE_FLIT" )?   1 : tmp2;
-	/* verilator lint_on WIDTH */
-	assign buffer_empty = ~recieve_more_than_0;
-    
-				/*
-
+    
+    import pronoc_pkg::*;
+    
+    localparam 
+        PCK_CNTw    =   log2(MAX_PCK_NUM+1),
+        CLK_CNTw    =   log2(MAX_SIM_CLKs+1);
+    
+    input  reset,clk, pck_wr, pck_rd;
+    input  [RAw-1 :0] current_r_addr;
+    input  [EAw-1 : 0] current_e_addr;
+    input  [CLK_CNTw-1 :0] clk_counter;    
+    input  [PCK_SIZw-1 :0] pck_size_in;
+    input  [DAw-1 :0] dest_e_addr_in;
+    output [DAw-1 :0] dest_e_addr_o;
+    input  valid_dst; 
+    
+    output [PCK_CNTw-1 :0] pck_number;
+    output [CLK_CNTw-1 :0] pck_timestamp;  
+    output [PCK_SIZw-1 :0] pck_size_o;
+    output buffer_full,pck_ready;
+    
+    output [DSTPw-1 :0] destport; 
+    reg    [PCK_CNTw-1 :0] packet_counter;  
+    wire   buffer_empty; 
+    
+    assign pck_ready = ~buffer_empty & valid_dst;
+    
+    generate 
+    if((CAST_TYPE == "UNICAST") && (IS_LOOKAHEAD==1'b1)) begin : conv
+    //The router is configured with lookaheadrouting. 
+    //The header flit is supposed to carry the destinaion output port 
+        conventional_routing #(
+            .LOCATED_IN_NI(1)
+        ) routing_module (
+            .reset(reset),
+            .clk(clk),
+            .current_r_addr(current_r_addr),
+            .dest_e_addr(dest_e_addr_o),
+            .src_e_addr(current_e_addr),
+            .destport(destport)
+        );
+    end 
+    endgenerate
+    fifo_stat_t timestamp_fifo_stat;
+    assign buffer_full = (MIN_PCK_SIZE==1) ? timestamp_fifo_stat.nearly_full : timestamp_fifo_stat.full;
+    
+    wire  [DAw-1 :0] tmp1;
+    wire  [PCK_SIZw-1 : 0] tmp2;
+    fwft_fifo_bram #(
+        .DATA_WIDTH(CLK_CNTw+PCK_SIZw+DAw),
+        .MAX_DEPTH(TIMSTMP_FIFO_NUM)        
+    ) timestamp_fifo (
+        .din({dest_e_addr_in,pck_size_in,clk_counter}),
+        .wr_en(pck_wr),
+        .rd_en(pck_rd),
+        .dout({tmp1,tmp2,pck_timestamp}),
+        .stat_o(timestamp_fifo_stat),
+        .reset(reset),
+        .clk(clk)
+    );
+    
+    //assign dest_e_addr_o = dest_e_addr_in;
+    
+    assign dest_e_addr_o =tmp1;
+    /* verilator lint_off WIDTH */
+    assign pck_size_o = (IS_SINGLE_FLIT )?   1 : tmp2;
+    /* verilator lint_on WIDTH */
+    assign buffer_empty = timestamp_fifo_stat.empty;
+    
+    /*
     bram_based_fifo #(
         .Dw(CLK_CNTw),
         .B(TIMSTMP_FIFO_NUM)
@@ -1060,114 +891,74 @@ module packet_gen
         .wr_en(pck_wr),
         .rd_en(pck_rd),
         .dout(pck_timestamp),
-        .full(timestamp_fifo_full),
-        .nearly_full(timestamp_fifo_nearly_full),
-        .empty(buffer_empty),
+        .stat_o(timestamp_fifo_stat),
         .reset(reset),
         .clk(clk)
     );
-				 */ 
-    
-	always @ (`pronoc_clk_reset_edge )begin 
-		if(`pronoc_reset) begin 
-				packet_counter <= {PCK_CNTw{1'b0}};	
-			end else begin 
-				if(pck_rd) begin 
-					packet_counter <= packet_counter+1'b1;
-	
-				end
-			end
-		end
-	
-		assign pck_number = packet_counter;
-	
-
-endmodule    
- 
- 
- 
-/********************
+    */ 
+    
+    always @ (`pronoc_clk_reset_edge )begin 
+        if(`pronoc_reset) begin 
+            packet_counter <= {PCK_CNTw{1'b0}};
+        end else begin 
+            if(pck_rd) begin 
+                packet_counter <= packet_counter+1'b1;
+            end
+        end
+    end
+    
+    assign pck_number = packet_counter;
+    
+endmodule
 
-    distance_gen 
 
+/********************
+*    distance_gen 
 ********************/
-
-module distance_gen #(
-	parameter TOPOLOGY  = "MESH",
-	parameter T1=4,
-	parameter T2=4,
-	parameter T3=4,
-	parameter EAw=2,
-	parameter DISTw=4
-
-)(
-	src_e_addr,
-	dest_e_addr,
-	distance
+module distance_gen (
+    src_e_addr,
+    dest_e_addr,
+    distance
 );
-
-	input [EAw-1 : 0] src_e_addr;
-	input [EAw-1 : 0] dest_e_addr;
-	output [DISTw-1 : 0]   distance;
-	
-	generate 
-	/* verilator lint_off WIDTH */ 
-	if (TOPOLOGY ==    "MESH" || TOPOLOGY ==  "TORUS" || TOPOLOGY == "RING" || TOPOLOGY == "LINE")begin : tori_noc 
-	/* verilator lint_on WIDTH */ 
-	
-		mesh_torus_distance_gen #(
-			.T1(T1),
-			.T2(T2),
-			.T3(T3),
-			.TOPOLOGY(TOPOLOGY),
-			.DISTw(DISTw),
-			.EAw(EAw)
-		)
-		distance_gen
-		(
-			.src_e_addr(src_e_addr),
-			.dest_e_addr(dest_e_addr),
-			.distance(distance)
-		);
-	/* verilator lint_off WIDTH */ 
-	end else if (TOPOLOGY ==    "FMESH") begin :fmesh
-	/* verilator lint_on WIDTH */ 
-		fmesh_distance_gen #(
-			.T1(T1),
-			.T2(T2),
-			.T3(T3),			
-			.DISTw(DISTw),
-			.EAw(EAw)
-		)
-		distance_gen
-		(
-			.src_e_addr(src_e_addr),
-			.dest_e_addr(dest_e_addr),
-			.distance(distance)
-		);
-			
-	/* verilator lint_off WIDTH */ 
-	end else if (TOPOLOGY == "FATTREE" || TOPOLOGY == "TREE") begin : fat 
-	/* verilator lint_on WIDTH */    
-		fattree_distance_gen #(
-			.K(T1),
-			.L(T2)
-		)
-		distance_gen
-		(
-			.src_addr_encoded(src_e_addr),
-			.dest_addr_encoded(dest_e_addr),
-			.distance(distance)
-		);
-	end else if (TOPOLOGY == "STAR") begin 
-    
-				assign distance =1 ;
-	end
-	endgenerate
-
-endmodule		
-
-
-
-
-		
+    import pronoc_pkg::*;
+    input [EAw-1 : 0] src_e_addr;
+    input [EAw-1 : 0] dest_e_addr;
+    output [DISTw-1 : 0]   distance;
+    
+    generate 
+    if (IS_MESH | IS_LINE) begin : mesh_noc
+        mesh_line_distance_gen distance_gen (
+            .src_e_addr(src_e_addr),
+            .dest_e_addr(dest_e_addr),
+            .distance(distance)
+        );
+    
+    end else if (IS_TORUS | IS_RING) begin : tori_noc 
+        ring_torus_distance_gen distance_gen (
+            .src_e_addr(src_e_addr),
+            .dest_e_addr(dest_e_addr),
+            .distance(distance)
+        );
+        
+    end else if (IS_FMESH) begin :fmesh
+        fmesh_distance_gen  distance_gen (
+            .src_e_addr(src_e_addr),
+            .dest_e_addr(dest_e_addr),
+            .distance(distance)
+        );
+        
+    end else if (IS_FATTREE | IS_TREE) begin : fat 
+        fattree_distance_gen #(
+            .K(T1),
+            .L(T2)
+        ) distance_gen (
+            .src_addr_encoded(src_e_addr),
+            .dest_addr_encoded(dest_e_addr),
+            .distance(distance)
+        );
+    end else if (IS_STAR) begin 
+        assign distance =1;
+    end
+    endgenerate
+    
+endmodule
diff --git a/mpsoc/rtl/src_noc/tree_noc_top.sv b/mpsoc/rtl/src_noc/tree_noc_top.sv
index 5944d04..0912041 100644
--- a/mpsoc/rtl/src_noc/tree_noc_top.sv
+++ b/mpsoc/rtl/src_noc/tree_noc_top.sv
@@ -1,178 +1,170 @@
 `include "pronoc_def.v"
+/**********************************************************************
+**    File: tree_noc_top.v
+**    
+**    Copyright (C) 2014-2017  Alireza Monemi
+**    
+**    This file is part of ProNoC 
+**
+**    ProNoC ( stands for Prototype Network-on-chip)  is free software: 
+**    you can redistribute it and/or modify it under the terms of the GNU
+**    Lesser General Public License as published by the Free Software Foundation,
+**    either version 2 of the License, or (at your option) any later version.
+**
+**     ProNoC is distributed in the hope that it will be useful, but WITHOUT
+**     ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+**     or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
+**     Public License for more details.
+**
+**     You should have received a copy of the GNU Lesser General Public
+**     License along with ProNoC. If not, see <http:**www.gnu.org/licenses/>.
+**
+**    Description:
+**    
+**    Tree Topology NoC with Multiple Layers
+**
+**    This module implements a Tree Network-on-Chip (NoC) topology with 
+**    a hierarchical structure consisting of multiple layers. The network 
+**    has a single root router with *k* ports, each of which connects to 
+**    a child router. These child routers (leaves) have *k+1* ports, 
+**    enabling them to connect to their child routers or endpoints. 
+**    The tree structure can have *l* layers, where each layer contains 
+**    routers that further branch out to create a scalable and efficient network.
+**
+**    Key Features:
+**    - A single root router with *k* ports.
+**    - Child routers (leaves) each have *k+1* ports.
+**    - The network can have *l* layers, with each layer connected to the 
+**      previous layer in a hierarchical manner.
+**    - Scalability through hierarchical routing, allowing for efficient 
+**      communication in large systems.
+**    - Suitable for systems where hierarchical control and scalability are essential.
+**
+**********************************************************************/
 
-/**************************************
- * Module: tree
- * Date:2019-01-01  
- * Author: alireza     
- *
- * 
-Description: 
-
-    Tree      
-
- ***************************************/
-
- 
-module  tree_noc_top #(
-	parameter NOC_ID=0
-) (
-	reset,
-	clk,    
-	chan_in_all,
-	chan_out_all,
-	router_event
+module  tree_noc_top (
+    reset,
+    clk,
+    chan_in_all,
+    chan_out_all,
+    router_event
 );
-  
-  	`NOC_CONF 
-  	
-	input   clk,reset;
-	//Endpoints ports 
-	input   smartflit_chanel_t chan_in_all  [NE-1 : 0];
-	output  smartflit_chanel_t chan_out_all [NE-1 : 0];
-	
-	//Events
-	output  router_event_t  router_event [NR-1 : 0][MAX_P-1 : 0];
-	
-	//all routers port 
-	smartflit_chanel_t    router_chan_in   [NR-1 :0][MAX_P-1 : 0];
-	smartflit_chanel_t    router_chan_out  [NR-1 :0][MAX_P-1 : 0]; 
-                         
-   
-        
-	function integer addrencode;
-		input integer pos,k,n,kw;
-		integer pow,i,tmp;begin
-			addrencode=0;
-			pow=1;
-			for (i = 0; i <n; i=i+1 ) begin 
-				tmp=(pos/pow);
-				tmp=tmp%k;
-				tmp=tmp<<i*kw;
-				addrencode=addrencode | tmp;
-				pow=pow * k;
-			end
-		end   
-	endfunction 
     
-	localparam
-		PV = V * MAX_P,		
-		PFw = MAX_P * Fw,
-		CONG_ALw = CONGw * MAX_P,
-		PLKw = MAX_P * LKw,
-		PLw = MAX_P * Lw,       
-		PRAw = MAX_P * RAw; // {layer , Pos} width   
+    import pronoc_pkg::*; 
     
+    input   clk,reset;
+    //Endpoints ports 
+    input   smartflit_chanel_t chan_in_all  [NE-1 : 0];
+    output  smartflit_chanel_t chan_out_all [NE-1 : 0];
     
-
+    //Events
+    output  router_event_t  router_event [NR-1 : 0][MAX_P-1 : 0];
     
-   
+    //all routers port 
+    smartflit_chanel_t  router_chan_in   [NR-1 :0][MAX_P-1 : 0];
+    smartflit_chanel_t  router_chan_out  [NR-1 :0][MAX_P-1 : 0]; 
     
-	wire [LKw-1 : 0] current_pos_addr [NR-1 :0];
-	wire [Lw-1  : 0] current_layer_addr [NR-1 :0];   
-	wire [RAw-1 : 0] current_r_addr [NR-1 : 0];
+    function integer addrencode;
+        input integer pos,k,n,kw;
+        integer pow,i,tmp;begin
+            addrencode=0;
+            pow=1;
+            for (i = 0; i <n; i=i+1 ) begin 
+                tmp=(pos/pow);
+                tmp=tmp%k;
+                tmp=tmp<<i*kw;
+                addrencode=addrencode | tmp;
+                pow=pow * k;
+            end
+        end   
+    endfunction 
     
+    wire [LKw-1 : 0] current_pos_addr [NR-1 :0];
+    wire [Lw-1  : 0] current_layer_addr [NR-1 :0];   
+    router_config_t router_config_in [NR-1 :0];
     
-     
+    /****************
+    *    add roots
+    *****************/
+    localparam [Lw-1 : 0] ROOT_L = Lw'(L-1); 
+    localparam ROOT_ID = 0;
+    localparam BOUND = ( MAX_P > K ) ? K : MAX_P;
     
-	//add root 
-
-	localparam [Lw-1 : 0] ROOT_L = L-1; 
-	localparam ROOT_ID = 0;
- 
-	assign current_layer_addr [ROOT_ID] = ROOT_L;
-	assign current_pos_addr [ROOT_ID] = {LKw{1'b0}};       
-	assign current_r_addr[ROOT_ID] = {current_layer_addr [ROOT_ID],current_pos_addr[ROOT_ID]};
-
- 
-	router_top # (
-		.NOC_ID(NOC_ID),
-			.P(K)
-		)
-		root_router
-		(              
-			.current_r_id    (ROOT_ID),
-			.current_r_addr  (current_r_addr [ROOT_ID]), 
-			.chan_in         (router_chan_in [ROOT_ID][K-1:0]), 
-			.chan_out        (router_chan_out[ROOT_ID][K-1:0]), 
-			.router_event    (router_event[ROOT_ID][K-1 : 0]),
-			.clk             (clk            ), 
-			.reset           (reset          )
-		);
-	
-
-	genvar pos,level;
-
-
-	//add leaves
-	generate
-		for( level=1; level<L; level=level+1) begin :level_lp
-			localparam NPOS1 = powi(K,level); // number of routers in this level
-			localparam NRATTOP1 = sum_powi ( K,level); // number of routers at top levels : from root until last level
-			for( pos=0; pos<NPOS1; pos=pos+1) begin : pos_lp 
-                localparam RID = NRATTOP1+pos;
-				router_top # (
-					.NOC_ID(NOC_ID),
-					.P(K+1)// leaves have K+1 port number						
-					)
-					the_router
-					(                                  
-						.current_r_id    (RID),
-						.current_r_addr  (current_r_addr [RID]), 
-						.chan_in         (router_chan_in [RID]), 
-						.chan_out        (router_chan_out[RID]), 
-						.router_event    (router_event[RID]),
-						.clk             (clk            ), 
-						.reset           (reset          )						
-					);  
-   
-			end//pos
-		end // level
-       
-   
-		//connect all up connections
-		for (level = 1; level<L; level=level+1) begin : level_c
-			localparam  NPOS = powi(K,level); // number of routers in this level
-			localparam L1 = L-1-level;
-			localparam level2= level - 1;
-			localparam L2 = L-1-level2;
-			for ( pos = 0; pos < NPOS; pos=pos+1 ) begin : pos_c
-          
-				localparam ID1 = sum_powi ( K,level) + pos;        
-				localparam FATTREE_EQ_POS1 = pos*(K**L1);
-				localparam ADR_CODE1=addrencode(FATTREE_EQ_POS1,K,L,Kw);       
-				localparam POS2 = pos /K ;
-				localparam ID2 = sum_powi ( K,level-1) + (pos/K);
-				localparam PORT2= pos % K;  
-				localparam FATTREE_EQ_POS2 = POS2*(K**L2);
-				localparam ADR_CODE2=addrencode(FATTREE_EQ_POS2,K,L,Kw);
-        
-				// node_connection('Router[id1][k] to router[id2][pos%k];  
-				assign  router_chan_in [ID1][K] = router_chan_out [ID2][PORT2];
-				assign  router_chan_in [ID2][PORT2] = router_chan_out [ID1][K];  
-							
-				assign current_layer_addr [ID1] = L1[Lw-1 : 0];
-				assign current_pos_addr [ID1] = ADR_CODE1 [LKw-1 : 0];         
-				assign current_r_addr [ID1] = {current_layer_addr [ID1],current_pos_addr[ID1]};
-       
-        
-			end// pos
+    assign current_layer_addr [ROOT_ID] = ROOT_L;
+    assign current_pos_addr [ROOT_ID] = {LKw{1'b0}};
+    assign router_config_in[ROOT_ID].router_id = ROOT_ID [NRw-1:0];
+    assign router_config_in[ROOT_ID].router_addr = {current_layer_addr [ROOT_ID],current_pos_addr[ROOT_ID]};
+    router_top # (
+        .ROUTER_ID(ROOT_ID),
+        .P(K)
+    ) root_router (
+        .router_config_in(router_config_in[ROOT_ID]),
+        .chan_in(router_chan_in [ROOT_ID][BOUND-1:0]), 
+        .chan_out(router_chan_out[ROOT_ID][BOUND-1:0]), 
+        .router_event(router_event[ROOT_ID][BOUND-1 : 0]),
+        .clk(clk), 
+        .reset(reset)
+    );
     
-		end //level
-
-
-		// connect endpoints 
-   
-		for ( pos = 0; pos <  NE; pos=pos+1 ) begin : endpoints
-			//  node_connection T[pos] R[rid][pos %k];
-			localparam RID= sum_powi(K,L-1)+(pos/K);
-			localparam RPORT = pos%K;
+    genvar pos,level;
     
-			//$dotfile=$dotfile.node_connection('T',$i,undef,undef,'R',$r,undef,$i%($k));    
-			assign router_chan_in [RID][RPORT] =    chan_in_all [pos];                     
-			assign chan_out_all [pos] = router_chan_out [RID][RPORT];
- 
-		end
-	endgenerate    
-
-
-endmodule
+    /****************
+    *    add leaves
+    *****************/
+    generate
+    for( level=1; level<L; level=level+1) begin :level_lp
+        localparam NPOS1 = powi(K,level); // number of routers in this level
+        localparam NRATTOP1 = sum_powi ( K,level); // number of routers at top levels : from root until last level
+        for( pos=0; pos<NPOS1; pos=pos+1) begin : pos_lp 
+            localparam RID = NRATTOP1+pos;
+            assign router_config_in[RID].router_id = RID[NRw-1 : 0];
+            router_top # (
+                .ROUTER_ID(RID),
+                .P(K+1)// leaves have K+1 port number 
+            ) the_router (
+                .router_config_in(router_config_in[RID]),
+                .chan_in (router_chan_in [RID]), 
+                .chan_out (router_chan_out[RID]), 
+                .router_event (router_event[RID]),
+                .clk (clk), 
+                .reset (reset)
+            );  
+        end//pos
+    end // level
+    
+    //connect all up connections
+    for (level = 1; level<L; level=level+1) begin : level_c
+        localparam  NPOS = powi(K,level); // number of routers in this level
+        localparam L1 = L-1-level;
+        //localparam level2= level - 1;
+        //localparam L2 = L-1-level2;
+        for ( pos = 0; pos < NPOS; pos=pos+1 ) begin : pos_c
+            localparam ID1 = sum_powi ( K,level) + pos;
+            localparam FATTREE_EQ_POS1 = pos*(K**L1);
+            localparam ADR_CODE1=addrencode(FATTREE_EQ_POS1,K,L,Kw);
+            //localparam POS2 = pos /K ;
+            localparam ID2 = sum_powi ( K,level-1) + (pos/K);
+            localparam PORT2= pos % K;  
+            //localparam FATTREE_EQ_POS2 = POS2*(K**L2);
+            // node_connection('Router[id1][k] to router[id2][pos%k]; 
+            if(IS_TREE) begin
+                assign  router_chan_in [ID1][K] = router_chan_out [ID2][PORT2];
+                assign  router_chan_in [ID2][PORT2] = router_chan_out [ID1][K];
+            end
+            assign current_layer_addr [ID1] = L1[Lw-1 : 0];
+            assign current_pos_addr [ID1] = ADR_CODE1 [LKw-1 : 0];
+            assign router_config_in[ID1].router_addr =  {current_layer_addr [ID1],current_pos_addr[ID1]};
+        end// pos
+    end //level
+    
+    // connect endpoints 
+    for ( pos = 0; pos <  NE; pos=pos+1 ) begin : endpoints
+        //  node_connection T[pos] R[rid][pos %k];
+        localparam RID= sum_powi(K,L-1)+(pos/K);
+        localparam RPORT = pos%K;
+        //$dotfile=$dotfile.node_connection('T',$i,undef,undef,'R',$r,undef,$i%($k));
+        assign router_chan_in [RID][RPORT] =    chan_in_all [pos];
+        assign chan_out_all [pos] = router_chan_out [RID][RPORT];
+    end
+    endgenerate
+endmodule
\ No newline at end of file
diff --git a/mpsoc/rtl/src_noc/tree_route.sv b/mpsoc/rtl/src_noc/tree_route.sv
new file mode 100644
index 0000000..12ff422
--- /dev/null
+++ b/mpsoc/rtl/src_noc/tree_route.sv
@@ -0,0 +1,304 @@
+`include "pronoc_def.v"
+/**************************************
+*
+*   tree route function
+*
+***************************************/
+
+// ============================================================
+//  TREE: Nearest Common Ancestor w
+// ============================================================
+
+module tree_nca_routing  #(
+   parameter K   = 2, // number of last level individual router`s endpoints.
+   parameter L   = 2 // Fattree layer number (The height of FT)
+)(
+    current_addr_encoded,    // connected to current router x address
+    current_level,    //connected to current router y address
+    dest_addr_encoded,        // destination address
+    destport_encoded    // router output port
+);
+    function integer log2;
+    input integer number; begin   
+        log2=(number <=1) ? 1: 0;    
+        while(2**log2<number) begin    
+            log2=log2+1;    
+        end        
+    end   
+    endfunction // log2 
+    
+    localparam
+        Kw = log2(K),
+        LKw= L*Kw,
+        Lw = log2(L),
+        DSPw= log2(K+1);       
+    
+    input  [LKw-1 : 0]    current_addr_encoded;
+    input  [Lw-1 : 0]    current_level;    
+    input  [LKw-1 : 0]    dest_addr_encoded;
+    output [DSPw-1: 0]    destport_encoded;
+    
+    /******************
+    * There is always one destination path that can be
+    * selected for each destination endpoint. Hence we 
+    * can use the binary address of destination port      
+    *******************/   
+    
+    wire  [Kw-1 : 0]  current_addr [L-1 : 0];
+    wire  [Kw-1 : 0]  parrent_dest_addr [L-1 : 0];
+    wire  [Kw-1 : 0]  dest_addr [L-1 : 0];
+    wire  [DSPw-1 : 0]  current_node_dest_port;
+    wire [L-1 : 0] parrents_node_missmatch;   
+    
+    assign current_addr [0]={Kw{1'b0}}; 
+    assign parrent_dest_addr [0]={Kw{1'b0}}; 
+    
+    genvar i;
+    generate 
+    for(i=1; i<L; i=i+1)begin : caddr
+        /* verilator lint_off WIDTH */ 
+        assign current_addr [i] = (current_level <i)? current_addr_encoded[i*Kw-1 : (i-1)*Kw] : {Kw{1'b0}};
+        assign parrent_dest_addr [i] = (current_level<i)? dest_addr_encoded[(i+1)*Kw-1 : i*Kw] : {Kw{1'b0}};
+        /* verilator lint_on WIDTH */ 
+    end
+    
+    for(i=0; i<L; i=i+1) begin : daddr
+    // assign current_addr [i] = (current_level >=i)? current_addr_encoded[(i+1)*Kw-1 : i*Kw] : {Kw{1'b0}};
+        assign dest_addr [i] =  dest_addr_encoded[(i+1)*Kw-1 : i*Kw];
+        assign parrents_node_missmatch[i]=  current_addr [i] !=  parrent_dest_addr [i]; 
+    end//for
+    
+    if(DSPw==Kw) begin :eq
+        assign current_node_dest_port = dest_addr[current_level];
+    end else begin :neq
+        assign current_node_dest_port = {1'b0,dest_addr[current_level]};
+    end    
+    endgenerate
+    assign destport_encoded = (parrents_node_missmatch != {L{1'b0}}) ? /*go up*/ K[DSPw-1: 0] : /*go down*/current_node_dest_port;
+endmodule
+
+
+/*************************
+*  tree_conventional_routing 
+***********************/
+module tree_conventional_routing #(
+    parameter ROUTE_NAME = "NCA",
+    parameter K   = 2, // number of last level individual router`s endpoints.
+    parameter L   = 2 // Fattree layer number (The height of FT)
+)(
+    current_addr_encoded,    // connected to current router x address
+    current_level,    //connected to current router y address
+    dest_addr_encoded,        // destination address
+    destport_encoded    // router output port
+);
+    function integer log2;
+    input integer number; begin   
+        log2=(number <=1) ? 1: 0;    
+        while(2**log2<number) begin    
+            log2=log2+1;    
+        end        
+    end   
+    endfunction // log2 
+    
+    localparam
+        Kw = log2(K),
+        LKw= L*Kw,
+        Lw = log2(L),
+        DSPw= log2(K+1);
+    input  [LKw-1 : 0]    current_addr_encoded;
+    input  [Lw-1 : 0]    current_level;    
+    input  [LKw-1 : 0]    dest_addr_encoded;
+    output [DSPw-1 : 0]    destport_encoded;
+    
+    tree_nca_routing #(
+        .K(K),
+        .L(L)
+    ) nca_random_up (
+        .current_addr_encoded(current_addr_encoded),
+        .current_level(current_level),
+        .dest_addr_encoded(dest_addr_encoded),
+        .destport_encoded(destport_encoded)
+    );
+endmodule
+
+
+
+/************************************************
+*        deterministic_look_ahead_routing
+**********************************************/
+
+module  tree_deterministic_look_ahead_routing # (
+    parameter P=4
+) (
+    destport_encoded,// current router destination port 
+    dest_addr_encoded,
+    neighbors_rx,
+    neighbors_ry,
+    lkdestport_encoded // look ahead destination port     
+);
+    import pronoc_pkg::*;
+    
+    localparam
+        Pw=log2(P),
+        PLw = P * Lw,
+        PLKw = P * LKw,
+        DSPw= log2(K+1);
+        
+    input  [DSPw-1 : 0]    destport_encoded;
+    input  [LKw-1 : 0]    dest_addr_encoded;
+    input  [PLKw-1 : 0]  neighbors_rx;
+    input  [PLw-1 : 0]  neighbors_ry;
+    output [DSPw-1: 0]    lkdestport_encoded;
+    
+    wire  [LKw-1 : 0]    next_addr_encoded;
+    wire  [Lw-1 : 0]    next_level;  
+    wire  [DSPw-1: 0] lkdestport_encoded;  
+    
+    next_router_addr_selector_bin #(
+        .P(P),
+        .RXw(LKw), 
+        .RYw(Lw)
+    ) addr_predictor (
+        .destport_bin(destport_encoded[Pw-1 : 0]),
+        .neighbors_rx(neighbors_rx),
+        .neighbors_ry(neighbors_ry),
+        .next_rx(next_addr_encoded),
+        .next_ry(next_level)
+    );
+    
+    tree_conventional_routing #(
+        .ROUTE_NAME(ROUTE_NAME),
+        .K(K),
+        .L(L)
+    ) conv_routing (
+        .current_addr_encoded(next_addr_encoded),
+        .current_level(next_level),
+        .dest_addr_encoded(dest_addr_encoded),
+        .destport_encoded(lkdestport_encoded)
+    );
+endmodule
+
+
+/************************************
+*     tree_look_ahead_routing
+*************************************/
+module tree_look_ahead_routing #(
+    parameter P = 4 // port number
+)(
+    reset,
+    clk,
+    destport_encoded,// current router destination port 
+    dest_addr_encoded,
+    neighbors_rx,
+    neighbors_ry,
+    lkdestport_encoded // look ahead destination port
+);
+    import pronoc_pkg::*;
+    
+    localparam
+        PLw = P * Lw,
+        PLKw = P * LKw,
+        DSPw= log2(K+1);
+    
+    input  [DSPw-1 : 0] destport_encoded;
+    input  [LKw-1 : 0] dest_addr_encoded;
+    input  [PLKw-1 : 0] neighbors_rx;
+    input  [PLw-1 : 0] neighbors_ry;
+    output [DSPw-1: 0] lkdestport_encoded;
+    input reset,clk;
+    
+    logic [DSPw-1 : 0] destport_encoded_delayed;
+    logic [LKw-1 : 0]  dest_addr_encoded_delayed;
+    
+    tree_deterministic_look_ahead_routing #(
+        .P(P)
+    ) look_ahead_routing (
+        .destport_encoded(destport_encoded_delayed),
+        .dest_addr_encoded(dest_addr_encoded_delayed),
+        .neighbors_rx(neighbors_rx),
+        .neighbors_ry(neighbors_ry),
+        .lkdestport_encoded(lkdestport_encoded)
+    );
+    always_ff @ (`pronoc_clk_reset_edge) begin
+        if (`pronoc_reset) begin
+            destport_encoded_delayed  <= '0;  // zero DSPw bits
+            dest_addr_encoded_delayed <= '0;  // zero LKw bits
+        end else begin
+            destport_encoded_delayed  <= destport_encoded;
+            dest_addr_encoded_delayed <= dest_addr_encoded;
+        end
+    end
+endmodule
+
+
+
+
+/*************
+ * tree_destport_encoder
+ * ***********/
+module tree_destport_decoder #(
+    parameter K=2 
+)(
+    destport_decoded_o,
+    destport_encoded_i  
+);
+    function integer log2;
+    input integer number; begin   
+        log2=(number <=1) ? 1: 0;    
+        while(2**log2<number) begin    
+            log2=log2+1;    
+        end        
+    end   
+    endfunction // log2 
+    
+    localparam
+        MAX_P = K+1,
+        DSPw= log2(MAX_P);     
+    
+    input  [DSPw-1 : 0] destport_encoded_i;
+    output logic [MAX_P-1 : 0] destport_decoded_o; 
+    
+    //bin_to_one_hot
+    always_comb begin
+        destport_decoded_o = {MAX_P{1'b0}};
+        destport_decoded_o[destport_encoded_i] = 1'b1;
+    end
+endmodule
+
+
+//decode and mask destport  
+module  tree_destp_generator #(
+    parameter K=2,
+    parameter P=K+1,
+    parameter SW_LOC=0,
+    parameter DSTPw=4,
+    parameter SELF_LOOP_EN = 0
+)(
+    dest_port_in_encoded,
+    dest_port_out
+);
+    localparam
+        MAX_P = K+1,
+        P_1 = (SELF_LOOP_EN )? P : P-1;
+
+    input  [DSTPw-1: 0] dest_port_in_encoded;
+    output [P_1-1 : 0] dest_port_out;
+    
+    wire [MAX_P-1 : 0] destport_decoded;
+    
+    tree_destport_decoder #(
+        .K(K)
+    ) destport_decoder(
+        .destport_encoded_i(dest_port_in_encoded),
+        .destport_decoded_o(destport_decoded)
+    );
+    
+    destport_non_selfloop_fix #(
+        .SELF_LOOP_EN(SELF_LOOP_EN),
+        .P(P),
+        .SW_LOC(SW_LOC)
+    ) conv (
+        .destport_in(destport_decoded[P-1 : 0]),
+        .destport_out(dest_port_out[P_1-1 : 0 ])
+    );  
+endmodule
\ No newline at end of file
diff --git a/mpsoc/rtl/src_noc/tree_route.v b/mpsoc/rtl/src_noc/tree_route.v
deleted file mode 100644
index e70ba4f..0000000
--- a/mpsoc/rtl/src_noc/tree_route.v
+++ /dev/null
@@ -1,399 +0,0 @@
-`timescale 1ns / 1ps
-
-/**************************************
-*
-*   tree route function
-*
-***************************************/
-
-// ============================================================
-//  TREE: Nearest Common Ancestor w
-// ============================================================
-
-module tree_nca_routing  #(
-   parameter K   = 2, // number of last level individual router`s endpoints.
-   parameter L   = 2 // Fattree layer number (The height of FT)
-  
-)
-(
-   
-    current_addr_encoded,    // connected to current router x address
-    current_level,    //connected to current router y address
-    dest_addr_encoded,        // destination address
-    destport_encoded    // router output port
-        
-);
-    
-
-    function integer log2;
-      input integer number; begin   
-         log2=(number <=1) ? 1: 0;    
-         while(2**log2<number) begin    
-            log2=log2+1;    
-         end        
-      end   
-    endfunction // log2 
-
-        
-    localparam
-        Kw = log2(K),
-        LKw= L*Kw,
-        Lw = log2(L),
-        DSPw= log2(K+1);       
-  
-    input  [LKw-1 :0]    current_addr_encoded;
-    input  [Lw-1  :0]    current_level;    
-    input  [LKw-1 :0]    dest_addr_encoded;
-    output [DSPw-1:0]    destport_encoded;
-    
-    /******************
-        There is always one destination path that can be selected for each destination endpoint
-        Hence we can use the binary address of destination port      
-    *******************/   
-    
-    wire  [Kw-1 :0]  current_addr [L-1 : 0];
-    wire  [Kw-1 :0]  parrent_dest_addr [L-1 : 0];
-    wire  [Kw-1 :0]  dest_addr [L-1 : 0];
-    wire  [DSPw-1 :0]  current_node_dest_port;
-    
-    wire [L-1 : 0] parrents_node_missmatch;   
-    
-    assign current_addr [0]={Kw{1'b0}}; 
-    assign parrent_dest_addr [0]={Kw{1'b0}}; 
-       
-    genvar i;
-    generate 
-    for(i=1; i<L; i=i+1)begin : caddr
-        /* verilator lint_off WIDTH */ 
-        assign current_addr [i] = (current_level <i)? current_addr_encoded[i*Kw-1 : (i-1)*Kw] : {Kw{1'b0}};
-        assign parrent_dest_addr [i] = (current_level<i)? dest_addr_encoded[(i+1)*Kw-1 : i*Kw] : {Kw{1'b0}};
-        /* verilator lint_on WIDTH */ 
-    end
-    
-    
-    for(i=0; i<L; i=i+1) begin : daddr
-       // assign current_addr [i] = (current_level >=i)? current_addr_encoded[(i+1)*Kw-1 : i*Kw] : {Kw{1'b0}};
-       
-        assign dest_addr [i] =  dest_addr_encoded[(i+1)*Kw-1 : i*Kw];
-        assign parrents_node_missmatch[i]=  current_addr [i] !=  parrent_dest_addr [i]; 
-    end//for
-    
-    if(DSPw==Kw) begin :eq
-        assign current_node_dest_port = dest_addr[current_level];
-    end else begin :neq
-        assign current_node_dest_port = {1'b0,dest_addr[current_level]};
-    end    
-    endgenerate
-   
-    assign destport_encoded = (parrents_node_missmatch != {L{1'b0}}) ? /*go up*/ K[DSPw-1: 0] :  /*go down*/current_node_dest_port;
-      
-endmodule
-
-
-/*************************
- *  tree_conventional_routing 
- * **********************/
-
-
-module tree_conventional_routing #(
-    parameter ROUTE_NAME = "NCA",
-    parameter K   = 2, // number of last level individual router`s endpoints.
-    parameter L   = 2 // Fattree layer number (The height of FT)
- )
-(
-  
-    current_addr_encoded,    // connected to current router x address
-    current_level,    //connected to current router y address
-    dest_addr_encoded,        // destination address
-    destport_encoded    // router output port
-        
-);
-    
-
-    function integer log2;
-      input integer number; begin   
-         log2=(number <=1) ? 1: 0;    
-         while(2**log2<number) begin    
-            log2=log2+1;    
-         end        
-      end   
-    endfunction // log2 
-        
-    localparam
-        Kw = log2(K),
-        LKw= L*Kw,
-        Lw = log2(L),
-        DSPw= log2(K+1);
-   
-    input  [LKw-1 :0]    current_addr_encoded;
-    input  [Lw-1  :0]    current_level;    
-    input  [LKw-1 :0]    dest_addr_encoded;
-    output [DSPw-1  :0]    destport_encoded;
-  
-        tree_nca_routing #(
-            .K(K),
-            .L(L)
-        )
-        nca_random_up
-        (
-            .current_addr_encoded(current_addr_encoded),
-            .current_level(current_level),
-            .dest_addr_encoded(dest_addr_encoded),
-            .destport_encoded(destport_encoded)
-        );
-  
-
-endmodule
-
-
-
-/************************************************
-        deterministic_look_ahead_routing
-**********************************************/
-
-module  tree_deterministic_look_ahead_routing #(
-    parameter P=4,
-    parameter ROUTE_NAME = "NCA_RND_UP",
-    parameter K   = 2, // number of last level individual router`s endpoints.
-    parameter L   = 2 // Fattree layer number (The height of FT)
-    
-  )
-  (
-    destport_encoded,// current router destination port 
-    dest_addr_encoded,
-    neighbors_rx,
-    neighbors_ry,
-    lkdestport_encoded // look ahead destination port     
- );
-    
-   
-   function integer log2;
-      input integer number; begin   
-         log2=(number <=1) ? 1: 0;    
-         while(2**log2<number) begin    
-            log2=log2+1;    
-         end        
-      end   
-    endfunction // log2 
-
-        
-    localparam
-        Kw = log2(K),
-        LKw= L*Kw,
-        Lw = log2(L),
-        Pw=log2(P),
-        PLw = P * Lw,
-        PLKw = P * LKw,
-        DSPw= log2(K+1);
-                    
-   
-    input  [DSPw-1 :0]    destport_encoded;
-    input  [LKw-1 :0]    dest_addr_encoded;
-    input  [PLKw-1 : 0]  neighbors_rx;
-    input  [PLw-1 : 0]  neighbors_ry;
-    output [DSPw-1: 0]    lkdestport_encoded;
-      
-      
-    wire  [LKw-1 :0]    next_addr_encoded;
-    wire  [Lw-1  :0]    next_level;  
-    wire  [DSPw-1:0] lkdestport_encoded;  
-             
-    next_router_addr_selector_bin #(
-         .P(P),
-         .RXw(LKw), 
-         .RYw(Lw)
-    )
-    addr_predictor
-    (
-        .destport_bin(destport_encoded[Pw-1 : 0]),
-        .neighbors_rx(neighbors_rx),
-        .neighbors_ry(neighbors_ry),
-        .next_rx(next_addr_encoded),
-        .next_ry(next_level)
-    );
-  
-     
-    tree_conventional_routing #(        
-        .ROUTE_NAME(ROUTE_NAME),
-        .K(K),
-        .L(L)        
-    )
-    conv_routing
-    (
-      
-        .current_addr_encoded(next_addr_encoded),
-        .current_level(next_level),
-        .dest_addr_encoded(dest_addr_encoded),
-        .destport_encoded(lkdestport_encoded)
-    );
-     
- endmodule
-
-
-
-/************************************
-
-     tree_look_ahead_routing
-
-*************************************/
-
-module tree_look_ahead_routing #(
-    parameter ROUTE_NAME = "NCA",
-    parameter P = 4,
-    parameter L = 2,
-    parameter K = 2
-   
-)
-(
-    reset,
-    clk,
-    destport_encoded,// current router destination port 
-    dest_addr_encoded,
-    neighbors_rx,
-    neighbors_ry,
-    lkdestport_encoded // look ahead destination port     
-);
-    
-   function integer log2;
-      input integer number; begin   
-         log2=(number <=1) ? 1: 0;    
-         while(2**log2<number) begin    
-            log2=log2+1;    
-         end        
-      end   
-    endfunction // log2 
-
-        
-    localparam
-        Kw = log2(K),
-        LKw= L*Kw,
-        Lw = log2(L),
-        PLw = P * Lw,
-        PLKw = P * LKw,
-        DSPw= log2(K+1);
-   
-    input  [DSPw-1 :0]    destport_encoded;
-    input  [LKw-1 :0]    dest_addr_encoded;
-    input  [PLKw-1 : 0]  neighbors_rx;
-    input  [PLw-1 : 0]  neighbors_ry;
-    output [DSPw-1: 0]    lkdestport_encoded;
-    input                   reset,clk;
-    
-    wire  [DSPw-1 :0]    destport_encoded_delayed;
-    wire  [LKw-1 :0]    dest_addr_encoded_delayed;
-    
-     tree_deterministic_look_ahead_routing #(
-        .P(P),
-        .ROUTE_NAME(ROUTE_NAME),
-        .K(K),
-        .L(L)
-     )
-     look_ahead_routing
-     (
-        .destport_encoded(destport_encoded_delayed),
-        .dest_addr_encoded(dest_addr_encoded_delayed),
-        .neighbors_rx(neighbors_rx),
-        .neighbors_ry(neighbors_ry),
-        .lkdestport_encoded(lkdestport_encoded)
-     );
-     
-      pronoc_register #(.W(DSPw)) reg1 (.in(destport_encoded  ), .out(destport_encoded_delayed), .reset(reset), .clk(clk));
-      pronoc_register #(.W(LKw )) reg2 (.in(dest_addr_encoded ), .out(dest_addr_encoded_delayed),.reset(reset), .clk(clk));
-     
-        
-
-    
-endmodule
-
-
-
-
-
- /*************
- * tree_destport_encoder
- * ***********/
-
- module tree_destport_decoder #(
-     parameter K=2 
- )(
-    destport_decoded_o,
-    destport_encoded_i  
- );
-     function integer log2;
-      input integer number; begin   
-         log2=(number <=1) ? 1: 0;    
-         while(2**log2<number) begin    
-            log2=log2+1;    
-         end        
-      end   
-    endfunction // log2 
- 
-    localparam
-        MAX_P = K+1,
-        DSPw= log2(MAX_P);     
- 
-    input  [DSPw-1 : 0] destport_encoded_i;
-    output [MAX_P-1 : 0] destport_decoded_o; 
-    
-    
-    bin_to_one_hot #(
-        .BIN_WIDTH(DSPw),
-        .ONE_HOT_WIDTH(MAX_P)
-    )
-    cnvt
-    (
-        .bin_code(destport_encoded_i),
-        .one_hot_code(destport_decoded_o)
-    );
-       
-endmodule
-
-
-
-//decode and mask destport  
-module  tree_destp_generator #(
-    parameter K=2,
-    parameter P=K+1,
-    parameter SW_LOC=0,
-    parameter DSTPw=4,
-    parameter SELF_LOOP_EN = "NO"
-)(
-    dest_port_in_encoded,
-    dest_port_out
-);
-
-
-    localparam
-        MAX_P = K+1,
-        P_1 = (SELF_LOOP_EN == "NO")? P-1 : P;
-        
-    input  [DSTPw-1:0] dest_port_in_encoded;
-    output [P_1-1 : 0] dest_port_out;    
-    
-    wire [MAX_P-1 : 0] destport_decoded;
-  
-        tree_destport_decoder #(           
-            .K(K)
-        )
-        destport_decoder
-        (
-            .destport_encoded_i(dest_port_in_encoded),
-            .destport_decoded_o(destport_decoded)
-        );
-        
-    generate 
-    if(SELF_LOOP_EN == "NO") begin : nslp      
-        remove_sw_loc_one_hot #(
-            .P(P),
-            .SW_LOC(SW_LOC)
-        )
-        conv
-        (
-            .destport_in(destport_decoded[P-1 : 0]),
-            .destport_out(dest_port_out[P_1-1  :   0 ])
-        );  
-    end else begin : slp
-        assign dest_port_out = destport_decoded;    
-    end
-    endgenerate
- endmodule
diff --git a/mpsoc/rtl/src_noc/wrra.v b/mpsoc/rtl/src_noc/wrra.sv
similarity index 68%
rename from mpsoc/rtl/src_noc/wrra.v
rename to mpsoc/rtl/src_noc/wrra.sv
index eaf80ec..afcbf1e 100644
--- a/mpsoc/rtl/src_noc/wrra.v
+++ b/mpsoc/rtl/src_noc/wrra.sv
@@ -1,5 +1,4 @@
-`timescale 1ns / 1ps
-
+`include "pronoc_def.v"
 /**********************************************************************
 **  File:  wrra.v
 **  Date:2017-07-11   
@@ -43,22 +42,18 @@ module  wrra #(
     parameter ARBITER_WIDTH = 8,
     parameter WEIGHTw = 4, // maximum weight size in bits
     parameter EXT_P_EN = 1 
-        
-)
-(  
-   
-   ext_pr_en_i,
-   clk, 
-   reset, 
-   request, 
-   grant,
-   any_grant,
-   weight_array,
-   winner_weight_consumed
+)(  
+    ext_pr_en_i,
+    clk, 
+    reset, 
+    request, 
+    grant,
+    any_grant,
+    weight_array,
+    winner_weight_consumed
 );
-
     localparam WEIGHT_ARRAYw= WEIGHTw * ARBITER_WIDTH;
-
+    
     input                                  ext_pr_en_i;
     input     [ARBITER_WIDTH-1  :    0]    request;
     output    [ARBITER_WIDTH-1  :    0]    grant;
@@ -67,8 +62,7 @@ module  wrra #(
     input                                  reset;
     input    [WEIGHT_ARRAYw-1   :   0]     weight_array;
     output                                 winner_weight_consumed;
-
-
+    
     wire [WEIGHTw-1 :   0] weight [ARBITER_WIDTH-1  :   0];
     wire [ARBITER_WIDTH-1:  0] weight_counter_is_reset;
     
@@ -77,47 +71,26 @@ module  wrra #(
     for (i=0; i<ARBITER_WIDTH; i=i+1) begin : wcount 
         // seperate wieghts
         assign weight [i] = weight_array [ ((i+1)*WEIGHTw)-1    :   i*WEIGHTw];
-       
         weight_counter #(
             .WEIGHTw(WEIGHTw)
-        )
-        w_counter
-        (
+        ) w_counter (
             .load_i(1'b0),
             .weight_i(weight [i]),
             .reset(reset),
             .clk(clk),
             .decr(grant[i]),
-            .out(weight_counter_is_reset[i])
+            .Q_out(weight_counter_is_reset[i])
         );
-    
     end
     endgenerate
     
-      
-    
     // one hot mux
-    
-    onehot_mux_1D #(
-        .W(1),
-        .N(ARBITER_WIDTH)        
-    )
-    mux
-    (
-        .in(weight_counter_is_reset),
-        .out(winner_weight_consumed),
-        .sel(grant)
-    );
-    
+    assign winner_weight_consumed = |(weight_counter_is_reset & grant);    
     wire priority_en = (EXT_P_EN == 1) ? ext_pr_en_i & winner_weight_consumed : winner_weight_consumed;
-
     //round robin arbiter with external priority
-
-     arbiter_priority_en #(
+    arbiter_priority_en #(
         .ARBITER_WIDTH(ARBITER_WIDTH)
-    )
-    rra
-    (
+    ) rra (
         .request(request),
         .grant(grant),
         .any_grant(any_grant),
@@ -125,32 +98,21 @@ module  wrra #(
         .reset(reset),
         .priority_en(priority_en)
     );
-
 endmodule
 
 
-
-
-
-
 module  rra_priority_lock #(
-    parameter    ARBITER_WIDTH    =8        
-)
-(  
-   
-   ext_pr_en_i,
-   winner_weight_consumed,
-   pr_en_array_i,
-   
-   clk, 
-   reset, 
-  
-   request, 
-   grant,
-   any_grant
+    parameter ARBITER_WIDTH  = 8
+)(  
+    ext_pr_en_i,
+    winner_weight_consumed,
+    pr_en_array_i,
+    clk, 
+    reset, 
+    request, 
+    grant,
+    any_grant
 );
-
-    
     input     [ARBITER_WIDTH-1:     0]     pr_en_array_i;
     input                                  ext_pr_en_i;
     output                                 winner_weight_consumed;
@@ -160,29 +122,13 @@ module  rra_priority_lock #(
     input                                  clk;
     input                                  reset;  
     
-    
     // one hot mux
-    
-    onehot_mux_1D #(
-        .W(1),
-        .N(ARBITER_WIDTH)        
-    )
-    mux
-    (
-        .in(pr_en_array_i),
-        .out(winner_weight_consumed),
-        .sel(grant)
-    );
-    
+    assign winner_weight_consumed = |(pr_en_array_i & grant);
     wire priority_en = ext_pr_en_i & winner_weight_consumed;
-
     //round robin arbiter with external priority
-
-     arbiter_priority_en #(
+    arbiter_priority_en #(
         .ARBITER_WIDTH(ARBITER_WIDTH)
-    )
-    rra
-    (
+    ) rra (
         .request(request),
         .grant(grant),
         .any_grant(any_grant),
@@ -190,57 +136,47 @@ module  rra_priority_lock #(
         .reset(reset),
         .priority_en(priority_en)
     );
-
 endmodule
 
-
-
-
-
 /**************
 *   weight_counter
-*
 ***************/
-
-
 module weight_counter #(
     parameter WEIGHTw=4
 )(
-    
     weight_i,
     decr,
     load_i,
-    out,
+    Q_out,
     reset,
-    clk    
-
+    clk
 );
-
     input [WEIGHTw-1    :   0]  weight_i;
     input reset,clk,decr,load_i;
-    output  out;
+    output  Q_out;
     wire [WEIGHTw-1    :   0]  weight;
-
-    reg  [WEIGHTw-1    :   0] counter_next;
-    wire [WEIGHTw-1    :   0] counter;
+    
+    logic  [WEIGHTw-1    :   0] counter_next;
+    logic [WEIGHTw-1    :   0] counter;
     wire couner_zero, load;
     
     assign couner_zero = counter == {WEIGHTw{1'b0}};
     assign load =  (counter > weight_i) | load_i;
-    assign out = couner_zero;
+    assign Q_out = couner_zero;
     assign weight= (weight_i == {WEIGHTw{1'b0}} )? 1 : weight_i; // minimum weight is 1;
     always @(*)begin 
         counter_next = counter;
         if(load) counter_next  = weight- 1'b1 ;
         if(decr) counter_next  = (couner_zero)? weight-1'b1  : counter - 1'b1; // if the couner has zero value then the load is active not decrese
-    
     end
     
-    pronoc_register #(.W(WEIGHTw)) reg2 (.in(counter_next ), .out(counter), .reset(reset), .clk(clk));
-  
-  
-
-
+    always_ff @ (`pronoc_clk_reset_edge) begin
+        if (`pronoc_reset) begin
+            counter <= '0;  
+        end else begin
+            counter <= counter_next;
+        end
+    end
 endmodule
 
 
@@ -248,87 +184,77 @@ endmodule
 *   weight_counter
 *
 ***************/
-
-
 module classic_weight_counter #(
     parameter WEIGHTw=4
 )(
-    
     weight_i,
     decr,
     load_i,
-    out,
+    Q_out,
     reset,
-    clk    
-
+    clk
 );
-
     input [WEIGHTw-1    :   0]  weight_i;
     input reset,clk,decr,load_i;
-    output  out;
+    output  Q_out;
     wire [WEIGHTw-1    :   0]  weight;
-
-    reg  [WEIGHTw-1    :   0] counter_next;
-    wire [WEIGHTw-1    :   0] counter;
-    wire couner_zero, load;
     
-    assign couner_zero = counter == {WEIGHTw{1'b0}};
+    logic [WEIGHTw-1    :   0] counter_next;
+    logic [WEIGHTw-1    :   0] counter;
+    wire counter_zero, load;
+    
+    assign counter_zero = counter == {WEIGHTw{1'b0}};
     assign load =  (counter > weight_i) | load_i;
-    assign out = couner_zero;
+    assign Q_out = counter_zero;
     assign weight= (weight_i == {WEIGHTw{1'b0}} )? 1 : weight_i; // minimum weight is 1;
     always @(*)begin 
         counter_next = counter;
         if(load) counter_next  = weight- 1'b1 ;
-        if(decr && !couner_zero) counter_next  = counter - 1'b1; // if the couner has zero value then the load is active not decrese
-    
+        if(decr && !counter_zero) counter_next  = counter - 1'b1; // if the counter has zero value then the load is active not decrese
     end
     
-    pronoc_register #(.W(WEIGHTw)) reg2 (.in(counter_next ), .out(counter), .reset(reset), .clk(clk));
-    
-    
+    always_ff @ (`pronoc_clk_reset_edge) begin
+        if (`pronoc_reset) begin
+            counter <= '0; 
+        end else begin
+            counter <= counter_next;
+        end
+    end
 endmodule
 
-
-
 /***************
 *   weight_control
 ***************/
-
-
 module  weight_control #(
     parameter ARBITER_TYPE="WRRA",
     parameter SW_LOC=0,
     parameter WEIGHTw= 4,
     parameter WRRA_CONFIG_INDEX=0,
     parameter P=5,
-    parameter SELF_LOOP_EN = "NO"
-)
-(
-   
+    parameter SELF_LOOP_EN = 0
+)(
     sw_is_granted,
     flit_is_tail,  
     iport_weight,
     granted_dest_port,
     weight_is_consumed_o, 
     oports_weight,  
-    refresh_w_counter,     
+    refresh_w_counter,
     clk,
-    reset           
-);      
-
+    reset
+);
     localparam 
         W = WEIGHTw,
         WP = W * P,
-        P_1 = (SELF_LOOP_EN=="NO") ?  P-1 : P;
-    
+        P_1 = (SELF_LOOP_EN) ?  P : P-1;
     localparam [W-1 : 0] INIT_WEIGHT = 1;
     localparam [W-1 : 0] MAX_WEIGHT = {W{1'b1}}-1'b1;
+    localparam  
+        PROPOGATE_EQUALL = (WRRA_CONFIG_INDEX==0 ),
+        PROPOGATE_LIMITED = (WRRA_CONFIG_INDEX==1 ),
+        PROPOGATE_NEQ1 = (WRRA_CONFIG_INDEX==2 ),
+        PROPOGATE_NEQ2 = (WRRA_CONFIG_INDEX==3 );
         
-    localparam  PROPOGATE_EQUALL = (WRRA_CONFIG_INDEX==0 ),
-                PROPOGATE_LIMITED = (WRRA_CONFIG_INDEX==1 ),
-                PROPOGATE_NEQ1 = (WRRA_CONFIG_INDEX==2 ),
-                PROPOGATE_NEQ2 = (WRRA_CONFIG_INDEX==3 );
-                
     input  sw_is_granted , flit_is_tail;
     input  [WEIGHTw-1 : 0] iport_weight;
     input  clk,reset;                  
@@ -336,7 +262,7 @@ module  weight_control #(
     input  [P_1-1 : 0] granted_dest_port; 
     output [WP-1 : 0] oports_weight;  
     input refresh_w_counter;
-  
+    
     // wire ivc_empty = ~ivc_not_empty;    
     wire counter_is_reset;
     wire weight_dcrease_en = sw_is_granted & flit_is_tail;
@@ -345,13 +271,11 @@ module  weight_control #(
     reg  [W-1 : 0] oport_weight [P-1 : 0];
     
     generate
-    if(SELF_LOOP_EN == "NO") begin : nslp
+    if(SELF_LOOP_EN == 0) begin : nslp
         add_sw_loc_one_hot #(
             .P(P),
             .SW_LOC(SW_LOC)
-        )
-        add_sw_loc
-        (
+        ) add_sw_loc  (
             .destport_in(granted_dest_port),
             .destport_out(dest_port)
         );
@@ -361,40 +285,29 @@ module  weight_control #(
     endgenerate
     
     assign oports_weight [W-1 : 0] = {W{1'b0}};
-    
     genvar i;
     generate 
-    
-    
     if(PROPOGATE_EQUALL | PROPOGATE_LIMITED )begin : eq         
-        
-         for (i=1;i<P;i=i+1)begin : port
-             if(i==SW_LOC) begin : if1
+        for (i=1;i<P;i=i+1)begin : P_
+            if(i==SW_LOC) begin : if1
                 assign oports_weight [(i+1)*W-1 : i*W] = {W{1'b0}};
-             end else begin :else1
+            end else begin :else1
                 assign oports_weight[(i+1)*W-1 : i*W]  = iport_weight; 
             end
          end //for
-           
     end else if (PROPOGATE_NEQ1) begin :neq1
-        
         always @(*)begin 
-               oport_weight_counter[0]= {W{1'b0}};// the output port weight of local port is useless. hence fix it as zero.
-               oport_weight[0]= {W{1'b0}};
+            oport_weight_counter[0]= {W{1'b0}};// the output port weight of local port is useless. hence fix it as zero.
+            oport_weight[0]= {W{1'b0}};
         end
-    
-         
-        for (i=1;i<P;i=i+1)begin : port
-             if(i==SW_LOC) begin : if1
-                
+        for (i=1;i<P;i=i+1)begin : P_
+            if(i==SW_LOC) begin : if1
                 always @(*) begin 
                     oport_weight_counter[i]= {W{1'b0}};// The loopback injection is forbiden hence it will be always as zero.
                     oport_weight[i]= {W{1'b0}};
                 end
                 assign oports_weight [(i+1)*W-1 : i*W] = {W{1'b0}};
-             end else begin :else1
-        
-
+            end else begin :else1
                 always @ (`pronoc_clk_reset_edge )begin 
                     if(`pronoc_reset) begin 
                         oport_weight_counter[i]<=INIT_WEIGHT;
@@ -412,34 +325,23 @@ module  weight_control #(
                     end
                 end //always
                 assign oports_weight [(i+1)*W-1 : i*W] = oport_weight[i];
-             end  //else 
-        
-           
-           
+            end  //else 
         end //for
-    
-    
     end else begin : neq2 //if (PROPOGATE_NEQ1) :neq1 
-        
-    
-         
-    for (i=0;i<P;i=i+1)begin : port
-        if(i==0) begin : local_p
-            always @ (posedge clk)begin             
-                        oport_weight_counter[i]<= {W{1'b0}};// the output port weight of local port is useless. hence fix it as zero.
-                        oport_weight[i]<= {W{1'b0}};
-            end//always
-        end//local_p
-
-             else if(i==SW_LOC) begin : if1
-                
-               always @ (posedge clk)begin 
+        for (i=0;i<P;i=i+1)begin : port
+            if(i==0) begin : local_p
+                always @ (posedge clk)begin             
+                    oport_weight_counter[i]<= {W{1'b0}};// the output port weight of local port is useless. hence fix it as zero.
+                    oport_weight[i]<= {W{1'b0}};
+                end//always
+            end//local_p
+            else if(i==SW_LOC) begin : if1
+                always @ (posedge clk)begin 
                     oport_weight_counter[i]<= {W{1'b0}};// The loopback injection is forbiden hence it will be always as zero.
                     oport_weight[i]<= {W{1'b0}};
                 end
                 assign oports_weight [(i+1)*W-1 : i*W] = {W{1'b0}};
-             end else begin :else1
-        
+            end else begin :else1
                 always @ (`pronoc_clk_reset_edge )begin 
                     if(`pronoc_reset) begin 
                         oport_weight_counter[i]<= INIT_WEIGHT;
@@ -448,7 +350,6 @@ module  weight_control #(
                         else if (weight_dcrease_en && dest_port[i] && oport_weight_counter[i] <MAX_WEIGHT )oport_weight_counter[i]<= oport_weight_counter[i] +1'b1;
                     end
                 end //always
-                
                 always @ (`pronoc_clk_reset_edge )begin 
                     if(`pronoc_reset) begin 
                         oport_weight[i]<={W{1'b0}};
@@ -464,81 +365,53 @@ module  weight_control #(
                         end//weight_dcr                          
                     end//else reset
                 end //always
-                
                 assign oports_weight [(i+1)*W-1 : i*W] = oport_weight[i];
-             end  //else            
-           
+            end  //else            
         end //for    
-    
-    end
-
-
-
-
+    end //neq2
     /* verilator lint_off WIDTH */
     if(ARBITER_TYPE == "WRRA_CLASSIC") begin : wrra_classic 
     /* verilator lint_on WIDTH */
         // use classic WRRA. only for compasrion with propsoed wrra 
-    
         classic_weight_counter #(
             .WEIGHTw(WEIGHTw)
-        )
-           iport_weight_counter
-        (
+        ) iport_weight_counter  (
             .load_i(refresh_w_counter),    
             .weight_i(iport_weight),
             .reset(reset),
             .clk(clk),
             .decr(weight_dcrease_en),
-            .out(counter_is_reset)
+            .Q_out(counter_is_reset)
         );     
-    
     end else begin : wrra_mine
         // weight counters   
         weight_counter #(
             .WEIGHTw(WEIGHTw)
-        )
-        iport_weight_counter
-        (
+        ) iport_weight_counter (
             .load_i(refresh_w_counter),    
             .weight_i(iport_weight),
             .reset(reset),
             .clk(clk),
             .decr(weight_dcrease_en),
-            .out(counter_is_reset)
+            .Q_out(counter_is_reset)
         ); 
-    
-    
     end    
-    
     endgenerate
-    
-      
-  
-    
-   
-    
-    
     assign weight_is_consumed_o = counter_is_reset; //  & flit_is_tail ;
-
 endmodule
 
 
-
-
 /***************
 *       wrra_contention_gen
 * generate contention based on number of request to 
 * the same output port
 ***************/
-
-
 module  wrra_contention_gen #(
     parameter V=4,
     parameter P=5,
     parameter WRRA_CONFIG_INDEX=0,
     parameter WEIGHTw = 4, // WRRA width
-    parameter SELF_LOOP_EN ="NO"
+    parameter SELF_LOOP_EN = 0
 )(
     ovc_is_assigned_all, 
     ivc_request_all,
@@ -548,18 +421,17 @@ module  wrra_contention_gen #(
     contention_all,
     limited_oport_weight_all    
 );
-
     function integer log2;
-      input integer number; begin   
-         log2=(number <=1) ? 1: 0;    
-         while(2**log2<number) begin    
+    input integer number; begin   
+        log2=(number <=1) ? 1: 0;    
+        while(2**log2<number) begin    
             log2=log2+1;    
-         end       
-      end   
+        end       
+    end   
     endfunction // log2 
     
     localparam 
-        P_1 = (SELF_LOOP_EN == "NO") ?  P-1 : P,
+        P_1 = (SELF_LOOP_EN) ?  P : P-1,
         PV = P * V, 
         VP_1= V * P_1,
         PVP_1 = PV * P_1,
@@ -568,13 +440,10 @@ module  wrra_contention_gen #(
         W= WEIGHTw,
         WP= W * P,
         WPP = WP * P; 
-        
-        localparam 
-            VALID_IF_HAS_FLIT  = 1, //1: has flit 0: VC-Assigned
-            PROPOGATE_EQUALL = (WRRA_CONFIG_INDEX==0 ),
-            PROPOGATE_LIMITED = (WRRA_CONFIG_INDEX==1 );
-       
-        
+    localparam 
+        VALID_IF_HAS_FLIT  = 1, //1: has flit 0: VC-Assigned
+        PROPOGATE_EQUALL = (WRRA_CONFIG_INDEX==0 ),
+        PROPOGATE_LIMITED = (WRRA_CONFIG_INDEX==1 );
     input  [PVP_1-1 :  0] dest_port_all;
     input  [PV-1 : 0] ovc_is_assigned_all; 
     input  [PV-1 : 0] ivc_request_all;
@@ -583,93 +452,65 @@ module  wrra_contention_gen #(
     input  [WPP-1 : 0] oports_weight_all;
     input  [WP-1 : 0] limited_oport_weight_all;
     
-    
     wire [P-1 : 0] destport_sum [P-1 : 0];//destport_sum[inport-num][out-num]=  out-port is requested by inport-num
     wire [P-1 : 0] contention_one_hot [P-1  :   0];  //contention_one_hot[outport-num][inport-num]=  inport- is requesting this outport
-    
     wire [W-1 : 0] iport_weight [P-1  :   0];
     wire [W-1 : 0] weight_sum [P-1  :   0];  
     wire [W-1 : 0] contention [P-1  :   0];  
     wire [WP-1 : 0] weight_array_per_outport [P-1  :   0]; 
     wire [WP-1: 0] oports_weight [P-1  :   0]; 
     // weight_array_per_outport[outport-num][inport-num]= weight-inport-num if  inport- is requesting this outport
+    wire [PV-1 : 0] weight_is_valid = (VALID_IF_HAS_FLIT)? ivc_request_all : ovc_is_assigned_all ;
     
-   
-   wire [PV-1 : 0] weight_is_valid = (VALID_IF_HAS_FLIT)? ivc_request_all : ovc_is_assigned_all ;
-   
     genvar j,i;
     generate 
     for (i=0;i<P; i=i+1) begin : port_lp
         assign iport_weight[i]= iport_weight_all[(i+1)*W-1  : i*W]; 
         assign oports_weight[i]= oports_weight_all [(i+1)*WP-1  : i*WP];       
-       
-         //get the lis of all destination ports requested by each port
-         wrra_inputport_destports_sum #(
+        //get the lis of all destination ports requested by each port
+        wrra_inputport_destports_sum #(
             .V(V),
             .P(P),
             .SW_LOC(i),
             .SELF_LOOP_EN(SELF_LOOP_EN)
-         )
-         destports_sum
-         (
+        ) accumulator (
             .weight_is_valid(weight_is_valid[(i+1)*V-1  : i*V]),
             .dest_ports(dest_port_all [(i+1)*VP_1-1  : i*VP_1]),
             .destports_sum(destport_sum[i])
-         );
-         
-        
-         
-         
-         for (j=0;j<P;j=j+1) begin : outlp1 
+        );
+        for (j=0;j<P;j=j+1) begin : outlp1 
             assign  contention_one_hot[j][i] =  destport_sum[i][j];
             if(PROPOGATE_EQUALL | PROPOGATE_LIMITED ) begin : peq
-               assign  weight_array_per_outport[j][(i+1)*W-1  : i*W] = (contention_one_hot[j][i])? iport_weight[i] : {W{1'b0}}; 
+                assign  weight_array_per_outport[j][(i+1)*W-1  : i*W] = (contention_one_hot[j][i])? iport_weight[i] : {W{1'b0}}; 
             end  
             else begin : pneq
-               assign  weight_array_per_outport[j][(i+1)*W-1  : i*W] = (contention_one_hot[j][i])? oports_weight[i][(j+1)*W-1 : j*W] : {W{1'b0}};               
+                assign  weight_array_per_outport[j][(i+1)*W-1  : i*W] = (contention_one_hot[j][i])? oports_weight[i][(j+1)*W-1 : j*W] : {W{1'b0}};               
             end         
-         end//for
-         
-                 
-         //contention is the sum of all inputports weights requesting this outputport
-         accumulator #(
+        end//for
+        //contention is the sum of all inputports weights requesting this outputport
+        accumulator #(
             .INw(WP),
             .OUTw(W),
             .NUM(P)
-         
-         )
-         accum
-         (
+        ) accum (
             .in_all(weight_array_per_outport[i]),
-            .out(weight_sum[i])         
-         );
-         
-       
-         if(PROPOGATE_LIMITED) begin : limted
-         
+            .sum_o(weight_sum[i])         
+        );
+        if(PROPOGATE_LIMITED) begin : limted
             wire [W-1 : 0] limited_oport_weight [P-1 : 0]; 
             for (j=0;j<P;j=j+1) begin : outlp1 
                 assign  limited_oport_weight [j] = limited_oport_weight_all [(j+1)*W-1 : j*W];
                 assign contention[j] = (limited_oport_weight [j] > weight_sum [j]) ? weight_sum [j] : limited_oport_weight [j];
                 
             end
-         
-         
-         end else begin : eq_or_actual
+        end else begin : eq_or_actual
             for (j=0;j<P;j=j+1) begin : outlp1 
                 assign contention[j] = weight_sum [j];
             end
-         end
-         
-         
-         
-       
-         
-         assign contention_all[(i+1)*W-1 : i*W] =  contention[i];
-    
+        end
+        assign contention_all[(i+1)*W-1 : i*W] =  contention[i];
     end    
     endgenerate  
-
 endmodule
 
 
@@ -677,71 +518,58 @@ module  wrra_inputport_destports_sum #(
     parameter V=4,
     parameter P=5,
     parameter SW_LOC=0,
-    parameter SELF_LOOP_EN = "NO"
+    parameter SELF_LOOP_EN = 0
 )(
     weight_is_valid,
     dest_ports,
     destports_sum
-    
 );
-
     localparam 
-        P_1 = (SELF_LOOP_EN== "NO")? P - 1 : P,
+        P_1 = (SELF_LOOP_EN) ? P : P - 1,
         VP_1 = V * P_1;
-
     input [V-1 : 0] weight_is_valid;
     input [VP_1-1 : 0] dest_ports;
     output [P-1 : 0] destports_sum;
-     
-    wire [VP_1-1 : 0] dest_ports_masked;     
-
-  
-    wire  [P_1-1    :   0] sum;
     
+    wire [P_1-1 : 0] dest_ports_masked [V-1 : 0]; // dest_ports_masked[inport-num][outport-num]=  out-port is requested by inport-num
+    wire [P_1-1 : 0] sum;
+
     genvar i;
     generate 
     for (i=0;i<V; i=i+1) begin : port_lp
-        assign  dest_ports_masked [(i+1)*P_1-1  : i*P_1] =  (weight_is_valid[i]) ? dest_ports [(i+1)*P_1-1  : i*P_1] : {P_1{1'b0}};     
-    end    
-    
-    
-    custom_or #(
-        .IN_NUM(V),
-        .OUT_WIDTH(P_1)
-    )
-    custom_or(
-        .or_in(dest_ports_masked),
-        .or_out(sum)
+        assign  dest_ports_masked [i] =  (weight_is_valid[i]) ? dest_ports [(i+1)*P_1-1  : i*P_1] : {P_1{1'b0}};
+    end
+
+    reduction_or #(
+        .N(V),
+        .W(P_1)
+    )reduction_or(
+        .D_in(dest_ports_masked),
+        .Q_out(sum)
     );
-    
-    
-    if(SELF_LOOP_EN=="NO") begin : nslp
+
+    if(SELF_LOOP_EN == 0) begin : nslp
         add_sw_loc_one_hot #(
             .P(P),
             .SW_LOC(SW_LOC)
-        )
-        add_sw_loc
-        (
+        ) add_sw_loc (
             .destport_in(sum),
             .destport_out(destports_sum)
         );
     end else begin : slp
-        assign destports_sum = sum;    
+        assign destports_sum = sum;
     end
     endgenerate
 endmodule
 
 /***************
 *   weights_update
-*
 ***************/
-
 module weights_update # (
-    parameter NOC_ID=0,
     parameter ARBITER_TYPE="WRRA",
     parameter V=4,
     parameter P=5,
-    parameter Fw = 36,    //flit width;  
+    parameter Fw = 36,    //flit width;
     parameter WEIGHTw=4,
     parameter C = 4,
     parameter WRRA_CONFIG_INDEX=0,
@@ -749,8 +577,6 @@ module weights_update # (
     parameter EAw = 3,
     parameter DSTPw=P-1,
     parameter ADD_PIPREG_AFTER_CROSSBAR=0
-   
-
 )(
     limited_oports_weight,
     contention_all, 
@@ -762,7 +588,6 @@ module weights_update # (
     clk,
     reset
 );
-
     function integer log2;
     input integer number; begin   
         log2=(number <=1) ? 1: 0;    
@@ -771,36 +596,29 @@ module weights_update # (
         end       
     end   
     endfunction // log2  
-     
-
     localparam        
         PFw = P * Fw,
         W= WEIGHTw,
         WP= W * P,
         ALL_WEIGHTw=log2(WP);
-        
-    localparam  PROPOGATE_LIMITED = (WRRA_CONFIG_INDEX==1 ),
-                INIT_WEIGHT = 1;
-       
-
+    localparam  
+        PROPOGATE_LIMITED = (WRRA_CONFIG_INDEX==1 ),
+        INIT_WEIGHT = 1;
     input [WP-1 : 0] contention_all;
-    input [PFw-1 :  0]  flit_in_all;
-    output[PFw-1 :  0]  flit_out_all;
+    input [Fw-1 :  0]  flit_in_all [P-1:0];
+    output[Fw-1 :  0]  flit_out_all [P-1:0];
     input [P-1 :  0]  flit_out_wr_all;
     input [WP-1: 0] iport_weight_all;
     output[WP-1 : 0] limited_oports_weight;  
     output refresh_w_counter;
     input clk,reset;
-       
+    
     //assign refresh_w_counter = 1'b0;   
-       
     genvar i;
     generate 
     //nonlocal port
     for (i=1; i<P; i=i+1) begin : non_local_port
-    
         weight_update_per_port #(
-            .NOC_ID(NOC_ID),
             .V(V),
             .C(C),
             .P(P),
@@ -811,165 +629,114 @@ module weights_update # (
             .WEIGHTw(WEIGHTw),
             .WRRA_CONFIG_INDEX(WRRA_CONFIG_INDEX),
             .ADD_PIPREG_AFTER_CROSSBAR(ADD_PIPREG_AFTER_CROSSBAR)
-        )
-        update_per_port
-        (
+        )  update_per_port (
             .contention_in(contention_all[(i+1)*W-1  :   i*W]),
-            .flit_in(flit_in_all[ (i+1)*Fw-1 : i*Fw]),
-            .flit_out(flit_out_all[(i+1)*Fw-1 : i*Fw]),
+            .flit_in(flit_in_all[i]),
+            .flit_out(flit_out_all[i]),
             .flit_out_wr(flit_out_wr_all[i]),
             .clk(clk),
             .reset(reset)
         );       
-    
     end
-       
-    
     if(PROPOGATE_LIMITED) begin : limited
-       
         wire [ALL_WEIGHTw-1 :   0] iweight_sum;
         wire [P-1   :   0] flit_out_is_tail,tail_flit_is_sent;
         wire any_tail_is_sent;
-        
         wire capture_o_weights;
         reg  [W-1 : 0] oport_weight_counter [P-1 : 0];
         reg  [W-1 : 0] limited_oport_weight [P-1 : 0];
-        
         assign tail_flit_is_sent = (flit_out_wr_all & flit_out_is_tail);
         assign any_tail_is_sent = | tail_flit_is_sent;
         for (i=0; i<P; i=i+1) begin : lp
-            assign flit_out_is_tail[i] = flit_out_all[(i+1)*Fw-2];
-            
-                always @ (`pronoc_clk_reset_edge )begin 
-                    if(`pronoc_reset) begin 
-                        oport_weight_counter[i]<=INIT_WEIGHT;
-                    end else begin 
-                        if (any_tail_is_sent && capture_o_weights) oport_weight_counter[i]<= INIT_WEIGHT;
-                        else if (any_tail_is_sent && tail_flit_is_sent[i] && oport_weight_counter[i] != {W{1'b1}})oport_weight_counter[i]<= oport_weight_counter[i] +1'b1;
-                    end
-                end //always
-                
-                always @ (`pronoc_clk_reset_edge )begin 
-                    if(`pronoc_reset) begin 
-                        limited_oport_weight[i]<={W{1'b0}};
-                    end else begin 
-                        if (any_tail_is_sent && capture_o_weights) limited_oport_weight[i]<= oport_weight_counter[i];  //capture oweight counters                    
-                    end
-                end //always
+            assign flit_out_is_tail[i] = flit_out_all[i][Fw-2];
+            always @ (`pronoc_clk_reset_edge )begin 
+                if(`pronoc_reset) begin 
+                    oport_weight_counter[i]<=INIT_WEIGHT;
+                end else begin 
+                    if (any_tail_is_sent && capture_o_weights) oport_weight_counter[i]<= INIT_WEIGHT;
+                    else if (any_tail_is_sent && tail_flit_is_sent[i] && oport_weight_counter[i] != {W{1'b1}})oport_weight_counter[i]<= oport_weight_counter[i] +1'b1;
+                end
+            end //always
                 
-                assign limited_oports_weight [(i+1)*W-1 : i*W] = limited_oport_weight[i];
-            
+            always @ (`pronoc_clk_reset_edge )begin 
+                if(`pronoc_reset) begin 
+                    limited_oport_weight[i]<={W{1'b0}};
+                end else begin 
+                    if (any_tail_is_sent && capture_o_weights) limited_oport_weight[i]<= oport_weight_counter[i];  //capture oweight counters                    
+                end
+            end //always
             
+            assign limited_oports_weight [(i+1)*W-1 : i*W] = limited_oport_weight[i];
         end
         //all input wights summation
-         accumulator #(
+        accumulator #(
             .INw(WP),
             .OUTw(ALL_WEIGHTw),
             .NUM(P)
-         
-         )
-         accum
-         (
+        ) accum (
             .in_all(iport_weight_all),
-            .out(iweight_sum)         
-         );
-         
+            .sum_o(iweight_sum)         
+        );
         
-         
-         weight_counter #(
+        weight_counter #(
             .WEIGHTw(ALL_WEIGHTw)
-         )
-         weight_counter
-         (
+        ) weight_counter (
             .weight_i(iweight_sum),
             .reset(reset),
             .clk(clk),
             .decr(any_tail_is_sent),
             .load_i(1'b0),
-            .out(capture_o_weights )
-         // .out(refresh_w_counter)
-         );
-         
-         
-         
-         
-         
-    
+            .Q_out(capture_o_weights )
+         // .Q_out(refresh_w_counter)
+        );
+        
     end else begin :dontcare
         assign limited_oports_weight = {WP{1'bX}};    
     end 
-    
-   
     /* verilator lint_off WIDTH */    
     if(ARBITER_TYPE == "WRRA")begin  : wrra
     /* verilator lint_on WIDTH */
-    
-         assign refresh_w_counter=1'b0;
-    
-   
+        assign refresh_w_counter=1'b0;
     end else begin  :wrra_classic
-    
-    
-       
         wire [ALL_WEIGHTw-1 :   0] iweight_sum;
         wire any_tail_is_sent;
         wire [P-1   :   0] flit_out_is_tail,tail_flit_is_sent;
         for (i=0; i<P; i=i+1) begin : lp2
-            assign flit_out_is_tail[i] = flit_out_all[(i+1)*Fw-2];
+            assign flit_out_is_tail[i] = flit_out_all[i][Fw-2];
         end
         
-        
         assign tail_flit_is_sent = (flit_out_wr_all & flit_out_is_tail);
         assign any_tail_is_sent = | tail_flit_is_sent;
-    
-    
-    
-         //all input wights summation
-         accumulator #(
+        //all input wights summation
+        accumulator #(
             .INw(WP),
             .OUTw(ALL_WEIGHTw),
             .NUM(P)
-         
-         )
-         accum
-         (
+        ) accum (
             .in_all(iport_weight_all),
-            .out(iweight_sum)         
-         );
-         
+            .sum_o(iweight_sum)         
+        );
         
-         
-         weight_counter #(
+        weight_counter #(
             .WEIGHTw(ALL_WEIGHTw)
-         )
-         weight_counter
-         (
+        ) weight_counter  (
             .weight_i(iweight_sum-1),
             .reset(reset),
             .clk(clk),
             .decr(any_tail_is_sent),
             .load_i(1'b0),
-            .out(refresh_w_counter)
-         );
-    
+            .Q_out(refresh_w_counter)
+        );
     end  
-    
     endgenerate
     
-    
-       
-    
     // localport 
-    assign flit_out_all[Fw-1 : 0] = flit_in_all [Fw-1 : 0]; 
-
-
-
+    assign flit_out_all[0] = flit_in_all [0]; 
 endmodule
 
 
 
 module weight_update_per_port # (
-    parameter NOC_ID=0,
     parameter V=4,
     parameter C=2,
     parameter P=5,
@@ -980,7 +747,6 @@ module weight_update_per_port # (
     parameter TOPOLOGY =    "MESH",//"MESH","TORUS","RING"   
     parameter WRRA_CONFIG_INDEX=0,
     parameter ADD_PIPREG_AFTER_CROSSBAR=0
-   
 )(
     contention_in, 
     flit_in,
@@ -989,32 +755,25 @@ module weight_update_per_port # (
     clk,
     reset
 );                  
-
     localparam 
         W=WEIGHTw,  
         WEIGHT_LATCHED = 0;  //(WRRA_CONFIG_INDEX==0 || WRRA_CONFIG_INDEX==1 || WRRA_CONFIG_INDEX==2 || WRRA_CONFIG_INDEX==3 ); //1: no latched  0: latched
-           
     
     input [W-1 : 0] contention_in;
     input [Fw-1 :  0]  flit_in;
     output[Fw-1 :  0]  flit_out;
     input flit_out_wr;
     input clk,reset;  
-   
     
     wire flit_is_hdr = flit_in[Fw-1];
     reg [W-1 : 0]  contention;
-   
     generate
     if(WEIGHT_LATCHED == 1) begin : add_latch
-     
         wire update = flit_out_wr & flit_is_hdr;
         wire [W-1 : 0] contention_out;
         output_weight_latch #(
             .WEIGHTw (WEIGHTw)    
-        )
-        out_weight_latch
-        (
+        ) out_weight_latch  (
             .weight_in(contention_in),
             .weight_out(contention_out),
             .clk(clk),
@@ -1022,49 +781,38 @@ module weight_update_per_port # (
             .update( update )    
         );   
         always @ (*) begin 
-           contention= contention_out;
+            contention= contention_out;
         end
-     
-     end else  if(ADD_PIPREG_AFTER_CROSSBAR==1)begin : add_reg 
-
+    end else  if(ADD_PIPREG_AFTER_CROSSBAR==1)begin : add_reg 
         always @ (`pronoc_clk_reset_edge )begin 
             if(`pronoc_reset) begin 
                 contention<={W{1'b0}};
             end else begin 
-                 contention<= contention_in;
+                contention<= contention_in;
             end
         end//always
-        
-        
-     end else begin : no_reg
+    end else begin : no_reg
         always @ (*) begin 
-           contention= contention_in;
+            contention= contention_in;
         end
     end  
     endgenerate 
-     
-    wire [Fw-1 : 0] hdr_flit_new; 
     
-    hdr_flit_weight_update #(
-        .NOC_ID(NOC_ID)
-    ) updater (
+    wire [Fw-1 : 0] hdr_flit_new; 
+    hdr_flit_weight_update updater (
         .new_weight(contention),
         .flit_in(flit_in),
-        .flit_out(hdr_flit_new)    
+        .flit_out(hdr_flit_new)
     );
-        
-        
-   // assign flit_out = (flit_is_hdr) ? {flit_in[Fw-1 : WEIGHT_LSB+WEIGHTw ] ,contention, flit_in[WEIGHT_LSB-1 : 0] }   : flit_in;
+    
+    // assign flit_out = (flit_is_hdr) ? {flit_in[Fw-1 : WEIGHT_LSB+WEIGHTw ] ,contention, flit_in[WEIGHT_LSB-1 : 0] }   : flit_in;
     assign flit_out = (flit_is_hdr) ? hdr_flit_new  : flit_in;
-        
-
 endmodule
 
 
 
-
 module output_weight_latch #(
-    parameter WEIGHTw =4    
+    parameter WEIGHTw =4
 )(
     weight_in,
     weight_out,
@@ -1075,34 +823,32 @@ module output_weight_latch #(
 
     localparam W=WEIGHTw;
     
-     input [W-1 : 0] weight_in;
-     output reg [W-1 : 0] weight_out;
-     input clk, reset, update;
-     
-     reg  [W-1 : 0] counter,counter_next,weight_out_next;
-     
-     wire less =  weight_in <  weight_out; 
-     wire counter_is_zero = counter == {W{1'b0}};
-   
-     always @ (*)begin 
+    input [W-1 : 0] weight_in;
+    output reg [W-1 : 0] weight_out;
+    input clk, reset, update;
+    
+    reg  [W-1 : 0] counter,counter_next,weight_out_next;
+    wire less =  weight_in <  weight_out; 
+    wire counter_is_zero = counter == {W{1'b0}};
+    
+    always @ (*)begin 
         counter_next = counter;
         weight_out_next = weight_out; 
         if(update)begin 
             if (less ) begin // input weight is smaller than the captured one before
                if(counter_is_zero) begin // 
-                   weight_out_next = weight_in;
-               end else begin 
-                 counter_next =   counter - 1'b1;           
-               end
+                    weight_out_next = weight_in;
+                end else begin 
+                    counter_next =   counter - 1'b1;           
+                end
             end
             else begin 
                 counter_next = (weight_in[W-1] != 1'b1) ?  {weight_in[W-2:0],1'b0} : {W{1'b1}}; 
                 weight_out_next = weight_in;
             end    
         end  
-     end
-
-
+    end
+    
     always @ (`pronoc_clk_reset_edge )begin 
         if(`pronoc_reset) begin 
             counter = {WEIGHTw{1'b0}};
@@ -1112,10 +858,4 @@ module output_weight_latch #(
             weight_out = weight_out_next; 
         end
     end//always
-
-endmodule
-
-
-
-
-
+endmodule
\ No newline at end of file
diff --git a/mpsoc/rtl/src_openpiton/custom_include.v b/mpsoc/rtl/src_openpiton/custom_include.v
index 204e3a4..1767ac4 100644
--- a/mpsoc/rtl/src_openpiton/custom_include.v
+++ b/mpsoc/rtl/src_openpiton/custom_include.v
@@ -1,11 +1,10 @@
-
 //get new x according to concentration
 function integer get_pronoc_X;
     input integer piton_nx;  // openpiton x
     input integer piton_ny;  // openpiton y
     input integer concent;   //concentration value
     input integer dim_max_diff; // max allowable diff between pronoc_x and pronoc_y
-	integer min , x , y, size, diff;
+    integer min , x , y, size, diff;
     begin  
         if  (concent == 1) get_pronoc_X = piton_nx;
         else begin 
@@ -17,7 +16,7 @@ function integer get_pronoc_X;
                     diff = (x<y) ? y - x : x - y;
                     if ( size >= (piton_nx * piton_ny) && diff <= dim_max_diff &&  size < min ) begin
                         min = size; 
-                        get_pronoc_X = x;								
+                        get_pronoc_X = x;
                     end
                 end
             end
@@ -31,7 +30,7 @@ function integer get_pronoc_Y;
     input integer piton_ny;  // openpiton y
     input integer concent;   //concentration value
     input integer dim_max_diff; // max allowable diff between pronoc_x and pronoc_y
-	integer min , x , y, size, diff;
+    integer min , x , y, size, diff;
     begin
         if  (concent == 1) get_pronoc_Y = piton_ny;
         else begin    
@@ -43,7 +42,7 @@ function integer get_pronoc_Y;
                     diff = (x<y) ? y - x : x - y;
                     if ( size >= (piton_nx * piton_ny) && diff <= dim_max_diff &&  size < min ) begin
                         min = size; 
-                        get_pronoc_Y = y;								
+                        get_pronoc_Y = y;
                     end
                 end
             end
diff --git a/mpsoc/rtl/src_openpiton/noc_localparam.v b/mpsoc/rtl/src_openpiton/noc_localparam.v
index 8f5b70b..3d959d3 100644
--- a/mpsoc/rtl/src_openpiton/noc_localparam.v
+++ b/mpsoc/rtl/src_openpiton/noc_localparam.v
@@ -2,25 +2,27 @@
 
 `include "define.tmp.h"
 
-    localparam NOC_ID=0;   
+    localparam NOC_ID=0;
 
 //NoC parameters
 	localparam TOPOLOGY="FMESH";
 	localparam T1=`PITON_X_TILES;
 	localparam T2=`PITON_Y_TILES;
 	localparam T3=1;
+	localparam T4=1;
 	localparam V=1;
 	localparam C=0;
 	localparam B=4;
 	localparam LB=16;
 
-	localparam ROUTE_NAME="XY";
+	localparam ROUTE_NAME="DOR";
+	localparam ROUTE_MODE="LOOKAHEAD";
 	localparam PCK_TYPE="MULTI_FLIT";
 	localparam MIN_PCK_SIZE=1;
 	localparam BYTE_EN=0;
 	localparam CAST_TYPE="UNICAST";
 	localparam MCAST_ENDP_LIST=10'h3ff;
-	localparam SSA_EN="YES";
+	localparam SSA_EN=1;
 	localparam SMART_MAX=0;
 	localparam CONGESTION_INDEX=3;
 	localparam ESCAP_VC_MASK=1'b1;
@@ -32,10 +34,14 @@
 	localparam FIRST_ARBITER_EXT_P_EN=0;
 	localparam SWA_ARBITER_TYPE="RRA";
 	localparam WEIGHTw=4;
-	localparam SELF_LOOP_EN="YES";
+	localparam SELF_LOOP_EN=1;
 	localparam AVC_ATOMIC_EN=0;
 	localparam CLASS_SETTING={V{1'b1}};
- 	localparam  CVw=(C==0)? V : C * V;
+ 	localparam CVw=(C==0)? V : C * V;
+ 	localparam HETERO_VC=0;
+ 	localparam MAX_ROUTER=1;
+ 	localparam MAX_PORT=1;
+ 	localparam int VC_CONFIG_TABLE [MAX_ROUTER][MAX_PORT]='{'{0}};
 
 	localparam Fpay= 
         (NOC_ID=="N1") ? `PITON_NOC1_WIDTH : 
diff --git a/mpsoc/rtl/src_openpiton/piton_mesh.sv b/mpsoc/rtl/src_openpiton/piton_mesh.sv
index a0c0961..a1ce763 100644
--- a/mpsoc/rtl/src_openpiton/piton_mesh.sv
+++ b/mpsoc/rtl/src_openpiton/piton_mesh.sv
@@ -1,440 +1,303 @@
 `timescale      1ns/1ps
-
 `include "define.tmp.h"
-		                                      
-/*********************************            
- *                                            
- *   pack openpiton routers ports	          
- * 	                                          
- * 	******************************/           
-			                                  
-module piton_router_top                       
-	                 
-(                                        
-		                                      
-	clk,                                  
-	reset,                             
-	  
-	current_r_addr,
-						
-	chan_in,                              
-	chan_out				              
-);                                        
-	  
-	import piton_pkg::*;  
-	import pronoc_pkg::*;          
-	
-	localparam P=5;                        
-		                                      
-	                                          
-	input 	clk, reset;  
-	input   [RAw-1 : 0] current_r_addr;
-	
-		                                      
-	input  piton_chan_t chan_in  [P-1 : 0];   
-	output piton_chan_t chan_out [P-1 : 0];	  
-		  
-	
-	wire [`NOC_X_WIDTH-1:0] myLocX;       // thi
-	wire [`NOC_Y_WIDTH-1:0] myLocY;             
-	wire [`NOC_CHIPID_WIDTH-1:0] myChipID;
-	
-	  
-	assign myLocY = (current_r_addr / `PITON_X_TILES ) % `PITON_Y_TILES ;
-	assign myLocX = (current_r_addr % `PITON_X_TILES );
-	assign myChipID =0;
-  		                                      
-	dynamic_node_top_wrap router              
-		(                                         
-			.clk(clk),                            
-			.reset_in(reset),                     
-			// dataIn (to input blocks)           
-			.dataIn_N(chan_in[NORTH].data),       
-			.dataIn_E(chan_in[EAST ].data),       
-			.dataIn_S(chan_in[SOUTH].data),       
-			.dataIn_W(chan_in[WEST ].data),       
-			.dataIn_P(chan_in[LOCAL].data),       
-			// validIn (to input blocks)          
-			.validIn_N(chan_in[NORTH].valid),     
-			.validIn_E(chan_in[EAST ].valid),     
-			.validIn_S(chan_in[SOUTH].valid),     
-			.validIn_W(chan_in[WEST ].valid),     
-			.validIn_P(chan_in[LOCAL].valid),     
-			// yummy (from nighboring inputlocks) 
-			.yummyIn_N(chan_in[NORTH].yummy),     
-			.yummyIn_E(chan_in[EAST ].yummy),     
-			.yummyIn_S(chan_in[SOUTH].yummy),     
-			.yummyIn_W(chan_in[WEST ].yummy),     
-			.yummyIn_P(chan_in[LOCAL].yummy),     
-			// My Absolute Address                
-			.myLocX(myLocX),                      
-			.myLocY(myLocY),                      
-			.myChipID(myChipID),                  
-			//.ec_cfg(15'b0),//ec_dyn_cfg[14:0]), 
-			//.store_meter_partner_address_X(5'b0)
-			//.store_meter_partner_address_Y(5'b0)
-			// DataOut (from crossbar)            
-			.dataOut_N(chan_out[NORTH].data),     
-			.dataOut_E(chan_out[EAST ].data),     
-			.dataOut_S(chan_out[SOUTH].data),     
-			.dataOut_W(chan_out[WEST ].data),     
-			.dataOut_P(chan_out[LOCAL].data),     
-			// validOut (from crossbar)           
-			.validOut_N(chan_out[NORTH].valid),   
-			.validOut_E(chan_out[EAST ].valid),   
-			.validOut_S(chan_out[SOUTH].valid),   
-			.validOut_W(chan_out[WEST ].valid),   
-			.validOut_P(chan_out[LOCAL].valid),   
-			// yummyOut (to neighboring outpu     
-			.yummyOut_N(chan_out[NORTH].yummy),   
-			.yummyOut_E(chan_out[EAST ].yummy),   
-			.yummyOut_W(chan_out[WEST].yummy),   
-			.yummyOut_S(chan_out[SOUTH ].yummy),   
-			.yummyOut_P(chan_out[LOCAL].yummy),   
-			// thanksIn (to CGNO)                 
-			.thanksIn_P()//?                      
-		);	                                  
-		                                      
-endmodule		                              
-
+/*********************************
+ *   pack openpiton routers ports
+ *******************************/
+module piton_router_top
+(
+    clk,
+    reset,
+    current_r_addr,
+    chan_in,
+    chan_out
+);
+    import piton_pkg::*;
+    import pronoc_pkg::*;
+    localparam P=5;
+    input     clk, reset;
+    input   [RAw-1 : 0] current_r_addr;
+    input  piton_chan_t chan_in  [P-1 : 0];
+    output piton_chan_t chan_out [P-1 : 0];
+    wire [`NOC_X_WIDTH-1:0] myLocX;       // thi
+    wire [`NOC_Y_WIDTH-1:0] myLocY;
+    wire [`NOC_CHIPID_WIDTH-1:0] myChipID;
+    assign myLocY = (current_r_addr / `PITON_X_TILES ) % `PITON_Y_TILES ;
+    assign myLocX = (current_r_addr % `PITON_X_TILES );
+    assign myChipID =0;
+    dynamic_node_top_wrap router (
+        .clk(clk),
+        .reset_in(reset),
+        // dataIn (to input blocks)
+        .dataIn_N(chan_in[NORTH].data),
+        .dataIn_E(chan_in[EAST ].data),
+        .dataIn_S(chan_in[SOUTH].data),
+        .dataIn_W(chan_in[WEST ].data),
+        .dataIn_P(chan_in[LOCAL].data),
+        // validIn (to input blocks)
+        .validIn_N(chan_in[NORTH].valid),
+        .validIn_E(chan_in[EAST ].valid),
+        .validIn_S(chan_in[SOUTH].valid),
+        .validIn_W(chan_in[WEST ].valid),
+        .validIn_P(chan_in[LOCAL].valid),
+        // yummy (from nighboring inputlocks)
+        .yummyIn_N(chan_in[NORTH].yummy),
+        .yummyIn_E(chan_in[EAST ].yummy),
+        .yummyIn_S(chan_in[SOUTH].yummy),
+        .yummyIn_W(chan_in[WEST ].yummy),
+        .yummyIn_P(chan_in[LOCAL].yummy),
+        // My Absolute Address
+        .myLocX(myLocX),
+        .myLocY(myLocY),
+        .myChipID(myChipID),
+        //.ec_cfg(15'b0),//ec_dyn_cfg[14:0]),
+        //.store_meter_partner_address_X(5'b0)
+        //.store_meter_partner_address_Y(5'b0)
+        // DataOut (from crossbar)
+        .dataOut_N(chan_out[NORTH].data),
+        .dataOut_E(chan_out[EAST ].data),
+        .dataOut_S(chan_out[SOUTH].data),
+        .dataOut_W(chan_out[WEST ].data),
+        .dataOut_P(chan_out[LOCAL].data),
+        // validOut (from crossbar)
+        .validOut_N(chan_out[NORTH].valid),
+        .validOut_E(chan_out[EAST ].valid),
+        .validOut_S(chan_out[SOUTH].valid),
+        .validOut_W(chan_out[WEST ].valid),
+        .validOut_P(chan_out[LOCAL].valid),
+        // yummyOut (to neighboring outpu
+        .yummyOut_N(chan_out[NORTH].yummy),
+        .yummyOut_E(chan_out[EAST ].yummy),
+        .yummyOut_W(chan_out[WEST].yummy),
+        .yummyOut_S(chan_out[SOUTH ].yummy),
+        .yummyOut_P(chan_out[LOCAL].yummy),
+        // thanksIn (to CGNO)
+        .thanksIn_P()//?
+    );
+endmodule
 /*********************
- * piton_mesh 
- * 
+ * piton_mesh
  * ********************/
-
-`define router_id(x,y)                         ((y * NX) +    x)
-`define endp_id(x,y,l)                         ((y * NX) +    x) * NL + l 
-
-
+`define router_id(x,y) ((y * NX) +  x)
+`define endp_id(x,y,l)  ((y * NX) + x) * NL + l
 module piton_mesh
-	
-(                                        
-		                                      
-	clk,                                  
-	reset,                                
-	    
-	chan_in_all,                              
-	chan_out_all				              
-);                                     
-
-
-	import piton_pkg::*;     
-	import pronoc_pkg::*;    
-	
- 	input clk, reset;                                
-	    
- 
- 	//local ports 
- 	input   piton_chan_t chan_in_all  [NE-1 : 0];
- 	output  piton_chan_t chan_out_all [NE-1 : 0];
-	
- 	//all routers port 
- 	piton_chan_t    router_chan_in   [NR-1 :0][MAX_P-1 : 0];
- 	piton_chan_t    router_chan_out  [NR-1 :0][MAX_P-1 : 0];
-
- 	wire [RAw-1 : 0] current_r_addr [NR-1 : 0];
-
-
- 	// mesh torus            
- 	localparam
- 		EAST   =       3'd1, 
- 		NORTH  =       3'd2,  
- 		WEST   =       3'd3,  
- 		SOUTH  =       3'd4;
- 	//ring line            
- 	localparam 
- 		FORWARD =  2'd1,
- 		BACKWARD=  2'd2;
-
-
- 	genvar x,y,l;
- 	generate 
- 	/* verilator lint_off WIDTH */ 
- 	if( TOPOLOGY == "RING" || TOPOLOGY == "LINE") begin : ring_line 
- 	/* verilator lint_on WIDTH */ 
- 		for  (x=0;   x<NX; x=x+1) begin :Router_
-             
-                       
- 			assign current_r_addr [x] = x[RAw-1: 0];   
-	
- 			piton_router_top the_router (
- 						.current_r_addr  (current_r_addr [x]), 
- 						.chan_in         (router_chan_in [x]), 
- 						.chan_out        (router_chan_out[x]), 
- 						.clk             (clk            ), 
- 						.reset           (reset          ));
-	
- 				if(x    <   NX-1) begin: not_last_node            
- 					assign  router_chan_in[x][FORWARD] = router_chan_out [(x+1)][BACKWARD];
- 				end else begin :last_node
- 					/* verilator lint_off WIDTH */ 
- 					if(TOPOLOGY == "LINE") begin : line_last_x
- 						/* verilator lint_on WIDTH */ 
- 						assign  router_chan_in[x][FORWARD]= {PITON_CHANEL_w{1'b0}};										      
- 					end else begin : ring_last_x
- 						assign router_chan_in[x][FORWARD]= router_chan_out [0][BACKWARD];
- 					end
- 				end 
-            
- 				if(x>0)begin :not_first_x
- 					assign router_chan_in[x][BACKWARD]= router_chan_out [(x-1)][FORWARD];					
- 				end else begin :first_x
- 					/* verilator lint_off WIDTH */ 
- 					if(TOPOLOGY == "LINE") begin : line_first_x
- 						/* verilator lint_on WIDTH */ 
- 						assign  router_chan_in[x][BACKWARD]={PITON_CHANEL_w{1'b0}};					
- 					end else begin : ring_first_x
- 						assign  router_chan_in[x][BACKWARD]= router_chan_out [(NX-1)][FORWARD];											
- 					end
- 				end            
-            
- 				// connect other local ports
- 				for  (l=0;   l<NL; l=l+1) begin :locals
- 					localparam ENDPID = `endp_id(x,0,l); 
- 					localparam LOCALP = (l==0) ? l : l + R2R_CHANELS_MESH_TORI; // first local port is connected to router port 0. The rest are connected at the end  
- 					assign router_chan_in[x][LOCALP]= chan_in_all [ENDPID];
- 					assign chan_out_all [ENDPID] = router_chan_out[x][LOCALP];
-					                
- 				end// locals               
- 			end//x    
-			
- 		end else begin :mesh_torus
- 			for (y=0;    y<NY;    y=y+1) begin: y_loop
- 				for (x=0;    x<NX; x=x+1) begin :x_loop
- 					localparam R_ADDR = (y<<NXw) + x;            
- 					localparam ROUTER_NUM = (y * NX) +    x;					
- 					assign current_r_addr [ROUTER_NUM] = R_ADDR[RAw-1 :0];
-             	
- 					piton_router_top  the_router (
- 							.current_r_addr  (current_r_addr [ROUTER_NUM]),    
- 							.chan_in         (router_chan_in [ROUTER_NUM]), 
- 							.chan_out        (router_chan_out[ROUTER_NUM]), 
- 							.clk             (clk            ), 
- 							.reset           (reset          ));
-					
-							
- 					/*
+(
+    clk,
+    reset,
+    chan_in_all,
+    chan_out_all
+);
+    import piton_pkg::*;
+    import pronoc_pkg::*;
+    input clk, reset;
+    //local ports
+    input   piton_chan_t chan_in_all  [NE-1 : 0];
+    output  piton_chan_t chan_out_all [NE-1 : 0];
+    //all routers port
+    piton_chan_t    router_chan_in   [NR-1 :0][MAX_P-1 : 0];
+    piton_chan_t    router_chan_out  [NR-1 :0][MAX_P-1 : 0];
+    wire [RAw-1 : 0] current_r_addr [NR-1 : 0];
+    // mesh torus
+    localparam
+        EAST   =       3'd1,
+        NORTH  =       3'd2,
+        WEST   =       3'd3,
+        SOUTH  =       3'd4;
+    //ring line
+    localparam
+        FORWARD =  2'd1,
+        BACKWARD=  2'd2;
+    genvar x,y,l;
+    generate
+    if(IS_1D_TOPO) begin : D1_
+        for  (x=0;   x<NX; x=x+1) begin :Router_
+            assign current_r_addr [x] = x[RAw-1: 0];
+            piton_router_top the_router (
+                .current_r_addr  (current_r_addr [x]),
+                .chan_in         (router_chan_in [x]),
+                .chan_out        (router_chan_out[x]),
+                .clk             (clk            ),
+                .reset           (reset          ));
+            if(x    <   NX-1) begin: not_last_node
+                assign  router_chan_in[x][FORWARD] = router_chan_out [(x+1)][BACKWARD];
+            end else begin :last_node
+                if(IS_LINE) begin : line_last_x
+                    assign  router_chan_in[x][FORWARD]= {PITON_CHANEL_w{1'b0}};
+                end else begin : ring_last_x
+                    assign router_chan_in[x][FORWARD]= router_chan_out [0][BACKWARD];
+                end
+            end
+            if(x>0)begin :not_first_x
+                    assign router_chan_in[x][BACKWARD]= router_chan_out [(x-1)][FORWARD];
+            end else begin :first_x
+                if(IS_LINE) begin : line_first_x
+                    assign  router_chan_in[x][BACKWARD]={PITON_CHANEL_w{1'b0}};
+                end else begin : ring_first_x
+                    assign  router_chan_in[x][BACKWARD]= router_chan_out [(NX-1)][FORWARD];
+                end
+            end
+            // connect other local ports
+            for  (l=0;   l<NL; l=l+1) begin :locals
+                localparam ENDPID = `endp_id(x,0,l);
+                localparam LOCALP = (l==0) ? l : l + R2R_CHANELS_REGULAR; // first local port is connected to router port 0. The rest are connected at the end
+                assign router_chan_in[x][LOCALP]= chan_in_all [ENDPID];
+                assign chan_out_all [ENDPID] = router_chan_out[x][LOCALP];
+            end// locals
+        end//x
+    end else begin : D2_
+        for (y=0;    y<NY;    y=y+1) begin: y_loop
+            for (x=0;    x<NX; x=x+1) begin :x_loop
+                localparam R_ADDR = (y<<NXw) + x;
+                localparam ROUTER_NUM = (y * NX) +    x;
+                assign current_r_addr [ROUTER_NUM] = R_ADDR[RAw-1 :0];
+                piton_router_top  the_router (
+                    .current_r_addr  (current_r_addr [ROUTER_NUM]),
+                    .chan_in         (router_chan_in [ROUTER_NUM]),
+                    .chan_out        (router_chan_out[ROUTER_NUM]),
+                    .clk             (clk            ),
+                    .reset           (reset          ));
+    /*
     in [x,y][east] <------  out [x+1 ,y  ][west] ;
     in [x,y][north] <------ out [x   ,y-1][south] ;
     in [x,y][west] <------  out [x-1 ,y  ][east] ;
     in [x,y][south] <------ out [x   ,y+1][north] ;
- 					 */    
-        
-        
- 					if(x    <    NX-1) begin: not_last_x
- 						assign router_chan_in[`router_id(x,y)][EAST]= router_chan_out [`router_id(x+1,y)][WEST];
- 						//assign    router_credit_in_all [`SELECT_WIRE(x,y,EAST,V)] = router_credit_out_all [`SELECT_WIRE((x+1),y,WEST,V)];					
- 					end else begin :last_x
- 						/* verilator lint_off WIDTH */ 
- 						if(TOPOLOGY == "MESH") begin :last_x_mesh
- 							/* verilator lint_on WIDTH */ 
- 							assign router_chan_in[`router_id(x,y)][EAST] = {PITON_CHANEL_w{1'b0}};					
- 							/* verilator lint_off WIDTH */ 
- 						end else if(TOPOLOGY == "TORUS") begin : last_x_torus
- 							/* verilator lint_on WIDTH */ 
- 							assign router_chan_in[`router_id(x,y)][EAST] = router_chan_out [`router_id(0,y)][WEST];						
- 							/* verilator lint_off WIDTH */ 
- 						end else if(TOPOLOGY == "FMESH") begin : last_x_fmesh //connect to endp
- 							/* verilator lint_on WIDTH */ 
- 							localparam EAST_ID = NX*NY*NL + 2*NX + NY +y; 
- 							assign router_chan_in [`router_id(x,y)][EAST] =    chan_in_all [EAST_ID];
- 							assign chan_out_all [EAST_ID] = router_chan_out [`router_id(x,y)][EAST];						 
- 						end //topology
- 					end 
-            
-        
- 					if(y>0) begin : not_first_y
- 						assign router_chan_in[`router_id(x,y)][NORTH] =  router_chan_out [`router_id(x,(y-1))][SOUTH];					
- 					end else begin :first_y
- 						/* verilator lint_off WIDTH */ 
- 						if(TOPOLOGY == "MESH") begin : first_y_mesh
- 							/* verilator lint_on WIDTH */ 
- 							assign router_chan_in[`router_id(x,y)][NORTH] =  {PITON_CHANEL_w{1'b0}};												
- 							/* verilator lint_off WIDTH */ 
- 						end else if(TOPOLOGY == "TORUS") begin :first_y_torus
- 							/* verilator lint_on WIDTH */ 
- 							assign router_chan_in[`router_id(x,y)][NORTH] =  router_chan_out [`router_id(x,(NY-1))][SOUTH];						
- 							/* verilator lint_off WIDTH */ 
- 						end else if(TOPOLOGY == "FMESH") begin : first_y_fmesh //connect to endp
- 							/* verilator lint_on WIDTH */ 	
- 							localparam NORTH_ID = NX*NY*NL + x; 
- 							assign router_chan_in [`router_id(x,y)][NORTH] =    chan_in_all [NORTH_ID];
- 							assign chan_out_all [NORTH_ID] = router_chan_out [`router_id(x,y)][NORTH];
- 						end//topology
- 					end//y>0
-            
-            
- 					if(x>0)begin :not_first_x
- 						assign    router_chan_in[`router_id(x,y)][WEST] =  router_chan_out [`router_id((x-1),y)][EAST];					
- 					end else begin :first_x
- 						/* verilator lint_off WIDTH */ 
- 						if(TOPOLOGY == "MESH") begin :first_x_mesh
- 							/* verilator lint_on WIDTH */ 
- 							assign    router_chan_in[`router_id(x,y)][WEST] =   {PITON_CHANEL_w{1'b0}};						
- 							/* verilator lint_off WIDTH */                
- 						end else if(TOPOLOGY == "TORUS") begin :first_x_torus
- 							/* verilator lint_on WIDTH */ 
- 							assign    router_chan_in[`router_id(x,y)][WEST] =   router_chan_out [`router_id((NX-1),y)][EAST] ;						
- 							/* verilator lint_off WIDTH */ 
- 						end else if(TOPOLOGY == "FMESH") begin : first_x_fmesh //connect to endp
- 							/* verilator lint_on WIDTH */ 	
- 							localparam WEST_ID = NX*NY*NL +2*NX + y; 
- 							assign router_chan_in [`router_id(x,y)][WEST] =    chan_in_all [WEST_ID];
- 							assign chan_out_all [WEST_ID] = router_chan_out [`router_id(x,y)][WEST];						
- 						end//topology
- 					end    
-            
- 					if(y    <    NY-1) begin : firsty
- 						assign  router_chan_in[`router_id(x,y)][SOUTH] =    router_chan_out [`router_id(x,(y+1))][NORTH];					
- 					end else     begin : lasty
- 						/* verilator lint_off WIDTH */ 
- 						if(TOPOLOGY == "MESH") begin :ly_mesh
- 							/* verilator lint_on WIDTH */ 
- 							assign  router_chan_in[`router_id(x,y)][SOUTH]=  {PITON_CHANEL_w{1'b0}};						
- 							/* verilator lint_off WIDTH */ 
- 						end else if(TOPOLOGY == "TORUS") begin :ly_torus
- 							/* verilator lint_on WIDTH */ 
- 							assign  router_chan_in[`router_id(x,y)][SOUTH]=    router_chan_out [`router_id(x,0)][NORTH];						
- 						end else if(TOPOLOGY == "FMESH") begin : ly_fmesh //connect to endp
- 							/* verilator lint_on WIDTH */ 	
- 							localparam SOUTH_ID = NX*NY*NL + NX + x; 
- 							assign router_chan_in [`router_id(x,y)][SOUTH] =    chan_in_all [SOUTH_ID];
- 							assign chan_out_all [SOUTH_ID] = router_chan_out [`router_id(x,y)][SOUTH];
- 						end//topology
- 					end          
-        
-        
- 					// endpoint(s) connection
- 					// connect other local ports
- 					for  (l=0;   l<NL; l=l+1) begin :locals
- 						localparam ENDPID = `endp_id(x,y,l); 
- 						localparam LOCALP = (l==0) ? l : l + R2R_CHANELS_MESH_TORI; // first local port is connected to router port 0. The rest are connected at the end  
-                
- 						assign router_chan_in [`router_id(x,y)][LOCALP] =    chan_in_all [ENDPID];
- 						assign chan_out_all [ENDPID] = router_chan_out [`router_id(x,y)][LOCALP];			
-                              
- 					end// locals                 
-    
- 				end //y
- 			end //x
- 		end// mesh_torus        
-    
- 	endgenerate
-	
-endmodule	
-
-
-
-
-module piton_mesh_pronoc_wrap
-	               
-                     
-	(                                        
-		                                      
-			clk,                                  
-			reset,                                
-	    
-			chan_in_all,                              
-			chan_out_all				              
-		);                          
-	import piton_pkg::*;     
-	import pronoc_pkg::*;          
-    
-	input   clk,reset;
-	//local ports  ProNoC interface
-	input   smartflit_chanel_t chan_in_all  [NE-1 : 0];
-	output  smartflit_chanel_t chan_out_all [NE-1 : 0];
-
-	
-	
-	//piton interface  
-	piton_chan_t piton_chan_in_all  [NE-1 : 0];
-	piton_chan_t piton_chan_out_all [NE-1 : 0];
-	
-	
-	piton_mesh pmesh(                                        
-              
-		.clk         (clk         ),                         
-		.reset       (reset       ),                     
-		.chan_in_all (piton_chan_in_all ),                             
-		.chan_out_all(piton_chan_out_all)				              
-		);                                     
-
-	localparam
-		NX = T1,
-		NY = T2,
-		RXw = log2(NX),    // number of node in x axis
-		RYw = log2(NY),
-		EXw = log2(NX),    // number of node in x axis
-		EYw = log2(NY);   // number of node in y axis
-    
-    
-	wire [RXw-1 : 0] current_x [NE-1 : 0];
-	wire [RYw-1 : 0] current_y [NE-1 : 0];
-	reg [`XY_WIDTH-1:0] myLocX [NE-1 : 0];       // thi
-	reg [`XY_WIDTH-1:0] myLocY [NE-1 : 0];             
-	reg [`CHIP_ID_WIDTH-1:0] myChipID[NE-1 : 0];
-	
-	genvar i;
-	generate 
-	for (i=0; i<NE;i++) begin :E_
-		
-		
-		mesh_tori_router_addr_decode #(
-				.TOPOLOGY(TOPOLOGY),
-				.T1(T1),
-				.T2(T2),
-				.T3(T3),
-				.RAw(RAw)
-			)
-			r_addr_decode
-			(
-				.r_addr(i[RAw-1:0]),
-				.rx(current_x[i]),
-				.ry(current_y[i]),
-				.valid()
-			);
-		
-		
-		always @(*) begin 
-			myLocX[i]   = {`XY_WIDTH{1'b0}};
-			myLocY[i]   = {`XY_WIDTH{1'b0}};
-			myChipID[i] = {`CHIP_ID_WIDTH{1'b0}};
-		
-			myLocX[i]  [RXw-1 : 0] = current_x[i];
-			myLocY[i]  [RYw-1 : 0] = current_y[i];
-			
-		end
-		
-		piton_to_pronoc_wrapper #(.NOC_NUM(1),.TILE_NUM(i),.CHIP_SET_PORT(0),.FLATID_WIDTH(FLATID_WIDTH)) pi2pr_wrapper1
-			(
-				.default_chipid(myChipID[i]), .default_coreid_x(myLocX[i]), .default_coreid_y(myLocY[i]), .flat_tileid(i[FLATID_WIDTH-1 : 0]),	
-				.reset(reset),
-				.clk (clk),
-				.dataIn (piton_chan_out_all[i].data),
-				.validIn(piton_chan_out_all[i].valid),
-				.yummyIn(piton_chan_out_all[i].yummy),
-				.chan_out(chan_out_all[i]),
-				.current_r_addr_i(i[RAw-1:0])
-			);	
-
-		pronoc_to_piton_wrapper  #(.NOC_NUM(1),.TILE_NUM(i),.FLATID_WIDTH(FLATID_WIDTH)) pr2pi_wrapper1
-			(
-				.default_chipid(myChipID[i]), .default_coreid_x(myLocX[i]), .default_coreid_y(myLocY[i]), .flat_tileid(i[FLATID_WIDTH-1:0]),	
-				.reset(reset),
-				.clk (clk),
-				.dataOut (piton_chan_in_all[i].data ),
-				.validOut(piton_chan_in_all[i].valid ),
-				.yummyOut(piton_chan_in_all[i].yummy ),
-				.chan_in (chan_in_all[i] ),
-				.current_r_addr_o( )
-			);			
-		
-	end
-	endgenerate
-
+    */
+                if(x    <    NX-1) begin: not_last_x
+                    assign router_chan_in[`router_id(x,y)][EAST]= router_chan_out [`router_id(x+1,y)][WEST];
+                    //assign    router_credit_in_all [`SELECT_WIRE(x,y,EAST,V)] = router_credit_out_all [`SELECT_WIRE((x+1),y,WEST,V)];
+                end else begin :last_x
+                    if(IS_MESH) begin :last_x_mesh
+                        assign router_chan_in[`router_id(x,y)][EAST] = {PITON_CHANEL_w{1'b0}};
+                    end else if(IS_TORUS) begin : last_x_torus
+                        assign router_chan_in[`router_id(x,y)][EAST] = router_chan_out [`router_id(0,y)][WEST];
+                    end else if(IS_MESH) begin : last_x_fmesh //connect to endp
+                        localparam EAST_ID = NX*NY*NL + 2*NX + NY +y;
+                        assign router_chan_in [`router_id(x,y)][EAST] =    chan_in_all [EAST_ID];
+                        assign chan_out_all [EAST_ID] = router_chan_out [`router_id(x,y)][EAST];
+                    end //topology
+                end
+                if(y>0) begin : not_first_y
+                    assign router_chan_in[`router_id(x,y)][NORTH] =  router_chan_out [`router_id(x,(y-1))][SOUTH];
+                end else begin :first_y
+                    if(IS_MESH) begin : first_y_mesh
+                        assign router_chan_in[`router_id(x,y)][NORTH] =  {PITON_CHANEL_w{1'b0}};
+                    end else if(IS_TORUS) begin :first_y_torus
+                        assign router_chan_in[`router_id(x,y)][NORTH] =  router_chan_out [`router_id(x,(NY-1))][SOUTH];
+                    end else if(IS_FMESH) begin : first_y_fmesh //connect to endp
+                        localparam NORTH_ID = NX*NY*NL + x;
+                        assign router_chan_in [`router_id(x,y)][NORTH] =    chan_in_all [NORTH_ID];
+                        assign chan_out_all [NORTH_ID] = router_chan_out [`router_id(x,y)][NORTH];
+                    end//topology
+                end//y>0
+                if(x>0)begin :not_first_x
+                    assign    router_chan_in[`router_id(x,y)][WEST] =  router_chan_out [`router_id((x-1),y)][EAST];
+                end else begin :first_x
+                    if(IS_MESH) begin :first_x_mesh
+                        assign    router_chan_in[`router_id(x,y)][WEST] =   {PITON_CHANEL_w{1'b0}};
+                    end else if(IS_TORUS) begin :first_x_torus
+                        assign    router_chan_in[`router_id(x,y)][WEST] =   router_chan_out [`router_id((NX-1),y)][EAST] ;
+                        end else if(IS_FMESH) begin : first_x_fmesh //connect to endp
+                        localparam WEST_ID = NX*NY*NL +2*NX + y;
+                        assign router_chan_in [`router_id(x,y)][WEST] =    chan_in_all [WEST_ID];
+                        assign chan_out_all [WEST_ID] = router_chan_out [`router_id(x,y)][WEST];
+                    end//topology
+                end
+                if(y    <    NY-1) begin : firsty
+                    assign  router_chan_in[`router_id(x,y)][SOUTH] =    router_chan_out [`router_id(x,(y+1))][NORTH];
+                end else     begin : lasty
+                    if(IS_MESH) begin :ly_mesh
+                        assign  router_chan_in[`router_id(x,y)][SOUTH]=  {PITON_CHANEL_w{1'b0}};
+                    end else if(IS_TORUS) begin :ly_torus
+                        assign  router_chan_in[`router_id(x,y)][SOUTH]=    router_chan_out [`router_id(x,0)][NORTH];
+                    end else if(IS_FMESH) begin : ly_fmesh //connect to endp
+                        localparam SOUTH_ID = NX*NY*NL + NX + x;
+                        assign router_chan_in [`router_id(x,y)][SOUTH] =    chan_in_all [SOUTH_ID];
+                        assign chan_out_all [SOUTH_ID] = router_chan_out [`router_id(x,y)][SOUTH];
+                    end//topology
+                end
+                // endpoint(s) connection
+                // connect other local ports
+                for  (l=0;   l<NL; l=l+1) begin :locals
+                    localparam ENDPID = `endp_id(x,y,l);
+                    localparam LOCALP = (l==0) ? l : l + R2R_CHANELS_REGULAR; // first local port is connected to router port 0. The rest are connected at the end
+                    assign router_chan_in [`router_id(x,y)][LOCALP] =    chan_in_all [ENDPID];
+                    assign chan_out_all [ENDPID] = router_chan_out [`router_id(x,y)][LOCALP];
+                end// locals
+            end //y
+        end //x
+    end// regular_topo
+    endgenerate
 endmodule
-
-
-
-
+module piton_mesh_pronoc_wrap (
+    clk,
+    reset,
+    chan_in_all,
+    chan_out_all
+);
+    import piton_pkg::*;
+    import pronoc_pkg::*;
+    input   clk,reset;
+    //local ports  ProNoC interface
+    input   smartflit_chanel_t chan_in_all  [NE-1 : 0];
+    output  smartflit_chanel_t chan_out_all [NE-1 : 0];
+    //piton interface
+    piton_chan_t piton_chan_in_all  [NE-1 : 0];
+    piton_chan_t piton_chan_out_all [NE-1 : 0];
+    piton_mesh pmesh(
+        .clk         (clk         ),
+        .reset       (reset       ),
+        .chan_in_all (piton_chan_in_all ),
+        .chan_out_all(piton_chan_out_all)
+        );
+    localparam
+        NX = T1,
+        NY = T2,
+        RXw = log2(NX),    // number of node in x axis
+        RYw = log2(NY),
+        EXw = log2(NX),    // number of node in x axis
+        EYw = log2(NY);   // number of node in y axis
+    wire [RXw-1 : 0] current_x [NE-1 : 0];
+    wire [RYw-1 : 0] current_y [NE-1 : 0];
+    reg [`XY_WIDTH-1:0] myLocX [NE-1 : 0];       // thi
+    reg [`XY_WIDTH-1:0] myLocY [NE-1 : 0];
+    reg [`CHIP_ID_WIDTH-1:0] myChipID[NE-1 : 0];
+    genvar i;
+    generate
+    for (i=0; i<NE;i++) begin :E_
+        regular_topo_router_addr_decode  r_addr_decode  (
+            .r_addr(i[RAw-1:0]),
+            .rx(current_x[i]),
+            .ry(current_y[i]),
+            .valid()
+        );
+        always_comb begin
+            myLocX[i]   = {`XY_WIDTH{1'b0}};
+            myLocY[i]   = {`XY_WIDTH{1'b0}};
+            myChipID[i] = {`CHIP_ID_WIDTH{1'b0}};
+            myLocX[i]  [RXw-1 : 0] = current_x[i];
+            myLocY[i]  [RYw-1 : 0] = current_y[i];
+        end
+        piton_to_pronoc_wrapper #(.NOC_NUM(1),.TILE_NUM(i),.CHIP_SET_PORT(0),.FLATID_WIDTH(FLATID_WIDTH)) pi2pr_wrapper1
+        (
+            .default_chipid(myChipID[i]), .default_coreid_x(myLocX[i]), .default_coreid_y(myLocY[i]), .flat_tileid(i[FLATID_WIDTH-1 : 0]),
+            .reset(reset),
+            .clk (clk),
+            .dataIn (piton_chan_out_all[i].data),
+            .validIn(piton_chan_out_all[i].valid),
+            .yummyIn(piton_chan_out_all[i].yummy),
+            .chan_out(chan_out_all[i]),
+            .current_r_addr_i(i[RAw-1:0])
+        );
+        pronoc_to_piton_wrapper  #(.NOC_NUM(1),.TILE_NUM(i),.FLATID_WIDTH(FLATID_WIDTH)) pr2pi_wrapper1
+        (
+            .default_chipid(myChipID[i]), .default_coreid_x(myLocX[i]), .default_coreid_y(myLocY[i]), .flat_tileid(i[FLATID_WIDTH-1:0]),
+            .reset(reset),
+            .clk (clk),
+            .dataOut (piton_chan_in_all[i].data ),
+            .validOut(piton_chan_in_all[i].valid ),
+            .yummyOut(piton_chan_in_all[i].yummy ),
+            .chan_in (chan_in_all[i] ),
+            .current_r_addr_o( )
+        );
+    end
+    endgenerate
+endmodule
\ No newline at end of file
diff --git a/mpsoc/rtl/src_openpiton/piton_pkg.sv b/mpsoc/rtl/src_openpiton/piton_pkg.sv
index 8bb3116..4c3ad6d 100644
--- a/mpsoc/rtl/src_openpiton/piton_pkg.sv
+++ b/mpsoc/rtl/src_openpiton/piton_pkg.sv
@@ -1,19 +1,17 @@
 `timescale     1ns/1ps
 /****************************************************************************
- * pronoc_pkg.sv
+ * piton_pkg.sv
  ****************************************************************************/
 
 package piton_pkg; 
-	`include "define.tmp.h"
-	localparam FLATID_WIDTH = 8;
-	
-	typedef struct packed {
-		logic [`DATA_WIDTH-1:0] 	data;
-		logic valid;
-		logic yummy; 
-	} piton_chan_t;
-	localparam PITON_CHANEL_w = $bits(piton_chan_t); 
-	
-	
-	
+    `include "define.tmp.h"
+    localparam FLATID_WIDTH = 8;
+    
+    typedef struct packed {
+        logic [`DATA_WIDTH-1:0]     data;
+        logic valid;
+        logic yummy; 
+    } piton_chan_t;
+    localparam PITON_CHANEL_w = $bits(piton_chan_t); 
+    
 endpackage :piton_pkg
diff --git a/mpsoc/rtl/src_openpiton/piton_tail_hdr_detect.sv b/mpsoc/rtl/src_openpiton/piton_tail_hdr_detect.sv
new file mode 100644
index 0000000..d0a38b5
--- /dev/null
+++ b/mpsoc/rtl/src_openpiton/piton_tail_hdr_detect.sv
@@ -0,0 +1,68 @@
+/**************************************************************
+ * File        : piton_tail_hdr_detect.sv
+ * Description : Detect if an OpenPiton flit is a tail or a header
+ *
+ * Author      :  Alireza Monemi
+ * Date        :  2025
+ **************************************************************/
+`include "define.tmp.h"
+
+module piton_tail_hdr_detect #(
+    parameter FLIT_WIDTH=64
+)(
+    reset,
+    clk,
+    length_in,
+    valid,
+    ready,
+    is_tail,
+    is_header
+);
+    input  wire reset,clk;
+    input  wire valid,ready;
+    input  wire [`MSG_LENGTH_WIDTH-1 : 0] length_in;
+    output wire is_tail, is_header;
+
+    localparam
+        CHANEL_WORLD_NUM = FLIT_WIDTH/64;
+    localparam  [1:0]
+        HEADER = 1,
+        BODY   = 2;
+    reg [1:0] flit_type,flit_type_next;
+    reg  [`MSG_LENGTH_WIDTH-1  : 0] remain, remain_next;
+
+    always_comb begin
+        remain_next = remain;
+        flit_type_next = flit_type;
+        if(valid & ready) begin
+            case(flit_type)
+            HEADER: begin
+                if (length_in >= CHANEL_WORLD_NUM ) begin
+                    flit_type_next = BODY;
+                    remain_next = length_in  - CHANEL_WORLD_NUM;
+                end
+            end //HEADER
+            BODY: begin
+                if(remain < CHANEL_WORLD_NUM) begin
+                    flit_type_next = HEADER;
+                end else if (remain >= CHANEL_WORLD_NUM ) begin
+                    remain_next = remain  - CHANEL_WORLD_NUM;
+                end
+            end //BODY
+            endcase
+        end
+    end//always
+
+    always @ (posedge clk) begin
+        if (reset)  begin
+            remain <= {`MSG_LENGTH_WIDTH{1'b0}};
+            flit_type <=HEADER;
+        end else begin
+            remain <= remain_next;
+            flit_type <= flit_type_next;
+        end
+    end
+
+    assign is_tail = (flit_type == HEADER)? (length_in < CHANEL_WORLD_NUM) : (remain < CHANEL_WORLD_NUM);
+    assign is_header = (flit_type == HEADER);
+endmodule
diff --git a/mpsoc/rtl/src_openpiton/wrapper.sv b/mpsoc/rtl/src_openpiton/piton_wrapper.sv
similarity index 69%
rename from mpsoc/rtl/src_openpiton/wrapper.sv
rename to mpsoc/rtl/src_openpiton/piton_wrapper.sv
index 73acf1c..70d5d5b 100644
--- a/mpsoc/rtl/src_openpiton/wrapper.sv
+++ b/mpsoc/rtl/src_openpiton/piton_wrapper.sv
@@ -1,146 +1,119 @@
-/****************************************************************************
- * wrapper.sv
- ****************************************************************************/
-
-/**
- * Module: pronoc_to_piton_wrapper
- * 
- * TODO: Add module documentation
- */
-`timescale      1ns/1ps
-
+/**************************************************************
+ * File        : wrapper.sv
+ * Description : Contains the necessary modules for adapting
+ *               ProNoC with OpenPiton dynamic-node integration.
+ *
+ * Author      :  Alireza Monemi
+ * Date        :  2025
+ **************************************************************/
 `include "define.tmp.h"
 `include "pronoc_def.v"
 
-
-
 module piton_to_pronoc_endp_addr_converter
 #(
-        parameter CHIP_SET_PORT = 3,
-        parameter NOC_ID=0
-)      
-(
+    parameter CHIP_SET_PORT = 3
+) (
     default_chipid_i,
     piton_chipid_i,
     piton_coreid_x_i,
     piton_coreid_y_i,
     piton_fbits_i,
-
     pronoc_endp_addr_o,
     piton_end_addr_coded_o
 );
-
-    `NOC_CONF
-
-    localparam  
+    import pronoc_pkg::*;
+    localparam
         PRESERVED_DATw = (`MSG_LENGTH_WIDTH + `MSG_TYPE_WIDTH + `MSG_MSHRID_WIDTH + `MSG_OPTIONS_1_WIDTH ),
         HEAD_DATw      = (64-MSB_BE-1),
         ADDR_CODED     = (HEAD_DATw - PRESERVED_DATw);
-
-
+    
     input  [`NOC_CHIPID_WIDTH-1:0]  default_chipid_i;
     input  [`NOC_CHIPID_WIDTH-1:0]  piton_chipid_i;
     input  [`NOC_X_WIDTH-1:0]       piton_coreid_x_i;
     input  [`NOC_Y_WIDTH-1:0]       piton_coreid_y_i;
-    input  [`MSG_SRC_FBITS_WIDTH-1:0]  piton_fbits_i;       
+    input  [`MSG_SRC_FBITS_WIDTH-1:0]  piton_fbits_i;
     output [EAw-1 : 0] pronoc_endp_addr_o;
     output [ADDR_CODED-1 : 0] piton_end_addr_coded_o;
-
+    
     generate 
         if(T3==1) begin:same
             piton_to_pronoc_endp_addr_converter_same_topology  #(
-                .CHIP_SET_PORT(CHIP_SET_PORT),
-                .NOC_ID(NOC_ID)
+                .CHIP_SET_PORT(CHIP_SET_PORT)
             ) conv (
                 .default_chipid_i  (default_chipid_i),
                 .piton_chipid_i    (piton_chipid_i),
                 .piton_coreid_x_i  (piton_coreid_x_i),
                 .piton_coreid_y_i  (piton_coreid_y_i),
-                .piton_fbits_i     (piton_fbits_i ),                    
+                .piton_fbits_i     (piton_fbits_i ),
                 .pronoc_endp_addr_o (pronoc_endp_addr_o),
-                .piton_end_addr_coded_o(piton_end_addr_coded_o)        
+                .piton_end_addr_coded_o(piton_end_addr_coded_o)
             );    
-
         end else begin :diff
             piton_to_pronoc_endp_addr_converter_diffrent_topology  #(
-                .CHIP_SET_PORT(CHIP_SET_PORT),
-                .NOC_ID(NOC_ID)
+                .CHIP_SET_PORT(CHIP_SET_PORT)
             ) conv (
                 .default_chipid_i  (default_chipid_i),
                 .piton_chipid_i    (piton_chipid_i),
                 .piton_coreid_x_i  (piton_coreid_x_i),
                 .piton_coreid_y_i  (piton_coreid_y_i),
-                .piton_fbits_i     (piton_fbits_i ),                    
+                .piton_fbits_i     (piton_fbits_i ),
                 .pronoc_endp_addr_o (pronoc_endp_addr_o),
-                .piton_end_addr_coded_o(piton_end_addr_coded_o)        
+                .piton_end_addr_coded_o(piton_end_addr_coded_o)
             );    
-
-
         end 
     endgenerate
-
 endmodule
 
 
 module piton_to_pronoc_endp_addr_converter_diffrent_topology
 #(
-    parameter CHIP_SET_PORT = 3,
-    parameter NOC_ID=0
-)
-(
+    parameter CHIP_SET_PORT = 3
+)(
     default_chipid_i,
     piton_chipid_i,
     piton_coreid_x_i,
     piton_coreid_y_i,
     piton_fbits_i,
-
     pronoc_endp_addr_o,
     piton_end_addr_coded_o
 );
 
-    `NOC_CONF
+    import pronoc_pkg::*;
     localparam  
         PRESERVED_DATw = (`MSG_LENGTH_WIDTH + `MSG_TYPE_WIDTH + `MSG_MSHRID_WIDTH + `MSG_OPTIONS_1_WIDTH ),
         HEAD_DATw      = (64-MSB_BE-1),
         ADDR_CODED     = (HEAD_DATw - PRESERVED_DATw);
-
     input  [`NOC_CHIPID_WIDTH-1:0]  default_chipid_i;
     input  [`NOC_CHIPID_WIDTH-1:0]  piton_chipid_i;
     input  [`NOC_X_WIDTH-1:0]       piton_coreid_x_i;
     input  [`NOC_Y_WIDTH-1:0]       piton_coreid_y_i;
-    input  [`MSG_SRC_FBITS_WIDTH-1:0]  piton_fbits_i;       
-
+    input  [`MSG_SRC_FBITS_WIDTH-1:0]  piton_fbits_i;
     output reg [EAw-1 : 0] pronoc_endp_addr_o;
     output reg [ADDR_CODED-1 : 0] piton_end_addr_coded_o;
-
     localparam [3:0] 
         FBIT_NONE = 4'b0000,
         FBIT_W  = 4'b0010,
         FBIT_S  = 4'b0011,
         FBIT_E  = 4'b0100,
         FBIT_N  = 4'b0101;
-
     localparam       
         Xw = log2(NX),    // number of node in x axis
-        Yw = log2(NY);    // number of node in y axis       
-
+        Yw = log2(NY);    // number of node in y axis
     localparam 
         PITON_TOPOLOGY = "FMESH",
         PITON_Xw = log2(`PITON_X_TILES),    // number of node in x axis
-        PITON_Yw = log2(`PITON_Y_TILES),    // number of node in y axis         
+        PITON_Yw = log2(`PITON_Y_TILES),    // number of node in y axis
         PITON_NE =(`PITON_X_TILES * `PITON_Y_TILES) + 2 * (`PITON_X_TILES+`PITON_Y_TILES),
         PITON_MAX_P = 5, 
         PITON_NLw= log2(PITON_MAX_P),
         PITON_EAw = PITON_Xw + PITON_Yw + log2(PITON_MAX_P),
         PITON_NEw = log2(PITON_NE);
-
     wire [PITON_NLw-1: 0] piton_edge_port;
     assign piton_edge_port =
         (piton_fbits_i [3:0] == FBIT_NONE) ? LOCAL:
         (piton_fbits_i [3:0] == FBIT_W   ) ? WEST:
         (piton_fbits_i [3:0] == FBIT_S   ) ? SOUTH:
         (piton_fbits_i [3:0] == FBIT_E   ) ? EAST: NORTH;
-
     wire [PITON_Xw-1 : 0] piton_x =  piton_coreid_x_i;
     wire [PITON_Xw-1 : 0] piton_y =  piton_coreid_y_i;
     wire [EAw-1 : 0] pronoc_endp_addr , chipset_endp_addr;
@@ -149,109 +122,89 @@ module piton_to_pronoc_endp_addr_converter_diffrent_topology
     //find  piton index
     wire [PITON_EAw-1 : 0] piton_e_addr = {piton_l,piton_y,piton_x}; 
     wire [PITON_NEw-1 : 0] piton_id;
-    endp_addr_decoder #( .TOPOLOGY(PITON_TOPOLOGY),   .T1(`PITON_X_TILES), .T2(`PITON_Y_TILES), .T3(1), .EAw(PITON_EAw),  .NE(PITON_NE))
-        encode1 ( .id(piton_id), .code(piton_e_addr ));
-
+    endp_addr_decoder encode1 ( .id_out(piton_id), .code_in(piton_e_addr ));
     reg [NEw-1 : 0] ProNoC_id;
-
     generate 
         if (PITON_NEw < NEw) begin 
-            always @ (*) begin 
+            always_comb begin 
                 ProNoC_id =0;
                 ProNoC_id [PITON_NEw-1 : 0] = piton_id;
             end
         end else begin 
-            always @ (*) begin                 
+            always_comb begin
                 ProNoC_id =0;
                 ProNoC_id  = piton_id [ NEw-1 : 0];
             end
         end
     endgenerate 
-
-    endp_addr_encoder #( .TOPOLOGY(TOPOLOGY), .T1(T1), .T2(T2), .T3(T3), .EAw(EAw),  .NE(NE)) 
-        encode2 ( .id(ProNoC_id), .code( pronoc_endp_addr1 ));
-    
+    endp_addr_encoder encode2 ( .id_in(ProNoC_id), .code_out( pronoc_endp_addr1 ));
     // The address2 is generated for pronoc in OP and its not coded based on OP so no need to convert it.
     // It is indicated when msb of fbit is one  
     wire   [`NOC_X_WIDTH + `NOC_Y_WIDTH-1 : 0]   input_merged = {piton_coreid_y_i ,    piton_coreid_x_i};
     assign pronoc_endp_addr2 = input_merged [EAw-1 : 0];
     assign pronoc_endp_addr  = (piton_fbits_i[3]) ? pronoc_endp_addr2 : pronoc_endp_addr1;
-
     localparam [NEw-1 : 0] CHIP_SET_ID = T1*T2*T3+2*T1; // endp connected  of west port of router 0-0
-    endp_addr_encoder #( .TOPOLOGY(TOPOLOGY), .T1(T1), .T2(T2), .T3(T3), .EAw(EAw),  .NE(NE)) 
-        encode3 ( .id(CHIP_SET_ID), .code( chipset_endp_addr ));
-
+    endp_addr_encoder encode3 ( .id_in(CHIP_SET_ID), .code_out( chipset_endp_addr ));
     assign pronoc_endp_addr_o =  (piton_chipid_i == default_chipid_i ) ? pronoc_endp_addr : chipset_endp_addr;
-
-    always @ (*) begin 
+    always_comb begin 
         piton_end_addr_coded_o = {ADDR_CODED{1'b0}};
         piton_end_addr_coded_o [Yw+Xw-1 : 0] =   {piton_coreid_y_i[Yw-1 : 0],  piton_coreid_x_i[Xw-1 : 0]};
         if(piton_chipid_i == 8192 ) begin 
             piton_end_addr_coded_o[ADDR_CODED-1]=1'b1;
         end// TODO need to know how chip id coded from zero to max or from 8192 to zero
     end
-
 endmodule
 
 
 
 module piton_to_pronoc_endp_addr_converter_same_topology 
 #(
-    parameter CHIP_SET_PORT = 3,
-    parameter NOC_ID=0
-)
-(
+    parameter CHIP_SET_PORT = 3
+)(
     default_chipid_i,
     piton_chipid_i,
     piton_coreid_x_i,
     piton_coreid_y_i,
     piton_fbits_i,
-
     pronoc_endp_addr_o,
     piton_end_addr_coded_o
 );
 
-    `NOC_CONF
-    
+    import pronoc_pkg::*;
     localparam  
         PRESERVED_DATw = (`MSG_LENGTH_WIDTH + `MSG_TYPE_WIDTH + `MSG_MSHRID_WIDTH + `MSG_OPTIONS_1_WIDTH ),
         HEAD_DATw      = (64-MSB_BE-1),
         ADDR_CODED     = (HEAD_DATw - PRESERVED_DATw);
-
     input  [`NOC_CHIPID_WIDTH-1:0]  default_chipid_i;
     input  [`NOC_CHIPID_WIDTH-1:0]  piton_chipid_i;
     input  [`NOC_X_WIDTH-1:0]       piton_coreid_x_i;
     input  [`NOC_Y_WIDTH-1:0]       piton_coreid_y_i;
     input  [`MSG_SRC_FBITS_WIDTH-1:0]  piton_fbits_i;
     
-    
     output reg [EAw-1 : 0] pronoc_endp_addr_o;
     output reg    [ADDR_CODED-1 : 0] piton_end_addr_coded_o;
     
     localparam [3:0] 
-        FBIT_NONE    =4'b0000,
+        FBIT_NONE =4'b0000,
         FBIT_W    =4'b0010,
         FBIT_S    =4'b0011,
         FBIT_E    =4'b0100,
         FBIT_N    =4'b0101;
-    
-    localparam        
+    localparam
         Xw = log2(NX),    // number of node in x axis
         Yw = log2(NY);    // number of node in y axis
     
-    
     wire [EAw-Yw-Xw-1 : 0] edge_port;
-        assign edge_port = (piton_fbits_i [3:0] == FBIT_NONE) ? LOCAL:
-                           (piton_fbits_i [3:0] == FBIT_W   ) ? WEST:
-                           (piton_fbits_i [3:0] == FBIT_S   ) ? SOUTH:
-                           (piton_fbits_i [3:0] == FBIT_E   ) ? EAST: NORTH;
+        assign edge_port = 
+            (piton_fbits_i [3:0] == FBIT_NONE) ? LOCAL:
+            (piton_fbits_i [3:0] == FBIT_W   ) ? WEST:
+            (piton_fbits_i [3:0] == FBIT_S   ) ? SOUTH:
+            (piton_fbits_i [3:0] == FBIT_E   ) ? EAST: NORTH;
     
     //coded for FMESH topology
-    generate 
-    
-    
+    generate
     if(TOPOLOGY == "FMESH") begin 
-        always @ (*) begin 
+        always_comb begin 
             pronoc_endp_addr_o = {EAw{1'b0}};
             if(piton_chipid_i == default_chipid_i ) begin 
                 pronoc_endp_addr_o [Yw+Xw-1 : 0] =  {piton_coreid_y_i[Yw-1 : 0],  piton_coreid_x_i[Xw-1 : 0]};
@@ -263,83 +216,69 @@ module piton_to_pronoc_endp_addr_converter_same_topology
             end
         end    
     end else begin //"mesh" 
-        always @ (*) begin 
+        always_comb begin 
             pronoc_endp_addr_o = {EAw{1'b0}};
-            pronoc_endp_addr_o [Yw+Xw-1 : 0] =  {piton_coreid_y_i[Yw-1 : 0],  piton_coreid_x_i[Xw-1 : 0]};            
+            pronoc_endp_addr_o [Yw+Xw-1 : 0] =  {piton_coreid_y_i[Yw-1 : 0],  piton_coreid_x_i[Xw-1 : 0]};
         end    
     end
     endgenerate
-
-    always @ (*) begin 
+    
+    always_comb begin 
         piton_end_addr_coded_o = {ADDR_CODED{1'b0}};
         piton_end_addr_coded_o [Yw+Xw-1 : 0] =   {piton_coreid_y_i[Yw-1 : 0],  piton_coreid_x_i[Xw-1 : 0]};
         if(piton_chipid_i == 8192 ) begin 
             piton_end_addr_coded_o[ADDR_CODED-1]=1'b1;
         end// TODO need to know how chip id coded from zero to max or from 8192 to zero
-    end    
-    
-    
-endmodule    
+    end
+endmodule
 
 
-module pronoc_to_piton_endp_addr_converter #(
-	parameter NOC_ID=0
-)(
-    piton_end_addr_coded_i,    
-    
+module pronoc_to_piton_endp_addr_converter (
+    piton_end_addr_coded_i,
     piton_chipid_o,
     piton_coreid_x_o,
     piton_coreid_y_o
-    
 );
-
-    `NOC_CONF
-
-//coded for FMESH topology
-localparam    
-    Xw = log2(NX),    // number of node in x axis
-    Yw = log2(NY);    // number of node in y axis
-
-localparam  
+    import pronoc_pkg::*;
+    
+    //coded for FMESH topology
+    localparam    
+        Xw = log2(NX),    // number of node in x axis
+        Yw = log2(NY);    // number of node in y axis
+    localparam  
         PRESERVED_DATw = (`MSG_LENGTH_WIDTH + `MSG_TYPE_WIDTH + `MSG_MSHRID_WIDTH + `MSG_OPTIONS_1_WIDTH ),
         HEAD_DATw      = (64-MSB_BE-1),
         ADDR_CODED     = (HEAD_DATw - PRESERVED_DATw);
-
-output  [`NOC_CHIPID_WIDTH-1:0]  piton_chipid_o;
-output  reg [`NOC_X_WIDTH-1:0]   piton_coreid_x_o;
-output  reg [`NOC_Y_WIDTH-1:0]   piton_coreid_y_o;
-
-input   [ADDR_CODED-1 : 0] piton_end_addr_coded_i;
-
-
-    always @(*)begin 
+    
+    output  [`NOC_CHIPID_WIDTH-1:0]  piton_chipid_o;
+    output  reg [`NOC_X_WIDTH-1:0]   piton_coreid_x_o;
+    output  reg [`NOC_Y_WIDTH-1:0]   piton_coreid_y_o;
+    input   [ADDR_CODED-1 : 0] piton_end_addr_coded_i;
+    
+    always_comb begin 
         piton_coreid_x_o = {`MSG_DST_X_WIDTH{1'b0}}; 
         piton_coreid_y_o = {`MSG_DST_Y_WIDTH{1'b0}}; 
         {piton_coreid_y_o[Yw-1 : 0],  piton_coreid_x_o[Xw-1 : 0]}=piton_end_addr_coded_i [Yw+Xw-1 : 0];
     end
     //TODO regen chip ID 
     assign piton_chipid_o = (piton_end_addr_coded_i[ADDR_CODED-1]==1'b1)? 8192 : 0;
-    
 endmodule
 
 
 
-module piton_to_pronoc_wrapper 
-    
-    #(
-    parameter NOC_ID=0,
+module piton_to_pronoc_wrapper  #(
     parameter TILE_NUM =0,
     parameter CHIP_SET_PORT = 3,
     parameter FLATID_WIDTH=8
-    )(
-    default_chipid,  default_coreid_x, default_coreid_y, flat_tileid,    
+)(
+    default_chipid,  default_coreid_x, default_coreid_y, flat_tileid,
     reset, clk,
     dataIn, validIn, yummyIn,
     current_r_addr_i,
     chan_out
-    );    
+);
     
-    `NOC_CONF
+    import pronoc_pkg::*;
     localparam  
         PRESERVED_DATw = (`MSG_LENGTH_WIDTH + `MSG_TYPE_WIDTH + `MSG_MSHRID_WIDTH + `MSG_OPTIONS_1_WIDTH ),
         HEAD_DATw      = (64-MSB_BE-1),
@@ -350,15 +289,13 @@ module piton_to_pronoc_wrapper
     input  [`NOC_X_WIDTH-1:0]       default_coreid_x;
     input  [`NOC_Y_WIDTH-1:0]       default_coreid_y;
     input  [FLATID_WIDTH-1:0] flat_tileid;
-    
-    input [Fpay-1:0]         dataIn;
-    input                               validIn;
-    input                               yummyIn;
+    input  [Fpay-1:0]  dataIn;
+    input  validIn;
+    input  yummyIn;
     
     //pronoc
     input [RAw-1 : 0] current_r_addr_i;
     output  smartflit_chanel_t chan_out; 
-    
     input reset,clk;
     
     wire [`MSG_DST_CHIPID_WIDTH-1   :0] dest_chipid = dataIn [ `MSG_DST_CHIPID];
@@ -371,40 +308,35 @@ module piton_to_pronoc_wrapper
     wire [`MSG_OPTIONS_1_WIDTH-1    :0] option1     = dataIn [ `MSG_OPTIONS_1];
     
     wire tail,head;
-    tail_hdr_detect #(
+    piton_tail_hdr_detect #(
         .FLIT_WIDTH(Fpay)
     )piton_hdr(
         .reset(reset),
         .clk(clk),
-        .flit_in(dataIn),
+        .length_in(dataIn[ `MSG_LENGTH ]),
         .valid(validIn),
         .ready(1'b1),
         .is_tail(tail),
         .is_header(head)
-    );    
+    );
     
     wire [EAw-1 : 0] src_e_addr, dest_e_addr;
     wire [DSTPw-1 : 0] destport;
     wire [ADDR_CODED-1 : 0] dest_coded;
     
     piton_to_pronoc_endp_addr_converter #(
-		.NOC_ID(NOC_ID),
-		.CHIP_SET_PORT(CHIP_SET_PORT)
-		) src_conv (
+        .CHIP_SET_PORT(CHIP_SET_PORT)
+        ) src_conv (
         .default_chipid_i  (default_chipid),
         .piton_chipid_i    (default_chipid),
         .piton_coreid_x_i  (default_coreid_x),
         .piton_coreid_y_i  (default_coreid_y),
         .piton_fbits_i     (4'd0),
-            
         .pronoc_endp_addr_o (src_e_addr),
         .piton_end_addr_coded_o()
-        
-    );    
+    );
     
-    piton_to_pronoc_endp_addr_converter  #(
-		.NOC_ID(NOC_ID)
-	)dst_conv (
+    piton_to_pronoc_endp_addr_converter dst_conv (
         .default_chipid_i  (default_chipid),
         .piton_chipid_i    (dest_chipid),
         .piton_coreid_x_i  (dest_x),
@@ -413,31 +345,24 @@ module piton_to_pronoc_wrapper
         .pronoc_endp_addr_o (dest_e_addr),
         .piton_end_addr_coded_o(dest_coded)
         
-    );     
-    
-    conventional_routing #(
-        .TOPOLOGY(TOPOLOGY),
-        .ROUTE_NAME(ROUTE_NAME),
-        .ROUTE_TYPE(ROUTE_TYPE),
-        .T1(T1),
-        .T2(T2),
-        .T3(T3),
-        .RAw(RAw),
-        .EAw(EAw),
-        .DSTPw(DSTPw),
-        .LOCATED_IN_NI(1)
-    ) routing_module (
-        .reset(reset),
-        .clk(clk),
-        .current_r_addr(current_r_addr_i),
-        .dest_e_addr(dest_e_addr),
-        .src_e_addr(src_e_addr),
-        .destport(destport)
     );
-
-    
-    //endp_addr_decoder  #( .TOPOLOGY(TOPOLOGY), .T1(T1), .T2(T2), .T3(T3), .EAw(EAw),  .NE(NE)) decod1 ( .id(TILE_NUM), .code(current_e_addr));
-
+    generate 
+    if((CAST_TYPE == "UNICAST") && (IS_LOOKAHEAD==1'b1)) begin : conv
+    //The router is configured with lookaheadrouting. 
+    //The header flit is supposed to carry the destinaion output port 
+        conventional_routing #(
+            .LOCATED_IN_NI(1)
+        ) routing_module (
+            .reset(reset),
+            .clk(clk),
+            .current_r_addr(current_r_addr_i),
+            .dest_e_addr(dest_e_addr),
+            .src_e_addr(src_e_addr),
+            .destport(destport)
+        );
+    end
+    endgenerate
+    //endp_addr_decoder  decod1 ( .id_out(TILE_NUM), .code_in(current_e_addr));
     localparam DATA_w = HEAD_DATw + Fpay - 64; 
     wire [DATA_w-1 : 0] head_data;
     generate 
@@ -447,21 +372,18 @@ module piton_to_pronoc_wrapper
             assign head_data=  {dataIn[Fpay -1  : 64],dest_coded ,length, msg_type,  mshrid,option1}; 
         end
     endgenerate
-
+    
     wire [Fw-1 : 0] header_flit;
     reg [WEIGHTw-1 : 0] win;
-    
-    always @(*) begin 
+    always_comb begin 
         win={WEIGHTw{1'b0}};
         win[0]=1'b1;
     end    
     
-    
-    header_flit_generator    #(
-        .NOC_ID(NOC_ID),
-		.DATA_w(DATA_w) // header flit can carry Optional data. The data will be placed after control data.  Fpay >= DATA_w + CTRL_BITS_w  
+    header_flit_generator  #(
+        .DATA_w(DATA_w) // header flit can carry Optional data. The data will be placed after control data.  Fpay >= DATA_w + CTRL_BITS_w  
     )head_gen(
-        .flit_out(header_flit),    
+        .flit_out(header_flit),
         .src_e_addr_in(src_e_addr),
         .dest_e_addr_in(dest_e_addr),
         .destport_in(destport),
@@ -469,27 +391,27 @@ module piton_to_pronoc_wrapper
         .weight_in(win), 
         .vc_num_in(1'b1),
         .be_in(1'b0),
-        .data_in(head_data)    
+        .data_in(head_data)
     );
     
-    assign chan_out.ctrl_chanel.credit_init_val = 4;
-    
-    assign chan_out.flit_chanel.flit.hdr_flag =head;
-    assign chan_out.flit_chanel.flit.tail_flag=tail;
-    assign chan_out.flit_chanel.flit.vc=1'b1;
-    assign chan_out.flit_chanel.flit_wr=validIn;
-    assign chan_out.flit_chanel.credit=yummyIn;
-    assign chan_out.flit_chanel.flit.payload = (head)? header_flit[Fpay-1 : 0] : dataIn;
-    assign chan_out.smart_chanel = {SMART_CHANEL_w{1'b0}};
-    assign chan_out.flit_chanel.congestion = {CONGw{1'b0}};
-    
+    always_comb begin
+        chan_out.ctrl_chanel.credit_init_val = 4;
+        chan_out.flit_chanel.flit.hdr_flag =head;
+        chan_out.flit_chanel.flit.tail_flag=tail;
+        chan_out.flit_chanel.flit.vc=1'b1;
+        chan_out.flit_chanel.flit_wr=validIn;
+        chan_out.flit_chanel.credit=yummyIn;
+        chan_out.flit_chanel.flit.payload = (head)? header_flit[Fpay-1 : 0] : dataIn;
+        chan_out.smart_chanel = {SMART_CHANEL_w{1'b0}};
+        chan_out.flit_chanel.congestion = {CONGw{1'b0}};
+    end
     /*
     always @ (posedge clk) begin 
         if(validIn==1'b1 && flit_type==    HEADER)begin 
             $display("%t***Tile %d ***NoC %d************payload length =%d*************************",$time,TILE_NUM,NOC_ID,length);
             $display("%t*** src (c=%d,x=%d,y=%d) sends to dst (c=%d,x=%d,y=%d chan_out=%x)",$time,
                     default_chipid, default_coreid_x, default_coreid_y, dest_chipid,dest_x,dest_y,chan_out);
-//$finish;
+            //$finish;
         end
     end
     */
@@ -503,20 +425,17 @@ module piton_to_pronoc_wrapper
         (default_coreid_x != (TILE_NUM % `X_TILES ))) begin 
         $display ("ERROR: Address missmatch! ");
         $finish;
-        end        
+        end
     end
     //synthesis translate_on
     */
 endmodule
-/********************************
- *         pronoc_to_piton_wrapper  
- * ***************************/
 
 
-
-module pronoc_to_piton_wrapper         
-#(
-    parameter NOC_ID=0,
+/********************************
+ *       pronoc_to_piton_wrapper  
+ * ***************************/
+module pronoc_to_piton_wrapper #(
     parameter PORT_NUM=0,
     parameter TILE_NUM =0,
     parameter FLATID_WIDTH=8
@@ -526,58 +445,45 @@ module pronoc_to_piton_wrapper
     dataOut, validOut, yummyOut,
     current_r_addr_o,
     chan_in
-);    
-
-    `NOC_CONF
+);
+    import pronoc_pkg::*;
     localparam  
         PRESERVED_DATw = (`MSG_LENGTH_WIDTH + `MSG_TYPE_WIDTH + `MSG_MSHRID_WIDTH + `MSG_OPTIONS_1_WIDTH ),
         HEAD_DATw      = (64-MSB_BE-1),
         ADDR_CODED     = (HEAD_DATw - PRESERVED_DATw);
-
     //piton out
     input  [`NOC_CHIPID_WIDTH-1:0]  default_chipid;
-    input  [`NOC_X_WIDTH-1:0]       default_coreid_x;
-    input  [`NOC_Y_WIDTH-1:0]       default_coreid_y;
+    input  [`NOC_X_WIDTH-1:0] default_coreid_x;
+    input  [`NOC_Y_WIDTH-1:0] default_coreid_y;
     input  [FLATID_WIDTH-1:0] flat_tileid;
-    
-    output [Fpay-1:0]        dataOut;
-    output                              validOut;
-    output                              yummyOut;
-    
+    output [Fpay-1:0] dataOut;
+    output validOut;
+    output yummyOut;
     output [RAw-1 : 0] current_r_addr_o;
-    
     //pronoc in
     input  smartflit_chanel_t chan_in; 
-    
     input reset,clk;
     
+    assign current_r_addr_o = chan_in.ctrl_chanel.router_addr;
     
-    assign current_r_addr_o = chan_in.ctrl_chanel.neighbors_r_addr;
-    
-    
-    localparam        
+    localparam
         Xw = log2(NX),    // number of node in x axis
         Yw = log2(NY);    // number of node in y axis
     
-    
     enum bit [1:0] {HEADER, BODY,TAIL} flit_type,flit_type_next;
-    
     localparam DATA_w = HEAD_DATw + Fpay - 64; 
     hdr_flit_t hdr_flit;
     wire [DATA_w-1 : 0] head_dat;
-
     //extract ProNoC header flit data
     header_flit_info #(
-        .NOC_ID(NOC_ID),
         .DATA_w(DATA_w)
     )extract(
         .flit(chan_in.flit_chanel.flit),
-        .hdr_flit(hdr_flit),        
-        .data_o(head_dat)    
+        .hdr_flit(hdr_flit),
+        .data_o(head_dat)
     );
     
     wire [Fpay-1:0] header_flit;
-    
     wire [`MSG_DST_CHIPID_WIDTH-1   :0] dest_chipid;
     reg  [`MSG_DST_X_WIDTH-1        :0] dest_x     ;
     reg  [`MSG_DST_Y_WIDTH-1        :0] dest_y     ;
@@ -586,52 +492,34 @@ module pronoc_to_piton_wrapper
     wire [`MSG_TYPE_WIDTH-1         :0] msg_type   ;
     wire [`MSG_MSHRID_WIDTH-1       :0] mshrid     ;
     wire [`MSG_OPTIONS_1_WIDTH-1    :0] option1    ;
-
     wire [ADDR_CODED-1 : 0] dest_coded;
     
-
     assign {dest_coded, length, msg_type, mshrid, option1}  =  head_dat [HEAD_DATw-1 : 0]; 
-    
-    pronoc_to_piton_endp_addr_converter#(
-		.NOC_ID(NOC_ID)
-		)addr_conv ( 
-        .piton_end_addr_coded_i(dest_coded),        
+    pronoc_to_piton_endp_addr_converter addr_conv ( 
+        .piton_end_addr_coded_i(dest_coded),
         .piton_chipid_o (dest_chipid),
         .piton_coreid_x_o(dest_x),
-        .piton_coreid_y_o(dest_y)    
+        .piton_coreid_y_o(dest_y)
     );
-
-    
     wire [MAX_P-1:0] destport_one_hot;
-    
-    
     //    FBITS coding
     localparam [3: 0] 
-        FBITS_WEST         =  4'b0010, 
-        FBITS_SOUTH      =  4'b0011,   
-        FBITS_EAST       =  4'b0100,   
-        FBITS_NORTH      =  4'b0101,   
-        FBITS_PROCESSOR  =  4'b0000;  
-    /*    
-        ProNoC destination port order num
-        LOCAL   =   0
-        EAST    =   1
-        NORTH   =   2 
-        WEST    =   3
-        SOUTH   =   4         
-    */    
+        FBITS_WEST       =  4'b0010,
+        FBITS_SOUTH      =  4'b0011,
+        FBITS_EAST       =  4'b0100,
+        FBITS_NORTH      =  4'b0101,
+        FBITS_PROCESSOR  =  4'b0000;
         
-    //assign dest_fbits =        (PORT_NUM==0) ? 4'b0000:4'b0010;//offchip    
+    //assign dest_fbits =  (PORT_NUM==0) ? 4'b0000:4'b0010;//offchip
     
     /*
     always @(posedge clk) begin
         if(validOut) begin 
-            $display("********************************************destport_one_hot=%b; dest_fbits=%b",destport_one_hot,dest_fbits);
+            $display("Destport_one_hot=%b; dest_fbits=%b",destport_one_hot,dest_fbits);
             $finish;
         end
     end
     */
-    
     assign dest_fbits = 
         (destport_one_hot [LOCAL]) ? FBITS_PROCESSOR:
         (destport_one_hot [EAST ]) ? FBITS_EAST:
@@ -640,74 +528,24 @@ module pronoc_to_piton_wrapper
         (destport_one_hot [SOUTH ]) ? FBITS_SOUTH: FBITS_PROCESSOR;
     
     wire [DSTPw-1 : 0] dstp_encoded = hdr_flit.destport;
-    
-    
-    
     localparam 
         ELw = log2(T3),
         Pw  = log2(MAX_P),
-        PLw = (TOPOLOGY == "FMESH") ? Pw : ELw;
-
+        PLw = (IS_FMESH) ? Pw : ELw;
     wire [PLw-1 : 0] endp_p_in;
-    generate
-    if(TOPOLOGY == "FMESH") begin : fmesh
-        fmesh_endp_addr_decode #(
-            .T1(T1),
-            .T2(T2),
-            .T3(T3),
-            .EAw(EAw)
-        )
-        endp_addr_decode
-        (
-            .e_addr(hdr_flit.dest_e_addr),
-            .ex(),
-            .ey(),
-            .ep(endp_p_in),
-            .valid()
-        );
-    end else begin : mesh
-        mesh_tori_endp_addr_decode #(
-            .TOPOLOGY("MESH"),
-            .T1(T1),
-            .T2(T2),
-            .T3(T3),
-            .EAw(EAw)
-        )
-        endp_addr_decode
-        (
-            .e_addr(hdr_flit.dest_e_addr),
-            .ex( ),
-            .ey( ),
-            .el(endp_p_in),
-            .valid( )
-        );
-
-    end
-    endgenerate
+    assign endp_p_in = hdr_flit.dest_e_addr [DAw-1 : DAw-PLw];
     destp_generator #(
-            .TOPOLOGY(TOPOLOGY),
-            .ROUTE_NAME(ROUTE_NAME),
-            .ROUTE_TYPE(ROUTE_TYPE),
-            .T1(T1),
-            .NL(T3),
-            .P(MAX_P),
-            .PLw(PLw),
-            .DSTPw(DSTPw),        
-            .SELF_LOOP_EN (SELF_LOOP_EN),
-            .SW_LOC(PORT_NUM)
-        )
-        decoder
-        (
-            .destport_one_hot (destport_one_hot),
-            .dest_port_encoded(dstp_encoded),             
-            .dest_port_out(),   
-            .endp_localp_num(endp_p_in),
-            .swap_port_presel(),
-            .port_pre_sel(),
-            .odd_column(1'b0)
-        );
-    
-    
+        .P(MAX_P),
+        .SW_LOC(PORT_NUM)
+    ) decoder (
+        .destport_one_hot (destport_one_hot),
+        .dest_port_encoded(dstp_encoded),
+        .dest_port_out(),   
+        .endp_localp_num(endp_p_in),
+        .swap_port_presel(),
+        .port_pre_sel(),
+        .odd_column(1'b0)
+    );
     
     assign header_flit [ `MSG_DST_CHIPID] = dest_chipid; 
     assign header_flit [ `MSG_DST_X]      = dest_x; 
@@ -719,11 +557,10 @@ module pronoc_to_piton_wrapper
     assign header_flit [ `MSG_OPTIONS_1]  = option1; 
     
     generate 
-    if(Fpay > 64) begin :R_           
+    if(Fpay > 64) begin :R_
         assign  header_flit [Fpay - 1 : 64] =  head_dat[Fpay + HEAD_DATw -65 :HEAD_DATw]; 
     end
     endgenerate
-        
     
     wire head = chan_in.flit_chanel.flit.hdr_flag;
     wire tail = chan_in.flit_chanel.flit.tail_flag;
@@ -731,43 +568,31 @@ module pronoc_to_piton_wrapper
     assign validOut = chan_in.flit_chanel.flit_wr;
     assign yummyOut = chan_in.flit_chanel.credit;
     assign dataOut  = (head)? header_flit[Fpay-1 : 0] : chan_in.flit_chanel.flit.payload;
-    
-
 endmodule
 
-    
+
 /*********************
  *   pack noc_top ports 
- *     
  * ******************/
-
-module  noc_top_packed #(
-	parameter NOC_ID=0
-)
-(
+module  noc_top_packed (
     reset,
-    clk,    
+    clk,
     chan_in_all,
-    chan_out_all  
+    chan_out_all
 );
-
-    `NOC_CONF
+    import pronoc_pkg::*;
     localparam  
         PRESERVED_DATw = (`MSG_LENGTH_WIDTH + `MSG_TYPE_WIDTH + `MSG_MSHRID_WIDTH + `MSG_OPTIONS_1_WIDTH ),
         HEAD_DATw      = (64-MSB_BE-1),
         ADDR_CODED     = (HEAD_DATw - PRESERVED_DATw);
-
     input   clk,reset;
     //local ports 
     input   smartflit_chanel_t [NE-1 : 0] chan_in_all  ;
-    output  smartflit_chanel_t [NE-1 : 0] chan_out_all ;    
-
+    output  smartflit_chanel_t [NE-1 : 0] chan_out_all ;
     smartflit_chanel_t chan_in_all_unpacked  [NE-1 : 0];
     smartflit_chanel_t chan_out_all_unpacked [NE-1 : 0];
     
-    
     genvar i;
-    
     generate
     for (i=0;i<NE;i++) begin: E_
         assign chan_in_all_unpacked[i]=chan_in_all[i];
@@ -775,45 +600,36 @@ module  noc_top_packed #(
     end//for
     endgenerate
     
-    
-    noc_top #(
-		.NOC_ID(NOC_ID)
-		)unpacked (
+    noc_top  unpacked (
         .reset(reset),
-        .clk(clk),    
+        .clk(clk),
         .chan_in_all(chan_in_all_unpacked),
-        .chan_out_all(chan_out_all_unpacked)            
+        .chan_out_all(chan_out_all_unpacked)
     );
     
     //synthesis translate_off
     initial begin 
-        display_noc_parameters();         
-    end     
+        display_noc_parameters();
+    end
     //synthesis translate_on
     
-    
-    
-    
-endmodule    
+endmodule
 
 
-module ground_pronoc_end_port         
+module ground_pronoc_end_port
     #(
-        parameter TILE_NUM=0,
-        parameter NOC_ID=0
+        parameter TILE_NUM=0
     )(
         clk,
         reset,
         chan_in,
-        chan_out        
+        chan_out
     );
     
-    `NOC_CONF
-    
+    import pronoc_pkg::*;
     input  reset,clk;
     input   smartflit_chanel_t chan_in;
     output  smartflit_chanel_t    chan_out;
-    
     assign chan_out = {SMARTFLIT_CHANEL_w{1'b0}};
     //synthesis translate_off
     always @(posedge clk) begin 
@@ -823,87 +639,69 @@ module ground_pronoc_end_port
         end
     end
     //synthesis translate_on
-
 endmodule
 
 
 
-
-module pronoc_noc     
+module pronoc_noc
     #(
-    parameter NOC_ID=0,
     parameter CHIP_SET_PORT=3,
     parameter FLATID_WIDTH=8
     )(
         dataIn_flatten,
         validIn,
         yummyIn,
-        
         dataOut_flatten,
         validOut,
         yummyOut,
-        
         default_chipid,
         default_coreid_x_flatten,
         default_coreid_y_flatten,
         flat_tileid_flatten,
-
         reset,
         clk
-    
     );
-
-    `NOC_CONF
-
+    
+    import pronoc_pkg::*;
     input clk,reset;
     input [Fpay*NE-1:0] dataIn_flatten;
     input [NE-1 : 0] validIn;
     input [NE-1 : 0] yummyIn;
-    
     output [Fpay*NE-1:0] dataOut_flatten;
     output [NE-1 : 0] validOut;
     output [NE-1 : 0] yummyOut; 
-    
     input  [`NOC_CHIPID_WIDTH-1:0]  default_chipid;
     input  [`NOC_X_WIDTH*NE-1:0]    default_coreid_x_flatten;
     input  [`NOC_Y_WIDTH*NE-1:0]    default_coreid_y_flatten;
     input  [FLATID_WIDTH*NE-1:0]    flat_tileid_flatten;
     
-
     wire [Fpay-1:0] dataIn [NE-1 : 0];
     wire [Fpay-1:0] dataOut [NE-1 : 0];    
     wire [`NOC_X_WIDTH-1:0]  default_coreid_x[NE-1 : 0];
     wire [`NOC_Y_WIDTH-1:0]  default_coreid_y[NE-1 : 0];
     wire [FLATID_WIDTH-1:0]  flat_tileid[NE-1 : 0];
-
     smartflit_chanel_t pronoc_chan_in  [NE-1 : 0];
     smartflit_chanel_t pronoc_chan_out [NE-1 : 0];
     wire [RAw-1 : 0] current_r_addr  [NE-1 : 0];    
     
     genvar i;
-
-        
     generate
     for (i=0;i<NE;i++) begin: E_
-        
         assign dataIn [i] = dataIn_flatten [(i+1)* Fpay -1 :  i * Fpay];
         assign dataOut_flatten [(i+1)* Fpay -1 :  i * Fpay] = dataOut [i];
         assign default_coreid_x[i]=default_coreid_x_flatten[(i+1)*`NOC_X_WIDTH-1 : i*`NOC_X_WIDTH];
         assign default_coreid_y[i]=default_coreid_y_flatten[(i+1)*`NOC_Y_WIDTH-1 : i*`NOC_Y_WIDTH];
         assign flat_tileid[i]=flat_tileid_flatten[(i+1)*FLATID_WIDTH-1 : i*FLATID_WIDTH];
-
         pronoc_to_piton_wrapper 
         #(
-            .NOC_ID(NOC_ID),
             .PORT_NUM(0),
             .TILE_NUM(i),
             .FLATID_WIDTH(FLATID_WIDTH)
-        )pr2pi
-        (
+        ) pr2pi (
             .default_chipid(default_chipid),
             .default_coreid_x(default_coreid_x[i]), 
             .default_coreid_y(default_coreid_y[i]),
-            .flat_tileid(flat_tileid[i]),    
+            .flat_tileid(flat_tileid[i]),
             .reset(reset),
             .clk(clk),
             .dataOut(dataOut[i]),
@@ -911,20 +709,18 @@ module pronoc_noc
             .yummyOut(yummyOut[i]),
             .current_r_addr_o(current_r_addr[i]),
             .chan_in(pronoc_chan_out[i])
-        );    
+        );
         
-        piton_to_pronoc_wrapper      
+        piton_to_pronoc_wrapper
         #(
-            .NOC_ID(NOC_ID),
             .TILE_NUM(i),
             .CHIP_SET_PORT(CHIP_SET_PORT),
             .FLATID_WIDTH(FLATID_WIDTH)
-        )pi2pr
-        (
+        ) pi2pr (
             .default_chipid (default_chipid),
             .default_coreid_x(default_coreid_x[i]),
             .default_coreid_y(default_coreid_y[i]),
-            .flat_tileid(flat_tileid[i]),    
+            .flat_tileid(flat_tileid[i]),
             .reset(reset),
             .clk(clk),
             .dataIn(dataIn[i]),
@@ -932,22 +728,15 @@ module pronoc_noc
             .yummyIn(yummyIn[i]),
             .current_r_addr_i(current_r_addr[i]),
             .chan_out(pronoc_chan_in[i])
-        );    
-        
-        
-        
-        
+        );
     end//for
     endgenerate
     
-    
-    noc_top #(
-		.NOC_ID(NOC_ID)
-		)noc (
+    noc_top  noc (
         .reset(reset),
-        .clk(clk),    
+        .clk(clk),
         .chan_in_all (pronoc_chan_in ),
         .chan_out_all(pronoc_chan_out),
-        .router_event()            
+        .router_event( )
     );
-endmodule
\ No newline at end of file
+endmodule
diff --git a/mpsoc/rtl/src_peripheral/bus/wishbone_bus.v b/mpsoc/rtl/src_peripheral/bus/wishbone_bus.v
index 872380d..dcd9313 100755
--- a/mpsoc/rtl/src_peripheral/bus/wishbone_bus.v
+++ b/mpsoc/rtl/src_peripheral/bus/wishbone_bus.v
@@ -472,7 +472,7 @@ endgenerate
     )
     check_one_hot
     (
-        .in(s_sel_one_hot),
+        .D_in(s_sel_one_hot),
         .result(sel_is_one_hot)  
     
     );    
@@ -561,7 +561,7 @@ module  is_one_hot #(
     parameter INw= 20
 )
 (
-    in,
+    D_in,
     result         
 );
 
@@ -575,21 +575,21 @@ module  is_one_hot #(
     endfunction // log2 
     
     
-    input [INw-1  :   0] in;
+    input [INw-1  :   0] D_in;
     output result;
     
     localparam Aw = log2(INw+1);   
   
     reg [Aw-1 :   0] sum;   
-   
-  
-  // This is supposed to be synyhesized as "sum=in[0]+in[1]+...in[Num-1]"; 
+
+
+  // This is supposed to be synyhesized as "sum=D_in[0]+D_in[1]+...D_in[Num-1]"; 
   // It works with Quartus, Verilator and Modelsim compilers  
     integer k; 
     always @(*)begin 
         sum=0;
         for (k=0;k<INw;k=k+1)begin        
-             sum= sum + {{(Aw-1){1'b0}},in[k]};        
+            sum= sum + {{(Aw-1){1'b0}},D_in[k]};        
         end   
     end
     
diff --git a/mpsoc/rtl/src_peripheral/clk_source/xilinx_pll/xilinx_pll_sim/freq_gen.v b/mpsoc/rtl/src_peripheral/clk_source/xilinx_pll/xilinx_pll_sim/freq_gen.v
index 00cd380..bf63a12 100644
--- a/mpsoc/rtl/src_peripheral/clk_source/xilinx_pll/xilinx_pll_sim/freq_gen.v
+++ b/mpsoc/rtl/src_peripheral/clk_source/xilinx_pll/xilinx_pll_sim/freq_gen.v
@@ -29,7 +29,7 @@ module freq_gen (
 	/* needed to achieve phase lock, by detecting the first rising edge of the clk
 	 * and aligning the output clk to it */
 	input clk,
-	output reg out,
+	output reg Q_out,
 	/* period length is multiplied by 1000 for higher precision */
 	output reg [31:0] out_period_length_1000);
 
@@ -39,11 +39,11 @@ module freq_gen (
 	/* generate the wanted frequency */
 	always begin
 		if (PWRDWN) begin
-			out <= 1'bx;
+			Q_out <= 1'bx;
 			start <= 1'bx;
 			#1;
 		end else if (RST) begin
-			out <= 1'b0;
+			Q_out <= 1'b0;
 			start <= 1'b0;
 			#1;
 		end else if (ref_period_1000 > 0 && start) begin
@@ -54,10 +54,10 @@ module freq_gen (
 			 * easy solution to returning floating point numbers.
 			 */
 			out_period_length_1000 <= ((ref_period_1000 / 1000.0) * ((D * (O_1000 / 1000.0) * 1.0) / (M_1000 / 1000.0)) * 1000);
-			out <= ~out;
+			Q_out <= ~Q_out;
 			#(((ref_period_1000 / 1000.0) * ((D * (O_1000 / 1000.0) * 1.0) / (M_1000 / 1000.0))) / 2.0);
 		end else begin
-			out <= 1'b0;
+			Q_out <= 1'b0;
 			#1;
 		end
 	end
diff --git a/mpsoc/rtl/src_peripheral/clk_source/xilinx_pll/xilinx_pll_sim/plle2_base_sim.v b/mpsoc/rtl/src_peripheral/clk_source/xilinx_pll/xilinx_pll_sim/plle2_base_sim.v
index 65159cf..def2c59 100644
--- a/mpsoc/rtl/src_peripheral/clk_source/xilinx_pll/xilinx_pll_sim/plle2_base_sim.v
+++ b/mpsoc/rtl/src_peripheral/clk_source/xilinx_pll/xilinx_pll_sim/plle2_base_sim.v
@@ -157,7 +157,7 @@ module plle2_base_sim #(
 		.period_length((clkin_period_length_1000 / 1000.0)),
 		.period_stable(period_stable));
 
-	wire out[0:6];
+	wire Q_out[0:6];
 	wire [31:0] out_period_length_1000[0:6];
 	wire lock[0:6];
 
@@ -175,7 +175,7 @@ module plle2_base_sim #(
 				.period_stable(period_stable),
 				.ref_period_1000((clkin_period_length_1000)),
 				.clk(clkin),
-				.out(out[i]),
+				.Q_out(Q_out[i]),
 				.out_period_length_1000(out_period_length_1000[i]));
 		end
 	endgenerate
@@ -186,7 +186,7 @@ module plle2_base_sim #(
 			phase_shift ps (
 				.RST(RST),
 				.PWRDWN(PWRDWN),
-				.clk(out[i]),
+				.clk(Q_out[i]),
 				.shift_1000(CLKOUT_PHASE_INT_1000[i] + CLKFBOUT_PHASE_INT_1000),
 				.duty_cycle(CLKOUT_DUTY_CYCLE_INT_1000[i] / 10),
 				.clk_period_1000(out_period_length_1000[i]),
@@ -209,7 +209,7 @@ module plle2_base_sim #(
 		.period_stable(period_stable),
 		.ref_period_1000((clkin_period_length_1000)),
 		.clk(clkin),
-		.out(fb_out),
+		.Q_out(fb_out),
 		.out_period_length_1000(fb_out_period_length_1000));
 
 	phase_shift fb_ps (
diff --git a/mpsoc/rtl/src_peripheral/jtag/jtag_wb/xilinx_jtag_wb.v b/mpsoc/rtl/src_peripheral/jtag/jtag_wb/xilinx_jtag_wb.v
index d742fc9..ae3f3f0 100644
--- a/mpsoc/rtl/src_peripheral/jtag/jtag_wb/xilinx_jtag_wb.v
+++ b/mpsoc/rtl/src_peripheral/jtag/jtag_wb/xilinx_jtag_wb.v
@@ -64,7 +64,7 @@ module xilinx_jtag_wb #(
     input reset;//,clk;
     output reg cpu_en, system_reset;
     
-   // output [7: 0 ] out;
+   // output [7: 0 ] Q_out;
     
     input [JWB_NUM*WB2Jw-1  : 0] wb_to_jtag_all;
     output[JWB_NUM*J2WBw-1 : 0] jtag_to_wb_all; 
@@ -127,8 +127,8 @@ module xilinx_jtag_wb #(
                 (
                 .clk(clk),
                 .jtag_clk(tclk),
-                .in(wb_to_jtag_ack_all[i]),
-                .out(wb_to_jtag_ack_all_latched[i])
+                .D_in(wb_to_jtag_ack_all[i]),
+                .Q_out(wb_to_jtag_ack_all_latched[i])
             );
       
             
@@ -277,32 +277,32 @@ endmodule
 module wb_to_jtag_latch  (
     clk,
     jtag_clk,
-    in,
-    out
+    D_in,
+    Q_out
 );
 
-   input clk,jtag_clk,in;
-   output out;
-   
+   input clk,jtag_clk,D_in;
+   output Q_out;
+
    reg out_latch,reset_out;
     
     
     always @ (posedge clk) begin 
-        if(in) out_latch<=1'b1;
+        if(D_in) out_latch<=1'b1;
         else if(reset_out) out_latch<=1'b0;    
     end
     
    always @(posedge jtag_clk)begin 
-        if(out_latch | in) reset_out<=1'b1;
+        if(out_latch | D_in) reset_out<=1'b1;
         else reset_out<=1'b0;
    
    end
     
-    
-    
-    assign out =  reset_out ; 
-    
-  
+
+
+    assign Q_out =  reset_out ; 
+
+
 endmodule
 
   
diff --git a/mpsoc/rtl/src_peripheral/ni/ni_master.sv b/mpsoc/rtl/src_peripheral/ni/ni_master.sv
index 754c513..234ef82 100644
--- a/mpsoc/rtl/src_peripheral/ni/ni_master.sv
+++ b/mpsoc/rtl/src_peripheral/ni/ni_master.sv
@@ -2,31 +2,31 @@
 //`define MONITOR_DAT_FLITS 
 
 /**********************************************************************
-**	File:  ni.sv 
-**	Date:2017-06-04
+**    File:  ni.sv 
+**    Date:2017-06-04
 **    
-**	Copyright (C) 2014-2017  Alireza Monemi
+**    Copyright (C) 2014-2017  Alireza Monemi
 **    
-**	This file is part of ProNoC 
+**    This file is part of ProNoC 
 **
-**	ProNoC ( stands for Prototype Network-on-chip)  is free software: 
-**	you can redistribute it and/or modify it under the terms of the GNU
-**	Lesser General Public License as published by the Free Software Foundation,
-**	either version 2 of the License, or (at your option) any later version.
+**    ProNoC ( stands for Prototype Network-on-chip)  is free software: 
+**    you can redistribute it and/or modify it under the terms of the GNU
+**    Lesser General Public License as published by the Free Software Foundation,
+**    either version 2 of the License, or (at your option) any later version.
 **
-** 	ProNoC is distributed in the hope that it will be useful, but WITHOUT
-** 	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
-** 	or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
-** 	Public License for more details.
+**     ProNoC is distributed in the hope that it will be useful, but WITHOUT
+**     ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+**     or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
+**     Public License for more details.
 **
-** 	You should have received a copy of the GNU Lesser General Public
-** 	License along with ProNoC. If not, see <http:**www.gnu.org/licenses/>.
+**     You should have received a copy of the GNU Lesser General Public
+**     License along with ProNoC. If not, see <http:**www.gnu.org/licenses/>.
 **
 **
-**	Description: multi-chanel DMA-based network interface for 
+**    Description: multi-chanel DMA-based network interface for 
 **  handling packetizing/depacketizing data to/form NoC. 
 **  Can support CRC32 
-**	
+**    
 **
 *******************************************************************/
 
@@ -34,8 +34,7 @@
 
 
 module  ni_master 
-	#(    
-    parameter NOC_ID=0,
+    #(
     parameter MAX_TRANSACTION_WIDTH=10, // Maximum transaction size will be 2 power of MAX_DMA_TRANSACTION_WIDTH words 
     parameter MAX_BURST_SIZE =256, // in words
     parameter CRC_EN= "NO",// "YES","NO" if CRC is enable then the CRC32 of all packet data is calculated and sent via tail flit. 
@@ -43,25 +42,22 @@ module  ni_master
     // The header Data pre capture width. It Will be enabled when it is larger than zero. The header data can optionally carry a short width Data. This data can be pre-captured (completely/partially) 
     // by the NI before saving the packet in a memory buffer. This can give some hints to the software regarding the incoming 
     // packet such as its type, or source port so the software can store the packet in its appropriate buffer.
-        
     //wishbone port parameters
-    parameter Dw            =   32,
-    parameter S_Aw          =   7,
-    parameter M_Aw          =   32,
-    parameter TAGw          =   3,
-    parameter SELw          =   4
+    parameter Dw   = 32,
+    parameter S_Aw = 7,
+    parameter M_Aw = 32,
+    parameter TAGw = 3,
+    parameter SELw = 4
 )
 (
     //general 
     reset,
     clk,  
-      
     //noc interface  
     current_r_addr,
     current_e_addr,
     chan_in,
     chan_out,  
-     
     //wishbone slave interface signals
     s_dat_i,
     s_sel_i,
@@ -72,7 +68,6 @@ module  ni_master
     s_we_i,    
     s_dat_o,
     s_ack_o,
-       
     //wishbone master rd interface signals
     m_send_sel_o,
     m_send_addr_o,
@@ -82,7 +77,6 @@ module  ni_master
     m_send_we_o,
     m_send_dat_i,
     m_send_ack_i,
-    
     //wishbone master wr interface signals
     m_receive_sel_o,
     m_receive_dat_o,
@@ -92,28 +86,18 @@ module  ni_master
     m_receive_cyc_o,
     m_receive_we_o,
     m_receive_ack_i,
-    
     //interrupt interface
     irq    
-
 );
 
-   `NOC_CONF
-
-   
- 
-    input reset,clk;   
-
-
-     // NOC interfaces
+import pronoc_pkg::*;
+    input reset,clk;
+    // NOC interfaces
     input   [RAw-1   :   0]  current_r_addr;
     input   [EAw-1   :   0]  current_e_addr;
-    
-    input   smartflit_chanel_t 	chan_in;
-    output  smartflit_chanel_t 	chan_out;    
-    
-    
-   //wishbone slave interface signals
+    input   smartflit_chanel_t     chan_in;
+    output  smartflit_chanel_t     chan_out;    
+    //wishbone slave interface signals
     input   [Dw-1       :   0]      s_dat_i;
     input   [SELw-1     :   0]      s_sel_i;
     input   [S_Aw-1     :   0]      s_addr_i;  
@@ -134,7 +118,7 @@ module  ni_master
     output                          m_send_we_o;
     input   [Dw-1           :  0]   m_send_dat_i;
     input                           m_send_ack_i;    
-     
+    
      //wishbone write master interface signals
     output  [SELw-1          :   0] m_receive_sel_o;
     output  [Dw-1            :   0] m_receive_dat_o;
@@ -145,14 +129,10 @@ module  ni_master
     output                          m_receive_we_o;
     input                           m_receive_ack_i;   
     
-      //Interrupt  interface
+    //Interrupt  interface
     output                          irq;  
-  
     wire                            s_ack_o_next;    
     
-    
-    
-    
     logic  [Fw-1   :   0]  flit_out;     
     logic                  flit_out_wr;   
     logic   [V-1    :   0]  credit_in;
@@ -160,68 +140,55 @@ module  ni_master
     logic                   flit_in_wr;   
     logic  [V-1    :   0]  credit_out;     
     
-    
-    assign 	chan_out.flit_chanel.flit = flit_out; 
+    assign     chan_out.flit_chanel.flit = flit_out; 
     assign  chan_out.flit_chanel.flit_wr = flit_out_wr;
     assign  chan_out.flit_chanel.credit = credit_out;
-		
-		
     assign flit_in   =  chan_in.flit_chanel.flit;   
     assign flit_in_wr=  chan_in.flit_chanel.flit_wr; 
     assign credit_in =  chan_in.flit_chanel.credit;  
     
     //old ni.v file    
-    
     localparam 
         CTRL_FLGw=14,
         CHw=log2(V),
         BURST_SIZE_w= log2(MAX_BURST_SIZE+1),
         STATUS1w=  2 * CHw + 4;
-    
 /*   Wishbone bus slave address :
- 
- VC specific registers       
-       address bits       
- [4+Vw:4]      [3:0]                     
+VC specific registers
+    address bits
+    [4+Vw:4]   [3:0]
                 1  :   CTRL_FLAGS    :  {invalid_send_req_err,burst_size_err_isr,send_data_size_err_isr,crc_miss_match_isr,rcive_buff_ovrflw_err_isr,got_packet_isr, packet_is_saved_isr, packet_is_sent_isr,got_any_errorint_en,got_packet_int_en, packet_is_saved_int_en, packet_is_sent_int_en,receive_is_busy, send_is_busy}; 
-        
                 2  :   SEND_DEST_WB_ADDR        // The destination router address
                 3  :   SEND_POINTER_WB_ADDR,    // The address of data to be sent in byte 
- Virtual        4  :   SEND_DATA_SIZE,          // The size of data to be sent in byte  
- chanel        5  :   SEND_HDR_DATA            // The short width data that can be sent by header flit  
- number        
-                8  :   RECEIVE_SRC_WB_ADDR       // The source router (the router which is sent this packet).
+    Virtual     4  :   SEND_DATA_SIZE,          // The size of data to be sent in byte  
+    chanel      5  :   SEND_HDR_DATA            // The short width data that can be sent by header flit  
+    number      8  :   RECEIVE_SRC_WB_ADDR       // The source router (the router which is sent this packet).
                 9  :   RECEIVE_POINTER_WB_ADDR   // The address pointer of receiver memory in byte
                 10 :   RECEIVE_DATA_SIZE_WB_ADDR // The size of received data in byte
                 11 :   RECEIVE_MAX_BUFF_SIZ      // The receiver allocated buffer size in words. If the packet size is bigger than the buffer size the rest of it will be discarded
                 12 :   RECEIVE_START_INDEX_WB_ADDR  // The received data is written on RECEIVE_POINTER_WB_ADDR + RECEIVE_START_INDEX_WB_ADDR. If the write address reach to the end of buffer pointer, it starts at the RECEIVE_POINTER_WB_ADDR.   
                 13 :   RECEIVE_CTRL_WB_ADDR      // The NI receiver control register 
                 14 :   RECEIVE_PRECAP_DATA_ADDR  // The port address to the header flit data which can be pre-captured before buffering the actual data. 
- 
- Shared registers for all VCs
-    address bits       
-      [5:0]   
-       0:    STATUS_WB_ADDR     // status1:  {send_vc_enable_binary, receive_vc_enable_binary, any_err_isr_en,any_got_packet_isr_en,any_packet_is_saved_isr_en,any_packet_is_sent_isr_en}  
-       16:   BURST_SIZE_WB_ADDR  // The burst size in words        
-       32: reserved 
-      
+Shared registers for all VCs
+    address bits
+    [5:0]
+    0:    STATUS_WB_ADDR     // status1:  {send_vc_enable_binary, receive_vc_enable_binary, any_err_isr_en,any_got_packet_isr_en,any_packet_is_saved_isr_en,any_packet_is_sent_isr_en}  
+    16:   BURST_SIZE_WB_ADDR  // The burst size in words        
+    32: reserved 
 */
     localparam 
         chanel_ADDRw= 4,
         chanel_REGw = 4,
         GENRL_ADRw=2;
-    
-    wire [CHw-1 :   0] vc_addr = s_addr_i [chanel_REGw+CHw-1	:	chanel_REGw];
+    wire [CHw-1 :   0] vc_addr = s_addr_i [chanel_REGw+CHw-1    :    chanel_REGw];
     wire [GENRL_ADRw-1 :   0] genrl_reg_addr = s_addr_i [chanel_REGw+GENRL_ADRw-1  :   chanel_REGw];
     wire [chanel_ADDRw-1     :   0] vc_s_addr_i = s_addr_i [chanel_ADDRw-1: 0];
-
 //general registers     
     localparam [GENRL_ADRw-1  :   0]
         STATUS1_WB_ADDR  =   0,          // status1 
-      //  STATUS2_WB_ADDR  =   1,          // status2 
-     //   STATUS3_WB_ADDR  =   3,          // status3
-        BURST_SIZE_WB_ADDR = 1;      
-    
+        //STATUS2_WB_ADDR  =   1,          // status2 
+        //STATUS3_WB_ADDR  =   3,          // status3
+        BURST_SIZE_WB_ADDR = 1;
  //Readonly registers per VC
     localparam [chanel_ADDRw-1  :   0]
         GENERAL_REGS_WB_ADDR=0,
@@ -229,17 +196,13 @@ module  ni_master
         RECEIVE_SRC_WB_ADDR =8,         // The source router (the router which is sent this packet).
         RECEIVE_DATA_SIZE_WB_ADDR = 10,  // The size of received data in byte  
         RECEIVE_PRECAP_DATA_ADDR=14;
-  
-    
     localparam 
         WORLD_SIZE = Dw/8,
         OFFSETw= log2(WORLD_SIZE),        
         HDw = Fpay - (2*EAw) -  DSTPw - WEIGHTw,
         PRE_Dw = (HDATA_PRECAPw>0)? HDATA_PRECAPw : 1,
         MAX_PCK_SIZE_IN_BYTE = MAX_TRANSACTION_WIDTH + log2(Fpay/8);
-      
-        
- 
+    
     reg [BURST_SIZE_w-1  :   0] burst_size, burst_size_next,burst_counter,burst_counter_next;      
     wire [V-1 :   0] receive_vc_is_busy, send_vc_is_busy;
     wire [V-1 :   0] receive_vc_enable,send_vc_enable,vc_state_reg_enable;
@@ -270,9 +233,6 @@ module  ni_master
     wire [MAX_TRANSACTION_WIDTH-1    :   0] receive_vc_max_buff_siz [V-1   :  0];
     wire [MAX_TRANSACTION_WIDTH-1    :   0] receive_vc_start_index  [V-1   :  0];
     wire [OFFSETw-1 : 0] receive_vc_start_index_offset [V-1   :  0];
-    
-    
-    
     wire [V-1   :  0]   send_vc_start, receive_vc_start; 
     wire  received_flit_is_tail,received_flit_is_hdr;    
     wire [EAw-1  :   0]  vc_dest_e_addr [V-1   :  0];
@@ -282,7 +242,6 @@ module  ni_master
     wire [HDw-1 : 0] vc_hdr_data [V-1:0];
     wire [V-1    :   0]  send_vc_send_hdr,send_vc_send_tail;
     wire [V-1    :   0]  send_vc_done,receive_vc_done;    
-  
     wire [EAw-1   :   0]  dest_e_addr;
     wire [Cw-1   :   0]  pck_class;
     wire [BEw-1 : 0 ] be_in;
@@ -292,11 +251,6 @@ module  ni_master
     wire burst_counter_dec= | vc_burst_counter_dec;
     wire fifo_wr = | vc_fifo_wr; 
     wire fifo_rd = | vc_fifo_rd;
-    
-    
-    
-   
-    
     wire last_burst = (burst_counter == 1);
     wire burst_is_set =  (burst_size>0);    
     wire [Cw-1   :   0] received_class_next;
@@ -310,23 +264,16 @@ module  ni_master
     reg [BEw-1 : 0] receive_vc_be [V-1 : 0];
     wire [CTRL_FLGw-1 : 0] vc_ctrl_flags [V-1 : 0];
     reg [V-1    :   0] crc_miss_match;    
-    
     wire [V-1    :   0] burst_size_err,send_data_size_err,rcive_buff_ovrflw_err;
     wire [V-1    :   0] invalid_send_req_err;           
-     
     wire [V-1 : 0] vc_irq;
-   
-  
-            
-    wire  [STATUS1w-1  :0] status1;
-   // wire  [STATUS2w-1  :0] status2; 
-  //  wire  [STATUS3w-1  :0] status3;
     
- 
+    wire  [STATUS1w-1  :0] status1;
+    // wire  [STATUS2w-1  :0] status2; 
+    // wire  [STATUS3w-1  :0] status3;
     wire [DSTPw-1 : 0] destport;
     wire [WEIGHTw-1 : 0] weight;  
     wire [HDw-1 : 0 ] hdr_data; 
-   
     wire [V-1 :0] vc_any_err_isr        ;
     wire [V-1 :0] vc_got_packet_isr     ;
     wire [V-1 :0] vc_packet_is_saved_isr; 
@@ -338,22 +285,17 @@ module  ni_master
     assign any_got_packet_isr = |  vc_got_packet_isr      ;
     assign any_packet_is_saved_isr = |  vc_packet_is_saved_isr;
     assign any_packet_is_sent_isr  = |  vc_packet_is_sent_isr;
-  //  assign status1= {vc_got_error_isr, receive_vc_got_packet_isr, receive_vc_packet_is_saved_isr, send_vc_packet_is_sent_isr};    
- //   assign status2= {vc_got_error_int_en, receive_vc_got_packet_int_en, receive_vc_packet_is_saved_int_en, send_vc_packet_is_sent_int_en};
+    //  assign status1= {vc_got_error_isr, receive_vc_got_packet_isr, receive_vc_packet_is_saved_isr, send_vc_packet_is_sent_isr};    
+    //  assign status2= {vc_got_error_int_en, receive_vc_got_packet_int_en, receive_vc_packet_is_saved_int_en, send_vc_packet_is_sent_int_en};
     assign status1= {send_vc_enable_binary, receive_vc_enable_binary, any_err_isr,any_got_packet_isr,any_packet_is_saved_isr,any_packet_is_sent_isr};
-      
-    
     assign  irq =|vc_irq;
-    
     wire [7: 0] temp;
     generate
     if (HDw >= 8) assign temp = rsv_hdr_dat [vc_addr][7:0];
     else assign temp = {{(8-HDw){1'b0}},rsv_hdr_dat [vc_addr]};
     endgenerate
-                                
-                   
-    //read wb registers                
-    always @(*)begin 
+    //read wb registers
+    always_comb begin 
         s_dat_o ={Dw{1'b0}};
         case(vc_s_addr_i)
         GENERAL_REGS_WB_ADDR:begin // This is a general address. check the general address filed
@@ -365,17 +307,15 @@ module  ni_master
                 s_dat_o = {{(Dw-BURST_SIZE_w){1'b0}}, burst_size};  
             end 
             default: begin 
-            	s_dat_o ={Dw{1'b0}};
+                s_dat_o ={Dw{1'b0}};
             end
             endcase
         end//0
-                
+        
         CTRL_FLAGS_WB_ADDR: begin 
-             s_dat_o[CTRL_FLGw-1     : 0] = vc_ctrl_flags[vc_addr];           
+            s_dat_o[CTRL_FLGw-1     : 0] = vc_ctrl_flags[vc_addr];           
         end  
-      
         RECEIVE_SRC_WB_ADDR: begin 
-            
             s_dat_o[EAw-1: 0]   =   src_e_addr[vc_addr];   // first&second bytes
             s_dat_o[Cw+15: 16]  =   class_in[vc_addr];  //third byte  
             s_dat_o[31: 24] =       temp;   // 4th byte
@@ -383,102 +323,75 @@ module  ni_master
         
         RECEIVE_DATA_SIZE_WB_ADDR: begin        
             s_dat_o   [MAX_PCK_SIZE_IN_BYTE-1    :   0] = receive_dat_size_in_byte[vc_addr];
-        end        
-        
+        end
         RECEIVE_PRECAP_DATA_ADDR: begin 
-        	s_dat_o[PRE_Dw-1 : 0 ] =  (HDATA_PRECAPw>0)? recive_vc_precap_data[vc_addr][PRE_Dw-1 : 0 ]: {{PRE_Dw{1'b0}}};        
+            s_dat_o[PRE_Dw-1 : 0 ] =  (HDATA_PRECAPw>0)? recive_vc_precap_data[vc_addr][PRE_Dw-1 : 0 ]: {{PRE_Dw{1'b0}}};        
         end
         default: begin 
-             s_dat_o ={Dw{1'b0}};
-        end       
-        endcase      
-    end      
-     
-   
-   
+            s_dat_o ={Dw{1'b0}};
+        end
+        endcase
+    end
     
     //write wb registers
-    always @ (*)begin 
+    always_comb begin 
         burst_counter_next=burst_counter;
         burst_size_next= burst_size;
         if(burst_counter_ld)    burst_counter_next = burst_size;
         if(burst_counter_dec)   burst_counter_next= burst_counter- 1'b1;
-         
         if((s_stb_i  &    s_we_i) && (vc_s_addr_i == GENERAL_REGS_WB_ADDR)) begin // This is a general address. check the general address filed
             case(genrl_reg_addr)
             BURST_SIZE_WB_ADDR: begin 
                 if (send_vc_is_busy == {V{1'b0}}) burst_size_next=s_dat_i [BURST_SIZE_w-1 : 0];    
             end //BURST_SIZE_WB_ADDR
-                                 
-		    default begin
-
-		    end                   
+            default begin
+            
+            end
             endcase
-        end//  if(s_stb_i  &    s_we_i)   
-           
+        end//  if(s_stb_i  &    s_we_i)
     end 
-    
-   
-    
-    
-`ifdef SYNC_RESET_MODE 
+    `ifdef SYNC_RESET_MODE 
     always @ (posedge clk )begin 
-`else 
+    `else 
     always @ (posedge clk or posedge reset)begin 
-`endif 
-    
-    
-   
+    `endif 
         if(reset) begin 
             burst_counter <= {BURST_SIZE_w{1'b0}};
             burst_size <= {BURST_SIZE_w{1'b1}};
             s_ack_o <= 1'b0;  
-           
-	   
         end else begin 
             burst_counter<= burst_counter_next; 
             burst_size <= burst_size_next; 
             s_ack_o <= s_ack_o_next;  
-            
-	    
         end 
     end 
     
-   
     bin_to_one_hot #(
         .BIN_WIDTH(CHw),
         .ONE_HOT_WIDTH(V)
-   )
-   convert
-   (
+    ) convert  (
         .bin_code(vc_addr),
         .one_hot_code(vc_state_reg_enable)
-   );
-   
-    assign s_ack_o_next    =   s_stb_i & (~s_ack_o);
+    );
     
+    assign s_ack_o_next    =   s_stb_i & (~s_ack_o);
     
     genvar i;
     generate
     
-     wire [V-1 : 0 ] precap_hdr_flit_wr;
-     wire [HDATA_PRECAPw-1 : 0 ] precap_din;
-     wire [V-1 : 0] precap_hdr_flit_rd = (fifo_rd & received_flit_is_hdr) ?  receive_vc_enable : {V{1'b0}};
-     wire [HDATA_PRECAPw-1 : 0 ] precap_dout  [V-1 : 0] ;    
-     wire [V-1 : 0 ] precap_valid;
+    wire [V-1 : 0 ] precap_hdr_flit_wr;
+    wire [HDATA_PRECAPw-1 : 0 ] precap_din;
+    wire [V-1 : 0] precap_hdr_flit_rd = (fifo_rd & received_flit_is_hdr) ?  receive_vc_enable : {V{1'b0}};
+    wire [HDATA_PRECAPw-1 : 0 ] precap_dout  [V-1 : 0] ;    
+    fifo_stat_t precap_fifo_stat [V-1 : 0];
+    wire [V-1 : 0 ] precap_valid;
     
-        
     //capture data before saving the actual flit in memory
-    if(HDATA_PRECAPw > 0 ) begin : precap      
-      
+    if(HDATA_PRECAPw > 0 ) begin : precap
         wire [EAw-1 : 0] src_endp_addr;
-        
         extract_header_flit_info #(
-            .NOC_ID(NOC_ID),
-            .DATA_w(HDATA_PRECAPw)           
-        )
-        data_extractor
-        (
+            .DATA_w(HDATA_PRECAPw)
+        )  data_extractor   (
             .flit_in(flit_in),
             .flit_in_wr(flit_in_wr),
             .src_e_addr_o(src_endp_addr ),
@@ -493,90 +406,54 @@ module  ni_master
             .hdr_flit_wr_o(precap_hdr_flit_wr),
             .data_o(precap_din)
         ); 
-        
-        
-//synthesis translate_off
-//synopsys  translate_off    
-`ifdef MONITOR_HDR_FLITS 
-always @(posedge clk) begin
-    
-    if(precap_hdr_flit_wr)begin 
-        $display("%t: endp %d got a packet with port address %d from endp %d",$time,current_e_addr,precap_din,src_endp_addr);
-    end
-    
-    if(send_hdr & flit_out_wr)begin 
-        $display("%t: endp %d sends a packet with port address %d to endp %d",$time,current_e_addr,hdr_data,dest_e_addr);
-    end
-    
-    
-end
-`endif
+        `ifdef SIMULATION
+        `ifdef MONITOR_HDR_FLITS 
+        always @(posedge clk) begin
+            if(precap_hdr_flit_wr)begin 
+                $display("%t: endp %d got a packet with port address %d from endp %d",$time,current_e_addr,precap_din,src_endp_addr);
+            end
 
-`ifdef MONITOR_DAT_FLITS 
-    always @(posedge clk) begin
-        if(flit_out_wr & ~send_hdr) begin 
-            $display("%t: endp %u V %u sends %h",$time,current_e_addr,  flit_out [Fpay+V-1 : Fpay],  flit_out [Fpay-1 : 0 ]);    
+            if(send_hdr & flit_out_wr)begin 
+                $display("%t: endp %d sends a packet with port address %d to endp %d",$time,current_e_addr,hdr_data,dest_e_addr);
+            end
         end
-    end
-`endif
-
-//synopsys  translate_on 
-//synthesis translate_on
-        
-        
-        
-       for (i=0;i<V; i=i+1) begin : vc__          
-          
-          fwft_fifo #(
-            .DATA_WIDTH(HDATA_PRECAPw),
-            .MAX_DEPTH(LB/MIN_PCK_SIZE),//maximum packet number which can be stored in buffer 
-            .IGNORE_SAME_LOC_RD_WR_WARNING("YES")
-          )
-          precap_data_fifo
-          (
-            .din(precap_din),
-            .wr_en(precap_hdr_flit_wr[i]),
-            .rd_en(precap_hdr_flit_rd[i]),
-            .dout(precap_dout[i]),
-            .full( ),
-            .nearly_full( ),
-            .recieve_more_than_0(precap_valid[i] ),
-            .recieve_more_than_1( ),
-            .reset(reset),
-            .clk(clk)
-          );
-      
-          assign recive_vc_precap_data[i] = precap_dout[i]; 
-      
-        //synthesis translate_off
-        //synopsys  translate_off  
-        always @(posedge clk)begin 
-             if(s_stb_i  &  ~s_we_i &  (vc_addr==i) & (vc_s_addr_i == RECEIVE_PRECAP_DATA_ADDR) )begin
-                    if( precap_valid[i] == 1'b0) $display( "Warning: Reading invalid precap-data %m");    
-             end           
-        end     
-        //synopsys  translate_on   
-        //synthesis translate_on 
-     
-      
+        `endif
+        `ifdef MONITOR_DAT_FLITS 
+            always @(posedge clk) begin
+                if(flit_out_wr & ~send_hdr) begin 
+                    $display("%t: endp %u V %u sends %h",$time,current_e_addr,  flit_out [Fpay+V-1 : Fpay],  flit_out [Fpay-1 : 0 ]);    
+                end
+            end
+        `endif
+        `endif
+        for (i=0;i<V; i=i+1) begin : vc__
+            fwft_fifo #(
+                .DATA_WIDTH(HDATA_PRECAPw),
+                .MAX_DEPTH(LB/MIN_PCK_SIZE),//maximum packet number which can be stored in buffer 
+                .IGNORE_SAME_LOC_RD_WR_WARNING(1) //"YES"
+            )  precap_data_fifo  (
+                .din(precap_din),
+                .wr_en(precap_hdr_flit_wr[i]),
+                .rd_en(precap_hdr_flit_rd[i]),
+                .dout(precap_dout[i]),
+                .status_o(precap_fifo_stat[i]),
+                .reset(reset),
+                .clk(clk)
+            );
+            assign recive_vc_precap_data[i] = precap_dout[i]; 
+            `ifdef SIMULATION  
+            always @(posedge clk)begin 
+                if(s_stb_i  &  ~s_we_i &  (vc_addr==i) & (vc_s_addr_i == RECEIVE_PRECAP_DATA_ADDR) )begin
+                    if( precap_fifo_stat[i].empty) $display( "Warning: Reading invalid precap-data %m");    
+                end
+            end
+            `endif
         end
-           
-    end    
-    
-      
-    
+    end
     assign chan_out.ctrl_chanel.endp_port =1'b1;
     
-    
-    
     for (i=0;i<V; i=i+1) begin : vc_    
-    
-    	
-		assign chan_out.ctrl_chanel.credit_init_val[i]= LB;
-    
-       
-       
-       
+        assign chan_out.ctrl_chanel.credit_init_val[i]= LB;
         ni_vc_wb_slave_regs #(
             .MAX_TRANSACTION_WIDTH(MAX_TRANSACTION_WIDTH),
             .DEBUG_EN(DEBUG_EN),
@@ -590,15 +467,10 @@ end
             .S_Aw(chanel_REGw),
             .WEIGHTw(WEIGHTw),
             .BYTE_EN(BYTE_EN)
-            
-        )        
-        wb_slave_registers
-        (
-//synthesis translate_off
-//synopsys  translate_off    
+        )  wb_slave_registers (
+            `ifdef SIMULATION
             .current_e_addr(current_e_addr),
-//synopsys  translate_on   
-//synthesis translate_on
+            `endif
             .clk(clk),
             .reset(reset),
             .state_reg_enable(vc_state_reg_enable[i]),
@@ -611,7 +483,6 @@ end
             .receive_start_index_offset(receive_vc_start_index_offset[i]),
             .receive_done(receive_vc_done[i]),
             .send_done(send_vc_done[i]),
-           
             .send_data_size(send_vc_data_size[i]),
             .receive_max_buff_siz(receive_vc_max_buff_siz[i]),
             .dest_e_addr(vc_dest_e_addr[i]),
@@ -621,34 +492,26 @@ end
             .send_start(send_vc_start[i]),
             .receive_start(receive_vc_start[i]),
             .receive_vc_got_packet(receive_vc_got_packet[i]),
-                   
-	        .burst_size_err(burst_size_err[i]),
+            .burst_size_err(burst_size_err[i]),
             .send_data_size_err(send_data_size_err[i]),
             .rcive_buff_ovrflw_err(rcive_buff_ovrflw_err[i]),
-	        .crc_miss_match_err( crc_miss_match[i]),
-	        .invalid_send_req_err(invalid_send_req_err[i]),  
-	        
-	        .receive_vc_got_hdr_flit_at_head(receive_vc_got_hdr_flit_at_head[i]),
-	        .receive_is_busy(receive_vc_is_busy[i]),
-	        .send_is_busy(send_vc_is_busy[i]),	        
-	        .ctrl_flags(vc_ctrl_flags[i]),
-	                                                         
-	        .any_err_isr          (vc_any_err_isr        [i]),
-	        .got_packet_isr       (vc_got_packet_isr     [i]),
-	        .packet_is_saved_isr  (vc_packet_is_saved_isr[i]),
-	        .packet_is_sent_isr   (vc_packet_is_sent_isr [i]),
-	        
-	        
-	        .irq(vc_irq[i]),
-	        
-	        .s_dat_i(s_dat_i),
+            .crc_miss_match_err( crc_miss_match[i]),
+            .invalid_send_req_err(invalid_send_req_err[i]),  
+            .receive_vc_got_hdr_flit_at_head(receive_vc_got_hdr_flit_at_head[i]),
+            .receive_is_busy(receive_vc_is_busy[i]),
+            .send_is_busy(send_vc_is_busy[i]),            
+            .ctrl_flags(vc_ctrl_flags[i]),
+            .any_err_isr          (vc_any_err_isr        [i]),
+            .got_packet_isr       (vc_got_packet_isr     [i]),
+            .packet_is_saved_isr  (vc_packet_is_saved_isr[i]),
+            .packet_is_sent_isr   (vc_packet_is_sent_isr [i]),
+            .irq(vc_irq[i]),
+            .s_dat_i(s_dat_i),
             .s_addr_i(s_addr_i[chanel_REGw-1:0]),
             .s_stb_i(s_stb_i),
             .s_cyc_i(s_cyc_i),
             .s_we_i(s_we_i)
         );   
-    
-    
         ni_vc_dma #(
             .CRC_EN(CRC_EN),
             .MAX_TRANSACTION_WIDTH(MAX_TRANSACTION_WIDTH),
@@ -658,9 +521,7 @@ end
             .SELw(SELw),
             .Fpay(Fpay),
             .BYTE_EN(BYTE_EN)
-        )
-        vc_dma
-        (
+        )   vc_dma   (
             .reset(reset),
             .clk(clk),
             .status(),            
@@ -700,7 +561,6 @@ end
             .send_fifo_rd(credit_in[i]),
             .receive_fifo_empty(vc_fifo_empty[i]),
             .receive_fifo_rd(vc_fifo_rd[i]),          
-         
             //errors
             .burst_size_err(burst_size_err[i]),
             .send_data_size_err(send_data_size_err[i]),
@@ -713,11 +573,10 @@ end
             .m_send_stb_o(vc_m_send_stb_o[i]),
             .m_send_cyc_o(vc_m_send_cyc_o[i]),
             .m_send_we_o(vc_m_send_we_o[i]),
-        //  .m_send_dat_i(m_send_dat_i),
+            //.m_send_dat_i(m_send_dat_i),
             .m_send_ack_i(m_send_ack_i),           
-            
             .m_receive_sel_o(vc_m_receive_sel_o[i]),
-        //  .m_receive_dat_o(vc_m_receive_dat_o[i]),
+            //  .m_receive_dat_o(vc_m_receive_dat_o[i]),
             .m_receive_addr_o(vc_m_receive_addr_o[i]),
             .m_receive_cti_o(vc_m_receive_cti_o[i]),
             .m_receive_stb_o(vc_m_receive_stb_o[i]),
@@ -725,13 +584,12 @@ end
             .m_receive_we_o(vc_m_receive_we_o[i]),
             .m_receive_ack_i(m_receive_ack_i)
         );
-     
-`ifdef SYNC_RESET_MODE 
-    always @ (posedge clk )begin 
-`else 
-    always @ (posedge clk or posedge reset)begin 
-`endif         
-             
+        `ifdef SYNC_RESET_MODE 
+        always @ (posedge clk )
+        `else 
+        always @ (posedge clk or posedge reset)
+        `endif 
+            begin
             if(reset) begin 
                 class_in[i]<= {Cw{1'b0}};
                 src_e_addr[i]<= {EAw{1'b0}};
@@ -744,32 +602,25 @@ end
                 receive_vc_be[i]<= received_be_next;
             end
         end//always
-   
     end  // for loop vc_
-    
-/* verilator lint_off WIDTH */ 
+    /* verilator lint_off WIDTH */ 
     if(  CRC_EN == "YES") begin :crc_blk
-/* verilator lint_on WIDTH */
-   
-      reg fifo_rd_delayed;
-`ifdef SYNC_RESET_MODE 
+    /* verilator lint_on WIDTH */
+    reg fifo_rd_delayed;
+    `ifdef SYNC_RESET_MODE 
     always @ (posedge clk )begin 
-`else 
+    `else 
     always @ (posedge clk or posedge reset)begin 
-`endif   
+    `endif   
         if(reset) fifo_rd_delayed <=1'b0;
         else fifo_rd_delayed <= fifo_rd;
-      end
-  
-      wire send_crc_enable =  flit_out_wr & ~send_hdr &   ~send_tail;
-      wire receive_crc_enable =  fifo_rd_delayed & ~ received_flit_is_tail & ~received_flit_is_hdr;
-      wire [31:0]  send_crc_out,receive_crc_out;
-                                        
+    end
+    wire send_crc_enable =  flit_out_wr & ~send_hdr &   ~send_tail;
+    wire receive_crc_enable =  fifo_rd_delayed & ~ received_flit_is_tail & ~received_flit_is_hdr;
+    wire [31:0]  send_crc_out,receive_crc_out;
         crc_32_multi_chanel #(
             .chanel(V)
-        )
-        send_crc
-        (
+        )  send_crc  (
             .reset(reset),
             .clk(clk),
             .crc_reset(send_hdr),
@@ -780,27 +631,24 @@ end
         );        
         
         crc_32_multi_chanel #(
-        	.chanel(V)
-        )
-         receive_crc
-         (
-        	.reset(reset),
-        	.clk(clk),
-        	.crc_reset(received_flit_is_hdr),
-        	.crc_enable(receive_crc_enable),
-        	.chanel_in(receive_vc_enable_binary),
-        	.data_in(m_receive_dat_o[Fpay-1 : 0]),
-        	.crc_out(receive_crc_out)
+            .chanel(V)
+        ) receive_crc (
+            .reset(reset),
+            .clk(clk),
+            .crc_reset(received_flit_is_hdr),
+            .crc_enable(receive_crc_enable),
+            .chanel_in(receive_vc_enable_binary),
+            .data_in(m_receive_dat_o[Fpay-1 : 0]),
+            .crc_out(receive_crc_out)
         );
         
         for (i=0;i<V;i=i+1) begin: crc_v
         
-`ifdef SYNC_RESET_MODE 
+    `ifdef SYNC_RESET_MODE 
             always @ (posedge clk )begin 
-`else 
+    `else 
             always @ (posedge clk or posedge reset)begin 
-`endif 
-                  
+    `endif 
                 if(reset) begin 
                     crc_miss_match[i] <= 1'b0;
                 end else begin 
@@ -808,101 +656,73 @@ end
                         crc_miss_match[i] <= receive_crc_out[31:0] != m_receive_dat_o[31 : 0];
                     end                
                 end
-            
             end
         end//for
-        
         assign tail_flit_out[31 : 0]  =  send_crc_out;
     end   else begin : no_crc 
         assign tail_flit_out   =  m_send_dat_i [Fpay-1 : 0];
-        //always @(*) crc_miss_match = {V{1'b0}};
-	always @(posedge clk) crc_miss_match <= {V{1'b0}};
+        //always_comb crc_miss_match = {V{1'b0}};
+    always @(posedge clk) crc_miss_match <= {V{1'b0}};
     end
-      
-  
+
     if(V> 1) begin : multi_chanel
-    
         // round roubin arbiter
         bus_arbiter # (
             .M (V)
-        )
-        receive_arbiter
-        (
+        )  receive_arbiter  (
             .request (receive_vc_is_active),
             .grant  (receive_vc_enable),
             .clk (clk),
             .reset (reset)
         );
-                
+        
         bus_arbiter # (
             .M (V)
-        )
-        send_arbiter
-        (
+        )   send_arbiter   (
             .request (send_vc_is_active),
             .grant  (send_vc_enable),
             .clk (clk),
             .reset (reset)
         );
         
-        
         one_hot_to_bin #(
             .ONE_HOT_WIDTH(V),
             .BIN_WIDTH(CHw)
-        )
-        send_en_conv
-        (
+        )  send_en_conv  (
             .one_hot_code(send_vc_enable),
             .bin_code(send_vc_enable_binary)
         );
-        
-        
-         one_hot_to_bin #(
+        one_hot_to_bin #(
             .ONE_HOT_WIDTH(V),
             .BIN_WIDTH(CHw)
-        )
-        receive_en_conv
-        (
+        )  receive_en_conv   (
             .one_hot_code(receive_vc_enable),
             .bin_code(receive_vc_enable_binary)
         );
-        
-        
+    
     end else begin : single_chanel // if we have just one chanel there is no need for arbitration
         assign receive_vc_enable =  receive_vc_is_active;
         assign send_vc_enable =  send_vc_is_active;
         assign send_vc_enable_binary = 1'b0;
         assign receive_vc_enable_binary = 1'b0;
     end
-    endgenerate  
-  
-   
-  
-    conventional_routing #(
-        .NOC_ID(NOC_ID),
-        .TOPOLOGY(TOPOLOGY),
-        .ROUTE_NAME(ROUTE_NAME),
-        .ROUTE_TYPE(ROUTE_TYPE),  
-        .T1(T1),
-        .T2(T2),
-        .T3(T3),
-        .RAw(RAw),
-        .EAw(EAw),
-        .DSTPw(DSTPw),
-        .LOCATED_IN_NI(1)
-    ) route_compute (
-        .reset(reset),
-        .clk(clk),
-        .current_r_addr(current_r_addr),
-        .src_e_addr(current_e_addr),
-        .dest_e_addr(dest_e_addr),
-        .destport(destport)
-    );
-  
-        
+    if((CAST_TYPE == "UNICAST") && (IS_LOOKAHEAD==1'b1)) begin : uni
+    //The router is configured with lookaheadrouting. 
+    //The header flit is supposed to carry the destinaion output port
+        conventional_routing #(
+            .LOCATED_IN_NI(1)
+        ) route_compute (
+            .reset(reset),
+            .clk(clk),
+            .current_r_addr(current_r_addr),
+            .src_e_addr(current_e_addr),
+            .dest_e_addr(dest_e_addr),
+            .destport(destport)
+        );
+    end
+    endgenerate
     header_flit_generator #(
-        .NOC_ID(NOC_ID),
-        .DATA_w(HDw)       
+        .DATA_w(HDw)
     ) hdr_flit_gen (
         .flit_out(hdr_flit_out),
         .class_in(pck_class),
@@ -912,30 +732,27 @@ end
         .vc_num_in(send_vc_enable),
         .weight_in(weight),
         .be_in(be_in),
-        .data_in(hdr_data)        
+        .data_in(hdr_data)
     );
     
-  wire [V-1    :   0] wr_vc_send =  (fifo_wr) ? send_vc_enable : {V{1'b0}};  
-  
-  
-  ovc_status #(
-    .V(V),
-    .B(LB),
-    .CRDTw(CRDTw)    
-  )
-  the_ovc_status
-  (
-    .credit_init_val_in ( chan_in.ctrl_chanel.credit_init_val),
-  	.wr_in(wr_vc_send),
-    .credit_in(credit_in),
-    .full_vc(vc_fifo_full),
-    .nearly_full_vc(vc_fifo_nearly_full),
-    .empty_vc( ),
-    .clk(clk),
-    .reset(reset)
-  );   
+    wire [V-1 : 0] wr_vc_send =  (fifo_wr) ? send_vc_enable : {V{1'b0}};
     
-    // header info mux    
+    ovc_status #(
+        .V(V),
+        .B(LB),
+        .CRDTw(CRDTw)
+    ) the_ovc_status (
+        .credit_init_val_in ( chan_in.ctrl_chanel.credit_init_val),
+        .wr_in(wr_vc_send),
+        .credit_in(credit_in),
+        .full_vc(vc_fifo_full),
+        .nearly_full_vc(vc_fifo_nearly_full),
+        .empty_vc( ),
+        .clk(clk),
+        .reset(reset)
+    );
+    
+    // header info mux
     assign dest_e_addr = vc_dest_e_addr[send_vc_enable_binary];
     assign pck_class  = vc_pck_class[send_vc_enable_binary];
     assign weight =   vc_weight[send_vc_enable_binary];  
@@ -944,49 +761,37 @@ end
     assign send_tail = send_vc_send_tail[send_vc_enable_binary]; 
     assign be_in = vc_be_in[send_vc_enable_binary];
     
-    //wb multiplexors    
+    //wb multiplexors
     assign m_send_sel_o  = vc_m_send_sel_o[send_vc_enable_binary];
     assign m_send_addr_o = vc_m_send_addr_o[send_vc_enable_binary];
     assign m_send_cti_o  = vc_m_send_cti_o[send_vc_enable_binary];
     assign m_send_stb_o  = vc_m_send_stb_o[send_vc_enable_binary];
     assign m_send_cyc_o  = vc_m_send_cyc_o[send_vc_enable_binary];
-    assign m_send_we_o   = vc_m_send_we_o[send_vc_enable_binary];       
-                        
+    assign m_send_we_o   = vc_m_send_we_o[send_vc_enable_binary];
+    
     assign m_receive_sel_o = vc_m_receive_sel_o[receive_vc_enable_binary];
     assign m_receive_addr_o= vc_m_receive_addr_o[receive_vc_enable_binary];
     assign m_receive_cti_o = vc_m_receive_cti_o[receive_vc_enable_binary];
     assign m_receive_stb_o = vc_m_receive_stb_o[receive_vc_enable_binary];
     assign m_receive_cyc_o = vc_m_receive_cyc_o[receive_vc_enable_binary];
     assign m_receive_we_o  = vc_m_receive_we_o[receive_vc_enable_binary];    
-          
+
     wire [V-1    :   0]  flit_in_vc_num = flit_in [Fpay+V-1    :   Fpay]; 
     wire [V-1    :   0]  ififo_vc_not_empty; 
     assign vc_fifo_empty = ~ ififo_vc_not_empty;
     assign receive_vc_got_packet = ififo_vc_not_empty;
     assign receive_vc_got_hdr_flit_at_head=  ififo_vc_not_empty & receive_vc_fsm_is_ideal;
-        
-    
-    
     
     wire [Fw-1  :   0] fifo_dout;
-    
     localparam LBw = log2(LB);
-    
     flit_buffer #(
         .V(V),
-        .B(LB),
-        .SSA_EN("NO"),
-        .Fw(Fw),
-		.PCK_TYPE(PCK_TYPE),
-		.CAST_TYPE(CAST_TYPE),
-		.DEBUG_EN(DEBUG_EN)
-     )
-     the_ififo
-     (
-        .din(flit_in),     // Data in
-        .vc_num_wr(flit_in_vc_num),//write virtual chanel    
+        .B(LB)
+    ) the_ififo  (
+        .din(flit_in), // Data in
+        .vc_num_wr(flit_in_vc_num),//write virtual chanel
         .wr_en(flit_in_wr),   // Write enable
-        .vc_num_rd(receive_vc_enable),//read virtual chanel     
+        .vc_num_rd(receive_vc_enable),//read virtual chanel
         .rd_en(fifo_rd),   // Read the next word
         .dout(fifo_dout),    // Data out
         .vc_not_empty(ififo_vc_not_empty),
@@ -994,15 +799,12 @@ end
         .clk(clk),
         .ssa_rd({V{1'b0}}),
         .multiple_dest(),
-        .sub_rd_ptr_ld()  
+        .sub_rd_ptr_ld()
     ); 
     
-   extract_header_flit_info #(
-        .NOC_ID(NOC_ID),
-        .DATA_w (HDw)      
-    )
-    extractor
-    (
+    extract_header_flit_info #(
+        .DATA_w (HDw)
+    )  extractor (
         .flit_in(fifo_dout),
         .flit_in_wr(),
         .class_o(received_class_next),
@@ -1017,43 +819,36 @@ end
         .be_o(received_be_next),
         .data_o(received_hdr_dat_next)
     );  
-  
-  
- 
-  assign m_receive_dat_o = fifo_dout[Dw-1   :   0];
-  assign received_flit_is_tail = fifo_dout[Fw-2];
-  assign received_flit_is_hdr  = fifo_dout[Fw-1];  
-//  assign any_vc_got_pck = |receive_vc_got_packet;
-
+    assign m_receive_dat_o = fifo_dout[Dw-1   :   0];
+    assign received_flit_is_tail = fifo_dout[Fw-2];
+    assign received_flit_is_hdr  = fifo_dout[Fw-1];  
+    //  assign any_vc_got_pck = |receive_vc_got_packet;
     localparam [1:0] 
-        HDR_FLAG           =   2'b10,
-        BDY_FLAG            =   2'b00,
-        TAIL_FLAG          =   2'b01;
- 
-  assign credit_out = vc_fifo_rd;
-  assign flit_out_wr= fifo_wr;  
-  assign flit_out [Fpay+V-1 : Fpay] = send_vc_enable;    
-  assign flit_out [Fpay-1   : 0   ] = (send_hdr)?  hdr_flit_out [Fpay-1 : 0] :
-                                      (send_tail)? tail_flit_out :  m_send_dat_i [Fpay-1 : 0];
-  assign flit_out [Fw-1 : Fw-2] =   (send_hdr)?  HDR_FLAG : 
-                                    (send_tail)?  TAIL_FLAG    : BDY_FLAG;                                       
+        HDR_FLAG =   2'b10,
+        BDY_FLAG =   2'b00,
+        TAIL_FLAG =   2'b01;
+    assign credit_out = vc_fifo_rd;
+    assign flit_out_wr= fifo_wr;  
+    assign flit_out [Fpay+V-1 : Fpay] = send_vc_enable;    
+    assign flit_out [Fpay-1   : 0   ] = 
+        (send_hdr)?  hdr_flit_out [Fpay-1 : 0] :
+        (send_tail)? tail_flit_out :  m_send_dat_i [Fpay-1 : 0];
+    assign flit_out [Fw-1 : Fw-2] =
+        (send_hdr)?  HDR_FLAG : 
+        (send_tail)?  TAIL_FLAG : BDY_FLAG;
 endmodule
- 
- 
-  
+    
 /******************
 *   ovc_status
 *******************/
- 
- module ovc_status #(
+    
+module ovc_status #(
     parameter V     =   4,
     parameter B =   16,
     parameter CRDTw =4
-)
-(
-   
-	input   [V-1 : 0] [CRDTw-1 : 0 ] credit_init_val_in,
-	input   [V-1            :0] wr_in,
+)(
+    input   [V-1 : 0] [CRDTw-1 : 0 ] credit_init_val_in,
+    input   [V-1            :0] wr_in,
     input   [V-1            :0] credit_in,
     output  [V-1            :0] full_vc,
     output  [V-1            :0] nearly_full_vc,
@@ -1062,45 +857,35 @@ endmodule
     input                       reset
 );
 
- 
-	 function integer log2;
-	 input integer number; begin   
-	 	log2=(number <=1) ? 1: 0;    
-	 	while(2**log2<number) begin    
-	 		log2=log2+1;    
-	 	end 	   
-	 end   
-	 endfunction // log2 
-    
-  
- 	localparam  DEPTH_WIDTH =   log2(B+1);
- 
-    
-	 reg  [DEPTH_WIDTH-1 : 0] credit    [V-1 : 0];
-	 wire  [V-1 : 0] cand_vc_next;
-	
-    
-	 genvar i;
-	 generate
-	 	for(i=0;i<V;i=i+1) begin : vc_loop
-	 	`ifdef SYNC_RESET_MODE 
-	 		always @ (posedge clk )begin 
-	 	`else 
-	 		always @ (posedge clk or posedge reset)begin 
-	 	`endif  
-	 	if(reset)begin
-	 	credit[i]<= credit_init_val_in[i][DEPTH_WIDTH-1:0];
-	    end else begin
-	    	if(  wr_in[i]  && ~credit_in[i])   credit[i] <= credit[i]-1'b1;
-	    	if( ~wr_in[i]  &&  credit_in[i])   credit[i] <= credit[i]+1'b1;
-	    end //reset
-	    end//always
-
-	    assign  full_vc[i]   = (credit[i] == {DEPTH_WIDTH{1'b0}});
-	    assign  nearly_full_vc[i]=  (credit[i] == 1) |  full_vc[i];
-	    assign  empty_vc[i]  = (credit[i] == credit_init_val_in[i][DEPTH_WIDTH-1:0]);
-      end//for
+    function integer log2;
+    input integer number; begin   
+        log2=(number <=1) ? 1: 0;    
+        while(2**log2<number) begin    
+            log2=log2+1;    
+        end        
+    end   
+    endfunction // log2 
+    localparam  DEPTH_WIDTH =   log2(B+1);
+    reg  [DEPTH_WIDTH-1 : 0] credit    [V-1 : 0];
+    wire  [V-1 : 0] cand_vc_next;
+    genvar i;
+    generate
+        for(i=0;i<V;i=i+1) begin : vc_loop
+        `ifdef SYNC_RESET_MODE 
+            always @ (posedge clk )begin 
+        `else 
+            always @ (posedge clk or posedge reset)begin 
+        `endif  
+        if(reset)begin
+        credit[i]<= credit_init_val_in[i][DEPTH_WIDTH-1:0];
+        end else begin
+            if(  wr_in[i]  && ~credit_in[i])   credit[i] <= credit[i]-1'b1;
+            if( ~wr_in[i]  &&  credit_in[i])   credit[i] <= credit[i]+1'b1;
+        end //reset
+        end//always
+        assign  full_vc[i]   = (credit[i] == {DEPTH_WIDTH{1'b0}});
+        assign  nearly_full_vc[i]=  (credit[i] == 1) |  full_vc[i];
+        assign  empty_vc[i]  = (credit[i] == credit_init_val_in[i][DEPTH_WIDTH-1:0]);
+    end//for
     endgenerate
-endmodule
- 
- 
+endmodule
\ No newline at end of file
diff --git a/mpsoc/rtl/src_peripheral/ni/ni_slave.v b/mpsoc/rtl/src_peripheral/ni/ni_slave.v
index c13b0b3..6cab0b2 100644
--- a/mpsoc/rtl/src_peripheral/ni/ni_slave.v
+++ b/mpsoc/rtl/src_peripheral/ni/ni_slave.v
@@ -45,7 +45,7 @@ module  ni_slave #(
     parameter DST_ADR_HDR_WIDTH  =8,
     parameter SRC_ADR_HDR_WIDTH   =8,
     parameter TOPOLOGY =    "MESH",//"MESH","TORUS","RING" 
-    parameter ROUTE_NAME    =   "XY",
+    parameter ROUTE_NAME    =   "DOR",
     parameter NX = 4,   // number of node in x axis
     parameter NY = 4,   // number of node in y axis
     parameter C = 4,    //  number of flit class 
diff --git a/mpsoc/rtl/src_synfull/dpi_int_pkg.sv b/mpsoc/rtl/src_synfull/dpi_int_pkg.sv
index 134740e..2b01bb0 100644
--- a/mpsoc/rtl/src_synfull/dpi_int_pkg.sv
+++ b/mpsoc/rtl/src_synfull/dpi_int_pkg.sv
@@ -1,24 +1,20 @@
 `include "pronoc_def.v"
 
-
-
 package dpi_int_pkg;
 
-parameter NOC_ID=0;
-
-`NOC_CONF
+import pronoc_pkg::*;
 
- typedef struct packed {
-     logic [NEw-1 : 0] dest  ;
-     logic [PCK_SIZw-1 : 0] size  ;
-     logic [NEw-1 : 0] src   ;
-     logic [31:0]      id    ;
-     logic             valid ;
- } req_t;  
+typedef struct packed {
+    logic [NEw-1 : 0] dest;
+    logic [PCK_SIZw-1 : 0] size;
+    logic [NEw-1 : 0] src;
+    logic [31:0] id;
+    logic valid;
+} req_t;
 
- typedef struct packed {
-     logic [31:0]      id    ;
-     logic             valid ;
- } deliver_t;  
+typedef struct packed {
+    logic [31:0] id;
+    logic valid;
+} deliver_t;
 
 endpackage
diff --git a/mpsoc/rtl/src_synfull/dpi_interface.sv b/mpsoc/rtl/src_synfull/dpi_interface.sv
index e6acdee..3931606 100644
--- a/mpsoc/rtl/src_synfull/dpi_interface.sv
+++ b/mpsoc/rtl/src_synfull/dpi_interface.sv
@@ -1,9 +1,7 @@
-
 `include "pronoc_def.v"
 parameter NOC_ID=0;
-`NOC_CONF
-import dpi_int_pkg::*; 
-
+import pronoc_pkg::*;
+import dpi_int_pkg::*;
 module top_dpi_interface (
     input   logic               clk_i, rst_i  ,
     input   logic               init_i                          ,
@@ -13,171 +11,150 @@ module top_dpi_interface (
     output  req_t     [NE-1:0]  synfull_pronoc_req_all_o        ,
     output  logic               endCom_o                             
 );
-
-
-import "DPI-C" function void c_dpi_interface ( 
-    logic          startCom            , 
-    logic          getData             ,
-    logic          ejectReq            , 
-    logic          queueReq            , 
-    output  logic  endCom              , 
-    output  logic  newReq              , 
-    output  int    source_all[NE]      , 
-    output  int    destination_all[NE] , 
-    output  int    address_all[NE]     ,
-    output  int    opcode_all[NE]      ,
-    output  int    id_all[NE]          ,
-    output  int    valid_all[NE]       ,
-    input   int    rtrn_pkgid_all[NE]  ,
-    input   int    rtrn_valid_all[NE]  ,       
-    input   int    NEready_all[NE]     ,                  
-    output  int    size_all[NE]        ,
-    input   int    enqueue_valid[NE]   ,
-    input   int    enqueue_src[NE]     ,
-    input   int    enqueue_dst[NE]     ,
-    input   int    enqueue_id[NE]      ,
-    input   int    enqueue_size[NE]                      
-);
-
-import "DPI-C" function void connection_init( 
-    logic           startCom     , 
-    output logic    ready         
-);
-
-int destination ;
-int opcode      ;
-int source      ;
-int addr        ;
-int pkgid       ;
-int NEready_all[NE]             ;
-int syn_source_all[NE]          ;
-int syn_size_all[NE]            ;
-int syn_opcode_all[NE]          ;
-int syn_destination_all[NE]     ;
-int syn_address_all[NE]         ;
-int syn_pkgid_all[NE]           ;
-int syn_valid_all[NE]           ;
-int chi_req_pkgid_all[NE]       ;
-int chi_req_valid_all[NE]       ;
-
-int enqueue_valid[NE];
-int enqueue_src[NE]  ;
-int enqueue_dst[NE]  ;
-int enqueue_id[NE]   ;
-int enqueue_size[NE] ;
-
-int _enqueue_valid[NE];
-int _enqueue_src[NE]  ;
-int _enqueue_dst[NE]  ;
-int _enqueue_id[NE]   ;
-int _enqueue_size[NE] ;
-
-logic newData             ;
-logic newReq              ;
-logic ready_connection    ;
-logic eject_req           ;
-logic queue_req           ;
-logic endCom              ;
-
-logic [NE-1:0] valid_check ;
-logic [NE-1:0] queue_check ;
-
-// socket connection
-always_ff @(posedge clk_i) begin 
-    connection_init(
-        init_i,ready_connection
+    import "DPI-C" function void c_dpi_interface ( 
+        logic          startCom            , 
+        logic          getData             ,
+        logic          ejectReq            , 
+        logic          queueReq            , 
+        output  logic  endCom              , 
+        output  logic  newReq              , 
+        output  int    source_all[NE]      , 
+        output  int    destination_all[NE] , 
+        output  int    address_all[NE]     ,
+        output  int    opcode_all[NE]      ,
+        output  int    id_all[NE]          ,
+        output  int    valid_all[NE]       ,
+        input   int    rtrn_pkgid_all[NE]  ,
+        input   int    rtrn_valid_all[NE]  ,       
+        input   int    NEready_all[NE]     ,                  
+        output  int    size_all[NE]        ,
+        input   int    enqueue_valid[NE]   ,
+        input   int    enqueue_src[NE]     ,
+        input   int    enqueue_dst[NE]     ,
+        input   int    enqueue_id[NE]      ,
+        input   int    enqueue_size[NE]                      
     );
-end
-
-// trace injection
-always_ff @(posedge clk_i) begin 
-    c_dpi_interface(
-        startCom_i&ready_connection ,
-        clk_i                       ,
-        eject_req                   ,
-        queue_req                   ,
-        endCom_o                    ,
-        newData                     ,
-        syn_source_all              ,
-        syn_destination_all         ,
-        syn_address_all             , 
-        syn_opcode_all              , 
-        syn_pkgid_all               , 
-        syn_valid_all               ,
-        chi_req_pkgid_all           ,  
-        chi_req_valid_all           ,           
-        NEready_all                 ,
-        syn_size_all                ,
-        enqueue_valid               ,
-        enqueue_src                 ,  
-        enqueue_dst                 ,  
-        enqueue_id                  ,   
-        enqueue_size                 
+    
+    import "DPI-C" function void connection_init( 
+        logic           startCom     , 
+        output logic    ready         
     );
-end
-
-genvar k;
-generate     
-for(k=0;k<NE;k=k+1)begin
-    //to pronoc
-    assign synfull_pronoc_req_all_o[k].dest  = syn_destination_all[k];
-    assign synfull_pronoc_req_all_o[k].size  = syn_size_all[k];
-    assign synfull_pronoc_req_all_o[k].src   = syn_source_all[k];
-    assign synfull_pronoc_req_all_o[k].id    = syn_pkgid_all[k];
-    assign synfull_pronoc_req_all_o[k].valid = syn_valid_all[k][0] & NE_ready_all_i[k] ;
-
-    //from pronoc
-    assign chi_req_pkgid_all[k]       = pronoc_synfull_del_all_i[k].id       ;
-    assign chi_req_valid_all[k]       = pronoc_synfull_del_all_i[k].valid    ;
-    assign NEready_all[k]             = NE_ready_all_i[k]                    ;
-
-    assign valid_check[k] = pronoc_synfull_del_all_i[k].valid;
-    assign queue_check[k] = (syn_valid_all[k][0] & !NE_ready_all_i[k]);
-
-
-    //to enqueue
-    assign enqueue_valid[k] = (syn_valid_all[k][0] & !NE_ready_all_i[k]) ? 1 : 0  ;
-    assign enqueue_src[k]   = syn_source_all[k]                         ;
-    assign enqueue_dst[k]   = syn_destination_all[k]                    ;
-    assign enqueue_id[k]    = syn_pkgid_all[k]                          ;
-    assign enqueue_size[k]  = syn_size_all[k]                           ;
-
-     //always @* begin
-     //    if(syn_valid_all[k][0] & !NE_ready_all_i[k]) begin 
-     //        $display ("not injected because the router injector is not ready: %d", syn_pkgid_all[k]);
-     //    end      
-     //end
-end
-endgenerate
-
-assign eject_req = !(valid_check=='0);
-assign queue_req = !(queue_check=='0);
-
-
-always_ff @ (posedge clk_i) begin
-    if (!rst_i) begin
-        _enqueue_valid <= '{default:'0} ;
-        _enqueue_src   <= '{default:'0} ;
-        _enqueue_dst   <= '{default:'0} ;
-        _enqueue_id    <= '{default:'0} ;
-        _enqueue_size  <= '{default:'0} ;
+    
+    int destination ;
+    int opcode      ;
+    int source      ;
+    int addr        ;
+    int pkgid       ;
+    int NEready_all[NE]             ;
+    int syn_source_all[NE]          ;
+    int syn_size_all[NE]            ;
+    int syn_opcode_all[NE]          ;
+    int syn_destination_all[NE]     ;
+    int syn_address_all[NE]         ;
+    int syn_pkgid_all[NE]           ;
+    int syn_valid_all[NE]           ;
+    int chi_req_pkgid_all[NE]       ;
+    int chi_req_valid_all[NE]       ;
+    
+    int enqueue_valid[NE];
+    int enqueue_src[NE]  ;
+    int enqueue_dst[NE]  ;
+    int enqueue_id[NE]   ;
+    int enqueue_size[NE] ;
+    
+    int _enqueue_valid[NE];
+    int _enqueue_src[NE]  ;
+    int _enqueue_dst[NE]  ;
+    int _enqueue_id[NE]   ;
+    int _enqueue_size[NE] ;
+    
+    logic newData             ;
+    logic newReq              ;
+    logic ready_connection    ;
+    logic eject_req           ;
+    logic queue_req           ;
+    logic endCom              ;
+    logic [NE-1:0] valid_check ;
+    logic [NE-1:0] queue_check ;
+    // socket connection
+    always_ff @ (posedge clk_i) begin 
+        connection_init(
+            init_i,ready_connection
+        );
+    end
+    // trace injection
+    always_ff @ (posedge clk_i) begin 
+        c_dpi_interface(
+            startCom_i&ready_connection ,
+            clk_i                       ,
+            eject_req                   ,
+            queue_req                   ,
+            endCom_o                    ,
+            newData                     ,
+            syn_source_all              ,
+            syn_destination_all         ,
+            syn_address_all             , 
+            syn_opcode_all              , 
+            syn_pkgid_all               , 
+            syn_valid_all               ,
+            chi_req_pkgid_all           ,  
+            chi_req_valid_all           ,           
+            NEready_all                 ,
+            syn_size_all                ,
+            enqueue_valid               ,
+            enqueue_src                 ,  
+            enqueue_dst                 ,  
+            enqueue_id                  ,   
+            enqueue_size                 
+        );
+    end
+    genvar k;
+    generate     
+    for(k=0;k<NE;k=k+1)begin
+        //to pronoc
+        assign synfull_pronoc_req_all_o[k].dest  = syn_destination_all[k];
+        assign synfull_pronoc_req_all_o[k].size  = syn_size_all[k];
+        assign synfull_pronoc_req_all_o[k].src   = syn_source_all[k];
+        assign synfull_pronoc_req_all_o[k].id    = syn_pkgid_all[k];
+        assign synfull_pronoc_req_all_o[k].valid = syn_valid_all[k][0] & NE_ready_all_i[k] ;
+        //from pronoc
+        assign chi_req_pkgid_all[k]       = pronoc_synfull_del_all_i[k].id       ;
+        assign chi_req_valid_all[k]       = pronoc_synfull_del_all_i[k].valid    ;
+        assign NEready_all[k]             = NE_ready_all_i[k]                    ;
+        assign valid_check[k] = pronoc_synfull_del_all_i[k].valid;
+        assign queue_check[k] = (syn_valid_all[k][0] & !NE_ready_all_i[k]);
+        //to enqueue
+        assign enqueue_valid[k] = (syn_valid_all[k][0] & !NE_ready_all_i[k]) ? 1 : 0  ;
+        assign enqueue_src[k]   = syn_source_all[k]                         ;
+        assign enqueue_dst[k]   = syn_destination_all[k]                    ;
+        assign enqueue_id[k]    = syn_pkgid_all[k]                          ;
+        assign enqueue_size[k]  = syn_size_all[k]                           ;
+        
+         //always @* begin
+         //    if(syn_valid_all[k][0] & !NE_ready_all_i[k]) begin 
+         //        $display ("not injected because the router injector is not ready: %d", syn_pkgid_all[k]);
+         //    end      
+         //end
     end
-    else begin
-        _enqueue_valid <= enqueue_valid ;
-        _enqueue_src   <= enqueue_src   ;
-        _enqueue_dst   <= enqueue_dst   ;
-        _enqueue_id    <= enqueue_id    ;
-        _enqueue_size  <= enqueue_size  ;
+    endgenerate
+    
+    assign eject_req = !(valid_check=='0);
+    assign queue_req = !(queue_check=='0);
+    
+    always_ff @ (posedge clk_i) begin
+        if (!rst_i) begin
+            _enqueue_valid <= '{default:'0} ;
+            _enqueue_src   <= '{default:'0} ;
+            _enqueue_dst   <= '{default:'0} ;
+            _enqueue_id    <= '{default:'0} ;
+            _enqueue_size  <= '{default:'0} ;
+        end
+        else begin
+            _enqueue_valid <= enqueue_valid ;
+            _enqueue_src   <= enqueue_src   ;
+            _enqueue_dst   <= enqueue_dst   ;
+            _enqueue_id    <= enqueue_id    ;
+            _enqueue_size  <= enqueue_size  ;
+        end
     end
-end
-
-
-
-
-
-
-
-
-
-
-endmodule
+endmodule
\ No newline at end of file
diff --git a/mpsoc/rtl/src_synfull/synfull_top.sv b/mpsoc/rtl/src_synfull/synfull_top.sv
index d3f6613..4d170f9 100755
--- a/mpsoc/rtl/src_synfull/synfull_top.sv
+++ b/mpsoc/rtl/src_synfull/synfull_top.sv
@@ -1,10 +1,8 @@
-// synthesis translate_off
 `include "pronoc_def.v"
 
-
+`ifdef SIMULATION
 module synfull_top;
-    parameter NOC_ID=0;
-    `NOC_CONF
+    import pronoc_pkg::*;
     import dpi_int_pkg::*; 
     
     reg     reset ,clk;
@@ -15,7 +13,6 @@ module synfull_top;
         forever clk = #10 ~clk;
     end 
     
-    
     smartflit_chanel_t chan_in_all  [NE-1 : 0];
     smartflit_chanel_t chan_out_all [NE-1 : 0];
     router_event_t router_event [NR-1 : 0] [MAX_P-1 : 0];
@@ -23,27 +20,24 @@ module synfull_top;
     pck_injct_t pck_injct_in [NE-1 : 0];
     pck_injct_t _pck_injct_in [NE-1 : 0];
     pck_injct_t pck_injct_out[NE-1 : 0];
-
+    
     logic [NE-1 : 0] NE_ready_all    ;
     logic [NE-1 : 0] init_socket     ;
     logic [NE-1 : 0] wakeup_synfull  ;
     logic [NE-1 : 0] end_injection   ;
     logic            end_synfull     ;
-
+    
     req_t     [NE-1 : 0] synfull_pronoc_req_all  ;
     deliver_t [NE-1 : 0] pronoc_synfull_del_all  ;
     
-    noc_top #( 
-		.NOC_ID(NOC_ID)
-	) the_noc (
+    noc_top  the_noc (
         .reset(reset),
-        .clk(clk),    
+        .clk(clk),
         .chan_in_all(chan_in_all),
         .chan_out_all(chan_out_all),
         .router_event(router_event)
     );
-
-
+    
     top_dpi_interface synfull (
         .clk_i(clk), .rst_i(reset),
         .init_i                     (init_socket[0]         ),
@@ -53,11 +47,9 @@ module synfull_top;
         .NE_ready_all_i             (NE_ready_all           ),
         .endCom_o                   (end_injection[0]       )  
     );
-
-        
+    
     reg [NEw-1 : 0] dest_id [NE-1 : 0];
     wire [NEw-1: 0] current_e_addr [NE-1 : 0];
-    
     reg [63 : 0]  total_sent_pck_count;
     reg [63 : 0]  total_sent_flit_count;
     reg [63 : 0]  total_rsv_pck_count;
@@ -65,120 +57,86 @@ module synfull_top;
     reg [63 : 0]  total_queued_pck_count;
     reg [63 : 0]  clk_count;
     
-    
-    
-    initial begin
-
-		//print_parameter 
-    	display_noc_parameters();	
-		$display ("Simulation parameters-------------");
-		if(DEBUG_EN)
-			$display ("\tDebuging is enabled");
-		else
-			$display ("\tDebuging is disabled");
-
-	
-
-	end//initial
-
-    
-    
-	wire [31:0] fifo_id [NE-1 : 0];
-	wire [PCK_SIZw-1 : 0]  fifo_size [NE-1 :0];
+    initial begin      
+        //print_parameter 
+        display_noc_parameters();    
+        $display ("Simulation parameters-------------");
+        if(DEBUG_EN)
+            $display ("\tDebuging is enabled");
+        else
+            $display ("\tDebuging is disabled");
+    end//initial
+    
+    wire [31:0] fifo_id [NE-1 : 0];
+    wire [PCK_SIZw-1 : 0]  fifo_size [NE-1 :0];
     wire [NEw-1 : 0] fifo_dest [NE-1 : 0];
-    wire [NE-1 : 0] fifo_wr,fifo_rd ,fifo_full,fifo_not_empty;
-        
+    fifo_stat_t fifo_stat [NE-1 : 0];
+    wire [NE-1 : 0] fifo_wr,fifo_rd;
+    
     genvar i;
     generate 
     for(i=0; i< NE; i=i+1) begin 
-    	
-    	assign fifo_wr[i] = 
-    		(pck_injct_out[i].ready == 1'b0 &&  synfull_pronoc_req_all[i].valid==1'b1) ||  
-    		(fifo_not_empty[i]==1'b1  &&  synfull_pronoc_req_all[i].valid==1'b1);
-    	    
-    	
-    	assign fifo_rd[i] = 
-    		(pck_injct_out[i].ready == 1'b1 && fifo_not_empty[i]==1'b1 );
-    	
-    	
-    	    fwft_fifo_bram #(
-    			.DATA_WIDTH(32+PCK_SIZw+NEw),
-    			.MAX_DEPTH(1000000),
-    			.IGNORE_SAME_LOC_RD_WR_WARNING("NO") 
-    		)
-    		fifo
-    		(
-    			.din({synfull_pronoc_req_all[i].id,synfull_pronoc_req_all[i].size,synfull_pronoc_req_all[i].dest}),     // Data in
-    			.wr_en(fifo_wr[i]),   // Write enable
-    			.rd_en(fifo_rd[i]),   // Read the next word
-    			.dout({fifo_id[i],fifo_size[i],fifo_dest[i]}),    // Data out
-    			.full( fifo_full[i]),
-    			.nearly_full(),
-    			.recieve_more_than_0(fifo_not_empty[i]),
-    			.recieve_more_than_1(),
-    			.reset(reset),
-    			.clk (clk)
-    
-    		);
-    	
-    	
-    	
-    	
-    	
+        assign fifo_wr[i] = 
+            (pck_injct_out[i].ready == 1'b0 &&  synfull_pronoc_req_all[i].valid==1'b1) ||  
+            (fifo_stat[i].has_data  &&  synfull_pronoc_req_all[i].valid==1'b1);
+        
+        assign fifo_rd[i] = 
+            (pck_injct_out[i].ready == 1'b1 && fifo_stat[i].has_data==1'b1 );
+        
+        fwft_fifo_bram #(
+            .DATA_WIDTH(32+PCK_SIZw+NEw),
+            .MAX_DEPTH(1000000),
+            .IGNORE_SAME_LOC_RD_WR_WARNING(0) //"NO"
+        ) fifo  (
+            .din({synfull_pronoc_req_all[i].id,synfull_pronoc_req_all[i].size,synfull_pronoc_req_all[i].dest}),     // Data in
+            .wr_en(fifo_wr[i]),   // Write enable
+            .rd_en(fifo_rd[i]),   // Read the next word
+            .dout({fifo_id[i],fifo_size[i],fifo_dest[i]}),    // Data out
+            .stat_o(fifo_stat[i]),
+            .reset(reset),
+            .clk (clk)
+        );
+        
         //from synfull 
-        assign pck_injct_in[i].data = (fifo_not_empty[i])?  fifo_id[i] : synfull_pronoc_req_all[i].id;
-        assign pck_injct_in[i].size = (fifo_not_empty[i])?  fifo_size[i] : synfull_pronoc_req_all[i].size;
-        assign pck_injct_in[i].pck_wr =  (fifo_not_empty[i])?   fifo_rd[i] :  (  synfull_pronoc_req_all[i].valid & pck_injct_out[i].ready == 1'b1);  
+        assign pck_injct_in[i].data = (fifo_stat[i].has_data)?  fifo_id[i] : synfull_pronoc_req_all[i].id;
+        assign pck_injct_in[i].size = (fifo_stat[i].has_data)?  fifo_size[i] : synfull_pronoc_req_all[i].size;
+        assign pck_injct_in[i].pck_wr =  (fifo_stat[i].has_data)?   fifo_rd[i] :  (  synfull_pronoc_req_all[i].valid & pck_injct_out[i].ready == 1'b1);
         assign pck_injct_in[i].ready = 1'b1;
-        assign dest_id[i] =(fifo_not_empty[i])? fifo_dest[i] : synfull_pronoc_req_all[i].dest;             
-       
+        assign dest_id[i] =(fifo_stat[i].has_data)? fifo_dest[i] : synfull_pronoc_req_all[i].dest;
         //to synfull
         assign pronoc_synfull_del_all[i].id    = pck_injct_out[i].data   ; 
         assign pronoc_synfull_del_all[i].valid = pck_injct_out[i].pck_wr ;
         assign NE_ready_all[i] = 1'b1 ; //pck_injct_out[i].ready;
-        
         assign pck_injct_in[i].class_num = _pck_injct_in[i].class_num; 
         assign pck_injct_in[i].init_weight = _pck_injct_in[i].init_weight;
         assign pck_injct_in[i].vc = _pck_injct_in[i].vc;
         
-        
-        endp_addr_encoder #( .TOPOLOGY(TOPOLOGY), .T1(T1), .T2(T2), .T3(T3), .EAw(EAw),  .NE(NE)) encode1 ( .id(i[NEw-1 :0]), .code(current_e_addr[i]));
-        
-        packet_injector #(
-			.NOC_ID(NOC_ID)
-		) pck_inj(
+        endp_addr_encoder encode1 ( .id_in(i[NEw-1 :0]), .code_out(current_e_addr[i]));
+        packet_injector  pck_inj (
             //general
             .current_e_addr(current_e_addr[i]),
             .reset(reset),
-            .clk(clk),      
+            .clk(clk),
             //noc port
             .chan_in(chan_out_all[i]),
-            .chan_out(chan_in_all[i]),  
+            .chan_out(chan_in_all[i]),
             //control interafce
             .pck_injct_in(pck_injct_in[i]),
-            .pck_injct_out(pck_injct_out[i])        
-        );          
-    
-
-        endp_addr_encoder #( .TOPOLOGY(TOPOLOGY), .T1(T1), .T2(T2), .T3(T3), .EAw(EAw),  .NE(NE)) encode2 ( .id(dest_id[i]), .code(pck_injct_in[i].endp_addr));
-        
+            .pck_injct_out(pck_injct_out[i])
+        );
+        endp_addr_encoder encode2 ( .id_in(dest_id[i]), .code_out(pck_injct_in[i].endp_addr));
+        reg [31:0]k;
         
-       reg [31:0]k;
-       
-      
-       
-
         initial begin 
-`ifdef ACTIVE_LOW_RESET_MODE 
-        reset = 1'b0;
- `else 
-        reset = 1'b1;
-`endif  
+        `ifdef ACTIVE_LOW_RESET_MODE 
+            reset = 1'b0;
+        `else 
+            reset = 1'b1;
+        `endif  
             k=0;
             init_socket[i] = 1'b0;
             wakeup_synfull[i] = 1'b0;
             print_router_st=1'b0;
-            
             @(posedge clk) #1;
             _pck_injct_in[i].class_num=0; 
             _pck_injct_in[i].init_weight=1;
@@ -202,67 +160,54 @@ module synfull_top;
             $display ( "\t simulation clk count = %d",   clk_count);
             $display ( "\t Total queued packets = %d",total_queued_pck_count);
             $display ( "\t Total sent packets = %d", total_sent_pck_count);
-			$display ( "\t Total sent flits = %d", 	 total_sent_flit_count);  
-			$display ( "\t Total received packets = %d", total_rsv_pck_count);
-			$display ( "\t Total received flits = %d", 	 total_rsv_flit_count);  
-            
-            
+            $display ( "\t Total sent flits = %d",      total_sent_flit_count);  
+            $display ( "\t Total received packets = %d", total_rsv_pck_count);
+            $display ( "\t Total received flits = %d",      total_rsv_flit_count);  
             $finish;
         end
         
         always @(posedge clk) begin
-			if(pck_injct_out[i].pck_wr) begin 
-				$display ("%t:pck_inj(%d) got a packet: source=%d, size=%d, data=%h",$time,i,
-				pck_injct_out[i].endp_addr,pck_injct_out[i].size,pck_injct_out[i].data);
-									
-			end		
+            if(pck_injct_out[i].pck_wr) begin 
+                $display ("%t:pck_inj(%d) got a packet: source=%d, size=%d, data=%h",$time,i,
+                pck_injct_out[i].endp_addr,pck_injct_out[i].size,pck_injct_out[i].data);
+            end        
         end
-    
-      
     end//for
     endgenerate
     
     integer k;
-     
     always @(posedge clk) begin
-    	if(`pronoc_reset) begin 
-    		clk_count =0;
-    		total_sent_pck_count =0;
-    		total_sent_flit_count=0;
-    		total_rsv_pck_count  =0;
-    		total_rsv_flit_count =0;  
-    		total_queued_pck_count = 0;
-    	end else begin          	
-    		clk_count++;
-    		for(k=0; k< NE; k=k+1) begin : endpoints    		
-	    		if(pck_injct_out[k].pck_wr) begin 
-	    			total_rsv_pck_count++;
-	    			total_rsv_flit_count+=pck_injct_out[k].size;				
-	    		end 
-	    		if(pck_injct_in[k].pck_wr) begin 
-	    			total_sent_pck_count++;
-	    			total_sent_flit_count+=pck_injct_in[k].size;				
-	    		end 
-	    		if(synfull_pronoc_req_all[k].valid) begin
-	    			total_queued_pck_count++;
-	    		end    		
-    		end	
-	    end
-
+        if(`pronoc_reset) begin 
+            clk_count =0;
+            total_sent_pck_count =0;
+            total_sent_flit_count=0;
+            total_rsv_pck_count  =0;
+            total_rsv_flit_count =0;  
+            total_queued_pck_count = 0;
+        end else begin              
+            clk_count++;
+            for(k=0; k< NE; k=k+1) begin : endpoints            
+                if(pck_injct_out[k].pck_wr) begin 
+                    total_rsv_pck_count++;
+                    total_rsv_flit_count+=pck_injct_out[k].size;
+                end 
+                if(pck_injct_in[k].pck_wr) begin 
+                    total_sent_pck_count++;
+                    total_sent_flit_count+=pck_injct_in[k].size;
+                end 
+                if(synfull_pronoc_req_all[k].valid) begin
+                    total_queued_pck_count++;
+                end 
+            end
+        end
     end
     
-    
-    routers_statistic_collector # (
-        .NOC_ID(NOC_ID)
-    ) router_stat ( 
-    	.reset(reset),
-    	.clk(clk),		
-    	.router_event(router_event),
-    	.print(print_router_st)
+    routers_statistic_collector router_stat ( 
+        .reset(reset),
+        .clk(clk),
+        .router_event(router_event),
+        .print(print_router_st)
     );
-    
-    
-   
 endmodule
-// synthesis translate_on
+`endif
 
diff --git a/mpsoc/rtl/src_topology/common/custom_conv_routing.v b/mpsoc/rtl/src_topology/common/custom_conv_routing.v
new file mode 100644
index 0000000..961ada2
--- /dev/null
+++ b/mpsoc/rtl/src_topology/common/custom_conv_routing.v
@@ -0,0 +1,45 @@
+`timescale 1ns / 1ps
+
+module custom_conv_routing  #(
+    parameter TOPOLOGY = "CUSTOM_NAME",
+    parameter ROUTE_NAME = "CUSTOM_NAME",
+    parameter ROUTE_TYPE = "DETERMINISTIC",
+    parameter RAw = 3,  
+    parameter EAw = 3,   
+    parameter DSTPw=4  
+)(
+    current_r_addr,
+    dest_e_addr,
+    src_e_addr,
+    destport
+);
+    
+    input   [RAw-1   :0] current_r_addr;
+    input   [EAw-1   :0] dest_e_addr;
+    input   [EAw-1   :0] src_e_addr;
+    output  [DSTPw-1 :0] destport;    
+
+
+    generate
+    
+    //do not modify this line ===Tcustom1Rcustom===
+    /* verilator lint_off WIDTH */
+    if(TOPOLOGY == "custom1" && ROUTE_NAME== "custom" ) begin : Tcustom1Rcustom
+    /* verilator lint_on WIDTH */
+        Tcustom1Rcustom_conv_routing_comb  #(
+            .RAw(RAw),
+            .EAw(EAw),
+            .DSTPw(DSTPw)
+        ) the_routing (
+            .current_r_addr(current_r_addr),
+            .dest_e_addr(dest_e_addr),
+            .src_e_addr(src_e_addr),
+            .destport(destport)
+        );
+    end
+    endgenerate
+ 
+ 
+ 
+ 
+endmodule
diff --git a/mpsoc/rtl/src_topology/common/custom_lkh_routing.v b/mpsoc/rtl/src_topology/common/custom_lkh_routing.v
index 2976de0..a18c5d2 100644
--- a/mpsoc/rtl/src_topology/common/custom_lkh_routing.v
+++ b/mpsoc/rtl/src_topology/common/custom_lkh_routing.v
@@ -1,77 +1,46 @@
 `timescale 1ns / 1ps
 
 module custom_lkh_routing  #(
-	parameter TOPOLOGY = "CUSTOM_NAME",
+    parameter TOPOLOGY = "CUSTOM_NAME",
     parameter ROUTE_NAME = "CUSTOM_NAME",
-	parameter ROUTE_TYPE = "DETERMINISTIC",
-	parameter RAw = 3,  
-	parameter EAw = 3,   
-	parameter DSTPw=4  
-)
-(
-	current_r_addr,
-	dest_e_addr,
-	src_e_addr,
-	destport,
-	reset,
-	clk
+    parameter ROUTE_TYPE = "DETERMINISTIC",
+    parameter RAw = 3,  
+    parameter EAw = 3,   
+    parameter DSTPw=4  
+)(
+    current_r_addr,
+    dest_e_addr,
+    src_e_addr,
+    destport,
+    reset,
+    clk
 );
     
-	input   [RAw-1   :0] current_r_addr;
-	input   [EAw-1   :0] dest_e_addr;
-	input   [EAw-1   :0] src_e_addr;
-	output  [DSTPw-1 :0] destport;	
-	input reset,clk;
+    input   [RAw-1   :0] current_r_addr;
+    input   [EAw-1   :0] dest_e_addr;
+    input   [EAw-1   :0] src_e_addr;
+    output  [DSTPw-1 :0] destport;    
+    input reset,clk;
 
-    generate 
-    
-       
+    generate
      
-	//do not modify this line ===Tcustom1Rcustom===
+    //do not modify this line ===Tcustom1Rcustom===
+    /* verilator lint_off WIDTH */
     if(TOPOLOGY == "custom1" && ROUTE_NAME== "custom" ) begin : Tcustom1Rcustom
-     
-	   Tcustom1Rcustom_look_ahead_routing  #(
+    /* verilator lint_on WIDTH */
+        Tcustom1Rcustom_look_ahead_routing  #(
             .RAw(RAw),  
             .EAw(EAw),   
             .DSTPw(DSTPw)  
-        )
-        the_lkh_routing
-        (
+        ) the_lkh_routing (
             .current_r_addr(current_r_addr),
             .dest_e_addr(dest_e_addr),
             .src_e_addr(src_e_addr),
             .destport(destport),
             .reset(reset),
-            .clk(clk)        
-        );    
-    
-    end	
-    
+            .clk(clk)
+        );
+    end
     endgenerate
-    	
- 
-    	
- 
-    	
- 
-    	
- 
-    	
- 
-    	
  
-    	
- 
-    	
- 
-    	
- 
-    	
- 
-    	
- 
-    	
- 
-    
-
 endmodule
diff --git a/mpsoc/rtl/src_topology/common/custom_ni_routing.v b/mpsoc/rtl/src_topology/common/custom_ni_routing.v
index 54283e7..3b7ad6a 100644
--- a/mpsoc/rtl/src_topology/common/custom_ni_routing.v
+++ b/mpsoc/rtl/src_topology/common/custom_ni_routing.v
@@ -1,73 +1,33 @@
 `timescale 1ns / 1ps
-
 module custom_ni_routing  #(
-    parameter NOC_ID = 0,
     parameter TOPOLOGY = "CUSTOM_NAME",
     parameter ROUTE_NAME = "CUSTOM_NAME",
     parameter ROUTE_TYPE = "DETERMINISTIC",
     parameter RAw  = 4,  
     parameter EAw  = 4,   
     parameter DSTPw = 4   
-)
-(
+) (
     dest_e_addr,
     src_e_addr,
-    destport        
-);    
-
+    destport
+);
     input   [EAw-1   :0] dest_e_addr;
     input   [EAw-1   :0] src_e_addr;
     output  [DSTPw-1 :0] destport;   
-
-
-   generate 
-    
-        
-     
-	//do not modify this line ===Tcustom1Rcustom===
+    generate 
+    //do not modify this line ===Tcustom1Rcustom===
+    /* verilator lint_off WIDTH */
     if(TOPOLOGY == "custom1" && ROUTE_NAME== "custom" ) begin : Tcustom1Rcustom
-    
-        Tcustom1Rcustom_conventional_routing  #(
-           	.RAw(RAw),  
+    /* verilator lint_on WIDTH */
+        Tcustom1Rcustom_ni_routing  #(
+            .RAw(RAw),  
             .EAw(EAw),   
             .DSTPw(DSTPw)  
-        )
-        the_conventional_routing
-        (
+        )  the_ni_routing  (
             .dest_e_addr(dest_e_addr),
             .src_e_addr(src_e_addr),
-            .destport(destport)        
-        );    
-    
-    end	
-    
+            .destport(destport)
+        );
+    end
     endgenerate
-    	
- 
-    	
- 
-    	
- 
-    	
- 
-    	
- 
-    	
- 
-    	
- 
-    	
- 
-    	
- 
-    	
- 
-    	
- 
-    	
- 
- 
-
 endmodule
- 
- 
diff --git a/mpsoc/rtl/src_topology/common/custom_noc_top.sv b/mpsoc/rtl/src_topology/common/custom_noc_top.sv
index ecafc7d..53c02a6 100644
--- a/mpsoc/rtl/src_topology/common/custom_noc_top.sv
+++ b/mpsoc/rtl/src_topology/common/custom_noc_top.sv
@@ -1,72 +1,36 @@
 `include "pronoc_def.v"
 
 module   custom_noc_top 
-	#(
-		parameter NOC_ID=0
-	)(
-
+    (
     reset,
-    clk,    
+    clk,
     chan_in_all,
     chan_out_all,
-    router_event  
+    router_event
 );
-
-    `NOC_CONF
-    
-	input   clk,reset;
-	//local ports 
-	input   smartflit_chanel_t chan_in_all  [NE-1 : 0];
-	output  smartflit_chanel_t chan_out_all [NE-1 : 0];
-	
-	//Events
-	output  router_event_t  router_event [NR-1 : 0][MAX_P-1 : 0];
-	   
-
-    generate 
-
-          
-
-	
+    import pronoc_pkg::*;
     
-     
-	
+    input   clk,reset;
+    //local ports 
+    input   smartflit_chanel_t chan_in_all  [NE-1 : 0];
+    output  smartflit_chanel_t chan_out_all [NE-1 : 0];
     
-     
-	
+    //Events
+    output  router_event_t  router_event [NR-1 : 0][MAX_P-1 : 0];
+    generate 
     
-     
-	//do not modify this line ===custom1===
+    //do not modify this line ===custom1===
+    /* verilator lint_off WIDTH */
     if(TOPOLOGY == "custom1" ) begin : Tcustom1
-    
-		custom1_noc_genvar #(
-			.NOC_ID(NOC_ID)
-		) the_noc (	
-		    .reset(reset),
-		    .clk(clk),    
-		    .chan_in_all(chan_in_all),
-		    .chan_out_all(chan_out_all),
-		    .router_event(router_event)  
-		);
+    /* verilator lint_on WIDTH */
+        custom1_noc_genvar the_noc (
+            .reset(reset),
+            .clk(clk),
+            .chan_in_all(chan_in_all),
+            .chan_out_all(chan_out_all),
+            .router_event(router_event)  
+        );
     end
-    
     endgenerate
-	
-	 
-	
-	 
-	
-	 
-	
-	 
-	
-	 
-	
-	 
-	
-	 
-	
-
-
-
-endmodule	 
+    
+endmodule 
diff --git a/mpsoc/rtl/src_topology/custom1/Tcustom1Rcustom_conv_routing.v b/mpsoc/rtl/src_topology/custom1/Tcustom1Rcustom_conv_routing.v
new file mode 100644
index 0000000..0bfd980
--- /dev/null
+++ b/mpsoc/rtl/src_topology/custom1/Tcustom1Rcustom_conv_routing.v
@@ -0,0 +1,420 @@
+
+/**************************************************************************
+**    WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT ARE LIKELY TO BE
+**    OVERWRITTEN AND LOST. Rename this file if you wish to do any modification.
+****************************************************************************/
+
+
+/**********************************************************************
+**    File: /home/alireza/work/git/hca_git/git-hub/ProNoC/mpsoc/rtl/src_topology/custom1/Tcustom1Rcustom_conv_routing.v
+**    
+**    Copyright (C) 2014-2022  Alireza Monemi
+**    
+**    This file is part of ProNoC 2.2.0 
+**
+**    ProNoC ( stands for Prototype Network-on-chip)  is free software: 
+**    you can redistribute it and/or modify it under the terms of the GNU
+**    Lesser General Public License as published by the Free Software Foundation,
+**    either version 2 of the License, or (at your option) any later version.
+**
+**     ProNoC is distributed in the hope that it will be useful, but WITHOUT
+**     ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+**     or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
+**     Public License for more details.
+**
+**     You should have received a copy of the GNU Lesser General Public
+**     License along with ProNoC. If not, see <http:**www.gnu.org/licenses/>.
+******************************************************************************/ 
+
+    
+`include "pronoc_def.v"
+/*******************
+*  Tcustom1Rcustom_conv_routing
+*******************/
+module Tcustom1Rcustom_conv_routing  #(
+    parameter RAw = 3,
+    parameter EAw = 3,
+    parameter DSTPw=4
+)(
+    reset,
+    clk,
+    current_r_addr,
+    dest_e_addr,
+    src_e_addr,
+    destport
+);
+    input   [RAw-1   :0] current_r_addr;
+    input   [EAw-1   :0] dest_e_addr;
+    input   [EAw-1   :0] src_e_addr;
+    output  [DSTPw-1 :0] destport;
+    input reset,clk;
+    reg [EAw-1   :0] dest_e_addr_delay;
+    reg [EAw-1   :0] src_e_addr_delay;
+    
+    always @ (`pronoc_clk_reset_edge )begin 
+        if(`pronoc_reset)begin
+            dest_e_addr_delay<={EAw{1'b0}};
+            src_e_addr_delay<={EAw{1'b0}};
+        end else begin 
+            dest_e_addr_delay<=dest_e_addr;
+            src_e_addr_delay<=src_e_addr;
+        end
+    end
+    
+    Tcustom1Rcustom_conv_routing_comb  #(
+        .RAw(RAw),
+        .EAw(EAw),
+        .DSTPw(DSTPw)
+    ) lkp_cmb  (
+        .current_r_addr(current_r_addr),
+        .dest_e_addr(dest_e_addr_delay),
+        .src_e_addr(src_e_addr_delay),
+        .destport(destport)
+    );
+endmodule
+
+/*******************
+*  Tcustom1Rcustom_conv_routing_comb
+*******************/
+module Tcustom1Rcustom_conv_routing_comb  #(
+    parameter RAw = 3,
+    parameter EAw = 3,
+    parameter DSTPw=4
+)(
+    current_r_addr,
+    dest_e_addr,
+    src_e_addr,
+    destport
+);
+    input   [RAw-1   :0] current_r_addr;
+    input   [EAw-1   :0] dest_e_addr;
+    input   [EAw-1   :0] src_e_addr;
+    output reg [DSTPw-1 :0] destport;
+
+localparam [EAw-1 : 0]    E0=0;
+localparam [EAw-1 : 0]    E1=1;
+localparam [EAw-1 : 0]    E2=2;
+localparam [EAw-1 : 0]    E3=3;
+localparam [EAw-1 : 0]    E4=4;
+localparam [EAw-1 : 0]    E5=5;
+localparam [EAw-1 : 0]    E6=6;
+localparam [EAw-1 : 0]    E7=7;
+localparam [EAw-1 : 0]    E8=8;
+localparam [EAw-1 : 0]    E9=9;
+localparam [EAw-1 : 0]    E10=10;
+localparam [EAw-1 : 0]    E11=11;
+localparam [EAw-1 : 0]    E12=12;
+localparam [EAw-1 : 0]    E13=13;
+localparam [EAw-1 : 0]    E14=14;
+localparam [EAw-1 : 0]    E15=15;
+
+
+    always@(*)begin
+        destport=0;
+        case(current_r_addr) //current_r_addr of each individual router is fixed. So this CASE will be optimized by the synthesizer for each router. 
+        0: begin
+            case({src_e_addr,dest_e_addr})
+            {E1,E0},{E2,E0},{E3,E0},{E4,E0},{E5,E0},{E6,E0},{E7,E0},{E8,E0},{E9,E0},{E10,E0},{E11,E0},{E12,E0},{E13,E0},{E14,E0},{E15,E0}: begin 
+                destport= 0; 
+            end
+            {E0,E1},{E0,E2},{E0,E3},{E0,E7},{E0,E10}: begin 
+                destport= 1; 
+            end
+            {E0,E4},{E0,E5},{E0,E6},{E0,E8},{E0,E9},{E0,E11},{E0,E12},{E0,E13},{E0,E14},{E0,E15}: begin 
+                destport= 2; 
+            end
+            default: begin 
+                destport= {DSTPw{1'bX}};
+            end
+            endcase
+        end//0
+        1: begin
+            case({src_e_addr,dest_e_addr})
+            {E0,E1},{E2,E1},{E3,E1},{E4,E1},{E5,E1},{E6,E1},{E7,E1},{E8,E1},{E9,E1},{E10,E1},{E11,E1},{E12,E1},{E13,E1},{E14,E1},{E15,E1}: begin 
+                destport= 0; 
+            end
+            {E1,E0},{E1,E4},{E1,E7},{E1,E8},{E1,E9},{E1,E10},{E1,E12},{E1,E15},{E2,E0},{E2,E7},{E2,E9},{E2,E10},{E2,E12}: begin 
+                destport= 1; 
+            end
+            {E1,E2},{E1,E3},{E1,E5},{E1,E6},{E1,E11},{E1,E13},{E1,E14}: begin 
+                destport= 2; 
+            end
+            default: begin 
+                destport= {DSTPw{1'bX}};
+            end
+            endcase
+        end//1
+        2: begin
+            case({src_e_addr,dest_e_addr})
+            {E0,E2},{E1,E2},{E3,E2},{E4,E2},{E5,E2},{E6,E2},{E7,E2},{E8,E2},{E9,E2},{E10,E2},{E11,E2},{E12,E2},{E13,E2},{E14,E2},{E15,E2}: begin 
+                destport= 0; 
+            end
+            {E1,E3},{E1,E5},{E1,E6},{E1,E11},{E1,E13},{E1,E14},{E2,E3},{E2,E4},{E2,E5},{E2,E6},{E2,E8},{E2,E11},{E2,E13},{E2,E14},{E2,E15}: begin 
+                destport= 1; 
+            end
+            {E2,E0},{E2,E1},{E2,E7},{E2,E9},{E2,E10},{E2,E12}: begin 
+                destport= 2; 
+            end
+            default: begin 
+                destport= {DSTPw{1'bX}};
+            end
+            endcase
+        end//2
+        3: begin
+            case({src_e_addr,dest_e_addr})
+            {E0,E3},{E1,E3},{E2,E3},{E4,E3},{E5,E3},{E6,E3},{E7,E3},{E8,E3},{E9,E3},{E10,E3},{E11,E3},{E12,E3},{E13,E3},{E14,E3},{E15,E3}: begin 
+                destport= 0; 
+            end
+            {E3,E2},{E3,E10},{E3,E11},{E3,E12}: begin 
+                destport= 1; 
+            end
+            {E3,E0},{E3,E1},{E3,E4},{E3,E5},{E3,E6},{E3,E7},{E3,E8},{E3,E9},{E3,E13},{E3,E14},{E3,E15}: begin 
+                destport= 2; 
+            end
+            default: begin 
+                destport= {DSTPw{1'bX}};
+            end
+            endcase
+        end//3
+        4: begin
+            case({src_e_addr,dest_e_addr})
+            {E0,E4},{E1,E4},{E2,E4},{E3,E4},{E5,E4},{E6,E4},{E7,E4},{E8,E4},{E9,E4},{E10,E4},{E11,E4},{E12,E4},{E13,E4},{E14,E4},{E15,E4}: begin 
+                destport= 0; 
+            end
+            {E3,E1},{E3,E6},{E3,E7},{E3,E8},{E3,E13},{E3,E14},{E4,E1},{E4,E6},{E4,E7},{E4,E8},{E4,E10},{E4,E13}: begin 
+                destport= 1; 
+            end
+            {E4,E3},{E5,E3},{E6,E3},{E7,E3},{E8,E3},{E9,E3},{E10,E3},{E12,E3},{E13,E3},{E14,E3},{E15,E3}: begin 
+                destport= 2; 
+            end
+            {E3,E0},{E3,E5},{E3,E9},{E3,E15},{E4,E0},{E4,E2},{E4,E5},{E4,E9},{E4,E11},{E4,E12},{E4,E14},{E4,E15}: begin 
+                destport= 3; 
+            end
+            default: begin 
+                destport= {DSTPw{1'bX}};
+            end
+            endcase
+        end//4
+        5: begin
+            case({src_e_addr,dest_e_addr})
+            {E0,E5},{E1,E5},{E2,E5},{E3,E5},{E4,E5},{E6,E5},{E7,E5},{E8,E5},{E9,E5},{E10,E5},{E11,E5},{E12,E5},{E13,E5},{E14,E5},{E15,E5}: begin 
+                destport= 0; 
+            end
+            {E0,E14},{E0,E15},{E3,E15},{E4,E12},{E4,E15},{E5,E1},{E5,E7},{E5,E8},{E5,E10},{E5,E11},{E5,E12},{E5,E15},{E6,E1},{E6,E2},{E6,E7},{E6,E8},{E6,E10},{E6,E11},{E6,E12},{E6,E14},{E6,E15},{E9,E2},{E9,E11},{E9,E15}: begin 
+                destport= 1; 
+            end
+            {E0,E4},{E0,E6},{E0,E13},{E5,E2},{E5,E3},{E5,E4},{E5,E6},{E5,E13},{E5,E14},{E9,E3},{E9,E4},{E9,E6},{E9,E13},{E9,E14}: begin 
+                destport= 2; 
+            end
+            {E3,E0},{E3,E9},{E4,E0},{E4,E9},{E5,E0},{E5,E9},{E6,E0},{E6,E9},{E11,E0},{E13,E0},{E13,E9},{E14,E9},{E15,E0},{E15,E9}: begin 
+                destport= 3; 
+            end
+            default: begin 
+                destport= {DSTPw{1'bX}};
+            end
+            endcase
+        end//5
+        6: begin
+            case({src_e_addr,dest_e_addr})
+            {E0,E6},{E1,E6},{E2,E6},{E3,E6},{E4,E6},{E5,E6},{E7,E6},{E8,E6},{E9,E6},{E10,E6},{E11,E6},{E12,E6},{E13,E6},{E14,E6},{E15,E6}: begin 
+                destport= 0; 
+            end
+            {E0,E4},{E0,E13},{E4,E2},{E4,E11},{E4,E14},{E5,E2},{E5,E3},{E5,E4},{E5,E13},{E5,E14},{E6,E3},{E6,E4},{E6,E13},{E9,E3},{E9,E4},{E9,E13},{E9,E14}: begin 
+                destport= 1; 
+            end
+            {E3,E0},{E3,E5},{E3,E9},{E3,E15},{E4,E0},{E4,E5},{E4,E9},{E4,E12},{E4,E15},{E6,E0},{E6,E1},{E6,E2},{E6,E5},{E6,E7},{E6,E8},{E6,E9},{E6,E10},{E6,E11},{E6,E12},{E6,E14},{E6,E15}: begin 
+                destport= 2; 
+            end
+            default: begin 
+                destport= {DSTPw{1'bX}};
+            end
+            endcase
+        end//6
+        7: begin
+            case({src_e_addr,dest_e_addr})
+            {E0,E7},{E1,E7},{E2,E7},{E3,E7},{E4,E7},{E5,E7},{E6,E7},{E8,E7},{E9,E7},{E10,E7},{E11,E7},{E12,E7},{E13,E7},{E14,E7},{E15,E7}: begin 
+                destport= 0; 
+            end
+            {E1,E4},{E1,E8},{E1,E9},{E1,E12},{E1,E15},{E2,E9},{E2,E12},{E7,E2},{E7,E3},{E7,E4},{E7,E5},{E7,E6},{E7,E8},{E7,E9},{E7,E11},{E7,E12},{E7,E13},{E7,E14},{E7,E15}: begin 
+                destport= 1; 
+            end
+            {E1,E0},{E1,E10},{E2,E0},{E2,E10},{E3,E10},{E4,E10},{E7,E0},{E7,E10},{E11,E10},{E13,E10},{E14,E0},{E14,E10}: begin 
+                destport= 2; 
+            end
+            {E0,E1},{E3,E1},{E4,E1},{E5,E1},{E6,E1},{E7,E1},{E8,E1},{E9,E1},{E10,E1},{E11,E1},{E12,E1},{E13,E1},{E14,E1},{E15,E1}: begin 
+                destport= 3; 
+            end
+            default: begin 
+                destport= {DSTPw{1'bX}};
+            end
+            endcase
+        end//7
+        8: begin
+            case({src_e_addr,dest_e_addr})
+            {E0,E8},{E1,E8},{E2,E8},{E3,E8},{E4,E8},{E5,E8},{E6,E8},{E7,E8},{E9,E8},{E10,E8},{E11,E8},{E12,E8},{E13,E8},{E14,E8},{E15,E8}: begin 
+                destport= 0; 
+            end
+            {E1,E9},{E1,E12},{E1,E15},{E2,E9},{E2,E12},{E7,E9},{E7,E12},{E8,E0},{E8,E4},{E8,E5},{E8,E9},{E8,E10},{E8,E12}: begin 
+                destport= 1; 
+            end
+            {E1,E4},{E7,E2},{E7,E3},{E7,E4},{E7,E5},{E7,E6},{E7,E11},{E7,E13},{E7,E14},{E7,E15},{E8,E2},{E8,E3},{E8,E6},{E8,E11},{E8,E13},{E8,E14},{E8,E15}: begin 
+                destport= 2; 
+            end
+            {E3,E1},{E3,E7},{E3,E10},{E4,E1},{E4,E7},{E4,E10},{E8,E1},{E8,E7},{E9,E1},{E9,E7},{E11,E1},{E11,E7},{E11,E10},{E13,E1},{E13,E7},{E13,E10},{E14,E0},{E14,E1},{E14,E7},{E14,E10}: begin 
+                destport= 3; 
+            end
+            default: begin 
+                destport= {DSTPw{1'bX}};
+            end
+            endcase
+        end//8
+        9: begin
+            case({src_e_addr,dest_e_addr})
+            {E0,E9},{E1,E9},{E2,E9},{E3,E9},{E4,E9},{E5,E9},{E6,E9},{E7,E9},{E8,E9},{E10,E9},{E11,E9},{E12,E9},{E13,E9},{E14,E9},{E15,E9}: begin 
+                destport= 0; 
+            end
+            {E0,E8},{E0,E11},{E0,E12},{E9,E1},{E9,E7},{E9,E8},{E9,E10},{E9,E12}: begin 
+                destport= 1; 
+            end
+            {E0,E4},{E0,E5},{E0,E6},{E0,E13},{E0,E14},{E0,E15},{E9,E2},{E9,E3},{E9,E4},{E9,E5},{E9,E6},{E9,E11},{E9,E13},{E9,E14},{E9,E15}: begin 
+                destport= 2; 
+            end
+            {E3,E0},{E4,E0},{E5,E0},{E6,E0},{E8,E0},{E9,E0},{E11,E0},{E12,E0},{E13,E0},{E15,E0}: begin 
+                destport= 3; 
+            end
+            default: begin 
+                destport= {DSTPw{1'bX}};
+            end
+            endcase
+        end//9
+        10: begin
+            case({src_e_addr,dest_e_addr})
+            {E0,E10},{E1,E10},{E2,E10},{E3,E10},{E4,E10},{E5,E10},{E6,E10},{E7,E10},{E8,E10},{E9,E10},{E11,E10},{E12,E10},{E13,E10},{E14,E10},{E15,E10}: begin 
+                destport= 0; 
+            end
+            {E0,E2},{E0,E3},{E10,E2},{E10,E3},{E10,E4},{E10,E5},{E10,E6},{E10,E8},{E10,E9},{E10,E11},{E10,E12},{E10,E13},{E10,E14},{E10,E15}: begin 
+                destport= 1; 
+            end
+            {E0,E1},{E0,E7},{E5,E1},{E5,E7},{E6,E1},{E6,E7},{E10,E1},{E10,E7},{E12,E1},{E12,E7},{E15,E1},{E15,E7}: begin 
+                destport= 2; 
+            end
+            {E1,E0},{E2,E0},{E7,E0},{E10,E0},{E14,E0}: begin 
+                destport= 3; 
+            end
+            default: begin 
+                destport= {DSTPw{1'bX}};
+            end
+            endcase
+        end//10
+        11: begin
+            case({src_e_addr,dest_e_addr})
+            {E0,E11},{E1,E11},{E2,E11},{E3,E11},{E4,E11},{E5,E11},{E6,E11},{E7,E11},{E8,E11},{E9,E11},{E10,E11},{E12,E11},{E13,E11},{E14,E11},{E15,E11}: begin 
+                destport= 0; 
+            end
+            {E1,E5},{E1,E6},{E1,E13},{E1,E14},{E2,E4},{E2,E5},{E2,E6},{E2,E8},{E2,E13},{E2,E14},{E2,E15},{E3,E10},{E3,E12},{E11,E0},{E11,E1},{E11,E4},{E11,E5},{E11,E6},{E11,E7},{E11,E8},{E11,E9},{E11,E10},{E11,E12},{E11,E13},{E11,E14},{E11,E15}: begin 
+                destport= 1; 
+            end
+            {E0,E2},{E3,E2},{E4,E2},{E5,E2},{E6,E2},{E7,E2},{E8,E2},{E9,E2},{E10,E2},{E11,E2},{E12,E2},{E13,E2},{E14,E2},{E15,E2}: begin 
+                destport= 2; 
+            end
+            {E0,E3},{E1,E3},{E2,E3},{E11,E3}: begin 
+                destport= 3; 
+            end
+            default: begin 
+                destport= {DSTPw{1'bX}};
+            end
+            endcase
+        end//11
+        12: begin
+            case({src_e_addr,dest_e_addr})
+            {E0,E12},{E1,E12},{E2,E12},{E3,E12},{E4,E12},{E5,E12},{E6,E12},{E7,E12},{E8,E12},{E9,E12},{E10,E12},{E11,E12},{E13,E12},{E14,E12},{E15,E12}: begin 
+                destport= 0; 
+            end
+            {E0,E2},{E0,E3},{E0,E11},{E1,E15},{E8,E4},{E8,E5},{E10,E2},{E10,E3},{E10,E4},{E10,E5},{E10,E6},{E10,E11},{E10,E13},{E10,E14},{E10,E15},{E12,E2},{E12,E3},{E12,E4},{E12,E5},{E12,E6},{E12,E11},{E12,E13},{E12,E14},{E12,E15}: begin 
+                destport= 1; 
+            end
+            {E1,E9},{E2,E9},{E7,E9},{E8,E0},{E8,E9},{E10,E9},{E11,E9},{E12,E0},{E12,E9}: begin 
+                destport= 2; 
+            end
+            {E5,E1},{E5,E7},{E5,E10},{E6,E1},{E6,E7},{E6,E10},{E8,E10},{E9,E10},{E12,E1},{E12,E7},{E12,E10},{E15,E1},{E15,E7},{E15,E10}: begin 
+                destport= 3; 
+            end
+            {E0,E8},{E5,E8},{E6,E8},{E9,E1},{E9,E7},{E9,E8},{E10,E8},{E12,E8},{E15,E8}: begin 
+                destport= 4; 
+            end
+            default: begin 
+                destport= {DSTPw{1'bX}};
+            end
+            endcase
+        end//12
+        13: begin
+            case({src_e_addr,dest_e_addr})
+            {E0,E13},{E1,E13},{E2,E13},{E3,E13},{E4,E13},{E5,E13},{E6,E13},{E7,E13},{E8,E13},{E9,E13},{E10,E13},{E11,E13},{E12,E13},{E14,E13},{E15,E13}: begin 
+                destport= 0; 
+            end
+            {E0,E4},{E1,E4},{E2,E4},{E5,E3},{E5,E4},{E6,E3},{E6,E4},{E7,E3},{E7,E4},{E8,E3},{E8,E4},{E9,E3},{E9,E4},{E10,E3},{E10,E4},{E11,E4},{E12,E3},{E12,E4},{E13,E3},{E13,E4},{E14,E3},{E14,E4},{E15,E3},{E15,E4}: begin 
+                destport= 2; 
+            end
+            {E1,E6},{E2,E6},{E3,E6},{E4,E6},{E7,E6},{E8,E6},{E10,E6},{E11,E6},{E12,E6},{E13,E6},{E14,E6},{E15,E6}: begin 
+                destport= 3; 
+            end
+            {E3,E1},{E3,E7},{E3,E8},{E3,E14},{E4,E1},{E4,E2},{E4,E7},{E4,E8},{E4,E10},{E4,E11},{E4,E14},{E5,E2},{E5,E14},{E9,E14},{E13,E0},{E13,E1},{E13,E2},{E13,E5},{E13,E7},{E13,E8},{E13,E9},{E13,E10},{E13,E11},{E13,E12},{E13,E14},{E13,E15}: begin 
+                destport= 4; 
+            end
+            default: begin 
+                destport= {DSTPw{1'bX}};
+            end
+            endcase
+        end//13
+        14: begin
+            case({src_e_addr,dest_e_addr})
+            {E0,E14},{E1,E14},{E2,E14},{E3,E14},{E4,E14},{E5,E14},{E6,E14},{E7,E14},{E8,E14},{E9,E14},{E10,E14},{E11,E14},{E12,E14},{E13,E14},{E15,E14}: begin 
+                destport= 0; 
+            end
+            {E1,E5},{E1,E13},{E2,E5},{E2,E15},{E3,E12},{E7,E5},{E7,E15},{E8,E15},{E11,E0},{E11,E5},{E11,E9},{E11,E12},{E11,E15},{E13,E0},{E13,E5},{E13,E9},{E13,E12},{E13,E15},{E14,E5},{E14,E9},{E14,E12},{E14,E15}: begin 
+                destport= 1; 
+            end
+            {E1,E4},{E1,E6},{E2,E4},{E2,E6},{E2,E13},{E7,E3},{E7,E4},{E7,E6},{E7,E13},{E8,E3},{E8,E6},{E8,E13},{E11,E4},{E11,E6},{E11,E13},{E14,E3},{E14,E4},{E14,E6},{E14,E13}: begin 
+                destport= 2; 
+            end
+            {E2,E8},{E3,E1},{E3,E7},{E3,E8},{E3,E10},{E4,E1},{E4,E7},{E4,E8},{E4,E10},{E11,E1},{E11,E7},{E11,E8},{E11,E10},{E13,E1},{E13,E7},{E13,E8},{E13,E10},{E14,E0},{E14,E1},{E14,E7},{E14,E8},{E14,E10}: begin 
+                destport= 3; 
+            end
+            {E0,E2},{E0,E3},{E0,E11},{E4,E2},{E4,E11},{E5,E2},{E5,E11},{E6,E2},{E6,E11},{E7,E2},{E7,E11},{E8,E2},{E8,E11},{E9,E2},{E9,E11},{E10,E2},{E10,E11},{E12,E2},{E12,E11},{E13,E2},{E13,E11},{E14,E2},{E14,E11},{E15,E2},{E15,E11}: begin 
+                destport= 4; 
+            end
+            default: begin 
+                destport= {DSTPw{1'bX}};
+            end
+            endcase
+        end//14
+        15: begin
+            case({src_e_addr,dest_e_addr})
+            {E0,E15},{E1,E15},{E2,E15},{E3,E15},{E4,E15},{E5,E15},{E6,E15},{E7,E15},{E8,E15},{E9,E15},{E10,E15},{E11,E15},{E12,E15},{E13,E15},{E14,E15}: begin 
+                destport= 0; 
+            end
+            {E3,E12},{E4,E12},{E5,E1},{E5,E7},{E5,E8},{E5,E10},{E5,E12},{E6,E1},{E6,E7},{E6,E8},{E6,E10},{E6,E12},{E11,E9},{E11,E12},{E13,E12},{E14,E12},{E15,E1},{E15,E7},{E15,E8},{E15,E10},{E15,E12}: begin 
+                destport= 1; 
+            end
+            {E0,E2},{E0,E3},{E0,E11},{E0,E14},{E5,E11},{E6,E2},{E6,E11},{E6,E14},{E9,E2},{E9,E11},{E10,E2},{E10,E11},{E10,E14},{E12,E2},{E12,E11},{E12,E14},{E15,E2},{E15,E11},{E15,E14}: begin 
+                destport= 2; 
+            end
+            {E1,E13},{E8,E4},{E10,E3},{E10,E4},{E10,E6},{E10,E13},{E12,E3},{E12,E4},{E12,E6},{E12,E13},{E15,E3},{E15,E4},{E15,E6},{E15,E13}: begin 
+                destport= 3; 
+            end
+            {E1,E5},{E2,E5},{E7,E5},{E8,E5},{E10,E5},{E11,E0},{E11,E5},{E12,E5},{E13,E0},{E13,E5},{E13,E9},{E14,E5},{E14,E9},{E15,E0},{E15,E5},{E15,E9}: begin 
+                destport= 4; 
+            end
+            default: begin 
+                destport= {DSTPw{1'bX}};
+            end
+            endcase
+        end//15
+        default: begin 
+            destport= {DSTPw{1'bX}};
+        end
+        endcase
+    end
+
+
+endmodule
diff --git a/mpsoc/rtl/src_topology/custom1/Tcustom1Rcustom_conventional_routing.v b/mpsoc/rtl/src_topology/custom1/Tcustom1Rcustom_conventional_routing.v
deleted file mode 100644
index 0e7ffae..0000000
--- a/mpsoc/rtl/src_topology/custom1/Tcustom1Rcustom_conventional_routing.v
+++ /dev/null
@@ -1,323 +0,0 @@
-
-/**************************************************************************
-**	WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT ARE LIKELY TO BE
-**	OVERWRITTEN AND LOST. Rename this file if you wish to do any modification.
-****************************************************************************/
-
-
-/**********************************************************************
-**	File: /home/alireza/work/git/pronoc/mpsoc/rtl/src_topology/custom1/Tcustom1Rcustom_conventional_routing.v
-**    
-**	Copyright (C) 2014-2021  Alireza Monemi
-**    
-**	This file is part of ProNoC 2.1.0 
-**
-**	ProNoC ( stands for Prototype Network-on-chip)  is free software: 
-**	you can redistribute it and/or modify it under the terms of the GNU
-**	Lesser General Public License as published by the Free Software Foundation,
-**	either version 2 of the License, or (at your option) any later version.
-**
-** 	ProNoC is distributed in the hope that it will be useful, but WITHOUT
-** 	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
-** 	or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
-** 	Public License for more details.
-**
-** 	You should have received a copy of the GNU Lesser General Public
-** 	License along with ProNoC. If not, see <http:**www.gnu.org/licenses/>.
-******************************************************************************/ 
-module Tcustom1Rcustom_conventional_routing  #(
-	parameter RAw = 3,  
-	parameter EAw = 3,   
-	parameter DSTPw=4  
-)
-(
-	dest_e_addr,
-	src_e_addr,
-	destport        
-);
-    
-	input   [EAw-1   :0] dest_e_addr;
-	input   [EAw-1   :0] src_e_addr;
-	output reg [DSTPw-1 :0] destport;	
-        
-    
-	always@(*)begin
-		destport=0;
-		case(src_e_addr) //source address of each individual NI is fixed. So this CASE will be optimized by the synthesizer for each endpoint. 
-		0: begin
-			case(dest_e_addr)
-			1,2,3,7,10: begin 
-				destport= 1; 
-			end
-			4,5,6,8,9,11,12,13,14,15: begin 
-				destport= 2; 
-			end
-
-			default: begin 
-				destport= {DSTPw{1'bX}};
-			end
-			endcase
-		end//0
-		1: begin
-			case(dest_e_addr)
-			0,4,7,8,9,10,12,15: begin 
-				destport= 1; 
-			end
-			2,3,5,6,11,13,14: begin 
-				destport= 2; 
-			end
-
-			default: begin 
-				destport= {DSTPw{1'bX}};
-			end
-			endcase
-		end//1
-		2: begin
-			case(dest_e_addr)
-			3,4,5,6,8,11,13,14,15: begin 
-				destport= 1; 
-			end
-			0,1,7,9,10,12: begin 
-				destport= 2; 
-			end
-
-			default: begin 
-				destport= {DSTPw{1'bX}};
-			end
-			endcase
-		end//2
-		3: begin
-			case(dest_e_addr)
-			2,10,11,12: begin 
-				destport= 1; 
-			end
-			0,1,4,5,6,7,8,9,13,14,15: begin 
-				destport= 2; 
-			end
-
-			default: begin 
-				destport= {DSTPw{1'bX}};
-			end
-			endcase
-		end//3
-		4: begin
-			case(dest_e_addr)
-			1,6,7,8,10,13: begin 
-				destport= 1; 
-			end
-			3: begin 
-				destport= 2; 
-			end
-			0,2,5,9,11,12,14,15: begin 
-				destport= 3; 
-			end
-
-			default: begin 
-				destport= {DSTPw{1'bX}};
-			end
-			endcase
-		end//4
-		5: begin
-			case(dest_e_addr)
-			1,7,8,10,11,12,15: begin 
-				destport= 1; 
-			end
-			2,3,4,6,13,14: begin 
-				destport= 2; 
-			end
-			0,9: begin 
-				destport= 3; 
-			end
-
-			default: begin 
-				destport= {DSTPw{1'bX}};
-			end
-			endcase
-		end//5
-		6: begin
-			case(dest_e_addr)
-			3,4,13: begin 
-				destport= 1; 
-			end
-			0,1,2,5,7,8,9,10,11,12,14,15: begin 
-				destport= 2; 
-			end
-
-			default: begin 
-				destport= {DSTPw{1'bX}};
-			end
-			endcase
-		end//6
-		7: begin
-			case(dest_e_addr)
-			2,3,4,5,6,8,9,11,12,13,14,15: begin 
-				destport= 1; 
-			end
-			0,10: begin 
-				destport= 2; 
-			end
-			1: begin 
-				destport= 3; 
-			end
-
-			default: begin 
-				destport= {DSTPw{1'bX}};
-			end
-			endcase
-		end//7
-		8: begin
-			case(dest_e_addr)
-			0,4,5,9,10,12: begin 
-				destport= 1; 
-			end
-			2,3,6,11,13,14,15: begin 
-				destport= 2; 
-			end
-			1,7: begin 
-				destport= 3; 
-			end
-
-			default: begin 
-				destport= {DSTPw{1'bX}};
-			end
-			endcase
-		end//8
-		9: begin
-			case(dest_e_addr)
-			1,7,8,10,12: begin 
-				destport= 1; 
-			end
-			2,3,4,5,6,11,13,14,15: begin 
-				destport= 2; 
-			end
-			0: begin 
-				destport= 3; 
-			end
-
-			default: begin 
-				destport= {DSTPw{1'bX}};
-			end
-			endcase
-		end//9
-		10: begin
-			case(dest_e_addr)
-			2,3,4,5,6,8,9,11,12,13,14,15: begin 
-				destport= 1; 
-			end
-			1,7: begin 
-				destport= 2; 
-			end
-			0: begin 
-				destport= 3; 
-			end
-
-			default: begin 
-				destport= {DSTPw{1'bX}};
-			end
-			endcase
-		end//10
-		11: begin
-			case(dest_e_addr)
-			0,1,4,5,6,7,8,9,10,12,13,14,15: begin 
-				destport= 1; 
-			end
-			2: begin 
-				destport= 2; 
-			end
-			3: begin 
-				destport= 3; 
-			end
-
-			default: begin 
-				destport= {DSTPw{1'bX}};
-			end
-			endcase
-		end//11
-		12: begin
-			case(dest_e_addr)
-			2,3,4,5,6,11,13,14,15: begin 
-				destport= 1; 
-			end
-			0,9: begin 
-				destport= 2; 
-			end
-			1,7,10: begin 
-				destport= 3; 
-			end
-			8: begin 
-				destport= 4; 
-			end
-
-			default: begin 
-				destport= {DSTPw{1'bX}};
-			end
-			endcase
-		end//12
-		13: begin
-			case(dest_e_addr)
-			3,4: begin 
-				destport= 2; 
-			end
-			6: begin 
-				destport= 3; 
-			end
-			0,1,2,5,7,8,9,10,11,12,14,15: begin 
-				destport= 4; 
-			end
-
-			default: begin 
-				destport= {DSTPw{1'bX}};
-			end
-			endcase
-		end//13
-		14: begin
-			case(dest_e_addr)
-			5,9,12,15: begin 
-				destport= 1; 
-			end
-			3,4,6,13: begin 
-				destport= 2; 
-			end
-			0,1,7,8,10: begin 
-				destport= 3; 
-			end
-			2,11: begin 
-				destport= 4; 
-			end
-
-			default: begin 
-				destport= {DSTPw{1'bX}};
-			end
-			endcase
-		end//14
-		15: begin
-			case(dest_e_addr)
-			1,7,8,10,12: begin 
-				destport= 1; 
-			end
-			2,11,14: begin 
-				destport= 2; 
-			end
-			3,4,6,13: begin 
-				destport= 3; 
-			end
-			0,5,9: begin 
-				destport= 4; 
-			end
-
-			default: begin 
-				destport= {DSTPw{1'bX}};
-			end
-			endcase
-		end//15
-
-		default: begin 
-			destport= {DSTPw{1'bX}};
-		end
-		endcase
-	end
-
-		
-	
-endmodule  
-    
diff --git a/mpsoc/rtl/src_topology/custom1/Tcustom1Rcustom_conventional_routing_genvar.v b/mpsoc/rtl/src_topology/custom1/Tcustom1Rcustom_conventional_routing_genvar.v
deleted file mode 100644
index 75cac59..0000000
--- a/mpsoc/rtl/src_topology/custom1/Tcustom1Rcustom_conventional_routing_genvar.v
+++ /dev/null
@@ -1,380 +0,0 @@
-
-/**************************************************************************
-**	WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT ARE LIKELY TO BE
-**	OVERWRITTEN AND LOST. Rename this file if you wish to do any modification.
-****************************************************************************/
-
-
-/**********************************************************************
-**	File: /home/alireza/work/git/pronoc/mpsoc/rtl/src_topology/custom1/Tcustom1Rcustom_conventional_routing_genvar.v
-**    
-**	Copyright (C) 2014-2021  Alireza Monemi
-**    
-**	This file is part of ProNoC 2.1.0 
-**
-**	ProNoC ( stands for Prototype Network-on-chip)  is free software: 
-**	you can redistribute it and/or modify it under the terms of the GNU
-**	Lesser General Public License as published by the Free Software Foundation,
-**	either version 2 of the License, or (at your option) any later version.
-**
-** 	ProNoC is distributed in the hope that it will be useful, but WITHOUT
-** 	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
-** 	or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
-** 	Public License for more details.
-**
-** 	You should have received a copy of the GNU Lesser General Public
-** 	License along with ProNoC. If not, see <http:**www.gnu.org/licenses/>.
-******************************************************************************/ 
-module Tcustom1Rcustom_conventional_routing_genvar  #(
-	parameter RAw = 3,  
-	parameter EAw = 3,   
-	parameter DSTPw=4,
-	parameter SRC_E_ADDR=0  
-)
-(
-	dest_e_addr,
-	destport        
-);
-    
-	input   [EAw-1   :0] dest_e_addr;
-	output reg [DSTPw-1 :0] destport;	
-        
-    
-	generate
-
-	if(SRC_E_ADDR == 0) begin : SRC0
-		always@(*)begin	
-			destport= 0; 
-			case(dest_e_addr)
-			1,2,3,7,10: begin 
-				destport= 1; 
-			end
-			4,5,6,8,9,11,12,13,14,15: begin 
-				destport= 2; 
-			end
-			default: begin 
-				destport= {DSTPw{1'bX}};
-			end
-
-			endcase
-		end
-	end//SRC0
-
-	if(SRC_E_ADDR == 1) begin : SRC1
-		always@(*)begin	
-			destport= 0; 
-			case(dest_e_addr)
-			0,4,7,8,9,10,12,15: begin 
-				destport= 1; 
-			end
-			2,3,5,6,11,13,14: begin 
-				destport= 2; 
-			end
-			default: begin 
-				destport= {DSTPw{1'bX}};
-			end
-
-			endcase
-		end
-	end//SRC1
-
-	if(SRC_E_ADDR == 2) begin : SRC2
-		always@(*)begin	
-			destport= 0; 
-			case(dest_e_addr)
-			3,4,5,6,8,11,13,14,15: begin 
-				destport= 1; 
-			end
-			0,1,7,9,10,12: begin 
-				destport= 2; 
-			end
-			default: begin 
-				destport= {DSTPw{1'bX}};
-			end
-
-			endcase
-		end
-	end//SRC2
-
-	if(SRC_E_ADDR == 3) begin : SRC3
-		always@(*)begin	
-			destport= 0; 
-			case(dest_e_addr)
-			2,10,11,12: begin 
-				destport= 1; 
-			end
-			0,1,4,5,6,7,8,9,13,14,15: begin 
-				destport= 2; 
-			end
-			default: begin 
-				destport= {DSTPw{1'bX}};
-			end
-
-			endcase
-		end
-	end//SRC3
-
-	if(SRC_E_ADDR == 4) begin : SRC4
-		always@(*)begin	
-			destport= 0; 
-			case(dest_e_addr)
-			1,6,7,8,10,13: begin 
-				destport= 1; 
-			end
-			3: begin 
-				destport= 2; 
-			end
-			0,2,5,9,11,12,14,15: begin 
-				destport= 3; 
-			end
-			default: begin 
-				destport= {DSTPw{1'bX}};
-			end
-
-			endcase
-		end
-	end//SRC4
-
-	if(SRC_E_ADDR == 5) begin : SRC5
-		always@(*)begin	
-			destport= 0; 
-			case(dest_e_addr)
-			1,7,8,10,11,12,15: begin 
-				destport= 1; 
-			end
-			2,3,4,6,13,14: begin 
-				destport= 2; 
-			end
-			0,9: begin 
-				destport= 3; 
-			end
-			default: begin 
-				destport= {DSTPw{1'bX}};
-			end
-
-			endcase
-		end
-	end//SRC5
-
-	if(SRC_E_ADDR == 6) begin : SRC6
-		always@(*)begin	
-			destport= 0; 
-			case(dest_e_addr)
-			3,4,13: begin 
-				destport= 1; 
-			end
-			0,1,2,5,7,8,9,10,11,12,14,15: begin 
-				destport= 2; 
-			end
-			default: begin 
-				destport= {DSTPw{1'bX}};
-			end
-
-			endcase
-		end
-	end//SRC6
-
-	if(SRC_E_ADDR == 7) begin : SRC7
-		always@(*)begin	
-			destport= 0; 
-			case(dest_e_addr)
-			2,3,4,5,6,8,9,11,12,13,14,15: begin 
-				destport= 1; 
-			end
-			0,10: begin 
-				destport= 2; 
-			end
-			1: begin 
-				destport= 3; 
-			end
-			default: begin 
-				destport= {DSTPw{1'bX}};
-			end
-
-			endcase
-		end
-	end//SRC7
-
-	if(SRC_E_ADDR == 8) begin : SRC8
-		always@(*)begin	
-			destport= 0; 
-			case(dest_e_addr)
-			0,4,5,9,10,12: begin 
-				destport= 1; 
-			end
-			2,3,6,11,13,14,15: begin 
-				destport= 2; 
-			end
-			1,7: begin 
-				destport= 3; 
-			end
-			default: begin 
-				destport= {DSTPw{1'bX}};
-			end
-
-			endcase
-		end
-	end//SRC8
-
-	if(SRC_E_ADDR == 9) begin : SRC9
-		always@(*)begin	
-			destport= 0; 
-			case(dest_e_addr)
-			1,7,8,10,12: begin 
-				destport= 1; 
-			end
-			2,3,4,5,6,11,13,14,15: begin 
-				destport= 2; 
-			end
-			0: begin 
-				destport= 3; 
-			end
-			default: begin 
-				destport= {DSTPw{1'bX}};
-			end
-
-			endcase
-		end
-	end//SRC9
-
-	if(SRC_E_ADDR == 10) begin : SRC10
-		always@(*)begin	
-			destport= 0; 
-			case(dest_e_addr)
-			2,3,4,5,6,8,9,11,12,13,14,15: begin 
-				destport= 1; 
-			end
-			1,7: begin 
-				destport= 2; 
-			end
-			0: begin 
-				destport= 3; 
-			end
-			default: begin 
-				destport= {DSTPw{1'bX}};
-			end
-
-			endcase
-		end
-	end//SRC10
-
-	if(SRC_E_ADDR == 11) begin : SRC11
-		always@(*)begin	
-			destport= 0; 
-			case(dest_e_addr)
-			0,1,4,5,6,7,8,9,10,12,13,14,15: begin 
-				destport= 1; 
-			end
-			2: begin 
-				destport= 2; 
-			end
-			3: begin 
-				destport= 3; 
-			end
-			default: begin 
-				destport= {DSTPw{1'bX}};
-			end
-
-			endcase
-		end
-	end//SRC11
-
-	if(SRC_E_ADDR == 12) begin : SRC12
-		always@(*)begin	
-			destport= 0; 
-			case(dest_e_addr)
-			2,3,4,5,6,11,13,14,15: begin 
-				destport= 1; 
-			end
-			0,9: begin 
-				destport= 2; 
-			end
-			1,7,10: begin 
-				destport= 3; 
-			end
-			8: begin 
-				destport= 4; 
-			end
-			default: begin 
-				destport= {DSTPw{1'bX}};
-			end
-
-			endcase
-		end
-	end//SRC12
-
-	if(SRC_E_ADDR == 13) begin : SRC13
-		always@(*)begin	
-			destport= 0; 
-			case(dest_e_addr)
-			3,4: begin 
-				destport= 2; 
-			end
-			6: begin 
-				destport= 3; 
-			end
-			0,1,2,5,7,8,9,10,11,12,14,15: begin 
-				destport= 4; 
-			end
-			default: begin 
-				destport= {DSTPw{1'bX}};
-			end
-
-			endcase
-		end
-	end//SRC13
-
-	if(SRC_E_ADDR == 14) begin : SRC14
-		always@(*)begin	
-			destport= 0; 
-			case(dest_e_addr)
-			5,9,12,15: begin 
-				destport= 1; 
-			end
-			3,4,6,13: begin 
-				destport= 2; 
-			end
-			0,1,7,8,10: begin 
-				destport= 3; 
-			end
-			2,11: begin 
-				destport= 4; 
-			end
-			default: begin 
-				destport= {DSTPw{1'bX}};
-			end
-
-			endcase
-		end
-	end//SRC14
-
-	if(SRC_E_ADDR == 15) begin : SRC15
-		always@(*)begin	
-			destport= 0; 
-			case(dest_e_addr)
-			1,7,8,10,12: begin 
-				destport= 1; 
-			end
-			2,11,14: begin 
-				destport= 2; 
-			end
-			3,4,6,13: begin 
-				destport= 3; 
-			end
-			0,5,9: begin 
-				destport= 4; 
-			end
-			default: begin 
-				destport= {DSTPw{1'bX}};
-			end
-
-			endcase
-		end
-	end//SRC15
-
-	endgenerate
-
-		
-	
-endmodule  
-    
diff --git a/mpsoc/rtl/src_topology/custom1/Tcustom1Rcustom_look_ahead_routing.v b/mpsoc/rtl/src_topology/custom1/Tcustom1Rcustom_look_ahead_routing.v
index f3e92cf..bacdb03 100644
--- a/mpsoc/rtl/src_topology/custom1/Tcustom1Rcustom_look_ahead_routing.v
+++ b/mpsoc/rtl/src_topology/custom1/Tcustom1Rcustom_look_ahead_routing.v
@@ -1,452 +1,438 @@
 
 /**************************************************************************
-**	WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT ARE LIKELY TO BE
-**	OVERWRITTEN AND LOST. Rename this file if you wish to do any modification.
+**    WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT ARE LIKELY TO BE
+**    OVERWRITTEN AND LOST. Rename this file if you wish to do any modification.
 ****************************************************************************/
 
 
 /**********************************************************************
-**	File: /home/alireza/work/git/pronoc/mpsoc/rtl/src_topology/custom1/Tcustom1Rcustom_look_ahead_routing.v
+**    File: /home/alireza/work/git/ProNoC-repos/github-pronoc/mpsoc/rtl/src_topology/custom1/Tcustom1Rcustom_look_ahead_routing.v
 **    
-**	Copyright (C) 2014-2021  Alireza Monemi
+**    Copyright (C) 2014-2022  Alireza Monemi
 **    
-**	This file is part of ProNoC 2.1.0 
+**    This file is part of ProNoC 2.2.0 
 **
-**	ProNoC ( stands for Prototype Network-on-chip)  is free software: 
-**	you can redistribute it and/or modify it under the terms of the GNU
-**	Lesser General Public License as published by the Free Software Foundation,
-**	either version 2 of the License, or (at your option) any later version.
+**    ProNoC ( stands for Prototype Network-on-chip)  is free software: 
+**    you can redistribute it and/or modify it under the terms of the GNU
+**    Lesser General Public License as published by the Free Software Foundation,
+**    either version 2 of the License, or (at your option) any later version.
 **
-** 	ProNoC is distributed in the hope that it will be useful, but WITHOUT
-** 	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
-** 	or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
-** 	Public License for more details.
+**     ProNoC is distributed in the hope that it will be useful, but WITHOUT
+**     ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+**     or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
+**     Public License for more details.
 **
-** 	You should have received a copy of the GNU Lesser General Public
-** 	License along with ProNoC. If not, see <http:**www.gnu.org/licenses/>.
+**     You should have received a copy of the GNU Lesser General Public
+**     License along with ProNoC. If not, see <http:**www.gnu.org/licenses/>.
 ******************************************************************************/ 
 
- 
- `include "pronoc_def.v"
+    
+`include "pronoc_def.v"
 /*******************
 *  Tcustom1Rcustom_look_ahead_routing
-*******************/  
+*******************/
 module Tcustom1Rcustom_look_ahead_routing  #(
-	parameter RAw = 3,  
-	parameter EAw = 3,   
-	parameter DSTPw=4  
-)
-(
-	reset,
-	clk,
-	current_r_addr,
-	dest_e_addr,
-	src_e_addr,
-	destport        
+    parameter RAw = 3,
+    parameter EAw = 3,
+    parameter DSTPw=4
+)(
+    reset,
+    clk,
+    current_r_addr,
+    dest_e_addr,
+    src_e_addr,
+    destport
 );
+    input   [RAw-1   :0] current_r_addr;
+    input   [EAw-1   :0] dest_e_addr;
+    input   [EAw-1   :0] src_e_addr;
+    output  [DSTPw-1 :0] destport;
+    input reset,clk;
+    reg [EAw-1   :0] dest_e_addr_delay;
+    reg [EAw-1   :0] src_e_addr_delay;
     
-	input   [RAw-1   :0] current_r_addr;
-	input   [EAw-1   :0] dest_e_addr;
-	input   [EAw-1   :0] src_e_addr;
-	output  [DSTPw-1 :0] destport;	
-	input reset,clk;
-
-	reg [EAw-1   :0] dest_e_addr_delay;
-	reg [EAw-1   :0] src_e_addr_delay;
-
-	always @ (`pronoc_clk_reset_edge )begin 
-        if(`pronoc_reset)begin 
-			dest_e_addr_delay<={EAw{1'b0}};
-			src_e_addr_delay<={EAw{1'b0}};			
-		end else begin 
-			dest_e_addr_delay<=dest_e_addr;
-			src_e_addr_delay<=src_e_addr;					
-		end 	
-	end
-
-	Tcustom1Rcustom_look_ahead_routing_comb  #(
-		.RAw(RAw),  
-		.EAw(EAw),   
-		.DSTPw(DSTPw)  
-	)
-	lkp_cmb
-	(
-		.current_r_addr(current_r_addr),
-		.dest_e_addr(dest_e_addr_delay),
-		.src_e_addr(src_e_addr_delay),
-		.destport(destport)        
-	);
-
+    always @ (`pronoc_clk_reset_edge )begin 
+        if(`pronoc_reset)begin
+            dest_e_addr_delay<={EAw{1'b0}};
+            src_e_addr_delay<={EAw{1'b0}};
+        end else begin 
+            dest_e_addr_delay<=dest_e_addr;
+            src_e_addr_delay<=src_e_addr;
+        end
+    end
+    
+    Tcustom1Rcustom_look_ahead_routing_comb  #(
+        .RAw(RAw),
+        .EAw(EAw),
+        .DSTPw(DSTPw)
+    ) lkp_cmb  (
+        .current_r_addr(current_r_addr),
+        .dest_e_addr(dest_e_addr_delay),
+        .src_e_addr(src_e_addr_delay),
+        .destport(destport)
+    );
+endmodule
 
-	
-endmodule  
- 
 /*******************
 *  Tcustom1Rcustom_look_ahead_routing_comb
-*******************/ 
-  
- module Tcustom1Rcustom_look_ahead_routing_comb  #(
-	parameter RAw = 3,  
-	parameter EAw = 3,   
-	parameter DSTPw=4  
-)
-(
-	current_r_addr,
-	dest_e_addr,
-	src_e_addr,
-	destport        
+*******************/
+module Tcustom1Rcustom_look_ahead_routing_comb  #(
+    parameter RAw = 3,
+    parameter EAw = 3,
+    parameter DSTPw=4
+)(
+    current_r_addr,
+    dest_e_addr,
+    src_e_addr,
+    destport
 );
-    
-	input   [RAw-1   :0] current_r_addr;
-	input   [EAw-1   :0] dest_e_addr;
-	input   [EAw-1   :0] src_e_addr;
-	output reg [DSTPw-1 :0] destport;	
+    input   [RAw-1   :0] current_r_addr;
+    input   [EAw-1   :0] dest_e_addr;
+    input   [EAw-1   :0] src_e_addr;
+    output reg [DSTPw-1 :0] destport;
 
-localparam [EAw-1 : 0]	E0=0;
-localparam [EAw-1 : 0]	E1=1;
-localparam [EAw-1 : 0]	E2=2;
-localparam [EAw-1 : 0]	E3=3;
-localparam [EAw-1 : 0]	E4=4;
-localparam [EAw-1 : 0]	E5=5;
-localparam [EAw-1 : 0]	E6=6;
-localparam [EAw-1 : 0]	E7=7;
-localparam [EAw-1 : 0]	E8=8;
-localparam [EAw-1 : 0]	E9=9;
-localparam [EAw-1 : 0]	E10=10;
-localparam [EAw-1 : 0]	E11=11;
-localparam [EAw-1 : 0]	E12=12;
-localparam [EAw-1 : 0]	E13=13;
-localparam [EAw-1 : 0]	E14=14;
-localparam [EAw-1 : 0]	E15=15;
+localparam [EAw-1 : 0]    E0=0;
+localparam [EAw-1 : 0]    E1=1;
+localparam [EAw-1 : 0]    E2=2;
+localparam [EAw-1 : 0]    E3=3;
+localparam [EAw-1 : 0]    E4=4;
+localparam [EAw-1 : 0]    E5=5;
+localparam [EAw-1 : 0]    E6=6;
+localparam [EAw-1 : 0]    E7=7;
+localparam [EAw-1 : 0]    E8=8;
+localparam [EAw-1 : 0]    E9=9;
+localparam [EAw-1 : 0]    E10=10;
+localparam [EAw-1 : 0]    E11=11;
+localparam [EAw-1 : 0]    E12=12;
+localparam [EAw-1 : 0]    E13=13;
+localparam [EAw-1 : 0]    E14=14;
+localparam [EAw-1 : 0]    E15=15;
 
-        
-	always@(*)begin
-		destport=0;
-		case(current_r_addr) //current_r_addr of each individual router is fixed. So this CASE will be optimized by the synthesizer for each router. 
-		0: begin
-			case({src_e_addr,dest_e_addr})
-			{E0,E9},{E0,E10}: begin 
-				destport= 0; 
-			end
-			{E0,E2},{E0,E3},{E0,E8},{E0,E11},{E0,E12}: begin 
-				destport= 1; 
-			end
-			{E0,E1},{E0,E4},{E0,E5},{E0,E6},{E0,E7},{E0,E13},{E0,E14},{E0,E15}: begin 
-				destport= 2; 
-			end
-			default: begin 
-				destport= {DSTPw{1'bX}};
-			end
-			endcase
-		end//0
-		1: begin
-			case({src_e_addr,dest_e_addr})
-			{E1,E2},{E1,E7},{E2,E7}: begin 
-				destport= 0; 
-			end
-			{E1,E3},{E1,E4},{E1,E5},{E1,E6},{E1,E8},{E1,E9},{E1,E11},{E1,E12},{E1,E13},{E1,E14},{E1,E15},{E2,E9},{E2,E12}: begin 
-				destport= 1; 
-			end
-			{E1,E0},{E1,E10},{E2,E0},{E2,E10}: begin 
-				destport= 2; 
-			end
-			default: begin 
-				destport= {DSTPw{1'bX}};
-			end
-			endcase
-		end//1
-		2: begin
-			case({src_e_addr,dest_e_addr})
-			{E1,E11},{E2,E1},{E2,E11}: begin 
-				destport= 0; 
-			end
-			{E1,E5},{E1,E6},{E1,E13},{E1,E14},{E2,E0},{E2,E4},{E2,E5},{E2,E6},{E2,E7},{E2,E8},{E2,E9},{E2,E10},{E2,E12},{E2,E13},{E2,E14},{E2,E15}: begin 
-				destport= 1; 
-			end
-			{E1,E3},{E2,E3}: begin 
-				destport= 3; 
-			end
-			default: begin 
-				destport= {DSTPw{1'bX}};
-			end
-			endcase
-		end//2
-		3: begin
-			case({src_e_addr,dest_e_addr})
-			{E3,E4},{E3,E11}: begin 
-				destport= 0; 
-			end
-			{E3,E1},{E3,E6},{E3,E7},{E3,E8},{E3,E10},{E3,E12},{E3,E13},{E3,E14}: begin 
-				destport= 1; 
-			end
-			{E3,E2}: begin 
-				destport= 2; 
-			end
-			{E3,E0},{E3,E5},{E3,E9},{E3,E15}: begin 
-				destport= 3; 
-			end
-			default: begin 
-				destport= {DSTPw{1'bX}};
-			end
-			endcase
-		end//3
-		4: begin
-			case({src_e_addr,dest_e_addr})
-			{E3,E13},{E4,E3},{E4,E13},{E5,E3},{E6,E3},{E7,E3},{E8,E3},{E9,E3},{E10,E3},{E12,E3},{E13,E3},{E14,E3},{E15,E3}: begin 
-				destport= 0; 
-			end
-			{E4,E2},{E4,E11},{E4,E14}: begin 
-				destport= 1; 
-			end
-			{E3,E0},{E3,E5},{E3,E9},{E3,E15},{E4,E0},{E4,E5},{E4,E9},{E4,E12},{E4,E15}: begin 
-				destport= 2; 
-			end
-			{E3,E6},{E4,E6}: begin 
-				destport= 3; 
-			end
-			{E3,E1},{E3,E7},{E3,E8},{E3,E14},{E4,E1},{E4,E7},{E4,E8},{E4,E10}: begin 
-				destport= 4; 
-			end
-			default: begin 
-				destport= {DSTPw{1'bX}};
-			end
-			endcase
-		end//4
-		5: begin
-			case({src_e_addr,dest_e_addr})
-			{E0,E6},{E0,E15},{E3,E9},{E3,E15},{E4,E9},{E4,E15},{E5,E6},{E5,E9},{E5,E15},{E6,E9},{E6,E15},{E9,E6},{E9,E15},{E13,E9},{E14,E9},{E15,E9}: begin 
-				destport= 0; 
-			end
-			{E0,E4},{E0,E13},{E4,E12},{E5,E1},{E5,E2},{E5,E3},{E5,E4},{E5,E7},{E5,E8},{E5,E10},{E5,E12},{E5,E13},{E5,E14},{E6,E1},{E6,E7},{E6,E8},{E6,E10},{E6,E12},{E9,E3},{E9,E4},{E9,E13},{E9,E14}: begin 
-				destport= 1; 
-			end
-			{E0,E14},{E5,E11},{E6,E2},{E6,E11},{E6,E14},{E9,E2},{E9,E11}: begin 
-				destport= 2; 
-			end
-			{E3,E0},{E4,E0},{E5,E0},{E6,E0},{E11,E0},{E13,E0},{E15,E0}: begin 
-				destport= 3; 
-			end
-			default: begin 
-				destport= {DSTPw{1'bX}};
-			end
-			endcase
-		end//5
-		6: begin
-			case({src_e_addr,dest_e_addr})
-			{E0,E13},{E3,E5},{E4,E5},{E5,E13},{E6,E5},{E6,E13},{E9,E13}: begin 
-				destport= 0; 
-			end
-			{E3,E15},{E4,E12},{E4,E15},{E6,E1},{E6,E2},{E6,E7},{E6,E8},{E6,E10},{E6,E11},{E6,E12},{E6,E14},{E6,E15}: begin 
-				destport= 1; 
-			end
-			{E0,E4},{E5,E3},{E5,E4},{E6,E3},{E6,E4},{E9,E3},{E9,E4}: begin 
-				destport= 2; 
-			end
-			{E3,E0},{E3,E9},{E4,E0},{E4,E9},{E6,E0},{E6,E9}: begin 
-				destport= 3; 
-			end
-			{E4,E2},{E4,E11},{E4,E14},{E5,E2},{E5,E14},{E9,E14}: begin 
-				destport= 4; 
-			end
-			default: begin 
-				destport= {DSTPw{1'bX}};
-			end
-			endcase
-		end//6
-		7: begin
-			case({src_e_addr,dest_e_addr})
-			{E0,E1},{E1,E8},{E1,E10},{E2,E10},{E3,E1},{E3,E10},{E4,E1},{E4,E10},{E5,E1},{E6,E1},{E7,E1},{E7,E8},{E7,E10},{E8,E1},{E9,E1},{E10,E1},{E11,E1},{E11,E10},{E12,E1},{E13,E1},{E13,E10},{E14,E1},{E14,E10},{E15,E1}: begin 
-				destport= 0; 
-			end
-			{E1,E9},{E1,E12},{E1,E15},{E2,E9},{E2,E12},{E7,E9},{E7,E12}: begin 
-				destport= 1; 
-			end
-			{E1,E4},{E7,E2},{E7,E3},{E7,E4},{E7,E5},{E7,E6},{E7,E11},{E7,E13},{E7,E14},{E7,E15}: begin 
-				destport= 2; 
-			end
-			{E1,E0},{E2,E0},{E7,E0},{E14,E0}: begin 
-				destport= 3; 
-			end
-			default: begin 
-				destport= {DSTPw{1'bX}};
-			end
-			endcase
-		end//7
-		8: begin
-			case({src_e_addr,dest_e_addr})
-			{E1,E12},{E2,E12},{E3,E7},{E4,E7},{E7,E12},{E7,E14},{E8,E7},{E8,E12},{E8,E14},{E9,E7},{E11,E7},{E13,E7},{E14,E7}: begin 
-				destport= 0; 
-			end
-			{E1,E15},{E7,E5},{E7,E15},{E8,E4},{E8,E5},{E8,E15}: begin 
-				destport= 1; 
-			end
-			{E1,E4},{E1,E9},{E2,E9},{E3,E10},{E4,E10},{E7,E3},{E7,E4},{E7,E6},{E7,E9},{E7,E13},{E8,E0},{E8,E3},{E8,E6},{E8,E9},{E8,E13},{E11,E10},{E13,E10},{E14,E0},{E14,E10}: begin 
-				destport= 2; 
-			end
-			{E3,E1},{E4,E1},{E8,E1},{E8,E10},{E9,E1},{E11,E1},{E13,E1},{E14,E1}: begin 
-				destport= 3; 
-			end
-			{E7,E2},{E7,E11},{E8,E2},{E8,E11}: begin 
-				destport= 4; 
-			end
-			default: begin 
-				destport= {DSTPw{1'bX}};
-			end
-			endcase
-		end//8
-		9: begin
-			case({src_e_addr,dest_e_addr})
-			{E0,E5},{E0,E12},{E3,E0},{E4,E0},{E5,E0},{E6,E0},{E8,E0},{E9,E0},{E9,E5},{E9,E12},{E11,E0},{E12,E0},{E13,E0},{E15,E0}: begin 
-				destport= 0; 
-			end
-			{E0,E11},{E0,E14},{E0,E15},{E9,E2},{E9,E11},{E9,E15}: begin 
-				destport= 1; 
-			end
-			{E0,E4},{E0,E6},{E0,E13},{E9,E3},{E9,E4},{E9,E6},{E9,E13},{E9,E14}: begin 
-				destport= 2; 
-			end
-			{E9,E10}: begin 
-				destport= 3; 
-			end
-			{E0,E8},{E9,E1},{E9,E7},{E9,E8}: begin 
-				destport= 4; 
-			end
-			default: begin 
-				destport= {DSTPw{1'bX}};
-			end
-			endcase
-		end//9
-		10: begin
-			case({src_e_addr,dest_e_addr})
-			{E0,E7},{E1,E0},{E2,E0},{E5,E7},{E6,E7},{E7,E0},{E10,E0},{E10,E7},{E10,E12},{E12,E7},{E14,E0},{E15,E7}: begin 
-				destport= 0; 
-			end
-			{E0,E2},{E0,E3},{E10,E2},{E10,E3},{E10,E4},{E10,E5},{E10,E6},{E10,E11},{E10,E13},{E10,E14},{E10,E15}: begin 
-				destport= 1; 
-			end
-			{E10,E9}: begin 
-				destport= 2; 
-			end
-			{E0,E1},{E5,E1},{E6,E1},{E10,E1},{E12,E1},{E15,E1}: begin 
-				destport= 3; 
-			end
-			{E10,E8}: begin 
-				destport= 4; 
-			end
-			default: begin 
-				destport= {DSTPw{1'bX}};
-			end
-			endcase
-		end//10
-		11: begin
-			case({src_e_addr,dest_e_addr})
-			{E0,E2},{E0,E3},{E1,E3},{E1,E14},{E2,E3},{E2,E14},{E3,E2},{E4,E2},{E5,E2},{E6,E2},{E7,E2},{E8,E2},{E9,E2},{E10,E2},{E11,E2},{E11,E3},{E11,E14},{E12,E2},{E13,E2},{E14,E2},{E15,E2}: begin 
-				destport= 0; 
-			end
-			{E1,E5},{E1,E13},{E2,E5},{E2,E15},{E3,E12},{E11,E0},{E11,E5},{E11,E9},{E11,E12},{E11,E15}: begin 
-				destport= 1; 
-			end
-			{E1,E6},{E2,E4},{E2,E6},{E2,E13},{E11,E4},{E11,E6},{E11,E13}: begin 
-				destport= 2; 
-			end
-			{E2,E8},{E3,E10},{E11,E1},{E11,E7},{E11,E8},{E11,E10}: begin 
-				destport= 3; 
-			end
-			default: begin 
-				destport= {DSTPw{1'bX}};
-			end
-			endcase
-		end//11
-		12: begin
-			case({src_e_addr,dest_e_addr})
-			{E0,E8},{E1,E9},{E1,E15},{E2,E9},{E5,E8},{E5,E10},{E6,E8},{E6,E10},{E7,E9},{E8,E9},{E8,E10},{E9,E8},{E9,E10},{E10,E8},{E10,E9},{E10,E15},{E11,E9},{E12,E8},{E12,E9},{E12,E10},{E12,E15},{E15,E8},{E15,E10}: begin 
-				destport= 0; 
-			end
-			{E0,E2},{E0,E3},{E0,E11},{E5,E1},{E5,E7},{E6,E1},{E6,E7},{E10,E2},{E10,E11},{E10,E14},{E12,E1},{E12,E2},{E12,E7},{E12,E11},{E12,E14},{E15,E1},{E15,E7}: begin 
-				destport= 2; 
-			end
-			{E8,E0},{E8,E4},{E9,E1},{E9,E7},{E10,E3},{E10,E4},{E10,E6},{E10,E13},{E12,E0},{E12,E3},{E12,E4},{E12,E6},{E12,E13}: begin 
-				destport= 3; 
-			end
-			{E8,E5},{E10,E5},{E12,E5}: begin 
-				destport= 4; 
-			end
-			default: begin 
-				destport= {DSTPw{1'bX}};
-			end
-			endcase
-		end//12
-		13: begin
-			case({src_e_addr,dest_e_addr})
-			{E0,E4},{E1,E4},{E1,E6},{E2,E4},{E2,E6},{E3,E6},{E3,E14},{E4,E6},{E4,E14},{E5,E4},{E5,E14},{E6,E4},{E7,E4},{E7,E6},{E8,E4},{E8,E6},{E9,E4},{E9,E14},{E10,E4},{E10,E6},{E11,E4},{E11,E6},{E12,E4},{E12,E6},{E13,E4},{E13,E6},{E13,E14},{E14,E4},{E14,E6},{E15,E4},{E15,E6}: begin 
-				destport= 0; 
-			end
-			{E13,E0},{E13,E5},{E13,E9},{E13,E12},{E13,E15}: begin 
-				destport= 1; 
-			end
-			{E5,E3},{E6,E3},{E7,E3},{E8,E3},{E9,E3},{E10,E3},{E12,E3},{E13,E3},{E14,E3},{E15,E3}: begin 
-				destport= 2; 
-			end
-			{E3,E1},{E3,E7},{E3,E8},{E4,E1},{E4,E7},{E4,E8},{E4,E10},{E13,E1},{E13,E7},{E13,E8},{E13,E10}: begin 
-				destport= 3; 
-			end
-			{E4,E2},{E4,E11},{E5,E2},{E13,E2},{E13,E11}: begin 
-				destport= 4; 
-			end
-			default: begin 
-				destport= {DSTPw{1'bX}};
-			end
-			endcase
-		end//13
-		14: begin
-			case({src_e_addr,dest_e_addr})
-			{E0,E11},{E2,E8},{E2,E13},{E2,E15},{E3,E8},{E4,E8},{E4,E11},{E5,E11},{E6,E11},{E7,E11},{E7,E13},{E7,E15},{E8,E11},{E8,E13},{E8,E15},{E9,E11},{E10,E11},{E11,E8},{E11,E13},{E11,E15},{E12,E11},{E13,E8},{E13,E11},{E13,E15},{E14,E8},{E14,E11},{E14,E13},{E14,E15},{E15,E11}: begin 
-				destport= 0; 
-			end
-			{E3,E12},{E11,E9},{E11,E12},{E13,E12},{E14,E12}: begin 
-				destport= 1; 
-			end
-			{E0,E2},{E1,E4},{E2,E4},{E4,E2},{E5,E2},{E6,E2},{E7,E2},{E7,E3},{E7,E4},{E8,E2},{E8,E3},{E9,E2},{E10,E2},{E11,E4},{E12,E2},{E13,E2},{E14,E2},{E14,E3},{E14,E4},{E15,E2}: begin 
-				destport= 2; 
-			end
-			{E0,E3},{E1,E6},{E1,E13},{E2,E6},{E3,E1},{E3,E7},{E3,E10},{E4,E1},{E4,E7},{E4,E10},{E7,E6},{E8,E6},{E11,E1},{E11,E6},{E11,E7},{E11,E10},{E13,E1},{E13,E7},{E13,E10},{E14,E0},{E14,E1},{E14,E6},{E14,E7},{E14,E10}: begin 
-				destport= 3; 
-			end
-			{E1,E5},{E2,E5},{E7,E5},{E11,E0},{E11,E5},{E13,E0},{E13,E5},{E13,E9},{E14,E5},{E14,E9}: begin 
-				destport= 4; 
-			end
-			default: begin 
-				destport= {DSTPw{1'bX}};
-			end
-			endcase
-		end//14
-		15: begin
-			case({src_e_addr,dest_e_addr})
-			{E0,E14},{E1,E5},{E1,E13},{E2,E5},{E3,E12},{E4,E12},{E5,E12},{E6,E12},{E6,E14},{E7,E5},{E8,E5},{E10,E5},{E10,E13},{E10,E14},{E11,E5},{E11,E12},{E12,E5},{E12,E13},{E12,E14},{E13,E5},{E13,E12},{E14,E5},{E14,E12},{E15,E5},{E15,E12},{E15,E13},{E15,E14}: begin 
-				destport= 0; 
-			end
-			{E8,E4},{E10,E3},{E10,E4},{E11,E9},{E12,E3},{E12,E4},{E15,E3},{E15,E4}: begin 
-				destport= 2; 
-			end
-			{E5,E1},{E5,E7},{E5,E10},{E6,E1},{E6,E7},{E6,E10},{E10,E6},{E11,E0},{E12,E6},{E13,E0},{E13,E9},{E14,E9},{E15,E0},{E15,E1},{E15,E6},{E15,E7},{E15,E9},{E15,E10}: begin 
-				destport= 3; 
-			end
-			{E0,E2},{E0,E3},{E0,E11},{E5,E8},{E5,E11},{E6,E2},{E6,E8},{E6,E11},{E9,E2},{E9,E11},{E10,E2},{E10,E11},{E12,E2},{E12,E11},{E15,E2},{E15,E8},{E15,E11}: begin 
-				destport= 4; 
-			end
-			default: begin 
-				destport= {DSTPw{1'bX}};
-			end
-			endcase
-		end//15
-		default: begin 
-			destport= {DSTPw{1'bX}};
-		end
-		endcase
-	end
-  
 
-	
-endmodule  
+    always@(*)begin
+        destport=0;
+        case(current_r_addr) //current_r_addr of each individual router is fixed. So this CASE will be optimized by the synthesizer for each router. 
+        0: begin
+            case({src_e_addr,dest_e_addr})
+            {E0,E9},{E0,E10}: begin 
+                destport= 0; 
+            end
+            {E0,E2},{E0,E3},{E0,E8},{E0,E11},{E0,E12}: begin 
+                destport= 1; 
+            end
+            {E0,E1},{E0,E4},{E0,E5},{E0,E6},{E0,E7},{E0,E13},{E0,E14},{E0,E15}: begin 
+                destport= 2; 
+            end
+            default: begin 
+                destport= {DSTPw{1'bX}};
+            end
+            endcase
+        end//0
+        1: begin
+            case({src_e_addr,dest_e_addr})
+            {E1,E2},{E1,E7},{E2,E7}: begin 
+                destport= 0; 
+            end
+            {E1,E3},{E1,E4},{E1,E5},{E1,E6},{E1,E8},{E1,E9},{E1,E11},{E1,E12},{E1,E13},{E1,E14},{E1,E15},{E2,E9},{E2,E12}: begin 
+                destport= 1; 
+            end
+            {E1,E0},{E1,E10},{E2,E0},{E2,E10}: begin 
+                destport= 2; 
+            end
+            default: begin 
+                destport= {DSTPw{1'bX}};
+            end
+            endcase
+        end//1
+        2: begin
+            case({src_e_addr,dest_e_addr})
+            {E1,E11},{E2,E1},{E2,E11}: begin 
+                destport= 0; 
+            end
+            {E1,E5},{E1,E6},{E1,E13},{E1,E14},{E2,E0},{E2,E4},{E2,E5},{E2,E6},{E2,E7},{E2,E8},{E2,E9},{E2,E10},{E2,E12},{E2,E13},{E2,E14},{E2,E15}: begin 
+                destport= 1; 
+            end
+            {E1,E3},{E2,E3}: begin 
+                destport= 3; 
+            end
+            default: begin 
+                destport= {DSTPw{1'bX}};
+            end
+            endcase
+        end//2
+        3: begin
+            case({src_e_addr,dest_e_addr})
+            {E3,E4},{E3,E11}: begin 
+                destport= 0; 
+            end
+            {E3,E1},{E3,E6},{E3,E7},{E3,E8},{E3,E10},{E3,E12},{E3,E13},{E3,E14}: begin 
+                destport= 1; 
+            end
+            {E3,E2}: begin 
+                destport= 2; 
+            end
+            {E3,E0},{E3,E5},{E3,E9},{E3,E15}: begin 
+                destport= 3; 
+            end
+            default: begin 
+                destport= {DSTPw{1'bX}};
+            end
+            endcase
+        end//3
+        4: begin
+            case({src_e_addr,dest_e_addr})
+            {E3,E13},{E4,E3},{E4,E13},{E5,E3},{E6,E3},{E7,E3},{E8,E3},{E9,E3},{E10,E3},{E12,E3},{E13,E3},{E14,E3},{E15,E3}: begin 
+                destport= 0; 
+            end
+            {E4,E2},{E4,E11},{E4,E14}: begin 
+                destport= 1; 
+            end
+            {E3,E0},{E3,E5},{E3,E9},{E3,E15},{E4,E0},{E4,E5},{E4,E9},{E4,E12},{E4,E15}: begin 
+                destport= 2; 
+            end
+            {E3,E6},{E4,E6}: begin 
+                destport= 3; 
+            end
+            {E3,E1},{E3,E7},{E3,E8},{E3,E14},{E4,E1},{E4,E7},{E4,E8},{E4,E10}: begin 
+                destport= 4; 
+            end
+            default: begin 
+                destport= {DSTPw{1'bX}};
+            end
+            endcase
+        end//4
+        5: begin
+            case({src_e_addr,dest_e_addr})
+            {E0,E6},{E0,E15},{E3,E9},{E3,E15},{E4,E9},{E4,E15},{E5,E6},{E5,E9},{E5,E15},{E6,E9},{E6,E15},{E9,E6},{E9,E15},{E13,E9},{E14,E9},{E15,E9}: begin 
+                destport= 0; 
+            end
+            {E0,E4},{E0,E13},{E4,E12},{E5,E1},{E5,E2},{E5,E3},{E5,E4},{E5,E7},{E5,E8},{E5,E10},{E5,E12},{E5,E13},{E5,E14},{E6,E1},{E6,E7},{E6,E8},{E6,E10},{E6,E12},{E9,E3},{E9,E4},{E9,E13},{E9,E14}: begin 
+                destport= 1; 
+            end
+            {E0,E14},{E5,E11},{E6,E2},{E6,E11},{E6,E14},{E9,E2},{E9,E11}: begin 
+                destport= 2; 
+            end
+            {E3,E0},{E4,E0},{E5,E0},{E6,E0},{E11,E0},{E13,E0},{E15,E0}: begin 
+                destport= 3; 
+            end
+            default: begin 
+                destport= {DSTPw{1'bX}};
+            end
+            endcase
+        end//5
+        6: begin
+            case({src_e_addr,dest_e_addr})
+            {E0,E13},{E3,E5},{E4,E5},{E5,E13},{E6,E5},{E6,E13},{E9,E13}: begin 
+                destport= 0; 
+            end
+            {E3,E15},{E4,E12},{E4,E15},{E6,E1},{E6,E2},{E6,E7},{E6,E8},{E6,E10},{E6,E11},{E6,E12},{E6,E14},{E6,E15}: begin 
+                destport= 1; 
+            end
+            {E0,E4},{E5,E3},{E5,E4},{E6,E3},{E6,E4},{E9,E3},{E9,E4}: begin 
+                destport= 2; 
+            end
+            {E3,E0},{E3,E9},{E4,E0},{E4,E9},{E6,E0},{E6,E9}: begin 
+                destport= 3; 
+            end
+            {E4,E2},{E4,E11},{E4,E14},{E5,E2},{E5,E14},{E9,E14}: begin 
+                destport= 4; 
+            end
+            default: begin 
+                destport= {DSTPw{1'bX}};
+            end
+            endcase
+        end//6
+        7: begin
+            case({src_e_addr,dest_e_addr})
+            {E0,E1},{E1,E8},{E1,E10},{E2,E10},{E3,E1},{E3,E10},{E4,E1},{E4,E10},{E5,E1},{E6,E1},{E7,E1},{E7,E8},{E7,E10},{E8,E1},{E9,E1},{E10,E1},{E11,E1},{E11,E10},{E12,E1},{E13,E1},{E13,E10},{E14,E1},{E14,E10},{E15,E1}: begin 
+                destport= 0; 
+            end
+            {E1,E9},{E1,E12},{E1,E15},{E2,E9},{E2,E12},{E7,E9},{E7,E12}: begin 
+                destport= 1; 
+            end
+            {E1,E4},{E7,E2},{E7,E3},{E7,E4},{E7,E5},{E7,E6},{E7,E11},{E7,E13},{E7,E14},{E7,E15}: begin 
+                destport= 2; 
+            end
+            {E1,E0},{E2,E0},{E7,E0},{E14,E0}: begin 
+                destport= 3; 
+            end
+            default: begin 
+                destport= {DSTPw{1'bX}};
+            end
+            endcase
+        end//7
+        8: begin
+            case({src_e_addr,dest_e_addr})
+            {E1,E12},{E2,E12},{E3,E7},{E4,E7},{E7,E12},{E7,E14},{E8,E7},{E8,E12},{E8,E14},{E9,E7},{E11,E7},{E13,E7},{E14,E7}: begin 
+                destport= 0; 
+            end
+            {E1,E15},{E7,E5},{E7,E15},{E8,E4},{E8,E5},{E8,E15}: begin 
+                destport= 1; 
+            end
+            {E1,E4},{E1,E9},{E2,E9},{E3,E10},{E4,E10},{E7,E3},{E7,E4},{E7,E6},{E7,E9},{E7,E13},{E8,E0},{E8,E3},{E8,E6},{E8,E9},{E8,E13},{E11,E10},{E13,E10},{E14,E0},{E14,E10}: begin 
+                destport= 2; 
+            end
+            {E3,E1},{E4,E1},{E8,E1},{E8,E10},{E9,E1},{E11,E1},{E13,E1},{E14,E1}: begin 
+                destport= 3; 
+            end
+            {E7,E2},{E7,E11},{E8,E2},{E8,E11}: begin 
+                destport= 4; 
+            end
+            default: begin 
+                destport= {DSTPw{1'bX}};
+            end
+            endcase
+        end//8
+        9: begin
+            case({src_e_addr,dest_e_addr})
+            {E0,E5},{E0,E12},{E3,E0},{E4,E0},{E5,E0},{E6,E0},{E8,E0},{E9,E0},{E9,E5},{E9,E12},{E11,E0},{E12,E0},{E13,E0},{E15,E0}: begin 
+                destport= 0; 
+            end
+            {E0,E11},{E0,E14},{E0,E15},{E9,E2},{E9,E11},{E9,E15}: begin 
+                destport= 1; 
+            end
+            {E0,E4},{E0,E6},{E0,E13},{E9,E3},{E9,E4},{E9,E6},{E9,E13},{E9,E14}: begin 
+                destport= 2; 
+            end
+            {E9,E10}: begin 
+                destport= 3; 
+            end
+            {E0,E8},{E9,E1},{E9,E7},{E9,E8}: begin 
+                destport= 4; 
+            end
+            default: begin 
+                destport= {DSTPw{1'bX}};
+            end
+            endcase
+        end//9
+        10: begin
+            case({src_e_addr,dest_e_addr})
+            {E0,E7},{E1,E0},{E2,E0},{E5,E7},{E6,E7},{E7,E0},{E10,E0},{E10,E7},{E10,E12},{E12,E7},{E14,E0},{E15,E7}: begin 
+                destport= 0; 
+            end
+            {E0,E2},{E0,E3},{E10,E2},{E10,E3},{E10,E4},{E10,E5},{E10,E6},{E10,E11},{E10,E13},{E10,E14},{E10,E15}: begin 
+                destport= 1; 
+            end
+            {E10,E9}: begin 
+                destport= 2; 
+            end
+            {E0,E1},{E5,E1},{E6,E1},{E10,E1},{E12,E1},{E15,E1}: begin 
+                destport= 3; 
+            end
+            {E10,E8}: begin 
+                destport= 4; 
+            end
+            default: begin 
+                destport= {DSTPw{1'bX}};
+            end
+            endcase
+        end//10
+        11: begin
+            case({src_e_addr,dest_e_addr})
+            {E0,E2},{E0,E3},{E1,E3},{E1,E14},{E2,E3},{E2,E14},{E3,E2},{E4,E2},{E5,E2},{E6,E2},{E7,E2},{E8,E2},{E9,E2},{E10,E2},{E11,E2},{E11,E3},{E11,E14},{E12,E2},{E13,E2},{E14,E2},{E15,E2}: begin 
+                destport= 0; 
+            end
+            {E1,E5},{E1,E13},{E2,E5},{E2,E15},{E3,E12},{E11,E0},{E11,E5},{E11,E9},{E11,E12},{E11,E15}: begin 
+                destport= 1; 
+            end
+            {E1,E6},{E2,E4},{E2,E6},{E2,E13},{E11,E4},{E11,E6},{E11,E13}: begin 
+                destport= 2; 
+            end
+            {E2,E8},{E3,E10},{E11,E1},{E11,E7},{E11,E8},{E11,E10}: begin 
+                destport= 3; 
+            end
+            default: begin 
+                destport= {DSTPw{1'bX}};
+            end
+            endcase
+        end//11
+        12: begin
+            case({src_e_addr,dest_e_addr})
+            {E0,E8},{E1,E9},{E1,E15},{E2,E9},{E5,E8},{E5,E10},{E6,E8},{E6,E10},{E7,E9},{E8,E9},{E8,E10},{E9,E8},{E9,E10},{E10,E8},{E10,E9},{E10,E15},{E11,E9},{E12,E8},{E12,E9},{E12,E10},{E12,E15},{E15,E8},{E15,E10}: begin 
+                destport= 0; 
+            end
+            {E0,E2},{E0,E3},{E0,E11},{E5,E1},{E5,E7},{E6,E1},{E6,E7},{E10,E2},{E10,E11},{E10,E14},{E12,E1},{E12,E2},{E12,E7},{E12,E11},{E12,E14},{E15,E1},{E15,E7}: begin 
+                destport= 2; 
+            end
+            {E8,E0},{E8,E4},{E9,E1},{E9,E7},{E10,E3},{E10,E4},{E10,E6},{E10,E13},{E12,E0},{E12,E3},{E12,E4},{E12,E6},{E12,E13}: begin 
+                destport= 3; 
+            end
+            {E8,E5},{E10,E5},{E12,E5}: begin 
+                destport= 4; 
+            end
+            default: begin 
+                destport= {DSTPw{1'bX}};
+            end
+            endcase
+        end//12
+        13: begin
+            case({src_e_addr,dest_e_addr})
+            {E0,E4},{E1,E4},{E1,E6},{E2,E4},{E2,E6},{E3,E6},{E3,E14},{E4,E6},{E4,E14},{E5,E4},{E5,E14},{E6,E4},{E7,E4},{E7,E6},{E8,E4},{E8,E6},{E9,E4},{E9,E14},{E10,E4},{E10,E6},{E11,E4},{E11,E6},{E12,E4},{E12,E6},{E13,E4},{E13,E6},{E13,E14},{E14,E4},{E14,E6},{E15,E4},{E15,E6}: begin 
+                destport= 0; 
+            end
+            {E13,E0},{E13,E5},{E13,E9},{E13,E12},{E13,E15}: begin 
+                destport= 1; 
+            end
+            {E5,E3},{E6,E3},{E7,E3},{E8,E3},{E9,E3},{E10,E3},{E12,E3},{E13,E3},{E14,E3},{E15,E3}: begin 
+                destport= 2; 
+            end
+            {E3,E1},{E3,E7},{E3,E8},{E4,E1},{E4,E7},{E4,E8},{E4,E10},{E13,E1},{E13,E7},{E13,E8},{E13,E10}: begin 
+                destport= 3; 
+            end
+            {E4,E2},{E4,E11},{E5,E2},{E13,E2},{E13,E11}: begin 
+                destport= 4; 
+            end
+            default: begin 
+                destport= {DSTPw{1'bX}};
+            end
+            endcase
+        end//13
+        14: begin
+            case({src_e_addr,dest_e_addr})
+            {E0,E11},{E2,E8},{E2,E13},{E2,E15},{E3,E8},{E4,E8},{E4,E11},{E5,E11},{E6,E11},{E7,E11},{E7,E13},{E7,E15},{E8,E11},{E8,E13},{E8,E15},{E9,E11},{E10,E11},{E11,E8},{E11,E13},{E11,E15},{E12,E11},{E13,E8},{E13,E11},{E13,E15},{E14,E8},{E14,E11},{E14,E13},{E14,E15},{E15,E11}: begin 
+                destport= 0; 
+            end
+            {E3,E12},{E11,E9},{E11,E12},{E13,E12},{E14,E12}: begin 
+                destport= 1; 
+            end
+            {E0,E2},{E1,E4},{E2,E4},{E4,E2},{E5,E2},{E6,E2},{E7,E2},{E7,E3},{E7,E4},{E8,E2},{E8,E3},{E9,E2},{E10,E2},{E11,E4},{E12,E2},{E13,E2},{E14,E2},{E14,E3},{E14,E4},{E15,E2}: begin 
+                destport= 2; 
+            end
+            {E0,E3},{E1,E6},{E1,E13},{E2,E6},{E3,E1},{E3,E7},{E3,E10},{E4,E1},{E4,E7},{E4,E10},{E7,E6},{E8,E6},{E11,E1},{E11,E6},{E11,E7},{E11,E10},{E13,E1},{E13,E7},{E13,E10},{E14,E0},{E14,E1},{E14,E6},{E14,E7},{E14,E10}: begin 
+                destport= 3; 
+            end
+            {E1,E5},{E2,E5},{E7,E5},{E11,E0},{E11,E5},{E13,E0},{E13,E5},{E13,E9},{E14,E5},{E14,E9}: begin 
+                destport= 4; 
+            end
+            default: begin 
+                destport= {DSTPw{1'bX}};
+            end
+            endcase
+        end//14
+        15: begin
+            case({src_e_addr,dest_e_addr})
+            {E0,E14},{E1,E5},{E1,E13},{E2,E5},{E3,E12},{E4,E12},{E5,E12},{E6,E12},{E6,E14},{E7,E5},{E8,E5},{E10,E5},{E10,E13},{E10,E14},{E11,E5},{E11,E12},{E12,E5},{E12,E13},{E12,E14},{E13,E5},{E13,E12},{E14,E5},{E14,E12},{E15,E5},{E15,E12},{E15,E13},{E15,E14}: begin 
+                destport= 0; 
+            end
+            {E8,E4},{E10,E3},{E10,E4},{E11,E9},{E12,E3},{E12,E4},{E15,E3},{E15,E4}: begin 
+                destport= 2; 
+            end
+            {E5,E1},{E5,E7},{E5,E10},{E6,E1},{E6,E7},{E6,E10},{E10,E6},{E11,E0},{E12,E6},{E13,E0},{E13,E9},{E14,E9},{E15,E0},{E15,E1},{E15,E6},{E15,E7},{E15,E9},{E15,E10}: begin 
+                destport= 3; 
+            end
+            {E0,E2},{E0,E3},{E0,E11},{E5,E8},{E5,E11},{E6,E2},{E6,E8},{E6,E11},{E9,E2},{E9,E11},{E10,E2},{E10,E11},{E12,E2},{E12,E11},{E15,E2},{E15,E8},{E15,E11}: begin 
+                destport= 4; 
+            end
+            default: begin 
+                destport= {DSTPw{1'bX}};
+            end
+            endcase
+        end//15
+        default: begin 
+            destport= {DSTPw{1'bX}};
+        end
+        endcase
+    end
 
 
+endmodule
diff --git a/mpsoc/rtl/src_topology/custom1/Tcustom1Rcustom_look_ahead_routing_genvar.v b/mpsoc/rtl/src_topology/custom1/Tcustom1Rcustom_look_ahead_routing_genvar.v
index 4902d38..0116eb1 100644
--- a/mpsoc/rtl/src_topology/custom1/Tcustom1Rcustom_look_ahead_routing_genvar.v
+++ b/mpsoc/rtl/src_topology/custom1/Tcustom1Rcustom_look_ahead_routing_genvar.v
@@ -1,462 +1,445 @@
 
 /**************************************************************************
-**	WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT ARE LIKELY TO BE
-**	OVERWRITTEN AND LOST. Rename this file if you wish to do any modification.
+**    WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT ARE LIKELY TO BE
+**    OVERWRITTEN AND LOST. Rename this file if you wish to do any modification.
 ****************************************************************************/
 
 
 /**********************************************************************
-**	File: /home/alireza/work/git/pronoc/mpsoc/rtl/src_topology/custom1/Tcustom1Rcustom_look_ahead_routing_genvar.v
+**    File: /home/alireza/work/git/ProNoC-repos/github-pronoc/mpsoc/rtl/src_topology/custom1/Tcustom1Rcustom_look_ahead_routing_genvar.v
 **    
-**	Copyright (C) 2014-2021  Alireza Monemi
+**    Copyright (C) 2014-2022  Alireza Monemi
 **    
-**	This file is part of ProNoC 2.1.0 
+**    This file is part of ProNoC 2.2.0 
 **
-**	ProNoC ( stands for Prototype Network-on-chip)  is free software: 
-**	you can redistribute it and/or modify it under the terms of the GNU
-**	Lesser General Public License as published by the Free Software Foundation,
-**	either version 2 of the License, or (at your option) any later version.
+**    ProNoC ( stands for Prototype Network-on-chip)  is free software: 
+**    you can redistribute it and/or modify it under the terms of the GNU
+**    Lesser General Public License as published by the Free Software Foundation,
+**    either version 2 of the License, or (at your option) any later version.
 **
-** 	ProNoC is distributed in the hope that it will be useful, but WITHOUT
-** 	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
-** 	or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
-** 	Public License for more details.
+**     ProNoC is distributed in the hope that it will be useful, but WITHOUT
+**     ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+**     or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
+**     Public License for more details.
 **
-** 	You should have received a copy of the GNU Lesser General Public
-** 	License along with ProNoC. If not, see <http:**www.gnu.org/licenses/>.
+**     You should have received a copy of the GNU Lesser General Public
+**     License along with ProNoC. If not, see <http:**www.gnu.org/licenses/>.
 ******************************************************************************/ 
 
- `include "pronoc_def.v"
- 
+`include "pronoc_def.v"
 /*****************************
-*	Tcustom1Rcustom_look_ahead_routing_genvar
+*    Tcustom1Rcustom_look_ahead_routing_genvar
 ******************************/ 
 module Tcustom1Rcustom_look_ahead_routing_genvar  #(
-	parameter RAw = 3,  
-	parameter EAw = 3,   
-	parameter DSTPw=4,
-	parameter CURRENT_R_ADDR=0
-)
-(
-	dest_e_addr,
-	src_e_addr,
-	destport,
-	reset,
-	clk        
+    parameter RAw = 3,  
+    parameter EAw = 3,   
+    parameter DSTPw=4,
+    parameter CURRENT_R_ADDR=0
+)(
+    dest_e_addr,
+    src_e_addr,
+    destport,
+    reset,
+    clk
 );
-
-	input   [EAw-1   :0] dest_e_addr;
-	input   [EAw-1   :0] src_e_addr;
-	output  [DSTPw-1 :0] destport;
-	input reset,clk;
-
-	reg [EAw-1   :0] dest_e_addr_delay;
-	reg [EAw-1   :0] src_e_addr_delay;
-
-	 always @ (`pronoc_clk_reset_edge )begin 
+    
+    input   [EAw-1   :0] dest_e_addr;
+    input   [EAw-1   :0] src_e_addr;
+    output  [DSTPw-1 :0] destport;
+    input reset,clk;
+    
+    reg [EAw-1   :0] dest_e_addr_delay;
+    reg [EAw-1   :0] src_e_addr_delay;
+    
+    always @ (`pronoc_clk_reset_edge )begin 
         if(`pronoc_reset) begin 
-			dest_e_addr_delay<={EAw{1'b0}};
-			src_e_addr_delay<={EAw{1'b0}};			
-		end else begin 
-			dest_e_addr_delay<=dest_e_addr;
-			src_e_addr_delay<=src_e_addr;					
-		end 	
-	end
-
-	custom1_look_ahead_routing_genvar_comb  #(
-		.RAw(RAw),  
-		.EAw(EAw),   
-		.DSTPw(DSTPw),
-		.CURRENT_R_ADDR(CURRENT_R_ADDR)  
-	)
-	lkp_cmb
-	(
-		
-		.dest_e_addr(dest_e_addr_delay),
-		.src_e_addr(src_e_addr_delay),
-		.destport(destport)        
-	);
+            dest_e_addr_delay<={EAw{1'b0}};
+            src_e_addr_delay<={EAw{1'b0}};
+        end else begin 
+            dest_e_addr_delay<=dest_e_addr;
+            src_e_addr_delay<=src_e_addr;
+        end
+    end
+    Tcustom1Rcustom_look_ahead_routing_genvar_comb  #(
+        .RAw(RAw),
+        .EAw(EAw),
+        .DSTPw(DSTPw),
+        .CURRENT_R_ADDR(CURRENT_R_ADDR)
+    ) lkp_cmb (
+        .dest_e_addr(dest_e_addr_delay),
+        .src_e_addr(src_e_addr_delay),
+        .destport(destport)
+    );
+endmodule
 
-
-	
-endmodule   
- 
 /*******************
 * Tcustom1Rcustom_look_ahead_routing_genvar_comb
 ********************/ 
-  
- 
- module Tcustom1Rcustom_look_ahead_routing_genvar_comb  #(
-	parameter RAw = 3,  
-	parameter EAw = 3,   
-	parameter DSTPw=4,
-	parameter CURRENT_R_ADDR=0
-)
-(
-	dest_e_addr,
-	src_e_addr,
-	destport        
+module Tcustom1Rcustom_look_ahead_routing_genvar_comb  #(
+    parameter RAw = 3,
+    parameter EAw = 3,
+    parameter DSTPw=4,
+    parameter CURRENT_R_ADDR=0
+) (
+    dest_e_addr,
+    src_e_addr,
+    destport
 );
-
-	input   [EAw-1   :0] dest_e_addr;
-	input   [EAw-1   :0] src_e_addr;
-	output  reg [DSTPw-1 :0] destport;
-
-localparam [EAw-1 : 0]	E0=0;
-localparam [EAw-1 : 0]	E1=1;
-localparam [EAw-1 : 0]	E2=2;
-localparam [EAw-1 : 0]	E3=3;
-localparam [EAw-1 : 0]	E4=4;
-localparam [EAw-1 : 0]	E5=5;
-localparam [EAw-1 : 0]	E6=6;
-localparam [EAw-1 : 0]	E7=7;
-localparam [EAw-1 : 0]	E8=8;
-localparam [EAw-1 : 0]	E9=9;
-localparam [EAw-1 : 0]	E10=10;
-localparam [EAw-1 : 0]	E11=11;
-localparam [EAw-1 : 0]	E12=12;
-localparam [EAw-1 : 0]	E13=13;
-localparam [EAw-1 : 0]	E14=14;
-localparam [EAw-1 : 0]	E15=15;
-
-        
-	generate
-	if(CURRENT_R_ADDR == 0) begin :R0
-		always@(*)begin	
-			destport= 0; 
-			case({src_e_addr,dest_e_addr})
-			{E0,E9},{E0,E10}: begin 
-				destport= 0; 
-			end
-			{E0,E2},{E0,E3},{E0,E8},{E0,E11},{E0,E12}: begin 
-				destport= 1; 
-			end
-			{E0,E1},{E0,E4},{E0,E5},{E0,E6},{E0,E7},{E0,E13},{E0,E14},{E0,E15}: begin 
-				destport= 2; 
-			end
-			endcase
-		end
-	end//R0
-
-	if(CURRENT_R_ADDR == 1) begin :R1
-		always@(*)begin	
-			destport= 0; 
-			case({src_e_addr,dest_e_addr})
-			{E1,E2},{E1,E7},{E2,E7}: begin 
-				destport= 0; 
-			end
-			{E1,E3},{E1,E4},{E1,E5},{E1,E6},{E1,E8},{E1,E9},{E1,E11},{E1,E12},{E1,E13},{E1,E14},{E1,E15},{E2,E9},{E2,E12}: begin 
-				destport= 1; 
-			end
-			{E1,E0},{E1,E10},{E2,E0},{E2,E10}: begin 
-				destport= 2; 
-			end
-			endcase
-		end
-	end//R1
-
-	if(CURRENT_R_ADDR == 2) begin :R2
-		always@(*)begin	
-			destport= 0; 
-			case({src_e_addr,dest_e_addr})
-			{E1,E11},{E2,E1},{E2,E11}: begin 
-				destport= 0; 
-			end
-			{E1,E5},{E1,E6},{E1,E13},{E1,E14},{E2,E0},{E2,E4},{E2,E5},{E2,E6},{E2,E7},{E2,E8},{E2,E9},{E2,E10},{E2,E12},{E2,E13},{E2,E14},{E2,E15}: begin 
-				destport= 1; 
-			end
-			{E1,E3},{E2,E3}: begin 
-				destport= 3; 
-			end
-			endcase
-		end
-	end//R2
-
-	if(CURRENT_R_ADDR == 3) begin :R3
-		always@(*)begin	
-			destport= 0; 
-			case({src_e_addr,dest_e_addr})
-			{E3,E4},{E3,E11}: begin 
-				destport= 0; 
-			end
-			{E3,E1},{E3,E6},{E3,E7},{E3,E8},{E3,E10},{E3,E12},{E3,E13},{E3,E14}: begin 
-				destport= 1; 
-			end
-			{E3,E2}: begin 
-				destport= 2; 
-			end
-			{E3,E0},{E3,E5},{E3,E9},{E3,E15}: begin 
-				destport= 3; 
-			end
-			endcase
-		end
-	end//R3
-
-	if(CURRENT_R_ADDR == 4) begin :R4
-		always@(*)begin	
-			destport= 0; 
-			case({src_e_addr,dest_e_addr})
-			{E3,E13},{E4,E3},{E4,E13},{E5,E3},{E6,E3},{E7,E3},{E8,E3},{E9,E3},{E10,E3},{E12,E3},{E13,E3},{E14,E3},{E15,E3}: begin 
-				destport= 0; 
-			end
-			{E4,E2},{E4,E11},{E4,E14}: begin 
-				destport= 1; 
-			end
-			{E3,E0},{E3,E5},{E3,E9},{E3,E15},{E4,E0},{E4,E5},{E4,E9},{E4,E12},{E4,E15}: begin 
-				destport= 2; 
-			end
-			{E3,E6},{E4,E6}: begin 
-				destport= 3; 
-			end
-			{E3,E1},{E3,E7},{E3,E8},{E3,E14},{E4,E1},{E4,E7},{E4,E8},{E4,E10}: begin 
-				destport= 4; 
-			end
-			endcase
-		end
-	end//R4
-
-	if(CURRENT_R_ADDR == 5) begin :R5
-		always@(*)begin	
-			destport= 0; 
-			case({src_e_addr,dest_e_addr})
-			{E0,E6},{E0,E15},{E3,E9},{E3,E15},{E4,E9},{E4,E15},{E5,E6},{E5,E9},{E5,E15},{E6,E9},{E6,E15},{E9,E6},{E9,E15},{E13,E9},{E14,E9},{E15,E9}: begin 
-				destport= 0; 
-			end
-			{E0,E4},{E0,E13},{E4,E12},{E5,E1},{E5,E2},{E5,E3},{E5,E4},{E5,E7},{E5,E8},{E5,E10},{E5,E12},{E5,E13},{E5,E14},{E6,E1},{E6,E7},{E6,E8},{E6,E10},{E6,E12},{E9,E3},{E9,E4},{E9,E13},{E9,E14}: begin 
-				destport= 1; 
-			end
-			{E0,E14},{E5,E11},{E6,E2},{E6,E11},{E6,E14},{E9,E2},{E9,E11}: begin 
-				destport= 2; 
-			end
-			{E3,E0},{E4,E0},{E5,E0},{E6,E0},{E11,E0},{E13,E0},{E15,E0}: begin 
-				destport= 3; 
-			end
-			endcase
-		end
-	end//R5
-
-	if(CURRENT_R_ADDR == 6) begin :R6
-		always@(*)begin	
-			destport= 0; 
-			case({src_e_addr,dest_e_addr})
-			{E0,E13},{E3,E5},{E4,E5},{E5,E13},{E6,E5},{E6,E13},{E9,E13}: begin 
-				destport= 0; 
-			end
-			{E3,E15},{E4,E12},{E4,E15},{E6,E1},{E6,E2},{E6,E7},{E6,E8},{E6,E10},{E6,E11},{E6,E12},{E6,E14},{E6,E15}: begin 
-				destport= 1; 
-			end
-			{E0,E4},{E5,E3},{E5,E4},{E6,E3},{E6,E4},{E9,E3},{E9,E4}: begin 
-				destport= 2; 
-			end
-			{E3,E0},{E3,E9},{E4,E0},{E4,E9},{E6,E0},{E6,E9}: begin 
-				destport= 3; 
-			end
-			{E4,E2},{E4,E11},{E4,E14},{E5,E2},{E5,E14},{E9,E14}: begin 
-				destport= 4; 
-			end
-			endcase
-		end
-	end//R6
-
-	if(CURRENT_R_ADDR == 7) begin :R7
-		always@(*)begin	
-			destport= 0; 
-			case({src_e_addr,dest_e_addr})
-			{E0,E1},{E1,E8},{E1,E10},{E2,E10},{E3,E1},{E3,E10},{E4,E1},{E4,E10},{E5,E1},{E6,E1},{E7,E1},{E7,E8},{E7,E10},{E8,E1},{E9,E1},{E10,E1},{E11,E1},{E11,E10},{E12,E1},{E13,E1},{E13,E10},{E14,E1},{E14,E10},{E15,E1}: begin 
-				destport= 0; 
-			end
-			{E1,E9},{E1,E12},{E1,E15},{E2,E9},{E2,E12},{E7,E9},{E7,E12}: begin 
-				destport= 1; 
-			end
-			{E1,E4},{E7,E2},{E7,E3},{E7,E4},{E7,E5},{E7,E6},{E7,E11},{E7,E13},{E7,E14},{E7,E15}: begin 
-				destport= 2; 
-			end
-			{E1,E0},{E2,E0},{E7,E0},{E14,E0}: begin 
-				destport= 3; 
-			end
-			endcase
-		end
-	end//R7
-
-	if(CURRENT_R_ADDR == 8) begin :R8
-		always@(*)begin	
-			destport= 0; 
-			case({src_e_addr,dest_e_addr})
-			{E1,E12},{E2,E12},{E3,E7},{E4,E7},{E7,E12},{E7,E14},{E8,E7},{E8,E12},{E8,E14},{E9,E7},{E11,E7},{E13,E7},{E14,E7}: begin 
-				destport= 0; 
-			end
-			{E1,E15},{E7,E5},{E7,E15},{E8,E4},{E8,E5},{E8,E15}: begin 
-				destport= 1; 
-			end
-			{E1,E4},{E1,E9},{E2,E9},{E3,E10},{E4,E10},{E7,E3},{E7,E4},{E7,E6},{E7,E9},{E7,E13},{E8,E0},{E8,E3},{E8,E6},{E8,E9},{E8,E13},{E11,E10},{E13,E10},{E14,E0},{E14,E10}: begin 
-				destport= 2; 
-			end
-			{E3,E1},{E4,E1},{E8,E1},{E8,E10},{E9,E1},{E11,E1},{E13,E1},{E14,E1}: begin 
-				destport= 3; 
-			end
-			{E7,E2},{E7,E11},{E8,E2},{E8,E11}: begin 
-				destport= 4; 
-			end
-			endcase
-		end
-	end//R8
-
-	if(CURRENT_R_ADDR == 9) begin :R9
-		always@(*)begin	
-			destport= 0; 
-			case({src_e_addr,dest_e_addr})
-			{E0,E5},{E0,E12},{E3,E0},{E4,E0},{E5,E0},{E6,E0},{E8,E0},{E9,E0},{E9,E5},{E9,E12},{E11,E0},{E12,E0},{E13,E0},{E15,E0}: begin 
-				destport= 0; 
-			end
-			{E0,E11},{E0,E14},{E0,E15},{E9,E2},{E9,E11},{E9,E15}: begin 
-				destport= 1; 
-			end
-			{E0,E4},{E0,E6},{E0,E13},{E9,E3},{E9,E4},{E9,E6},{E9,E13},{E9,E14}: begin 
-				destport= 2; 
-			end
-			{E9,E10}: begin 
-				destport= 3; 
-			end
-			{E0,E8},{E9,E1},{E9,E7},{E9,E8}: begin 
-				destport= 4; 
-			end
-			endcase
-		end
-	end//R9
-
-	if(CURRENT_R_ADDR == 10) begin :R10
-		always@(*)begin	
-			destport= 0; 
-			case({src_e_addr,dest_e_addr})
-			{E0,E7},{E1,E0},{E2,E0},{E5,E7},{E6,E7},{E7,E0},{E10,E0},{E10,E7},{E10,E12},{E12,E7},{E14,E0},{E15,E7}: begin 
-				destport= 0; 
-			end
-			{E0,E2},{E0,E3},{E10,E2},{E10,E3},{E10,E4},{E10,E5},{E10,E6},{E10,E11},{E10,E13},{E10,E14},{E10,E15}: begin 
-				destport= 1; 
-			end
-			{E10,E9}: begin 
-				destport= 2; 
-			end
-			{E0,E1},{E5,E1},{E6,E1},{E10,E1},{E12,E1},{E15,E1}: begin 
-				destport= 3; 
-			end
-			{E10,E8}: begin 
-				destport= 4; 
-			end
-			endcase
-		end
-	end//R10
-
-	if(CURRENT_R_ADDR == 11) begin :R11
-		always@(*)begin	
-			destport= 0; 
-			case({src_e_addr,dest_e_addr})
-			{E0,E2},{E0,E3},{E1,E3},{E1,E14},{E2,E3},{E2,E14},{E3,E2},{E4,E2},{E5,E2},{E6,E2},{E7,E2},{E8,E2},{E9,E2},{E10,E2},{E11,E2},{E11,E3},{E11,E14},{E12,E2},{E13,E2},{E14,E2},{E15,E2}: begin 
-				destport= 0; 
-			end
-			{E1,E5},{E1,E13},{E2,E5},{E2,E15},{E3,E12},{E11,E0},{E11,E5},{E11,E9},{E11,E12},{E11,E15}: begin 
-				destport= 1; 
-			end
-			{E1,E6},{E2,E4},{E2,E6},{E2,E13},{E11,E4},{E11,E6},{E11,E13}: begin 
-				destport= 2; 
-			end
-			{E2,E8},{E3,E10},{E11,E1},{E11,E7},{E11,E8},{E11,E10}: begin 
-				destport= 3; 
-			end
-			endcase
-		end
-	end//R11
-
-	if(CURRENT_R_ADDR == 12) begin :R12
-		always@(*)begin	
-			destport= 0; 
-			case({src_e_addr,dest_e_addr})
-			{E0,E8},{E1,E9},{E1,E15},{E2,E9},{E5,E8},{E5,E10},{E6,E8},{E6,E10},{E7,E9},{E8,E9},{E8,E10},{E9,E8},{E9,E10},{E10,E8},{E10,E9},{E10,E15},{E11,E9},{E12,E8},{E12,E9},{E12,E10},{E12,E15},{E15,E8},{E15,E10}: begin 
-				destport= 0; 
-			end
-			{E0,E2},{E0,E3},{E0,E11},{E5,E1},{E5,E7},{E6,E1},{E6,E7},{E10,E2},{E10,E11},{E10,E14},{E12,E1},{E12,E2},{E12,E7},{E12,E11},{E12,E14},{E15,E1},{E15,E7}: begin 
-				destport= 2; 
-			end
-			{E8,E0},{E8,E4},{E9,E1},{E9,E7},{E10,E3},{E10,E4},{E10,E6},{E10,E13},{E12,E0},{E12,E3},{E12,E4},{E12,E6},{E12,E13}: begin 
-				destport= 3; 
-			end
-			{E8,E5},{E10,E5},{E12,E5}: begin 
-				destport= 4; 
-			end
-			endcase
-		end
-	end//R12
-
-	if(CURRENT_R_ADDR == 13) begin :R13
-		always@(*)begin	
-			destport= 0; 
-			case({src_e_addr,dest_e_addr})
-			{E0,E4},{E1,E4},{E1,E6},{E2,E4},{E2,E6},{E3,E6},{E3,E14},{E4,E6},{E4,E14},{E5,E4},{E5,E14},{E6,E4},{E7,E4},{E7,E6},{E8,E4},{E8,E6},{E9,E4},{E9,E14},{E10,E4},{E10,E6},{E11,E4},{E11,E6},{E12,E4},{E12,E6},{E13,E4},{E13,E6},{E13,E14},{E14,E4},{E14,E6},{E15,E4},{E15,E6}: begin 
-				destport= 0; 
-			end
-			{E13,E0},{E13,E5},{E13,E9},{E13,E12},{E13,E15}: begin 
-				destport= 1; 
-			end
-			{E5,E3},{E6,E3},{E7,E3},{E8,E3},{E9,E3},{E10,E3},{E12,E3},{E13,E3},{E14,E3},{E15,E3}: begin 
-				destport= 2; 
-			end
-			{E3,E1},{E3,E7},{E3,E8},{E4,E1},{E4,E7},{E4,E8},{E4,E10},{E13,E1},{E13,E7},{E13,E8},{E13,E10}: begin 
-				destport= 3; 
-			end
-			{E4,E2},{E4,E11},{E5,E2},{E13,E2},{E13,E11}: begin 
-				destport= 4; 
-			end
-			endcase
-		end
-	end//R13
-
-	if(CURRENT_R_ADDR == 14) begin :R14
-		always@(*)begin	
-			destport= 0; 
-			case({src_e_addr,dest_e_addr})
-			{E0,E11},{E2,E8},{E2,E13},{E2,E15},{E3,E8},{E4,E8},{E4,E11},{E5,E11},{E6,E11},{E7,E11},{E7,E13},{E7,E15},{E8,E11},{E8,E13},{E8,E15},{E9,E11},{E10,E11},{E11,E8},{E11,E13},{E11,E15},{E12,E11},{E13,E8},{E13,E11},{E13,E15},{E14,E8},{E14,E11},{E14,E13},{E14,E15},{E15,E11}: begin 
-				destport= 0; 
-			end
-			{E3,E12},{E11,E9},{E11,E12},{E13,E12},{E14,E12}: begin 
-				destport= 1; 
-			end
-			{E0,E2},{E1,E4},{E2,E4},{E4,E2},{E5,E2},{E6,E2},{E7,E2},{E7,E3},{E7,E4},{E8,E2},{E8,E3},{E9,E2},{E10,E2},{E11,E4},{E12,E2},{E13,E2},{E14,E2},{E14,E3},{E14,E4},{E15,E2}: begin 
-				destport= 2; 
-			end
-			{E0,E3},{E1,E6},{E1,E13},{E2,E6},{E3,E1},{E3,E7},{E3,E10},{E4,E1},{E4,E7},{E4,E10},{E7,E6},{E8,E6},{E11,E1},{E11,E6},{E11,E7},{E11,E10},{E13,E1},{E13,E7},{E13,E10},{E14,E0},{E14,E1},{E14,E6},{E14,E7},{E14,E10}: begin 
-				destport= 3; 
-			end
-			{E1,E5},{E2,E5},{E7,E5},{E11,E0},{E11,E5},{E13,E0},{E13,E5},{E13,E9},{E14,E5},{E14,E9}: begin 
-				destport= 4; 
-			end
-			endcase
-		end
-	end//R14
-
-	if(CURRENT_R_ADDR == 15) begin :R15
-		always@(*)begin	
-			destport= 0; 
-			case({src_e_addr,dest_e_addr})
-			{E0,E14},{E1,E5},{E1,E13},{E2,E5},{E3,E12},{E4,E12},{E5,E12},{E6,E12},{E6,E14},{E7,E5},{E8,E5},{E10,E5},{E10,E13},{E10,E14},{E11,E5},{E11,E12},{E12,E5},{E12,E13},{E12,E14},{E13,E5},{E13,E12},{E14,E5},{E14,E12},{E15,E5},{E15,E12},{E15,E13},{E15,E14}: begin 
-				destport= 0; 
-			end
-			{E8,E4},{E10,E3},{E10,E4},{E11,E9},{E12,E3},{E12,E4},{E15,E3},{E15,E4}: begin 
-				destport= 2; 
-			end
-			{E5,E1},{E5,E7},{E5,E10},{E6,E1},{E6,E7},{E6,E10},{E10,E6},{E11,E0},{E12,E6},{E13,E0},{E13,E9},{E14,E9},{E15,E0},{E15,E1},{E15,E6},{E15,E7},{E15,E9},{E15,E10}: begin 
-				destport= 3; 
-			end
-			{E0,E2},{E0,E3},{E0,E11},{E5,E8},{E5,E11},{E6,E2},{E6,E8},{E6,E11},{E9,E2},{E9,E11},{E10,E2},{E10,E11},{E12,E2},{E12,E11},{E15,E2},{E15,E8},{E15,E11}: begin 
-				destport= 4; 
-			end
-			endcase
-		end
-	end//R15
-
-	endgenerate
-  
-
-	
-endmodule  
-
-
+    input   [EAw-1   :0] dest_e_addr;
+    input   [EAw-1   :0] src_e_addr;
+    output  reg [DSTPw-1 :0] destport;
+localparam [EAw-1 : 0]    E0=0;
+localparam [EAw-1 : 0]    E1=1;
+localparam [EAw-1 : 0]    E2=2;
+localparam [EAw-1 : 0]    E3=3;
+localparam [EAw-1 : 0]    E4=4;
+localparam [EAw-1 : 0]    E5=5;
+localparam [EAw-1 : 0]    E6=6;
+localparam [EAw-1 : 0]    E7=7;
+localparam [EAw-1 : 0]    E8=8;
+localparam [EAw-1 : 0]    E9=9;
+localparam [EAw-1 : 0]    E10=10;
+localparam [EAw-1 : 0]    E11=11;
+localparam [EAw-1 : 0]    E12=12;
+localparam [EAw-1 : 0]    E13=13;
+localparam [EAw-1 : 0]    E14=14;
+localparam [EAw-1 : 0]    E15=15;
+
+
+    generate
+    if(CURRENT_R_ADDR == 0) begin :R0
+        always@(*)begin
+            destport= 0;
+            case({src_e_addr,dest_e_addr})
+            {E0,E9},{E0,E10}: begin 
+                destport= 0; 
+            end
+            {E0,E2},{E0,E3},{E0,E8},{E0,E11},{E0,E12}: begin 
+                destport= 1; 
+            end
+            {E0,E1},{E0,E4},{E0,E5},{E0,E6},{E0,E7},{E0,E13},{E0,E14},{E0,E15}: begin 
+                destport= 2; 
+            end
+            endcase
+        end
+    end//R0
+
+    if(CURRENT_R_ADDR == 1) begin :R1
+        always@(*)begin
+            destport= 0;
+            case({src_e_addr,dest_e_addr})
+            {E1,E2},{E1,E7},{E2,E7}: begin 
+                destport= 0; 
+            end
+            {E1,E3},{E1,E4},{E1,E5},{E1,E6},{E1,E8},{E1,E9},{E1,E11},{E1,E12},{E1,E13},{E1,E14},{E1,E15},{E2,E9},{E2,E12}: begin 
+                destport= 1; 
+            end
+            {E1,E0},{E1,E10},{E2,E0},{E2,E10}: begin 
+                destport= 2; 
+            end
+            endcase
+        end
+    end//R1
+
+    if(CURRENT_R_ADDR == 2) begin :R2
+        always@(*)begin
+            destport= 0;
+            case({src_e_addr,dest_e_addr})
+            {E1,E11},{E2,E1},{E2,E11}: begin 
+                destport= 0; 
+            end
+            {E1,E5},{E1,E6},{E1,E13},{E1,E14},{E2,E0},{E2,E4},{E2,E5},{E2,E6},{E2,E7},{E2,E8},{E2,E9},{E2,E10},{E2,E12},{E2,E13},{E2,E14},{E2,E15}: begin 
+                destport= 1; 
+            end
+            {E1,E3},{E2,E3}: begin 
+                destport= 3; 
+            end
+            endcase
+        end
+    end//R2
+
+    if(CURRENT_R_ADDR == 3) begin :R3
+        always@(*)begin
+            destport= 0;
+            case({src_e_addr,dest_e_addr})
+            {E3,E4},{E3,E11}: begin 
+                destport= 0; 
+            end
+            {E3,E1},{E3,E6},{E3,E7},{E3,E8},{E3,E10},{E3,E12},{E3,E13},{E3,E14}: begin 
+                destport= 1; 
+            end
+            {E3,E2}: begin 
+                destport= 2; 
+            end
+            {E3,E0},{E3,E5},{E3,E9},{E3,E15}: begin 
+                destport= 3; 
+            end
+            endcase
+        end
+    end//R3
+
+    if(CURRENT_R_ADDR == 4) begin :R4
+        always@(*)begin
+            destport= 0;
+            case({src_e_addr,dest_e_addr})
+            {E3,E13},{E4,E3},{E4,E13},{E5,E3},{E6,E3},{E7,E3},{E8,E3},{E9,E3},{E10,E3},{E12,E3},{E13,E3},{E14,E3},{E15,E3}: begin 
+                destport= 0; 
+            end
+            {E4,E2},{E4,E11},{E4,E14}: begin 
+                destport= 1; 
+            end
+            {E3,E0},{E3,E5},{E3,E9},{E3,E15},{E4,E0},{E4,E5},{E4,E9},{E4,E12},{E4,E15}: begin 
+                destport= 2; 
+            end
+            {E3,E6},{E4,E6}: begin 
+                destport= 3; 
+            end
+            {E3,E1},{E3,E7},{E3,E8},{E3,E14},{E4,E1},{E4,E7},{E4,E8},{E4,E10}: begin 
+                destport= 4; 
+            end
+            endcase
+        end
+    end//R4
+
+    if(CURRENT_R_ADDR == 5) begin :R5
+        always@(*)begin
+            destport= 0;
+            case({src_e_addr,dest_e_addr})
+            {E0,E6},{E0,E15},{E3,E9},{E3,E15},{E4,E9},{E4,E15},{E5,E6},{E5,E9},{E5,E15},{E6,E9},{E6,E15},{E9,E6},{E9,E15},{E13,E9},{E14,E9},{E15,E9}: begin 
+                destport= 0; 
+            end
+            {E0,E4},{E0,E13},{E4,E12},{E5,E1},{E5,E2},{E5,E3},{E5,E4},{E5,E7},{E5,E8},{E5,E10},{E5,E12},{E5,E13},{E5,E14},{E6,E1},{E6,E7},{E6,E8},{E6,E10},{E6,E12},{E9,E3},{E9,E4},{E9,E13},{E9,E14}: begin 
+                destport= 1; 
+            end
+            {E0,E14},{E5,E11},{E6,E2},{E6,E11},{E6,E14},{E9,E2},{E9,E11}: begin 
+                destport= 2; 
+            end
+            {E3,E0},{E4,E0},{E5,E0},{E6,E0},{E11,E0},{E13,E0},{E15,E0}: begin 
+                destport= 3; 
+            end
+            endcase
+        end
+    end//R5
+
+    if(CURRENT_R_ADDR == 6) begin :R6
+        always@(*)begin
+            destport= 0;
+            case({src_e_addr,dest_e_addr})
+            {E0,E13},{E3,E5},{E4,E5},{E5,E13},{E6,E5},{E6,E13},{E9,E13}: begin 
+                destport= 0; 
+            end
+            {E3,E15},{E4,E12},{E4,E15},{E6,E1},{E6,E2},{E6,E7},{E6,E8},{E6,E10},{E6,E11},{E6,E12},{E6,E14},{E6,E15}: begin 
+                destport= 1; 
+            end
+            {E0,E4},{E5,E3},{E5,E4},{E6,E3},{E6,E4},{E9,E3},{E9,E4}: begin 
+                destport= 2; 
+            end
+            {E3,E0},{E3,E9},{E4,E0},{E4,E9},{E6,E0},{E6,E9}: begin 
+                destport= 3; 
+            end
+            {E4,E2},{E4,E11},{E4,E14},{E5,E2},{E5,E14},{E9,E14}: begin 
+                destport= 4; 
+            end
+            endcase
+        end
+    end//R6
+
+    if(CURRENT_R_ADDR == 7) begin :R7
+        always@(*)begin
+            destport= 0;
+            case({src_e_addr,dest_e_addr})
+            {E0,E1},{E1,E8},{E1,E10},{E2,E10},{E3,E1},{E3,E10},{E4,E1},{E4,E10},{E5,E1},{E6,E1},{E7,E1},{E7,E8},{E7,E10},{E8,E1},{E9,E1},{E10,E1},{E11,E1},{E11,E10},{E12,E1},{E13,E1},{E13,E10},{E14,E1},{E14,E10},{E15,E1}: begin 
+                destport= 0; 
+            end
+            {E1,E9},{E1,E12},{E1,E15},{E2,E9},{E2,E12},{E7,E9},{E7,E12}: begin 
+                destport= 1; 
+            end
+            {E1,E4},{E7,E2},{E7,E3},{E7,E4},{E7,E5},{E7,E6},{E7,E11},{E7,E13},{E7,E14},{E7,E15}: begin 
+                destport= 2; 
+            end
+            {E1,E0},{E2,E0},{E7,E0},{E14,E0}: begin 
+                destport= 3; 
+            end
+            endcase
+        end
+    end//R7
+
+    if(CURRENT_R_ADDR == 8) begin :R8
+        always@(*)begin
+            destport= 0;
+            case({src_e_addr,dest_e_addr})
+            {E1,E12},{E2,E12},{E3,E7},{E4,E7},{E7,E12},{E7,E14},{E8,E7},{E8,E12},{E8,E14},{E9,E7},{E11,E7},{E13,E7},{E14,E7}: begin 
+                destport= 0; 
+            end
+            {E1,E15},{E7,E5},{E7,E15},{E8,E4},{E8,E5},{E8,E15}: begin 
+                destport= 1; 
+            end
+            {E1,E4},{E1,E9},{E2,E9},{E3,E10},{E4,E10},{E7,E3},{E7,E4},{E7,E6},{E7,E9},{E7,E13},{E8,E0},{E8,E3},{E8,E6},{E8,E9},{E8,E13},{E11,E10},{E13,E10},{E14,E0},{E14,E10}: begin 
+                destport= 2; 
+            end
+            {E3,E1},{E4,E1},{E8,E1},{E8,E10},{E9,E1},{E11,E1},{E13,E1},{E14,E1}: begin 
+                destport= 3; 
+            end
+            {E7,E2},{E7,E11},{E8,E2},{E8,E11}: begin 
+                destport= 4; 
+            end
+            endcase
+        end
+    end//R8
+
+    if(CURRENT_R_ADDR == 9) begin :R9
+        always@(*)begin
+            destport= 0;
+            case({src_e_addr,dest_e_addr})
+            {E0,E5},{E0,E12},{E3,E0},{E4,E0},{E5,E0},{E6,E0},{E8,E0},{E9,E0},{E9,E5},{E9,E12},{E11,E0},{E12,E0},{E13,E0},{E15,E0}: begin 
+                destport= 0; 
+            end
+            {E0,E11},{E0,E14},{E0,E15},{E9,E2},{E9,E11},{E9,E15}: begin 
+                destport= 1; 
+            end
+            {E0,E4},{E0,E6},{E0,E13},{E9,E3},{E9,E4},{E9,E6},{E9,E13},{E9,E14}: begin 
+                destport= 2; 
+            end
+            {E9,E10}: begin 
+                destport= 3; 
+            end
+            {E0,E8},{E9,E1},{E9,E7},{E9,E8}: begin 
+                destport= 4; 
+            end
+            endcase
+        end
+    end//R9
+
+    if(CURRENT_R_ADDR == 10) begin :R10
+        always@(*)begin
+            destport= 0;
+            case({src_e_addr,dest_e_addr})
+            {E0,E7},{E1,E0},{E2,E0},{E5,E7},{E6,E7},{E7,E0},{E10,E0},{E10,E7},{E10,E12},{E12,E7},{E14,E0},{E15,E7}: begin 
+                destport= 0; 
+            end
+            {E0,E2},{E0,E3},{E10,E2},{E10,E3},{E10,E4},{E10,E5},{E10,E6},{E10,E11},{E10,E13},{E10,E14},{E10,E15}: begin 
+                destport= 1; 
+            end
+            {E10,E9}: begin 
+                destport= 2; 
+            end
+            {E0,E1},{E5,E1},{E6,E1},{E10,E1},{E12,E1},{E15,E1}: begin 
+                destport= 3; 
+            end
+            {E10,E8}: begin 
+                destport= 4; 
+            end
+            endcase
+        end
+    end//R10
+
+    if(CURRENT_R_ADDR == 11) begin :R11
+        always@(*)begin
+            destport= 0;
+            case({src_e_addr,dest_e_addr})
+            {E0,E2},{E0,E3},{E1,E3},{E1,E14},{E2,E3},{E2,E14},{E3,E2},{E4,E2},{E5,E2},{E6,E2},{E7,E2},{E8,E2},{E9,E2},{E10,E2},{E11,E2},{E11,E3},{E11,E14},{E12,E2},{E13,E2},{E14,E2},{E15,E2}: begin 
+                destport= 0; 
+            end
+            {E1,E5},{E1,E13},{E2,E5},{E2,E15},{E3,E12},{E11,E0},{E11,E5},{E11,E9},{E11,E12},{E11,E15}: begin 
+                destport= 1; 
+            end
+            {E1,E6},{E2,E4},{E2,E6},{E2,E13},{E11,E4},{E11,E6},{E11,E13}: begin 
+                destport= 2; 
+            end
+            {E2,E8},{E3,E10},{E11,E1},{E11,E7},{E11,E8},{E11,E10}: begin 
+                destport= 3; 
+            end
+            endcase
+        end
+    end//R11
+
+    if(CURRENT_R_ADDR == 12) begin :R12
+        always@(*)begin
+            destport= 0;
+            case({src_e_addr,dest_e_addr})
+            {E0,E8},{E1,E9},{E1,E15},{E2,E9},{E5,E8},{E5,E10},{E6,E8},{E6,E10},{E7,E9},{E8,E9},{E8,E10},{E9,E8},{E9,E10},{E10,E8},{E10,E9},{E10,E15},{E11,E9},{E12,E8},{E12,E9},{E12,E10},{E12,E15},{E15,E8},{E15,E10}: begin 
+                destport= 0; 
+            end
+            {E0,E2},{E0,E3},{E0,E11},{E5,E1},{E5,E7},{E6,E1},{E6,E7},{E10,E2},{E10,E11},{E10,E14},{E12,E1},{E12,E2},{E12,E7},{E12,E11},{E12,E14},{E15,E1},{E15,E7}: begin 
+                destport= 2; 
+            end
+            {E8,E0},{E8,E4},{E9,E1},{E9,E7},{E10,E3},{E10,E4},{E10,E6},{E10,E13},{E12,E0},{E12,E3},{E12,E4},{E12,E6},{E12,E13}: begin 
+                destport= 3; 
+            end
+            {E8,E5},{E10,E5},{E12,E5}: begin 
+                destport= 4; 
+            end
+            endcase
+        end
+    end//R12
+
+    if(CURRENT_R_ADDR == 13) begin :R13
+        always@(*)begin
+            destport= 0;
+            case({src_e_addr,dest_e_addr})
+            {E0,E4},{E1,E4},{E1,E6},{E2,E4},{E2,E6},{E3,E6},{E3,E14},{E4,E6},{E4,E14},{E5,E4},{E5,E14},{E6,E4},{E7,E4},{E7,E6},{E8,E4},{E8,E6},{E9,E4},{E9,E14},{E10,E4},{E10,E6},{E11,E4},{E11,E6},{E12,E4},{E12,E6},{E13,E4},{E13,E6},{E13,E14},{E14,E4},{E14,E6},{E15,E4},{E15,E6}: begin 
+                destport= 0; 
+            end
+            {E13,E0},{E13,E5},{E13,E9},{E13,E12},{E13,E15}: begin 
+                destport= 1; 
+            end
+            {E5,E3},{E6,E3},{E7,E3},{E8,E3},{E9,E3},{E10,E3},{E12,E3},{E13,E3},{E14,E3},{E15,E3}: begin 
+                destport= 2; 
+            end
+            {E3,E1},{E3,E7},{E3,E8},{E4,E1},{E4,E7},{E4,E8},{E4,E10},{E13,E1},{E13,E7},{E13,E8},{E13,E10}: begin 
+                destport= 3; 
+            end
+            {E4,E2},{E4,E11},{E5,E2},{E13,E2},{E13,E11}: begin 
+                destport= 4; 
+            end
+            endcase
+        end
+    end//R13
+
+    if(CURRENT_R_ADDR == 14) begin :R14
+        always@(*)begin
+            destport= 0;
+            case({src_e_addr,dest_e_addr})
+            {E0,E11},{E2,E8},{E2,E13},{E2,E15},{E3,E8},{E4,E8},{E4,E11},{E5,E11},{E6,E11},{E7,E11},{E7,E13},{E7,E15},{E8,E11},{E8,E13},{E8,E15},{E9,E11},{E10,E11},{E11,E8},{E11,E13},{E11,E15},{E12,E11},{E13,E8},{E13,E11},{E13,E15},{E14,E8},{E14,E11},{E14,E13},{E14,E15},{E15,E11}: begin 
+                destport= 0; 
+            end
+            {E3,E12},{E11,E9},{E11,E12},{E13,E12},{E14,E12}: begin 
+                destport= 1; 
+            end
+            {E0,E2},{E1,E4},{E2,E4},{E4,E2},{E5,E2},{E6,E2},{E7,E2},{E7,E3},{E7,E4},{E8,E2},{E8,E3},{E9,E2},{E10,E2},{E11,E4},{E12,E2},{E13,E2},{E14,E2},{E14,E3},{E14,E4},{E15,E2}: begin 
+                destport= 2; 
+            end
+            {E0,E3},{E1,E6},{E1,E13},{E2,E6},{E3,E1},{E3,E7},{E3,E10},{E4,E1},{E4,E7},{E4,E10},{E7,E6},{E8,E6},{E11,E1},{E11,E6},{E11,E7},{E11,E10},{E13,E1},{E13,E7},{E13,E10},{E14,E0},{E14,E1},{E14,E6},{E14,E7},{E14,E10}: begin 
+                destport= 3; 
+            end
+            {E1,E5},{E2,E5},{E7,E5},{E11,E0},{E11,E5},{E13,E0},{E13,E5},{E13,E9},{E14,E5},{E14,E9}: begin 
+                destport= 4; 
+            end
+            endcase
+        end
+    end//R14
+
+    if(CURRENT_R_ADDR == 15) begin :R15
+        always@(*)begin
+            destport= 0;
+            case({src_e_addr,dest_e_addr})
+            {E0,E14},{E1,E5},{E1,E13},{E2,E5},{E3,E12},{E4,E12},{E5,E12},{E6,E12},{E6,E14},{E7,E5},{E8,E5},{E10,E5},{E10,E13},{E10,E14},{E11,E5},{E11,E12},{E12,E5},{E12,E13},{E12,E14},{E13,E5},{E13,E12},{E14,E5},{E14,E12},{E15,E5},{E15,E12},{E15,E13},{E15,E14}: begin 
+                destport= 0; 
+            end
+            {E8,E4},{E10,E3},{E10,E4},{E11,E9},{E12,E3},{E12,E4},{E15,E3},{E15,E4}: begin 
+                destport= 2; 
+            end
+            {E5,E1},{E5,E7},{E5,E10},{E6,E1},{E6,E7},{E6,E10},{E10,E6},{E11,E0},{E12,E6},{E13,E0},{E13,E9},{E14,E9},{E15,E0},{E15,E1},{E15,E6},{E15,E7},{E15,E9},{E15,E10}: begin 
+                destport= 3; 
+            end
+            {E0,E2},{E0,E3},{E0,E11},{E5,E8},{E5,E11},{E6,E2},{E6,E8},{E6,E11},{E9,E2},{E9,E11},{E10,E2},{E10,E11},{E12,E2},{E12,E11},{E15,E2},{E15,E8},{E15,E11}: begin 
+                destport= 4; 
+            end
+            endcase
+        end
+    end//R15
+
+    endgenerate
+
+
+endmodule
diff --git a/mpsoc/rtl/src_topology/custom1/Tcustom1Rcustom_ni_routing.v b/mpsoc/rtl/src_topology/custom1/Tcustom1Rcustom_ni_routing.v
new file mode 100644
index 0000000..094583d
--- /dev/null
+++ b/mpsoc/rtl/src_topology/custom1/Tcustom1Rcustom_ni_routing.v
@@ -0,0 +1,319 @@
+
+/**************************************************************************
+**    WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT ARE LIKELY TO BE
+**    OVERWRITTEN AND LOST. Rename this file if you wish to do any modification.
+****************************************************************************/
+
+
+/**********************************************************************
+**    File: /home/alireza/work/git/hca_git/git-hub/ProNoC/mpsoc/rtl/src_topology/custom1/Tcustom1Rcustom_ni_routing.v
+**    
+**    Copyright (C) 2014-2022  Alireza Monemi
+**    
+**    This file is part of ProNoC 2.2.0 
+**
+**    ProNoC ( stands for Prototype Network-on-chip)  is free software: 
+**    you can redistribute it and/or modify it under the terms of the GNU
+**    Lesser General Public License as published by the Free Software Foundation,
+**    either version 2 of the License, or (at your option) any later version.
+**
+**     ProNoC is distributed in the hope that it will be useful, but WITHOUT
+**     ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+**     or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
+**     Public License for more details.
+**
+**     You should have received a copy of the GNU Lesser General Public
+**     License along with ProNoC. If not, see <http:**www.gnu.org/licenses/>.
+******************************************************************************/ 
+module Tcustom1Rcustom_ni_routing  #(
+    parameter RAw = 3,
+    parameter EAw = 3,
+    parameter DSTPw=4
+)
+(
+    dest_e_addr,
+    src_e_addr,
+    destport
+);
+    input   [EAw-1   :0] dest_e_addr;
+    input   [EAw-1   :0] src_e_addr;
+    output reg [DSTPw-1 :0] destport;
+    
+    always@(*)begin
+        destport=0;
+        case(src_e_addr) //source address of each individual NI is fixed. So this CASE will be optimized by the synthesizer for each endpoint. 
+        0: begin
+            case(dest_e_addr)
+            1,2,3,7,10: begin 
+                destport= 1; 
+            end
+            4,5,6,8,9,11,12,13,14,15: begin 
+                destport= 2; 
+            end
+
+            default: begin 
+                destport= {DSTPw{1'bX}};
+            end
+            endcase
+        end//0
+        1: begin
+            case(dest_e_addr)
+            0,4,7,8,9,10,12,15: begin 
+                destport= 1; 
+            end
+            2,3,5,6,11,13,14: begin 
+                destport= 2; 
+            end
+
+            default: begin 
+                destport= {DSTPw{1'bX}};
+            end
+            endcase
+        end//1
+        2: begin
+            case(dest_e_addr)
+            3,4,5,6,8,11,13,14,15: begin 
+                destport= 1; 
+            end
+            0,1,7,9,10,12: begin 
+                destport= 2; 
+            end
+
+            default: begin 
+                destport= {DSTPw{1'bX}};
+            end
+            endcase
+        end//2
+        3: begin
+            case(dest_e_addr)
+            2,10,11,12: begin 
+                destport= 1; 
+            end
+            0,1,4,5,6,7,8,9,13,14,15: begin 
+                destport= 2; 
+            end
+
+            default: begin 
+                destport= {DSTPw{1'bX}};
+            end
+            endcase
+        end//3
+        4: begin
+            case(dest_e_addr)
+            1,6,7,8,10,13: begin 
+                destport= 1; 
+            end
+            3: begin 
+                destport= 2; 
+            end
+            0,2,5,9,11,12,14,15: begin 
+                destport= 3; 
+            end
+
+            default: begin 
+                destport= {DSTPw{1'bX}};
+            end
+            endcase
+        end//4
+        5: begin
+            case(dest_e_addr)
+            1,7,8,10,11,12,15: begin 
+                destport= 1; 
+            end
+            2,3,4,6,13,14: begin 
+                destport= 2; 
+            end
+            0,9: begin 
+                destport= 3; 
+            end
+
+            default: begin 
+                destport= {DSTPw{1'bX}};
+            end
+            endcase
+        end//5
+        6: begin
+            case(dest_e_addr)
+            3,4,13: begin 
+                destport= 1; 
+            end
+            0,1,2,5,7,8,9,10,11,12,14,15: begin 
+                destport= 2; 
+            end
+
+            default: begin 
+                destport= {DSTPw{1'bX}};
+            end
+            endcase
+        end//6
+        7: begin
+            case(dest_e_addr)
+            2,3,4,5,6,8,9,11,12,13,14,15: begin 
+                destport= 1; 
+            end
+            0,10: begin 
+                destport= 2; 
+            end
+            1: begin 
+                destport= 3; 
+            end
+
+            default: begin 
+                destport= {DSTPw{1'bX}};
+            end
+            endcase
+        end//7
+        8: begin
+            case(dest_e_addr)
+            0,4,5,9,10,12: begin 
+                destport= 1; 
+            end
+            2,3,6,11,13,14,15: begin 
+                destport= 2; 
+            end
+            1,7: begin 
+                destport= 3; 
+            end
+
+            default: begin 
+                destport= {DSTPw{1'bX}};
+            end
+            endcase
+        end//8
+        9: begin
+            case(dest_e_addr)
+            1,7,8,10,12: begin 
+                destport= 1; 
+            end
+            2,3,4,5,6,11,13,14,15: begin 
+                destport= 2; 
+            end
+            0: begin 
+                destport= 3; 
+            end
+
+            default: begin 
+                destport= {DSTPw{1'bX}};
+            end
+            endcase
+        end//9
+        10: begin
+            case(dest_e_addr)
+            2,3,4,5,6,8,9,11,12,13,14,15: begin 
+                destport= 1; 
+            end
+            1,7: begin 
+                destport= 2; 
+            end
+            0: begin 
+                destport= 3; 
+            end
+
+            default: begin 
+                destport= {DSTPw{1'bX}};
+            end
+            endcase
+        end//10
+        11: begin
+            case(dest_e_addr)
+            0,1,4,5,6,7,8,9,10,12,13,14,15: begin 
+                destport= 1; 
+            end
+            2: begin 
+                destport= 2; 
+            end
+            3: begin 
+                destport= 3; 
+            end
+
+            default: begin 
+                destport= {DSTPw{1'bX}};
+            end
+            endcase
+        end//11
+        12: begin
+            case(dest_e_addr)
+            2,3,4,5,6,11,13,14,15: begin 
+                destport= 1; 
+            end
+            0,9: begin 
+                destport= 2; 
+            end
+            1,7,10: begin 
+                destport= 3; 
+            end
+            8: begin 
+                destport= 4; 
+            end
+
+            default: begin 
+                destport= {DSTPw{1'bX}};
+            end
+            endcase
+        end//12
+        13: begin
+            case(dest_e_addr)
+            3,4: begin 
+                destport= 2; 
+            end
+            6: begin 
+                destport= 3; 
+            end
+            0,1,2,5,7,8,9,10,11,12,14,15: begin 
+                destport= 4; 
+            end
+
+            default: begin 
+                destport= {DSTPw{1'bX}};
+            end
+            endcase
+        end//13
+        14: begin
+            case(dest_e_addr)
+            5,9,12,15: begin 
+                destport= 1; 
+            end
+            3,4,6,13: begin 
+                destport= 2; 
+            end
+            0,1,7,8,10: begin 
+                destport= 3; 
+            end
+            2,11: begin 
+                destport= 4; 
+            end
+
+            default: begin 
+                destport= {DSTPw{1'bX}};
+            end
+            endcase
+        end//14
+        15: begin
+            case(dest_e_addr)
+            1,7,8,10,12: begin 
+                destport= 1; 
+            end
+            2,11,14: begin 
+                destport= 2; 
+            end
+            3,4,6,13: begin 
+                destport= 3; 
+            end
+            0,5,9: begin 
+                destport= 4; 
+            end
+
+            default: begin 
+                destport= {DSTPw{1'bX}};
+            end
+            endcase
+        end//15
+
+        default: begin 
+            destport= {DSTPw{1'bX}};
+        end
+        endcase
+    end
+
+    
+endmodule  
diff --git a/mpsoc/rtl/src_topology/custom1/Tcustom1Rcustom_ni_routing_genvar.v b/mpsoc/rtl/src_topology/custom1/Tcustom1Rcustom_ni_routing_genvar.v
new file mode 100644
index 0000000..e2b52dd
--- /dev/null
+++ b/mpsoc/rtl/src_topology/custom1/Tcustom1Rcustom_ni_routing_genvar.v
@@ -0,0 +1,358 @@
+
+/**************************************************************************
+**    WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT ARE LIKELY TO BE
+**    OVERWRITTEN AND LOST. Rename this file if you wish to do any modification.
+****************************************************************************/
+
+
+/**********************************************************************
+**    File: /home/alireza/work/git/hca_git/git-hub/ProNoC/mpsoc/rtl/src_topology/custom1/Tcustom1Rcustom_ni_routing_genvar.v
+**    
+**    Copyright (C) 2014-2022  Alireza Monemi
+**    
+**    This file is part of ProNoC 2.2.0 
+**
+**    ProNoC ( stands for Prototype Network-on-chip)  is free software: 
+**    you can redistribute it and/or modify it under the terms of the GNU
+**    Lesser General Public License as published by the Free Software Foundation,
+**    either version 2 of the License, or (at your option) any later version.
+**
+**     ProNoC is distributed in the hope that it will be useful, but WITHOUT
+**     ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+**     or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
+**     Public License for more details.
+**
+**     You should have received a copy of the GNU Lesser General Public
+**     License along with ProNoC. If not, see <http:**www.gnu.org/licenses/>.
+******************************************************************************/ 
+module Tcustom1Rcustom_ni_routing_genvar  #(
+    parameter RAw = 3,
+    parameter EAw = 3,
+    parameter DSTPw=4,
+    parameter SRC_E_ADDR=0  
+) (
+    dest_e_addr,
+    destport
+);
+    input   [EAw-1   :0] dest_e_addr;
+    output reg [DSTPw-1 :0] destport;
+    
+    generate
+    if(SRC_E_ADDR == 0) begin : SRC0
+        always@(*)begin
+            destport= 0; 
+            case(dest_e_addr)
+            1,2,3,7,10: begin 
+                destport= 1; 
+            end
+            4,5,6,8,9,11,12,13,14,15: begin 
+                destport= 2; 
+            end
+            default: begin 
+                destport= {DSTPw{1'bX}};
+            end
+            endcase
+        end
+    end//SRC0
+
+    if(SRC_E_ADDR == 1) begin : SRC1
+        always@(*)begin
+            destport= 0; 
+            case(dest_e_addr)
+            0,4,7,8,9,10,12,15: begin 
+                destport= 1; 
+            end
+            2,3,5,6,11,13,14: begin 
+                destport= 2; 
+            end
+            default: begin 
+                destport= {DSTPw{1'bX}};
+            end
+            endcase
+        end
+    end//SRC1
+
+    if(SRC_E_ADDR == 2) begin : SRC2
+        always@(*)begin
+            destport= 0; 
+            case(dest_e_addr)
+            3,4,5,6,8,11,13,14,15: begin 
+                destport= 1; 
+            end
+            0,1,7,9,10,12: begin 
+                destport= 2; 
+            end
+            default: begin 
+                destport= {DSTPw{1'bX}};
+            end
+            endcase
+        end
+    end//SRC2
+
+    if(SRC_E_ADDR == 3) begin : SRC3
+        always@(*)begin
+            destport= 0; 
+            case(dest_e_addr)
+            2,10,11,12: begin 
+                destport= 1; 
+            end
+            0,1,4,5,6,7,8,9,13,14,15: begin 
+                destport= 2; 
+            end
+            default: begin 
+                destport= {DSTPw{1'bX}};
+            end
+            endcase
+        end
+    end//SRC3
+
+    if(SRC_E_ADDR == 4) begin : SRC4
+        always@(*)begin
+            destport= 0; 
+            case(dest_e_addr)
+            1,6,7,8,10,13: begin 
+                destport= 1; 
+            end
+            3: begin 
+                destport= 2; 
+            end
+            0,2,5,9,11,12,14,15: begin 
+                destport= 3; 
+            end
+            default: begin 
+                destport= {DSTPw{1'bX}};
+            end
+            endcase
+        end
+    end//SRC4
+
+    if(SRC_E_ADDR == 5) begin : SRC5
+        always@(*)begin
+            destport= 0; 
+            case(dest_e_addr)
+            1,7,8,10,11,12,15: begin 
+                destport= 1; 
+            end
+            2,3,4,6,13,14: begin 
+                destport= 2; 
+            end
+            0,9: begin 
+                destport= 3; 
+            end
+            default: begin 
+                destport= {DSTPw{1'bX}};
+            end
+            endcase
+        end
+    end//SRC5
+
+    if(SRC_E_ADDR == 6) begin : SRC6
+        always@(*)begin
+            destport= 0; 
+            case(dest_e_addr)
+            3,4,13: begin 
+                destport= 1; 
+            end
+            0,1,2,5,7,8,9,10,11,12,14,15: begin 
+                destport= 2; 
+            end
+            default: begin 
+                destport= {DSTPw{1'bX}};
+            end
+            endcase
+        end
+    end//SRC6
+
+    if(SRC_E_ADDR == 7) begin : SRC7
+        always@(*)begin
+            destport= 0; 
+            case(dest_e_addr)
+            2,3,4,5,6,8,9,11,12,13,14,15: begin 
+                destport= 1; 
+            end
+            0,10: begin 
+                destport= 2; 
+            end
+            1: begin 
+                destport= 3; 
+            end
+            default: begin 
+                destport= {DSTPw{1'bX}};
+            end
+            endcase
+        end
+    end//SRC7
+
+    if(SRC_E_ADDR == 8) begin : SRC8
+        always@(*)begin
+            destport= 0; 
+            case(dest_e_addr)
+            0,4,5,9,10,12: begin 
+                destport= 1; 
+            end
+            2,3,6,11,13,14,15: begin 
+                destport= 2; 
+            end
+            1,7: begin 
+                destport= 3; 
+            end
+            default: begin 
+                destport= {DSTPw{1'bX}};
+            end
+            endcase
+        end
+    end//SRC8
+
+    if(SRC_E_ADDR == 9) begin : SRC9
+        always@(*)begin
+            destport= 0; 
+            case(dest_e_addr)
+            1,7,8,10,12: begin 
+                destport= 1; 
+            end
+            2,3,4,5,6,11,13,14,15: begin 
+                destport= 2; 
+            end
+            0: begin 
+                destport= 3; 
+            end
+            default: begin 
+                destport= {DSTPw{1'bX}};
+            end
+            endcase
+        end
+    end//SRC9
+
+    if(SRC_E_ADDR == 10) begin : SRC10
+        always@(*)begin
+            destport= 0; 
+            case(dest_e_addr)
+            2,3,4,5,6,8,9,11,12,13,14,15: begin 
+                destport= 1; 
+            end
+            1,7: begin 
+                destport= 2; 
+            end
+            0: begin 
+                destport= 3; 
+            end
+            default: begin 
+                destport= {DSTPw{1'bX}};
+            end
+            endcase
+        end
+    end//SRC10
+
+    if(SRC_E_ADDR == 11) begin : SRC11
+        always@(*)begin
+            destport= 0; 
+            case(dest_e_addr)
+            0,1,4,5,6,7,8,9,10,12,13,14,15: begin 
+                destport= 1; 
+            end
+            2: begin 
+                destport= 2; 
+            end
+            3: begin 
+                destport= 3; 
+            end
+            default: begin 
+                destport= {DSTPw{1'bX}};
+            end
+            endcase
+        end
+    end//SRC11
+
+    if(SRC_E_ADDR == 12) begin : SRC12
+        always@(*)begin
+            destport= 0; 
+            case(dest_e_addr)
+            2,3,4,5,6,11,13,14,15: begin 
+                destport= 1; 
+            end
+            0,9: begin 
+                destport= 2; 
+            end
+            1,7,10: begin 
+                destport= 3; 
+            end
+            8: begin 
+                destport= 4; 
+            end
+            default: begin 
+                destport= {DSTPw{1'bX}};
+            end
+            endcase
+        end
+    end//SRC12
+
+    if(SRC_E_ADDR == 13) begin : SRC13
+        always@(*)begin
+            destport= 0; 
+            case(dest_e_addr)
+            3,4: begin 
+                destport= 2; 
+            end
+            6: begin 
+                destport= 3; 
+            end
+            0,1,2,5,7,8,9,10,11,12,14,15: begin 
+                destport= 4; 
+            end
+            default: begin 
+                destport= {DSTPw{1'bX}};
+            end
+            endcase
+        end
+    end//SRC13
+
+    if(SRC_E_ADDR == 14) begin : SRC14
+        always@(*)begin
+            destport= 0; 
+            case(dest_e_addr)
+            5,9,12,15: begin 
+                destport= 1; 
+            end
+            3,4,6,13: begin 
+                destport= 2; 
+            end
+            0,1,7,8,10: begin 
+                destport= 3; 
+            end
+            2,11: begin 
+                destport= 4; 
+            end
+            default: begin 
+                destport= {DSTPw{1'bX}};
+            end
+            endcase
+        end
+    end//SRC14
+
+    if(SRC_E_ADDR == 15) begin : SRC15
+        always@(*)begin
+            destport= 0; 
+            case(dest_e_addr)
+            1,7,8,10,12: begin 
+                destport= 1; 
+            end
+            2,11,14: begin 
+                destport= 2; 
+            end
+            3,4,6,13: begin 
+                destport= 3; 
+            end
+            0,5,9: begin 
+                destport= 4; 
+            end
+            default: begin 
+                destport= {DSTPw{1'bX}};
+            end
+            endcase
+        end
+    end//SRC15
+
+    endgenerate
+
+    
+endmodule
diff --git a/mpsoc/rtl/src_topology/custom1/custom1.png b/mpsoc/rtl/src_topology/custom1/custom1.png
index ed1a814..584d953 100644
Binary files a/mpsoc/rtl/src_topology/custom1/custom1.png and b/mpsoc/rtl/src_topology/custom1/custom1.png differ
diff --git a/mpsoc/rtl/src_topology/custom1/custom1_noc.h b/mpsoc/rtl/src_topology/custom1/custom1_noc.h
deleted file mode 100644
index 0040896..0000000
--- a/mpsoc/rtl/src_topology/custom1/custom1_noc.h
+++ /dev/null
@@ -1,103 +0,0 @@
-
-
- #define TNUM_0 1
- #define RNUM_0 0
- #define TNUM_1 1
- #define RNUM_1 1
- #define TNUM_2 1
- #define RNUM_2 2
- #define TNUM_3 1
- #define RNUM_3 3
- #define TNUM_4 2
- #define RNUM_4 0
- #define TNUM_5 2
- #define RNUM_5 1
- #define TNUM_6 2
- #define RNUM_6 2
- #define TNUM_7 2
- #define RNUM_7 3
- #define TNUM_8 2
- #define RNUM_8 4
- #define TNUM_9 2
- #define RNUM_9 5
- #define TNUM_10 2
- #define RNUM_10 6
- #define TNUM_11 2
- #define RNUM_11 7
- #define TNUM_12 3
- #define RNUM_12 0
- #define TNUM_13 3
- #define RNUM_13 1
- #define TNUM_14 3
- #define RNUM_14 2
- #define TNUM_15 3
- #define RNUM_15 3
-
-
-void topology_connect_all_nodes (void){
-   	 	connect_r2e(TNUM_0,RNUM_0,0,0);
-	conect_r2r(TNUM_0,RNUM_0,1,TNUM_10,RNUM_10,3);
-	conect_r2r(TNUM_0,RNUM_0,2,TNUM_9,RNUM_9,3);
-	connect_r2e(TNUM_1,RNUM_1,0,1);
-	conect_r2r(TNUM_1,RNUM_1,1,TNUM_7,RNUM_7,3);
-	conect_r2r(TNUM_1,RNUM_1,2,TNUM_2,RNUM_2,2);
-	connect_r2e(TNUM_2,RNUM_2,0,2);
-	conect_r2r(TNUM_2,RNUM_2,1,TNUM_11,RNUM_11,2);
-	conect_r2r(TNUM_2,RNUM_2,2,TNUM_1,RNUM_1,2);
-	connect_r2e(TNUM_3,RNUM_3,0,3);
-	conect_r2r(TNUM_3,RNUM_3,1,TNUM_11,RNUM_11,3);
-	conect_r2r(TNUM_3,RNUM_3,2,TNUM_4,RNUM_4,2);
-	connect_r2e(TNUM_4,RNUM_4,0,4);
-	conect_r2r(TNUM_4,RNUM_4,1,TNUM_13,RNUM_13,2);
-	conect_r2r(TNUM_4,RNUM_4,2,TNUM_3,RNUM_3,2);
-	conect_r2r(TNUM_4,RNUM_4,3,TNUM_6,RNUM_6,3);
-	connect_r2e(TNUM_5,RNUM_5,0,5);
-	conect_r2r(TNUM_5,RNUM_5,1,TNUM_15,RNUM_15,4);
-	conect_r2r(TNUM_5,RNUM_5,2,TNUM_6,RNUM_6,2);
-	conect_r2r(TNUM_5,RNUM_5,3,TNUM_9,RNUM_9,2);
-	connect_r2e(TNUM_6,RNUM_6,0,6);
-	conect_r2r(TNUM_6,RNUM_6,1,TNUM_13,RNUM_13,3);
-	conect_r2r(TNUM_6,RNUM_6,2,TNUM_5,RNUM_5,2);
-	conect_r2r(TNUM_6,RNUM_6,3,TNUM_4,RNUM_4,3);
-	connect_r2e(TNUM_7,RNUM_7,0,7);
-	conect_r2r(TNUM_7,RNUM_7,1,TNUM_8,RNUM_8,3);
-	conect_r2r(TNUM_7,RNUM_7,2,TNUM_10,RNUM_10,2);
-	conect_r2r(TNUM_7,RNUM_7,3,TNUM_1,RNUM_1,1);
-	connect_r2e(TNUM_8,RNUM_8,0,8);
-	conect_r2r(TNUM_8,RNUM_8,1,TNUM_12,RNUM_12,4);
-	conect_r2r(TNUM_8,RNUM_8,2,TNUM_14,RNUM_14,3);
-	conect_r2r(TNUM_8,RNUM_8,3,TNUM_7,RNUM_7,1);
-	connect_r2e(TNUM_9,RNUM_9,0,9);
-	conect_r2r(TNUM_9,RNUM_9,1,TNUM_12,RNUM_12,2);
-	conect_r2r(TNUM_9,RNUM_9,2,TNUM_5,RNUM_5,3);
-	conect_r2r(TNUM_9,RNUM_9,3,TNUM_0,RNUM_0,2);
-	connect_r2e(TNUM_10,RNUM_10,0,10);
-	conect_r2r(TNUM_10,RNUM_10,1,TNUM_12,RNUM_12,3);
-	conect_r2r(TNUM_10,RNUM_10,2,TNUM_7,RNUM_7,2);
-	conect_r2r(TNUM_10,RNUM_10,3,TNUM_0,RNUM_0,1);
-	connect_r2e(TNUM_11,RNUM_11,0,11);
-	conect_r2r(TNUM_11,RNUM_11,1,TNUM_14,RNUM_14,4);
-	conect_r2r(TNUM_11,RNUM_11,2,TNUM_2,RNUM_2,1);
-	conect_r2r(TNUM_11,RNUM_11,3,TNUM_3,RNUM_3,1);
-	connect_r2e(TNUM_12,RNUM_12,0,12);
-	conect_r2r(TNUM_12,RNUM_12,1,TNUM_15,RNUM_15,1);
-	conect_r2r(TNUM_12,RNUM_12,2,TNUM_9,RNUM_9,1);
-	conect_r2r(TNUM_12,RNUM_12,3,TNUM_10,RNUM_10,1);
-	conect_r2r(TNUM_12,RNUM_12,4,TNUM_8,RNUM_8,1);
-	connect_r2e(TNUM_13,RNUM_13,0,13);
-	conect_r2r(TNUM_13,RNUM_13,1,TNUM_15,RNUM_15,3);
-	conect_r2r(TNUM_13,RNUM_13,2,TNUM_4,RNUM_4,1);
-	conect_r2r(TNUM_13,RNUM_13,3,TNUM_6,RNUM_6,1);
-	conect_r2r(TNUM_13,RNUM_13,4,TNUM_14,RNUM_14,2);
-	connect_r2e(TNUM_14,RNUM_14,0,14);
-	conect_r2r(TNUM_14,RNUM_14,1,TNUM_15,RNUM_15,2);
-	conect_r2r(TNUM_14,RNUM_14,2,TNUM_13,RNUM_13,4);
-	conect_r2r(TNUM_14,RNUM_14,3,TNUM_8,RNUM_8,2);
-	conect_r2r(TNUM_14,RNUM_14,4,TNUM_11,RNUM_11,1);
-	connect_r2e(TNUM_15,RNUM_15,0,15);
-	conect_r2r(TNUM_15,RNUM_15,1,TNUM_12,RNUM_12,1);
-	conect_r2r(TNUM_15,RNUM_15,2,TNUM_14,RNUM_14,1);
-	conect_r2r(TNUM_15,RNUM_15,3,TNUM_13,RNUM_13,1);
-	conect_r2r(TNUM_15,RNUM_15,4,TNUM_5,RNUM_5,1);
-
-}
diff --git a/mpsoc/rtl/src_topology/custom1/custom1_noc.sv b/mpsoc/rtl/src_topology/custom1/custom1_noc.sv
index 2e29eba..42c1352 100644
--- a/mpsoc/rtl/src_topology/custom1/custom1_noc.sv
+++ b/mpsoc/rtl/src_topology/custom1/custom1_noc.sv
@@ -1,946 +1,862 @@
 
 /**************************************************************************
-**	WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT ARE LIKELY TO BE
-**	OVERWRITTEN AND LOST. Rename this file if you wish to do any modification.
+**    WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT ARE LIKELY TO BE
+**    OVERWRITTEN AND LOST. Rename this file if you wish to do any modification.
 ****************************************************************************/
 
 
 /**********************************************************************
-**	File: /home/alireza/work/git/pronoc/mpsoc/rtl/src_topology/custom1/custom1_noc.sv
+**    File: /home/alireza/work/git/ProNoC-repos/github-pronoc/mpsoc/rtl/src_topology/custom1/custom1_noc.sv
 **    
-**	Copyright (C) 2014-2021  Alireza Monemi
+**    Copyright (C) 2014-2022  Alireza Monemi
 **    
-**	This file is part of ProNoC 2.1.0 
+**    This file is part of ProNoC 2.2.0 
 **
-**	ProNoC ( stands for Prototype Network-on-chip)  is free software: 
-**	you can redistribute it and/or modify it under the terms of the GNU
-**	Lesser General Public License as published by the Free Software Foundation,
-**	either version 2 of the License, or (at your option) any later version.
+**    ProNoC ( stands for Prototype Network-on-chip)  is free software: 
+**    you can redistribute it and/or modify it under the terms of the GNU
+**    Lesser General Public License as published by the Free Software Foundation,
+**    either version 2 of the License, or (at your option) any later version.
 **
-** 	ProNoC is distributed in the hope that it will be useful, but WITHOUT
-** 	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
-** 	or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
-** 	Public License for more details.
+**     ProNoC is distributed in the hope that it will be useful, but WITHOUT
+**     ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+**     or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
+**     Public License for more details.
 **
-** 	You should have received a copy of the GNU Lesser General Public
-** 	License along with ProNoC. If not, see <http:**www.gnu.org/licenses/>.
+**     You should have received a copy of the GNU Lesser General Public
+**     License along with ProNoC. If not, see <http:**www.gnu.org/licenses/>.
 ******************************************************************************/ 
 
 `include "pronoc_def.v"
 
 module   custom1_noc
-#(
-	parameter NOC_ID=0
-)
 (
-		reset,
-	clk,
-	//T0,
-	T0_chan_in,
-	T0_chan_out,
-	T0_router_event,
-	//T1,
-	T1_chan_in,
-	T1_chan_out,
-	T1_router_event,
-	//T2,
-	T2_chan_in,
-	T2_chan_out,
-	T2_router_event,
-	//T3,
-	T3_chan_in,
-	T3_chan_out,
-	T3_router_event,
-	//T4,
-	T4_chan_in,
-	T4_chan_out,
-	T4_router_event,
-	//T5,
-	T5_chan_in,
-	T5_chan_out,
-	T5_router_event,
-	//T6,
-	T6_chan_in,
-	T6_chan_out,
-	T6_router_event,
-	//T7,
-	T7_chan_in,
-	T7_chan_out,
-	T7_router_event,
-	//T8,
-	T8_chan_in,
-	T8_chan_out,
-	T8_router_event,
-	//T9,
-	T9_chan_in,
-	T9_chan_out,
-	T9_router_event,
-	//T10,
-	T10_chan_in,
-	T10_chan_out,
-	T10_router_event,
-	//T11,
-	T11_chan_in,
-	T11_chan_out,
-	T11_router_event,
-	//T12,
-	T12_chan_in,
-	T12_chan_out,
-	T12_router_event,
-	//T13,
-	T13_chan_in,
-	T13_chan_out,
-	T13_router_event,
-	//T14,
-	T14_chan_in,
-	T14_chan_out,
-	T14_router_event,
-	//T15,
-	T15_chan_in,
-	T15_chan_out,
-	T15_router_event
+        reset,
+    clk,
+    //T0,
+    T0_chan_in,
+    T0_chan_out,
+    T0_router_event,
+    //T1,
+    T1_chan_in,
+    T1_chan_out,
+    T1_router_event,
+    //T2,
+    T2_chan_in,
+    T2_chan_out,
+    T2_router_event,
+    //T3,
+    T3_chan_in,
+    T3_chan_out,
+    T3_router_event,
+    //T4,
+    T4_chan_in,
+    T4_chan_out,
+    T4_router_event,
+    //T5,
+    T5_chan_in,
+    T5_chan_out,
+    T5_router_event,
+    //T6,
+    T6_chan_in,
+    T6_chan_out,
+    T6_router_event,
+    //T7,
+    T7_chan_in,
+    T7_chan_out,
+    T7_router_event,
+    //T8,
+    T8_chan_in,
+    T8_chan_out,
+    T8_router_event,
+    //T9,
+    T9_chan_in,
+    T9_chan_out,
+    T9_router_event,
+    //T10,
+    T10_chan_in,
+    T10_chan_out,
+    T10_router_event,
+    //T11,
+    T11_chan_in,
+    T11_chan_out,
+    T11_router_event,
+    //T12,
+    T12_chan_in,
+    T12_chan_out,
+    T12_router_event,
+    //T13,
+    T13_chan_in,
+    T13_chan_out,
+    T13_router_event,
+    //T14,
+    T14_chan_in,
+    T14_chan_out,
+    T14_router_event,
+    //T15,
+    T15_chan_in,
+    T15_chan_out,
+    T15_router_event
 );
-	
-	`NOC_CONF
-	 
-    input reset,clk;    
-       
+    import pronoc_pkg::*;
     
-	/*******************
-	*		T0
-	*******************/
-	input  smartflit_chanel_t T0_chan_in;
-	output smartflit_chanel_t T0_chan_out;
-	output router_event_t T0_router_event;
-
-	/*******************
-	*		T1
-	*******************/
-	input  smartflit_chanel_t T1_chan_in;
-	output smartflit_chanel_t T1_chan_out;
-	output router_event_t T1_router_event;
-
-	/*******************
-	*		T2
-	*******************/
-	input  smartflit_chanel_t T2_chan_in;
-	output smartflit_chanel_t T2_chan_out;
-	output router_event_t T2_router_event;
-
-	/*******************
-	*		T3
-	*******************/
-	input  smartflit_chanel_t T3_chan_in;
-	output smartflit_chanel_t T3_chan_out;
-	output router_event_t T3_router_event;
-
-	/*******************
-	*		T4
-	*******************/
-	input  smartflit_chanel_t T4_chan_in;
-	output smartflit_chanel_t T4_chan_out;
-	output router_event_t T4_router_event;
-
-	/*******************
-	*		T5
-	*******************/
-	input  smartflit_chanel_t T5_chan_in;
-	output smartflit_chanel_t T5_chan_out;
-	output router_event_t T5_router_event;
-
-	/*******************
-	*		T6
-	*******************/
-	input  smartflit_chanel_t T6_chan_in;
-	output smartflit_chanel_t T6_chan_out;
-	output router_event_t T6_router_event;
-
-	/*******************
-	*		T7
-	*******************/
-	input  smartflit_chanel_t T7_chan_in;
-	output smartflit_chanel_t T7_chan_out;
-	output router_event_t T7_router_event;
-
-	/*******************
-	*		T8
-	*******************/
-	input  smartflit_chanel_t T8_chan_in;
-	output smartflit_chanel_t T8_chan_out;
-	output router_event_t T8_router_event;
-
-	/*******************
-	*		T9
-	*******************/
-	input  smartflit_chanel_t T9_chan_in;
-	output smartflit_chanel_t T9_chan_out;
-	output router_event_t T9_router_event;
-
-	/*******************
-	*		T10
-	*******************/
-	input  smartflit_chanel_t T10_chan_in;
-	output smartflit_chanel_t T10_chan_out;
-	output router_event_t T10_router_event;
-
-	/*******************
-	*		T11
-	*******************/
-	input  smartflit_chanel_t T11_chan_in;
-	output smartflit_chanel_t T11_chan_out;
-	output router_event_t T11_router_event;
-
-	/*******************
-	*		T12
-	*******************/
-	input  smartflit_chanel_t T12_chan_in;
-	output smartflit_chanel_t T12_chan_out;
-	output router_event_t T12_router_event;
-
-	/*******************
-	*		T13
-	*******************/
-	input  smartflit_chanel_t T13_chan_in;
-	output smartflit_chanel_t T13_chan_out;
-	output router_event_t T13_router_event;
-
-	/*******************
-	*		T14
-	*******************/
-	input  smartflit_chanel_t T14_chan_in;
-	output smartflit_chanel_t T14_chan_out;
-	output router_event_t T14_router_event;
-
-	/*******************
-	*		T15
-	*******************/
-	input  smartflit_chanel_t T15_chan_in;
-	output smartflit_chanel_t T15_chan_out;
-	output router_event_t T15_router_event;
-
-	/*******************
-	*		R0
-	*******************/
-	wire R0_clk;
-	wire R0_reset;
-
-	wire [RAw-1 :  0] R0_current_r_addr;
-
-	smartflit_chanel_t    R0_chan_in   [3-1 : 0];
-	smartflit_chanel_t    R0_chan_out  [3-1 : 0]; 
-	router_event_t R0_router_event [3-1 : 0]; 
-
-
-	/*******************
-	*		R1
-	*******************/
-	wire R1_clk;
-	wire R1_reset;
-
-	wire [RAw-1 :  0] R1_current_r_addr;
-
-	smartflit_chanel_t    R1_chan_in   [3-1 : 0];
-	smartflit_chanel_t    R1_chan_out  [3-1 : 0]; 
-	router_event_t R1_router_event [3-1 : 0]; 
-
-
-	/*******************
-	*		R2
-	*******************/
-	wire R2_clk;
-	wire R2_reset;
-
-	wire [RAw-1 :  0] R2_current_r_addr;
-
-	smartflit_chanel_t    R2_chan_in   [3-1 : 0];
-	smartflit_chanel_t    R2_chan_out  [3-1 : 0]; 
-	router_event_t R2_router_event [3-1 : 0]; 
-
-
-	/*******************
-	*		R3
-	*******************/
-	wire R3_clk;
-	wire R3_reset;
-
-	wire [RAw-1 :  0] R3_current_r_addr;
-
-	smartflit_chanel_t    R3_chan_in   [3-1 : 0];
-	smartflit_chanel_t    R3_chan_out  [3-1 : 0]; 
-	router_event_t R3_router_event [3-1 : 0]; 
-
-
-	/*******************
-	*		R4
-	*******************/
-	wire R4_clk;
-	wire R4_reset;
-
-	wire [RAw-1 :  0] R4_current_r_addr;
-
-	smartflit_chanel_t    R4_chan_in   [4-1 : 0];
-	smartflit_chanel_t    R4_chan_out  [4-1 : 0]; 
-	router_event_t R4_router_event [4-1 : 0]; 
-
-
-	/*******************
-	*		R5
-	*******************/
-	wire R5_clk;
-	wire R5_reset;
-
-	wire [RAw-1 :  0] R5_current_r_addr;
-
-	smartflit_chanel_t    R5_chan_in   [4-1 : 0];
-	smartflit_chanel_t    R5_chan_out  [4-1 : 0]; 
-	router_event_t R5_router_event [4-1 : 0]; 
-
-
-	/*******************
-	*		R6
-	*******************/
-	wire R6_clk;
-	wire R6_reset;
-
-	wire [RAw-1 :  0] R6_current_r_addr;
-
-	smartflit_chanel_t    R6_chan_in   [4-1 : 0];
-	smartflit_chanel_t    R6_chan_out  [4-1 : 0]; 
-	router_event_t R6_router_event [4-1 : 0]; 
-
-
-	/*******************
-	*		R7
-	*******************/
-	wire R7_clk;
-	wire R7_reset;
-
-	wire [RAw-1 :  0] R7_current_r_addr;
-
-	smartflit_chanel_t    R7_chan_in   [4-1 : 0];
-	smartflit_chanel_t    R7_chan_out  [4-1 : 0]; 
-	router_event_t R7_router_event [4-1 : 0]; 
-
-
-	/*******************
-	*		R12
-	*******************/
-	wire R12_clk;
-	wire R12_reset;
-
-	wire [RAw-1 :  0] R12_current_r_addr;
-
-	smartflit_chanel_t    R12_chan_in   [4-1 : 0];
-	smartflit_chanel_t    R12_chan_out  [4-1 : 0]; 
-	router_event_t R12_router_event [4-1 : 0]; 
-
-
-	/*******************
-	*		R13
-	*******************/
-	wire R13_clk;
-	wire R13_reset;
-
-	wire [RAw-1 :  0] R13_current_r_addr;
-
-	smartflit_chanel_t    R13_chan_in   [4-1 : 0];
-	smartflit_chanel_t    R13_chan_out  [4-1 : 0]; 
-	router_event_t R13_router_event [4-1 : 0]; 
-
-
-	/*******************
-	*		R14
-	*******************/
-	wire R14_clk;
-	wire R14_reset;
-
-	wire [RAw-1 :  0] R14_current_r_addr;
-
-	smartflit_chanel_t    R14_chan_in   [4-1 : 0];
-	smartflit_chanel_t    R14_chan_out  [4-1 : 0]; 
-	router_event_t R14_router_event [4-1 : 0]; 
-
-
-	/*******************
-	*		R15
-	*******************/
-	wire R15_clk;
-	wire R15_reset;
-
-	wire [RAw-1 :  0] R15_current_r_addr;
-
-	smartflit_chanel_t    R15_chan_in   [4-1 : 0];
-	smartflit_chanel_t    R15_chan_out  [4-1 : 0]; 
-	router_event_t R15_router_event [4-1 : 0]; 
-
-
-	/*******************
-	*		R8
-	*******************/
-	wire R8_clk;
-	wire R8_reset;
-
-	wire [RAw-1 :  0] R8_current_r_addr;
-
-	smartflit_chanel_t    R8_chan_in   [5-1 : 0];
-	smartflit_chanel_t    R8_chan_out  [5-1 : 0]; 
-	router_event_t R8_router_event [5-1 : 0]; 
-
-
-	/*******************
-	*		R9
-	*******************/
-	wire R9_clk;
-	wire R9_reset;
-
-	wire [RAw-1 :  0] R9_current_r_addr;
-
-	smartflit_chanel_t    R9_chan_in   [5-1 : 0];
-	smartflit_chanel_t    R9_chan_out  [5-1 : 0]; 
-	router_event_t R9_router_event [5-1 : 0]; 
-
-
-	/*******************
-	*		R10
-	*******************/
-	wire R10_clk;
-	wire R10_reset;
-
-	wire [RAw-1 :  0] R10_current_r_addr;
-
-	smartflit_chanel_t    R10_chan_in   [5-1 : 0];
-	smartflit_chanel_t    R10_chan_out  [5-1 : 0]; 
-	router_event_t R10_router_event [5-1 : 0]; 
-
-
-	/*******************
-	*		R11
-	*******************/
-	wire R11_clk;
-	wire R11_reset;
-
-	wire [RAw-1 :  0] R11_current_r_addr;
-
-	smartflit_chanel_t    R11_chan_in   [5-1 : 0];
-	smartflit_chanel_t    R11_chan_out  [5-1 : 0]; 
-	router_event_t R11_router_event [5-1 : 0]; 
-
+    input reset,clk;
+    
+    
+    /*******************
+    *        T0
+    *******************/
+    input  smartflit_chanel_t T0_chan_in;
+    output smartflit_chanel_t T0_chan_out;
+    output router_event_t T0_router_event;
+
+    /*******************
+    *        T1
+    *******************/
+    input  smartflit_chanel_t T1_chan_in;
+    output smartflit_chanel_t T1_chan_out;
+    output router_event_t T1_router_event;
+
+    /*******************
+    *        T2
+    *******************/
+    input  smartflit_chanel_t T2_chan_in;
+    output smartflit_chanel_t T2_chan_out;
+    output router_event_t T2_router_event;
+
+    /*******************
+    *        T3
+    *******************/
+    input  smartflit_chanel_t T3_chan_in;
+    output smartflit_chanel_t T3_chan_out;
+    output router_event_t T3_router_event;
+
+    /*******************
+    *        T4
+    *******************/
+    input  smartflit_chanel_t T4_chan_in;
+    output smartflit_chanel_t T4_chan_out;
+    output router_event_t T4_router_event;
+
+    /*******************
+    *        T5
+    *******************/
+    input  smartflit_chanel_t T5_chan_in;
+    output smartflit_chanel_t T5_chan_out;
+    output router_event_t T5_router_event;
+
+    /*******************
+    *        T6
+    *******************/
+    input  smartflit_chanel_t T6_chan_in;
+    output smartflit_chanel_t T6_chan_out;
+    output router_event_t T6_router_event;
+
+    /*******************
+    *        T7
+    *******************/
+    input  smartflit_chanel_t T7_chan_in;
+    output smartflit_chanel_t T7_chan_out;
+    output router_event_t T7_router_event;
+
+    /*******************
+    *        T8
+    *******************/
+    input  smartflit_chanel_t T8_chan_in;
+    output smartflit_chanel_t T8_chan_out;
+    output router_event_t T8_router_event;
+
+    /*******************
+    *        T9
+    *******************/
+    input  smartflit_chanel_t T9_chan_in;
+    output smartflit_chanel_t T9_chan_out;
+    output router_event_t T9_router_event;
+
+    /*******************
+    *        T10
+    *******************/
+    input  smartflit_chanel_t T10_chan_in;
+    output smartflit_chanel_t T10_chan_out;
+    output router_event_t T10_router_event;
+
+    /*******************
+    *        T11
+    *******************/
+    input  smartflit_chanel_t T11_chan_in;
+    output smartflit_chanel_t T11_chan_out;
+    output router_event_t T11_router_event;
+
+    /*******************
+    *        T12
+    *******************/
+    input  smartflit_chanel_t T12_chan_in;
+    output smartflit_chanel_t T12_chan_out;
+    output router_event_t T12_router_event;
+
+    /*******************
+    *        T13
+    *******************/
+    input  smartflit_chanel_t T13_chan_in;
+    output smartflit_chanel_t T13_chan_out;
+    output router_event_t T13_router_event;
+
+    /*******************
+    *        T14
+    *******************/
+    input  smartflit_chanel_t T14_chan_in;
+    output smartflit_chanel_t T14_chan_out;
+    output router_event_t T14_router_event;
+
+    /*******************
+    *        T15
+    *******************/
+    input  smartflit_chanel_t T15_chan_in;
+    output smartflit_chanel_t T15_chan_out;
+    output router_event_t T15_router_event;
+
+    /*******************
+    *        R0
+    *******************/
+    wire R0_clk;
+    wire R0_reset;
+    smartflit_chanel_t    R0_chan_in   [3-1 : 0];
+    smartflit_chanel_t    R0_chan_out  [3-1 : 0]; 
+    router_event_t R0_router_event [3-1 : 0]; 
+
+    /*******************
+    *        R1
+    *******************/
+    wire R1_clk;
+    wire R1_reset;
+    smartflit_chanel_t    R1_chan_in   [3-1 : 0];
+    smartflit_chanel_t    R1_chan_out  [3-1 : 0]; 
+    router_event_t R1_router_event [3-1 : 0]; 
+
+    /*******************
+    *        R2
+    *******************/
+    wire R2_clk;
+    wire R2_reset;
+    smartflit_chanel_t    R2_chan_in   [3-1 : 0];
+    smartflit_chanel_t    R2_chan_out  [3-1 : 0]; 
+    router_event_t R2_router_event [3-1 : 0]; 
+
+    /*******************
+    *        R3
+    *******************/
+    wire R3_clk;
+    wire R3_reset;
+    smartflit_chanel_t    R3_chan_in   [3-1 : 0];
+    smartflit_chanel_t    R3_chan_out  [3-1 : 0]; 
+    router_event_t R3_router_event [3-1 : 0]; 
+
+    /*******************
+    *        R4
+    *******************/
+    wire R4_clk;
+    wire R4_reset;
+    smartflit_chanel_t    R4_chan_in   [4-1 : 0];
+    smartflit_chanel_t    R4_chan_out  [4-1 : 0]; 
+    router_event_t R4_router_event [4-1 : 0]; 
+
+    /*******************
+    *        R5
+    *******************/
+    wire R5_clk;
+    wire R5_reset;
+    smartflit_chanel_t    R5_chan_in   [4-1 : 0];
+    smartflit_chanel_t    R5_chan_out  [4-1 : 0]; 
+    router_event_t R5_router_event [4-1 : 0]; 
+
+    /*******************
+    *        R6
+    *******************/
+    wire R6_clk;
+    wire R6_reset;
+    smartflit_chanel_t    R6_chan_in   [4-1 : 0];
+    smartflit_chanel_t    R6_chan_out  [4-1 : 0]; 
+    router_event_t R6_router_event [4-1 : 0]; 
+
+    /*******************
+    *        R7
+    *******************/
+    wire R7_clk;
+    wire R7_reset;
+    smartflit_chanel_t    R7_chan_in   [4-1 : 0];
+    smartflit_chanel_t    R7_chan_out  [4-1 : 0]; 
+    router_event_t R7_router_event [4-1 : 0]; 
+
+    /*******************
+    *        R12
+    *******************/
+    wire R12_clk;
+    wire R12_reset;
+    smartflit_chanel_t    R12_chan_in   [4-1 : 0];
+    smartflit_chanel_t    R12_chan_out  [4-1 : 0]; 
+    router_event_t R12_router_event [4-1 : 0]; 
+
+    /*******************
+    *        R13
+    *******************/
+    wire R13_clk;
+    wire R13_reset;
+    smartflit_chanel_t    R13_chan_in   [4-1 : 0];
+    smartflit_chanel_t    R13_chan_out  [4-1 : 0]; 
+    router_event_t R13_router_event [4-1 : 0]; 
+
+    /*******************
+    *        R14
+    *******************/
+    wire R14_clk;
+    wire R14_reset;
+    smartflit_chanel_t    R14_chan_in   [4-1 : 0];
+    smartflit_chanel_t    R14_chan_out  [4-1 : 0]; 
+    router_event_t R14_router_event [4-1 : 0]; 
+
+    /*******************
+    *        R15
+    *******************/
+    wire R15_clk;
+    wire R15_reset;
+    smartflit_chanel_t    R15_chan_in   [4-1 : 0];
+    smartflit_chanel_t    R15_chan_out  [4-1 : 0]; 
+    router_event_t R15_router_event [4-1 : 0]; 
+
+    /*******************
+    *        R8
+    *******************/
+    wire R8_clk;
+    wire R8_reset;
+    smartflit_chanel_t    R8_chan_in   [5-1 : 0];
+    smartflit_chanel_t    R8_chan_out  [5-1 : 0]; 
+    router_event_t R8_router_event [5-1 : 0]; 
+
+    /*******************
+    *        R9
+    *******************/
+    wire R9_clk;
+    wire R9_reset;
+    smartflit_chanel_t    R9_chan_in   [5-1 : 0];
+    smartflit_chanel_t    R9_chan_out  [5-1 : 0]; 
+    router_event_t R9_router_event [5-1 : 0]; 
+
+    /*******************
+    *        R10
+    *******************/
+    wire R10_clk;
+    wire R10_reset;
+    smartflit_chanel_t    R10_chan_in   [5-1 : 0];
+    smartflit_chanel_t    R10_chan_out  [5-1 : 0]; 
+    router_event_t R10_router_event [5-1 : 0]; 
+
+    /*******************
+    *        R11
+    *******************/
+    wire R11_clk;
+    wire R11_reset;
+    smartflit_chanel_t    R11_chan_in   [5-1 : 0];
+    smartflit_chanel_t    R11_chan_out  [5-1 : 0]; 
+    router_event_t R11_router_event [5-1 : 0]; 
 
     
-    	
-	/*******************
-	*		R0
-	*******************/
-	router_top #(
-		.NOC_ID(NOC_ID),
-		.P(3)		
-	)
-	R0
-	(	
-		.clk(R0_clk), 
-		.reset(R0_reset),
-		.current_r_id(0),
-		.current_r_addr  (R0_current_r_addr), 
-		.chan_in   (R0_chan_in), 
-		.chan_out  (R0_chan_out),
-		.router_event (R0_router_event)
-	);
-
-		assign R0_clk = clk;
-		assign R0_reset = reset;
-		assign R0_current_r_addr = 0;
-//Connect R0 port 0 to  T0 port 0
- 		assign R0_chan_in [0]  = T0_chan_in;
- 		assign T0_chan_out = R0_chan_out [0];
- 		assign T0_router_event = R0_router_event [0];
-//Connect R0 port 1 to  R14 port 3
- 		assign R0_chan_in [1]   = R14_chan_out [3];
-//Connect R0 port 2 to  R13 port 3
- 		assign R0_chan_in [2]   = R13_chan_out [3];
-	
-	/*******************
-	*		R1
-	*******************/
-	router_top #(
-		.NOC_ID(NOC_ID),
-		.P(3)		
-	)
-	R1
-	(	
-		.clk(R1_clk), 
-		.reset(R1_reset),
-		.current_r_id(1),
-		.current_r_addr  (R1_current_r_addr), 
-		.chan_in   (R1_chan_in), 
-		.chan_out  (R1_chan_out),
-		.router_event (R1_router_event)
-	);
-
-		assign R1_clk = clk;
-		assign R1_reset = reset;
-		assign R1_current_r_addr = 1;
-//Connect R1 port 0 to  T1 port 0
- 		assign R1_chan_in [0]  = T1_chan_in;
- 		assign T1_chan_out = R1_chan_out [0];
- 		assign T1_router_event = R1_router_event [0];
-//Connect R1 port 1 to  R7 port 3
- 		assign R1_chan_in [1]   = R7_chan_out [3];
-//Connect R1 port 2 to  R2 port 2
- 		assign R1_chan_in [2]   = R2_chan_out [2];
-	
-	/*******************
-	*		R2
-	*******************/
-	router_top #(
-		.NOC_ID(NOC_ID),
-		.P(3)		
-	)
-	R2
-	(	
-		.clk(R2_clk), 
-		.reset(R2_reset),
-		.current_r_id(2),
-		.current_r_addr  (R2_current_r_addr), 
-		.chan_in   (R2_chan_in), 
-		.chan_out  (R2_chan_out),
-		.router_event (R2_router_event)
-	);
-
-		assign R2_clk = clk;
-		assign R2_reset = reset;
-		assign R2_current_r_addr = 2;
-//Connect R2 port 0 to  T2 port 0
- 		assign R2_chan_in [0]  = T2_chan_in;
- 		assign T2_chan_out = R2_chan_out [0];
- 		assign T2_router_event = R2_router_event [0];
-//Connect R2 port 1 to  R15 port 2
- 		assign R2_chan_in [1]   = R15_chan_out [2];
-//Connect R2 port 2 to  R1 port 2
- 		assign R2_chan_in [2]   = R1_chan_out [2];
-	
-	/*******************
-	*		R3
-	*******************/
-	router_top #(
-		.NOC_ID(NOC_ID),
-		.P(3)		
-	)
-	R3
-	(	
-		.clk(R3_clk), 
-		.reset(R3_reset),
-		.current_r_id(3),
-		.current_r_addr  (R3_current_r_addr), 
-		.chan_in   (R3_chan_in), 
-		.chan_out  (R3_chan_out),
-		.router_event (R3_router_event)
-	);
-
-		assign R3_clk = clk;
-		assign R3_reset = reset;
-		assign R3_current_r_addr = 3;
-//Connect R3 port 0 to  T3 port 0
- 		assign R3_chan_in [0]  = T3_chan_in;
- 		assign T3_chan_out = R3_chan_out [0];
- 		assign T3_router_event = R3_router_event [0];
-//Connect R3 port 1 to  R15 port 3
- 		assign R3_chan_in [1]   = R15_chan_out [3];
-//Connect R3 port 2 to  R4 port 2
- 		assign R3_chan_in [2]   = R4_chan_out [2];
-	
-	/*******************
-	*		R4
-	*******************/
-	router_top #(
-		.NOC_ID(NOC_ID),
-		.P(4)		
-	)
-	R4
-	(	
-		.clk(R4_clk), 
-		.reset(R4_reset),
-		.current_r_id(4),
-		.current_r_addr  (R4_current_r_addr), 
-		.chan_in   (R4_chan_in), 
-		.chan_out  (R4_chan_out),
-		.router_event (R4_router_event)
-	);
-
-		assign R4_clk = clk;
-		assign R4_reset = reset;
-		assign R4_current_r_addr = 4;
-//Connect R4 port 0 to  T4 port 0
- 		assign R4_chan_in [0]  = T4_chan_in;
- 		assign T4_chan_out = R4_chan_out [0];
- 		assign T4_router_event = R4_router_event [0];
-//Connect R4 port 1 to  R9 port 2
- 		assign R4_chan_in [1]   = R9_chan_out [2];
-//Connect R4 port 2 to  R3 port 2
- 		assign R4_chan_in [2]   = R3_chan_out [2];
-//Connect R4 port 3 to  R6 port 3
- 		assign R4_chan_in [3]   = R6_chan_out [3];
-	
-	/*******************
-	*		R5
-	*******************/
-	router_top #(
-		.NOC_ID(NOC_ID),
-		.P(4)		
-	)
-	R5
-	(	
-		.clk(R5_clk), 
-		.reset(R5_reset),
-		.current_r_id(5),
-		.current_r_addr  (R5_current_r_addr), 
-		.chan_in   (R5_chan_in), 
-		.chan_out  (R5_chan_out),
-		.router_event (R5_router_event)
-	);
-
-		assign R5_clk = clk;
-		assign R5_reset = reset;
-		assign R5_current_r_addr = 5;
-//Connect R5 port 0 to  T5 port 0
- 		assign R5_chan_in [0]  = T5_chan_in;
- 		assign T5_chan_out = R5_chan_out [0];
- 		assign T5_router_event = R5_router_event [0];
-//Connect R5 port 1 to  R11 port 4
- 		assign R5_chan_in [1]   = R11_chan_out [4];
-//Connect R5 port 2 to  R6 port 2
- 		assign R5_chan_in [2]   = R6_chan_out [2];
-//Connect R5 port 3 to  R13 port 2
- 		assign R5_chan_in [3]   = R13_chan_out [2];
-	
-	/*******************
-	*		R6
-	*******************/
-	router_top #(
-		.NOC_ID(NOC_ID),
-		.P(4)		
-	)
-	R6
-	(	
-		.clk(R6_clk), 
-		.reset(R6_reset),
-		.current_r_id(6),
-		.current_r_addr  (R6_current_r_addr), 
-		.chan_in   (R6_chan_in), 
-		.chan_out  (R6_chan_out),
-		.router_event (R6_router_event)
-	);
-
-		assign R6_clk = clk;
-		assign R6_reset = reset;
-		assign R6_current_r_addr = 6;
-//Connect R6 port 0 to  T6 port 0
- 		assign R6_chan_in [0]  = T6_chan_in;
- 		assign T6_chan_out = R6_chan_out [0];
- 		assign T6_router_event = R6_router_event [0];
-//Connect R6 port 1 to  R9 port 3
- 		assign R6_chan_in [1]   = R9_chan_out [3];
-//Connect R6 port 2 to  R5 port 2
- 		assign R6_chan_in [2]   = R5_chan_out [2];
-//Connect R6 port 3 to  R4 port 3
- 		assign R6_chan_in [3]   = R4_chan_out [3];
-	
-	/*******************
-	*		R7
-	*******************/
-	router_top #(
-		.NOC_ID(NOC_ID),
-		.P(4)		
-	)
-	R7
-	(	
-		.clk(R7_clk), 
-		.reset(R7_reset),
-		.current_r_id(7),
-		.current_r_addr  (R7_current_r_addr), 
-		.chan_in   (R7_chan_in), 
-		.chan_out  (R7_chan_out),
-		.router_event (R7_router_event)
-	);
-
-		assign R7_clk = clk;
-		assign R7_reset = reset;
-		assign R7_current_r_addr = 7;
-//Connect R7 port 0 to  T7 port 0
- 		assign R7_chan_in [0]  = T7_chan_in;
- 		assign T7_chan_out = R7_chan_out [0];
- 		assign T7_router_event = R7_router_event [0];
-//Connect R7 port 1 to  R12 port 3
- 		assign R7_chan_in [1]   = R12_chan_out [3];
-//Connect R7 port 2 to  R14 port 2
- 		assign R7_chan_in [2]   = R14_chan_out [2];
-//Connect R7 port 3 to  R1 port 1
- 		assign R7_chan_in [3]   = R1_chan_out [1];
-	
-	/*******************
-	*		R12
-	*******************/
-	router_top #(
-		.NOC_ID(NOC_ID),
-		.P(4)		
-	)
-	R12
-	(	
-		.clk(R12_clk), 
-		.reset(R12_reset),
-		.current_r_id(8),
-		.current_r_addr  (R12_current_r_addr), 
-		.chan_in   (R12_chan_in), 
-		.chan_out  (R12_chan_out),
-		.router_event (R12_router_event)
-	);
-
-		assign R12_clk = clk;
-		assign R12_reset = reset;
-		assign R12_current_r_addr = 8;
-//Connect R12 port 0 to  T8 port 0
- 		assign R12_chan_in [0]  = T8_chan_in;
- 		assign T8_chan_out = R12_chan_out [0];
- 		assign T8_router_event = R12_router_event [0];
-//Connect R12 port 1 to  R8 port 4
- 		assign R12_chan_in [1]   = R8_chan_out [4];
-//Connect R12 port 2 to  R10 port 3
- 		assign R12_chan_in [2]   = R10_chan_out [3];
-//Connect R12 port 3 to  R7 port 1
- 		assign R12_chan_in [3]   = R7_chan_out [1];
-	
-	/*******************
-	*		R13
-	*******************/
-	router_top #(
-		.NOC_ID(NOC_ID),
-		.P(4)		
-	)
-	R13
-	(	
-		.clk(R13_clk), 
-		.reset(R13_reset),
-		.current_r_id(9),
-		.current_r_addr  (R13_current_r_addr), 
-		.chan_in   (R13_chan_in), 
-		.chan_out  (R13_chan_out),
-		.router_event (R13_router_event)
-	);
-
-		assign R13_clk = clk;
-		assign R13_reset = reset;
-		assign R13_current_r_addr = 9;
-//Connect R13 port 0 to  T9 port 0
- 		assign R13_chan_in [0]  = T9_chan_in;
- 		assign T9_chan_out = R13_chan_out [0];
- 		assign T9_router_event = R13_router_event [0];
-//Connect R13 port 1 to  R8 port 2
- 		assign R13_chan_in [1]   = R8_chan_out [2];
-//Connect R13 port 2 to  R5 port 3
- 		assign R13_chan_in [2]   = R5_chan_out [3];
-//Connect R13 port 3 to  R0 port 2
- 		assign R13_chan_in [3]   = R0_chan_out [2];
-	
-	/*******************
-	*		R14
-	*******************/
-	router_top #(
-		.NOC_ID(NOC_ID),
-		.P(4)		
-	)
-	R14
-	(	
-		.clk(R14_clk), 
-		.reset(R14_reset),
-		.current_r_id(10),
-		.current_r_addr  (R14_current_r_addr), 
-		.chan_in   (R14_chan_in), 
-		.chan_out  (R14_chan_out),
-		.router_event (R14_router_event)
-	);
-
-		assign R14_clk = clk;
-		assign R14_reset = reset;
-		assign R14_current_r_addr = 10;
-//Connect R14 port 0 to  T10 port 0
- 		assign R14_chan_in [0]  = T10_chan_in;
- 		assign T10_chan_out = R14_chan_out [0];
- 		assign T10_router_event = R14_router_event [0];
-//Connect R14 port 1 to  R8 port 3
- 		assign R14_chan_in [1]   = R8_chan_out [3];
-//Connect R14 port 2 to  R7 port 2
- 		assign R14_chan_in [2]   = R7_chan_out [2];
-//Connect R14 port 3 to  R0 port 1
- 		assign R14_chan_in [3]   = R0_chan_out [1];
-	
-	/*******************
-	*		R15
-	*******************/
-	router_top #(
-		.NOC_ID(NOC_ID),
-		.P(4)		
-	)
-	R15
-	(	
-		.clk(R15_clk), 
-		.reset(R15_reset),
-		.current_r_id(11),
-		.current_r_addr  (R15_current_r_addr), 
-		.chan_in   (R15_chan_in), 
-		.chan_out  (R15_chan_out),
-		.router_event (R15_router_event)
-	);
-
-		assign R15_clk = clk;
-		assign R15_reset = reset;
-		assign R15_current_r_addr = 11;
-//Connect R15 port 0 to  T11 port 0
- 		assign R15_chan_in [0]  = T11_chan_in;
- 		assign T11_chan_out = R15_chan_out [0];
- 		assign T11_router_event = R15_router_event [0];
-//Connect R15 port 1 to  R10 port 4
- 		assign R15_chan_in [1]   = R10_chan_out [4];
-//Connect R15 port 2 to  R2 port 1
- 		assign R15_chan_in [2]   = R2_chan_out [1];
-//Connect R15 port 3 to  R3 port 1
- 		assign R15_chan_in [3]   = R3_chan_out [1];
-	
-	/*******************
-	*		R8
-	*******************/
-	router_top #(
-		.NOC_ID(NOC_ID),
-		.P(5)		
-	)
-	R8
-	(	
-		.clk(R8_clk), 
-		.reset(R8_reset),
-		.current_r_id(12),
-		.current_r_addr  (R8_current_r_addr), 
-		.chan_in   (R8_chan_in), 
-		.chan_out  (R8_chan_out),
-		.router_event (R8_router_event)
-	);
-
-		assign R8_clk = clk;
-		assign R8_reset = reset;
-		assign R8_current_r_addr = 12;
-//Connect R8 port 0 to  T12 port 0
- 		assign R8_chan_in [0]  = T12_chan_in;
- 		assign T12_chan_out = R8_chan_out [0];
- 		assign T12_router_event = R8_router_event [0];
-//Connect R8 port 1 to  R11 port 1
- 		assign R8_chan_in [1]   = R11_chan_out [1];
-//Connect R8 port 2 to  R13 port 1
- 		assign R8_chan_in [2]   = R13_chan_out [1];
-//Connect R8 port 3 to  R14 port 1
- 		assign R8_chan_in [3]   = R14_chan_out [1];
-//Connect R8 port 4 to  R12 port 1
- 		assign R8_chan_in [4]   = R12_chan_out [1];
-	
-	/*******************
-	*		R9
-	*******************/
-	router_top #(
-		.NOC_ID(NOC_ID),
-		.P(5)		
-	)
-	R9
-	(	
-		.clk(R9_clk), 
-		.reset(R9_reset),
-		.current_r_id(13),
-		.current_r_addr  (R9_current_r_addr), 
-		.chan_in   (R9_chan_in), 
-		.chan_out  (R9_chan_out),
-		.router_event (R9_router_event)
-	);
-
-		assign R9_clk = clk;
-		assign R9_reset = reset;
-		assign R9_current_r_addr = 13;
-//Connect R9 port 0 to  T13 port 0
- 		assign R9_chan_in [0]  = T13_chan_in;
- 		assign T13_chan_out = R9_chan_out [0];
- 		assign T13_router_event = R9_router_event [0];
-//Connect R9 port 1 to  R11 port 3
- 		assign R9_chan_in [1]   = R11_chan_out [3];
-//Connect R9 port 2 to  R4 port 1
- 		assign R9_chan_in [2]   = R4_chan_out [1];
-//Connect R9 port 3 to  R6 port 1
- 		assign R9_chan_in [3]   = R6_chan_out [1];
-//Connect R9 port 4 to  R10 port 2
- 		assign R9_chan_in [4]   = R10_chan_out [2];
-	
-	/*******************
-	*		R10
-	*******************/
-	router_top #(
-		.NOC_ID(NOC_ID),
-		.P(5)		
-	)
-	R10
-	(	
-		.clk(R10_clk), 
-		.reset(R10_reset),
-		.current_r_id(14),
-		.current_r_addr  (R10_current_r_addr), 
-		.chan_in   (R10_chan_in), 
-		.chan_out  (R10_chan_out),
-		.router_event (R10_router_event)
-	);
-
-		assign R10_clk = clk;
-		assign R10_reset = reset;
-		assign R10_current_r_addr = 14;
-//Connect R10 port 0 to  T14 port 0
- 		assign R10_chan_in [0]  = T14_chan_in;
- 		assign T14_chan_out = R10_chan_out [0];
- 		assign T14_router_event = R10_router_event [0];
-//Connect R10 port 1 to  R11 port 2
- 		assign R10_chan_in [1]   = R11_chan_out [2];
-//Connect R10 port 2 to  R9 port 4
- 		assign R10_chan_in [2]   = R9_chan_out [4];
-//Connect R10 port 3 to  R12 port 2
- 		assign R10_chan_in [3]   = R12_chan_out [2];
-//Connect R10 port 4 to  R15 port 1
- 		assign R10_chan_in [4]   = R15_chan_out [1];
-	
-	/*******************
-	*		R11
-	*******************/
-	router_top #(
-		.NOC_ID(NOC_ID),
-		.P(5)		
-	)
-	R11
-	(	
-		.clk(R11_clk), 
-		.reset(R11_reset),
-		.current_r_id(15),
-		.current_r_addr  (R11_current_r_addr), 
-		.chan_in   (R11_chan_in), 
-		.chan_out  (R11_chan_out),
-		.router_event (R11_router_event)
-	);
-
-		assign R11_clk = clk;
-		assign R11_reset = reset;
-		assign R11_current_r_addr = 15;
-//Connect R11 port 0 to  T15 port 0
- 		assign R11_chan_in [0]  = T15_chan_in;
- 		assign T15_chan_out = R11_chan_out [0];
- 		assign T15_router_event = R11_router_event [0];
-//Connect R11 port 1 to  R8 port 1
- 		assign R11_chan_in [1]   = R8_chan_out [1];
-//Connect R11 port 2 to  R10 port 1
- 		assign R11_chan_in [2]   = R10_chan_out [1];
-//Connect R11 port 3 to  R9 port 1
- 		assign R11_chan_in [3]   = R9_chan_out [1];
-//Connect R11 port 4 to  R5 port 1
- 		assign R11_chan_in [4]   = R5_chan_out [1];
+        
+    /*******************
+    *        R0
+    *******************/
+    router_config_t R0_router_config_in;
+    router_top #(
+        .ROUTER_ID(0),
+        .P(3)
+    ) R0 (
+        .clk(R0_clk), 
+        .reset(R0_reset),
+        .router_config_in(R0_router_config_in),
+        .chan_in   (R0_chan_in), 
+        .chan_out  (R0_chan_out),
+        .router_event (R0_router_event)
+    );
+
+        assign R0_clk = clk;
+        assign R0_reset = reset;
+        assign R0_router_config_in.router_addr = 0;
+        assign R0_router_config_in.router_id = 0;
+    //Connect R0 port 0 to  T0 port 0
+    assign R0_chan_in [0]  = T0_chan_in;
+    assign T0_chan_out = R0_chan_out [0];
+    assign T0_router_event = R0_router_event [0];
+    //Connect R0 port 1 to  R14 port 3
+    assign R0_chan_in [1]   = R14_chan_out [3];
+    //Connect R0 port 2 to  R13 port 3
+    assign R0_chan_in [2]   = R13_chan_out [3];
+    
+    /*******************
+    *        R1
+    *******************/
+    router_config_t R1_router_config_in;
+    router_top #(
+        .ROUTER_ID(1),
+        .P(3)
+    ) R1 (
+        .clk(R1_clk), 
+        .reset(R1_reset),
+        .router_config_in(R1_router_config_in),
+        .chan_in   (R1_chan_in), 
+        .chan_out  (R1_chan_out),
+        .router_event (R1_router_event)
+    );
+
+        assign R1_clk = clk;
+        assign R1_reset = reset;
+        assign R1_router_config_in.router_addr = 1;
+        assign R1_router_config_in.router_id = 1;
+    //Connect R1 port 0 to  T1 port 0
+    assign R1_chan_in [0]  = T1_chan_in;
+    assign T1_chan_out = R1_chan_out [0];
+    assign T1_router_event = R1_router_event [0];
+    //Connect R1 port 1 to  R7 port 3
+    assign R1_chan_in [1]   = R7_chan_out [3];
+    //Connect R1 port 2 to  R2 port 2
+    assign R1_chan_in [2]   = R2_chan_out [2];
+    
+    /*******************
+    *        R2
+    *******************/
+    router_config_t R2_router_config_in;
+    router_top #(
+        .ROUTER_ID(2),
+        .P(3)
+    ) R2 (
+        .clk(R2_clk), 
+        .reset(R2_reset),
+        .router_config_in(R2_router_config_in),
+        .chan_in   (R2_chan_in), 
+        .chan_out  (R2_chan_out),
+        .router_event (R2_router_event)
+    );
+
+        assign R2_clk = clk;
+        assign R2_reset = reset;
+        assign R2_router_config_in.router_addr = 2;
+        assign R2_router_config_in.router_id = 2;
+    //Connect R2 port 0 to  T2 port 0
+    assign R2_chan_in [0]  = T2_chan_in;
+    assign T2_chan_out = R2_chan_out [0];
+    assign T2_router_event = R2_router_event [0];
+    //Connect R2 port 1 to  R15 port 2
+    assign R2_chan_in [1]   = R15_chan_out [2];
+    //Connect R2 port 2 to  R1 port 2
+    assign R2_chan_in [2]   = R1_chan_out [2];
+    
+    /*******************
+    *        R3
+    *******************/
+    router_config_t R3_router_config_in;
+    router_top #(
+        .ROUTER_ID(3),
+        .P(3)
+    ) R3 (
+        .clk(R3_clk), 
+        .reset(R3_reset),
+        .router_config_in(R3_router_config_in),
+        .chan_in   (R3_chan_in), 
+        .chan_out  (R3_chan_out),
+        .router_event (R3_router_event)
+    );
+
+        assign R3_clk = clk;
+        assign R3_reset = reset;
+        assign R3_router_config_in.router_addr = 3;
+        assign R3_router_config_in.router_id = 3;
+    //Connect R3 port 0 to  T3 port 0
+    assign R3_chan_in [0]  = T3_chan_in;
+    assign T3_chan_out = R3_chan_out [0];
+    assign T3_router_event = R3_router_event [0];
+    //Connect R3 port 1 to  R15 port 3
+    assign R3_chan_in [1]   = R15_chan_out [3];
+    //Connect R3 port 2 to  R4 port 2
+    assign R3_chan_in [2]   = R4_chan_out [2];
+    
+    /*******************
+    *        R4
+    *******************/
+    router_config_t R4_router_config_in;
+    router_top #(
+        .ROUTER_ID(4),
+        .P(4)
+    ) R4 (
+        .clk(R4_clk), 
+        .reset(R4_reset),
+        .router_config_in(R4_router_config_in),
+        .chan_in   (R4_chan_in), 
+        .chan_out  (R4_chan_out),
+        .router_event (R4_router_event)
+    );
+
+        assign R4_clk = clk;
+        assign R4_reset = reset;
+        assign R4_router_config_in.router_addr = 4;
+        assign R4_router_config_in.router_id = 4;
+    //Connect R4 port 0 to  T4 port 0
+    assign R4_chan_in [0]  = T4_chan_in;
+    assign T4_chan_out = R4_chan_out [0];
+    assign T4_router_event = R4_router_event [0];
+    //Connect R4 port 1 to  R9 port 2
+    assign R4_chan_in [1]   = R9_chan_out [2];
+    //Connect R4 port 2 to  R3 port 2
+    assign R4_chan_in [2]   = R3_chan_out [2];
+    //Connect R4 port 3 to  R6 port 3
+    assign R4_chan_in [3]   = R6_chan_out [3];
+    
+    /*******************
+    *        R5
+    *******************/
+    router_config_t R5_router_config_in;
+    router_top #(
+        .ROUTER_ID(5),
+        .P(4)
+    ) R5 (
+        .clk(R5_clk), 
+        .reset(R5_reset),
+        .router_config_in(R5_router_config_in),
+        .chan_in   (R5_chan_in), 
+        .chan_out  (R5_chan_out),
+        .router_event (R5_router_event)
+    );
+
+        assign R5_clk = clk;
+        assign R5_reset = reset;
+        assign R5_router_config_in.router_addr = 5;
+        assign R5_router_config_in.router_id = 5;
+    //Connect R5 port 0 to  T5 port 0
+    assign R5_chan_in [0]  = T5_chan_in;
+    assign T5_chan_out = R5_chan_out [0];
+    assign T5_router_event = R5_router_event [0];
+    //Connect R5 port 1 to  R11 port 4
+    assign R5_chan_in [1]   = R11_chan_out [4];
+    //Connect R5 port 2 to  R6 port 2
+    assign R5_chan_in [2]   = R6_chan_out [2];
+    //Connect R5 port 3 to  R13 port 2
+    assign R5_chan_in [3]   = R13_chan_out [2];
+    
+    /*******************
+    *        R6
+    *******************/
+    router_config_t R6_router_config_in;
+    router_top #(
+        .ROUTER_ID(6),
+        .P(4)
+    ) R6 (
+        .clk(R6_clk), 
+        .reset(R6_reset),
+        .router_config_in(R6_router_config_in),
+        .chan_in   (R6_chan_in), 
+        .chan_out  (R6_chan_out),
+        .router_event (R6_router_event)
+    );
+
+        assign R6_clk = clk;
+        assign R6_reset = reset;
+        assign R6_router_config_in.router_addr = 6;
+        assign R6_router_config_in.router_id = 6;
+    //Connect R6 port 0 to  T6 port 0
+    assign R6_chan_in [0]  = T6_chan_in;
+    assign T6_chan_out = R6_chan_out [0];
+    assign T6_router_event = R6_router_event [0];
+    //Connect R6 port 1 to  R9 port 3
+    assign R6_chan_in [1]   = R9_chan_out [3];
+    //Connect R6 port 2 to  R5 port 2
+    assign R6_chan_in [2]   = R5_chan_out [2];
+    //Connect R6 port 3 to  R4 port 3
+    assign R6_chan_in [3]   = R4_chan_out [3];
+    
+    /*******************
+    *        R7
+    *******************/
+    router_config_t R7_router_config_in;
+    router_top #(
+        .ROUTER_ID(7),
+        .P(4)
+    ) R7 (
+        .clk(R7_clk), 
+        .reset(R7_reset),
+        .router_config_in(R7_router_config_in),
+        .chan_in   (R7_chan_in), 
+        .chan_out  (R7_chan_out),
+        .router_event (R7_router_event)
+    );
+
+        assign R7_clk = clk;
+        assign R7_reset = reset;
+        assign R7_router_config_in.router_addr = 7;
+        assign R7_router_config_in.router_id = 7;
+    //Connect R7 port 0 to  T7 port 0
+    assign R7_chan_in [0]  = T7_chan_in;
+    assign T7_chan_out = R7_chan_out [0];
+    assign T7_router_event = R7_router_event [0];
+    //Connect R7 port 1 to  R12 port 3
+    assign R7_chan_in [1]   = R12_chan_out [3];
+    //Connect R7 port 2 to  R14 port 2
+    assign R7_chan_in [2]   = R14_chan_out [2];
+    //Connect R7 port 3 to  R1 port 1
+    assign R7_chan_in [3]   = R1_chan_out [1];
+    
+    /*******************
+    *        R12
+    *******************/
+    router_config_t R12_router_config_in;
+    router_top #(
+        .ROUTER_ID(8),
+        .P(4)
+    ) R12 (
+        .clk(R12_clk), 
+        .reset(R12_reset),
+        .router_config_in(R12_router_config_in),
+        .chan_in   (R12_chan_in), 
+        .chan_out  (R12_chan_out),
+        .router_event (R12_router_event)
+    );
+
+        assign R12_clk = clk;
+        assign R12_reset = reset;
+        assign R12_router_config_in.router_addr = 8;
+        assign R12_router_config_in.router_id = 8;
+    //Connect R12 port 0 to  T8 port 0
+    assign R12_chan_in [0]  = T8_chan_in;
+    assign T8_chan_out = R12_chan_out [0];
+    assign T8_router_event = R12_router_event [0];
+    //Connect R12 port 1 to  R8 port 4
+    assign R12_chan_in [1]   = R8_chan_out [4];
+    //Connect R12 port 2 to  R10 port 3
+    assign R12_chan_in [2]   = R10_chan_out [3];
+    //Connect R12 port 3 to  R7 port 1
+    assign R12_chan_in [3]   = R7_chan_out [1];
+    
+    /*******************
+    *        R13
+    *******************/
+    router_config_t R13_router_config_in;
+    router_top #(
+        .ROUTER_ID(9),
+        .P(4)
+    ) R13 (
+        .clk(R13_clk), 
+        .reset(R13_reset),
+        .router_config_in(R13_router_config_in),
+        .chan_in   (R13_chan_in), 
+        .chan_out  (R13_chan_out),
+        .router_event (R13_router_event)
+    );
+
+        assign R13_clk = clk;
+        assign R13_reset = reset;
+        assign R13_router_config_in.router_addr = 9;
+        assign R13_router_config_in.router_id = 9;
+    //Connect R13 port 0 to  T9 port 0
+    assign R13_chan_in [0]  = T9_chan_in;
+    assign T9_chan_out = R13_chan_out [0];
+    assign T9_router_event = R13_router_event [0];
+    //Connect R13 port 1 to  R8 port 2
+    assign R13_chan_in [1]   = R8_chan_out [2];
+    //Connect R13 port 2 to  R5 port 3
+    assign R13_chan_in [2]   = R5_chan_out [3];
+    //Connect R13 port 3 to  R0 port 2
+    assign R13_chan_in [3]   = R0_chan_out [2];
+    
+    /*******************
+    *        R14
+    *******************/
+    router_config_t R14_router_config_in;
+    router_top #(
+        .ROUTER_ID(10),
+        .P(4)
+    ) R14 (
+        .clk(R14_clk), 
+        .reset(R14_reset),
+        .router_config_in(R14_router_config_in),
+        .chan_in   (R14_chan_in), 
+        .chan_out  (R14_chan_out),
+        .router_event (R14_router_event)
+    );
+
+        assign R14_clk = clk;
+        assign R14_reset = reset;
+        assign R14_router_config_in.router_addr = 10;
+        assign R14_router_config_in.router_id = 10;
+    //Connect R14 port 0 to  T10 port 0
+    assign R14_chan_in [0]  = T10_chan_in;
+    assign T10_chan_out = R14_chan_out [0];
+    assign T10_router_event = R14_router_event [0];
+    //Connect R14 port 1 to  R8 port 3
+    assign R14_chan_in [1]   = R8_chan_out [3];
+    //Connect R14 port 2 to  R7 port 2
+    assign R14_chan_in [2]   = R7_chan_out [2];
+    //Connect R14 port 3 to  R0 port 1
+    assign R14_chan_in [3]   = R0_chan_out [1];
+    
+    /*******************
+    *        R15
+    *******************/
+    router_config_t R15_router_config_in;
+    router_top #(
+        .ROUTER_ID(11),
+        .P(4)
+    ) R15 (
+        .clk(R15_clk), 
+        .reset(R15_reset),
+        .router_config_in(R15_router_config_in),
+        .chan_in   (R15_chan_in), 
+        .chan_out  (R15_chan_out),
+        .router_event (R15_router_event)
+    );
+
+        assign R15_clk = clk;
+        assign R15_reset = reset;
+        assign R15_router_config_in.router_addr = 11;
+        assign R15_router_config_in.router_id = 11;
+    //Connect R15 port 0 to  T11 port 0
+    assign R15_chan_in [0]  = T11_chan_in;
+    assign T11_chan_out = R15_chan_out [0];
+    assign T11_router_event = R15_router_event [0];
+    //Connect R15 port 1 to  R10 port 4
+    assign R15_chan_in [1]   = R10_chan_out [4];
+    //Connect R15 port 2 to  R2 port 1
+    assign R15_chan_in [2]   = R2_chan_out [1];
+    //Connect R15 port 3 to  R3 port 1
+    assign R15_chan_in [3]   = R3_chan_out [1];
+    
+    /*******************
+    *        R8
+    *******************/
+    router_config_t R8_router_config_in;
+    router_top #(
+        .ROUTER_ID(12),
+        .P(5)
+    ) R8 (
+        .clk(R8_clk), 
+        .reset(R8_reset),
+        .router_config_in(R8_router_config_in),
+        .chan_in   (R8_chan_in), 
+        .chan_out  (R8_chan_out),
+        .router_event (R8_router_event)
+    );
+
+        assign R8_clk = clk;
+        assign R8_reset = reset;
+        assign R8_router_config_in.router_addr = 12;
+        assign R8_router_config_in.router_id = 12;
+    //Connect R8 port 0 to  T12 port 0
+    assign R8_chan_in [0]  = T12_chan_in;
+    assign T12_chan_out = R8_chan_out [0];
+    assign T12_router_event = R8_router_event [0];
+    //Connect R8 port 1 to  R11 port 1
+    assign R8_chan_in [1]   = R11_chan_out [1];
+    //Connect R8 port 2 to  R13 port 1
+    assign R8_chan_in [2]   = R13_chan_out [1];
+    //Connect R8 port 3 to  R14 port 1
+    assign R8_chan_in [3]   = R14_chan_out [1];
+    //Connect R8 port 4 to  R12 port 1
+    assign R8_chan_in [4]   = R12_chan_out [1];
+    
+    /*******************
+    *        R9
+    *******************/
+    router_config_t R9_router_config_in;
+    router_top #(
+        .ROUTER_ID(13),
+        .P(5)
+    ) R9 (
+        .clk(R9_clk), 
+        .reset(R9_reset),
+        .router_config_in(R9_router_config_in),
+        .chan_in   (R9_chan_in), 
+        .chan_out  (R9_chan_out),
+        .router_event (R9_router_event)
+    );
+
+        assign R9_clk = clk;
+        assign R9_reset = reset;
+        assign R9_router_config_in.router_addr = 13;
+        assign R9_router_config_in.router_id = 13;
+    //Connect R9 port 0 to  T13 port 0
+    assign R9_chan_in [0]  = T13_chan_in;
+    assign T13_chan_out = R9_chan_out [0];
+    assign T13_router_event = R9_router_event [0];
+    //Connect R9 port 1 to  R11 port 3
+    assign R9_chan_in [1]   = R11_chan_out [3];
+    //Connect R9 port 2 to  R4 port 1
+    assign R9_chan_in [2]   = R4_chan_out [1];
+    //Connect R9 port 3 to  R6 port 1
+    assign R9_chan_in [3]   = R6_chan_out [1];
+    //Connect R9 port 4 to  R10 port 2
+    assign R9_chan_in [4]   = R10_chan_out [2];
+    
+    /*******************
+    *        R10
+    *******************/
+    router_config_t R10_router_config_in;
+    router_top #(
+        .ROUTER_ID(14),
+        .P(5)
+    ) R10 (
+        .clk(R10_clk), 
+        .reset(R10_reset),
+        .router_config_in(R10_router_config_in),
+        .chan_in   (R10_chan_in), 
+        .chan_out  (R10_chan_out),
+        .router_event (R10_router_event)
+    );
+
+        assign R10_clk = clk;
+        assign R10_reset = reset;
+        assign R10_router_config_in.router_addr = 14;
+        assign R10_router_config_in.router_id = 14;
+    //Connect R10 port 0 to  T14 port 0
+    assign R10_chan_in [0]  = T14_chan_in;
+    assign T14_chan_out = R10_chan_out [0];
+    assign T14_router_event = R10_router_event [0];
+    //Connect R10 port 1 to  R11 port 2
+    assign R10_chan_in [1]   = R11_chan_out [2];
+    //Connect R10 port 2 to  R9 port 4
+    assign R10_chan_in [2]   = R9_chan_out [4];
+    //Connect R10 port 3 to  R12 port 2
+    assign R10_chan_in [3]   = R12_chan_out [2];
+    //Connect R10 port 4 to  R15 port 1
+    assign R10_chan_in [4]   = R15_chan_out [1];
+    
+    /*******************
+    *        R11
+    *******************/
+    router_config_t R11_router_config_in;
+    router_top #(
+        .ROUTER_ID(15),
+        .P(5)
+    ) R11 (
+        .clk(R11_clk), 
+        .reset(R11_reset),
+        .router_config_in(R11_router_config_in),
+        .chan_in   (R11_chan_in), 
+        .chan_out  (R11_chan_out),
+        .router_event (R11_router_event)
+    );
+
+        assign R11_clk = clk;
+        assign R11_reset = reset;
+        assign R11_router_config_in.router_addr = 15;
+        assign R11_router_config_in.router_id = 15;
+    //Connect R11 port 0 to  T15 port 0
+    assign R11_chan_in [0]  = T15_chan_in;
+    assign T15_chan_out = R11_chan_out [0];
+    assign T15_router_event = R11_router_event [0];
+    //Connect R11 port 1 to  R8 port 1
+    assign R11_chan_in [1]   = R8_chan_out [1];
+    //Connect R11 port 2 to  R10 port 1
+    assign R11_chan_in [2]   = R10_chan_out [1];
+    //Connect R11 port 3 to  R9 port 1
+    assign R11_chan_in [3]   = R9_chan_out [1];
+    //Connect R11 port 4 to  R5 port 1
+    assign R11_chan_in [4]   = R5_chan_out [1];
 
     
     
-             
+    
 endmodule
diff --git a/mpsoc/rtl/src_topology/custom1/custom1_noc_genvar.sv b/mpsoc/rtl/src_topology/custom1/custom1_noc_genvar.sv
index 2b2a459..cd4eb81 100644
--- a/mpsoc/rtl/src_topology/custom1/custom1_noc_genvar.sv
+++ b/mpsoc/rtl/src_topology/custom1/custom1_noc_genvar.sv
@@ -1,291 +1,258 @@
 
 /**************************************************************************
-**	WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT ARE LIKELY TO BE
-**	OVERWRITTEN AND LOST. Rename this file if you wish to do any modification.
+**    WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT ARE LIKELY TO BE
+**    OVERWRITTEN AND LOST. Rename this file if you wish to do any modification.
 ****************************************************************************/
 
 
 /**********************************************************************
-**	File: /home/alireza/work/git/pronoc/mpsoc/rtl/src_topology/custom1/custom1_noc_genvar.sv
+**    File: /home/alireza/work/git/ProNoC-repos/github-pronoc/mpsoc/rtl/src_topology/custom1/custom1_noc_genvar.sv
 **    
-**	Copyright (C) 2014-2021  Alireza Monemi
+**    Copyright (C) 2014-2022  Alireza Monemi
 **    
-**	This file is part of ProNoC 2.1.0 
+**    This file is part of ProNoC 2.2.0 
 **
-**	ProNoC ( stands for Prototype Network-on-chip)  is free software: 
-**	you can redistribute it and/or modify it under the terms of the GNU
-**	Lesser General Public License as published by the Free Software Foundation,
-**	either version 2 of the License, or (at your option) any later version.
+**    ProNoC ( stands for Prototype Network-on-chip)  is free software: 
+**    you can redistribute it and/or modify it under the terms of the GNU
+**    Lesser General Public License as published by the Free Software Foundation,
+**    either version 2 of the License, or (at your option) any later version.
 **
-** 	ProNoC is distributed in the hope that it will be useful, but WITHOUT
-** 	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
-** 	or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
-** 	Public License for more details.
+**     ProNoC is distributed in the hope that it will be useful, but WITHOUT
+**     ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+**     or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
+**     Public License for more details.
 **
-** 	You should have received a copy of the GNU Lesser General Public
-** 	License along with ProNoC. If not, see <http:**www.gnu.org/licenses/>.
+**     You should have received a copy of the GNU Lesser General Public
+**     License along with ProNoC. If not, see <http:**www.gnu.org/licenses/>.
 ******************************************************************************/ 
 
 `include "pronoc_def.v"
 
-module   custom1_noc_genvar    
-#(
-	parameter NOC_ID=0
-)(
-
+module   custom1_noc_genvar
+(
     reset,
-    clk,    
+    clk,
     chan_in_all,
     chan_out_all,
-    router_event  
+    router_event
 );
+import pronoc_pkg::*;
 
-`NOC_CONF
+    input  reset;
+    input  clk;
+    input  smartflit_chanel_t chan_in_all  [NE-1 : 0];
+    output smartflit_chanel_t chan_out_all [NE-1 : 0];
     
-
-	input  reset;
-	input  clk;
-	input  smartflit_chanel_t chan_in_all  [NE-1 : 0];
-	output smartflit_chanel_t chan_out_all [NE-1 : 0];
-
-//Events
-	output  router_event_t  router_event [NR-1 : 0][MAX_P-1 : 0];
-
-//all routers port 
-	smartflit_chanel_t    router_chan_in   [NR-1 :0][MAX_P-1 : 0];
-	smartflit_chanel_t    router_chan_out  [NR-1 :0][MAX_P-1 : 0];
-
-
-	wire [RAw-1 : 0] current_r_addr [NR-1 : 0];
-
-
-
-
+    //Events
+    output  router_event_t  router_event [NR-1 : 0][MAX_P-1 : 0];
+    //all routers port 
+    smartflit_chanel_t    router_chan_in   [NR-1 :0][MAX_P-1 : 0];
+    smartflit_chanel_t    router_chan_out  [NR-1 :0][MAX_P-1 : 0];
+    router_config_t router_config [NR-1 : 0];
 
 
 
-   
 
-	genvar i;
-	generate	
-	
-	for( i=0; i<4; i=i+1) begin : router_3_port_lp
-	localparam RID = i;
-	assign current_r_addr [RID] = RID[RAw-1: 0]; 
-
-	router_top #(
-		.NOC_ID(NOC_ID),
-		.P(3)
-	)
-	router_3_port
-	(	
-		.clk(clk), 
-		.reset(reset),
-		.current_r_id(RID),
-		.current_r_addr(current_r_addr[RID]),	
-		.chan_in  (router_chan_in [RID] [2 : 0]), 
-		.chan_out (router_chan_out[RID] [2 : 0]),
-		.router_event(router_event[RID] [2 : 0])	
-	);
-    
-    
-    
-	end    
-			
-	for( i=0; i<8; i=i+1) begin : router_4_port_lp
-	localparam RID = i+4;
-	assign current_r_addr [RID] = RID[RAw-1: 0]; 
-
-	router_top #(
-		.NOC_ID(NOC_ID),
-		.P(4)
-	)
-	router_4_port
-	(	
-		.clk(clk), 
-		.reset(reset),
-		.current_r_id(RID),
-		.current_r_addr(current_r_addr[RID]),	
-		.chan_in  (router_chan_in [RID] [3 : 0]), 
-		.chan_out (router_chan_out[RID] [3 : 0]),
-		.router_event(router_event[RID] [3 : 0])	
-	);
+    genvar i;
+    generate   
+    if (TOPOLOGY == "custom1" ) begin  
     
-    
-    
-	end    
-			
-	for( i=0; i<4; i=i+1) begin : router_5_port_lp
-	localparam RID = i+12;
-	assign current_r_addr [RID] = RID[RAw-1: 0]; 
+    for( i=0; i<4; i=i+1) begin : router_3_port_lp
+        localparam RID = i;
+        assign router_config [RID].router_id = RID[RAw-1: 0];
+        assign router_config [RID].router_addr = RID[RAw-1: 0];
+        router_top #(
+            .ROUTER_ID(RID),
+            .P(3)
+        ) router_3_port (
+            .clk(clk), 
+            .reset(reset),
+            .router_config_in(router_config[RID]),
+            .chan_in  (router_chan_in [RID] [2 : 0]),
+            .chan_out (router_chan_out[RID] [2 : 0]),
+            .router_event(router_event[RID] [2 : 0])
+        );
+    end
 
-	router_top #(
-		.NOC_ID(NOC_ID),
-		.P(5)
-	)
-	router_5_port
-	(	
-		.clk(clk), 
-		.reset(reset),
-		.current_r_id(RID),
-		.current_r_addr(current_r_addr[RID]),	
-		.chan_in  (router_chan_in [RID] [4 : 0]), 
-		.chan_out (router_chan_out[RID] [4 : 0]),
-		.router_event(router_event[RID] [4 : 0])	
-	);
-    
-    
-    
-	end    
-			endgenerate
+    for( i=0; i<8; i=i+1) begin : router_4_port_lp
+        localparam RID = i+4;
+        assign router_config [RID].router_id = RID[RAw-1: 0];
+        assign router_config [RID].router_addr = RID[RAw-1: 0];
+        router_top #(
+            .ROUTER_ID(RID),
+            .P(4)
+        ) router_4_port (
+            .clk(clk), 
+            .reset(reset),
+            .router_config_in(router_config[RID]),
+            .chan_in  (router_chan_in [RID] [3 : 0]),
+            .chan_out (router_chan_out[RID] [3 : 0]),
+            .router_event(router_event[RID] [3 : 0])
+        );
+    end
 
+    for( i=0; i<4; i=i+1) begin : router_5_port_lp
+        localparam RID = i+12;
+        assign router_config [RID].router_id = RID[RAw-1: 0];
+        assign router_config [RID].router_addr = RID[RAw-1: 0];
+        router_top #(
+            .ROUTER_ID(RID),
+            .P(5)
+        ) router_5_port (
+            .clk(clk), 
+            .reset(reset),
+            .router_config_in(router_config[RID]),
+            .chan_in  (router_chan_in [RID] [4 : 0]),
+            .chan_out (router_chan_out[RID] [4 : 0]),
+            .router_event(router_event[RID] [4 : 0])
+        );
+    end
 
-//Connect R0 input ports 0 to  T0 output ports 0
-		assign  router_chan_in [0][0] = chan_in_all [0];
-		assign  chan_out_all [0] = router_chan_out [0][0];
-//Connect R0 input ports 1 to  R14 output ports 3
-		assign  router_chan_in [0][1] = router_chan_out [10][3];
-//Connect R0 input ports 2 to  R13 output ports 3
-		assign  router_chan_in [0][2] = router_chan_out [9][3];
-//Connect R1 input ports 0 to  T1 output ports 0
-		assign  router_chan_in [1][0] = chan_in_all [1];
-		assign  chan_out_all [1] = router_chan_out [1][0];
-//Connect R1 input ports 1 to  R7 output ports 3
-		assign  router_chan_in [1][1] = router_chan_out [7][3];
-//Connect R1 input ports 2 to  R2 output ports 2
-		assign  router_chan_in [1][2] = router_chan_out [2][2];
-//Connect R2 input ports 0 to  T2 output ports 0
-		assign  router_chan_in [2][0] = chan_in_all [2];
-		assign  chan_out_all [2] = router_chan_out [2][0];
-//Connect R2 input ports 1 to  R15 output ports 2
-		assign  router_chan_in [2][1] = router_chan_out [11][2];
-//Connect R2 input ports 2 to  R1 output ports 2
-		assign  router_chan_in [2][2] = router_chan_out [1][2];
-//Connect R3 input ports 0 to  T3 output ports 0
-		assign  router_chan_in [3][0] = chan_in_all [3];
-		assign  chan_out_all [3] = router_chan_out [3][0];
-//Connect R3 input ports 1 to  R15 output ports 3
-		assign  router_chan_in [3][1] = router_chan_out [11][3];
-//Connect R3 input ports 2 to  R4 output ports 2
-		assign  router_chan_in [3][2] = router_chan_out [4][2];
-//Connect R4 input ports 0 to  T4 output ports 0
-		assign  router_chan_in [4][0] = chan_in_all [4];
-		assign  chan_out_all [4] = router_chan_out [4][0];
-//Connect R4 input ports 1 to  R9 output ports 2
-		assign  router_chan_in [4][1] = router_chan_out [13][2];
-//Connect R4 input ports 2 to  R3 output ports 2
-		assign  router_chan_in [4][2] = router_chan_out [3][2];
-//Connect R4 input ports 3 to  R6 output ports 3
-		assign  router_chan_in [4][3] = router_chan_out [6][3];
-//Connect R5 input ports 0 to  T5 output ports 0
-		assign  router_chan_in [5][0] = chan_in_all [5];
-		assign  chan_out_all [5] = router_chan_out [5][0];
-//Connect R5 input ports 1 to  R11 output ports 4
-		assign  router_chan_in [5][1] = router_chan_out [15][4];
-//Connect R5 input ports 2 to  R6 output ports 2
-		assign  router_chan_in [5][2] = router_chan_out [6][2];
-//Connect R5 input ports 3 to  R13 output ports 2
-		assign  router_chan_in [5][3] = router_chan_out [9][2];
-//Connect R6 input ports 0 to  T6 output ports 0
-		assign  router_chan_in [6][0] = chan_in_all [6];
-		assign  chan_out_all [6] = router_chan_out [6][0];
-//Connect R6 input ports 1 to  R9 output ports 3
-		assign  router_chan_in [6][1] = router_chan_out [13][3];
-//Connect R6 input ports 2 to  R5 output ports 2
-		assign  router_chan_in [6][2] = router_chan_out [5][2];
-//Connect R6 input ports 3 to  R4 output ports 3
-		assign  router_chan_in [6][3] = router_chan_out [4][3];
-//Connect R7 input ports 0 to  T7 output ports 0
-		assign  router_chan_in [7][0] = chan_in_all [7];
-		assign  chan_out_all [7] = router_chan_out [7][0];
-//Connect R7 input ports 1 to  R12 output ports 3
-		assign  router_chan_in [7][1] = router_chan_out [8][3];
-//Connect R7 input ports 2 to  R14 output ports 2
-		assign  router_chan_in [7][2] = router_chan_out [10][2];
-//Connect R7 input ports 3 to  R1 output ports 1
-		assign  router_chan_in [7][3] = router_chan_out [1][1];
-//Connect R12 input ports 0 to  T8 output ports 0
-		assign  router_chan_in [8][0] = chan_in_all [8];
-		assign  chan_out_all [8] = router_chan_out [8][0];
-//Connect R12 input ports 1 to  R8 output ports 4
-		assign  router_chan_in [8][1] = router_chan_out [12][4];
-//Connect R12 input ports 2 to  R10 output ports 3
-		assign  router_chan_in [8][2] = router_chan_out [14][3];
-//Connect R12 input ports 3 to  R7 output ports 1
-		assign  router_chan_in [8][3] = router_chan_out [7][1];
-//Connect R13 input ports 0 to  T9 output ports 0
-		assign  router_chan_in [9][0] = chan_in_all [9];
-		assign  chan_out_all [9] = router_chan_out [9][0];
-//Connect R13 input ports 1 to  R8 output ports 2
-		assign  router_chan_in [9][1] = router_chan_out [12][2];
-//Connect R13 input ports 2 to  R5 output ports 3
-		assign  router_chan_in [9][2] = router_chan_out [5][3];
-//Connect R13 input ports 3 to  R0 output ports 2
-		assign  router_chan_in [9][3] = router_chan_out [0][2];
-//Connect R14 input ports 0 to  T10 output ports 0
-		assign  router_chan_in [10][0] = chan_in_all [10];
-		assign  chan_out_all [10] = router_chan_out [10][0];
-//Connect R14 input ports 1 to  R8 output ports 3
-		assign  router_chan_in [10][1] = router_chan_out [12][3];
-//Connect R14 input ports 2 to  R7 output ports 2
-		assign  router_chan_in [10][2] = router_chan_out [7][2];
-//Connect R14 input ports 3 to  R0 output ports 1
-		assign  router_chan_in [10][3] = router_chan_out [0][1];
-//Connect R15 input ports 0 to  T11 output ports 0
-		assign  router_chan_in [11][0] = chan_in_all [11];
-		assign  chan_out_all [11] = router_chan_out [11][0];
-//Connect R15 input ports 1 to  R10 output ports 4
-		assign  router_chan_in [11][1] = router_chan_out [14][4];
-//Connect R15 input ports 2 to  R2 output ports 1
-		assign  router_chan_in [11][2] = router_chan_out [2][1];
-//Connect R15 input ports 3 to  R3 output ports 1
-		assign  router_chan_in [11][3] = router_chan_out [3][1];
-//Connect R8 input ports 0 to  T12 output ports 0
-		assign  router_chan_in [12][0] = chan_in_all [12];
-		assign  chan_out_all [12] = router_chan_out [12][0];
-//Connect R8 input ports 1 to  R11 output ports 1
-		assign  router_chan_in [12][1] = router_chan_out [15][1];
-//Connect R8 input ports 2 to  R13 output ports 1
-		assign  router_chan_in [12][2] = router_chan_out [9][1];
-//Connect R8 input ports 3 to  R14 output ports 1
-		assign  router_chan_in [12][3] = router_chan_out [10][1];
-//Connect R8 input ports 4 to  R12 output ports 1
-		assign  router_chan_in [12][4] = router_chan_out [8][1];
-//Connect R9 input ports 0 to  T13 output ports 0
-		assign  router_chan_in [13][0] = chan_in_all [13];
-		assign  chan_out_all [13] = router_chan_out [13][0];
-//Connect R9 input ports 1 to  R11 output ports 3
-		assign  router_chan_in [13][1] = router_chan_out [15][3];
-//Connect R9 input ports 2 to  R4 output ports 1
-		assign  router_chan_in [13][2] = router_chan_out [4][1];
-//Connect R9 input ports 3 to  R6 output ports 1
-		assign  router_chan_in [13][3] = router_chan_out [6][1];
-//Connect R9 input ports 4 to  R10 output ports 2
-		assign  router_chan_in [13][4] = router_chan_out [14][2];
-//Connect R10 input ports 0 to  T14 output ports 0
-		assign  router_chan_in [14][0] = chan_in_all [14];
-		assign  chan_out_all [14] = router_chan_out [14][0];
-//Connect R10 input ports 1 to  R11 output ports 2
-		assign  router_chan_in [14][1] = router_chan_out [15][2];
-//Connect R10 input ports 2 to  R9 output ports 4
-		assign  router_chan_in [14][2] = router_chan_out [13][4];
-//Connect R10 input ports 3 to  R12 output ports 2
-		assign  router_chan_in [14][3] = router_chan_out [8][2];
-//Connect R10 input ports 4 to  R15 output ports 1
-		assign  router_chan_in [14][4] = router_chan_out [11][1];
-//Connect R11 input ports 0 to  T15 output ports 0
-		assign  router_chan_in [15][0] = chan_in_all [15];
-		assign  chan_out_all [15] = router_chan_out [15][0];
-//Connect R11 input ports 1 to  R8 output ports 1
-		assign  router_chan_in [15][1] = router_chan_out [12][1];
-//Connect R11 input ports 2 to  R10 output ports 1
-		assign  router_chan_in [15][2] = router_chan_out [14][1];
-//Connect R11 input ports 3 to  R9 output ports 1
-		assign  router_chan_in [15][3] = router_chan_out [13][1];
-//Connect R11 input ports 4 to  R5 output ports 1
-		assign  router_chan_in [15][4] = router_chan_out [5][1];
-  
+    //Connect R0 input ports 0 to  T0 output ports 0
+    assign  router_chan_in [0][0] = chan_in_all [0];
+    assign  chan_out_all [0] = router_chan_out [0][0];
+    //Connect R0 input ports 1 to  R14 output ports 3
+    assign  router_chan_in [0][1] = router_chan_out [10][3];
+    //Connect R0 input ports 2 to  R13 output ports 3
+    assign  router_chan_in [0][2] = router_chan_out [9][3];
+    //Connect R1 input ports 0 to  T1 output ports 0
+    assign  router_chan_in [1][0] = chan_in_all [1];
+    assign  chan_out_all [1] = router_chan_out [1][0];
+    //Connect R1 input ports 1 to  R7 output ports 3
+    assign  router_chan_in [1][1] = router_chan_out [7][3];
+    //Connect R1 input ports 2 to  R2 output ports 2
+    assign  router_chan_in [1][2] = router_chan_out [2][2];
+    //Connect R2 input ports 0 to  T2 output ports 0
+    assign  router_chan_in [2][0] = chan_in_all [2];
+    assign  chan_out_all [2] = router_chan_out [2][0];
+    //Connect R2 input ports 1 to  R15 output ports 2
+    assign  router_chan_in [2][1] = router_chan_out [11][2];
+    //Connect R2 input ports 2 to  R1 output ports 2
+    assign  router_chan_in [2][2] = router_chan_out [1][2];
+    //Connect R3 input ports 0 to  T3 output ports 0
+    assign  router_chan_in [3][0] = chan_in_all [3];
+    assign  chan_out_all [3] = router_chan_out [3][0];
+    //Connect R3 input ports 1 to  R15 output ports 3
+    assign  router_chan_in [3][1] = router_chan_out [11][3];
+    //Connect R3 input ports 2 to  R4 output ports 2
+    assign  router_chan_in [3][2] = router_chan_out [4][2];
+    //Connect R4 input ports 0 to  T4 output ports 0
+    assign  router_chan_in [4][0] = chan_in_all [4];
+    assign  chan_out_all [4] = router_chan_out [4][0];
+    //Connect R4 input ports 1 to  R9 output ports 2
+    assign  router_chan_in [4][1] = router_chan_out [13][2];
+    //Connect R4 input ports 2 to  R3 output ports 2
+    assign  router_chan_in [4][2] = router_chan_out [3][2];
+    //Connect R4 input ports 3 to  R6 output ports 3
+    assign  router_chan_in [4][3] = router_chan_out [6][3];
+    //Connect R5 input ports 0 to  T5 output ports 0
+    assign  router_chan_in [5][0] = chan_in_all [5];
+    assign  chan_out_all [5] = router_chan_out [5][0];
+    //Connect R5 input ports 1 to  R11 output ports 4
+    assign  router_chan_in [5][1] = router_chan_out [15][4];
+    //Connect R5 input ports 2 to  R6 output ports 2
+    assign  router_chan_in [5][2] = router_chan_out [6][2];
+    //Connect R5 input ports 3 to  R13 output ports 2
+    assign  router_chan_in [5][3] = router_chan_out [9][2];
+    //Connect R6 input ports 0 to  T6 output ports 0
+    assign  router_chan_in [6][0] = chan_in_all [6];
+    assign  chan_out_all [6] = router_chan_out [6][0];
+    //Connect R6 input ports 1 to  R9 output ports 3
+    assign  router_chan_in [6][1] = router_chan_out [13][3];
+    //Connect R6 input ports 2 to  R5 output ports 2
+    assign  router_chan_in [6][2] = router_chan_out [5][2];
+    //Connect R6 input ports 3 to  R4 output ports 3
+    assign  router_chan_in [6][3] = router_chan_out [4][3];
+    //Connect R7 input ports 0 to  T7 output ports 0
+    assign  router_chan_in [7][0] = chan_in_all [7];
+    assign  chan_out_all [7] = router_chan_out [7][0];
+    //Connect R7 input ports 1 to  R12 output ports 3
+    assign  router_chan_in [7][1] = router_chan_out [8][3];
+    //Connect R7 input ports 2 to  R14 output ports 2
+    assign  router_chan_in [7][2] = router_chan_out [10][2];
+    //Connect R7 input ports 3 to  R1 output ports 1
+    assign  router_chan_in [7][3] = router_chan_out [1][1];
+    //Connect R12 input ports 0 to  T8 output ports 0
+    assign  router_chan_in [8][0] = chan_in_all [8];
+    assign  chan_out_all [8] = router_chan_out [8][0];
+    //Connect R12 input ports 1 to  R8 output ports 4
+    assign  router_chan_in [8][1] = router_chan_out [12][4];
+    //Connect R12 input ports 2 to  R10 output ports 3
+    assign  router_chan_in [8][2] = router_chan_out [14][3];
+    //Connect R12 input ports 3 to  R7 output ports 1
+    assign  router_chan_in [8][3] = router_chan_out [7][1];
+    //Connect R13 input ports 0 to  T9 output ports 0
+    assign  router_chan_in [9][0] = chan_in_all [9];
+    assign  chan_out_all [9] = router_chan_out [9][0];
+    //Connect R13 input ports 1 to  R8 output ports 2
+    assign  router_chan_in [9][1] = router_chan_out [12][2];
+    //Connect R13 input ports 2 to  R5 output ports 3
+    assign  router_chan_in [9][2] = router_chan_out [5][3];
+    //Connect R13 input ports 3 to  R0 output ports 2
+    assign  router_chan_in [9][3] = router_chan_out [0][2];
+    //Connect R14 input ports 0 to  T10 output ports 0
+    assign  router_chan_in [10][0] = chan_in_all [10];
+    assign  chan_out_all [10] = router_chan_out [10][0];
+    //Connect R14 input ports 1 to  R8 output ports 3
+    assign  router_chan_in [10][1] = router_chan_out [12][3];
+    //Connect R14 input ports 2 to  R7 output ports 2
+    assign  router_chan_in [10][2] = router_chan_out [7][2];
+    //Connect R14 input ports 3 to  R0 output ports 1
+    assign  router_chan_in [10][3] = router_chan_out [0][1];
+    //Connect R15 input ports 0 to  T11 output ports 0
+    assign  router_chan_in [11][0] = chan_in_all [11];
+    assign  chan_out_all [11] = router_chan_out [11][0];
+    //Connect R15 input ports 1 to  R10 output ports 4
+    assign  router_chan_in [11][1] = router_chan_out [14][4];
+    //Connect R15 input ports 2 to  R2 output ports 1
+    assign  router_chan_in [11][2] = router_chan_out [2][1];
+    //Connect R15 input ports 3 to  R3 output ports 1
+    assign  router_chan_in [11][3] = router_chan_out [3][1];
+    //Connect R8 input ports 0 to  T12 output ports 0
+    assign  router_chan_in [12][0] = chan_in_all [12];
+    assign  chan_out_all [12] = router_chan_out [12][0];
+    //Connect R8 input ports 1 to  R11 output ports 1
+    assign  router_chan_in [12][1] = router_chan_out [15][1];
+    //Connect R8 input ports 2 to  R13 output ports 1
+    assign  router_chan_in [12][2] = router_chan_out [9][1];
+    //Connect R8 input ports 3 to  R14 output ports 1
+    assign  router_chan_in [12][3] = router_chan_out [10][1];
+    //Connect R8 input ports 4 to  R12 output ports 1
+    assign  router_chan_in [12][4] = router_chan_out [8][1];
+    //Connect R9 input ports 0 to  T13 output ports 0
+    assign  router_chan_in [13][0] = chan_in_all [13];
+    assign  chan_out_all [13] = router_chan_out [13][0];
+    //Connect R9 input ports 1 to  R11 output ports 3
+    assign  router_chan_in [13][1] = router_chan_out [15][3];
+    //Connect R9 input ports 2 to  R4 output ports 1
+    assign  router_chan_in [13][2] = router_chan_out [4][1];
+    //Connect R9 input ports 3 to  R6 output ports 1
+    assign  router_chan_in [13][3] = router_chan_out [6][1];
+    //Connect R9 input ports 4 to  R10 output ports 2
+    assign  router_chan_in [13][4] = router_chan_out [14][2];
+    //Connect R10 input ports 0 to  T14 output ports 0
+    assign  router_chan_in [14][0] = chan_in_all [14];
+    assign  chan_out_all [14] = router_chan_out [14][0];
+    //Connect R10 input ports 1 to  R11 output ports 2
+    assign  router_chan_in [14][1] = router_chan_out [15][2];
+    //Connect R10 input ports 2 to  R9 output ports 4
+    assign  router_chan_in [14][2] = router_chan_out [13][4];
+    //Connect R10 input ports 3 to  R12 output ports 2
+    assign  router_chan_in [14][3] = router_chan_out [8][2];
+    //Connect R10 input ports 4 to  R15 output ports 1
+    assign  router_chan_in [14][4] = router_chan_out [11][1];
+    //Connect R11 input ports 0 to  T15 output ports 0
+    assign  router_chan_in [15][0] = chan_in_all [15];
+    assign  chan_out_all [15] = router_chan_out [15][0];
+    //Connect R11 input ports 1 to  R8 output ports 1
+    assign  router_chan_in [15][1] = router_chan_out [12][1];
+    //Connect R11 input ports 2 to  R10 output ports 1
+    assign  router_chan_in [15][2] = router_chan_out [14][1];
+    //Connect R11 input ports 3 to  R9 output ports 1
+    assign  router_chan_in [15][3] = router_chan_out [13][1];
+    //Connect R11 input ports 4 to  R5 output ports 1
+    assign  router_chan_in [15][4] = router_chan_out [5][1];
 
-  
-             
+end // topology
+endgenerate
 endmodule
diff --git a/mpsoc/rtl/src_topology/custom_flist.f b/mpsoc/rtl/src_topology/custom_flist.f
index 84acb86..d5173d1 100644
--- a/mpsoc/rtl/src_topology/custom_flist.f
+++ b/mpsoc/rtl/src_topology/custom_flist.f
@@ -1,10 +1,12 @@
 +incdir+./
-./custom1/Tcustom1Rcustom_look_ahead_routing_genvar.v
-./custom1/custom1_noc_genvar.sv
-./custom1/Tcustom1Rcustom_conventional_routing_genvar.v
-./custom1/custom1_noc.sv
-./custom1/Tcustom1Rcustom_conventional_routing.v
-./custom1/Tcustom1Rcustom_look_ahead_routing.v
+./common/custom_lkh_routing.v
 ./common/custom_ni_routing.v
+./common/custom_conv_routing.v
 ./common/custom_noc_top.sv
-./common/custom_lkh_routing.v
+./custom1/Tcustom1Rcustom_conv_routing.v
+./custom1/Tcustom1Rcustom_ni_routing_genvar.v
+./custom1/Tcustom1Rcustom_ni_routing.v
+./custom1/custom1_noc.sv
+./custom1/Tcustom1Rcustom_look_ahead_routing.v
+./custom1/Tcustom1Rcustom_look_ahead_routing_genvar.v
+./custom1/custom1_noc_genvar.sv
diff --git a/mpsoc/rtl/src_topology/param.obj b/mpsoc/rtl/src_topology/param.obj
index 0d11666..fdf2aff 100644
--- a/mpsoc/rtl/src_topology/param.obj
+++ b/mpsoc/rtl/src_topology/param.obj
@@ -1,16 +1,22 @@
 #######################################################################
-##	File: /home/alireza/work/git/pronoc/mpsoc/rtl/src_topology/param.obj
+##    File: /home/alireza/work/git/hca_git/git-hub/ProNoC/mpsoc/rtl/src_topology/param.obj
 ##    
-##	Copyright (C) 2014-2021  Alireza Monemi
+##    Copyright (C) 2014-2022  Alireza Monemi
 ##    
-##	This file is part of ProNoC 2.1.0 
+##    This file is part of ProNoC 2.2.0 
 ##
-## 	WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT 
-##	MAY CAUSE UNEXPECTED BEHAVIOR.
+##     WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT 
+##    MAY CAUSE UNEXPECTED BEHAVIOR.
 ################################################################################
-
 $Topology = {
               '"mesh4x4"' => {
+                               'T1' => 16,
+                               'ROUTE_NAME' => '"custom","m4"',
+                               'ROUTER_Ps' => {
+                                                '5' => 16
+                                              },
+                               'T2' => 16,
+                               'T3' => 5,
                                'er_addr' => [
                                               4,
                                               5,
@@ -28,16 +34,17 @@ $Topology = {
                                               13,
                                               14,
                                               15
-                                            ],
-                               'T3' => 5,
-                               'T1' => 16,
-                               'ROUTE_NAME' => '"custom","m4"',
-                               'T2' => 16,
-                               'ROUTER_Ps' => {
-                                                '5' => 16
-                                              }
+                                            ]
                              },
               '"custom1"' => {
+                               'ROUTE_NAME' => '"custom"',
+                               'T1' => 16,
+                               'T3' => 5,
+                               'ROUTER_Ps' => {
+                                                '3' => 4,
+                                                '4' => 8,
+                                                '5' => 4
+                                              },
                                'T2' => 16,
                                'er_addr' => [
                                               0,
@@ -56,14 +63,6 @@ $Topology = {
                                               13,
                                               14,
                                               15
-                                            ],
-                               'ROUTER_Ps' => {
-                                                '3' => 4,
-                                                '5' => 4,
-                                                '4' => 8
-                                              },
-                               'T1' => 16,
-                               'ROUTE_NAME' => '"custom"',
-                               'T3' => 5
+                                            ]
                              }
             };
diff --git a/mpsoc/script/multimesh/deprecated/Readme b/mpsoc/script/multimesh/deprecated/Readme
new file mode 100644
index 0000000..804a9ec
--- /dev/null
+++ b/mpsoc/script/multimesh/deprecated/Readme
@@ -0,0 +1,18 @@
+### **Generating Multi-Mesh Configuration**
+
+To generate a multi-mesh configuration, follow these steps:
+
+1. **Open a terminal.**
+2. **Run the following command:**
+
+   ```bash
+   bash [ProNoC_dir]/mpsoc/script/yaml_noc_gen/yaml_noc_gen.pl [ProNoC_dir]/mpsoc/noc_configs/[config_file_name].yml
+   ```
+
+   - Replace **`[ProNoC_dir]`** with the path to your **ProNoC** installation directory.
+   - Replace **`[config_file_name]`** with the **YAML configuration file** that defines your multi-mesh network settings.
+
+
+This script will generate the required multi-mesh NoC configuration based on the settings defined in the YAML file.
+
+
diff --git a/mpsoc/script/multimesh/deprecated/channel_size_extractor.py b/mpsoc/script/multimesh/deprecated/channel_size_extractor.py
new file mode 100755
index 0000000..ee5650b
--- /dev/null
+++ b/mpsoc/script/multimesh/deprecated/channel_size_extractor.py
@@ -0,0 +1,41 @@
+import argparse
+import subprocess
+import os
+
+from pyslang import ScriptSession
+
+
+PRONOC_CHANNEL_WIDTH_NAME = "SMARTFLIT_CHANEL_w"
+
+def preprocess_pronoc_pkg(pyslang_opts):
+    result = subprocess.run(['python', os.path.join(os.environ["DV_ROOT"],
+                                                    "tools/bin/",
+                                                    'pyslang_preprocess.py')] \
+                             + pyslang_opts, capture_output=True, text=True)
+    return result.stdout
+
+def evaluate_pronoc_channel_size(noc_pkg, noc_id):
+    session = ScriptSession()
+    # Seg-fault turnaround: add a final ";" right after package definition
+    session.eval(noc_pkg + ";")
+    look_for = f"pronoc_pkg_N{noc_id}::{PRONOC_CHANNEL_WIDTH_NAME}_N{noc_id}"
+    result = session.eval(f"{look_for}")
+    if str(result) == "<unset>":
+        raise Exception(f"Error: cannot retrieve {look_for}")
+    print(result, end='')
+
+if __name__ == "__main__":
+    parser = argparse.ArgumentParser(description=f"Retrieve the channel" + \
+                                     f" size ({PRONOC_CHANNEL_WIDTH_NAME})"+ \
+                                     " of a ProNoC SystemVerilog Package")
+    parser.add_argument('noc_id', type=int, help='Network-on-Chip ID')
+    parser.add_argument('pyslang_params', nargs=argparse.REMAINDER,
+                        help='A series of parameters passed to pyslang for' + \
+                             ' pre-processing')
+    args = parser.parse_args()
+
+    # Call Pyslang pre-processor on ProNoC NoC PKG
+    preprocessed_src = preprocess_pronoc_pkg(args.pyslang_params)
+    # Evaluate the ProNoC channel size of the PKG
+    evaluate_pronoc_channel_size(preprocessed_src, args.noc_id)
+
diff --git a/mpsoc/script/multimesh/deprecated/multi_mesh.pl b/mpsoc/script/multimesh/deprecated/multi_mesh.pl
new file mode 100644
index 0000000..fba1424
--- /dev/null
+++ b/mpsoc/script/multimesh/deprecated/multi_mesh.pl
@@ -0,0 +1,101 @@
+#add home dir in perl 5.6
+use FindBin;
+use lib $FindBin::Bin;
+use constant::boolean;
+
+use strict;
+use warnings;
+
+# Function to add an edge with separate parent and child nodes
+sub add_edge_old {
+    my ($graph,$parent_cluster, $parent_node, $child_cluster, $child_node, $dir) = @_;
+    # Initialize clusters if not present
+    $graph->{$parent_cluster} //= { parents => [], children => [] };
+    $graph->{$child_cluster}   //= { parents => [], children => [] };
+    # Add child connection to parent
+    push @{$graph->{$parent_cluster}{children}}, { cluster => $child_cluster, parent_node => $parent_node, child_node => $child_node, dir=>$dir};
+    # Add parent connection to child
+    push @{$graph->{$child_cluster}{parents}}, { cluster => $parent_cluster, parent_node => $parent_node, child_node => $child_node, dir=>$dir};
+}
+
+# Function to add an edge with separate parent and child nodes
+sub add_edge {
+    my ($graph,$src_cluster, $src_node, $dest_cluster, $dest_node, $dir) = @_;
+    # Initialize clusters if not present
+    $graph->{$src_cluster} //= { $dir => [] };
+    # Add child connection to parent
+    push @{$graph->{$src_cluster}{$dir}}, { cluster => $dest_cluster, src_node => $src_node, dest_node => $dest_node};
+}
+
+sub get_clusters_in_dir {
+    my ($graph, $cluster,$dir) = @_;
+    my @childs = exists $graph->{$cluster} ? map { $_->{cluster} } @{$graph->{$cluster}{$dir}} : ();
+    return unify (@childs);
+}
+
+sub dfs_assign_ids {
+    my ($graph, $global_id, $cluster, $visited, $current_id) = @_;
+    return $current_id if exists $visited->{$cluster};  # Skip if already visited
+    $visited->{$cluster} = 1;
+    $global_id->{$cluster} = $current_id++;  # Assign and increment ID
+    foreach my $child (get_clusters_in_dir($graph, $cluster, 'up')) {
+        $current_id = dfs_assign_ids($graph, $global_id, $child, $visited, $current_id);
+    }
+    return $current_id;
+}
+
+sub find_interpose{
+    my $config = shift;
+    my @f= keys %{$config->{multi_mesh}};
+    return $f[0];
+}
+
+# Function to start DFS traversal from a root cluster
+sub assign_global_ids {
+    my ($graph, $global_id, $root_cluster) = @_;
+    my %visited;
+    dfs_assign_ids($graph, $global_id, $root_cluster, \%visited, 0);  # Start ID from 0
+}
+
+# Function to get cluster IDs with DFS ordering
+sub get_cluster_ids {
+    my ($config,$graph) = @_;
+    my %global_id;  # Stores assigned IDs
+    my $I = find_interpose($config);  # Find the root cluster
+    assign_global_ids($graph, \%global_id, $I);  # Start DFS from root
+    return %global_id;
+}
+
+sub unify {
+    my %seen;
+    return grep { !$seen{$_}++ } @_;
+}
+
+sub get_all_connection_nodes_to_a_cluster {
+    my ($graph, $cluster_key, $direction, $target_cluster) = @_;
+    return unless exists $graph->{$cluster_key}{$direction};  # Ensure the path exists
+    my @src_nodes = map { $_->{src_node} }
+                    grep { $_->{cluster} eq $target_cluster }
+                    @{ $graph->{$cluster_key}{$direction} };
+    return @src_nodes;  # Return as an array
+}
+
+sub get_clusters_up_to_leaf {
+    my ($tree, $cluster)=@_;
+    my %visited;
+    return get_clusters_up_to_leaf_unique($tree, $cluster, \%visited);
+}
+
+sub get_clusters_up_to_leaf_unique {
+    my ($tree, $cluster, $visited) = @_;
+    return if exists $visited->{$cluster};  # Avoid duplicates
+    $visited->{$cluster} = 1;
+    return ($cluster) unless exists $tree->{$cluster}{'up'};
+    my @leaves = ($cluster);
+    foreach my $child (@{$tree->{$cluster}{'up'}}) {
+        push @leaves, get_clusters_up_to_leaf_unique($tree, $child->{cluster}, $visited);
+    }
+    return @leaves;
+}
+
+return 1;
diff --git a/mpsoc/script/multimesh/deprecated/yaml_noc_gen.pl b/mpsoc/script/multimesh/deprecated/yaml_noc_gen.pl
new file mode 100644
index 0000000..e3cb196
--- /dev/null
+++ b/mpsoc/script/multimesh/deprecated/yaml_noc_gen.pl
@@ -0,0 +1,1141 @@
+#add home dir in perl 5.6
+use FindBin;
+use lib $FindBin::Bin;
+use constant::boolean;
+
+use strict;
+use warnings;
+#use YAML::XS qw(LoadFile);
+use Data::Dumper;
+use List::MoreUtils qw(uniq);
+use File::Basename;
+use File::Copy;
+use File::Path qw(make_path);
+use List::Util qw(min max);
+use YAML::PP;
+use YAML::PP::Common;
+my $yp = YAML::PP->new( preserve => YAML::PP::Common->PRESERVE_ORDER );
+
+require "src/multi_mesh.pl";
+
+
+my $dirname = dirname(__FILE__);
+my $noc_dir = "$dirname/../../rtl/src_noc";
+my $noc_param_object_file="$dirname/../../Integration_test/synthetic_sim/src/deafult_noc_param";
+
+my $yaml_file = $ARGV[0];
+my $out_dir= "$dirname/../../rtl/src_multi_mesh/build";
+
+if (!defined $yaml_file)  {
+    print "Error:
+    usage: perl yaml_noc_gen.pl yamal_file  target_dir\n";
+    exit 1;
+}
+
+my $config = $yp->load_file( $yaml_file );
+my %cluster_tree; # a Tree struct saving cluster connections in parent child format
+my %cluster_ids; #keep cluster ids based on dfs
+
+#my $config = LoadFile($yaml_file);
+my $topology = $config->{'topology'};
+my $buffer_depth=$config->{'buffer_depth'};
+my $flit_size=$config->{'flit_size'};
+
+
+# Create directory with -p equivalent
+make_path($out_dir) or die "Failed to create directory '$out_dir': $!" unless(-d $out_dir);
+
+generate_pronoc_multimesh() if(exists $config->{'multi_mesh'});
+
+
+sub connect_nodes{
+    my ($self,$node1,$port1,$node2,$port2)=@_;
+    $self->{'PCONNECT'}{$node1}{"Port[$port1]"}="$node2,$port2";
+    # $self->{$node2}{'PCONNECT'}{$port2}="$node1,$port1";
+}
+
+
+sub connect_nodes_local{
+    my ($self,$mesh1,$x1,$y1,$z1,$port1,$mesh2,$x2,$y2,$z2,$port2,$dim_x,$dim_y,$dim_z)=@_;
+    my $id1=$x1 + $y1*$dim_x+ $z1*$dim_x*$dim_y;
+    my $node1=$mesh1."_".$id1;
+    my $id2=$x2+ $y2*$dim_x+ $z2*$dim_x*$dim_y;
+    my $node2=$mesh2."_".$id2;
+    connect_nodes($self,$node1,$port1,$node2,$port2);
+}
+
+sub update_multimesh_config {
+    my ($mesh,$config,$vcs)=@_;
+    my $dim_x = $config->{'multi_mesh'}{$mesh}{'dim_x'};
+    my $dim_y = $config->{'multi_mesh'}{$mesh}{'dim_y'};
+    my $dim_z = $config->{'multi_mesh'}{$mesh}{'dim_z'};
+    my $vc    = $config->{'multi_mesh'}{$mesh}{'n_virtual_channels'};
+    my $first_router_id = $config->{'router_counter'}//0;
+    my $cluster_counter = $config->{'cluster_counter'}//0;
+    $config->{'max_x'} = max($config->{'max_x'} // 0, $dim_x);
+    $config->{'max_y'} = max($config->{'max_y'} // 0, $dim_y);
+    $config->{'max_z'} = max($config->{'max_z'} // 0, $dim_z);
+    $config->{'cluster_counter'} = $cluster_counter+1;
+    $vcs->{$mesh}=$vc;
+    my $nodes_num = $dim_x * $dim_y * $dim_z;
+    my $max_port=7;
+    $config->{'multi_mesh'}{$mesh}{'MAX_P'}=$max_port;
+    $config->{'multi_mesh'}{$mesh}{'RID_INT'}=$first_router_id;
+    $config->{'multi_mesh'}{$mesh}{'NR'}=$nodes_num;
+    $first_router_id+=$nodes_num;
+    $config->{'router_counter'}=$first_router_id;
+    $config->{'endp_counter'}=$first_router_id;
+    my ($LOCAL, $EAST, $NORTH, $WEST, $SOUTH, $UP, $DOWN) = (0..6);
+    my  $CLUSTER = ($dim_z==1)? 5 : 7;
+ #   for my $x (0..$dim_x-1) {
+ #       for my $y (0..$dim_y-1) {
+ #           for my $z (0..$dim_z-1) {
+ #               connect_nodes_local($config,$mesh,$x,$y,$z,$EAST,$mesh,($x+1),$y,$z,$WEST,$dim_x,$dim_y,$dim_z) if ($x < $dim_x-1);
+ #               connect_nodes_local($config,$mesh,$x,$y,$z,$NORTH,$mesh,$x,$y-1,$z,$SOUTH,$dim_x,$dim_y,$dim_z) if ($y > 0  );
+ #               connect_nodes_local($config,$mesh,$x,$y,$z,$WEST,$mesh,$x-1,$y,$z,$EAST,$dim_x,$dim_y,$dim_z)  if ($x > 0);
+ #               connect_nodes_local($config,$mesh,$x,$y,$z,$SOUTH,$mesh,$x,$y+1,$z,$NORTH,$dim_x,$dim_y,$dim_z) if ($y<$dim_y-1);
+ #               if($dim_z>1){
+ #                   connect_nodes_local($config,$mesh,$x,$y,$z,$UP,$mesh,$x,$y,$z+1,$DOWN,$dim_x,$dim_y,$dim_z) if($z<$dim_z-1);
+ #                   connect_nodes_local($config,$mesh,$x,$y,$z,$DOWN,$mesh,$x,$y,$z-1,$UP,$dim_x,$dim_y,$dim_z) if($z>0 );
+ #               }
+ #           }
+ #       }
+ #   }
+}
+
+#sub get_all_minimal_paths_between_two_endps{
+#    my ($self,$src, $dst)=@_;
+#    my @proceed_nodes;
+#    my @head_nodes;
+#    my $offset = 1; # this make sure a minimal path selection.
+#    my $max_len = 1000;
+#    push (@head_nodes,$src);
+#    push (@proceed_nodes,$src);
+#    my @paths;
+#    my @ports;
+#    my @paths_to_dst;
+#    my @ports_to_dst;
+#    my @first_path=($src);
+#    my @first_port=(0);
+#    $paths[0]=\@first_path;
+#    $ports[0]=\@first_port;
+#    # select one path
+#    my $n=0;
+#    my $min_dist=1000000;
+#    do{
+#        my @current_path= @{$paths[$n]};
+#        my @current_port= @{$ports[$n]};
+#        # get head node
+#        my $head_node =     $current_path[-1];
+#        if(defined $head_node){
+#            # get connected nodes for all ports
+#            #print "hn=$head_node\n";
+#            my $pnum =  7;
+#            for (my $i=0;$i<$pnum; $i++){
+#                my @new_path=@current_path;
+#                my @new_ports=@current_port;
+#                my $src_port = "Port[${i}]";
+#                my $connect = $self->{'PCONNECT'}{$head_node}{$src_port};
+#                if(defined $connect){
+#                    my ($node,$pnode)=split(/\s*,\s*/,$connect);
+#                    #add connected nodes to head_nodes if they are not in path before
+#                    if(!defined get_scolar_pos($node,@new_path)){
+#                        my $size=scalar @new_path;
+#                        #if ($min_dist > $size){
+#                        if( ($min_dist+$offset) > $size &&   $max_len>=$size){
+#                            push (@new_path,$node);
+#                            push (@new_ports,$pnode);
+#                            push (@paths,\@new_path);
+#                            push (@ports,\@new_ports);
+#                            if($node eq $dst){
+#                                push(@paths_to_dst,\@new_path);
+#                                push(@ports_to_dst,\@new_ports);
+#                                $min_dist=$size+1 if ($min_dist > $size);
+#                            }
+#                        }
+#                    } #if
+#                }
+#            }#for
+#        }
+#        $n++;
+#    # print "******$n,    @{$paths[$n]}\n" if defined $paths[$n];
+#    }while( defined $paths[$n]);
+#    #print "\@paths_to_dst". Dumper(@paths_to_dst). "\n \@ports_to_dst". Dumper(@ports_to_dst) . "\n" ;
+#    return (\@paths_to_dst,\@ports_to_dst);
+#}
+
+
+sub gen_multi_mesh_io_assign {
+    my $mesh=shift;
+    return
+    "
+    for(int i=0;i<CLUSTER_${mesh}_NE;i++) begin
+        CLUSTER_${mesh}_endpoint_chan_in[i] = chan_in_all[CLUSTER_${mesh}_EID_INIT+i];
+        chan_out_all[CLUSTER_${mesh}_EID_INIT+i]= CLUSTER_${mesh}_endpoint_chan_out[i];
+    end
+    ";
+}
+
+sub gen_io_name_per_cluster {
+    my $mesh=shift;
+    return
+    "    CLUSTER_${mesh}_endpoint_chan_in,
+    CLUSTER_${mesh}_endpoint_chan_out,\n";
+}
+
+sub gen_multi_mesh_cluster_localparam {
+    my ($mesh,$config) =@_;
+
+    $config->{'multi_mesh'}{$mesh}{'EID_INT'} = $config->{'multi_mesh'}{$mesh}{'RID_INT'};
+    my $opt_nr = "-1";
+    my $opt_ne = "+1";
+    # Not interposer case
+    if ($config->{'multi_mesh'}{$mesh}{'RID_INT'}) {
+        $opt_ne = "";
+        $opt_nr = "";
+        $config->{'multi_mesh'}{$mesh}{'EID_INT'} = $config->{'multi_mesh'}{$mesh}{'RID_INT'}+1;
+    }
+
+    return"
+    /****************
+    * CLUSTER_${mesh} localparams
+    ****************/
+    localparam
+        CLUSTER_${mesh}_NX = $config->{'multi_mesh'}{$mesh}{'dim_x'},
+        CLUSTER_${mesh}_NY = $config->{'multi_mesh'}{$mesh}{'dim_y'},
+        CLUSTER_${mesh}_NZ = $config->{'multi_mesh'}{$mesh}{'dim_z'},
+        CLUSTER_${mesh}_MAX_P = $config->{'multi_mesh'}{$mesh}{'MAX_P'},
+        CLUSTER_${mesh}_RID_INIT = $config->{'multi_mesh'}{$mesh}{'RID_INT'},
+        CLUSTER_${mesh}_EID_INIT = $config->{'multi_mesh'}{$mesh}{'EID_INT'},
+        CLUSTER_${mesh}_NE = CLUSTER_${mesh}_NX * CLUSTER_${mesh}_NY * CLUSTER_${mesh}_NZ${opt_ne},
+        CLUSTER_${mesh}_NR = CLUSTER_${mesh}_NE${opt_nr},
+        CLUSTER_${mesh}_NVP = 2 * (CLUSTER_${mesh}_NX * CLUSTER_${mesh}_NY);
+";
+}
+
+
+sub gen_multi_mesh_cluster_instant {
+    my $mesh=shift;
+    return "
+    `ifdef IO_PER_CLUSTER
+    input smartflit_chanel_t CLUSTER_${mesh}_endpoint_chan_in [CLUSTER_${mesh}_NE-1:0];
+    output smartflit_chanel_t CLUSTER_${mesh}_endpoint_chan_out[CLUSTER_${mesh}_NE-1:0];
+    `else
+    smartflit_chanel_t CLUSTER_${mesh}_endpoint_chan_in [CLUSTER_${mesh}_NE-1:0];
+    smartflit_chanel_t CLUSTER_${mesh}_endpoint_chan_out[CLUSTER_${mesh}_NE-1:0];
+    `endif
+    smartflit_chanel_t CLUSTER_${mesh}_inter_cluster_chan_in[CLUSTER_${mesh}_NVP-1:0];
+    smartflit_chanel_t CLUSTER_${mesh}_inter_cluster_chan_out[CLUSTER_${mesh}_NVP-1:0];
+    router_event_t CLUSTER_${mesh}_router_event [CLUSTER_${mesh}_NR-1:0][CLUSTER_${mesh}_MAX_P-1:0];
+
+    mesh_cluster #(
+        .NOC_ID(NOC_ID),
+        .CLUSTER_ID(${mesh}_ID),
+        .RID_INIT(CLUSTER_${mesh}_RID_INIT),
+        .CLUSTER_NX(CLUSTER_${mesh}_NX),
+        .CLUSTER_NY(CLUSTER_${mesh}_NY),
+        .CLUSTER_NZ(CLUSTER_${mesh}_NZ),
+        .CLUSTER_NE(CLUSTER_${mesh}_NE)
+    )the_${mesh}(
+        .reset(reset),
+        .clk(clk),
+        .cluster_id(${mesh}_ID),
+        .endpoint_chan_in(CLUSTER_${mesh}_endpoint_chan_in),
+        .endpoint_chan_out(CLUSTER_${mesh}_endpoint_chan_out),
+        .inter_cluster_chan_in(CLUSTER_${mesh}_inter_cluster_chan_in),
+        .inter_cluster_chan_out(CLUSTER_${mesh}_inter_cluster_chan_out),
+        .router_event(CLUSTER_${mesh}_router_event)
+    );\n    ";
+}
+
+sub get_xyz {
+    my ($config, $mesh, $id) = @_;
+    my $dim_x = $config->{'multi_mesh'}{$mesh}{'dim_x'};
+    my $dim_y = $config->{'multi_mesh'}{$mesh}{'dim_y'};
+    my $dim_z = $config->{'multi_mesh'}{$mesh}{'dim_z'};
+    my $z = int($id / ($dim_x * $dim_y));  # Compute Z index
+    my $l = $id % ($dim_x * $dim_y);       # Remaining index in the XY plane
+    my $x = $l % $dim_x;                   # Compute X index
+    my $y = int($l / $dim_x);              # Compute Y index
+    return ($x, $y, $z);
+}
+
+sub process_vertival_link_placement{
+    my ($ref,$src,$dst,$dir,$verticals)=@_;
+    my @links=@{$ref};
+    foreach my $link (@links){
+        my ($src_endp,$dst_endp)=@$link;
+        #print "$dir link : $src $src_endp $dst $dst_endp \n";
+        $verticals->{$dir}=()if (! exists $verticals->{$dir});
+        push @{$verticals->{$dir}}, "$src:$src_endp:$dst:$dst_endp";
+        my $node1=$src."_".$src_endp;
+        my $node2=$dst."_".$dst_endp;
+        my $port1 = 7;
+        my $port2 = 7;
+        connect_nodes($config,$node1,$port1,$node2,$port2);
+        add_edge(\%cluster_tree,$src,$src_endp,$dst,$dst_endp,$dir);
+    }
+}
+
+sub vertical_links_placement{
+    my ($mesh,$config,$vref,$I)=@_;
+    foreach my $direction (keys %{ $config->{'multi_mesh'}{$mesh}{'vertical_links_placement'} }) {
+        my $ref1=$config->{'multi_mesh'}{$mesh}{'vertical_links_placement'}{$direction};
+        if (ref($ref1) eq 'HASH'){
+            foreach my $dst_mesh (sort keys %{$ref1}){
+                process_vertival_link_placement(@{$ref1}{$dst_mesh},$mesh,$dst_mesh,$direction,$vref);
+            }
+        }else{
+            process_vertival_link_placement($ref1,$mesh,$I,$direction,$vref);
+        }
+    }
+}
+
+sub process_vertival_link_selection{
+    my ($ref,$src,$dst,$dir,$verticals)=@_;
+    my @links=@{$ref};
+    foreach my $link (@links){
+        my ($src_endp,$dst_endp)=@$link;
+        #print "$dir link : $src $src_endp $dst $dst_endp \n";
+        $verticals->{$dir}{$src}{$dst}{$src_endp}=$dst_endp;
+    }
+}
+sub vertical_links_selection{
+    my ($mesh,$config,$vref,$I)=@_;
+    foreach my $direction (keys %{ $config->{'multi_mesh'}{$mesh}{'vertical_links_selection'} }) {
+        my $ref1=$config->{'multi_mesh'}{$mesh}{'vertical_links_selection'}{$direction};
+        if (ref($ref1) eq 'HASH'){
+            foreach my $dst_mesh (sort keys %{$ref1}){
+                process_vertival_link_selection(@{$ref1}{$dst_mesh},$mesh,$dst_mesh,$direction,$vref);
+            }
+        }else{
+            process_vertival_link_selection($ref1,$mesh,$I,$direction,$vref);
+        }
+    }
+}
+
+sub get_vp_id{
+    my ($config,$mesh, $node,$dir)=@_;
+    my ($x, $y, $z) = get_xyz($config, $mesh, $node);
+    my $dimx = $config->{'multi_mesh'}{$mesh}{'dim_x'};
+    my $dimy = $config->{'multi_mesh'}{$mesh}{'dim_y'};
+    my $dimz = $config->{'multi_mesh'}{$mesh}{'dim_z'};
+    # Ensure inter-cluster connections are only at the first (0) or last ($dimz-1) position in the Z dimension
+    if ($z != 0 && $z != $dimz - 1) {
+        die "Error: Inter-cluster connection at Z=$z is invalid. It must be at either the first (0) or last ($dimz-1) position in the Z dimension.";
+    }
+    # If the router is at the first Z-dimension layer (Z=0) and not the only layer,
+    # it must only have a 'down' connection.
+    if ($z == 0 && $dimz > 1 && $dir ne 'down') {
+        die "Error: Routers at the first Z layer (Z=0) can only have a 'down' connection.";
+    }
+    # If the router is at the last Z-dimension layer (Z=$dimz-1) and not the only layer,
+    # it must only have an 'up' connection.
+    if ($z == $dimz - 1 && $dimz > 1 && $dir ne 'up') {
+        die "Error: Routers at the last Z layer (Z=$dimz-1) can only have an 'up' connection.";
+    }
+    my $vp= ($dir eq 'down')? ($y * $dimx) + $x : ($dimx * $dimy) + ($y * $dimx) + $x;
+    return $vp;
+}
+
+sub gen_multi_mesh_vertical_link_assign{
+    my ($vref,$is_connected,$connections_hash)=@_;
+    my %verticals=%{$vref};
+    my $links_assign="";
+    my $unconnected_err="";
+    foreach my $dir  (sort keys %verticals){
+        #get number of up/down links
+        my @connections = @{$verticals{$dir}};
+        my $link_num=scalar @connections;
+        my $DIR = uc $dir;
+        #$rtl_cluster_instant.="    localparam ${DIR}_LINK_NUM=$link_num;\n";
+        $links_assign.="        //cluster_to_cluster $dir connections\n";
+        foreach my $c (@connections){
+            my ($src,$src_endp,$dst,$dst_endp) = split ":", $c;
+            #print "($src:$src_endp:$dst:$dst_endp)\n";
+            my $src_dir=$dir;
+            my $src_vp = get_vp_id($config,$src,$src_endp,$src_dir);
+            my $dst_dir= ($src_dir eq 'up')? 'down' : 'up';
+            my $dst_vp = get_vp_id($config,$dst,$dst_endp,$dst_dir);
+            $links_assign.="        CLUSTER_${dst}_inter_cluster_chan_in[$dst_vp] = CLUSTER_${src}_inter_cluster_chan_out[$src_vp]; // ${src}[$src_endp] dir $src_dir to ${dst}[$dst_endp] dir $dst_dir\n";
+            $is_connected->{'IN'}{$dst}{$dst_vp}=1;
+            $is_connected->{'OUT'}{$src}{$src_vp}=1;
+            # Store the connection in a hash
+            $connections_hash->{"$src,$src_vp"}{"$dst,$dst_vp"} = 1;
+        }
+    }#$direction
+    $links_assign.="        //Unconnected cluster connections are grounded\n";
+    my %connected = %{$is_connected->{'IN'}};
+    foreach my $m (sort keys %connected){
+        foreach my $p (sort { $a <=> $b } keys %{$connected{$m}}){
+            if ($connected{$m}{$p}==0){
+                $links_assign.="        CLUSTER_${m}_inter_cluster_chan_in[$p] = is_grounded;\n";
+            }
+        }
+    }
+    %connected = %{$is_connected->{'OUT'}};
+    foreach my $m (sort keys %connected){
+        foreach my $p (sort { $a <=> $b } keys %{$connected{$m}}){
+            if ($connected{$m}{$p}==0){
+                $unconnected_err.="        if( CLUSTER_${m}_inter_cluster_chan_out[$p].flit_chanel.flit_wr) begin `ERROR_UNCNT(\"${m}\",$p) end\n";
+            }
+        }
+    }
+    return ($links_assign,$unconnected_err);
+}
+
+sub gen_multimesh_unidir_vlinks{
+    my ($vref,$connections_hash)=@_;
+    my %verticals=%{$vref};
+    my $uni_dir="";
+    foreach my $dir  (sort keys %verticals){
+        my @connections = @{$verticals{$dir}};
+        foreach my $c (@connections) {
+            my ($src, $src_endp, $dst, $dst_endp) = split ":", $c;
+            my $src_dir=$dir;
+            my $src_vp = get_vp_id($config,$src,$src_endp,$src_dir);
+            my $dst_dir= ($src_dir eq 'up')? 'down' : 'up';
+            my $dst_vp = get_vp_id($config,$dst,$dst_endp,$dst_dir);
+
+            # Check if the reverse connection exists
+            if (!exists $connections_hash->{"$dst,$dst_vp"}{"$src,$src_vp"}) {
+                #push @unidirectional_channels, "$src:$src_endp:$dst:$dst_endp";
+                print "[info]: Unidirectional chanel is detected $src,$src_endp -> $dst,$dst_endp\n";
+                $uni_dir.=
+"                CLUSTER_${src}_inter_cluster_chan_in[$src_vp].flit_chanel.credit = CLUSTER_${dst}_inter_cluster_chan_out[$dst_vp].flit_chanel.credit;
+                 CLUSTER_${src}_inter_cluster_chan_in[$src_vp].ctrl_chanel = CLUSTER_${dst}_inter_cluster_chan_out[$dst_vp].ctrl_chanel;\n"
+            }
+        }
+    }#$direction
+    return  $uni_dir;
+}
+
+sub gen_noc_localparam {
+    my ($vcs,$config)=@_;
+    my $rtl="";
+    #Create Noc configuration file
+    my @values = values %$vcs;
+    # Compute min and max
+    my $min_vc = min(@values);
+    my $max_vc = max(@values);
+    my $pp;
+    $pp= do "$noc_param_object_file";
+    die "Error reading: $@" if $@;
+    $pp->{'noc_param'}{"TOPOLOGY"}="\"$topology\"";
+    $pp->{'noc_param'}{"T1"}=$config->{'router_counter'};
+    $pp->{'noc_param'}{"MIN_PCK_SIZE"}= 1;
+    #$pp->{'noc_param'}{"T2"}=$config->{'endp_counter'};
+    $pp->{'noc_param'}{"T3"}=1;
+    $pp->{'noc_param'}{"V"}=$max_vc;
+    $pp->{'noc_param'}{"B"}=$config->{'buffer_depth'};
+    $pp->{'noc_param'}{"Fpay"}=64;
+    $pp->{'noc_param'}{"ROUTE_NAME"}="\"$config->{'routing_algorithm'}\"";
+    $pp->{'noc_param'}{"SELF_LOOP_EN"} = '"YES"';
+
+    if($min_vc !=$max_vc ){
+        $pp->{'noc_param'}{'HETERO_VC'} = 1;
+        $pp->{'noc_param'}{'MAX_ROUTER'} = $config->{'router_counter'};  ;
+        $pp->{'noc_param'}{'MAX_PORT'} = 1;
+        my $hetero_vc="'{\n    //VC  cluster local_id global_id\n";
+        my $coma="";
+        foreach my $mesh (keys %{$config->{multi_mesh}}) {
+            my $nr =$config->{'multi_mesh'}{$mesh}{'NR'};
+            my $rid_int= $config->{'multi_mesh'}{$mesh}{'RID_INT'};
+            my $r=0;
+            my $v=$vcs->{$mesh};
+            for (my $n=$rid_int; $n < $rid_int + $nr;$n++){
+                    $hetero_vc.= "    $coma'{$v} // $mesh:  r$r   R$n  \n";
+                    $coma=",";
+                    $r++;
+            }
+        }
+        $hetero_vc.="} ";
+        $pp->{'noc_param'}{'int VC_CONFIG_TABLE [MAX_ROUTER][MAX_PORT]'} = "$hetero_vc";
+    } else {
+        $pp->{'noc_param'}{'HETERO_VC'} = 0;
+        my $homogeneous_vc = "'{'{0}};";
+        $pp->{'noc_param'}{'int VC_CONFIG_TABLE [MAX_ROUTER][MAX_PORT]'} = "$homogeneous_vc";
+    }
+
+    my $param = $pp->{'noc_param'};
+    my %default_noc_param=%{$param};
+    my @params_order=@{$pp->{'parameters_order'}{'noc_param'}};
+    $rtl.="
+    `ifdef   NOC_LOCAL_PARAM
+    /*************************************
+    *   ProNoC localparams
+    *************************************/\n
+    `include \"define.tmp.h\"\n";
+    foreach my $p (@params_order){
+        next if ($p eq "T2");
+        $rtl.="    localparam $p = $default_noc_param{$p};\n";
+    }
+
+    my $count = 0;
+    my @lines;
+    foreach my $mesh (keys %{$config->{multi_mesh}}) {
+        push @lines, sprintf("        %s_ID = %d,", uc $mesh , $cluster_ids{$mesh});
+    }
+    $rtl.="
+    /*************************************
+    *   multimesh localparams
+    *************************************/
+    localparam\n".join("\n", @lines)."
+        MAX_RID= T1,
+        RIDw = \$clog2(MAX_RID),
+        CLUSTER_NUM = $config->{'cluster_counter'},
+        CLUSTER_IDw= (CLUSTER_NUM==1) ? 1 : \$clog2(CLUSTER_NUM),
+        CLUSTER_MAX_X=$config->{'max_x'},
+        CLUSTER_Xw = (CLUSTER_MAX_X==1)? 1 : \$clog2(CLUSTER_MAX_X),
+        CLUSTER_MAX_Y=$config->{'max_y'},
+        CLUSTER_Yw = (CLUSTER_MAX_Y==1)? 1 : \$clog2(CLUSTER_MAX_Y),
+        CLUSTER_MAX_Z=$config->{'max_z'},
+        CLUSTER_Zw = (CLUSTER_MAX_Z==1)? 1 : \$clog2(CLUSTER_MAX_Z);
+
+    typedef struct packed {
+        logic [CLUSTER_IDw-1: 0] c;
+        logic [CLUSTER_Zw-1 : 0] z;
+        logic [CLUSTER_Yw-1 : 0] y;
+        logic [CLUSTER_Xw-1 : 0] x;
+    } multimesh_router_addr_t;
+    localparam T2= \$bits(multimesh_router_addr_t);
+    ";
+
+    return $rtl;
+}
+sub gen_muli_mesh_topology_rtl{
+    my ($rtl_io_per_cluster,$rtl_cluster_instant,$rtl_io_assign, $rtl_vertical_links_assign ,$v_err ) = @_;
+    return
+    "
+`include \"pronoc_def.v\"
+module multi_mesh #(
+    parameter NOC_ID=0
+    )(
+    `ifndef IO_PER_CLUSTER
+    chan_in_all,
+    chan_out_all,
+    router_event,
+    `else
+$rtl_io_per_cluster
+    `endif
+    reset,
+    clk
+);
+
+    `NOC_CONF
+    `ifndef IO_PER_CLUSTER
+    input   smartflit_chanel_t chan_in_all  [NE-1 : 0];
+    output  smartflit_chanel_t chan_out_all [NE-1 : 0];
+    //Events
+    output  router_event_t  router_event [NR-1 : 0][MAX_P-1 : 0];
+    `endif
+
+    input reset,clk;
+
+    //Unused Input channels are connected to ground
+    smartflit_chanel_t is_grounded = {SMARTFLIT_CHANEL_w{1'b0}};
+
+$rtl_cluster_instant
+
+    //chiplet interconnect
+    always_comb begin
+    `ifndef IO_PER_CLUSTER
+$rtl_io_assign
+    `endif
+$rtl_vertical_links_assign    end
+
+`define ERROR_UNCNT(cluster, port) \\
+        \$display(\"Error: A flit was injected into an unconnected NoC router port.\"); \\
+        \$display(\"Cluster: \%s, Port: %0d\", cluster, port); \\
+        \$display(\"Simulation will terminate due to this unexpected behavior.\"); \\
+        \$finish;
+
+
+`ifdef SIMULATION
+    always \@ ( posedge clk ) begin
+$v_err
+    end
+`endif
+
+endmodule
+";
+}
+sub get_rtl_hdr_file{
+    my $file_name=shift;
+    return
+"//Autogen warning for $file_name ....
+//lisence
+";
+}
+###########
+# functions
+###########
+sub gen_noc_cluster_id_func{
+    my $config=shift;
+    my $lines1="";
+    my $lines2="";
+    my $if="if";
+    my $addr_id_rtl="";
+    my $lines3="";
+    foreach my $mesh (keys %{$config->{multi_mesh}}) {
+        my $MESH=uc $mesh;
+        $lines1.="        $if (rid < CLUSTER_${MESH}_RID_INIT + CLUSTER_${MESH}_NR)   router_id_to_cluster_id =${MESH}_ID;\n";
+        $lines2.="        $if (rid < CLUSTER_${MESH}_RID_INIT + CLUSTER_${MESH}_NR)   router_id_to_cluster_router_id = rid - CLUSTER_${MESH}_RID_INIT;\n";
+        $if="else if";
+    }
+    return"
+    function automatic [CLUSTER_IDw-1:0] router_id_to_cluster_id ;
+    input [RIDw-1 : 0] rid;
+    begin
+$lines1    end
+    endfunction
+
+    //This function get the global unique router id and return the router local id in cluster
+    function automatic [RIDw-1 : 0] router_id_to_cluster_router_id ;
+    input [RIDw-1 : 0] rid;
+    begin
+$lines2   end
+    endfunction
+";
+}
+
+sub find_nearest_vlink {
+    my ($config, $mesh, $up, $dir, $rid) = @_;
+    my @nodes = get_all_connection_nodes_to_a_cluster(\%cluster_tree, $mesh, $dir, $up);
+    my $min;
+    my $nearest_node;
+    foreach my $node (@nodes) {
+        my ($x1, $y1, $z1) = get_xyz($config, $mesh, $node);
+        my ($x2, $y2, $z2) = get_xyz($config, $mesh, $rid);
+        my $manhattan_dist = abs($x1 - $x2) + abs($y1 - $y2) + abs($z1 - $z2);
+        if (!defined $min || $manhattan_dist < $min) {
+            $min = $manhattan_dist;
+            $nearest_node = $node;
+        }
+    }
+    return $nearest_node;
+}
+
+sub get_cmin_cmax{
+    my($tree,$mesh)=@_;
+    my @up_leaf = get_clusters_up_to_leaf ($tree, $mesh);
+    # Get the IDs of all leaf clusters
+    my @ids = sort { $a <=> $b } map { $cluster_ids{$_} } @up_leaf;
+    # Ensure the IDs are continuous
+    for my $i (0 .. $#ids - 1) {
+        die "Error: Cluster IDs are not continuous!: @ids \n" if $ids[$i] + 1 != $ids[$i + 1];
+    }
+    # Return the min and max ID
+    return ($ids[0], $ids[-1]);
+}
+
+sub create_inter_cluster_routing {
+    my ($config,$Vlinks_sel)=@_;
+    my $not_dynamic="";
+    my $not_dynamic_modules="";
+    my $if="if";
+    foreach my $mesh (keys %{$config->{multi_mesh}}) {
+        my $MESH=uc $mesh;
+        my $nr =$config->{'multi_mesh'}{$mesh}{'NR'};
+        $not_dynamic .="    $if ( CLUSTER_ID == ${MESH}_ID ) begin
+        hard_coded_icr_${MESH} #(
+            .CLUSTER_ID(CLUSTER_ID),
+            .RID(RID)
+        )icr_comb (
+            .dest_address(dest_address),
+            .local_cluster_endp_addr(local_cluster_endp_addr),
+            .up_dir_sel(up_dir_sel)
+        );\n";
+        $if="else if";
+        $not_dynamic_modules .=
+    "module hard_coded_icr_${MESH} #(
+    parameter CLUSTER_ID=0,
+    parameter RID=0\n)(
+    dest_address,
+    local_cluster_endp_addr,
+    up_dir_sel\n);
+    `NOC_CONF
+    input multimesh_router_addr_t dest_address;
+    output multimesh_router_addr_t local_cluster_endp_addr;
+    output logic up_dir_sel;
+    localparam unsigned [CLUSTER_IDw-1 : 0] current_cluster_id = CLUSTER_ID;
+    typedef struct packed {
+        logic [CLUSTER_IDw-1 : 0] Cmin,Cmax;
+        multimesh_router_addr_t endp_addr;
+        bit valid;
+    } cluster_hid_entry_t;
+    multimesh_router_addr_t
+        local_cluster_endp_addr_up_dir,
+        local_cluster_endp_addr_down_dir;
+    ";
+        my @up_clusters = get_clusters_in_dir (\%cluster_tree,$mesh,'up');
+        my @down_clusters = get_clusters_in_dir (\%cluster_tree,$mesh,'down');
+        if(scalar @down_clusters>1){
+            die "Error: multiple Cluster @down_clusters are detected for $mesh chiplet which is not supported by 2.5 D mesh \n";
+        }
+        my $no_down=((scalar @down_clusters)==0)? 1 : 0;
+        $not_dynamic_modules .= " " x 8 . "localparam NO_DOWNLINK = $no_down;\n";
+        if(scalar @up_clusters){
+            my $s=scalar @up_clusters;
+            $not_dynamic_modules .= " " x 8 . "localparam MAX_ENTRY_${MESH} = $s;\n";
+            $not_dynamic_modules .= " " x 8 . "cluster_hid_entry_t  address_table [MAX_ENTRY_${MESH}];\n";
+            $not_dynamic_modules .= " " x 8 . "multimesh_router_addr_t endp_addr_array [MAX_ENTRY_${MESH}];\n";
+            $not_dynamic_modules .= " " x 8 . "wire [CLUSTER_IDw-1 : 0] Cmax_array_${MESH} [MAX_ENTRY_${MESH}];\n";
+            $not_dynamic_modules .= " " x 8 . "wire [CLUSTER_IDw-1 : 0] Cmin_array_${MESH} [MAX_ENTRY_${MESH}];\n";
+            my $i=0;
+            foreach my $up (@up_clusters){
+                my ($cmin,$cmax) = get_cmin_cmax(\%cluster_tree,$up);
+                $not_dynamic_modules .= " " x 8 . "assign Cmax_array_${MESH} [$i]= $cmax;\n";
+                $not_dynamic_modules .= " " x 8 . "assign Cmin_array_${MESH} [$i]= $cmin;\n";
+                $i++;
+            }
+        }else {
+            $not_dynamic_modules .=" " x 8 ."//There are no upper chiplet. Select between local and down chiplet\n";
+        }
+        $not_dynamic_modules .=" " x 8 ."generate \n case (RID)\n";
+        for (my $rid=0;$rid<$nr;$rid++){
+            $not_dynamic_modules .=" " x 8 . "$rid: begin \n";
+            my $i=0;
+            my $coma="";
+            foreach my $up (@up_clusters){
+                #check if vertical link connection exsited in yaml file
+                my $local_dst=$Vlinks_sel->{'up'}{$mesh}{$up}{$rid};
+                my $via_yml = (defined $local_dst)? 1:0;
+                $local_dst= ($via_yml==1)? $local_dst : find_nearest_vlink($config,$mesh,$up,"up",$rid);
+                my ($x,$y,$z)=get_xyz($config,$mesh,$local_dst);
+                my $comment =($via_yml ==1)?
+                    "S:Yaml,T:$up,R:$local_dst":
+                    "S:Auto,T:$up,R:$local_dst";
+                $not_dynamic_modules .=" "  x 12 . "assign endp_addr_array[$i]='{x:$x, y:$y, z:$z, c:${mesh}_ID};/*$comment*/\n";
+                $i++;
+                $coma=",";
+            }
+            unless($no_down){
+            my $local_dst=find_nearest_vlink($config,$mesh,$down_clusters[0],"down",$rid);
+            my ($x,$y,$z)=get_xyz($config,$mesh,$local_dst);
+            my $comment ="S:Auto,T:$down_clusters[0],R:$local_dst";
+            $not_dynamic_modules .=" "  x 12 . "assign local_cluster_endp_addr_down_dir ='{x:$x, y:$y, z:$z, c:${mesh}_ID};/*$comment*/\n";
+            }
+            $not_dynamic_modules .=" "  x 8 ."end //$rid\n";
+        }
+        $not_dynamic_modules .=" " x 8 . "endcase\n    endgenerate\n";
+        if(scalar @up_clusters){
+            $not_dynamic_modules .=" " x 8 . "always_comb begin
+            local_cluster_endp_addr_up_dir=0;
+            up_dir_sel=1'b0;
+            for (int i=0;i< MAX_ENTRY_${MESH};i++) begin
+                if(Cmin_array_${MESH}[i] <= dest_address.c &&  dest_address.c <= Cmax_array_${MESH}[i]) begin
+                    local_cluster_endp_addr_up_dir = endp_addr_array[i];
+                    up_dir_sel=1'b1;
+                end
+            end
+        end\n";
+        }else{
+            $not_dynamic_modules .=" " x 8 . "always_comb begin
+            local_cluster_endp_addr_up_dir=0;
+            up_dir_sel=1'b0;
+        end\n";
+        }
+    $not_dynamic .="    end\n";
+    $not_dynamic_modules .="
+    assign local_cluster_endp_addr =
+        ( dest_address.c == current_cluster_id )? dest_address:
+        ( up_dir_sel) ? local_cluster_endp_addr_up_dir:
+        local_cluster_endp_addr_down_dir;
+endmodule\n\n";
+    }
+
+my $rtl="
+`include \"pronoc_def.v\"
+module global_id_to_local_cluster_endp #(
+    parameter NOC_ID=0
+    `ifndef DYNAMIC_CLUSTER_INIT
+    ,parameter CLUSTER_ID=0,
+    parameter RID=0
+    `endif
+)(
+    `ifdef DYNAMIC_CLUSTER_INIT
+    address_table,
+    local_cluster_endp_addr_down_dir,
+    current_cluster_id,
+    `endif
+    dest_address,
+    local_cluster_endp_addr,
+    up_dir_sel
+);
+    `NOC_CONF
+    input multimesh_router_addr_t dest_address;
+    output multimesh_router_addr_t local_cluster_endp_addr;
+    output logic up_dir_sel;
+
+    `ifdef DYNAMIC_CLUSTER_INIT
+    input  cluster_hid_entry_t  address_table [MAX_ENTRY];
+    input  multimesh_router_addr_t local_cluster_endp_addr_down_dir;
+    input [CLUSTER_IDw-1 : 0] current_cluster_id;
+    `endif
+
+    `ifndef DYNAMIC_CLUSTER_INIT
+    generate
+$not_dynamic
+    endgenerate
+    `else
+    dynamic_icr  icr (
+        .dest_address(dest_address),
+        .local_cluster_endp_addr(local_cluster_endp_addr),
+        .local_cluster_endp_addr_down_dir(local_cluster_endp_addr_down_dir),
+        .current_cluster_id(current_cluster_id),
+        .address_table(address_table),
+        up_dir_sel(up_dir_sel)
+    );
+    `endif
+endmodule
+
+`ifdef DYNAMIC_CLUSTER_INIT
+module dynamic_icr (
+    dest_address,
+    local_cluster_endp_addr,
+    local_cluster_endp_addr_down_dir,
+    current_cluster_id,
+    address_table,
+    up_dir_sel
+);
+    `NOC_CONF
+    input multimesh_router_addr_t dest_address;
+    output multimesh_router_addr_t local_cluster_endp_addr;
+    input multimesh_router_addr_t    local_cluster_endp_addr_down_dir;
+    input [CLUSTER_IDw-1 : 0] current_cluster_id;
+    input cluster_hid_entry_t  address_table [MAX_ENTRY];
+    output logic up_dir_sel;
+
+    multimesh_router_addr_t local_cluster_endp_addr_up_dir;
+
+    always_comb begin
+        local_cluster_endp_addr_up_dir=0;
+        up_dir_sel=1'b0;
+        for (int i=0;i< MAX_ENTRY;i++) begin
+            if(address_table[i].valid) begin
+                if(address_table[i].Cmin <= dest_address.c &&  dest_address.c < address_table[i].Cmax) begin
+                    local_cluster_endp_addr_up_dir = address_table[i].endp_addr;
+                    up_dir_sel=1'b1;
+                end
+            end
+        end
+    end
+
+    assign local_cluster_endp_addr =
+        ( dest_address.c == current_cluster_id )? dest_address:
+        ( up_dir_sel) ? local_cluster_endp_addr_up_dir:
+        local_cluster_endp_addr_down_dir;
+endmodule
+
+module dynamic_hids_per_router (
+    local_cluster_endp_addr_down_dir,
+    current_cluster_id,
+    address_table,
+    program_port,
+    reset,
+    clk
+);
+    `NOC_CONF
+    output cluster_hid_entry_t  address_table [MAX_ENTRY];
+    input clk,reset;
+    input program_port_t program_port;
+    output multimesh_router_addr_t local_cluster_endp_addr_down_dir;
+    output logic [CLUSTER_IDw-1 : 0] current_cluster_id;
+
+    always_ff @(posedge clk or posedge reset) begin
+        if(reset) begin
+            local_cluster_endp_addr_down_dir=0;
+            foreach (address_table[i]) begin
+                address_table[i].valid <= 1'b0;
+                current_cluster_id<=0;
+            end
+        end else begin
+            if(program_port.data.valid) begin
+                if( !program_port.down_sel ) begin
+                        address_table[program_port.addr] <= program_port.data;
+                        current_cluster_id <= program_port.current_cluster_id;
+                end else local_cluster_endp_addr_down_dir=program_port.data.endp_addr;
+            end
+        end
+    end
+endmodule
+
+`else
+$not_dynamic_modules
+`endif
+
+";
+return $rtl;
+
+
+}
+###########
+#   modules
+#########
+
+sub create_routing_modules{
+    my $rtl = multimesh_address_encoder(@_);
+    $rtl.= multimesh_address_decoder(@_);
+    return $rtl;
+}
+
+sub  multimesh_address_decoder{
+    my $config=shift;
+    my $lines="";
+    foreach my $mesh (keys %{$config->{multi_mesh}}) {
+        my $MESH=uc $mesh;
+        $lines.="
+        for (int z=0; z<CLUSTER_${MESH}_NZ; z=z+1) begin: ${MESH}Z_
+            for (int y=0; y<CLUSTER_${MESH}_NY; y=y+1) begin: ${MESH}Y_
+                for (int x=0; x<CLUSTER_${MESH}_NX; x=x+1) begin: ${MESH}X_
+                    //int  RID=(z*(CLUSTER_${MESH}_NY * CLUSTER_${MESH}_NY) + (y * CLUSTER_${MESH}_NX) + x) + CLUSTER_${MESH}_RID_INIT;
+                    multimesh_router_addr_t  CODED;
+                    CODED.x=x;
+                    CODED.y=y;
+                    CODED.z=z;
+                    CODED.c=${MESH}_ID;
+                    addr_table[CODED]=(z*(CLUSTER_${MESH}_NY * CLUSTER_${MESH}_NY) + (y * CLUSTER_${MESH}_NX) + x) + CLUSTER_${MESH}_RID_INIT;
+                end
+            end
+        end
+        ";
+    }
+
+return "
+
+module multimesh_address_decoder (
+    rid_out,
+    addr_st_i
+);
+    `NOC_CONF
+    output  [RIDw-1 : 0] rid_out;
+    input multimesh_router_addr_t addr_st_i;
+    localparam BITS= \$bits(multimesh_router_addr_t);
+    logic [RIDw-1 : 0] addr_table [2**BITS-1 :0];
+    always_comb begin
+    $lines
+    end
+    assign rid_out = addr_table [addr_st_i];
+endmodule
+";
+}
+
+sub  multimesh_address_encoder{
+    my $config=shift;
+    my $lines="";
+    foreach my $mesh (keys %{$config->{multi_mesh}}) {
+        my $MESH=uc $mesh;
+        $lines.="
+        for (z=0; z<CLUSTER_${MESH}_NZ; z=z+1) begin: ${MESH}Z_
+            for (y=0; y<CLUSTER_${MESH}_NY; y=y+1) begin: ${MESH}Y_
+                for (x=0; x<CLUSTER_${MESH}_NX; x=x+1) begin: ${MESH}X_
+                    localparam RID=(z*(CLUSTER_${MESH}_NY * CLUSTER_${MESH}_NY) + (y * CLUSTER_${MESH}_NX) + x) + CLUSTER_${MESH}_RID_INIT;
+                    assign addr_table [RID].x=x;
+                    assign addr_table [RID].y=y;
+                    assign addr_table [RID].z=z;
+                    assign addr_table [RID].c=${MESH}_ID;
+                end
+            end
+        end
+        ";
+    }
+    return "
+`include \"pronoc_def.v\"
+
+module multimesh_address_encoder (
+    rid_in,
+    addr_st_o
+);
+    `NOC_CONF
+    input  [RIDw-1 : 0] rid_in;
+    output multimesh_router_addr_t addr_st_o;
+
+    multimesh_router_addr_t addr_table [MAX_RID];
+    genvar x,y,z;
+    generate
+    $lines
+    endgenerate
+
+    assign addr_st_o = addr_table [rid_in];
+endmodule"
+;
+
+}
+
+sub multimesh_routing_xyz {
+    my $conf=shift;
+    return "
+
+module multimesh_route #(
+    parameter type multimesh_router_addr_t
+)(
+    current_router_addr_i,
+    destination_router_addr_i,
+    router_port_out
+);
+    `NOC_CONF
+    input  multimesh_router_addr_t current_router_addr_i,destination_router_addr_i;
+    output [MAX_P-1 : 0] router_port_out;
+
+    generate
+    if(current_router_addr_in.c != destination_router_addr_i.c) begin
+        multimesh_cluster_to_clusterr_route  c_to_c(
+            .current_router_addr_i(current_router_addr_i),
+            .destination_router_addr_i(destination_router_addr_i),
+            .router_port_out(router_port_out)
+        );
+    end else begin
+        intercluster_route_xyz the_xyz (
+            .current_router_addr_i(current_router_addr_i),
+            .destination_router_addr_i(destination_router_addr_i),
+            .router_port_out(router_port_out)
+        );
+    end
+    endgenerate
+endmodule
+";
+}
+
+sub get_scolar_pos{
+    my ($item,@list)=@_;
+    return (grep { $list[$_] eq $item } 0..$#list)[0];
+}
+
+sub create_rtl_file{
+    my ($rtl_file,$rtl_code)=@_;
+    # Extract filename and extension
+    my ($filename, $dirs, $ext) = fileparse($rtl_file, qr/\.[^.]*/);
+    my $header=get_rtl_hdr_file("$filename.$ext");
+
+    open(my $output_fh, '>', $rtl_file) or die "Could not create file '$rtl_file' $!";
+    print $output_fh $header.$rtl_code;
+    close($output_fh);
+    print"[info:] Create $rtl_file\n";
+}
+
+sub generate_pronoc_multimesh{
+    my %verticals;
+    my %Vlinks_sel;
+    my %is_connected;
+    my %connections_hash;
+    my %vcs;
+    #generate routers_global_ids
+    my $I=find_interpose($config);
+    my %router_ids;
+    my $multimesh_rtl_file="$out_dir/".lc $topology.".sv";
+    my $noc_param_file="$out_dir/noc_localparam.v";
+    my $multimesh_routing_file="$out_dir/". lc ${topology}."_routing.sv";
+    my $intercluster_routing_table="$out_dir/". lc ${topology}."_icr.sv";
+    my $rtl_io_per_cluster ="";
+    my $rtl_cluster_instant="";
+    my $rtl_io_assign="";
+    my $rtl_cluster_localparam="";
+    my $rtl_noc_localparam="";
+    my $rtl_vertical_links_assign="";
+
+    print"[info:]generating $topology topology file in $multimesh_rtl_file\n";
+    foreach my $mesh (keys %{$config->{multi_mesh}}) {
+        print "\t[info:] Add CLUSTER_${mesh} instantiation \n";
+        update_multimesh_config($mesh,$config,\%vcs);
+        $rtl_io_assign.=gen_multi_mesh_io_assign($mesh);
+        $rtl_io_per_cluster.=gen_io_name_per_cluster($mesh);
+        $rtl_cluster_localparam.=gen_multi_mesh_cluster_localparam($mesh,$config);
+        $rtl_cluster_instant.=gen_multi_mesh_cluster_instant($mesh);
+        my $nodes_num = $config->{'multi_mesh'}{$mesh}{'NR'};
+        for( my $i=0; $i<$nodes_num; $i++) {
+            $is_connected{'IN'}{$mesh}{$i}=0;
+            $is_connected{'OUT'}{$mesh}{$i}=0;
+        }
+        if (exists $config->{'multi_mesh'}{$mesh}{'vertical_links_placement'}) {
+            vertical_links_placement($mesh,$config,\%verticals,$I);
+        }
+        if (exists $config->{'multi_mesh'}{$mesh}{'vertical_links_selection'}){
+            vertical_links_selection($mesh,$config,\%Vlinks_sel,$I);
+        }
+    }
+    %cluster_ids=get_cluster_ids($config,\%cluster_tree);
+    my ($v_links,$v_err)=gen_multi_mesh_vertical_link_assign(\%verticals,\%is_connected,\%connections_hash);
+    $rtl_vertical_links_assign.=$v_links;
+    #Uni directional channels
+    my $uni_dir=gen_multimesh_unidir_vlinks(\%verticals,\%connections_hash);
+    if (length ($uni_dir) >3){
+        $rtl_vertical_links_assign.=
+        "//fix credit/ctrl chanel connection for unidirectional channels\n$uni_dir";
+    }
+
+    my $rtl_code=gen_muli_mesh_topology_rtl  ($rtl_io_per_cluster,$rtl_cluster_instant,$rtl_io_assign, $rtl_vertical_links_assign, $v_err  ) ;
+    create_rtl_file( $multimesh_rtl_file,$rtl_code);
+
+    $rtl_code=gen_noc_localparam(\%vcs,$config);
+    $rtl_code.=$rtl_cluster_localparam;
+    $rtl_code.=gen_noc_cluster_id_func($config);
+    $rtl_code.="  typedef struct packed {
+        logic [CLUSTER_IDw-1 : 0] Cmin,Cmax;
+        multimesh_router_addr_t endp_addr;
+        bit valid;
+    } cluster_hid_entry_t;
+
+    localparam [1:0]
+        Z_PLUS_SEL=2'b00,
+        Z_MIN_SEL=2'b01,
+        BOTH_SEL=2'b10,
+        SAME_SEL=2'b11;
+
+
+    `ifdef DYNAMIC_CLUSTER_INIT
+    localparam MAX_ENTRY=10;
+    typedef struct packed {
+        cluster_hid_entry_t data;
+        logic [\$clog2(MAX_ENTRY)-1 : 0] addr;
+        logic [CLUSTER_IDw-1 : 0] current_cluster_id;
+        bit down_sel;
+    } program_port_t;
+    `endif
+    `endif\n";
+    create_rtl_file($noc_param_file,$rtl_code);
+    $rtl_code=create_routing_modules($config);
+    create_rtl_file($multimesh_routing_file,$rtl_code);
+    $rtl_code= create_inter_cluster_routing($config,\%Vlinks_sel);
+    create_rtl_file($intercluster_routing_table,$rtl_code);
+
+#my @children = get_clusters_in_dir (\%cluster_tree,'C1','down');
+#print "'C1 down: @children\n";
+#@children = get_clusters_in_dir (\%cluster_tree,'C1','up');
+#print "'C1 up: @children\n";
+#@children = get_clusters_in_dir (\%cluster_tree,'I','down');
+#print "'I down: @children\n";
+#@children = get_clusters_in_dir (\%cluster_tree,'I','up');
+#print "'I up: @children\n";
+#print Dumper(\%cluster_ids);
+
+}
+
+#sub get_nearest_vlink{
+#    my ($config,$mesh1,$id1,$mesh2,$id2)=@_;
+#    print "$mesh1,$id1,$mesh2,$id2\n";
+#    return undef if($mesh1 eq $mesh2);
+#    my ($paths_to_dst,$ports_to_dst) = get_all_minimal_paths_between_two_endps($config,$mesh1."_".$id1,$mesh2."_".$id2);
+#    my $min_index=100000;
+#    my $i=0;
+#    my @a;
+#    foreach my $path (@{$ports_to_dst}) {
+#        if (defined $path){
+#            my @ports=@{$path};
+#            my $p= get_scolar_pos(7,@ports) //  get_scolar_pos(5,@ports);
+#            if($min_index>$p){
+#                $min_index=$p;
+#                @a= @{$paths_to_dst->[$i]};
+#            }
+#        }
+#        $i++;
+#    }
+#
+#    my @l=split ("_", $a[$min_index-1]);
+#    #print "** @a : $min_index\n";
+#    print "local selection $a[$min_index-1]\n mesh is $l[0], id is $l[1]\n";
+#    return $l[1];
+#}
+
+1;
+
diff --git a/mpsoc/script/multimesh/pronoc_dp_gen.py b/mpsoc/script/multimesh/pronoc_dp_gen.py
new file mode 100755
index 0000000..c60a527
--- /dev/null
+++ b/mpsoc/script/multimesh/pronoc_dp_gen.py
@@ -0,0 +1,862 @@
+from collections import defaultdict
+import os
+import sys
+
+piton_dir = os.environ.get('PITON_ROOT', "")
+if piton_dir == "":
+    raise Exception("PITON_ROOT must be defined")
+
+sys.path.append(os.path.join(piton_dir,
+                             "piton/tools/bin"))
+
+from piton_common import *
+
+# Number of ports necessary for Depth-First
+MAX_PORT = 7
+
+# Indentation size
+TAB = " "*4
+
+# System Configuration
+chip_infos = {}
+
+# Define Virtual Channels Constants
+# NOTE: The values should not be modified for now as the ProNoC router does not
+# support that Z_MIN_VC = 2 when using a single VC on the interposer. Z- must
+# have the VC index 0 (i.e. a one-hot encoded value of 1).
+Z_MIN_VC  = 1 # 2'd01
+Z_PLUS_VC = 2 # 2'd10
+Z_MIN_VC_IDX  = Z_MIN_VC  - 1
+Z_PLUS_VC_IDX = Z_PLUS_VC - 1
+
+
+# Load system configuration from the caller
+def load_chip_infos(piton_chip_infos):
+    global chip_infos
+    chip_infos = piton_chip_infos
+
+
+# Open and write the code in a specific file
+def write_in_file(path_to_file, content):
+    filename, ext = os.path.splitext(os.path.basename(path_to_file))
+    header = f"// {filename}{ext} -- auto-generated\n"
+
+    with open(path_to_file, 'w') as output_fh:
+        output_fh.write(header + content)
+    print(f"[info] Create {path_to_file}")
+
+
+# Bulk generation of all multimesh files
+def generate_pronoc_multimesh(out_dir):
+    multimesh_rtl_file = os.path.join(out_dir, "multi_mesh.sv")
+    noc_param_file = os.path.join(out_dir, "noc_localparam.v")
+    multimesh_routing_file = os.path.join(out_dir, "multi_mesh_routing.sv")
+    intercluster_routing_table = os.path.join(out_dir, "multi_mesh_icr.sv")
+    rtl_intercluster_channels = ""
+    rtl_cluster_instant = ""
+    rtl_io_assign = ""
+    rtl_cluster_localparam = ""
+    rtl_vertical_links_assign = ""
+
+    print(f"[info] Generating topology file in {multimesh_rtl_file}")
+
+    for chip_name, chip_info in chip_infos.items():
+        print(f"\t[info] Add CLUSTER_{chip_name} instantiation")
+        rtl_io_assign += gen_multi_mesh_io_assign(chip_name)
+        rtl_intercluster_channels += gen_io_name_per_cluster(chip_name)
+        rtl_cluster_localparam += gen_multi_mesh_cluster_localparam(chip_info)
+        rtl_cluster_instant += gen_multi_mesh_cluster_instant(chip_name)
+
+    v_links, _, v_err, grounded_signals = gen_multi_mesh_vertical_link_assign()
+    rtl_vertical_links_assign += v_links
+
+    rtl_code = gen_multi_mesh_topology_rtl(rtl_cluster_instant, rtl_io_assign,
+                                           rtl_vertical_links_assign, v_err,
+                                           grounded_signals)
+    write_in_file(multimesh_rtl_file, rtl_code)
+
+    rtl_code = gen_noc_localparam()
+    rtl_code += rtl_cluster_localparam
+    rtl_code += f"""
+{TAB}typedef struct packed {{
+{TAB}{TAB}logic [CLUSTER_IDw-1:0] Cmin, Cmax;
+{TAB}{TAB}multimesh_router_addr_t endp_addr;
+{TAB}{TAB}bit valid;
+{TAB}}} cluster_hid_entry_t;
+
+{TAB}localparam [V-1:0]
+{TAB}{TAB}Z_PLUS_VC = {Z_PLUS_VC},
+{TAB}{TAB}Z_MIN_VC  = {Z_MIN_VC};
+
+{TAB}localparam
+{TAB}{TAB}Z_PLUS_VC_IDX = {Z_PLUS_VC_IDX},
+{TAB}{TAB}Z_MIN_VC_IDX  = {Z_MIN_VC_IDX};
+
+`ifdef DYNAMIC_CLUSTER_INIT
+{TAB}localparam DYN_ICRT_MAX_ENTRY = 10;
+{TAB}typedef struct packed {{
+{TAB}{TAB}cluster_hid_entry_t data;
+{TAB}{TAB}logic [$clog2(DYN_ICRT_MAX_ENTRY)-1:0] addr;
+{TAB}{TAB}logic [CLUSTER_IDw-1:0] current_cluster_id;
+{TAB}{TAB}bit down_sel;
+{TAB}}} program_port_t;
+`endif // DYNAMIC_CLUSTER_INIT
+"""
+    rtl_code += "`endif // NOC_LOCAL_PARAM\n"
+    write_in_file(noc_param_file, rtl_code)
+    rtl_code = create_routing_modules()
+    write_in_file(multimesh_routing_file, rtl_code)
+    rtl_code = create_inter_cluster_routing()
+    write_in_file(intercluster_routing_table, rtl_code)
+
+
+def gen_multi_mesh_io_assign(chip_name):
+    CHIP = chip_name.upper()
+    return f"""
+{TAB}{TAB}for (int i = 0; i < CLUSTER_{CHIP}_NE; i++) begin
+{TAB}{TAB}{TAB}CLUSTER_{chip_name}_endpoint_chan_in[i] = chan_in_all[CLUSTER_{CHIP}_EID_INIT+i];
+{TAB}{TAB}{TAB}chan_out_all[CLUSTER_{CHIP}_EID_INIT+i]= CLUSTER_{chip_name}_endpoint_chan_out[i];
+{TAB}{TAB}end
+"""
+
+
+def gen_io_name_per_cluster(chip_name):
+    return f"""
+{TAB}CLUSTER_{chip_name}_endpoint_chan_in,
+{TAB}CLUSTER_{chip_name}_endpoint_chan_out,
+"""
+
+
+def gen_multi_mesh_cluster_localparam(chip_info):
+    CHIP = chip_info._name.upper()
+    return f"""
+{TAB}/****************
+{TAB}* CLUSTER_{CHIP} localparams
+{TAB}****************/
+{TAB}localparam
+{TAB}{TAB}CLUSTER_{CHIP}_NX = {chip_info._dim_x},
+{TAB}{TAB}CLUSTER_{CHIP}_NY = {chip_info._dim_y},
+{TAB}{TAB}CLUSTER_{CHIP}_NZ = {chip_info._dim_z},
+{TAB}{TAB}CLUSTER_{CHIP}_MAX_P = {MAX_PORT},
+{TAB}{TAB}// Only used in standalone mode (w/o OpenPiton)
+{TAB}{TAB}CLUSTER_{CHIP}_RID_INIT = {chip_info._chip_offset_id},
+{TAB}{TAB}// Only used in standalone mode (w/o OpenPiton)
+{TAB}{TAB}CLUSTER_{CHIP}_EID_INIT = {chip_info._chip_offset_id},
+{TAB}{TAB}// Only used in standalone mode (w/o OpenPiton)
+{TAB}{TAB}CLUSTER_{CHIP}_NE = CLUSTER_{CHIP}_NX * CLUSTER_{CHIP}_NY * CLUSTER_{CHIP}_NZ,
+{TAB}{TAB}// Only used in standalone mode (w/o OpenPiton)
+{TAB}{TAB}CLUSTER_{CHIP}_NR = CLUSTER_{CHIP}_NE,
+{TAB}{TAB}CLUSTER_{CHIP}_NVP = 2 * (CLUSTER_{CHIP}_NX * CLUSTER_{CHIP}_NY);
+"""
+
+
+def gen_multi_mesh_cluster_instant(chip_name):
+    CHIP = chip_name.upper()
+    return f"""
+{TAB}smartflit_chanel_t CLUSTER_{chip_name}_endpoint_chan_in [CLUSTER_{CHIP}_NE-1:0];
+{TAB}smartflit_chanel_t CLUSTER_{chip_name}_endpoint_chan_out[CLUSTER_{CHIP}_NE-1:0];
+{TAB}smartflit_chanel_t CLUSTER_{chip_name}_inter_cluster_chan_in[CLUSTER_{CHIP}_NVP-1:0];
+{TAB}smartflit_chanel_t CLUSTER_{chip_name}_inter_cluster_chan_out[CLUSTER_{CHIP}_NVP-1:0];
+{TAB}router_event_t CLUSTER_{chip_name}_router_event[CLUSTER_{CHIP}_NR-1:0][CLUSTER_{CHIP}_MAX_P-1:0];
+
+{TAB}mesh_cluster #(
+{TAB}{TAB}.CLUSTER_ID({CHIP}_ID),
+{TAB}{TAB}.RID_INIT(CLUSTER_{CHIP}_RID_INIT),
+{TAB}{TAB}.CLUSTER_NX(CLUSTER_{CHIP}_NX),
+{TAB}{TAB}.CLUSTER_NY(CLUSTER_{CHIP}_NY),
+{TAB}{TAB}.CLUSTER_NZ(CLUSTER_{CHIP}_NZ),
+{TAB}{TAB}.CLUSTER_NE(CLUSTER_{CHIP}_NE)
+{TAB}) noc_{chip_name}(
+{TAB}{TAB}.reset(reset),
+{TAB}{TAB}.clk(clk),
+{TAB}{TAB}.cluster_id({CHIP}_ID[CLUSTER_IDw-1:0]),
+{TAB}{TAB}.endpoint_chan_in(CLUSTER_{chip_name}_endpoint_chan_in),
+{TAB}{TAB}.endpoint_chan_out(CLUSTER_{chip_name}_endpoint_chan_out),
+{TAB}{TAB}.inter_cluster_chan_in(CLUSTER_{chip_name}_inter_cluster_chan_in),
+{TAB}{TAB}.inter_cluster_chan_out(CLUSTER_{chip_name}_inter_cluster_chan_out),
+{TAB}{TAB}.router_event(CLUSTER_{chip_name}_router_event)
+{TAB});
+
+{TAB}assign router_event[CLUSTER_{CHIP}_RID_INIT +: CLUSTER_{CHIP}_NR] = CLUSTER_{chip_name}_router_event;
+"""
+
+
+def compute_vlink_idx(chip_info, lid, vdir_is_down):
+    x, y, z = convert_local_id_to_xyz(chip_info, lid)
+    dimx = chip_info._dim_x
+    dimy = chip_info._dim_y
+    dimz = chip_info._dim_z
+
+    if z != 0 and z != dimz - 1:
+        raise ValueError(f"Error: Inter-cluster connection at Z={z} is " + \
+                          "invalid. It must be at either the first (0) " + \
+                         f"or last ({dimz-1}) position in the Z dimension.")
+    if z == 0 and dimz > 1 and not(vdir_is_down):
+        raise ValueError("Error: Routers at the first Z layer (Z=0) can" + \
+                         " only have a 'down' connection.")
+    if z == dimz - 1 and dimz > 1 and vdir_is_down:
+        raise ValueError(f"Error: Routers at the last Z layer (Z={dimz-1})" + \
+                          "can only have an 'up' connection.")
+
+    vp = (y * dimx) + x if vdir_is_down else \
+                        (dimx * dimy) + (y * dimx) + x
+    return vp
+
+
+def gen_multi_mesh_vertical_link_assign(noc_id=0):
+    is_connected = defaultdict(lambda: defaultdict(dict))
+
+    for chip_name, chip_info in chip_infos.items():
+        # Up and Down connections account for 2 * number of routers
+        connections_num = chip_info.get_number_of_routers() * 2
+        # Initialize the base 'connection' dictionary
+        for i in range(connections_num):
+            is_connected['OUT'][chip_name][i] = 0
+            is_connected['IN'][chip_name][i]  = 0
+
+    noc_adapters    = "`ifdef PITON_MULTICHIP\n"
+    links_assign    = "`ifndef PITON_MULTICHIP\n"
+    unconnected_err = ""
+
+    for connections in iter_on_vertical_connections(chip_infos):
+        (src_chip, src_endp, dst_chip, dst_endp, src_dir_is_down) = connections
+        src_chip_info = chip_infos[src_chip]
+        # Compute the src vlink idx in the bunch of wires
+        src_vp = compute_vlink_idx(src_chip_info, int(src_endp),
+                                   src_dir_is_down)
+        # "Z+" credits are released on index Z_PLUS_VC_IDX
+        # "Z-" credits are released on Z_MIN_VC_IDX
+        credit_idx = Z_MIN_VC_IDX if src_dir_is_down else Z_PLUS_VC_IDX
+
+        dst_dir_is_down = not src_dir_is_down
+        dst_chip_info = chip_infos[dst_chip]
+        # Compute the dst vlink idx in the bunch of wires
+        dst_vp = compute_vlink_idx(dst_chip_info, int(dst_endp),
+                                   dst_dir_is_down)
+
+        src_dir = "down" if src_dir_is_down else "up"
+        dst_dir = "down" if dst_dir_is_down else "up"
+
+        # Used with OpenPiton
+        noc_adapters += f"""\
+{TAB}{TAB}noc{noc_id}_inter_chip_adapter_{src_chip}_{dst_chip} {src_chip}_{dst_chip}_noc_adapter_{src_endp}_{dst_endp}(
+{TAB}{TAB}{TAB}.clk(clk),
+{TAB}{TAB}{TAB}.rst_n(rst_n),
+
+{TAB}{TAB}{TAB}.flit_wr_i(CLUSTER_{src_chip}_inter_cluster_chan_out[{src_vp}].flit_chanel.flit_wr),
+{TAB}{TAB}{TAB}.flit_data_i(CLUSTER_{src_chip}_inter_cluster_chan_out[{src_vp}].flit_chanel.flit),
+{TAB}{TAB}{TAB}.flit_wr_o(CLUSTER_{dst_chip}_inter_cluster_chan_in[{dst_vp}].flit_chanel.flit_wr),
+{TAB}{TAB}{TAB}.flit_data_o(CLUSTER_{dst_chip}_inter_cluster_chan_in[{dst_vp}].flit_chanel.flit),
+
+{TAB}{TAB}{TAB}.downstream_credit_i(CLUSTER_{dst_chip}_inter_cluster_chan_out[{dst_vp}].flit_chanel.credit[{credit_idx}]),
+{TAB}{TAB}{TAB}.upstream_credit_o(CLUSTER_{src_chip}_inter_cluster_chan_in[{src_vp}].flit_chanel.credit[{credit_idx}]),
+
+{TAB}{TAB}{TAB}.downstream_ctrl_i(CLUSTER_{dst_chip}_inter_cluster_chan_out[{dst_vp}].ctrl_chanel),
+{TAB}{TAB}{TAB}.upstream_ctrl_o(CLUSTER_{src_chip}_inter_cluster_chan_in[{src_vp}].ctrl_chanel)
+{TAB}{TAB});
+{TAB}{TAB}assign CLUSTER_{src_chip}_inter_cluster_chan_in[{src_vp}].flit_chanel.credit[{int(not(credit_idx))}] = 1'b0;\n
+"""
+        # Used in standalone mode
+        links_assign += f"""\
+{TAB}{TAB}// {src_chip}[{src_endp}] dir {src_dir} to {dst_chip}[{dst_endp}] dir {dst_dir}
+{TAB}{TAB}CLUSTER_{dst_chip}_inter_cluster_chan_in[{dst_vp}].flit_chanel.flit_wr = CLUSTER_{src_chip}_inter_cluster_chan_out[{src_vp}].flit_chanel.flit_wr;
+{TAB}{TAB}CLUSTER_{dst_chip}_inter_cluster_chan_in[{dst_vp}].flit_chanel.flit = CLUSTER_{src_chip}_inter_cluster_chan_out[{src_vp}].flit_chanel.flit;
+{TAB}{TAB}CLUSTER_{src_chip}_inter_cluster_chan_in[{src_vp}].flit_chanel.credit = CLUSTER_{dst_chip}_inter_cluster_chan_out[{dst_vp}].flit_chanel.credit;
+{TAB}{TAB}CLUSTER_{src_chip}_inter_cluster_chan_in[{src_vp}].ctrl_chanel = CLUSTER_{dst_chip}_inter_cluster_chan_out[{dst_vp}].ctrl_chanel;
+"""
+        is_connected['OUT'][dst_chip][dst_vp] = 1
+        is_connected['IN'][src_chip][src_vp]  = 1
+
+    noc_adapters += "`endif // PITON_MULTICHIP\n"
+    links_assign += "`endif // PITON_MULTICHIP\n"
+
+    links_assign += f"\n{TAB}{TAB}// Tie to the ground unconnected vertical ports\n"
+
+    out_connections = is_connected['OUT']
+    in_connections  = is_connected['IN']
+    # NOTE: Veloce place and route doesn't like the grounding...
+    links_assign += "`ifndef VELOCE_EMULATION\n"
+    for dst_chip in sorted(out_connections.keys()):
+        for dst_vp in sorted(out_connections[dst_chip].keys()):
+            # Output vertical links are not assigned and their associated input
+            # control channel is not used
+            if out_connections[dst_chip][dst_vp] == 0 and \
+               in_connections[dst_chip][dst_vp] == 0:
+                links_assign += f"""\
+{TAB}{TAB}CLUSTER_{dst_chip}_inter_cluster_chan_in[{dst_vp}] = is_grounded_{dst_chip};
+"""
+    links_assign += "`endif // VELOCE_EMULATION\n"
+
+    for src_chip in sorted(in_connections.keys()):
+        for src_vp in sorted(in_connections[src_chip].keys()):
+            # Output vertical links are not assigned
+            if in_connections[src_chip][src_vp] == 0:
+                unconnected_err += f"""\
+{TAB}{TAB}if (CLUSTER_{src_chip}_inter_cluster_chan_out[{src_vp}].flit_chanel.flit_wr) begin
+{TAB}{TAB}{TAB}`ERROR_UNCNT(\"{src_chip}\",{src_vp})
+{TAB}{TAB}end
+"""
+
+    grounded_signals = ""
+    for dst_chip in sorted(out_connections.keys()):
+        grounded_signals += f"{TAB}smartflit_chanel_t is_grounded_{dst_chip} = {{SMARTFLIT_CHANEL_w{{1'b0}}}};\n"
+
+    return (links_assign, noc_adapters, unconnected_err, grounded_signals)
+
+
+def gen_noc_localparam():
+    rtl = ""
+
+    # Generate both Buffer Depth and Payload Size Selection
+    #
+    # The goal is to generate a Verilog-string like this:
+    # (NOC_CHIP_ID == 0) ?
+    #   (NOC_ID == "N1") ? `PITON_CHIPA_NOC1_BUFFER_SIZE :
+    #   (NOC_ID == "N2") ? `PITON_CHIPA_NOC2_BUFFER_SIZE :
+    #                      `PITON_CHIPA_NOC3_BUFFER_SIZE
+    # : (NOC_CHIP_ID == 1) ?
+    #   (NOC_ID == "N1") ? `PITON_CHIPB_NOC1_BUFFER_SIZE :
+    #   (NOC_ID == "N2") ? `PITON_CHIPB_NOC2_BUFFER_SIZE :
+    #                      `PITON_CHIPA_NOC3_BUFFER_SIZE
+    # : (NOC_CHIP_ID == 2) ?
+    # ...
+    # so the NoC select the appropriate buffer depth (B) and payload size
+    # (Fpay)
+
+    template_buffer_sel = \
+        '(NOC_ID == "N1") ? `PITON__CHIP__NOC1_BUFFER_SIZE : ' + \
+        '(NOC_ID == "N2") ? `PITON__CHIP__NOC2_BUFFER_SIZE : ' + \
+                           '`PITON__CHIP__NOC3_BUFFER_SIZE'
+
+    template_width_sel = \
+        '(NOC_ID == "N1") ? `PITON__CHIP__NOC1_WIDTH : ' + \
+        '(NOC_ID == "N2") ? `PITON__CHIP__NOC2_WIDTH : ' + \
+                           '`PITON__CHIP__NOC3_WIDTH'
+
+    buffer_sel = ""
+    width_sel  = ""
+    noc1_buffer_depths = []
+    noc2_buffer_depths = []
+    noc3_buffer_depths = []
+    nb_routers = 0
+    min_vc = None
+    max_vc = None
+
+    for i, (chip_name, chip_info) in enumerate(chip_infos.items()):
+        CHIPID = chip_info._chipid
+        CHIPNAME = chip_name.upper()
+
+        # Not the last chip
+        if i < len(chip_infos.items()) - 1:
+            buffer_sel += f"(NOC_CHIP_ID == {CHIPID}) ? "
+            width_sel  += f"(NOC_CHIP_ID == {CHIPID}) ? "
+
+        buffer_sel += template_buffer_sel.replace("_CHIP_", CHIPNAME)
+        width_sel  += template_width_sel.replace("_CHIP_", CHIPNAME)
+
+        if i < len(chip_infos.items()) - 1:
+            buffer_sel += " : "
+            width_sel  += " : "
+
+        noc1_buffer_depths.append(chip_info.retrieve_noc_buffers_depth()[0])
+        noc2_buffer_depths.append(chip_info.retrieve_noc_buffers_depth()[1])
+        noc3_buffer_depths.append(chip_info.retrieve_noc_buffers_depth()[2])
+
+        nb_routers += chip_info.get_number_of_routers()
+
+        min_vc = chip_info._nb_virtual_channels if min_vc is None else \
+                  min(min_vc, chip_info._nb_virtual_channels)
+        max_vc = chip_info._nb_virtual_channels if max_vc is None else \
+                  max(max_vc, chip_info._nb_virtual_channels)
+
+    # Use ProNoC's LB parameter as the maximal buffer value in the 3.5D
+    # topology for a given physical NoC.
+    # Compute the maximal buffer depth across all chips for any NoC channel.
+    # This is used to compute the width of both the credit and credit
+    # initialization channels, for the whole system.
+    LB = \
+        f'(NOC_ID == "N1") ? {max(noc1_buffer_depths)} : ' + \
+        f'(NOC_ID == "N2") ? {max(noc2_buffer_depths)} : ' + \
+                           f'{max(noc3_buffer_depths)}'
+
+    # Name of the ProNoC multi-chip topology
+    # This topology supports multiple clusters of 2D-meshes, interconnected
+    # vertically
+    topology = "MULTI_MESH"
+
+    # Dictionary representing the main noc_localparam attributes
+    param_attribs = {
+        'TOPOLOGY': f'"{topology}"',
+        'T1': nb_routers,
+        'T3': 1,
+        'T4': 1,
+        'V' : 2,
+        'ROUTE_MODE': '\"CONVENTIONAL\"',
+        'B': "PRESEL_B",
+        'LB': "PRESEL_LB",
+        'Fpay': "PRESEL_Fpay",
+        'ROUTE_NAME': '\"DEPTH_FIRST\"',
+        'PCK_TYPE': '\"MULTI_FLIT\"',
+        'MIN_PCK_SIZE': 1,
+        'BYTE_EN': 0,
+        'SSA_EN': '\"NO\"',
+        "SMART_MAX": 0,
+        "CONGESTION_INDEX": 3,
+        "ESCAP_VC_MASK": "2'b01",
+        "VC_REALLOCATION_TYPE": '\"NONATOMIC\"',
+        "COMBINATION_TYPE": '\"COMB_NONSPEC\"',
+        "MUX_TYPE": '\"BINARY\"',
+        "C": 0,
+        "CLASS_SETTING": "{V{1'b1}}",
+        "DEBUG_EN": 1,
+        "ADD_PIPREG_AFTER_CROSSBAR": "1'b0",
+        "FIRST_ARBITER_EXT_P_EN": 1,
+        "SWA_ARBITER_TYPE": '\"RRA\"',
+        "WEIGHTw": 4,
+        'SELF_LOOP_EN': 1,
+        "AVC_ATOMIC_EN": 0,
+        "MAX_PCK_NUM": 1000000000,
+        "MAX_PCK_SIZ": 16383,
+        "MAX_SIM_CLKs": 1000000000,
+        "TIMSTMP_FIFO_NUM": 16,
+        "CVw": "(C==0)? V : C * V",
+        "CAST_TYPE": '\"UNICAST\"',
+        "MCAST_ENDP_LIST": "'b1111"
+    }
+
+    param_attribs['MAX_ROUTER'] = nb_routers
+    param_attribs['MAX_PORT'] = MAX_PORT
+
+    hetero_vc_enabled = min_vc != max_vc or max_vc < 2
+    param_attribs['HETERO_VC'] = int(hetero_vc_enabled)
+    hetero_vc = f"""'{{
+{TAB}{TAB}// VC chip local_id global_id
+"""
+    for chip_name, chip_info in chip_infos.items():
+        nr = chip_info.get_number_of_routers()
+        rid_int = chip_info._chip_offset_id
+        r = 0
+        v = chip_info._nb_virtual_channels
+        for n in range(rid_int, rid_int + nr):
+            ports = range(int(param_attribs['MAX_PORT']))
+            hetero_vc += f"{TAB}{TAB}// {chip_name}: r{r} R{n}\n"
+            hetero_vc += TAB*2 + "'{"
+            for port in ports:
+                if hetero_vc_enabled:
+                    hetero_vc += str(v)
+                else:
+                    hetero_vc += "0"
+                if port != ports[-1]:
+                    hetero_vc += ", "
+            if n < nb_routers-1:
+                hetero_vc += "},\n"
+            else:
+                hetero_vc += "}\n"
+            r += 1
+    hetero_vc += f"{TAB}}}"
+    param_attribs['int VC_CONFIG_TABLE[MAX_ROUTER][MAX_PORT]'] = hetero_vc
+
+    rtl +=f"""
+`ifdef NOC_LOCAL_PARAM
+
+{TAB}/*************************************
+{TAB}*   ProNoC localparams
+{TAB}*************************************/
+
+{TAB}// NOTE: values modified automatically by phy_noc.pl
+{TAB}localparam NOC_ID = 0;
+{TAB}localparam NOC_CHIP_ID = 0;
+
+`ifdef PITON_PRONOC
+{TAB}// OpenPiton header
+{TAB}`include "define.tmp.h"
+
+{TAB}localparam PRESEL_B = {buffer_sel};
+{TAB}localparam PRESEL_LB = {LB};
+{TAB}localparam PRESEL_Fpay = {width_sel};
+`else
+{TAB}// ProNoC Standalone settings
+{TAB}localparam PRESEL_B = 4;
+{TAB}localparam PRESEL_LB = 4;
+{TAB}localparam PRESEL_Fpay = 64;
+`endif // PITON_PRONOC
+"""
+    # Generate the list of localparam attributes
+    for p in param_attribs.keys():
+        rtl += f"{TAB}localparam {p} = {param_attribs[p]};\n"
+
+    lines = []
+    MAX_CHIP_X = 0
+    MAX_CHIP_Y = 0
+    MAX_CHIP_Z = 0
+    for chip_name, chip_info in chip_infos.items():
+        lines.append(f"{TAB}{TAB}{chip_name.upper()}_ID = {chip_info._chipid},\n")
+        MAX_CHIP_X = max(MAX_CHIP_X, chip_info._dim_x)
+        MAX_CHIP_Y = max(MAX_CHIP_Y, chip_info._dim_y)
+        MAX_CHIP_Z = max(MAX_CHIP_Z, chip_info._dim_z)
+
+    rtl += f"""
+{TAB}/*************************************
+{TAB}*   multimesh localparams
+{TAB}*************************************/
+{TAB}localparam
+{"".join(lines)}
+{TAB}{TAB}MAX_RID = T1,
+{TAB}{TAB}RIDw = $clog2(MAX_RID),
+{TAB}{TAB}CLUSTER_NUM = {len(chip_infos.items())},
+{TAB}{TAB}CLUSTER_IDw = (CLUSTER_NUM == 1) ? 1 : $clog2(CLUSTER_NUM),
+{TAB}{TAB}CLUSTER_MAX_X = {str(MAX_CHIP_X)},
+{TAB}{TAB}CLUSTER_Xw = (CLUSTER_MAX_X == 1)? 1 : $clog2(CLUSTER_MAX_X),
+{TAB}{TAB}CLUSTER_MAX_Y = {str(MAX_CHIP_Y)},
+{TAB}{TAB}CLUSTER_Yw = (CLUSTER_MAX_Y == 1)? 1 : $clog2(CLUSTER_MAX_Y),
+{TAB}{TAB}CLUSTER_MAX_Z = {str(MAX_CHIP_Z)},
+{TAB}{TAB}CLUSTER_Zw = (CLUSTER_MAX_Z == 1)? 1 : $clog2(CLUSTER_MAX_Z);
+
+{TAB}typedef struct packed {{
+{TAB}{TAB}logic [CLUSTER_IDw-1:0] c;
+{TAB}{TAB}logic [CLUSTER_Zw-1 :0] z;
+{TAB}{TAB}logic [CLUSTER_Yw-1 :0] y;
+{TAB}{TAB}logic [CLUSTER_Xw-1 :0] x;
+{TAB}}} multimesh_router_addr_t;
+{TAB}localparam T2 = $bits(multimesh_router_addr_t);
+"""
+    return rtl
+
+
+def gen_multi_mesh_topology_rtl(rtl_cluster_instant, rtl_io_assign,
+                                rtl_vertical_links_assign, v_err,
+                                grounded_signals):
+    return f"""
+`include "pronoc_def.v"
+
+module multi_mesh
+{TAB}import pronoc_pkg::*;
+(
+{TAB}input  logic clk,
+{TAB}input  logic reset,
+{TAB}input  smartflit_chanel_t chan_in_all[NE-1:0],
+{TAB}output smartflit_chanel_t chan_out_all[NE-1:0],
+{TAB}output router_event_t router_event[NR-1:0][MAX_P-1:0]
+);
+
+{TAB}// Unused Input channels are connected to ground
+{grounded_signals}
+{rtl_cluster_instant}
+
+{TAB}// Chiplet interconnect
+{TAB}always_comb begin
+{rtl_io_assign}
+{rtl_vertical_links_assign}
+{TAB}end
+
+`define ERROR_UNCNT(cluster, port) \\
+{TAB}$display("Error: A flit was injected into an unconnected NoC router port."); \\
+{TAB}$display("Cluster: %s, Port: %0d", cluster, port); \\
+{TAB}$display("Simulation will terminate due to this unexpected behavior."); \\
+{TAB}$finish;
+
+`ifdef SIMULATION
+{TAB}always @(posedge clk) begin
+{v_err}
+{TAB}end
+`endif
+
+endmodule
+"""
+
+
+def create_routing_modules():
+    rtl = multimesh_address_encoder()
+    rtl += multimesh_address_decoder()
+    return rtl
+
+
+def multimesh_address_decoder():
+    lines = ""
+    for chip_name, _ in chip_infos.items():
+        CHIP = chip_name.upper()
+        lines += f"""
+{TAB}{TAB}for (int z=0; z<CLUSTER_{CHIP}_NZ; z=z+1) begin: {CHIP}Z_
+{TAB}{TAB}{TAB}for (int y=0; y<CLUSTER_{CHIP}_NY; y=y+1) begin: {CHIP}Y_
+{TAB}{TAB}{TAB}{TAB}for (int x=0; x<CLUSTER_{CHIP}_NX; x=x+1) begin: {CHIP}X_
+{TAB}{TAB}{TAB}{TAB}{TAB}multimesh_router_addr_t CODED;
+{TAB}{TAB}{TAB}{TAB}{TAB}CODED.x = x;
+{TAB}{TAB}{TAB}{TAB}{TAB}CODED.y = y;
+{TAB}{TAB}{TAB}{TAB}{TAB}CODED.z = z;
+{TAB}{TAB}{TAB}{TAB}{TAB}CODED.c = {CHIP}_ID;
+{TAB}{TAB}{TAB}{TAB}{TAB}addr_table[CODED] = (z * (CLUSTER_{CHIP}_NY * CLUSTER_{CHIP}_NY) + (y * CLUSTER_{CHIP}_NX) + x) + CLUSTER_{CHIP}_RID_INIT;
+{TAB}{TAB}{TAB}{TAB}end
+{TAB}{TAB}{TAB}end
+{TAB}{TAB}end
+"""
+
+    return f"""
+module multimesh_address_decoder
+{TAB}import pronoc_pkg::*;
+(
+{TAB}output [RIDw-1:0] rid_out,
+{TAB}input multimesh_router_addr_t addr_st_i
+);
+
+{TAB}localparam BITS = $bits(multimesh_router_addr_t);
+{TAB}logic [RIDw-1:0] addr_table[2**BITS-1:0];
+{TAB}always_comb begin
+{lines}
+{TAB}end
+{TAB}assign rid_out = addr_table[addr_st_i];
+endmodule
+"""
+
+
+def multimesh_address_encoder():
+    lines = ""
+    for chip_name, _ in chip_infos.items():
+        CHIP = chip_name.upper()
+        lines += f"""
+{TAB}{TAB}for (z = 0; z < CLUSTER_{CHIP}_NZ; z = z + 1) begin: {CHIP}Z_
+{TAB}{TAB}{TAB}for (y = 0; y < CLUSTER_{CHIP}_NY; y = y + 1) begin: {CHIP}Y_
+{TAB}{TAB}{TAB}{TAB}for (x = 0; x < CLUSTER_{CHIP}_NX; x = x + 1) begin: {CHIP}X_
+{TAB}{TAB}{TAB}{TAB}{TAB}localparam RID = (z * (CLUSTER_{CHIP}_NY * CLUSTER_{CHIP}_NY) + (y * CLUSTER_{CHIP}_NX) + x) + CLUSTER_{CHIP}_RID_INIT;
+{TAB}{TAB}{TAB}{TAB}{TAB}assign addr_table[RID].x = x;
+{TAB}{TAB}{TAB}{TAB}{TAB}assign addr_table[RID].y = y;
+{TAB}{TAB}{TAB}{TAB}{TAB}assign addr_table[RID].z = z;
+{TAB}{TAB}{TAB}{TAB}{TAB}assign addr_table[RID].c = {CHIP}_ID;
+{TAB}{TAB}{TAB}{TAB}end
+{TAB}{TAB}{TAB}end
+{TAB}{TAB}end
+"""
+
+    return f"""
+`include "pronoc_def.v"
+
+module multimesh_address_encoder
+{TAB}import pronoc_pkg::*;
+(
+{TAB}input  logic [RIDw-1:0] rid_in,
+{TAB}output multimesh_router_addr_t addr_st_o
+);
+
+{TAB}multimesh_router_addr_t addr_table[MAX_RID];
+{TAB}genvar x,y,z;
+{TAB}generate
+{lines}
+{TAB}endgenerate
+
+{TAB}assign addr_st_o = addr_table[rid_in];
+endmodule
+"""
+
+
+def create_inter_cluster_routing():
+    not_dynamic = ""
+    static_icr_modules = ""
+    cond_statement = "if"
+
+    for chip_name, chip_info in chip_infos.items():
+        CHIP = chip_name.upper()
+        not_dynamic += f"""\
+    {cond_statement} (CLUSTER_ID == {CHIP}_ID) begin
+{TAB}{TAB}hard_coded_icr_{chip_name} #(
+{TAB}{TAB}{TAB}.CLUSTER_ID(CLUSTER_ID),
+{TAB}{TAB}{TAB}.RID(RID)
+{TAB}{TAB}) icr_comb(
+{TAB}{TAB}{TAB}.dest_address(dest_address),
+{TAB}{TAB}{TAB}.local_cluster_endp_addr(local_cluster_endp_addr),
+{TAB}{TAB}{TAB}.up_dir_sel(up_dir_sel)
+{TAB}{TAB});
+"""
+        cond_statement = "else if"
+        static_icr_modules += f"""
+module hard_coded_icr_{chip_name}
+{TAB}import pronoc_pkg::*;
+#(
+{TAB}parameter CLUSTER_ID = 0,
+{TAB}parameter RID = 0
+)(
+{TAB}input multimesh_router_addr_t dest_address,
+{TAB}output multimesh_router_addr_t local_cluster_endp_addr,
+{TAB}output logic up_dir_sel
+);
+
+{TAB}localparam unsigned [CLUSTER_IDw-1:0] current_cluster_id = CLUSTER_ID;
+{TAB}typedef struct packed {{
+{TAB}{TAB}logic [CLUSTER_IDw-1:0] Cmin, Cmax;
+{TAB}{TAB}multimesh_router_addr_t endp_addr;
+{TAB}{TAB}bit valid;
+{TAB}}} cluster_hid_entry_t;
+{TAB}multimesh_router_addr_t
+{TAB}{TAB}local_cluster_endp_addr_up_dir,
+{TAB}{TAB}local_cluster_endp_addr_down_dir;
+"""
+        no_down_chip = int(not chip_info.has_down_chip())
+        static_icr_modules += f"{TAB}localparam NO_DOWNLINK = {no_down_chip};\n"
+
+        up_clusters = chip_info._chipid_up_to_destchip.keys()
+        if len(up_clusters) > 0:
+            static_icr_modules += f"{TAB}localparam MAX_ENTRY_{CHIP} = {len(up_clusters)};\n"
+            static_icr_modules += f"{TAB}cluster_hid_entry_t address_table[MAX_ENTRY_{CHIP}];\n"
+            static_icr_modules += f"{TAB}multimesh_router_addr_t endp_addr_array[MAX_ENTRY_{CHIP}];\n"
+            static_icr_modules += f"{TAB}wire [CLUSTER_IDw-1:0] Cmax_array_{chip_name}[MAX_ENTRY_{CHIP}];\n"
+            static_icr_modules += f"{TAB}wire [CLUSTER_IDw-1:0] Cmin_array_{chip_name}[MAX_ENTRY_{CHIP}];\n"
+            i = 0
+            for c_min_id, c_max_id in up_clusters:
+                static_icr_modules += f"{TAB}assign Cmax_array_{chip_name}[{i}] = {c_max_id};\n"
+                static_icr_modules += f"{TAB}assign Cmin_array_{chip_name}[{i}] = {c_min_id};\n"
+                i += 1
+        else:
+            static_icr_modules += f"{TAB}{TAB}// There are no upper chiplet. Select between local and down chiplet\n"
+        static_icr_modules += f"{TAB}generate \n{TAB}{TAB}case (RID)\n"
+
+        for rid in range(chip_info.get_number_of_routers()):
+            static_icr_modules += f"{TAB}{TAB}{rid}: begin\n"
+            i = 0
+            for (_, _), upper_chip in chip_info._chipid_up_to_destchip.items():
+                ldest = chip_info._destchip_up_to_ldst[upper_chip, rid]
+                x, y, z = convert_local_id_to_xyz(chip_info, ldest)
+                static_icr_modules += f"{TAB}{TAB}{TAB}/* T:{upper_chip}, R:{ldest} */\n"
+                static_icr_modules += f"{TAB}{TAB}{TAB}assign endp_addr_array[{i}] = '{{x:{x}, y:{y}, z:{z}, c:{CHIP}_ID}};\n"
+                i += 1
+            if not no_down_chip:
+                ldest = chip_info._destchip_down_to_ldst[rid]
+                x, y, z = convert_local_id_to_xyz(chip_info, ldest)
+                down_cluster = chip_info._destchip_down
+                static_icr_modules += f"{TAB}{TAB}{TAB}/* T:{down_cluster}, R:{ldest} */\n"
+                static_icr_modules += f"{TAB}{TAB}{TAB}assign local_cluster_endp_addr_down_dir = '{{x:{x}, y:{y}, z:{z}, c:{CHIP}_ID}};\n"
+            static_icr_modules += f"{TAB}{TAB}end //{rid}\n"
+        static_icr_modules += f"{TAB}{TAB}endcase\n{TAB}endgenerate\n"
+
+        if len(up_clusters) > 0:
+            static_icr_modules += f"""
+{TAB}always_comb begin
+{TAB}{TAB}local_cluster_endp_addr_up_dir = 0;
+{TAB}{TAB}up_dir_sel = 1'b0;
+{TAB}{TAB}for (int i = 0; i < MAX_ENTRY_{CHIP}; i++) begin
+{TAB}{TAB}{TAB}if (Cmin_array_{chip_name}[i] <= dest_address.c &&
+{TAB}{TAB}{TAB}    dest_address.c <= Cmax_array_{chip_name}[i]) begin
+{TAB}{TAB}{TAB}{TAB}local_cluster_endp_addr_up_dir = endp_addr_array[i];
+{TAB}{TAB}{TAB}{TAB}up_dir_sel = 1'b1;
+{TAB}{TAB}{TAB}end
+{TAB}{TAB}end
+{TAB}end
+"""
+        else:
+            static_icr_modules += f"""
+{TAB}always_comb begin
+{TAB}{TAB}local_cluster_endp_addr_up_dir = 0;
+{TAB}{TAB}up_dir_sel = 1'b0;
+{TAB}end
+"""
+        not_dynamic += f"{TAB}end\n"
+        static_icr_modules += f"""
+{TAB}assign local_cluster_endp_addr =
+{TAB}{TAB}(dest_address.c == current_cluster_id) ? dest_address :
+{TAB}{TAB}(up_dir_sel) ? local_cluster_endp_addr_up_dir :
+{TAB}{TAB}local_cluster_endp_addr_down_dir;
+endmodule
+"""
+    rtl = f"""
+`include "pronoc_def.v"
+module global_id_to_local_cluster_endp
+{TAB}import pronoc_pkg::*;
+#(
+`ifndef DYNAMIC_CLUSTER_INIT
+{TAB}parameter CLUSTER_ID = 0,
+{TAB}parameter RID = 0
+`endif
+)(
+`ifdef DYNAMIC_CLUSTER_INIT
+{TAB}input  cluster_hid_entry_t     address_table[DYN_ICRT_MAX_ENTRY],
+{TAB}input  multimesh_router_addr_t local_cluster_endp_addr_down_dir,
+{TAB}input  logic [CLUSTER_IDw-1:0] current_cluster_id,
+`endif
+{TAB}input  multimesh_router_addr_t dest_address,
+{TAB}output multimesh_router_addr_t local_cluster_endp_addr,
+{TAB}output logic up_dir_sel
+);
+
+`ifndef DYNAMIC_CLUSTER_INIT
+{TAB}generate
+{not_dynamic}
+{TAB}endgenerate
+`else
+{TAB}dynamic_icr icr(
+{TAB}{TAB}.dest_address(dest_address),
+{TAB}{TAB}.local_cluster_endp_addr(local_cluster_endp_addr),
+{TAB}{TAB}.local_cluster_endp_addr_down_dir(local_cluster_endp_addr_down_dir),
+{TAB}{TAB}.current_cluster_id(current_cluster_id),
+{TAB}{TAB}.address_table(address_table),
+{TAB}{TAB}.up_dir_sel(up_dir_sel)
+{TAB});
+`endif
+endmodule
+
+`ifdef DYNAMIC_CLUSTER_INIT
+module dynamic_icr
+{TAB}import pronoc_pkg::*;
+(
+{TAB}input  multimesh_router_addr_t dest_address,
+{TAB}output multimesh_router_addr_t local_cluster_endp_addr,
+{TAB}input  multimesh_router_addr_t local_cluster_endp_addr_down_dir,
+{TAB}input  logic [CLUSTER_IDw-1:0] current_cluster_id,
+{TAB}input  cluster_hid_entry_t     address_table[DYN_ICRT_MAX_ENTRY],
+{TAB}output logic                   up_dir_sel
+);
+
+{TAB}multimesh_router_addr_t local_cluster_endp_addr_up_dir;
+
+{TAB}always_comb begin
+{TAB}{TAB}local_cluster_endp_addr_up_dir = 0;
+{TAB}{TAB}up_dir_sel = 1'b0;
+{TAB}{TAB}for (int i = 0; i < DYN_ICRT_MAX_ENTRY; i++) begin
+{TAB}{TAB}{TAB}if (address_table[i].valid) begin
+{TAB}{TAB}{TAB}{TAB}if (address_table[i].Cmin <= dest_address.c &&
+{TAB}{TAB}{TAB}{TAB}    dest_address.c < address_table[i].Cmax) begin
+{TAB}{TAB}{TAB}{TAB}{TAB}local_cluster_endp_addr_up_dir = address_table[i].endp_addr;
+{TAB}{TAB}{TAB}{TAB}{TAB}up_dir_sel = 1'b1;
+{TAB}{TAB}{TAB}{TAB}end
+{TAB}{TAB}{TAB}end
+{TAB}{TAB}end
+{TAB}end
+
+{TAB}assign local_cluster_endp_addr =
+{TAB}{TAB}(dest_address.c == current_cluster_id) ? dest_address :
+{TAB}{TAB}(up_dir_sel) ? local_cluster_endp_addr_up_dir :
+{TAB}{TAB}local_cluster_endp_addr_down_dir;
+endmodule
+
+module dynamic_hids_per_router
+{TAB}import pronoc_pkg::*;
+(
+{TAB}input  logic clk,
+{TAB}input  logic reset,
+{TAB}output multimesh_router_addr_t local_cluster_endp_addr_down_dir,
+{TAB}output logic [CLUSTER_IDw-1:0] current_cluster_id,
+{TAB}output cluster_hid_entry_t address_table[DYN_ICRT_MAX_ENTRY],
+{TAB}input  program_port_t program_port
+);
+
+{TAB}always_ff @(posedge clk or posedge reset) begin
+{TAB}{TAB}if (reset) begin
+{TAB}{TAB}{TAB}local_cluster_endp_addr_down_dir = 0;
+{TAB}{TAB}{TAB}foreach (address_table[i]) begin
+{TAB}{TAB}{TAB}{TAB}address_table[i].valid <= 1'b0;
+{TAB}{TAB}{TAB}{TAB}current_cluster_id <= 0;
+{TAB}{TAB}{TAB}end
+{TAB}{TAB}end else begin
+{TAB}{TAB}{TAB}if (program_port.data.valid) begin
+{TAB}{TAB}{TAB}{TAB}if (!program_port.down_sel) begin
+{TAB}{TAB}{TAB}{TAB}{TAB}address_table[program_port.addr] <= program_port.data;
+{TAB}{TAB}{TAB}{TAB}{TAB}current_cluster_id <= program_port.current_cluster_id;
+{TAB}{TAB}{TAB}{TAB}end else begin
+{TAB}{TAB}{TAB}{TAB}{TAB}local_cluster_endp_addr_down_dir = program_port.data.endp_addr;
+{TAB}{TAB}{TAB}{TAB}end
+{TAB}{TAB}{TAB}end
+{TAB}{TAB}end
+{TAB}end
+endmodule
+
+`else
+{static_icr_modules}
+`endif
+"""
+    return rtl
diff --git a/mpsoc/script/multimesh/run_test.sh b/mpsoc/script/multimesh/run_test.sh
new file mode 100755
index 0000000..31a3ec8
--- /dev/null
+++ b/mpsoc/script/multimesh/run_test.sh
@@ -0,0 +1,81 @@
+#!/bin/bash
+
+# Enable strict mode
+set -euo pipefail
+
+# Get the script's full and directory path
+SCRPT_FULL_PATH=$(realpath "${BASH_SOURCE[0]}")
+SCRPT_DIR_PATH=$(dirname "$SCRPT_FULL_PATH")
+
+# Define root and work directories
+root=$(realpath "$SCRPT_DIR_PATH/../..")
+work="$root/../mpsoc_work/multi_mesh"
+
+# Generate NoC configuration from YAML
+CONFIG_FILE="$PITON_ROOT/configs/multi_chip/2d5_36cores.yaml"
+
+echo "[INFO] This script generates a MultiMesh NoC using the configuration file: $CONFIG_FILE."
+echo "[INFO] It then runs a Random Uniform traffic test on the generated NoC."
+echo "[INFO] To test a different NoC configuration, modify the CONFIG_FILE variable in this script."
+echo "[INFO] To adjust synthetic traffic settings (e.g., traffic pattern, number of injected packets, packet size, etc ..), modify the parameters in src/sim_param.sv.
+"
+
+echo "work: $work"
+echo "SCRIPT_DIR_PATH: $SCRPT_DIR_PATH"
+
+# Export necessary environment variables
+export WORK_MMESH="$work"
+export SOURCE_DIR="$SCRPT_DIR_PATH/src"
+
+# Ensure required tools exist
+command -v realpath >/dev/null 2>&1 || { echo "Error: realpath is required but not installed." >&2; exit 1; }
+command -v perl >/dev/null 2>&1 || { echo "Error: perl is required but not installed." >&2; exit 1; }
+
+
+# Change to script directory
+cd "$SCRPT_DIR_PATH"
+
+
+if [[ ! -f "$CONFIG_FILE" ]]; then
+    echo "Error: NoC config file not found at $CONFIG_FILE"
+    exit 1
+fi
+
+# NOTE: This generates by default the multi-mesh modules in $root/rtl/src_multi_mesh/build
+python3 $PITON_ROOT/piton/tools/bin/piton_arch.py --filename "$CONFIG_FILE" --gen_sv
+
+# Copy generated parameter file, ensuring the source exists
+SRC_FILE="$root/rtl/src_multi_mesh/build/noc_localparam.v"
+DEST_FILE="$root/rtl/src_noc/noc_localparam.v"
+if [[ -f "$SRC_FILE" ]]; then
+    cp "$SRC_FILE" "$DEST_FILE"
+else
+    echo "Error: Source file $SRC_FILE not found."
+    exit 1
+fi
+
+# Create working directory if it does not exist
+mkdir -p "$work"
+
+# Source QuestaSim environment script
+QUESTA_ENV_SCRIPT="$work/../Questa_20.4.sh"
+if [[ -f "$QUESTA_ENV_SCRIPT" ]]; then
+    source "$QUESTA_ENV_SCRIPT"
+else
+    echo "Warning: QuestaSim environment script not found at $QUESTA_ENV_SCRIPT. Simulation may fail."
+fi
+
+# Move to working directory and run ModelSim script
+cd "$work"
+if [[ ! -f "$SCRPT_DIR_PATH/src/model.tcl" ]]; then
+    echo "Error: ModelSim script not found at $SCRPT_DIR_PATH/src/model.tcl"
+    exit 1
+fi
+
+command -v vsim >/dev/null 2>&1 || { echo "Error: vsim (QuestaSim) is required but not installed." >&2; exit 1; }
+
+vsim -do "$SCRPT_DIR_PATH/src/model.tcl"
+
+# Return to original directory
+cd -
+
diff --git a/mpsoc/script/multimesh/src/file_list.f b/mpsoc/script/multimesh/src/file_list.f
new file mode 100644
index 0000000..0e60bd1
--- /dev/null
+++ b/mpsoc/script/multimesh/src/file_list.f
@@ -0,0 +1,6 @@
++incdir+./
++incdir+./../../../rtl/src_noc/
+-F  ../../../rtl/src_noc/noc_filelist.f
+-F  ../../../rtl/src_multi_mesh/multi_mesh.flist
+-F  ../../../rtl/src_modelsim/filelist.f
+-sv ../../../rtl/src_modelsim/testbench_noc.sv
diff --git a/mpsoc/script/multimesh/src/model.tcl b/mpsoc/script/multimesh/src/model.tcl
new file mode 100644
index 0000000..25f1e97
--- /dev/null
+++ b/mpsoc/script/multimesh/src/model.tcl
@@ -0,0 +1,33 @@
+#!/usr/bin/tclsh
+
+transcript on
+
+if {![info exists env(WORK_MMESH)]} {
+    puts "Error: WORK environment variable is not set."
+    exit 1
+}
+
+if {![info exists env(SOURCE_DIR)]} {
+    puts "Error: SOURCE_DIR environment variable is not set."
+    exit 1
+}
+
+set rtl_work $env(WORK_MMESH)/rtl_work
+set src_dir  $env(SOURCE_DIR)
+
+if {[file exists $rtl_work]} {
+    vdel -lib $rtl_work -all
+}
+vlib $rtl_work
+vmap work $rtl_work
+
+
+vlog +define+SIMULATION+MULTI_MESH_ASSERTIONS +acc=rn -F $src_dir/file_list.f
+
+vsim -t 1ps  -L $rtl_work -L work -voptargs="+acc"  testbench_noc
+
+add wave *
+view structure
+view signals
+run -all
+quit
diff --git a/mpsoc/script/multimesh/src/sim_param.sv b/mpsoc/script/multimesh/src/sim_param.sv
new file mode 100644
index 0000000..92a5673
--- /dev/null
+++ b/mpsoc/script/multimesh/src/sim_param.sv
@@ -0,0 +1,34 @@
+
+// simulation parameter setting
+
+`ifdef INCLUDE_SIM_PARAM
+    localparam
+        TRAFFIC="RANDOM", // "NEIGHBOR", "BIT_COMPLEMENT", "TRANSPOSE2", "RANDOM", "CUSTOM", "HOTSPOT"
+        PCK_SIZ_SEL="random-range",
+        AVG_LATENCY_METRIC= "HEAD_2_TAIL",
+        // Simulation min/max packet size
+        // NOTE: The injected packet take a size randomly selected between min and max values
+        MIN_PACKET_SIZE=5,
+        MAX_PACKET_SIZE=5,
+        STOP_PCK_NUM=2000, // simulation stops when #STOP_PCK_NUM packets are injected in the NoC
+        STOP_SIM_CLK=1000; // simulation stops when #STOP_SIM_CLK cycles are passed
+
+    // parameters for setting hotspot traffic pattern
+    localparam HOTSPOT_NODE_NUM = 0;
+    hotspot_t hotspot_info [0:0];
+
+    // parameters for setting point-to-point custom traffic pattern
+    localparam CUSTOM_NODE_NUM = 0;
+    wire [NEw-1:0] custom_traffic_t[NE-1:0];
+    wire [NE-1:0]  custom_traffic_en;
+
+    localparam MCAST_TRAFFIC_RATIO = 0;
+    localparam MCAST_PCK_SIZ_MAX   = 0;
+    localparam MCAST_PCK_SIZ_MIN   = 0;
+
+    localparam DISCRETE_PCK_SIZ_NUM = 1;
+    rnd_discrete_t rnd_discrete [DISCRETE_PCK_SIZ_NUM-1:0];
+
+    // flit injection ratio in %
+    parameter INJRATIO=50;
+`endif
diff --git a/mpsoc/script/noc_yml_gen/gen_mesh_yaml.pl b/mpsoc/script/noc_yml_gen/gen_mesh_yaml.pl
new file mode 100644
index 0000000..490d111
--- /dev/null
+++ b/mpsoc/script/noc_yml_gen/gen_mesh_yaml.pl
@@ -0,0 +1,95 @@
+#!/usr/bin/perl
+use strict;
+use warnings;
+use YAML::PP;
+use YAML::PP::Common qw/ PRESERVE_ORDER PRESERVE_FLOW_STYLE YAML_FLOW_SEQUENCE_STYLE YAML_FLOW_MAPPING_STYLE /;
+
+my $yp = YAML::PP->new(
+    preserve => PRESERVE_ORDER,    # preserve mapping order when dumping
+);
+
+# Usage:
+#   ./gen_mesh_yaml.pl <xdim> <ydim> <endpoints_per_node>
+my ($xdim, $ydim, $eps_per_node) = @ARGV;
+die "Usage: $0 <xdim> <ydim> <endpoints_per_node>\n"
+    unless defined $xdim && defined $ydim && defined $eps_per_node;
+
+my $num_nodes = $xdim * $ydim;
+
+############################################################
+# Helpers: create preserved sequence/map objects
+############################################################
+sub oseq {
+    my ($arr_ref) = @_;
+    # create a preserved sequence object from arrayref
+    return $yp->preserved_sequence([ @$arr_ref ]);
+}
+
+sub omap {
+    my ($hashref) = @_;
+    # create a preserved mapping object and populate keys in insertion order
+    my $pm = $yp->preserved_mapping({});
+    # copy keys in insertion order from provided hashref
+    # NOTE: the passed-in hashref may be a normal hash; we iterate in numeric order where appropriate
+    foreach my $k (keys %$hashref) {
+        $pm->{$k} = $hashref->{$k};
+    }
+    return $pm;
+}
+
+############################################################
+# Generate nodes (id + endpoints) as preserved sequence of preserved maps
+############################################################
+
+my @node_items;
+my $ep_id = 0;
+
+for my $id (0 .. $num_nodes - 1) {
+    my @eps = map { $ep_id++ } 1 .. $eps_per_node;
+
+    # create preserved mapping for this node, and preserved sequence for endpoints
+    my $node_map = $yp->preserved_mapping({});
+    $node_map->{id}        = $id;
+    $node_map->{endpoints} = $yp->preserved_sequence(\@eps);
+
+    push @node_items, $node_map;
+}
+
+my $nodes_seq = $yp->preserved_sequence(\@node_items);
+
+############################################################
+# Generate mesh connections (preserved sequence of preserved maps)
+############################################################
+
+my @conn_items;
+
+for my $y (0 .. $ydim - 1) {
+    for my $x (0 .. $xdim - 1) {
+        my $id = $y * $xdim + $x;
+        my @dest;
+
+        push @dest, $id - 1     if $x > 0;              # left
+        push @dest, $id + 1     if $x < $xdim - 1;      # right
+        push @dest, $id - $xdim if $y > 0;              # up
+        push @dest, $id + $xdim if $y < $ydim - 1;      # down
+
+        my $conn_map = $yp->preserved_mapping({});
+        $conn_map->{source} = $id;
+        $conn_map->{dest}   = $yp->preserved_sequence(\@dest);
+
+        push @conn_items, $conn_map;
+    }
+}
+
+my $conns_seq = $yp->preserved_sequence(\@conn_items);
+
+############################################################
+# Top-level preserved mapping (ordered)
+############################################################
+
+my $top = $yp->preserved_mapping({});
+$top->{nodes}       = $nodes_seq;
+$top->{connections} = $conns_seq;
+
+print $yp->dump($top);
+
diff --git a/mpsoc/script/noc_yml_gen/mesh_4x4.yml b/mpsoc/script/noc_yml_gen/mesh_4x4.yml
new file mode 100644
index 0000000..7c5c0ae
--- /dev/null
+++ b/mpsoc/script/noc_yml_gen/mesh_4x4.yml
@@ -0,0 +1,131 @@
+---
+nodes:
+- id: 0
+  endpoints:
+  - 0
+- id: 1
+  endpoints:
+  - 1
+- id: 2
+  endpoints:
+  - 2
+- id: 3
+  endpoints:
+  - 3
+- id: 4
+  endpoints:
+  - 4
+- id: 5
+  endpoints:
+  - 5
+- id: 6
+  endpoints:
+  - 6
+- id: 7
+  endpoints:
+  - 7
+- id: 8
+  endpoints:
+  - 8
+- id: 9
+  endpoints:
+  - 9
+- id: 10
+  endpoints:
+  - 10
+- id: 11
+  endpoints:
+  - 11
+- id: 12
+  endpoints:
+  - 12
+- id: 13
+  endpoints:
+  - 13
+- id: 14
+  endpoints:
+  - 14
+- id: 15
+  endpoints:
+  - 15
+connections:
+- source: 0
+  dest:
+  - 1
+  - 4
+- source: 1
+  dest:
+  - 0
+  - 2
+  - 5
+- source: 2
+  dest:
+  - 1
+  - 3
+  - 6
+- source: 3
+  dest:
+  - 2
+  - 7
+- source: 4
+  dest:
+  - 5
+  - 0
+  - 8
+- source: 5
+  dest:
+  - 4
+  - 6
+  - 1
+  - 9
+- source: 6
+  dest:
+  - 5
+  - 7
+  - 2
+  - 10
+- source: 7
+  dest:
+  - 6
+  - 3
+  - 11
+- source: 8
+  dest:
+  - 9
+  - 4
+  - 12
+- source: 9
+  dest:
+  - 8
+  - 10
+  - 5
+  - 13
+- source: 10
+  dest:
+  - 9
+  - 11
+  - 6
+  - 14
+- source: 11
+  dest:
+  - 10
+  - 7
+  - 15
+- source: 12
+  dest:
+  - 13
+  - 8
+- source: 13
+  dest:
+  - 12
+  - 14
+  - 9
+- source: 14
+  dest:
+  - 13
+  - 15
+  - 10
+- source: 15
+  dest:
+  - 14
+  - 11
diff --git a/mpsoc/script/parameter.sh b/mpsoc/script/parameter.sh
index 414d85c..98c2e12 100755
--- a/mpsoc/script/parameter.sh
+++ b/mpsoc/script/parameter.sh
@@ -23,14 +23,14 @@ CORE_NUM(){
     COMBINATION_TYPE="COMB_NONSPEC" # "BASELINE" or "COMB_SPEC1" or "COMB_SPEC2" or "COMB_NONSPEC"
     FIRST_ARBITER_EXT_P_EN=0  
     
-    ROUTE_NAME="XY" # Routing algorithm
-    #    mesh :  "XY"        , "WEST_FIRST"      , "NORTH_LAST"      , "NEGETIVE_FIRST"      , "DUATO"
-    #   torus:  "TRANC_XY"  , "TRANC_WEST_FIRST", "TRANC_NORTH_LAST", "TRANC_NEGETIVE_FIRST", "TRANC_DUATO"
+    ROUTE_NAME="DOR" # Routing algorithm
+    #    mesh :  "DOR"        , "WEST_FIRST"      , "NORTH_LAST"      , "NEGETIVE_FIRST"      , "FULL_ADPT"
+    #   torus:  "TRANC_DOR"  , "TRANC_WEST_FIRST", "TRANC_NORTH_LAST", "TRANC_NEGETIVE_FIRST", "TRANC_FULL_ADPT"
     
     
     CLASS_SETTING="{CVw{1'b1}}"   
     
-    SSA_EN="NO"  # "YES","NO"
+    SSA_EN=0  # 1,0
     SWA_ARBITER_TYPE="RRA" # "RRA"  ,"WRRA"
     WEIGHTw=4
     
@@ -41,8 +41,6 @@ CORE_NUM(){
     C1_p=0
     C2_p=0
     C3_p=0
-     
-    
     
  # Simulation parameters: 
     AVG_LATENCY_METRIC="HEAD_2_TAIL"  
@@ -58,15 +56,11 @@ CORE_NUM(){
     HOTSPOT_CORE_4=$(CORE_NUM 3 3)
     HOTSPOT_CORE_5=$(CORE_NUM 2 2)
     
-                 
-    
-    
     MAX_PCK_NUM=128000
     MAX_SIM_CLKs=100000
     MAX_PCK_SIZ=10  # maximum flit number in a single packet
     TIMSTMP_FIFO_NUM=64
     
-   
     
     ESCAP_VC_MASK="1"  # mask escape vc
     DEBUG_EN=1
@@ -76,14 +70,12 @@ CORE_NUM(){
                             # 2: packets are routed to the ports connected to the routers with less active ivc requests
                         # 3: packets are routed to the ports connected to the routers with less active ivc requests that are not granted 
 
-    
-                         
 # Simulation C file constant:  
     PACKET_SIZE=2    # packet size in flit. Minimum is 2
 
 
 # 
-    ROUTE_SUBFUNC="NORTH_LAST"  # "NORTH_LAST" ,"XY"
+    ROUTE_SUBFUNC="NORTH_LAST"  # "NORTH_LAST" ,"DOR"
     AVC_ATOMIC_EN=0
     STND_DEV_EN=0 # 1: generate standard devision  
     
@@ -101,7 +93,7 @@ generate_parameter_v (){
     printf " parameter VC_REALLOCATION_TYPE=\"$VC_REALLOCATION_TYPE\";\n" >> parameter.v    
     printf " parameter COMBINATION_TYPE=\"$COMBINATION_TYPE\";\n" >> parameter.v    
     printf " parameter FIRST_ARBITER_EXT_P_EN=$FIRST_ARBITER_EXT_P_EN;\n" >> parameter.v     
-       
+    
     printf " parameter ROUTE_NAME=\"$ROUTE_NAME\";\n" >> parameter.v    
     printf " parameter CONGESTION_INDEX=$CONGESTION_INDEX;\n" >> parameter.v
     printf " parameter C0_p=$C0_p;\n" >> parameter.v    
@@ -120,8 +112,8 @@ generate_parameter_v (){
     printf " parameter MAX_SIM_CLKs=$MAX_SIM_CLKs;\n" >> parameter.v    
     printf " parameter MAX_PCK_SIZ=$MAX_PCK_SIZ;\n" >> parameter.v    
     printf " parameter TIMSTMP_FIFO_NUM=$TIMSTMP_FIFO_NUM;\n" >> parameter.v    
-    printf " parameter ROUTE_TYPE = (ROUTE_NAME == \"XY\" || ROUTE_NAME == \"TRANC_XY\" )?    \"DETERMINISTIC\" : \n" >> parameter.v    
-    printf "                        (ROUTE_NAME == \"DUATO\" || ROUTE_NAME == \"TRANC_DUATO\" )?   \"FULL_ADAPTIVE\": \"PAR_ADAPTIVE\"; \n" >> parameter.v              
+    printf " parameter ROUTE_TYPE = (ROUTE_NAME == \"DOR\" || ROUTE_NAME == \"TRANC_DOR\" )?    \"DETERMINISTIC\" : \n" >> parameter.v    
+    printf "                        (ROUTE_NAME == \"FULL_ADPT\" || ROUTE_NAME == \"TRANC_FULL_ADPT\" )?   \"FULL_ADAPTIVE\": \"PAR_ADAPTIVE\"; \n" >> parameter.v              
     printf " parameter DEBUG_EN=$DEBUG_EN;\n" >> parameter.v     
     printf " parameter ROUTE_SUBFUNC= \"$ROUTE_SUBFUNC\";\n">> parameter.v     
     printf " parameter AVC_ATOMIC_EN= $AVC_ATOMIC_EN;\n">> parameter.v    
@@ -130,11 +122,10 @@ generate_parameter_v (){
     printf " parameter CVw=(C==0)? V : C * V;\n" >>  parameter.v
     printf " parameter [CVw-1:   0] CLASS_SETTING = $CLASS_SETTING;\n">>  parameter.v 
     printf " parameter [V-1    :    0] ESCAP_VC_MASK=$ESCAP_VC_MASK;\n" >> parameter.v    
-    printf " parameter SSA_EN= \"$SSA_EN\";\n">> parameter.v  
+    printf " parameter SSA_EN= $SSA_EN;\n">> parameter.v  
     printf " parameter SWA_ARBITER_TYPE=\"$SWA_ARBITER_TYPE\";\n">> parameter.v    
-    printf " parameter WEIGHTw=$WEIGHTw;\n">> parameter.v                    
-    printf " \n\n \`endif " >> parameter.v        
-    
+    printf " parameter WEIGHTw=$WEIGHTw;\n">> parameter.v
+    printf " \n\n \`endif " >> parameter.v
     
 }
 
@@ -180,9 +171,8 @@ generate_parameter_h (){
     printf "\t #define    CVw    (C==0)? V : C * V\n" >>  parameter.h
     printf "\t #define    CLASS_SETTING   \"$CLASS_SETTING\"\n">>  parameter.h 
     printf "\t #define    ESCAP_VC_MASK    $ESCAP_VC_MASK\n">>  parameter.h
-    printf "\t #define    SSA_EN \"$SSA_EN\"\n" >> parameter.h 
-    printf "\t #define    SWA_ARBITER_TYPE \"$SWA_ARBITER_TYPE\"\n">> parameter.h    
-    printf "\t #define    WEIGHTw=$WEIGHTw\n">> parameter.h                                            
-    printf " \n\n #endif " >> parameter.h        
-        
+    printf "\t #define    SSA_EN $SSA_EN\n" >> parameter.h 
+    printf "\t #define    SWA_ARBITER_TYPE \"$SWA_ARBITER_TYPE\"\n">> parameter.h 
+    printf "\t #define    WEIGHTw=$WEIGHTw\n">> parameter.h
+    printf " \n\n #endif " >> parameter.h
 }
diff --git a/mpsoc/script/phy_noc_gen/Ambachi_nocs_gen.sh b/mpsoc/script/phy_noc_gen/Ambachi_nocs_gen.sh
new file mode 100644
index 0000000..e8ec66d
--- /dev/null
+++ b/mpsoc/script/phy_noc_gen/Ambachi_nocs_gen.sh
@@ -0,0 +1,49 @@
+#!/bin/bash
+
+# This script generates three physical NoCs for OpenPiton using ProNoC RTL code.
+# Each physical NoC (phynoc) is configured with unified module and parameter names.
+# The NoC number is appended to parameters, functions, and module names to ensure uniqueness.
+
+# Get the full path of the script
+SCRIPT_FULL_PATH=$(realpath "${BASH_SOURCE[0]}")
+SCRIPT_DIR_PATH=$(dirname "$SCRIPT_FULL_PATH")
+
+# OpenPiton target NoC directory
+op_nocs_dir="$SCRIPT_DIR_PATH/../../rtl/src_ambachi"
+
+# ProNoC RTL dir
+pronoc_dir="$SCRIPT_DIR_PATH/../../rtl/src_noc"
+
+# Script to create physical NoCs
+phy_noc_gen="$SCRIPT_DIR_PATH/phy_noc.pl"
+
+cp "$op_nocs_dir/chi_wrapper.sv" "$pronoc_dir/chi_wrapper.sv"
+mv -f "$pronoc_dir/noc_localparam.v" "$pronoc_dir/noc_localparam.v.tmp"
+cp "$op_nocs_dir/noc_localparam.v" "$pronoc_dir/noc_localparam.v"
+
+# Loop to generate three physical NoCs
+IN=""
+LIST=""
+arr=("dat" "rsp" "snp" "req")
+
+for i in "${arr[@]}"; do
+    mkdir -p "$op_nocs_dir/nocs/noc_$i"
+    perl "$phy_noc_gen" "$i" "$op_nocs_dir/nocs/noc_$i"
+    IN+="+incdir+./noc_${i}\n"
+    LIST+="-F ./noc_${i}/noc_filelist_${i}.f\n"
+    LIST+="./noc_${i}/chi_wrapper_${i}.sv\n"
+    #remove common files from noc_filelist_${i}.f
+    sed -i '/arbiter.v/d' "$op_nocs_dir/nocs/noc_$i/noc_filelist_${i}.f"
+    sed -i '/main_comp.v/d' "$op_nocs_dir/nocs/noc_$i/noc_filelist_${i}.f"
+done
+
+# Add common files to the file list
+LIST+="./arbiter.v\n"
+LIST+="./main_comp.v\n"
+
+# Clean up and restore the original file
+rm "$pronoc_dir/chi_wrapper.sv"
+mv "$pronoc_dir/noc_localparam.v.tmp" "$pronoc_dir/noc_localparam.v"
+
+# Generate the file list for physical NoCs
+printf "${IN}$LIST" > "$op_nocs_dir/nocs/Flist.pronoc"
diff --git a/mpsoc/script/phy_noc_gen/OpenPiton_nocs_gen.sh b/mpsoc/script/phy_noc_gen/OpenPiton_nocs_gen.sh
old mode 100644
new mode 100755
index 81548ed..4b4b0dc
--- a/mpsoc/script/phy_noc_gen/OpenPiton_nocs_gen.sh
+++ b/mpsoc/script/phy_noc_gen/OpenPiton_nocs_gen.sh
@@ -1,8 +1,11 @@
 #!/bin/bash
 
 # This script generates three physical NoCs for OpenPiton using ProNoC RTL code.
+# Depending on the arguments given, the script will either use the Fmesh or the
+# Multi-mesh topology.
 # Each physical NoC (phynoc) is configured with unified module and parameter names.
-# The NoC number is appended to parameters, functions, and module names to ensure uniqueness.
+# The NoC number and the chip name are appended to parameters, functions, and
+# module names to ensure uniqueness.
 
 # Get the full path of the script
 SCRIPT_FULL_PATH=$(realpath "${BASH_SOURCE[0]}")
@@ -10,6 +13,8 @@ SCRIPT_DIR_PATH=$(dirname "$SCRIPT_FULL_PATH")
 
 # OpenPiton target NoC directory
 op_nocs_dir="$SCRIPT_DIR_PATH/../../rtl/src_openpiton"
+multimesh_nocs_dir="$SCRIPT_DIR_PATH/../../rtl/src_multi_mesh"
+build_multimesh_nocs_dir="$SCRIPT_DIR_PATH/../../rtl/src_multi_mesh/build"
 
 # ProNoC RTL dir
 pronoc_dir="$SCRIPT_DIR_PATH/../../rtl/src_noc"
@@ -17,24 +22,127 @@ pronoc_dir="$SCRIPT_DIR_PATH/../../rtl/src_noc"
 # Script to create physical NoCs
 phy_noc_gen="$SCRIPT_DIR_PATH/phy_noc.pl"
 
-cp "$op_nocs_dir/wrapper.sv" "$pronoc_dir/wrapper.sv"
-mv "$pronoc_dir/noc_localparam.v" "$pronoc_dir/noc_localparam.v.tmp"
-cp "$op_nocs_dir/noc_localparam.v" "$pronoc_dir/noc_localparam.v"
+# Build directory
+phy_nocs_out_dir="$op_nocs_dir/nocs"
+
+# Depth-First NoC Config File
+dp_config_file=""
+
+# Optional path pointing on an intermediate ProNoC source directory
+intermediate_pronoc_dir="$pronoc_dir"
+
+# Parse script options
+while [[ $# -gt 0 ]]; do
+    case "$1" in
+        --custom_phy_nocs_out_dir)
+            phy_nocs_out_dir="$2"
+            shift 2
+            ;;
+        --config-file)
+            dp_config_file="$2"
+            shift 2
+            ;;
+        --intermediate-dir)
+            intermediate_pronoc_dir="$2"
+            build_multimesh_nocs_dir="$intermediate_pronoc_dir/../src_multi_mesh/build"
+            shift 2
+            ;;
+        *)
+            echo "Invalid Option: $1" >&2
+            exit 1
+            ;;
+    esac
+done
+
+# Check if intermediate_pronoc_dir and pronoc_dir points to different paths
+# If that is the case, copy all necessary files to compile the design in this
+# intermediate directory
+if [ ! "$intermediate_pronoc_dir" -ef "$pronoc_dir" ]; then
+    mkdir -p "$intermediate_pronoc_dir"
+    cp -r "$pronoc_dir/"* "$intermediate_pronoc_dir"
+    cp "$pronoc_dir/../pronoc_def.v" "$intermediate_pronoc_dir/../"
+    cp "$pronoc_dir/../arbiter.v"    "$intermediate_pronoc_dir/../"
+    cp "$pronoc_dir/../main_comp.v"  "$intermediate_pronoc_dir/../"
+fi
+
+# If Multi-mesh is used, launch the generation of the sources
+if [ -n "$dp_config_file" ]; then
+    python3 $PITON_ROOT/piton/tools/bin/piton_arch.py --filename "$dp_config_file" --gen_sv --build_dir "$build_multimesh_nocs_dir"
+    if [ $? -ne 0 ]; then
+        echo "NoC generation from $dp_config_file failed"
+        exit 1
+    fi
+fi
+
+# If Multi-mesh is used, copy the related sources in the main source directory
+if [ -n "$dp_config_file" ]; then
+    cp "$multimesh_nocs_dir/mesh_cluster.sv" "$intermediate_pronoc_dir/mesh_cluster.sv"
+    cp "$build_multimesh_nocs_dir/multi_mesh_icr.sv" "$intermediate_pronoc_dir/multi_mesh_icr.sv"
+    cp "$build_multimesh_nocs_dir/multi_mesh_routing.sv" "$intermediate_pronoc_dir/multi_mesh_routing.sv"
+fi
+
+# If the ProNoC sources are compiled in-place, save the previous noc_localparam file
+if [ "$intermediate_pronoc_dir" -ef "$pronoc_dir" ]; then
+    mv "$pronoc_dir/noc_localparam.v" "$pronoc_dir/noc_localparam.v.tmp"
+fi
+
+# Copy this module, needed for both Fmesh/Multi-mesh wrapper
+cp "$op_nocs_dir/piton_tail_hdr_detect.sv" "$intermediate_pronoc_dir/piton_tail_hdr_detect.sv"
+
+# Copy either the Multi-mesh or the Fmesh wrapper/noc_localparam, depending on the option given
+if [ -n "$dp_config_file" ]; then
+    cp "$multimesh_nocs_dir/piton_wrapper.sv" "$intermediate_pronoc_dir/piton_wrapper.sv"
+    cp "$build_multimesh_nocs_dir/noc_localparam.v" "$intermediate_pronoc_dir/noc_localparam.v"
+else
+    cp "$op_nocs_dir/piton_wrapper.sv" "$intermediate_pronoc_dir/piton_wrapper.sv"
+    cp "$op_nocs_dir/noc_localparam.v" "$intermediate_pronoc_dir/noc_localparam.v"
+fi
+
+# Base values for Fmesh topology
+chips_name=('base')
+chips_id=('0')
+
+if [ -n "$dp_config_file" ]; then
+    # Retrieve the list of chips name and chipid
+    list_chips_name=$(python3 $PITON_ROOT/piton/tools/bin/piton_arch.py --filename "$dp_config_file" --list_chips_name)
+    list_chips_id=$(python3 $PITON_ROOT/piton/tools/bin/piton_arch.py --filename "$dp_config_file" --list_chips_id)
+    # Convert bash strings into arrays
+    read -ra chips_name <<< "$list_chips_name"
+    read -ra chips_id <<< "$list_chips_id"
+fi
 
 # Loop to generate three physical NoCs
 IN=""
 LIST=""
-for i in {1..3}; do
-    mkdir -p "$op_nocs_dir/nocs/noc$i"
-    perl "$phy_noc_gen" "N$i" "$op_nocs_dir/nocs/noc$i"
-    IN+="+incdir+./noc${i}\n"
-    LIST+="-F ./noc${i}/noc_filelist_N${i}.f\n"
-    LIST+="./noc${i}/wrapper_N${i}.sv\n"
+for i in "${!chips_name[@]}"; do
+    chip_name="${chips_name[i]}"
+    chip_id="${chips_id[i]}"
+    for i in {1..3}; do
+        mkdir -p "$phy_nocs_out_dir/${chip_name}/noc$i"
+        perl "$phy_noc_gen" "N${i}" "$phy_nocs_out_dir/$chip_name/noc$i" "$intermediate_pronoc_dir" "${chip_name}" "${chip_id}"
+        IN+="+incdir+./$chip_name/noc${i}\n"
+        LIST+="-F ./$chip_name/noc${i}/noc_filelist_${chip_name}_N${i}.f\n"
+        LIST+="./$chip_name/noc${i}/piton_wrapper_${chip_name}_N${i}.sv\n"
+        LIST+="./$chip_name/noc${i}/piton_tail_hdr_detect_${chip_name}_N${i}.sv\n"
+        if [ -n "$dp_config_file" ]; then
+            LIST+="./$chip_name/noc${i}/mesh_cluster_${chip_name}_N${i}.sv\n"
+            LIST+="./$chip_name/noc${i}/multi_mesh_icr_${chip_name}_N${i}.sv\n"
+            LIST+="./$chip_name/noc${i}/multi_mesh_routing_${chip_name}_N${i}.sv\n"
+        fi
+    done
 done
 
 # Clean up and restore the original file
-rm "$pronoc_dir/wrapper.sv"
-mv "$pronoc_dir/noc_localparam.v.tmp" "$pronoc_dir/noc_localparam.v"
+if [ "$intermediate_pronoc_dir" -ef "$pronoc_dir" ]; then
+    rm "$pronoc_dir/piton_wrapper.sv"
+    rm "$pronoc_dir/piton_tail_hdr_detect.sv"
+    if [ -n "$dp_config_file" ]; then
+        rm "$pronoc_dir/mesh_cluster.sv"
+        rm "$pronoc_dir/multi_mesh_icr.sv"
+        rm "$pronoc_dir/multi_mesh_routing.sv"
+    fi
+    mv "$pronoc_dir/noc_localparam.v.tmp" "$pronoc_dir/noc_localparam.v"
+fi
 
 # Generate the file list for physical NoCs
-printf "${IN}$LIST" > "$op_nocs_dir/nocs/Flist.pronoc"
+printf "${IN}$LIST" > "$phy_nocs_out_dir/Flist.pronoc"
diff --git a/mpsoc/script/phy_noc_gen/phy_noc.pl b/mpsoc/script/phy_noc_gen/phy_noc.pl
index c02f109..f156ff9 100644
--- a/mpsoc/script/phy_noc_gen/phy_noc.pl
+++ b/mpsoc/script/phy_noc_gen/phy_noc.pl
@@ -8,6 +8,9 @@
 #add home dir in perl 5.6
 use FindBin;
 use lib $FindBin::Bin;
+
+use lib "$FindBin::Bin/../../Integration_test/synthetic_sim/src/perl_lib";
+
 use constant::boolean;
 
 
@@ -18,12 +21,14 @@
 use File::Basename;
 use File::Copy;
 
+use Cwd 'realpath';
 my $dirname = dirname(__FILE__);
-my $noc_dir = "$dirname/../../rtl/src_noc";
-
 
 my $noc_id = $ARGV[0];
-my $out_dir= $ARGV[1];
+my $out_dir = $ARGV[1];
+my $noc_dir = $ARGV[2];
+my $chip_name = $ARGV[3];
+my $chip_id = $ARGV[4];
 
 if (!defined $noc_id) {
     print "Error: No NoC_ID is given. You need to give the NoC ID as input. All RTL modules names and parameters are appended with [NOC_ID].
@@ -32,22 +37,31 @@
 }
 $out_dir = "./$noc_id" if(!defined $out_dir);
 
+if (!defined $noc_dir) {
+    $noc_dir = realpath("$dirname/../../rtl/src_noc");
+}
+
+# Build suffix for replacements
+my $suffix = "${noc_id}";
+$suffix = "${chip_name}_" . $suffix if defined $chip_name;
+
 #check that NoC ID is valid verilog syntac
 #Identifiers may contain alphabetic characters, numeric characters, the underscore, and the dollar sign (a-z A-Z 0-9 _ $ )
 if ($noc_id =~ /[^a-zA-Z0-9_\$]+/){
-		 #print "use of illegal character after\n" ;
-		 my @w= split /([^a-zA-Z0-9_\$]+)/, $noc_id; 
-		 die "NOC_ID ($noc_id) contains the illegal character of \"$w[1]\" after $w[0]. Identifiers may contain alphabetic characters, numeric characters, the underscore, and the dollar sign (a-z A-Z 0-9 _ \$ )\n";
+    #print "use of illegal character after\n" ;
+    my @w= split /([^a-zA-Z0-9_\$]+)/, $noc_id; 
+    die "NOC_ID ($noc_id) contains the illegal character of \"$w[1]\" after $w[0]. Identifiers may contain alphabetic characters, numeric characters, the underscore, and the dollar sign (a-z A-Z 0-9 _ \$ )\n";
 
 }
 
 
-my %replace;
-$replace{"`NOC_CONF"} = "import pronoc_pkg_${noc_id}::*;";
-$replace{"noc_localparam.v"} = "noc_localparam_${noc_id}.v";
-$replace{"topology_localparam.v"} = "topology_localparam_${noc_id}.v";
-$replace{"pronoc_pkg"} = "pronoc_pkg_${noc_id}";
-$replace{"NOC_ID=0"} = "NOC_ID=\"$ARGV[0]\"";
+#Note that white spaces in replace keys are autumatically translated to \s*
+my %replace = (
+    'import pronoc_pkg::*;'  => "import pronoc_pkg_${suffix}::*;",
+    'noc_localparam.v'       => "noc_localparam_${suffix}.v",
+    'topology_localparam.v'  => "topology_localparam_${suffix}.v",
+    'pronoc_pkg'             => "pronoc_pkg_${suffix}"
+);
 
 
 
@@ -68,8 +82,6 @@
 @common_file = grep { $_ ne '.' && $_ ne '..' &&  -f "$noc_dir/../$_" } @common_file;
 closedir($dir);
 
-
-
 #get list of all modules
 my @module_names;
 foreach my $file (@files) {
@@ -78,10 +90,10 @@
     # Read the file line by line
     while (my $line = <$fh>) {
         # Match module keyword followed by name until encountering space, #, ;, or (
-         while ($line =~ /^\s*module\s+(\w+)[\s#;\(]/g) {
-          push @module_names, $1;
+        while ($line =~ /^\s*module\s+(\w+)[\s#;\(]/g) {
+            push @module_names, $1;
         }
-    }   
+    }
 }
 
 #get the list of all parameters/localparam 
@@ -99,14 +111,14 @@
     # Remove content within quotes
     $file_content =~ s/"(?:[^"\\]|\\.)*"//g;
     # Find all parameters and localparams
-    while ($file_content =~ /\b(parameter|localparam)\s+(.*?);/sg) {
-        my $declaration = $2;
+    while ($file_content =~ /\b(parameter|localparam)\b\s*(\[[^\]]*\]\s*)?(.*?);/sg) {
+        my $declaration = $3;
         # Split the declaration into individual parameter assignments
         my @params = split /,\s*/, $declaration;
         foreach my $param (@params) {
-            # Extract the parameter name
-            if ($param =~ /^\s*(\w+)/) {
-                push @param_list ,$1;
+            # Extract the parameter name while skipping 'int', 'signed', 'unsigned'
+            if ($param =~ /^\s*(?:int|signed|unsigned)?\s*([a-zA-Z_]\w*)/) {
+                push @param_list, $1;
             }
         }
     }
@@ -125,8 +137,22 @@
     $file_content =~ s/"(?:[^"\\]|\\.)*"//g;
     # Find all structs
     while ($file_content =~ /typedef\s+struct\s+packed\s*{.*?}\s*(\w+)\s*;/sg) {
-     my $struct_name = $1;
-     push @replaces, $struct_name;    
+        my $struct_name = $1;
+        push @replaces, $struct_name;
+    }
+
+    open $fh, '<', "$noc_dir/noc_localparam.v" or die "Cannot open file noc_localparam.v: $!\n";
+    $file_content = do { local $/; <$fh> };
+    close $fh;
+    # Remove single-line and multi-line comments
+    $file_content =~ s{//.*$}{}mg;  # Remove single-line comments
+    $file_content =~ s{/\*.*?\*/}{}sg;  # Remove multi-line comments
+    # Remove content within quotes
+    $file_content =~ s/"(?:[^"\\]|\\.)*"//g;
+    # Find all structs
+    while ($file_content =~ /typedef\s+struct\s+packed\s*{.*?}\s*(\w+)\s*;/sg) {
+        my $struct_name = $1;
+        push @replaces, $struct_name;
     }
 
 
@@ -141,8 +167,8 @@
     $file_content =~ s/"(?:[^"\\]|\\.)*"//g;
     # Find all structs
     while ($file_content =~ /function\s+automatic\s+integer\s+(\w+)\s*;/sg) {
-       my $func = $1;
-       push @replaces, $func;      
+        my $func = $1;
+        push @replaces, $func;
     }
 
 
@@ -150,40 +176,51 @@
 
 # Pre-compile regular expressions
 my $before = qr/[%!~,=><:\/\n\s\[\]\{\}\(\)\+\-\*\\\.]/;
-my $after  = qr/[%!~,=><:\/\s;\[\]\(\)\{\}\+\-\*\\\^]/;
+#my $after  = qr/[%!~,=><:\/\s;\[\]\(\)\{\}\+\-\*\\\^]/;
+my $after  = qr/[%!~,=><:\/\s;\[\]\(\)\{\}\+\-\*\\\^']/;
 
 # Compile module replacement regex
-my %module_replacements = map { $_ => "${_}_$noc_id" } @module_names;
+my %module_replacements = map { $_ => "${_}_${suffix}" } @module_names;
 my $module_regex = join '|', map { quotemeta } @module_names;
 
 # Compile file replacement regex
 my %file_replacements = map { 
     my ($file_name, $extension) = /^(.+)\.(\w+)$/;
-    $_ => "${file_name}_${noc_id}.$extension"
+    $_ => "${file_name}_${suffix}.$extension"
 } @files;
 my $file_regex = join '|', map { quotemeta } @files;
 
 # Compile key replacement regex
-my %key_replacements = map { $_ => "${_}_${noc_id}" } @replaces;
+my %key_replacements = map { $_ => "${_}_${suffix}" } @replaces;
 my $key_regex = join '|', map { quotemeta } @replaces;
 
-# Compile replace hash regex
-my $replace_regex = join '|', map { quotemeta } keys %replace;
+# Compile replace hash regex (spaces become \s*)
+my $replace_regex = join '|',
+    map {
+        my $pattern = $_;
+
+        # Escape all regex metacharacters except space
+        $pattern =~ s/([^\w\s])/\\$1/g;
+
+        # Convert literal spaces to \s*
+        $pattern =~ s/ /\\s*/g;
+
+        $pattern;
+    } sort keys %replace;
 
 
 foreach my $file (@files) {
     #print "$file\n";    
     my ($file_name, $extension) = $file =~ /^(.+)\.(\w+)$/;
-    my $output_filename = "$out_dir/${file_name}_${noc_id}.$extension";
+    my $output_filename = "$out_dir/${file_name}_${suffix}.$extension";
     
     open(my $input_fh, '<', "$noc_dir/$file") or die "Could not open file '$file' $!";
 
     # Open a new file for writing the modified content
     open(my $output_fh, '>', $output_filename) or die "Could not create file '$output_filename' $!";
     if($file eq "pronoc_pkg.sv"){
-         print $output_fh "`define IMPORT_PRONOC_PCK\n`define PRONOC_PKG\n";
+        print $output_fh "`define IMPORT_PRONOC_PCK\n`define PRONOC_PKG\n";
     }
-   
 
 # Read the input file line by line
 while (my $line = <$input_fh>) {
@@ -191,11 +228,19 @@
     $line =~ s/\b($module_regex)\b/$module_replacements{$1}/g;
 
     # Replace keys in %replace hash
-    $line =~ s/($replace_regex)/$replace{$1}/g;
+    $line =~ s/($replace_regex)/$replace{space_match($1)}/g;
+    #print "$line =~ s/($replace_regex)/\$replace{$1}/g;\n";
 
     # Replace file names
     $line =~ s/($file_regex)/$file_replacements{$1}/g;
 
+    # Replace NOC_ID (handle space around '=')
+    $line =~ s/NOC_ID\s*=\s*0/NOC_ID = "$ARGV[0]"/g;
+
+    if (defined $chip_id) {
+        $line =~ s/NOC_CHIP_ID\s*=\s*0/NOC_CHIP_ID = $chip_id/g;
+    }
+
     # Replace keys with boundary checks
     #$line =~ s/($before)($key_regex)($after)/$1$key_replacements{$2}$3/g;
     while ($line =~ s/($before)($key_regex)($after)/$1$key_replacements{$2}$3/g) {}   
@@ -203,7 +248,25 @@
     # Write the modified line to the output file
     print $output_fh $line;
 }
-  
+
+
+
+sub space_match {
+    my $in = shift;
+
+    # 1. Exact match
+    return $in if exists $replace{$in};
+    # 2. Pattern match (spaces → \s*)
+    foreach my $key (sort keys %replace) {
+        my $new_key = $key;
+        $new_key =~ s/ /\\s*/g;   # replace space with \s*
+        if ($in =~ /^$new_key$/) {
+            return $key;
+        }
+    }
+    # 3. Default return
+    return $in;
+}
 
 # Close the input and output files
 close($input_fh);
diff --git a/mpsoc/script/synfull/model.tcl b/mpsoc/script/synfull/model.tcl
index a022919..4023a35 100644
--- a/mpsoc/script/synfull/model.tcl
+++ b/mpsoc/script/synfull/model.tcl
@@ -32,7 +32,7 @@ vmap work $rtl_work
 
 vlog  +acc=rn  -F $::env(LM_FILE_LIST)
 
-vsim -t 1ps  -L $rtl_work -L work -voptargs="+acc"  $top -sv_lib $DPI_LIB
+vsim -suppress vopt-14408 -t 1ps  -L $rtl_work -L work -voptargs="+acc"  $top -sv_lib $DPI_LIB
 
 add wave *
 view structure
diff --git a/mpsoc/script/synfull/noc_localparam.v b/mpsoc/script/synfull/noc_localparam.v
index 83104ba..feff061 100644
--- a/mpsoc/script/synfull/noc_localparam.v
+++ b/mpsoc/script/synfull/noc_localparam.v
@@ -1,79 +1,79 @@
 
 /**************************************************************************
-**	WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT ARE LIKELY TO BE
-**	OVERWRITTEN AND LOST. Rename this file if you wish to do any modification.
+**    WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT ARE LIKELY TO BE
+**    OVERWRITTEN AND LOST. Rename this file if you wish to do any modification.
 ****************************************************************************/
 
 
 /**********************************************************************
-**	File: noc_localparam.v
+**    File: noc_localparam.v
 **    
-**	Copyright (C) 2014-2019  Alireza Monemi
+**    Copyright (C) 2014-2019  Alireza Monemi
 **    
-**	This file is part of ProNoC 1.9.1 
+**    This file is part of ProNoC 1.9.1 
 **
-**	ProNoC ( stands for Prototype Network-on-chip)  is free software: 
-**	you can redistribute it and/or modify it under the terms of the GNU
-**	Lesser General Public License as published by the Free Software Foundation,
-**	either version 2 of the License, or (at your option) any later version.
+**    ProNoC ( stands for Prototype Network-on-chip)  is free software: 
+**    you can redistribute it and/or modify it under the terms of the GNU
+**    Lesser General Public License as published by the Free Software Foundation,
+**    either version 2 of the License, or (at your option) any later version.
 **
-** 	ProNoC is distributed in the hope that it will be useful, but WITHOUT
-** 	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
-** 	or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
-** 	Public License for more details.
+**     ProNoC is distributed in the hope that it will be useful, but WITHOUT
+**     ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+**     or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
+**     Public License for more details.
 **
-** 	You should have received a copy of the GNU Lesser General Public
-** 	License along with ProNoC. If not, see <http:**www.gnu.org/licenses/>.
+**     You should have received a copy of the GNU Lesser General Public
+**     License along with ProNoC. If not, see <http:**www.gnu.org/licenses/>.
 ******************************************************************************/ 
 
-	
-	`ifdef   NOC_LOCAL_PARAM 
- 
- 
-	
+    
+    `ifdef   NOC_LOCAL_PARAM 
 
 //NoC parameters
-	localparam TOPOLOGY="MESH";
-	localparam T1=4;
-	localparam T2=4;
-	localparam T3=2;
-	localparam V=1;
-	localparam B=4;
-	localparam LB=4;
-	localparam Fpay=64;
-	localparam ROUTE_NAME="XY";
-	localparam PCK_TYPE="MULTI_FLIT";
-	localparam MIN_PCK_SIZE=1;
-	localparam BYTE_EN=0;
-	localparam SSA_EN="NO";
-	localparam SMART_MAX=0;
-	localparam CONGESTION_INDEX=3;
-	localparam ESCAP_VC_MASK=1;
-	localparam VC_REALLOCATION_TYPE="NONATOMIC";
-	localparam COMBINATION_TYPE="COMB_NONSPEC";
-	localparam MUX_TYPE="BINARY";
-	localparam C=2;
-	localparam DEBUG_EN=1;
-	localparam ADD_PIPREG_AFTER_CROSSBAR=1'b1;
-	localparam FIRST_ARBITER_EXT_P_EN=1;
-	localparam SWA_ARBITER_TYPE="RRA";
-	localparam WEIGHTw=4;
-	localparam SELF_LOOP_EN="YES";
-	localparam AVC_ATOMIC_EN=0;
-	localparam CVw=(C==0)? V : C * V;
-	localparam CLASS_SETTING={CVw{1'b1}};
+    localparam TOPOLOGY="MESH";
+    localparam T1=4;
+    localparam T2=4;
+    localparam T3=2;
+    localparam V=1;
+    localparam B=4;
+    localparam LB=4;
+    localparam Fpay=64;
+    localparam ROUTE_NAME="DOR";
+    localparam PCK_TYPE="MULTI_FLIT";
+    localparam MIN_PCK_SIZE=1;
+    localparam BYTE_EN=0;
+    localparam SSA_EN=0;
+    localparam SMART_MAX=0;
+    localparam CONGESTION_INDEX=3;
+    localparam ESCAP_VC_MASK=1;
+    localparam VC_REALLOCATION_TYPE="NONATOMIC";
+    localparam COMBINATION_TYPE="COMB_NONSPEC";
+    localparam MUX_TYPE="BINARY";
+    localparam C=2;
+    localparam DEBUG_EN=1;
+    localparam ADD_PIPREG_AFTER_CROSSBAR=1'b1;
+    localparam FIRST_ARBITER_EXT_P_EN=1;
+    localparam SWA_ARBITER_TYPE="RRA";
+    localparam WEIGHTw=4;
+    localparam SELF_LOOP_EN=1;
+    localparam AVC_ATOMIC_EN=0;
+    localparam CVw=(C==0)? V : C * V;
+    localparam CLASS_SETTING={CVw{1'b1}};
     localparam CAST_TYPE = "UNICAST";
-	localparam MCAST_ENDP_LIST = 'b11110011;	
-//	localparam MCAST_PRTLw=6;
-	
-	//simulation parameter	
-	//localparam MAX_RATIO = 1000;
-	localparam MAX_PCK_NUM = 1000000000;
-	localparam MAX_PCK_SIZ = 16383; 
-	localparam MAX_SIM_CLKs=  1000000000;
-	localparam TIMSTMP_FIFO_NUM = 16;	
-	
-		
-
- 
- `endif
+    localparam MCAST_ENDP_LIST = 'b11110011;
+    
+    localparam MAX_ROUTER=1;
+    localparam MAX_PORT=1;
+    localparam int VC_CONFIG_TABLE [MAX_ROUTER][MAX_PORT]='{'{0}};
+    localparam HETERO_VC=0;
+    
+//    localparam MCAST_PRTLw=6;
+    
+    //simulation parameter
+    //localparam MAX_RATIO = 1000;
+    localparam MAX_PCK_NUM = 1000000000;
+    localparam MAX_PCK_SIZ = 16383; 
+    localparam MAX_SIM_CLKs=  1000000000;
+    localparam TIMSTMP_FIFO_NUM = 16;
+    
+`endif
diff --git a/mpsoc/script/synfull/run_modelsim b/mpsoc/script/synfull/run_modelsim
index f09121d..c5a6112 100755
--- a/mpsoc/script/synfull/run_modelsim
+++ b/mpsoc/script/synfull/run_modelsim
@@ -9,10 +9,7 @@ SCRPT_FULL_PATH=$(realpath ${BASH_SOURCE[0]})
 SCRPT_DIR_PATH=$(dirname $SCRPT_FULL_PATH)
 
 #questasim
-LM_LICENSE="1717@epi03.bsc.es"
 VSIM_BIN="vsim"
-
-export LM_LICENSE_FILE=${LM_LICENSE}
 export LM_WORK_PLACE=${PRONOC_WORK}/simulation
 export LM_FILE_LIST="$SCRPT_DIR_PATH/modelsim_filelist.f"
 export PATH=$PATH:$MODELSIM_BIN
diff --git a/mpsoc/script/verilator_2D_mesh.sh b/mpsoc/script/verilator_2D_mesh.sh
index d91e71d..a4cf231 100755
--- a/mpsoc/script/verilator_2D_mesh.sh
+++ b/mpsoc/script/verilator_2D_mesh.sh
@@ -41,9 +41,9 @@ CORE_NUM(){
     COMBINATION_TYPE="COMB_NONSPEC" # "BASELINE" or "COMB_SPEC1" or "COMB_SPEC2" or "COMB_NONSPEC"
     FIRST_ARBITER_EXT_P_EN=1  
     TOPOLOGY="MESH" #"MESH" or "TORUS"
-    ROUTE_NAME="DUATO" # Routing algorithm
-	#    mesh :  "XY"        , "WEST_FIRST"      , "NORTH_LAST"      , "NEGETIVE_FIRST"      , "DUATO"
-    #   torus:  "TRANC_XY"  , "TRANC_WEST_FIRST", "TRANC_NORTH_LAST", "TRANC_NEGETIVE_FIRST", "TRANC_DUATO"
+    ROUTE_NAME="FULL_ADPT" # Routing algorithm
+	#    mesh :  "DOR"        , "WEST_FIRST"      , "NORTH_LAST"      , "NEGETIVE_FIRST"      , "FULL_ADPT"
+    #   torus:  "TRANC_DOR"  , "TRANC_WEST_FIRST", "TRANC_NORTH_LAST", "TRANC_NEGETIVE_FIRST", "TRANC_FULL_ADPT"
     CONGESTION_INDEX="VC" #"CREDIT","VC"  
     CLASS_SETTING="4'b1111"           
 	#0: no class. packets can be sent to any available OVC
@@ -81,7 +81,7 @@ CORE_NUM(){
 
 
 # 	for minimal fully adaptive on 2D mesh paper 
-	ROUTING_SUBFUNCTION= "XY" # "XY" "NORTH_LAST"
+	ROUTING_SUBFUNCTION= "DOR" # "DOR" "NORTH_LAST"
 	AVC_REALLOCATION= "" 	
 
 generate_parameter_v (){
@@ -112,8 +112,8 @@ generate_parameter_v (){
     printf " parameter TOTAL_PKT_PER_ROUTER=$TOTAL_PKT_PER_ROUTER;\n" >> parameter.v	
     printf " parameter MAX_DELAY_BTWN_PCKTS=$MAX_DELAY_BTWN_PCKTS;\n" >> parameter.v	
 	printf " parameter DEBUG_EN=$DEBUG_EN;\n" >> parameter.v	
-	printf " parameter ROUTE_TYPE = (ROUTE_NAME == \"XY\" || ROUTE_NAME == \"TRANC_XY\" )?    \"DETERMINISTIC\" : \n" >> parameter.v	
-    printf "			            (ROUTE_NAME == \"DUATO\" || ROUTE_NAME == \"TRANC_DUATO\" )?   \"FULL_ADAPTIVE\": \"PAR_ADAPTIVE\"; \n" >> parameter.v	          
+	printf " parameter ROUTE_TYPE = (ROUTE_NAME == \"DOR\" || ROUTE_NAME == \"TRANC_DOR\" )?    \"DETERMINISTIC\" : \n" >> parameter.v	
+    printf "			            (ROUTE_NAME == \"FULL_ADPT\" || ROUTE_NAME == \"TRANC_FULL_ADPT\" )?   \"FULL_ADAPTIVE\": \"PAR_ADAPTIVE\"; \n" >> parameter.v	          
 	printf " parameter ADD_PIPREG_AFTER_CROSSBAR= $ADD_PIPREG_AFTER_CROSSBAR;\n" >>  parameter.v
 	printf " parameter CVw=(C==0)? V : C * V;\n" >>  parameter.v
 	printf " parameter [CVw-1:   0] CLASS_SETTING = $CLASS_SETTING;\n">>  parameter.v 
@@ -168,7 +168,7 @@ for PACKET_SIZE in  3 2 4 6
 	for  TRAFFIC in  "RANDOM"  "TRANSPOSE1" "TRANSPOSE2"  "HOTSPOT"
 	do
 
-		for  ROUTE_NAME in "XY" "WEST_FIRST" "NORTH_LAST"  "NEGETIVE_FIRST"  "DUATO"
+		for  ROUTE_NAME in "DOR" "WEST_FIRST" "NORTH_LAST"  "NEGETIVE_FIRST"  "FULL_ADPT"
 		do
 			# regenerate NoC
 			generate_parameter_v
@@ -190,7 +190,7 @@ for PACKET_SIZE in  3 2 4 6
 		#run multiple testbench files in the same time
 		cd $multiple_path
 		
-		for  ROUTE_NAME in "XY" "WEST_FIRST" "NORTH_LAST"  "NEGETIVE_FIRST"  "DUATO"
+		for  ROUTE_NAME in "DOR" "WEST_FIRST" "NORTH_LAST"  "NEGETIVE_FIRST"  "FULL_ADPT"
 		do	
 			
 			./$ROUTE_NAME$TRAFFIC"_"$PACKET_SIZE $ROUTE_NAME$TRAFFIC"_"$PACKET_SIZE &	
@@ -200,7 +200,7 @@ for PACKET_SIZE in  3 2 4 6
 		wait
 		
 		# merge the result in one file 
-		for  ROUTE_NAME in "XY" "WEST_FIRST" "NORTH_LAST"  "NEGETIVE_FIRST"  "DUATO"
+		for  ROUTE_NAME in "DOR" "WEST_FIRST" "NORTH_LAST"  "NEGETIVE_FIRST"  "FULL_ADPT"
 		do	
 		data_file=$data_path/$TRAFFIC"_"$PACKET_SIZE"_all.txt"
 		plot_file=$plot_path/$TRAFFIC"_"$PACKET_SIZE".eps"
diff --git a/mpsoc/smart-netrace/models/B4_V1_S0 b/mpsoc/smart-netrace/models/B4_V1_S0
index db60b5c..6f9937f 100644
--- a/mpsoc/smart-netrace/models/B4_V1_S0
+++ b/mpsoc/smart-netrace/models/B4_V1_S0
@@ -1,10 +1,10 @@
 $model = bless( {
 		'noc_param'=> {
-						"ROUTE_NAME" => "\"XY\"",    					
+						"ROUTE_NAME" => "\"DOR\"",    					
 		"ADD_PIPREG_AFTER_CROSSBAR" => "1'b1",				
 		"V" => "1",
 		"B" => "4",
-		"SELF_LOOP_EN" => "\"YES\"",
+		"SELF_LOOP_EN" => "1",
 		"SMART_MAX" => "0",
 		"ESCAP_VC_MASK" => "1'b1",
 	}
diff --git a/mpsoc/smart-netrace/models/B4_V1_S2 b/mpsoc/smart-netrace/models/B4_V1_S2
index 8a996e0..94c23d7 100644
--- a/mpsoc/smart-netrace/models/B4_V1_S2
+++ b/mpsoc/smart-netrace/models/B4_V1_S2
@@ -1,10 +1,10 @@
 $model = bless( {
 		'noc_param'=> {
-						"ROUTE_NAME" => "\"XY\"",    					
+						"ROUTE_NAME" => "\"DOR\"",    					
 		"ADD_PIPREG_AFTER_CROSSBAR" => "1'b1",						
 		"V" => "1",
 		"B" => "4",
-		"SELF_LOOP_EN" => "\"YES\"",
+		"SELF_LOOP_EN" => "1",
 		"SMART_MAX" => "2",
 		"ESCAP_VC_MASK" => "1'b1",
 	}
diff --git a/mpsoc/smart-netrace/models/B4_V1_S4 b/mpsoc/smart-netrace/models/B4_V1_S4
index f9f2e0b..8bcb6e2 100644
--- a/mpsoc/smart-netrace/models/B4_V1_S4
+++ b/mpsoc/smart-netrace/models/B4_V1_S4
@@ -1,10 +1,10 @@
 $model = bless( {
 		'noc_param'=> {
-						"ROUTE_NAME" => "\"XY\"",    					
+						"ROUTE_NAME" => "\"DOR\"",    					
 		"ADD_PIPREG_AFTER_CROSSBAR" => "1'b1",						
 		"V" => "1",
 		"B" => "4",
-		"SELF_LOOP_EN" => "\"YES\"",
+		"SELF_LOOP_EN" => "1",
 		"SMART_MAX" => "4",
 		"ESCAP_VC_MASK" => "1'b1",
 	}
diff --git a/mpsoc/smart-netrace/models/B4_V1_S7 b/mpsoc/smart-netrace/models/B4_V1_S7
index a13f851..936f5e9 100644
--- a/mpsoc/smart-netrace/models/B4_V1_S7
+++ b/mpsoc/smart-netrace/models/B4_V1_S7
@@ -1,10 +1,10 @@
 $model = bless( {
 		'noc_param'=> {
-						"ROUTE_NAME" => "\"XY\"",    					
+						"ROUTE_NAME" => "\"DOR\"",    					
 		"ADD_PIPREG_AFTER_CROSSBAR" => "1'b1",						
 		"V" => "1",
 		"B" => "4",
-		"SELF_LOOP_EN" => "\"YES\"",
+		"SELF_LOOP_EN" => "1",
 		"SMART_MAX" => "7",
 		"ESCAP_VC_MASK" => "1'b1",
 	}
diff --git a/mpsoc/smart-netrace/src/deafult_noc_param b/mpsoc/smart-netrace/src/deafult_noc_param
index e884438..4c3b565 100644
--- a/mpsoc/smart-netrace/src/deafult_noc_param
+++ b/mpsoc/smart-netrace/src/deafult_noc_param
@@ -8,11 +8,11 @@ $model = bless( {
 "B" => "4",
 "LB" => "B",
 "Fpay" => "32",
-"ROUTE_NAME" => "\"XY\"",
+"ROUTE_NAME" => "\"DOR\"",
 "PCK_TYPE" => "  \"MULTI_FLIT\"",  
 "MIN_PCK_SIZE" => "2",
 "BYTE_EN" => "0",
-"SSA_EN" => "\"NO\"",
+"SSA_EN" => "0",
 "CONGESTION_INDEX" => "3",
 "ESCAP_VC_MASK" => "2'b01",
 "VC_REALLOCATION_TYPE" => "\"NONATOMIC\"",
@@ -28,7 +28,7 @@ $model = bless( {
 "AVC_ATOMIC_EN" => "0",
 "CLASS_SETTING" => "{V{1'b1}}",
 "SMART_MAX" => "0",
-"SELF_LOOP_EN" => "\"NO\"",
+"SELF_LOOP_EN" => "0",
 "MAX_PCK_NUM " => " 1000000000",
 "MAX_PCK_SIZ " => " 16383" ,
 "MAX_SIM_CLKs" => "  1000000000",
diff --git a/mpsoc/smart-netrace/src/src.pl b/mpsoc/smart-netrace/src/src.pl
index 9030313..3ce2da7 100755
--- a/mpsoc/smart-netrace/src/src.pl
+++ b/mpsoc/smart-netrace/src/src.pl
@@ -21,7 +21,7 @@
 use warnings;
 
 my $pp;
-	$pp= do "$src/deafult_noc_param";
+	$pp= do "$src/default_noc_param";
 	die "Error reading: $@" if $@;
 
 	my $param = $pp->{'noc_param'};
@@ -535,7 +535,7 @@ sub check_sim_results{
 	
 		my @errors = unix_grep("$file","ERROR:");
 		if (scalar @errors  ){
-			append_text_to_file($report,"\t Error in running simulation: @errors \n");	
+			append_text_to_file($report,"\t Error in running simulation:\n @errors \n");	
 			$self->{'name'}{"$name"}{'traffic'}{$traffic}{'overal_result'}="Failed";
 			$self->{'name'}{"$name"}{'traffic'}{$traffic}{'message'}="@errors";
 			return;						
diff --git a/mpsoc/src_c/jtag/jtag_libusb/out b/mpsoc/src_c/jtag/jtag_libusb/out
index 906c100..e051380 100644
--- a/mpsoc/src_c/jtag/jtag_libusb/out
+++ b/mpsoc/src_c/jtag/jtag_libusb/out
@@ -13,7 +13,7 @@ Router parameters:
 	AVC_ATOMIC_EN:0 
 	Congestion Index:3 
 	ADD_PIPREG_AFTER_CROSSBAR:0
-	SSA_EN enabled:NO 
+	SSA_EN enabled:0 
 	Switch allocator arbitration type:RRA 
 
 Simulation parameters
diff --git a/mpsoc/src_c/jtag/test_rtl/jtag_ram_test/src_verilog/lib/arbiter.v b/mpsoc/src_c/jtag/test_rtl/jtag_ram_test/src_verilog/lib/arbiter.v
old mode 100644
new mode 100755
index fdc288c..16708f1
--- a/mpsoc/src_c/jtag/test_rtl/jtag_ram_test/src_verilog/lib/arbiter.v
+++ b/mpsoc/src_c/jtag/test_rtl/jtag_ram_test/src_verilog/lib/arbiter.v
@@ -1,61 +1,54 @@
- `timescale     1ns/1ps
+`include "pronoc_def.v"
 /**********************************************************************
-**	File: arbiter.v
+**    File: arbiter.v
 **    
-**	Copyright (C) 2014-2017  Alireza Monemi
+**    Copyright (C) 2014-2017  Alireza Monemi
 **    
-**	This file is part of ProNoC 
+**    This file is part of ProNoC 
 **
-**	ProNoC ( stands for Prototype Network-on-chip)  is free software: 
-**	you can redistribute it and/or modify it under the terms of the GNU
-**	Lesser General Public License as published by the Free Software Foundation,
-**	either version 2 of the License, or (at your option) any later version.
+**    ProNoC ( stands for Prototype Network-on-chip)  is free software: 
+**    you can redistribute it and/or modify it under the terms of the GNU
+**    Lesser General Public License as published by the Free Software Foundation,
+**    either version 2 of the License, or (at your option) any later version.
 **
-** 	ProNoC is distributed in the hope that it will be useful, but WITHOUT
-** 	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
-** 	or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
-** 	Public License for more details.
+**     ProNoC is distributed in the hope that it will be useful, but WITHOUT
+**     ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+**     or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
+**     Public License for more details.
 **
-** 	You should have received a copy of the GNU Lesser General Public
-** 	License along with ProNoC. If not, see <http:**www.gnu.org/licenses/>.
+**     You should have received a copy of the GNU Lesser General Public
+**     License along with ProNoC. If not, see <http:**www.gnu.org/licenses/>.
 **
 **
 **
-**	Description: 
-**	This file contains several Fixed prority and round robin 
-**	arbiters 
+**    Description: 
+**    This file contains several Fixed prority and round robin 
+**    arbiters 
 **
 ******************************************************************************/ 
 
 
 /*****************************************
-*        
 * general round robin arbiter
-* 
-*
 ******************************************/
+`ifndef PRONOC_ARBITER
+`define PRONOC_ARBITER
 
 module arbiter #(
     parameter    ARBITER_WIDTH    =8
-        
-)
-(    
-   clk, 
-   reset, 
-   request, 
-   grant,
-   any_grant
+)(    
+    clk, 
+    reset, 
+    request, 
+    grant,
+    any_grant
 );
-
+    input [ARBITER_WIDTH-1 : 0] request;
+    output [ARBITER_WIDTH-1 : 0] grant;
+    output any_grant;
+    input clk;
+    input reset;
     
-    input    [ARBITER_WIDTH-1             :    0]    request;
-    output    [ARBITER_WIDTH-1            :    0]    grant;
-    output                                        any_grant;
-    input                                        clk;
-    input                                        reset;
-
-
-
     generate 
     if(ARBITER_WIDTH==1)  begin: w1
         assign grant= request;
@@ -64,23 +57,18 @@ module arbiter #(
         //my own arbiter 
         my_one_hot_arbiter #(
             .ARBITER_WIDTH    (ARBITER_WIDTH)
-        )
-        one_hot_arb
-        (    
+        ) one_hot_arb (    
             .clk            (clk), 
             .reset         (reset), 
             .request        (request), 
             .grant        (grant),
             .any_grant    (any_grant)
         );
-    
     end else begin : wb4
         
         thermo_arbiter #(
             .ARBITER_WIDTH    (ARBITER_WIDTH)
-        )
-        one_hot_arb
-        (    
+        )  one_hot_arb   (    
             .clk            (clk), 
             .reset         (reset), 
             .request        (request), 
@@ -97,30 +85,22 @@ endmodule
 * RRA with external priority enable signal
 *
 ******************************************/
-
 module arbiter_priority_en #(
-        parameter    ARBITER_WIDTH    =8
-        
-)
-(    
-   clk, 
-   reset, 
-   request, 
-   grant,
-   any_grant,
-   priority_en
+    parameter    ARBITER_WIDTH    =8
+)(    
+    clk, 
+    reset, 
+    request, 
+    grant,
+    any_grant,
+    priority_en
 );
-
-  
-
-
-    input        [ARBITER_WIDTH-1             :    0]    request;
-    output    [ARBITER_WIDTH-1            :    0]    grant;
-    output                                            any_grant;
-    input                                                clk;
-    input                                                reset;
-    input                                              priority_en;
-    
+    input [ARBITER_WIDTH-1 : 0] request;
+    output [ARBITER_WIDTH-1 : 0] grant;
+    output any_grant;
+    input clk;
+    input reset;
+    input priority_en;
     
     generate 
     if(ARBITER_WIDTH==1)  begin: w1
@@ -130,25 +110,19 @@ module arbiter_priority_en #(
         //my own arbiter 
         my_one_hot_arbiter_priority_en #(
             .ARBITER_WIDTH    (ARBITER_WIDTH)
-        )
-        one_hot_arb
-        (    
+        )  one_hot_arb  (    
             .clk            (clk), 
             .reset         (reset), 
             .request        (request), 
             .grant        (grant),
             .any_grant    (any_grant),
             .priority_en (priority_en)
-            
         );
-    
     end else begin :wb4
         
         thermo_arbiter_priority_en #(
             .ARBITER_WIDTH    (ARBITER_WIDTH)
-        )
-        one_hot_arb
-        (    
+        )  one_hot_arb  (    
             .clk            (clk), 
             .reset         (reset), 
             .request        (request), 
@@ -161,657 +135,457 @@ endgenerate
 endmodule
 
 
-
 /******************************************************
-*	my_one_hot_arbiter
+*    my_one_hot_arbiter
 * RRA with binary-coded priority register. Binary-coded 
 * Priority results in less area cost and CPD for arbire 
 * width of 4 and smaller only. 
 *
 ******************************************************/
-      
-    
-
 module my_one_hot_arbiter #(
     parameter ARBITER_WIDTH    =4
-    
-    
-)
-(
-    input        [ARBITER_WIDTH-1             :    0]    request,
-    output    [ARBITER_WIDTH-1            :    0]    grant,
-    output                                            any_grant,
-    input                                                clk,
-    input                                                reset
+)(
+    input [ARBITER_WIDTH-1 : 0] request,
+    output [ARBITER_WIDTH-1 : 0] grant,
+    output any_grant,
+    input clk,
+    input reset
 );
-   
+
     function integer log2;
-      input integer number; begin   
-         log2=(number <=1) ? 1: 0;    
-         while(2**log2<number) begin    
-            log2=log2+1;    
-         end 	   
-      end   
+    input integer number; begin
+        log2=(number <=1) ? 1: 0;
+        while(2**log2<number) begin
+            log2=log2+1;
+        end 
+    end   
     endfunction // log2 
     
     localparam ARBITER_BIN_WIDTH= log2(ARBITER_WIDTH);
-    reg     [ARBITER_BIN_WIDTH-1        :    0]     low_pr;
-    wire     [ARBITER_BIN_WIDTH-1        :    0]     grant_bcd;
+    reg     [ARBITER_BIN_WIDTH-1 : 0] low_pr;
+    wire [ARBITER_BIN_WIDTH-1 : 0] grant_bcd;
     
     one_hot_to_bin #(
-        .ONE_HOT_WIDTH    (ARBITER_WIDTH)
-    )conv
-    (
+        .ONE_HOT_WIDTH(ARBITER_WIDTH)
+    )conv (
     .one_hot_code(grant),
     .bin_code(grant_bcd)
-
     );
     
-    
-`ifdef SYNC_RESET_MODE 
-    always @ (posedge clk )begin 
-`else 
-    always @ (posedge clk or posedge reset)begin 
-`endif     
-
-        if(reset) begin
-            low_pr    <=    {ARBITER_BIN_WIDTH{1'b0}};
+    always @ (`pronoc_clk_reset_edge )begin 
+        if(`pronoc_reset) begin
+            low_pr <= {ARBITER_BIN_WIDTH{1'b0}};
         end else begin
             if(any_grant) low_pr <= grant_bcd;
         end
     end
-    
-
     assign any_grant = | request;
-
     generate 
-        if(ARBITER_WIDTH    ==2) begin: w2        arbiter_2_one_hot arb( .in(request) , .out(grant), .low_pr(low_pr)); end
-        if(ARBITER_WIDTH    ==3) begin: w3        arbiter_3_one_hot arb( .in(request) , .out(grant), .low_pr(low_pr)); end
-        if(ARBITER_WIDTH    ==4) begin: w4        arbiter_4_one_hot arb( .in(request) , .out(grant), .low_pr(low_pr)); end
+        if(ARBITER_WIDTH    ==2) begin: w2  arbiter_2_one_hot arb( .D_in(request) , .Q_out(grant), .low_pr(low_pr)); end
+        if(ARBITER_WIDTH    ==3) begin: w3  arbiter_3_one_hot arb( .D_in(request) , .Q_out(grant), .low_pr(low_pr)); end
+        if(ARBITER_WIDTH    ==4) begin: w4  arbiter_4_one_hot arb( .D_in(request) , .Q_out(grant), .low_pr(low_pr)); end
     endgenerate
-
 endmodule
 
 
 module arbiter_2_one_hot(
-     input      [1             :    0]    in,
-     output    reg[1                :    0]    out,
-     input                                low_pr
+    input [1 : 0] D_in,
+    output reg[1 : 0] Q_out,
+    input low_pr
 );
-always @(*) begin
-     out=2'b00;
-      case(low_pr)
-         1'd0:
-             if(in[1])                 out=2'b10;
-             else if(in[0])         out=2'b01;
-         1'd1:
-             if(in[0])                 out=2'b01;
-             else if(in[1])         out=2'b10;
-          default: out=2'b00;
-     endcase 
-  end
- endmodule 
-
-
+    always @(*) begin
+        Q_out=2'b00;
+        case(low_pr)
+            1'd0:
+                if(D_in[1])              Q_out=2'b10;
+                else if(D_in[0])         Q_out=2'b01;
+            1'd1:
+                if(D_in[0])              Q_out=2'b01;
+                else if(D_in[1])         Q_out=2'b10;
+            default: Q_out=2'b00;
+        endcase 
+    end
+endmodule 
 
 
 module arbiter_3_one_hot(
-     input      [2             :    0]    in,
-     output    reg[2                :    0]    out,
-     input        [1                :    0]    low_pr
+    input [2 : 0] D_in,
+    output reg[2 : 0] Q_out,
+    input [1 : 0] low_pr
 );
-always @(*) begin
-  out=3'b000;
-      case(low_pr)
-         2'd0:
-             if(in[1])                 out=3'b010;
-             else if(in[2])         out=3'b100;
-             else if(in[0])         out=3'b001;
-         2'd1:
-             if(in[2])                 out=3'b100;
-             else if(in[0])         out=3'b001;
-             else if(in[1])         out=3'b010;
-         2'd2:
-             if(in[0])                 out=3'b001;
-             else if(in[1])         out=3'b010;
-             else if(in[2])         out=3'b100;
-         default: out=3'b000;
-     endcase 
-  end
- endmodule 
-
-
- module arbiter_4_one_hot(
-     input      [3             :    0]    in,
-     output    reg[3                :    0]    out,
-     input        [1                :    0]    low_pr
+    always @(*) begin
+        Q_out=3'b000;
+        case(low_pr)
+            2'd0:
+                if(D_in[1])              Q_out=3'b010;
+                else if(D_in[2])         Q_out=3'b100;
+                else if(D_in[0])         Q_out=3'b001;
+            2'd1:
+                if(D_in[2])              Q_out=3'b100;
+                else if(D_in[0])         Q_out=3'b001;
+                else if(D_in[1])         Q_out=3'b010;
+            2'd2:
+                if(D_in[0])              Q_out=3'b001;
+                else if(D_in[1])         Q_out=3'b010;
+                else if(D_in[2])         Q_out=3'b100;
+            default: Q_out=3'b000;
+        endcase 
+    end
+endmodule 
+
+
+module arbiter_4_one_hot(
+    input [3 : 0] D_in,
+    output reg[3 : 0] Q_out,
+    input [1 : 0] low_pr
 );
-always @(*) begin
-  out=4'b0000;
-      case(low_pr)
-         2'd0:
-             if(in[1])                 out=4'b0010;
-             else if(in[2])         out=4'b0100;
-             else if(in[3])         out=4'b1000;
-             else if(in[0])         out=4'b0001;
-         2'd1:
-             if(in[2])                 out=4'b0100;
-             else if(in[3])         out=4'b1000;
-             else if(in[0])         out=4'b0001;
-             else if(in[1])         out=4'b0010;
-         2'd2:
-             if(in[3])                 out=4'b1000;
-             else if(in[0])         out=4'b0001;
-             else if(in[1])         out=4'b0010;
-             else if(in[2])         out=4'b0100;
-         2'd3:
-             if(in[0])                 out=4'b0001;
-             else if(in[1])         out=4'b0010;
-             else if(in[2])         out=4'b0100;
-             else if(in[3])         out=4'b1000;
-         default: out=4'b0000;
-     endcase 
-  end
- endmodule 
+    always @(*) begin
+        Q_out=4'b0000;
+        case(low_pr)
+            2'd0:
+                if(D_in[1])              Q_out=4'b0010;
+                else if(D_in[2])         Q_out=4'b0100;
+                else if(D_in[3])         Q_out=4'b1000;
+                else if(D_in[0])         Q_out=4'b0001;
+            2'd1:
+                if(D_in[2])              Q_out=4'b0100;
+                else if(D_in[3])         Q_out=4'b1000;
+                else if(D_in[0])         Q_out=4'b0001;
+                else if(D_in[1])         Q_out=4'b0010;
+            2'd2:
+                if(D_in[3])              Q_out=4'b1000;
+                else if(D_in[0])         Q_out=4'b0001;
+                else if(D_in[1])         Q_out=4'b0010;
+                else if(D_in[2])         Q_out=4'b0100;
+            2'd3:
+                if(D_in[0])              Q_out=4'b0001;
+                else if(D_in[1])         Q_out=4'b0010;
+                else if(D_in[2])         Q_out=4'b0100;
+                else if(D_in[3])         Q_out=4'b1000;
+            default: Q_out=4'b0000;
+        endcase 
+    end
+endmodule 
 
 
 /******************************************************
-*	my_one_hot_arbiter_priority_en
+*    my_one_hot_arbiter_priority_en
 * 
 ******************************************************/
-
-
-
 module my_one_hot_arbiter_priority_en #(
     parameter ARBITER_WIDTH    =4
-    
-    
-)
-(
-    input        [ARBITER_WIDTH-1             :    0]    request,
-    output    [ARBITER_WIDTH-1            :    0]    grant,
-    output                                            any_grant,
-    input                                                clk,
-    input                                                reset,
-    input                                                priority_en
+)(
+    input [ARBITER_WIDTH-1 : 0] request,
+    output [ARBITER_WIDTH-1 : 0] grant,
+    output any_grant,
+    input clk,
+    input reset,
+    input priority_en
 );
-   
     function integer log2;
-      input integer number; begin   
-         log2=(number <=1) ? 1: 0;    
-         while(2**log2<number) begin    
-            log2=log2+1;    
-         end 	   
-      end   
+    input integer number; begin
+        log2=(number <=1) ? 1: 0;
+        while(2**log2<number) begin
+            log2=log2+1;
+        end
+    end
     endfunction // log2 
     
     localparam ARBITER_BIN_WIDTH= log2(ARBITER_WIDTH);
-    reg     [ARBITER_BIN_WIDTH-1        :    0]     low_pr;
-    wire     [ARBITER_BIN_WIDTH-1        :    0]     grant_bcd;
+    reg     [ARBITER_BIN_WIDTH-1 : 0] low_pr;
+    wire [ARBITER_BIN_WIDTH-1 : 0] grant_bcd;
     
     one_hot_to_bin #(
         .ONE_HOT_WIDTH    (ARBITER_WIDTH)
-    )conv 
-    (
+    )conv (
         .one_hot_code(grant),
         .bin_code(grant_bcd)
     );
-
-`ifdef SYNC_RESET_MODE 
-    always @ (posedge clk )begin 
-`else 
-    always @ (posedge clk or posedge reset)begin 
-`endif 
-   
-        if(reset) begin
+    
+    always @ (`pronoc_clk_reset_edge )begin 
+        if(`pronoc_reset) begin
             low_pr    <=    {ARBITER_BIN_WIDTH{1'b0}};
         end else begin
             if(priority_en) low_pr <= grant_bcd;
         end
     end
     
-
     assign any_grant = | request;
-
     generate 
-        if(ARBITER_WIDTH    ==2) begin :w2        arbiter_2_one_hot arb( .in(request) , .out(grant), .low_pr(low_pr)); end
-        if(ARBITER_WIDTH    ==3) begin :w3        arbiter_3_one_hot arb( .in(request) , .out(grant), .low_pr(low_pr)); end
-        if(ARBITER_WIDTH    ==4) begin :w4        arbiter_4_one_hot arb( .in(request) , .out(grant), .low_pr(low_pr)); end
+        if(ARBITER_WIDTH    ==2) begin : w2 arbiter_2_one_hot arb( .D_in(request) , .Q_out(grant), .low_pr(low_pr)); end
+        if(ARBITER_WIDTH    ==3) begin : w3 arbiter_3_one_hot arb( .D_in(request) , .Q_out(grant), .low_pr(low_pr)); end
+        if(ARBITER_WIDTH    ==4) begin : w4 arbiter_4_one_hot arb( .D_in(request) , .Q_out(grant), .low_pr(low_pr)); end
     endgenerate
-
-endmodule   
+endmodule
 
 
 
 /*******************
-*
 *    thermo_arbiter RRA
-*
 ********************/
-
 module thermo_gen #(
     parameter WIDTH=16
-
-
 )(
-    input  [WIDTH-1    :    0]in,
-    output [WIDTH-1    :    0]out
+    input [WIDTH-1 : 0]D_in,
+    output [WIDTH-1 : 0]Q_out
 );
     genvar i;
     generate
     for(i=0;i<WIDTH;i=i+1)begin :lp
-        assign out[i]= | in[i    :0];    
+        assign Q_out[i]= | D_in[i :0];    
     end
     endgenerate
-
 endmodule
- 
- 
- 
- 
-module thermo_arbiter #(
- parameter    ARBITER_WIDTH    =4
-        
-)
-(    
-   clk, 
-   reset, 
-   request, 
-   grant,
-   any_grant
-);
 
-        
-
-    
-    input        [ARBITER_WIDTH-1             :    0]    request;
-    output    [ARBITER_WIDTH-1            :    0]    grant;
-    output                                            any_grant;
-    input                                                reset,clk;
-    
-    
-    wire        [ARBITER_WIDTH-1             :    0]    termo1,termo2,mux_out,masked_request,edge_mask;
-    reg        [ARBITER_WIDTH-1             :    0]    pr;
-
-
-    thermo_gen #(
-        .WIDTH(ARBITER_WIDTH)
-    ) tm1
-    (
-        .in(request),
-        .out(termo1)
-    );
-
-
-
-
-    thermo_gen #(
-        .WIDTH(ARBITER_WIDTH)
-    ) tm2
-    (
-        .in(masked_request),
-        .out(termo2)
-    );
 
+module thermo_arbiter #(
+    parameter    ARBITER_WIDTH    =4
+)(    
+    clk, 
+    reset, 
+    request, 
+    grant,
+    any_grant
+);
+    input [ARBITER_WIDTH-1 : 0] request;
+    output [ARBITER_WIDTH-1 : 0] grant;
+    output any_grant;
+    input reset,clk;
+    wire [ARBITER_WIDTH-1 : 0] mux_out,masked_request,edge_mask;
+    reg       [ARBITER_WIDTH-1 : 0] pr;
+    reg       [ARBITER_WIDTH-1 : 0] termo1,termo2;
+    integer i;
+    always @(*) begin 
+        for(i=0;i<ARBITER_WIDTH; i=i+1) begin 
+            termo1[i] = |(request << (ARBITER_WIDTH - 1 - i));
+            termo2[i] = |(masked_request << (ARBITER_WIDTH - 1 - i));
+        end
+    end
     
     assign mux_out=(termo2[ARBITER_WIDTH-1])? termo2 : termo1;
     assign masked_request= request & pr;
     assign any_grant=termo1[ARBITER_WIDTH-1];
-
-`ifdef SYNC_RESET_MODE 
-    always @ (posedge clk )begin 
-`else 
-    always @ (posedge clk or posedge reset)begin 
-`endif 
-        if(reset) pr<= {ARBITER_WIDTH{1'b1}};
+    
+    always @ (`pronoc_clk_reset_edge )begin 
+            if(`pronoc_reset) pr<= {ARBITER_WIDTH{1'b1}};
         else begin 
             if(any_grant) pr<= edge_mask;
         end
     end
-
+    
     assign edge_mask= {mux_out[ARBITER_WIDTH-2:0],1'b0};
     assign grant= mux_out ^ edge_mask;
+endmodule
 
 
 
-endmodule
-    
-    
-
- 
- 
 module thermo_arbiter_priority_en #(
- parameter    ARBITER_WIDTH    =4
-        
-)
-(    
-   clk, 
-   reset, 
-   request, 
-   grant,
-   any_grant,
-   priority_en
+    parameter    ARBITER_WIDTH    =4
+)(    
+    clk, 
+    reset, 
+    request, 
+    grant,
+    any_grant,
+    priority_en
 );
-
-        
-
-    
-    input        [ARBITER_WIDTH-1             :    0]    request;
-    output    [ARBITER_WIDTH-1            :    0]    grant;
-    output                                            any_grant;
-    input                                                reset,clk;
+    input [ARBITER_WIDTH-1 : 0] request;
+    output [ARBITER_WIDTH-1 : 0] grant;
+    output any_grant;
+    input reset,clk;
     input priority_en;
     
-    wire        [ARBITER_WIDTH-1             :    0]    termo1,termo2,mux_out,masked_request,edge_mask;
-    reg        [ARBITER_WIDTH-1             :    0]    pr;
-
-
-    thermo_gen #(
-        .WIDTH(ARBITER_WIDTH)
-    ) tm1
-    (
-        .in(request),
-        .out(termo1)
-    );
-
-
-
-
-    thermo_gen #(
-        .WIDTH(ARBITER_WIDTH)
-    ) tm2
-    (
-        .in(masked_request),
-        .out(termo2)
-    );
-
-    
-assign mux_out=(termo2[ARBITER_WIDTH-1])? termo2 : termo1;
-assign masked_request= request & pr;
-assign any_grant=termo1[ARBITER_WIDTH-1];
-
-`ifdef SYNC_RESET_MODE 
-    always @ (posedge clk )begin 
-`else 
-    always @ (posedge clk or posedge reset)begin 
-`endif 
-
- 
-    if(reset) pr<= {ARBITER_WIDTH{1'b1}};
-    else begin 
-        if(priority_en) pr<= edge_mask;
+    wire [ARBITER_WIDTH-1 : 0] mux_out,masked_request,edge_mask;
+    reg   [ARBITER_WIDTH-1 : 0] pr;
+    reg   [ARBITER_WIDTH-1 : 0] termo1,termo2;
+    integer i;
+    always @(*) begin 
+        for(i=0;i<ARBITER_WIDTH; i=i+1) begin 
+            termo1[i] = |(request << (ARBITER_WIDTH - 1 - i));
+            termo2[i] = |(masked_request << (ARBITER_WIDTH - 1 - i));
+        end
     end
 
-end
-
-assign edge_mask= {mux_out[ARBITER_WIDTH-2:0],1'b0};
-assign grant= mux_out ^ edge_mask;
-
-
-
-endmodule
+    assign mux_out=(termo2[ARBITER_WIDTH-1])? termo2 : termo1;
+    assign masked_request= request & pr;
+    assign any_grant=termo1[ARBITER_WIDTH-1];
+    always @ (`pronoc_clk_reset_edge )begin 
+            if(`pronoc_reset) pr<= {ARBITER_WIDTH{1'b1}};
+        else begin 
+            if(priority_en) pr<= edge_mask;
+        end
+    end
     
+    assign edge_mask= {mux_out[ARBITER_WIDTH-2:0],1'b0};
+    assign grant= mux_out ^ edge_mask;
+endmodule
 
 
-
-
-
-
- 
 module thermo_arbiter_ext_priority #(
- parameter    ARBITER_WIDTH    =4
-        
-)
-(    
-   
-   request, 
-   grant,
-   any_grant,
-   priority_in
-  
+    parameter    ARBITER_WIDTH    =4
+)(
+    request, 
+    grant,
+    any_grant,
+    priority_in
 );
-
-        
-
-    
-    input        [ARBITER_WIDTH-1             :    0]    request;
-    output    [ARBITER_WIDTH-1            :    0]    grant;
-    output                                            any_grant;
-    input   [ARBITER_WIDTH-1            :   0]  priority_in;
-
-    wire        [ARBITER_WIDTH-1             :    0]    termo1,termo2,mux_out,masked_request,edge_mask;
-    wire        [ARBITER_WIDTH-1             :    0]    pr;
-
-
-    thermo_gen #(
-        .WIDTH(ARBITER_WIDTH)
-    ) tm1
-    (
-        .in(request),
-        .out(termo1)
-    );
-
-
-
-
-    thermo_gen #(
-        .WIDTH(ARBITER_WIDTH)
-    ) tm2
-    (
-        .in(masked_request),
-        .out(termo2)
-    );
-
-
-    thermo_gen #(
-        .WIDTH(ARBITER_WIDTH)
-    ) tm3
-    (
-        .in(priority_in),
-        .out(pr)
-    );
-
+    input [ARBITER_WIDTH-1 : 0] request;
+    output [ARBITER_WIDTH-1 : 0] grant;
+    output any_grant;
+    input [ARBITER_WIDTH-1 : 0] priority_in;
+    
+    wire [ARBITER_WIDTH-1 : 0] mux_out,masked_request,edge_mask;
+    reg [ARBITER_WIDTH-1 : 0] termo1,termo2,pr;
+    
+    integer i;
+    always @(*) begin 
+        for(i=0;i<ARBITER_WIDTH; i=i+1) begin 
+            termo1[i] = |(request << (ARBITER_WIDTH - 1 - i));
+            termo2[i] = |(masked_request << (ARBITER_WIDTH - 1 - i));
+            pr[i] = |(priority_in << (ARBITER_WIDTH - 1 - i));
+        end
+    end
     
-assign mux_out=(termo2[ARBITER_WIDTH-1])? termo2 : termo1;
-assign masked_request= request & pr;
-assign any_grant=termo1[ARBITER_WIDTH-1];
-
-
-assign edge_mask= {mux_out[ARBITER_WIDTH-2:0],1'b0};
-assign grant= mux_out ^ edge_mask;
-
-
-
+    assign mux_out=(termo2[ARBITER_WIDTH-1])? termo2 : termo1;
+    assign masked_request= request & pr;
+    assign any_grant=termo1[ARBITER_WIDTH-1];
+    assign edge_mask= {mux_out[ARBITER_WIDTH-2:0],1'b0};
+    assign grant= mux_out ^ edge_mask;
 endmodule
-    
-
 
 /********************************
-*    
 *   Tree arbiter
-* 
-*******************************/
-
+******************************/
 module tree_arbiter #(
-        parameter    GROUP_NUM        =4,
-        parameter    ARBITER_WIDTH    =16
-)
-(    
-   clk, 
-   reset, 
-   request, 
-   grant,
-   any_grant
+    parameter    GROUP_NUM        =4,
+    parameter    ARBITER_WIDTH    =16
+)(
+    clk, 
+    reset, 
+    request, 
+    grant,
+    any_grant
 );
-
- 
     function integer log2;
-      input integer number; begin   
-         log2=(number <=1) ? 1: 0;    
-         while(2**log2<number) begin    
-            log2=log2+1;    
-         end 	   
-      end   
+    input integer number; begin
+        log2=(number <=1) ? 1: 0;
+        while(2**log2<number) begin
+            log2=log2+1;
+        end
+    end
     endfunction // log2 
-
-  localparam N = ARBITER_WIDTH;
-  localparam S = log2(ARBITER_WIDTH); // ceil of log_2 of N - put manually
-  
-
-  // I/O interface
-  input           clk;
-  input           reset;
-  input  [N-1:0]  request;
-  output [N-1:0]  grant;
-  output          any_grant;
-
-
+    
+    localparam N = ARBITER_WIDTH;
+    localparam S = log2(ARBITER_WIDTH); // ceil of log_2 of N - put manually
+    // I/O interface
+    input clk;
+    input reset;
+    input [N-1:0] request;
+    output [N-1:0] grant;
+    output any_grant;
+    
     localparam GROUP_WIDTH    =    ARBITER_WIDTH/GROUP_NUM;
-  
-  wire [GROUP_WIDTH-1        :    0]    group_req    [GROUP_NUM-1        :    0];
-  wire [GROUP_WIDTH-1        :    0]    group_grant [GROUP_NUM-1        :    0];
-  wire [GROUP_WIDTH-1        :    0]    grant_masked[GROUP_NUM-1        :    0];
-  
-  wire [GROUP_NUM-1            :    0] any_group_member_req;
-  wire [GROUP_NUM-1            :    0] any_group_member_grant;
- 
+    wire [GROUP_WIDTH-1 : 0] group_req    [GROUP_NUM-1 : 0];
+    wire [GROUP_WIDTH-1 : 0] group_grant [GROUP_NUM-1 : 0];
+    wire [GROUP_WIDTH-1 : 0] grant_masked[GROUP_NUM-1 : 0];
+    wire [GROUP_NUM-1 : 0] any_group_member_req;
+    wire [GROUP_NUM-1 : 0] any_group_member_grant;
     
     genvar i;
     generate
     for (i=0;i<GROUP_NUM;i=i+1) begin :group_lp
-        
         //seprate inputs in group
-        assign group_req[i]    =    request[(i+1)*GROUP_WIDTH-1        :    i*GROUP_WIDTH];
-        
+        assign group_req[i] =    request[(i+1)*GROUP_WIDTH-1 : i*GROUP_WIDTH];
         //check if any member of qrup has request
-        assign any_group_member_req[i]    =    | group_req[i];
-        
+        assign any_group_member_req[i] =    | group_req[i];
         //arbiterate one request from each group
         arbiter #(
             .ARBITER_WIDTH    (GROUP_WIDTH)
-        )group_member_arbiter
-        (    
+        )group_member_arbiter   (    
             .clk            (clk), 
             .reset        (reset), 
             .request        (group_req[i]), 
             .grant        (group_grant[i]),
             .any_grant    ()
         );
-        
-    // mask the non selected groups        
+        // mask the non selected groups        
         assign grant_masked [i] = (any_group_member_grant[i])?    group_grant[i]: {GROUP_WIDTH{1'b0}};
-    
-    //assemble the grants
-        assign grant [(i+1)*GROUP_WIDTH-1        :    i*GROUP_WIDTH] = grant_masked [i];
-    
-    
+        //assemble the grants
+        assign grant [(i+1)*GROUP_WIDTH-1 : i*GROUP_WIDTH] = grant_masked [i];
     end
     endgenerate
     
     //select one group which has atleast one active request
-    
     //arbiterate one request from each group
-        arbiter #(
-            .ARBITER_WIDTH    (GROUP_NUM)
-        )second_arbiter
-        (    
-            .clk        (clk), 
-            .reset        (reset), 
-            .request    (any_group_member_req), 
-            .grant        (any_group_member_grant),
-            .any_grant    (any_grant)
-        );
-                
-    
- 
- endmodule 
- 
-
+    arbiter #(
+        .ARBITER_WIDTH    (GROUP_NUM)
+    )second_arbiter (    
+        .clk        (clk), 
+        .reset        (reset), 
+        .request    (any_group_member_req), 
+        .grant        (any_group_member_grant),
+        .any_grant    (any_grant)
+    );
+endmodule 
 
 
- 
- 
 /*******************************
-
-    my_one_hot_arbiter_ext_priority
-
+*    my_one_hot_arbiter_ext_priority
 *******************************/
-
 module my_one_hot_arbiter_ext_priority #(
     parameter ARBITER_WIDTH =4
-    
-    
-)
-(
-    input   [ARBITER_WIDTH-1            :   0]  request,
-    input   [ARBITER_WIDTH-1            :   0]  priority_in,
-    output  [ARBITER_WIDTH-1            :   0]  grant,
-    output                                      any_grant
+)(
+    input [ARBITER_WIDTH-1 : 0] request,
+    input [ARBITER_WIDTH-1 : 0] priority_in,
+    output [ARBITER_WIDTH-1 : 0] grant,
+    output any_grant
 );
- 
+    
     function integer log2;
-      input integer number; begin   
-         log2=(number <=1) ? 1: 0;    
-         while(2**log2<number) begin    
-            log2=log2+1;    
-         end 	   
-      end   
+    input integer number; begin
+        log2=(number <=1) ? 1: 0;
+        while(2**log2<number) begin
+            log2=log2+1;
+        end
+    end
     endfunction // log2 
-
+    
     localparam ARBITER_BIN_WIDTH= log2(ARBITER_WIDTH);
-    wire    [ARBITER_BIN_WIDTH-1        :   0]  low_pr;
-      
-   
-    wire [ARBITER_WIDTH-1            :   0] low_pr_one_hot = {priority_in[0],priority_in[ARBITER_BIN_WIDTH-1:1]};
+    wire [ARBITER_BIN_WIDTH-1 : 0] low_pr;
+    wire [ARBITER_WIDTH-1 : 0] low_pr_one_hot = {priority_in[0],priority_in[ARBITER_BIN_WIDTH-1:1]};
     
     one_hot_to_bin #(
         .ONE_HOT_WIDTH    (ARBITER_WIDTH)
-    )conv 
-    (
+    )conv (
         .one_hot_code(low_pr_one_hot),
         .bin_code(low_pr)
     );
-      
-
     assign any_grant = | request;
-
     generate 
-        if(ARBITER_WIDTH    ==2) begin: w2       arbiter_2_one_hot arb( .in(request) , .out(grant), .low_pr(low_pr)); end
-        if(ARBITER_WIDTH    ==3) begin: w3       arbiter_3_one_hot arb( .in(request) , .out(grant), .low_pr(low_pr)); end
-        if(ARBITER_WIDTH    ==4) begin: w4       arbiter_4_one_hot arb( .in(request) , .out(grant), .low_pr(low_pr)); end
+        if(ARBITER_WIDTH    ==2) begin: w2       arbiter_2_one_hot arb( .D_in(request) , .Q_out(grant), .low_pr(low_pr)); end
+        if(ARBITER_WIDTH    ==3) begin: w3       arbiter_3_one_hot arb( .D_in(request) , .Q_out(grant), .low_pr(low_pr)); end
+        if(ARBITER_WIDTH    ==4) begin: w4       arbiter_4_one_hot arb( .D_in(request) , .Q_out(grant), .low_pr(low_pr)); end
     endgenerate
-
 endmodule
 
 
 /*********************************
-*
 *       arbiter_ext_priority
-*
 **********************************/
-
-
- module arbiter_ext_priority  #(
-        parameter   ARBITER_WIDTH   =8
-        
-)
-(   
-  
-   request, 
-   grant,
-   priority_in,
-   any_grant
+module arbiter_ext_priority  #(
+    parameter   ARBITER_WIDTH   =8
+)(   
+    request, 
+    grant,
+    priority_in,
+    any_grant
 );
-
-    
-    input   [ARBITER_WIDTH-1            :   0]  request;
-    input   [ARBITER_WIDTH-1            :   0]  priority_in;
-    output  [ARBITER_WIDTH-1            :   0]  grant;
-    output                                      any_grant;
- 
-   /*
+    input [ARBITER_WIDTH-1 : 0] request;
+    input [ARBITER_WIDTH-1 : 0] priority_in;
+    output [ARBITER_WIDTH-1 : 0] grant;
+    output any_grant;
+    /*
     generate 
-  
     if(ARBITER_WIDTH<=4) begin :ws4
         //my own arbiter 
         my_one_hot_arbiter_ext_priority #(
@@ -819,22 +593,16 @@ endmodule
         )
         one_hot_arb
         (   
-           
             .request    (request),
             .priority_in(priority_in), 
             .grant      (grant),
             .any_grant  (any_grant)
         );
-    
     end else begin :wb4
     */
-        
         thermo_arbiter_ext_priority #(
             .ARBITER_WIDTH  (ARBITER_WIDTH)
-        )
-        one_hot_arb
-        (   
-            
+        ) one_hot_arb  (   
             .request    (request), 
             .priority_in(priority_in), 
             .grant      (grant),
@@ -842,54 +610,50 @@ endmodule
         );
    // end
    // endgenerate
- 
- 
- 
- 
 endmodule 
- 
-
-
-
 
 
 
-    
-
- /*
- module fixed_priority_arbiter #(
-     parameter   ARBITER_WIDTH   =8,
-     parameter   HIGH_PRORITY_BIT = "HSB"
- )
- (   
-  
-   request, 
-   grant,
-   any_grant
+module fixed_priority_arbiter #(
+    parameter   ARBITER_WIDTH   =8,
+    parameter   HIGH_PRORITY_BIT = "HSB"
+) (   
+    request, 
+    grant,
+    any_grant
 );
-
-    
-    input   [ARBITER_WIDTH-1            :   0]  request;
-    output  [ARBITER_WIDTH-1            :   0]  grant;
-    output                                      any_grant;
-   
-    wire    [ARBITER_WIDTH-1            :   0]  cout;
-    reg     [ARBITER_WIDTH-1            :   0]  cin;
-    
-    
-    assign  any_grant= | request;
-    
+    input [ARBITER_WIDTH-1 : 0] request;
+    output [ARBITER_WIDTH-1 : 0] grant;
+    output any_grant;
+    /*
+    wire [ARBITER_WIDTH-1 : 0] cout;
+    reg     [ARBITER_WIDTH-1 : 0] cin;
     assign grant    = cin & request;
     assign cout     = cin & ~request; 
-    
-     always @(*) begin 
+    always @(*) begin 
         if( HIGH_PRORITY_BIT == "HSB")  cin      = {1'b1, cout[ARBITER_WIDTH-1 :1]}; // hsb has highest priority
         else                            cin      = {cout[ARBITER_WIDTH-2 :0] ,1'b1}; // lsb has highest priority
     end//always
-endmodule
+    */
     
-*/
-
- 
- 
- 
+    assign  any_grant= | request;
+    wire [ARBITER_WIDTH-1 : 0] termo_code, edge_mask;
+    
+    genvar i;
+    generate
+    if( HIGH_PRORITY_BIT == "LSB") begin :hsb
+        for(i=0;i<ARBITER_WIDTH;i=i+1)begin :lp
+            assign termo_code[i]= | request[i :0];    
+        end
+        assign edge_mask=  {termo_code[ARBITER_WIDTH-2:0],1'b0};
+    end else begin :hsb
+        for(i=0;i<ARBITER_WIDTH;i=i+1)begin :lp
+            assign termo_code[i]= | request[ARBITER_WIDTH-1 :i];    
+        end
+        assign edge_mask=  {1'b0, termo_code[ARBITER_WIDTH-1:1]};
+    end
+    endgenerate
+    
+    assign grant= termo_code ^ edge_mask;
+endmodule
+`endif
\ No newline at end of file
diff --git a/mpsoc/src_c/jtag/test_rtl/jtag_ram_test/src_verilog/lib/main_comp.v b/mpsoc/src_c/jtag/test_rtl/jtag_ram_test/src_verilog/lib/main_comp.v
index e30a1c6..dc8ba8a 100644
--- a/mpsoc/src_c/jtag/test_rtl/jtag_ram_test/src_verilog/lib/main_comp.v
+++ b/mpsoc/src_c/jtag/test_rtl/jtag_ram_test/src_verilog/lib/main_comp.v
@@ -1,186 +1,205 @@
- `timescale  1ns/1ps
-
-
+`include "pronoc_def.v"
 /**********************************************************************
-**	File:  main_comp.v
+**    File: main_comp.v
 **    
-**	Copyright (C) 2014-2017  Alireza Monemi
+**    Copyright (C) 2014-2017  Alireza Monemi
 **    
-**	This file is part of ProNoC 
+**    This file is part of ProNoC 
 **
-**	ProNoC ( stands for Prototype Network-on-chip)  is free software: 
-**	you can redistribute it and/or modify it under the terms of the GNU
-**	Lesser General Public License as published by the Free Software Foundation,
-**	either version 2 of the License, or (at your option) any later version.
+**    ProNoC ( stands for Prototype Network-on-chip)  is free software: 
+**    you can redistribute it and/or modify it under the terms of the GNU
+**    Lesser General Public License as published by the Free Software Foundation,
+**    either version 2 of the License, or (at your option) any later version.
 **
-** 	ProNoC is distributed in the hope that it will be useful, but WITHOUT
-** 	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
-** 	or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
-** 	Public License for more details.
+**     ProNoC is distributed in the hope that it will be useful, but WITHOUT
+**     ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+**     or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
+**     Public License for more details.
 **
-** 	You should have received a copy of the GNU Lesser General Public
-** 	License along with ProNoC. If not, see <http:**www.gnu.org/licenses/>.
+**     You should have received a copy of the GNU Lesser General Public
+**     License along with ProNoC. If not, see <http:**www.gnu.org/licenses/>.
 **
 **
-**	Description: 
-**	This file contains several general RTL modules such as 
-**	different types of multiplexors, converters and counters ...
+**    Description: 
+**    This file contains several general RTL modules such as 
+**    different types of multiplexors, converters and counters ...
 **
 **************************************************************/
+`ifndef PRONOC_COMMON
+`define PRONOC_COMMON
+
+module pronoc_register #(
+    parameter W=1,
+    parameter  RESET_TO={W{1'b0}}
+)( 
+    input [W-1: 0] D_in,
+    input reset,    
+    input clk,      
+    output reg [W-1: 0] Q_out
+);
+    always @ (`pronoc_clk_reset_edge )begin 
+        if(`pronoc_reset)   Q_out <= W'(RESET_TO);
+        else  Q_out <= D_in;
+    end
+endmodule
 
 
+module pronoc_register_reset_init #(
+    parameter W=1       
+)( 
+    input [W-1: 0] D_in,
+    input reset,    
+    input clk,      
+    output reg [W-1: 0] Q_out,
+    input [W-1 : 0] reset_to
+);
+    always @ (`pronoc_clk_reset_edge )begin 
+        if(`pronoc_reset)   Q_out<=reset_to;
+        else        Q_out<=D_in;
+    end   
+endmodule
 
 
+module pronoc_register_reset_init_ld_en   #(
+    parameter W=1       
+)( 
+    input [W-1: 0] D_in,
+    input reset,    
+    input clk, 
+    input ld,
+    output reg [W-1: 0] Q_out,
+    input [W-1 : 0] reset_to
+);    
+    always @ (`pronoc_clk_reset_edge )begin 
+        if(`pronoc_reset)   Q_out<=reset_to;
+        else  if(ld)      Q_out<=D_in;
+    end        
+endmodule
 
 
-
-/*********************************
-
+module pronoc_register_ld_en  #(
+    parameter W=1,
+    parameter  RESET_TO={W{1'b0}}
+)( 
+    input [W-1: 0] D_in,
+    input reset,    
+    input clk,  
+    input ld,
+    output [W-1: 0] Q_out
+);
+    pronoc_register_reset_init_ld_en  #(
+        .W(W)           
+    )reg1( 
+        .D_in(D_in),
+        .reset(reset),  
+        .clk(clk),  
+        .ld(ld),
+        .Q_out(Q_out),
+        .reset_to(RESET_TO[W-1 : 0])
+    );
+endmodule
 
 
-    multiplexer
 
-    
-    
+/*********************************
+*   multiplexer
 ********************************/
-
 module one_hot_mux #(
-        parameter   IN_WIDTH      = 20,
-        parameter   SEL_WIDTH =   5, 
-        parameter   OUT_WIDTH = IN_WIDTH/SEL_WIDTH
-
-    )
-    (
-        input [IN_WIDTH-1       :0] mux_in,
-        output[OUT_WIDTH-1  :0] mux_out,
-        input[SEL_WIDTH-1   :0] sel
-
-    );
-
-    wire [IN_WIDTH-1    :0] mask;
-    wire [IN_WIDTH-1    :0] masked_mux_in;
-    wire [SEL_WIDTH-1:0]    mux_out_gen [OUT_WIDTH-1:0]; 
+    parameter   IN_WIDTH = 20,
+    parameter   SEL_WIDTH = 5, 
+    parameter   OUT_WIDTH = IN_WIDTH/SEL_WIDTH
+)(
+    input [IN_WIDTH-1 : 0] mux_in,
+    output[OUT_WIDTH-1 : 0] mux_out,
+    input[SEL_WIDTH-1 : 0] sel
+);
+    wire [IN_WIDTH-1 : 0] mask;
+    wire [IN_WIDTH-1 : 0] masked_mux_in;
+    wire [SEL_WIDTH-1: 0]    mux_out_gen [OUT_WIDTH-1: 0]; 
     
     genvar i,j;
-    
     //first selector masking
     generate    // first_mask = {sel[0],sel[0],sel[0],....,sel[n],sel[n],sel[n]}
         for(i=0; i<SEL_WIDTH; i=i+1) begin : mask_loop
-            assign mask[(i+1)*OUT_WIDTH-1 : (i)*OUT_WIDTH]  =   {OUT_WIDTH{sel[i]} };
+            assign mask[(i+1)*OUT_WIDTH-1 : (i)*OUT_WIDTH] = {OUT_WIDTH{sel[i]} };
         end
-        
-        assign masked_mux_in    = mux_in & mask;
-        
+        assign masked_mux_in = mux_in & mask;
         for(i=0; i<OUT_WIDTH; i=i+1) begin : lp1
             for(j=0; j<SEL_WIDTH; j=j+1) begin : lp2
-                assign mux_out_gen [i][j]   =   masked_mux_in[i+OUT_WIDTH*j];
+                assign mux_out_gen [i][j] = masked_mux_in[i+OUT_WIDTH*j];
             end
             assign mux_out[i] = | mux_out_gen [i];
         end
     endgenerate
-    
 endmodule
 
 
-
-
-
-    
 /******************************
-
-    One hot demultiplexer
-
+*    One hot demultiplexer
 ****************************/   
-    
-
 module one_hot_demux    #(
-        parameter IN_WIDTH=5,
-        parameter SEL_WIDTH=4,
-        parameter OUT_WIDTH=IN_WIDTH*SEL_WIDTH
-    )
-    (
-        input   [SEL_WIDTH-1        :   0] demux_sel,//selectore
-        input   [IN_WIDTH-1         :   0] demux_in,//repeated
-        output  [OUT_WIDTH-1        :   0]  demux_out
-    );
+    parameter IN_WIDTH=5,
+    parameter SEL_WIDTH=4,
+    parameter OUT_WIDTH=IN_WIDTH*SEL_WIDTH
+)(
+    input   [SEL_WIDTH-1 : 0] demux_sel,//selectore
+    input   [IN_WIDTH-1 : 0] demux_in,//repeated
+    output  [OUT_WIDTH-1 : 0]  demux_out
+);
 
     genvar i,j;
     generate 
     for(i=0;i<SEL_WIDTH;i=i+1)begin :loop1
         for(j=0;j<IN_WIDTH;j=j+1)begin :loop2
-                assign demux_out[i*IN_WIDTH+j] =     demux_sel[i]   &   demux_in[j];
+                assign demux_out[i*IN_WIDTH+j] = demux_sel[i]   &   demux_in[j];
         end//for j
     end//for i
     endgenerate
-
-    
-
 endmodule
 
 /**************************
-
-
-    custom_or
-
-    
+*    reduction_or
 ***************************/
-
-
-module custom_or #(
-    parameter IN_NUM        =   4,
-    parameter OUT_WIDTH =   5
+module reduction_or #(
+    parameter W = 5,//out width
+    parameter N = 4 //array lenght 
 )(
-    or_in,
-    or_out
+    D_in,
+    Q_out
 );
-    
-    localparam IN_WIDTH  = IN_NUM*OUT_WIDTH;
-    
-    input [IN_WIDTH-1       :   0]  or_in;
-    output[OUT_WIDTH-1      :   0]  or_out;
-
-    wire        [IN_NUM-1       :   0] in_sep   [OUT_WIDTH-1        :   0];
-    genvar i,j;
-    generate
-    for (i=0;i<OUT_WIDTH;i=i+1) begin: sep_loop
-        for (j=0;j<IN_NUM;j=j+1) begin: sep_loop
-            assign in_sep[i][j]= or_in [j*OUT_WIDTH+i];
-        end
-        assign or_out[i]= |in_sep[i];
+    input  [W-1 : 0] D_in [N-1 : 0];
+    output reg [W-1 : 0] Q_out;
+    
+    // assign Q_out = D_in.or(); //it is not synthesizable able by some compiler
+    always_comb begin
+        Q_out = {W{1'b0}};
+        for (int i = 0; i < N; i++)
+            Q_out |=   D_in[i];
     end
-    endgenerate
-    
-    
 endmodule
 
 
 /*****************************************
-
-sum the output of all ports except the output of  port itself
-
-
+* sum the output of all ports 
+* except the output of  port itself
 ****************************************/
-
-
 module outport_sum #(
     parameter IN_ARRAY_WIDTH =10,
-    parameter IN_NUM     =5,
-    parameter IN_WIDTH  =   IN_ARRAY_WIDTH/IN_NUM,
-    parameter CMP_VAL   =   IN_WIDTH/(IN_NUM-1),
+    parameter IN_NUM =5,
+    parameter IN_WIDTH = IN_ARRAY_WIDTH/IN_NUM,
+    parameter CMP_VAL = IN_WIDTH/(IN_NUM-1),
     parameter OUT_WIDTH = (IN_ARRAY_WIDTH/IN_NUM)+CMP_VAL
-    
-    )
-    (
-    input   [IN_ARRAY_WIDTH-1       :   0]  in,
-    output  [OUT_WIDTH-1                :   0]  out
+)(
+    input   [IN_ARRAY_WIDTH-1 : 0]  D_in,
+    output  [OUT_WIDTH-1 : 0]  Q_out
 );
     
     genvar i,j;
-    wire [IN_WIDTH-1        :   0]      in_sep  [IN_NUM-1       :   0];
-    wire [IN_NUM-2          :   0]      gen         [OUT_WIDTH-1    :   0];
+    wire [IN_WIDTH-1 : 0]      in_sep  [IN_NUM-1 : 0];
+    wire [IN_NUM-2 : 0]      gen         [OUT_WIDTH-1 : 0];
     generate 
         for(i=0;i<IN_NUM; i=i+1      ) begin : lp
-            assign in_sep[i]  = in[(IN_WIDTH*(i+1))-1   : IN_WIDTH*i];
+            assign in_sep[i] = D_in[(IN_WIDTH*(i+1))-1 : IN_WIDTH*i];
         end
         for (j=0;j<IN_NUM-1;j=j+1)begin : loop1
                 for(i=0;i<OUT_WIDTH; i=i+1  )begin : loop2
@@ -196,612 +215,276 @@ module outport_sum #(
                 end// for i
             end// for j
         for(i=0;i<OUT_WIDTH; i=i+1       ) begin : lp2
-            assign out[i]               = |  gen[i];
+            assign Q_out[i] = |  gen[i];
         end
     endgenerate
 endmodule
 
 /***********************************
-
-        module bin_to_one_hot 
-        
-
+*   module bin_to_one_hot 
 ************************************/
-
-
 module bin_to_one_hot #(
-    parameter BIN_WIDTH     =   2,
-    parameter ONE_HOT_WIDTH =   2**BIN_WIDTH
+    parameter BIN_WIDTH = 2,
+    parameter ONE_HOT_WIDTH = 2**BIN_WIDTH
     
-)
-(
-    input   [BIN_WIDTH-1            :   0]  bin_code,
-    output  [ONE_HOT_WIDTH-1        :   0] one_hot_code
- );
+)(
+    input   [BIN_WIDTH-1 : 0]  bin_code,
+    output reg [ONE_HOT_WIDTH-1 : 0] one_hot_code
+);
 
-    genvar i;
-    generate 
-        for(i=0; i<ONE_HOT_WIDTH; i=i+1) begin :one_hot_gen_loop
-                assign one_hot_code[i] = (bin_code == i[BIN_WIDTH-1         :   0]);
-        end
-    endgenerate
- 
+    always @(*) begin
+        one_hot_code = {ONE_HOT_WIDTH{1'b0}};
+        one_hot_code[bin_code] = 1'b1;
+    end
+
+    
 endmodule
 
 /***********************************
-
-        one_hot_to_binary
-
+*        one_hot_to_binary
 ************************************/
-
-
-
 module one_hot_to_bin #(
-    parameter ONE_HOT_WIDTH =   4,
-    parameter BIN_WIDTH     =  (ONE_HOT_WIDTH>1)? log2(ONE_HOT_WIDTH):1
-)
-(
-    input   [ONE_HOT_WIDTH-1        :   0] one_hot_code,
-    output  [BIN_WIDTH-1            :   0]  bin_code
-
+    parameter ONE_HOT_WIDTH = 4,
+    parameter BIN_WIDTH = (ONE_HOT_WIDTH > 1) ? $clog2(ONE_HOT_WIDTH) : 1
+)(
+    input   [ONE_HOT_WIDTH-1 : 0] one_hot_code,
+    output  [BIN_WIDTH-1 : 0]  bin_code
 );
-
-  
-    function integer log2;
-      input integer number; begin   
-         log2=(number <=1) ? 1: 0;    
-         while(2**log2<number) begin    
-            log2=log2+1;    
-         end 	   
-      end   
-    endfunction // log2 
-
-localparam MUX_IN_WIDTH =   BIN_WIDTH* ONE_HOT_WIDTH;
-
-wire [MUX_IN_WIDTH-1        :   0]  bin_temp ;
-
-genvar i;
-generate 
+    localparam MUX_IN_WIDTH = BIN_WIDTH * ONE_HOT_WIDTH;
+    wire [MUX_IN_WIDTH-1 : 0]  bin_temp ;
+    genvar i;
+    generate 
     if(ONE_HOT_WIDTH>1)begin :if1
         for(i=0; i<ONE_HOT_WIDTH; i=i+1) begin :mux_in_gen_loop
-            assign bin_temp[(i+1)*BIN_WIDTH-1 : i*BIN_WIDTH] =  i[BIN_WIDTH-1:0];
+            assign bin_temp[(i+1)*BIN_WIDTH-1 : i*BIN_WIDTH] = i[BIN_WIDTH-1: 0];
         end
-
-
         one_hot_mux #(
-            .IN_WIDTH   (MUX_IN_WIDTH),
-            .SEL_WIDTH  (ONE_HOT_WIDTH)
-            
-        )
-        one_hot_to_bcd_mux
-        (
-            .mux_in     (bin_temp),
-            .mux_out        (bin_code),
-            .sel            (one_hot_code)
-    
+            .IN_WIDTH (MUX_IN_WIDTH),
+            .SEL_WIDTH (ONE_HOT_WIDTH)
+        ) mux (
+            .mux_in (bin_temp),
+            .mux_out (bin_code),
+            .sel (one_hot_code)
         );
-     end else begin :els
-        assign  bin_code = one_hot_code;
-     
-     end
-
-endgenerate
-
+    end else begin :els
+        // assign  bin_code = one_hot_code;
+        assign  bin_code = 1'b0;
+    end
+    endgenerate
 endmodule
 
 
-
 /****************************************
-
-            binary_mux
-
+*     binary_mux
 ***************************************/
-
 module binary_mux #(
-        parameter   IN_WIDTH         =   20,
-        parameter   OUT_WIDTH       =   5
-    )
-    (
-        mux_in,
-        mux_out,
-        sel
-
-    );
-    
-  
-    function integer log2;
-      input integer number; begin   
-         log2=(number <=1) ? 1: 0;    
-         while(2**log2<number) begin    
-            log2=log2+1;    
-         end 	   
-      end   
-    endfunction // log2 
-
-     localparam  IN_NUM          =   IN_WIDTH/OUT_WIDTH,
-                 SEL_WIDTH_BIN   = (IN_NUM>1)?  log2(IN_NUM): 1; 
-                 
-                 
-    input   [IN_WIDTH-1         :0] mux_in;
-    output  [OUT_WIDTH-1        :0] mux_out;
-    input   [SEL_WIDTH_BIN-1    :0] sel;                 
+    parameter IN_WIDTH = 20,
+    parameter OUT_WIDTH = 5
+)(
+    mux_in,
+    mux_out,
+    sel
+);
+    localparam  
+        IN_NUM = IN_WIDTH / OUT_WIDTH,
+        SEL_WIDTH_BIN = (IN_NUM > 1) ? $clog2(IN_NUM) : 1; 
+    input   [IN_WIDTH-1 : 0] mux_in;
+    output  [OUT_WIDTH-1 : 0] mux_out;
+    input   [SEL_WIDTH_BIN-1 : 0] sel;                 
     genvar i;
-     
-    
-	generate 
-		if(IN_NUM>1) begin :if1
-			wire [OUT_WIDTH-1       :0] mux_in_2d [IN_NUM -1    :0];
-			for (i=0; i< IN_NUM; i=i+1) begin : loop
-				assign mux_in_2d[i] =mux_in[((i+1)*OUT_WIDTH)-1 :   i*OUT_WIDTH];   
-			end
-			assign mux_out = mux_in_2d[sel];		
-		end else  begin :els
-			assign mux_out = mux_in;			
-		end
-	endgenerate
-    
+    generate 
+        if(IN_NUM > 1) begin 
+            wire [OUT_WIDTH-1 : 0] mux_in_2d [IN_NUM -1 : 0];
+            for (i=0; i< IN_NUM; i=i+1) begin : loop
+                assign mux_in_2d[i] = mux_in[((i+1)*OUT_WIDTH)-1 : i*OUT_WIDTH];   
+            end
+            assign mux_out = mux_in_2d[sel];        
+        end else  begin 
+            assign mux_out = mux_in;            
+        end
+    endgenerate
 endmodule
 
 
-/******************************
-
-    set_bits_counter 
-
-*******************************/
-
-
-module set_bits_counter #(
-    parameter IN_WIDTH =120,
-    parameter OUT_WIDTH = log2(IN_WIDTH+1)
-    )
-    (
-    input   [IN_WIDTH-1         :   0]  in,
-    output  [OUT_WIDTH-1        :   0]  out
-    
+module  accumulator #(
+    parameter INw= 20,
+    parameter OUTw=4,
+    parameter NUM =5
+)(
+    in_all,
+    sum_o         
 );
-  
     function integer log2;
-      input integer number; begin   
-         log2=(number <=1) ? 1: 0;    
-         while(2**log2<number) begin    
+    input integer number; begin   
+        log2=(number <=1) ? 1: 0;    
+        while(2**log2<number) begin    
             log2=log2+1;    
-         end 	   
-      end   
+        end       
+    end   
     endfunction // log2 
-
     
-    wire    [IN_WIDTH-2     :   0]  addrin2;
-    wire    [OUT_WIDTH-1    :   0]  addrout [IN_WIDTH-2         :   0];
-    wire    [OUT_WIDTH-1    :   0]  addrin1 [IN_WIDTH-1         :   0];
-    
-    
-    assign out          = addrin1 [IN_WIDTH-1];
+    localparam 
+        N = INw/NUM,
+        SUMw = log2(NUM)+N; 
+    input [INw-1 : 0] in_all;
+    output[OUTw-1 : 0] sum_o;
     
+    wire [N-1 : 0] in [NUM-1 : 0];
+    reg [SUMw-1 : 0] sum;
     genvar i;
-    //always @(*)begin
-    assign  addrin1[0] = {{(OUT_WIDTH-1){1'b0}},in[0]};
-    generate        
-        for (i=0; i<IN_WIDTH-1; i=i+1) begin : loop
-                assign  addrin1[i+1]  = addrout[i];
-                assign  addrin2[i]    = in[i+1];
-                assign  addrout[i]    = addrin1[i] + addrin2 [i];
-        end
+    generate 
+    for (i=0; i<NUM; i=i+1)begin : lp
+        assign in[i] = in_all[(i+1)*N-1 : i*N];
+    end
+    
+    if(  SUMw == OUTw) begin : equal
+        assign sum_o = sum;
+    end else if(SUMw >  OUTw) begin : bigger
+        assign sum_o = (sum[SUMw-1 : OUTw] > 0 ) ? {OUTw{1'b1}} : sum[OUTw-1 : 0] ;
+    end else begin : less
+        assign sum_o = {{(OUTw-SUMw){1'b0}},  sum} ;
+    end
     endgenerate
-
+    // This is supposed to be synyhesized as "sum=in[0]+in[1]+...in[Num-1]"; 
+    // It works with Quartus, Verilator and Modelsim compilers  
+    integer k; 
+    always @(*)begin 
+        sum = {SUMw{1'b0}};
+        for (k=0;k<NUM;k=k+1)begin 
+            sum= sum + {{(SUMw-N){1'b0}},in[k]};
+        end
+    end
+    //In case your compiler could not synthesize or wrongly synthesizes it try this
+    //assumming the maximum NUM as parameter can be 20:
+    /*
+    generate 
+    wire [N-1 : 0] tmp [19 : 0];
+    for (i=0; i<NUM; i=i+1)begin : lp
+        assign tmp[i] = in_all[(i+1)*N-1 : i*N];    
+    end
+    for (i=NUM; i<20; i=i+1)begin : lp2
+        assign tmp[i] = {N{1'b0}};    
+    end
+    
+    always @(*)begin 
+            sum= tmp[0] + tmp[1]+ tmp[2] + ...+ tmp[19];        
+    end
+    endgenerate     
+    */
 endmodule
 
-
-
-
-
-
 /******************************
-
-    check_single_bit_assertation
-
+*    check_single_bit_assertation
 *******************************/
-
-
-module check_single_bit_assertation #(
+module is_onehot0 #(
     parameter IN_WIDTH =2
-    
-    )
-    (
-    input   [IN_WIDTH-1         :   0]  in,
+)(
+    input   [IN_WIDTH-1 : 0]  D_in,
     output  result
-    
-    );
-  
+);
     function integer log2;
-      input integer number; begin   
-         log2=(number <=1) ? 1: 0;    
-         while(2**log2<number) begin    
+    input integer number; begin   
+        log2=(number <=1) ? 1: 0;    
+        while(2**log2<number) begin    
             log2=log2+1;    
-         end 	   
-      end   
+        end        
+    end   
     endfunction // log2 
-
-
     
     localparam OUT_WIDTH = log2(IN_WIDTH+1);
-    
-    wire [OUT_WIDTH-1   :   0]  sum;
-    
-    parallel_counter #(
-        .IN_WIDTH (IN_WIDTH)
-    )counter
-    (
-        .in(in),
-        .out(sum)
+    wire [OUT_WIDTH-1 : 0]  sum;
+    
+    accumulator #(
+        .INw(IN_WIDTH),
+        .OUTw(OUT_WIDTH),
+        .NUM(IN_WIDTH)
+    ) accum (
+        .in_all(D_in),
+        .sum_o(sum)         
     );
-
     assign result = (sum <=1)? 1'b1: 1'b0;
-    
-    
 endmodule
 
 /**********************************
-
-fast_minimum_number
-
+*fast_minimum_number
 ***********************************/
-
-
 module fast_minimum_number#(
-    parameter NUM_OF_INPUTS     =   8,
-    parameter DATA_WIDTH            =   5,
-    parameter IN_ARRAY_WIDTH    =   NUM_OF_INPUTS   * DATA_WIDTH
-)
-(
-    input  [IN_ARRAY_WIDTH-1            :   0] in_array,
-    output [NUM_OF_INPUTS-1             :   0]  min_out
+    parameter NUM_OF_INPUTS = 8,
+    parameter DATA_WIDTH = 5,
+    parameter IN_ARRAY_WIDTH = NUM_OF_INPUTS   * DATA_WIDTH
+)(
+    input  [IN_ARRAY_WIDTH-1 : 0] in_array,
+    output [NUM_OF_INPUTS-1 : 0]  min_out
 );
 
     genvar i,j;
-    wire [DATA_WIDTH-1                  :   0]  numbers             [NUM_OF_INPUTS-1            :0];    
-    wire [NUM_OF_INPUTS-2               :   0]  comp_array          [NUM_OF_INPUTS-1            :0];    
-        
+    wire [DATA_WIDTH-1 : 0]  numbers             [NUM_OF_INPUTS-1 : 0];    
+    wire [NUM_OF_INPUTS-2 : 0]  comp_array          [NUM_OF_INPUTS-1 : 0];    
+    
     generate
     if(NUM_OF_INPUTS==1)begin:if1
         assign min_out = 1'b1;
     end
     else begin : els//(vc num >1)
         for(i=0; i<NUM_OF_INPUTS;  i=i+1) begin : loop_i
-                assign numbers[i]   = in_array  [(i+1)* DATA_WIDTH-1: i*DATA_WIDTH];
+                assign numbers[i] = in_array  [(i+1)* DATA_WIDTH-1: i*DATA_WIDTH];
                 for(j=0; j<NUM_OF_INPUTS-1;  j=j+1) begin : loop_j
                             if(i>j) begin :if1 assign comp_array [i][j] = ~ comp_array [j][i-1]; end
                             else   begin :els     assign comp_array [i]   [j] = numbers[i]<= numbers[j+1]; end
                 end//for j
-                assign min_out[i]=  & comp_array[i];
+                assign min_out[i]= & comp_array[i];
         end//for i
     end//else
     endgenerate
-    
-endmodule
-
-
-/********************************************
-
-        Carry-based reduction parallel counter
-
-
-********************************************/
-module parallel_counter  #(
-    parameter IN_WIDTH =120 // max 127
-)
-(
-    in,
-    out    
-);
-    
-    
-   
-    function integer log2;
-      input integer number; begin   
-         log2=(number <=1) ? 1: 0;    
-         while(2**log2<number) begin    
-            log2=log2+1;    
-         end 	   
-      end   
-    endfunction // log2 
-    
-  localparam OUT_WIDTH = log2(IN_WIDTH+1);
-  localparam PCIw      = (IN_WIDTH < 8   )? 7    :
-                         (IN_WIDTH < 16  )? 15   :
-                         (IN_WIDTH < 31  )? 31   :
-                         (IN_WIDTH < 36  )? 63   :   127;
-                         
-                         
-   localparam PCOw      = (IN_WIDTH < 8  )? 3   :
-                         (IN_WIDTH < 16  )? 4   :
-                         (IN_WIDTH < 31  )? 5   :
-                         (IN_WIDTH < 36  )? 6   :   7;                         
-  
-input   [IN_WIDTH-1         :   0]  in;
-output  [OUT_WIDTH-1        :   0]  out;
-     
-wire [PCIw-1    :   0]  pc_in;
-wire [PCOw-1    :   0]  pc_out;
-
-generate 
-    if(PCIw > IN_WIDTH ) begin :w1
-        assign   pc_in = {{(PCIw-IN_WIDTH){1'b0}},in};
-    end else begin:els
-         assign   pc_in=in;
-    end // if 
-    
-    if(PCIw == 7) begin :w7
-       
-        PC_7_3   pc (
-            .in(pc_in),
-            .out(pc_out)
-        );
-    
-    end else if(PCIw == 15) begin :w15
-          PC_15_4   pc (
-            .in(pc_in),
-            .out(pc_out)
-           );
-    
-    end else if(PCIw == 31) begin :w31
-        PC_31_5   pc (
-            .in(pc_in),
-            .out(pc_out)
-        );   
-    end else if(PCIw == 63) begin :w63
-         PC_63_6   pc (
-            .in(pc_in),
-            .out(pc_out)
-        );   
-    
-    end else  begin :w127
-         PC_127_7 pc (
-            .in(pc_in),
-            .out(pc_out)
-        );   
-    end
-    
- endgenerate
- 
- assign out = pc_out[OUT_WIDTH-1    :   0];
- 
 endmodule
 
 
 
-//carry-sum generation blocks
-module CS_GEN (
-    in,
-    abc,
-    s
-);
-    input   [6  :   0] in;
-    output  s;
-    output  [2  :   0] abc;
-    
-    wire      a,b,c,s;
-    wire    [3  :   0] in1;
-    wire    [2  :   0] in2;
-    wire    [2  :   0] j1;
-    wire    [1  :   0] j2;
-    
-    assign {in2,in1} =  in;
-    assign j1= in1[3]+in1[2]+in1[1]+in1[0];
-    assign j2= in2[2]+in2[1]+in2[0];
-    
-    //s is asserted when both in1 and in2 have odd number of ones.
-    assign s    = j1[0] ^ j2[0];
-    // a is asserted when there are at least two ones in in1 (i.e., j1 >= 2);
-    assign  a   =   (j1 >   3'd1);
-    
-    //b is asserted when there are at least two ones in in2 (i.e., j2 >= 2);
-    assign  b   =   (j2 >   2'd1);
-    
-    // C is asserted when when j1 equals 4 or when  s is asserted
-    assign c    =   (j1==4) | (j1[0] & j2[0]);
-
-    assign abc = {a,b,c};
-endmodule
-
-/*************************
- 
- (7,3) parallel counter
- 
-*************************/
-
-module PC_7_3 (
-    in,
-    out
-
-);
-    input   [6    : 0]  in;
-    output  [2    : 0]  out;
-    
-    wire    [2    : 0] abc;
-   
-    CS_GEN cs(
-        .in(in),
-        .abc(abc),
-        .s(out[0])
-    );
-   
-    assign out[2:1] = abc[2]+abc[1]+abc[0];  
-    
-  
-
-
-endmodule
-
-/*************************
-
-    (15,4) parallel counter
-    
-*************************/
-
-module PC_15_4 (
-    in,
-    out
-
-);
-    input   [14   : 0]  in;
-    output  [3    : 0]  out;
-    
-    wire    [2:0]   abc0,abc1;
-    wire            s0,s1,b2;
-   
-    CS_GEN cs0(
-        .in     (in  [6  :   0]),
-        .abc    (abc0),
-        .s      (s0)
-    );
-    
-     CS_GEN cs1(
-        .in     (in  [13  :   7]),
-        .abc    (abc1),
-        .s      (s1)
-    );
-    
-    assign {b2,out[0]}  =in  [14] + s0 +s1;
-    
-    PC_7_3 pc_sub(
-        .in({abc0,abc1,b2}),
-        .out(out[3:1])
-    );  
-    
-  
-
-
-endmodule
-
-
-// (31,5) parallel counter
-module PC_31_5 (
-    in,
-    out
-
-);
-    localparam CS_NUM   =   5;
-    
-    input   [30         : 0]  in;
-    output  [4          : 0]  out;
-    
-   
-    wire    [CS_NUM-1   : 0]   s;
-    wire    [(CS_NUM*7)-1   :   0]  cs_in;
-    wire    [14         :   0]  pc_15_in;
-    
-    assign cs_in ={s[3:0] ,in };
-    
-    genvar i;
-    generate 
-    for (i=0;i<CS_NUM;i=i+1) begin: lp    
-        CS_GEN cs(
-            .in     (cs_in     [(i+1)*7-1  :  i*7]),
-            .abc    (pc_15_in  [(i+1)*3-1  :  i*3]),
-            .s      (s      [i])
-        );
-        
-    end//for
-    endgenerate
-    
-    PC_15_4 pc_15(
-        .in    (pc_15_in ),
-        .out   (out[4:1])
-    );
-    
-    assign out[0] = s[4];
-    
- endmodule
-
-/*************************
- 
- (63,6) parallel counter
- 
-**************************/
-
-module PC_63_6 (
-    in,
-    out
-
-);
-    localparam CS_NUM   =   10;
-    
-    input   [62         : 0]  in;
-    output  [5          : 0]  out;
-    
-   
-    wire    [CS_NUM-1   : 0]   s;
-    wire    [(CS_NUM*7)-1   :   0]  cs_in;
-    wire    [30         : 0]  pc_31_in;
-    
-    assign cs_in ={s[7:0] ,in };
-    
-    genvar i;
-    generate 
-    for (i=0;i<CS_NUM;i=i+1) begin:lp    
-        CS_GEN cs(
-            .in     (cs_in     [(i+1)*7-1  :  i*7]),
-            .abc    (pc_31_in  [(i+1)*3-1  :  i*3]),
-            .s      (s      [i])
-        );
-        
-    end//for
-    endgenerate
-    
-    assign {pc_31_in[30],out[0]}    =   s[7]+s[8]+s[9];
-         
-    PC_31_5 pc_31(
-        .in(pc_31_in ),
-        .out(out[5:1])
-    );
- endmodule
-
-/*************************
-
- (127,7) parallel counter
-
-*************************/
-
-module PC_127_7 (
-    in,
-    out
-
+module start_delay_gen #(
+    parameter NC = 64 //number of cores
+)(
+    clk,
+    reset,
+    start_i,
+    start_o
 );
-    localparam CS_NUM   =   21;
-    
-    input   [126        : 0]  in;
-    output  [6          : 0]  out;
-    
-   
-    wire    [CS_NUM-1       : 0]   s;
-    wire    [(CS_NUM*7)-1   : 0]  cs_in;//147
-    wire    [62             : 0]  pc_63_in;
-    
-    assign cs_in ={s[19:0] ,in };
-    
-    genvar i;
+    input reset,clk,start_i;
+    output [NC-1 : 0] start_o;
+    reg start_i_reg;
+    wire start;
+    wire cnt_increase;
+    reg [NC-1 : 0] start_o_next;
+    reg [NC-1 : 0] start_o_reg;
+    
+    assign start= start_i_reg|start_i;
     generate 
-    for (i=0;i<CS_NUM;i=i+1) begin :lp   
-        CS_GEN cs(
-            .in     (cs_in     [(i+1)*7-1  :  i*7]),
-            .abc    (pc_63_in  [(i+1)*3-1  :  i*3]),
-            .s      (s      [i])
-        );
-        
-    end//for
+    if(NC > 2) begin :l1
+        always @(*)begin 
+            if(NC[0]==1'b0)begin // odd
+                start_o_next={start_o[NC-3: 0],start_o[NC-2],start};
+            end else begin //even
+                start_o_next={start_o[NC-3: 0],start_o[NC-1],start};
+            end    
+        end
+    end else begin :l2
+        always @(*) start_o_next = {NC{start}}; 
+    end
     endgenerate
     
-    assign {out[0]}    =   s[20];
-         
-    PC_63_6 pc63(
-        .in(pc_63_in),
-        .out(out[6:1])
-    );
-   
-    
- endmodule
-
-
-
-
-
+    reg [2: 0] counter;
+    assign cnt_increase=(counter==3'd0);
+    always @ (`pronoc_clk_reset_edge )begin 
+        if(`pronoc_reset)  begin             
+            start_o_reg <= {NC{1'b0}};
+            start_i_reg <= 1'b0;
+            counter <= 3'd0;
+        end else begin 
+            counter <= counter+3'd1;
+            start_i_reg <= start_i;
+            if(cnt_increase | start) start_o_reg <= start_o_next;
+            
+        end//reset
+    end //always
+    assign start_o=(cnt_increase | start)? start_o_reg : {NC{1'b0}};
+endmodule
+`endif
\ No newline at end of file
diff --git a/mpsoc/src_c/plot/parameter.v b/mpsoc/src_c/plot/parameter.v
index 01b9350..66b4001 100755
--- a/mpsoc/src_c/plot/parameter.v
+++ b/mpsoc/src_c/plot/parameter.v
@@ -12,7 +12,7 @@
  parameter COMBINATION_TYPE="BASELINE";
  parameter FIRST_ARBITER_EXT_P_EN=0;
  parameter TOPOLOGY="MESH";
- parameter ROUTE_NAME="XY";
+ parameter ROUTE_NAME="DOR";
  parameter CONGESTION_INDEX=3;
  parameter CLASS_CONFIG_NUM=0;
  parameter C0_p=100;
@@ -32,8 +32,8 @@
  parameter MAX_PCK_SIZ=10;
  parameter TIMSTMP_FIFO_NUM=64;
  parameter [V-1	:	0] ESCAP_VC_MASK=1;
- parameter ROUTE_TYPE = (ROUTE_NAME == "XY" || ROUTE_NAME == "TRANC_XY" || ROUTE_NAME == "TRANC")?    "DETERMINISTIC" : 
-			            (ROUTE_NAME == "DUATO" || ROUTE_NAME == "TRANC_DUATO" )?   "FULL_ADAPTIVE": "PAR_ADAPTIVE"; 
+ parameter ROUTE_TYPE = (ROUTE_NAME == "DOR" || ROUTE_NAME == "TRANC_DOR" || ROUTE_NAME == "TRANC")?    "DETERMINISTIC" : 
+			            (ROUTE_NAME == "FULL_ADPT" || ROUTE_NAME == "TRANC_FULL_ADPT" )?   "FULL_ADAPTIVE": "PAR_ADAPTIVE"; 
  parameter DEBUG_EN=0;
  parameter ROUTE_SUBFUNC= "NORTH_LAST";
  parameter AVC_ATOMIC_EN= 0;
diff --git a/mpsoc/src_c/synfull/traffic-generator/src/Makefile b/mpsoc/src_c/synfull/traffic-generator/src/Makefile
index d32dd29..b02034b 100644
--- a/mpsoc/src_c/synfull/traffic-generator/src/Makefile
+++ b/mpsoc/src_c/synfull/traffic-generator/src/Makefile
@@ -1,33 +1,35 @@
 # Makefile
-CPP    = g++ -std=gnu++0x -g
+CPP      = g++ -std=gnu++0x -g
 CPPFLAGS = -Wall -Wextra -pedantic -O2 -I. -Inetstream 
 
-PROG = tgen
-PROGDIR :=
-OBJDIR := obj
+PROG     = tgen
+PROGDIR  :=
+OBJDIR   = obj
 
-CPP_SRCS:=$(wildcard *.cpp)
-NET_SRCS:=$(wildcard netstream/*.cpp)
+CPP_SRCS := $(wildcard *.cpp)
+NET_SRCS := $(wildcard netstream/*.cpp)
+SRCS     := $(CPP_SRCS) $(NET_SRCS)
 
-OBJS :=  \
-	$(CPP_SRCS:%.cpp=${OBJDIR}/%.o)\
-	$(NET_SRCS:%.cpp=${OBJDIR}/%.o)\
+OBJS := $(SRCS:%.cpp=${OBJDIR}/%.o)
 
 #--- Make rules ---
 all: $(PROG)
- 
+
 $(PROG): $(OBJS)
-	$(CPP) $^ -o $(PROGDIR)$@	
-	ar -cr synful.a ./obj/*.o
+	$(CPP) $^ -o $(PROGDIR)$@
+	ar -cr synful.a $(OBJS)
 	cp synful.a ../../
 	cp synful.h ../../
 	cp ./tgen ../../../../script/synfull/tgen
-	rm -rf $(OBJDIR)
-	 
+
+# Pattern rule for building object files
 ${OBJDIR}/%.o: %.cpp
-	mkdir -p $(OBJDIR)/netstream
+	@mkdir -p $(dir $@)
 	$(CPP) $(CPPFLAGS) -c $< -o $@
-	
+
+# Clean rule
 clean:
 	rm -rf $(OBJDIR)
-	rm -f $(PROGDIR)$(PROG)
+	rm -f $(PROGDIR)$(PROG) synful.a
+
+.PHONY: all clean
diff --git a/mpsoc/src_verilator/histogram.h b/mpsoc/src_verilator/histogram.h
new file mode 100644
index 0000000..9a36356
--- /dev/null
+++ b/mpsoc/src_verilator/histogram.h
@@ -0,0 +1,110 @@
+#ifndef HISTOGRAM_H
+    #define HISTOGRAM_H
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+typedef struct {
+    int id;     // Histogram ID
+    int value;  // Histogram value
+    int* count; // Pointer to count
+} Entry;
+
+Entry* histogram = NULL;
+size_t histogram_size = 0;
+size_t histogram_capacity = 0;
+
+void record(int id,int number) {
+    // Search for the number
+    for (size_t i = 0; i < histogram_size; i++) {
+        if (histogram[i].value == number && histogram[i].id == id) {
+            (*(histogram[i].count)) += 1;
+            return;
+        }
+    }
+
+    // Not found — add a new entry
+    if (histogram_size == histogram_capacity) {
+        histogram_capacity = histogram_capacity == 0 ? 8 : histogram_capacity * 2;
+        histogram = (Entry*) realloc(histogram, histogram_capacity * sizeof(Entry));
+        if (!histogram) {
+            perror("realloc failed");
+            exit(1);
+        }
+    }
+    histogram[histogram_size].id = id;
+    histogram[histogram_size].value = number;
+    histogram[histogram_size].count = (int*) malloc(sizeof(int));
+    if (!histogram[histogram_size].count) {
+        perror("malloc failed");
+        exit(1);
+    }
+    *(histogram[histogram_size].count) = 1;
+    histogram_size++;
+}
+
+int compare_entries(const void* a, const void* b) {
+    const Entry* ea = (const Entry*)a;
+    const Entry* eb = (const Entry*)b;
+    return (ea->value - eb->value);
+}
+
+void print_histogram(int id, const char* title1, const char* title2) {
+    // Count how many entries match the histogram ID
+    size_t count = 0;
+    for (size_t i = 0; i < histogram_size; i++) {
+        if (histogram[i].id == id) {
+            count++;
+        }
+    }
+
+    if (count == 0) {
+        printf("Histogram ID %d not found.\n", id);
+        return;
+    }
+
+    // Copy matching entries into a temporary array
+    Entry* temp = (Entry*) malloc(count * sizeof(Entry));
+    if (!temp) {
+        perror("malloc failed");
+        exit(1);
+    }
+
+    size_t idx = 0;
+    for (size_t i = 0; i < histogram_size; i++) {
+        if (histogram[i].id == id) {
+            temp[idx++] = histogram[i];
+        }
+    }
+
+    // Sort the array by value
+    qsort(temp, count, sizeof(Entry), compare_entries);
+
+    // Print header
+    printf("%s", title1);
+    for (size_t i = 0; i < count; i++) {
+        printf("%d,", temp[i].value);
+    }
+
+    // Print counts
+    printf("%s", title2);
+    for (size_t i = 0; i < count; i++) {
+        printf("%d,", *(temp[i].count));
+    }
+
+    free(temp);
+}
+
+void cleanup_histogram() {
+    for (size_t i = 0; i < histogram_size; i++) {
+        free(histogram[i].count);
+    }
+    free(histogram);
+    histogram = NULL;
+    histogram_size = 0;
+    histogram_capacity = 0;
+}
+
+
+
+#endif // HISTOGRAM_H
diff --git a/mpsoc/src_verilator/netrace_lib.h b/mpsoc/src_verilator/netrace_lib.h
index 016e3ef..6eb74fc 100644
--- a/mpsoc/src_verilator/netrace_lib.h
+++ b/mpsoc/src_verilator/netrace_lib.h
@@ -48,74 +48,67 @@ unsigned int read_done=0;
 
 typedef struct queue_node queue_node_t;
 struct queue_node {
-	nt_packet_t* packet;
-	unsigned long long int cycle;
+    nt_packet_t* packet;
+    unsigned long long int cycle;
 };
 
 
 unsigned long long int calc_packet_timing( nt_packet_t* packet ) {
-	
-	int n_hops = abs( packet->src -  packet->dst );
-	if( n_hops <= 0 ) n_hops = 1;
-	return 3*n_hops;
+    
+    int n_hops = abs( packet->src -  packet->dst );
+    if( n_hops <= 0 ) n_hops = 1;
+    return 3*n_hops;
 }
 
 
 
 void netrace_init( char * tracefile){
-	int i=0;
-	nt_open_trfile( tracefile );
-	if( ignore_dependencies ) {
-		nt_disable_dependencies();
-		printf("\tDependencies is turned off in tracking cleared packets list\n");
-	}
-	if( reader_throttling ) {
-		printf("\treader throttling is enabled\n");
-	}
-	nt_print_trheader();
-	header = nt_get_trheader();
-	nt_seek_region( &header->regions[start_region] );
-	for(i = 0; i < start_region; i++ ) {
-		nt_cycle += header->regions[i].num_cycles;
-	}
-	if(nt_cycle){
-		printf("\tThe simulation start at region %u and %llu cycle\n",start_region,nt_cycle);
-		nt_start_cycle=nt_cycle;
-	}
-
-	waiting  = (queue_t**) malloc( NE * sizeof(queue_t*) );
-	inject   = (queue_t**) malloc( NE * sizeof(queue_t*) );
-	traverse = (queue_t**) malloc( NE * sizeof(queue_t*) );
-	if( (waiting == NULL) || (inject == NULL) || (traverse == NULL) ) {
-		printf( "ERROR: malloc fail queues\n" );
-		exit(0);
-	}
-
-	for( i = 0; i < NE; ++i ) {
-		waiting[i]  = queue_new();
-		inject[i]   = queue_new();
-		traverse[i] = queue_new();
-	}
-
-
-	if( !reader_throttling ) {
-		trace_packet = nt_read_packet();
-	} else if( !ignore_dependencies ) {
-		nt_init_self_throttling();
-	}
-
-	MIN_PACKET_SIZE = (8*8)/Fpay;
-	MAX_PACKET_SIZE = (64*8)/Fpay;
-	AVG_PACKET_SIZE=(MIN_PACKET_SIZE+MAX_PACKET_SIZE)/2;// average packet size
-	int p=(MAX_PACKET_SIZE-MIN_PACKET_SIZE)+1;
-	rsv_size_array = (unsigned int*) calloc ( p , sizeof(int));
-	if (rsv_size_array==NULL){
-		fprintf(stderr,"ERROR: cannot allocate (%d x int) memory for rsv_size_array. \n",p);
-		 exit(1);
-	}
-
-
-	if(verbosity==1) 	printf("\e[?25l"); //To hide the cursor:
+    int i=0;
+    nt_open_trfile( tracefile );
+    if( ignore_dependencies ) {
+        nt_disable_dependencies();
+        printf("\tDependencies is turned off in tracking cleared packets list\n");
+    }
+    if( reader_throttling ) {
+        printf("\treader throttling is enabled\n");
+    }
+    nt_print_trheader();
+    header = nt_get_trheader();
+    nt_seek_region( &header->regions[start_region] );
+    for(i = 0; i < start_region; i++ ) {
+        nt_cycle += header->regions[i].num_cycles;
+    }
+    if(nt_cycle){
+        printf("\tThe simulation start at region %u and %llu cycle\n",start_region,nt_cycle);
+        nt_start_cycle=nt_cycle;
+    }
+
+    waiting  = (queue_t**) malloc( NE * sizeof(queue_t*) );
+    inject   = (queue_t**) malloc( NE * sizeof(queue_t*) );
+    traverse = (queue_t**) malloc( NE * sizeof(queue_t*) );
+    if( (waiting == NULL) || (inject == NULL) || (traverse == NULL) ) {
+        printf( "ERROR: malloc fail queues\n" );
+        exit(0);
+    }
+
+    for( i = 0; i < NE; ++i ) {
+        waiting[i]  = queue_new();
+        inject[i]   = queue_new();
+        traverse[i] = queue_new();
+    }
+
+
+    if( !reader_throttling ) {
+        trace_packet = nt_read_packet();
+    } else if( !ignore_dependencies ) {
+        nt_init_self_throttling();
+    }
+
+    MIN_PACKET_SIZE = (8*8)/Fpay;
+    MAX_PACKET_SIZE = (64*8)/Fpay;
+    AVG_PACKET_SIZE=(MIN_PACKET_SIZE+MAX_PACKET_SIZE)/2;// average packet size
+    int p=(MAX_PACKET_SIZE-MIN_PACKET_SIZE)+1;
+    if(verbosity==1)     printf("\e[?25l"); //To hide the cursor:
 
 }
 
@@ -123,265 +116,265 @@ void netrace_init( char * tracefile){
 
 
 void netrace_eval(unsigned int eval_num){
-	int i;
-	unsigned int pronoc_src_id,pronoc_dst_id;
-
-	if((reset==reset_active_high) || (count_en==0))	return;
-
-	if((( nt_cycle > header->num_cycles) || (read_done==1 )) && nt_packets_left==0 )  simulation_done=1;
-
-	// Reset packets remaining check
-	nt_packets_left = 0;
-
-	// Get packets for this cycle
-	if((end_sim_pck_num == 0 ) || (end_sim_pck_num > nt_total_rd_pck )){
-		if( reader_throttling ) {
-			nt_packet_list_t* list;
-			for( list = nt_get_cleared_packets_list(); list != NULL; list = list->next ) {
-				if( list->node_packet != NULL ) {
-					trace_packet = list->node_packet;
-					queue_node_t* new_node = (queue_node_t*) nt_checked_malloc( sizeof(queue_node_t) );
-					new_node->packet = trace_packet;
-					new_node->cycle = (trace_packet->cycle > nt_cycle) ? trace_packet->cycle : nt_cycle;
-					pronoc_src_id=traffic_model_mapping[trace_packet->src];
-					queue_push( inject[pronoc_src_id], new_node, new_node->cycle );
-					nt_total_rd_pck++;
-				} else {
-					printf( "ERROR: Malformed packet list" );
-					exit(-1);
-				}
-			}
-			nt_empty_cleared_packets_list();
-		} else {
-			while( (trace_packet != NULL) && (trace_packet->cycle == nt_cycle) ) {
-				// Place in appropriate queue
-				queue_node_t* new_node = (queue_node_t*) nt_checked_malloc( sizeof(queue_node_t) );
-				new_node->packet = trace_packet;
-				new_node->cycle = (trace_packet->cycle > nt_cycle) ? trace_packet->cycle : nt_cycle;
-				pronoc_src_id=traffic_model_mapping[trace_packet->src];
-				if( ignore_dependencies || nt_dependencies_cleared( trace_packet ) ) {
-					// Add to inject queue
-					queue_push( inject[pronoc_src_id], new_node, new_node->cycle );
-					nt_total_rd_pck++;
-				} else {
-					// Add to waiting queue
-					queue_push( waiting[pronoc_src_id], new_node, new_node->cycle );
-					nt_total_rd_pck++;
-				}
-				// Get another packet from trace
-				trace_packet = nt_read_packet();
-			}
-			if( (trace_packet != NULL) && (trace_packet->cycle < nt_cycle) ) {
-				// Error check: Crash and burn
-				printf( "ERROR: Invalid trace_packet cycle time: %llu, current cycle: %llu\n", trace_packet->cycle, nt_cycle );
-				exit(-1);
-			}
-		}
-	}else {//if ~end_sim_pck_num
-		read_done=1;
-	}
-
-	if(eval_num<netrace_speed_up-1) {
-		nt_cycle++;
-		nt_packets_left=1;
-		return;
-	}
-
-
-	// Inject where possible (max one per node)
-	//header->num_nodes;
-	for( i = 0; i < NE; ++i ) {
-		nt_packets_left |= !queue_empty( inject[i] );
-		//TODO define sent vc policy
-		int sent_vc = 0;
-
-		if(pck_inj[i]->pck_injct_in_pck_wr){
-			//the wr_pck should be asserted only for single cycle
-			pck_inj[i]->pck_injct_in_pck_wr  	   = 0;
-			continue;
-		}
-
-		pck_inj[i]->pck_injct_in_pck_wr  	   = 0;
-		if((pck_inj[i]->pck_injct_out_ready & (0x1<<sent_vc)) == 0){
-			//This pck injector is not ready yet
-			continue;
-		}
-
-		queue_node_t* temp_node = (queue_node_t*) queue_peek_front( inject[i] );
-		if( temp_node != NULL ) {
-			packet = temp_node->packet;
-			if( (packet != NULL) && (temp_node->cycle <= nt_cycle) ) {
-
-				if(verbosity>1) {
-					printf( "Inject: %llu ", nt_cycle );
-					nt_print_packet( packet );
-				}
-				temp_node = (queue_node_t*) queue_pop_front( inject[i] );
-				temp_node->cycle = nt_cycle;//injection time
-				pronoc_dst_id =  traffic_model_mapping[packet->dst];
-				queue_push( traverse[pronoc_dst_id ], temp_node, temp_node->cycle );
-				long int ptr_addr = reinterpret_cast<long int> (temp_node);
-				int flit_num = (nt_get_packet_size(packet)* 8) / Fpay;
-				if(flit_num< pck_inj[i]->min_pck_size) flit_num = pck_inj[i]->min_pck_size;
-
-				if(IS_SELF_LOOP_EN ==0){
-					if(pronoc_dst_id == i ){
-						 fprintf(stderr,"ERROR: ProNoC is not configured with self-loop enable and Netrace aims to inject\n a "
-								 "packet with identical source and destination address. Enable the SELF_LOOP parameter\n"
-								 "in ProNoC and rebuild the simulation model\n");
-						 exit(1);
-					}
-				}
-				unsigned int sent_class =0;
-				pck_inj[i]->pck_injct_in_data         = ptr_addr;
-				pck_inj[i]->pck_injct_in_size         = flit_num;
-				pck_inj[i]->pck_injct_in_endp_addr    = endp_addr_encoder(pronoc_dst_id);
-				pck_inj[i]->pck_injct_in_class_num    = sent_class;
-				pck_inj[i]->pck_injct_in_init_weight  = 1;
-				pck_inj[i]->pck_injct_in_vc           = 0x1<<sent_vc;
-				pck_inj[i]->pck_injct_in_pck_wr  	   = 1;
-				total_sent_pck_num++;
-
-				#if (C>1)
-					sent_stat[i][sent_class].pck_num ++;
-					sent_stat[i][sent_class].flit_num +=flit_num;
-				#else
-					sent_stat[i].pck_num ++;
-					sent_stat[i].flit_num +=flit_num;
-				#endif
-			}
-		}
-	}
+    int i;
+    unsigned int pronoc_src_id,pronoc_dst_id;
+
+    if((reset==reset_active_high) || (count_en==0))    return;
+
+    if((( nt_cycle > header->num_cycles) || (read_done==1 )) && nt_packets_left==0 )  simulation_done=1;
+
+    // Reset packets remaining check
+    nt_packets_left = 0;
+
+    // Get packets for this cycle
+    if((end_sim_pck_num == 0 ) || (end_sim_pck_num > nt_total_rd_pck )){
+        if( reader_throttling ) {
+            nt_packet_list_t* list;
+            for( list = nt_get_cleared_packets_list(); list != NULL; list = list->next ) {
+                if( list->node_packet != NULL ) {
+                    trace_packet = list->node_packet;
+                    queue_node_t* new_node = (queue_node_t*) nt_checked_malloc( sizeof(queue_node_t) );
+                    new_node->packet = trace_packet;
+                    new_node->cycle = (trace_packet->cycle > nt_cycle) ? trace_packet->cycle : nt_cycle;
+                    pronoc_src_id=traffic_model_mapping[trace_packet->src];
+                    queue_push( inject[pronoc_src_id], new_node, new_node->cycle );
+                    nt_total_rd_pck++;
+                } else {
+                    printf( "ERROR: Malformed packet list" );
+                    exit(-1);
+                }
+            }
+            nt_empty_cleared_packets_list();
+        } else {
+            while( (trace_packet != NULL) && (trace_packet->cycle == nt_cycle) ) {
+                // Place in appropriate queue
+                queue_node_t* new_node = (queue_node_t*) nt_checked_malloc( sizeof(queue_node_t) );
+                new_node->packet = trace_packet;
+                new_node->cycle = (trace_packet->cycle > nt_cycle) ? trace_packet->cycle : nt_cycle;
+                pronoc_src_id=traffic_model_mapping[trace_packet->src];
+                if( ignore_dependencies || nt_dependencies_cleared( trace_packet ) ) {
+                    // Add to inject queue
+                    queue_push( inject[pronoc_src_id], new_node, new_node->cycle );
+                    nt_total_rd_pck++;
+                } else {
+                    // Add to waiting queue
+                    queue_push( waiting[pronoc_src_id], new_node, new_node->cycle );
+                    nt_total_rd_pck++;
+                }
+                // Get another packet from trace
+                trace_packet = nt_read_packet();
+            }
+            if( (trace_packet != NULL) && (trace_packet->cycle < nt_cycle) ) {
+                // Error check: Crash and burn
+                printf( "ERROR: Invalid trace_packet cycle time: %llu, current cycle: %llu\n", trace_packet->cycle, nt_cycle );
+                exit(-1);
+            }
+        }
+    }else {//if ~end_sim_pck_num
+        read_done=1;
+    }
+
+    if(eval_num<netrace_speed_up-1) {
+        nt_cycle++;
+        nt_packets_left=1;
+        return;
+    }
+
+
+    // Inject where possible (max one per node)
+    //header->num_nodes;
+    for( i = 0; i < NE; ++i ) {
+        nt_packets_left |= !queue_empty( inject[i] );
+        //TODO define sent vc policy
+        int sent_vc = 0;
+
+        if(pck_inj[i]->pck_injct_in_pck_wr){
+            //the wr_pck should be asserted only for single cycle
+            pck_inj[i]->pck_injct_in_pck_wr         = 0;
+            continue;
+        }
+
+        pck_inj[i]->pck_injct_in_pck_wr         = 0;
+        if((pck_inj[i]->pck_injct_out_ready & (0x1<<sent_vc)) == 0){
+            //This pck injector is not ready yet
+            continue;
+        }
+
+        queue_node_t* temp_node = (queue_node_t*) queue_peek_front( inject[i] );
+        if( temp_node != NULL ) {
+            packet = temp_node->packet;
+            if( (packet != NULL) && (temp_node->cycle <= nt_cycle) ) {
+
+                if(verbosity>1) {
+                    printf( "Inject: %llu ", nt_cycle );
+                    nt_print_packet( packet );
+                }
+                temp_node = (queue_node_t*) queue_pop_front( inject[i] );
+                temp_node->cycle = nt_cycle;//injection time
+                pronoc_dst_id =  traffic_model_mapping[packet->dst];
+                queue_push( traverse[pronoc_dst_id ], temp_node, temp_node->cycle );
+                long int ptr_addr = reinterpret_cast<long int> (temp_node);
+                int flit_num = (nt_get_packet_size(packet)* 8) / Fpay;
+                if(flit_num< pck_inj[i]->min_pck_size) flit_num = pck_inj[i]->min_pck_size;
+
+                if(SELF_LOOP_EN == 0){
+                    if(pronoc_dst_id == i ){
+                         fprintf(stderr,"ERROR: ProNoC is not configured with self-loop enable and Netrace aims to inject\n a "
+                                 "packet with identical source and destination address. Enable the SELF_LOOP parameter\n"
+                                 "in ProNoC and rebuild the simulation model\n");
+                         exit(1);
+                    }
+                }
+                unsigned int sent_class =0;
+                pck_inj[i]->pck_injct_in_data         = ptr_addr;
+                pck_inj[i]->pck_injct_in_size         = flit_num;
+                pck_inj[i]->pck_injct_in_endp_addr    = endp_addr_encoder(pronoc_dst_id);
+                pck_inj[i]->pck_injct_in_class_num    = sent_class;
+                pck_inj[i]->pck_injct_in_init_weight  = 1;
+                pck_inj[i]->pck_injct_in_vc           = 0x1<<sent_vc;
+                pck_inj[i]->pck_injct_in_pck_wr         = 1;
+                total_sent_pck_num++;
+
+                #if (C>1)
+                    sent_stat[i][sent_class].pck_num ++;
+                    sent_stat[i][sent_class].flit_num +=flit_num;
+                #else
+                    sent_stat[i].pck_num ++;
+                    sent_stat[i].flit_num +=flit_num;
+                #endif
+            }
+        }
+    }
 
 /*
-	// Step all network components, Eject where possible
-		for( i = 0; i < header->num_nodes; ++i ) {
-			nt_packets_left |= !queue_empty( traverse[i] );
-			queue_node_t* temp_node = (queue_node_t*) queue_peek_front( traverse[i] );
-			if( temp_node != NULL ) {
-				packet = temp_node->packet;
-				if( (packet != NULL) && (temp_node->cycle <= nt_cycle) ) {
-					printf( "Eject: %llu ", nt_cycle );
-					nt_print_packet( packet );
-					nt_clear_dependencies_free_packet( packet );
-					temp_node = (queue_node_t*) queue_pop_front( traverse[i] );
-					free( temp_node );
-				}
-			}
-		}
+    // Step all network components, Eject where possible
+        for( i = 0; i < header->num_nodes; ++i ) {
+            nt_packets_left |= !queue_empty( traverse[i] );
+            queue_node_t* temp_node = (queue_node_t*) queue_peek_front( traverse[i] );
+            if( temp_node != NULL ) {
+                packet = temp_node->packet;
+                if( (packet != NULL) && (temp_node->cycle <= nt_cycle) ) {
+                    printf( "Eject: %llu ", nt_cycle );
+                    nt_print_packet( packet );
+                    nt_clear_dependencies_free_packet( packet );
+                    temp_node = (queue_node_t*) queue_pop_front( traverse[i] );
+                    free( temp_node );
+                }
+            }
+        }
 */
 
-	// Step all network components, Eject where possible
-	for( i = 0; i < NE; ++i ) {
-		nt_packets_left |= !queue_empty( traverse[i] );
-		//check which pck injector got a packet
-		if(pck_inj[i]->pck_injct_out_pck_wr==0) continue;
-		//we have got a packet
-		//printf( "data=%lx\n",pck_inj[i]->pck_injct_out_data);
-
-		queue_node_t* temp_node = (queue_node_t*)  pck_inj[i]->pck_injct_out_data;
-		if( temp_node != NULL ) {
-			packet = temp_node->packet;
-			if( packet != NULL){
-				if(verbosity>1) {
-					printf( "Eject: %llu ", nt_cycle );
-					nt_print_packet( packet );
-				}
-				// remove from traverse
-				nt_clear_dependencies_free_packet( packet );
-				queue_remove( traverse[i], temp_node );
-				unsigned long long int    clk_num_h2t= (nt_cycle - temp_node->cycle)/netrace_speed_up;
-				unsigned int    clk_num_h2h= clk_num_h2t - pck_inj[i]->pck_injct_out_h2t_delay;
-				/*
-				printf("clk_num_h2t (%llu) h2t_delay(%u)\n", clk_num_h2t , pck_inj[i]->pck_injct_out_h2t_delay);
-				if(clk_num_h2t < pck_inj[i]->pck_injct_out_h2t_delay){
-					fprintf(stderr, "ERROR:clk_num_h2t (%llu) is smaller than  injector h2t_delay(%u)\n", clk_num_h2t , pck_inj[i]->pck_injct_out_h2t_delay);
-					exit(1);
-				}
-				*/
-
-				pronoc_src_id=traffic_model_mapping[packet->src];
-				total_rsv_pck_num++;
-				update_statistic_at_ejection (
-					i,//	core_num
-					clk_num_h2h, // clk_num_h2h,
-					(unsigned int) clk_num_h2t, // clk_num_h2t,
-					pck_inj[i]->pck_injct_out_distance, //    distance,
-					pck_inj[i]->pck_injct_out_class_num,//  	class_num,
-					pronoc_src_id,//		unsigned int 	src
-					pck_inj[i]->pck_injct_out_size
-				);
-
-				free( temp_node );
-
-			}
-		}
-	}
-		// Check for cleared dependences... or not
-		if( !reader_throttling ) {
-		for( i = 0; i < NE; ++i ) {
-			nt_packets_left |= !queue_empty( waiting[i] );
-			node_t* temp = waiting[i]->head;
-			while( temp != NULL ) {
-				queue_node_t* temp_node = (queue_node_t*) temp->elem;
-				packet = temp_node->packet;
-				temp = temp->next;
-				if( nt_dependencies_cleared( packet ) ) {
-					// remove from waiting
-					queue_remove( waiting[i], temp_node );
-					// add to inject
-					queue_node_t* new_node = (queue_node_t*) nt_checked_malloc( sizeof(queue_node_t) );
-					new_node->packet = packet;
-					new_node->cycle = nt_cycle + L2_LATENCY;
-					queue_push( inject[i], new_node, new_node->cycle );
-					free( temp_node );
-				}
-			}
-		}
-	}
-	nt_cycle++;
+    // Step all network components, Eject where possible
+    for( i = 0; i < NE; ++i ) {
+        nt_packets_left |= !queue_empty( traverse[i] );
+        //check which pck injector got a packet
+        if(pck_inj[i]->pck_injct_out_pck_wr==0) continue;
+        //we have got a packet
+        //printf( "data=%lx\n",pck_inj[i]->pck_injct_out_data);
+
+        queue_node_t* temp_node = (queue_node_t*)  pck_inj[i]->pck_injct_out_data;
+        if( temp_node != NULL ) {
+            packet = temp_node->packet;
+            if( packet != NULL){
+                if(verbosity>1) {
+                    printf( "Eject: %llu ", nt_cycle );
+                    nt_print_packet( packet );
+                }
+                // remove from traverse
+                nt_clear_dependencies_free_packet( packet );
+                queue_remove( traverse[i], temp_node );
+                unsigned long long int    clk_num_h2t= (nt_cycle - temp_node->cycle)/netrace_speed_up;
+                unsigned int    clk_num_h2h= clk_num_h2t - pck_inj[i]->pck_injct_out_h2t_delay;
+                /*
+                printf("clk_num_h2t (%llu) h2t_delay(%u)\n", clk_num_h2t , pck_inj[i]->pck_injct_out_h2t_delay);
+                if(clk_num_h2t < pck_inj[i]->pck_injct_out_h2t_delay){
+                    fprintf(stderr, "ERROR:clk_num_h2t (%llu) is smaller than  injector h2t_delay(%u)\n", clk_num_h2t , pck_inj[i]->pck_injct_out_h2t_delay);
+                    exit(1);
+                }
+                */
+
+                pronoc_src_id=traffic_model_mapping[packet->src];
+                total_rsv_pck_num++;
+                update_statistic_at_ejection (
+                    i,//    core_num
+                    clk_num_h2h, // clk_num_h2h,
+                    (unsigned int) clk_num_h2t, // clk_num_h2t,
+                    pck_inj[i]->pck_injct_out_distance, //    distance,
+                    pck_inj[i]->pck_injct_out_class_num,//      class_num,
+                    pronoc_src_id,//        unsigned int     src
+                    pck_inj[i]->pck_injct_out_size
+                );
+
+                free( temp_node );
+
+            }
+        }
+    }
+        // Check for cleared dependences... or not
+        if( !reader_throttling ) {
+        for( i = 0; i < NE; ++i ) {
+            nt_packets_left |= !queue_empty( waiting[i] );
+            node_t* temp = waiting[i]->head;
+            while( temp != NULL ) {
+                queue_node_t* temp_node = (queue_node_t*) temp->elem;
+                packet = temp_node->packet;
+                temp = temp->next;
+                if( nt_dependencies_cleared( packet ) ) {
+                    // remove from waiting
+                    queue_remove( waiting[i], temp_node );
+                    // add to inject
+                    queue_node_t* new_node = (queue_node_t*) nt_checked_malloc( sizeof(queue_node_t) );
+                    new_node->packet = packet;
+                    new_node->cycle = nt_cycle + L2_LATENCY;
+                    queue_push( inject[i], new_node, new_node->cycle );
+                    free( temp_node );
+                }
+            }
+        }
+    }
+    nt_cycle++;
 }
 
 
 void netrace_posedge_event(){
-	unsigned int i;
-	clk = 1;       // Toggle clock
-	update_all_router_stat();
-	for(i=0;i<netrace_speed_up; i++)  netrace_eval(i);
-	//connect_clk_reset_start_all();
-	sim_eval_all();
-	//print total sent packet each 1024 clock cycles
-	if(verbosity==1) if(nt_cycle&0x3FF) printf("\rTotal sent packet: %9d", total_sent_pck_num);
+    unsigned int i;
+    clk = 1;       // Toggle clock
+    update_all_router_stat();
+    for(i=0;i<netrace_speed_up; i++)  netrace_eval(i);
+    //connect_clk_reset_start_all();
+    sim_eval_all();
+    //print total sent packet each 1024 clock cycles
+    if(verbosity==1) if(nt_cycle&0x3FF) printf("\rTotal sent packet: %9d", total_sent_pck_num);
 }
 
 
 void netrace_negedge_event( ){
-	int i;
-	clk = 0;
-	topology_connect_all_nodes ();
-	//connect_clk_reset_start_all();
-	sim_eval_all();
+    int i;
+    clk = 0;
+    topology_connect_all_nodes ();
+    //connect_clk_reset_start_all();
+    sim_eval_all();
 }
 
 
 
 
 void netrace_final_report(){
-	int i;
-	unsigned int worst_sent=0, worst_rsv=0;
-	unsigned long long int total_clock = (nt_cycle-nt_start_cycle);
-	unsigned long long int pronoc_total_clock = total_clock/netrace_speed_up;
-
-	if(verbosity==1) 	printf("\e[?25h");//To re-enable the cursor:
-	printf("\nNetrace simulation results-------------------\n"
-			"\tNetrace end clock cycles: %llu\n"
-			"\tNetrace duration clock cycles: %llu\n"
-			"\tProNoC  duration clock cycles: %llu\n"
-			"\tSimulation clock cycles: %llu\n"
-	,nt_cycle,total_clock,pronoc_total_clock,pronoc_total_clock);
-
-	print_statistic_new (pronoc_total_clock);
-	printf("Netrace simulation results-------------------\n");
+    int i;
+    unsigned int worst_sent=0, worst_rsv=0;
+    unsigned long long int total_clock = (nt_cycle-nt_start_cycle);
+    unsigned long long int pronoc_total_clock = total_clock/netrace_speed_up;
+
+    if(verbosity==1)     printf("\e[?25h");//To re-enable the cursor:
+    printf("\nNetrace simulation results-------------------\n"
+            "\tNetrace end clock cycles: %llu\n"
+            "\tNetrace duration clock cycles: %llu\n"
+            "\tProNoC  duration clock cycles: %llu\n"
+            "\tSimulation clock cycles: %llu\n"
+    ,nt_cycle,total_clock,pronoc_total_clock,pronoc_total_clock);
+
+    print_statistic_new (pronoc_total_clock);
+    printf("Netrace simulation results-------------------\n");
 }
 
 
diff --git a/mpsoc/src_verilator/simulator.cpp b/mpsoc/src_verilator/simulator.cpp
index 2fd0c34..f773427 100755
--- a/mpsoc/src_verilator/simulator.cpp
+++ b/mpsoc/src_verilator/simulator.cpp
@@ -7,49 +7,41 @@
 #include <stdint.h>
 #include <inttypes.h>
 #include <verilated.h>          // Defines common routines
-
 #include "Vtraffic.h"
 #include "Vpck_inj.h"
 #include <thread>
 #include <vector>
 #include <atomic>
-
-
 #include <cstdint>
 #include <cstdlib>
 #include <iostream>
-
+#ifdef FLAT_MODE
+#include "Vnoc.h"
+#endif
 
 #include "simulator.h"
 
-
-
-
 int main(int argc, char** argv) {
     char change_injection_ratio=0;
     int i,j,x,y;//,report_delay_counter=0;
-
-    char deafult_out[] = {"result"};
+    char default_out[] = {"result"};
     NEw=Log2(NE);
     for(i=0;i<NE;i++)   custom_traffic_table[i]=INJECT_OFF; //off
     Verilated::commandArgs(argc, argv);   // Remember args
     processArgs ( argc,  argv );
-    allocate_rsv_pck_counters();
     if (class_percentage==NULL) {
             class_percentage =   (int *) malloc(sizeof(int));
             class_percentage[0]=100;
     }
-
-
+    #ifdef FLAT_MODE
+    noc_top = new Vnoc;
+    #else 
     Vrouter_new();
+    #endif
     if (ENDP_TYPE == PCK_INJECTOR)    for(i=0;i<NE;i++)    pck_inj[i]  = new Vpck_inj;
     else                            for(i=0;i<NE;i++)    traffic[i]  = new Vtraffic;
-
-
-
     FIXED_SRC_DST_PAIR = strcmp (TRAFFIC,"RANDOM") &  strcmp(TRAFFIC,"HOTSPOT") & strcmp(TRAFFIC,"random") & strcmp(TRAFFIC,"hot spot") & strcmp(TRAFFIC,"TASK");
-
-
+    
     /********************
     *    initialize input
     *********************/
@@ -57,12 +49,10 @@ int main(int argc, char** argv) {
     reset_active_high=1;
     reset_all_register();
     start_i=0;
-
+    
     mcast_init();
-
-
-
     topology_init();
+    
     if( TRAFFIC_TYPE == NETRACE){
         netrace_init(netrace_file); // should be called first to initiate header
         pck_inj_init((int)header->num_nodes);
@@ -72,19 +62,19 @@ int main(int argc, char** argv) {
         synful_init(synful_file,synful_SSExit,synful_random_seed,sim_end_clk_num,end_sim_pck_num);
     }
     else     traffic_gen_init();
-
-
-
+    
     main_time=0;
-    print_parameter();
     if( thread_num>1) initial_threads();
-
     while (!Verilated::gotFinish()) {
+        if(main_time == 1) print_parameter();
         if(main_time - saved_time < 50) {//set reset and start
+            #ifdef FLAT_MODE
+            reset_active_high = ((noc_top->router_event[0][0] & ACTIVE_HIGH_RST)!=0) ? 1 : 0;
+            #else
             reset_active_high = ((router1[0]->router_event[0] & ACTIVE_HIGH_RST)!=0) ? 1 : 0;
+            #endif
             if (main_time-saved_time >= 10 ) reset = (reset_active_high)? 0 :1;           
             else reset = reset_active_high;     ;//keep system in reset
-
             if(main_time == saved_time+21){ count_en=1; start_i=1;}
             if(main_time == saved_time+23) start_i=0;
         }
@@ -92,8 +82,6 @@ int main(int argc, char** argv) {
         if(TRAFFIC_TYPE==NETRACE) netrace_posedge_event();
         else if(TRAFFIC_TYPE ==SYNFUL) synful_posedge_event();
         else traffic_clk_posedge_event();
-
-
         //The valus of all registers and input ports valuse change @ posedge of the clock. Once clk is deasserted,  as multiple modules are connected inside the testbench we need several eval for propogating combinational logic values
         //between modules when the clock .
         for (i=0;i<SMART_MAX+2;i++) {
@@ -101,30 +89,24 @@ int main(int argc, char** argv) {
             else if(TRAFFIC_TYPE ==SYNFUL) synful_negedge_event();
             else traffic_clk_negedge_event( );
         }
-
         if(simulation_done){
-
             if( TRAFFIC_TYPE == NETRACE) netrace_final_report();
             else if(TRAFFIC_TYPE ==SYNFUL) synful_final_report();
             else traffic_gen_final_report();
             sim_final_all();
             return 0;
         }
-
         main_time++;
-
     }//Simulating is done
-
     sim_final_all();
     return 0;
-
 }
 
-
 #define __FILENAME__ (__FILE__ + SOURCE_PATH_SIZE)
 
 void  usage(char * bin_name){
-    printf("Usage:\n"
+    printf(
+"Usage:\n"
 " %s -t <synthetic Traffic Pattern name> [synthetic Traffic options]\n"
 " %s -f <Task file> [Task options]\n"
 " %s -F <netrace file> [Netrace options] \n"
@@ -196,79 +178,71 @@ bin_name,bin_name,bin_name,bin_name
 }
 
 
-
 void netrace_processArgs (int argc, char **argv )
 {
-   char c;
-
-   /* don't want getopt to moan - I can do that just fine thanks! */
-   opterr = 0;
-   if (argc < 2)  usage(argv[0]);
-   while ((c = getopt (argc, argv, "F:dr:lv:T:n:s:")) != -1)
-   {
-     switch (c)
-     {
-         case 'F':
-             TRAFFIC_TYPE=NETRACE;
-             TRAFFIC=(char *) "NETRACE";
-             ENDP_TYPE = PCK_INJECTOR;
-             netrace_file = optarg;
-             break;
-         case 'd':
-             ignore_dependencies=1;
-             break;
-         case 'r':
+    char c;    
+    opterr = 0;
+    if (argc < 2)  usage(argv[0]);
+    while ((c = getopt (argc, argv, "F:dr:lv:T:n:s:")) != -1)
+    {
+        switch (c)
+        {
+        case 'F':
+            TRAFFIC_TYPE=NETRACE;
+            TRAFFIC=(char *) "NETRACE";
+            ENDP_TYPE = PCK_INJECTOR;
+            netrace_file = optarg;
+            break;
+        case 'd':
+            ignore_dependencies=1;
+            break;
+        case 'r':
             start_region=atoi(optarg);
-             break;
-         case 'l':
-             reader_throttling=1;
-             break;
-         case 'v':
-             verbosity= atoi(optarg);
-             break;
-         case 'T':
+            break;
+        case 'l':
+            reader_throttling=1;
+            break;
+        case 'v':
+            verbosity= atoi(optarg);
+            break;
+        case 'T':
             thread_num = atoi(optarg);
             break;
-         case 'n':
-             end_sim_pck_num=atoi(optarg);
-             break;
-         case 's':
-             netrace_speed_up=atoi(optarg);
-
-             break;
-         case '?':
-             if (isprint (optopt))
-                 fprintf (stderr, "Unknown option `-%c'.\n", optopt);
-             else
-                 fprintf (stderr,  "Unknown option character `\\x%x'.\n",  optopt);
-         default:
-                usage(argv[0]);
-                exit(1);
-      }
+        case 'n':
+            end_sim_pck_num=atoi(optarg);
+            break;
+        case 's':
+            netrace_speed_up=atoi(optarg);        
+            break;
+        case '?':
+            if (isprint (optopt))
+                fprintf (stderr, "Unknown option `-%c'.\n", optopt);
+            else
+                fprintf (stderr,  "Unknown option character `\\x%x'.\n",  optopt);
+        default:
+            usage(argv[0]);
+            exit(1);
+        }
     }
 }
 
-
-
 void synthetic_task_processArgs (int argc, char **argv )
 {
-   char c;
-   int p;
-   int array[10];
-   float f;
-
-   /* don't want getopt to moan - I can do that just fine thanks! */
-   opterr = 0;
-   if (argc < 2)  usage(argv[0]);
-   while ((c = getopt (argc, argv, "t:m:n:c:i:p:h:H:f:T:u:Q")) != -1)
-      {
-     switch (c)
+    char c;
+    int p;
+    int array[10];
+    float f;
+    opterr = 0;
+    if (argc < 2)  usage(argv[0]);
+    while ((c = getopt (argc, argv, "t:m:n:c:i:p:h:H:f:T:u:Q")) != -1)
+    {
+        switch (c)
         {
-         case 'f':
-             TRAFFIC_TYPE=TASK;
-             TRAFFIC=(char *) "TASK";
-             task_traffic_init(optarg);
-             break;
+        case 'f':
+            TRAFFIC_TYPE=TASK;
+            TRAFFIC=(char *) "TASK";
+            task_traffic_init(optarg);
+            break;
         case 't':
             TRAFFIC=optarg;
             total_active_routers=-1;
@@ -277,16 +251,16 @@ void synthetic_task_processArgs (int argc, char **argv )
             MIN_PACKET_SIZE=atoi(optarg);
             break;
         case 'n':
-             end_sim_pck_num=atoi(optarg);
-             break;
+            end_sim_pck_num=atoi(optarg);
+            break;
         case 'c':
-             sim_end_clk_num=atoi(optarg);
-             break;
+            sim_end_clk_num=atoi(optarg);
+            break;
         case 'i':
-             f=atof(optarg);
-             f*=(MAX_RATIO/100);
-             ratio= (int) f;
-             break;
+            f=atof(optarg);
+            f*=(MAX_RATIO/100);
+            ratio= (int) f;
+            break;
         case 'p':
             p= parse_string (optarg, array);
             if (p==0) {
@@ -303,7 +277,6 @@ void synthetic_task_processArgs (int argc, char **argv )
             break;
         case 'm':
             update_pck_size(optarg);
-
             break;
         case 'H':
             update_custom_traffic(optarg);
@@ -324,69 +297,63 @@ void synthetic_task_processArgs (int argc, char **argv )
             update_mcast_traffic(optarg);
             break;
         case '?':
-           if (isprint (optopt))
-          fprintf (stderr, "Unknown option `-%c'.\n", optopt);
-           else
-          fprintf (stderr, "Unknown option character `\\x%x'.\n", optopt);
+            if (isprint (optopt))
+                fprintf (stderr, "Unknown option `-%c'.\n", optopt);
+            else
+                fprintf (stderr, "Unknown option character `\\x%x'.\n", optopt);
         default:
-           usage(argv[0]);
-           exit(1);
+            usage(argv[0]);
+            exit(1);
         }
-      }
+    }
 }
 
-
-
-
 void synful_processArgs (int argc, char **argv)
 {
-   char c;
-   /* don't want getopt to moan - I can do that just fine thanks! */
-   opterr = 0;
-   if (argc < 2)  usage(argv[0]);
-   while ((c = getopt (argc, argv, "S:c:sn:v:T:r:w:")) != -1)
-   {
-     switch (c)
-     {
-         case 'S':
-             TRAFFIC_TYPE=SYNFUL;
-             TRAFFIC=(char *) "SYNFUL";
-             synful_file = optarg;
-             ENDP_TYPE   =PCK_INJECTOR;
-             break;
-         case 'c':
-             sim_end_clk_num=atoi(optarg);
-             break;
-         case 's':
-             synful_SSExit =true;
-             break;
-         case 'n':
-             end_sim_pck_num=atoi(optarg);
-             break;
-         case 'v':
-              verbosity= atoi(optarg);
-              break;
-         case 'w':
-              synful_flitw= atoi(optarg);
-              break;
-         case 'T':
-             thread_num = atoi(optarg);
-             break;
-         case 'r':
-             synful_random_seed = atoi(optarg);
-             break;
-         case '?':
-             if (isprint (optopt)) fprintf (stderr, "Unknown option `-%c'.\n", optopt);
-             else fprintf (stderr, "Unknown option character `\\x%x'.\n", optopt);
-         default:
-              usage(argv[0]);
-              exit(1);
-     }//switch
-   }//while
+    char c;   
+    opterr = 0;
+    if (argc < 2)  usage(argv[0]);
+    while ((c = getopt (argc, argv, "S:c:sn:v:T:r:w:")) != -1)
+    {
+        switch (c)
+        {
+        case 'S':
+            TRAFFIC_TYPE=SYNFUL;
+            TRAFFIC=(char *) "SYNFUL";
+            synful_file = optarg;
+            ENDP_TYPE   =PCK_INJECTOR;
+            break;
+        case 'c':
+            sim_end_clk_num=atoi(optarg);
+            break;
+        case 's':
+            synful_SSExit =true;
+            break;
+        case 'n':
+            end_sim_pck_num=atoi(optarg);
+            break;
+        case 'v':
+            verbosity= atoi(optarg);
+            break;
+        case 'w':
+            synful_flitw= atoi(optarg);
+            break;
+        case 'T':
+            thread_num = atoi(optarg);
+            break;
+        case 'r':
+            synful_random_seed = atoi(optarg);
+            break;
+        case '?':
+            if (isprint (optopt)) fprintf (stderr, "Unknown option `-%c'.\n", optopt);
+            else fprintf (stderr, "Unknown option character `\\x%x'.\n", optopt);
+        default:
+            usage(argv[0]);
+            exit(1);
+        }//switch
+    }//while
 }
 
-
-
 int parse_string ( char * str, int * array)
 {
     int i=0;
@@ -398,27 +365,20 @@ int parse_string ( char * str, int * array)
         i++;
         pt = strtok (NULL, ",");
     }
-   return i;
+    return i;
 }
 
-
-
-
-
-
 unsigned int pck_dst_gen_unicast (     unsigned int core_num, unsigned char * inject_en) {
     if(TRAFFIC_TYPE==TASK)    return      pck_dst_gen_task_graph ( core_num, inject_en);
-    if((strcmp (TOPOLOGY,"MESH")==0)||(strcmp (TOPOLOGY,"TORUS")==0))    return  pck_dst_gen_2D (core_num, inject_en);
-    return pck_dst_gen_1D (core_num, inject_en);
+    return  pck_dst_gen_synthetic   (core_num, inject_en);
 }
 
-
 void mcast_full_rnd (unsigned int core_num){
     unsigned int rnd;
     int a;
     for(;;)  {
         DEST_ADDR_ASSIGN_RAND(traffic[core_num]->dest_e_addr);
-        if((strcmp (SELF_LOOP_EN,"NO")==0)) DEST_ADDR_BIT_CLR(traffic[core_num]->dest_e_addr,core_num);
+        if(SELF_LOOP_EN==0) DEST_ADDR_BIT_CLR(traffic[core_num]->dest_e_addr,core_num);
         DEST_ADDR_IS_ZERO(a,traffic[core_num]->dest_e_addr);
         //rnd = rand() & ~(0x1<<core_num);
         //rnd &= ((1<<NE) -1);
@@ -427,7 +387,6 @@ void mcast_full_rnd (unsigned int core_num){
     }
 }
 
-
 void mcast_partial_rnd (unsigned int core_num){
     unsigned int rnd;int a;
     //printf("m[%d]=%d\n",core_num,mcast_list_array[core_num]);
@@ -437,7 +396,7 @@ void mcast_partial_rnd (unsigned int core_num){
         for(;;){
             DEST_ADDR_ASSIGN_RAND(traffic[core_num]->dest_e_addr);
             DEST_ADDR_BIT_CLR(traffic[core_num]->dest_e_addr,0);
-            if((strcmp (SELF_LOOP_EN,"NO")==0))    DEST_ADDR_BIT_CLR(traffic[core_num]->dest_e_addr,self_node_addr);
+            if(SELF_LOOP_EN==0)    DEST_ADDR_BIT_CLR(traffic[core_num]->dest_e_addr,self_node_addr);
             //rnd = rand() & ~((0x1<<(self_node_addr+1))|0x1); // generate a random multicast destination. remove the current node flag and unicast_flag from destination list
             //rnd &= ((1<<(MCAST_PRTLw+1)) -1);
             //printf("rnd=%d\n",rnd);
@@ -457,15 +416,11 @@ void mcast_partial_rnd (unsigned int core_num){
         }
     }
 //this function should not come here
-
 }
 
-
-
-
 void pck_dst_gen (     unsigned int core_num, unsigned char * inject_en) {
     unsigned int dest = pck_dst_gen_unicast (core_num, inject_en);
-//    printf("inject_en=%u, core_num=%u, dest=%u\n",*inject_en, core_num,dest);
+    // printf("inject_en=%u, core_num=%u, dest=%u\n",*inject_en, core_num,dest);
     if(IS_UNICAST){
         traffic[core_num]->dest_e_addr= dest;
         return;
@@ -473,14 +428,12 @@ void pck_dst_gen (     unsigned int core_num, unsigned char * inject_en) {
     else if (*inject_en==0) return;
     //multicast
     DEST_ADDR_ASSIGN_ZERO(traffic[core_num]->dest_e_addr);//reset traffic[core_num]->dest_e_addr
-
     unsigned int dest_id = endp_addr_decoder (dest);
     //*inject_en = dest_id !=core_num;
-
     unsigned int rnd = rand() % 100; // 0~99
     if(rnd >= mcast.ratio){
         //send a unicast packet
-        if((strcmp (SELF_LOOP_EN,"NO")==0) && dest_id==core_num){
+        if(SELF_LOOP_EN==0 && dest_id==core_num){
             *inject_en=0;
             return;
         }
@@ -495,7 +448,6 @@ void pck_dst_gen (     unsigned int core_num, unsigned char * inject_en) {
         return;
     }
     traffic[core_num]->pck_size_in=rnd_between(mcast.min,mcast.max);
-
     if (IS_MCAST_FULL) {
         mcast_full_rnd (core_num);
         return;
@@ -504,43 +456,40 @@ void pck_dst_gen (     unsigned int core_num, unsigned char * inject_en) {
         mcast_partial_rnd(core_num);
         return;
     }
-
     return; //IS_BCAST_FULL | IS_BCAST_PARTIAL  traffic[core_num]->dest_e_addr=0;
 }
 
-
-
 void update_hotspot(char * str){
-     int i;
-     int array[1000];
-     int p;
-     int acuum=0;
-     hotspot_st * new_node;
-     p= parse_string (str, array);
-     if (p<4){
-            fprintf(stderr,"ERROR: in hotspot traffic parameters. 4 value should be given as hotspot parameter\n");
-            exit(1);
-     }
-     HOTSPOT_NUM=array[0];
-     if (p<1+HOTSPOT_NUM*3){
-            fprintf(stderr,"ERROR: in hotspot traffic parameters \n");
-            exit(1);
-     }
-     new_node =  (hotspot_st *) malloc( HOTSPOT_NUM * sizeof(hotspot_st));
-     if( new_node == NULL){
-         fprintf(stderr,"ERROR: cannot allocate memory for hotspot traffic\n");
-           exit(1);
-        }
-     for (i=1;i<3*HOTSPOT_NUM; i+=3){
+    int i;
+    int array[1000];
+    int p;
+    int acuum=0;
+    hotspot_st * new_node;
+    p= parse_string (str, array);
+    if (p<4){
+        fprintf(stderr,"ERROR: in hotspot traffic parameters. 4 value should be given as hotspot parameter\n");
+        exit(1);
+    }
+    HOTSPOT_NUM=array[0];
+    if (p<1+HOTSPOT_NUM*3){
+        fprintf(stderr,"ERROR: in hotspot traffic parameters \n");
+        exit(1);
+    }
+    new_node =  (hotspot_st *) malloc( HOTSPOT_NUM * sizeof(hotspot_st));
+    if( new_node == NULL){
+        fprintf(stderr,"ERROR: cannot allocate memory for hotspot traffic\n");
+        exit(1);
+    }
+    for (i=1;i<3*HOTSPOT_NUM; i+=3){
         new_node[i/3]. ip_num = array[i];
         new_node[i/3]. send_enable=array[i+1];
         new_node[i/3]. percentage =  acuum + array[i+2];
         acuum= new_node[i/3]. percentage;    
-     }
-     if(acuum> 1000){
-             printf("Warning: The hotspot traffic summation %f exceed than 100 percent.  \n", (float) acuum /10);
-     }
-     hotspots=new_node;
+    }
+    if(acuum> 1000){
+        printf("Warning: The hotspot traffic summation %f exceed than 100 percent.  \n", (float) acuum /10);
+    }
+    hotspots=new_node;
 }
 
 void  update_mcast_traffic(char * str){
@@ -552,12 +501,9 @@ void  update_mcast_traffic(char * str){
     if(p>0)    mcast.ratio =array[0];
     if(p>1)    mcast.min =array[1];
     if(p>2)    mcast.max =array[2];
-
     if (mcast.ratio > 100)       { printf("ERROR: The given multicast traffic ratio (%d) is larger than 100\n",mcast.ratio);     exit(1);}
     if (mcast.min < MIN_PCK_SIZE){ printf("ERROR: The given multicast minimum packet size (%d) is larger than %d minimum packet size supported by the NoC\n",mcast.min, MIN_PCK_SIZE);     exit(1);}
     if (mcast.max > max_valid)   { printf("ERROR: The given multicast maximum packet size (%d) is larger than %d maximum router buffer size\n",mcast.max, max_valid);     exit(1);};
-
-
 }
 
 void update_custom_traffic (char * str){
@@ -578,8 +524,6 @@ void update_pck_size(char *str){
     char *pt,*pt2;
     MIN_PACKET_SIZE=100000;
     MAX_PACKET_SIZE=1;
-
-
     pt = strtok (str,",");
     if(*pt=='R'){//random range
         p= parse_string (str+2, array);
@@ -587,7 +531,6 @@ void update_pck_size(char *str){
             fprintf(stderr,"ERROR: Wrong Packet size format %s. It should be \"R,min,max\" : \n",str);
             exit(1);
         }
-
         MIN_PACKET_SIZE=array[0];
         MAX_PACKET_SIZE=array[1];
         AVG_PACKET_SIZE=(MIN_PACKET_SIZE+MAX_PACKET_SIZE)/2;// average packet size
@@ -613,49 +556,32 @@ void update_pck_size(char *str){
             printf("ERROR: Memory not allocated.\n");
             exit(1);
         }
-
         for (i=0; i<p; i++){
-
             //printf("I[%u]=%u,\n",i,array[i]);
             discrete_size[i] = array[i];
             if(MIN_PACKET_SIZE > array[i]) MIN_PACKET_SIZE = array[i];
             if(MAX_PACKET_SIZE < array[i]) MAX_PACKET_SIZE = array[i];
         }
-
         p= parse_string (pt2+1, array);
         int sum=0;
         AVG_PACKET_SIZE=0;
         for (i=0; i<p; i++){
             //printf("P[%u]=%u,\n",i,array[i]);
             if(i<in){
-                 sum+=array[i];
-                 discrete_prob[i]=sum;
-                 AVG_PACKET_SIZE+=discrete_size[i] * array[i];
-
+                sum+=array[i];
+                discrete_prob[i]=sum;
+                AVG_PACKET_SIZE+=discrete_size[i] * array[i];
             }
         }
         AVG_PACKET_SIZE/=100;
-
         if(sum!=100){
             fprintf(stderr,"ERROR: The accumulatio of the first %u probebility values is %u which is not equal to 100\n",in,sum);
             exit(1);
         }
-
     }else {
         fprintf(stderr,"ERROR: Wrong Packet size format %s. It should start with one of \"D\" or \"R\" letter\n",str);
         exit(1);
     }
-
-
-}
-
-void allocate_rsv_pck_counters (void) {
-    int p=(MAX_PACKET_SIZE-MIN_PACKET_SIZE)+1;
-    rsv_size_array = (unsigned int*) calloc ( p , sizeof(int));
-    if (rsv_size_array==NULL){
-         fprintf(stderr,"ERROR: cannot allocate memory for rsv_size_array\n");
-         exit(1);
-    }
 }
 
 
@@ -665,27 +591,14 @@ void task_traffic_init (char * str) {
     MIN_PACKET_SIZE = task_graph_min_pck_size;
     MAX_PACKET_SIZE = task_graph_max_pck_size;
     AVG_PACKET_SIZE=(MIN_PACKET_SIZE+MAX_PACKET_SIZE)/2;// average packet size
-    int p=(MAX_PACKET_SIZE-MIN_PACKET_SIZE)+1;
-    rsv_size_array = (unsigned int*) calloc ( p , sizeof(int));
-    if (rsv_size_array==NULL){
-        fprintf(stderr,"ERROR: cannot allocate (%d x int) memory for rsv_size_array. \n",p);
-        exit(1);
-    }
+    int p=(MAX_PACKET_SIZE-MIN_PACKET_SIZE)+1;    
 }
 
-
-
-
-
-
-
 void processArgs (int argc, char **argv ){
     int i;
-
     mcast.ratio=50;
     mcast.min= MIN_PCK_SIZE;
     mcast.max= (B > LB)? LB : B;
-
     for( i = 1; i < argc; ++i ) {
         if( strcmp(argv[i], "-t") == 0 ) {
             synthetic_task_processArgs ( argc, argv );
@@ -693,7 +606,6 @@ void processArgs (int argc, char **argv ){
         } else if( strcmp(argv[i], "-f") == 0 ) {
             synthetic_task_processArgs ( argc, argv );
             return;
-
         } else if( strcmp(argv[i], "-F") == 0 ) {
             netrace_processArgs (argc, argv );
             return;
@@ -707,101 +619,78 @@ void processArgs (int argc, char **argv ){
     exit(1);
 }
 
-
 int get_new_pck_size(){
-        if(pck_size_sel ==  RANDOM_discrete){
-                int rnd = rand() % 100; // 0~99
-                int i=0;
-                while( rnd > discrete_prob[i] ) i++;
-                return discrete_size [i];
-        }
-        //random range
-        return rnd_between(MIN_PACKET_SIZE,MAX_PACKET_SIZE);
+    if(pck_size_sel ==  RANDOM_discrete){
+        int rnd = rand() % 100; // 0~99
+        int i=0;
+        while( rnd > discrete_prob[i] ) i++;
+        return discrete_size [i];
+    }
+    //random range
+    return rnd_between(MIN_PACKET_SIZE,MAX_PACKET_SIZE);
 }
 
-
-
-
-
-
 void traffic_gen_final_report(){
     int i;
     for (i=0;i<NE;i++) if(traffic[i]->pck_number>0) total_active_endp       =     total_active_endp +1;
     printf("\nsimulation results-------------------\n");
     printf("\tSimulation clock cycles:%d\n",clk_counter);
-    printf("\n\tTotal received packet in different size:\n");
-    printf("\tflit_size,");
-    for (i=0;i<=(MAX_PACKET_SIZE - MIN_PACKET_SIZE);i++){
-        if(rsv_size_array[i]>0) printf("%u,",i+ MIN_PACKET_SIZE);
-    }
-    printf("\n\t#pck,");
-    for (i=0;i<=(MAX_PACKET_SIZE - MIN_PACKET_SIZE);i++){
-           if(rsv_size_array[i]>0) printf("%u,",rsv_size_array[i]);
-    }
-    printf("\n");
-
-//    printf(" total received flits:%d\n",total_rsv_flit_number);
-//    printf(" total sent flits:%d\n",total_sent_flit_number);
     print_statistic_new (clk_counter);
-
 }
 
-
 void traffic_gen_init( void ){
     int i;
     unsigned int dest_e_addr;
     for (i=0;i<NE;i++){
-            unsigned char inject_en;
-            random_var[i] = 100;
-            traffic[i]->current_e_addr        = endp_addr_encoder(i);
-            traffic[i]->start=0;
-            traffic[i]->pck_class_in=  pck_class_in_gen( i);
-            traffic[i]->pck_size_in=get_new_pck_size();
-            pck_dst_gen (i, &inject_en);
-            //traffic[i]->dest_e_addr= dest_e_addr;
-            if(inject_en == 0) traffic[i]->stop=1;
-            //printf("src=%u, des_eaddr=%x, dest=%x\n", i,dest_e_addr, endp_addr_decoder(dest_e_addr));
-            if(inject_done) traffic[i]->stop=1;
-            traffic[i]->start_delay=rnd_between(10,500);
-            if(TRAFFIC_TYPE==SYNTHETIC){
-                //traffic[i]->avg_pck_size_in=AVG_PACKET_SIZE;
-                traffic[i]->ratio=ratio;
-                traffic[i]->init_weight=1;
-            }
+        unsigned char inject_en;
+        random_var[i] = 100;        
+        traffic[i]->current_e_addr        = endp_addr_encoder(i);
+        traffic[i]->start=0;
+        traffic[i]->pck_class_in=  pck_class_in_gen( i);
+        traffic[i]->pck_size_in=get_new_pck_size();
+        pck_dst_gen (i, &inject_en);
+        //traffic[i]->dest_e_addr= dest_e_addr;
+        if(inject_en == 0) traffic[i]->stop=1;
+        //printf("src=%u, des_eaddr=%x, dest=%x\n", i,dest_e_addr, endp_addr_decoder(dest_e_addr));
+        if(inject_done) traffic[i]->stop=1;
+        traffic[i]->start_delay=rnd_between(10,500);
+        if(TRAFFIC_TYPE==SYNTHETIC){
+            //traffic[i]->avg_pck_size_in=AVG_PACKET_SIZE;
+            traffic[i]->ratio=ratio;
+            traffic[i]->init_weight=1;
+        }
     }
 }
 
 void pck_inj_init (int model_node_num){
     int i,tmp;
     for (i=0;i<NE;i++){
-           pck_inj[i]->current_e_addr        = endp_addr_encoder(i);
-           pck_inj[i]->pck_injct_in_ready= (0x1<<V)-1;
-           pck_inj[i]->pck_injct_in_pck_wr=0;
+        pck_inj[i]->current_e_addr        = endp_addr_encoder(i);
+        pck_inj[i]->pck_injct_in_ready= (0x1<<V)-1;
+        pck_inj[i]->pck_injct_in_pck_wr=0;
     }
     std::cout << "Node mapping---------------------" << std::endl;
     std::cout << "\tMapping " << model_node_num << " " << TRAFFIC  << " Nodes to " << NE << " ProNoC Nodes" << std::endl;
     std::cout << "\t" << TRAFFIC  << "\tID \t<-> ProNoC ID "<< std::endl;
     traffic_model_mapping = (int *) malloc( model_node_num * sizeof(int));
     for (i=0;i<model_node_num;i++){
-    //TODO mapping should be done according to number of NE and should be set by the user later
-               if(NE<=model_node_num){
-                   // we have less or equal number of injectors in traffic model thatn the number of modes in ProNoC
-                   // So we need to map multiples injector nodes from the model to one packet injector
-                   tmp = ((i* NE)/model_node_num);
-                   traffic_model_mapping[i]=tmp;
-               } else {
-                   // we have more endpoints that what is defined in the model
-                   if(i<model_node_num) traffic_model_mapping[i]=i;
-               }
-               std::cout<< "\t\t" << i << "\t<->\t"  << tmp << std::endl;
-
+        //TODO mapping should be done according to number of NE and should be set by the user later
+        if(NE<=model_node_num){
+            // we have less or equal number of injectors in traffic model thatn the number of modes in ProNoC
+            // So we need to map multiples injector nodes from the model to one packet injector
+            tmp = ((i* NE)/model_node_num);
+            traffic_model_mapping[i]=tmp;
+        } else {
+            // we have more endpoints that what is defined in the model
+            if(i<model_node_num) traffic_model_mapping[i]=i;
+        }
+        std::cout<< "\t\t" << i << "\t<->\t"  << tmp << std::endl;
     }
     std::cout << "Node mapping---------------------" << std::endl;
 }
 
 /*************
  * sc_time_stamp
- *
  * **********/
 double sc_time_stamp () {       // Called by $time in Verilog
     return main_time;
@@ -817,7 +706,6 @@ int pow2( int num){
 volatile int *  lock;
 unsigned int  nr_per_thread=0;
 unsigned int  ne_per_thread=0;
-
 void thread_function (int n){
     int i;
     unsigned int node=0;
@@ -834,11 +722,9 @@ void thread_function (int n){
             if( TRAFFIC_TYPE == NETRACE)   pck_inj[node]->eval();
             else   traffic[node]->eval();
         }
-
         //router1[n]->eval();
         //if( TRAFFIC_TYPE == NETRACE)   pck_inj[n]->eval();
         //else   traffic[n]->eval();
-
         lock[n]=0;
         if(n==0) break;//first thread is the main process
     }
@@ -858,8 +744,6 @@ class alignas(64) Vthread
     int ne_per_thread;
     // Member Functions()
     //Parameterized Constructor
-
-
     void function ( ){
         int i;
         unsigned int node=0;
@@ -880,13 +764,19 @@ class alignas(64) Vthread
                         traffic[node]->clk    = clk;
                     }
                 }//endp
+                #ifdef FLAT_MODE
+                if(n==0){//
+                    noc_top->reset= reset;
+                    noc_top->clk  = clk;
+                    noc_top->eval();
+                }
+                #else 
                 for(i=0;i<nr_per_thread;i++){
                     node= (n * nr_per_thread)+i;
                     if (node >= NR) break;
                     //if(router_is_active[node] | (Quick_sim_en==0))
                     single_router_reset_clk(node);
                 }
-
                 //eval
                 for(i=0;i<nr_per_thread;i++){
                     node= (n * nr_per_thread)+i;
@@ -894,6 +784,7 @@ class alignas(64) Vthread
                     //if(router_is_active[node] | (Quick_sim_en==0))
                     single_router_eval(node);
                 }
+                #endif
                 for(i=0;i<ne_per_thread;i++){
                     node= (n * ne_per_thread)+i;
                     if (node >= NE) break;
@@ -902,7 +793,6 @@ class alignas(64) Vthread
                 }
                 eval=false;
             }
-
             if(copy){
                 for  (int i=0;   i<R2R_TABLE_SIZ; i++) {
                     if(
@@ -912,8 +802,6 @@ class alignas(64) Vthread
                     )
                     topology_connect_r2r(i);
                 }
-
-
                 for(i=0;i<ne_per_thread;i++){
                     node= (n * ne_per_thread)+i;
                     if (node >= NE) break;
@@ -921,7 +809,6 @@ class alignas(64) Vthread
                 }
                 copy=false;
             }
-
             if(update){
                 for(i=0;i<nr_per_thread;i++){
                     node= (n * nr_per_thread)+i;
@@ -930,29 +817,23 @@ class alignas(64) Vthread
                 }
                 update=false;
             }
-
             //router1[n]->eval();
             //if( TRAFFIC_TYPE == NETRACE)   pck_inj[n]->eval();
             //else   traffic[n]->eval();
-
-
             if(n==0) break;//first thread is the main process
         }
     }
-
     Vthread(int x,int r,int e)
     {
-       n=x; nr_per_thread=r; ne_per_thread=e;
-       eval=false;
-       copy =false;
-       update=false;
-       if(n!=0) {
-         std::thread th {&Vthread::function,this};
-         th.detach();
-       }
+        n=x; nr_per_thread=r; ne_per_thread=e;
+        eval=false;
+        copy =false;
+        update=false;
+        if(n!=0) {
+            std::thread th {&Vthread::function,this};
+            th.detach();
+        }
     }
-
-
 };
 
 Vthread ** thread;
@@ -964,19 +845,15 @@ void initial_threads (void){
     unsigned int  ne_per_thread=0;
     nr_per_thread = (NR % thread_num)?  (unsigned int)(NR/thread_num) + 1 :  (unsigned int)(NR/thread_num);
     ne_per_thread = (NE % thread_num)?  (unsigned int)(NE/thread_num) + 1 :  (unsigned int)(NE/thread_num);
-
     //std::vector<std::thread> threads(thread_num-1);
     //lock = new int[thread_num];
     //for(i=0;i<thread_num;i++) lock [i]=0;
-
     //Dynamically Allocating Memory
     thread = (Vthread **) new Vthread * [thread_num];
     for(i=0;i<thread_num;i++) thread[i] = new Vthread(i,nr_per_thread,ne_per_thread) ;
-
     //initiates (thread_num-1) number of live thread
     //for(i=0;i<thread_num-1;i++) threads[i] = std::thread(&thread_function, (i+1));
     //for (auto& th : threads)    th.detach();
-
     unsigned maxThreads = std::thread::hardware_concurrency();
     printf("Thread is initiated as following:\n"
     "\tMax hardware supported threads:%u\n"
@@ -986,9 +863,6 @@ void initial_threads (void){
     ,maxThreads,thread_num,nr_per_thread,ne_per_thread);
 }
 
-
-
-
 void sim_eval_all (void){
     int i;
     if(thread_num>1) {
@@ -997,23 +871,22 @@ void sim_eval_all (void){
         thread[0]->function();
         for(i=0;i<thread_num;i++)while(thread[i]->eval);
     }else{// no thread
-
         connect_clk_reset_start_all();
-
         //routers_eval();
+        #ifdef FLAT_MODE
+            noc_top->eval();
+        #else
         for(i=0;i<NR;i++){
             //if(router_is_active[i] | (Quick_sim_en==0))
             single_router_eval(i);
         }
+        #endif
         if(ENDP_TYPE == PCK_INJECTOR) for(i=0;i<NE;i++) pck_inj[i]->eval();
         else for(i=0;i<NE;i++) traffic[i]->eval();
     }
 }
 
-
 void topology_connect_all_nodes (void){
-
-
     int i;
     if(thread_num>1) {
         for(i=0;i<thread_num;i++) thread[i]->copy=true;
@@ -1027,19 +900,22 @@ void topology_connect_all_nodes (void){
     for  (int n=0; n<R2R_TABLE_SIZ; n++) {
         topology_connect_r2r(n);
     }
-
     for (int n=0;n<NE; n++){
         topology_connect_r2e(n);
     }
 }
 
-
 void sim_final_all (void){
     int i;
+    #ifdef FLAT_MODE
+    noc_top->final();
+    #else
     routers_final();
+    #endif
     if(ENDP_TYPE == PCK_INJECTOR) for(i=0;i<NE;i++) pck_inj[i]->final();
     else for(i=0;i<NE;i++) traffic[i]->final();
     //noc->final();
+    cleanup_histogram();
 }
 
 void connect_clk_reset_start_all(void){
@@ -1058,20 +934,22 @@ void connect_clk_reset_start_all(void){
             traffic[i]->clk    = clk;
         }
     }
+    #ifdef FLAT_MODE
+    noc_top->reset= reset;
+    noc_top->clk=clk;
+    #else
     connect_routers_reset_clk();
+    #endif
 }
 
-
 void traffic_clk_negedge_event(void){
     int i;
     clk = 0;
     //for (i=0;i<NR;i++) router_is_active [i]=0;
     topology_connect_all_nodes ();
-
     for (i=0;i<NE;i++){
         if(inject_done) traffic[i]->stop=1;
     }
-
     sim_eval_all();
 }
 
@@ -1093,7 +971,6 @@ void update_traffic_injector_st (unsigned int i){
             //printf("src=%u, dest=%x\n", i,endp_addr_decoder(dest_e_addr));
         }
     }
-
     if(traffic[i]->flit_out_wr==1){
         total_sent_flit_number++;
         if (!IS_UNICAST){
@@ -1107,11 +984,9 @@ void update_traffic_injector_st (unsigned int i){
         sent_stat [i].flit_num++;
         #endif
     }
-
     if(traffic[i]->flit_in_wr==1){
         total_rsv_flit_number++;
     }
-
     if(traffic[i]->hdr_flit_sent==1){
         total_sent_pck_num++;
         #if (C>1)
@@ -1124,17 +999,13 @@ void update_traffic_injector_st (unsigned int i){
 
 void update_all_traffic_injector_st(){
     for (int i=0;i<NE;i++){
-            update_traffic_injector_st(i);
-        }
-
+        update_traffic_injector_st(i);
+    }
 }
 
-
-
 void traffic_clk_posedge_event(void) {
     int i;
     unsigned int dest_e_addr;
-
     clk = 1;       // Toggle clock
     if(count_en) clk_counter++;
     inject_done= ((total_sent_pck_num >= end_sim_pck_num) || (clk_counter>= sim_end_clk_num) || total_active_routers == 0);
@@ -1142,7 +1013,6 @@ void traffic_clk_posedge_event(void) {
     total_rsv_flit_number_old=total_rsv_flit_number;
     update_all_router_stat();
     update_all_traffic_injector_st();
-
     if(inject_done){
         if(total_rsv_flit_number_old == total_rsv_flit_number){
             ideal_rsv_cnt++;
@@ -1154,27 +1024,19 @@ void traffic_clk_posedge_event(void) {
         }else ideal_rsv_cnt=0;
         if(total_expect_rsv_flit_num == total_rsv_flit_number ) simulation_done=1;
     }
-
     sim_eval_all();
-
 }
 
-
 /**********************************
- *
  *     update_noc_statistic
- *
- *
  *********************************/
-
 void update_rsvd_st (
-        statistic_t *     rsvd_stat,
-        unsigned int       clk_num_h2h,
-        unsigned int    clk_num_h2t,
-        unsigned int     latency,
-        unsigned int    distance,
-        unsigned int    pck_size
-
+    statistic_t *     rsvd_stat,
+    unsigned int       clk_num_h2h,
+    unsigned int    clk_num_h2t,
+    unsigned int     latency,
+    unsigned int    distance,
+    unsigned int    pck_size
 ) {
     rsvd_stat->pck_num ++;
     rsvd_stat->flit_num+=  pck_size;
@@ -1193,33 +1055,22 @@ void update_sent_st (
     statistic_t *  sent_stat,
     unsigned int     latency
 ) {
-
     if (sent_stat->worst_latency < latency ) sent_stat->worst_latency=latency;
     if (sent_stat->min_latency==0          ) sent_stat->min_latency  =latency;
     if (sent_stat->min_latency   > latency ) sent_stat->min_latency  =latency;
-
 }
 
 
 void update_statistic_at_ejection (
-    int    core_num,
-    unsigned int       clk_num_h2h,
-    unsigned int    clk_num_h2t,
-    unsigned int    distance,
-    unsigned int      class_num,
-    unsigned int     src,
-    unsigned int    pck_size
+    int core_num,
+    unsigned int clk_num_h2h,
+    unsigned int clk_num_h2t,
+    unsigned int distance,
+    unsigned int class_num,
+    unsigned int src,
+    unsigned int pck_size
     ){
-
-
-
-    if(ENDP_TYPE == TRFC_INJECTOR) {
-        if( traffic[core_num]->pck_size_o >= MIN_PACKET_SIZE && traffic[core_num]->pck_size_o <=MAX_PACKET_SIZE){
-              if(rsv_size_array!=NULL)     rsv_size_array[traffic[core_num]->pck_size_o-MIN_PACKET_SIZE]++;
-        }
-    }
-
-    if(verbosity==0 && ( TRAFFIC_TYPE == NETRACE || TRAFFIC_TYPE ==SYNFUL)) if((total_rsv_pck_num & 0X1FFFF )==0 ) printf(" Packets recived total=%u\n",total_rsv_pck_num);
+    record (PACK_SIZE_HISTO, pck_size);  
     unsigned int latency = (strcmp (AVG_LATENCY_METRIC,"HEAD_2_TAIL")==0)? clk_num_h2t :  clk_num_h2h;
     #if(C>1)
         update_rsvd_st ( &rsvd_stat[core_num][class_num],      clk_num_h2h,   clk_num_h2t,     latency,    distance,pck_size);
@@ -1228,84 +1079,70 @@ void update_statistic_at_ejection (
         update_rsvd_st ( &rsvd_stat[core_num], clk_num_h2h,   clk_num_h2t,     latency,    distance,pck_size);
         update_sent_st ( &sent_stat[src     ], latency);
     #endif
-
     update_rsvd_st ( &endp_to_endp[src][core_num],      clk_num_h2h,   clk_num_h2t,     latency,    distance, pck_size);
-
 }
 
-
-
-
-
 void update_noc_statistic (    int    core_num){
-    unsigned int       clk_num_h2h =traffic[core_num]->time_stamp_h2h;
-    unsigned int    clk_num_h2t =traffic[core_num]->time_stamp_h2t;
-    unsigned int    distance=traffic[core_num]->distance;
-    unsigned int      class_num=traffic[core_num]->pck_class_out;
-    unsigned int    src_e_addr=traffic[core_num]->src_e_addr;
-    unsigned int     src = endp_addr_decoder (src_e_addr);
-    unsigned int    pck_size = traffic[core_num]-> pck_size_o;
+    unsigned int  clk_num_h2h =traffic[core_num]->time_stamp_h2h;
+    unsigned int  clk_num_h2t =traffic[core_num]->time_stamp_h2t;
+    unsigned int  distance=traffic[core_num]->distance;
+    unsigned int  class_num=traffic[core_num]->pck_class_out;
+    unsigned int  src_e_addr=traffic[core_num]->src_e_addr;
+    unsigned int  src = endp_addr_decoder (src_e_addr);
+    unsigned int  pck_size = traffic[core_num]-> pck_size_o;
     update_statistic_at_ejection ( core_num,    clk_num_h2h,  clk_num_h2t,  distance,      class_num,     src,pck_size);
-
-
 }
 
 avg_st_t finilize_statistic (unsigned long int total_clk, statistic_t rsvd_stat){
-
-     avg_st_t avg_statistic;
-     avg_statistic.avg_throughput= ((double)(rsvd_stat.flit_num*100)/NE )/total_clk;
-     avg_statistic.avg_latency_flit    = rsvd_stat.sum_clk_h2h/rsvd_stat.pck_num;
-     avg_statistic.avg_latency_pck       = rsvd_stat.sum_clk_h2t/rsvd_stat.pck_num;
-     avg_statistic.avg_latency_per_hop = ( rsvd_stat.pck_num==0)? 0 : rsvd_stat.sum_clk_per_hop/rsvd_stat.pck_num;
-     avg_statistic.avg_pck_siz        = ( rsvd_stat.pck_num==0)? 0 : (double)(rsvd_stat.flit_num / rsvd_stat.pck_num);
-     #if (STND_DEV_EN)
-          avg_statistic.std_dev =standard_dev( rsvd_stat.sum_clk_pow2,rsvd_stat.pck_num, avg_statistic.avg_latency_flit);
-     #endif
-     return avg_statistic;
+    avg_st_t avg_statistic;
+    avg_statistic.avg_throughput= ((double)(rsvd_stat.flit_num*100)/NE )/total_clk;
+    avg_statistic.avg_latency_flit    = rsvd_stat.sum_clk_h2h/rsvd_stat.pck_num;
+    avg_statistic.avg_latency_pck       = rsvd_stat.sum_clk_h2t/rsvd_stat.pck_num;
+    avg_statistic.avg_latency_per_hop = ( rsvd_stat.pck_num==0)? 0 : rsvd_stat.sum_clk_per_hop/rsvd_stat.pck_num;
+    avg_statistic.avg_pck_siz        = ( rsvd_stat.pck_num==0)? 0 : (double)(rsvd_stat.flit_num / rsvd_stat.pck_num);
+    #if (STND_DEV_EN)
+        avg_statistic.std_dev =standard_dev( rsvd_stat.sum_clk_pow2,rsvd_stat.pck_num, avg_statistic.avg_latency_flit);
+    #endif
+    return avg_statistic;
 }
 
 template<typename T>
     void myout(T value)
     {
-       std::cout << value << std::endl;
+        std::cout << value << std::endl;
     }
+
 template<typename First, typename ... Rest>
     void myout(First first, Rest ... rest)
     {
-       std::cout << first << ",";
-       myout(rest...);
+        std::cout << first << ",";
+        myout(rest...);
     }
 
 void print_st_single (unsigned long int total_clk, statistic_t rsvd_stat, statistic_t sent_stat){
-
-
-
     avg_st_t avg;
     avg=finilize_statistic (total_clk,  rsvd_stat);
-
     myout(
-            sent_stat.pck_num,
-            rsvd_stat.pck_num,
-            sent_stat.flit_num,
-            rsvd_stat.flit_num,
-            sent_stat.worst_latency,
-            rsvd_stat.worst_latency,
-            sent_stat.min_latency,
-            rsvd_stat.min_latency,
-            avg.avg_latency_per_hop,
-            avg.avg_latency_flit,
-            avg.avg_latency_pck,
-            avg.avg_throughput,
-            avg.avg_pck_siz,
-            #if (STND_DEV_EN)
-            avg.std_dev
-            #endif
+        sent_stat.pck_num,
+        rsvd_stat.pck_num,
+        sent_stat.flit_num,
+        rsvd_stat.flit_num,
+        sent_stat.worst_latency,
+        rsvd_stat.worst_latency,
+        sent_stat.min_latency,
+        rsvd_stat.min_latency,
+        avg.avg_latency_per_hop,
+        avg.avg_latency_flit,
+        avg.avg_latency_pck,
+        avg.avg_throughput,
+        avg.avg_pck_siz,
+        #if (STND_DEV_EN)
+        avg.std_dev
+        #endif
     );
-//    printf("\n");
-
+    // printf("\n");
 }
 
-
 void merge_statistic (statistic_t * merge_stat, statistic_t stat_in){
     merge_stat->pck_num+=stat_in.pck_num;
     merge_stat->flit_num+=stat_in.flit_num;
@@ -1318,52 +1155,46 @@ void merge_statistic (statistic_t * merge_stat, statistic_t stat_in){
     #if (STND_DEV_EN)
         merge_stat->sum_clk_pow2 +=stat_in.sum_clk_pow2;
     #endif
-
 }
 
 void print_statistic_new (unsigned long int total_clk){
     int i;
-
-
+    printf("\n\tTotal received packet in different sizes:\n");
+    print_histogram(PACK_SIZE_HISTO,"\tflit_size,","\n\t#pck,");
+    printf("\n");
     print_router_st();
     print_endp_to_endp_st("pck_num");
     print_endp_to_endp_st("flit_num");
-
-    printf( "\n\tEndpoints Statistics:\n"
-            "\t#EID,"
-            "sent_stat.pck_num,"
-            "rsvd_stat.pck_num,"
-            "sent_stat.flit_num,"
-            "rsvd_stat.flit_num,"
-            "sent_stat.worst_latency,"
-            "rsvd_stat.worst_latency,"
-            "sent_stat.min_latency,"
-            "rsvd_stat.min_latency,"
-            "avg_latency_per_hop,"
-            "avg_latency_flit,"
-            "avg_latency_pck,"
-            "avg_throughput(%%),"
-            "avg_pck_size,"
-            #if (STND_DEV_EN)
-            "avg.std_dev"
-            #endif
-            "\n");
-
-
-
-#if(C>1)
+    printf( 
+        "\n\tEndpoints Statistics:\n"
+        "\t#EID,"
+        "sent_stat.pck_num,"
+        "rsvd_stat.pck_num,"
+        "sent_stat.flit_num,"
+        "rsvd_stat.flit_num,"
+        "sent_stat.worst_latency,"
+        "rsvd_stat.worst_latency,"
+        "sent_stat.min_latency,"
+        "rsvd_stat.min_latency,"
+        "avg_latency_per_hop,"
+        "avg_latency_flit,"
+        "avg_latency_pck,"
+        "avg_throughput(%%),"
+        "avg_pck_size,"
+        #if (STND_DEV_EN)
+        "avg.std_dev"
+        #endif
+        "\n");
+    #if(C>1)
     int c;
     statistic_t sent_stat_class [NE];
     statistic_t rsvd_stat_class [NE];
     statistic_t sent_stat_per_class [C];
     statistic_t rsvd_stat_per_class [C];
-
     memset (&rsvd_stat_class,0,sizeof(statistic_t)*NE);
     memset (&sent_stat_class,0,sizeof(statistic_t)*NE);
     memset (&rsvd_stat_per_class,0,sizeof(statistic_t)*C);
     memset (&sent_stat_per_class,0,sizeof(statistic_t)*C);
-
-
     for (i=0; i<NE;i++){
         for (c=0; c<C;c++){
             merge_statistic (&rsvd_stat_class[i],rsvd_stat[i][c]);
@@ -1372,19 +1203,11 @@ void print_statistic_new (unsigned long int total_clk){
             merge_statistic (&sent_stat_per_class[c],sent_stat[i][c]);
         }
     }
-
-
-
-
-#else
+    #else
     #define sent_stat_class  sent_stat
     #define rsvd_stat_class  rsvd_stat
-#endif
-
-
-
-
-
+    #endif
+    
     statistic_t rsvd_stat_total, sent_stat_total;
     memset (&rsvd_stat_total,0,sizeof(statistic_t));
     memset (&sent_stat_total,0,sizeof(statistic_t));
@@ -1394,80 +1217,25 @@ void print_statistic_new (unsigned long int total_clk){
     }
     printf("\ttotal,");
     print_st_single (total_clk, rsvd_stat_total,sent_stat_total);
-
-#if(C>1)
+    #if(C>1)
     for (c=0; c<C;c++){
         printf("\ttotal_class%u,",c);
         print_st_single (total_clk, rsvd_stat_per_class[c],sent_stat_per_class[c]);
     }
-#endif
-
+    #endif
     for (i=0; i<NE;i++){
         printf("\t%u,",i);
         print_st_single (total_clk, rsvd_stat_class[i],sent_stat_class[i] );
     }
-
-
-
-
-
 }
 
-
-
-
-
-
-
 void print_parameter (){
-    printf ("NoC parameters:---------------- \n");
-    printf ("\tTopology: %s\n",TOPOLOGY);
-    printf ("\tRouting algorithm: %s\n",ROUTE_NAME);
-    printf ("\tVC_per port: %d\n", V);
-    printf ("\tNon-local port buffer_width per VC: %d\n", B);
-    printf ("\tLocal port buffer_width per VC: %d\n", LB);
-
-    #if defined (IS_MESH) || defined (IS_FMESH) || defined (IS_TORUS)
-        printf ("\tRouter num in row: %d \n",T1);
-        printf ("\tRouter num in column: %d \n",T2);
-        printf ("\tEndpoint num per router: %d\n",T3);
-    #elif defined (IS_LINE) || defined (IS_RING )
-        printf ("\tTotal Router num: %d \n",T1);
-        printf ("\tEndpoint num per router: %d\n",T3);
-    #elif defined (IS_FATTREE) || defined (IS_TREE)
-        printf ("\tK: %d \n",T1);
-        printf ("\tL: %d \n",T2);
-    #elif defined (IS_STAR)
-        printf ("\tTotal Endpoints number: %d \n",T1);
-    #else//CUSTOM
-        printf ("\tTotal Endpoints number: %d \n",T1);
-        printf ("\tTotal Routers number: %d \n",T2);
-    #endif
-
-    printf ("\tNumber of Class: %d\n", C);
-    printf ("\tFlit data width: %d \n", Fpay);
-    printf ("\tVC reallocation mechanism: %s \n",  VC_REALLOCATION_TYPE);
-    printf ("\tVC/sw combination mechanism: %s \n", COMBINATION_TYPE);
-    printf ("\tAVC_ATOMIC_EN:%d \n", AVC_ATOMIC_EN);
-    printf ("\tCongestion Index:%d \n",CONGESTION_INDEX);
-    printf ("\tADD_PIPREG_AFTER_CROSSBAR:%d\n",ADD_PIPREG_AFTER_CROSSBAR);
-    printf ("\tSSA_EN enabled:%s \n",SSA_EN);
-    printf ("\tSwitch allocator arbitration type:%s \n",SWA_ARBITER_TYPE);
-    printf ("\tMinimum supported packet size:%d flit(s) \n",MIN_PCK_SIZE);
-    printf ("\tLoop back is enabled:%s \n",SELF_LOOP_EN);
-    printf ("\tNumber of multihop bypass (SMART max):%d \n",SMART_MAX);
-    printf ("\tCastying type:%s.\n",CAST_TYPE);
-    if (IS_MCAST_PARTIAL){
-        printf ("\tCAST LIST:%s\n",MCAST_ENDP_LIST);
-    }
-    printf ("NoC parameters:---------------- \n");
     printf ("\nSimulation parameters-------------\n");
     #if(DEBUG_EN)
         printf ("\tDebuging is enabled\n");
     #else
         printf ("\tDebuging is disabled\n");
     #endif   
-   
     //if(strcmp (AVG_LATENCY_METRIC,"HEAD_2_TAIL")==0)printf ("\tOutput is the average latency on sending the packet header until receiving tail\n");
     //else printf ("\tOutput is the average latency on sending the packet header until receiving header flit at destination node\n");
     printf ("\tTraffic pattern:%s\n",TRAFFIC);
@@ -1482,8 +1250,6 @@ void print_parameter (){
     if (strcmp (CAST_TYPE,"UNICAST")){
         printf ("\tMULTICAST traffic ratio: %d(%%), min: %d, max: %d\n", mcast.ratio,mcast.min,mcast.max);
     }
-
-
     //printf ("\tTotal packets sent by one router: %u\n", TOTAL_PKT_PER_ROUTER);
     if(sim_end_clk_num!=0) printf ("\tSimulation timeout =%d\n", sim_end_clk_num);
     if(end_sim_pck_num!=0) printf ("\tSimulation ends on total packet num of =%d\n", end_sim_pck_num);
@@ -1493,107 +1259,72 @@ void print_parameter (){
     }
     if( TRAFFIC_TYPE == SYNTHETIC) printf("\tFlit injection ratio per router is =%f (flits/clk/Total Endpoint %%)\n",(float)ratio*100/MAX_RATIO);
     printf ("Simulation parameters-------------\n");
-
-
-
 }
 
-
-
-
-
 /************************
- *
  *     reset system
- *
- *
  * *******************/
-
 void reset_all_register (void){
     int i;
-     total_active_endp=0;
-     total_rsv_pck_num=0;
-     total_sent_pck_num=0;
-     sum_clk_h2h=0;
-     sum_clk_h2t=0;
-     ideal_rsv_cnt=0;
-#if (STND_DEV_EN)
-     sum_clk_pow2=0;
-#endif
-
-     sum_clk_per_hop=0;
-     count_en=0;
-     clk_counter=0;
-
-     for(i=0;i<C;i++)
-     {
-         total_rsv_pck_num_per_class[i]=0;
-         sum_clk_h2h_per_class[i]=0;
-         sum_clk_h2t_per_class[i]=0;
-          sum_clk_per_hop_per_class[i]=0;
-#if (STND_DEV_EN)
-          sum_clk_pow2_per_class[i]=0;
-#endif
-
-     }  //for
-     total_sent_flit_number=0;
-     total_expect_rsv_flit_num=0;
-
-
+    total_active_endp=0;
+    total_rsv_pck_num=0;
+    total_sent_pck_num=0;
+    sum_clk_h2h=0;
+    sum_clk_h2t=0;
+    ideal_rsv_cnt=0;
+    #if (STND_DEV_EN)
+    sum_clk_pow2=0;
+    #endif
+    sum_clk_per_hop=0;
+    count_en=0;
+    clk_counter=0;
+    for(i=0;i<C;i++)
+    {
+        total_rsv_pck_num_per_class[i]=0;
+        sum_clk_h2h_per_class[i]=0;
+        sum_clk_h2t_per_class[i]=0;
+        sum_clk_per_hop_per_class[i]=0;
+    #if (STND_DEV_EN)
+        sum_clk_pow2_per_class[i]=0;
+    #endif
+    }  //for
+    total_sent_flit_number=0;
+    total_expect_rsv_flit_num=0;
 }
 
-
-
-
 /***********************
- *
  *     standard_dev
- *
  * ******************/
-
 #if (STND_DEV_EN)
 /************************
  * std_dev = sqrt[(B-A^2/N)/N]  = sqrt [(B/N)- (A/N)^2] = sqrt [B/N - mean^2]
  * A = sum of the values
  * B = sum of the squarded values
  * *************/
-
 double standard_dev( double sum_pow2, unsigned int  total_num, double average){
     double std_dev;
-
     /*
     double  A, B, N;
     N= total_num;
     A= average * N;
     B= sum_pow2;
-
     A=(A*A)/N;
     std_dev = (B-A)/N;
     std_dev = sqrt(std_dev);
 */
     if(total_num==0) return 0;
-
     std_dev = sum_pow2/(double)total_num; //B/N
     std_dev -= (average*average);// (B/N) - mean^2
     std_dev = sqroot(std_dev);// sqrt [B/N - mean^2]
-
     return std_dev;
-
 }
-
 #endif
 
-
-
 /**********************
- *
  *    pck_class_in_gen
- *
  * *****************/
-
 unsigned char  pck_class_in_gen(
-     unsigned int  core_num
-
+    unsigned int  core_num
 ) {
     unsigned char pck_class_in;
     unsigned char  rnd=rand()%100;
@@ -1609,9 +1340,6 @@ unsigned char  pck_class_in_gen(
     return 0;
 }
 
-
-
-
 void update_injct_var(unsigned int src,  unsigned int injct_var){
     //printf("before%u=%u\n",src,random_var[src]);
     random_var[src]= rnd_between(100-injct_var, 100+injct_var);
@@ -1619,64 +1347,50 @@ void update_injct_var(unsigned int src,  unsigned int injct_var){
 }
 
 unsigned int pck_dst_gen_task_graph ( unsigned int src, unsigned char * inject_en){
-     task_t  task;
+    task_t  task;
     float f,v;
     *inject_en=1;
     int index = task_graph_abstract[src].active_index;
-
     if(index == DISABLE){
         traffic[src]->ratio=0;
         traffic[src]->stop=1;
         *inject_en=0;
         return INJECT_OFF; //disable sending
     }
-
     if(    read(task_graph_data[src],index,&task)==0){
         traffic[src]->ratio=0;
         traffic[src]->stop=1;
         *inject_en=0;
         return INJECT_OFF; //disable sending
-
     }
-
-#if (C>1)
+    #if (C>1)
     if(sent_stat[src][traffic[src]->flit_out_class].pck_num & 0xFF){//sent 255 packets
-#else
+    #else
     if(sent_stat[src].pck_num & 0xFF){//sent 255 packets
-#endif
-
-            //printf("uu=%u\n",task.jnjct_var);
-            update_injct_var(src, task.jnjct_var);
-
-        }
-
+    #endif
+        //printf("uu=%u\n",task.jnjct_var);
+        update_injct_var(src, task.jnjct_var);
+    }
     task_graph_total_pck_num++;
     task.pck_sent = task.pck_sent +1;
     task.burst_sent= task.burst_sent+1;
     task.byte_sent = task.byte_sent + (task.avg_pck_size * (Fpay/8) );
-
     traffic[src]->pck_class_in=  pck_class_in_gen(src);
     //traffic[src]->avg_pck_size_in=task.avg_pck_size;
     traffic[src]->pck_size_in=rnd_between(task.min_pck_size,task.max_pck_size);
-
     f=  task.injection_rate;
     v= random_var[src];
     f*= (v /100);
     if(f>100) f= 100;
     f=  f * MAX_RATIO / 100;
-
     traffic[src]->ratio=(unsigned int)f;
     traffic[src]->init_weight=task.initial_weight;
-
     if (task.burst_sent >= task.burst_size){
         task.burst_sent=0;
         task_graph_abstract[src].active_index=task_graph_abstract[src].active_index+1;
         if(task_graph_abstract[src].active_index>=task_graph_abstract[src].total_index) task_graph_abstract[src].active_index=0;
-
     }
-
     update_by_index(task_graph_data[src],index,task);
-
     if (task.byte_sent  >= task.bytes){ // This task is done remove it from the queue
                 remove_by_index(&task_graph_data[src],index);
                 task_graph_abstract[src].total_index = task_graph_abstract[src].total_index-1;
@@ -1690,11 +1404,9 @@ unsigned int pck_dst_gen_task_graph ( unsigned int src, unsigned char * inject_e
                 }
                 if(task_graph_abstract[src].active_index>=task_graph_abstract[src].total_index) task_graph_abstract[src].active_index=0;
     }
-
     return endp_addr_encoder(task.dst);
 }
 
-
 void update_all_router_stat(void){
     if(thread_num>1) {
         int i;
@@ -1709,13 +1421,12 @@ void update_all_router_stat(void){
 }
 
 void update_router_st (
-        unsigned int Pnum,
-        unsigned int rid,
-        void * event,
-        size_t size
+    unsigned int Pnum,
+    unsigned int rid,
+    void * event,
+    size_t size
 ){
     unsigned int port_event;
-
     for (int p=0;p<Pnum;p++){
         if (size == sizeof(unsigned char)) {
             unsigned char * eventArr = (unsigned char *)event;
@@ -1730,7 +1441,6 @@ void update_router_st (
             port_event = eventArr[p];
         }
         
-           
         if(port_event & FLIT_IN_WR_FLG ) router_stat [rid][p].flit_num_in++;
         if(port_event & PCK_IN_WR_FLG  ) router_stat [rid][p].pck_num_in++;
         if(port_event & FLIT_OUT_WR_FLG) router_stat [rid][p].flit_num_out++;
@@ -1744,35 +1454,31 @@ void update_router_st (
     }
 }
 
-
 void print_router_st (void) {
-
     //report router statistic
-    printf("\n\n\tRouters' statistics:\n");
-    printf("\t#RID, #Port,"
-           "flit_in,"
-           "pck_in,"
-           "flit_out,"
+    printf("\n\n\tRouters Statistics:\n");
+    printf(
+        "\t#RID, #Port,"
+        "flit_in,"
+        "pck_in,"
+        "flit_out,"
         "pck_out,"
         "flit_in_buffered,"
         "flit_in_bypassed,"
     );
     if(SMART_MAX>0) for (int k=0;k<SMART_MAX+1;k++) printf("bypsd_%0d_times,",k);
     printf("\n");
-
     for (int i=0; i<NR; i++){
-
-           for (int p=0;p<MAX_P;p++){
-
-               printf("\t%u,%u,",i,p);
-               printf("%d,%d,%d,%d,%d,%d,",
+        for (int p=0;p<MAX_P;p++){
+            printf("\t%u,%u,",i,p);
+            printf("%d,%d,%d,%d,%d,%d,",
                 router_stat [i][p].flit_num_in,
                 router_stat [i][p].pck_num_in,
                 router_stat [i][p].flit_num_out,
                 router_stat [i][p].pck_num_out,
                 router_stat [i][p].flit_num_in_buffered,
                 router_stat [i][p].flit_num_in_bypassed
-                );
+            );
             if(SMART_MAX>0) for (int k=0;k<SMART_MAX+1;k++) printf("%d," ,router_stat [i][p].bypass_counter[k]);
             printf("\n");
             router_stat_accum [i].flit_num_in              += router_stat [i][p].flit_num_in;
@@ -1782,23 +1488,21 @@ void print_router_st (void) {
             router_stat_accum [i].flit_num_in_buffered     += router_stat [i][p].flit_num_in_buffered;
             router_stat_accum [i].flit_num_in_bypassed     += router_stat [i][p].flit_num_in_bypassed;
             if(SMART_MAX>0) for (int k=0;k<SMART_MAX+1;k++) router_stat_accum [i].bypass_counter[k]+= router_stat [i][p].bypass_counter[k];
-
-           }
-           printf("\t%u,total,",i);
-           printf("%d,%d,%d,%d,%d,%d,",
-        router_stat_accum [i].flit_num_in,
-        router_stat_accum [i].pck_num_in,
-        router_stat_accum [i].flit_num_out,
-        router_stat_accum [i].pck_num_out,
-        router_stat_accum [i].flit_num_in_buffered,
-        router_stat_accum [i].flit_num_in_bypassed
-           );
-           if(SMART_MAX>0) for (int k=0;k<SMART_MAX+1;k++) printf("%d," , router_stat_accum [i].bypass_counter[k]);
-           printf("\n");
-      }
+        }
+        printf("\t%u,total,",i);
+        printf("%d,%d,%d,%d,%d,%d,",
+            router_stat_accum [i].flit_num_in,
+            router_stat_accum [i].pck_num_in,
+            router_stat_accum [i].flit_num_out,
+            router_stat_accum [i].pck_num_out,
+            router_stat_accum [i].flit_num_in_buffered,
+            router_stat_accum [i].flit_num_in_bypassed
+        );
+        if(SMART_MAX>0) for (int k=0;k<SMART_MAX+1;k++) printf("%d," , router_stat_accum [i].bypass_counter[k]);
+        printf("\n");
+    }
 }
 
-
 void print_endp_to_endp_st(const char * st)  {
     printf ("\n\tEndp_to_Endp %s:\n\t#EID,",st);
     for (int src=0; src<NE; src++) printf ("%u,",src);
diff --git a/mpsoc/src_verilator/simulator.h b/mpsoc/src_verilator/simulator.h
index ddffd98..6aaf36f 100644
--- a/mpsoc/src_verilator/simulator.h
+++ b/mpsoc/src_verilator/simulator.h
@@ -1,51 +1,51 @@
 
 #ifndef SIMULATOR_H
-	#define  SIMULATOR_H
+    #define  SIMULATOR_H
 
 #if (__cplusplus > 201103L) //"C++11\n";
 
-	void* operator new(std::size_t size, std::align_val_t align) {
-	#if defined(_WIN32) || defined(__CYGWIN__)
-		auto ptr = _aligned_malloc(size, static_cast<std::size_t>(align));
-	#else
-		auto ptr = aligned_alloc(static_cast<std::size_t>(align), size);
-	#endif
-
-		if (!ptr)
-			throw std::bad_alloc{};
-	/*
-		std::cout << "new: " << size << ", align: "
-				  << static_cast<std::size_t>(align)
-				  << ", ptr: " << ptr << '\n';
-	*/
-		return ptr;
-
-	}
-
-	void operator delete(void* ptr, std::size_t size, std::align_val_t align) noexcept {
-	/*
-		std::cout << "delete: " << size << ", align: "
-				  << static_cast<std::size_t>(align)
-				  << ", ptr : " << ptr << '\n';
-	*/
-	#if defined(_WIN32) || defined(__CYGWIN__)
-		_aligned_free(ptr);
-	#else
-		free(ptr);
-	#endif
-	}
-
-	void operator delete(void* ptr, std::align_val_t align) noexcept {
-	  /*  std::cout << "delete: align: "
-				  << static_cast<std::size_t>(align)
-				  << ", ptr : " << ptr << '\n';
-	  */
-	#if defined(_WIN32) || defined(__CYGWIN__)
-		_aligned_free(ptr);
-	#else
-		free(ptr);
-	#endif
-	}
+    void* operator new(std::size_t size, std::align_val_t align) {
+    #if defined(_WIN32) || defined(__CYGWIN__)
+        auto ptr = _aligned_malloc(size, static_cast<std::size_t>(align));
+    #else
+        auto ptr = aligned_alloc(static_cast<std::size_t>(align), size);
+    #endif
+
+        if (!ptr)
+            throw std::bad_alloc{};
+    /*
+        std::cout << "new: " << size << ", align: "
+                  << static_cast<std::size_t>(align)
+                  << ", ptr: " << ptr << '\n';
+    */
+        return ptr;
+
+    }
+
+    void operator delete(void* ptr, std::size_t size, std::align_val_t align) noexcept {
+    /*
+        std::cout << "delete: " << size << ", align: "
+                  << static_cast<std::size_t>(align)
+                  << ", ptr : " << ptr << '\n';
+    */
+    #if defined(_WIN32) || defined(__CYGWIN__)
+        _aligned_free(ptr);
+    #else
+        free(ptr);
+    #endif
+    }
+
+    void operator delete(void* ptr, std::align_val_t align) noexcept {
+      /*  std::cout << "delete: align: "
+                  << static_cast<std::size_t>(align)
+                  << ", ptr : " << ptr << '\n';
+      */
+    #if defined(_WIN32) || defined(__CYGWIN__)
+        _aligned_free(ptr);
+    #else
+        free(ptr);
+    #endif
+    }
 
 #endif
 
@@ -61,8 +61,8 @@
 #define SYNFUL    3
 
 //injector type
-#define PCK_INJECTOR	0
-#define TRFC_INJECTOR 	1
+#define PCK_INJECTOR    0
+#define TRFC_INJECTOR     1
 
 #define STND_DEV_EN 1
 
@@ -73,44 +73,50 @@ int ENDP_TYPE   =TRFC_INJECTOR;
 
    
 int get_router_num (int , int );
-	
-
-
-	#define ideal_port router_top_v__DOT__router__DOT__router_is_ideal
-	#define active_port router_top_v__DOT__router__DOT__nb_router_active
-	#define pck_active_port  packet_injector_verilator__DOT__endp_is_active
-	#define traffic_active_port traffic_gen_top__DOT__endp_is_active
-
-	#define CHAN_SIZE   sizeof(router1[0]->chan_in[0])
-
-	#define conect_r2r(T1,r1,p1,T2,r2,p2)  \
-		memcpy(&router##T1 [r1]->chan_in[p1] , &router##T2 [r2]->chan_out[p2], CHAN_SIZE )
-
-//		router_is_active[get_router_num(T1,r1)] |=(( router##T1 [r1]-> ideal_port!=0) |  (router##T2 [r2]-> active_port[p2]==1))
-
-	#define connect_r2gnd(T,r,p)\
-		memset(&router##T [r]->chan_in [p],0x00,CHAN_SIZE);
-
-
-	#define connect_r2e(T,r,p,e) \
-		void * addr1, * addr2;\
-		addr1=(ENDP_TYPE == PCK_INJECTOR)? &pck_inj[e]->chan_out  : &traffic[e]->chan_out;\
-		addr2=(ENDP_TYPE == PCK_INJECTOR)? &pck_inj[e]->chan_in  : &traffic[e]->chan_in;\
-		memcpy(&router##T [r]->chan_in[p], addr1, CHAN_SIZE );\
-		memcpy(addr2, &router##T [r]->chan_out[p], CHAN_SIZE )
-
-
-
-
-
-//		router_is_active[get_router_num(T,r)] |= (ENDP_TYPE == PCK_INJECTOR)? \
-			(( router##T [r]-> ideal_port!=0) |  (pck_inj[e]->pck_active_port==1)):\
-			(( router##T [r]-> ideal_port!=0) |  (traffic[e]->traffic_active_port==1))
+    
+
+
+    #define ideal_port router_top_v__DOT__router__DOT__router_is_ideal
+    #define active_port router_top_v__DOT__router__DOT__nb_router_active
+    #define pck_active_port  packet_injector_verilator__DOT__endp_is_active
+    #define traffic_active_port traffic_gen_top__DOT__endp_is_active
+
+    
+#ifndef FLAT_MODE
+    #define CHAN_SIZE   sizeof(router1[0]->chan_in[0])
+    #define conect_r2r(T1,r1,p1,T2,r2,p2)  \
+        memcpy(&router##T1 [r1]->chan_in[p1] , &router##T2 [r2]->chan_out[p2], CHAN_SIZE )
+//        router_is_active[get_router_num(T1,r1)] |=(( router##T1 [r1]-> ideal_port!=0) |  (router##T2 [r2]-> active_port[p2]==1))
+
+    #define connect_r2gnd(T,r,p)\
+        memset(&router##T [r]->chan_in [p],0x00,CHAN_SIZE);
+
+
+    #define connect_r2e(T,r,p,e) \
+        void * addr1, * addr2;\
+        addr1=(ENDP_TYPE == PCK_INJECTOR)? &pck_inj[e]->chan_out  : &traffic[e]->chan_out;\
+        addr2=(ENDP_TYPE == PCK_INJECTOR)? &pck_inj[e]->chan_in  : &traffic[e]->chan_in;\
+        memcpy(&router##T [r]->chan_in[p], addr1, CHAN_SIZE );\
+        memcpy(addr2, &router##T [r]->chan_out[p], CHAN_SIZE )
+
+#else 
+    #define CHAN_SIZE   sizeof(noc_top->chan_in_all[0])
+    #define conect_r2r(T1,r1,p1,T2,r2,p2) while(0)
+    #define connect_r2e(T,r,p,e) \
+        void * addr1, * addr2;\
+        addr1=(ENDP_TYPE == PCK_INJECTOR)? &pck_inj[e]->chan_out  : &traffic[e]->chan_out;\
+        addr2=(ENDP_TYPE == PCK_INJECTOR)? &pck_inj[e]->chan_in  : &traffic[e]->chan_in;\
+        memcpy(&noc_top->chan_in_all[e], addr1, CHAN_SIZE );\
+        memcpy(addr2, &noc_top->chan_out_all[e], CHAN_SIZE )
+#endif
 
 
 
+//        router_is_active[get_router_num(T,r)] |= (ENDP_TYPE == PCK_INJECTOR)? \
+            (( router##T [r]-> ideal_port!=0) |  (pck_inj[e]->pck_active_port==1)):\
+            (( router##T [r]-> ideal_port!=0) |  (traffic[e]->traffic_active_port==1))
 
-#define IS_SELF_LOOP_EN   (strcmp(SELF_LOOP_EN ,"YES")==0)
+#define IS_SELF_LOOP_EN   SELF_LOOP_EN
 #define IS_UNICAST        (strcmp(CAST_TYPE,"UNICAST")==0)
 #define IS_MCAST_FULL     (strcmp(CAST_TYPE,"MULTICAST_FULL")==0)
 #define IS_MCAST_PARTIAL  (strcmp(CAST_TYPE,"MULTICAST_PARTIAL")==0)
@@ -123,9 +129,11 @@ int get_router_num (int , int );
 
 int reset,clk;
 
-Vtraffic		*traffic[NE]; // for synthetic and trace traffic pattern
+Vtraffic        *traffic[NE]; // for synthetic and trace traffic pattern
 Vpck_inj        *pck_inj[NE]; // for netrace
-
+#ifdef FLAT_MODE
+Vnoc            *noc_top; // for flat mode
+#endif
 
 
 unsigned char reset_active_high=1;
@@ -137,7 +145,6 @@ unsigned int sim_end_clk_num;
 unsigned long int nt_tr_list_pck=0;
 int netrace_speed_up =1;
 
-unsigned int * rsv_size_array;
 int AVG_PACKET_SIZE=5;
 int MIN_PACKET_SIZE=5;
 int MAX_PACKET_SIZE=5;
@@ -147,38 +154,38 @@ unsigned int random_var[NE] = {100};
 
 
 typedef struct  statistic_struct {
-	unsigned int pck_num;
-	unsigned int flit_num;
-	unsigned int worst_latency;
-	unsigned int min_latency;
-	double sum_clk_h2h;
-	double sum_clk_h2t;
-	double sum_clk_per_hop;
+    unsigned int pck_num;
+    unsigned int flit_num;
+    unsigned int worst_latency;
+    unsigned int min_latency;
+    double sum_clk_h2h;
+    double sum_clk_h2t;
+    double sum_clk_per_hop;
 #if (STND_DEV_EN)
-	double sum_clk_pow2;
+    double sum_clk_pow2;
 #endif
 
 } statistic_t;
 
 
 typedef struct  avg_st_struct {
-	double avg_latency_per_hop;
-	double avg_latency_flit;
-	double avg_latency_pck;
-	double avg_throughput;
-	double avg_pck_siz;
+    double avg_latency_per_hop;
+    double avg_latency_flit;
+    double avg_latency_pck;
+    double avg_throughput;
+    double avg_pck_siz;
 #if (STND_DEV_EN)
-	double std_dev;
+    double std_dev;
 #endif
 
 } avg_st_t;
 
 #define BYPASS_LSB          7
-#define FLIT_IN_WR_FLG    	(1<<6)
-#define PCK_IN_WR_FLG 		(1<<5)
-#define FLIT_OUT_WR_FLG 	(1<<4)
-#define PCK_OUT_WR_FLG		(1<<3)
-#define FLIT_IN_BYPASSED 	(1<<2)
+#define FLIT_IN_WR_FLG        (1<<6)
+#define PCK_IN_WR_FLG         (1<<5)
+#define FLIT_OUT_WR_FLG     (1<<4)
+#define PCK_OUT_WR_FLG        (1<<3)
+#define FLIT_IN_BYPASSED     (1<<2)
 #define ACTIVE_HIGH_RST     (1<<1)
 #define EMPTY_FLG           (1<<0)
 
@@ -186,13 +193,13 @@ typedef struct  avg_st_struct {
 
 
 typedef  struct  router_st_struct {
-	unsigned int pck_num_in;
-	unsigned int flit_num_in;
-	unsigned int pck_num_out;
-	unsigned int flit_num_out;
-	unsigned int flit_num_in_bypassed;
-	unsigned int flit_num_in_buffered;
-	unsigned int bypass_counter [SMART_NUM+1 ] ;
+    unsigned int pck_num_in;
+    unsigned int flit_num_in;
+    unsigned int pck_num_out;
+    unsigned int flit_num_out;
+    unsigned int flit_num_in_bypassed;
+    unsigned int flit_num_in_buffered;
+    unsigned int bypass_counter [SMART_NUM+1 ] ;
 } router_st_t;
 
 alignas(64) router_st_t router_stat [NR][MAX_P];
@@ -200,24 +207,24 @@ router_st_t router_stat_accum [NR];
 
 
 #if (C>1)
-	statistic_t sent_stat [NE][C];
-	statistic_t rsvd_stat [NE][C];
+    statistic_t sent_stat [NE][C];
+    statistic_t rsvd_stat [NE][C];
 #else
-	statistic_t sent_stat [NE];
-	statistic_t rsvd_stat [NE];
+    statistic_t sent_stat [NE];
+    statistic_t rsvd_stat [NE];
 #endif
 
-	statistic_t endp_to_endp [NE][NE];
+    statistic_t endp_to_endp [NE][NE];
 
 typedef struct mcast_struct {
-	int ratio;
-	int min;
-	int max;
+    int ratio;
+    int min;
+    int max;
 }mcast_t;
 
 
-void update_statistic_at_ejection (	int	, 	unsigned int, unsigned int, unsigned int,  unsigned int, unsigned int ,unsigned int);
-void update_noc_statistic (	int);
+void update_statistic_at_ejection (    int    ,     unsigned int, unsigned int, unsigned int,  unsigned int, unsigned int ,unsigned int);
+void update_noc_statistic (    int);
 unsigned char pck_class_in_gen(unsigned int);
 unsigned int pck_dst_gen_task_graph ( unsigned int, unsigned char *);
 void print_statistic (void);
@@ -241,7 +248,6 @@ void update_hotspot(char * );
 void update_mcast_traffic(char * str);
 void initial_threads (void);
 void print_statistic_new (unsigned long int);
-void allocate_rsv_pck_counters (void);
 void update_all_router_stat(void);
 void print_router_st(void);
 void print_endp_to_endp_st(const char *);
@@ -253,7 +259,11 @@ void update_traffic_injector_st (unsigned int );
 #include "netrace_lib.h"
 #include "synful_wrapper.h"
 
-#define RATIO_INIT		2
+#define PACK_SIZE_HISTO  0
+
+#include "histogram.h"
+
+#define RATIO_INIT        2
 #define DISABLE -1
 #define MY_VL_SETBIT_W(data,bit) (data[VL_BITWORD_I(bit)] |= (VL_UL(1) << VL_BITBIT_I(bit)))
 
@@ -278,12 +288,12 @@ unsigned int saved_time = 0;
 
 unsigned int sum_clk_h2h=0;
 unsigned int sum_clk_h2t=0;
-double 		 sum_clk_per_hop=0;
+double          sum_clk_per_hop=0;
 const int  CC=(C==0)? 1 : C;
 unsigned int total_rsv_pck_num_per_class[CC]={0};
 unsigned int sum_clk_h2h_per_class[CC]={0};
 unsigned int sum_clk_h2t_per_class[CC]={0};
-double 		 sum_clk_per_hop_per_class[CC]={0};
+double          sum_clk_per_hop_per_class[CC]={0};
 
 unsigned int clk_counter,ideal_rsv_cnt;
 unsigned int count_en;
@@ -311,64 +321,64 @@ mcast_t mcast;
 
 
 #if (STND_DEV_EN)
-	//#include <math.h>
-	double sqroot (double s){
-		int i;	
-		double root = s/3;
-		if (s<=0) return 0;
-		for(i=0;i<32;i++) root = (root +s/root)/2;
-		return root;
-	}
-	
-	double 	     sum_clk_pow2=0;
-	double 	     sum_clk_pow2_per_class[C];
-	double standard_dev( double , unsigned int, double);
+    //#include <math.h>
+    double sqroot (double s){
+        int i;    
+        double root = s/3;
+        if (s<=0) return 0;
+        for(i=0;i<32;i++) root = (root +s/root)/2;
+        return root;
+    }
+    
+    double          sum_clk_pow2=0;
+    double          sum_clk_pow2_per_class[C];
+    double standard_dev( double , unsigned int, double);
 #endif
 
 
-	// set data[bit] to 1
-		#define VL_BIT_SET_I(data, bit) data |= (VL_UL(1) << VL_BITBIT_I(bit))
-		#define VL_BIT_SET_Q(data, bit) data |= (1ULL << VL_BITBIT_Q(bit))
-		#define VL_BIT_SET_E(data, bit) data |= (VL_EUL(1) << VL_BITBIT_E(bit))
-		#define VL_BIT_SET_W(data, bit) (data)[VL_BITWORD_E(bit)] |= (VL_EUL(1) << VL_BITBIT_E(bit))
-
-		// set data[bit] to 0
-		#define VL_BIT_CLR_I(data, bit) data &= ~(VL_UL(1) << VL_BITBIT_I(bit))
-		#define VL_BIT_CLR_Q(data, bit) data &= ~(1ULL << VL_BITBIT_Q(bit))
-		#define VL_BIT_CLR_E(data, bit) data &= ~ (VL_EUL(1) << VL_BITBIT_E(bit))
-		#define VL_BIT_CLR_W(data, bit) (data)[VL_BITWORD_E(bit)] &= ~ (VL_EUL(1) << VL_BITBIT_E(bit))
-
-
-		#if   (DAw<=VL_IDATASIZE)
-			#define DEST_ADDR_BIT_SET(data, bit)  VL_BIT_SET_I(data, bit)
-			#define DEST_ADDR_BIT_CLR(data, bit)  VL_BIT_CLR_I(data, bit)
-			#define DEST_ADDR_ASSIGN_RAND(data)   data = rand() & ((1<<DAw) -1)
-			#define DEST_ADDR_ASSIGN_ZERO(data)   data = 0
-			#define DEST_ADDR_ASSIGN_INT(data,val) data = val & ((1<<DAw) -1)
-			#define DEST_ADDR_IS_ZERO(a,data) a= (data ==0)
-		#elif (DAw<=VL_QUADSIZE)
-			#define DEST_ADDR_BIT_SET(data, bit)  VL_BIT_SET_Q(data, bit)
-			#define DEST_ADDR_BIT_CLR(data, bit)  VL_BIT_CLR_Q(data, bit)
-			#define DEST_ADDR_ASSIGN_RAND(data)   data = (rand()&0xFFFFFFFF) | \
-			(QData)	(rand() & ((1ULL<<(DAw-32)) -1))	<<32
-			#define DEST_ADDR_ASSIGN_ZERO(data)   data = 0ULL
-			#define DEST_ADDR_ASSIGN_INT(data,val) data = val & ((1ULL<<32) -1)
-			#define DEST_ADDR_IS_ZERO(a,data) a= (data == 0ULL)
-		#else
-			#define DEST_ADDR_BIT_SET(data, bit)  VL_BIT_SET_W(data, bit)
-			#define DEST_ADDR_BIT_CLR(data, bit)  VL_BIT_CLR_W(data, bit)
-			#define DEST_ADDR_ASSIGN_RAND(data) \
-			for(int n=0;n<=VL_BITWORD_E(DAw-1)-1;n++)  (data)[n]=rand();\
-			(data)[VL_BITWORD_E(DAw-1)]=rand() & ((1ULL<<(VL_BITBIT_E(DAw-1)+1)) -1)
-			#define DEST_ADDR_ASSIGN_ZERO(data) \
-			for(int n=0;n<=VL_BITWORD_E(DAw-1);n++)  (data)[n]= 0
-			#define DEST_ADDR_ASSIGN_INT(data,val) (data)[0] = val
-
-			#define DEST_ADDR_IS_ZERO(a,data) \
-			a=1; for(int n=0;n<=VL_BITWORD_E(DAw-1)-1;n++) 	\
-			if (a==1) a= ((data)[n]==0);\
-			if (a==1) a= ((data)[VL_BITWORD_E(DAw-1)] & ((1ULL<<(VL_BITBIT_E(DAw-1)+1)) -1))==0
-		#endif
+    // set data[bit] to 1
+        #define VL_BIT_SET_I(data, bit) data |= (VL_UL(1) << VL_BITBIT_I(bit))
+        #define VL_BIT_SET_Q(data, bit) data |= (1ULL << VL_BITBIT_Q(bit))
+        #define VL_BIT_SET_E(data, bit) data |= (VL_EUL(1) << VL_BITBIT_E(bit))
+        #define VL_BIT_SET_W(data, bit) (data)[VL_BITWORD_E(bit)] |= (VL_EUL(1) << VL_BITBIT_E(bit))
+
+        // set data[bit] to 0
+        #define VL_BIT_CLR_I(data, bit) data &= ~(VL_UL(1) << VL_BITBIT_I(bit))
+        #define VL_BIT_CLR_Q(data, bit) data &= ~(1ULL << VL_BITBIT_Q(bit))
+        #define VL_BIT_CLR_E(data, bit) data &= ~ (VL_EUL(1) << VL_BITBIT_E(bit))
+        #define VL_BIT_CLR_W(data, bit) (data)[VL_BITWORD_E(bit)] &= ~ (VL_EUL(1) << VL_BITBIT_E(bit))
+
+
+        #if   (DAw<=VL_IDATASIZE)
+            #define DEST_ADDR_BIT_SET(data, bit)  VL_BIT_SET_I(data, bit)
+            #define DEST_ADDR_BIT_CLR(data, bit)  VL_BIT_CLR_I(data, bit)
+            #define DEST_ADDR_ASSIGN_RAND(data)   data = rand() & ((1<<DAw) -1)
+            #define DEST_ADDR_ASSIGN_ZERO(data)   data = 0
+            #define DEST_ADDR_ASSIGN_INT(data,val) data = val & ((1<<DAw) -1)
+            #define DEST_ADDR_IS_ZERO(a,data) a= (data ==0)
+        #elif (DAw<=VL_QUADSIZE)
+            #define DEST_ADDR_BIT_SET(data, bit)  VL_BIT_SET_Q(data, bit)
+            #define DEST_ADDR_BIT_CLR(data, bit)  VL_BIT_CLR_Q(data, bit)
+            #define DEST_ADDR_ASSIGN_RAND(data)   data = (rand()&0xFFFFFFFF) | \
+            (QData)    (rand() & ((1ULL<<(DAw-32)) -1))    <<32
+            #define DEST_ADDR_ASSIGN_ZERO(data)   data = 0ULL
+            #define DEST_ADDR_ASSIGN_INT(data,val) data = val & ((1ULL<<32) -1)
+            #define DEST_ADDR_IS_ZERO(a,data) a= (data == 0ULL)
+        #else
+            #define DEST_ADDR_BIT_SET(data, bit)  VL_BIT_SET_W(data, bit)
+            #define DEST_ADDR_BIT_CLR(data, bit)  VL_BIT_CLR_W(data, bit)
+            #define DEST_ADDR_ASSIGN_RAND(data) \
+            for(int n=0;n<=VL_BITWORD_E(DAw-1)-1;n++)  (data)[n]=rand();\
+            (data)[VL_BITWORD_E(DAw-1)]=rand() & ((1ULL<<(VL_BITBIT_E(DAw-1)+1)) -1)
+            #define DEST_ADDR_ASSIGN_ZERO(data) \
+            for(int n=0;n<=VL_BITWORD_E(DAw-1);n++)  (data)[n]= 0
+            #define DEST_ADDR_ASSIGN_INT(data,val) (data)[0] = val
+
+            #define DEST_ADDR_IS_ZERO(a,data) \
+            a=1; for(int n=0;n<=VL_BITWORD_E(DAw-1)-1;n++)     \
+            if (a==1) a= ((data)[n]==0);\
+            if (a==1) a= ((data)[VL_BITWORD_E(DAw-1)] & ((1ULL<<(VL_BITBIT_E(DAw-1)+1)) -1))==0
+        #endif
 
 
 #endif
diff --git a/mpsoc/src_verilator/synful_wrapper.h b/mpsoc/src_verilator/synful_wrapper.h
index f248eed..214a4d2 100644
--- a/mpsoc/src_verilator/synful_wrapper.h
+++ b/mpsoc/src_verilator/synful_wrapper.h
@@ -1,5 +1,5 @@
 #ifndef _SYNFUL_WRAPPER_H
-	#define  _SYNFUL_WRAPPER_H
+    #define  _SYNFUL_WRAPPER_H
 
 
 #include <iostream>
@@ -19,162 +19,162 @@ extern queue_t** synful_inject;
 
 
 void synful_init(char * fname, bool ss_exit, int seed,unsigned int max_clk, unsigned int max_pck){
-	//std::cout << "Initiating synful with: " << fname << "random seed:" << seed << std::endl;
+    //std::cout << "Initiating synful with: " << fname << "random seed:" << seed << std::endl;
     synful_model_init(fname, ss_exit,seed,max_clk, max_pck, traffic_model_mapping );
 
- 	synful_inject   = (queue_t**) malloc( NE * sizeof(queue_t*) );
- 	synful_traverse = (queue_t**) malloc( NE * sizeof(queue_t*) );
-
- 	if(synful_inject == NULL || synful_traverse == NULL ) {
-		printf( "ERROR: malloc fail queues\n" );
-		exit(0);
-	}
-	for(int i = 0; i <  NE; ++i ) {
-		synful_inject[i]     = queue_new();
-		synful_traverse[i]   = queue_new();
-	}
+    synful_inject   = (queue_t**) malloc( NE * sizeof(queue_t*) );
+    synful_traverse = (queue_t**) malloc( NE * sizeof(queue_t*) );
+
+    if(synful_inject == NULL || synful_traverse == NULL ) {
+        printf( "ERROR: malloc fail queues\n" );
+        exit(0);
+    }
+    for(int i = 0; i <  NE; ++i ) {
+        synful_inject[i]     = queue_new();
+        synful_traverse[i]   = queue_new();
+    }
 }
 
 
 void synful_final_report(){
-	int i;
+    int i;
 
-	if(verbosity==1) 	printf("\e[?25h");//To re-enable the cursor:
-	printf("\nSynful simulation results-------------------\n"
-			"\tSimulation clock cycles: %llu\n"
-	,synful_cycle);
-	print_statistic_new (synful_cycle);
+    if(verbosity==1)     printf("\e[?25h");//To re-enable the cursor:
+    printf("\nSynful simulation results-------------------\n"
+            "\tSimulation clock cycles: %llu\n"
+    ,synful_cycle);
+    print_statistic_new (synful_cycle);
 }
 
 
 
 void synful_eval( ){
-	int i;
-	unsigned int pronoc_src_id,pronoc_dst_id;
-
-	if((reset==reset_active_high) || (count_en==0))	return;
-
-	if((( synful_cycle > sim_end_clk_num) || (total_sent_pck_num>= end_sim_pck_num )) && synful_packets_left==0 )  simulation_done=1;
-
-	// Reset packets remaining check
-	synful_packets_left = 0;
-
-	synful_run_one_cycle ();
-
-
-	// Inject where possible (max one per node)
-	for( i = 0; i < NE; ++i ) {
-		synful_packets_left |= !queue_empty( synful_inject[i] );
-
-		//TODO define sent vc policy
-		int sent_vc = 0;
-
-		if(pck_inj[i]->pck_injct_in_pck_wr){
-			//the wr_pck should be asserted only for single cycle
-			pck_inj[i]->pck_injct_in_pck_wr  	   = 0;
-			continue;
-		}
-
-		pck_inj[i]->pck_injct_in_pck_wr  	   = 0;
-		if((pck_inj[i]->pck_injct_out_ready & (0x1<<sent_vc)) == 0){
-			//This pck injector is not ready yet
-			continue;
-		}
-
-		pronoc_pck_t* temp_node = (pronoc_pck_t*) queue_peek_front( synful_inject[i] );
-		if( temp_node != NULL ) {
-			if(verbosity>1) {
-				printf( "Inject: %llu ", synful_cycle );
-				synful_print_packet( temp_node );
-			}
-			temp_node = (pronoc_pck_t*) queue_pop_front( synful_inject[i] );
-
-			pronoc_dst_id =  traffic_model_mapping[temp_node->dest];
-			queue_push( synful_traverse[pronoc_dst_id], temp_node, synful_cycle );
-			int flit_num =  temp_node->packetSize / synful_flitw ;
-			if (flit_num*synful_flitw !=temp_node->packetSize) flit_num++;
-			if (flit_num < pck_inj[i]->min_pck_size) flit_num = pck_inj[i]->min_pck_size;
-
-			if(IS_SELF_LOOP_EN ==0){
-				if(pronoc_dst_id == i ){
-					 fprintf(stderr,"ERROR: ProNoC is not configured with self-loop enable and Netrace aims to inject\n a "
-							 "packet with identical source and destination address. Enable the SELF_LOOP parameter\n"
-							 "in ProNoC and rebuild the simulation model\n");
-					 exit(1);
-				}
-			}
-
-			unsigned int sent_class =0;
-			long int ptr_addr = reinterpret_cast<long int> (temp_node);
-			pck_inj[i]->pck_injct_in_data         = ptr_addr;
-			pck_inj[i]->pck_injct_in_size         = flit_num;
-			pck_inj[i]->pck_injct_in_endp_addr    = endp_addr_encoder(pronoc_dst_id);
-			pck_inj[i]->pck_injct_in_class_num    = sent_class;
-			pck_inj[i]->pck_injct_in_init_weight  = 1;
-			pck_inj[i]->pck_injct_in_vc           = 0x1<<sent_vc;
-			pck_inj[i]->pck_injct_in_pck_wr  	   = 1;
-			total_sent_pck_num++;
-
-			#if (C>1)
-				sent_stat[i][sent_class].pck_num ++;
-				sent_stat[i][sent_class].flit_num +=flit_num;
-			#else
-				sent_stat[i].pck_num ++;
-				sent_stat[i].flit_num +=flit_num;
-			#endif
-		}//temp!=NULL
-	}//inject
-
-
-
-	// Step all network components, Eject where possible
-	for( i = 0; i < NE; ++i ) {
-		synful_packets_left |= !queue_empty( synful_traverse[i] );
-		//check which pck injector got a packet
-		if(pck_inj[i]->pck_injct_out_pck_wr==0) continue;
-		//we have got a packet
-		//printf( "data=%lx\n",pck_inj[i]->pck_injct_out_data);
-
-		pronoc_pck_t* temp_node = (pronoc_pck_t*)  pck_inj[i]->pck_injct_out_data;
-		if( temp_node != NULL ) {
-			if(verbosity>1) {
-				printf( "Eject: %llu ", synful_cycle );
-				synful_print_packet(temp_node);
-			}
-			//send it to synful
-			synful_Eject (temp_node);
-
-			// remove from traverse
-
-			queue_remove( synful_traverse[i], temp_node );
-			unsigned long long int    clk_num_h2t= (synful_cycle - temp_node->cycle);
-			unsigned int    clk_num_h2h= clk_num_h2t - pck_inj[i]->pck_injct_out_h2t_delay;
-			/*
-				printf("clk_num_h2t (%llu) h2t_delay(%u)\n", clk_num_h2t , pck_inj[i]->pck_injct_out_h2t_delay);
-				if(clk_num_h2t < pck_inj[i]->pck_injct_out_h2t_delay){
-					fprintf(stderr, "ERROR:clk_num_h2t (%llu) is smaller than  injector h2t_delay(%u)\n", clk_num_h2t , pck_inj[i]->pck_injct_out_h2t_delay);
-					exit(1);
-				}
-			*/
-			pronoc_src_id=traffic_model_mapping[temp_node->source];
-			update_statistic_at_ejection (
-					i,//	core_num
-					clk_num_h2h, // clk_num_h2h,
-					(unsigned int) clk_num_h2t, // clk_num_h2t,
-					pck_inj[i]->pck_injct_out_distance, //    distance,
-					pck_inj[i]->pck_injct_out_class_num,//  	class_num,
-					pronoc_src_id, //temp_node->source
-					pck_inj[i]->pck_injct_out_size
-			);
-
-				free( temp_node );
-
-		}//emp_node != NULL
-	}//for
-
-	synful_cycle++;
-
-	//std::cout << synful_cycle << std::endl;
+    int i;
+    unsigned int pronoc_src_id,pronoc_dst_id;
+
+    if((reset==reset_active_high) || (count_en==0))    return;
+
+    if((( synful_cycle > sim_end_clk_num) || (total_sent_pck_num>= end_sim_pck_num )) && synful_packets_left==0 )  simulation_done=1;
+
+    // Reset packets remaining check
+    synful_packets_left = 0;
+
+    synful_run_one_cycle ();
+
+
+    // Inject where possible (max one per node)
+    for( i = 0; i < NE; ++i ) {
+        synful_packets_left |= !queue_empty( synful_inject[i] );
+
+        //TODO define sent vc policy
+        int sent_vc = 0;
+
+        if(pck_inj[i]->pck_injct_in_pck_wr){
+            //the wr_pck should be asserted only for single cycle
+            pck_inj[i]->pck_injct_in_pck_wr         = 0;
+            continue;
+        }
+
+        pck_inj[i]->pck_injct_in_pck_wr         = 0;
+        if((pck_inj[i]->pck_injct_out_ready & (0x1<<sent_vc)) == 0){
+            //This pck injector is not ready yet
+            continue;
+        }
+
+        pronoc_pck_t* temp_node = (pronoc_pck_t*) queue_peek_front( synful_inject[i] );
+        if( temp_node != NULL ) {
+            if(verbosity>1) {
+                printf( "Inject: %llu ", synful_cycle );
+                synful_print_packet( temp_node );
+            }
+            temp_node = (pronoc_pck_t*) queue_pop_front( synful_inject[i] );
+
+            pronoc_dst_id =  traffic_model_mapping[temp_node->dest];
+            queue_push( synful_traverse[pronoc_dst_id], temp_node, synful_cycle );
+            int flit_num =  temp_node->packetSize / synful_flitw ;
+            if (flit_num*synful_flitw !=temp_node->packetSize) flit_num++;
+            if (flit_num < pck_inj[i]->min_pck_size) flit_num = pck_inj[i]->min_pck_size;
+
+            if(SELF_LOOP_EN ==0){
+                if(pronoc_dst_id == i ){
+                    fprintf(stderr,"ERROR: ProNoC is not configured with self-loop enable and Netrace aims to inject\n a "
+                            "packet with identical source and destination address. Enable the SELF_LOOP parameter\n"
+                            "in ProNoC and rebuild the simulation model\n");
+                    exit(1);
+                }
+            }
+
+            unsigned int sent_class =0;
+            long int ptr_addr = reinterpret_cast<long int> (temp_node);
+            pck_inj[i]->pck_injct_in_data         = ptr_addr;
+            pck_inj[i]->pck_injct_in_size         = flit_num;
+            pck_inj[i]->pck_injct_in_endp_addr    = endp_addr_encoder(pronoc_dst_id);
+            pck_inj[i]->pck_injct_in_class_num    = sent_class;
+            pck_inj[i]->pck_injct_in_init_weight  = 1;
+            pck_inj[i]->pck_injct_in_vc           = 0x1<<sent_vc;
+            pck_inj[i]->pck_injct_in_pck_wr         = 1;
+            total_sent_pck_num++;
+
+            #if (C>1)
+                sent_stat[i][sent_class].pck_num ++;
+                sent_stat[i][sent_class].flit_num +=flit_num;
+            #else
+                sent_stat[i].pck_num ++;
+                sent_stat[i].flit_num +=flit_num;
+            #endif
+        }//temp!=NULL
+    }//inject
+
+
+
+    // Step all network components, Eject where possible
+    for( i = 0; i < NE; ++i ) {
+        synful_packets_left |= !queue_empty( synful_traverse[i] );
+        //check which pck injector got a packet
+        if(pck_inj[i]->pck_injct_out_pck_wr==0) continue;
+        //we have got a packet
+        //printf( "data=%lx\n",pck_inj[i]->pck_injct_out_data);
+
+        pronoc_pck_t* temp_node = (pronoc_pck_t*)  pck_inj[i]->pck_injct_out_data;
+        if( temp_node != NULL ) {
+            if(verbosity>1) {
+                printf( "Eject: %llu ", synful_cycle );
+                synful_print_packet(temp_node);
+            }
+            //send it to synful
+            synful_Eject (temp_node);
+
+            // remove from traverse
+
+            queue_remove( synful_traverse[i], temp_node );
+            unsigned long long int    clk_num_h2t= (synful_cycle - temp_node->cycle);
+            unsigned int    clk_num_h2h= clk_num_h2t - pck_inj[i]->pck_injct_out_h2t_delay;
+            /*
+                printf("clk_num_h2t (%llu) h2t_delay(%u)\n", clk_num_h2t , pck_inj[i]->pck_injct_out_h2t_delay);
+                if(clk_num_h2t < pck_inj[i]->pck_injct_out_h2t_delay){
+                    fprintf(stderr, "ERROR:clk_num_h2t (%llu) is smaller than  injector h2t_delay(%u)\n", clk_num_h2t , pck_inj[i]->pck_injct_out_h2t_delay);
+                    exit(1);
+                }
+            */
+            pronoc_src_id=traffic_model_mapping[temp_node->source];
+            update_statistic_at_ejection (
+                    i,//    core_num
+                    clk_num_h2h, // clk_num_h2h,
+                    (unsigned int) clk_num_h2t, // clk_num_h2t,
+                    pck_inj[i]->pck_injct_out_distance, //    distance,
+                    pck_inj[i]->pck_injct_out_class_num,//      class_num,
+                    pronoc_src_id, //temp_node->source
+                    pck_inj[i]->pck_injct_out_size
+            );
+
+                free( temp_node );
+
+        }//emp_node != NULL
+    }//for
+
+    synful_cycle++;
+
+    //std::cout << synful_cycle << std::endl;
 
 }
 
@@ -183,22 +183,22 @@ void synful_eval( ){
 
 
 void synful_negedge_event( ){
-	int i;
-	clk = 0;
-	topology_connect_all_nodes ();
-	//connect_clk_reset_start_all();
-	sim_eval_all();
+    int i;
+    clk = 0;
+    topology_connect_all_nodes ();
+    //connect_clk_reset_start_all();
+    sim_eval_all();
 }
 
 void synful_posedge_event(){
-	unsigned int i;
-	clk = 1;       // Toggle clock
-	update_all_router_stat();
-	synful_eval();
-	//connect_clk_reset_start_all();
-	sim_eval_all();
-	//print total sent packet each 1024 clock cycles
-	if(verbosity==1) if(synful_cycle&0x3FF) printf("\rTotal sent packet: %9d", total_sent_pck_num);
+    unsigned int i;
+    clk = 1;       // Toggle clock
+    update_all_router_stat();
+    synful_eval();
+    //connect_clk_reset_start_all();
+    sim_eval_all();
+    //print total sent packet each 1024 clock cycles
+    if(verbosity==1) if(synful_cycle&0x3FF) printf("\rTotal sent packet: %9d", total_sent_pck_num);
 }
 
 
diff --git a/mpsoc/src_verilator/topology/custom/custom1_noc.h b/mpsoc/src_verilator/topology/custom/custom1_noc.h
index e5dbcc4..469dc4d 100644
--- a/mpsoc/src_verilator/topology/custom/custom1_noc.h
+++ b/mpsoc/src_verilator/topology/custom/custom1_noc.h
@@ -1,139 +1,137 @@
 
 
-
-//Connect R0 input ports 1 to  R14 output ports 3
+    //Connect R0 input ports 1 to  R14 output ports 3
 void single_r2r0(void){conect_r2r(1,0,1,2,6,3);}
-//Connect R0 input ports 2 to  R13 output ports 3
+    //Connect R0 input ports 2 to  R13 output ports 3
 void single_r2r1(void){conect_r2r(1,0,2,2,5,3);}
-//Connect R1 input ports 1 to  R7 output ports 3
+    //Connect R1 input ports 1 to  R7 output ports 3
 void single_r2r2(void){conect_r2r(1,1,1,2,3,3);}
-//Connect R1 input ports 2 to  R2 output ports 2
+    //Connect R1 input ports 2 to  R2 output ports 2
 void single_r2r3(void){conect_r2r(1,1,2,1,2,2);}
-//Connect R2 input ports 1 to  R15 output ports 2
+    //Connect R2 input ports 1 to  R15 output ports 2
 void single_r2r4(void){conect_r2r(1,2,1,2,7,2);}
-//Connect R2 input ports 2 to  R1 output ports 2
+    //Connect R2 input ports 2 to  R1 output ports 2
 void single_r2r5(void){conect_r2r(1,2,2,1,1,2);}
-//Connect R3 input ports 1 to  R15 output ports 3
+    //Connect R3 input ports 1 to  R15 output ports 3
 void single_r2r6(void){conect_r2r(1,3,1,2,7,3);}
-//Connect R3 input ports 2 to  R4 output ports 2
+    //Connect R3 input ports 2 to  R4 output ports 2
 void single_r2r7(void){conect_r2r(1,3,2,2,0,2);}
-//Connect R4 input ports 1 to  R9 output ports 2
+    //Connect R4 input ports 1 to  R9 output ports 2
 void single_r2r8(void){conect_r2r(2,0,1,3,1,2);}
-//Connect R4 input ports 2 to  R3 output ports 2
+    //Connect R4 input ports 2 to  R3 output ports 2
 void single_r2r9(void){conect_r2r(2,0,2,1,3,2);}
-//Connect R4 input ports 3 to  R6 output ports 3
+    //Connect R4 input ports 3 to  R6 output ports 3
 void single_r2r10(void){conect_r2r(2,0,3,2,2,3);}
-//Connect R5 input ports 1 to  R11 output ports 4
+    //Connect R5 input ports 1 to  R11 output ports 4
 void single_r2r11(void){conect_r2r(2,1,1,3,3,4);}
-//Connect R5 input ports 2 to  R6 output ports 2
+    //Connect R5 input ports 2 to  R6 output ports 2
 void single_r2r12(void){conect_r2r(2,1,2,2,2,2);}
-//Connect R5 input ports 3 to  R13 output ports 2
+    //Connect R5 input ports 3 to  R13 output ports 2
 void single_r2r13(void){conect_r2r(2,1,3,2,5,2);}
-//Connect R6 input ports 1 to  R9 output ports 3
+    //Connect R6 input ports 1 to  R9 output ports 3
 void single_r2r14(void){conect_r2r(2,2,1,3,1,3);}
-//Connect R6 input ports 2 to  R5 output ports 2
+    //Connect R6 input ports 2 to  R5 output ports 2
 void single_r2r15(void){conect_r2r(2,2,2,2,1,2);}
-//Connect R6 input ports 3 to  R4 output ports 3
+    //Connect R6 input ports 3 to  R4 output ports 3
 void single_r2r16(void){conect_r2r(2,2,3,2,0,3);}
-//Connect R7 input ports 1 to  R12 output ports 3
+    //Connect R7 input ports 1 to  R12 output ports 3
 void single_r2r17(void){conect_r2r(2,3,1,2,4,3);}
-//Connect R7 input ports 2 to  R14 output ports 2
+    //Connect R7 input ports 2 to  R14 output ports 2
 void single_r2r18(void){conect_r2r(2,3,2,2,6,2);}
-//Connect R7 input ports 3 to  R1 output ports 1
+    //Connect R7 input ports 3 to  R1 output ports 1
 void single_r2r19(void){conect_r2r(2,3,3,1,1,1);}
-//Connect R12 input ports 1 to  R8 output ports 4
+    //Connect R12 input ports 1 to  R8 output ports 4
 void single_r2r20(void){conect_r2r(2,4,1,3,0,4);}
-//Connect R12 input ports 2 to  R10 output ports 3
+    //Connect R12 input ports 2 to  R10 output ports 3
 void single_r2r21(void){conect_r2r(2,4,2,3,2,3);}
-//Connect R12 input ports 3 to  R7 output ports 1
+    //Connect R12 input ports 3 to  R7 output ports 1
 void single_r2r22(void){conect_r2r(2,4,3,2,3,1);}
-//Connect R13 input ports 1 to  R8 output ports 2
+    //Connect R13 input ports 1 to  R8 output ports 2
 void single_r2r23(void){conect_r2r(2,5,1,3,0,2);}
-//Connect R13 input ports 2 to  R5 output ports 3
+    //Connect R13 input ports 2 to  R5 output ports 3
 void single_r2r24(void){conect_r2r(2,5,2,2,1,3);}
-//Connect R13 input ports 3 to  R0 output ports 2
+    //Connect R13 input ports 3 to  R0 output ports 2
 void single_r2r25(void){conect_r2r(2,5,3,1,0,2);}
-//Connect R14 input ports 1 to  R8 output ports 3
+    //Connect R14 input ports 1 to  R8 output ports 3
 void single_r2r26(void){conect_r2r(2,6,1,3,0,3);}
-//Connect R14 input ports 2 to  R7 output ports 2
+    //Connect R14 input ports 2 to  R7 output ports 2
 void single_r2r27(void){conect_r2r(2,6,2,2,3,2);}
-//Connect R14 input ports 3 to  R0 output ports 1
+    //Connect R14 input ports 3 to  R0 output ports 1
 void single_r2r28(void){conect_r2r(2,6,3,1,0,1);}
-//Connect R15 input ports 1 to  R10 output ports 4
+    //Connect R15 input ports 1 to  R10 output ports 4
 void single_r2r29(void){conect_r2r(2,7,1,3,2,4);}
-//Connect R15 input ports 2 to  R2 output ports 1
+    //Connect R15 input ports 2 to  R2 output ports 1
 void single_r2r30(void){conect_r2r(2,7,2,1,2,1);}
-//Connect R15 input ports 3 to  R3 output ports 1
+    //Connect R15 input ports 3 to  R3 output ports 1
 void single_r2r31(void){conect_r2r(2,7,3,1,3,1);}
-//Connect R8 input ports 1 to  R11 output ports 1
+    //Connect R8 input ports 1 to  R11 output ports 1
 void single_r2r32(void){conect_r2r(3,0,1,3,3,1);}
-//Connect R8 input ports 2 to  R13 output ports 1
+    //Connect R8 input ports 2 to  R13 output ports 1
 void single_r2r33(void){conect_r2r(3,0,2,2,5,1);}
-//Connect R8 input ports 3 to  R14 output ports 1
+    //Connect R8 input ports 3 to  R14 output ports 1
 void single_r2r34(void){conect_r2r(3,0,3,2,6,1);}
-//Connect R8 input ports 4 to  R12 output ports 1
+    //Connect R8 input ports 4 to  R12 output ports 1
 void single_r2r35(void){conect_r2r(3,0,4,2,4,1);}
-//Connect R9 input ports 1 to  R11 output ports 3
+    //Connect R9 input ports 1 to  R11 output ports 3
 void single_r2r36(void){conect_r2r(3,1,1,3,3,3);}
-//Connect R9 input ports 2 to  R4 output ports 1
+    //Connect R9 input ports 2 to  R4 output ports 1
 void single_r2r37(void){conect_r2r(3,1,2,2,0,1);}
-//Connect R9 input ports 3 to  R6 output ports 1
+    //Connect R9 input ports 3 to  R6 output ports 1
 void single_r2r38(void){conect_r2r(3,1,3,2,2,1);}
-//Connect R9 input ports 4 to  R10 output ports 2
+    //Connect R9 input ports 4 to  R10 output ports 2
 void single_r2r39(void){conect_r2r(3,1,4,3,2,2);}
-//Connect R10 input ports 1 to  R11 output ports 2
+    //Connect R10 input ports 1 to  R11 output ports 2
 void single_r2r40(void){conect_r2r(3,2,1,3,3,2);}
-//Connect R10 input ports 2 to  R9 output ports 4
+    //Connect R10 input ports 2 to  R9 output ports 4
 void single_r2r41(void){conect_r2r(3,2,2,3,1,4);}
-//Connect R10 input ports 3 to  R12 output ports 2
+    //Connect R10 input ports 3 to  R12 output ports 2
 void single_r2r42(void){conect_r2r(3,2,3,2,4,2);}
-//Connect R10 input ports 4 to  R15 output ports 1
+    //Connect R10 input ports 4 to  R15 output ports 1
 void single_r2r43(void){conect_r2r(3,2,4,2,7,1);}
-//Connect R11 input ports 1 to  R8 output ports 1
+    //Connect R11 input ports 1 to  R8 output ports 1
 void single_r2r44(void){conect_r2r(3,3,1,3,0,1);}
-//Connect R11 input ports 2 to  R10 output ports 1
+    //Connect R11 input ports 2 to  R10 output ports 1
 void single_r2r45(void){conect_r2r(3,3,2,3,2,1);}
-//Connect R11 input ports 3 to  R9 output ports 1
+    //Connect R11 input ports 3 to  R9 output ports 1
 void single_r2r46(void){conect_r2r(3,3,3,3,1,1);}
-//Connect R11 input ports 4 to  R5 output ports 1
+    //Connect R11 input ports 4 to  R5 output ports 1
 void single_r2r47(void){conect_r2r(3,3,4,2,1,1);}
 
 
-//Connect R0 input ports 0 to  T0 output ports 0
+    //Connect R0 input ports 0 to  T0 output ports 0
 void single_r2e0(void) {connect_r2e(1,0,0,0);}
-//Connect R1 input ports 0 to  T1 output ports 0
+    //Connect R1 input ports 0 to  T1 output ports 0
 void single_r2e1(void) {connect_r2e(1,1,0,1);}
-//Connect R2 input ports 0 to  T2 output ports 0
+    //Connect R2 input ports 0 to  T2 output ports 0
 void single_r2e2(void) {connect_r2e(1,2,0,2);}
-//Connect R3 input ports 0 to  T3 output ports 0
+    //Connect R3 input ports 0 to  T3 output ports 0
 void single_r2e3(void) {connect_r2e(1,3,0,3);}
-//Connect R4 input ports 0 to  T4 output ports 0
+    //Connect R4 input ports 0 to  T4 output ports 0
 void single_r2e4(void) {connect_r2e(2,0,0,4);}
-//Connect R5 input ports 0 to  T5 output ports 0
+    //Connect R5 input ports 0 to  T5 output ports 0
 void single_r2e5(void) {connect_r2e(2,1,0,5);}
-//Connect R6 input ports 0 to  T6 output ports 0
+    //Connect R6 input ports 0 to  T6 output ports 0
 void single_r2e6(void) {connect_r2e(2,2,0,6);}
-//Connect R7 input ports 0 to  T7 output ports 0
+    //Connect R7 input ports 0 to  T7 output ports 0
 void single_r2e7(void) {connect_r2e(2,3,0,7);}
-//Connect R12 input ports 0 to  T8 output ports 0
+    //Connect R12 input ports 0 to  T8 output ports 0
 void single_r2e8(void) {connect_r2e(2,4,0,8);}
-//Connect R13 input ports 0 to  T9 output ports 0
+    //Connect R13 input ports 0 to  T9 output ports 0
 void single_r2e9(void) {connect_r2e(2,5,0,9);}
-//Connect R14 input ports 0 to  T10 output ports 0
+    //Connect R14 input ports 0 to  T10 output ports 0
 void single_r2e10(void) {connect_r2e(2,6,0,10);}
-//Connect R15 input ports 0 to  T11 output ports 0
+    //Connect R15 input ports 0 to  T11 output ports 0
 void single_r2e11(void) {connect_r2e(2,7,0,11);}
-//Connect R8 input ports 0 to  T12 output ports 0
+    //Connect R8 input ports 0 to  T12 output ports 0
 void single_r2e12(void) {connect_r2e(3,0,0,12);}
-//Connect R9 input ports 0 to  T13 output ports 0
+    //Connect R9 input ports 0 to  T13 output ports 0
 void single_r2e13(void) {connect_r2e(3,1,0,13);}
-//Connect R10 input ports 0 to  T14 output ports 0
+    //Connect R10 input ports 0 to  T14 output ports 0
 void single_r2e14(void) {connect_r2e(3,2,0,14);}
-//Connect R11 input ports 0 to  T15 output ports 0
+    //Connect R11 input ports 0 to  T15 output ports 0
 void single_r2e15(void) {connect_r2e(3,3,0,15);}
 
 
-
 void (*r2r_func_ptr[48])() = {
 single_r2r0,single_r2r1,single_r2r2,single_r2r3,single_r2r4,single_r2r5,single_r2r6,single_r2r7,single_r2r8,single_r2r9
 ,single_r2r10,single_r2r11,single_r2r12,single_r2r13,single_r2r14,single_r2r15,single_r2r16,single_r2r17,single_r2r18,single_r2r19
@@ -145,17 +143,15 @@ single_r2e0,single_r2e1,single_r2e2,single_r2e3,single_r2e4,single_r2e5,single_r
 ,single_r2e10,single_r2e11,single_r2e12,single_r2e13,single_r2e14,single_r2e15};
 
 void topology_connect_r2r (int n){
-	 (*r2r_func_ptr[n])();
+        (*r2r_func_ptr[n])();
 }
 
 void topology_connect_r2e (int n){
-	 (*r2e_func_ptr[n])();
+        (*r2e_func_ptr[n])();
 }
 
-
-
 void topology_init(void){
-	router1[0]->current_r_addr=0;
+    router1[0]->current_r_addr=0;
 router1[0]->current_r_id=0;
 router1[1]->current_r_addr=1;
 router1[1]->current_r_id=1;
@@ -187,55 +183,55 @@ router3[2]->current_r_addr=14;
 router3[2]->current_r_id=14;
 router3[3]->current_r_addr=15;
 router3[3]->current_r_id=15;
-	r2r_cnt_all[0] =(r2r_cnt_table_t){.id1=0, .t1=1, .r1=0, .p1=1,.id2=10, .t2=2, .r2=6, .p2=3 };
-	r2r_cnt_all[1] =(r2r_cnt_table_t){.id1=0, .t1=1, .r1=0, .p1=2,.id2=9, .t2=2, .r2=5, .p2=3 };
-	r2r_cnt_all[2] =(r2r_cnt_table_t){.id1=1, .t1=1, .r1=1, .p1=1,.id2=7, .t2=2, .r2=3, .p2=3 };
-	r2r_cnt_all[3] =(r2r_cnt_table_t){.id1=1, .t1=1, .r1=1, .p1=2,.id2=2, .t2=1, .r2=2, .p2=2 };
-	r2r_cnt_all[4] =(r2r_cnt_table_t){.id1=2, .t1=1, .r1=2, .p1=1,.id2=11, .t2=2, .r2=7, .p2=2 };
-	r2r_cnt_all[5] =(r2r_cnt_table_t){.id1=2, .t1=1, .r1=2, .p1=2,.id2=1, .t2=1, .r2=1, .p2=2 };
-	r2r_cnt_all[6] =(r2r_cnt_table_t){.id1=3, .t1=1, .r1=3, .p1=1,.id2=11, .t2=2, .r2=7, .p2=3 };
-	r2r_cnt_all[7] =(r2r_cnt_table_t){.id1=3, .t1=1, .r1=3, .p1=2,.id2=4, .t2=2, .r2=0, .p2=2 };
-	r2r_cnt_all[8] =(r2r_cnt_table_t){.id1=4, .t1=2, .r1=0, .p1=1,.id2=13, .t2=3, .r2=1, .p2=2 };
-	r2r_cnt_all[9] =(r2r_cnt_table_t){.id1=4, .t1=2, .r1=0, .p1=2,.id2=3, .t2=1, .r2=3, .p2=2 };
-	r2r_cnt_all[10] =(r2r_cnt_table_t){.id1=4, .t1=2, .r1=0, .p1=3,.id2=6, .t2=2, .r2=2, .p2=3 };
-	r2r_cnt_all[11] =(r2r_cnt_table_t){.id1=5, .t1=2, .r1=1, .p1=1,.id2=15, .t2=3, .r2=3, .p2=4 };
-	r2r_cnt_all[12] =(r2r_cnt_table_t){.id1=5, .t1=2, .r1=1, .p1=2,.id2=6, .t2=2, .r2=2, .p2=2 };
-	r2r_cnt_all[13] =(r2r_cnt_table_t){.id1=5, .t1=2, .r1=1, .p1=3,.id2=9, .t2=2, .r2=5, .p2=2 };
-	r2r_cnt_all[14] =(r2r_cnt_table_t){.id1=6, .t1=2, .r1=2, .p1=1,.id2=13, .t2=3, .r2=1, .p2=3 };
-	r2r_cnt_all[15] =(r2r_cnt_table_t){.id1=6, .t1=2, .r1=2, .p1=2,.id2=5, .t2=2, .r2=1, .p2=2 };
-	r2r_cnt_all[16] =(r2r_cnt_table_t){.id1=6, .t1=2, .r1=2, .p1=3,.id2=4, .t2=2, .r2=0, .p2=3 };
-	r2r_cnt_all[17] =(r2r_cnt_table_t){.id1=7, .t1=2, .r1=3, .p1=1,.id2=8, .t2=2, .r2=4, .p2=3 };
-	r2r_cnt_all[18] =(r2r_cnt_table_t){.id1=7, .t1=2, .r1=3, .p1=2,.id2=10, .t2=2, .r2=6, .p2=2 };
-	r2r_cnt_all[19] =(r2r_cnt_table_t){.id1=7, .t1=2, .r1=3, .p1=3,.id2=1, .t2=1, .r2=1, .p2=1 };
-	r2r_cnt_all[20] =(r2r_cnt_table_t){.id1=8, .t1=2, .r1=4, .p1=1,.id2=12, .t2=3, .r2=0, .p2=4 };
-	r2r_cnt_all[21] =(r2r_cnt_table_t){.id1=8, .t1=2, .r1=4, .p1=2,.id2=14, .t2=3, .r2=2, .p2=3 };
-	r2r_cnt_all[22] =(r2r_cnt_table_t){.id1=8, .t1=2, .r1=4, .p1=3,.id2=7, .t2=2, .r2=3, .p2=1 };
-	r2r_cnt_all[23] =(r2r_cnt_table_t){.id1=9, .t1=2, .r1=5, .p1=1,.id2=12, .t2=3, .r2=0, .p2=2 };
-	r2r_cnt_all[24] =(r2r_cnt_table_t){.id1=9, .t1=2, .r1=5, .p1=2,.id2=5, .t2=2, .r2=1, .p2=3 };
-	r2r_cnt_all[25] =(r2r_cnt_table_t){.id1=9, .t1=2, .r1=5, .p1=3,.id2=0, .t2=1, .r2=0, .p2=2 };
-	r2r_cnt_all[26] =(r2r_cnt_table_t){.id1=10, .t1=2, .r1=6, .p1=1,.id2=12, .t2=3, .r2=0, .p2=3 };
-	r2r_cnt_all[27] =(r2r_cnt_table_t){.id1=10, .t1=2, .r1=6, .p1=2,.id2=7, .t2=2, .r2=3, .p2=2 };
-	r2r_cnt_all[28] =(r2r_cnt_table_t){.id1=10, .t1=2, .r1=6, .p1=3,.id2=0, .t2=1, .r2=0, .p2=1 };
-	r2r_cnt_all[29] =(r2r_cnt_table_t){.id1=11, .t1=2, .r1=7, .p1=1,.id2=14, .t2=3, .r2=2, .p2=4 };
-	r2r_cnt_all[30] =(r2r_cnt_table_t){.id1=11, .t1=2, .r1=7, .p1=2,.id2=2, .t2=1, .r2=2, .p2=1 };
-	r2r_cnt_all[31] =(r2r_cnt_table_t){.id1=11, .t1=2, .r1=7, .p1=3,.id2=3, .t2=1, .r2=3, .p2=1 };
-	r2r_cnt_all[32] =(r2r_cnt_table_t){.id1=12, .t1=3, .r1=0, .p1=1,.id2=15, .t2=3, .r2=3, .p2=1 };
-	r2r_cnt_all[33] =(r2r_cnt_table_t){.id1=12, .t1=3, .r1=0, .p1=2,.id2=9, .t2=2, .r2=5, .p2=1 };
-	r2r_cnt_all[34] =(r2r_cnt_table_t){.id1=12, .t1=3, .r1=0, .p1=3,.id2=10, .t2=2, .r2=6, .p2=1 };
-	r2r_cnt_all[35] =(r2r_cnt_table_t){.id1=12, .t1=3, .r1=0, .p1=4,.id2=8, .t2=2, .r2=4, .p2=1 };
-	r2r_cnt_all[36] =(r2r_cnt_table_t){.id1=13, .t1=3, .r1=1, .p1=1,.id2=15, .t2=3, .r2=3, .p2=3 };
-	r2r_cnt_all[37] =(r2r_cnt_table_t){.id1=13, .t1=3, .r1=1, .p1=2,.id2=4, .t2=2, .r2=0, .p2=1 };
-	r2r_cnt_all[38] =(r2r_cnt_table_t){.id1=13, .t1=3, .r1=1, .p1=3,.id2=6, .t2=2, .r2=2, .p2=1 };
-	r2r_cnt_all[39] =(r2r_cnt_table_t){.id1=13, .t1=3, .r1=1, .p1=4,.id2=14, .t2=3, .r2=2, .p2=2 };
-	r2r_cnt_all[40] =(r2r_cnt_table_t){.id1=14, .t1=3, .r1=2, .p1=1,.id2=15, .t2=3, .r2=3, .p2=2 };
-	r2r_cnt_all[41] =(r2r_cnt_table_t){.id1=14, .t1=3, .r1=2, .p1=2,.id2=13, .t2=3, .r2=1, .p2=4 };
-	r2r_cnt_all[42] =(r2r_cnt_table_t){.id1=14, .t1=3, .r1=2, .p1=3,.id2=8, .t2=2, .r2=4, .p2=2 };
-	r2r_cnt_all[43] =(r2r_cnt_table_t){.id1=14, .t1=3, .r1=2, .p1=4,.id2=11, .t2=2, .r2=7, .p2=1 };
-	r2r_cnt_all[44] =(r2r_cnt_table_t){.id1=15, .t1=3, .r1=3, .p1=1,.id2=12, .t2=3, .r2=0, .p2=1 };
-	r2r_cnt_all[45] =(r2r_cnt_table_t){.id1=15, .t1=3, .r1=3, .p1=2,.id2=14, .t2=3, .r2=2, .p2=1 };
-	r2r_cnt_all[46] =(r2r_cnt_table_t){.id1=15, .t1=3, .r1=3, .p1=3,.id2=13, .t2=3, .r2=1, .p2=1 };
-	r2r_cnt_all[47] =(r2r_cnt_table_t){.id1=15, .t1=3, .r1=3, .p1=4,.id2=5, .t2=2, .r2=1, .p2=1 };
+    r2r_cnt_all[0] =(r2r_cnt_table_t){.id1=0, .t1=1, .r1=0, .p1=1,.id2=10, .t2=2, .r2=6, .p2=3 };
+    r2r_cnt_all[1] =(r2r_cnt_table_t){.id1=0, .t1=1, .r1=0, .p1=2,.id2=9, .t2=2, .r2=5, .p2=3 };
+    r2r_cnt_all[2] =(r2r_cnt_table_t){.id1=1, .t1=1, .r1=1, .p1=1,.id2=7, .t2=2, .r2=3, .p2=3 };
+    r2r_cnt_all[3] =(r2r_cnt_table_t){.id1=1, .t1=1, .r1=1, .p1=2,.id2=2, .t2=1, .r2=2, .p2=2 };
+    r2r_cnt_all[4] =(r2r_cnt_table_t){.id1=2, .t1=1, .r1=2, .p1=1,.id2=11, .t2=2, .r2=7, .p2=2 };
+    r2r_cnt_all[5] =(r2r_cnt_table_t){.id1=2, .t1=1, .r1=2, .p1=2,.id2=1, .t2=1, .r2=1, .p2=2 };
+    r2r_cnt_all[6] =(r2r_cnt_table_t){.id1=3, .t1=1, .r1=3, .p1=1,.id2=11, .t2=2, .r2=7, .p2=3 };
+    r2r_cnt_all[7] =(r2r_cnt_table_t){.id1=3, .t1=1, .r1=3, .p1=2,.id2=4, .t2=2, .r2=0, .p2=2 };
+    r2r_cnt_all[8] =(r2r_cnt_table_t){.id1=4, .t1=2, .r1=0, .p1=1,.id2=13, .t2=3, .r2=1, .p2=2 };
+    r2r_cnt_all[9] =(r2r_cnt_table_t){.id1=4, .t1=2, .r1=0, .p1=2,.id2=3, .t2=1, .r2=3, .p2=2 };
+    r2r_cnt_all[10] =(r2r_cnt_table_t){.id1=4, .t1=2, .r1=0, .p1=3,.id2=6, .t2=2, .r2=2, .p2=3 };
+    r2r_cnt_all[11] =(r2r_cnt_table_t){.id1=5, .t1=2, .r1=1, .p1=1,.id2=15, .t2=3, .r2=3, .p2=4 };
+    r2r_cnt_all[12] =(r2r_cnt_table_t){.id1=5, .t1=2, .r1=1, .p1=2,.id2=6, .t2=2, .r2=2, .p2=2 };
+    r2r_cnt_all[13] =(r2r_cnt_table_t){.id1=5, .t1=2, .r1=1, .p1=3,.id2=9, .t2=2, .r2=5, .p2=2 };
+    r2r_cnt_all[14] =(r2r_cnt_table_t){.id1=6, .t1=2, .r1=2, .p1=1,.id2=13, .t2=3, .r2=1, .p2=3 };
+    r2r_cnt_all[15] =(r2r_cnt_table_t){.id1=6, .t1=2, .r1=2, .p1=2,.id2=5, .t2=2, .r2=1, .p2=2 };
+    r2r_cnt_all[16] =(r2r_cnt_table_t){.id1=6, .t1=2, .r1=2, .p1=3,.id2=4, .t2=2, .r2=0, .p2=3 };
+    r2r_cnt_all[17] =(r2r_cnt_table_t){.id1=7, .t1=2, .r1=3, .p1=1,.id2=8, .t2=2, .r2=4, .p2=3 };
+    r2r_cnt_all[18] =(r2r_cnt_table_t){.id1=7, .t1=2, .r1=3, .p1=2,.id2=10, .t2=2, .r2=6, .p2=2 };
+    r2r_cnt_all[19] =(r2r_cnt_table_t){.id1=7, .t1=2, .r1=3, .p1=3,.id2=1, .t2=1, .r2=1, .p2=1 };
+    r2r_cnt_all[20] =(r2r_cnt_table_t){.id1=8, .t1=2, .r1=4, .p1=1,.id2=12, .t2=3, .r2=0, .p2=4 };
+    r2r_cnt_all[21] =(r2r_cnt_table_t){.id1=8, .t1=2, .r1=4, .p1=2,.id2=14, .t2=3, .r2=2, .p2=3 };
+    r2r_cnt_all[22] =(r2r_cnt_table_t){.id1=8, .t1=2, .r1=4, .p1=3,.id2=7, .t2=2, .r2=3, .p2=1 };
+    r2r_cnt_all[23] =(r2r_cnt_table_t){.id1=9, .t1=2, .r1=5, .p1=1,.id2=12, .t2=3, .r2=0, .p2=2 };
+    r2r_cnt_all[24] =(r2r_cnt_table_t){.id1=9, .t1=2, .r1=5, .p1=2,.id2=5, .t2=2, .r2=1, .p2=3 };
+    r2r_cnt_all[25] =(r2r_cnt_table_t){.id1=9, .t1=2, .r1=5, .p1=3,.id2=0, .t2=1, .r2=0, .p2=2 };
+    r2r_cnt_all[26] =(r2r_cnt_table_t){.id1=10, .t1=2, .r1=6, .p1=1,.id2=12, .t2=3, .r2=0, .p2=3 };
+    r2r_cnt_all[27] =(r2r_cnt_table_t){.id1=10, .t1=2, .r1=6, .p1=2,.id2=7, .t2=2, .r2=3, .p2=2 };
+    r2r_cnt_all[28] =(r2r_cnt_table_t){.id1=10, .t1=2, .r1=6, .p1=3,.id2=0, .t2=1, .r2=0, .p2=1 };
+    r2r_cnt_all[29] =(r2r_cnt_table_t){.id1=11, .t1=2, .r1=7, .p1=1,.id2=14, .t2=3, .r2=2, .p2=4 };
+    r2r_cnt_all[30] =(r2r_cnt_table_t){.id1=11, .t1=2, .r1=7, .p1=2,.id2=2, .t2=1, .r2=2, .p2=1 };
+    r2r_cnt_all[31] =(r2r_cnt_table_t){.id1=11, .t1=2, .r1=7, .p1=3,.id2=3, .t2=1, .r2=3, .p2=1 };
+    r2r_cnt_all[32] =(r2r_cnt_table_t){.id1=12, .t1=3, .r1=0, .p1=1,.id2=15, .t2=3, .r2=3, .p2=1 };
+    r2r_cnt_all[33] =(r2r_cnt_table_t){.id1=12, .t1=3, .r1=0, .p1=2,.id2=9, .t2=2, .r2=5, .p2=1 };
+    r2r_cnt_all[34] =(r2r_cnt_table_t){.id1=12, .t1=3, .r1=0, .p1=3,.id2=10, .t2=2, .r2=6, .p2=1 };
+    r2r_cnt_all[35] =(r2r_cnt_table_t){.id1=12, .t1=3, .r1=0, .p1=4,.id2=8, .t2=2, .r2=4, .p2=1 };
+    r2r_cnt_all[36] =(r2r_cnt_table_t){.id1=13, .t1=3, .r1=1, .p1=1,.id2=15, .t2=3, .r2=3, .p2=3 };
+    r2r_cnt_all[37] =(r2r_cnt_table_t){.id1=13, .t1=3, .r1=1, .p1=2,.id2=4, .t2=2, .r2=0, .p2=1 };
+    r2r_cnt_all[38] =(r2r_cnt_table_t){.id1=13, .t1=3, .r1=1, .p1=3,.id2=6, .t2=2, .r2=2, .p2=1 };
+    r2r_cnt_all[39] =(r2r_cnt_table_t){.id1=13, .t1=3, .r1=1, .p1=4,.id2=14, .t2=3, .r2=2, .p2=2 };
+    r2r_cnt_all[40] =(r2r_cnt_table_t){.id1=14, .t1=3, .r1=2, .p1=1,.id2=15, .t2=3, .r2=3, .p2=2 };
+    r2r_cnt_all[41] =(r2r_cnt_table_t){.id1=14, .t1=3, .r1=2, .p1=2,.id2=13, .t2=3, .r2=1, .p2=4 };
+    r2r_cnt_all[42] =(r2r_cnt_table_t){.id1=14, .t1=3, .r1=2, .p1=3,.id2=8, .t2=2, .r2=4, .p2=2 };
+    r2r_cnt_all[43] =(r2r_cnt_table_t){.id1=14, .t1=3, .r1=2, .p1=4,.id2=11, .t2=2, .r2=7, .p2=1 };
+    r2r_cnt_all[44] =(r2r_cnt_table_t){.id1=15, .t1=3, .r1=3, .p1=1,.id2=12, .t2=3, .r2=0, .p2=1 };
+    r2r_cnt_all[45] =(r2r_cnt_table_t){.id1=15, .t1=3, .r1=3, .p1=2,.id2=14, .t2=3, .r2=2, .p2=1 };
+    r2r_cnt_all[46] =(r2r_cnt_table_t){.id1=15, .t1=3, .r1=3, .p1=3,.id2=13, .t2=3, .r2=1, .p2=1 };
+    r2r_cnt_all[47] =(r2r_cnt_table_t){.id1=15, .t1=3, .r1=3, .p1=4,.id2=5, .t2=2, .r2=1, .p2=1 };
 
-	R2R_TABLE_SIZ=48;
-	 	 
+    R2R_TABLE_SIZ=48;
+          
 }
diff --git a/mpsoc/src_verilator/topology/fattree.h b/mpsoc/src_verilator/topology/fattree.h
index e16d878..c21a753 100644
--- a/mpsoc/src_verilator/topology/fattree.h
+++ b/mpsoc/src_verilator/topology/fattree.h
@@ -1,247 +1,202 @@
 #ifndef FATTREE_H
-	#define FATTREE_H
-
-
-
-unsigned int    Lw;
-unsigned int    Kw;
-unsigned int    LKw;
-unsigned int    RAw_FATTREE;
-unsigned int    EAw_FATTREE;
-unsigned int    NE_FATTREE;
-unsigned int    NR_FATTREE;
-unsigned int    DSTPw_FATTREE ;
-unsigned int    MAX_P_FATTREE ;
-
-
+#define FATTREE_H
+    
+unsigned int Lw;
+unsigned int Kw;
+unsigned int LKw;
+unsigned int RAw_FATTREE;
+unsigned int EAw_FATTREE;
+unsigned int NE_FATTREE;
+unsigned int NR_FATTREE;
+unsigned int DSTPw_FATTREE;
+unsigned int MAX_P_FATTREE;
 unsigned int NPOS = powi( K, L-1);
 unsigned int CHAN_PER_DIRECTION = (K * powi( L , L-1 )); //up or down
-unsigned int CHAN_PER_LEVEL = 2*(K * powi( K , L-1 )); //up+down
-
-
-
-
-
-
+unsigned int CHAN_PER_LEVEL = 2 * (K * powi( K , L-1 )); //up+down
 
+#ifndef FLAT_MODE
 inline void fatree_local_addr (unsigned int t1, unsigned int r1, unsigned int addr, unsigned int id){
-	if (t1==1 ){
-		router1[r1]->current_r_addr = addr;
-		router1[r1]->current_r_id   = id;
-	}
-	else{
-		router2[r1]->current_r_addr = addr;
-		router2[r1]->current_r_id   = id;
-	}
-
+    if (t1==1 ){
+        router1[r1]->current_r_addr = addr;
+        router1[r1]->current_r_id   = id;
+    }
+    else{
+        router2[r1]->current_r_addr = addr;
+        router2[r1]->current_r_id   = id;
+    }
 }
-
+#endif //FLAT_MODE
 
 unsigned int fattree_addrencode( unsigned int pos, unsigned int k, unsigned int l){
-	unsigned int pow,i,tmp=0;
-	unsigned int addrencode=0;
-	unsigned int kw=0;
-	while((0x1<<kw) < k)kw++;
-	pow=1;
-	for (i = 0; i <l; i=i+1 ) {
-		tmp=(pos/pow);
-		tmp=tmp%k;
-		tmp=tmp<<(i)*kw;
-		addrencode=addrencode | tmp;
-		pow=pow * k;
-	}
-	 return addrencode;
+    unsigned int pow,i,tmp=0;
+    unsigned int addrencode=0;
+    unsigned int kw=0;
+    while((0x1<<kw) < k)kw++;
+    pow=1;
+    for (i = 0; i <l; i=i+1 ) {
+        tmp=(pos/pow);
+        tmp=tmp%k;
+        tmp=tmp<<(i)*kw;
+        addrencode=addrencode | tmp;
+        pow=pow * k;
+    }
+    return addrencode;
 }
 
-
 unsigned int fattree_addrdecode(unsigned int addrencode , unsigned int k, unsigned int l){
-	unsigned int kw=0;
-	unsigned int mask=0;
-	unsigned int pow,i,tmp;
-	unsigned int pos=0;
-	while((0x1<<kw) < k){
-		kw++;
-		mask<<=1;
-		mask|=0x1;
-	}
-	pow=1;
-	for (i = 0; i <l; i=i+1 ) {
-		tmp = addrencode & mask;
-		tmp=(tmp*pow);
-		pos= pos + tmp;
-		pow=pow * k;
-		addrencode>>=kw;
-	}
-	return pos;
+    unsigned int kw=0;
+    unsigned int mask=0;
+    unsigned int pow,i,tmp;
+    unsigned int pos=0;
+    while((0x1<<kw) < k){
+        kw++;
+        mask<<=1;
+        mask|=0x1;
+    }
+    pow=1;
+    for (i = 0; i <l; i=i+1 ) {
+        tmp = addrencode & mask;
+        tmp=(tmp*pow);
+        pos= pos + tmp;
+        pow=pow * k;
+        addrencode>>=kw;
+    }
+    return pos;
 }
 
 unsigned int endp_addr_encoder ( unsigned int id){
-			return fattree_addrencode(id, T1, T2);
+    return fattree_addrencode(id, T1, T2);
 }
 
 unsigned int endp_addr_decoder (unsigned int code){
-		return fattree_addrdecode(code, T1, T2);
+    return fattree_addrdecode(code, T1, T2);
 }
 
-
 void topology_init (void){
-	unsigned int pos,level,port;
-
-	Lw= Log2(L);
-	Kw=Log2(K);
-	LKw=L*Kw;
-	RAw_FATTREE =  LKw + Lw;
-	EAw_FATTREE  = LKw;
-	NE_FATTREE = powi( K,L ); 
-	NR_FATTREE = L * powi( K , L - 1 );  // total number of routers  
-	DSTPw_FATTREE = K+1;
-	MAX_P_FATTREE = 2*K;		
-	#define NRL (NE/K) //number of router in  each layer     
-
+    unsigned int pos,level,port;
+    Lw= Log2(L);
+    Kw=Log2(K);
+    LKw=L*Kw;
+    RAw_FATTREE =  LKw + Lw;
+    EAw_FATTREE  = LKw;
+    NE_FATTREE = powi( K,L ); 
+    NR_FATTREE = L * powi( K , L - 1 );  // total number of routers  
+    DSTPw_FATTREE = K+1;
+    MAX_P_FATTREE = 2*K;        
+    #define NRL (NE/K) //number of router in  each layer     
     unsigned int num = 0;
-	//connect all down input chanels
-	for (level = 0; level<L-1; level=level+1) {// : level_c
-	/* verilator lint_off WIDTH */
-		unsigned int  LEAVE_L = L-1-level;
-	/* verilator lint_on WIDTH */    
-		//input chanel are numbered interleavely, the interleaev dep}s on level
-		unsigned int ROUTERS_PER_NEIGHBORHOOD = powi(K,L-1-(level)); 
-		unsigned int ROUTERS_PER_BRANCH = powi(K,L-1-(level+1)); 
-		unsigned int LEVEL_OFFSET = ROUTERS_PER_NEIGHBORHOOD*K;
-		for ( pos = 0; pos < NPOS; pos=pos+1 ) {// : pos_c
-		    unsigned int ADRRENCODED=fattree_addrencode(pos,K,L);
-		    unsigned int NEIGHBORHOOD = (pos/ROUTERS_PER_NEIGHBORHOOD);
-		    unsigned int NEIGHBORHOOD_POS = pos % ROUTERS_PER_NEIGHBORHOOD;
-		    for ( port = 0; port < K; port=port+1 ) {// : port_c
-		        unsigned int LINK = 
-		            ((level+1)*CHAN_PER_LEVEL - CHAN_PER_DIRECTION)  //which levellevel
-		            +NEIGHBORHOOD* LEVEL_OFFSET   //region in level
-		            +port*ROUTERS_PER_BRANCH*K //sub region in region
-		            +(NEIGHBORHOOD_POS)%ROUTERS_PER_BRANCH*K //router in subregion
-		            +(NEIGHBORHOOD_POS)/ROUTERS_PER_BRANCH; //port on router
-
-
-		        unsigned int L2= (LINK+CHAN_PER_DIRECTION)/CHAN_PER_LEVEL;
-		        unsigned int POS2 = ((LINK+CHAN_PER_DIRECTION) % CHAN_PER_LEVEL)/K;
-		        unsigned int PORT2= (((LINK+CHAN_PER_DIRECTION) % CHAN_PER_LEVEL)  %K)+K;
-		        unsigned int ID1 =NRL*level+pos;
-		        unsigned int ID2 =NRL*L2 + POS2;
-		        unsigned int POS_ADR_CODE2= fattree_addrencode(POS2,K,L);
-		        unsigned int POS_ADR_CODE1= fattree_addrencode(pos,K,L);
-		       
-		
-		     	
-				
-		       //fattree_connect(Ti(ID1),Ri(ID1),port,Ti(ID2),Ri(ID2),PORT2);
-		        r2r_cnt_all[num] =(r2r_cnt_table_t){.id1=ID1, .t1=Ti(ID1), .r1=Ri(ID1), .p1=port, .id2=ID2, .t2=Ti(ID2), .r2=Ri(ID2), .p2=PORT2 };
-		        unsigned int current_layer_addr = LEAVE_L;
-		        unsigned int current_pos_addr   = ADRRENCODED;  
-				unsigned int addr = (current_layer_addr << LKw)| current_pos_addr;       
-		       
+    #ifndef FLAT_MODE
+    //connect all down input chanels
+    for (level = 0; level<L-1; level=level+1) {// : level_c
+    /* verilator lint_off WIDTH */
+        unsigned int  LEAVE_L = L-1-level;
+    /* verilator lint_on WIDTH */    
+        //input chanel are numbered interleavely, the interleaev dep}s on level
+        unsigned int ROUTERS_PER_NEIGHBORHOOD = powi(K,L-1-(level)); 
+        unsigned int ROUTERS_PER_BRANCH = powi(K,L-1-(level+1)); 
+        unsigned int LEVEL_OFFSET = ROUTERS_PER_NEIGHBORHOOD*K;
+        for ( pos = 0; pos < NPOS; pos=pos+1 ) {// : pos_c
+            unsigned int ADRRENCODED=fattree_addrencode(pos,K,L);
+            unsigned int NEIGHBORHOOD = (pos/ROUTERS_PER_NEIGHBORHOOD);
+            unsigned int NEIGHBORHOOD_POS = pos % ROUTERS_PER_NEIGHBORHOOD;
+            for ( port = 0; port < K; port=port+1 ) {// : port_c
+                unsigned int LINK = 
+                    ((level+1)*CHAN_PER_LEVEL - CHAN_PER_DIRECTION)  //which levellevel
+                    +NEIGHBORHOOD* LEVEL_OFFSET   //region in level
+                    +port*ROUTERS_PER_BRANCH*K //sub region in region
+                    +(NEIGHBORHOOD_POS)%ROUTERS_PER_BRANCH*K //router in subregion
+                    +(NEIGHBORHOOD_POS)/ROUTERS_PER_BRANCH; //port on router
+                unsigned int L2= (LINK+CHAN_PER_DIRECTION)/CHAN_PER_LEVEL;
+                unsigned int POS2 = ((LINK+CHAN_PER_DIRECTION) % CHAN_PER_LEVEL)/K;
+                unsigned int PORT2= (((LINK+CHAN_PER_DIRECTION) % CHAN_PER_LEVEL)  %K)+K;
+                unsigned int ID1 =NRL*level+pos;
+                unsigned int ID2 =NRL*L2 + POS2;
+                unsigned int POS_ADR_CODE2= fattree_addrencode(POS2,K,L);
+                unsigned int POS_ADR_CODE1= fattree_addrencode(pos,K,L);
+                
+               //fattree_connect(Ti(ID1),Ri(ID1),port,Ti(ID2),Ri(ID2),PORT2);
+                r2r_cnt_all[num] =(r2r_cnt_table_t){.id1=ID1, .t1=Ti(ID1), .r1=Ri(ID1), .p1=port, .id2=ID2, .t2=Ti(ID2), .r2=Ri(ID2), .p2=PORT2 };
+                unsigned int current_layer_addr = LEAVE_L;
+                unsigned int current_pos_addr   = ADRRENCODED;  
+                unsigned int addr = (current_layer_addr << LKw)| current_pos_addr;       
+                
 //printf( "[%u] = t1=%u, r1=%u, p1=%u, t2=%u, r2=%u, p2=%u \n",  num, r2r_cnt_all[num].t1, r2r_cnt_all[num].r1, r2r_cnt_all[num].p1, r2r_cnt_all[num].t2, r2r_cnt_all[num].r2, r2r_cnt_all[num].p2 );
-				 //assign current_r_addr [ID1] = {current_layer_addr [ID1],current_pos_addr[ID1]};
-				fatree_local_addr(Ti(ID1),Ri(ID1),  addr, ID1);
-
-
-				if(level==L-2){// 
-					current_layer_addr  =0;
-		        	current_pos_addr = POS_ADR_CODE2;
-					addr = (current_layer_addr << LKw)| current_pos_addr;           
-		        	 //assign current_r_addr [ID2] = {current_layer_addr [ID2],current_pos_addr[ID2]};
-					fatree_local_addr(Ti(ID2),Ri(ID2),  addr, ID2);
-				}//if
-		     num++;
-		     }
-		}
-	} 
-
-	R2R_TABLE_SIZ=num;
-
-	for ( pos = 0; pos <  NE; pos=pos+1 ) {// : }points
-		unsigned int RID= NRL*(L-1)+(pos/K);
-		unsigned int RPORT = pos%K;
-		//connected router encoded address
-		unsigned int  CURRENTPOS=   fattree_addrencode(pos/K,K,L);
-		
- 
-		//assign router_chan_out [RID][RPORT] =    chan_in_all [pos];                     
-		//assign chan_out_all [pos] = router_chan_in [RID][RPORT]; 
-		//assign er_addr [pos] = CURRENTPOS [RAw-1 : 0];
-       
-		r2e_cnt_all[pos].r1=Ri(RID);
-		r2e_cnt_all[pos].p1=RPORT;
-		er_addr [pos] = CURRENTPOS;
-
-		//printf( "[%u] =r1=%u,p1=%u\n",pos,r2e_cnt_all[pos].r1,r2e_cnt_all[pos].p1);
-
-		//connect_r2e(2,Ri(RID),RPORT,pos);     
-   }
+                 //assign current_r_addr [ID1] = {current_layer_addr [ID1],current_pos_addr[ID1]};
+                fatree_local_addr(Ti(ID1),Ri(ID1),  addr, ID1);
+                if(level==L-2){// 
+                    current_layer_addr  =0;
+                    current_pos_addr = POS_ADR_CODE2;
+                    addr = (current_layer_addr << LKw)| current_pos_addr;           
+                     //assign current_r_addr [ID2] = {current_layer_addr [ID2],current_pos_addr[ID2]};
+                    fatree_local_addr(Ti(ID2),Ri(ID2),  addr, ID2);
+                }//if
+            num++;
+            }
+        }
+    } 
+    R2R_TABLE_SIZ=num;
+    for ( pos = 0; pos <  NE; pos=pos+1 ) {// : }points
+        unsigned int RID= NRL*(L-1)+(pos/K);
+        unsigned int RPORT = pos%K;
+        //connected router encoded address
+        unsigned int  CURRENTPOS=   fattree_addrencode(pos/K,K,L);
+        
+        //assign router_chan_out [RID][RPORT] =    chan_in_all [pos];                     
+        //assign chan_out_all [pos] = router_chan_in [RID][RPORT]; 
+        //assign er_addr [pos] = CURRENTPOS [RAw-1 : 0];
+        r2e_cnt_all[pos].r1=Ri(RID);
+        r2e_cnt_all[pos].p1=RPORT;
+        er_addr [pos] = CURRENTPOS;
+        //printf( "[%u] =r1=%u,p1=%u\n",pos,r2e_cnt_all[pos].r1,r2e_cnt_all[pos].p1);
+        //connect_r2e(2,Ri(RID),RPORT,pos);     
+    }
+    #endif //FLAT_MODE
 }
 
-
-
 void topology_connect_r2r (int n){
-	fattree_connect(r2r_cnt_all[n]);
+    fattree_connect(r2r_cnt_all[n]);
 }
 
 void topology_connect_r2e (int n){
-	connect_r2e(2,r2e_cnt_all[n].r1,r2e_cnt_all[n].p1,n);
+    connect_r2e(2,r2e_cnt_all[n].r1,r2e_cnt_all[n].p1,n);
 }
 
-
-
 /*
 void topology_connect_all_nodes (void){
-
-	unsigned int pos,level,port;
-	unsigned int num = 0;
-	
-	for (level = 0; level<L-1; level=level+1) {// : level_c
-		for ( pos = 0; pos < NPOS; pos=pos+1 ) {// : pos_c
-		   for ( port = 0; port < K; port=port+1 ) {// : port_c		           
-						
-		        fattree_connect(r2r_cnt_all[num]);
-		        num++;
-		        	     
-		     }
-		}
-	} 
-     
-   
-	for ( pos = 0; pos <  NE; pos=pos+1 ) {// : }points
-		
-		
-		connect_r2e(2,r2e_cnt_all[pos].r1,r2e_cnt_all[pos].p1,pos);     
-
- 
-	 }
-	
+    unsigned int pos,level,port;
+    unsigned int num = 0;
+    for (level = 0; level<L-1; level=level+1) {// : level_c
+        for ( pos = 0; pos < NPOS; pos=pos+1 ) {// : pos_c
+            for ( port = 0; port < K; port=port+1 ) {// : port_c                   
+                        
+                fattree_connect(r2r_cnt_all[num]);
+                num++;
+            }
+        }
+    } 
+    for ( pos = 0; pos <  NE; pos=pos+1 ) {// : }points
+        
+        
+        connect_r2e(2,r2e_cnt_all[pos].r1,r2e_cnt_all[pos].p1,pos);     
+    }
 }
 */
 
-
 unsigned int get_mah_distance ( unsigned int id1, unsigned int id2){
-
-	unsigned int k =T1;
-	unsigned int l =T2;
-
-	unsigned int pow,tmp1,tmp2;
-	unsigned int distance=0;
-	pow=1;
-	for (unsigned int i = 0; i <l; i=i+1 ) {
-		tmp1=(id1/pow);
-		tmp2=(id2/pow);
-		tmp1=tmp1 % k;
-		tmp2=tmp2 % k;
-		pow=pow * k;
-		if(tmp1!=tmp2) distance= (i+1)*2-1 ; //distance obtained based on the highest level index which differ
-
-	}
-	 return distance;
+    unsigned int k =T1;
+    unsigned int l =T2;
+    unsigned int pow,tmp1,tmp2;
+    unsigned int distance=0;
+    pow=1;
+    for (unsigned int i = 0; i <l; i=i+1 ) {
+        tmp1=(id1/pow);
+        tmp2=(id2/pow);
+        tmp1=tmp1 % k;
+        tmp2=tmp2 % k;
+        pow=pow * k;
+        if(tmp1!=tmp2) distance= (i+1)*2-1 ; //distance obtained based on the highest level index which differ
+    }
+    return distance;
 }
 
-
-
-
-
 #endif
diff --git a/mpsoc/src_verilator/topology/mesh.h b/mpsoc/src_verilator/topology/mesh.h
index adf6ef4..5f9ba85 100644
--- a/mpsoc/src_verilator/topology/mesh.h
+++ b/mpsoc/src_verilator/topology/mesh.h
@@ -1,560 +1,294 @@
 #ifndef MESH_H
-	#define MESH_H
-
-	#define  LOCAL		0
-	#define  EAST       1
-	#define  NORTH      2
-	#define  WEST       3
-	#define  SOUTH      4
-
-	//ring line
-	#define  FORWARD    1
-	#define  BACKWARD   2
-	#define router_id(x,y)  ((y * T1) +    x)
-	#define endp_id(x,y,l)  ((y * T1) +    x) * T3 + l
-
-
-
-	unsigned int nxw=0;
-	unsigned int nyw=0;
-	unsigned int maskx=0;
-	unsigned int masky=0;
-
-
-
-	void mesh_tori_addrencod_sep(unsigned int id, unsigned int *x, unsigned int *y, unsigned int *l){
-		(*l)=id%T3; // id%NL
-		(*x)=(id/T3)%T1;// (id/NL)%NX
-		(*y)=(id/T3)/T1;// (id/NL)/NX
-	}
-
-
-	void mesh_tori_addr_sep(unsigned int code, unsigned int *x, unsigned int *y, unsigned int *l){
-		(*x) = code &  maskx;
-		code>>=nxw;
-		(*y) = code &  masky;
-		code>>=nyw;
-		(*l) = code;
-	}
-
-	void ring_line_addr_sep(unsigned int code, unsigned int *x, unsigned int *l){
-		(*x) = code &  maskx;
-		code>>=nxw;		
-		(*l) = code;
-	}
-
-	unsigned int mesh_tori_addr_join(unsigned int x, unsigned int y, unsigned int l){
-		unsigned int addrencode=0;
-		addrencode =(T3==1)?   (y<<nxw | x) : (l<<(nxw+nyw)|  (y<<nxw) | x);
-		return addrencode;
-	}
-
-    unsigned int ring_line_addr_join(unsigned int x, unsigned int l){
-		unsigned int addrencode=0;
-		addrencode =(T3==1)?   x : (l<<nxw) | x;
-		return addrencode;
-	}
-
-
-	unsigned int mesh_tori_addrencode (unsigned int id){
-		unsigned int y, x, l;
-		mesh_tori_addrencod_sep(id,&x,&y,&l);
-		return mesh_tori_addr_join(x,y,l);
-	}
-
-	unsigned int ring_line_addrencode (unsigned int id){
-		unsigned int y , x, l;
-		mesh_tori_addrencod_sep(id,&x,&y,&l);
-		return ring_line_addr_join(x,l);
-	}
-
-
-	void fmesh_addrencod_sep(unsigned int id, unsigned int *x, unsigned int *y, unsigned int *p){
-		unsigned int  l, diff,mul,addrencode;
-		mul  = T1*T2*T3;
-		if(id < mul) {
-			*y = ((id/T3) / T1 );
-			*x = ((id/T3) % T1 );
-			l = (id % T3);
-			*p = (l==0)? LOCAL : 4+l;
-		}else{
-			diff = id -  mul ;
-			if( diff <  T1) { //top mesh edge
-					*y = 0;
-					*x = diff;
-					*p = NORTH;
-			} else if  ( diff < 2* T1) { //bottom mesh edge
-					*y = T2-1;
-					*x = diff-T1;
-					*p = SOUTH;
-			} else if  ( diff < (2* T1) + T2 ) { //left mesh edge
-					*y = diff - (2* T1);
-					*x = 0;
-					*p = WEST;
-			} else { //right mesh edge
-					*y = diff - (2* T1) -T2;
-					*x = T1-1;
-					*p = EAST;
-			}
-		}
-
-	}
-
-
-	unsigned int fmesh_addrencode(unsigned int id){
-	//input integer in,nx,nxw,nl,nyw,ny;
-		unsigned int  y, x, p, addrencode;
-		fmesh_addrencod_sep(id, &x, &y, &p);
-		addrencode = ( p<<(nxw+nyw) | (y<<nxw) | x);
-		return addrencode;
-	}
-
-
-	unsigned int fmesh_endp_addr_decoder (unsigned int code){
-		unsigned int x, y, p;
-		mesh_tori_addr_sep(code,&x,&y,&p);
-		if(p== LOCAL)	return ((y*T1)+x)*T3;
-		if(p > SOUTH)   return ((y*T1)+x)*T3+(p-SOUTH);
-		if(p== NORTH)   return ((T1*T2*T3) + x);
-		if(p== SOUTH)   return ((T1*T2*T3) + T1 + x);
-		if(p== WEST )   return ((T1*T2*T3) + 2*T1 + y);
-		if(p== EAST )   return ((T1*T2*T3) + 2*T1 + T2 + y);
-		return 0;//should not reach here
-	}
-
-
-
-
-
-
-	unsigned int mesh_tori_endp_addr_decoder (unsigned int code){
-		unsigned int x, y, l;
-		mesh_tori_addr_sep(code,&x,&y,&l);
-		//if(code==0x1a) printf("code=%x,x=%u,y=%u,l=%u\n",code,x,y,l);
-		return ((y*T1)+x)*T3+l;
-	}
-
-	unsigned int ring_line_endp_addr_decoder (unsigned int code){
-		unsigned int x, l;
-		ring_line_addr_sep(code,&x,&l);
-		//if(code==0x1a) printf("code=%x,x=%u,y=%u,l=%u\n",code,x,y,l);
-		return x*T3+l;
-	}
-
-
-
-
-	unsigned int endp_addr_encoder ( unsigned int id){
-			#if defined (IS_MESH) || defined (IS_TORUS)
-				return mesh_tori_addrencode(id);
-			#elif  defined (IS_LINE) || defined (IS_RING )
-				return ring_line_addrencode(id);
-			#else
-				return fmesh_addrencode(id);
-			#endif
-	}
-
-
-	unsigned int endp_addr_decoder (unsigned int code){
-		#if defined (IS_MESH) || defined (IS_TORUS)
-			return mesh_tori_endp_addr_decoder (code);
-		#elif defined (IS_LINE) || defined (IS_RING )
-			return ring_line_endp_addr_decoder (code);		
-		#endif
-		return fmesh_endp_addr_decoder (code);
-	}
+#define MESH_H
+
+#define  LOCAL      0
+#define  EAST       1
+#define  NORTH      2
+#define  SOUTH      4
+//ring line
+#define  FORWARD    1
+#define  BACKWARD   2
+
+#define UP          5
+#define DOWN        6
+
+#if defined (IS_LINE) || defined (IS_RING )
+    #define X_MAX  T1
+    #define Y_MAX  1
+    #define Z_MAX  1
+    #define L_MAX  T3
+    #define DIM    1
+#elif defined (IS_MESH_3D)
+    #define X_MAX  T1
+    #define Y_MAX  T2
+    #define Z_MAX  T3
+    #define L_MAX  T4
+    #define DIM    3
+#elif defined (IS_TORUS) || defined (IS_MESH) || defined (IS_FMESH)
+    #define X_MAX  T1
+    #define Y_MAX  T2
+    #define Z_MAX  1
+    #define L_MAX  T3
+    #define DIM    2
+#endif
 
+#if defined (IS_LINE) || defined (IS_RING )
+    #define  WEST       BACKWARD
+    #define R2R_CHANELS_MESH_TORI   2
+#else 
+    #define  WEST       3
+    #if defined (IS_MESH_3D)
+        #define R2R_CHANELS_MESH_TORI   6
+    #else
+        #define R2R_CHANELS_MESH_TORI   4
+    #endif //IS_MESH_3D
+#endif
 
-void topology_connect_r2r (int n){
-	conect_r2r(1,r2r_cnt_all[n].r1,r2r_cnt_all[n].p1,1,r2r_cnt_all[n].r2,r2r_cnt_all[n].p2);
+#define router_id(x,y,z) (((z) * Y_MAX * X_MAX) + ((y) * X_MAX) + x)
+#define endp_id(x,y,z,l) ((router_id(x,y,z) * L_MAX) + l)
+
+unsigned int nxw=0;
+unsigned int nyw=0;
+unsigned int nzw=0;
+unsigned int maskx=0;
+unsigned int masky=0;
+unsigned int maskz=0;
+
+
+
+unsigned int fmesh_l_coords_fix(unsigned int x, unsigned  int y, unsigned int l){
+    if(l == LOCAL) return l;
+    if(l > SOUTH) return l;
+    if(x==0 && l == WEST) return l;
+    if(x== (T1-1) && l == EAST) return l;
+    if(y==0 && l == NORTH) return l;
+    if(y== (T2-1) && l == SOUTH) return l;
+    if(x==0) return WEST;
+    if(x== (T1-1)) return EAST;
+    if(y==0) return NORTH;
+    if(y== (T2-1)) return SOUTH;
+    return  LOCAL;
 }
 
-void topology_connect_r2e (int n){
-	connect_r2e(1,r2e_cnt_all[n].r1,r2e_cnt_all[n].p1,n);
+void fmesh_Eid_to_coords(unsigned int id, unsigned int *x, unsigned int *y, unsigned int *p){
+    unsigned int  l, diff,mul,addrencode;
+    mul  = T1*T2*T3;
+    if(id < mul) {
+        *y = ((id/T3) / T1 );
+        *x = ((id/T3) % T1 );
+        l = (id % T3);
+        *p = (l==0)? LOCAL : 4+l;
+    }else{
+        diff = id -  mul ;
+        if( diff <  T1) { //top mesh edge
+            *y = 0;
+            *x = diff;
+            *p = NORTH;
+        } else if  ( diff < 2* T1) { //bottom mesh edge
+            *y = T2-1;
+            *x = diff-T1;
+            *p = SOUTH;
+        } else if  ( diff < (2* T1) + T2 ) { //left mesh edge
+            *y = diff - (2* T1);
+            *x = 0;
+            *p = WEST;
+        } else { //right mesh edge
+            *y = diff - (2* T1) -T2;
+            *x = T1-1;
+            *p = EAST;
+        }
+    }
 }
 
+void regular_topo_Eid_to_coords(unsigned int EID, unsigned int * x, unsigned int * y, unsigned int * z, unsigned int * l){
+#if defined (IS_FMESH)
+    (*z)=0;
+    fmesh_Eid_to_coords(EID, x, y, l);
+    return;
+#endif
+    (*l) = EID % L_MAX;
+    unsigned int RID = EID / L_MAX;
+    (*x) = RID % X_MAX;
+    (*y) = (RID / X_MAX) % Y_MAX;
+    (*z) = RID / (X_MAX * Y_MAX);
+}
 
+unsigned int regular_topo_coords_to_Eaddr(unsigned int x, unsigned int y, unsigned int z, unsigned int l){
+    unsigned int code=x;
+    unsigned int shift =nxw;
+    if(DIM > 1) {
+        code|=y<<shift;
+        shift+=nyw;
+    } 
+    if(DIM > 2) {
+        code|=z<<shift;
+        shift+=nzw;
+    }
+    code|=l<<shift;
+    return code;
+}
 
 
 
+void regular_topo_Eaddr_to_coords(unsigned int code, unsigned int *x, unsigned int *y, unsigned int *z, unsigned int *l){
+    (*x) = code &  maskx;
+    code>>=nxw;
+    if(DIM > 1) {
+        (*y) = code &  masky;
+        code>>=nyw;
+    } else (*y)=0;
+    if(DIM > 2) {
+        (*z) = code &  maskz;
+        code>>=nzw;
+    } else (*z)=0;
+    (*l) = code;
+}
 
+unsigned int reqular_topo_addr_encode (unsigned int id){
+    unsigned int y, x, z, l;
+    regular_topo_Eid_to_coords(id,&x,&y,&z,&l);
+    return regular_topo_coords_to_Eaddr(x,y,z,l);
+}
 
+unsigned int regular_topo_addr_decoder (unsigned int code){
+    unsigned int y, x, z, l;
+    regular_topo_Eaddr_to_coords(code,&x,&y,&z,&l);
+    return endp_id(x,y,z,l);
+}
 
+unsigned int fmesh_endp_addr_decoder (unsigned int code){
+    unsigned int x, y, z, p;
+    regular_topo_Eaddr_to_coords(code,&x,&y,&z,&p);
+    if(p== LOCAL)   return ((y*T1)+x)*T3;
+    if(p > SOUTH)   return ((y*T1)+x)*T3+(p-SOUTH);
+    if(p== NORTH)   return ((T1*T2*T3) + x);
+    if(p== SOUTH)   return ((T1*T2*T3) + T1 + x);
+    if(p== WEST )   return ((T1*T2*T3) + 2*T1 + y);
+    if(p== EAST )   return ((T1*T2*T3) + 2*T1 + T2 + y);
+    return 0;//should not reach here
+}
 
-void topology_connect_all_nodes_old (void){
-
-	
-	unsigned int  x,y,l;
-	#if defined (IS_LINE) || defined (IS_RING )
-			#define R2R_CHANELS_MESH_TORI   2
-			for  (x=0;   x<T1; x=x+1) {
-
-				router1[x]->current_r_addr = x;
-				router1[x]->current_r_id   = x;
-				if(x    <   T1-1){// not_last_node
-					//assign  router_chan_in[x][FORWARD] = router_chan_out [(x+1)][BACKWARD];
-					conect_r2r(1,x,FORWARD,1,(x+1),BACKWARD);
-
-				} else { //last_node
-					
-					#if defined (IS_LINE) // : line_last_x
-						//assign  router_chan_in[x][FORWARD]= {SMARTFLIT_CHANEL_w{1'b0}};
-						connect_r2gnd(1,x,FORWARD);				
-					#else // : ring_last_x
-						//assign router_chan_in[x][FORWARD]= router_chan_out [0][BACKWARD];
-						conect_r2r(1,x,FORWARD,1,0,BACKWARD);
-					#endif
-				}
-
-				if(x>0){// :not_first_x
-					//assign router_chan_in[x][BACKWARD]= router_chan_out [(x-1)][FORWARD];
-					conect_r2r(1,x,BACKWARD,1,(x-1),FORWARD);
-				
-				}else {// :first_x
-					#if defined (IS_LINE) // : line_first_x
-						//assign  router_chan_in[x][BACKWARD]={SMARTFLIT_CHANEL_w{1'b0}};					
-						connect_r2gnd(1,x,BACKWARD);
-					#else // : ring_first_x
-						//assign  router_chan_in[x][BACKWARD]= router_chan_out [(NX-1)][FORWARD];											
-						conect_r2r(1,x,BACKWARD,1,(T1-1),FORWARD);
-					#endif
-				}
-
-				// connect other local ports
-				for  (l=0;   l<T3; l=l+1) {// :locals
-					unsigned int ENDPID = endp_id(x,0,l);
-					unsigned int LOCALP = (l==0) ? l : l + R2R_CHANELS_MESH_TORI; // first local port is connected to router port 0. The rest are connected at the }
-					//assign router_chan_in[x][LOCALP]= chan_in_all [ENDPID];
-					//assign chan_out_all [ENDPID] = router_chan_out[x][LOCALP];
-					connect_r2e(1,x,LOCALP,ENDPID);
-					er_addr [ENDPID] = x;
-					
-				}// locals
-			}//x
-			
-		#else // :mesh_torus
-			#define R2R_CHANELS_MESH_TORI   4
-			for (y=0;    y<T2;    y=y+1) {//: y_loop
-				for (x=0;    x<T1; x=x+1) {// :x_loop
-				unsigned int R_ADDR = (y<<nxw) + x;
-				unsigned int ROUTER_NUM = (y * T1) +    x;					
-				//assign current_r_addr [ROUTER_NUM] = R_ADDR[RAw-1 :0];
-             	router1[ROUTER_NUM]->current_r_addr = R_ADDR;
-             	router1[ROUTER_NUM]->current_r_id   = ROUTER_NUM;
-
-				if(x    <    T1-1) {//: not_last_x
-					//assign router_chan_in[`router_id(x,y)][EAST]= router_chan_out [`router_id(x+1,y)][WEST];
-					conect_r2r(1,router_id(x,y),EAST,1,router_id(x+1,y),WEST);
-									
-				}else {// :last_x
-					#if defined (IS_MESH) // :last_x_mesh
-						//	assign router_chan_in[`router_id(x,y)][EAST] = {SMARTFLIT_CHANEL_w{1'b0}};					
-						connect_r2gnd(1,router_id(x,y),EAST);
-					#elif defined (IS_TORUS) // : last_x_torus
-						//assign router_chan_in[`router_id(x,y)][EAST] = router_chan_out [`router_id(0,y)][WEST];
-						conect_r2r(1,router_id(x,y),EAST,1,router_id(0,y),WEST);
-					#elif defined (IS_FMESH) //:last_x_fmesh
-						//connect to endp
-						unsigned int  EAST_ID = T1*T2*T3 + 2*T1 + T2 + y;
-						connect_r2e(1,router_id(x,y),EAST,EAST_ID);
-						er_addr [EAST_ID] = R_ADDR;
-					#endif//topology
-				}
-
-
-				if(y>0) {// : not_first_y
-					//assign router_chan_in[`router_id(x,y)][NORTH] =  router_chan_out [`router_id(x,(y-1))][SOUTH];					
-					conect_r2r(1,router_id(x,y),NORTH,1,router_id(x,(y-1)),SOUTH);		
-				}else {// :first_y
-					#if defined (IS_MESH) // : first_y_mesh
-					 	//assign router_chan_in[`router_id(x,y)][NORTH] =  {SMARTFLIT_CHANEL_w{1'b0}};												
-					 	connect_r2gnd(1,router_id(x,y),NORTH);	
-					#elif defined (IS_TORUS)// :first_y_torus
-						//assign router_chan_in[`router_id(x,y)][NORTH] =  router_chan_out [`router_id(x,(T2-1))][SOUTH];
-						conect_r2r(1,router_id(x,y),NORTH,1,router_id(x,(T2-1)),SOUTH);							
-					#elif defined (IS_FMESH) // :first_y_fmesh
-						unsigned int NORTH_ID = T1*T2*T3 + x;
-						connect_r2e(1,router_id(x,y),NORTH,NORTH_ID);
-						er_addr [NORTH_ID] = R_ADDR;
-					#endif//topology
-				}//y>0
-
-
-				if(x>0){// :not_first_x
-					//assign    router_chan_in[`router_id(x,y)][WEST] =  router_chan_out [`router_id((x-1),y)][EAST];					
-					conect_r2r(1,router_id(x,y),WEST,1,router_id((x-1),y),EAST);	
-				}else {// :first_x
-					
-					#if defined (IS_MESH) // :first_x_mesh
-						//assign    router_chan_in[`router_id(x,y)][WEST] =   {SMARTFLIT_CHANEL_w{1'b0}};
-						connect_r2gnd(1,router_id(x,y),WEST);							
-						
-					#elif defined (IS_TORUS) // :first_x_torus
-						//assign    router_chan_in[`router_id(x,y)][WEST] =   router_chan_out [`router_id((NX-1),y)][EAST] ;						
-						conect_r2r(1,router_id(x,y),WEST,1,router_id((T1-1),y),EAST);
-					#elif defined (IS_FMESH) // :first_x_fmesh
-						unsigned int WEST_ID = T1*T2*T3 + 2*T1 + y;
-						connect_r2e(1,router_id(x,y),WEST,WEST_ID);
-						er_addr [WEST_ID] = R_ADDR;
-					#endif//topology
-				}
+unsigned int fmesh_addrencode(unsigned int id){
+    unsigned int  y, x, p, addrencode;
+    fmesh_Eid_to_coords(id, &x, &y, &p);
+    addrencode = ( p<<(nxw+nyw) | (y<<nxw) | x);
+    return addrencode;
+}
 
-				if(y    <    T2-1) {// : firsty
-					//assign  router_chan_in[`router_id(x,y)][SOUTH] =    router_chan_out [`router_id(x,(y+1))][NORTH];					
-					conect_r2r(1,router_id(x,y),SOUTH,1,router_id(x,(y+1)),NORTH);
-				}else     {// : lasty
-					
-					#if defined (IS_MESH) // :ly_mesh
-						
-						//assign  router_chan_in[`router_id(x,y)][SOUTH]=  {SMARTFLIT_CHANEL_w{1'b0}};
-						connect_r2gnd(1,router_id(x,y),SOUTH);	
-						
-					#elif defined (IS_TORUS) // :ly_torus
-						//assign  router_chan_in[`router_id(x,y)][SOUTH]=    router_chan_out [`router_id(x,0)][NORTH];
-						conect_r2r(1,router_id(x,y),SOUTH,1,router_id(x,0),NORTH);
-					#elif defined (IS_FMESH)  // :ly_Fmesh
-						unsigned int SOUTH_ID = T1*T2*T3 + T1 + x;
-						connect_r2e(1,router_id(x,y),SOUTH,SOUTH_ID);
-						er_addr [SOUTH_ID] = R_ADDR;
-					#endif//topology
-				}
+unsigned int endp_addr_encoder ( unsigned int id){
+        #if defined (IS_FMESH)
+            return fmesh_addrencode(id);
+        #else 
+            return reqular_topo_addr_encode(id);
+        #endif
+}
 
+unsigned int endp_addr_decoder (unsigned int code){
+    #if defined (IS_FMESH)
+    return fmesh_endp_addr_decoder (code);
+    #else 
+    return regular_topo_addr_decoder (code);
+    #endif
+}
 
-				// endpoint(s) connection
-				// connect other local ports
-				for  (l=0;   l<T3; l=l+1) {// :locals
-					unsigned int ENDPID = endp_id(x,y,l);
-					unsigned int LOCALP = (l==0) ? l : l + R2R_CHANELS_MESH_TORI; // first local port is connected to router port 0. The rest are connected at the }
+static inline void topology_connect_r2r (int n){
+    //printf("%d,%d -> %d,%d\n",r2r_cnt_all[n].r1, r2r_cnt_all[n].p1,r2r_cnt_all[n].r2,r2r_cnt_all[n].p2);
+    conect_r2r(1,r2r_cnt_all[n].r1,r2r_cnt_all[n].p1,1,r2r_cnt_all[n].r2,r2r_cnt_all[n].p2);
+}
 
-					//assign router_chan_in [`router_id(x,y)][LOCALP] =    chan_in_all [ENDPID];
-					//assign chan_out_all [ENDPID] = router_chan_out [`router_id(x,y)][LOCALP];	
-					//assign er_addr [ENDPID] = R_ADDR;		
-                    connect_r2e(1,router_id(x,y),LOCALP,ENDPID);
-					er_addr [ENDPID] = R_ADDR;
-				}// locals
+static inline void topology_connect_r2e (int n){
+    //printf ("%d,%d -> %d\n",r2e_cnt_all[n].r1,r2e_cnt_all[n].p1,n);
+    connect_r2e(1,r2e_cnt_all[n].r1,r2e_cnt_all[n].p1,n);
+}
 
-			}//y
-		}//x
-	#endif
+#define fill_r2r_cnt(T1,R1,P1,T2,R2,P2)    (r2r_cnt_table_t){.id1=R1,.t1=T1,.r1=R1,.p1=P1,.id2=R2,.t2=T2,.r2=R2,.p2=P2}
 
-	
-}	
 
-#define fill_r2r_cnt(T1,R1,P1,T2,R2,P2)	(r2r_cnt_table_t){.id1=R1,.t1=T1,.r1=R1,.p1=P1,.id2=R2,.t2=T2,.r2=R2,.p2=P2}
+static inline void topology_edge_connect(unsigned id1, unsigned id2, unsigned int p1, unsigned int p2, unsigned int fmesh_id,unsigned int R_ADDR, unsigned *num) {
+    #if defined (IS_MESH) || defined (IS_MESH_3D) || defined (IS_LINE)
+        connect_r2gnd(1,id1,p1);
+    #elif defined (IS_TORUS) || defined (IS_RING) 
+        r2r_cnt_all[*num]=fill_r2r_cnt(1,id1,p1,1,id2,p2);
+        (*num)++;
+    #elif defined (IS_FMESH) 
+        r2e_cnt_all[fmesh_id].r1=id1;
+        r2e_cnt_all[fmesh_id].p1=p1;
+        er_addr [fmesh_id] = R_ADDR;
+    #endif//topology
+}
 
 void topology_init(void){
-	nxw=Log2(T1);
-	nyw=Log2(T2);
+    nxw=Log2(X_MAX);
+    nyw=Log2(Y_MAX);
+    nzw=Log2(Z_MAX);
+    
     maskx = (0x1<<nxw)-1;
-    masky = (0x1<<nyw)-1;	
+    masky = (0x1<<nyw)-1;
+    maskz = (0x1<<nzw)-1;
+    
     unsigned int num=0;
-    unsigned int  x,y,l;
-    #if defined (IS_LINE) || defined (IS_RING )
-    	#define R2R_CHANELS_MESH_TORI   2
-    	for  (x=0;   x<T1; x=x+1) {
-
-    		router1[x]->current_r_addr = x;
-    		router1[x]->current_r_id   = x;
-    		if(x    <   T1-1){// not_last_node
-    			//assign  router_chan_in[x][FORWARD] = router_chan_out [(x+1)][BACKWARD];
-    			//conect_r2r(1,x,FORWARD,1,(x+1),BACKWARD);
-    			r2r_cnt_all[num]=fill_r2r_cnt(1,x,FORWARD,1,(x+1),BACKWARD);
-    			num++;
-    		} else { //last_node
-   					#if defined (IS_LINE) // : line_last_x
-    				//assign  router_chan_in[x][FORWARD]= {SMARTFLIT_CHANEL_w{1'b0}};
-    					connect_r2gnd(1,x,FORWARD);
-    				#else // : ring_last_x
-    				//assign router_chan_in[x][FORWARD]= router_chan_out [0][BACKWARD];
-    					//conect_r2r(1,x,FORWARD,1,0,BACKWARD);
-    					r2r_cnt_all[num]=fill_r2r_cnt(1,x,FORWARD,1,0,BACKWARD);
-    					num++;
-    				#endif
-    			}
-
-    				if(x>0){// :not_first_x
-    					//assign router_chan_in[x][BACKWARD]= router_chan_out [(x-1)][FORWARD];
-    					//conect_r2r(1,x,BACKWARD,1,(x-1),FORWARD);
-    					r2r_cnt_all[num]=fill_r2r_cnt(1,x,BACKWARD,1,(x-1),FORWARD);
-    					num++;
-    				}else {// :first_x
-    					#if defined (IS_LINE) // : line_first_x
-    						//assign  router_chan_in[x][BACKWARD]={SMARTFLIT_CHANEL_w{1'b0}};
-    						connect_r2gnd(1,x,BACKWARD);
-    					#else // : ring_first_x
-    						//assign  router_chan_in[x][BACKWARD]= router_chan_out [(NX-1)][FORWARD];
-    						//conect_r2r(1,x,BACKWARD,1,(T1-1),FORWARD);
-    						r2r_cnt_all[num]=fill_r2r_cnt(1,x,BACKWARD,1,(T1-1),FORWARD);
-    						num++;
-    					#endif
-    				}
-
-    				// connect other local ports
-    				for  (l=0;   l<T3; l=l+1) {// :locals
-    					unsigned int ENDPID = endp_id(x,0,l);
-    					unsigned int LOCALP = (l==0) ? l : l + R2R_CHANELS_MESH_TORI; // first local port is connected to router port 0. The rest are connected at the }
-    					//assign router_chan_in[x][LOCALP]= chan_in_all [ENDPID];
-    					//assign chan_out_all [ENDPID] = router_chan_out[x][LOCALP];
-    					//connect_r2e(1,x,LOCALP,ENDPID);
-    					r2e_cnt_all[ENDPID].r1=x;
-    					r2e_cnt_all[ENDPID].p1=LOCALP;
-    					er_addr [ENDPID] = x;
-
-    				}// locals
-    			}//x
-
-    		#else // :mesh_torus
-    			#define R2R_CHANELS_MESH_TORI   4
-    			for (y=0;    y<T2;    y=y+1) {//: y_loop
-    				for (x=0;    x<T1; x=x+1) {// :x_loop
-    				unsigned int R_ADDR = (y<<nxw) + x;
-    				unsigned int ROUTER_NUM = (y * T1) +    x;
-    				//assign current_r_addr [ROUTER_NUM] = R_ADDR[RAw-1 :0];
-                 	router1[ROUTER_NUM]->current_r_addr = R_ADDR;
-                 	router1[ROUTER_NUM]->current_r_id   = ROUTER_NUM;
-
-    				if(x    <    T1-1) {//: not_last_x
-    					//assign router_chan_in[`router_id(x,y)][EAST]= router_chan_out [`router_id(x+1,y)][WEST];
-    					//conect_r2r(1,router_id(x,y),EAST,1,router_id(x+1,y),WEST);
-    					r2r_cnt_all[num]=fill_r2r_cnt(1,router_id(x,y),EAST,1,router_id(x+1,y),WEST);
-    					num++;
-
-    				}else {// :last_x
-    					#if defined (IS_MESH) // :last_x_mesh
-    						//	assign router_chan_in[`router_id(x,y)][EAST] = {SMARTFLIT_CHANEL_w{1'b0}};
-    						connect_r2gnd(1,router_id(x,y),EAST);
-    					#elif defined (IS_TORUS) // : last_x_torus
-    						//assign router_chan_in[`router_id(x,y)][EAST] = router_chan_out [`router_id(0,y)][WEST];
-    						//conect_r2r(1,router_id(x,y),EAST,1,router_id(0,y),WEST);
-    						r2r_cnt_all[num]=fill_r2r_cnt(1,router_id(x,y),EAST,1,router_id(0,y),WEST);
-    						num++;
-    					#elif defined (IS_FMESH) //:last_x_fmesh
-    						//connect to endp
-    						unsigned int  EAST_ID = T1*T2*T3 + 2*T1 + T2 + y;
-    						//connect_r2e(1,router_id(x,y),EAST,EAST_ID);
-    						r2e_cnt_all[EAST_ID].r1=router_id(x,y);
-    						r2e_cnt_all[EAST_ID].p1=EAST;
-    						er_addr [EAST_ID] = R_ADDR;
-    					#endif//topology
-    				}
-
-
-    				if(y>0) {// : not_first_y
-    					//assign router_chan_in[`router_id(x,y)][NORTH] =  router_chan_out [`router_id(x,(y-1))][SOUTH];
-    					//conect_r2r(1,router_id(x,y),NORTH,1,router_id(x,(y-1)),SOUTH);
-    					r2r_cnt_all[num]=fill_r2r_cnt(1,router_id(x,y),NORTH,1,router_id(x,(y-1)),SOUTH);
-    					num++;
-    				}else {// :first_y
-    					#if defined (IS_MESH) // : first_y_mesh
-    					 	//assign router_chan_in[`router_id(x,y)][NORTH] =  {SMARTFLIT_CHANEL_w{1'b0}};
-    					 	connect_r2gnd(1,router_id(x,y),NORTH);
-    					#elif defined (IS_TORUS)// :first_y_torus
-    						//assign router_chan_in[`router_id(x,y)][NORTH] =  router_chan_out [`router_id(x,(T2-1))][SOUTH];
-    						//conect_r2r(1,router_id(x,y),NORTH,1,router_id(x,(T2-1)),SOUTH);
-    					 	r2r_cnt_all[num]=fill_r2r_cnt(1,router_id(x,y),NORTH,1,router_id(x,(T2-1)),SOUTH);
-    					 	num++;
-    					#elif defined (IS_FMESH) // :first_y_fmesh
-    						unsigned int NORTH_ID = T1*T2*T3 + x;
-    						//connect_r2e(1,router_id(x,y),NORTH,NORTH_ID);
-    						r2e_cnt_all[NORTH_ID].r1=router_id(x,y);
-    						r2e_cnt_all[NORTH_ID].p1=NORTH;
-    						er_addr [NORTH_ID] = R_ADDR;
-    					#endif//topology
-    				}//y>0
-
-
-    				if(x>0){// :not_first_x
-    					//assign    router_chan_in[`router_id(x,y)][WEST] =  router_chan_out [`router_id((x-1),y)][EAST];
-    					//conect_r2r(1,router_id(x,y),WEST,1,router_id((x-1),y),EAST);
-    					r2r_cnt_all[num]=fill_r2r_cnt(1,router_id(x,y),WEST,1,router_id((x-1),y),EAST);
-    					num++;
-
-    				}else {// :first_x
-
-    					#if defined (IS_MESH) // :first_x_mesh
-    						//assign    router_chan_in[`router_id(x,y)][WEST] =   {SMARTFLIT_CHANEL_w{1'b0}};
-    						connect_r2gnd(1,router_id(x,y),WEST);
-
-    					#elif defined (IS_TORUS) // :first_x_torus
-    						//assign    router_chan_in[`router_id(x,y)][WEST] =   router_chan_out [`router_id((NX-1),y)][EAST] ;
-    						//conect_r2r(1,router_id(x,y),WEST,1,router_id((T1-1),y),EAST);
-    						r2r_cnt_all[num]=fill_r2r_cnt(1,router_id(x,y),WEST,1,router_id((T1-1),y),EAST);
-    						num++;
-    					#elif defined (IS_FMESH) // :first_x_fmesh
-    						unsigned int WEST_ID = T1*T2*T3 + 2*T1 + y;
-    						//connect_r2e(1,router_id(x,y),WEST,WEST_ID);
-    						r2e_cnt_all[WEST_ID].r1=router_id(x,y);
-    						r2e_cnt_all[WEST_ID].p1=WEST;
-    						er_addr [WEST_ID] = R_ADDR;
-    					#endif//topology
-    				}
-
-    				if(y    <    T2-1) {// : firsty
-    					//assign  router_chan_in[`router_id(x,y)][SOUTH] =    router_chan_out [`router_id(x,(y+1))][NORTH];
-    				//	conect_r2r(1,router_id(x,y),SOUTH,1,router_id(x,(y+1)),NORTH);
-    					r2r_cnt_all[num]=fill_r2r_cnt(1,router_id(x,y),SOUTH,1,router_id(x,(y+1)),NORTH);
-    					num++;
-    				}else     {// : lasty
-
-    					#if defined (IS_MESH) // :ly_mesh
-
-    						//assign  router_chan_in[`router_id(x,y)][SOUTH]=  {SMARTFLIT_CHANEL_w{1'b0}};
-    						connect_r2gnd(1,router_id(x,y),SOUTH);
-
-    					#elif defined (IS_TORUS) // :ly_torus
-    						//assign  router_chan_in[`router_id(x,y)][SOUTH]=    router_chan_out [`router_id(x,0)][NORTH];
-    					//	conect_r2r(1,router_id(x,y),SOUTH,1,router_id(x,0),NORTH);
-    						r2r_cnt_all[num]=fill_r2r_cnt(1,router_id(x,y),SOUTH,1,router_id(x,0),NORTH);
-    						num++;
-    					#elif defined (IS_FMESH)  // :ly_Fmesh
-    						unsigned int SOUTH_ID = T1*T2*T3 + T1 + x;
-    						//connect_r2e(1,router_id(x,y),SOUTH,SOUTH_ID);
-    						r2e_cnt_all[SOUTH_ID].r1=router_id(x,y);
-    						r2e_cnt_all[SOUTH_ID].p1=SOUTH;
-    						er_addr [SOUTH_ID] = R_ADDR;
-    					#endif//topology
-    				}
-
-
-    				// endpoint(s) connection
-    				// connect other local ports
-    				for  (l=0;   l<T3; l=l+1) {// :locals
-    					unsigned int ENDPID = endp_id(x,y,l);
-    					unsigned int LOCALP = (l==0) ? l : l + R2R_CHANELS_MESH_TORI; // first local port is connected to router port 0. The rest are connected at the }
-
-    					//assign router_chan_in [`router_id(x,y)][LOCALP] =    chan_in_all [ENDPID];
-    					//assign chan_out_all [ENDPID] = router_chan_out [`router_id(x,y)][LOCALP];
-    					//assign er_addr [ENDPID] = R_ADDR;
-                       // connect_r2e(1,router_id(x,y),LOCALP,ENDPID);
-                        r2e_cnt_all[ENDPID].r1=router_id(x,y);
-                       	r2e_cnt_all[ENDPID].p1=LOCALP;
-    					er_addr [ENDPID] = R_ADDR;
-    				}// locals
-
-    			}//y
-    		}//x
-    	#endif
-
-    	R2R_TABLE_SIZ=num;
-
+    unsigned int  x,y,z,l;
+    #ifndef FLAT_MODE
+    for (z=0; z<Z_MAX; z++) {
+        for (y=0; y<Y_MAX;  y++) {
+            for (x=0; x<X_MAX; x++) {
+                unsigned int ROUTER_NUM =router_id(x,y,z);
+                unsigned int R_ADDR =(z<<(nxw+nyw)) + (y<<nxw) + x;
+                router1[ROUTER_NUM]->current_r_addr = R_ADDR;
+                router1[ROUTER_NUM]->current_r_id   = ROUTER_NUM;
+                unsigned int FMESH_EAST_ID  = T1*T2*T3 + 2*T1 + T2 + y;
+                unsigned int FMESH_WEST_ID  = T1*T2*T3 + 2*T1 + y;
+                unsigned int FMESH_SOUTH_ID = T1*T2*T3 + T1 + x;
+                unsigned int FMESH_NORTH_ID = T1*T2*T3 + x;
+                // endpoint(s) connection
+                for  (l=0; l<L_MAX; l++) {// :locals
+                    unsigned int ENDPID = endp_id(x,y,z,l);
+                    unsigned int LOCALP = (l==0) ? l : l + R2R_CHANELS_MESH_TORI; // first local port is connected to router port 0. The rest are connected at the }
+                    r2e_cnt_all[ENDPID].r1=router_id(x,y,z);
+                    r2e_cnt_all[ENDPID].p1=LOCALP;
+                    er_addr [ENDPID] = R_ADDR;
+                }// locals
+                
+                if(x < X_MAX-1) r2r_cnt_all[num++]=fill_r2r_cnt(1,router_id(x,y,z),EAST,1,router_id(x+1,y,z),WEST);
+                else topology_edge_connect(ROUTER_NUM,router_id(0,y,z),EAST, WEST, FMESH_EAST_ID, R_ADDR, &num);
+                
+                if(x>0) r2r_cnt_all[num++]=fill_r2r_cnt(1,ROUTER_NUM,WEST,1,router_id((x-1),y,z),EAST);
+                else topology_edge_connect(ROUTER_NUM, router_id((X_MAX-1),y,z), WEST, EAST, FMESH_WEST_ID, R_ADDR, &num);
+                if(DIM==1) continue;
+                if (y < Y_MAX-1) r2r_cnt_all[num++] = fill_r2r_cnt(1, ROUTER_NUM, SOUTH, 1, router_id(x, y + 1, z), NORTH);
+                else topology_edge_connect(ROUTER_NUM, router_id(x, 0, z), SOUTH, NORTH, FMESH_SOUTH_ID, R_ADDR, &num);
+                
+                if (y>0) r2r_cnt_all[num++] = fill_r2r_cnt(1, ROUTER_NUM, NORTH, 1, router_id(x, y - 1, z), SOUTH);
+                else topology_edge_connect(ROUTER_NUM, router_id(x, (Y_MAX-1), z), NORTH, SOUTH, FMESH_NORTH_ID, R_ADDR, &num);
+                if(DIM==2) continue;
+                if (z < Z_MAX-1) r2r_cnt_all[num++] = fill_r2r_cnt(1, router_id(x, y, z), UP, 1, router_id(x, y, z + 1), DOWN);
+                else    connect_r2gnd(1,ROUTER_NUM,UP);
+                if (z > 0)  r2r_cnt_all[num++] = fill_r2r_cnt(1, ROUTER_NUM, DOWN, 1, router_id(x, y, z - 1), UP);
+                else connect_r2gnd(1,ROUTER_NUM,DOWN);
+            }//y
+        }//x
+    }//z
+    #endif //FLAT_MODE
+    R2R_TABLE_SIZ=num;
 }
 
 
 unsigned int get_mah_distance ( unsigned int id1, unsigned int id2){
-	#if defined (IS_FMESH)
-		unsigned int x1,y1,p1,x2,y2,p2;
-		fmesh_addrencod_sep	   ( id1, &x1, &y1, &p1);
-		fmesh_addrencod_sep	   ( id2, &x2, &y2, &p2);
+    #if defined (IS_FMESH)
+        unsigned int x1,y1,p1,x2,y2,p2;
+        fmesh_Eid_to_coords       ( id1, &x1, &y1, &p1);
+        fmesh_Eid_to_coords       ( id2, &x2, &y2, &p2);
+        unsigned int z1=0;
+        unsigned int z2=0;
     #else
-		unsigned int x1,y1,l1,x2,y2,l2;
-		mesh_tori_addrencod_sep(id1, &x1, &y1, &l1);
-		mesh_tori_addrencod_sep(id2, &x2, &y2, &l2);
-	#endif
-
-	unsigned int x_diff = (x1 > x2) ? (x1 - x2) : (x2 - x1);
-	unsigned int y_diff = (y1 > y2) ? (y1 - y2) : (y2 - y1);
-	return x_diff + y_diff;
+        unsigned int x1,y1,z1,l1,x2,y2,z2,l2;
+        regular_topo_Eid_to_coords(id1, &x1, &y1, &z1, &l1);
+        regular_topo_Eid_to_coords(id2, &x2, &y2, &z2, &l2);
+    #endif
+    unsigned int x_diff = (x1 > x2) ? (x1 - x2) : (x2 - x1);
+    unsigned int y_diff = (y1 > y2) ? (y1 - y2) : (y2 - y1);
+    unsigned int z_diff = (z1 > z2) ? (z1 - z2) : (z2 - z1);
+    return x_diff + y_diff + z_diff;
 }
 
-
-#endif
+#endif
\ No newline at end of file
diff --git a/mpsoc/src_verilator/topology/star.h b/mpsoc/src_verilator/topology/star.h
index 18fc1a0..3e76ee5 100644
--- a/mpsoc/src_verilator/topology/star.h
+++ b/mpsoc/src_verilator/topology/star.h
@@ -1,20 +1,14 @@
 #ifndef STAR_H
-	#define STAR_H
-
- 
+    #define STAR_H
 
 void topology_connect_all_nodes_old (void){
-
-
-	unsigned int pos;
-	for ( pos = 0; pos <  NE; pos=pos+1 ) {// : endpoints   
-
-		//assign router_chan_out [0][pos] =   chan_in_all [pos];
-		//assign chan_out_all [pos] 		=   router_chan_in [0][pos];
+    unsigned int pos;
+    for ( pos = 0; pos <  NE; pos=pos+1 ) {// : endpoints   
+        //assign router_chan_out [0][pos] =   chan_in_all [pos];
+        //assign chan_out_all [pos]         =   router_chan_in [0][pos];
         connect_r2e(1,0,pos,pos); 
-	    er_addr [pos] = 0;        
- 
-	}//pos 
+        er_addr [pos] = 0;        
+    }//pos 
 }
 
 void topology_connect_r2r (unsigned int n){
@@ -22,14 +16,11 @@ void topology_connect_r2r (unsigned int n){
 }
 
 void topology_connect_r2e (unsigned int n){
-	connect_r2e(1,0,n,n);
+    connect_r2e(1,0,n,n);
 }
 
-
-
-
 unsigned int endp_addr_encoder ( unsigned int id){
-	return id;
+    return id;
 }
 
 unsigned int endp_addr_decoder (unsigned int code){
@@ -37,13 +28,13 @@ unsigned int endp_addr_decoder (unsigned int code){
 }
 
 void topology_init (void){
-	router1[0]->current_r_addr = 0;
-	router1[0]->current_r_id   = 0;
-	for ( int pos = 0; pos <  NE; pos=pos+1 ) {// : endpoints
-		  er_addr [pos] = 0;
-
-	}
-
+    #ifndef FLAT_MODE
+    router1[0]->current_r_addr = 0;
+    router1[0]->current_r_id   = 0;
+    for ( int pos = 0; pos <  NE; pos=pos+1 ) {// : endpoints
+        er_addr [pos] = 0;
+    }
+    #endif
 }
 
 #endif
diff --git a/mpsoc/src_verilator/topology/topology_top.h b/mpsoc/src_verilator/topology/topology_top.h
index 66bff05..5143e4d 100644
--- a/mpsoc/src_verilator/topology/topology_top.h
+++ b/mpsoc/src_verilator/topology/topology_top.h
@@ -1,143 +1,129 @@
 #ifndef TOPOLOGY_TOP_H
 #define TOPOLOGY_TOP_H
 
-	unsigned int	R2R_TABLE_SIZ =0;
-
-	#define CNT_R2R_SIZ  (NR * MAX_P)     //((NR1+NR2+1)*(K+1))
-	#define CNT_R2E_SIZ  (NE+1)
-
-	typedef struct R2R_CNT_TABLE {
-		unsigned int id1;
-		unsigned int t1;
-		unsigned int r1;
-		unsigned int p1;
-		unsigned int id2;
-		unsigned int t2;
-		unsigned int r2;
-		unsigned int p2;
-	} r2r_cnt_table_t;
-
-	r2r_cnt_table_t r2r_cnt_all[CNT_R2R_SIZ];
-
-	typedef struct R2E_CNT_TABLE {
-		unsigned int r1;
-		unsigned int p1;
-	} r2e_cnt_table_t;
-
-	r2e_cnt_table_t r2e_cnt_all[CNT_R2E_SIZ];
-
-
-	int get_router_num (int NR_num, int NR_id){
-		int offset=0;
-		if(NR_num* sizeof(int) > sizeof(router_NRs)){
-				fprintf(stderr,"ERROR: NR%u is not defined\n",NR_num);
-				exit(1);
-		}
-		while (NR_num > 1) {
-			NR_num-=1;
-			offset += router_NRs[NR_num];
-		}
-		return offset + NR_id;	
-	}	
-
-
-	unsigned int er_addr [NE+1]; 
-	char start_i=0;
-	char start_o[NE+1]={0};
-
-	unsigned int Log2 (unsigned int n){
-		unsigned int l=1;
-		while((0x1<<l) < n)l++;
-		return l;
-	}
+    unsigned int    R2R_TABLE_SIZ =0;
+
+    #define CNT_R2R_SIZ  (NR * MAX_P)     //((NR1+NR2+1)*(K+1))
+    #define CNT_R2E_SIZ  (NE+1)
+
+    typedef struct R2R_CNT_TABLE {
+        unsigned int id1;
+        unsigned int t1;
+        unsigned int r1;
+        unsigned int p1;
+        unsigned int id2;
+        unsigned int t2;
+        unsigned int r2;
+        unsigned int p2;
+    } r2r_cnt_table_t;
+
+    r2r_cnt_table_t r2r_cnt_all[CNT_R2R_SIZ];
+
+    typedef struct R2E_CNT_TABLE {
+        unsigned int r1;
+        unsigned int p1;
+    } r2e_cnt_table_t;
+
+    r2e_cnt_table_t r2e_cnt_all[CNT_R2E_SIZ];
+
+    #ifndef FLAT_MODE
+    int get_router_num (int NR_num, int NR_id){
+        int offset=0;
+        if(NR_num* sizeof(int) > sizeof(router_NRs)){
+                fprintf(stderr,"ERROR: NR%u is not defined\n",NR_num);
+                exit(1);
+        }
+        while (NR_num > 1) {
+            NR_num-=1;
+            offset += router_NRs[NR_num];
+        }
+        return offset + NR_id;
+    }    
+    #endif
+
+    unsigned int er_addr [NE+1]; 
+    char start_i=0;
+    char start_o[NE+1]={0};
+
+    unsigned int Log2 (unsigned int n){
+        unsigned int l=1;
+        while((0x1<<l) < n)l++;
+        return l;
+    }
 
-	unsigned int powi (unsigned int x, unsigned int y){ // x^y
-		unsigned int i;        
-		unsigned int pow=1;
+    unsigned int powi (unsigned int x, unsigned int y){ // x^y
+        unsigned int i;
+        unsigned int pow=1;
         for (int i = 0; i <y; i=i+1 ) {
             pow=pow * x;
         }
-		return pow;    
-	}
+        return pow;
+    }
 
-	unsigned int sum_powi (unsigned int x, unsigned int y){//x^(y-1) + x^(y-2) + ...+ 1;
+    unsigned int sum_powi (unsigned int x, unsigned int y){//x^(y-1) + x^(y-2) + ...+ 1;
         unsigned int i; 
         unsigned int sum = 0;
         for (i = 0; i < y; i=i+1){
             sum = sum + powi( x, i );
-      	}   
-		return sum;
+        }   
+        return sum;
     }
 
 #if defined (IS_FATTREE) || defined (IS_TREE)
-		inline unsigned int  Ti( unsigned int id){
-		  return (id < NR1)? 1 : 2;
-		}
-		inline unsigned int Ri(unsigned int id){
-			return  (id < NR1)? id : id-NR1;
-		}
-		
-		#define 	K T1
-		#define     L T2 
-		
-
-
-
-		inline void fattree_connect ( r2r_cnt_table_t in){
-			unsigned int t1 = in.t1;
-			unsigned int r1 = in.r1; 
-			unsigned int p1 = in.p1; 
-			unsigned int t2 = in.t2; 
-			unsigned int r2 = in.r2;
-			unsigned int p2 = in.p2;
-
-			if (t1==1 && t2 == 1) {
-				conect_r2r(1,r1,p1,1,r2,p2);
-				conect_r2r(1,r2,p2,1,r1,p1);
-			}
-			else if (t1==1 && t2 == 2) {
-				conect_r2r(1,r1,p1,2,r2,p2);
-				conect_r2r(2,r2,p2,1,r1,p1);
-			}
-			else if (t1==2 && t2 == 1){
-				conect_r2r(2,r1,p1,1,r2,p2);
-				conect_r2r(1,r2,p2,2,r1,p1);
-			}
-			else{
-				conect_r2r(2,r1,p1,2,r2,p2);
-				conect_r2r(2,r2,p2,2,r1,p1);
-			}
-		}
-#endif
-
-	
-
-
-	#if defined (IS_MESH) || defined (IS_FMESH) || defined (IS_TORUS) || defined (IS_LINE) || defined (IS_RING )
-
-
-
-
-		#include "mesh.h"
-	#elif  defined (IS_FATTREE)
-		#include "fattree.h"
-	#elif  defined (IS_TREE)
-		#include "tree.h"
-	#elif  defined (IS_STAR)
-		#include "star.h"
-	#else
-		//custom not coded
-		unsigned int endp_addr_encoder ( unsigned int id){
-			return id;
-		}
-
-		unsigned int endp_addr_decoder (unsigned int code){
-			return code;
-		}
-		#include "custom.h"
-
-	#endif
-
-
-#endif
+    #ifndef FLAT_MODE
+        inline unsigned int  Ti( unsigned int id){
+            return (id < NR1)? 1 : 2;
+        }
+        inline unsigned int Ri(unsigned int id){
+            return  (id < NR1)? id : id-NR1;
+        }
+    #endif   //FLAT_MODE
+    #define     K T1
+    #define     L T2 
+    
+        inline void fattree_connect ( r2r_cnt_table_t in){
+            unsigned int t1 = in.t1;
+            unsigned int r1 = in.r1; 
+            unsigned int p1 = in.p1; 
+            unsigned int t2 = in.t2; 
+            unsigned int r2 = in.r2;
+            unsigned int p2 = in.p2;
+            if (t1==1 && t2 == 1) {
+                conect_r2r(1,r1,p1,1,r2,p2);
+                conect_r2r(1,r2,p2,1,r1,p1);
+            }
+            else if (t1==1 && t2 == 2) {
+                conect_r2r(1,r1,p1,2,r2,p2);
+                conect_r2r(2,r2,p2,1,r1,p1);
+            }
+            else if (t1==2 && t2 == 1){
+                conect_r2r(2,r1,p1,1,r2,p2);
+                conect_r2r(1,r2,p2,2,r1,p1);
+            }
+            else{
+                conect_r2r(2,r1,p1,2,r2,p2);
+                conect_r2r(2,r2,p2,2,r1,p1);
+            }
+        }
+#endif //IS_FATTREE || IS_TREE
+
+    #if defined (IS_MESH) || defined (IS_FMESH) || defined (IS_TORUS) || defined (IS_LINE) || defined (IS_RING ) || defined (IS_MESH_3D)
+        #include "mesh.h"
+    #elif  defined (IS_FATTREE)
+        #include "fattree.h"
+    #elif  defined (IS_TREE)
+        #include "tree.h"
+    #elif  defined (IS_STAR)
+        #include "star.h"
+    #else
+        //custom not coded
+        unsigned int endp_addr_encoder ( unsigned int id){
+            return id;
+        }
+        unsigned int endp_addr_decoder (unsigned int code){
+            return code;
+        }
+        #include "custom.h"
+    #endif 
+#endif //TOPOLOGY_TOP_H
 
diff --git a/mpsoc/src_verilator/topology/tree.h b/mpsoc/src_verilator/topology/tree.h
index 420e336..f1aa3a9 100644
--- a/mpsoc/src_verilator/topology/tree.h
+++ b/mpsoc/src_verilator/topology/tree.h
@@ -1,225 +1,157 @@
 #ifndef BINTREE_H
-	#define BINTREE_H
-
- 
-
-
+#define BINTREE_H
 #define ROOT_L  (L-1) 
 #define ROOT_ID  0
 
-
-  
 unsigned int    Lw;
 unsigned int    Kw;
 unsigned int    LKw; 
 
-
-
-
-
-
-
-
-
-
 unsigned int bintree_addrencode( unsigned int pos, unsigned int k, unsigned int l){
-	unsigned int pow,i,tmp=0;
-	unsigned int addrencode=0;
-	unsigned int kw=0;
-	while((0x1<<kw) < k)kw++;
-	pow=1;
-	for (i = 0; i <l; i=i+1 ) {
-		tmp=(pos/pow);
-		tmp=tmp%k;
-		tmp=tmp<<(i)*kw;
-		addrencode=addrencode | tmp;
-		pow=pow * k;
-	}
-	 return addrencode;
+    unsigned int pow,i,tmp=0;
+    unsigned int addrencode=0;
+    unsigned int kw=0;
+    while((0x1<<kw) < k)kw++;
+    pow=1;
+    for (i = 0; i <l; i=i+1 ) {
+        tmp=(pos/pow);
+        tmp=tmp%k;
+        tmp=tmp<<(i)*kw;
+        addrencode=addrencode | tmp;
+        pow=pow * k;
+    }
+    return addrencode;
 }
 
-
 unsigned int bintree_addrdecode(unsigned int addrencode , unsigned int k, unsigned int l){
-	unsigned int kw=0;
-	unsigned int mask=0;
-	unsigned int pow,i,tmp;
-	unsigned int pos=0;
-	while((0x1<<kw) < k){
-		kw++;
-		mask<<=1;
-		mask|=0x1;
-	}
-	pow=1;
-	for (i = 0; i <l; i=i+1 ) {
-		tmp = addrencode & mask;
-		tmp=(tmp*pow);
-		pos= pos + tmp;
-		pow=pow * k;
-		addrencode>>=kw;
-	}
-	return pos;
+    unsigned int kw=0;
+    unsigned int mask=0;
+    unsigned int pow,i,tmp;
+    unsigned int pos=0;
+    while((0x1<<kw) < k){
+        kw++;
+        mask<<=1;
+        mask|=0x1;
+    }
+    pow=1;
+    for (i = 0; i <l; i=i+1 ) {
+        tmp = addrencode & mask;
+        tmp=(tmp*pow);
+        pos= pos + tmp;
+        pow=pow * k;
+        addrencode>>=kw;
+    }
+    return pos;
 }
 
-
-
 unsigned int endp_addr_encoder ( unsigned int id){
-			return bintree_addrencode(id, T1, T2);
+    return bintree_addrencode(id, T1, T2);
 }
 
 unsigned int endp_addr_decoder (unsigned int code){
-		return bintree_addrdecode(code, T1, T2);
+    return bintree_addrdecode(code, T1, T2);
 }
 
-	
-	
 void topology_init (void){
-	
-	Lw=Log2(L);
-	Kw=Log2(K);
-	LKw=L*Kw; 
-	
- 	
-	//assign current_layer_addr [ROOT_ID] = ROOT_L;
-	//assign current_pos_addr [ROOT_ID] = {LKw{1'b0}}; 
-	unsigned int addr = ROOT_L << LKw; 
-	router1[ROOT_ID]->current_r_addr = addr; 
-	router1[ROOT_ID]->current_r_id   = ROOT_ID;
-
-
-	unsigned int pos,level;
-	unsigned int num = 0;
-	//connect all up connections
-	for (level = 1; level<L; level=level+1) { // : level_c		
-		unsigned int L1 = L-1-level;
-		unsigned int level2= level - 1;
-		unsigned int L2 = L-1-level2;
-		unsigned int NPOS = powi(K,level); // number of routers in this level
-		for ( pos = 0; pos < NPOS; pos=pos+1 ) { // : pos_c
-          
-			unsigned int ID1 = sum_powi ( K,level) + pos;        
-			unsigned int BINTREE_EQ_POS1 = pos* powi(K,L1);
-			unsigned int ADR_CODE1=bintree_addrencode(BINTREE_EQ_POS1,K,L);       
-			unsigned int POS2 = pos /K ;
-			unsigned int ID2 = sum_powi ( K,level-1) + (pos/K);
-			unsigned int PORT2= pos % K;  
-			unsigned int BINTREE_EQ_POS2 = POS2*powi(K,L2);
-			unsigned int ADR_CODE2=bintree_addrencode(BINTREE_EQ_POS2,K,L);
-
-			
-			      
-			// node_connection('Router[id1][k] to router[id2][pos%k];  
-			//assign  router_chan_out [ID1][K] = router_chan_in [ID2][PORT2];
-			//assign  router_chan_out [ID2][PORT2]= router_chan_in[ID1][K];  
-			//bintree_connect(Ti(ID1),Ri(ID1),port,Ti(ID2),Ri(ID2),PORT2);
-		    r2r_cnt_all[num] =(r2r_cnt_table_t){.id1=ID1, .t1=Ti(ID1), .r1=Ri(ID1), .p1=K,.id2=ID2, .t2=Ti(ID2), .r2=Ri(ID2), .p2=PORT2 };    			
-
-			
-			   
-			
-			unsigned int current_layer_addr  = L1;
-			unsigned int current_pos_addr    = ADR_CODE1;         
-			//assign current_r_addr [ID1] = {current_layer_addr [ID1],current_pos_addr[ID1]};
-			unsigned int addr = (current_layer_addr << LKw)| current_pos_addr;    
-       		
-			router2[Ri(ID1)]->current_r_addr = addr;
-			router2[Ri(ID1)]->current_r_id   = ID1;
-
-			//printf( "[%u] =(addr=%x), t1=%u, r1=%u, p1=%u, t2=%u, r2=%u, p2=%u \n",  num,addr, r2r_cnt_all[num].t1, r2r_cnt_all[num].r1, r2r_cnt_all[num].p1, r2r_cnt_all[num].t2, r2r_cnt_all[num].r2, r2r_cnt_all[num].p2 );
-
-
-			
-			
-
-
-
-        	 num++;
-			}// pos
-    
-		} //level
-
-		R2R_TABLE_SIZ=num;
-
-		// connect }points 
-   
-		for ( pos = 0; pos <  NE; pos=pos+1 ) { // : }points
-			//  node_connection T[pos] R[rid][pos %k];
-			unsigned int RID= sum_powi(K,L-1)+(pos/K);
-			unsigned int RPORT = pos%K;
-    		unsigned int CURRENTPOS=   bintree_addrencode(pos/K,K,L);
-			  
-			//assign router_chan_out [RID][RPORT] =    chan_in_all [pos];                     
-			//assign chan_out_all [pos] = router_chan_in [RID][RPORT];
-			r2e_cnt_all[pos].r1=Ri(RID);
-			r2e_cnt_all[pos].p1=RPORT;
-
-			er_addr [pos] = CURRENTPOS;
- 
-		} //pos    
-	
+    Lw=Log2(L);
+    Kw=Log2(K);
+    LKw=L*Kw; 
+    #ifndef FLAT_MODE
+    //assign current_layer_addr [ROOT_ID] = ROOT_L;
+    //assign current_pos_addr [ROOT_ID] = {LKw{1'b0}}; 
+    unsigned int addr = ROOT_L << LKw; 
+    router1[ROOT_ID]->current_r_addr = addr; 
+    router1[ROOT_ID]->current_r_id   = ROOT_ID;
+    unsigned int pos,level;
+    unsigned int num = 0;
+    //connect all up connections
+    for (level = 1; level<L; level=level+1) { // : level_c        
+        unsigned int L1 = L-1-level;
+        unsigned int level2= level - 1;
+        unsigned int L2 = L-1-level2;
+        unsigned int NPOS = powi(K,level); // number of routers in this level
+        for ( pos = 0; pos < NPOS; pos=pos+1 ) { // : pos_c
+            unsigned int ID1 = sum_powi ( K,level) + pos;        
+            unsigned int BINTREE_EQ_POS1 = pos* powi(K,L1);
+            unsigned int ADR_CODE1=bintree_addrencode(BINTREE_EQ_POS1,K,L);       
+            unsigned int POS2 = pos /K ;
+            unsigned int ID2 = sum_powi ( K,level-1) + (pos/K);
+            unsigned int PORT2= pos % K;  
+            unsigned int BINTREE_EQ_POS2 = POS2*powi(K,L2);
+            unsigned int ADR_CODE2=bintree_addrencode(BINTREE_EQ_POS2,K,L);
+            // node_connection('Router[id1][k] to router[id2][pos%k];  
+            //assign  router_chan_out [ID1][K] = router_chan_in [ID2][PORT2];
+            //assign  router_chan_out [ID2][PORT2]= router_chan_in[ID1][K];  
+            //bintree_connect(Ti(ID1),Ri(ID1),port,Ti(ID2),Ri(ID2),PORT2);
+            r2r_cnt_all[num] =(r2r_cnt_table_t){.id1=ID1, .t1=Ti(ID1), .r1=Ri(ID1), .p1=K,.id2=ID2, .t2=Ti(ID2), .r2=Ri(ID2), .p2=PORT2 };                
+            unsigned int current_layer_addr  = L1;
+            unsigned int current_pos_addr    = ADR_CODE1;         
+            //assign current_r_addr [ID1] = {current_layer_addr [ID1],current_pos_addr[ID1]};
+            unsigned int addr = (current_layer_addr << LKw)| current_pos_addr;    
+            router2[Ri(ID1)]->current_r_addr = addr;
+            router2[Ri(ID1)]->current_r_id   = ID1;
+            //printf( "[%u] =(addr=%x), t1=%u, r1=%u, p1=%u, t2=%u, r2=%u, p2=%u \n",  num,addr, r2r_cnt_all[num].t1, r2r_cnt_all[num].r1, r2r_cnt_all[num].p1, r2r_cnt_all[num].t2, r2r_cnt_all[num].r2, r2r_cnt_all[num].p2 );
+            num++;
+        }// pos
+    } //level
+    R2R_TABLE_SIZ=num;
+    // connect }points 
+    for ( pos = 0; pos <  NE; pos=pos+1 ) { // : }points
+        //  node_connection T[pos] R[rid][pos %k];
+        unsigned int RID= sum_powi(K,L-1)+(pos/K);
+        unsigned int RPORT = pos%K;
+        unsigned int CURRENTPOS=   bintree_addrencode(pos/K,K,L);
+        //assign router_chan_out [RID][RPORT] =    chan_in_all [pos];                     
+        //assign chan_out_all [pos] = router_chan_in [RID][RPORT];
+        r2e_cnt_all[pos].r1=Ri(RID);
+        r2e_cnt_all[pos].p1=RPORT;
+        er_addr [pos] = CURRENTPOS;
+    } //pos 
+    #endif  //FLAT_MODE 
 }
- 
 
 void topology_connect_r2r (int n){
-	fattree_connect(r2r_cnt_all[n]);
+    fattree_connect(r2r_cnt_all[n]);
 }
 
 void topology_connect_r2e (int n){
-	connect_r2e(2,r2e_cnt_all[n].r1,r2e_cnt_all[n].p1,n);
+    connect_r2e(2,r2e_cnt_all[n].r1,r2e_cnt_all[n].p1,n);
 }
 
 /*
 void topology_connect_all_nodes (void){
-	unsigned int pos,level;
-	unsigned int num=0;
-	//connect all up connections
-	for (level = 1; level<L; level=level+1) { // : level_c
-		unsigned int NPOS = powi(K,level); // number of routers in this level
-		for ( pos = 0; pos < NPOS; pos=pos+1 ) { // : pos_c
-          	
-			  fattree_connect(r2r_cnt_all[num]); 
-			  num++;   
-			
-		}// pos
-    
-	} //level
-
-
-	// connect }points 
-   
-	for ( pos = 0; pos <  NE; pos=pos+1 ) { // : }points
-			
-			connect_r2e(2,r2e_cnt_all[pos].r1,r2e_cnt_all[pos].p1,pos);     
- 
-	
-	} 
+    unsigned int pos,level;
+    unsigned int num=0;
+    //connect all up connections
+    for (level = 1; level<L; level=level+1) { // : level_c
+        unsigned int NPOS = powi(K,level); // number of routers in this level
+        for ( pos = 0; pos < NPOS; pos=pos+1 ) { // : pos_c
+            fattree_connect(r2r_cnt_all[num]); 
+            num++;   
+        }// pos
+    } //level
+    // connect }points 
+    for ( pos = 0; pos <  NE; pos=pos+1 ) { // : }points
+        connect_r2e(2,r2e_cnt_all[pos].r1,r2e_cnt_all[pos].p1,pos);
+    }
 }
-
 */
 
 unsigned int get_mah_distance ( unsigned int id1, unsigned int id2){
-
-	unsigned int k =T1;
-	unsigned int l =T2;
-
-	unsigned int pow,tmp1,tmp2;
-	unsigned int distance=0;
-	pow=1;
-	for (unsigned int i = 0; i <l; i=i+1 ) {
-		tmp1=(id1/pow);
-		tmp2=(id2/pow);
-		tmp1=tmp1 % k;
-		tmp2=tmp2 % k;
-		pow=pow * k;
-		if(tmp1!=tmp2) distance= (i+1)*2-1; //distance obtained based on the highest level index which differ
-
-	}
-	 return distance;
+    unsigned int k =T1;
+    unsigned int l =T2;
+    unsigned int pow,tmp1,tmp2;
+    unsigned int distance=0;
+    pow=1;
+    for (unsigned int i = 0; i <l; i=i+1 ) {
+        tmp1=(id1/pow);
+        tmp2=(id2/pow);
+        tmp1=tmp1 % k;
+        tmp2=tmp2 % k;
+        pow=pow * k;
+        if(tmp1!=tmp2) distance= (i+1)*2-1; //distance obtained based on the highest level index which differ
+    }
+    return distance;
 }
 
-
-
-
-#endif
-
-
-	
+#endif
\ No newline at end of file
diff --git a/mpsoc/src_verilator/traffic_synthetic.h b/mpsoc/src_verilator/traffic_synthetic.h
index baf8875..faab96e 100755
--- a/mpsoc/src_verilator/traffic_synthetic.h
+++ b/mpsoc/src_verilator/traffic_synthetic.h
@@ -6,6 +6,35 @@
 
 //#include "topology.h"
 
+#if defined (IS_LINE) || defined (IS_RING )
+    #define NX  T1
+    #define NY  1
+    #define NZ  1
+    #define NL  T3
+#elif defined (IS_MESH_3D)
+    #define NX  T1
+    #define NY  T2
+    #define NZ  T3
+    #define NL  T4
+#elif defined (IS_TORUS) || defined (IS_MESH) 
+    #define NX  T1
+    #define NY  T2
+    #define NZ  1
+    #define NL  T3
+#elif  defined (IS_FMESH)
+    #define NX  T1
+    #define NY  T2
+    #define NZ  1
+    #define NL  T3+4
+#else 
+    #define NX  NE
+    #define NY  1
+    #define NZ  1
+    #define NL  1
+    #define UNREGULAR_TOPO
+#endif
+
+
 
 extern int TRAFFIC_TYPE;
 extern int HOTSPOT_NUM;
@@ -15,265 +44,50 @@ extern unsigned char  NEw;
 int custom_traffic_table[NE];
 
 typedef struct HOTSPOT_NODE {
-	int  ip_num;
-	char send_enable;
-	int  percentage; // x10	
+    int  ip_num;
+    char send_enable;
+    int  percentage; // x10
 } hotspot_st;
 
 hotspot_st * hotspots;
-	
+    
 unsigned int pck_dst_gen_1D (unsigned int, unsigned char *);
 
 // number, b:bit location  W: number width log2(num)
 int getBit(int num, int b, int W)
 {
-	while(b<0) b+=W; 
-	b%=W;
-	return (num >> b) & 0x1;
+    while(b<0) b+=W; 
+    b%=W;
+    return (num >> b) & 0x1;
 }
 
 // number; b:bit location;  W: number width log2(num); v: 1 assert the bit, 0 deassert the bit; 
 void setBit(int *num, int b,   int W, int v)
 {
     while(b<0) b+=W; 
-	b%=W;
+    b%=W;
     int mask = 1 << b;
     //printf("b=%d\n", b);
-	if (v == 0)*num  = *num & ~mask; // assert bit
+    if (v == 0)*num  = *num & ~mask; // assert bit
     else *num = *num | mask; // deassert bit
-      
 }
 
-			 
-unsigned int get_rnd_ip (unsigned int core_num){
-	unsigned int rnd=rand()%NE;
-	if(IS_SELF_LOOP_EN) return rnd;
-	//make sure its not same as sender core
-	while (rnd==core_num)	rnd=rand()%NE;
-	return rnd;
-}
-
-#if (defined (IS_MESH) || defined (IS_TORUS) || defined (IS_LINE) || defined (IS_RING) )
-
-unsigned int pck_dst_gen_2D (unsigned int core_num, unsigned char * inject_en){
-	//for mesh-tori
-	unsigned int current_l,current_x, current_y;
-	unsigned int dest_l,dest_x,dest_y;
-	mesh_tori_addrencod_sep(core_num,&current_x,&current_y,&current_l);
-	* inject_en=1;
-	unsigned int rnd=0;
-	unsigned int rnd100=0;
-	unsigned int max_percent=100/HOTSPOT_NUM;
-	int i;
-
-	if((strcmp (TRAFFIC,"RANDOM")==0) || (strcmp (TRAFFIC,"random")==0)){
-		//get a random IP core
-	    return endp_addr_encoder(get_rnd_ip(core_num));
-	}	
-
-	if ((strcmp(TRAFFIC,"HOTSPOT")==0) || (strcmp (TRAFFIC,"hot spot")==0)){
-		unsigned int rnd1000=0;
-		rnd=get_rnd_ip(core_num);
-
-		rnd1000=rand()%1000; // generate a random number between 0 & 1000
-		for (i=0;i<HOTSPOT_NUM; i++){
-			if ( hotspots[i].send_enable == 0 && core_num ==hotspots[i].ip_num){
-				//rnd = core_num; // turn off the core
-				//return endp_addr_encoder(rnd);
-				*inject_en=0;
-				return INJECT_OFF;
-			}
-		}
-		for (i=0;i<HOTSPOT_NUM; i++){
-			if (rnd1000 < hotspots[i].percentage && core_num !=hotspots[i].ip_num) {
-				rnd = hotspots[i].ip_num;
-				return endp_addr_encoder(rnd);
-			}
-		}
-		return endp_addr_encoder(rnd);
-	}
 
-	if(( strcmp(TRAFFIC ,"TRANSPOSE1")==0)|| (strcmp (TRAFFIC,"transposed 1")==0)){
-		 dest_x = T1-current_y-1;
-		 dest_y = T2-current_x-1;
-		 dest_l = T3-current_l-1;
-		 return mesh_tori_addr_join(dest_x,dest_y,dest_l);
-	}
-
-	if(( strcmp(TRAFFIC ,"TRANSPOSE2")==0)|| (strcmp (TRAFFIC,"transposed 2")==0)){
-		dest_x = current_y;
-		dest_y = current_x;
-		dest_l = current_l;
-		return mesh_tori_addr_join(dest_x,dest_y,dest_l);
-	}
-
-	if(( strcmp(TRAFFIC ,"BIT_REVERSE")==0)|| (strcmp (TRAFFIC,"bit reverse")==0)){
-		//di = sb−i−1
-		int tmp=0;
-		for(i=0; i< NEw; i++)  setBit(&tmp , i, NEw, getBit(core_num, NEw-i-1, NEw));
-		return endp_addr_encoder(tmp);
-	}
-
-	if(( strcmp(TRAFFIC ,"BIT_COMPLEMENT") ==0)|| (strcmp (TRAFFIC,"bit complement")==0)){
-		int tmp=0;
-		for(i=0; i< NEw; i++)  setBit(&tmp , i, NEw, getBit(core_num, i, NEw)==0);
-		return endp_addr_encoder(tmp);
-	}
-
-	if(( strcmp(TRAFFIC ,"TORNADO") == 0)|| (strcmp (TRAFFIC,"tornado")==0)){
-		//[(x+(k/2-1)) mod k, (y+(k/2-1)) mod k],
-			dest_x = ((current_x + ((T1/2)-1))%T1);
-			dest_y = ((current_y + ((T2/2)-1))%T2);
-			dest_l = current_l;
-			return mesh_tori_addr_join(dest_x,dest_y,dest_l);
-     }
-
-    if(( strcmp(TRAFFIC ,"SHUFFLE") == 0)|| (strcmp (TRAFFIC,"shuffle")==0)){
-		//di = si−1 mod b
-		int tmp=0;
-		for(i=0; i< NEw; i++)  setBit(&tmp , i, NEw, getBit(core_num, i-1, NEw));
-		return endp_addr_encoder(tmp);
-     }
-
-    if(( strcmp(TRAFFIC ,"BIT_ROTATION") == 0)|| (strcmp (TRAFFIC,"bit rotation")==0)){
-		//di = si+1 mod b
-		int tmp=0;
-		for(i=0; i< NEw; i++)  setBit(&tmp , i, NEw, getBit(core_num, i+1, NEw));
-		return endp_addr_encoder(tmp);
-     }
-
-    if(( strcmp(TRAFFIC ,"NEIGHBOR") == 0)|| (strcmp (TRAFFIC,"neighbor")==0)){
-		//dx = sx + 1 mod k
-		 dest_x = (current_x + 1)%T1;
-		 dest_y = (current_y + 1)%T2;
-		 dest_l = current_l;
-		 return mesh_tori_addr_join(dest_x,dest_y,dest_l);
-     }    
-     
-     if(( strcmp(TRAFFIC ,"CUSTOM") == 0)|| (strcmp (TRAFFIC,"custom")==0)){
-    	 if (custom_traffic_table[core_num]== INJECT_OFF){
-    		 *inject_en=0;
-    		 return INJECT_OFF;
-    	 }
-		 return endp_addr_encoder(custom_traffic_table[core_num]);
-
-     }  
-
-         fprintf (stderr,"ERROR: traffic %s is an unsupported traffic pattern\n",TRAFFIC);
-         *inject_en=0;
-         return INJECT_OFF;
-
-}
-
-#else
-
-	unsigned int pck_dst_gen_2D (unsigned int core_num, unsigned char * inject_en){
-		return pck_dst_gen_1D (core_num,inject_en );
-	}
-
-#endif
-
-
-unsigned int pck_dst_gen_1D (unsigned int core_num, unsigned char  *inject_en){
-
-	unsigned int rnd=0;
-	unsigned int rnd100=0;
-	unsigned int max_percent=100/HOTSPOT_NUM;
-	int i;
-	
-	*inject_en=1;
-	if((strcmp (TRAFFIC,"RANDOM")==0) || (strcmp (TRAFFIC,"random")==0)){
-		 return endp_addr_encoder(get_rnd_ip(core_num));
-	}
-	
-	if ((strcmp(TRAFFIC,"HOTSPOT")==0) || (strcmp (TRAFFIC,"hot spot")==0)){
-		unsigned int rnd1000=0;
-		int i;
-		rnd=get_rnd_ip(core_num);
-		rnd1000=rand()%1000; // generate a random number between 0 & 1000
-		for (i=0;i<HOTSPOT_NUM; i++){
-			if ( hotspots[i].send_enable == 0 && core_num ==hotspots[i].ip_num){
-				*inject_en=0;
-				return INJECT_OFF;
-			}
-		}
-		
-		for (i=0;i<HOTSPOT_NUM; i++){
-			if (rnd1000 < hotspots[i].percentage && core_num !=hotspots[i].ip_num) {
-				rnd = hotspots[i].ip_num;
-				return endp_addr_encoder(rnd % NE );
-			}
-		}
-		return endp_addr_encoder(rnd % NE );
-	} 
-	
-	
-	if(( strcmp(TRAFFIC ,"TRANSPOSE1")==0)|| (strcmp (TRAFFIC,"transposed 1")==0)){
-		  return endp_addr_encoder(NE-core_num-1);
-	} 
-	if(( strcmp(TRAFFIC ,"TRANSPOSE2")==0)|| (strcmp (TRAFFIC,"transposed 2")==0)){
-		 return endp_addr_encoder(NE-core_num-1);
-	} 
-	
-	if(( strcmp(TRAFFIC ,"BIT_REVERSE")==0)|| (strcmp (TRAFFIC,"bit reverse")==0)){
-		int tmp=0;
-		for(i=0; i< NEw; i++)  setBit(&tmp , i, NEw, getBit(core_num, NEw-i-1, NEw));
-		return endp_addr_encoder(tmp);
-	 } 
-	 
-	 if(( strcmp(TRAFFIC ,"BIT_COMPLEMENT") ==0)|| (strcmp (TRAFFIC,"bit complement")==0)){
-		 int tmp=0;
-		 for(i=0; i< NEw; i++)  setBit(&tmp , i, NEw, getBit(core_num, i, NEw)==0);
-		 return endp_addr_encoder(tmp%NE);
-	 }  
-	 
-	 if(( strcmp(TRAFFIC ,"TORNADO") == 0)|| (strcmp (TRAFFIC,"tornado")==0)){
-		//[(x+(k/2-1)) mod k, (y+(k/2-1)) mod k],
-		 return endp_addr_encoder((core_num + ((NE/2)-1))%NE);
-     }
-
-     if(( strcmp(TRAFFIC ,"SHUFFLE") == 0)|| (strcmp (TRAFFIC,"shuffle")==0)){
-		//di = si−1 mod b
-		int tmp=0;
-		for(i=0; i< NEw; i++)  setBit(&tmp , i, NEw, getBit(core_num, i-1, NEw));
-		return endp_addr_encoder(tmp%NE);
-	 }
-
-     if(( strcmp(TRAFFIC ,"BIT_ROTATION") == 0)|| (strcmp (TRAFFIC,"bit rotation")==0)){
-		//di = si+1 mod b
-		int tmp=0;
-		for(i=0; i< NEw; i++)  setBit(&tmp , i, NEw, getBit(core_num, i+1, NEw));
-		return endp_addr_encoder(tmp%NE);
-
-     }
-
-     if(( strcmp(TRAFFIC ,"NEIGHBOR") == 0)|| (strcmp (TRAFFIC,"neighbor")==0)){
-		//dx = sx + 1 mod k
-    	 return endp_addr_encoder((core_num + 1)%NE);
-	 }
-     
-     if(( strcmp(TRAFFIC ,"CUSTOM") == 0)|| (strcmp (TRAFFIC,"custom")==0)){
-    	 if (custom_traffic_table[core_num]== INJECT_OFF){
-    		 *inject_en=0;
-    		 return INJECT_OFF;
-    	 }
-     	 return endp_addr_encoder(custom_traffic_table[core_num]);
-
-     }
-
-     fprintf (stderr,"ERROR: traffic %s is an unsupported traffic pattern\n",TRAFFIC);
-     *inject_en=0;
-	 return  INJECT_OFF;
+unsigned int get_rnd_ip (unsigned int core_num){
+    unsigned int rnd=rand()%NE;
+    if(SELF_LOOP_EN) return rnd;
+    //make sure its not same as sender core
+    while (rnd==core_num)    rnd=rand()%NE;
+    return rnd;
 }
 
-
 unsigned int rnd_between (unsigned int a, unsigned int b){
-	unsigned int rnd,diff,min;
-	if(a==b) return a;
-	diff= (a<b) ?  b-a+1 : a-b+1;
-	min= (a<b) ?  a : b;
-	rnd = (rand() % diff) +  min;
-	return rnd;
+    unsigned int rnd,diff,min;
+    if(a==b) return a;
+    diff= (a<b) ?  b-a+1 : a-b+1;
+    min= (a<b) ?  a : b;
+    rnd = (rand() % diff) +  min;
+    return rnd;
 }
 
 char mcast_list[1024];
@@ -281,11 +95,9 @@ char mcast_list[1024];
 void reverse(char str1[], int index, int size)
 {
     char temp;
-
     temp = str1[index];
     str1[index] = str1[size - index];
     str1[size - index] = temp;
-
     if (index == size / 2)
     {
         return;
@@ -297,82 +109,201 @@ char * mcast_list_array;
 unsigned int MCAST_PRTLw=0;
 
 void mcast_init(){
-	mcast_list_array = (char *) malloc(NE * sizeof(char));
-	if (IS_MCAST_FULL){
-    	for(int i=0; i< NE; i++) {
-    		mcast_list_array[i]=1;
-    		MCAST_PRTLw=NE;
-    	}
-    	return;
+    mcast_list_array = (char *) malloc(NE * sizeof(char));
+    if (IS_MCAST_FULL){
+        for(int i=0; i< NE; i++) {
+            mcast_list_array[i]=1;
+            MCAST_PRTLw=NE;
+        }
+        return;
     }
-	//partial
-
-	int hex=0;
-	int bin=0;
-	char * temp_str;
-	temp_str = (char *) malloc(strlen(MCAST_ENDP_LIST) * sizeof(char));
-	sscanf(MCAST_ENDP_LIST,"%s",temp_str );
-
-	char * t = strstr(temp_str, "\'h");
-	if(t) hex=1;
-	else {
-	    t = strstr(temp_str, "\'b");
-	    if(t) bin=1;
-	}
-	if(hex==0 && bin == 0){
-		fprintf (stderr,"ERROR: MCAST_ENDP_LIST (%s) is given in wrong format. Only hex ('h) and bin ('b) format is accepted. \n",MCAST_ENDP_LIST);
-		exit(1);
-	}
-
-	t+=2;
-	int size = strlen(t);
-	reverse(t, 0, size - 1);
-
-	int i=0;
+    //partial
+    int hex=0;
+    int bin=0;
+    char * temp_str;
+    temp_str = (char *) malloc(strlen(MCAST_ENDP_LIST) * sizeof(char));
+    sscanf(MCAST_ENDP_LIST,"%s",temp_str );
+    char * t = strstr(temp_str, "\'h");
+    if(t) hex=1;
+    else {
+        t = strstr(temp_str, "\'b");
+        if(t) bin=1;
+    }
+    if(hex==0 && bin == 0){
+        fprintf (stderr,"ERROR: MCAST_ENDP_LIST (%s) is given in wrong format. Only hex ('h) and bin ('b) format is accepted. \n",MCAST_ENDP_LIST);
+        exit(1);
+    }
+    t+=2;
+    int size = strlen(t);
+    reverse(t, 0, size - 1);
+    int i=0;
     char u [2];
     u [1] =0;
-
     if(hex){
-		for(i=0; i< size; i++) {
-			unsigned int ch ;
-			u[0] = t[i];
-			sscanf(u , "%x", &ch);
-			ch&=0xf;
-		   	mcast_list_array[i*4  ] = (ch & 0x1);
-			mcast_list_array[i*4+1] = (ch & 0x2)>>1;
-			mcast_list_array[i*4+2] = (ch & 0x4)>>2;
-			mcast_list_array[i*4+3] = (ch & 0x8)>>3;
-		}
-	}else if(bin){
-		for(i=0; i< size; i++) {
-			unsigned int ch ;
-			u[0] = t[i];
-			sscanf(u , "%x", &ch);
-			ch&=0xf;
-			mcast_list_array[i  ] = ch;
-		}
-
-	}
-
-	for (i=0;i<NE;i++){
-		if(mcast_list_array[i] ==1) MCAST_PRTLw++;
-//	printf("mcast_list_array[%u]=%u\n",i,mcast_list_array[i]);
-	}
-//	printf("mcastw=%u\n",MCAST_PRTLw);
-
+        for(i=0; i< size; i++) {
+            unsigned int ch ;
+            u[0] = t[i];
+            sscanf(u , "%x", &ch);
+            ch&=0xf;
+            mcast_list_array[i*4  ] = (ch & 0x1);
+            mcast_list_array[i*4+1] = (ch & 0x2)>>1;
+            mcast_list_array[i*4+2] = (ch & 0x4)>>2;
+            mcast_list_array[i*4+3] = (ch & 0x8)>>3;
+        }
+    }else if(bin){
+        for(i=0; i< size; i++) {
+            unsigned int ch ;
+            u[0] = t[i];
+            sscanf(u , "%x", &ch);
+            ch&=0xf;
+            mcast_list_array[i  ] = ch;
+        }
+    }
+    for (i=0;i<NE;i++){
+        if(mcast_list_array[i] ==1) MCAST_PRTLw++;
+// printf("mcast_list_array[%u]=%u\n",i,mcast_list_array[i]);
+    }
+// printf("mcastw=%u\n",MCAST_PRTLw);
 }
 
-
 unsigned int  endp_id_to_mcast_id (unsigned int  endp_id){
+    int i=0;
+    if (IS_MCAST_FULL) return endp_id;
+    int  id=0;
+    for (i=0;i<endp_id;i++) {
+        if( mcast_list_array[i]==1) id++;
+    }
+    return id;
+}
 
-        int i=0;
-        if (IS_MCAST_FULL) return endp_id;
-        int  id=0;
-        for (i=0;i<endp_id;i++) {
-                if( mcast_list_array[i]==1) id++;
-        }
-        return id;
+unsigned int pck_dst_gen_return_func (unsigned int dest_x,unsigned int dest_y,unsigned int dest_z,unsigned int dest_l){
+#ifdef UNREGULAR_TOPO
+    return endp_addr_encoder(dest_x);
+#else 
+    #ifdef IS_FMESH
+    dest_l = fmesh_l_coords_fix(dest_x, dest_y, dest_l);
+    #endif  
+    return regular_topo_coords_to_Eaddr(dest_x,dest_y,dest_z,dest_l);
+#endif
 }
 
+unsigned int pck_dst_gen_synthetic (unsigned int core_num, unsigned char * inject_en){
+    * inject_en=1;
+    unsigned int rnd=0;
+    unsigned int rnd100=0;
+    unsigned int max_percent=100/HOTSPOT_NUM;
+    int i;
+    
+    if((strcmp (TRAFFIC,"RANDOM")==0) || (strcmp (TRAFFIC,"random")==0)){
+        //get a random IP core
+        return endp_addr_encoder(get_rnd_ip(core_num));
+    }
+    
+    if ((strcmp(TRAFFIC,"HOTSPOT")==0) || (strcmp (TRAFFIC,"hot spot")==0)){
+        unsigned int rnd1000=0;
+        rnd=get_rnd_ip(core_num);
+        rnd1000=rand()%1000; // generate a random number between 0 & 1000
+        for (i=0;i<HOTSPOT_NUM; i++){
+            if ( hotspots[i].send_enable == 0 && core_num ==hotspots[i].ip_num){
+                //rnd = core_num; // turn off the core
+                //return endp_addr_encoder(rnd);
+                *inject_en=0;
+                return INJECT_OFF;
+            }
+        }
+        for (i=0;i<HOTSPOT_NUM; i++){
+            if (rnd1000 < hotspots[i].percentage && core_num !=hotspots[i].ip_num) {
+                rnd = hotspots[i].ip_num;
+                return endp_addr_encoder(rnd);
+            }
+        }
+        return endp_addr_encoder(rnd);
+    }
+    
+    if(( strcmp(TRAFFIC ,"BIT_REVERSE")==0)|| (strcmp (TRAFFIC,"bit reverse")==0)){
+        //di = sb−i−1
+        int tmp=0;
+        for(i=0; i< NEw; i++)  setBit(&tmp , i, NEw, getBit(core_num, NEw-i-1, NEw));
+        return endp_addr_encoder(tmp);
+    }
+    
+    if(( strcmp(TRAFFIC ,"BIT_COMPLEMENT") ==0)|| (strcmp (TRAFFIC,"bit complement")==0)){
+        int tmp=0;
+        for(i=0; i< NEw; i++)  setBit(&tmp , i, NEw, getBit(core_num, i, NEw)==0);
+        return endp_addr_encoder(tmp);
+    }
+    
+    if(( strcmp(TRAFFIC ,"SHUFFLE") == 0)|| (strcmp (TRAFFIC,"shuffle")==0)){
+        //di = si−1 mod b
+        int tmp=0;
+        for(i=0; i< NEw; i++)  setBit(&tmp , i, NEw, getBit(core_num, i-1, NEw));
+        return endp_addr_encoder(tmp);
+    }
+    
+    if(( strcmp(TRAFFIC ,"BIT_ROTATION") == 0)|| (strcmp (TRAFFIC,"bit rotation")==0)){
+        //di = si+1 mod b
+        int tmp=0;
+        for(i=0; i< NEw; i++)  setBit(&tmp , i, NEw, getBit(core_num, i+1, NEw));
+        return endp_addr_encoder(tmp);
+    }
+    
+    if(( strcmp(TRAFFIC ,"CUSTOM") == 0)|| (strcmp (TRAFFIC,"custom")==0)){
+        if (custom_traffic_table[core_num]== INJECT_OFF){
+            *inject_en=0;
+            return INJECT_OFF;
+        }
+        return endp_addr_encoder(custom_traffic_table[core_num]);
+    } 
+    unsigned int current_l, current_x, current_y, current_z;
+    unsigned int dest_l,dest_x, dest_y, dest_z;
+#ifdef UNREGULAR_TOPO
+    current_l=0; current_x=0; current_y=0; current_z=0;
+    current_x = core_num;
+#else 
+    regular_topo_Eid_to_coords(core_num, &current_x, &current_y, &current_z, &current_l);
+#endif
+    if(( strcmp(TRAFFIC ,"TRANSPOSE1")==0) || (strcmp (TRAFFIC,"transposed 1")==0)){
+        dest_x =
+            (NZ==1 && NY==1) ? (NX-current_x-1) :
+            (NY-current_y-1) % NX;
+        dest_y =
+            ( NZ==1 ) ? ((NX-current_x-1) % NY) : 
+            ((NZ-current_z-1)  % NY);
+        dest_z = (NX-current_x-1) % NZ;
+        dest_l = NL-current_l-1;
+        return pck_dst_gen_return_func(dest_x,dest_y,dest_z,dest_l);
+    }
+    if(( strcmp(TRAFFIC ,"TRANSPOSE2")==0) || (strcmp (TRAFFIC,"transposed 2")==0)){
+        dest_x =
+            (NZ==1 && NY==1)? NX-current_x-1:  //same as transposed 1
+            current_y % NX;
+        dest_y =
+            ( NZ==1)? (current_x % NY) : 
+            current_z  % NY;
+        dest_z = dest_x % NZ;
+        dest_l = NL-current_l-1;
+        return pck_dst_gen_return_func(dest_x,dest_y,dest_z,dest_l);
+    }
+    if(( strcmp(TRAFFIC ,"TORNADO") == 0)|| (strcmp (TRAFFIC,"tornado")==0)){
+        //[(x+(k/2-1)) mod k, (y+(k/2-1)) mod k],
+        dest_x = ((current_x + ((NX/2)-1))%NX);
+        dest_y =(NY==1)? 0 : ((current_y + ((NY/2)-1))%NY);
+        dest_z =(NZ==1)? 0 : ((current_z + ((NZ/2)-1))%NZ);
+        dest_l =(NL==1)? 0 : ((current_l + ((NL/2)-1))%NL);
+        return pck_dst_gen_return_func(dest_x,dest_y,dest_z,dest_l);
+    }
+    if(( strcmp(TRAFFIC ,"NEIGHBOR") == 0)|| (strcmp (TRAFFIC,"neighbor")==0)){
+        //dx = sx + 1 mod k
+        dest_x = (current_x + 1)%NX;
+        dest_y = (current_y + 1)%NY;
+        dest_z = (current_z + 1)%NZ;
+        dest_l = current_l;
+        return pck_dst_gen_return_func(dest_x,dest_y,dest_z,dest_l);
+    }
+    
+    fprintf (stderr,"ERROR: traffic %s is an unsupported traffic pattern\n",TRAFFIC);
+    *inject_en=0;
+    return INJECT_OFF;
+}
 
 #endif
diff --git a/mpsoc/src_verilator/traffic_task_graph.h b/mpsoc/src_verilator/traffic_task_graph.h
index fe30551..10c5863 100755
--- a/mpsoc/src_verilator/traffic_task_graph.h
+++ b/mpsoc/src_verilator/traffic_task_graph.h
@@ -1,54 +1,42 @@
 #ifndef TRAFFIC_TASK_GRAPH_H
 #define TRAFFIC_TASK_GRAPH_H
 
-
-
 #define SET_AUTO -1
 
-
-
 #define MAX_LINE_LEN 1000
-#define DEAFULT_INIT_WEIGHT		1
-#define DEAFULT_MIN_PCK_SIZE	8 // must be larger than 1
-
-
+#define DEFAULT_INIT_WEIGHT     1
+#define DEFAULT_MIN_PCK_SIZE    8 // must be larger than 1
 
 typedef struct INDEX_INFO{
-	unsigned int active_index;
-	unsigned int total_index;
+    unsigned int active_index;
+    unsigned int total_index;
 } index_t;
 
-
-
 typedef struct TRAFFIC_TASK {
-	char enable;
+    char enable;
     unsigned int src;
     unsigned int dst; // ID of the destination endpoint (PE)
-    unsigned int bytes;			
+    unsigned int bytes;
     unsigned int initial_weight;
-    unsigned int min_pck_size;		//in flit
-    unsigned int max_pck_size;		//in flit
-   
-    unsigned int avg_pck_size;		//in flit
+    unsigned int min_pck_size;        //in flit
+    unsigned int max_pck_size;        //in flit
+    
+    unsigned int avg_pck_size;        //in flit
     unsigned int estimated_total_pck_num;
     unsigned int burst_size;
     float injection_rate;
     unsigned int jnjct_var;
-   
+    
     unsigned int pck_sent;
     unsigned int byte_sent;
     unsigned int burst_sent;
 } task_t;
 
-
-
 typedef struct endpt {
-     task_t task;
+    task_t task;
     struct endpt * next;
 } endpt_t;
 
-
-
 unsigned int total_active_routers=0;
 unsigned int task_graph_total_pck_num=0;
 unsigned int task_graph_min_pck_size=999999;
@@ -57,16 +45,13 @@ unsigned int task_graph_max_pck_size=0;
 endpt_t * task_graph_data[NE];
 index_t task_graph_abstract[NE];
 
-
-
-
 void push(endpt_t ** head,  task_t task) {
     endpt_t * new_endpt;
     new_endpt =  (endpt_t *) malloc(sizeof(endpt_t));
     if( new_endpt == NULL){
-       	printf("ERROR: cannot allocate memory in push function\n");
-   	    exit(1);
-   	}
+        printf("ERROR: cannot allocate memory in push function\n");
+        exit(1);
+    }
     new_endpt->task=task;
     new_endpt->next = *head;
     *head = new_endpt;
@@ -75,210 +60,179 @@ void push(endpt_t ** head,  task_t task) {
 int pop(endpt_t ** head) {
    // int retval = -1;
     endpt_t * next_endpt = NULL;
-
     if (*head == NULL) {
         return -1;
     }
-
     next_endpt = (*head)->next;
     //retval = (*head)->val;
     free(*head);
     *head = next_endpt;
-	return 1;
+    return 1;
     //return retval;
 }
 
-
 int remove_by_index(endpt_t ** head, int n) {
     int i = 0;
-   // int retval = -1;
+    // int retval = -1;
     endpt_t * current = *head;
     endpt_t * temp_endpt = NULL;
-
     if (n == 0) {
         return pop(head);
     }
-
     for (i = 0; i < n-1; i++) {
         if (current->next == NULL) {
             return -1;
         }
         current = current->next;
     }
-
     temp_endpt = current->next;
     //retval = temp_endpt->val;
     current->next = temp_endpt->next;
     free(temp_endpt);
     return 1;
-
 }
 
-
 int update_by_index(endpt_t * head,int loc,  task_t  task) {
     endpt_t * current = head;
-	int i;
-	for (i=0;i<loc && current != NULL;i++){
-		current = current->next;
-		
-	}
-	if(current == NULL) return 0;
-	current->task=task;
+    int i;
+    for (i=0;i<loc && current != NULL;i++){
+        current = current->next;
+    }
+    if(current == NULL) return 0;
+    current->task=task;
     return 1;
-
 }
 
-
 int read(endpt_t * head, int loc,  task_t  * task ) {
     endpt_t * current = head;
-	int i;
-	for (i=0;i<loc && current != NULL;i++){
-		current = current->next;
-		
-	}
-	if(current == NULL) return 0;
-	*task =  current->task;
+    int i;
+    for (i=0;i<loc && current != NULL;i++){
+        current = current->next;
+    }
+    if(current == NULL) return 0;
+    *task =  current->task;
     return 1;
 }
 
-
 char* removewhiteSpacses (char * oldstr ) {
-	char *newstr = (char*) malloc(strlen(oldstr)+1);
-	char *np = newstr, *op = oldstr;
-	do {
-	   if (*op != ' ' && *op != '\t')
-		   *np++ = *op;
-	} while (*op++);
-	return newstr;
+    char *newstr = (char*) malloc(strlen(oldstr)+1);
+    char *np = newstr, *op = oldstr;
+    do {
+        if (*op != ' ' && *op != '\t') *np++ = *op;
+    } while (*op++);
+    return newstr;
 }
 
-
-int extract_traffic_data ( char * str,  task_t*  st)
-{
-	
-	unsigned int src;
-	unsigned int dst; // ID of the destination endpt (PE)
-	unsigned int bytes;		
-	unsigned int initial_weight;	
-	unsigned int min_pck_size;		//in flit
-	unsigned int max_pck_size;		//in flit
-	unsigned int burst;
-	float inject_rate;
-	int jnjct_var;
-	
-	int n;
-	n=sscanf( str, "%u,%u,%u,%u,%u,%u,%u,%f,%u",&src, &dst, &bytes, &initial_weight, &min_pck_size, &max_pck_size,&burst,&inject_rate,&jnjct_var);
-	
-	if (n<3) return 0;
-
-	st->src	= src;
-	st->dst=dst;
-	st->bytes=bytes;	
-	st->initial_weight=(n>3 && initial_weight >0 )? initial_weight :DEAFULT_INIT_WEIGHT;
-	st->min_pck_size=  (n>4 && min_pck_size>1 )? min_pck_size : DEAFULT_MIN_PCK_SIZE;
-	st->max_pck_size=  (n>5 && max_pck_size >= st->min_pck_size )? max_pck_size : st->min_pck_size;	
-	st->burst_size =   (n>6 )? burst : SET_AUTO;
-	st->injection_rate= (n>7 )? inject_rate : SET_AUTO;
-	st->jnjct_var= (n>8 )?  jnjct_var : 20;
-	//
-	st->avg_pck_size=  (st->min_pck_size + st->max_pck_size)/2;
-	st->estimated_total_pck_num = (bytes*8) /(st->avg_pck_size*Fpay);
-	if(st->estimated_total_pck_num==0) st->estimated_total_pck_num= 1; 
-	task_graph_total_pck_num=task_graph_total_pck_num+st->estimated_total_pck_num;
-	if(task_graph_min_pck_size > st->min_pck_size ) task_graph_min_pck_size=  st->min_pck_size;
-	if(task_graph_max_pck_size < st->max_pck_size ) task_graph_max_pck_size=  st->max_pck_size;
-
-	st->pck_sent=0;
-	st->byte_sent=0;
+int extract_traffic_data ( char * str,  task_t*  st) {
+    unsigned int src;
+    unsigned int dst; // ID of the destination endpt (PE)
+    unsigned int bytes;        
+    unsigned int initial_weight;    
+    unsigned int min_pck_size;        //in flit
+    unsigned int max_pck_size;        //in flit
+    unsigned int burst;
+    float inject_rate;
+    int jnjct_var;
+    
+    int n;
+    n=sscanf( str, "%u,%u,%u,%u,%u,%u,%u,%f,%u",&src, &dst, &bytes, &initial_weight, &min_pck_size, &max_pck_size,&burst,&inject_rate,&jnjct_var);
+    
+    if (n<3) return 0;
+    
+    st->src    = src;
+    st->dst=dst;
+    st->bytes=bytes;
+    st->initial_weight=(n>3 && initial_weight >0 )? initial_weight :DEFAULT_INIT_WEIGHT;
+    st->min_pck_size=  (n>4 && min_pck_size>1 )? min_pck_size : DEFAULT_MIN_PCK_SIZE;
+    st->max_pck_size=  (n>5 && max_pck_size >= st->min_pck_size )? max_pck_size : st->min_pck_size;
+    st->burst_size =   (n>6 )? burst : SET_AUTO;
+    st->injection_rate= (n>7 )? inject_rate : SET_AUTO;
+    st->jnjct_var= (n>8 )?  jnjct_var : 20;
+    //
+    st->avg_pck_size=  (st->min_pck_size + st->max_pck_size)/2;
+    st->estimated_total_pck_num = (bytes*8) /(st->avg_pck_size*Fpay);
+    if(st->estimated_total_pck_num==0) st->estimated_total_pck_num= 1; 
+    task_graph_total_pck_num=task_graph_total_pck_num+st->estimated_total_pck_num;
+    if(task_graph_min_pck_size > st->min_pck_size ) task_graph_min_pck_size=  st->min_pck_size;
+    if(task_graph_max_pck_size < st->max_pck_size ) task_graph_max_pck_size=  st->max_pck_size;
+    
+    st->pck_sent=0;
+    st->byte_sent=0;
     st->burst_sent=0;
-	
-   return 1;
+    
+    return 1;
 }
 
 int calcualte_traffic_parameters(endpt_t * head[NE],index_t (* info)){
-	int i,j;
-	 task_t  task;
-	
-	unsigned int max_bytes=0,accum[NE];
-	unsigned int min_total[NE];
-	
-	//find the maximum bytes that an IP sends
-	for(i=0;i<NE;i++){
-
-		info[i].active_index=-1;
-		j=0;
-		accum[i]=0;
-		if(head[i]!=NULL){
-			info[i].active_index=0;
-
-			min_total[i] = -1;
-			while(	read(head[i],j,&task)==1){
-				accum[i]=accum[i]+task.bytes;
-				if(  min_total[i] > task.estimated_total_pck_num) min_total[i] = task.estimated_total_pck_num;
-				j++;
-			}
-			info[i].total_index=j;
-			if(max_bytes < accum[i]) 	max_bytes=accum[i];
-		}
-
-	}
-	
-	
-	for(i=0;i<NE;i++){
-
-		j=0;
-		if(head[i]!=NULL){
-			while(	read(head[i],j,&task)==1){
-				if(task.burst_size ==SET_AUTO) task.burst_size = task.estimated_total_pck_num/min_total[i];
-				if(task.injection_rate ==SET_AUTO) task.injection_rate= (float)(200*accum[i] / (3*max_bytes));
-
-				update_by_index(head[i],j,task);
-				j++;
-			}
-		}
-	}
-	return 0;
-}	
-
-
-
+    int i,j;
+    task_t  task;
+    
+    unsigned int max_bytes=0,accum[NE];
+    unsigned int min_total[NE];
+    
+    //find the maximum bytes that an IP sends
+    for(i=0;i<NE;i++){
+        info[i].active_index=-1;
+        j=0;
+        accum[i]=0;
+        if(head[i]!=NULL){
+            info[i].active_index=0;
+            min_total[i] = -1;
+            while(    read(head[i],j,&task)==1){
+                accum[i]=accum[i]+task.bytes;
+                if(  min_total[i] > task.estimated_total_pck_num) min_total[i] = task.estimated_total_pck_num;
+                j++;
+            }
+            info[i].total_index=j;
+            if(max_bytes < accum[i])     max_bytes=accum[i];
+        }
+    }
+    
+    for(i=0;i<NE;i++){
+        j=0;
+        if(head[i]!=NULL){
+            while(    read(head[i],j,&task)==1){
+                if(task.burst_size ==SET_AUTO) task.burst_size = task.estimated_total_pck_num/min_total[i];
+                if(task.injection_rate ==SET_AUTO) task.injection_rate= (float)(200*accum[i] / (3*max_bytes));
+                update_by_index(head[i],j,task);
+                j++;
+            }
+        }
+    }
+    return 0;
+}
 
 
 void load_traffic_file(char * file, endpt_t * head[NE], index_t (* info)){
-	FILE * in;
-	char * line = NULL;
-   
-     task_t st;
+    FILE * in;
+    char * line = NULL;
+    task_t st;
     char l[MAX_LINE_LEN]; 
     in = fopen(file,"rb");
     int n,i;
-     
+    
     if(in == NULL){
-    	fprintf(stderr,"ERROR: cannot open %s file in read mode!\n",file);
-    	exit(1);
-	}
-
+        fprintf(stderr,"ERROR: cannot open %s file in read mode!\n",file);
+        exit(1);
+    }
+    
     for(i=0;i<NE;i++){
-    			head[i]=NULL;
+                head[i]=NULL;
     }
-
-		
-	while (fgets(l,MAX_LINE_LEN, in) != NULL)  {
-		line = removewhiteSpacses(l);
+    
+    while (fgets(l,MAX_LINE_LEN, in) != NULL)  {
+        line = removewhiteSpacses(l);
         if(line[0] != '%' && line[0] != 0 ) {
-			n=extract_traffic_data(line, &st);
-			if(n==0 || st.dst >=NE) continue;// the  destination address must be smaller than NC
-		    push(&head[st.src],st);
-		}	   
-	}
-	fclose(in);
-	calcualte_traffic_parameters(head,info);
-	for(i=0;i<NE;i++){
-		if(info[i].total_index !=0) total_active_routers++;
-	}
+            n=extract_traffic_data(line, &st);
+            if(n==0 || st.dst >=NE) continue;// the  destination address must be smaller than NC
+            push(&head[st.src],st);
+        }
+    }
+    fclose(in);
+    calcualte_traffic_parameters(head,info);
+    for(i=0;i<NE;i++){
+        if(info[i].total_index !=0) total_active_routers++;
+    }
 }
 
-
-
-
 #endif