From 4302fca429dcd7e16532503392d6de923527b0e3 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?=E7=8E=8B=E9=98=B3?= <657837019@qq.com>
Date: Thu, 18 Jun 2026 16:31:12 +0800
Subject: [PATCH] Add riscv sequential mode detection

---
 README.md      |  2 ++
 include/mipp.h | 81 ++++++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 83 insertions(+)

diff --git a/README.md b/README.md
index bce668f..948c86f 100644
--- a/README.md
+++ b/README.md
@@ -140,6 +140,8 @@ debugging or to bench a code.
 If you want to check the MIPP mode configuration, you can print the following 
 global variable: `mipp::InstructionFullType` (`std::string`).
 
+This is the current path used for `RISC-V` targets until a dedicated backend is added.
+
 ### Vector Register Declaration
 
 Just use the `mipp::Reg<T>` type.
diff --git a/include/mipp.h b/include/mipp.h
index d23f770..cb5584e 100644
--- a/include/mipp.h
+++ b/include/mipp.h
@@ -34,6 +34,59 @@ SOFTWARE.
 
 #define MIPP
 
+#if defined(__riscv)
+#define MIPP_RISCV
+#if defined(__riscv_xlen) && (__riscv_xlen == 64)
+#define MIPP_RISCV64
+#endif
+// When a RISC-V target is forced during portability checks, do not inherit host SIMD feature macros.
+#ifdef __ARM_FEATURE_SVE
+#undef __ARM_FEATURE_SVE
+#endif
+#ifdef __ARM_NEON__
+#undef __ARM_NEON__
+#endif
+#ifdef __ARM_NEON
+#undef __ARM_NEON
+#endif
+#ifdef __AVX512F__
+#undef __AVX512F__
+#endif
+#ifdef __AVX512__
+#undef __AVX512__
+#endif
+#ifdef __AVX2__
+#undef __AVX2__
+#endif
+#ifdef __AVX__
+#undef __AVX__
+#endif
+#ifdef __MIC__
+#undef __MIC__
+#endif
+#ifdef __KNCNI__
+#undef __KNCNI__
+#endif
+#ifdef __SSE4_2__
+#undef __SSE4_2__
+#endif
+#ifdef __SSE4_1__
+#undef __SSE4_1__
+#endif
+#ifdef __SSSE3__
+#undef __SSSE3__
+#endif
+#ifdef __SSE3__
+#undef __SSE3__
+#endif
+#ifdef __SSE2__
+#undef __SSE2__
+#endif
+#ifdef __SSE__
+#undef __SSE__
+#endif
+#endif
+
 #ifndef MIPP_NO_INTRINSICS
 #if defined(__ARM_FEATURE_SVE)
 #include <arm_sve.h>
@@ -423,12 +476,26 @@ inline std::vector<std::string> InstructionExtensions()
 	}
 
 // ------------------------------------------------------------------------------------------------- MIPP_NO_INTRINSICS
+#else
+#if defined(MIPP_RISCV64)
+	const std::string InstructionType = "RISC-V";
+	#define MIPP_NO
+
+	const std::string InstructionFullType = "RISC-V64_NO_INTRINSICS";
+	const std::string InstructionVersion  = "1";
+#elif defined(MIPP_RISCV)
+	const std::string InstructionType = "RISC-V";
+	#define MIPP_NO
+
+	const std::string InstructionFullType = "RISC-V_NO_INTRINSICS";
+	const std::string InstructionVersion  = "1";
 #else
 	const std::string InstructionType = "NO";
 	#define MIPP_NO
 
 	const std::string InstructionFullType = "NO_INTRINSICS";
 	const std::string InstructionVersion  = "1";
+#endif
 
 	#define MIPP_NO_INTRINSICS
 	#define MIPP_REQUIRED_ALIGNMENT 1
@@ -457,12 +524,26 @@ inline std::vector<std::string> InstructionExtensions()
 #endif
 
 // ------------------------------------------------------------------------------------------------- MIPP_NO_INTRINSICS
+#else
+#if defined(MIPP_RISCV64)
+	const std::string InstructionType     = "RISC-V";
+	#define MIPP_NO
+
+	const std::string InstructionFullType = "RISC-V64_NO_INTRINSICS";
+	const std::string InstructionVersion  = "1";
+#elif defined(MIPP_RISCV)
+	const std::string InstructionType     = "RISC-V";
+	#define MIPP_NO
+
+	const std::string InstructionFullType = "RISC-V_NO_INTRINSICS";
+	const std::string InstructionVersion  = "1";
 #else
 	const std::string InstructionType     = "NO";
 	#define MIPP_NO
 
 	const std::string InstructionFullType = "NO_INTRINSICS";
 	const std::string InstructionVersion  = "1";
+#endif
 
 #define MIPP_REQUIRED_ALIGNMENT 1
 #if UINTPTR_MAX == 0xffffffffffffffff