profiled skynet further, found that each skynet call to the pl costs 0.165ms， as such 24fps；
and the first image_stitch opeartion adds a cost, and the following ones cost are very low.
Nice design!
There still exists one timing problem:
Under 214MHz, there exists -3.014ns WNS unmet timing constrains in vivado 2019.2, in 3×3 conv modules. Is it normal or the Vivado version differences?
If design focus speed performance only , what other optimization could take? Does AXI bus clock alone to speed up the dram access? Appreciate if you could give some advice, thanks.
profiled skynet further, found that each skynet call to the pl costs 0.165ms， as such 24fps；
and the first image_stitch opeartion adds a cost, and the following ones cost are very low.
Nice design!
There still exists one timing problem:
Under 214MHz, there exists -3.014ns WNS unmet timing constrains in vivado 2019.2, in 3×3 conv modules. Is it normal or the Vivado version differences?
If design focus speed performance only , what other optimization could take? Does AXI bus clock alone to speed up the dram access? Appreciate if you could give some advice, thanks.